1# Firmware configuration file. 2# 3# Global limits (some are hardware limits, others are due to the firmware). 4# nvi = 128 virtual interfaces 5# niqflint = 1023 ingress queues with freelists and/or interrupts 6# nethctrl = 64K Ethernet or ctrl egress queues 7# neq = 64K egress queues of all kinds, including freelists 8# nexactf = 512 MPS TCAM entries, can oversubscribe. 9# 10 11[global] 12 rss_glb_config_mode = basicvirtual 13 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 14 15 # PL_TIMEOUT register 16 pl_timeout_value = 10000 # the timeout value in units of us 17 18 # SGE_THROTTLE_CONTROL 19 bar2throttlecount = 500 # bar2throttlecount in us 20 21 sge_timer_value = 1, 5, 10, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 22 23 reg[0x1124] = 0x00000400/0x00000400 # SGE_CONTROL2, enable VFIFO; if 24 # SGE_VFIFO_SIZE is not set, then 25 # firmware will set it up in function 26 # of number of egress queues used 27 28 reg[0x1130] = 0x00d5ffeb # SGE_DBP_FETCH_THRESHOLD, fetch 29 # threshold set to queue depth 30 # minus 128-entries for FL and HP 31 # queues, and 0xfff for LP which 32 # prompts the firmware to set it up 33 # in function of egress queues 34 # used 35 36 reg[0x113c] = 0x0002ffc0 # SGE_VFIFO_SIZE, set to 0x2ffc0 which 37 # prompts the firmware to set it up in 38 # function of number of egress queues 39 # used 40 41 # enable TP_OUT_CONFIG.IPIDSPLITMODE 42 reg[0x7d04] = 0x00010000/0x00010000 43 44 # disable TP_PARA_REG3.RxFragEn 45 reg[0x7d6c] = 0x00000000/0x00007000 46 47 # enable TP_PARA_REG6.EnableCSnd 48 reg[0x7d78] = 0x00000400/0x00000000 49 50 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 51 52 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 53 filterMask = protocol, fcoe 54 55 tp_pmrx = 36, 512 56 tp_pmrx_pagesize = 64K 57 58 # TP number of RX channels (0 = auto) 59 tp_nrxch = 0 60 61 tp_pmtx = 46, 512 62 tp_pmtx_pagesize = 64K 63 64 # TP number of TX channels (0 = auto) 65 tp_ntxch = 0 66 67 # TP OFLD MTUs 68 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 69 70 # TP_GLOBAL_CONFIG 71 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable 72 73 # TP_PC_CONFIG 74 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError 75 76 # TP_PARA_REG0 77 reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6 78 79 # cluster, lan, or wan. 80 tp_tcptuning = lan 81 82 # MC configuration 83 mc_mode_brc[0] = 1 # mc0 - 1: enable BRC, 0: enable RBC 84 mc_mode_brc[1] = 1 # mc1 - 1: enable BRC, 0: enable RBC 85 86 # ULP_TX_CONFIG 87 reg[0x8dc0] = 0x00000004/0x00000004 # Enable more error msg for ... 88 # TPT error. 89 90# PFs 0-3. These get 8 MSI/8 MSI-X vectors each. VFs are supported by 91# these 4 PFs only. 92[function "0"] 93 wx_caps = all 94 r_caps = all 95 nvi = 1 96 rssnvi = 0 97 niqflint = 2 98 nethctrl = 2 99 neq = 4 100 nexactf = 2 101 cmask = all 102 pmask = 0x1 103 104[function "1"] 105 wx_caps = all 106 r_caps = all 107 nvi = 1 108 rssnvi = 0 109 niqflint = 2 110 nethctrl = 2 111 neq = 4 112 nexactf = 2 113 cmask = all 114 pmask = 0x2 115 116[function "2"] 117 wx_caps = all 118 r_caps = all 119 nvi = 1 120 rssnvi = 0 121 niqflint = 2 122 nethctrl = 2 123 neq = 4 124 nexactf = 2 125 cmask = all 126 pmask = 0x4 127 128[function "3"] 129 wx_caps = all 130 r_caps = all 131 nvi = 1 132 rssnvi = 0 133 niqflint = 2 134 nethctrl = 2 135 neq = 4 136 nexactf = 2 137 cmask = all 138 pmask = 0x8 139 140# PF4 is the resource-rich PF that the bus/nexus driver attaches to. 141# It gets 32 MSI/128 MSI-X vectors. 142[function "4"] 143 wx_caps = all 144 r_caps = all 145 nvi = 32 146 rssnvi = 16 147 niqflint = 512 148 nethctrl = 1024 149 neq = 2048 150 nqpcq = 8192 151 nexactf = 456 152 cmask = all 153 pmask = all 154 nethofld = 8192 155 156 # driver will mask off features it won't use 157 protocol = ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu, iscsi_t10dif 158 159 tp_l2t = 4096 160 tp_ddp = 2 161 tp_ddp_iscsi = 2 162 tp_stag = 2 163 tp_pbl = 5 164 tp_rq = 7 165 166 # TCAM has 8K cells; each region must start at a multiple of 128 cell. 167 # Each entry in these categories takes 4 cells each. nhash will use the 168 # TCAM iff there is room left (that is, the rest don't add up to 2048). 169 nroute = 32 170 nclip = 32 171 nfilter = 1008 172 nserver = 512 173 nhash = 16384 174 175# PF5 is the SCSI Controller PF. It gets 32 MSI/40 MSI-X vectors. 176# Not used right now. 177[function "5"] 178 nvi = 1 179 rssnvi = 0 180 181# PF6 is the FCoE Controller PF. It gets 32 MSI/40 MSI-X vectors. 182# Not used right now. 183[function "6"] 184 nvi = 1 185 rssnvi = 0 186 187# The following function, 1023, is not an actual PCIE function but is used to 188# configure and reserve firmware internal resources that come from the global 189# resource pool. 190[function "1023"] 191 wx_caps = all 192 r_caps = all 193 nvi = 4 194 rssnvi = 0 195 cmask = all 196 pmask = all 197 nexactf = 8 198 nfilter = 16 199 200# For Virtual functions, we only allow NIC functionality and we only allow 201# access to one port (1 << PF). Note that because of limitations in the 202# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 203# and GTS registers, the number of Ingress and Egress Queues must be a power 204# of 2. 205# 206[function "0/*"] 207 wx_caps = 0x82 208 r_caps = 0x86 209 nvi = 1 210 rssnvi = 0 211 niqflint = 2 212 nethctrl = 2 213 neq = 4 214 nexactf = 2 215 cmask = all 216 pmask = 0x1 217 218[function "1/*"] 219 wx_caps = 0x82 220 r_caps = 0x86 221 nvi = 1 222 rssnvi = 0 223 niqflint = 2 224 nethctrl = 2 225 neq = 4 226 nexactf = 2 227 cmask = all 228 pmask = 0x2 229 230[function "2/*"] 231 wx_caps = 0x82 232 r_caps = 0x86 233 nvi = 1 234 rssnvi = 0 235 niqflint = 2 236 nethctrl = 2 237 neq = 4 238 nexactf = 2 239 cmask = all 240 pmask = 0x4 241 242[function "3/*"] 243 wx_caps = 0x82 244 r_caps = 0x86 245 nvi = 1 246 rssnvi = 0 247 niqflint = 2 248 nethctrl = 2 249 neq = 4 250 nexactf = 2 251 cmask = all 252 pmask = 0x8 253 254# MPS has 192K buffer space for ingress packets from the wire as well as 255# loopback path of the L2 switch. 256[port "0"] 257 dcb = none 258 bg_mem = 25 259 lpbk_mem = 25 260 hwm = 30 261 lwm = 15 262 dwm = 30 263 264[port "1"] 265 dcb = none 266 bg_mem = 25 267 lpbk_mem = 25 268 hwm = 30 269 lwm = 15 270 dwm = 30 271 272[port "2"] 273 dcb = none 274 bg_mem = 25 275 lpbk_mem = 25 276 hwm = 30 277 lwm = 15 278 dwm = 30 279 280[port "3"] 281 dcb = none 282 bg_mem = 25 283 lpbk_mem = 25 284 hwm = 30 285 lwm = 15 286 dwm = 30 287 288[fini] 289 version = 0x1 290 checksum = 0x34da8705 291# 292# 293