1# Chelsio T4 Factory Default configuration file. 2# 3# Copyright (C) 2010-2017 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF 6# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT 7# IN PHYSICAL DAMAGE TO T4 ADAPTERS. 8 9# This file provides the default, power-on configuration for 4-port T4-based 10# adapters shipped from the factory. These defaults are designed to address 11# the needs of the vast majority of T4 customers. The basic idea is to have 12# a default configuration which allows a customer to plug a T4 adapter in and 13# have it work regardless of OS, driver or application except in the most 14# unusual and/or demanding customer applications. 15# 16# Many of the T4 resources which are described by this configuration are 17# finite. This requires balancing the configuration/operation needs of 18# device drivers across OSes and a large number of customer application. 19# 20# Some of the more important resources to allocate and their constaints are: 21# 1. Virtual Interfaces: 128. 22# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions 23# must use a power of 2 Ingress Queues. 24# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a 25# power of 2 Egress Queues. 26# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV 27# Virtual Functions based off of a Physical Function all get the 28# same umber of MSI-X Vectors as the base Physical Function. 29# Additionally, regardless of whether Virtual Functions are enabled or 30# not, their MSI-X "needs" are counted by the PCI-E implementation. 31# And finally, all Physical Funcations capable of supporting Virtual 32# Functions (PF0-3) must have the same number of configured TotalVFs in 33# their SR-IOV Capabilities. 34# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 35# address matching on Ingress Packets. 36# 37# Some of the important OS/Driver resource needs are: 38# 6. Some OS Drivers will manage all resources through a single Physical 39# Function (currently PF0 but it could be any Physical Function). Thus, 40# this "Unified PF" will need to have enough resources allocated to it 41# to allow for this. And because of the MSI-X resource allocation 42# constraints mentioned above, this probably means we'll either have to 43# severely limit the TotalVFs if we continue to use PF0 as the Unified PF 44# or we'll need to move the Unified PF into the PF4-7 range since those 45# Physical Functions don't have any Virtual Functions associated with 46# them. 47# 7. Some OS Drivers will manage different ports and functions (NIC, 48# storage, etc.) on different Physical Functions. For example, NIC 49# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 50# 51# Some of the customer application needs which need to be accommodated: 52# 8. Some customers will want to support large CPU count systems with 53# good scaling. Thus, we'll need to accommodate a number of 54# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 55# to be involved per port and per application function. For example, 56# in the case where all ports and application functions will be 57# managed via a single Unified PF and we want to accommodate scaling up 58# to 8 CPUs, we would want: 59# 60# 4 ports * 61# 3 application functions (NIC, FCoE, iSCSI) per port * 62# 8 Ingress Queue/MSI-X Vectors per application function 63# 64# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 65# (Plus a few for Firmware Event Queues, etc.) 66# 67# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow 68# Virtual Machines to directly access T4 functionality via SR-IOV 69# Virtual Functions and "PCI Device Passthrough" -- this is especially 70# true for the NIC application functionality. (Note that there is 71# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual 72# Functions so this is in fact solely limited to NIC.) 73# 74 75 76# Global configuration settings. 77# 78[global] 79 rss_glb_config_mode = basicvirtual 80 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 81 82 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 83 # Page Size and a 64B L1 Cache Line Size. It programs the 84 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 85 # If a Master PF Driver finds itself on a machine with different 86 # parameters, then the Master PF Driver is responsible for initializing 87 # these parameters to appropriate values. 88 # 89 # Notes: 90 # 1. The Free List Buffer Sizes below are raw and the firmware will 91 # round them up to the Ingress Padding Boundary. 92 # 2. The SGE Timer Values below are expressed below in microseconds. 93 # The firmware will convert these values to Core Clock Ticks when 94 # it processes the configuration parameters. 95 # 96 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 97 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 98 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 99 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 100 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 101 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 102 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 103 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 104 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 105 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 106 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 107 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 108 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 109 reg[0x10a8] = 0x2000/0x2000 # SGE_DOORBELL_CONTROL 110 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 111 112 # enable TP_OUT_CONFIG.IPIDSPLITMODE 113 reg[0x7d04] = 0x00010000/0x00010000 114 115 # disable TP_PARA_REG3.RxFragEn 116 reg[0x7d6c] = 0x00000000/0x00007000 117 118 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT 119 120 # TP_VLAN_PRI_MAP to select filter tuples 121 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 122 # protocol, tos, vlan, vnic_id, port, fcoe 123 # valid filterModes are described the Terminator 4 Data Book 124 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 125 126 # filter tuples enforced in LE active region (equal to or subset of filterMode) 127 filterMask = protocol, fcoe 128 129 # Percentage of dynamic memory (in either the EDRAM or external MEM) 130 # to use for TP RX payload 131 tp_pmrx = 34 132 133 # TP RX payload page size 134 tp_pmrx_pagesize = 64K 135 136 # TP number of RX channels 137 tp_nrxch = 0 # 0 (auto) = 1 138 139 # Percentage of dynamic memory (in either the EDRAM or external MEM) 140 # to use for TP TX payload 141 tp_pmtx = 32 142 143 # TP TX payload page size 144 tp_pmtx_pagesize = 64K 145 146 # TP number of TX channels 147 tp_ntxch = 0 # 0 (auto) = equal number of ports 148 149 # TP OFLD MTUs 150 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 151 152 # ULPRX iSCSI Page Sizes 153 reg[0x19168] = 0x04020100 # 64K, 16K, 8K and 4K 154 155# Some "definitions" to make the rest of this a bit more readable. We support 156# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 157# per function per port ... 158# 159# NMSIX = 1088 # available MSI-X Vectors 160# NVI = 128 # available Virtual Interfaces 161# NMPSTCAM = 336 # MPS TCAM entries 162# 163# NPORTS = 4 # ports 164# NCPUS = 8 # CPUs we want to support scalably 165# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 166 167# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 168# PF" which many OS Drivers will use to manage most or all functions. 169# 170# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 171# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 172# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 173# will be specified as the "Ingress Queue Asynchronous Destination Index." 174# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 175# than or equal to the number of Ingress Queues ... 176# 177# NVI_NIC = 4 # NIC access to NPORTS 178# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 179# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 180# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 181# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 182# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 183# 184# NVI_OFLD = 0 # Offload uses NIC function to access ports 185# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 186# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 187# NEQ_OFLD = 16 # Offload Egress Queues (FL) 188# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 189# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 190# 191# NVI_RDMA = 0 # RDMA uses NIC function to access ports 192# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 193# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 194# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 195# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 196# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 197# 198# NEQ_WD = 128 # Wire Direct TX Queues and FLs 199# NETHCTRL_WD = 64 # Wire Direct TX Queues 200# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 201# 202# NVI_ISCSI = 4 # ISCSI access to NPORTS 203# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 204# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 205# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 206# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 207# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 208# 209# NVI_FCOE = 4 # FCOE access to NPORTS 210# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 211# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 212# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 213# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 214# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 215 216# Two extra Ingress Queues per function for Firmware Events and Forwarded 217# Interrupts, and two extra interrupts per function for Firmware Events (or a 218# Forwarded Interrupt Queue) and General Interrupts per function. 219# 220# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 221# # Forwarded Interrupts 222# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 223# # General Interrupts 224 225# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 226# their interrupts forwarded to another set of Forwarded Interrupt Queues. 227# 228# NVI_HYPERV = 16 # VMs we want to support 229# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 230# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 231# NEQ_HYPERV = 32 # VIQs Free Lists 232# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 233# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 234 235# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 236# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 237# 238# NVI_UNIFIED = 28 239# NFLIQ_UNIFIED = 106 240# NETHCTRL_UNIFIED = 32 241# NEQ_UNIFIED = 124 242# NMPSTCAM_UNIFIED = 40 243# 244# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 245# that up to 128 to make sure the Unified PF doesn't run out of resources. 246# 247# NMSIX_UNIFIED = 128 248# 249# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 250# which is 34 but they're probably safe with 32. 251# 252# NMSIX_STORAGE = 32 253 254# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 255# associated with it. Thus, the MSI-X Vector allocations we give to the 256# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 257# provision many more Virtual Functions than we can if the UnifiedPF were 258# one of PF0-3. 259# 260 261# All of the below PCI-E parameters are actually stored in various *_init.txt 262# files. We include them below essentially as comments. 263# 264# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 265# ports 0-3. 266# 267# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 268# 269# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 270# storage applications across all four possible ports. 271# 272# Additionally, since the UnifiedPF isn't one of the per-port Physical 273# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 274# different PCI Device IDs which will allow Unified and Per-Port Drivers 275# to directly select the type of Physical Function to which they wish to be 276# attached. 277# 278# Note that the actual values used for the PCI-E Intelectual Property will be 279# 1 less than those below since that's the way it "counts" things. For 280# readability, we use the number we actually mean ... 281# 282# PF0_INT = 8 # NCPUS 283# PF1_INT = 8 # NCPUS 284# PF2_INT = 8 # NCPUS 285# PF3_INT = 8 # NCPUS 286# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 287# 288# PF4_INT = 128 # NMSIX_UNIFIED 289# PF5_INT = 32 # NMSIX_STORAGE 290# PF6_INT = 32 # NMSIX_STORAGE 291# PF7_INT = 0 # Nothing Assigned 292# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 293# 294# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 295# 296# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 297# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 298# 299# NVF = 16 300 301# For those OSes which manage different ports on different PFs, we need 302# only enough resources to support a single port's NIC application functions 303# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 304# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 305# managed on the "storage PFs" (see below). 306# 307[function "0"] 308 nvf = 16 # NVF on this function 309 wx_caps = all # write/execute permissions for all commands 310 r_caps = all # read permissions for all commands 311 nvi = 1 # 1 port 312 niqflint = 8 # NCPUS "Queue Sets" 313 nethctrl = 8 # NCPUS "Queue Sets" 314 neq = 16 # niqflint + nethctrl Egress Queues 315 nexactf = 8 # number of exact MPSTCAM MAC filters 316 cmask = all # access to all channels 317 pmask = 0x1 # access to only one port 318 319[function "1"] 320 nvf = 16 # NVF on this function 321 wx_caps = all # write/execute permissions for all commands 322 r_caps = all # read permissions for all commands 323 nvi = 1 # 1 port 324 niqflint = 8 # NCPUS "Queue Sets" 325 nethctrl = 8 # NCPUS "Queue Sets" 326 neq = 16 # niqflint + nethctrl Egress Queues 327 nexactf = 8 # number of exact MPSTCAM MAC filters 328 cmask = all # access to all channels 329 pmask = 0x2 # access to only one port 330 331[function "2"] 332 nvf = 16 # NVF on this function 333 wx_caps = all # write/execute permissions for all commands 334 r_caps = all # read permissions for all commands 335 nvi = 1 # 1 port 336 niqflint = 8 # NCPUS "Queue Sets" 337 nethctrl = 8 # NCPUS "Queue Sets" 338 neq = 16 # niqflint + nethctrl Egress Queues 339 nexactf = 8 # number of exact MPSTCAM MAC filters 340 cmask = all # access to all channels 341 pmask = 0x4 # access to only one port 342 343[function "3"] 344 nvf = 16 # NVF on this function 345 wx_caps = all # write/execute permissions for all commands 346 r_caps = all # read permissions for all commands 347 nvi = 1 # 1 port 348 niqflint = 8 # NCPUS "Queue Sets" 349 nethctrl = 8 # NCPUS "Queue Sets" 350 neq = 16 # niqflint + nethctrl Egress Queues 351 nexactf = 8 # number of exact MPSTCAM MAC filters 352 cmask = all # access to all channels 353 pmask = 0x8 # access to only one port 354 355# Some OS Drivers manage all application functions for all ports via PF4. 356# Thus we need to provide a large number of resources here. For Egress 357# Queues we need to account for both TX Queues as well as Free List Queues 358# (because the host is responsible for producing Free List Buffers for the 359# hardware to consume). 360# 361[function "4"] 362 wx_caps = all # write/execute permissions for all commands 363 r_caps = all # read permissions for all commands 364 nvi = 28 # NVI_UNIFIED 365 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 366 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 367 neq = 256 # NEQ_UNIFIED + NEQ_WD 368 nexactf = 40 # NMPSTCAM_UNIFIED 369 cmask = all # access to all channels 370 pmask = all # access to all four ports ... 371 nethofld = 1024 # number of user mode ethernet flow contexts 372 nroute = 32 # number of routing region entries 373 nclip = 32 # number of clip region entries 374 nfilter = 496 # number of filter region entries 375 nserver = 496 # number of server region entries 376 nhash = 12288 # number of hash region entries 377 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu 378 tp_l2t = 3072 379 tp_ddp = 3 380 tp_ddp_iscsi = 2 381 tp_stag = 3 382 tp_pbl = 10 383 tp_rq = 13 384 385# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 386# need to have Virtual Interfaces on each of the four ports with up to NCPUS 387# "Queue Sets" each. 388# 389[function "5"] 390 wx_caps = all # write/execute permissions for all commands 391 r_caps = all # read permissions for all commands 392 nvi = 4 # NPORTS 393 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 394 nethctrl = 32 # NPORTS*NCPUS 395 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 396 nexactf = 4 # NPORTS 397 cmask = all # access to all channels 398 pmask = all # access to all four ports ... 399 nserver = 16 400 nhash = 2048 401 tp_l2t = 1020 402 protocol = iscsi_initiator_fofld 403 tp_ddp_iscsi = 2 404 iscsi_ntask = 2048 405 iscsi_nsess = 2048 406 iscsi_nconn_per_session = 1 407 iscsi_ninitiator_instance = 64 408 409[function "6"] 410 wx_caps = all # write/execute permissions for all commands 411 r_caps = all # read permissions for all commands 412 nvi = 4 # NPORTS 413 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 414 nethctrl = 32 # NPORTS*NCPUS 415 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 416 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 417 # which is OK since < MIN(SUM PF0..3, PF4) 418 # and we never load PF0..3 and PF4 concurrently 419 cmask = all # access to all channels 420 pmask = all # access to all four ports ... 421 nhash = 2048 422 tp_l2t = 4 423 protocol = fcoe_initiator 424 tp_ddp = 1 425 fcoe_nfcf = 16 426 fcoe_nvnp = 32 427 fcoe_nssn = 1024 428 429# The following function, 1023, is not an actual PCIE function but is used to 430# configure and reserve firmware internal resources that come from the global 431# resource pool. 432# 433[function "1023"] 434 wx_caps = all # write/execute permissions for all commands 435 r_caps = all # read permissions for all commands 436 nvi = 4 # NVI_UNIFIED 437 cmask = all # access to all channels 438 pmask = all # access to all four ports ... 439 nexactf = 8 # NPORTS + DCBX + 440 nfilter = 16 # number of filter region entries 441 442# For Virtual functions, we only allow NIC functionality and we only allow 443# access to one port (1 << PF). Note that because of limitations in the 444# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 445# and GTS registers, the number of Ingress and Egress Queues must be a power 446# of 2. 447# 448[function "0/*"] # NVF 449 wx_caps = 0x82 # DMAQ | VF 450 r_caps = 0x86 # DMAQ | VF | PORT 451 nvi = 1 # 1 port 452 niqflint = 4 # 2 "Queue Sets" + NXIQ 453 nethctrl = 2 # 2 "Queue Sets" 454 neq = 4 # 2 "Queue Sets" * 2 455 nexactf = 4 456 cmask = all # access to all channels 457 pmask = 0x1 # access to only one port ... 458 459[function "1/*"] # NVF 460 wx_caps = 0x82 # DMAQ | VF 461 r_caps = 0x86 # DMAQ | VF | PORT 462 nvi = 1 # 1 port 463 niqflint = 4 # 2 "Queue Sets" + NXIQ 464 nethctrl = 2 # 2 "Queue Sets" 465 neq = 4 # 2 "Queue Sets" * 2 466 nexactf = 4 467 cmask = all # access to all channels 468 pmask = 0x2 # access to only one port ... 469 470[function "2/*"] # NVF 471 wx_caps = 0x82 # DMAQ | VF 472 r_caps = 0x86 # DMAQ | VF | PORT 473 nvi = 1 # 1 port 474 niqflint = 4 # 2 "Queue Sets" + NXIQ 475 nethctrl = 2 # 2 "Queue Sets" 476 neq = 4 # 2 "Queue Sets" * 2 477 nexactf = 4 478 cmask = all # access to all channels 479 pmask = 0x4 # access to only one port ... 480 481[function "3/*"] # NVF 482 wx_caps = 0x82 # DMAQ | VF 483 r_caps = 0x86 # DMAQ | VF | PORT 484 nvi = 1 # 1 port 485 niqflint = 4 # 2 "Queue Sets" + NXIQ 486 nethctrl = 2 # 2 "Queue Sets" 487 neq = 4 # 2 "Queue Sets" * 2 488 nexactf = 4 489 cmask = all # access to all channels 490 pmask = 0x8 # access to only one port ... 491 492# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 493# for packets from the wire as well as the loopback path of the L2 switch. The 494# folling params control how the buffer memory is distributed and the L2 flow 495# control settings: 496# 497# bg_mem: %-age of mem to use for port/buffer group 498# lpbk_mem: %-age of port/bg mem to use for loopback 499# hwm: high watermark; bytes available when starting to send pause 500# frames (in units of 0.1 MTU) 501# lwm: low watermark; bytes remaining when sending 'unpause' frame 502# (in inuits of 0.1 MTU) 503# dwm: minimum delta between high and low watermark (in units of 100 504# Bytes) 505# 506# 507 508[port "0"] 509 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 510 bg_mem = 25 511 lpbk_mem = 25 512 hwm = 30 513 lwm = 15 514 dwm = 30 515 dcb_app_tlv[0] = 0x8906, ethertype, 3 516 dcb_app_tlv[1] = 0x8914, ethertype, 3 517 dcb_app_tlv[2] = 3260, socketnum, 5 518 519[port "1"] 520 dcb = ppp, dcbx 521 bg_mem = 25 522 lpbk_mem = 25 523 hwm = 30 524 lwm = 15 525 dwm = 30 526 dcb_app_tlv[0] = 0x8906, ethertype, 3 527 dcb_app_tlv[1] = 0x8914, ethertype, 3 528 dcb_app_tlv[2] = 3260, socketnum, 5 529 530[port "2"] 531 dcb = ppp, dcbx 532 bg_mem = 25 533 lpbk_mem = 25 534 hwm = 30 535 lwm = 15 536 dwm = 30 537 dcb_app_tlv[0] = 0x8906, ethertype, 3 538 dcb_app_tlv[1] = 0x8914, ethertype, 3 539 dcb_app_tlv[2] = 3260, socketnum, 5 540 541[port "3"] 542 dcb = ppp, dcbx 543 bg_mem = 25 544 lpbk_mem = 25 545 hwm = 30 546 lwm = 15 547 dwm = 30 548 dcb_app_tlv[0] = 0x8906, ethertype, 3 549 dcb_app_tlv[1] = 0x8914, ethertype, 3 550 dcb_app_tlv[2] = 3260, socketnum, 5 551 552[fini] 553 version = 0x01000028 554 checksum = 0x5ceab421 555 556# Total resources used by above allocations: 557# Virtual Interfaces: 104 558# Ingress Queues/w Free Lists and Interrupts: 526 559# Egress Queues: 702 560# MPS TCAM Entries: 336 561# MSI-X Vectors: 736 562# Virtual Functions: 64 563# 564# 565