1# Chelsio T4 Factory Default configuration file. 2# 3# Copyright (C) 2010-2012 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF 6# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT 7# IN PHYSICAL DAMAGE TO T4 ADAPTERS. 8 9# This file provides the default, power-on configuration for 4-port T4-based 10# adapters shipped from the factory. These defaults are designed to address 11# the needs of the vast majority of T4 customers. The basic idea is to have 12# a default configuration which allows a customer to plug a T4 adapter in and 13# have it work regardless of OS, driver or application except in the most 14# unusual and/or demanding customer applications. 15# 16# Many of the T4 resources which are described by this configuration are 17# finite. This requires balancing the configuration/operation needs of 18# device drivers across OSes and a large number of customer application. 19# 20# Some of the more important resources to allocate and their constaints are: 21# 1. Virtual Interfaces: 128. 22# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions 23# must use a power of 2 Ingress Queues. 24# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a 25# power of 2 Egress Queues. 26# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV 27# Virtual Functions based off of a Physical Function all get the 28# same umber of MSI-X Vectors as the base Physical Function. 29# Additionally, regardless of whether Virtual Functions are enabled or 30# not, their MSI-X "needs" are counted by the PCI-E implementation. 31# And finally, all Physical Funcations capable of supporting Virtual 32# Functions (PF0-3) must have the same number of configured TotalVFs in 33# their SR-IOV Capabilities. 34# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 35# address matching on Ingress Packets. 36# 37# Some of the important OS/Driver resource needs are: 38# 6. Some OS Drivers will manage all resources through a single Physical 39# Function (currently PF0 but it could be any Physical Function). Thus, 40# this "Unified PF" will need to have enough resources allocated to it 41# to allow for this. And because of the MSI-X resource allocation 42# constraints mentioned above, this probably means we'll either have to 43# severely limit the TotalVFs if we continue to use PF0 as the Unified PF 44# or we'll need to move the Unified PF into the PF4-7 range since those 45# Physical Functions don't have any Virtual Functions associated with 46# them. 47# 7. Some OS Drivers will manage different ports and functions (NIC, 48# storage, etc.) on different Physical Functions. For example, NIC 49# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 50# 51# Some of the customer application needs which need to be accommodated: 52# 8. Some customers will want to support large CPU count systems with 53# good scaling. Thus, we'll need to accommodate a number of 54# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 55# to be involved per port and per application function. For example, 56# in the case where all ports and application functions will be 57# managed via a single Unified PF and we want to accommodate scaling up 58# to 8 CPUs, we would want: 59# 60# 4 ports * 61# 3 application functions (NIC, FCoE, iSCSI) per port * 62# 8 Ingress Queue/MSI-X Vectors per application function 63# 64# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 65# (Plus a few for Firmware Event Queues, etc.) 66# 67# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow 68# Virtual Machines to directly access T4 functionality via SR-IOV 69# Virtual Functions and "PCI Device Passthrough" -- this is especially 70# true for the NIC application functionality. (Note that there is 71# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual 72# Functions so this is in fact solely limited to NIC.) 73# 74 75 76# Global configuration settings. 77# 78[global] 79 rss_glb_config_mode = basicvirtual 80 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 81 82 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 83 # Page Size and a 64B L1 Cache Line Size. It programs the 84 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 85 # If a Master PF Driver finds itself on a machine with different 86 # parameters, then the Master PF Driver is responsible for initializing 87 # these parameters to appropriate values. 88 # 89 # Notes: 90 # 1. The Free List Buffer Sizes below are raw and the firmware will 91 # round them up to the Ingress Padding Boundary. 92 # 2. The SGE Timer Values below are expressed below in microseconds. 93 # The firmware will convert these values to Core Clock Ticks when 94 # it processes the configuration parameters. 95 # 96 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 97 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 98 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 99 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 100 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 101 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 102 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 103 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 104 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 105 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 106 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 107 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 108 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 109 reg[0x10a8] = 0x2000/0x2000 # SGE_DOORBELL_CONTROL 110 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 111 112 reg[0x7dc0] = 0x62f8849 # TP_SHIFT_CNT 113 114 # Selection of tuples for LE filter lookup, fields (and widths which 115 # must sum to <= 36): { IP Fragment (1), MPS Match Type (3), 116 # IP Protocol (8), [Inner] VLAN (17), Port (3), FCoE (1) } 117 # 118 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 119 120 # Percentage of dynamic memory (in either the EDRAM or external MEM) 121 # to use for TP RX payload 122 tp_pmrx = 30 123 124 # TP RX payload page size 125 tp_pmrx_pagesize = 64K 126 127 # TP number of RX channels 128 tp_nrxch = 0 # 0 (auto) = 1 129 130 # Percentage of dynamic memory (in either the EDRAM or external MEM) 131 # to use for TP TX payload 132 tp_pmtx = 50 133 134 # TP TX payload page size 135 tp_pmtx_pagesize = 64K 136 137 # TP number of TX channels 138 tp_ntxch = 0 # 0 (auto) = equal number of ports 139 140# Some "definitions" to make the rest of this a bit more readable. We support 141# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 142# per function per port ... 143# 144# NMSIX = 1088 # available MSI-X Vectors 145# NVI = 128 # available Virtual Interfaces 146# NMPSTCAM = 336 # MPS TCAM entries 147# 148# NPORTS = 4 # ports 149# NCPUS = 8 # CPUs we want to support scalably 150# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 151 152# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 153# PF" which many OS Drivers will use to manage most or all functions. 154# 155# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 156# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 157# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 158# will be specified as the "Ingress Queue Asynchronous Destination Index." 159# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 160# than or equal to the number of Ingress Queues ... 161# 162# NVI_NIC = 4 # NIC access to NPORTS 163# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 164# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 165# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 166# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 167# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 168# 169# NVI_OFLD = 0 # Offload uses NIC function to access ports 170# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 171# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 172# NEQ_OFLD = 16 # Offload Egress Queues (FL) 173# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 174# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 175# 176# NVI_RDMA = 0 # RDMA uses NIC function to access ports 177# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 178# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 179# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 180# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 181# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 182# 183# NEQ_WD = 128 # Wire Direct TX Queues and FLs 184# NETHCTRL_WD = 64 # Wire Direct TX Queues 185# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 186# 187# NVI_ISCSI = 4 # ISCSI access to NPORTS 188# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 189# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 190# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 191# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 192# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 193# 194# NVI_FCOE = 4 # FCOE access to NPORTS 195# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 196# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 197# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 198# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 199# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 200 201# Two extra Ingress Queues per function for Firmware Events and Forwarded 202# Interrupts, and two extra interrupts per function for Firmware Events (or a 203# Forwarded Interrupt Queue) and General Interrupts per function. 204# 205# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 206# # Forwarded Interrupts 207# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 208# # General Interrupts 209 210# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 211# their interrupts forwarded to another set of Forwarded Interrupt Queues. 212# 213# NVI_HYPERV = 16 # VMs we want to support 214# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 215# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 216# NEQ_HYPERV = 32 # VIQs Free Lists 217# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 218# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 219 220# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 221# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 222# 223# NVI_UNIFIED = 28 224# NFLIQ_UNIFIED = 106 225# NETHCTRL_UNIFIED = 32 226# NEQ_UNIFIED = 124 227# NMPSTCAM_UNIFIED = 40 228# 229# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 230# that up to 128 to make sure the Unified PF doesn't run out of resources. 231# 232# NMSIX_UNIFIED = 128 233# 234# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 235# which is 34 but they're probably safe with 32. 236# 237# NMSIX_STORAGE = 32 238 239# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 240# associated with it. Thus, the MSI-X Vector allocations we give to the 241# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 242# provision many more Virtual Functions than we can if the UnifiedPF were 243# one of PF0-3. 244# 245 246# All of the below PCI-E parameters are actually stored in various *_init.txt 247# files. We include them below essentially as comments. 248# 249# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 250# ports 0-3. 251# 252# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 253# 254# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 255# storage applications across all four possible ports. 256# 257# Additionally, since the UnifiedPF isn't one of the per-port Physical 258# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 259# different PCI Device IDs which will allow Unified and Per-Port Drivers 260# to directly select the type of Physical Function to which they wish to be 261# attached. 262# 263# Note that the actual values used for the PCI-E Intelectual Property will be 264# 1 less than those below since that's the way it "counts" things. For 265# readability, we use the number we actually mean ... 266# 267# PF0_INT = 8 # NCPUS 268# PF1_INT = 8 # NCPUS 269# PF2_INT = 8 # NCPUS 270# PF3_INT = 8 # NCPUS 271# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 272# 273# PF4_INT = 128 # NMSIX_UNIFIED 274# PF5_INT = 32 # NMSIX_STORAGE 275# PF6_INT = 32 # NMSIX_STORAGE 276# PF7_INT = 0 # Nothing Assigned 277# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 278# 279# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 280# 281# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 282# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 283# 284# NVF = 16 285 286# For those OSes which manage different ports on different PFs, we need 287# only enough resources to support a single port's NIC application functions 288# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 289# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 290# managed on the "storage PFs" (see below). 291# 292[function "0"] 293 nvf = 16 # NVF on this function 294 wx_caps = all # write/execute permissions for all commands 295 r_caps = all # read permissions for all commands 296 nvi = 1 # 1 port 297 niqflint = 8 # NCPUS "Queue Sets" 298 nethctrl = 8 # NCPUS "Queue Sets" 299 neq = 16 # niqflint + nethctrl Egress Queues 300 nexactf = 8 # number of exact MPSTCAM MAC filters 301 cmask = all # access to all channels 302 pmask = 0x1 # access to only one port 303 304[function "1"] 305 nvf = 16 # NVF on this function 306 wx_caps = all # write/execute permissions for all commands 307 r_caps = all # read permissions for all commands 308 nvi = 1 # 1 port 309 niqflint = 8 # NCPUS "Queue Sets" 310 nethctrl = 8 # NCPUS "Queue Sets" 311 neq = 16 # niqflint + nethctrl Egress Queues 312 nexactf = 8 # number of exact MPSTCAM MAC filters 313 cmask = all # access to all channels 314 pmask = 0x2 # access to only one port 315 316[function "2"] 317 nvf = 16 # NVF on this function 318 wx_caps = all # write/execute permissions for all commands 319 r_caps = all # read permissions for all commands 320 nvi = 1 # 1 port 321 niqflint = 8 # NCPUS "Queue Sets" 322 nethctrl = 8 # NCPUS "Queue Sets" 323 neq = 16 # niqflint + nethctrl Egress Queues 324 nexactf = 8 # number of exact MPSTCAM MAC filters 325 cmask = all # access to all channels 326 pmask = 0x4 # access to only one port 327 328[function "3"] 329 nvf = 16 # NVF on this function 330 wx_caps = all # write/execute permissions for all commands 331 r_caps = all # read permissions for all commands 332 nvi = 1 # 1 port 333 niqflint = 8 # NCPUS "Queue Sets" 334 nethctrl = 8 # NCPUS "Queue Sets" 335 neq = 16 # niqflint + nethctrl Egress Queues 336 nexactf = 8 # number of exact MPSTCAM MAC filters 337 cmask = all # access to all channels 338 pmask = 0x8 # access to only one port 339 340# Some OS Drivers manage all application functions for all ports via PF4. 341# Thus we need to provide a large number of resources here. For Egress 342# Queues we need to account for both TX Queues as well as Free List Queues 343# (because the host is responsible for producing Free List Buffers for the 344# hardware to consume). 345# 346[function "4"] 347 wx_caps = all # write/execute permissions for all commands 348 r_caps = all # read permissions for all commands 349 nvi = 28 # NVI_UNIFIED 350 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 351 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 352 neq = 256 # NEQ_UNIFIED + NEQ_WD 353 nexactf = 40 # NMPSTCAM_UNIFIED 354 cmask = all # access to all channels 355 pmask = all # access to all four ports ... 356 nethofld = 1024 # number of user mode ethernet flow contexts 357 nroute = 32 # number of routing region entries 358 nclip = 32 # number of clip region entries 359 nfilter = 496 # number of filter region entries 360 nserver = 496 # number of server region entries 361 nhash = 12288 # number of hash region entries 362 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu 363 tp_l2t = 3072 364 tp_ddp = 2 365 tp_ddp_iscsi = 2 366 tp_stag = 2 367 tp_pbl = 5 368 tp_rq = 7 369 370# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 371# need to have Virtual Interfaces on each of the four ports with up to NCPUS 372# "Queue Sets" each. 373# 374[function "5"] 375 wx_caps = all # write/execute permissions for all commands 376 r_caps = all # read permissions for all commands 377 nvi = 4 # NPORTS 378 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 379 nethctrl = 32 # NPORTS*NCPUS 380 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 381 nexactf = 4 # NPORTS 382 cmask = all # access to all channels 383 pmask = all # access to all four ports ... 384 nserver = 16 385 nhash = 2048 386 tp_l2t = 1024 387 protocol = iscsi_initiator_fofld 388 tp_ddp_iscsi = 2 389 iscsi_ntask = 2048 390 iscsi_nsess = 2048 391 iscsi_nconn_per_session = 1 392 iscsi_ninitiator_instance = 64 393 394[function "6"] 395 wx_caps = all # write/execute permissions for all commands 396 r_caps = all # read permissions for all commands 397 nvi = 4 # NPORTS 398 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 399 nethctrl = 32 # NPORTS*NCPUS 400 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 401 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 402 # which is OK since < MIN(SUM PF0..3, PF4) 403 # and we never load PF0..3 and PF4 concurrently 404 cmask = all # access to all channels 405 pmask = all # access to all four ports ... 406 nhash = 2048 407 protocol = fcoe_initiator 408 tp_ddp = 2 409 fcoe_nfcf = 16 410 fcoe_nvnp = 32 411 fcoe_nssn = 1024 412 413# The following function, 1023, is not an actual PCIE function but is used to 414# configure and reserve firmware internal resources that come from the global 415# resource pool. 416# 417[function "1023"] 418 wx_caps = all # write/execute permissions for all commands 419 r_caps = all # read permissions for all commands 420 nvi = 4 # NVI_UNIFIED 421 cmask = all # access to all channels 422 pmask = all # access to all four ports ... 423 nexactf = 8 # NPORTS + DCBX + 424 nfilter = 16 # number of filter region entries 425 426# For Virtual functions, we only allow NIC functionality and we only allow 427# access to one port (1 << PF). Note that because of limitations in the 428# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 429# and GTS registers, the number of Ingress and Egress Queues must be a power 430# of 2. 431# 432[function "0/*"] # NVF 433 wx_caps = 0x82 # DMAQ | VF 434 r_caps = 0x86 # DMAQ | VF | PORT 435 nvi = 1 # 1 port 436 niqflint = 4 # 2 "Queue Sets" + NXIQ 437 nethctrl = 2 # 2 "Queue Sets" 438 neq = 4 # 2 "Queue Sets" * 2 439 nexactf = 4 440 cmask = all # access to all channels 441 pmask = 0x1 # access to only one port ... 442 443[function "1/*"] # NVF 444 wx_caps = 0x82 # DMAQ | VF 445 r_caps = 0x86 # DMAQ | VF | PORT 446 nvi = 1 # 1 port 447 niqflint = 4 # 2 "Queue Sets" + NXIQ 448 nethctrl = 2 # 2 "Queue Sets" 449 neq = 4 # 2 "Queue Sets" * 2 450 nexactf = 4 451 cmask = all # access to all channels 452 pmask = 0x2 # access to only one port ... 453 454[function "2/*"] # NVF 455 wx_caps = 0x82 # DMAQ | VF 456 r_caps = 0x86 # DMAQ | VF | PORT 457 nvi = 1 # 1 port 458 niqflint = 4 # 2 "Queue Sets" + NXIQ 459 nethctrl = 2 # 2 "Queue Sets" 460 neq = 4 # 2 "Queue Sets" * 2 461 nexactf = 4 462 cmask = all # access to all channels 463 pmask = 0x4 # access to only one port ... 464 465[function "3/*"] # NVF 466 wx_caps = 0x82 # DMAQ | VF 467 r_caps = 0x86 # DMAQ | VF | PORT 468 nvi = 1 # 1 port 469 niqflint = 4 # 2 "Queue Sets" + NXIQ 470 nethctrl = 2 # 2 "Queue Sets" 471 neq = 4 # 2 "Queue Sets" * 2 472 nexactf = 4 473 cmask = all # access to all channels 474 pmask = 0x8 # access to only one port ... 475 476# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 477# for packets from the wire as well as the loopback path of the L2 switch. The 478# folling params control how the buffer memory is distributed and the L2 flow 479# control settings: 480# 481# bg_mem: %-age of mem to use for port/buffer group 482# lpbk_mem: %-age of port/bg mem to use for loopback 483# hwm: high watermark; bytes available when starting to send pause 484# frames (in units of 0.1 MTU) 485# lwm: low watermark; bytes remaining when sending 'unpause' frame 486# (in inuits of 0.1 MTU) 487# dwm: minimum delta between high and low watermark (in units of 100 488# Bytes) 489# 490[port "0"] 491 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 492 bg_mem = 25 493 lpbk_mem = 25 494 hwm = 30 495 lwm = 15 496 dwm = 30 497 498[port "1"] 499 dcb = ppp, dcbx 500 bg_mem = 25 501 lpbk_mem = 25 502 hwm = 30 503 lwm = 15 504 dwm = 30 505 506[port "2"] 507 dcb = ppp, dcbx 508 bg_mem = 25 509 lpbk_mem = 25 510 hwm = 30 511 lwm = 15 512 dwm = 30 513 514[port "3"] 515 dcb = ppp, dcbx 516 bg_mem = 25 517 lpbk_mem = 25 518 hwm = 30 519 lwm = 15 520 dwm = 30 521 522[fini] 523 version = 0x1425000d 524 checksum = 0x25c2f782 525 526# Total resources used by above allocations: 527# Virtual Interfaces: 104 528# Ingress Queues/w Free Lists and Interrupts: 526 529# Egress Queues: 702 530# MPS TCAM Entries: 336 531# MSI-X Vectors: 736 532# Virtual Functions: 64 533# 534# $FreeBSD$ 535# 536