1# Chelsio T4 Factory Default configuration file. 2# 3# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved. 4# 5# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF 6# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT 7# IN PHYSICAL DAMAGE TO T4 ADAPTERS. 8 9# This file provides the default, power-on configuration for 4-port T4-based 10# adapters shipped from the factory. These defaults are designed to address 11# the needs of the vast majority of T4 customers. The basic idea is to have 12# a default configuration which allows a customer to plug a T4 adapter in and 13# have it work regardless of OS, driver or application except in the most 14# unusual and/or demanding customer applications. 15# 16# Many of the T4 resources which are described by this configuration are 17# finite. This requires balancing the configuration/operation needs of 18# device drivers across OSes and a large number of customer application. 19# 20# Some of the more important resources to allocate and their constaints are: 21# 1. Virtual Interfaces: 128. 22# 2. Ingress Queues with Free Lists: 1024. PCI-E SR-IOV Virtual Functions 23# must use a power of 2 Ingress Queues. 24# 3. Egress Queues: 128K. PCI-E SR-IOV Virtual Functions must use a 25# power of 2 Egress Queues. 26# 4. MSI-X Vectors: 1088. A complication here is that the PCI-E SR-IOV 27# Virtual Functions based off of a Physical Function all get the 28# same umber of MSI-X Vectors as the base Physical Function. 29# Additionally, regardless of whether Virtual Functions are enabled or 30# not, their MSI-X "needs" are counted by the PCI-E implementation. 31# And finally, all Physical Funcations capable of supporting Virtual 32# Functions (PF0-3) must have the same number of configured TotalVFs in 33# their SR-IOV Capabilities. 34# 5. Multi-Port Support (MPS) TCAM: 336 entries to support MAC destination 35# address matching on Ingress Packets. 36# 37# Some of the important OS/Driver resource needs are: 38# 6. Some OS Drivers will manage all resources through a single Physical 39# Function (currently PF0 but it could be any Physical Function). Thus, 40# this "Unified PF" will need to have enough resources allocated to it 41# to allow for this. And because of the MSI-X resource allocation 42# constraints mentioned above, this probably means we'll either have to 43# severely limit the TotalVFs if we continue to use PF0 as the Unified PF 44# or we'll need to move the Unified PF into the PF4-7 range since those 45# Physical Functions don't have any Virtual Functions associated with 46# them. 47# 7. Some OS Drivers will manage different ports and functions (NIC, 48# storage, etc.) on different Physical Functions. For example, NIC 49# functions for ports 0-3 on PF0-3, FCoE on PF4, iSCSI on PF5, etc. 50# 51# Some of the customer application needs which need to be accommodated: 52# 8. Some customers will want to support large CPU count systems with 53# good scaling. Thus, we'll need to accommodate a number of 54# Ingress Queues and MSI-X Vectors to allow up to some number of CPUs 55# to be involved per port and per application function. For example, 56# in the case where all ports and application functions will be 57# managed via a single Unified PF and we want to accommodate scaling up 58# to 8 CPUs, we would want: 59# 60# 4 ports * 61# 3 application functions (NIC, FCoE, iSCSI) per port * 62# 8 Ingress Queue/MSI-X Vectors per application function 63# 64# for a total of 96 Ingress Queues and MSI-X Vectors on the Unified PF. 65# (Plus a few for Firmware Event Queues, etc.) 66# 67# 9. Some customers will want to use T4's PCI-E SR-IOV Capability to allow 68# Virtual Machines to directly access T4 functionality via SR-IOV 69# Virtual Functions and "PCI Device Passthrough" -- this is especially 70# true for the NIC application functionality. (Note that there is 71# currently no ability to use the TOE, FCoE, iSCSI, etc. via Virtual 72# Functions so this is in fact solely limited to NIC.) 73# 74 75 76# Global configuration settings. 77# 78[global] 79 rss_glb_config_mode = basicvirtual 80 rss_glb_config_options = tnlmapen,hashtoeplitz,tnlalllkp 81 82 # The following Scatter Gather Engine (SGE) settings assume a 4KB Host 83 # Page Size and a 64B L1 Cache Line Size. It programs the 84 # EgrStatusPageSize and IngPadBoundary to 64B and the PktShift to 2. 85 # If a Master PF Driver finds itself on a machine with different 86 # parameters, then the Master PF Driver is responsible for initializing 87 # these parameters to appropriate values. 88 # 89 # Notes: 90 # 1. The Free List Buffer Sizes below are raw and the firmware will 91 # round them up to the Ingress Padding Boundary. 92 # 2. The SGE Timer Values below are expressed below in microseconds. 93 # The firmware will convert these values to Core Clock Ticks when 94 # it processes the configuration parameters. 95 # 96 reg[0x1008] = 0x40810/0x21c70 # SGE_CONTROL 97 reg[0x100c] = 0x22222222 # SGE_HOST_PAGE_SIZE 98 reg[0x10a0] = 0x01040810 # SGE_INGRESS_RX_THRESHOLD 99 reg[0x1044] = 4096 # SGE_FL_BUFFER_SIZE0 100 reg[0x1048] = 65536 # SGE_FL_BUFFER_SIZE1 101 reg[0x104c] = 1536 # SGE_FL_BUFFER_SIZE2 102 reg[0x1050] = 9024 # SGE_FL_BUFFER_SIZE3 103 reg[0x1054] = 9216 # SGE_FL_BUFFER_SIZE4 104 reg[0x1058] = 2048 # SGE_FL_BUFFER_SIZE5 105 reg[0x105c] = 128 # SGE_FL_BUFFER_SIZE6 106 reg[0x1060] = 8192 # SGE_FL_BUFFER_SIZE7 107 reg[0x1064] = 16384 # SGE_FL_BUFFER_SIZE8 108 reg[0x10a4] = 0xa000a000/0xf000f000 # SGE_DBFIFO_STATUS 109 reg[0x10a8] = 0x2000/0x2000 # SGE_DOORBELL_CONTROL 110 sge_timer_value = 5, 10, 20, 50, 100, 200 # SGE_TIMER_VALUE* in usecs 111 112 # enable TP_OUT_CONFIG.IPIDSPLITMODE 113 reg[0x7d04] = 0x00010000/0x00010000 114 115 reg[0x7dc0] = 0x62f8849 # TP_SHIFT_CNT 116 117 # TP_VLAN_PRI_MAP to select filter tuples 118 # filter tuples : fragmentation, mpshittype, macmatch, ethertype, 119 # protocol, tos, vlan, vnic_id, port, fcoe 120 # valid filterModes are described the Terminator 4 Data Book 121 filterMode = fragmentation, mpshittype, protocol, vlan, port, fcoe 122 123 # filter tuples enforced in LE active region (equal to or subset of filterMode) 124 filterMask = protocol, fcoe 125 126 # Percentage of dynamic memory (in either the EDRAM or external MEM) 127 # to use for TP RX payload 128 tp_pmrx = 34 129 130 # TP RX payload page size 131 tp_pmrx_pagesize = 64K 132 133 # TP number of RX channels 134 tp_nrxch = 0 # 0 (auto) = 1 135 136 # Percentage of dynamic memory (in either the EDRAM or external MEM) 137 # to use for TP TX payload 138 tp_pmtx = 32 139 140 # TP TX payload page size 141 tp_pmtx_pagesize = 64K 142 143 # TP number of TX channels 144 tp_ntxch = 0 # 0 (auto) = equal number of ports 145 146 # TP OFLD MTUs 147 tp_mtus = 88, 256, 512, 576, 808, 1024, 1280, 1488, 1500, 2002, 2048, 4096, 4352, 8192, 9000, 9600 148 149# Some "definitions" to make the rest of this a bit more readable. We support 150# 4 ports, 3 functions (NIC, FCoE and iSCSI), scaling up to 8 "CPU Queue Sets" 151# per function per port ... 152# 153# NMSIX = 1088 # available MSI-X Vectors 154# NVI = 128 # available Virtual Interfaces 155# NMPSTCAM = 336 # MPS TCAM entries 156# 157# NPORTS = 4 # ports 158# NCPUS = 8 # CPUs we want to support scalably 159# NFUNCS = 3 # functions per port (NIC, FCoE, iSCSI) 160 161# Breakdown of Virtual Interface/Queue/Interrupt resources for the "Unified 162# PF" which many OS Drivers will use to manage most or all functions. 163# 164# Each Ingress Queue can use one MSI-X interrupt but some Ingress Queues can 165# use Forwarded Interrupt Ingress Queues. For these latter, an Ingress Queue 166# would be created and the Queue ID of a Forwarded Interrupt Ingress Queue 167# will be specified as the "Ingress Queue Asynchronous Destination Index." 168# Thus, the number of MSI-X Vectors assigned to the Unified PF will be less 169# than or equal to the number of Ingress Queues ... 170# 171# NVI_NIC = 4 # NIC access to NPORTS 172# NFLIQ_NIC = 32 # NIC Ingress Queues with Free Lists 173# NETHCTRL_NIC = 32 # NIC Ethernet Control/TX Queues 174# NEQ_NIC = 64 # NIC Egress Queues (FL, ETHCTRL/TX) 175# NMPSTCAM_NIC = 16 # NIC MPS TCAM Entries (NPORTS*4) 176# NMSIX_NIC = 32 # NIC MSI-X Interrupt Vectors (FLIQ) 177# 178# NVI_OFLD = 0 # Offload uses NIC function to access ports 179# NFLIQ_OFLD = 16 # Offload Ingress Queues with Free Lists 180# NETHCTRL_OFLD = 0 # Offload Ethernet Control/TX Queues 181# NEQ_OFLD = 16 # Offload Egress Queues (FL) 182# NMPSTCAM_OFLD = 0 # Offload MPS TCAM Entries (uses NIC's) 183# NMSIX_OFLD = 16 # Offload MSI-X Interrupt Vectors (FLIQ) 184# 185# NVI_RDMA = 0 # RDMA uses NIC function to access ports 186# NFLIQ_RDMA = 4 # RDMA Ingress Queues with Free Lists 187# NETHCTRL_RDMA = 0 # RDMA Ethernet Control/TX Queues 188# NEQ_RDMA = 4 # RDMA Egress Queues (FL) 189# NMPSTCAM_RDMA = 0 # RDMA MPS TCAM Entries (uses NIC's) 190# NMSIX_RDMA = 4 # RDMA MSI-X Interrupt Vectors (FLIQ) 191# 192# NEQ_WD = 128 # Wire Direct TX Queues and FLs 193# NETHCTRL_WD = 64 # Wire Direct TX Queues 194# NFLIQ_WD = 64 ` # Wire Direct Ingress Queues with Free Lists 195# 196# NVI_ISCSI = 4 # ISCSI access to NPORTS 197# NFLIQ_ISCSI = 4 # ISCSI Ingress Queues with Free Lists 198# NETHCTRL_ISCSI = 0 # ISCSI Ethernet Control/TX Queues 199# NEQ_ISCSI = 4 # ISCSI Egress Queues (FL) 200# NMPSTCAM_ISCSI = 4 # ISCSI MPS TCAM Entries (NPORTS) 201# NMSIX_ISCSI = 4 # ISCSI MSI-X Interrupt Vectors (FLIQ) 202# 203# NVI_FCOE = 4 # FCOE access to NPORTS 204# NFLIQ_FCOE = 34 # FCOE Ingress Queues with Free Lists 205# NETHCTRL_FCOE = 32 # FCOE Ethernet Control/TX Queues 206# NEQ_FCOE = 66 # FCOE Egress Queues (FL) 207# NMPSTCAM_FCOE = 32 # FCOE MPS TCAM Entries (NPORTS) 208# NMSIX_FCOE = 34 # FCOE MSI-X Interrupt Vectors (FLIQ) 209 210# Two extra Ingress Queues per function for Firmware Events and Forwarded 211# Interrupts, and two extra interrupts per function for Firmware Events (or a 212# Forwarded Interrupt Queue) and General Interrupts per function. 213# 214# NFLIQ_EXTRA = 6 # "extra" Ingress Queues 2*NFUNCS (Firmware and 215# # Forwarded Interrupts 216# NMSIX_EXTRA = 6 # extra interrupts 2*NFUNCS (Firmware and 217# # General Interrupts 218 219# Microsoft HyperV resources. The HyperV Virtual Ingress Queues will have 220# their interrupts forwarded to another set of Forwarded Interrupt Queues. 221# 222# NVI_HYPERV = 16 # VMs we want to support 223# NVIIQ_HYPERV = 2 # Virtual Ingress Queues with Free Lists per VM 224# NFLIQ_HYPERV = 40 # VIQs + NCPUS Forwarded Interrupt Queues 225# NEQ_HYPERV = 32 # VIQs Free Lists 226# NMPSTCAM_HYPERV = 16 # MPS TCAM Entries (NVI_HYPERV) 227# NMSIX_HYPERV = 8 # NCPUS Forwarded Interrupt Queues 228 229# Adding all of the above Unified PF resource needs together: (NIC + OFLD + 230# RDMA + ISCSI + FCOE + EXTRA + HYPERV) 231# 232# NVI_UNIFIED = 28 233# NFLIQ_UNIFIED = 106 234# NETHCTRL_UNIFIED = 32 235# NEQ_UNIFIED = 124 236# NMPSTCAM_UNIFIED = 40 237# 238# The sum of all the MSI-X resources above is 74 MSI-X Vectors but we'll round 239# that up to 128 to make sure the Unified PF doesn't run out of resources. 240# 241# NMSIX_UNIFIED = 128 242# 243# The Storage PFs could need up to NPORTS*NCPUS + NMSIX_EXTRA MSI-X Vectors 244# which is 34 but they're probably safe with 32. 245# 246# NMSIX_STORAGE = 32 247 248# Note: The UnifiedPF is PF4 which doesn't have any Virtual Functions 249# associated with it. Thus, the MSI-X Vector allocations we give to the 250# UnifiedPF aren't inherited by any Virtual Functions. As a result we can 251# provision many more Virtual Functions than we can if the UnifiedPF were 252# one of PF0-3. 253# 254 255# All of the below PCI-E parameters are actually stored in various *_init.txt 256# files. We include them below essentially as comments. 257# 258# For PF0-3 we assign 8 vectors each for NIC Ingress Queues of the associated 259# ports 0-3. 260# 261# For PF4, the Unified PF, we give it an MSI-X Table Size as outlined above. 262# 263# For PF5-6 we assign enough MSI-X Vectors to support FCoE and iSCSI 264# storage applications across all four possible ports. 265# 266# Additionally, since the UnifiedPF isn't one of the per-port Physical 267# Functions, we give the UnifiedPF and the PF0-3 Physical Functions 268# different PCI Device IDs which will allow Unified and Per-Port Drivers 269# to directly select the type of Physical Function to which they wish to be 270# attached. 271# 272# Note that the actual values used for the PCI-E Intelectual Property will be 273# 1 less than those below since that's the way it "counts" things. For 274# readability, we use the number we actually mean ... 275# 276# PF0_INT = 8 # NCPUS 277# PF1_INT = 8 # NCPUS 278# PF2_INT = 8 # NCPUS 279# PF3_INT = 8 # NCPUS 280# PF0_3_INT = 32 # PF0_INT + PF1_INT + PF2_INT + PF3_INT 281# 282# PF4_INT = 128 # NMSIX_UNIFIED 283# PF5_INT = 32 # NMSIX_STORAGE 284# PF6_INT = 32 # NMSIX_STORAGE 285# PF7_INT = 0 # Nothing Assigned 286# PF4_7_INT = 192 # PF4_INT + PF5_INT + PF6_INT + PF7_INT 287# 288# PF0_7_INT = 224 # PF0_3_INT + PF4_7_INT 289# 290# With the above we can get 17 VFs/PF0-3 (limited by 336 MPS TCAM entries) 291# but we'll lower that to 16 to make our total 64 and a nice power of 2 ... 292# 293# NVF = 16 294 295# For those OSes which manage different ports on different PFs, we need 296# only enough resources to support a single port's NIC application functions 297# on PF0-3. The below assumes that we're only doing NIC with NCPUS "Queue 298# Sets" for ports 0-3. The FCoE and iSCSI functions for such OSes will be 299# managed on the "storage PFs" (see below). 300# 301[function "0"] 302 nvf = 16 # NVF on this function 303 wx_caps = all # write/execute permissions for all commands 304 r_caps = all # read permissions for all commands 305 nvi = 1 # 1 port 306 niqflint = 8 # NCPUS "Queue Sets" 307 nethctrl = 8 # NCPUS "Queue Sets" 308 neq = 16 # niqflint + nethctrl Egress Queues 309 nexactf = 8 # number of exact MPSTCAM MAC filters 310 cmask = all # access to all channels 311 pmask = 0x1 # access to only one port 312 313[function "1"] 314 nvf = 16 # NVF on this function 315 wx_caps = all # write/execute permissions for all commands 316 r_caps = all # read permissions for all commands 317 nvi = 1 # 1 port 318 niqflint = 8 # NCPUS "Queue Sets" 319 nethctrl = 8 # NCPUS "Queue Sets" 320 neq = 16 # niqflint + nethctrl Egress Queues 321 nexactf = 8 # number of exact MPSTCAM MAC filters 322 cmask = all # access to all channels 323 pmask = 0x2 # access to only one port 324 325[function "2"] 326 nvf = 16 # NVF on this function 327 wx_caps = all # write/execute permissions for all commands 328 r_caps = all # read permissions for all commands 329 nvi = 1 # 1 port 330 niqflint = 8 # NCPUS "Queue Sets" 331 nethctrl = 8 # NCPUS "Queue Sets" 332 neq = 16 # niqflint + nethctrl Egress Queues 333 nexactf = 8 # number of exact MPSTCAM MAC filters 334 cmask = all # access to all channels 335 pmask = 0x4 # access to only one port 336 337[function "3"] 338 nvf = 16 # NVF on this function 339 wx_caps = all # write/execute permissions for all commands 340 r_caps = all # read permissions for all commands 341 nvi = 1 # 1 port 342 niqflint = 8 # NCPUS "Queue Sets" 343 nethctrl = 8 # NCPUS "Queue Sets" 344 neq = 16 # niqflint + nethctrl Egress Queues 345 nexactf = 8 # number of exact MPSTCAM MAC filters 346 cmask = all # access to all channels 347 pmask = 0x8 # access to only one port 348 349# Some OS Drivers manage all application functions for all ports via PF4. 350# Thus we need to provide a large number of resources here. For Egress 351# Queues we need to account for both TX Queues as well as Free List Queues 352# (because the host is responsible for producing Free List Buffers for the 353# hardware to consume). 354# 355[function "4"] 356 wx_caps = all # write/execute permissions for all commands 357 r_caps = all # read permissions for all commands 358 nvi = 28 # NVI_UNIFIED 359 niqflint = 170 # NFLIQ_UNIFIED + NLFIQ_WD 360 nethctrl = 100 # NETHCTRL_UNIFIED + NETHCTRL_WD 361 neq = 256 # NEQ_UNIFIED + NEQ_WD 362 nexactf = 40 # NMPSTCAM_UNIFIED 363 cmask = all # access to all channels 364 pmask = all # access to all four ports ... 365 nethofld = 1024 # number of user mode ethernet flow contexts 366 nroute = 32 # number of routing region entries 367 nclip = 32 # number of clip region entries 368 nfilter = 496 # number of filter region entries 369 nserver = 496 # number of server region entries 370 nhash = 12288 # number of hash region entries 371 protocol = nic_vm, ofld, rddp, rdmac, iscsi_initiator_pdu, iscsi_target_pdu 372 tp_l2t = 3072 373 tp_ddp = 3 374 tp_ddp_iscsi = 2 375 tp_stag = 3 376 tp_pbl = 10 377 tp_rq = 13 378 379# We have FCoE and iSCSI storage functions on PF5 and PF6 each of which may 380# need to have Virtual Interfaces on each of the four ports with up to NCPUS 381# "Queue Sets" each. 382# 383[function "5"] 384 wx_caps = all # write/execute permissions for all commands 385 r_caps = all # read permissions for all commands 386 nvi = 4 # NPORTS 387 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 388 nethctrl = 32 # NPORTS*NCPUS 389 neq = 64 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) 390 nexactf = 4 # NPORTS 391 cmask = all # access to all channels 392 pmask = all # access to all four ports ... 393 nserver = 16 394 nhash = 2048 395 tp_l2t = 1024 396 protocol = iscsi_initiator_fofld 397 tp_ddp_iscsi = 2 398 iscsi_ntask = 2048 399 iscsi_nsess = 2048 400 iscsi_nconn_per_session = 1 401 iscsi_ninitiator_instance = 64 402 403[function "6"] 404 wx_caps = all # write/execute permissions for all commands 405 r_caps = all # read permissions for all commands 406 nvi = 4 # NPORTS 407 niqflint = 34 # NPORTS*NCPUS + NMSIX_EXTRA 408 nethctrl = 32 # NPORTS*NCPUS 409 neq = 66 # NPORTS*NCPUS * 2 (FL, ETHCTRL/TX) + 2 (EXTRA) 410 nexactf = 32 # NPORTS + adding 28 exact entries for FCoE 411 # which is OK since < MIN(SUM PF0..3, PF4) 412 # and we never load PF0..3 and PF4 concurrently 413 cmask = all # access to all channels 414 pmask = all # access to all four ports ... 415 nhash = 2048 416 protocol = fcoe_initiator 417 tp_ddp = 1 418 fcoe_nfcf = 16 419 fcoe_nvnp = 32 420 fcoe_nssn = 1024 421 422# The following function, 1023, is not an actual PCIE function but is used to 423# configure and reserve firmware internal resources that come from the global 424# resource pool. 425# 426[function "1023"] 427 wx_caps = all # write/execute permissions for all commands 428 r_caps = all # read permissions for all commands 429 nvi = 4 # NVI_UNIFIED 430 cmask = all # access to all channels 431 pmask = all # access to all four ports ... 432 nexactf = 8 # NPORTS + DCBX + 433 nfilter = 16 # number of filter region entries 434 435# For Virtual functions, we only allow NIC functionality and we only allow 436# access to one port (1 << PF). Note that because of limitations in the 437# Scatter Gather Engine (SGE) hardware which checks writes to VF KDOORBELL 438# and GTS registers, the number of Ingress and Egress Queues must be a power 439# of 2. 440# 441[function "0/*"] # NVF 442 wx_caps = 0x82 # DMAQ | VF 443 r_caps = 0x86 # DMAQ | VF | PORT 444 nvi = 1 # 1 port 445 niqflint = 4 # 2 "Queue Sets" + NXIQ 446 nethctrl = 2 # 2 "Queue Sets" 447 neq = 4 # 2 "Queue Sets" * 2 448 nexactf = 4 449 cmask = all # access to all channels 450 pmask = 0x1 # access to only one port ... 451 452[function "1/*"] # NVF 453 wx_caps = 0x82 # DMAQ | VF 454 r_caps = 0x86 # DMAQ | VF | PORT 455 nvi = 1 # 1 port 456 niqflint = 4 # 2 "Queue Sets" + NXIQ 457 nethctrl = 2 # 2 "Queue Sets" 458 neq = 4 # 2 "Queue Sets" * 2 459 nexactf = 4 460 cmask = all # access to all channels 461 pmask = 0x2 # access to only one port ... 462 463[function "2/*"] # NVF 464 wx_caps = 0x82 # DMAQ | VF 465 r_caps = 0x86 # DMAQ | VF | PORT 466 nvi = 1 # 1 port 467 niqflint = 4 # 2 "Queue Sets" + NXIQ 468 nethctrl = 2 # 2 "Queue Sets" 469 neq = 4 # 2 "Queue Sets" * 2 470 nexactf = 4 471 cmask = all # access to all channels 472 pmask = 0x4 # access to only one port ... 473 474[function "3/*"] # NVF 475 wx_caps = 0x82 # DMAQ | VF 476 r_caps = 0x86 # DMAQ | VF | PORT 477 nvi = 1 # 1 port 478 niqflint = 4 # 2 "Queue Sets" + NXIQ 479 nethctrl = 2 # 2 "Queue Sets" 480 neq = 4 # 2 "Queue Sets" * 2 481 nexactf = 4 482 cmask = all # access to all channels 483 pmask = 0x8 # access to only one port ... 484 485# MPS features a 196608 bytes ingress buffer that is used for ingress buffering 486# for packets from the wire as well as the loopback path of the L2 switch. The 487# folling params control how the buffer memory is distributed and the L2 flow 488# control settings: 489# 490# bg_mem: %-age of mem to use for port/buffer group 491# lpbk_mem: %-age of port/bg mem to use for loopback 492# hwm: high watermark; bytes available when starting to send pause 493# frames (in units of 0.1 MTU) 494# lwm: low watermark; bytes remaining when sending 'unpause' frame 495# (in inuits of 0.1 MTU) 496# dwm: minimum delta between high and low watermark (in units of 100 497# Bytes) 498# 499# 500 501[port "0"] 502 dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload 503 bg_mem = 25 504 lpbk_mem = 25 505 hwm = 30 506 lwm = 15 507 dwm = 30 508 dcb_app_tlv[0] = 0x8906, ethertype, 3 509 dcb_app_tlv[1] = 0x8914, ethertype, 3 510 dcb_app_tlv[2] = 3260, socketnum, 5 511 512[port "1"] 513 dcb = ppp, dcbx 514 bg_mem = 25 515 lpbk_mem = 25 516 hwm = 30 517 lwm = 15 518 dwm = 30 519 dcb_app_tlv[0] = 0x8906, ethertype, 3 520 dcb_app_tlv[1] = 0x8914, ethertype, 3 521 dcb_app_tlv[2] = 3260, socketnum, 5 522 523[port "2"] 524 dcb = ppp, dcbx 525 bg_mem = 25 526 lpbk_mem = 25 527 hwm = 30 528 lwm = 15 529 dwm = 30 530 dcb_app_tlv[0] = 0x8906, ethertype, 3 531 dcb_app_tlv[1] = 0x8914, ethertype, 3 532 dcb_app_tlv[2] = 3260, socketnum, 5 533 534[port "3"] 535 dcb = ppp, dcbx 536 bg_mem = 25 537 lpbk_mem = 25 538 hwm = 30 539 lwm = 15 540 dwm = 30 541 dcb_app_tlv[0] = 0x8906, ethertype, 3 542 dcb_app_tlv[1] = 0x8914, ethertype, 3 543 dcb_app_tlv[2] = 3260, socketnum, 5 544 545[fini] 546 version = 0x14250012 547 checksum = 0xd9ae0325 548 549# Total resources used by above allocations: 550# Virtual Interfaces: 104 551# Ingress Queues/w Free Lists and Interrupts: 526 552# Egress Queues: 702 553# MPS TCAM Entries: 336 554# MSI-X Vectors: 736 555# Virtual Functions: 64 556# 557# $FreeBSD$ 558# 559