1 /*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Chelsio T5xx iSCSI driver 6 * 7 * Written by: Sreenivasa Honnur <shonnur@chelsio.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_inet.h" 35 #include "opt_inet6.h" 36 37 #include <sys/types.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/module.h> 41 #include <sys/systm.h> 42 43 #ifdef TCP_OFFLOAD 44 #include <sys/errno.h> 45 #include <sys/kthread.h> 46 #include <sys/smp.h> 47 #include <sys/socket.h> 48 #include <sys/socketvar.h> 49 #include <sys/mbuf.h> 50 #include <sys/lock.h> 51 #include <sys/mutex.h> 52 #include <sys/condvar.h> 53 54 #include <netinet/in.h> 55 #include <netinet/in_pcb.h> 56 #include <netinet/toecore.h> 57 #include <netinet/tcp_var.h> 58 #include <netinet/tcp_fsm.h> 59 60 #include <cam/scsi/scsi_all.h> 61 #include <cam/scsi/scsi_da.h> 62 #include <cam/ctl/ctl_io.h> 63 #include <cam/ctl/ctl.h> 64 #include <cam/ctl/ctl_backend.h> 65 #include <cam/ctl/ctl_error.h> 66 #include <cam/ctl/ctl_frontend.h> 67 #include <cam/ctl/ctl_debug.h> 68 #include <cam/ctl/ctl_ha.h> 69 #include <cam/ctl/ctl_ioctl.h> 70 71 #include <dev/iscsi/icl.h> 72 #include <dev/iscsi/iscsi_proto.h> 73 #include <dev/iscsi/iscsi_ioctl.h> 74 #include <dev/iscsi/iscsi.h> 75 #include <cam/ctl/ctl_frontend_iscsi.h> 76 77 #include <cam/cam.h> 78 #include <cam/cam_ccb.h> 79 #include <cam/cam_xpt.h> 80 #include <cam/cam_debug.h> 81 #include <cam/cam_sim.h> 82 #include <cam/cam_xpt_sim.h> 83 #include <cam/cam_xpt_periph.h> 84 #include <cam/cam_periph.h> 85 #include <cam/cam_compat.h> 86 #include <cam/scsi/scsi_message.h> 87 88 #include "common/common.h" 89 #include "common/t4_msg.h" 90 #include "common/t4_regs.h" /* for PCIE_MEM_ACCESS */ 91 #include "tom/t4_tom.h" 92 #include "cxgbei.h" 93 #include "cxgbei_ulp2_ddp.h" 94 95 static int worker_thread_count; 96 static struct cxgbei_worker_thread_softc *cwt_softc; 97 static struct proc *cxgbei_proc; 98 99 /* XXXNP some header instead. */ 100 struct icl_pdu *icl_cxgbei_new_pdu(int); 101 void icl_cxgbei_new_pdu_set_conn(struct icl_pdu *, struct icl_conn *); 102 void icl_cxgbei_conn_pdu_free(struct icl_conn *, struct icl_pdu *); 103 104 /* 105 * Direct Data Placement - 106 * Directly place the iSCSI Data-In or Data-Out PDU's payload into pre-posted 107 * final destination host-memory buffers based on the Initiator Task Tag (ITT) 108 * in Data-In or Target Task Tag (TTT) in Data-Out PDUs. 109 * The host memory address is programmed into h/w in the format of pagepod 110 * entries. 111 * The location of the pagepod entry is encoded into ddp tag which is used as 112 * the base for ITT/TTT. 113 */ 114 115 /* 116 * functions to program the pagepod in h/w 117 */ 118 static void inline 119 ppod_set(struct pagepod *ppod, 120 struct cxgbei_ulp2_pagepod_hdr *hdr, 121 struct cxgbei_ulp2_gather_list *gl, 122 unsigned int pidx) 123 { 124 int i; 125 126 memcpy(ppod, hdr, sizeof(*hdr)); 127 128 for (i = 0; i < (PPOD_PAGES + 1); i++, pidx++) { 129 ppod->addr[i] = pidx < gl->nelem ? 130 cpu_to_be64(gl->dma_sg[pidx].phys_addr) : 0ULL; 131 } 132 } 133 134 static void inline 135 ppod_clear(struct pagepod *ppod) 136 { 137 memset(ppod, 0, sizeof(*ppod)); 138 } 139 140 static inline void 141 ulp_mem_io_set_hdr(struct adapter *sc, int tid, struct ulp_mem_io *req, 142 unsigned int wr_len, unsigned int dlen, 143 unsigned int pm_addr) 144 { 145 struct ulptx_idata *idata = (struct ulptx_idata *)(req + 1); 146 147 INIT_ULPTX_WR(req, wr_len, 0, 0); 148 req->cmd = cpu_to_be32(V_ULPTX_CMD(ULP_TX_MEM_WRITE) | 149 V_ULP_MEMIO_ORDER(is_t4(sc)) | 150 V_T5_ULP_MEMIO_IMM(is_t5(sc))); 151 req->dlen = htonl(V_ULP_MEMIO_DATA_LEN(dlen >> 5)); 152 req->len16 = htonl(DIV_ROUND_UP(wr_len - sizeof(req->wr), 16) 153 | V_FW_WR_FLOWID(tid)); 154 req->lock_addr = htonl(V_ULP_MEMIO_ADDR(pm_addr >> 5)); 155 156 idata->cmd_more = htonl(V_ULPTX_CMD(ULP_TX_SC_IMM)); 157 idata->len = htonl(dlen); 158 } 159 160 #define PPOD_SIZE sizeof(struct pagepod) 161 #define ULPMEM_IDATA_MAX_NPPODS 1 /* 256/PPOD_SIZE */ 162 #define PCIE_MEMWIN_MAX_NPPODS 16 /* 1024/PPOD_SIZE */ 163 164 static int 165 ppod_write_idata(struct cxgbei_data *ci, 166 struct cxgbei_ulp2_pagepod_hdr *hdr, 167 unsigned int idx, unsigned int npods, 168 struct cxgbei_ulp2_gather_list *gl, 169 unsigned int gl_pidx, struct toepcb *toep) 170 { 171 u_int dlen = PPOD_SIZE * npods; 172 u_int pm_addr = idx * PPOD_SIZE + ci->llimit; 173 u_int wr_len = roundup(sizeof(struct ulp_mem_io) + 174 sizeof(struct ulptx_idata) + dlen, 16); 175 struct ulp_mem_io *req; 176 struct ulptx_idata *idata; 177 struct pagepod *ppod; 178 u_int i; 179 struct wrqe *wr; 180 struct adapter *sc = toep->vi->pi->adapter; 181 182 wr = alloc_wrqe(wr_len, toep->ctrlq); 183 if (wr == NULL) { 184 CXGBE_UNIMPLEMENTED("ppod_write_idata: alloc_wrqe failure"); 185 return (ENOMEM); 186 } 187 188 req = wrtod(wr); 189 memset(req, 0, wr_len); 190 ulp_mem_io_set_hdr(sc, toep->tid, req, wr_len, dlen, pm_addr); 191 idata = (struct ulptx_idata *)(req + 1); 192 193 ppod = (struct pagepod *)(idata + 1); 194 for (i = 0; i < npods; i++, ppod++, gl_pidx += PPOD_PAGES) { 195 if (!hdr) /* clear the pagepod */ 196 ppod_clear(ppod); 197 else /* set the pagepod */ 198 ppod_set(ppod, hdr, gl, gl_pidx); 199 } 200 201 t4_wrq_tx(sc, wr); 202 return 0; 203 } 204 205 int 206 t4_ddp_set_map(struct cxgbei_data *ci, void *iccp, 207 struct cxgbei_ulp2_pagepod_hdr *hdr, u_int idx, u_int npods, 208 struct cxgbei_ulp2_gather_list *gl, int reply) 209 { 210 struct icl_cxgbei_conn *icc = (struct icl_cxgbei_conn *)iccp; 211 struct toepcb *toep = icc->toep; 212 int err; 213 unsigned int pidx = 0, w_npods = 0, cnt; 214 215 /* 216 * on T4, if we use a mix of IMMD and DSGL with ULP_MEM_WRITE, 217 * the order would not be guaranteed, so we will stick with IMMD 218 */ 219 gl->tid = toep->tid; 220 gl->port_id = toep->vi->pi->port_id; 221 gl->egress_dev = (void *)toep->vi->ifp; 222 223 /* send via immediate data */ 224 for (; w_npods < npods; idx += cnt, w_npods += cnt, 225 pidx += PPOD_PAGES) { 226 cnt = npods - w_npods; 227 if (cnt > ULPMEM_IDATA_MAX_NPPODS) 228 cnt = ULPMEM_IDATA_MAX_NPPODS; 229 err = ppod_write_idata(ci, hdr, idx, cnt, gl, pidx, toep); 230 if (err) { 231 printf("%s: ppod_write_idata failed\n", __func__); 232 break; 233 } 234 } 235 return err; 236 } 237 238 void 239 t4_ddp_clear_map(struct cxgbei_data *ci, struct cxgbei_ulp2_gather_list *gl, 240 u_int tag, u_int idx, u_int npods, struct icl_cxgbei_conn *icc) 241 { 242 struct toepcb *toep = icc->toep; 243 int err = -1; 244 u_int pidx = 0; 245 u_int w_npods = 0; 246 u_int cnt; 247 248 for (; w_npods < npods; idx += cnt, w_npods += cnt, 249 pidx += PPOD_PAGES) { 250 cnt = npods - w_npods; 251 if (cnt > ULPMEM_IDATA_MAX_NPPODS) 252 cnt = ULPMEM_IDATA_MAX_NPPODS; 253 err = ppod_write_idata(ci, NULL, idx, cnt, gl, 0, toep); 254 if (err) 255 break; 256 } 257 } 258 259 static int 260 cxgbei_map_sg(struct cxgbei_sgl *sgl, struct ccb_scsiio *csio) 261 { 262 unsigned int data_len = csio->dxfer_len; 263 unsigned int sgoffset = (uint64_t)csio->data_ptr & PAGE_MASK; 264 unsigned int nsge; 265 unsigned char *sgaddr = csio->data_ptr; 266 unsigned int len = 0; 267 268 nsge = (csio->dxfer_len + sgoffset + PAGE_SIZE - 1) >> PAGE_SHIFT; 269 sgl->sg_addr = sgaddr; 270 sgl->sg_offset = sgoffset; 271 if (data_len < (PAGE_SIZE - sgoffset)) 272 len = data_len; 273 else 274 len = PAGE_SIZE - sgoffset; 275 276 sgl->sg_length = len; 277 278 data_len -= len; 279 sgaddr += len; 280 sgl = sgl+1; 281 282 while (data_len > 0) { 283 sgl->sg_addr = sgaddr; 284 len = (data_len < PAGE_SIZE)? data_len: PAGE_SIZE; 285 sgl->sg_length = len; 286 sgaddr += len; 287 data_len -= len; 288 sgl = sgl + 1; 289 } 290 291 return nsge; 292 } 293 294 static int 295 cxgbei_map_sg_tgt(struct cxgbei_sgl *sgl, union ctl_io *io) 296 { 297 unsigned int data_len, sgoffset, nsge; 298 unsigned char *sgaddr; 299 unsigned int len = 0, index = 0, ctl_sg_count, i; 300 struct ctl_sg_entry ctl_sg_entry, *ctl_sglist; 301 302 if (io->scsiio.kern_sg_entries > 0) { 303 ctl_sglist = (struct ctl_sg_entry *)io->scsiio.kern_data_ptr; 304 ctl_sg_count = io->scsiio.kern_sg_entries; 305 } else { 306 ctl_sglist = &ctl_sg_entry; 307 ctl_sglist->addr = io->scsiio.kern_data_ptr; 308 ctl_sglist->len = io->scsiio.kern_data_len; 309 ctl_sg_count = 1; 310 } 311 312 sgaddr = sgl->sg_addr = ctl_sglist[index].addr; 313 sgoffset = sgl->sg_offset = (uint64_t)sgl->sg_addr & PAGE_MASK; 314 data_len = ctl_sglist[index].len; 315 316 if (data_len < (PAGE_SIZE - sgoffset)) 317 len = data_len; 318 else 319 len = PAGE_SIZE - sgoffset; 320 321 sgl->sg_length = len; 322 323 data_len -= len; 324 sgaddr += len; 325 sgl = sgl+1; 326 327 len = 0; 328 for (i = 0; i< ctl_sg_count; i++) 329 len += ctl_sglist[i].len; 330 nsge = (len + sgoffset + PAGE_SIZE -1) >> PAGE_SHIFT; 331 while (data_len > 0) { 332 sgl->sg_addr = sgaddr; 333 len = (data_len < PAGE_SIZE)? data_len: PAGE_SIZE; 334 sgl->sg_length = len; 335 sgaddr += len; 336 data_len -= len; 337 sgl = sgl + 1; 338 if (data_len == 0) { 339 if (index == ctl_sg_count - 1) 340 break; 341 index++; 342 sgaddr = ctl_sglist[index].addr; 343 data_len = ctl_sglist[index].len; 344 } 345 } 346 347 return nsge; 348 } 349 350 static int 351 t4_sk_ddp_tag_reserve(struct cxgbei_data *ci, struct icl_cxgbei_conn *icc, 352 u_int xferlen, struct cxgbei_sgl *sgl, u_int sgcnt, u_int *ddp_tag) 353 { 354 struct cxgbei_ulp2_gather_list *gl; 355 int err = -EINVAL; 356 struct toepcb *toep = icc->toep; 357 358 gl = cxgbei_ulp2_ddp_make_gl_from_iscsi_sgvec(xferlen, sgl, sgcnt, ci, 0); 359 if (gl) { 360 err = cxgbei_ulp2_ddp_tag_reserve(ci, icc, toep->tid, 361 &ci->tag_format, ddp_tag, gl, 0, 0); 362 if (err) { 363 cxgbei_ulp2_ddp_release_gl(ci, gl); 364 } 365 } 366 367 return err; 368 } 369 370 static unsigned int 371 cxgbei_task_reserve_itt(struct icl_conn *ic, void **prv, 372 struct ccb_scsiio *scmd, unsigned int *itt) 373 { 374 struct icl_cxgbei_conn *icc = ic_to_icc(ic); 375 int xferlen = scmd->dxfer_len; 376 struct cxgbei_task_data *tdata = NULL; 377 struct cxgbei_sgl *sge = NULL; 378 struct toepcb *toep = icc->toep; 379 struct adapter *sc = td_adapter(toep->td); 380 struct cxgbei_data *ci = sc->iscsi_ulp_softc; 381 int err = -1; 382 383 MPASS(icc->icc_signature == CXGBEI_CONN_SIGNATURE); 384 385 tdata = (struct cxgbei_task_data *)*prv; 386 if (xferlen == 0 || tdata == NULL) 387 goto out; 388 if (xferlen < DDP_THRESHOLD) 389 goto out; 390 391 if ((scmd->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 392 tdata->nsge = cxgbei_map_sg(tdata->sgl, scmd); 393 if (tdata->nsge == 0) { 394 CTR1(KTR_CXGBE, "%s: map_sg failed", __func__); 395 return 0; 396 } 397 sge = tdata->sgl; 398 399 tdata->sc_ddp_tag = *itt; 400 401 CTR3(KTR_CXGBE, "%s: *itt:0x%x sc_ddp_tag:0x%x", 402 __func__, *itt, tdata->sc_ddp_tag); 403 if (cxgbei_ulp2_sw_tag_usable(&ci->tag_format, 404 tdata->sc_ddp_tag)) { 405 err = t4_sk_ddp_tag_reserve(ci, icc, scmd->dxfer_len, 406 sge, tdata->nsge, &tdata->sc_ddp_tag); 407 } else { 408 CTR3(KTR_CXGBE, 409 "%s: itt:0x%x sc_ddp_tag:0x%x not usable", 410 __func__, *itt, tdata->sc_ddp_tag); 411 } 412 } 413 out: 414 if (err < 0) 415 tdata->sc_ddp_tag = 416 cxgbei_ulp2_set_non_ddp_tag(&ci->tag_format, *itt); 417 418 return tdata->sc_ddp_tag; 419 } 420 421 static unsigned int 422 cxgbei_task_reserve_ttt(struct icl_conn *ic, void **prv, union ctl_io *io, 423 unsigned int *ttt) 424 { 425 struct icl_cxgbei_conn *icc = ic_to_icc(ic); 426 struct toepcb *toep = icc->toep; 427 struct adapter *sc = td_adapter(toep->td); 428 struct cxgbei_data *ci = sc->iscsi_ulp_softc; 429 struct cxgbei_task_data *tdata = NULL; 430 int xferlen, err = -1; 431 struct cxgbei_sgl *sge = NULL; 432 433 MPASS(icc->icc_signature == CXGBEI_CONN_SIGNATURE); 434 435 xferlen = (io->scsiio.kern_data_len - io->scsiio.ext_data_filled); 436 tdata = (struct cxgbei_task_data *)*prv; 437 if ((xferlen == 0) || (tdata == NULL)) 438 goto out; 439 if (xferlen < DDP_THRESHOLD) 440 goto out; 441 tdata->nsge = cxgbei_map_sg_tgt(tdata->sgl, io); 442 if (tdata->nsge == 0) { 443 CTR1(KTR_CXGBE, "%s: map_sg failed", __func__); 444 return 0; 445 } 446 sge = tdata->sgl; 447 448 tdata->sc_ddp_tag = *ttt; 449 if (cxgbei_ulp2_sw_tag_usable(&ci->tag_format, tdata->sc_ddp_tag)) { 450 err = t4_sk_ddp_tag_reserve(ci, icc, xferlen, sge, 451 tdata->nsge, &tdata->sc_ddp_tag); 452 } else { 453 CTR2(KTR_CXGBE, "%s: sc_ddp_tag:0x%x not usable", 454 __func__, tdata->sc_ddp_tag); 455 } 456 out: 457 if (err < 0) 458 tdata->sc_ddp_tag = 459 cxgbei_ulp2_set_non_ddp_tag(&ci->tag_format, *ttt); 460 return tdata->sc_ddp_tag; 461 } 462 463 static int 464 t4_sk_ddp_tag_release(struct icl_cxgbei_conn *icc, unsigned int ddp_tag) 465 { 466 struct toepcb *toep = icc->toep; 467 struct adapter *sc = td_adapter(toep->td); 468 struct cxgbei_data *ci = sc->iscsi_ulp_softc; 469 470 cxgbei_ulp2_ddp_tag_release(ci, ddp_tag, icc); 471 472 return (0); 473 } 474 475 static void 476 read_pdu_limits(struct adapter *sc, uint32_t *max_tx_pdu_len, 477 uint32_t *max_rx_pdu_len) 478 { 479 uint32_t tx_len, rx_len, r, v; 480 481 rx_len = t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE); 482 tx_len = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE); 483 484 r = t4_read_reg(sc, A_TP_PARA_REG2); 485 rx_len = min(rx_len, G_MAXRXDATA(r)); 486 tx_len = min(tx_len, G_MAXRXDATA(r)); 487 488 r = t4_read_reg(sc, A_TP_PARA_REG7); 489 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 490 rx_len = min(rx_len, v); 491 tx_len = min(tx_len, v); 492 493 /* Remove after FW_FLOWC_MNEM_TXDATAPLEN_MAX fix in firmware. */ 494 tx_len = min(tx_len, 3 * 4096); 495 496 *max_tx_pdu_len = rounddown2(tx_len, 512); 497 *max_rx_pdu_len = rounddown2(rx_len, 512); 498 } 499 500 /* 501 * Initialize the software state of the iSCSI ULP driver. 502 * 503 * ENXIO means firmware didn't set up something that it was supposed to. 504 */ 505 static int 506 cxgbei_init(struct adapter *sc, struct cxgbei_data *ci) 507 { 508 int nppods, bits, rc; 509 static const u_int pgsz_order[] = {0, 1, 2, 3}; 510 511 MPASS(sc->vres.iscsi.size > 0); 512 513 ci->llimit = sc->vres.iscsi.start; 514 ci->ulimit = sc->vres.iscsi.start + sc->vres.iscsi.size - 1; 515 read_pdu_limits(sc, &ci->max_tx_pdu_len, &ci->max_rx_pdu_len); 516 517 nppods = sc->vres.iscsi.size >> IPPOD_SIZE_SHIFT; 518 if (nppods <= 1024) 519 return (ENXIO); 520 521 bits = fls(nppods); 522 if (bits > IPPOD_IDX_MAX_SIZE) 523 bits = IPPOD_IDX_MAX_SIZE; 524 nppods = (1 << (bits - 1)) - 1; 525 526 rc = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR, 527 BUS_SPACE_MAXADDR, NULL, NULL, UINT32_MAX , 8, BUS_SPACE_MAXSIZE, 528 BUS_DMA_ALLOCNOW, NULL, NULL, &ci->ulp_ddp_tag); 529 if (rc != 0) { 530 device_printf(sc->dev, "%s: failed to create DMA tag: %u.\n", 531 __func__, rc); 532 return (rc); 533 } 534 535 ci->colors = malloc(nppods * sizeof(char), M_CXGBE, M_NOWAIT | M_ZERO); 536 ci->gl_map = malloc(nppods * sizeof(struct cxgbei_ulp2_gather_list *), 537 M_CXGBE, M_NOWAIT | M_ZERO); 538 if (ci->colors == NULL || ci->gl_map == NULL) { 539 bus_dma_tag_destroy(ci->ulp_ddp_tag); 540 free(ci->colors, M_CXGBE); 541 free(ci->gl_map, M_CXGBE); 542 return (ENOMEM); 543 } 544 545 mtx_init(&ci->map_lock, "ddp lock", NULL, MTX_DEF | MTX_DUPOK); 546 ci->nppods = nppods; 547 ci->idx_last = nppods; 548 ci->idx_bits = bits; 549 ci->idx_mask = (1 << bits) - 1; 550 ci->rsvd_tag_mask = (1 << (bits + IPPOD_IDX_SHIFT)) - 1; 551 552 ci->tag_format.sw_bits = bits; 553 ci->tag_format.rsvd_bits = bits; 554 ci->tag_format.rsvd_shift = IPPOD_IDX_SHIFT; 555 ci->tag_format.rsvd_mask = ci->idx_mask; 556 557 t4_iscsi_init(sc, ci->idx_mask << IPPOD_IDX_SHIFT, pgsz_order); 558 559 return (rc); 560 } 561 562 static int 563 do_rx_iscsi_hdr(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 564 { 565 struct adapter *sc = iq->adapter; 566 struct cpl_iscsi_hdr *cpl = mtod(m, struct cpl_iscsi_hdr *); 567 u_int tid = GET_TID(cpl); 568 struct toepcb *toep = lookup_tid(sc, tid); 569 struct icl_pdu *ip; 570 struct icl_cxgbei_pdu *icp; 571 572 M_ASSERTPKTHDR(m); 573 574 ip = icl_cxgbei_new_pdu(M_NOWAIT); 575 if (ip == NULL) 576 CXGBE_UNIMPLEMENTED("PDU allocation failure"); 577 icp = ip_to_icp(ip); 578 bcopy(mtod(m, caddr_t) + sizeof(*cpl), icp->ip.ip_bhs, sizeof(struct 579 iscsi_bhs)); 580 icp->icp_seq = ntohl(cpl->seq); 581 icp->icp_flags = ICPF_RX_HDR; 582 583 /* This is the start of a new PDU. There should be no old state. */ 584 MPASS(toep->ulpcb2 == NULL); 585 toep->ulpcb2 = icp; 586 587 #if 0 588 CTR4(KTR_CXGBE, "%s: tid %u, cpl->len hlen %u, m->m_len hlen %u", 589 __func__, tid, ntohs(cpl->len), m->m_len); 590 #endif 591 592 m_freem(m); 593 return (0); 594 } 595 596 static int 597 do_rx_iscsi_data(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 598 { 599 struct adapter *sc = iq->adapter; 600 struct cpl_iscsi_data *cpl = mtod(m, struct cpl_iscsi_data *); 601 u_int tid = GET_TID(cpl); 602 struct toepcb *toep = lookup_tid(sc, tid); 603 struct icl_cxgbei_pdu *icp = toep->ulpcb2; 604 605 M_ASSERTPKTHDR(m); 606 607 /* Must already have received the header (but not the data). */ 608 MPASS(icp != NULL); 609 MPASS(icp->icp_flags == ICPF_RX_HDR); 610 MPASS(icp->ip.ip_data_mbuf == NULL); 611 MPASS(icp->ip.ip_data_len == 0); 612 613 m_adj(m, sizeof(*cpl)); 614 615 icp->icp_flags |= ICPF_RX_FLBUF; 616 icp->ip.ip_data_mbuf = m; 617 icp->ip.ip_data_len = m->m_pkthdr.len; 618 619 #if 0 620 CTR4(KTR_CXGBE, "%s: tid %u, cpl->len dlen %u, m->m_len dlen %u", 621 __func__, tid, ntohs(cpl->len), m->m_len); 622 #endif 623 624 return (0); 625 } 626 627 static int 628 do_rx_iscsi_ddp(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m) 629 { 630 struct adapter *sc = iq->adapter; 631 const struct cpl_rx_data_ddp *cpl = (const void *)(rss + 1); 632 u_int tid = GET_TID(cpl); 633 struct toepcb *toep = lookup_tid(sc, tid); 634 struct inpcb *inp = toep->inp; 635 struct socket *so; 636 struct sockbuf *sb; 637 struct tcpcb *tp; 638 struct icl_cxgbei_conn *icc; 639 struct icl_conn *ic; 640 struct icl_cxgbei_pdu *icp = toep->ulpcb2; 641 struct icl_pdu *ip; 642 u_int pdu_len, val; 643 644 MPASS(m == NULL); 645 646 /* Must already be assembling a PDU. */ 647 MPASS(icp != NULL); 648 MPASS(icp->icp_flags & ICPF_RX_HDR); /* Data is optional. */ 649 ip = &icp->ip; 650 icp->icp_flags |= ICPF_RX_STATUS; 651 val = ntohl(cpl->ddpvld); 652 if (val & F_DDP_PADDING_ERR) 653 icp->icp_flags |= ICPF_PAD_ERR; 654 if (val & F_DDP_HDRCRC_ERR) 655 icp->icp_flags |= ICPF_HCRC_ERR; 656 if (val & F_DDP_DATACRC_ERR) 657 icp->icp_flags |= ICPF_DCRC_ERR; 658 if (ip->ip_data_mbuf == NULL) { 659 /* XXXNP: what should ip->ip_data_len be, and why? */ 660 icp->icp_flags |= ICPF_RX_DDP; 661 } 662 pdu_len = ntohs(cpl->len); /* includes everything. */ 663 664 INP_WLOCK(inp); 665 if (__predict_false(inp->inp_flags & (INP_DROPPED | INP_TIMEWAIT))) { 666 CTR4(KTR_CXGBE, "%s: tid %u, rx (%d bytes), inp_flags 0x%x", 667 __func__, tid, pdu_len, inp->inp_flags); 668 INP_WUNLOCK(inp); 669 icl_cxgbei_conn_pdu_free(NULL, ip); 670 #ifdef INVARIANTS 671 toep->ulpcb2 = NULL; 672 #endif 673 return (0); 674 } 675 676 tp = intotcpcb(inp); 677 MPASS(icp->icp_seq == tp->rcv_nxt); 678 MPASS(tp->rcv_wnd >= pdu_len); 679 tp->rcv_nxt += pdu_len; 680 tp->rcv_wnd -= pdu_len; 681 tp->t_rcvtime = ticks; 682 683 /* update rx credits */ 684 toep->rx_credits += pdu_len; 685 t4_rcvd(&toep->td->tod, tp); /* XXX: sc->tom_softc.tod */ 686 687 so = inp->inp_socket; 688 sb = &so->so_rcv; 689 SOCKBUF_LOCK(sb); 690 691 icc = toep->ulpcb; 692 if (__predict_false(icc == NULL || sb->sb_state & SBS_CANTRCVMORE)) { 693 CTR5(KTR_CXGBE, 694 "%s: tid %u, excess rx (%d bytes), icc %p, sb_state 0x%x", 695 __func__, tid, pdu_len, icc, sb->sb_state); 696 SOCKBUF_UNLOCK(sb); 697 INP_WUNLOCK(inp); 698 699 INP_INFO_RLOCK(&V_tcbinfo); 700 INP_WLOCK(inp); 701 tp = tcp_drop(tp, ECONNRESET); 702 if (tp) 703 INP_WUNLOCK(inp); 704 INP_INFO_RUNLOCK(&V_tcbinfo); 705 706 icl_cxgbei_conn_pdu_free(NULL, ip); 707 #ifdef INVARIANTS 708 toep->ulpcb2 = NULL; 709 #endif 710 return (0); 711 } 712 MPASS(icc->icc_signature == CXGBEI_CONN_SIGNATURE); 713 ic = &icc->ic; 714 icl_cxgbei_new_pdu_set_conn(ip, ic); 715 716 MPASS(m == NULL); /* was unused, we'll use it now. */ 717 m = sbcut_locked(sb, sbused(sb)); /* XXXNP: toep->sb_cc accounting? */ 718 if (__predict_false(m != NULL)) { 719 int len = m_length(m, NULL); 720 721 /* 722 * PDUs were received before the tid transitioned to ULP mode. 723 * Convert them to icl_cxgbei_pdus and send them to ICL before 724 * the PDU in icp/ip. 725 */ 726 CTR3(KTR_CXGBE, "%s: tid %u, %u bytes in so_rcv", __func__, tid, 727 len); 728 729 /* XXXNP: needs to be rewritten. */ 730 if (len == sizeof(struct iscsi_bhs) || len == 4 + sizeof(struct 731 iscsi_bhs)) { 732 struct icl_cxgbei_pdu *icp0; 733 struct icl_pdu *ip0; 734 735 ip0 = icl_cxgbei_new_pdu(M_NOWAIT); 736 icl_cxgbei_new_pdu_set_conn(ip0, ic); 737 if (ip0 == NULL) 738 CXGBE_UNIMPLEMENTED("PDU allocation failure"); 739 icp0 = ip_to_icp(ip0); 740 icp0->icp_seq = 0; /* XXX */ 741 icp0->icp_flags = ICPF_RX_HDR | ICPF_RX_STATUS; 742 m_copydata(m, 0, sizeof(struct iscsi_bhs), (void *)ip0->ip_bhs); 743 STAILQ_INSERT_TAIL(&icc->rcvd_pdus, ip0, ip_next); 744 } 745 m_freem(m); 746 } 747 748 #if 0 749 CTR4(KTR_CXGBE, "%s: tid %u, pdu_len %u, pdu_flags 0x%x", 750 __func__, tid, pdu_len, icp->icp_flags); 751 #endif 752 753 STAILQ_INSERT_TAIL(&icc->rcvd_pdus, ip, ip_next); 754 if ((icc->rx_flags & RXF_ACTIVE) == 0) { 755 struct cxgbei_worker_thread_softc *cwt = &cwt_softc[icc->cwt]; 756 757 mtx_lock(&cwt->cwt_lock); 758 icc->rx_flags |= RXF_ACTIVE; 759 TAILQ_INSERT_TAIL(&cwt->rx_head, icc, rx_link); 760 if (cwt->cwt_state == CWT_SLEEPING) { 761 cwt->cwt_state = CWT_RUNNING; 762 cv_signal(&cwt->cwt_cv); 763 } 764 mtx_unlock(&cwt->cwt_lock); 765 } 766 SOCKBUF_UNLOCK(sb); 767 INP_WUNLOCK(inp); 768 769 #ifdef INVARIANTS 770 toep->ulpcb2 = NULL; 771 #endif 772 773 return (0); 774 } 775 776 /* initiator */ 777 void 778 cxgbei_conn_task_reserve_itt(void *conn, void **prv, 779 void *scmd, unsigned int *itt) 780 { 781 unsigned int tag; 782 tag = cxgbei_task_reserve_itt(conn, prv, scmd, itt); 783 if (tag) 784 *itt = htonl(tag); 785 return; 786 } 787 788 /* target */ 789 void 790 cxgbei_conn_transfer_reserve_ttt(void *conn, void **prv, 791 void *scmd, unsigned int *ttt) 792 { 793 unsigned int tag; 794 tag = cxgbei_task_reserve_ttt(conn, prv, scmd, ttt); 795 if (tag) 796 *ttt = htonl(tag); 797 return; 798 } 799 800 void 801 cxgbei_cleanup_task(void *conn, void *ofld_priv) 802 { 803 struct icl_conn *ic = (struct icl_conn *)conn; 804 struct icl_cxgbei_conn *icc = ic_to_icc(ic); 805 struct cxgbei_task_data *tdata = ofld_priv; 806 struct adapter *sc = icc->sc; 807 struct cxgbei_data *ci = sc->iscsi_ulp_softc; 808 809 MPASS(icc->icc_signature == CXGBEI_CONN_SIGNATURE); 810 MPASS(tdata != NULL); 811 812 if (cxgbei_ulp2_is_ddp_tag(&ci->tag_format, tdata->sc_ddp_tag)) 813 t4_sk_ddp_tag_release(icc, tdata->sc_ddp_tag); 814 memset(tdata, 0, sizeof(*tdata)); 815 } 816 817 static int 818 cxgbei_activate(struct adapter *sc) 819 { 820 struct cxgbei_data *ci; 821 int rc; 822 823 ASSERT_SYNCHRONIZED_OP(sc); 824 825 if (uld_active(sc, ULD_ISCSI)) { 826 KASSERT(0, ("%s: iSCSI offload already enabled on adapter %p", 827 __func__, sc)); 828 return (0); 829 } 830 831 if (sc->iscsicaps == 0 || sc->vres.iscsi.size == 0) { 832 device_printf(sc->dev, 833 "not iSCSI offload capable, or capability disabled.\n"); 834 return (ENOSYS); 835 } 836 837 /* per-adapter softc for iSCSI */ 838 ci = malloc(sizeof(*ci), M_CXGBE, M_ZERO | M_NOWAIT); 839 if (ci == NULL) 840 return (ENOMEM); 841 842 rc = cxgbei_init(sc, ci); 843 if (rc != 0) { 844 free(ci, M_CXGBE); 845 return (rc); 846 } 847 848 sc->iscsi_ulp_softc = ci; 849 850 return (0); 851 } 852 853 static int 854 cxgbei_deactivate(struct adapter *sc) 855 { 856 857 ASSERT_SYNCHRONIZED_OP(sc); 858 859 if (sc->iscsi_ulp_softc != NULL) { 860 cxgbei_ddp_cleanup(sc->iscsi_ulp_softc); 861 free(sc->iscsi_ulp_softc, M_CXGBE); 862 sc->iscsi_ulp_softc = NULL; 863 } 864 865 return (0); 866 } 867 868 static void 869 cxgbei_activate_all(struct adapter *sc, void *arg __unused) 870 { 871 872 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4isact") != 0) 873 return; 874 875 /* Activate iSCSI if any port on this adapter has IFCAP_TOE enabled. */ 876 if (sc->offload_map && !uld_active(sc, ULD_ISCSI)) 877 (void) t4_activate_uld(sc, ULD_ISCSI); 878 879 end_synchronized_op(sc, 0); 880 } 881 882 static void 883 cxgbei_deactivate_all(struct adapter *sc, void *arg __unused) 884 { 885 886 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4isdea") != 0) 887 return; 888 889 if (uld_active(sc, ULD_ISCSI)) 890 (void) t4_deactivate_uld(sc, ULD_ISCSI); 891 892 end_synchronized_op(sc, 0); 893 } 894 895 static struct uld_info cxgbei_uld_info = { 896 .uld_id = ULD_ISCSI, 897 .activate = cxgbei_activate, 898 .deactivate = cxgbei_deactivate, 899 }; 900 901 static void 902 cwt_main(void *arg) 903 { 904 struct cxgbei_worker_thread_softc *cwt = arg; 905 struct icl_cxgbei_conn *icc = NULL; 906 struct icl_conn *ic; 907 struct icl_pdu *ip; 908 struct sockbuf *sb; 909 STAILQ_HEAD(, icl_pdu) rx_pdus = STAILQ_HEAD_INITIALIZER(rx_pdus); 910 911 MPASS(cwt != NULL); 912 913 mtx_lock(&cwt->cwt_lock); 914 MPASS(cwt->cwt_state == 0); 915 cwt->cwt_state = CWT_RUNNING; 916 cv_signal(&cwt->cwt_cv); 917 918 while (__predict_true(cwt->cwt_state != CWT_STOP)) { 919 cwt->cwt_state = CWT_RUNNING; 920 while ((icc = TAILQ_FIRST(&cwt->rx_head)) != NULL) { 921 TAILQ_REMOVE(&cwt->rx_head, icc, rx_link); 922 mtx_unlock(&cwt->cwt_lock); 923 924 ic = &icc->ic; 925 sb = &ic->ic_socket->so_rcv; 926 927 SOCKBUF_LOCK(sb); 928 MPASS(icc->rx_flags & RXF_ACTIVE); 929 if (__predict_true(!(sb->sb_state & SBS_CANTRCVMORE))) { 930 MPASS(STAILQ_EMPTY(&rx_pdus)); 931 STAILQ_SWAP(&icc->rcvd_pdus, &rx_pdus, icl_pdu); 932 SOCKBUF_UNLOCK(sb); 933 934 /* Hand over PDUs to ICL. */ 935 while ((ip = STAILQ_FIRST(&rx_pdus)) != NULL) { 936 STAILQ_REMOVE_HEAD(&rx_pdus, ip_next); 937 ic->ic_receive(ip); 938 } 939 940 SOCKBUF_LOCK(sb); 941 MPASS(STAILQ_EMPTY(&rx_pdus)); 942 } 943 MPASS(icc->rx_flags & RXF_ACTIVE); 944 if (STAILQ_EMPTY(&icc->rcvd_pdus) || 945 __predict_false(sb->sb_state & SBS_CANTRCVMORE)) { 946 icc->rx_flags &= ~RXF_ACTIVE; 947 } else { 948 /* 949 * More PDUs were received while we were busy 950 * handing over the previous batch to ICL. 951 * Re-add this connection to the end of the 952 * queue. 953 */ 954 mtx_lock(&cwt->cwt_lock); 955 TAILQ_INSERT_TAIL(&cwt->rx_head, icc, 956 rx_link); 957 mtx_unlock(&cwt->cwt_lock); 958 } 959 SOCKBUF_UNLOCK(sb); 960 961 mtx_lock(&cwt->cwt_lock); 962 } 963 964 /* Inner loop doesn't check for CWT_STOP, do that first. */ 965 if (__predict_false(cwt->cwt_state == CWT_STOP)) 966 break; 967 cwt->cwt_state = CWT_SLEEPING; 968 cv_wait(&cwt->cwt_cv, &cwt->cwt_lock); 969 } 970 971 MPASS(TAILQ_FIRST(&cwt->rx_head) == NULL); 972 mtx_assert(&cwt->cwt_lock, MA_OWNED); 973 cwt->cwt_state = CWT_STOPPED; 974 cv_signal(&cwt->cwt_cv); 975 mtx_unlock(&cwt->cwt_lock); 976 kthread_exit(); 977 } 978 979 static int 980 start_worker_threads(void) 981 { 982 int i, rc; 983 struct cxgbei_worker_thread_softc *cwt; 984 985 worker_thread_count = min(mp_ncpus, 32); 986 cwt_softc = malloc(worker_thread_count * sizeof(*cwt), M_CXGBE, 987 M_WAITOK | M_ZERO); 988 989 MPASS(cxgbei_proc == NULL); 990 for (i = 0, cwt = &cwt_softc[0]; i < worker_thread_count; i++, cwt++) { 991 mtx_init(&cwt->cwt_lock, "cwt lock", NULL, MTX_DEF); 992 cv_init(&cwt->cwt_cv, "cwt cv"); 993 TAILQ_INIT(&cwt->rx_head); 994 rc = kproc_kthread_add(cwt_main, cwt, &cxgbei_proc, NULL, 0, 0, 995 "cxgbei", "%d", i); 996 if (rc != 0) { 997 printf("cxgbei: failed to start thread #%d/%d (%d)\n", 998 i + 1, worker_thread_count, rc); 999 mtx_destroy(&cwt->cwt_lock); 1000 cv_destroy(&cwt->cwt_cv); 1001 bzero(&cwt, sizeof(*cwt)); 1002 if (i == 0) { 1003 free(cwt_softc, M_CXGBE); 1004 worker_thread_count = 0; 1005 1006 return (rc); 1007 } 1008 1009 /* Not fatal, carry on with fewer threads. */ 1010 worker_thread_count = i; 1011 rc = 0; 1012 break; 1013 } 1014 1015 /* Wait for thread to start before moving on to the next one. */ 1016 mtx_lock(&cwt->cwt_lock); 1017 while (cwt->cwt_state == 0) 1018 cv_wait(&cwt->cwt_cv, &cwt->cwt_lock); 1019 mtx_unlock(&cwt->cwt_lock); 1020 } 1021 1022 MPASS(cwt_softc != NULL); 1023 MPASS(worker_thread_count > 0); 1024 return (0); 1025 } 1026 1027 static void 1028 stop_worker_threads(void) 1029 { 1030 int i; 1031 struct cxgbei_worker_thread_softc *cwt = &cwt_softc[0]; 1032 1033 MPASS(worker_thread_count >= 0); 1034 1035 for (i = 0, cwt = &cwt_softc[0]; i < worker_thread_count; i++, cwt++) { 1036 mtx_lock(&cwt->cwt_lock); 1037 MPASS(cwt->cwt_state == CWT_RUNNING || 1038 cwt->cwt_state == CWT_SLEEPING); 1039 cwt->cwt_state = CWT_STOP; 1040 cv_signal(&cwt->cwt_cv); 1041 do { 1042 cv_wait(&cwt->cwt_cv, &cwt->cwt_lock); 1043 } while (cwt->cwt_state != CWT_STOPPED); 1044 mtx_unlock(&cwt->cwt_lock); 1045 } 1046 free(cwt_softc, M_CXGBE); 1047 } 1048 1049 /* Select a worker thread for a connection. */ 1050 u_int 1051 cxgbei_select_worker_thread(struct icl_cxgbei_conn *icc) 1052 { 1053 struct adapter *sc = icc->sc; 1054 struct toepcb *toep = icc->toep; 1055 u_int i, n; 1056 1057 n = worker_thread_count / sc->sge.nofldrxq; 1058 if (n > 0) 1059 i = toep->vi->pi->port_id * n + arc4random() % n; 1060 else 1061 i = arc4random() % worker_thread_count; 1062 1063 CTR3(KTR_CXGBE, "%s: tid %u, cwt %u", __func__, toep->tid, i); 1064 1065 return (i); 1066 } 1067 1068 static int 1069 cxgbei_mod_load(void) 1070 { 1071 int rc; 1072 1073 t4_register_cpl_handler(CPL_ISCSI_HDR, do_rx_iscsi_hdr); 1074 t4_register_cpl_handler(CPL_ISCSI_DATA, do_rx_iscsi_data); 1075 t4_register_cpl_handler(CPL_RX_ISCSI_DDP, do_rx_iscsi_ddp); 1076 1077 rc = start_worker_threads(); 1078 if (rc != 0) 1079 return (rc); 1080 1081 rc = t4_register_uld(&cxgbei_uld_info); 1082 if (rc != 0) { 1083 stop_worker_threads(); 1084 return (rc); 1085 } 1086 1087 t4_iterate(cxgbei_activate_all, NULL); 1088 1089 return (rc); 1090 } 1091 1092 static int 1093 cxgbei_mod_unload(void) 1094 { 1095 1096 t4_iterate(cxgbei_deactivate_all, NULL); 1097 1098 if (t4_unregister_uld(&cxgbei_uld_info) == EBUSY) 1099 return (EBUSY); 1100 1101 stop_worker_threads(); 1102 1103 t4_register_cpl_handler(CPL_ISCSI_HDR, NULL); 1104 t4_register_cpl_handler(CPL_ISCSI_DATA, NULL); 1105 t4_register_cpl_handler(CPL_RX_ISCSI_DDP, NULL); 1106 1107 return (0); 1108 } 1109 #endif 1110 1111 static int 1112 cxgbei_modevent(module_t mod, int cmd, void *arg) 1113 { 1114 int rc = 0; 1115 1116 #ifdef TCP_OFFLOAD 1117 switch (cmd) { 1118 case MOD_LOAD: 1119 rc = cxgbei_mod_load(); 1120 if (rc == 0) 1121 rc = icl_cxgbei_mod_load(); 1122 break; 1123 1124 case MOD_UNLOAD: 1125 rc = icl_cxgbei_mod_unload(); 1126 if (rc == 0) 1127 rc = cxgbei_mod_unload(); 1128 break; 1129 1130 default: 1131 rc = EINVAL; 1132 } 1133 #else 1134 printf("cxgbei: compiled without TCP_OFFLOAD support.\n"); 1135 rc = EOPNOTSUPP; 1136 #endif 1137 1138 return (rc); 1139 } 1140 1141 static moduledata_t cxgbei_mod = { 1142 "cxgbei", 1143 cxgbei_modevent, 1144 NULL, 1145 }; 1146 1147 MODULE_VERSION(cxgbei, 1); 1148 DECLARE_MODULE(cxgbei, cxgbei_mod, SI_SUB_EXEC, SI_ORDER_ANY); 1149 MODULE_DEPEND(cxgbei, t4_tom, 1, 1, 1); 1150 MODULE_DEPEND(cxgbei, cxgbe, 1, 1, 1); 1151 MODULE_DEPEND(cxgbei, icl, 1, 1, 1); 1152