1 /*- 2 * Copyright (c) 2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #ifndef __CUDBG_ENTITY_H__ 29 #define __CUDBG_ENTITY_H__ 30 31 #ifdef __GNUC__ 32 #define ATTRIBUTE_UNUSED __attribute__ ((unused)) 33 #else 34 #define ATTRIBUTE_UNUSED 35 #endif 36 37 #define MC0_FLAG 1 38 #define MC1_FLAG 2 39 #define EDC0_FLAG 3 40 #define EDC1_FLAG 4 41 42 #define NUM_PCIE_CONFIG_REGS 0x61 43 #define CUDBG_CTXT_SIZE_BYTES 24 44 #define CUDBG_MAX_INGRESS_QIDS 65536 45 #define CUDBG_MAX_FL_QIDS 2048 46 #define CUDBG_MAX_CNM_QIDS 1024 47 #define CUDBG_LOWMEM_MAX_CTXT_QIDS 256 48 #define ETH_ALEN 6 49 #define CUDBG_MAX_RPLC_SIZE 128 50 #define CUDBG_NUM_REQ_REGS 17 51 #define CUDBG_MAX_TCAM_TID 0x800 52 #define CUDBG_NUM_ULPTX 11 53 #define CUDBG_NUM_ULPTX_READ 512 54 55 #define SN_REG_ADDR 0x183f 56 #define BN_REG_ADDR 0x1819 57 #define NA_REG_ADDR 0x185a 58 #define MN_REG_ADDR 0x1803 59 60 #define A_MPS_VF_RPLCT_MAP0 0x1111c 61 #define A_MPS_VF_RPLCT_MAP1 0x11120 62 #define A_MPS_VF_RPLCT_MAP2 0x11124 63 #define A_MPS_VF_RPLCT_MAP3 0x11128 64 #define A_MPS_VF_RPLCT_MAP4 0x11300 65 #define A_MPS_VF_RPLCT_MAP5 0x11304 66 #define A_MPS_VF_RPLCT_MAP6 0x11308 67 #define A_MPS_VF_RPLCT_MAP7 0x1130c 68 69 #define PORT_TYPE_ADDR 0x1869 70 #define PORT_TYPE_LEN 8 71 72 /* For T6 */ 73 #define SN_T6_ADDR 0x83f 74 #define BN_T6_ADDR 0x819 75 #define NA_T6_ADDR 0x85a 76 #define MN_T6_ADDR 0x803 77 78 #define SN_MAX_LEN 24 79 #define BN_MAX_LEN 16 80 #define NA_MAX_LEN 12 81 #define MN_MAX_LEN 16 82 #define MAX_VPD_DATA_LEN 32 83 84 #define VPD_VER_ADDR 0x18c7 85 #define VPD_VER_LEN 2 86 #define SCFG_VER_ADDR 0x06 87 #define SCFG_VER_LEN 4 88 89 #define CUDBG_CIM_BUSY_BIT (1 << 17) 90 91 #define CUDBG_CHAC_PBT_ADDR 0x2800 92 #define CUDBG_CHAC_PBT_LRF 0x3000 93 #define CUDBG_CHAC_PBT_DATA 0x3800 94 #define CUDBG_PBT_DYNAMIC_ENTRIES 8 95 #define CUDBG_PBT_STATIC_ENTRIES 16 96 #define CUDBG_LRF_ENTRIES 8 97 #define CUDBG_PBT_DATA_ENTRIES 512 98 99 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001 100 #define CUDBG_TID_INFO_REV 1 101 #define CUDBG_MAC_STATS_REV 1 102 103 #ifndef ARRAY_SIZE 104 #define ARRAY_SIZE(_a) (sizeof((_a)) / sizeof((_a)[0])) 105 #endif 106 107 struct cudbg_pbt_tables { 108 u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES]; 109 u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES]; 110 u32 lrf_table[CUDBG_LRF_ENTRIES]; 111 u32 pbt_data[CUDBG_PBT_DATA_ENTRIES]; 112 }; 113 114 struct card_mem { 115 u16 size_mc0; 116 u16 size_mc1; 117 u16 size_edc0; 118 u16 size_edc1; 119 u16 mem_flag; 120 u16 res; 121 }; 122 123 struct rss_pf_conf { 124 u32 rss_pf_map; 125 u32 rss_pf_mask; 126 u32 rss_pf_config; 127 }; 128 129 struct cudbg_ch_cntxt { 130 uint32_t cntxt_type; 131 uint32_t cntxt_id; 132 uint32_t data[SGE_CTXT_SIZE / 4]; 133 }; 134 135 struct cudbg_tcam { 136 u32 filter_start; 137 u32 server_start; 138 u32 clip_start; 139 u32 routing_start; 140 u32 tid_hash_base; 141 u32 max_tid; 142 }; 143 144 #if 0 145 struct cudbg_mbox_log { 146 struct mbox_cmd entry; 147 u32 hi[MBOX_LEN / 8]; 148 u32 lo[MBOX_LEN / 8]; 149 }; 150 #endif 151 152 struct cudbg_tid_data { 153 u32 tid; 154 u32 dbig_cmd; 155 u32 dbig_conf; 156 u32 dbig_rsp_stat; 157 u32 data[CUDBG_NUM_REQ_REGS]; 158 }; 159 160 struct cudbg_cntxt_field { 161 char *name; 162 u32 start_bit; 163 u32 end_bit; 164 u32 shift; 165 u32 islog2; 166 }; 167 168 struct cudbg_mps_tcam { 169 u64 mask; 170 u32 rplc[8]; 171 u32 idx; 172 u32 cls_lo; 173 u32 cls_hi; 174 u32 rplc_size; 175 u32 vniy; 176 u32 vnix; 177 u32 dip_hit; 178 u32 vlan_vld; 179 u32 repli; 180 u16 ivlan; 181 u8 addr[ETH_ALEN]; 182 u8 lookup_type; 183 u8 port_num; 184 u8 reserved[2]; 185 }; 186 187 struct rss_vf_conf { 188 u32 rss_vf_vfl; 189 u32 rss_vf_vfh; 190 }; 191 192 struct rss_config { 193 u32 tp_rssconf; /* A_TP_RSS_CONFIG */ 194 u32 tp_rssconf_tnl; /* A_TP_RSS_CONFIG_TNL */ 195 u32 tp_rssconf_ofd; /* A_TP_RSS_CONFIG_OFD */ 196 u32 tp_rssconf_syn; /* A_TP_RSS_CONFIG_SYN */ 197 u32 tp_rssconf_vrt; /* A_TP_RSS_CONFIG_VRT */ 198 u32 tp_rssconf_cng; /* A_TP_RSS_CONFIG_CNG */ 199 u32 chip; 200 }; 201 202 struct struct_pm_stats { 203 u32 tx_cnt[T6_PM_NSTATS]; 204 u32 rx_cnt[T6_PM_NSTATS]; 205 u64 tx_cyc[T6_PM_NSTATS]; 206 u64 rx_cyc[T6_PM_NSTATS]; 207 }; 208 209 struct struct_hw_sched { 210 u32 kbps[NTX_SCHED]; 211 u32 ipg[NTX_SCHED]; 212 u32 pace_tab[NTX_SCHED]; 213 u32 mode; 214 u32 map; 215 }; 216 217 struct struct_tcp_stats { 218 struct tp_tcp_stats v4, v6; 219 }; 220 221 struct struct_tp_err_stats { 222 struct tp_err_stats stats; 223 u32 nchan; 224 }; 225 226 struct struct_tp_fcoe_stats { 227 struct tp_fcoe_stats stats[4]; 228 u32 nchan; 229 }; 230 231 struct struct_mac_stats { 232 u32 port_count; 233 struct port_stats stats[4]; 234 }; 235 236 struct struct_mac_stats_rev1 { 237 struct cudbg_ver_hdr ver_hdr; 238 u32 port_count; 239 u32 reserved; 240 struct port_stats stats[4]; 241 }; 242 243 struct struct_tp_cpl_stats { 244 struct tp_cpl_stats stats; 245 u32 nchan; 246 }; 247 248 struct struct_wc_stats { 249 u32 wr_cl_success; 250 u32 wr_cl_fail; 251 }; 252 253 struct struct_ulptx_la { 254 u32 rdptr[CUDBG_NUM_ULPTX]; 255 u32 wrptr[CUDBG_NUM_ULPTX]; 256 u32 rddata[CUDBG_NUM_ULPTX]; 257 u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ]; 258 }; 259 260 struct struct_ulprx_la { 261 u32 data[ULPRX_LA_SIZE * 8]; 262 u32 size; 263 }; 264 265 struct struct_cim_qcfg { 266 u8 chip; 267 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 268 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5]; 269 u16 thres[CIM_NUM_IBQ]; 270 u32 obq_wr[2 * CIM_NUM_OBQ_T5]; 271 u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)]; 272 }; 273 274 enum region_index { 275 REGN_DBQ_CONTEXS_IDX, 276 REGN_IMSG_CONTEXTS_IDX, 277 REGN_FLM_CACHE_IDX, 278 REGN_TCBS_IDX, 279 REGN_PSTRUCT_IDX, 280 REGN_TIMERS_IDX, 281 REGN_RX_FL_IDX, 282 REGN_TX_FL_IDX, 283 REGN_PSTRUCT_FL_IDX, 284 REGN_TX_PAYLOAD_IDX, 285 REGN_RX_PAYLOAD_IDX, 286 REGN_LE_HASH_IDX, 287 REGN_ISCSI_IDX, 288 REGN_TDDP_IDX, 289 REGN_TPT_IDX, 290 REGN_STAG_IDX, 291 REGN_RQ_IDX, 292 REGN_RQUDP_IDX, 293 REGN_PBL_IDX, 294 REGN_TXPBL_IDX, 295 REGN_DBVFIFO_IDX, 296 REGN_ULPRX_STATE_IDX, 297 REGN_ULPTX_STATE_IDX, 298 #ifndef __NO_DRIVER_OCQ_SUPPORT__ 299 REGN_ON_CHIP_Q_IDX, 300 #endif 301 }; 302 303 static const char * const region[] = { 304 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:", 305 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:", 306 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:", 307 "TDDP region:", "TPT region:", "STAG region:", "RQ region:", 308 "RQUDP region:", "PBL region:", "TXPBL region:", 309 "DBVFIFO region:", "ULPRX state:", "ULPTX state:", 310 #ifndef __NO_DRIVER_OCQ_SUPPORT__ 311 "On-chip queues:" 312 #endif 313 }; 314 315 /* Info relative to memory region (i.e. wrt 0). */ 316 struct struct_region_info { 317 bool exist; /* Does region exists in current memory region? */ 318 u32 start; /* Start wrt 0 */ 319 u32 end; /* End wrt 0 */ 320 }; 321 322 struct struct_port_usage { 323 u32 id; 324 u32 used; 325 u32 alloc; 326 }; 327 328 struct struct_lpbk_usage { 329 u32 id; 330 u32 used; 331 u32 alloc; 332 }; 333 334 struct struct_mem_desc { 335 u32 base; 336 u32 limit; 337 u32 idx; 338 }; 339 340 enum string_size_units { 341 STRING_UNITS_10, /* use powers of 10^3 (standard SI) */ 342 STRING_UNITS_2, /* use binary powers of 2^10 */ 343 }; 344 345 struct struct_meminfo { 346 struct struct_mem_desc avail[4]; 347 struct struct_mem_desc mem[ARRAY_SIZE(region) + 3]; 348 u32 avail_c; 349 u32 mem_c; 350 u32 up_ram_lo; 351 u32 up_ram_hi; 352 u32 up_extmem2_lo; 353 u32 up_extmem2_hi; 354 u32 rx_pages_data[3]; 355 u32 tx_pages_data[4]; 356 u32 p_structs; 357 struct struct_port_usage port_data[4]; 358 u32 port_used[4]; 359 u32 port_alloc[4]; 360 u32 loopback_used[NCHAN]; 361 u32 loopback_alloc[NCHAN]; 362 }; 363 364 #ifndef __GNUC__ 365 #pragma warning(disable : 4200) 366 #endif 367 368 struct struct_lb_stats { 369 int nchan; 370 struct lb_port_stats s[0]; 371 }; 372 373 struct struct_clk_info { 374 u64 retransmit_min; 375 u64 retransmit_max; 376 u64 persist_timer_min; 377 u64 persist_timer_max; 378 u64 keepalive_idle_timer; 379 u64 keepalive_interval; 380 u64 initial_srtt; 381 u64 finwait2_timer; 382 u32 dack_timer; 383 u32 res; 384 u32 cclk_ps; 385 u32 tre; 386 u32 dack_re; 387 char core_clk_period[32]; 388 char tp_timer_tick[32]; 389 char tcp_tstamp_tick[32]; 390 char dack_tick[32]; 391 }; 392 393 struct cim_pif_la { 394 int size; 395 u8 data[0]; 396 }; 397 398 struct struct_tp_la { 399 u32 size; 400 u32 mode; 401 u8 data[0]; 402 }; 403 404 struct field_desc { 405 const char *name; 406 u32 start; 407 u32 width; 408 }; 409 410 struct tp_mib_type { 411 char *key; 412 u32 addr; 413 u32 value; 414 }; 415 416 struct wtp_type_0 { 417 u32 sop; 418 u32 eop; 419 }; 420 421 struct wtp_type_1 { 422 u32 sop[2]; 423 u32 eop[2]; 424 }; 425 426 struct wtp_type_2 { 427 u32 sop[4]; 428 u32 eop[4]; 429 }; 430 431 struct wtp_type_3 { 432 u32 sop[4]; 433 u32 eop[4]; 434 u32 drops; 435 }; 436 437 struct wtp_data { 438 /*TX path, Request Work request sub-path:*/ 439 440 struct wtp_type_1 sge_pcie_cmd_req; /*SGE_DEBUG PC_Req_xOPn*/ 441 struct wtp_type_1 pcie_core_cmd_req; /*PCIE_CMDR_REQ_CNT*/ 442 443 444 /*TX path, Work request to uP sub-path*/ 445 struct wtp_type_1 core_pcie_cmd_rsp; /*PCIE_CMDR_RSP_CNT*/ 446 struct wtp_type_1 pcie_sge_cmd_rsp; /*SGE_DEBUG PC_Rsp_xOPn*/ 447 struct wtp_type_1 sge_cim; /*SGE_DEBUG CIM_xOPn*/ 448 449 /*TX path, Data request path from ULP_TX to core*/ 450 struct wtp_type_2 utx_sge_dma_req; /*SGE UD_Rx_xOPn*/ 451 struct wtp_type_2 sge_pcie_dma_req; /*SGE PD_Req_Rdn (no eops)*/ 452 struct wtp_type_2 pcie_core_dma_req; /*PCIE_DMAR_REQ_CNT (no eops)*/ 453 454 /*Main TX path, from core to wire*/ 455 struct wtp_type_2 core_pcie_dma_rsp; /*PCIE_DMAR_RSP_SOP_CNT/ 456 PCIE_DMAR_EOP_CNT*/ 457 struct wtp_type_2 pcie_sge_dma_rsp; /*SGE_DEBUG PD_Rsp_xOPn*/ 458 struct wtp_type_2 sge_utx; /*SGE_DEBUG U_Tx_xOPn*/ 459 struct wtp_type_2 utx_tp; /*ULP_TX_SE_CNT_CHn[xOP_CNT_ULP2TP]*/ 460 struct wtp_type_2 utx_tpcside; /*TP_DBG_CSIDE_RXn[RxXoPCnt]*/ 461 462 struct wtp_type_2 tpcside_rxpld; 463 struct wtp_type_2 tpcside_rxarb; /*TP_DBG_CSIDE_RXn[RxArbXopCnt]*/ 464 struct wtp_type_2 tpcside_rxcpl; 465 466 struct wtp_type_2 tpeside_mps; /*TP_DBG_ESDIE_PKT0[TxXoPCnt]*/ 467 struct wtp_type_2 tpeside_pm; 468 struct wtp_type_2 tpeside_pld; 469 470 /*Tx path, PCIE t5 DMA stat*/ 471 struct wtp_type_2 pcie_t5_dma_stat3; 472 473 /*Tx path, SGE debug data high index 6*/ 474 struct wtp_type_2 sge_debug_data_high_index_6; 475 476 /*Tx path, SGE debug data high index 3*/ 477 struct wtp_type_2 sge_debug_data_high_index_3; 478 479 /*Tx path, ULP SE CNT CHx*/ 480 struct wtp_type_2 ulp_se_cnt_chx; 481 482 /*pcie cmd stat 2*/ 483 struct wtp_type_2 pcie_cmd_stat2; 484 485 /*pcie cmd stat 3*/ 486 struct wtp_type_2 pcie_cmd_stat3; 487 488 struct wtp_type_2 pcie_dma1_stat2_core; 489 490 struct wtp_type_1 sge_work_req_pkt; 491 492 struct wtp_type_2 sge_debug_data_high_indx5; 493 494 /*Tx path, mac portx pkt count*/ 495 struct wtp_type_2 mac_portx_pkt_count; 496 497 /*Rx path, mac porrx pkt count*/ 498 struct wtp_type_2 mac_porrx_pkt_count; 499 500 /*Rx path, PCIE T5 dma1 stat 2*/ 501 struct wtp_type_2 pcie_dma1_stat2; 502 503 /*Rx path, sge debug data high index 7*/ 504 struct wtp_type_2 sge_debug_data_high_indx7; 505 506 /*Rx path, sge debug data high index 1*/ 507 struct wtp_type_1 sge_debug_data_high_indx1; 508 509 /*Rx path, TP debug CSIDE Tx register*/ 510 struct wtp_type_1 utx_tpcside_tx; 511 512 /*Rx path, LE DB response count*/ 513 struct wtp_type_0 le_db_rsp_cnt; 514 515 /*Rx path, TP debug Eside PKTx*/ 516 struct wtp_type_2 tp_dbg_eside_pktx; 517 518 /*Rx path, sge debug data high index 9*/ 519 struct wtp_type_1 sge_debug_data_high_indx9; 520 521 /*Tx path, mac portx aFramesTransmittesok*/ 522 struct wtp_type_2 mac_portx_aframestra_ok; 523 524 /*Rx path, mac portx aFramesTransmittesok*/ 525 struct wtp_type_2 mac_porrx_aframestra_ok; 526 527 /*Tx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/ 528 struct wtp_type_1 mac_portx_etherstatspkts; 529 530 /*Rx path, MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/ 531 struct wtp_type_1 mac_porrx_etherstatspkts; 532 533 struct wtp_type_3 tp_mps; /*MPS_TX_SE_CNT_TP01 and 534 MPS_TX_SE_CNT_TP34*/ 535 struct wtp_type_3 mps_xgm; /*MPS_TX_SE_CNT_MAC01 and 536 MPS_TX_SE_CNT_MAC34*/ 537 struct wtp_type_2 tx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/ 538 struct wtp_type_2 xgm_wire; /*XGMAC_PORT_XGM_STAT_TX_FRAME_LOW_PORT_N 539 (clear on read)*/ 540 541 /*RX path, from wire to core.*/ 542 struct wtp_type_2 wire_xgm; /*XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW_PORT_N 543 (clear on read)*/ 544 struct wtp_type_2 rx_xgm_xgm; /*XGMAC_PORT_PKT_CNT_PORT_n*/ 545 struct _xgm_mps { /*MPS_RX_SE_CNT_INn*/ 546 u32 sop[8]; /* => undef,*/ 547 u32 eop[8]; /* => undef,*/ 548 u32 drop; /* => undef,*/ 549 u32 cls_drop; /* => undef,*/ 550 u32 err; /* => undef,*/ 551 u32 bp; /* => undef,*/ 552 } xgm_mps; 553 554 struct wtp_type_3 mps_tp; /*MPS_RX_SE_CNT_OUT01 and 555 MPS_RX_SE_CNT_OUT23*/ 556 struct wtp_type_2 mps_tpeside; /*TP_DBG_ESIDE_PKTn*/ 557 struct wtp_type_1 tpeside_pmrx; /*???*/ 558 struct wtp_type_2 pmrx_ulprx; /*ULP_RX_SE_CNT_CHn[xOP_CNT_INn]*/ 559 struct wtp_type_2 ulprx_tpcside; /*ULP_RX_SE_CNT_CHn[xOP_CNT_OUTn]*/ 560 struct wtp_type_2 tpcside_csw; /*TP_DBG_CSIDE_TXn[TxSopCnt]*/ 561 struct wtp_type_2 tpcside_pm; 562 struct wtp_type_2 tpcside_uturn; 563 struct wtp_type_2 tpcside_txcpl; 564 struct wtp_type_1 tp_csw; /*SGE_DEBUG CPLSW_TP_Rx_xOPn*/ 565 struct wtp_type_1 csw_sge; /*SGE_DEBUG T_Rx_xOPn*/ 566 struct wtp_type_2 sge_pcie; /*SGE_DEBUG PD_Req_SopN - 567 PD_Req_RdN - PD_ReqIntN*/ 568 struct wtp_type_2 sge_pcie_ints; /*SGE_DEBUG PD_Req_IntN*/ 569 struct wtp_type_2 pcie_core_dmaw; /*PCIE_DMAW_SOP_CNT and 570 PCIE_DMAW_EOP_CNT*/ 571 struct wtp_type_2 pcie_core_dmai; /*PCIE_DMAI_CNT*/ 572 573 }; 574 575 struct tp_mib_data { 576 struct tp_mib_type TP_MIB_MAC_IN_ERR_0; 577 struct tp_mib_type TP_MIB_MAC_IN_ERR_1; 578 struct tp_mib_type TP_MIB_MAC_IN_ERR_2; 579 struct tp_mib_type TP_MIB_MAC_IN_ERR_3; 580 struct tp_mib_type TP_MIB_HDR_IN_ERR_0; 581 struct tp_mib_type TP_MIB_HDR_IN_ERR_1; 582 struct tp_mib_type TP_MIB_HDR_IN_ERR_2; 583 struct tp_mib_type TP_MIB_HDR_IN_ERR_3; 584 struct tp_mib_type TP_MIB_TCP_IN_ERR_0; 585 struct tp_mib_type TP_MIB_TCP_IN_ERR_1; 586 struct tp_mib_type TP_MIB_TCP_IN_ERR_2; 587 struct tp_mib_type TP_MIB_TCP_IN_ERR_3; 588 struct tp_mib_type TP_MIB_TCP_OUT_RST; 589 struct tp_mib_type TP_MIB_TCP_IN_SEG_HI; 590 struct tp_mib_type TP_MIB_TCP_IN_SEG_LO; 591 struct tp_mib_type TP_MIB_TCP_OUT_SEG_HI; 592 struct tp_mib_type TP_MIB_TCP_OUT_SEG_LO; 593 struct tp_mib_type TP_MIB_TCP_RXT_SEG_HI; 594 struct tp_mib_type TP_MIB_TCP_RXT_SEG_LO; 595 struct tp_mib_type TP_MIB_TNL_CNG_DROP_0; 596 struct tp_mib_type TP_MIB_TNL_CNG_DROP_1; 597 struct tp_mib_type TP_MIB_TNL_CNG_DROP_2; 598 struct tp_mib_type TP_MIB_TNL_CNG_DROP_3; 599 struct tp_mib_type TP_MIB_OFD_CHN_DROP_0; 600 struct tp_mib_type TP_MIB_OFD_CHN_DROP_1; 601 struct tp_mib_type TP_MIB_OFD_CHN_DROP_2; 602 struct tp_mib_type TP_MIB_OFD_CHN_DROP_3; 603 struct tp_mib_type TP_MIB_TNL_OUT_PKT_0; 604 struct tp_mib_type TP_MIB_TNL_OUT_PKT_1; 605 struct tp_mib_type TP_MIB_TNL_OUT_PKT_2; 606 struct tp_mib_type TP_MIB_TNL_OUT_PKT_3; 607 struct tp_mib_type TP_MIB_TNL_IN_PKT_0; 608 struct tp_mib_type TP_MIB_TNL_IN_PKT_1; 609 struct tp_mib_type TP_MIB_TNL_IN_PKT_2; 610 struct tp_mib_type TP_MIB_TNL_IN_PKT_3; 611 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_0; 612 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_1; 613 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_2; 614 struct tp_mib_type TP_MIB_TCP_V6IN_ERR_3; 615 struct tp_mib_type TP_MIB_TCP_V6OUT_RST; 616 struct tp_mib_type TP_MIB_TCP_V6IN_SEG_HI; 617 struct tp_mib_type TP_MIB_TCP_V6IN_SEG_LO; 618 struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_HI; 619 struct tp_mib_type TP_MIB_TCP_V6OUT_SEG_LO; 620 struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_HI; 621 struct tp_mib_type TP_MIB_TCP_V6RXT_SEG_LO; 622 struct tp_mib_type TP_MIB_OFD_ARP_DROP; 623 struct tp_mib_type TP_MIB_OFD_DFR_DROP; 624 struct tp_mib_type TP_MIB_CPL_IN_REQ_0; 625 struct tp_mib_type TP_MIB_CPL_IN_REQ_1; 626 struct tp_mib_type TP_MIB_CPL_IN_REQ_2; 627 struct tp_mib_type TP_MIB_CPL_IN_REQ_3; 628 struct tp_mib_type TP_MIB_CPL_OUT_RSP_0; 629 struct tp_mib_type TP_MIB_CPL_OUT_RSP_1; 630 struct tp_mib_type TP_MIB_CPL_OUT_RSP_2; 631 struct tp_mib_type TP_MIB_CPL_OUT_RSP_3; 632 struct tp_mib_type TP_MIB_TNL_LPBK_0; 633 struct tp_mib_type TP_MIB_TNL_LPBK_1; 634 struct tp_mib_type TP_MIB_TNL_LPBK_2; 635 struct tp_mib_type TP_MIB_TNL_LPBK_3; 636 struct tp_mib_type TP_MIB_TNL_DROP_0; 637 struct tp_mib_type TP_MIB_TNL_DROP_1; 638 struct tp_mib_type TP_MIB_TNL_DROP_2; 639 struct tp_mib_type TP_MIB_TNL_DROP_3; 640 struct tp_mib_type TP_MIB_FCOE_DDP_0; 641 struct tp_mib_type TP_MIB_FCOE_DDP_1; 642 struct tp_mib_type TP_MIB_FCOE_DDP_2; 643 struct tp_mib_type TP_MIB_FCOE_DDP_3; 644 struct tp_mib_type TP_MIB_FCOE_DROP_0; 645 struct tp_mib_type TP_MIB_FCOE_DROP_1; 646 struct tp_mib_type TP_MIB_FCOE_DROP_2; 647 struct tp_mib_type TP_MIB_FCOE_DROP_3; 648 struct tp_mib_type TP_MIB_FCOE_BYTE_0_HI; 649 struct tp_mib_type TP_MIB_FCOE_BYTE_0_LO; 650 struct tp_mib_type TP_MIB_FCOE_BYTE_1_HI; 651 struct tp_mib_type TP_MIB_FCOE_BYTE_1_LO; 652 struct tp_mib_type TP_MIB_FCOE_BYTE_2_HI; 653 struct tp_mib_type TP_MIB_FCOE_BYTE_2_LO; 654 struct tp_mib_type TP_MIB_FCOE_BYTE_3_HI; 655 struct tp_mib_type TP_MIB_FCOE_BYTE_3_LO; 656 struct tp_mib_type TP_MIB_OFD_VLN_DROP_0; 657 struct tp_mib_type TP_MIB_OFD_VLN_DROP_1; 658 struct tp_mib_type TP_MIB_OFD_VLN_DROP_2; 659 struct tp_mib_type TP_MIB_OFD_VLN_DROP_3; 660 struct tp_mib_type TP_MIB_USM_PKTS; 661 struct tp_mib_type TP_MIB_USM_DROP; 662 struct tp_mib_type TP_MIB_USM_BYTES_HI; 663 struct tp_mib_type TP_MIB_USM_BYTES_LO; 664 struct tp_mib_type TP_MIB_TID_DEL; 665 struct tp_mib_type TP_MIB_TID_INV; 666 struct tp_mib_type TP_MIB_TID_ACT; 667 struct tp_mib_type TP_MIB_TID_PAS; 668 struct tp_mib_type TP_MIB_RQE_DFR_MOD; 669 struct tp_mib_type TP_MIB_RQE_DFR_PKT; 670 }; 671 672 struct cudbg_reg_info { 673 const char *name; 674 unsigned int addr; 675 unsigned int len; 676 }; 677 678 struct tp1_reg_info { 679 char addr[10]; 680 char name[40]; 681 }; 682 683 struct ireg_field { 684 u32 ireg_addr; 685 u32 ireg_data; 686 u32 ireg_local_offset; 687 u32 ireg_offset_range; 688 }; 689 690 struct ireg_buf { 691 struct ireg_field tp_pio; 692 u32 outbuf[32]; 693 }; 694 695 struct tx_rate { 696 u64 nrate[NCHAN]; 697 u64 orate[NCHAN]; 698 u32 nchan; 699 }; 700 701 struct tid_info_region { 702 u32 ntids; 703 u32 nstids; 704 u32 stid_base; 705 u32 hash_base; 706 707 u32 natids; 708 u32 nftids; 709 u32 ftid_base; 710 u32 aftid_base; 711 u32 aftid_end; 712 713 /* Server filter region */ 714 u32 sftid_base; 715 u32 nsftids; 716 717 /* UO context range */ 718 u32 uotid_base; 719 u32 nuotids; 720 721 u32 sb; 722 u32 flags; 723 u32 le_db_conf; 724 u32 IP_users; 725 u32 IPv6_users; 726 727 u32 hpftid_base; 728 u32 nhpftids; 729 }; 730 731 struct tid_info_region_rev1 { 732 struct cudbg_ver_hdr ver_hdr; 733 struct tid_info_region tid; 734 u32 tid_start; 735 u32 reserved[16]; 736 }; 737 738 struct struct_vpd_data { 739 u8 sn[SN_MAX_LEN + 1]; 740 u8 bn[BN_MAX_LEN + 1]; 741 u8 na[NA_MAX_LEN + 1]; 742 u8 mn[MN_MAX_LEN + 1]; 743 u16 fw_major; 744 u16 fw_minor; 745 u16 fw_micro; 746 u16 fw_build; 747 u32 scfg_vers; 748 u32 vpd_vers; 749 }; 750 751 struct sw_state { 752 u32 fw_state; 753 u8 caller_string[100]; 754 u8 os_type; 755 u8 reserved[3]; 756 u32 reserved1[16]; 757 }; 758 759 static u32 ATTRIBUTE_UNUSED t6_tp_pio_array[][4] = { 760 {0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */ 761 {0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */ 762 {0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */ 763 {0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */ 764 {0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */ 765 {0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */ 766 {0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */ 767 {0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */ 768 {0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */ 769 {0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */ 770 {0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */ 771 {0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */ 772 }; 773 774 static u32 ATTRIBUTE_UNUSED t5_tp_pio_array[][4] = { 775 {0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */ 776 {0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */ 777 {0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */ 778 {0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */ 779 {0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */ 780 {0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */ 781 {0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */ 782 {0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */ 783 {0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */ 784 {0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */ 785 {0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */ 786 }; 787 788 static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array[][4] = { 789 {0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */ 790 {0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */ 791 {0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */ 792 }; 793 794 static u32 ATTRIBUTE_UNUSED t6_ma_ireg_array2[][4] = { 795 {0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */ 796 {0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */ 797 }; 798 799 static u32 ATTRIBUTE_UNUSED t6_hma_ireg_array[][4] = { 800 {0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */ 801 }; 802 static u32 ATTRIBUTE_UNUSED t5_pcie_pdbg_array[][4] = { 803 {0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */ 804 {0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */ 805 {0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */ 806 }; 807 808 static u32 ATTRIBUTE_UNUSED t5_pcie_config_array[][2] = { 809 {0x0, 0x34}, 810 {0x3c, 0x40}, 811 {0x50, 0x64}, 812 {0x70, 0x80}, 813 {0x94, 0xa0}, 814 {0xb0, 0xb8}, 815 {0xd0, 0xd4}, 816 {0x100, 0x128}, 817 {0x140, 0x148}, 818 {0x150, 0x164}, 819 {0x170, 0x178}, 820 {0x180, 0x194}, 821 {0x1a0, 0x1b8}, 822 {0x1c0, 0x208}, 823 }; 824 825 static u32 ATTRIBUTE_UNUSED t5_pcie_cdbg_array[][4] = { 826 {0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */ 827 {0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */ 828 }; 829 830 static u32 ATTRIBUTE_UNUSED t6_tp_tm_pio_array[1][4] = { 831 {0x7e18, 0x7e1c, 0x0, 12} 832 }; 833 834 static u32 ATTRIBUTE_UNUSED t5_tp_tm_pio_array[1][4] = { 835 {0x7e18, 0x7e1c, 0x0, 12} 836 }; 837 838 static u32 ATTRIBUTE_UNUSED t5_pm_rx_array[][4] = { 839 {0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */ 840 {0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */ 841 }; 842 843 static u32 ATTRIBUTE_UNUSED t5_pm_tx_array[][4] = { 844 {0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */ 845 {0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */ 846 }; 847 848 static u32 ATTRIBUTE_UNUSED t6_tp_mib_index_array[6][4] = { 849 {0x7e50, 0x7e54, 0x0, 13}, 850 {0x7e50, 0x7e54, 0x10, 6}, 851 {0x7e50, 0x7e54, 0x18, 21}, 852 {0x7e50, 0x7e54, 0x30, 32}, 853 {0x7e50, 0x7e54, 0x50, 22}, 854 {0x7e50, 0x7e54, 0x68, 12} 855 }; 856 857 static u32 ATTRIBUTE_UNUSED t5_tp_mib_index_array[9][4] = { 858 {0x7e50, 0x7e54, 0x0, 13}, 859 {0x7e50, 0x7e54, 0x10, 6}, 860 {0x7e50, 0x7e54, 0x18, 8}, 861 {0x7e50, 0x7e54, 0x20, 13}, 862 {0x7e50, 0x7e54, 0x30, 16}, 863 {0x7e50, 0x7e54, 0x40, 16}, 864 {0x7e50, 0x7e54, 0x50, 16}, 865 {0x7e50, 0x7e54, 0x60, 6}, 866 {0x7e50, 0x7e54, 0x68, 4} 867 }; 868 869 static u32 ATTRIBUTE_UNUSED t5_sge_dbg_index_array[9][4] = { 870 {0x10cc, 0x10d0, 0x0, 16}, 871 {0x10cc, 0x10d4, 0x0, 16}, 872 }; 873 874 static u32 ATTRIBUTE_UNUSED t6_up_cim_reg_array[][4] = { 875 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */ 876 {0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */ 877 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */ 878 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */ 879 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */ 880 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */ 881 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */ 882 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */ 883 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */ 884 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */ 885 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */ 886 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */ 887 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */ 888 889 }; 890 891 static u32 ATTRIBUTE_UNUSED t5_up_cim_reg_array[][4] = { 892 {0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */ 893 {0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */ 894 {0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */ 895 {0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */ 896 {0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */ 897 {0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */ 898 {0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */ 899 {0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */ 900 {0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */ 901 {0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */ 902 {0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */ 903 {0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */ 904 {0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */ 905 }; 906 907 #endif 908