1 /*- 2 * Copyright (c) 2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/types.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/malloc.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/sglist.h> 38 39 #include <opencrypto/cryptodev.h> 40 #include <opencrypto/xform.h> 41 42 #include "cryptodev_if.h" 43 44 #include "common/common.h" 45 #include "crypto/t4_crypto.h" 46 47 /* 48 * Requests consist of: 49 * 50 * +-------------------------------+ 51 * | struct fw_crypto_lookaside_wr | 52 * +-------------------------------+ 53 * | struct ulp_txpkt | 54 * +-------------------------------+ 55 * | struct ulptx_idata | 56 * +-------------------------------+ 57 * | struct cpl_tx_sec_pdu | 58 * +-------------------------------+ 59 * | struct cpl_tls_tx_scmd_fmt | 60 * +-------------------------------+ 61 * | key context header | 62 * +-------------------------------+ 63 * | AES key | ----- For requests with AES 64 * +-------------------------------+ - 65 * | IPAD (16-byte aligned) | \ 66 * +-------------------------------+ +---- For requests with HMAC 67 * | OPAD (16-byte aligned) | / 68 * +-------------------------------+ - 69 * | GMAC H | ----- For AES-GCM 70 * +-------------------------------+ - 71 * | struct cpl_rx_phys_dsgl | \ 72 * +-------------------------------+ +---- Destination buffer for 73 * | PHYS_DSGL entries | / non-hash-only requests 74 * +-------------------------------+ - 75 * | 16 dummy bytes | ----- Only for hash-only requests 76 * +-------------------------------+ 77 * | IV | ----- If immediate IV 78 * +-------------------------------+ 79 * | Payload | ----- If immediate Payload 80 * +-------------------------------+ - 81 * | struct ulptx_sgl | \ 82 * +-------------------------------+ +---- If payload via SGL 83 * | SGL entries | / 84 * +-------------------------------+ - 85 * 86 * Note that the key context must be padded to ensure 16-byte alignment. 87 * For HMAC requests, the key consists of the partial hash of the IPAD 88 * followed by the partial hash of the OPAD. 89 * 90 * Replies consist of: 91 * 92 * +-------------------------------+ 93 * | struct cpl_fw6_pld | 94 * +-------------------------------+ 95 * | hash digest | ----- For HMAC request with 96 * +-------------------------------+ 'hash_size' set in work request 97 * 98 * A 32-bit big-endian error status word is supplied in the last 4 99 * bytes of data[0] in the CPL_FW6_PLD message. bit 0 indicates a 100 * "MAC" error and bit 1 indicates a "PAD" error. 101 * 102 * The 64-bit 'cookie' field from the fw_crypto_lookaside_wr message 103 * in the request is returned in data[1] of the CPL_FW6_PLD message. 104 * 105 * For block cipher replies, the updated IV is supplied in data[2] and 106 * data[3] of the CPL_FW6_PLD message. 107 * 108 * For hash replies where the work request set 'hash_size' to request 109 * a copy of the hash in the reply, the hash digest is supplied 110 * immediately following the CPL_FW6_PLD message. 111 */ 112 113 /* 114 * The documentation for CPL_RX_PHYS_DSGL claims a maximum of 32 115 * SG entries. 116 */ 117 #define MAX_RX_PHYS_DSGL_SGE 32 118 #define DSGL_SGE_MAXLEN 65535 119 120 /* 121 * The adapter only supports requests with a total input or output 122 * length of 64k-1 or smaller. Longer requests either result in hung 123 * requests or incorrect results. 124 */ 125 #define MAX_REQUEST_SIZE 65535 126 127 static MALLOC_DEFINE(M_CCR, "ccr", "Chelsio T6 crypto"); 128 129 struct ccr_session_hmac { 130 struct auth_hash *auth_hash; 131 int hash_len; 132 unsigned int partial_digest_len; 133 unsigned int auth_mode; 134 unsigned int mk_size; 135 char ipad[CHCR_HASH_MAX_BLOCK_SIZE_128]; 136 char opad[CHCR_HASH_MAX_BLOCK_SIZE_128]; 137 }; 138 139 struct ccr_session_gmac { 140 int hash_len; 141 char ghash_h[GMAC_BLOCK_LEN]; 142 }; 143 144 struct ccr_session_blkcipher { 145 unsigned int cipher_mode; 146 unsigned int key_len; 147 unsigned int iv_len; 148 __be32 key_ctx_hdr; 149 char enckey[CHCR_AES_MAX_KEY_LEN]; 150 char deckey[CHCR_AES_MAX_KEY_LEN]; 151 }; 152 153 struct ccr_session { 154 bool active; 155 int pending; 156 enum { HMAC, BLKCIPHER, AUTHENC, GCM } mode; 157 union { 158 struct ccr_session_hmac hmac; 159 struct ccr_session_gmac gmac; 160 }; 161 struct ccr_session_blkcipher blkcipher; 162 }; 163 164 struct ccr_softc { 165 struct adapter *adapter; 166 device_t dev; 167 uint32_t cid; 168 int tx_channel_id; 169 struct ccr_session *sessions; 170 int nsessions; 171 struct mtx lock; 172 bool detaching; 173 struct sge_wrq *txq; 174 struct sge_rxq *rxq; 175 176 /* 177 * Pre-allocate S/G lists used when preparing a work request. 178 * 'sg_crp' contains an sglist describing the entire buffer 179 * for a 'struct cryptop'. 'sg_ulptx' is used to describe 180 * the data the engine should DMA as input via ULPTX_SGL. 181 * 'sg_dsgl' is used to describe the destination that cipher 182 * text and a tag should be written to. 183 */ 184 struct sglist *sg_crp; 185 struct sglist *sg_ulptx; 186 struct sglist *sg_dsgl; 187 188 /* Statistics. */ 189 uint64_t stats_blkcipher_encrypt; 190 uint64_t stats_blkcipher_decrypt; 191 uint64_t stats_hmac; 192 uint64_t stats_authenc_encrypt; 193 uint64_t stats_authenc_decrypt; 194 uint64_t stats_gcm_encrypt; 195 uint64_t stats_gcm_decrypt; 196 uint64_t stats_wr_nomem; 197 uint64_t stats_inflight; 198 uint64_t stats_mac_error; 199 uint64_t stats_pad_error; 200 uint64_t stats_bad_session; 201 uint64_t stats_sglist_error; 202 uint64_t stats_process_error; 203 }; 204 205 /* 206 * Crypto requests involve two kind of scatter/gather lists. 207 * 208 * Non-hash-only requests require a PHYS_DSGL that describes the 209 * location to store the results of the encryption or decryption 210 * operation. This SGL uses a different format (PHYS_DSGL) and should 211 * exclude the crd_skip bytes at the start of the data as well as 212 * any AAD or IV. For authenticated encryption requests it should 213 * cover include the destination of the hash or tag. 214 * 215 * The input payload may either be supplied inline as immediate data, 216 * or via a standard ULP_TX SGL. This SGL should include AAD, 217 * ciphertext, and the hash or tag for authenticated decryption 218 * requests. 219 * 220 * These scatter/gather lists can describe different subsets of the 221 * buffer described by the crypto operation. ccr_populate_sglist() 222 * generates a scatter/gather list that covers the entire crypto 223 * operation buffer that is then used to construct the other 224 * scatter/gather lists. 225 */ 226 static int 227 ccr_populate_sglist(struct sglist *sg, struct cryptop *crp) 228 { 229 int error; 230 231 sglist_reset(sg); 232 if (crp->crp_flags & CRYPTO_F_IMBUF) 233 error = sglist_append_mbuf(sg, (struct mbuf *)crp->crp_buf); 234 else if (crp->crp_flags & CRYPTO_F_IOV) 235 error = sglist_append_uio(sg, (struct uio *)crp->crp_buf); 236 else 237 error = sglist_append(sg, crp->crp_buf, crp->crp_ilen); 238 return (error); 239 } 240 241 /* 242 * Segments in 'sg' larger than 'maxsegsize' are counted as multiple 243 * segments. 244 */ 245 static int 246 ccr_count_sgl(struct sglist *sg, int maxsegsize) 247 { 248 int i, nsegs; 249 250 nsegs = 0; 251 for (i = 0; i < sg->sg_nseg; i++) 252 nsegs += howmany(sg->sg_segs[i].ss_len, maxsegsize); 253 return (nsegs); 254 } 255 256 /* These functions deal with PHYS_DSGL for the reply buffer. */ 257 static inline int 258 ccr_phys_dsgl_len(int nsegs) 259 { 260 int len; 261 262 len = (nsegs / 8) * sizeof(struct phys_sge_pairs); 263 if ((nsegs % 8) != 0) { 264 len += sizeof(uint16_t) * 8; 265 len += roundup2(nsegs % 8, 2) * sizeof(uint64_t); 266 } 267 return (len); 268 } 269 270 static void 271 ccr_write_phys_dsgl(struct ccr_softc *sc, void *dst, int nsegs) 272 { 273 struct sglist *sg; 274 struct cpl_rx_phys_dsgl *cpl; 275 struct phys_sge_pairs *sgl; 276 vm_paddr_t paddr; 277 size_t seglen; 278 u_int i, j; 279 280 sg = sc->sg_dsgl; 281 cpl = dst; 282 cpl->op_to_tid = htobe32(V_CPL_RX_PHYS_DSGL_OPCODE(CPL_RX_PHYS_DSGL) | 283 V_CPL_RX_PHYS_DSGL_ISRDMA(0)); 284 cpl->pcirlxorder_to_noofsgentr = htobe32( 285 V_CPL_RX_PHYS_DSGL_PCIRLXORDER(0) | 286 V_CPL_RX_PHYS_DSGL_PCINOSNOOP(0) | 287 V_CPL_RX_PHYS_DSGL_PCITPHNTENB(0) | V_CPL_RX_PHYS_DSGL_DCAID(0) | 288 V_CPL_RX_PHYS_DSGL_NOOFSGENTR(nsegs)); 289 cpl->rss_hdr_int.opcode = CPL_RX_PHYS_ADDR; 290 cpl->rss_hdr_int.qid = htobe16(sc->rxq->iq.abs_id); 291 cpl->rss_hdr_int.hash_val = 0; 292 sgl = (struct phys_sge_pairs *)(cpl + 1); 293 j = 0; 294 for (i = 0; i < sg->sg_nseg; i++) { 295 seglen = sg->sg_segs[i].ss_len; 296 paddr = sg->sg_segs[i].ss_paddr; 297 do { 298 sgl->addr[j] = htobe64(paddr); 299 if (seglen > DSGL_SGE_MAXLEN) { 300 sgl->len[j] = htobe16(DSGL_SGE_MAXLEN); 301 paddr += DSGL_SGE_MAXLEN; 302 seglen -= DSGL_SGE_MAXLEN; 303 } else { 304 sgl->len[j] = htobe16(seglen); 305 seglen = 0; 306 } 307 j++; 308 if (j == 8) { 309 sgl++; 310 j = 0; 311 } 312 } while (seglen != 0); 313 } 314 MPASS(j + 8 * (sgl - (struct phys_sge_pairs *)(cpl + 1)) == nsegs); 315 } 316 317 /* These functions deal with the ULPTX_SGL for input payload. */ 318 static inline int 319 ccr_ulptx_sgl_len(int nsegs) 320 { 321 u_int n; 322 323 nsegs--; /* first segment is part of ulptx_sgl */ 324 n = sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 325 return (roundup2(n, 16)); 326 } 327 328 static void 329 ccr_write_ulptx_sgl(struct ccr_softc *sc, void *dst, int nsegs) 330 { 331 struct ulptx_sgl *usgl; 332 struct sglist *sg; 333 struct sglist_seg *ss; 334 int i; 335 336 sg = sc->sg_ulptx; 337 MPASS(nsegs == sg->sg_nseg); 338 ss = &sg->sg_segs[0]; 339 usgl = dst; 340 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 341 V_ULPTX_NSGE(nsegs)); 342 usgl->len0 = htobe32(ss->ss_len); 343 usgl->addr0 = htobe64(ss->ss_paddr); 344 ss++; 345 for (i = 0; i < sg->sg_nseg - 1; i++) { 346 usgl->sge[i / 2].len[i & 1] = htobe32(ss->ss_len); 347 usgl->sge[i / 2].addr[i & 1] = htobe64(ss->ss_paddr); 348 ss++; 349 } 350 351 } 352 353 static bool 354 ccr_use_imm_data(u_int transhdr_len, u_int input_len) 355 { 356 357 if (input_len > CRYPTO_MAX_IMM_TX_PKT_LEN) 358 return (false); 359 if (roundup2(transhdr_len, 16) + roundup2(input_len, 16) > 360 SGE_MAX_WR_LEN) 361 return (false); 362 return (true); 363 } 364 365 static void 366 ccr_populate_wreq(struct ccr_softc *sc, struct chcr_wr *crwr, u_int kctx_len, 367 u_int wr_len, uint32_t sid, u_int imm_len, u_int sgl_len, u_int hash_size, 368 u_int iv_loc, struct cryptop *crp) 369 { 370 u_int cctx_size; 371 372 cctx_size = sizeof(struct _key_ctx) + kctx_len; 373 crwr->wreq.op_to_cctx_size = htobe32( 374 V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(FW_CRYPTO_LOOKASIDE_WR) | 375 V_FW_CRYPTO_LOOKASIDE_WR_COMPL(0) | 376 V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(imm_len) | 377 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(1) | 378 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(cctx_size >> 4)); 379 crwr->wreq.len16_pkd = htobe32( 380 V_FW_CRYPTO_LOOKASIDE_WR_LEN16(wr_len / 16)); 381 crwr->wreq.session_id = htobe32(sid); 382 crwr->wreq.rx_chid_to_rx_q_id = htobe32( 383 V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(sc->tx_channel_id) | 384 V_FW_CRYPTO_LOOKASIDE_WR_LCB(0) | 385 V_FW_CRYPTO_LOOKASIDE_WR_PHASH(0) | 386 V_FW_CRYPTO_LOOKASIDE_WR_IV(iv_loc) | 387 V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(0) | 388 V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(0) | 389 V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(sc->rxq->iq.abs_id)); 390 crwr->wreq.key_addr = 0; 391 crwr->wreq.pld_size_hash_size = htobe32( 392 V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(sgl_len) | 393 V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(hash_size)); 394 crwr->wreq.cookie = htobe64((uintptr_t)crp); 395 396 crwr->ulptx.cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 397 V_ULP_TXPKT_DATAMODIFY(0) | 398 V_ULP_TXPKT_CHANNELID(sc->tx_channel_id) | V_ULP_TXPKT_DEST(0) | 399 V_ULP_TXPKT_FID(0) | V_ULP_TXPKT_RO(1)); 400 crwr->ulptx.len = htobe32( 401 ((wr_len - sizeof(struct fw_crypto_lookaside_wr)) / 16)); 402 403 crwr->sc_imm.cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 404 V_ULP_TX_SC_MORE(imm_len != 0 ? 0 : 1)); 405 crwr->sc_imm.len = htobe32(wr_len - offsetof(struct chcr_wr, sec_cpl) - 406 sgl_len); 407 } 408 409 static int 410 ccr_hmac(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 411 struct cryptop *crp) 412 { 413 struct chcr_wr *crwr; 414 struct wrqe *wr; 415 struct auth_hash *axf; 416 struct cryptodesc *crd; 417 char *dst; 418 u_int hash_size_in_response, kctx_flits, kctx_len, transhdr_len, wr_len; 419 u_int imm_len, iopad_size; 420 int error, sgl_nsegs, sgl_len; 421 422 crd = crp->crp_desc; 423 424 /* Reject requests with too large of an input buffer. */ 425 if (crd->crd_len > MAX_REQUEST_SIZE) 426 return (EFBIG); 427 428 axf = s->hmac.auth_hash; 429 430 /* PADs must be 128-bit aligned. */ 431 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 432 433 /* 434 * The 'key' part of the context includes the aligned IPAD and 435 * OPAD. 436 */ 437 kctx_len = iopad_size * 2; 438 hash_size_in_response = axf->hashsize; 439 transhdr_len = HASH_TRANSHDR_SIZE(kctx_len); 440 441 if (ccr_use_imm_data(transhdr_len, crd->crd_len)) { 442 imm_len = crd->crd_len; 443 sgl_nsegs = 0; 444 sgl_len = 0; 445 } else { 446 imm_len = 0; 447 sglist_reset(sc->sg_ulptx); 448 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 449 crd->crd_skip, crd->crd_len); 450 if (error) 451 return (error); 452 sgl_nsegs = sc->sg_ulptx->sg_nseg; 453 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 454 } 455 456 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 457 wr = alloc_wrqe(wr_len, sc->txq); 458 if (wr == NULL) { 459 sc->stats_wr_nomem++; 460 return (ENOMEM); 461 } 462 crwr = wrtod(wr); 463 memset(crwr, 0, wr_len); 464 465 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 466 hash_size_in_response, IV_NOP, crp); 467 468 /* XXX: Hardcodes SGE loopback channel of 0. */ 469 crwr->sec_cpl.op_ivinsrtofst = htobe32( 470 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 471 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 472 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 473 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 474 V_CPL_TX_SEC_PDU_IVINSRTOFST(0)); 475 476 crwr->sec_cpl.pldlen = htobe32(crd->crd_len); 477 478 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 479 V_CPL_TX_SEC_PDU_AUTHSTART(1) | V_CPL_TX_SEC_PDU_AUTHSTOP(0)); 480 481 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 482 crwr->sec_cpl.seqno_numivs = htobe32( 483 V_SCMD_SEQ_NO_CTRL(0) | 484 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 485 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_NOP) | 486 V_SCMD_AUTH_MODE(s->hmac.auth_mode) | 487 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NO_TRUNC)); 488 crwr->sec_cpl.ivgen_hdrlen = htobe32( 489 V_SCMD_LAST_FRAG(0) | V_SCMD_MORE_FRAGS(0) | V_SCMD_MAC_ONLY(1)); 490 491 memcpy(crwr->key_ctx.key, s->hmac.ipad, s->hmac.partial_digest_len); 492 memcpy(crwr->key_ctx.key + iopad_size, s->hmac.opad, 493 s->hmac.partial_digest_len); 494 495 /* XXX: F_KEY_CONTEXT_SALT_PRESENT set, but 'salt' not set. */ 496 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16; 497 crwr->key_ctx.ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) | 498 V_KEY_CONTEXT_OPAD_PRESENT(1) | V_KEY_CONTEXT_SALT_PRESENT(1) | 499 V_KEY_CONTEXT_CK_SIZE(CHCR_KEYCTX_NO_KEY) | 500 V_KEY_CONTEXT_MK_SIZE(s->hmac.mk_size) | V_KEY_CONTEXT_VALID(1)); 501 502 dst = (char *)(crwr + 1) + kctx_len + DUMMY_BYTES; 503 if (imm_len != 0) 504 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip, 505 crd->crd_len, dst); 506 else 507 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 508 509 /* XXX: TODO backpressure */ 510 t4_wrq_tx(sc->adapter, wr); 511 512 return (0); 513 } 514 515 static int 516 ccr_hmac_done(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp, 517 const struct cpl_fw6_pld *cpl, int error) 518 { 519 struct cryptodesc *crd; 520 521 crd = crp->crp_desc; 522 if (error == 0) { 523 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 524 s->hmac.hash_len, (c_caddr_t)(cpl + 1)); 525 } 526 527 return (error); 528 } 529 530 static int 531 ccr_blkcipher(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 532 struct cryptop *crp) 533 { 534 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 535 struct chcr_wr *crwr; 536 struct wrqe *wr; 537 struct cryptodesc *crd; 538 char *dst; 539 u_int iv_loc, kctx_len, key_half, op_type, transhdr_len, wr_len; 540 u_int imm_len; 541 int dsgl_nsegs, dsgl_len; 542 int sgl_nsegs, sgl_len; 543 int error; 544 545 crd = crp->crp_desc; 546 547 if (s->blkcipher.key_len == 0) 548 return (EINVAL); 549 if (crd->crd_alg == CRYPTO_AES_CBC && 550 (crd->crd_len % AES_BLOCK_LEN) != 0) 551 return (EINVAL); 552 553 /* Reject requests with too large of an input buffer. */ 554 if (crd->crd_len > MAX_REQUEST_SIZE) 555 return (EFBIG); 556 557 iv_loc = IV_NOP; 558 if (crd->crd_flags & CRD_F_ENCRYPT) { 559 op_type = CHCR_ENCRYPT_OP; 560 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 561 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len); 562 else 563 arc4rand(iv, s->blkcipher.iv_len, 0); 564 iv_loc = IV_IMMEDIATE; 565 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) 566 crypto_copyback(crp->crp_flags, crp->crp_buf, 567 crd->crd_inject, s->blkcipher.iv_len, iv); 568 } else { 569 op_type = CHCR_DECRYPT_OP; 570 if (crd->crd_flags & CRD_F_IV_EXPLICIT) { 571 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len); 572 iv_loc = IV_IMMEDIATE; 573 } else 574 iv_loc = IV_DSGL; 575 } 576 577 sglist_reset(sc->sg_dsgl); 578 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crd->crd_skip, 579 crd->crd_len); 580 if (error) 581 return (error); 582 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 583 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 584 return (EFBIG); 585 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 586 587 /* The 'key' must be 128-bit aligned. */ 588 kctx_len = roundup2(s->blkcipher.key_len, 16); 589 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 590 591 if (ccr_use_imm_data(transhdr_len, crd->crd_len + 592 s->blkcipher.iv_len)) { 593 imm_len = crd->crd_len; 594 if (iv_loc == IV_DSGL) { 595 crypto_copydata(crp->crp_flags, crp->crp_buf, 596 crd->crd_inject, s->blkcipher.iv_len, iv); 597 iv_loc = IV_IMMEDIATE; 598 } 599 sgl_nsegs = 0; 600 sgl_len = 0; 601 } else { 602 imm_len = 0; 603 sglist_reset(sc->sg_ulptx); 604 if (iv_loc == IV_DSGL) { 605 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 606 crd->crd_inject, s->blkcipher.iv_len); 607 if (error) 608 return (error); 609 } 610 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 611 crd->crd_skip, crd->crd_len); 612 if (error) 613 return (error); 614 sgl_nsegs = sc->sg_ulptx->sg_nseg; 615 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 616 } 617 618 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 619 if (iv_loc == IV_IMMEDIATE) 620 wr_len += s->blkcipher.iv_len; 621 wr = alloc_wrqe(wr_len, sc->txq); 622 if (wr == NULL) { 623 sc->stats_wr_nomem++; 624 return (ENOMEM); 625 } 626 crwr = wrtod(wr); 627 memset(crwr, 0, wr_len); 628 629 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 0, 630 iv_loc, crp); 631 632 /* XXX: Hardcodes SGE loopback channel of 0. */ 633 crwr->sec_cpl.op_ivinsrtofst = htobe32( 634 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 635 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 636 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 637 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 638 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 639 640 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + crd->crd_len); 641 642 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 643 V_CPL_TX_SEC_PDU_CIPHERSTART(s->blkcipher.iv_len + 1) | 644 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0)); 645 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 646 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0)); 647 648 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 649 crwr->sec_cpl.seqno_numivs = htobe32( 650 V_SCMD_SEQ_NO_CTRL(0) | 651 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 652 V_SCMD_ENC_DEC_CTRL(op_type) | 653 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) | 654 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_NOP) | 655 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NOP) | 656 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) | 657 V_SCMD_NUM_IVS(0)); 658 crwr->sec_cpl.ivgen_hdrlen = htobe32( 659 V_SCMD_IV_GEN_CTRL(0) | 660 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 661 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len)); 662 663 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 664 switch (crd->crd_alg) { 665 case CRYPTO_AES_CBC: 666 if (crd->crd_flags & CRD_F_ENCRYPT) 667 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 668 s->blkcipher.key_len); 669 else 670 memcpy(crwr->key_ctx.key, s->blkcipher.deckey, 671 s->blkcipher.key_len); 672 break; 673 case CRYPTO_AES_ICM: 674 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 675 s->blkcipher.key_len); 676 break; 677 case CRYPTO_AES_XTS: 678 key_half = s->blkcipher.key_len / 2; 679 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half, 680 key_half); 681 if (crd->crd_flags & CRD_F_ENCRYPT) 682 memcpy(crwr->key_ctx.key + key_half, 683 s->blkcipher.enckey, key_half); 684 else 685 memcpy(crwr->key_ctx.key + key_half, 686 s->blkcipher.deckey, key_half); 687 break; 688 } 689 690 dst = (char *)(crwr + 1) + kctx_len; 691 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 692 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 693 if (iv_loc == IV_IMMEDIATE) { 694 memcpy(dst, iv, s->blkcipher.iv_len); 695 dst += s->blkcipher.iv_len; 696 } 697 if (imm_len != 0) 698 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip, 699 crd->crd_len, dst); 700 else 701 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 702 703 /* XXX: TODO backpressure */ 704 t4_wrq_tx(sc->adapter, wr); 705 706 return (0); 707 } 708 709 static int 710 ccr_blkcipher_done(struct ccr_softc *sc, struct ccr_session *s, 711 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 712 { 713 714 /* 715 * The updated IV to permit chained requests is at 716 * cpl->data[2], but OCF doesn't permit chained requests. 717 */ 718 return (error); 719 } 720 721 /* 722 * 'hashsize' is the length of a full digest. 'authsize' is the 723 * requested digest length for this operation which may be less 724 * than 'hashsize'. 725 */ 726 static int 727 ccr_hmac_ctrl(unsigned int hashsize, unsigned int authsize) 728 { 729 730 if (authsize == 10) 731 return (CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366); 732 if (authsize == 12) 733 return (CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT); 734 if (authsize == hashsize / 2) 735 return (CHCR_SCMD_HMAC_CTRL_DIV2); 736 return (CHCR_SCMD_HMAC_CTRL_NO_TRUNC); 737 } 738 739 static int 740 ccr_authenc(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 741 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde) 742 { 743 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 744 struct chcr_wr *crwr; 745 struct wrqe *wr; 746 struct auth_hash *axf; 747 char *dst; 748 u_int iv_loc, kctx_len, key_half, op_type, transhdr_len, wr_len; 749 u_int hash_size_in_response, imm_len, iopad_size; 750 u_int aad_start, aad_len, aad_stop; 751 u_int auth_start, auth_stop, auth_insert; 752 u_int cipher_start, cipher_stop; 753 u_int hmac_ctrl, input_len; 754 int dsgl_nsegs, dsgl_len; 755 int sgl_nsegs, sgl_len; 756 int error; 757 758 if (s->blkcipher.key_len == 0) 759 return (EINVAL); 760 if (crde->crd_alg == CRYPTO_AES_CBC && 761 (crde->crd_len % AES_BLOCK_LEN) != 0) 762 return (EINVAL); 763 764 /* 765 * AAD is only permitted before the cipher/plain text, not 766 * after. 767 */ 768 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip) 769 return (EINVAL); 770 771 axf = s->hmac.auth_hash; 772 hash_size_in_response = s->hmac.hash_len; 773 774 /* 775 * The IV is always stored at the start of the buffer even 776 * though it may be duplicated in the payload. The crypto 777 * engine doesn't work properly if the IV offset points inside 778 * of the AAD region, so a second copy is always required. 779 */ 780 iv_loc = IV_IMMEDIATE; 781 if (crde->crd_flags & CRD_F_ENCRYPT) { 782 op_type = CHCR_ENCRYPT_OP; 783 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 784 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 785 else 786 arc4rand(iv, s->blkcipher.iv_len, 0); 787 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0) 788 crypto_copyback(crp->crp_flags, crp->crp_buf, 789 crde->crd_inject, s->blkcipher.iv_len, iv); 790 } else { 791 op_type = CHCR_DECRYPT_OP; 792 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 793 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 794 else 795 crypto_copydata(crp->crp_flags, crp->crp_buf, 796 crde->crd_inject, s->blkcipher.iv_len, iv); 797 } 798 799 /* 800 * The output buffer consists of the cipher text followed by 801 * the hash when encrypting. For decryption it only contains 802 * the plain text. 803 */ 804 if (op_type == CHCR_ENCRYPT_OP) { 805 if (crde->crd_len + hash_size_in_response > MAX_REQUEST_SIZE) 806 return (EFBIG); 807 } else { 808 if (crde->crd_len > MAX_REQUEST_SIZE) 809 return (EFBIG); 810 } 811 sglist_reset(sc->sg_dsgl); 812 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip, 813 crde->crd_len); 814 if (error) 815 return (error); 816 if (op_type == CHCR_ENCRYPT_OP) { 817 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, 818 crda->crd_inject, hash_size_in_response); 819 if (error) 820 return (error); 821 } 822 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 823 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 824 return (EFBIG); 825 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 826 827 /* PADs must be 128-bit aligned. */ 828 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 829 830 /* 831 * The 'key' part of the key context consists of the key followed 832 * by the IPAD and OPAD. 833 */ 834 kctx_len = roundup2(s->blkcipher.key_len, 16) + iopad_size * 2; 835 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 836 837 /* 838 * The input buffer consists of the IV, any AAD, and then the 839 * cipher/plain text. For decryption requests the hash is 840 * appended after the cipher text. 841 */ 842 if (crda->crd_skip < crde->crd_skip) { 843 if (crda->crd_skip + crda->crd_len > crde->crd_skip) 844 aad_len = (crde->crd_skip - crda->crd_skip); 845 else 846 aad_len = crda->crd_len; 847 } else 848 aad_len = 0; 849 input_len = aad_len + crde->crd_len; 850 851 /* 852 * The firmware hangs if sent a request which is a 853 * bit smaller than MAX_REQUEST_SIZE. In particular, the 854 * firmware appears to require 512 - 16 bytes of spare room 855 * along with the size of the hash even if the hash isn't 856 * included in the input buffer. 857 */ 858 if (input_len + roundup2(axf->hashsize, 16) + (512 - 16) > 859 MAX_REQUEST_SIZE) 860 return (EFBIG); 861 if (op_type == CHCR_DECRYPT_OP) 862 input_len += hash_size_in_response; 863 if (ccr_use_imm_data(transhdr_len, s->blkcipher.iv_len + input_len)) { 864 imm_len = input_len; 865 sgl_nsegs = 0; 866 sgl_len = 0; 867 } else { 868 imm_len = 0; 869 sglist_reset(sc->sg_ulptx); 870 if (aad_len != 0) { 871 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 872 crda->crd_skip, aad_len); 873 if (error) 874 return (error); 875 } 876 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 877 crde->crd_skip, crde->crd_len); 878 if (error) 879 return (error); 880 if (op_type == CHCR_DECRYPT_OP) { 881 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 882 crda->crd_inject, hash_size_in_response); 883 if (error) 884 return (error); 885 } 886 sgl_nsegs = sc->sg_ulptx->sg_nseg; 887 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 888 } 889 890 /* 891 * Any auth-only data before the cipher region is marked as AAD. 892 * Auth-data that overlaps with the cipher region is placed in 893 * the auth section. 894 */ 895 if (aad_len != 0) { 896 aad_start = s->blkcipher.iv_len + 1; 897 aad_stop = aad_start + aad_len - 1; 898 } else { 899 aad_start = 0; 900 aad_stop = 0; 901 } 902 cipher_start = s->blkcipher.iv_len + aad_len + 1; 903 if (op_type == CHCR_DECRYPT_OP) 904 cipher_stop = hash_size_in_response; 905 else 906 cipher_stop = 0; 907 if (aad_len == crda->crd_len) { 908 auth_start = 0; 909 auth_stop = 0; 910 } else { 911 if (aad_len != 0) 912 auth_start = cipher_start; 913 else 914 auth_start = s->blkcipher.iv_len + crda->crd_skip - 915 crde->crd_skip + 1; 916 auth_stop = (crde->crd_skip + crde->crd_len) - 917 (crda->crd_skip + crda->crd_len) + cipher_stop; 918 } 919 if (op_type == CHCR_DECRYPT_OP) 920 auth_insert = hash_size_in_response; 921 else 922 auth_insert = 0; 923 924 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 925 if (iv_loc == IV_IMMEDIATE) 926 wr_len += s->blkcipher.iv_len; 927 wr = alloc_wrqe(wr_len, sc->txq); 928 if (wr == NULL) { 929 sc->stats_wr_nomem++; 930 return (ENOMEM); 931 } 932 crwr = wrtod(wr); 933 memset(crwr, 0, wr_len); 934 935 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 936 op_type == CHCR_DECRYPT_OP ? hash_size_in_response : 0, iv_loc, 937 crp); 938 939 /* XXX: Hardcodes SGE loopback channel of 0. */ 940 crwr->sec_cpl.op_ivinsrtofst = htobe32( 941 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 942 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 943 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 944 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 945 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 946 947 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + input_len); 948 949 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 950 V_CPL_TX_SEC_PDU_AADSTART(aad_start) | 951 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) | 952 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) | 953 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(cipher_stop >> 4)); 954 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 955 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(cipher_stop & 0xf) | 956 V_CPL_TX_SEC_PDU_AUTHSTART(auth_start) | 957 V_CPL_TX_SEC_PDU_AUTHSTOP(auth_stop) | 958 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert)); 959 960 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 961 hmac_ctrl = ccr_hmac_ctrl(axf->hashsize, hash_size_in_response); 962 crwr->sec_cpl.seqno_numivs = htobe32( 963 V_SCMD_SEQ_NO_CTRL(0) | 964 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 965 V_SCMD_ENC_DEC_CTRL(op_type) | 966 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) | 967 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) | 968 V_SCMD_AUTH_MODE(s->hmac.auth_mode) | 969 V_SCMD_HMAC_CTRL(hmac_ctrl) | 970 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) | 971 V_SCMD_NUM_IVS(0)); 972 crwr->sec_cpl.ivgen_hdrlen = htobe32( 973 V_SCMD_IV_GEN_CTRL(0) | 974 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 975 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len)); 976 977 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 978 switch (crde->crd_alg) { 979 case CRYPTO_AES_CBC: 980 if (crde->crd_flags & CRD_F_ENCRYPT) 981 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 982 s->blkcipher.key_len); 983 else 984 memcpy(crwr->key_ctx.key, s->blkcipher.deckey, 985 s->blkcipher.key_len); 986 break; 987 case CRYPTO_AES_ICM: 988 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 989 s->blkcipher.key_len); 990 break; 991 case CRYPTO_AES_XTS: 992 key_half = s->blkcipher.key_len / 2; 993 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half, 994 key_half); 995 if (crde->crd_flags & CRD_F_ENCRYPT) 996 memcpy(crwr->key_ctx.key + key_half, 997 s->blkcipher.enckey, key_half); 998 else 999 memcpy(crwr->key_ctx.key + key_half, 1000 s->blkcipher.deckey, key_half); 1001 break; 1002 } 1003 1004 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16); 1005 memcpy(dst, s->hmac.ipad, s->hmac.partial_digest_len); 1006 memcpy(dst + iopad_size, s->hmac.opad, s->hmac.partial_digest_len); 1007 1008 dst = (char *)(crwr + 1) + kctx_len; 1009 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 1010 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 1011 if (iv_loc == IV_IMMEDIATE) { 1012 memcpy(dst, iv, s->blkcipher.iv_len); 1013 dst += s->blkcipher.iv_len; 1014 } 1015 if (imm_len != 0) { 1016 if (aad_len != 0) { 1017 crypto_copydata(crp->crp_flags, crp->crp_buf, 1018 crda->crd_skip, aad_len, dst); 1019 dst += aad_len; 1020 } 1021 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip, 1022 crde->crd_len, dst); 1023 dst += crde->crd_len; 1024 if (op_type == CHCR_DECRYPT_OP) 1025 crypto_copydata(crp->crp_flags, crp->crp_buf, 1026 crda->crd_inject, hash_size_in_response, dst); 1027 } else 1028 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 1029 1030 /* XXX: TODO backpressure */ 1031 t4_wrq_tx(sc->adapter, wr); 1032 1033 return (0); 1034 } 1035 1036 static int 1037 ccr_authenc_done(struct ccr_softc *sc, struct ccr_session *s, 1038 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 1039 { 1040 struct cryptodesc *crd; 1041 1042 /* 1043 * The updated IV to permit chained requests is at 1044 * cpl->data[2], but OCF doesn't permit chained requests. 1045 * 1046 * For a decryption request, the hardware may do a verification 1047 * of the HMAC which will fail if the existing HMAC isn't in the 1048 * buffer. If that happens, clear the error and copy the HMAC 1049 * from the CPL reply into the buffer. 1050 * 1051 * For encryption requests, crd should be the cipher request 1052 * which will have CRD_F_ENCRYPT set. For decryption 1053 * requests, crp_desc will be the HMAC request which should 1054 * not have this flag set. 1055 */ 1056 crd = crp->crp_desc; 1057 if (error == EBADMSG && !CHK_PAD_ERR_BIT(be64toh(cpl->data[0])) && 1058 !(crd->crd_flags & CRD_F_ENCRYPT)) { 1059 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 1060 s->hmac.hash_len, (c_caddr_t)(cpl + 1)); 1061 error = 0; 1062 } 1063 return (error); 1064 } 1065 1066 static int 1067 ccr_gcm(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 1068 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde) 1069 { 1070 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 1071 struct chcr_wr *crwr; 1072 struct wrqe *wr; 1073 char *dst; 1074 u_int iv_len, iv_loc, kctx_len, op_type, transhdr_len, wr_len; 1075 u_int hash_size_in_response, imm_len; 1076 u_int aad_start, aad_stop, cipher_start, cipher_stop, auth_insert; 1077 u_int hmac_ctrl, input_len; 1078 int dsgl_nsegs, dsgl_len; 1079 int sgl_nsegs, sgl_len; 1080 int error; 1081 1082 if (s->blkcipher.key_len == 0) 1083 return (EINVAL); 1084 1085 /* 1086 * AAD is only permitted before the cipher/plain text, not 1087 * after. 1088 */ 1089 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip) 1090 return (EINVAL); 1091 1092 hash_size_in_response = s->gmac.hash_len; 1093 1094 /* 1095 * The IV is always stored at the start of the buffer even 1096 * though it may be duplicated in the payload. The crypto 1097 * engine doesn't work properly if the IV offset points inside 1098 * of the AAD region, so a second copy is always required. 1099 * 1100 * The IV for GCM is further complicated in that IPSec 1101 * provides a full 16-byte IV (including the counter), whereas 1102 * the /dev/crypto interface sometimes provides a full 16-byte 1103 * IV (if no IV is provided in the ioctl) and sometimes a 1104 * 12-byte IV (if the IV was explicit). For now the driver 1105 * always assumes a 12-byte IV and initializes the low 4 byte 1106 * counter to 1. 1107 */ 1108 iv_loc = IV_IMMEDIATE; 1109 if (crde->crd_flags & CRD_F_ENCRYPT) { 1110 op_type = CHCR_ENCRYPT_OP; 1111 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1112 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 1113 else 1114 arc4rand(iv, s->blkcipher.iv_len, 0); 1115 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0) 1116 crypto_copyback(crp->crp_flags, crp->crp_buf, 1117 crde->crd_inject, s->blkcipher.iv_len, iv); 1118 } else { 1119 op_type = CHCR_DECRYPT_OP; 1120 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1121 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 1122 else 1123 crypto_copydata(crp->crp_flags, crp->crp_buf, 1124 crde->crd_inject, s->blkcipher.iv_len, iv); 1125 } 1126 1127 /* 1128 * If the input IV is 12 bytes, append an explicit counter of 1129 * 1. 1130 */ 1131 if (s->blkcipher.iv_len == 12) { 1132 *(uint32_t *)&iv[12] = htobe32(1); 1133 iv_len = AES_BLOCK_LEN; 1134 } else 1135 iv_len = s->blkcipher.iv_len; 1136 1137 /* 1138 * The output buffer consists of the cipher text followed by 1139 * the tag when encrypting. For decryption it only contains 1140 * the plain text. 1141 */ 1142 if (op_type == CHCR_ENCRYPT_OP) { 1143 if (crde->crd_len + hash_size_in_response > MAX_REQUEST_SIZE) 1144 return (EFBIG); 1145 } else { 1146 if (crde->crd_len > MAX_REQUEST_SIZE) 1147 return (EFBIG); 1148 } 1149 sglist_reset(sc->sg_dsgl); 1150 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip, 1151 crde->crd_len); 1152 if (error) 1153 return (error); 1154 if (op_type == CHCR_ENCRYPT_OP) { 1155 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, 1156 crda->crd_inject, hash_size_in_response); 1157 if (error) 1158 return (error); 1159 } 1160 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 1161 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 1162 return (EFBIG); 1163 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 1164 1165 /* 1166 * The 'key' part of the key context consists of the key followed 1167 * by the Galois hash key. 1168 */ 1169 kctx_len = roundup2(s->blkcipher.key_len, 16) + GMAC_BLOCK_LEN; 1170 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 1171 1172 /* 1173 * The input buffer consists of the IV, any AAD, and then the 1174 * cipher/plain text. For decryption requests the hash is 1175 * appended after the cipher text. 1176 */ 1177 input_len = crda->crd_len + crde->crd_len; 1178 if (op_type == CHCR_DECRYPT_OP) 1179 input_len += hash_size_in_response; 1180 if (input_len > MAX_REQUEST_SIZE) 1181 return (EFBIG); 1182 if (ccr_use_imm_data(transhdr_len, iv_len + input_len)) { 1183 imm_len = input_len; 1184 sgl_nsegs = 0; 1185 sgl_len = 0; 1186 } else { 1187 imm_len = 0; 1188 sglist_reset(sc->sg_ulptx); 1189 if (crda->crd_len != 0) { 1190 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1191 crda->crd_skip, crda->crd_len); 1192 if (error) 1193 return (error); 1194 } 1195 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1196 crde->crd_skip, crde->crd_len); 1197 if (error) 1198 return (error); 1199 if (op_type == CHCR_DECRYPT_OP) { 1200 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1201 crda->crd_inject, hash_size_in_response); 1202 if (error) 1203 return (error); 1204 } 1205 sgl_nsegs = sc->sg_ulptx->sg_nseg; 1206 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 1207 } 1208 1209 if (crda->crd_len != 0) { 1210 aad_start = iv_len + 1; 1211 aad_stop = aad_start + crda->crd_len - 1; 1212 } else { 1213 aad_start = 0; 1214 aad_stop = 0; 1215 } 1216 cipher_start = iv_len + crda->crd_len + 1; 1217 if (op_type == CHCR_DECRYPT_OP) 1218 cipher_stop = hash_size_in_response; 1219 else 1220 cipher_stop = 0; 1221 if (op_type == CHCR_DECRYPT_OP) 1222 auth_insert = hash_size_in_response; 1223 else 1224 auth_insert = 0; 1225 1226 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 1227 if (iv_loc == IV_IMMEDIATE) 1228 wr_len += iv_len; 1229 wr = alloc_wrqe(wr_len, sc->txq); 1230 if (wr == NULL) { 1231 sc->stats_wr_nomem++; 1232 return (ENOMEM); 1233 } 1234 crwr = wrtod(wr); 1235 memset(crwr, 0, wr_len); 1236 1237 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 1238 0, iv_loc, crp); 1239 1240 /* XXX: Hardcodes SGE loopback channel of 0. */ 1241 crwr->sec_cpl.op_ivinsrtofst = htobe32( 1242 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 1243 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 1244 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 1245 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 1246 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 1247 1248 crwr->sec_cpl.pldlen = htobe32(iv_len + input_len); 1249 1250 /* 1251 * NB: cipherstop is explicitly set to 0. On encrypt it 1252 * should normally be set to 0 anyway (as the encrypt crd ends 1253 * at the end of the input). However, for decrypt the cipher 1254 * ends before the tag in the AUTHENC case (and authstop is 1255 * set to stop before the tag), but for GCM the cipher still 1256 * runs to the end of the buffer. Not sure if this is 1257 * intentional or a firmware quirk, but it is required for 1258 * working tag validation with GCM decryption. 1259 */ 1260 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 1261 V_CPL_TX_SEC_PDU_AADSTART(aad_start) | 1262 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) | 1263 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) | 1264 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0)); 1265 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 1266 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0) | 1267 V_CPL_TX_SEC_PDU_AUTHSTART(cipher_start) | 1268 V_CPL_TX_SEC_PDU_AUTHSTOP(cipher_stop) | 1269 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert)); 1270 1271 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 1272 hmac_ctrl = ccr_hmac_ctrl(AES_GMAC_HASH_LEN, hash_size_in_response); 1273 crwr->sec_cpl.seqno_numivs = htobe32( 1274 V_SCMD_SEQ_NO_CTRL(0) | 1275 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 1276 V_SCMD_ENC_DEC_CTRL(op_type) | 1277 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) | 1278 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_AES_GCM) | 1279 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_GHASH) | 1280 V_SCMD_HMAC_CTRL(hmac_ctrl) | 1281 V_SCMD_IV_SIZE(iv_len / 2) | 1282 V_SCMD_NUM_IVS(0)); 1283 crwr->sec_cpl.ivgen_hdrlen = htobe32( 1284 V_SCMD_IV_GEN_CTRL(0) | 1285 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 1286 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len)); 1287 1288 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 1289 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, s->blkcipher.key_len); 1290 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16); 1291 memcpy(dst, s->gmac.ghash_h, GMAC_BLOCK_LEN); 1292 1293 dst = (char *)(crwr + 1) + kctx_len; 1294 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 1295 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 1296 if (iv_loc == IV_IMMEDIATE) { 1297 memcpy(dst, iv, iv_len); 1298 dst += iv_len; 1299 } 1300 if (imm_len != 0) { 1301 if (crda->crd_len != 0) { 1302 crypto_copydata(crp->crp_flags, crp->crp_buf, 1303 crda->crd_skip, crda->crd_len, dst); 1304 dst += crda->crd_len; 1305 } 1306 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip, 1307 crde->crd_len, dst); 1308 dst += crde->crd_len; 1309 if (op_type == CHCR_DECRYPT_OP) 1310 crypto_copydata(crp->crp_flags, crp->crp_buf, 1311 crda->crd_inject, hash_size_in_response, dst); 1312 } else 1313 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 1314 1315 /* XXX: TODO backpressure */ 1316 t4_wrq_tx(sc->adapter, wr); 1317 1318 return (0); 1319 } 1320 1321 static int 1322 ccr_gcm_done(struct ccr_softc *sc, struct ccr_session *s, 1323 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 1324 { 1325 1326 /* 1327 * The updated IV to permit chained requests is at 1328 * cpl->data[2], but OCF doesn't permit chained requests. 1329 * 1330 * Note that the hardware should always verify the GMAC hash. 1331 */ 1332 return (error); 1333 } 1334 1335 static void 1336 ccr_identify(driver_t *driver, device_t parent) 1337 { 1338 struct adapter *sc; 1339 1340 sc = device_get_softc(parent); 1341 if (sc->cryptocaps & FW_CAPS_CONFIG_CRYPTO_LOOKASIDE && 1342 device_find_child(parent, "ccr", -1) == NULL) 1343 device_add_child(parent, "ccr", -1); 1344 } 1345 1346 static int 1347 ccr_probe(device_t dev) 1348 { 1349 1350 device_set_desc(dev, "Chelsio Crypto Accelerator"); 1351 return (BUS_PROBE_DEFAULT); 1352 } 1353 1354 static void 1355 ccr_sysctls(struct ccr_softc *sc) 1356 { 1357 struct sysctl_ctx_list *ctx; 1358 struct sysctl_oid *oid; 1359 struct sysctl_oid_list *children; 1360 1361 ctx = device_get_sysctl_ctx(sc->dev); 1362 1363 /* 1364 * dev.ccr.X. 1365 */ 1366 oid = device_get_sysctl_tree(sc->dev); 1367 children = SYSCTL_CHILDREN(oid); 1368 1369 /* 1370 * dev.ccr.X.stats. 1371 */ 1372 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 1373 NULL, "statistics"); 1374 children = SYSCTL_CHILDREN(oid); 1375 1376 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "hmac", CTLFLAG_RD, 1377 &sc->stats_hmac, 0, "HMAC requests submitted"); 1378 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_encrypt", CTLFLAG_RD, 1379 &sc->stats_blkcipher_encrypt, 0, 1380 "Cipher encryption requests submitted"); 1381 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_decrypt", CTLFLAG_RD, 1382 &sc->stats_blkcipher_decrypt, 0, 1383 "Cipher decryption requests submitted"); 1384 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_encrypt", CTLFLAG_RD, 1385 &sc->stats_authenc_encrypt, 0, 1386 "Combined AES+HMAC encryption requests submitted"); 1387 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_decrypt", CTLFLAG_RD, 1388 &sc->stats_authenc_decrypt, 0, 1389 "Combined AES+HMAC decryption requests submitted"); 1390 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_encrypt", CTLFLAG_RD, 1391 &sc->stats_gcm_encrypt, 0, "AES-GCM encryption requests submitted"); 1392 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_decrypt", CTLFLAG_RD, 1393 &sc->stats_gcm_decrypt, 0, "AES-GCM decryption requests submitted"); 1394 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "wr_nomem", CTLFLAG_RD, 1395 &sc->stats_wr_nomem, 0, "Work request memory allocation failures"); 1396 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "inflight", CTLFLAG_RD, 1397 &sc->stats_inflight, 0, "Requests currently pending"); 1398 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "mac_error", CTLFLAG_RD, 1399 &sc->stats_mac_error, 0, "MAC errors"); 1400 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "pad_error", CTLFLAG_RD, 1401 &sc->stats_pad_error, 0, "Padding errors"); 1402 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "bad_session", CTLFLAG_RD, 1403 &sc->stats_pad_error, 0, "Requests with invalid session ID"); 1404 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "sglist_error", CTLFLAG_RD, 1405 &sc->stats_pad_error, 0, "Requests for which DMA mapping failed"); 1406 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "process_error", CTLFLAG_RD, 1407 &sc->stats_pad_error, 0, "Requests failed during queueing"); 1408 } 1409 1410 static int 1411 ccr_attach(device_t dev) 1412 { 1413 struct ccr_softc *sc; 1414 int32_t cid; 1415 1416 /* 1417 * TODO: Crypto requests will panic if the parent device isn't 1418 * initialized so that the queues are up and running. Need to 1419 * figure out how to handle that correctly, maybe just reject 1420 * requests if the adapter isn't fully initialized? 1421 */ 1422 sc = device_get_softc(dev); 1423 sc->dev = dev; 1424 sc->adapter = device_get_softc(device_get_parent(dev)); 1425 sc->txq = &sc->adapter->sge.ctrlq[0]; 1426 sc->rxq = &sc->adapter->sge.rxq[0]; 1427 cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 1428 if (cid < 0) { 1429 device_printf(dev, "could not get crypto driver id\n"); 1430 return (ENXIO); 1431 } 1432 sc->cid = cid; 1433 sc->adapter->ccr_softc = sc; 1434 1435 /* XXX: TODO? */ 1436 sc->tx_channel_id = 0; 1437 1438 mtx_init(&sc->lock, "ccr", NULL, MTX_DEF); 1439 sc->sg_crp = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 1440 sc->sg_ulptx = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 1441 sc->sg_dsgl = sglist_alloc(MAX_RX_PHYS_DSGL_SGE, M_WAITOK); 1442 ccr_sysctls(sc); 1443 1444 crypto_register(cid, CRYPTO_SHA1_HMAC, 0, 0); 1445 crypto_register(cid, CRYPTO_SHA2_256_HMAC, 0, 0); 1446 crypto_register(cid, CRYPTO_SHA2_384_HMAC, 0, 0); 1447 crypto_register(cid, CRYPTO_SHA2_512_HMAC, 0, 0); 1448 crypto_register(cid, CRYPTO_AES_CBC, 0, 0); 1449 crypto_register(cid, CRYPTO_AES_ICM, 0, 0); 1450 crypto_register(cid, CRYPTO_AES_NIST_GCM_16, 0, 0); 1451 crypto_register(cid, CRYPTO_AES_128_NIST_GMAC, 0, 0); 1452 crypto_register(cid, CRYPTO_AES_192_NIST_GMAC, 0, 0); 1453 crypto_register(cid, CRYPTO_AES_256_NIST_GMAC, 0, 0); 1454 crypto_register(cid, CRYPTO_AES_XTS, 0, 0); 1455 return (0); 1456 } 1457 1458 static int 1459 ccr_detach(device_t dev) 1460 { 1461 struct ccr_softc *sc; 1462 int i; 1463 1464 sc = device_get_softc(dev); 1465 1466 mtx_lock(&sc->lock); 1467 for (i = 0; i < sc->nsessions; i++) { 1468 if (sc->sessions[i].active || sc->sessions[i].pending != 0) { 1469 mtx_unlock(&sc->lock); 1470 return (EBUSY); 1471 } 1472 } 1473 sc->detaching = true; 1474 mtx_unlock(&sc->lock); 1475 1476 crypto_unregister_all(sc->cid); 1477 free(sc->sessions, M_CCR); 1478 mtx_destroy(&sc->lock); 1479 sglist_free(sc->sg_dsgl); 1480 sglist_free(sc->sg_ulptx); 1481 sglist_free(sc->sg_crp); 1482 sc->adapter->ccr_softc = NULL; 1483 return (0); 1484 } 1485 1486 static void 1487 ccr_copy_partial_hash(void *dst, int cri_alg, union authctx *auth_ctx) 1488 { 1489 uint32_t *u32; 1490 uint64_t *u64; 1491 u_int i; 1492 1493 u32 = (uint32_t *)dst; 1494 u64 = (uint64_t *)dst; 1495 switch (cri_alg) { 1496 case CRYPTO_SHA1_HMAC: 1497 for (i = 0; i < SHA1_HASH_LEN / 4; i++) 1498 u32[i] = htobe32(auth_ctx->sha1ctx.h.b32[i]); 1499 break; 1500 case CRYPTO_SHA2_256_HMAC: 1501 for (i = 0; i < SHA2_256_HASH_LEN / 4; i++) 1502 u32[i] = htobe32(auth_ctx->sha256ctx.state[i]); 1503 break; 1504 case CRYPTO_SHA2_384_HMAC: 1505 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++) 1506 u64[i] = htobe64(auth_ctx->sha384ctx.state[i]); 1507 break; 1508 case CRYPTO_SHA2_512_HMAC: 1509 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++) 1510 u64[i] = htobe64(auth_ctx->sha512ctx.state[i]); 1511 break; 1512 } 1513 } 1514 1515 static void 1516 ccr_init_hmac_digest(struct ccr_session *s, int cri_alg, char *key, 1517 int klen) 1518 { 1519 union authctx auth_ctx; 1520 struct auth_hash *axf; 1521 u_int i; 1522 1523 /* 1524 * If the key is larger than the block size, use the digest of 1525 * the key as the key instead. 1526 */ 1527 axf = s->hmac.auth_hash; 1528 klen /= 8; 1529 if (klen > axf->blocksize) { 1530 axf->Init(&auth_ctx); 1531 axf->Update(&auth_ctx, key, klen); 1532 axf->Final(s->hmac.ipad, &auth_ctx); 1533 klen = axf->hashsize; 1534 } else 1535 memcpy(s->hmac.ipad, key, klen); 1536 1537 memset(s->hmac.ipad + klen, 0, axf->blocksize); 1538 memcpy(s->hmac.opad, s->hmac.ipad, axf->blocksize); 1539 1540 for (i = 0; i < axf->blocksize; i++) { 1541 s->hmac.ipad[i] ^= HMAC_IPAD_VAL; 1542 s->hmac.opad[i] ^= HMAC_OPAD_VAL; 1543 } 1544 1545 /* 1546 * Hash the raw ipad and opad and store the partial result in 1547 * the same buffer. 1548 */ 1549 axf->Init(&auth_ctx); 1550 axf->Update(&auth_ctx, s->hmac.ipad, axf->blocksize); 1551 ccr_copy_partial_hash(s->hmac.ipad, cri_alg, &auth_ctx); 1552 1553 axf->Init(&auth_ctx); 1554 axf->Update(&auth_ctx, s->hmac.opad, axf->blocksize); 1555 ccr_copy_partial_hash(s->hmac.opad, cri_alg, &auth_ctx); 1556 } 1557 1558 /* 1559 * Borrowed from AES_GMAC_Setkey(). 1560 */ 1561 static void 1562 ccr_init_gmac_hash(struct ccr_session *s, char *key, int klen) 1563 { 1564 static char zeroes[GMAC_BLOCK_LEN]; 1565 uint32_t keysched[4 * (RIJNDAEL_MAXNR + 1)]; 1566 int rounds; 1567 1568 rounds = rijndaelKeySetupEnc(keysched, key, klen); 1569 rijndaelEncrypt(keysched, rounds, zeroes, s->gmac.ghash_h); 1570 } 1571 1572 static int 1573 ccr_aes_check_keylen(int alg, int klen) 1574 { 1575 1576 switch (klen) { 1577 case 128: 1578 case 192: 1579 if (alg == CRYPTO_AES_XTS) 1580 return (EINVAL); 1581 break; 1582 case 256: 1583 break; 1584 case 512: 1585 if (alg != CRYPTO_AES_XTS) 1586 return (EINVAL); 1587 break; 1588 default: 1589 return (EINVAL); 1590 } 1591 return (0); 1592 } 1593 1594 /* 1595 * Borrowed from cesa_prep_aes_key(). We should perhaps have a public 1596 * function to generate this instead. 1597 * 1598 * NB: The crypto engine wants the words in the decryption key in reverse 1599 * order. 1600 */ 1601 static void 1602 ccr_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 1603 { 1604 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 1605 uint32_t *dkey; 1606 int i; 1607 1608 rijndaelKeySetupEnc(ek, enc_key, kbits); 1609 dkey = dec_key; 1610 dkey += (kbits / 8) / 4; 1611 1612 switch (kbits) { 1613 case 128: 1614 for (i = 0; i < 4; i++) 1615 *--dkey = htobe32(ek[4 * 10 + i]); 1616 break; 1617 case 192: 1618 for (i = 0; i < 2; i++) 1619 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 1620 for (i = 0; i < 4; i++) 1621 *--dkey = htobe32(ek[4 * 12 + i]); 1622 break; 1623 case 256: 1624 for (i = 0; i < 4; i++) 1625 *--dkey = htobe32(ek[4 * 13 + i]); 1626 for (i = 0; i < 4; i++) 1627 *--dkey = htobe32(ek[4 * 14 + i]); 1628 break; 1629 } 1630 MPASS(dkey == dec_key); 1631 } 1632 1633 static void 1634 ccr_aes_setkey(struct ccr_session *s, int alg, const void *key, int klen) 1635 { 1636 unsigned int ck_size, iopad_size, kctx_flits, kctx_len, kbits, mk_size; 1637 unsigned int opad_present; 1638 1639 if (alg == CRYPTO_AES_XTS) 1640 kbits = klen / 2; 1641 else 1642 kbits = klen; 1643 switch (kbits) { 1644 case 128: 1645 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128; 1646 break; 1647 case 192: 1648 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192; 1649 break; 1650 case 256: 1651 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256; 1652 break; 1653 default: 1654 panic("should not get here"); 1655 } 1656 1657 s->blkcipher.key_len = klen / 8; 1658 memcpy(s->blkcipher.enckey, key, s->blkcipher.key_len); 1659 switch (alg) { 1660 case CRYPTO_AES_CBC: 1661 case CRYPTO_AES_XTS: 1662 ccr_aes_getdeckey(s->blkcipher.deckey, key, kbits); 1663 break; 1664 } 1665 1666 kctx_len = roundup2(s->blkcipher.key_len, 16); 1667 switch (s->mode) { 1668 case AUTHENC: 1669 mk_size = s->hmac.mk_size; 1670 opad_present = 1; 1671 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 1672 kctx_len += iopad_size * 2; 1673 break; 1674 case GCM: 1675 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128; 1676 opad_present = 0; 1677 kctx_len += GMAC_BLOCK_LEN; 1678 break; 1679 default: 1680 mk_size = CHCR_KEYCTX_NO_KEY; 1681 opad_present = 0; 1682 break; 1683 } 1684 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16; 1685 s->blkcipher.key_ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) | 1686 V_KEY_CONTEXT_DUAL_CK(alg == CRYPTO_AES_XTS) | 1687 V_KEY_CONTEXT_OPAD_PRESENT(opad_present) | 1688 V_KEY_CONTEXT_SALT_PRESENT(1) | V_KEY_CONTEXT_CK_SIZE(ck_size) | 1689 V_KEY_CONTEXT_MK_SIZE(mk_size) | V_KEY_CONTEXT_VALID(1)); 1690 } 1691 1692 static int 1693 ccr_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri) 1694 { 1695 struct ccr_softc *sc; 1696 struct ccr_session *s; 1697 struct auth_hash *auth_hash; 1698 struct cryptoini *c, *hash, *cipher; 1699 unsigned int auth_mode, cipher_mode, iv_len, mk_size; 1700 unsigned int partial_digest_len; 1701 int error, i, sess; 1702 bool gcm_hash; 1703 1704 if (sidp == NULL || cri == NULL) 1705 return (EINVAL); 1706 1707 gcm_hash = false; 1708 cipher = NULL; 1709 hash = NULL; 1710 auth_hash = NULL; 1711 auth_mode = CHCR_SCMD_AUTH_MODE_NOP; 1712 cipher_mode = CHCR_SCMD_CIPHER_MODE_NOP; 1713 iv_len = 0; 1714 mk_size = 0; 1715 partial_digest_len = 0; 1716 for (c = cri; c != NULL; c = c->cri_next) { 1717 switch (c->cri_alg) { 1718 case CRYPTO_SHA1_HMAC: 1719 case CRYPTO_SHA2_256_HMAC: 1720 case CRYPTO_SHA2_384_HMAC: 1721 case CRYPTO_SHA2_512_HMAC: 1722 case CRYPTO_AES_128_NIST_GMAC: 1723 case CRYPTO_AES_192_NIST_GMAC: 1724 case CRYPTO_AES_256_NIST_GMAC: 1725 if (hash) 1726 return (EINVAL); 1727 hash = c; 1728 switch (c->cri_alg) { 1729 case CRYPTO_SHA1_HMAC: 1730 auth_hash = &auth_hash_hmac_sha1; 1731 auth_mode = CHCR_SCMD_AUTH_MODE_SHA1; 1732 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_160; 1733 partial_digest_len = SHA1_HASH_LEN; 1734 break; 1735 case CRYPTO_SHA2_256_HMAC: 1736 auth_hash = &auth_hash_hmac_sha2_256; 1737 auth_mode = CHCR_SCMD_AUTH_MODE_SHA256; 1738 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256; 1739 partial_digest_len = SHA2_256_HASH_LEN; 1740 break; 1741 case CRYPTO_SHA2_384_HMAC: 1742 auth_hash = &auth_hash_hmac_sha2_384; 1743 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_384; 1744 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512; 1745 partial_digest_len = SHA2_512_HASH_LEN; 1746 break; 1747 case CRYPTO_SHA2_512_HMAC: 1748 auth_hash = &auth_hash_hmac_sha2_512; 1749 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_512; 1750 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512; 1751 partial_digest_len = SHA2_512_HASH_LEN; 1752 break; 1753 case CRYPTO_AES_128_NIST_GMAC: 1754 case CRYPTO_AES_192_NIST_GMAC: 1755 case CRYPTO_AES_256_NIST_GMAC: 1756 gcm_hash = true; 1757 auth_mode = CHCR_SCMD_AUTH_MODE_GHASH; 1758 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128; 1759 break; 1760 } 1761 break; 1762 case CRYPTO_AES_CBC: 1763 case CRYPTO_AES_ICM: 1764 case CRYPTO_AES_NIST_GCM_16: 1765 case CRYPTO_AES_XTS: 1766 if (cipher) 1767 return (EINVAL); 1768 cipher = c; 1769 switch (c->cri_alg) { 1770 case CRYPTO_AES_CBC: 1771 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CBC; 1772 iv_len = AES_BLOCK_LEN; 1773 break; 1774 case CRYPTO_AES_ICM: 1775 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CTR; 1776 iv_len = AES_BLOCK_LEN; 1777 break; 1778 case CRYPTO_AES_NIST_GCM_16: 1779 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_GCM; 1780 iv_len = AES_GCM_IV_LEN; 1781 break; 1782 case CRYPTO_AES_XTS: 1783 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_XTS; 1784 iv_len = AES_BLOCK_LEN; 1785 break; 1786 } 1787 if (c->cri_key != NULL) { 1788 error = ccr_aes_check_keylen(c->cri_alg, 1789 c->cri_klen); 1790 if (error) 1791 return (error); 1792 } 1793 break; 1794 default: 1795 return (EINVAL); 1796 } 1797 } 1798 if (gcm_hash != (cipher_mode == CHCR_SCMD_CIPHER_MODE_AES_GCM)) 1799 return (EINVAL); 1800 if (hash == NULL && cipher == NULL) 1801 return (EINVAL); 1802 if (hash != NULL && hash->cri_key == NULL) 1803 return (EINVAL); 1804 1805 sc = device_get_softc(dev); 1806 mtx_lock(&sc->lock); 1807 if (sc->detaching) { 1808 mtx_unlock(&sc->lock); 1809 return (ENXIO); 1810 } 1811 sess = -1; 1812 for (i = 0; i < sc->nsessions; i++) { 1813 if (!sc->sessions[i].active && sc->sessions[i].pending == 0) { 1814 sess = i; 1815 break; 1816 } 1817 } 1818 if (sess == -1) { 1819 s = malloc(sizeof(*s) * (sc->nsessions + 1), M_CCR, 1820 M_NOWAIT | M_ZERO); 1821 if (s == NULL) { 1822 mtx_unlock(&sc->lock); 1823 return (ENOMEM); 1824 } 1825 if (sc->sessions != NULL) 1826 memcpy(s, sc->sessions, sizeof(*s) * sc->nsessions); 1827 sess = sc->nsessions; 1828 free(sc->sessions, M_CCR); 1829 sc->sessions = s; 1830 sc->nsessions++; 1831 } 1832 1833 s = &sc->sessions[sess]; 1834 1835 if (gcm_hash) 1836 s->mode = GCM; 1837 else if (hash != NULL && cipher != NULL) 1838 s->mode = AUTHENC; 1839 else if (hash != NULL) 1840 s->mode = HMAC; 1841 else { 1842 MPASS(cipher != NULL); 1843 s->mode = BLKCIPHER; 1844 } 1845 if (gcm_hash) { 1846 if (hash->cri_mlen == 0) 1847 s->gmac.hash_len = AES_GMAC_HASH_LEN; 1848 else 1849 s->gmac.hash_len = hash->cri_mlen; 1850 ccr_init_gmac_hash(s, hash->cri_key, hash->cri_klen); 1851 } else if (hash != NULL) { 1852 s->hmac.auth_hash = auth_hash; 1853 s->hmac.auth_mode = auth_mode; 1854 s->hmac.mk_size = mk_size; 1855 s->hmac.partial_digest_len = partial_digest_len; 1856 if (hash->cri_mlen == 0) 1857 s->hmac.hash_len = auth_hash->hashsize; 1858 else 1859 s->hmac.hash_len = hash->cri_mlen; 1860 ccr_init_hmac_digest(s, hash->cri_alg, hash->cri_key, 1861 hash->cri_klen); 1862 } 1863 if (cipher != NULL) { 1864 s->blkcipher.cipher_mode = cipher_mode; 1865 s->blkcipher.iv_len = iv_len; 1866 if (cipher->cri_key != NULL) 1867 ccr_aes_setkey(s, cipher->cri_alg, cipher->cri_key, 1868 cipher->cri_klen); 1869 } 1870 1871 s->active = true; 1872 mtx_unlock(&sc->lock); 1873 1874 *sidp = sess; 1875 return (0); 1876 } 1877 1878 static int 1879 ccr_freesession(device_t dev, uint64_t tid) 1880 { 1881 struct ccr_softc *sc; 1882 uint32_t sid; 1883 int error; 1884 1885 sc = device_get_softc(dev); 1886 sid = CRYPTO_SESID2LID(tid); 1887 mtx_lock(&sc->lock); 1888 if (sid >= sc->nsessions || !sc->sessions[sid].active) 1889 error = EINVAL; 1890 else { 1891 if (sc->sessions[sid].pending != 0) 1892 device_printf(dev, 1893 "session %d freed with %d pending requests\n", sid, 1894 sc->sessions[sid].pending); 1895 sc->sessions[sid].active = false; 1896 error = 0; 1897 } 1898 mtx_unlock(&sc->lock); 1899 return (error); 1900 } 1901 1902 static int 1903 ccr_process(device_t dev, struct cryptop *crp, int hint) 1904 { 1905 struct ccr_softc *sc; 1906 struct ccr_session *s; 1907 struct cryptodesc *crd, *crda, *crde; 1908 uint32_t sid; 1909 int error; 1910 1911 if (crp == NULL) 1912 return (EINVAL); 1913 1914 crd = crp->crp_desc; 1915 sid = CRYPTO_SESID2LID(crp->crp_sid); 1916 sc = device_get_softc(dev); 1917 mtx_lock(&sc->lock); 1918 if (sid >= sc->nsessions || !sc->sessions[sid].active) { 1919 sc->stats_bad_session++; 1920 error = EINVAL; 1921 goto out; 1922 } 1923 1924 error = ccr_populate_sglist(sc->sg_crp, crp); 1925 if (error) { 1926 sc->stats_sglist_error++; 1927 goto out; 1928 } 1929 1930 s = &sc->sessions[sid]; 1931 switch (s->mode) { 1932 case HMAC: 1933 if (crd->crd_flags & CRD_F_KEY_EXPLICIT) 1934 ccr_init_hmac_digest(s, crd->crd_alg, crd->crd_key, 1935 crd->crd_klen); 1936 error = ccr_hmac(sc, sid, s, crp); 1937 if (error == 0) 1938 sc->stats_hmac++; 1939 break; 1940 case BLKCIPHER: 1941 if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { 1942 error = ccr_aes_check_keylen(crd->crd_alg, 1943 crd->crd_klen); 1944 if (error) 1945 break; 1946 ccr_aes_setkey(s, crd->crd_alg, crd->crd_key, 1947 crd->crd_klen); 1948 } 1949 error = ccr_blkcipher(sc, sid, s, crp); 1950 if (error == 0) { 1951 if (crd->crd_flags & CRD_F_ENCRYPT) 1952 sc->stats_blkcipher_encrypt++; 1953 else 1954 sc->stats_blkcipher_decrypt++; 1955 } 1956 break; 1957 case AUTHENC: 1958 error = 0; 1959 switch (crd->crd_alg) { 1960 case CRYPTO_AES_CBC: 1961 case CRYPTO_AES_ICM: 1962 case CRYPTO_AES_XTS: 1963 /* Only encrypt-then-authenticate supported. */ 1964 crde = crd; 1965 crda = crd->crd_next; 1966 if (!(crde->crd_flags & CRD_F_ENCRYPT)) { 1967 error = EINVAL; 1968 break; 1969 } 1970 break; 1971 default: 1972 crda = crd; 1973 crde = crd->crd_next; 1974 if (crde->crd_flags & CRD_F_ENCRYPT) { 1975 error = EINVAL; 1976 break; 1977 } 1978 break; 1979 } 1980 if (error) 1981 break; 1982 if (crda->crd_flags & CRD_F_KEY_EXPLICIT) 1983 ccr_init_hmac_digest(s, crda->crd_alg, crda->crd_key, 1984 crda->crd_klen); 1985 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) { 1986 error = ccr_aes_check_keylen(crde->crd_alg, 1987 crde->crd_klen); 1988 if (error) 1989 break; 1990 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key, 1991 crde->crd_klen); 1992 } 1993 error = ccr_authenc(sc, sid, s, crp, crda, crde); 1994 if (error == 0) { 1995 if (crde->crd_flags & CRD_F_ENCRYPT) 1996 sc->stats_authenc_encrypt++; 1997 else 1998 sc->stats_authenc_decrypt++; 1999 } 2000 break; 2001 case GCM: 2002 error = 0; 2003 if (crd->crd_alg == CRYPTO_AES_NIST_GCM_16) { 2004 crde = crd; 2005 crda = crd->crd_next; 2006 } else { 2007 crda = crd; 2008 crde = crd->crd_next; 2009 } 2010 if (crda->crd_flags & CRD_F_KEY_EXPLICIT) 2011 ccr_init_gmac_hash(s, crda->crd_key, crda->crd_klen); 2012 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) { 2013 error = ccr_aes_check_keylen(crde->crd_alg, 2014 crde->crd_klen); 2015 if (error) 2016 break; 2017 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key, 2018 crde->crd_klen); 2019 } 2020 error = ccr_gcm(sc, sid, s, crp, crda, crde); 2021 if (error == 0) { 2022 if (crde->crd_flags & CRD_F_ENCRYPT) 2023 sc->stats_gcm_encrypt++; 2024 else 2025 sc->stats_gcm_decrypt++; 2026 } 2027 break; 2028 } 2029 2030 if (error == 0) { 2031 s->pending++; 2032 sc->stats_inflight++; 2033 } else 2034 sc->stats_process_error++; 2035 2036 out: 2037 mtx_unlock(&sc->lock); 2038 2039 if (error) { 2040 crp->crp_etype = error; 2041 crypto_done(crp); 2042 } 2043 2044 return (0); 2045 } 2046 2047 static int 2048 do_cpl6_fw_pld(struct sge_iq *iq, const struct rss_header *rss, 2049 struct mbuf *m) 2050 { 2051 struct ccr_softc *sc = iq->adapter->ccr_softc; 2052 struct ccr_session *s; 2053 const struct cpl_fw6_pld *cpl; 2054 struct cryptop *crp; 2055 uint32_t sid, status; 2056 int error; 2057 2058 if (m != NULL) 2059 cpl = mtod(m, const void *); 2060 else 2061 cpl = (const void *)(rss + 1); 2062 2063 crp = (struct cryptop *)(uintptr_t)be64toh(cpl->data[1]); 2064 sid = CRYPTO_SESID2LID(crp->crp_sid); 2065 status = be64toh(cpl->data[0]); 2066 if (CHK_MAC_ERR_BIT(status) || CHK_PAD_ERR_BIT(status)) 2067 error = EBADMSG; 2068 else 2069 error = 0; 2070 2071 mtx_lock(&sc->lock); 2072 MPASS(sid < sc->nsessions); 2073 s = &sc->sessions[sid]; 2074 s->pending--; 2075 sc->stats_inflight--; 2076 2077 switch (s->mode) { 2078 case HMAC: 2079 error = ccr_hmac_done(sc, s, crp, cpl, error); 2080 break; 2081 case BLKCIPHER: 2082 error = ccr_blkcipher_done(sc, s, crp, cpl, error); 2083 break; 2084 case AUTHENC: 2085 error = ccr_authenc_done(sc, s, crp, cpl, error); 2086 break; 2087 case GCM: 2088 error = ccr_gcm_done(sc, s, crp, cpl, error); 2089 break; 2090 } 2091 2092 if (error == EBADMSG) { 2093 if (CHK_MAC_ERR_BIT(status)) 2094 sc->stats_mac_error++; 2095 if (CHK_PAD_ERR_BIT(status)) 2096 sc->stats_pad_error++; 2097 } 2098 mtx_unlock(&sc->lock); 2099 crp->crp_etype = error; 2100 crypto_done(crp); 2101 m_freem(m); 2102 return (0); 2103 } 2104 2105 static int 2106 ccr_modevent(module_t mod, int cmd, void *arg) 2107 { 2108 2109 switch (cmd) { 2110 case MOD_LOAD: 2111 t4_register_cpl_handler(CPL_FW6_PLD, do_cpl6_fw_pld); 2112 return (0); 2113 case MOD_UNLOAD: 2114 t4_register_cpl_handler(CPL_FW6_PLD, NULL); 2115 return (0); 2116 default: 2117 return (EOPNOTSUPP); 2118 } 2119 } 2120 2121 static device_method_t ccr_methods[] = { 2122 DEVMETHOD(device_identify, ccr_identify), 2123 DEVMETHOD(device_probe, ccr_probe), 2124 DEVMETHOD(device_attach, ccr_attach), 2125 DEVMETHOD(device_detach, ccr_detach), 2126 2127 DEVMETHOD(cryptodev_newsession, ccr_newsession), 2128 DEVMETHOD(cryptodev_freesession, ccr_freesession), 2129 DEVMETHOD(cryptodev_process, ccr_process), 2130 2131 DEVMETHOD_END 2132 }; 2133 2134 static driver_t ccr_driver = { 2135 "ccr", 2136 ccr_methods, 2137 sizeof(struct ccr_softc) 2138 }; 2139 2140 static devclass_t ccr_devclass; 2141 2142 DRIVER_MODULE(ccr, t6nex, ccr_driver, ccr_devclass, ccr_modevent, NULL); 2143 MODULE_VERSION(ccr, 1); 2144 MODULE_DEPEND(ccr, crypto, 1, 1, 1); 2145 MODULE_DEPEND(ccr, t6nex, 1, 1, 1); 2146