1 /*- 2 * Copyright (c) 2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/types.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/malloc.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/sglist.h> 38 39 #include <opencrypto/cryptodev.h> 40 #include <opencrypto/xform.h> 41 42 #include "cryptodev_if.h" 43 44 #include "common/common.h" 45 #include "crypto/t4_crypto.h" 46 47 /* 48 * Requests consist of: 49 * 50 * +-------------------------------+ 51 * | struct fw_crypto_lookaside_wr | 52 * +-------------------------------+ 53 * | struct ulp_txpkt | 54 * +-------------------------------+ 55 * | struct ulptx_idata | 56 * +-------------------------------+ 57 * | struct cpl_tx_sec_pdu | 58 * +-------------------------------+ 59 * | struct cpl_tls_tx_scmd_fmt | 60 * +-------------------------------+ 61 * | key context header | 62 * +-------------------------------+ 63 * | AES key | ----- For requests with AES 64 * +-------------------------------+ - 65 * | IPAD (16-byte aligned) | \ 66 * +-------------------------------+ +---- For requests with HMAC 67 * | OPAD (16-byte aligned) | / 68 * +-------------------------------+ - 69 * | GMAC H | ----- For AES-GCM 70 * +-------------------------------+ - 71 * | struct cpl_rx_phys_dsgl | \ 72 * +-------------------------------+ +---- Destination buffer for 73 * | PHYS_DSGL entries | / non-hash-only requests 74 * +-------------------------------+ - 75 * | 16 dummy bytes | ----- Only for hash-only requests 76 * +-------------------------------+ 77 * | IV | ----- If immediate IV 78 * +-------------------------------+ 79 * | Payload | ----- If immediate Payload 80 * +-------------------------------+ - 81 * | struct ulptx_sgl | \ 82 * +-------------------------------+ +---- If payload via SGL 83 * | SGL entries | / 84 * +-------------------------------+ - 85 * 86 * Note that the key context must be padded to ensure 16-byte alignment. 87 * For HMAC requests, the key consists of the partial hash of the IPAD 88 * followed by the partial hash of the OPAD. 89 * 90 * Replies consist of: 91 * 92 * +-------------------------------+ 93 * | struct cpl_fw6_pld | 94 * +-------------------------------+ 95 * | hash digest | ----- For HMAC request with 96 * +-------------------------------+ 'hash_size' set in work request 97 * 98 * A 32-bit big-endian error status word is supplied in the last 4 99 * bytes of data[0] in the CPL_FW6_PLD message. bit 0 indicates a 100 * "MAC" error and bit 1 indicates a "PAD" error. 101 * 102 * The 64-bit 'cookie' field from the fw_crypto_lookaside_wr message 103 * in the request is returned in data[1] of the CPL_FW6_PLD message. 104 * 105 * For block cipher replies, the updated IV is supplied in data[2] and 106 * data[3] of the CPL_FW6_PLD message. 107 * 108 * For hash replies where the work request set 'hash_size' to request 109 * a copy of the hash in the reply, the hash digest is supplied 110 * immediately following the CPL_FW6_PLD message. 111 */ 112 113 /* 114 * The documentation for CPL_RX_PHYS_DSGL claims a maximum of 32 115 * SG entries. 116 */ 117 #define MAX_RX_PHYS_DSGL_SGE 32 118 #define DSGL_SGE_MAXLEN 65535 119 120 static MALLOC_DEFINE(M_CCR, "ccr", "Chelsio T6 crypto"); 121 122 struct ccr_session_hmac { 123 struct auth_hash *auth_hash; 124 int hash_len; 125 unsigned int partial_digest_len; 126 unsigned int auth_mode; 127 unsigned int mk_size; 128 char ipad[CHCR_HASH_MAX_BLOCK_SIZE_128]; 129 char opad[CHCR_HASH_MAX_BLOCK_SIZE_128]; 130 }; 131 132 struct ccr_session_gmac { 133 int hash_len; 134 char ghash_h[GMAC_BLOCK_LEN]; 135 }; 136 137 struct ccr_session_blkcipher { 138 unsigned int cipher_mode; 139 unsigned int key_len; 140 unsigned int iv_len; 141 __be32 key_ctx_hdr; 142 char enckey[CHCR_AES_MAX_KEY_LEN]; 143 char deckey[CHCR_AES_MAX_KEY_LEN]; 144 }; 145 146 struct ccr_session { 147 bool active; 148 int pending; 149 enum { HMAC, BLKCIPHER, AUTHENC, GCM } mode; 150 union { 151 struct ccr_session_hmac hmac; 152 struct ccr_session_gmac gmac; 153 }; 154 struct ccr_session_blkcipher blkcipher; 155 }; 156 157 struct ccr_softc { 158 struct adapter *adapter; 159 device_t dev; 160 uint32_t cid; 161 int tx_channel_id; 162 struct ccr_session *sessions; 163 int nsessions; 164 struct mtx lock; 165 bool detaching; 166 struct sge_wrq *txq; 167 struct sge_rxq *rxq; 168 169 /* 170 * Pre-allocate S/G lists used when preparing a work request. 171 * 'sg_crp' contains an sglist describing the entire buffer 172 * for a 'struct cryptop'. 'sg_ulptx' is used to describe 173 * the data the engine should DMA as input via ULPTX_SGL. 174 * 'sg_dsgl' is used to describe the destination that cipher 175 * text and a tag should be written to. 176 */ 177 struct sglist *sg_crp; 178 struct sglist *sg_ulptx; 179 struct sglist *sg_dsgl; 180 181 /* Statistics. */ 182 uint64_t stats_blkcipher_encrypt; 183 uint64_t stats_blkcipher_decrypt; 184 uint64_t stats_hmac; 185 uint64_t stats_authenc_encrypt; 186 uint64_t stats_authenc_decrypt; 187 uint64_t stats_gcm_encrypt; 188 uint64_t stats_gcm_decrypt; 189 uint64_t stats_wr_nomem; 190 uint64_t stats_inflight; 191 uint64_t stats_mac_error; 192 uint64_t stats_pad_error; 193 uint64_t stats_bad_session; 194 uint64_t stats_sglist_error; 195 uint64_t stats_process_error; 196 }; 197 198 /* 199 * Crypto requests involve two kind of scatter/gather lists. 200 * 201 * Non-hash-only requests require a PHYS_DSGL that describes the 202 * location to store the results of the encryption or decryption 203 * operation. This SGL uses a different format (PHYS_DSGL) and should 204 * exclude the crd_skip bytes at the start of the data as well as 205 * any AAD or IV. For authenticated encryption requests it should 206 * cover include the destination of the hash or tag. 207 * 208 * The input payload may either be supplied inline as immediate data, 209 * or via a standard ULP_TX SGL. This SGL should include AAD, 210 * ciphertext, and the hash or tag for authenticated decryption 211 * requests. 212 * 213 * These scatter/gather lists can describe different subsets of the 214 * buffer described by the crypto operation. ccr_populate_sglist() 215 * generates a scatter/gather list that covers the entire crypto 216 * operation buffer that is then used to construct the other 217 * scatter/gather lists. 218 */ 219 static int 220 ccr_populate_sglist(struct sglist *sg, struct cryptop *crp) 221 { 222 int error; 223 224 sglist_reset(sg); 225 if (crp->crp_flags & CRYPTO_F_IMBUF) 226 error = sglist_append_mbuf(sg, (struct mbuf *)crp->crp_buf); 227 else if (crp->crp_flags & CRYPTO_F_IOV) 228 error = sglist_append_uio(sg, (struct uio *)crp->crp_buf); 229 else 230 error = sglist_append(sg, crp->crp_buf, crp->crp_ilen); 231 return (error); 232 } 233 234 /* 235 * Segments in 'sg' larger than 'maxsegsize' are counted as multiple 236 * segments. 237 */ 238 static int 239 ccr_count_sgl(struct sglist *sg, int maxsegsize) 240 { 241 int i, nsegs; 242 243 nsegs = 0; 244 for (i = 0; i < sg->sg_nseg; i++) 245 nsegs += howmany(sg->sg_segs[i].ss_len, maxsegsize); 246 return (nsegs); 247 } 248 249 /* These functions deal with PHYS_DSGL for the reply buffer. */ 250 static inline int 251 ccr_phys_dsgl_len(int nsegs) 252 { 253 int len; 254 255 len = (nsegs / 8) * sizeof(struct phys_sge_pairs); 256 if ((nsegs % 8) != 0) { 257 len += sizeof(uint16_t) * 8; 258 len += roundup2(nsegs % 8, 2) * sizeof(uint64_t); 259 } 260 return (len); 261 } 262 263 static void 264 ccr_write_phys_dsgl(struct ccr_softc *sc, void *dst, int nsegs) 265 { 266 struct sglist *sg; 267 struct cpl_rx_phys_dsgl *cpl; 268 struct phys_sge_pairs *sgl; 269 vm_paddr_t paddr; 270 size_t seglen; 271 u_int i, j; 272 273 sg = sc->sg_dsgl; 274 cpl = dst; 275 cpl->op_to_tid = htobe32(V_CPL_RX_PHYS_DSGL_OPCODE(CPL_RX_PHYS_DSGL) | 276 V_CPL_RX_PHYS_DSGL_ISRDMA(0)); 277 cpl->pcirlxorder_to_noofsgentr = htobe32( 278 V_CPL_RX_PHYS_DSGL_PCIRLXORDER(0) | 279 V_CPL_RX_PHYS_DSGL_PCINOSNOOP(0) | 280 V_CPL_RX_PHYS_DSGL_PCITPHNTENB(0) | V_CPL_RX_PHYS_DSGL_DCAID(0) | 281 V_CPL_RX_PHYS_DSGL_NOOFSGENTR(nsegs)); 282 cpl->rss_hdr_int.opcode = CPL_RX_PHYS_ADDR; 283 cpl->rss_hdr_int.qid = htobe16(sc->rxq->iq.abs_id); 284 cpl->rss_hdr_int.hash_val = 0; 285 sgl = (struct phys_sge_pairs *)(cpl + 1); 286 j = 0; 287 for (i = 0; i < sg->sg_nseg; i++) { 288 seglen = sg->sg_segs[i].ss_len; 289 paddr = sg->sg_segs[i].ss_paddr; 290 do { 291 sgl->addr[j] = htobe64(paddr); 292 if (seglen > DSGL_SGE_MAXLEN) { 293 sgl->len[j] = htobe16(DSGL_SGE_MAXLEN); 294 paddr += DSGL_SGE_MAXLEN; 295 seglen -= DSGL_SGE_MAXLEN; 296 } else { 297 sgl->len[j] = htobe16(seglen); 298 seglen = 0; 299 } 300 j++; 301 if (j == 8) { 302 sgl++; 303 j = 0; 304 } 305 } while (seglen != 0); 306 } 307 MPASS(j + 8 * (sgl - (struct phys_sge_pairs *)(cpl + 1)) == nsegs); 308 } 309 310 /* These functions deal with the ULPTX_SGL for input payload. */ 311 static inline int 312 ccr_ulptx_sgl_len(int nsegs) 313 { 314 u_int n; 315 316 nsegs--; /* first segment is part of ulptx_sgl */ 317 n = sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 318 return (roundup2(n, 16)); 319 } 320 321 static void 322 ccr_write_ulptx_sgl(struct ccr_softc *sc, void *dst, int nsegs) 323 { 324 struct ulptx_sgl *usgl; 325 struct sglist *sg; 326 struct sglist_seg *ss; 327 int i; 328 329 sg = sc->sg_ulptx; 330 MPASS(nsegs == sg->sg_nseg); 331 ss = &sg->sg_segs[0]; 332 usgl = dst; 333 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 334 V_ULPTX_NSGE(nsegs)); 335 usgl->len0 = htobe32(ss->ss_len); 336 usgl->addr0 = htobe64(ss->ss_paddr); 337 ss++; 338 for (i = 0; i < sg->sg_nseg - 1; i++) { 339 usgl->sge[i / 2].len[i & 1] = htobe32(ss->ss_len); 340 usgl->sge[i / 2].addr[i & 1] = htobe64(ss->ss_paddr); 341 ss++; 342 } 343 344 } 345 346 static bool 347 ccr_use_imm_data(u_int transhdr_len, u_int input_len) 348 { 349 350 if (input_len > CRYPTO_MAX_IMM_TX_PKT_LEN) 351 return (false); 352 if (roundup2(transhdr_len, 16) + roundup2(input_len, 16) > 353 SGE_MAX_WR_LEN) 354 return (false); 355 return (true); 356 } 357 358 static void 359 ccr_populate_wreq(struct ccr_softc *sc, struct chcr_wr *crwr, u_int kctx_len, 360 u_int wr_len, uint32_t sid, u_int imm_len, u_int sgl_len, u_int hash_size, 361 u_int iv_loc, struct cryptop *crp) 362 { 363 u_int cctx_size; 364 365 cctx_size = sizeof(struct _key_ctx) + kctx_len; 366 crwr->wreq.op_to_cctx_size = htobe32( 367 V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(FW_CRYPTO_LOOKASIDE_WR) | 368 V_FW_CRYPTO_LOOKASIDE_WR_COMPL(0) | 369 V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(imm_len) | 370 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(1) | 371 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(cctx_size >> 4)); 372 crwr->wreq.len16_pkd = htobe32( 373 V_FW_CRYPTO_LOOKASIDE_WR_LEN16(wr_len / 16)); 374 crwr->wreq.session_id = htobe32(sid); 375 crwr->wreq.rx_chid_to_rx_q_id = htobe32( 376 V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(sc->tx_channel_id) | 377 V_FW_CRYPTO_LOOKASIDE_WR_LCB(0) | 378 V_FW_CRYPTO_LOOKASIDE_WR_PHASH(0) | 379 V_FW_CRYPTO_LOOKASIDE_WR_IV(iv_loc) | 380 V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(0) | 381 V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(0) | 382 V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(sc->rxq->iq.abs_id)); 383 crwr->wreq.key_addr = 0; 384 crwr->wreq.pld_size_hash_size = htobe32( 385 V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(sgl_len) | 386 V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(hash_size)); 387 crwr->wreq.cookie = htobe64((uintptr_t)crp); 388 389 crwr->ulptx.cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 390 V_ULP_TXPKT_DATAMODIFY(0) | 391 V_ULP_TXPKT_CHANNELID(sc->tx_channel_id) | V_ULP_TXPKT_DEST(0) | 392 V_ULP_TXPKT_FID(0) | V_ULP_TXPKT_RO(1)); 393 crwr->ulptx.len = htobe32( 394 ((wr_len - sizeof(struct fw_crypto_lookaside_wr)) / 16)); 395 396 crwr->sc_imm.cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 397 V_ULP_TX_SC_MORE(imm_len != 0 ? 0 : 1)); 398 crwr->sc_imm.len = htobe32(wr_len - offsetof(struct chcr_wr, sec_cpl) - 399 sgl_len); 400 } 401 402 static int 403 ccr_hmac(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 404 struct cryptop *crp) 405 { 406 struct chcr_wr *crwr; 407 struct wrqe *wr; 408 struct auth_hash *axf; 409 struct cryptodesc *crd; 410 char *dst; 411 u_int hash_size_in_response, kctx_flits, kctx_len, transhdr_len, wr_len; 412 u_int imm_len, iopad_size; 413 int error, sgl_nsegs, sgl_len; 414 415 axf = s->hmac.auth_hash; 416 417 /* PADs must be 128-bit aligned. */ 418 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 419 420 /* 421 * The 'key' part of the context includes the aligned IPAD and 422 * OPAD. 423 */ 424 kctx_len = iopad_size * 2; 425 hash_size_in_response = axf->hashsize; 426 transhdr_len = HASH_TRANSHDR_SIZE(kctx_len); 427 428 crd = crp->crp_desc; 429 if (ccr_use_imm_data(transhdr_len, crd->crd_len)) { 430 imm_len = crd->crd_len; 431 sgl_nsegs = 0; 432 sgl_len = 0; 433 } else { 434 imm_len = 0; 435 sglist_reset(sc->sg_ulptx); 436 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 437 crd->crd_skip, crd->crd_len); 438 if (error) 439 return (error); 440 sgl_nsegs = sc->sg_ulptx->sg_nseg; 441 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 442 } 443 444 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 445 wr = alloc_wrqe(wr_len, sc->txq); 446 if (wr == NULL) { 447 sc->stats_wr_nomem++; 448 return (ENOMEM); 449 } 450 crwr = wrtod(wr); 451 memset(crwr, 0, wr_len); 452 453 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 454 hash_size_in_response, IV_NOP, crp); 455 456 /* XXX: Hardcodes SGE loopback channel of 0. */ 457 crwr->sec_cpl.op_ivinsrtofst = htobe32( 458 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 459 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 460 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 461 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 462 V_CPL_TX_SEC_PDU_IVINSRTOFST(0)); 463 464 crwr->sec_cpl.pldlen = htobe32(crd->crd_len); 465 466 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 467 V_CPL_TX_SEC_PDU_AUTHSTART(1) | V_CPL_TX_SEC_PDU_AUTHSTOP(0)); 468 469 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 470 crwr->sec_cpl.seqno_numivs = htobe32( 471 V_SCMD_SEQ_NO_CTRL(0) | 472 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 473 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_NOP) | 474 V_SCMD_AUTH_MODE(s->hmac.auth_mode) | 475 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NO_TRUNC)); 476 crwr->sec_cpl.ivgen_hdrlen = htobe32( 477 V_SCMD_LAST_FRAG(0) | V_SCMD_MORE_FRAGS(0) | V_SCMD_MAC_ONLY(1)); 478 479 memcpy(crwr->key_ctx.key, s->hmac.ipad, s->hmac.partial_digest_len); 480 memcpy(crwr->key_ctx.key + iopad_size, s->hmac.opad, 481 s->hmac.partial_digest_len); 482 483 /* XXX: F_KEY_CONTEXT_SALT_PRESENT set, but 'salt' not set. */ 484 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16; 485 crwr->key_ctx.ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) | 486 V_KEY_CONTEXT_OPAD_PRESENT(1) | V_KEY_CONTEXT_SALT_PRESENT(1) | 487 V_KEY_CONTEXT_CK_SIZE(CHCR_KEYCTX_NO_KEY) | 488 V_KEY_CONTEXT_MK_SIZE(s->hmac.mk_size) | V_KEY_CONTEXT_VALID(1)); 489 490 dst = (char *)(crwr + 1) + kctx_len + DUMMY_BYTES; 491 if (imm_len != 0) 492 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip, 493 crd->crd_len, dst); 494 else 495 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 496 497 /* XXX: TODO backpressure */ 498 t4_wrq_tx(sc->adapter, wr); 499 500 return (0); 501 } 502 503 static int 504 ccr_hmac_done(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp, 505 const struct cpl_fw6_pld *cpl, int error) 506 { 507 struct cryptodesc *crd; 508 509 crd = crp->crp_desc; 510 if (error == 0) { 511 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 512 s->hmac.hash_len, (c_caddr_t)(cpl + 1)); 513 } 514 515 return (error); 516 } 517 518 static int 519 ccr_blkcipher(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 520 struct cryptop *crp) 521 { 522 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 523 struct chcr_wr *crwr; 524 struct wrqe *wr; 525 struct cryptodesc *crd; 526 char *dst; 527 u_int iv_loc, kctx_len, key_half, op_type, transhdr_len, wr_len; 528 u_int imm_len; 529 int dsgl_nsegs, dsgl_len; 530 int sgl_nsegs, sgl_len; 531 int error; 532 533 crd = crp->crp_desc; 534 535 if (s->blkcipher.key_len == 0) 536 return (EINVAL); 537 if (crd->crd_alg == CRYPTO_AES_CBC && 538 (crd->crd_len % AES_BLOCK_LEN) != 0) 539 return (EINVAL); 540 541 iv_loc = IV_NOP; 542 if (crd->crd_flags & CRD_F_ENCRYPT) { 543 op_type = CHCR_ENCRYPT_OP; 544 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 545 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len); 546 else 547 arc4rand(iv, s->blkcipher.iv_len, 0); 548 iv_loc = IV_IMMEDIATE; 549 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) 550 crypto_copyback(crp->crp_flags, crp->crp_buf, 551 crd->crd_inject, s->blkcipher.iv_len, iv); 552 } else { 553 op_type = CHCR_DECRYPT_OP; 554 if (crd->crd_flags & CRD_F_IV_EXPLICIT) { 555 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len); 556 iv_loc = IV_IMMEDIATE; 557 } else 558 iv_loc = IV_DSGL; 559 } 560 561 sglist_reset(sc->sg_dsgl); 562 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crd->crd_skip, 563 crd->crd_len); 564 if (error) 565 return (error); 566 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 567 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 568 return (EFBIG); 569 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 570 571 /* The 'key' must be 128-bit aligned. */ 572 kctx_len = roundup2(s->blkcipher.key_len, 16); 573 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 574 575 if (ccr_use_imm_data(transhdr_len, crd->crd_len + 576 s->blkcipher.iv_len)) { 577 imm_len = crd->crd_len; 578 if (iv_loc == IV_DSGL) { 579 crypto_copydata(crp->crp_flags, crp->crp_buf, 580 crd->crd_inject, s->blkcipher.iv_len, iv); 581 iv_loc = IV_IMMEDIATE; 582 } 583 sgl_nsegs = 0; 584 sgl_len = 0; 585 } else { 586 imm_len = 0; 587 sglist_reset(sc->sg_ulptx); 588 if (iv_loc == IV_DSGL) { 589 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 590 crd->crd_inject, s->blkcipher.iv_len); 591 if (error) 592 return (error); 593 } 594 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 595 crd->crd_skip, crd->crd_len); 596 if (error) 597 return (error); 598 sgl_nsegs = sc->sg_ulptx->sg_nseg; 599 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 600 } 601 602 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 603 if (iv_loc == IV_IMMEDIATE) 604 wr_len += s->blkcipher.iv_len; 605 wr = alloc_wrqe(wr_len, sc->txq); 606 if (wr == NULL) { 607 sc->stats_wr_nomem++; 608 return (ENOMEM); 609 } 610 crwr = wrtod(wr); 611 memset(crwr, 0, wr_len); 612 613 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 0, 614 iv_loc, crp); 615 616 /* XXX: Hardcodes SGE loopback channel of 0. */ 617 crwr->sec_cpl.op_ivinsrtofst = htobe32( 618 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 619 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 620 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 621 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 622 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 623 624 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + crd->crd_len); 625 626 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 627 V_CPL_TX_SEC_PDU_CIPHERSTART(s->blkcipher.iv_len + 1) | 628 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0)); 629 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 630 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0)); 631 632 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 633 crwr->sec_cpl.seqno_numivs = htobe32( 634 V_SCMD_SEQ_NO_CTRL(0) | 635 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 636 V_SCMD_ENC_DEC_CTRL(op_type) | 637 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) | 638 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_NOP) | 639 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NOP) | 640 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) | 641 V_SCMD_NUM_IVS(0)); 642 crwr->sec_cpl.ivgen_hdrlen = htobe32( 643 V_SCMD_IV_GEN_CTRL(0) | 644 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 645 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len)); 646 647 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 648 switch (crd->crd_alg) { 649 case CRYPTO_AES_CBC: 650 if (crd->crd_flags & CRD_F_ENCRYPT) 651 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 652 s->blkcipher.key_len); 653 else 654 memcpy(crwr->key_ctx.key, s->blkcipher.deckey, 655 s->blkcipher.key_len); 656 break; 657 case CRYPTO_AES_ICM: 658 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 659 s->blkcipher.key_len); 660 break; 661 case CRYPTO_AES_XTS: 662 key_half = s->blkcipher.key_len / 2; 663 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half, 664 key_half); 665 if (crd->crd_flags & CRD_F_ENCRYPT) 666 memcpy(crwr->key_ctx.key + key_half, 667 s->blkcipher.enckey, key_half); 668 else 669 memcpy(crwr->key_ctx.key + key_half, 670 s->blkcipher.deckey, key_half); 671 break; 672 } 673 674 dst = (char *)(crwr + 1) + kctx_len; 675 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 676 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 677 if (iv_loc == IV_IMMEDIATE) { 678 memcpy(dst, iv, s->blkcipher.iv_len); 679 dst += s->blkcipher.iv_len; 680 } 681 if (imm_len != 0) 682 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip, 683 crd->crd_len, dst); 684 else 685 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 686 687 /* XXX: TODO backpressure */ 688 t4_wrq_tx(sc->adapter, wr); 689 690 return (0); 691 } 692 693 static int 694 ccr_blkcipher_done(struct ccr_softc *sc, struct ccr_session *s, 695 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 696 { 697 698 /* 699 * The updated IV to permit chained requests is at 700 * cpl->data[2], but OCF doesn't permit chained requests. 701 */ 702 return (error); 703 } 704 705 /* 706 * 'hashsize' is the length of a full digest. 'authsize' is the 707 * requested digest length for this operation which may be less 708 * than 'hashsize'. 709 */ 710 static int 711 ccr_hmac_ctrl(unsigned int hashsize, unsigned int authsize) 712 { 713 714 if (authsize == 10) 715 return (CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366); 716 if (authsize == 12) 717 return (CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT); 718 if (authsize == hashsize / 2) 719 return (CHCR_SCMD_HMAC_CTRL_DIV2); 720 return (CHCR_SCMD_HMAC_CTRL_NO_TRUNC); 721 } 722 723 static int 724 ccr_authenc(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 725 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde) 726 { 727 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 728 struct chcr_wr *crwr; 729 struct wrqe *wr; 730 struct auth_hash *axf; 731 char *dst; 732 u_int iv_loc, kctx_len, key_half, op_type, transhdr_len, wr_len; 733 u_int hash_size_in_response, imm_len, iopad_size; 734 u_int aad_start, aad_len, aad_stop; 735 u_int auth_start, auth_stop, auth_insert; 736 u_int cipher_start, cipher_stop; 737 u_int hmac_ctrl, input_len; 738 int dsgl_nsegs, dsgl_len; 739 int sgl_nsegs, sgl_len; 740 int error; 741 742 if (s->blkcipher.key_len == 0) 743 return (EINVAL); 744 if (crde->crd_alg == CRYPTO_AES_CBC && 745 (crde->crd_len % AES_BLOCK_LEN) != 0) 746 return (EINVAL); 747 748 /* 749 * AAD is only permitted before the cipher/plain text, not 750 * after. 751 */ 752 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip) 753 return (EINVAL); 754 755 axf = s->hmac.auth_hash; 756 hash_size_in_response = s->hmac.hash_len; 757 758 /* 759 * The IV is always stored at the start of the buffer even 760 * though it may be duplicated in the payload. The crypto 761 * engine doesn't work properly if the IV offset points inside 762 * of the AAD region, so a second copy is always required. 763 */ 764 iv_loc = IV_IMMEDIATE; 765 if (crde->crd_flags & CRD_F_ENCRYPT) { 766 op_type = CHCR_ENCRYPT_OP; 767 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 768 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 769 else 770 arc4rand(iv, s->blkcipher.iv_len, 0); 771 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0) 772 crypto_copyback(crp->crp_flags, crp->crp_buf, 773 crde->crd_inject, s->blkcipher.iv_len, iv); 774 } else { 775 op_type = CHCR_DECRYPT_OP; 776 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 777 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 778 else 779 crypto_copydata(crp->crp_flags, crp->crp_buf, 780 crde->crd_inject, s->blkcipher.iv_len, iv); 781 } 782 783 /* 784 * The output buffer consists of the cipher text followed by 785 * the hash when encrypting. For decryption it only contains 786 * the plain text. 787 */ 788 sglist_reset(sc->sg_dsgl); 789 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip, 790 crde->crd_len); 791 if (error) 792 return (error); 793 if (op_type == CHCR_ENCRYPT_OP) { 794 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, 795 crda->crd_inject, hash_size_in_response); 796 if (error) 797 return (error); 798 } 799 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 800 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 801 return (EFBIG); 802 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 803 804 /* PADs must be 128-bit aligned. */ 805 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 806 807 /* 808 * The 'key' part of the key context consists of the key followed 809 * by the IPAD and OPAD. 810 */ 811 kctx_len = roundup2(s->blkcipher.key_len, 16) + iopad_size * 2; 812 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 813 814 /* 815 * The input buffer consists of the IV, any AAD, and then the 816 * cipher/plain text. For decryption requests the hash is 817 * appended after the cipher text. 818 */ 819 if (crda->crd_skip < crde->crd_skip) { 820 if (crda->crd_skip + crda->crd_len > crde->crd_skip) 821 aad_len = (crde->crd_skip - crda->crd_skip); 822 else 823 aad_len = crda->crd_len; 824 } else 825 aad_len = 0; 826 input_len = aad_len + crde->crd_len; 827 if (op_type == CHCR_DECRYPT_OP) 828 input_len += hash_size_in_response; 829 if (ccr_use_imm_data(transhdr_len, s->blkcipher.iv_len + input_len)) { 830 imm_len = input_len; 831 sgl_nsegs = 0; 832 sgl_len = 0; 833 } else { 834 imm_len = 0; 835 sglist_reset(sc->sg_ulptx); 836 if (aad_len != 0) { 837 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 838 crda->crd_skip, aad_len); 839 if (error) 840 return (error); 841 } 842 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 843 crde->crd_skip, crde->crd_len); 844 if (error) 845 return (error); 846 if (op_type == CHCR_DECRYPT_OP) { 847 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 848 crda->crd_inject, hash_size_in_response); 849 if (error) 850 return (error); 851 } 852 sgl_nsegs = sc->sg_ulptx->sg_nseg; 853 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 854 } 855 856 /* 857 * Any auth-only data before the cipher region is marked as AAD. 858 * Auth-data that overlaps with the cipher region is placed in 859 * the auth section. 860 */ 861 if (aad_len != 0) { 862 aad_start = s->blkcipher.iv_len + 1; 863 aad_stop = aad_start + aad_len - 1; 864 } else { 865 aad_start = 0; 866 aad_stop = 0; 867 } 868 cipher_start = s->blkcipher.iv_len + aad_len + 1; 869 if (op_type == CHCR_DECRYPT_OP) 870 cipher_stop = hash_size_in_response; 871 else 872 cipher_stop = 0; 873 if (aad_len == crda->crd_len) { 874 auth_start = 0; 875 auth_stop = 0; 876 } else { 877 if (aad_len != 0) 878 auth_start = cipher_start; 879 else 880 auth_start = s->blkcipher.iv_len + crda->crd_skip - 881 crde->crd_skip + 1; 882 auth_stop = (crde->crd_skip + crde->crd_len) - 883 (crda->crd_skip + crda->crd_len) + cipher_stop; 884 } 885 if (op_type == CHCR_DECRYPT_OP) 886 auth_insert = hash_size_in_response; 887 else 888 auth_insert = 0; 889 890 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 891 if (iv_loc == IV_IMMEDIATE) 892 wr_len += s->blkcipher.iv_len; 893 wr = alloc_wrqe(wr_len, sc->txq); 894 if (wr == NULL) { 895 sc->stats_wr_nomem++; 896 return (ENOMEM); 897 } 898 crwr = wrtod(wr); 899 memset(crwr, 0, wr_len); 900 901 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 902 op_type == CHCR_DECRYPT_OP ? hash_size_in_response : 0, iv_loc, 903 crp); 904 905 /* XXX: Hardcodes SGE loopback channel of 0. */ 906 crwr->sec_cpl.op_ivinsrtofst = htobe32( 907 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 908 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 909 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 910 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 911 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 912 913 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + input_len); 914 915 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 916 V_CPL_TX_SEC_PDU_AADSTART(aad_start) | 917 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) | 918 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) | 919 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(cipher_stop >> 4)); 920 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 921 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(cipher_stop & 0xf) | 922 V_CPL_TX_SEC_PDU_AUTHSTART(auth_start) | 923 V_CPL_TX_SEC_PDU_AUTHSTOP(auth_stop) | 924 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert)); 925 926 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 927 hmac_ctrl = ccr_hmac_ctrl(axf->hashsize, hash_size_in_response); 928 crwr->sec_cpl.seqno_numivs = htobe32( 929 V_SCMD_SEQ_NO_CTRL(0) | 930 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 931 V_SCMD_ENC_DEC_CTRL(op_type) | 932 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) | 933 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) | 934 V_SCMD_AUTH_MODE(s->hmac.auth_mode) | 935 V_SCMD_HMAC_CTRL(hmac_ctrl) | 936 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) | 937 V_SCMD_NUM_IVS(0)); 938 crwr->sec_cpl.ivgen_hdrlen = htobe32( 939 V_SCMD_IV_GEN_CTRL(0) | 940 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 941 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len)); 942 943 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 944 switch (crde->crd_alg) { 945 case CRYPTO_AES_CBC: 946 if (crde->crd_flags & CRD_F_ENCRYPT) 947 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 948 s->blkcipher.key_len); 949 else 950 memcpy(crwr->key_ctx.key, s->blkcipher.deckey, 951 s->blkcipher.key_len); 952 break; 953 case CRYPTO_AES_ICM: 954 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 955 s->blkcipher.key_len); 956 break; 957 case CRYPTO_AES_XTS: 958 key_half = s->blkcipher.key_len / 2; 959 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half, 960 key_half); 961 if (crde->crd_flags & CRD_F_ENCRYPT) 962 memcpy(crwr->key_ctx.key + key_half, 963 s->blkcipher.enckey, key_half); 964 else 965 memcpy(crwr->key_ctx.key + key_half, 966 s->blkcipher.deckey, key_half); 967 break; 968 } 969 970 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16); 971 memcpy(dst, s->hmac.ipad, s->hmac.partial_digest_len); 972 memcpy(dst + iopad_size, s->hmac.opad, s->hmac.partial_digest_len); 973 974 dst = (char *)(crwr + 1) + kctx_len; 975 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 976 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 977 if (iv_loc == IV_IMMEDIATE) { 978 memcpy(dst, iv, s->blkcipher.iv_len); 979 dst += s->blkcipher.iv_len; 980 } 981 if (imm_len != 0) { 982 if (aad_len != 0) { 983 crypto_copydata(crp->crp_flags, crp->crp_buf, 984 crda->crd_skip, aad_len, dst); 985 dst += aad_len; 986 } 987 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip, 988 crde->crd_len, dst); 989 dst += crde->crd_len; 990 if (op_type == CHCR_DECRYPT_OP) 991 crypto_copydata(crp->crp_flags, crp->crp_buf, 992 crda->crd_inject, hash_size_in_response, dst); 993 } else 994 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 995 996 /* XXX: TODO backpressure */ 997 t4_wrq_tx(sc->adapter, wr); 998 999 return (0); 1000 } 1001 1002 static int 1003 ccr_authenc_done(struct ccr_softc *sc, struct ccr_session *s, 1004 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 1005 { 1006 struct cryptodesc *crd; 1007 1008 /* 1009 * The updated IV to permit chained requests is at 1010 * cpl->data[2], but OCF doesn't permit chained requests. 1011 * 1012 * For a decryption request, the hardware may do a verification 1013 * of the HMAC which will fail if the existing HMAC isn't in the 1014 * buffer. If that happens, clear the error and copy the HMAC 1015 * from the CPL reply into the buffer. 1016 * 1017 * For encryption requests, crd should be the cipher request 1018 * which will have CRD_F_ENCRYPT set. For decryption 1019 * requests, crp_desc will be the HMAC request which should 1020 * not have this flag set. 1021 */ 1022 crd = crp->crp_desc; 1023 if (error == EBADMSG && !CHK_PAD_ERR_BIT(be64toh(cpl->data[0])) && 1024 !(crd->crd_flags & CRD_F_ENCRYPT)) { 1025 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 1026 s->hmac.hash_len, (c_caddr_t)(cpl + 1)); 1027 error = 0; 1028 } 1029 return (error); 1030 } 1031 1032 static int 1033 ccr_gcm(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 1034 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde) 1035 { 1036 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 1037 struct chcr_wr *crwr; 1038 struct wrqe *wr; 1039 char *dst; 1040 u_int iv_len, iv_loc, kctx_len, op_type, transhdr_len, wr_len; 1041 u_int hash_size_in_response, imm_len; 1042 u_int aad_start, aad_stop, cipher_start, cipher_stop, auth_insert; 1043 u_int hmac_ctrl, input_len; 1044 int dsgl_nsegs, dsgl_len; 1045 int sgl_nsegs, sgl_len; 1046 int error; 1047 1048 if (s->blkcipher.key_len == 0) 1049 return (EINVAL); 1050 1051 /* 1052 * AAD is only permitted before the cipher/plain text, not 1053 * after. 1054 */ 1055 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip) 1056 return (EINVAL); 1057 1058 hash_size_in_response = s->gmac.hash_len; 1059 1060 /* 1061 * The IV is always stored at the start of the buffer even 1062 * though it may be duplicated in the payload. The crypto 1063 * engine doesn't work properly if the IV offset points inside 1064 * of the AAD region, so a second copy is always required. 1065 * 1066 * The IV for GCM is further complicated in that IPSec 1067 * provides a full 16-byte IV (including the counter), whereas 1068 * the /dev/crypto interface sometimes provides a full 16-byte 1069 * IV (if no IV is provided in the ioctl) and sometimes a 1070 * 12-byte IV (if the IV was explicit). For now the driver 1071 * always assumes a 12-byte IV and initializes the low 4 byte 1072 * counter to 1. 1073 */ 1074 iv_loc = IV_IMMEDIATE; 1075 if (crde->crd_flags & CRD_F_ENCRYPT) { 1076 op_type = CHCR_ENCRYPT_OP; 1077 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1078 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 1079 else 1080 arc4rand(iv, s->blkcipher.iv_len, 0); 1081 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0) 1082 crypto_copyback(crp->crp_flags, crp->crp_buf, 1083 crde->crd_inject, s->blkcipher.iv_len, iv); 1084 } else { 1085 op_type = CHCR_DECRYPT_OP; 1086 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1087 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 1088 else 1089 crypto_copydata(crp->crp_flags, crp->crp_buf, 1090 crde->crd_inject, s->blkcipher.iv_len, iv); 1091 } 1092 1093 /* 1094 * If the input IV is 12 bytes, append an explicit counter of 1095 * 1. 1096 */ 1097 if (s->blkcipher.iv_len == 12) { 1098 *(uint32_t *)&iv[12] = htobe32(1); 1099 iv_len = AES_BLOCK_LEN; 1100 } else 1101 iv_len = s->blkcipher.iv_len; 1102 1103 /* 1104 * The output buffer consists of the cipher text followed by 1105 * the tag when encrypting. For decryption it only contains 1106 * the plain text. 1107 */ 1108 sglist_reset(sc->sg_dsgl); 1109 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip, 1110 crde->crd_len); 1111 if (error) 1112 return (error); 1113 if (op_type == CHCR_ENCRYPT_OP) { 1114 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, 1115 crda->crd_inject, hash_size_in_response); 1116 if (error) 1117 return (error); 1118 } 1119 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 1120 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 1121 return (EFBIG); 1122 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 1123 1124 /* 1125 * The 'key' part of the key context consists of the key followed 1126 * by the Galois hash key. 1127 */ 1128 kctx_len = roundup2(s->blkcipher.key_len, 16) + GMAC_BLOCK_LEN; 1129 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 1130 1131 /* 1132 * The input buffer consists of the IV, any AAD, and then the 1133 * cipher/plain text. For decryption requests the hash is 1134 * appended after the cipher text. 1135 */ 1136 input_len = crda->crd_len + crde->crd_len; 1137 if (op_type == CHCR_DECRYPT_OP) 1138 input_len += hash_size_in_response; 1139 if (ccr_use_imm_data(transhdr_len, iv_len + input_len)) { 1140 imm_len = input_len; 1141 sgl_nsegs = 0; 1142 sgl_len = 0; 1143 } else { 1144 imm_len = 0; 1145 sglist_reset(sc->sg_ulptx); 1146 if (crda->crd_len != 0) { 1147 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1148 crda->crd_skip, crda->crd_len); 1149 if (error) 1150 return (error); 1151 } 1152 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1153 crde->crd_skip, crde->crd_len); 1154 if (error) 1155 return (error); 1156 if (op_type == CHCR_DECRYPT_OP) { 1157 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1158 crda->crd_inject, hash_size_in_response); 1159 if (error) 1160 return (error); 1161 } 1162 sgl_nsegs = sc->sg_ulptx->sg_nseg; 1163 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 1164 } 1165 1166 if (crda->crd_len != 0) { 1167 aad_start = iv_len + 1; 1168 aad_stop = aad_start + crda->crd_len - 1; 1169 } else { 1170 aad_start = 0; 1171 aad_stop = 0; 1172 } 1173 cipher_start = iv_len + crda->crd_len + 1; 1174 if (op_type == CHCR_DECRYPT_OP) 1175 cipher_stop = hash_size_in_response; 1176 else 1177 cipher_stop = 0; 1178 if (op_type == CHCR_DECRYPT_OP) 1179 auth_insert = hash_size_in_response; 1180 else 1181 auth_insert = 0; 1182 1183 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 1184 if (iv_loc == IV_IMMEDIATE) 1185 wr_len += iv_len; 1186 wr = alloc_wrqe(wr_len, sc->txq); 1187 if (wr == NULL) { 1188 sc->stats_wr_nomem++; 1189 return (ENOMEM); 1190 } 1191 crwr = wrtod(wr); 1192 memset(crwr, 0, wr_len); 1193 1194 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 1195 0, iv_loc, crp); 1196 1197 /* XXX: Hardcodes SGE loopback channel of 0. */ 1198 crwr->sec_cpl.op_ivinsrtofst = htobe32( 1199 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 1200 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 1201 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 1202 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 1203 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 1204 1205 crwr->sec_cpl.pldlen = htobe32(iv_len + input_len); 1206 1207 /* 1208 * NB: cipherstop is explicitly set to 0. On encrypt it 1209 * should normally be set to 0 anyway (as the encrypt crd ends 1210 * at the end of the input). However, for decrypt the cipher 1211 * ends before the tag in the AUTHENC case (and authstop is 1212 * set to stop before the tag), but for GCM the cipher still 1213 * runs to the end of the buffer. Not sure if this is 1214 * intentional or a firmware quirk, but it is required for 1215 * working tag validation with GCM decryption. 1216 */ 1217 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 1218 V_CPL_TX_SEC_PDU_AADSTART(aad_start) | 1219 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) | 1220 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) | 1221 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0)); 1222 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 1223 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0) | 1224 V_CPL_TX_SEC_PDU_AUTHSTART(cipher_start) | 1225 V_CPL_TX_SEC_PDU_AUTHSTOP(cipher_stop) | 1226 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert)); 1227 1228 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 1229 hmac_ctrl = ccr_hmac_ctrl(AES_GMAC_HASH_LEN, hash_size_in_response); 1230 crwr->sec_cpl.seqno_numivs = htobe32( 1231 V_SCMD_SEQ_NO_CTRL(0) | 1232 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 1233 V_SCMD_ENC_DEC_CTRL(op_type) | 1234 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) | 1235 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_AES_GCM) | 1236 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_GHASH) | 1237 V_SCMD_HMAC_CTRL(hmac_ctrl) | 1238 V_SCMD_IV_SIZE(iv_len / 2) | 1239 V_SCMD_NUM_IVS(0)); 1240 crwr->sec_cpl.ivgen_hdrlen = htobe32( 1241 V_SCMD_IV_GEN_CTRL(0) | 1242 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 1243 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len)); 1244 1245 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 1246 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, s->blkcipher.key_len); 1247 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16); 1248 memcpy(dst, s->gmac.ghash_h, GMAC_BLOCK_LEN); 1249 1250 dst = (char *)(crwr + 1) + kctx_len; 1251 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 1252 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 1253 if (iv_loc == IV_IMMEDIATE) { 1254 memcpy(dst, iv, iv_len); 1255 dst += iv_len; 1256 } 1257 if (imm_len != 0) { 1258 if (crda->crd_len != 0) { 1259 crypto_copydata(crp->crp_flags, crp->crp_buf, 1260 crda->crd_skip, crda->crd_len, dst); 1261 dst += crda->crd_len; 1262 } 1263 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip, 1264 crde->crd_len, dst); 1265 dst += crde->crd_len; 1266 if (op_type == CHCR_DECRYPT_OP) 1267 crypto_copydata(crp->crp_flags, crp->crp_buf, 1268 crda->crd_inject, hash_size_in_response, dst); 1269 } else 1270 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 1271 1272 /* XXX: TODO backpressure */ 1273 t4_wrq_tx(sc->adapter, wr); 1274 1275 return (0); 1276 } 1277 1278 static int 1279 ccr_gcm_done(struct ccr_softc *sc, struct ccr_session *s, 1280 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 1281 { 1282 1283 /* 1284 * The updated IV to permit chained requests is at 1285 * cpl->data[2], but OCF doesn't permit chained requests. 1286 * 1287 * Note that the hardware should always verify the GMAC hash. 1288 */ 1289 return (error); 1290 } 1291 1292 static void 1293 ccr_identify(driver_t *driver, device_t parent) 1294 { 1295 struct adapter *sc; 1296 1297 sc = device_get_softc(parent); 1298 if (sc->cryptocaps & FW_CAPS_CONFIG_CRYPTO_LOOKASIDE && 1299 device_find_child(parent, "ccr", -1) == NULL) 1300 device_add_child(parent, "ccr", -1); 1301 } 1302 1303 static int 1304 ccr_probe(device_t dev) 1305 { 1306 1307 device_set_desc(dev, "Chelsio Crypto Accelerator"); 1308 return (BUS_PROBE_DEFAULT); 1309 } 1310 1311 static void 1312 ccr_sysctls(struct ccr_softc *sc) 1313 { 1314 struct sysctl_ctx_list *ctx; 1315 struct sysctl_oid *oid; 1316 struct sysctl_oid_list *children; 1317 1318 ctx = device_get_sysctl_ctx(sc->dev); 1319 1320 /* 1321 * dev.ccr.X. 1322 */ 1323 oid = device_get_sysctl_tree(sc->dev); 1324 children = SYSCTL_CHILDREN(oid); 1325 1326 /* 1327 * dev.ccr.X.stats. 1328 */ 1329 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 1330 NULL, "statistics"); 1331 children = SYSCTL_CHILDREN(oid); 1332 1333 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "hmac", CTLFLAG_RD, 1334 &sc->stats_hmac, 0, "HMAC requests submitted"); 1335 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_encrypt", CTLFLAG_RD, 1336 &sc->stats_blkcipher_encrypt, 0, 1337 "Cipher encryption requests submitted"); 1338 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_decrypt", CTLFLAG_RD, 1339 &sc->stats_blkcipher_decrypt, 0, 1340 "Cipher decryption requests submitted"); 1341 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_encrypt", CTLFLAG_RD, 1342 &sc->stats_authenc_encrypt, 0, 1343 "Combined AES+HMAC encryption requests submitted"); 1344 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_decrypt", CTLFLAG_RD, 1345 &sc->stats_authenc_decrypt, 0, 1346 "Combined AES+HMAC decryption requests submitted"); 1347 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_encrypt", CTLFLAG_RD, 1348 &sc->stats_gcm_encrypt, 0, "AES-GCM encryption requests submitted"); 1349 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_decrypt", CTLFLAG_RD, 1350 &sc->stats_gcm_decrypt, 0, "AES-GCM decryption requests submitted"); 1351 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "wr_nomem", CTLFLAG_RD, 1352 &sc->stats_wr_nomem, 0, "Work request memory allocation failures"); 1353 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "inflight", CTLFLAG_RD, 1354 &sc->stats_inflight, 0, "Requests currently pending"); 1355 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "mac_error", CTLFLAG_RD, 1356 &sc->stats_mac_error, 0, "MAC errors"); 1357 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "pad_error", CTLFLAG_RD, 1358 &sc->stats_pad_error, 0, "Padding errors"); 1359 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "bad_session", CTLFLAG_RD, 1360 &sc->stats_pad_error, 0, "Requests with invalid session ID"); 1361 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "sglist_error", CTLFLAG_RD, 1362 &sc->stats_pad_error, 0, "Requests for which DMA mapping failed"); 1363 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "process_error", CTLFLAG_RD, 1364 &sc->stats_pad_error, 0, "Requests failed during queueing"); 1365 } 1366 1367 static int 1368 ccr_attach(device_t dev) 1369 { 1370 struct ccr_softc *sc; 1371 int32_t cid; 1372 1373 /* 1374 * TODO: Crypto requests will panic if the parent device isn't 1375 * initialized so that the queues are up and running. Need to 1376 * figure out how to handle that correctly, maybe just reject 1377 * requests if the adapter isn't fully initialized? 1378 */ 1379 sc = device_get_softc(dev); 1380 sc->dev = dev; 1381 sc->adapter = device_get_softc(device_get_parent(dev)); 1382 sc->txq = &sc->adapter->sge.ctrlq[0]; 1383 sc->rxq = &sc->adapter->sge.rxq[0]; 1384 cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 1385 if (cid < 0) { 1386 device_printf(dev, "could not get crypto driver id\n"); 1387 return (ENXIO); 1388 } 1389 sc->cid = cid; 1390 sc->adapter->ccr_softc = sc; 1391 1392 /* XXX: TODO? */ 1393 sc->tx_channel_id = 0; 1394 1395 mtx_init(&sc->lock, "ccr", NULL, MTX_DEF); 1396 sc->sg_crp = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 1397 sc->sg_ulptx = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 1398 sc->sg_dsgl = sglist_alloc(MAX_RX_PHYS_DSGL_SGE, M_WAITOK); 1399 ccr_sysctls(sc); 1400 1401 crypto_register(cid, CRYPTO_SHA1_HMAC, 0, 0); 1402 crypto_register(cid, CRYPTO_SHA2_256_HMAC, 0, 0); 1403 crypto_register(cid, CRYPTO_SHA2_384_HMAC, 0, 0); 1404 crypto_register(cid, CRYPTO_SHA2_512_HMAC, 0, 0); 1405 crypto_register(cid, CRYPTO_AES_CBC, 0, 0); 1406 crypto_register(cid, CRYPTO_AES_ICM, 0, 0); 1407 crypto_register(cid, CRYPTO_AES_NIST_GCM_16, 0, 0); 1408 crypto_register(cid, CRYPTO_AES_128_NIST_GMAC, 0, 0); 1409 crypto_register(cid, CRYPTO_AES_192_NIST_GMAC, 0, 0); 1410 crypto_register(cid, CRYPTO_AES_256_NIST_GMAC, 0, 0); 1411 crypto_register(cid, CRYPTO_AES_XTS, 0, 0); 1412 return (0); 1413 } 1414 1415 static int 1416 ccr_detach(device_t dev) 1417 { 1418 struct ccr_softc *sc; 1419 int i; 1420 1421 sc = device_get_softc(dev); 1422 1423 mtx_lock(&sc->lock); 1424 for (i = 0; i < sc->nsessions; i++) { 1425 if (sc->sessions[i].active || sc->sessions[i].pending != 0) { 1426 mtx_unlock(&sc->lock); 1427 return (EBUSY); 1428 } 1429 } 1430 sc->detaching = true; 1431 mtx_unlock(&sc->lock); 1432 1433 crypto_unregister_all(sc->cid); 1434 free(sc->sessions, M_CCR); 1435 mtx_destroy(&sc->lock); 1436 sglist_free(sc->sg_dsgl); 1437 sglist_free(sc->sg_ulptx); 1438 sglist_free(sc->sg_crp); 1439 sc->adapter->ccr_softc = NULL; 1440 return (0); 1441 } 1442 1443 static void 1444 ccr_copy_partial_hash(void *dst, int cri_alg, union authctx *auth_ctx) 1445 { 1446 uint32_t *u32; 1447 uint64_t *u64; 1448 u_int i; 1449 1450 u32 = (uint32_t *)dst; 1451 u64 = (uint64_t *)dst; 1452 switch (cri_alg) { 1453 case CRYPTO_SHA1_HMAC: 1454 for (i = 0; i < SHA1_HASH_LEN / 4; i++) 1455 u32[i] = htobe32(auth_ctx->sha1ctx.h.b32[i]); 1456 break; 1457 case CRYPTO_SHA2_256_HMAC: 1458 for (i = 0; i < SHA2_256_HASH_LEN / 4; i++) 1459 u32[i] = htobe32(auth_ctx->sha256ctx.state[i]); 1460 break; 1461 case CRYPTO_SHA2_384_HMAC: 1462 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++) 1463 u64[i] = htobe64(auth_ctx->sha384ctx.state[i]); 1464 break; 1465 case CRYPTO_SHA2_512_HMAC: 1466 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++) 1467 u64[i] = htobe64(auth_ctx->sha512ctx.state[i]); 1468 break; 1469 } 1470 } 1471 1472 static void 1473 ccr_init_hmac_digest(struct ccr_session *s, int cri_alg, char *key, 1474 int klen) 1475 { 1476 union authctx auth_ctx; 1477 struct auth_hash *axf; 1478 u_int i; 1479 1480 /* 1481 * If the key is larger than the block size, use the digest of 1482 * the key as the key instead. 1483 */ 1484 axf = s->hmac.auth_hash; 1485 klen /= 8; 1486 if (klen > axf->blocksize) { 1487 axf->Init(&auth_ctx); 1488 axf->Update(&auth_ctx, key, klen); 1489 axf->Final(s->hmac.ipad, &auth_ctx); 1490 klen = axf->hashsize; 1491 } else 1492 memcpy(s->hmac.ipad, key, klen); 1493 1494 memset(s->hmac.ipad + klen, 0, axf->blocksize); 1495 memcpy(s->hmac.opad, s->hmac.ipad, axf->blocksize); 1496 1497 for (i = 0; i < axf->blocksize; i++) { 1498 s->hmac.ipad[i] ^= HMAC_IPAD_VAL; 1499 s->hmac.opad[i] ^= HMAC_OPAD_VAL; 1500 } 1501 1502 /* 1503 * Hash the raw ipad and opad and store the partial result in 1504 * the same buffer. 1505 */ 1506 axf->Init(&auth_ctx); 1507 axf->Update(&auth_ctx, s->hmac.ipad, axf->blocksize); 1508 ccr_copy_partial_hash(s->hmac.ipad, cri_alg, &auth_ctx); 1509 1510 axf->Init(&auth_ctx); 1511 axf->Update(&auth_ctx, s->hmac.opad, axf->blocksize); 1512 ccr_copy_partial_hash(s->hmac.opad, cri_alg, &auth_ctx); 1513 } 1514 1515 /* 1516 * Borrowed from AES_GMAC_Setkey(). 1517 */ 1518 static void 1519 ccr_init_gmac_hash(struct ccr_session *s, char *key, int klen) 1520 { 1521 static char zeroes[GMAC_BLOCK_LEN]; 1522 uint32_t keysched[4 * (RIJNDAEL_MAXNR + 1)]; 1523 int rounds; 1524 1525 rounds = rijndaelKeySetupEnc(keysched, key, klen); 1526 rijndaelEncrypt(keysched, rounds, zeroes, s->gmac.ghash_h); 1527 } 1528 1529 static int 1530 ccr_aes_check_keylen(int alg, int klen) 1531 { 1532 1533 switch (klen) { 1534 case 128: 1535 case 192: 1536 if (alg == CRYPTO_AES_XTS) 1537 return (EINVAL); 1538 break; 1539 case 256: 1540 break; 1541 case 512: 1542 if (alg != CRYPTO_AES_XTS) 1543 return (EINVAL); 1544 break; 1545 default: 1546 return (EINVAL); 1547 } 1548 return (0); 1549 } 1550 1551 /* 1552 * Borrowed from cesa_prep_aes_key(). We should perhaps have a public 1553 * function to generate this instead. 1554 * 1555 * NB: The crypto engine wants the words in the decryption key in reverse 1556 * order. 1557 */ 1558 static void 1559 ccr_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 1560 { 1561 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 1562 uint32_t *dkey; 1563 int i; 1564 1565 rijndaelKeySetupEnc(ek, enc_key, kbits); 1566 dkey = dec_key; 1567 dkey += (kbits / 8) / 4; 1568 1569 switch (kbits) { 1570 case 128: 1571 for (i = 0; i < 4; i++) 1572 *--dkey = htobe32(ek[4 * 10 + i]); 1573 break; 1574 case 192: 1575 for (i = 0; i < 2; i++) 1576 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 1577 for (i = 0; i < 4; i++) 1578 *--dkey = htobe32(ek[4 * 12 + i]); 1579 break; 1580 case 256: 1581 for (i = 0; i < 4; i++) 1582 *--dkey = htobe32(ek[4 * 13 + i]); 1583 for (i = 0; i < 4; i++) 1584 *--dkey = htobe32(ek[4 * 14 + i]); 1585 break; 1586 } 1587 MPASS(dkey == dec_key); 1588 } 1589 1590 static void 1591 ccr_aes_setkey(struct ccr_session *s, int alg, const void *key, int klen) 1592 { 1593 unsigned int ck_size, iopad_size, kctx_flits, kctx_len, kbits, mk_size; 1594 unsigned int opad_present; 1595 1596 if (alg == CRYPTO_AES_XTS) 1597 kbits = klen / 2; 1598 else 1599 kbits = klen; 1600 switch (kbits) { 1601 case 128: 1602 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128; 1603 break; 1604 case 192: 1605 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192; 1606 break; 1607 case 256: 1608 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256; 1609 break; 1610 default: 1611 panic("should not get here"); 1612 } 1613 1614 s->blkcipher.key_len = klen / 8; 1615 memcpy(s->blkcipher.enckey, key, s->blkcipher.key_len); 1616 switch (alg) { 1617 case CRYPTO_AES_CBC: 1618 case CRYPTO_AES_XTS: 1619 ccr_aes_getdeckey(s->blkcipher.deckey, key, kbits); 1620 break; 1621 } 1622 1623 kctx_len = roundup2(s->blkcipher.key_len, 16); 1624 switch (s->mode) { 1625 case AUTHENC: 1626 mk_size = s->hmac.mk_size; 1627 opad_present = 1; 1628 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 1629 kctx_len += iopad_size * 2; 1630 break; 1631 case GCM: 1632 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128; 1633 opad_present = 0; 1634 kctx_len += GMAC_BLOCK_LEN; 1635 break; 1636 default: 1637 mk_size = CHCR_KEYCTX_NO_KEY; 1638 opad_present = 0; 1639 break; 1640 } 1641 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16; 1642 s->blkcipher.key_ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) | 1643 V_KEY_CONTEXT_DUAL_CK(alg == CRYPTO_AES_XTS) | 1644 V_KEY_CONTEXT_OPAD_PRESENT(opad_present) | 1645 V_KEY_CONTEXT_SALT_PRESENT(1) | V_KEY_CONTEXT_CK_SIZE(ck_size) | 1646 V_KEY_CONTEXT_MK_SIZE(mk_size) | V_KEY_CONTEXT_VALID(1)); 1647 } 1648 1649 static int 1650 ccr_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri) 1651 { 1652 struct ccr_softc *sc; 1653 struct ccr_session *s; 1654 struct auth_hash *auth_hash; 1655 struct cryptoini *c, *hash, *cipher; 1656 unsigned int auth_mode, cipher_mode, iv_len, mk_size; 1657 unsigned int partial_digest_len; 1658 int error, i, sess; 1659 bool gcm_hash; 1660 1661 if (sidp == NULL || cri == NULL) 1662 return (EINVAL); 1663 1664 gcm_hash = false; 1665 cipher = NULL; 1666 hash = NULL; 1667 auth_hash = NULL; 1668 auth_mode = CHCR_SCMD_AUTH_MODE_NOP; 1669 cipher_mode = CHCR_SCMD_CIPHER_MODE_NOP; 1670 iv_len = 0; 1671 mk_size = 0; 1672 partial_digest_len = 0; 1673 for (c = cri; c != NULL; c = c->cri_next) { 1674 switch (c->cri_alg) { 1675 case CRYPTO_SHA1_HMAC: 1676 case CRYPTO_SHA2_256_HMAC: 1677 case CRYPTO_SHA2_384_HMAC: 1678 case CRYPTO_SHA2_512_HMAC: 1679 case CRYPTO_AES_128_NIST_GMAC: 1680 case CRYPTO_AES_192_NIST_GMAC: 1681 case CRYPTO_AES_256_NIST_GMAC: 1682 if (hash) 1683 return (EINVAL); 1684 hash = c; 1685 switch (c->cri_alg) { 1686 case CRYPTO_SHA1_HMAC: 1687 auth_hash = &auth_hash_hmac_sha1; 1688 auth_mode = CHCR_SCMD_AUTH_MODE_SHA1; 1689 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_160; 1690 partial_digest_len = SHA1_HASH_LEN; 1691 break; 1692 case CRYPTO_SHA2_256_HMAC: 1693 auth_hash = &auth_hash_hmac_sha2_256; 1694 auth_mode = CHCR_SCMD_AUTH_MODE_SHA256; 1695 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256; 1696 partial_digest_len = SHA2_256_HASH_LEN; 1697 break; 1698 case CRYPTO_SHA2_384_HMAC: 1699 auth_hash = &auth_hash_hmac_sha2_384; 1700 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_384; 1701 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512; 1702 partial_digest_len = SHA2_512_HASH_LEN; 1703 break; 1704 case CRYPTO_SHA2_512_HMAC: 1705 auth_hash = &auth_hash_hmac_sha2_512; 1706 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_512; 1707 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512; 1708 partial_digest_len = SHA2_512_HASH_LEN; 1709 break; 1710 case CRYPTO_AES_128_NIST_GMAC: 1711 case CRYPTO_AES_192_NIST_GMAC: 1712 case CRYPTO_AES_256_NIST_GMAC: 1713 gcm_hash = true; 1714 auth_mode = CHCR_SCMD_AUTH_MODE_GHASH; 1715 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128; 1716 break; 1717 } 1718 break; 1719 case CRYPTO_AES_CBC: 1720 case CRYPTO_AES_ICM: 1721 case CRYPTO_AES_NIST_GCM_16: 1722 case CRYPTO_AES_XTS: 1723 if (cipher) 1724 return (EINVAL); 1725 cipher = c; 1726 switch (c->cri_alg) { 1727 case CRYPTO_AES_CBC: 1728 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CBC; 1729 iv_len = AES_BLOCK_LEN; 1730 break; 1731 case CRYPTO_AES_ICM: 1732 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CTR; 1733 iv_len = AES_BLOCK_LEN; 1734 break; 1735 case CRYPTO_AES_NIST_GCM_16: 1736 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_GCM; 1737 iv_len = AES_GCM_IV_LEN; 1738 break; 1739 case CRYPTO_AES_XTS: 1740 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_XTS; 1741 iv_len = AES_BLOCK_LEN; 1742 break; 1743 } 1744 if (c->cri_key != NULL) { 1745 error = ccr_aes_check_keylen(c->cri_alg, 1746 c->cri_klen); 1747 if (error) 1748 return (error); 1749 } 1750 break; 1751 default: 1752 return (EINVAL); 1753 } 1754 } 1755 if (gcm_hash != (cipher_mode == CHCR_SCMD_CIPHER_MODE_AES_GCM)) 1756 return (EINVAL); 1757 if (hash == NULL && cipher == NULL) 1758 return (EINVAL); 1759 if (hash != NULL && hash->cri_key == NULL) 1760 return (EINVAL); 1761 1762 sc = device_get_softc(dev); 1763 mtx_lock(&sc->lock); 1764 if (sc->detaching) { 1765 mtx_unlock(&sc->lock); 1766 return (ENXIO); 1767 } 1768 sess = -1; 1769 for (i = 0; i < sc->nsessions; i++) { 1770 if (!sc->sessions[i].active && sc->sessions[i].pending == 0) { 1771 sess = i; 1772 break; 1773 } 1774 } 1775 if (sess == -1) { 1776 s = malloc(sizeof(*s) * (sc->nsessions + 1), M_CCR, 1777 M_NOWAIT | M_ZERO); 1778 if (s == NULL) { 1779 mtx_unlock(&sc->lock); 1780 return (ENOMEM); 1781 } 1782 if (sc->sessions != NULL) 1783 memcpy(s, sc->sessions, sizeof(*s) * sc->nsessions); 1784 sess = sc->nsessions; 1785 free(sc->sessions, M_CCR); 1786 sc->sessions = s; 1787 sc->nsessions++; 1788 } 1789 1790 s = &sc->sessions[sess]; 1791 1792 if (gcm_hash) 1793 s->mode = GCM; 1794 else if (hash != NULL && cipher != NULL) 1795 s->mode = AUTHENC; 1796 else if (hash != NULL) 1797 s->mode = HMAC; 1798 else { 1799 MPASS(cipher != NULL); 1800 s->mode = BLKCIPHER; 1801 } 1802 if (gcm_hash) { 1803 if (hash->cri_mlen == 0) 1804 s->gmac.hash_len = AES_GMAC_HASH_LEN; 1805 else 1806 s->gmac.hash_len = hash->cri_mlen; 1807 ccr_init_gmac_hash(s, hash->cri_key, hash->cri_klen); 1808 } else if (hash != NULL) { 1809 s->hmac.auth_hash = auth_hash; 1810 s->hmac.auth_mode = auth_mode; 1811 s->hmac.mk_size = mk_size; 1812 s->hmac.partial_digest_len = partial_digest_len; 1813 if (hash->cri_mlen == 0) 1814 s->hmac.hash_len = auth_hash->hashsize; 1815 else 1816 s->hmac.hash_len = hash->cri_mlen; 1817 ccr_init_hmac_digest(s, hash->cri_alg, hash->cri_key, 1818 hash->cri_klen); 1819 } 1820 if (cipher != NULL) { 1821 s->blkcipher.cipher_mode = cipher_mode; 1822 s->blkcipher.iv_len = iv_len; 1823 if (cipher->cri_key != NULL) 1824 ccr_aes_setkey(s, cipher->cri_alg, cipher->cri_key, 1825 cipher->cri_klen); 1826 } 1827 1828 s->active = true; 1829 mtx_unlock(&sc->lock); 1830 1831 *sidp = sess; 1832 return (0); 1833 } 1834 1835 static int 1836 ccr_freesession(device_t dev, uint64_t tid) 1837 { 1838 struct ccr_softc *sc; 1839 uint32_t sid; 1840 int error; 1841 1842 sc = device_get_softc(dev); 1843 sid = CRYPTO_SESID2LID(tid); 1844 mtx_lock(&sc->lock); 1845 if (sid >= sc->nsessions || !sc->sessions[sid].active) 1846 error = EINVAL; 1847 else { 1848 if (sc->sessions[sid].pending != 0) 1849 device_printf(dev, 1850 "session %d freed with %d pending requests\n", sid, 1851 sc->sessions[sid].pending); 1852 sc->sessions[sid].active = false; 1853 error = 0; 1854 } 1855 mtx_unlock(&sc->lock); 1856 return (error); 1857 } 1858 1859 static int 1860 ccr_process(device_t dev, struct cryptop *crp, int hint) 1861 { 1862 struct ccr_softc *sc; 1863 struct ccr_session *s; 1864 struct cryptodesc *crd, *crda, *crde; 1865 uint32_t sid; 1866 int error; 1867 1868 if (crp == NULL) 1869 return (EINVAL); 1870 1871 crd = crp->crp_desc; 1872 sid = CRYPTO_SESID2LID(crp->crp_sid); 1873 sc = device_get_softc(dev); 1874 mtx_lock(&sc->lock); 1875 if (sid >= sc->nsessions || !sc->sessions[sid].active) { 1876 sc->stats_bad_session++; 1877 error = EINVAL; 1878 goto out; 1879 } 1880 1881 error = ccr_populate_sglist(sc->sg_crp, crp); 1882 if (error) { 1883 sc->stats_sglist_error++; 1884 goto out; 1885 } 1886 1887 s = &sc->sessions[sid]; 1888 switch (s->mode) { 1889 case HMAC: 1890 if (crd->crd_flags & CRD_F_KEY_EXPLICIT) 1891 ccr_init_hmac_digest(s, crd->crd_alg, crd->crd_key, 1892 crd->crd_klen); 1893 error = ccr_hmac(sc, sid, s, crp); 1894 if (error == 0) 1895 sc->stats_hmac++; 1896 break; 1897 case BLKCIPHER: 1898 if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { 1899 error = ccr_aes_check_keylen(crd->crd_alg, 1900 crd->crd_klen); 1901 if (error) 1902 break; 1903 ccr_aes_setkey(s, crd->crd_alg, crd->crd_key, 1904 crd->crd_klen); 1905 } 1906 error = ccr_blkcipher(sc, sid, s, crp); 1907 if (error == 0) { 1908 if (crd->crd_flags & CRD_F_ENCRYPT) 1909 sc->stats_blkcipher_encrypt++; 1910 else 1911 sc->stats_blkcipher_decrypt++; 1912 } 1913 break; 1914 case AUTHENC: 1915 error = 0; 1916 switch (crd->crd_alg) { 1917 case CRYPTO_AES_CBC: 1918 case CRYPTO_AES_ICM: 1919 case CRYPTO_AES_XTS: 1920 /* Only encrypt-then-authenticate supported. */ 1921 crde = crd; 1922 crda = crd->crd_next; 1923 if (!(crde->crd_flags & CRD_F_ENCRYPT)) { 1924 error = EINVAL; 1925 break; 1926 } 1927 break; 1928 default: 1929 crda = crd; 1930 crde = crd->crd_next; 1931 if (crde->crd_flags & CRD_F_ENCRYPT) { 1932 error = EINVAL; 1933 break; 1934 } 1935 break; 1936 } 1937 if (error) 1938 break; 1939 if (crda->crd_flags & CRD_F_KEY_EXPLICIT) 1940 ccr_init_hmac_digest(s, crda->crd_alg, crda->crd_key, 1941 crda->crd_klen); 1942 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) { 1943 error = ccr_aes_check_keylen(crde->crd_alg, 1944 crde->crd_klen); 1945 if (error) 1946 break; 1947 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key, 1948 crde->crd_klen); 1949 } 1950 error = ccr_authenc(sc, sid, s, crp, crda, crde); 1951 if (error == 0) { 1952 if (crde->crd_flags & CRD_F_ENCRYPT) 1953 sc->stats_authenc_encrypt++; 1954 else 1955 sc->stats_authenc_decrypt++; 1956 } 1957 break; 1958 case GCM: 1959 error = 0; 1960 if (crd->crd_alg == CRYPTO_AES_NIST_GCM_16) { 1961 crde = crd; 1962 crda = crd->crd_next; 1963 } else { 1964 crda = crd; 1965 crde = crd->crd_next; 1966 } 1967 if (crda->crd_flags & CRD_F_KEY_EXPLICIT) 1968 ccr_init_gmac_hash(s, crda->crd_key, crda->crd_klen); 1969 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) { 1970 error = ccr_aes_check_keylen(crde->crd_alg, 1971 crde->crd_klen); 1972 if (error) 1973 break; 1974 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key, 1975 crde->crd_klen); 1976 } 1977 error = ccr_gcm(sc, sid, s, crp, crda, crde); 1978 if (error == 0) { 1979 if (crde->crd_flags & CRD_F_ENCRYPT) 1980 sc->stats_gcm_encrypt++; 1981 else 1982 sc->stats_gcm_decrypt++; 1983 } 1984 break; 1985 } 1986 1987 if (error == 0) { 1988 s->pending++; 1989 sc->stats_inflight++; 1990 } else 1991 sc->stats_process_error++; 1992 1993 out: 1994 mtx_unlock(&sc->lock); 1995 1996 if (error) { 1997 crp->crp_etype = error; 1998 crypto_done(crp); 1999 } 2000 2001 return (0); 2002 } 2003 2004 static int 2005 do_cpl6_fw_pld(struct sge_iq *iq, const struct rss_header *rss, 2006 struct mbuf *m) 2007 { 2008 struct ccr_softc *sc = iq->adapter->ccr_softc; 2009 struct ccr_session *s; 2010 const struct cpl_fw6_pld *cpl; 2011 struct cryptop *crp; 2012 uint32_t sid, status; 2013 int error; 2014 2015 if (m != NULL) 2016 cpl = mtod(m, const void *); 2017 else 2018 cpl = (const void *)(rss + 1); 2019 2020 crp = (struct cryptop *)(uintptr_t)be64toh(cpl->data[1]); 2021 sid = CRYPTO_SESID2LID(crp->crp_sid); 2022 status = be64toh(cpl->data[0]); 2023 if (CHK_MAC_ERR_BIT(status) || CHK_PAD_ERR_BIT(status)) 2024 error = EBADMSG; 2025 else 2026 error = 0; 2027 2028 mtx_lock(&sc->lock); 2029 MPASS(sid < sc->nsessions); 2030 s = &sc->sessions[sid]; 2031 s->pending--; 2032 sc->stats_inflight--; 2033 2034 switch (s->mode) { 2035 case HMAC: 2036 error = ccr_hmac_done(sc, s, crp, cpl, error); 2037 break; 2038 case BLKCIPHER: 2039 error = ccr_blkcipher_done(sc, s, crp, cpl, error); 2040 break; 2041 case AUTHENC: 2042 error = ccr_authenc_done(sc, s, crp, cpl, error); 2043 break; 2044 case GCM: 2045 error = ccr_gcm_done(sc, s, crp, cpl, error); 2046 break; 2047 } 2048 2049 if (error == EBADMSG) { 2050 if (CHK_MAC_ERR_BIT(status)) 2051 sc->stats_mac_error++; 2052 if (CHK_PAD_ERR_BIT(status)) 2053 sc->stats_pad_error++; 2054 } 2055 mtx_unlock(&sc->lock); 2056 crp->crp_etype = error; 2057 crypto_done(crp); 2058 m_freem(m); 2059 return (0); 2060 } 2061 2062 static int 2063 ccr_modevent(module_t mod, int cmd, void *arg) 2064 { 2065 2066 switch (cmd) { 2067 case MOD_LOAD: 2068 t4_register_cpl_handler(CPL_FW6_PLD, do_cpl6_fw_pld); 2069 return (0); 2070 case MOD_UNLOAD: 2071 t4_register_cpl_handler(CPL_FW6_PLD, NULL); 2072 return (0); 2073 default: 2074 return (EOPNOTSUPP); 2075 } 2076 } 2077 2078 static device_method_t ccr_methods[] = { 2079 DEVMETHOD(device_identify, ccr_identify), 2080 DEVMETHOD(device_probe, ccr_probe), 2081 DEVMETHOD(device_attach, ccr_attach), 2082 DEVMETHOD(device_detach, ccr_detach), 2083 2084 DEVMETHOD(cryptodev_newsession, ccr_newsession), 2085 DEVMETHOD(cryptodev_freesession, ccr_freesession), 2086 DEVMETHOD(cryptodev_process, ccr_process), 2087 2088 DEVMETHOD_END 2089 }; 2090 2091 static driver_t ccr_driver = { 2092 "ccr", 2093 ccr_methods, 2094 sizeof(struct ccr_softc) 2095 }; 2096 2097 static devclass_t ccr_devclass; 2098 2099 DRIVER_MODULE(ccr, t6nex, ccr_driver, ccr_devclass, ccr_modevent, NULL); 2100 MODULE_VERSION(ccr, 1); 2101 MODULE_DEPEND(ccr, crypto, 1, 1, 1); 2102 MODULE_DEPEND(ccr, t6nex, 1, 1, 1); 2103