1 /*- 2 * Copyright (c) 2017 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/types.h> 32 #include <sys/bus.h> 33 #include <sys/lock.h> 34 #include <sys/malloc.h> 35 #include <sys/mutex.h> 36 #include <sys/module.h> 37 #include <sys/sglist.h> 38 39 #include <opencrypto/cryptodev.h> 40 #include <opencrypto/xform.h> 41 42 #include "cryptodev_if.h" 43 44 #include "common/common.h" 45 #include "crypto/t4_crypto.h" 46 47 /* 48 * Requests consist of: 49 * 50 * +-------------------------------+ 51 * | struct fw_crypto_lookaside_wr | 52 * +-------------------------------+ 53 * | struct ulp_txpkt | 54 * +-------------------------------+ 55 * | struct ulptx_idata | 56 * +-------------------------------+ 57 * | struct cpl_tx_sec_pdu | 58 * +-------------------------------+ 59 * | struct cpl_tls_tx_scmd_fmt | 60 * +-------------------------------+ 61 * | key context header | 62 * +-------------------------------+ 63 * | AES key | ----- For requests with AES 64 * +-------------------------------+ - 65 * | IPAD (16-byte aligned) | \ 66 * +-------------------------------+ +---- For requests with HMAC 67 * | OPAD (16-byte aligned) | / 68 * +-------------------------------+ - 69 * | GMAC H | ----- For AES-GCM 70 * +-------------------------------+ - 71 * | struct cpl_rx_phys_dsgl | \ 72 * +-------------------------------+ +---- Destination buffer for 73 * | PHYS_DSGL entries | / non-hash-only requests 74 * +-------------------------------+ - 75 * | 16 dummy bytes | ----- Only for hash-only requests 76 * +-------------------------------+ 77 * | IV | ----- If immediate IV 78 * +-------------------------------+ 79 * | Payload | ----- If immediate Payload 80 * +-------------------------------+ - 81 * | struct ulptx_sgl | \ 82 * +-------------------------------+ +---- If payload via SGL 83 * | SGL entries | / 84 * +-------------------------------+ - 85 * 86 * Note that the key context must be padded to ensure 16-byte alignment. 87 * For HMAC requests, the key consists of the partial hash of the IPAD 88 * followed by the partial hash of the OPAD. 89 * 90 * Replies consist of: 91 * 92 * +-------------------------------+ 93 * | struct cpl_fw6_pld | 94 * +-------------------------------+ 95 * | hash digest | ----- For HMAC request with 96 * +-------------------------------+ 'hash_size' set in work request 97 * 98 * A 32-bit big-endian error status word is supplied in the last 4 99 * bytes of data[0] in the CPL_FW6_PLD message. bit 0 indicates a 100 * "MAC" error and bit 1 indicates a "PAD" error. 101 * 102 * The 64-bit 'cookie' field from the fw_crypto_lookaside_wr message 103 * in the request is returned in data[1] of the CPL_FW6_PLD message. 104 * 105 * For block cipher replies, the updated IV is supplied in data[2] and 106 * data[3] of the CPL_FW6_PLD message. 107 * 108 * For hash replies where the work request set 'hash_size' to request 109 * a copy of the hash in the reply, the hash digest is supplied 110 * immediately following the CPL_FW6_PLD message. 111 */ 112 113 /* 114 * The crypto engine supports a maximum AAD size of 511 bytes. 115 */ 116 #define MAX_AAD_LEN 511 117 118 /* 119 * The documentation for CPL_RX_PHYS_DSGL claims a maximum of 32 SG 120 * entries. While the CPL includes a 16-bit length field, the T6 can 121 * sometimes hang if an error occurs while processing a request with a 122 * single DSGL entry larger than 2k. 123 */ 124 #define MAX_RX_PHYS_DSGL_SGE 32 125 #define DSGL_SGE_MAXLEN 2048 126 127 /* 128 * The adapter only supports requests with a total input or output 129 * length of 64k-1 or smaller. Longer requests either result in hung 130 * requests or incorrect results. 131 */ 132 #define MAX_REQUEST_SIZE 65535 133 134 static MALLOC_DEFINE(M_CCR, "ccr", "Chelsio T6 crypto"); 135 136 struct ccr_session_hmac { 137 struct auth_hash *auth_hash; 138 int hash_len; 139 unsigned int partial_digest_len; 140 unsigned int auth_mode; 141 unsigned int mk_size; 142 char ipad[CHCR_HASH_MAX_BLOCK_SIZE_128]; 143 char opad[CHCR_HASH_MAX_BLOCK_SIZE_128]; 144 }; 145 146 struct ccr_session_gmac { 147 int hash_len; 148 char ghash_h[GMAC_BLOCK_LEN]; 149 }; 150 151 struct ccr_session_blkcipher { 152 unsigned int cipher_mode; 153 unsigned int key_len; 154 unsigned int iv_len; 155 __be32 key_ctx_hdr; 156 char enckey[CHCR_AES_MAX_KEY_LEN]; 157 char deckey[CHCR_AES_MAX_KEY_LEN]; 158 }; 159 160 struct ccr_session { 161 bool active; 162 int pending; 163 enum { HMAC, BLKCIPHER, AUTHENC, GCM } mode; 164 union { 165 struct ccr_session_hmac hmac; 166 struct ccr_session_gmac gmac; 167 }; 168 struct ccr_session_blkcipher blkcipher; 169 }; 170 171 struct ccr_softc { 172 struct adapter *adapter; 173 device_t dev; 174 uint32_t cid; 175 int tx_channel_id; 176 struct ccr_session *sessions; 177 int nsessions; 178 struct mtx lock; 179 bool detaching; 180 struct sge_wrq *txq; 181 struct sge_rxq *rxq; 182 183 /* 184 * Pre-allocate S/G lists used when preparing a work request. 185 * 'sg_crp' contains an sglist describing the entire buffer 186 * for a 'struct cryptop'. 'sg_ulptx' is used to describe 187 * the data the engine should DMA as input via ULPTX_SGL. 188 * 'sg_dsgl' is used to describe the destination that cipher 189 * text and a tag should be written to. 190 */ 191 struct sglist *sg_crp; 192 struct sglist *sg_ulptx; 193 struct sglist *sg_dsgl; 194 195 /* 196 * Pre-allocate a dummy output buffer for the IV and AAD for 197 * AEAD requests. 198 */ 199 char *iv_aad_buf; 200 struct sglist *sg_iv_aad; 201 202 /* Statistics. */ 203 uint64_t stats_blkcipher_encrypt; 204 uint64_t stats_blkcipher_decrypt; 205 uint64_t stats_hmac; 206 uint64_t stats_authenc_encrypt; 207 uint64_t stats_authenc_decrypt; 208 uint64_t stats_gcm_encrypt; 209 uint64_t stats_gcm_decrypt; 210 uint64_t stats_wr_nomem; 211 uint64_t stats_inflight; 212 uint64_t stats_mac_error; 213 uint64_t stats_pad_error; 214 uint64_t stats_bad_session; 215 uint64_t stats_sglist_error; 216 uint64_t stats_process_error; 217 uint64_t stats_sw_fallback; 218 }; 219 220 /* 221 * Crypto requests involve two kind of scatter/gather lists. 222 * 223 * Non-hash-only requests require a PHYS_DSGL that describes the 224 * location to store the results of the encryption or decryption 225 * operation. This SGL uses a different format (PHYS_DSGL) and should 226 * exclude the crd_skip bytes at the start of the data as well as 227 * any AAD or IV. For authenticated encryption requests it should 228 * cover include the destination of the hash or tag. 229 * 230 * The input payload may either be supplied inline as immediate data, 231 * or via a standard ULP_TX SGL. This SGL should include AAD, 232 * ciphertext, and the hash or tag for authenticated decryption 233 * requests. 234 * 235 * These scatter/gather lists can describe different subsets of the 236 * buffer described by the crypto operation. ccr_populate_sglist() 237 * generates a scatter/gather list that covers the entire crypto 238 * operation buffer that is then used to construct the other 239 * scatter/gather lists. 240 */ 241 static int 242 ccr_populate_sglist(struct sglist *sg, struct cryptop *crp) 243 { 244 int error; 245 246 sglist_reset(sg); 247 if (crp->crp_flags & CRYPTO_F_IMBUF) 248 error = sglist_append_mbuf(sg, (struct mbuf *)crp->crp_buf); 249 else if (crp->crp_flags & CRYPTO_F_IOV) 250 error = sglist_append_uio(sg, (struct uio *)crp->crp_buf); 251 else 252 error = sglist_append(sg, crp->crp_buf, crp->crp_ilen); 253 return (error); 254 } 255 256 /* 257 * Segments in 'sg' larger than 'maxsegsize' are counted as multiple 258 * segments. 259 */ 260 static int 261 ccr_count_sgl(struct sglist *sg, int maxsegsize) 262 { 263 int i, nsegs; 264 265 nsegs = 0; 266 for (i = 0; i < sg->sg_nseg; i++) 267 nsegs += howmany(sg->sg_segs[i].ss_len, maxsegsize); 268 return (nsegs); 269 } 270 271 /* These functions deal with PHYS_DSGL for the reply buffer. */ 272 static inline int 273 ccr_phys_dsgl_len(int nsegs) 274 { 275 int len; 276 277 len = (nsegs / 8) * sizeof(struct phys_sge_pairs); 278 if ((nsegs % 8) != 0) { 279 len += sizeof(uint16_t) * 8; 280 len += roundup2(nsegs % 8, 2) * sizeof(uint64_t); 281 } 282 return (len); 283 } 284 285 static void 286 ccr_write_phys_dsgl(struct ccr_softc *sc, void *dst, int nsegs) 287 { 288 struct sglist *sg; 289 struct cpl_rx_phys_dsgl *cpl; 290 struct phys_sge_pairs *sgl; 291 vm_paddr_t paddr; 292 size_t seglen; 293 u_int i, j; 294 295 sg = sc->sg_dsgl; 296 cpl = dst; 297 cpl->op_to_tid = htobe32(V_CPL_RX_PHYS_DSGL_OPCODE(CPL_RX_PHYS_DSGL) | 298 V_CPL_RX_PHYS_DSGL_ISRDMA(0)); 299 cpl->pcirlxorder_to_noofsgentr = htobe32( 300 V_CPL_RX_PHYS_DSGL_PCIRLXORDER(0) | 301 V_CPL_RX_PHYS_DSGL_PCINOSNOOP(0) | 302 V_CPL_RX_PHYS_DSGL_PCITPHNTENB(0) | V_CPL_RX_PHYS_DSGL_DCAID(0) | 303 V_CPL_RX_PHYS_DSGL_NOOFSGENTR(nsegs)); 304 cpl->rss_hdr_int.opcode = CPL_RX_PHYS_ADDR; 305 cpl->rss_hdr_int.qid = htobe16(sc->rxq->iq.abs_id); 306 cpl->rss_hdr_int.hash_val = 0; 307 sgl = (struct phys_sge_pairs *)(cpl + 1); 308 j = 0; 309 for (i = 0; i < sg->sg_nseg; i++) { 310 seglen = sg->sg_segs[i].ss_len; 311 paddr = sg->sg_segs[i].ss_paddr; 312 do { 313 sgl->addr[j] = htobe64(paddr); 314 if (seglen > DSGL_SGE_MAXLEN) { 315 sgl->len[j] = htobe16(DSGL_SGE_MAXLEN); 316 paddr += DSGL_SGE_MAXLEN; 317 seglen -= DSGL_SGE_MAXLEN; 318 } else { 319 sgl->len[j] = htobe16(seglen); 320 seglen = 0; 321 } 322 j++; 323 if (j == 8) { 324 sgl++; 325 j = 0; 326 } 327 } while (seglen != 0); 328 } 329 MPASS(j + 8 * (sgl - (struct phys_sge_pairs *)(cpl + 1)) == nsegs); 330 } 331 332 /* These functions deal with the ULPTX_SGL for input payload. */ 333 static inline int 334 ccr_ulptx_sgl_len(int nsegs) 335 { 336 u_int n; 337 338 nsegs--; /* first segment is part of ulptx_sgl */ 339 n = sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1)); 340 return (roundup2(n, 16)); 341 } 342 343 static void 344 ccr_write_ulptx_sgl(struct ccr_softc *sc, void *dst, int nsegs) 345 { 346 struct ulptx_sgl *usgl; 347 struct sglist *sg; 348 struct sglist_seg *ss; 349 int i; 350 351 sg = sc->sg_ulptx; 352 MPASS(nsegs == sg->sg_nseg); 353 ss = &sg->sg_segs[0]; 354 usgl = dst; 355 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) | 356 V_ULPTX_NSGE(nsegs)); 357 usgl->len0 = htobe32(ss->ss_len); 358 usgl->addr0 = htobe64(ss->ss_paddr); 359 ss++; 360 for (i = 0; i < sg->sg_nseg - 1; i++) { 361 usgl->sge[i / 2].len[i & 1] = htobe32(ss->ss_len); 362 usgl->sge[i / 2].addr[i & 1] = htobe64(ss->ss_paddr); 363 ss++; 364 } 365 366 } 367 368 static bool 369 ccr_use_imm_data(u_int transhdr_len, u_int input_len) 370 { 371 372 if (input_len > CRYPTO_MAX_IMM_TX_PKT_LEN) 373 return (false); 374 if (roundup2(transhdr_len, 16) + roundup2(input_len, 16) > 375 SGE_MAX_WR_LEN) 376 return (false); 377 return (true); 378 } 379 380 static void 381 ccr_populate_wreq(struct ccr_softc *sc, struct chcr_wr *crwr, u_int kctx_len, 382 u_int wr_len, uint32_t sid, u_int imm_len, u_int sgl_len, u_int hash_size, 383 struct cryptop *crp) 384 { 385 u_int cctx_size; 386 387 cctx_size = sizeof(struct _key_ctx) + kctx_len; 388 crwr->wreq.op_to_cctx_size = htobe32( 389 V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(FW_CRYPTO_LOOKASIDE_WR) | 390 V_FW_CRYPTO_LOOKASIDE_WR_COMPL(0) | 391 V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(imm_len) | 392 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(1) | 393 V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(cctx_size >> 4)); 394 crwr->wreq.len16_pkd = htobe32( 395 V_FW_CRYPTO_LOOKASIDE_WR_LEN16(wr_len / 16)); 396 crwr->wreq.session_id = htobe32(sid); 397 crwr->wreq.rx_chid_to_rx_q_id = htobe32( 398 V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(sc->tx_channel_id) | 399 V_FW_CRYPTO_LOOKASIDE_WR_LCB(0) | 400 V_FW_CRYPTO_LOOKASIDE_WR_PHASH(0) | 401 V_FW_CRYPTO_LOOKASIDE_WR_IV(IV_NOP) | 402 V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(0) | 403 V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(0) | 404 V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(sc->rxq->iq.abs_id)); 405 crwr->wreq.key_addr = 0; 406 crwr->wreq.pld_size_hash_size = htobe32( 407 V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(sgl_len) | 408 V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(hash_size)); 409 crwr->wreq.cookie = htobe64((uintptr_t)crp); 410 411 crwr->ulptx.cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) | 412 V_ULP_TXPKT_DATAMODIFY(0) | 413 V_ULP_TXPKT_CHANNELID(sc->tx_channel_id) | V_ULP_TXPKT_DEST(0) | 414 V_ULP_TXPKT_FID(0) | V_ULP_TXPKT_RO(1)); 415 crwr->ulptx.len = htobe32( 416 ((wr_len - sizeof(struct fw_crypto_lookaside_wr)) / 16)); 417 418 crwr->sc_imm.cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) | 419 V_ULP_TX_SC_MORE(imm_len != 0 ? 0 : 1)); 420 crwr->sc_imm.len = htobe32(wr_len - offsetof(struct chcr_wr, sec_cpl) - 421 sgl_len); 422 } 423 424 static int 425 ccr_hmac(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 426 struct cryptop *crp) 427 { 428 struct chcr_wr *crwr; 429 struct wrqe *wr; 430 struct auth_hash *axf; 431 struct cryptodesc *crd; 432 char *dst; 433 u_int hash_size_in_response, kctx_flits, kctx_len, transhdr_len, wr_len; 434 u_int imm_len, iopad_size; 435 int error, sgl_nsegs, sgl_len; 436 437 crd = crp->crp_desc; 438 439 /* Reject requests with too large of an input buffer. */ 440 if (crd->crd_len > MAX_REQUEST_SIZE) 441 return (EFBIG); 442 443 axf = s->hmac.auth_hash; 444 445 /* PADs must be 128-bit aligned. */ 446 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 447 448 /* 449 * The 'key' part of the context includes the aligned IPAD and 450 * OPAD. 451 */ 452 kctx_len = iopad_size * 2; 453 hash_size_in_response = axf->hashsize; 454 transhdr_len = HASH_TRANSHDR_SIZE(kctx_len); 455 456 if (crd->crd_len == 0) { 457 imm_len = axf->blocksize; 458 sgl_nsegs = 0; 459 sgl_len = 0; 460 } else if (ccr_use_imm_data(transhdr_len, crd->crd_len)) { 461 imm_len = crd->crd_len; 462 sgl_nsegs = 0; 463 sgl_len = 0; 464 } else { 465 imm_len = 0; 466 sglist_reset(sc->sg_ulptx); 467 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 468 crd->crd_skip, crd->crd_len); 469 if (error) 470 return (error); 471 sgl_nsegs = sc->sg_ulptx->sg_nseg; 472 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 473 } 474 475 wr_len = roundup2(transhdr_len, 16) + roundup2(imm_len, 16) + sgl_len; 476 if (wr_len > SGE_MAX_WR_LEN) 477 return (EFBIG); 478 wr = alloc_wrqe(wr_len, sc->txq); 479 if (wr == NULL) { 480 sc->stats_wr_nomem++; 481 return (ENOMEM); 482 } 483 crwr = wrtod(wr); 484 memset(crwr, 0, wr_len); 485 486 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 487 hash_size_in_response, crp); 488 489 /* XXX: Hardcodes SGE loopback channel of 0. */ 490 crwr->sec_cpl.op_ivinsrtofst = htobe32( 491 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 492 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 493 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 494 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 495 V_CPL_TX_SEC_PDU_IVINSRTOFST(0)); 496 497 crwr->sec_cpl.pldlen = htobe32(crd->crd_len == 0 ? axf->blocksize : 498 crd->crd_len); 499 500 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 501 V_CPL_TX_SEC_PDU_AUTHSTART(1) | V_CPL_TX_SEC_PDU_AUTHSTOP(0)); 502 503 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 504 crwr->sec_cpl.seqno_numivs = htobe32( 505 V_SCMD_SEQ_NO_CTRL(0) | 506 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 507 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_NOP) | 508 V_SCMD_AUTH_MODE(s->hmac.auth_mode) | 509 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NO_TRUNC)); 510 crwr->sec_cpl.ivgen_hdrlen = htobe32( 511 V_SCMD_LAST_FRAG(0) | 512 V_SCMD_MORE_FRAGS(crd->crd_len == 0 ? 1 : 0) | V_SCMD_MAC_ONLY(1)); 513 514 memcpy(crwr->key_ctx.key, s->hmac.ipad, s->hmac.partial_digest_len); 515 memcpy(crwr->key_ctx.key + iopad_size, s->hmac.opad, 516 s->hmac.partial_digest_len); 517 518 /* XXX: F_KEY_CONTEXT_SALT_PRESENT set, but 'salt' not set. */ 519 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16; 520 crwr->key_ctx.ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) | 521 V_KEY_CONTEXT_OPAD_PRESENT(1) | V_KEY_CONTEXT_SALT_PRESENT(1) | 522 V_KEY_CONTEXT_CK_SIZE(CHCR_KEYCTX_NO_KEY) | 523 V_KEY_CONTEXT_MK_SIZE(s->hmac.mk_size) | V_KEY_CONTEXT_VALID(1)); 524 525 dst = (char *)(crwr + 1) + kctx_len + DUMMY_BYTES; 526 if (crd->crd_len == 0) { 527 dst[0] = 0x80; 528 *(uint64_t *)(dst + axf->blocksize - sizeof(uint64_t)) = 529 htobe64(axf->blocksize << 3); 530 } else if (imm_len != 0) 531 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip, 532 crd->crd_len, dst); 533 else 534 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 535 536 /* XXX: TODO backpressure */ 537 t4_wrq_tx(sc->adapter, wr); 538 539 return (0); 540 } 541 542 static int 543 ccr_hmac_done(struct ccr_softc *sc, struct ccr_session *s, struct cryptop *crp, 544 const struct cpl_fw6_pld *cpl, int error) 545 { 546 struct cryptodesc *crd; 547 548 crd = crp->crp_desc; 549 if (error == 0) { 550 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 551 s->hmac.hash_len, (c_caddr_t)(cpl + 1)); 552 } 553 554 return (error); 555 } 556 557 static int 558 ccr_blkcipher(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 559 struct cryptop *crp) 560 { 561 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 562 struct chcr_wr *crwr; 563 struct wrqe *wr; 564 struct cryptodesc *crd; 565 char *dst; 566 u_int kctx_len, key_half, op_type, transhdr_len, wr_len; 567 u_int imm_len; 568 int dsgl_nsegs, dsgl_len; 569 int sgl_nsegs, sgl_len; 570 int error; 571 572 crd = crp->crp_desc; 573 574 if (s->blkcipher.key_len == 0 || crd->crd_len == 0) 575 return (EINVAL); 576 if (crd->crd_alg == CRYPTO_AES_CBC && 577 (crd->crd_len % AES_BLOCK_LEN) != 0) 578 return (EINVAL); 579 580 /* Reject requests with too large of an input buffer. */ 581 if (crd->crd_len > MAX_REQUEST_SIZE) 582 return (EFBIG); 583 584 if (crd->crd_flags & CRD_F_ENCRYPT) { 585 op_type = CHCR_ENCRYPT_OP; 586 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 587 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len); 588 else 589 arc4rand(iv, s->blkcipher.iv_len, 0); 590 if ((crd->crd_flags & CRD_F_IV_PRESENT) == 0) 591 crypto_copyback(crp->crp_flags, crp->crp_buf, 592 crd->crd_inject, s->blkcipher.iv_len, iv); 593 } else { 594 op_type = CHCR_DECRYPT_OP; 595 if (crd->crd_flags & CRD_F_IV_EXPLICIT) 596 memcpy(iv, crd->crd_iv, s->blkcipher.iv_len); 597 else 598 crypto_copydata(crp->crp_flags, crp->crp_buf, 599 crd->crd_inject, s->blkcipher.iv_len, iv); 600 } 601 602 sglist_reset(sc->sg_dsgl); 603 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crd->crd_skip, 604 crd->crd_len); 605 if (error) 606 return (error); 607 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 608 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 609 return (EFBIG); 610 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 611 612 /* The 'key' must be 128-bit aligned. */ 613 kctx_len = roundup2(s->blkcipher.key_len, 16); 614 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 615 616 if (ccr_use_imm_data(transhdr_len, crd->crd_len + 617 s->blkcipher.iv_len)) { 618 imm_len = crd->crd_len; 619 sgl_nsegs = 0; 620 sgl_len = 0; 621 } else { 622 imm_len = 0; 623 sglist_reset(sc->sg_ulptx); 624 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 625 crd->crd_skip, crd->crd_len); 626 if (error) 627 return (error); 628 sgl_nsegs = sc->sg_ulptx->sg_nseg; 629 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 630 } 631 632 wr_len = roundup2(transhdr_len, 16) + s->blkcipher.iv_len + 633 roundup2(imm_len, 16) + sgl_len; 634 if (wr_len > SGE_MAX_WR_LEN) 635 return (EFBIG); 636 wr = alloc_wrqe(wr_len, sc->txq); 637 if (wr == NULL) { 638 sc->stats_wr_nomem++; 639 return (ENOMEM); 640 } 641 crwr = wrtod(wr); 642 memset(crwr, 0, wr_len); 643 644 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 0, 645 crp); 646 647 /* XXX: Hardcodes SGE loopback channel of 0. */ 648 crwr->sec_cpl.op_ivinsrtofst = htobe32( 649 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 650 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 651 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 652 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 653 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 654 655 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + crd->crd_len); 656 657 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 658 V_CPL_TX_SEC_PDU_CIPHERSTART(s->blkcipher.iv_len + 1) | 659 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0)); 660 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 661 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0)); 662 663 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 664 crwr->sec_cpl.seqno_numivs = htobe32( 665 V_SCMD_SEQ_NO_CTRL(0) | 666 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 667 V_SCMD_ENC_DEC_CTRL(op_type) | 668 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) | 669 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_NOP) | 670 V_SCMD_HMAC_CTRL(CHCR_SCMD_HMAC_CTRL_NOP) | 671 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) | 672 V_SCMD_NUM_IVS(0)); 673 crwr->sec_cpl.ivgen_hdrlen = htobe32( 674 V_SCMD_IV_GEN_CTRL(0) | 675 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 676 V_SCMD_AADIVDROP(1) | V_SCMD_HDR_LEN(dsgl_len)); 677 678 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 679 switch (crd->crd_alg) { 680 case CRYPTO_AES_CBC: 681 if (crd->crd_flags & CRD_F_ENCRYPT) 682 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 683 s->blkcipher.key_len); 684 else 685 memcpy(crwr->key_ctx.key, s->blkcipher.deckey, 686 s->blkcipher.key_len); 687 break; 688 case CRYPTO_AES_ICM: 689 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 690 s->blkcipher.key_len); 691 break; 692 case CRYPTO_AES_XTS: 693 key_half = s->blkcipher.key_len / 2; 694 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half, 695 key_half); 696 if (crd->crd_flags & CRD_F_ENCRYPT) 697 memcpy(crwr->key_ctx.key + key_half, 698 s->blkcipher.enckey, key_half); 699 else 700 memcpy(crwr->key_ctx.key + key_half, 701 s->blkcipher.deckey, key_half); 702 break; 703 } 704 705 dst = (char *)(crwr + 1) + kctx_len; 706 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 707 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 708 memcpy(dst, iv, s->blkcipher.iv_len); 709 dst += s->blkcipher.iv_len; 710 if (imm_len != 0) 711 crypto_copydata(crp->crp_flags, crp->crp_buf, crd->crd_skip, 712 crd->crd_len, dst); 713 else 714 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 715 716 /* XXX: TODO backpressure */ 717 t4_wrq_tx(sc->adapter, wr); 718 719 return (0); 720 } 721 722 static int 723 ccr_blkcipher_done(struct ccr_softc *sc, struct ccr_session *s, 724 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 725 { 726 727 /* 728 * The updated IV to permit chained requests is at 729 * cpl->data[2], but OCF doesn't permit chained requests. 730 */ 731 return (error); 732 } 733 734 /* 735 * 'hashsize' is the length of a full digest. 'authsize' is the 736 * requested digest length for this operation which may be less 737 * than 'hashsize'. 738 */ 739 static int 740 ccr_hmac_ctrl(unsigned int hashsize, unsigned int authsize) 741 { 742 743 if (authsize == 10) 744 return (CHCR_SCMD_HMAC_CTRL_TRUNC_RFC4366); 745 if (authsize == 12) 746 return (CHCR_SCMD_HMAC_CTRL_IPSEC_96BIT); 747 if (authsize == hashsize / 2) 748 return (CHCR_SCMD_HMAC_CTRL_DIV2); 749 return (CHCR_SCMD_HMAC_CTRL_NO_TRUNC); 750 } 751 752 static int 753 ccr_authenc(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 754 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde) 755 { 756 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 757 struct chcr_wr *crwr; 758 struct wrqe *wr; 759 struct auth_hash *axf; 760 char *dst; 761 u_int kctx_len, key_half, op_type, transhdr_len, wr_len; 762 u_int hash_size_in_response, imm_len, iopad_size; 763 u_int aad_start, aad_len, aad_stop; 764 u_int auth_start, auth_stop, auth_insert; 765 u_int cipher_start, cipher_stop; 766 u_int hmac_ctrl, input_len; 767 int dsgl_nsegs, dsgl_len; 768 int sgl_nsegs, sgl_len; 769 int error; 770 771 /* 772 * If there is a need in the future, requests with an empty 773 * payload could be supported as HMAC-only requests. 774 */ 775 if (s->blkcipher.key_len == 0 || crde->crd_len == 0) 776 return (EINVAL); 777 if (crde->crd_alg == CRYPTO_AES_CBC && 778 (crde->crd_len % AES_BLOCK_LEN) != 0) 779 return (EINVAL); 780 781 /* 782 * Compute the length of the AAD (data covered by the 783 * authentication descriptor but not the encryption 784 * descriptor). To simplify the logic, AAD is only permitted 785 * before the cipher/plain text, not after. This is true of 786 * all currently-generated requests. 787 */ 788 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip) 789 return (EINVAL); 790 if (crda->crd_skip < crde->crd_skip) { 791 if (crda->crd_skip + crda->crd_len > crde->crd_skip) 792 aad_len = (crde->crd_skip - crda->crd_skip); 793 else 794 aad_len = crda->crd_len; 795 } else 796 aad_len = 0; 797 if (aad_len + s->blkcipher.iv_len > MAX_AAD_LEN) 798 return (EINVAL); 799 800 axf = s->hmac.auth_hash; 801 hash_size_in_response = s->hmac.hash_len; 802 803 /* 804 * The IV is always stored at the start of the buffer even 805 * though it may be duplicated in the payload. The crypto 806 * engine doesn't work properly if the IV offset points inside 807 * of the AAD region, so a second copy is always required. 808 */ 809 if (crde->crd_flags & CRD_F_ENCRYPT) { 810 op_type = CHCR_ENCRYPT_OP; 811 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 812 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 813 else 814 arc4rand(iv, s->blkcipher.iv_len, 0); 815 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0) 816 crypto_copyback(crp->crp_flags, crp->crp_buf, 817 crde->crd_inject, s->blkcipher.iv_len, iv); 818 } else { 819 op_type = CHCR_DECRYPT_OP; 820 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 821 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 822 else 823 crypto_copydata(crp->crp_flags, crp->crp_buf, 824 crde->crd_inject, s->blkcipher.iv_len, iv); 825 } 826 827 /* 828 * The output buffer consists of the cipher text followed by 829 * the hash when encrypting. For decryption it only contains 830 * the plain text. 831 * 832 * Due to a firmware bug, the output buffer must include a 833 * dummy output buffer for the IV and AAD prior to the real 834 * output buffer. 835 */ 836 if (op_type == CHCR_ENCRYPT_OP) { 837 if (s->blkcipher.iv_len + aad_len + crde->crd_len + 838 hash_size_in_response > MAX_REQUEST_SIZE) 839 return (EFBIG); 840 } else { 841 if (s->blkcipher.iv_len + aad_len + crde->crd_len > 842 MAX_REQUEST_SIZE) 843 return (EFBIG); 844 } 845 sglist_reset(sc->sg_dsgl); 846 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_iv_aad, 0, 847 s->blkcipher.iv_len + aad_len); 848 if (error) 849 return (error); 850 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip, 851 crde->crd_len); 852 if (error) 853 return (error); 854 if (op_type == CHCR_ENCRYPT_OP) { 855 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, 856 crda->crd_inject, hash_size_in_response); 857 if (error) 858 return (error); 859 } 860 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 861 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 862 return (EFBIG); 863 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 864 865 /* PADs must be 128-bit aligned. */ 866 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 867 868 /* 869 * The 'key' part of the key context consists of the key followed 870 * by the IPAD and OPAD. 871 */ 872 kctx_len = roundup2(s->blkcipher.key_len, 16) + iopad_size * 2; 873 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 874 875 /* 876 * The input buffer consists of the IV, any AAD, and then the 877 * cipher/plain text. For decryption requests the hash is 878 * appended after the cipher text. 879 */ 880 input_len = aad_len + crde->crd_len; 881 882 /* 883 * The firmware hangs if sent a request which is a 884 * bit smaller than MAX_REQUEST_SIZE. In particular, the 885 * firmware appears to require 512 - 16 bytes of spare room 886 * along with the size of the hash even if the hash isn't 887 * included in the input buffer. 888 */ 889 if (input_len + roundup2(axf->hashsize, 16) + (512 - 16) > 890 MAX_REQUEST_SIZE) 891 return (EFBIG); 892 if (op_type == CHCR_DECRYPT_OP) 893 input_len += hash_size_in_response; 894 if (ccr_use_imm_data(transhdr_len, s->blkcipher.iv_len + input_len)) { 895 imm_len = input_len; 896 sgl_nsegs = 0; 897 sgl_len = 0; 898 } else { 899 imm_len = 0; 900 sglist_reset(sc->sg_ulptx); 901 if (aad_len != 0) { 902 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 903 crda->crd_skip, aad_len); 904 if (error) 905 return (error); 906 } 907 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 908 crde->crd_skip, crde->crd_len); 909 if (error) 910 return (error); 911 if (op_type == CHCR_DECRYPT_OP) { 912 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 913 crda->crd_inject, hash_size_in_response); 914 if (error) 915 return (error); 916 } 917 sgl_nsegs = sc->sg_ulptx->sg_nseg; 918 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 919 } 920 921 /* 922 * Any auth-only data before the cipher region is marked as AAD. 923 * Auth-data that overlaps with the cipher region is placed in 924 * the auth section. 925 */ 926 if (aad_len != 0) { 927 aad_start = s->blkcipher.iv_len + 1; 928 aad_stop = aad_start + aad_len - 1; 929 } else { 930 aad_start = 0; 931 aad_stop = 0; 932 } 933 cipher_start = s->blkcipher.iv_len + aad_len + 1; 934 if (op_type == CHCR_DECRYPT_OP) 935 cipher_stop = hash_size_in_response; 936 else 937 cipher_stop = 0; 938 if (aad_len == crda->crd_len) { 939 auth_start = 0; 940 auth_stop = 0; 941 } else { 942 if (aad_len != 0) 943 auth_start = cipher_start; 944 else 945 auth_start = s->blkcipher.iv_len + crda->crd_skip - 946 crde->crd_skip + 1; 947 auth_stop = (crde->crd_skip + crde->crd_len) - 948 (crda->crd_skip + crda->crd_len) + cipher_stop; 949 } 950 if (op_type == CHCR_DECRYPT_OP) 951 auth_insert = hash_size_in_response; 952 else 953 auth_insert = 0; 954 955 wr_len = roundup2(transhdr_len, 16) + s->blkcipher.iv_len + 956 roundup2(imm_len, 16) + sgl_len; 957 if (wr_len > SGE_MAX_WR_LEN) 958 return (EFBIG); 959 wr = alloc_wrqe(wr_len, sc->txq); 960 if (wr == NULL) { 961 sc->stats_wr_nomem++; 962 return (ENOMEM); 963 } 964 crwr = wrtod(wr); 965 memset(crwr, 0, wr_len); 966 967 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 968 op_type == CHCR_DECRYPT_OP ? hash_size_in_response : 0, crp); 969 970 /* XXX: Hardcodes SGE loopback channel of 0. */ 971 crwr->sec_cpl.op_ivinsrtofst = htobe32( 972 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 973 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 974 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 975 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 976 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 977 978 crwr->sec_cpl.pldlen = htobe32(s->blkcipher.iv_len + input_len); 979 980 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 981 V_CPL_TX_SEC_PDU_AADSTART(aad_start) | 982 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) | 983 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) | 984 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(cipher_stop >> 4)); 985 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 986 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(cipher_stop & 0xf) | 987 V_CPL_TX_SEC_PDU_AUTHSTART(auth_start) | 988 V_CPL_TX_SEC_PDU_AUTHSTOP(auth_stop) | 989 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert)); 990 991 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 992 hmac_ctrl = ccr_hmac_ctrl(axf->hashsize, hash_size_in_response); 993 crwr->sec_cpl.seqno_numivs = htobe32( 994 V_SCMD_SEQ_NO_CTRL(0) | 995 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 996 V_SCMD_ENC_DEC_CTRL(op_type) | 997 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) | 998 V_SCMD_CIPH_MODE(s->blkcipher.cipher_mode) | 999 V_SCMD_AUTH_MODE(s->hmac.auth_mode) | 1000 V_SCMD_HMAC_CTRL(hmac_ctrl) | 1001 V_SCMD_IV_SIZE(s->blkcipher.iv_len / 2) | 1002 V_SCMD_NUM_IVS(0)); 1003 crwr->sec_cpl.ivgen_hdrlen = htobe32( 1004 V_SCMD_IV_GEN_CTRL(0) | 1005 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 1006 V_SCMD_AADIVDROP(0) | V_SCMD_HDR_LEN(dsgl_len)); 1007 1008 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 1009 switch (crde->crd_alg) { 1010 case CRYPTO_AES_CBC: 1011 if (crde->crd_flags & CRD_F_ENCRYPT) 1012 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 1013 s->blkcipher.key_len); 1014 else 1015 memcpy(crwr->key_ctx.key, s->blkcipher.deckey, 1016 s->blkcipher.key_len); 1017 break; 1018 case CRYPTO_AES_ICM: 1019 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, 1020 s->blkcipher.key_len); 1021 break; 1022 case CRYPTO_AES_XTS: 1023 key_half = s->blkcipher.key_len / 2; 1024 memcpy(crwr->key_ctx.key, s->blkcipher.enckey + key_half, 1025 key_half); 1026 if (crde->crd_flags & CRD_F_ENCRYPT) 1027 memcpy(crwr->key_ctx.key + key_half, 1028 s->blkcipher.enckey, key_half); 1029 else 1030 memcpy(crwr->key_ctx.key + key_half, 1031 s->blkcipher.deckey, key_half); 1032 break; 1033 } 1034 1035 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16); 1036 memcpy(dst, s->hmac.ipad, s->hmac.partial_digest_len); 1037 memcpy(dst + iopad_size, s->hmac.opad, s->hmac.partial_digest_len); 1038 1039 dst = (char *)(crwr + 1) + kctx_len; 1040 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 1041 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 1042 memcpy(dst, iv, s->blkcipher.iv_len); 1043 dst += s->blkcipher.iv_len; 1044 if (imm_len != 0) { 1045 if (aad_len != 0) { 1046 crypto_copydata(crp->crp_flags, crp->crp_buf, 1047 crda->crd_skip, aad_len, dst); 1048 dst += aad_len; 1049 } 1050 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip, 1051 crde->crd_len, dst); 1052 dst += crde->crd_len; 1053 if (op_type == CHCR_DECRYPT_OP) 1054 crypto_copydata(crp->crp_flags, crp->crp_buf, 1055 crda->crd_inject, hash_size_in_response, dst); 1056 } else 1057 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 1058 1059 /* XXX: TODO backpressure */ 1060 t4_wrq_tx(sc->adapter, wr); 1061 1062 return (0); 1063 } 1064 1065 static int 1066 ccr_authenc_done(struct ccr_softc *sc, struct ccr_session *s, 1067 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 1068 { 1069 struct cryptodesc *crd; 1070 1071 /* 1072 * The updated IV to permit chained requests is at 1073 * cpl->data[2], but OCF doesn't permit chained requests. 1074 * 1075 * For a decryption request, the hardware may do a verification 1076 * of the HMAC which will fail if the existing HMAC isn't in the 1077 * buffer. If that happens, clear the error and copy the HMAC 1078 * from the CPL reply into the buffer. 1079 * 1080 * For encryption requests, crd should be the cipher request 1081 * which will have CRD_F_ENCRYPT set. For decryption 1082 * requests, crp_desc will be the HMAC request which should 1083 * not have this flag set. 1084 */ 1085 crd = crp->crp_desc; 1086 if (error == EBADMSG && !CHK_PAD_ERR_BIT(be64toh(cpl->data[0])) && 1087 !(crd->crd_flags & CRD_F_ENCRYPT)) { 1088 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 1089 s->hmac.hash_len, (c_caddr_t)(cpl + 1)); 1090 error = 0; 1091 } 1092 return (error); 1093 } 1094 1095 static int 1096 ccr_gcm(struct ccr_softc *sc, uint32_t sid, struct ccr_session *s, 1097 struct cryptop *crp, struct cryptodesc *crda, struct cryptodesc *crde) 1098 { 1099 char iv[CHCR_MAX_CRYPTO_IV_LEN]; 1100 struct chcr_wr *crwr; 1101 struct wrqe *wr; 1102 char *dst; 1103 u_int iv_len, kctx_len, op_type, transhdr_len, wr_len; 1104 u_int hash_size_in_response, imm_len; 1105 u_int aad_start, aad_stop, cipher_start, cipher_stop, auth_insert; 1106 u_int hmac_ctrl, input_len; 1107 int dsgl_nsegs, dsgl_len; 1108 int sgl_nsegs, sgl_len; 1109 int error; 1110 1111 if (s->blkcipher.key_len == 0) 1112 return (EINVAL); 1113 1114 /* 1115 * The crypto engine doesn't handle GCM requests with an empty 1116 * payload, so handle those in software instead. 1117 */ 1118 if (crde->crd_len == 0) 1119 return (EMSGSIZE); 1120 1121 /* 1122 * AAD is only permitted before the cipher/plain text, not 1123 * after. 1124 */ 1125 if (crda->crd_len + crda->crd_skip > crde->crd_len + crde->crd_skip) 1126 return (EMSGSIZE); 1127 1128 if (crda->crd_len + AES_BLOCK_LEN > MAX_AAD_LEN) 1129 return (EMSGSIZE); 1130 1131 hash_size_in_response = s->gmac.hash_len; 1132 1133 /* 1134 * The IV is always stored at the start of the buffer even 1135 * though it may be duplicated in the payload. The crypto 1136 * engine doesn't work properly if the IV offset points inside 1137 * of the AAD region, so a second copy is always required. 1138 * 1139 * The IV for GCM is further complicated in that IPSec 1140 * provides a full 16-byte IV (including the counter), whereas 1141 * the /dev/crypto interface sometimes provides a full 16-byte 1142 * IV (if no IV is provided in the ioctl) and sometimes a 1143 * 12-byte IV (if the IV was explicit). For now the driver 1144 * always assumes a 12-byte IV and initializes the low 4 byte 1145 * counter to 1. 1146 */ 1147 if (crde->crd_flags & CRD_F_ENCRYPT) { 1148 op_type = CHCR_ENCRYPT_OP; 1149 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1150 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 1151 else 1152 arc4rand(iv, s->blkcipher.iv_len, 0); 1153 if ((crde->crd_flags & CRD_F_IV_PRESENT) == 0) 1154 crypto_copyback(crp->crp_flags, crp->crp_buf, 1155 crde->crd_inject, s->blkcipher.iv_len, iv); 1156 } else { 1157 op_type = CHCR_DECRYPT_OP; 1158 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1159 memcpy(iv, crde->crd_iv, s->blkcipher.iv_len); 1160 else 1161 crypto_copydata(crp->crp_flags, crp->crp_buf, 1162 crde->crd_inject, s->blkcipher.iv_len, iv); 1163 } 1164 1165 /* 1166 * If the input IV is 12 bytes, append an explicit counter of 1167 * 1. 1168 */ 1169 if (s->blkcipher.iv_len == 12) { 1170 *(uint32_t *)&iv[12] = htobe32(1); 1171 iv_len = AES_BLOCK_LEN; 1172 } else 1173 iv_len = s->blkcipher.iv_len; 1174 1175 /* 1176 * The output buffer consists of the cipher text followed by 1177 * the tag when encrypting. For decryption it only contains 1178 * the plain text. 1179 * 1180 * Due to a firmware bug, the output buffer must include a 1181 * dummy output buffer for the IV and AAD prior to the real 1182 * output buffer. 1183 */ 1184 if (op_type == CHCR_ENCRYPT_OP) { 1185 if (iv_len + crda->crd_len + crde->crd_len + 1186 hash_size_in_response > MAX_REQUEST_SIZE) 1187 return (EFBIG); 1188 } else { 1189 if (iv_len + crda->crd_len + crde->crd_len > MAX_REQUEST_SIZE) 1190 return (EFBIG); 1191 } 1192 sglist_reset(sc->sg_dsgl); 1193 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_iv_aad, 0, iv_len + 1194 crda->crd_len); 1195 if (error) 1196 return (error); 1197 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, crde->crd_skip, 1198 crde->crd_len); 1199 if (error) 1200 return (error); 1201 if (op_type == CHCR_ENCRYPT_OP) { 1202 error = sglist_append_sglist(sc->sg_dsgl, sc->sg_crp, 1203 crda->crd_inject, hash_size_in_response); 1204 if (error) 1205 return (error); 1206 } 1207 dsgl_nsegs = ccr_count_sgl(sc->sg_dsgl, DSGL_SGE_MAXLEN); 1208 if (dsgl_nsegs > MAX_RX_PHYS_DSGL_SGE) 1209 return (EFBIG); 1210 dsgl_len = ccr_phys_dsgl_len(dsgl_nsegs); 1211 1212 /* 1213 * The 'key' part of the key context consists of the key followed 1214 * by the Galois hash key. 1215 */ 1216 kctx_len = roundup2(s->blkcipher.key_len, 16) + GMAC_BLOCK_LEN; 1217 transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dsgl_len); 1218 1219 /* 1220 * The input buffer consists of the IV, any AAD, and then the 1221 * cipher/plain text. For decryption requests the hash is 1222 * appended after the cipher text. 1223 */ 1224 input_len = crda->crd_len + crde->crd_len; 1225 if (op_type == CHCR_DECRYPT_OP) 1226 input_len += hash_size_in_response; 1227 if (input_len > MAX_REQUEST_SIZE) 1228 return (EFBIG); 1229 if (ccr_use_imm_data(transhdr_len, iv_len + input_len)) { 1230 imm_len = input_len; 1231 sgl_nsegs = 0; 1232 sgl_len = 0; 1233 } else { 1234 imm_len = 0; 1235 sglist_reset(sc->sg_ulptx); 1236 if (crda->crd_len != 0) { 1237 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1238 crda->crd_skip, crda->crd_len); 1239 if (error) 1240 return (error); 1241 } 1242 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1243 crde->crd_skip, crde->crd_len); 1244 if (error) 1245 return (error); 1246 if (op_type == CHCR_DECRYPT_OP) { 1247 error = sglist_append_sglist(sc->sg_ulptx, sc->sg_crp, 1248 crda->crd_inject, hash_size_in_response); 1249 if (error) 1250 return (error); 1251 } 1252 sgl_nsegs = sc->sg_ulptx->sg_nseg; 1253 sgl_len = ccr_ulptx_sgl_len(sgl_nsegs); 1254 } 1255 1256 if (crda->crd_len != 0) { 1257 aad_start = iv_len + 1; 1258 aad_stop = aad_start + crda->crd_len - 1; 1259 } else { 1260 aad_start = 0; 1261 aad_stop = 0; 1262 } 1263 cipher_start = iv_len + crda->crd_len + 1; 1264 if (op_type == CHCR_DECRYPT_OP) 1265 cipher_stop = hash_size_in_response; 1266 else 1267 cipher_stop = 0; 1268 if (op_type == CHCR_DECRYPT_OP) 1269 auth_insert = hash_size_in_response; 1270 else 1271 auth_insert = 0; 1272 1273 wr_len = roundup2(transhdr_len, 16) + iv_len + roundup2(imm_len, 16) + 1274 sgl_len; 1275 if (wr_len > SGE_MAX_WR_LEN) 1276 return (EFBIG); 1277 wr = alloc_wrqe(wr_len, sc->txq); 1278 if (wr == NULL) { 1279 sc->stats_wr_nomem++; 1280 return (ENOMEM); 1281 } 1282 crwr = wrtod(wr); 1283 memset(crwr, 0, wr_len); 1284 1285 ccr_populate_wreq(sc, crwr, kctx_len, wr_len, sid, imm_len, sgl_len, 1286 0, crp); 1287 1288 /* XXX: Hardcodes SGE loopback channel of 0. */ 1289 crwr->sec_cpl.op_ivinsrtofst = htobe32( 1290 V_CPL_TX_SEC_PDU_OPCODE(CPL_TX_SEC_PDU) | 1291 V_CPL_TX_SEC_PDU_RXCHID(sc->tx_channel_id) | 1292 V_CPL_TX_SEC_PDU_ACKFOLLOWS(0) | V_CPL_TX_SEC_PDU_ULPTXLPBK(1) | 1293 V_CPL_TX_SEC_PDU_CPLLEN(2) | V_CPL_TX_SEC_PDU_PLACEHOLDER(0) | 1294 V_CPL_TX_SEC_PDU_IVINSRTOFST(1)); 1295 1296 crwr->sec_cpl.pldlen = htobe32(iv_len + input_len); 1297 1298 /* 1299 * NB: cipherstop is explicitly set to 0. On encrypt it 1300 * should normally be set to 0 anyway (as the encrypt crd ends 1301 * at the end of the input). However, for decrypt the cipher 1302 * ends before the tag in the AUTHENC case (and authstop is 1303 * set to stop before the tag), but for GCM the cipher still 1304 * runs to the end of the buffer. Not sure if this is 1305 * intentional or a firmware quirk, but it is required for 1306 * working tag validation with GCM decryption. 1307 */ 1308 crwr->sec_cpl.aadstart_cipherstop_hi = htobe32( 1309 V_CPL_TX_SEC_PDU_AADSTART(aad_start) | 1310 V_CPL_TX_SEC_PDU_AADSTOP(aad_stop) | 1311 V_CPL_TX_SEC_PDU_CIPHERSTART(cipher_start) | 1312 V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(0)); 1313 crwr->sec_cpl.cipherstop_lo_authinsert = htobe32( 1314 V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(0) | 1315 V_CPL_TX_SEC_PDU_AUTHSTART(cipher_start) | 1316 V_CPL_TX_SEC_PDU_AUTHSTOP(cipher_stop) | 1317 V_CPL_TX_SEC_PDU_AUTHINSERT(auth_insert)); 1318 1319 /* These two flits are actually a CPL_TLS_TX_SCMD_FMT. */ 1320 hmac_ctrl = ccr_hmac_ctrl(AES_GMAC_HASH_LEN, hash_size_in_response); 1321 crwr->sec_cpl.seqno_numivs = htobe32( 1322 V_SCMD_SEQ_NO_CTRL(0) | 1323 V_SCMD_PROTO_VERSION(CHCR_SCMD_PROTO_VERSION_GENERIC) | 1324 V_SCMD_ENC_DEC_CTRL(op_type) | 1325 V_SCMD_CIPH_AUTH_SEQ_CTRL(op_type == CHCR_ENCRYPT_OP ? 1 : 0) | 1326 V_SCMD_CIPH_MODE(CHCR_SCMD_CIPHER_MODE_AES_GCM) | 1327 V_SCMD_AUTH_MODE(CHCR_SCMD_AUTH_MODE_GHASH) | 1328 V_SCMD_HMAC_CTRL(hmac_ctrl) | 1329 V_SCMD_IV_SIZE(iv_len / 2) | 1330 V_SCMD_NUM_IVS(0)); 1331 crwr->sec_cpl.ivgen_hdrlen = htobe32( 1332 V_SCMD_IV_GEN_CTRL(0) | 1333 V_SCMD_MORE_FRAGS(0) | V_SCMD_LAST_FRAG(0) | V_SCMD_MAC_ONLY(0) | 1334 V_SCMD_AADIVDROP(0) | V_SCMD_HDR_LEN(dsgl_len)); 1335 1336 crwr->key_ctx.ctx_hdr = s->blkcipher.key_ctx_hdr; 1337 memcpy(crwr->key_ctx.key, s->blkcipher.enckey, s->blkcipher.key_len); 1338 dst = crwr->key_ctx.key + roundup2(s->blkcipher.key_len, 16); 1339 memcpy(dst, s->gmac.ghash_h, GMAC_BLOCK_LEN); 1340 1341 dst = (char *)(crwr + 1) + kctx_len; 1342 ccr_write_phys_dsgl(sc, dst, dsgl_nsegs); 1343 dst += sizeof(struct cpl_rx_phys_dsgl) + dsgl_len; 1344 memcpy(dst, iv, iv_len); 1345 dst += iv_len; 1346 if (imm_len != 0) { 1347 if (crda->crd_len != 0) { 1348 crypto_copydata(crp->crp_flags, crp->crp_buf, 1349 crda->crd_skip, crda->crd_len, dst); 1350 dst += crda->crd_len; 1351 } 1352 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip, 1353 crde->crd_len, dst); 1354 dst += crde->crd_len; 1355 if (op_type == CHCR_DECRYPT_OP) 1356 crypto_copydata(crp->crp_flags, crp->crp_buf, 1357 crda->crd_inject, hash_size_in_response, dst); 1358 } else 1359 ccr_write_ulptx_sgl(sc, dst, sgl_nsegs); 1360 1361 /* XXX: TODO backpressure */ 1362 t4_wrq_tx(sc->adapter, wr); 1363 1364 return (0); 1365 } 1366 1367 static int 1368 ccr_gcm_done(struct ccr_softc *sc, struct ccr_session *s, 1369 struct cryptop *crp, const struct cpl_fw6_pld *cpl, int error) 1370 { 1371 1372 /* 1373 * The updated IV to permit chained requests is at 1374 * cpl->data[2], but OCF doesn't permit chained requests. 1375 * 1376 * Note that the hardware should always verify the GMAC hash. 1377 */ 1378 return (error); 1379 } 1380 1381 /* 1382 * Handle a GCM request that is not supported by the crypto engine by 1383 * performing the operation in software. Derived from swcr_authenc(). 1384 */ 1385 static void 1386 ccr_gcm_soft(struct ccr_session *s, struct cryptop *crp, 1387 struct cryptodesc *crda, struct cryptodesc *crde) 1388 { 1389 struct auth_hash *axf; 1390 struct enc_xform *exf; 1391 void *auth_ctx; 1392 uint8_t *kschedule; 1393 char block[GMAC_BLOCK_LEN]; 1394 char digest[GMAC_DIGEST_LEN]; 1395 char iv[AES_BLOCK_LEN]; 1396 int error, i, len; 1397 1398 auth_ctx = NULL; 1399 kschedule = NULL; 1400 1401 /* Initialize the MAC. */ 1402 switch (s->blkcipher.key_len) { 1403 case 16: 1404 axf = &auth_hash_nist_gmac_aes_128; 1405 break; 1406 case 24: 1407 axf = &auth_hash_nist_gmac_aes_192; 1408 break; 1409 case 32: 1410 axf = &auth_hash_nist_gmac_aes_256; 1411 break; 1412 default: 1413 error = EINVAL; 1414 goto out; 1415 } 1416 auth_ctx = malloc(axf->ctxsize, M_CCR, M_NOWAIT); 1417 if (auth_ctx == NULL) { 1418 error = ENOMEM; 1419 goto out; 1420 } 1421 axf->Init(auth_ctx); 1422 axf->Setkey(auth_ctx, s->blkcipher.enckey, s->blkcipher.key_len); 1423 1424 /* Initialize the cipher. */ 1425 exf = &enc_xform_aes_nist_gcm; 1426 error = exf->setkey(&kschedule, s->blkcipher.enckey, 1427 s->blkcipher.key_len); 1428 if (error) 1429 goto out; 1430 1431 /* 1432 * This assumes a 12-byte IV from the crp. See longer comment 1433 * above in ccr_gcm() for more details. 1434 */ 1435 if (crde->crd_flags & CRD_F_ENCRYPT) { 1436 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1437 memcpy(iv, crde->crd_iv, 12); 1438 else 1439 arc4rand(iv, 12, 0); 1440 } else { 1441 if (crde->crd_flags & CRD_F_IV_EXPLICIT) 1442 memcpy(iv, crde->crd_iv, 12); 1443 else 1444 crypto_copydata(crp->crp_flags, crp->crp_buf, 1445 crde->crd_inject, 12, iv); 1446 } 1447 *(uint32_t *)&iv[12] = htobe32(1); 1448 1449 axf->Reinit(auth_ctx, iv, sizeof(iv)); 1450 1451 /* MAC the AAD. */ 1452 for (i = 0; i < crda->crd_len; i += sizeof(block)) { 1453 len = imin(crda->crd_len - i, sizeof(block)); 1454 crypto_copydata(crp->crp_flags, crp->crp_buf, crda->crd_skip + 1455 i, len, block); 1456 bzero(block + len, sizeof(block) - len); 1457 axf->Update(auth_ctx, block, sizeof(block)); 1458 } 1459 1460 exf->reinit(kschedule, iv); 1461 1462 /* Do encryption with MAC */ 1463 for (i = 0; i < crde->crd_len; i += sizeof(block)) { 1464 len = imin(crde->crd_len - i, sizeof(block)); 1465 crypto_copydata(crp->crp_flags, crp->crp_buf, crde->crd_skip + 1466 i, len, block); 1467 bzero(block + len, sizeof(block) - len); 1468 if (crde->crd_flags & CRD_F_ENCRYPT) { 1469 exf->encrypt(kschedule, block); 1470 axf->Update(auth_ctx, block, len); 1471 crypto_copyback(crp->crp_flags, crp->crp_buf, 1472 crde->crd_skip + i, len, block); 1473 } else { 1474 axf->Update(auth_ctx, block, len); 1475 } 1476 } 1477 1478 /* Length block. */ 1479 bzero(block, sizeof(block)); 1480 ((uint32_t *)block)[1] = htobe32(crda->crd_len * 8); 1481 ((uint32_t *)block)[3] = htobe32(crde->crd_len * 8); 1482 axf->Update(auth_ctx, block, sizeof(block)); 1483 1484 /* Finalize MAC. */ 1485 axf->Final(digest, auth_ctx); 1486 1487 /* Inject or validate tag. */ 1488 if (crde->crd_flags & CRD_F_ENCRYPT) { 1489 crypto_copyback(crp->crp_flags, crp->crp_buf, crda->crd_inject, 1490 sizeof(digest), digest); 1491 error = 0; 1492 } else { 1493 char digest2[GMAC_DIGEST_LEN]; 1494 1495 crypto_copydata(crp->crp_flags, crp->crp_buf, crda->crd_inject, 1496 sizeof(digest2), digest2); 1497 if (timingsafe_bcmp(digest, digest2, sizeof(digest)) == 0) { 1498 error = 0; 1499 1500 /* Tag matches, decrypt data. */ 1501 for (i = 0; i < crde->crd_len; i += sizeof(block)) { 1502 len = imin(crde->crd_len - i, sizeof(block)); 1503 crypto_copydata(crp->crp_flags, crp->crp_buf, 1504 crde->crd_skip + i, len, block); 1505 bzero(block + len, sizeof(block) - len); 1506 exf->decrypt(kschedule, block); 1507 crypto_copyback(crp->crp_flags, crp->crp_buf, 1508 crde->crd_skip + i, len, block); 1509 } 1510 } else 1511 error = EBADMSG; 1512 } 1513 1514 exf->zerokey(&kschedule); 1515 out: 1516 if (auth_ctx != NULL) { 1517 memset(auth_ctx, 0, axf->ctxsize); 1518 free(auth_ctx, M_CCR); 1519 } 1520 crp->crp_etype = error; 1521 crypto_done(crp); 1522 } 1523 1524 static void 1525 ccr_identify(driver_t *driver, device_t parent) 1526 { 1527 struct adapter *sc; 1528 1529 sc = device_get_softc(parent); 1530 if (sc->cryptocaps & FW_CAPS_CONFIG_CRYPTO_LOOKASIDE && 1531 device_find_child(parent, "ccr", -1) == NULL) 1532 device_add_child(parent, "ccr", -1); 1533 } 1534 1535 static int 1536 ccr_probe(device_t dev) 1537 { 1538 1539 device_set_desc(dev, "Chelsio Crypto Accelerator"); 1540 return (BUS_PROBE_DEFAULT); 1541 } 1542 1543 static void 1544 ccr_sysctls(struct ccr_softc *sc) 1545 { 1546 struct sysctl_ctx_list *ctx; 1547 struct sysctl_oid *oid; 1548 struct sysctl_oid_list *children; 1549 1550 ctx = device_get_sysctl_ctx(sc->dev); 1551 1552 /* 1553 * dev.ccr.X. 1554 */ 1555 oid = device_get_sysctl_tree(sc->dev); 1556 children = SYSCTL_CHILDREN(oid); 1557 1558 /* 1559 * dev.ccr.X.stats. 1560 */ 1561 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 1562 NULL, "statistics"); 1563 children = SYSCTL_CHILDREN(oid); 1564 1565 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "hmac", CTLFLAG_RD, 1566 &sc->stats_hmac, 0, "HMAC requests submitted"); 1567 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_encrypt", CTLFLAG_RD, 1568 &sc->stats_blkcipher_encrypt, 0, 1569 "Cipher encryption requests submitted"); 1570 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "cipher_decrypt", CTLFLAG_RD, 1571 &sc->stats_blkcipher_decrypt, 0, 1572 "Cipher decryption requests submitted"); 1573 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_encrypt", CTLFLAG_RD, 1574 &sc->stats_authenc_encrypt, 0, 1575 "Combined AES+HMAC encryption requests submitted"); 1576 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "authenc_decrypt", CTLFLAG_RD, 1577 &sc->stats_authenc_decrypt, 0, 1578 "Combined AES+HMAC decryption requests submitted"); 1579 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_encrypt", CTLFLAG_RD, 1580 &sc->stats_gcm_encrypt, 0, "AES-GCM encryption requests submitted"); 1581 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "gcm_decrypt", CTLFLAG_RD, 1582 &sc->stats_gcm_decrypt, 0, "AES-GCM decryption requests submitted"); 1583 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "wr_nomem", CTLFLAG_RD, 1584 &sc->stats_wr_nomem, 0, "Work request memory allocation failures"); 1585 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "inflight", CTLFLAG_RD, 1586 &sc->stats_inflight, 0, "Requests currently pending"); 1587 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "mac_error", CTLFLAG_RD, 1588 &sc->stats_mac_error, 0, "MAC errors"); 1589 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "pad_error", CTLFLAG_RD, 1590 &sc->stats_pad_error, 0, "Padding errors"); 1591 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "bad_session", CTLFLAG_RD, 1592 &sc->stats_bad_session, 0, "Requests with invalid session ID"); 1593 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "sglist_error", CTLFLAG_RD, 1594 &sc->stats_sglist_error, 0, 1595 "Requests for which DMA mapping failed"); 1596 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "process_error", CTLFLAG_RD, 1597 &sc->stats_process_error, 0, "Requests failed during queueing"); 1598 SYSCTL_ADD_U64(ctx, children, OID_AUTO, "sw_fallback", CTLFLAG_RD, 1599 &sc->stats_sw_fallback, 0, 1600 "Requests processed by falling back to software"); 1601 } 1602 1603 static int 1604 ccr_attach(device_t dev) 1605 { 1606 struct ccr_softc *sc; 1607 int32_t cid; 1608 1609 /* 1610 * TODO: Crypto requests will panic if the parent device isn't 1611 * initialized so that the queues are up and running. Need to 1612 * figure out how to handle that correctly, maybe just reject 1613 * requests if the adapter isn't fully initialized? 1614 */ 1615 sc = device_get_softc(dev); 1616 sc->dev = dev; 1617 sc->adapter = device_get_softc(device_get_parent(dev)); 1618 sc->txq = &sc->adapter->sge.ctrlq[0]; 1619 sc->rxq = &sc->adapter->sge.rxq[0]; 1620 cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); 1621 if (cid < 0) { 1622 device_printf(dev, "could not get crypto driver id\n"); 1623 return (ENXIO); 1624 } 1625 sc->cid = cid; 1626 sc->adapter->ccr_softc = sc; 1627 1628 /* XXX: TODO? */ 1629 sc->tx_channel_id = 0; 1630 1631 mtx_init(&sc->lock, "ccr", NULL, MTX_DEF); 1632 sc->sg_crp = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 1633 sc->sg_ulptx = sglist_alloc(TX_SGL_SEGS, M_WAITOK); 1634 sc->sg_dsgl = sglist_alloc(MAX_RX_PHYS_DSGL_SGE, M_WAITOK); 1635 sc->iv_aad_buf = malloc(MAX_AAD_LEN, M_CCR, M_WAITOK); 1636 sc->sg_iv_aad = sglist_build(sc->iv_aad_buf, MAX_AAD_LEN, M_WAITOK); 1637 ccr_sysctls(sc); 1638 1639 crypto_register(cid, CRYPTO_SHA1_HMAC, 0, 0); 1640 crypto_register(cid, CRYPTO_SHA2_256_HMAC, 0, 0); 1641 crypto_register(cid, CRYPTO_SHA2_384_HMAC, 0, 0); 1642 crypto_register(cid, CRYPTO_SHA2_512_HMAC, 0, 0); 1643 crypto_register(cid, CRYPTO_AES_CBC, 0, 0); 1644 crypto_register(cid, CRYPTO_AES_ICM, 0, 0); 1645 crypto_register(cid, CRYPTO_AES_NIST_GCM_16, 0, 0); 1646 crypto_register(cid, CRYPTO_AES_128_NIST_GMAC, 0, 0); 1647 crypto_register(cid, CRYPTO_AES_192_NIST_GMAC, 0, 0); 1648 crypto_register(cid, CRYPTO_AES_256_NIST_GMAC, 0, 0); 1649 crypto_register(cid, CRYPTO_AES_XTS, 0, 0); 1650 return (0); 1651 } 1652 1653 static int 1654 ccr_detach(device_t dev) 1655 { 1656 struct ccr_softc *sc; 1657 int i; 1658 1659 sc = device_get_softc(dev); 1660 1661 mtx_lock(&sc->lock); 1662 for (i = 0; i < sc->nsessions; i++) { 1663 if (sc->sessions[i].active || sc->sessions[i].pending != 0) { 1664 mtx_unlock(&sc->lock); 1665 return (EBUSY); 1666 } 1667 } 1668 sc->detaching = true; 1669 mtx_unlock(&sc->lock); 1670 1671 crypto_unregister_all(sc->cid); 1672 free(sc->sessions, M_CCR); 1673 mtx_destroy(&sc->lock); 1674 sglist_free(sc->sg_iv_aad); 1675 free(sc->iv_aad_buf, M_CCR); 1676 sglist_free(sc->sg_dsgl); 1677 sglist_free(sc->sg_ulptx); 1678 sglist_free(sc->sg_crp); 1679 sc->adapter->ccr_softc = NULL; 1680 return (0); 1681 } 1682 1683 static void 1684 ccr_copy_partial_hash(void *dst, int cri_alg, union authctx *auth_ctx) 1685 { 1686 uint32_t *u32; 1687 uint64_t *u64; 1688 u_int i; 1689 1690 u32 = (uint32_t *)dst; 1691 u64 = (uint64_t *)dst; 1692 switch (cri_alg) { 1693 case CRYPTO_SHA1_HMAC: 1694 for (i = 0; i < SHA1_HASH_LEN / 4; i++) 1695 u32[i] = htobe32(auth_ctx->sha1ctx.h.b32[i]); 1696 break; 1697 case CRYPTO_SHA2_256_HMAC: 1698 for (i = 0; i < SHA2_256_HASH_LEN / 4; i++) 1699 u32[i] = htobe32(auth_ctx->sha256ctx.state[i]); 1700 break; 1701 case CRYPTO_SHA2_384_HMAC: 1702 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++) 1703 u64[i] = htobe64(auth_ctx->sha384ctx.state[i]); 1704 break; 1705 case CRYPTO_SHA2_512_HMAC: 1706 for (i = 0; i < SHA2_512_HASH_LEN / 8; i++) 1707 u64[i] = htobe64(auth_ctx->sha512ctx.state[i]); 1708 break; 1709 } 1710 } 1711 1712 static void 1713 ccr_init_hmac_digest(struct ccr_session *s, int cri_alg, char *key, 1714 int klen) 1715 { 1716 union authctx auth_ctx; 1717 struct auth_hash *axf; 1718 u_int i; 1719 1720 /* 1721 * If the key is larger than the block size, use the digest of 1722 * the key as the key instead. 1723 */ 1724 axf = s->hmac.auth_hash; 1725 klen /= 8; 1726 if (klen > axf->blocksize) { 1727 axf->Init(&auth_ctx); 1728 axf->Update(&auth_ctx, key, klen); 1729 axf->Final(s->hmac.ipad, &auth_ctx); 1730 klen = axf->hashsize; 1731 } else 1732 memcpy(s->hmac.ipad, key, klen); 1733 1734 memset(s->hmac.ipad + klen, 0, axf->blocksize); 1735 memcpy(s->hmac.opad, s->hmac.ipad, axf->blocksize); 1736 1737 for (i = 0; i < axf->blocksize; i++) { 1738 s->hmac.ipad[i] ^= HMAC_IPAD_VAL; 1739 s->hmac.opad[i] ^= HMAC_OPAD_VAL; 1740 } 1741 1742 /* 1743 * Hash the raw ipad and opad and store the partial result in 1744 * the same buffer. 1745 */ 1746 axf->Init(&auth_ctx); 1747 axf->Update(&auth_ctx, s->hmac.ipad, axf->blocksize); 1748 ccr_copy_partial_hash(s->hmac.ipad, cri_alg, &auth_ctx); 1749 1750 axf->Init(&auth_ctx); 1751 axf->Update(&auth_ctx, s->hmac.opad, axf->blocksize); 1752 ccr_copy_partial_hash(s->hmac.opad, cri_alg, &auth_ctx); 1753 } 1754 1755 /* 1756 * Borrowed from AES_GMAC_Setkey(). 1757 */ 1758 static void 1759 ccr_init_gmac_hash(struct ccr_session *s, char *key, int klen) 1760 { 1761 static char zeroes[GMAC_BLOCK_LEN]; 1762 uint32_t keysched[4 * (RIJNDAEL_MAXNR + 1)]; 1763 int rounds; 1764 1765 rounds = rijndaelKeySetupEnc(keysched, key, klen); 1766 rijndaelEncrypt(keysched, rounds, zeroes, s->gmac.ghash_h); 1767 } 1768 1769 static int 1770 ccr_aes_check_keylen(int alg, int klen) 1771 { 1772 1773 switch (klen) { 1774 case 128: 1775 case 192: 1776 if (alg == CRYPTO_AES_XTS) 1777 return (EINVAL); 1778 break; 1779 case 256: 1780 break; 1781 case 512: 1782 if (alg != CRYPTO_AES_XTS) 1783 return (EINVAL); 1784 break; 1785 default: 1786 return (EINVAL); 1787 } 1788 return (0); 1789 } 1790 1791 /* 1792 * Borrowed from cesa_prep_aes_key(). We should perhaps have a public 1793 * function to generate this instead. 1794 * 1795 * NB: The crypto engine wants the words in the decryption key in reverse 1796 * order. 1797 */ 1798 static void 1799 ccr_aes_getdeckey(void *dec_key, const void *enc_key, unsigned int kbits) 1800 { 1801 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)]; 1802 uint32_t *dkey; 1803 int i; 1804 1805 rijndaelKeySetupEnc(ek, enc_key, kbits); 1806 dkey = dec_key; 1807 dkey += (kbits / 8) / 4; 1808 1809 switch (kbits) { 1810 case 128: 1811 for (i = 0; i < 4; i++) 1812 *--dkey = htobe32(ek[4 * 10 + i]); 1813 break; 1814 case 192: 1815 for (i = 0; i < 2; i++) 1816 *--dkey = htobe32(ek[4 * 11 + 2 + i]); 1817 for (i = 0; i < 4; i++) 1818 *--dkey = htobe32(ek[4 * 12 + i]); 1819 break; 1820 case 256: 1821 for (i = 0; i < 4; i++) 1822 *--dkey = htobe32(ek[4 * 13 + i]); 1823 for (i = 0; i < 4; i++) 1824 *--dkey = htobe32(ek[4 * 14 + i]); 1825 break; 1826 } 1827 MPASS(dkey == dec_key); 1828 } 1829 1830 static void 1831 ccr_aes_setkey(struct ccr_session *s, int alg, const void *key, int klen) 1832 { 1833 unsigned int ck_size, iopad_size, kctx_flits, kctx_len, kbits, mk_size; 1834 unsigned int opad_present; 1835 1836 if (alg == CRYPTO_AES_XTS) 1837 kbits = klen / 2; 1838 else 1839 kbits = klen; 1840 switch (kbits) { 1841 case 128: 1842 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_128; 1843 break; 1844 case 192: 1845 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_192; 1846 break; 1847 case 256: 1848 ck_size = CHCR_KEYCTX_CIPHER_KEY_SIZE_256; 1849 break; 1850 default: 1851 panic("should not get here"); 1852 } 1853 1854 s->blkcipher.key_len = klen / 8; 1855 memcpy(s->blkcipher.enckey, key, s->blkcipher.key_len); 1856 switch (alg) { 1857 case CRYPTO_AES_CBC: 1858 case CRYPTO_AES_XTS: 1859 ccr_aes_getdeckey(s->blkcipher.deckey, key, kbits); 1860 break; 1861 } 1862 1863 kctx_len = roundup2(s->blkcipher.key_len, 16); 1864 switch (s->mode) { 1865 case AUTHENC: 1866 mk_size = s->hmac.mk_size; 1867 opad_present = 1; 1868 iopad_size = roundup2(s->hmac.partial_digest_len, 16); 1869 kctx_len += iopad_size * 2; 1870 break; 1871 case GCM: 1872 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128; 1873 opad_present = 0; 1874 kctx_len += GMAC_BLOCK_LEN; 1875 break; 1876 default: 1877 mk_size = CHCR_KEYCTX_NO_KEY; 1878 opad_present = 0; 1879 break; 1880 } 1881 kctx_flits = (sizeof(struct _key_ctx) + kctx_len) / 16; 1882 s->blkcipher.key_ctx_hdr = htobe32(V_KEY_CONTEXT_CTX_LEN(kctx_flits) | 1883 V_KEY_CONTEXT_DUAL_CK(alg == CRYPTO_AES_XTS) | 1884 V_KEY_CONTEXT_OPAD_PRESENT(opad_present) | 1885 V_KEY_CONTEXT_SALT_PRESENT(1) | V_KEY_CONTEXT_CK_SIZE(ck_size) | 1886 V_KEY_CONTEXT_MK_SIZE(mk_size) | V_KEY_CONTEXT_VALID(1)); 1887 } 1888 1889 static int 1890 ccr_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri) 1891 { 1892 struct ccr_softc *sc; 1893 struct ccr_session *s; 1894 struct auth_hash *auth_hash; 1895 struct cryptoini *c, *hash, *cipher; 1896 unsigned int auth_mode, cipher_mode, iv_len, mk_size; 1897 unsigned int partial_digest_len; 1898 int error, i, sess; 1899 bool gcm_hash; 1900 1901 if (sidp == NULL || cri == NULL) 1902 return (EINVAL); 1903 1904 gcm_hash = false; 1905 cipher = NULL; 1906 hash = NULL; 1907 auth_hash = NULL; 1908 auth_mode = CHCR_SCMD_AUTH_MODE_NOP; 1909 cipher_mode = CHCR_SCMD_CIPHER_MODE_NOP; 1910 iv_len = 0; 1911 mk_size = 0; 1912 partial_digest_len = 0; 1913 for (c = cri; c != NULL; c = c->cri_next) { 1914 switch (c->cri_alg) { 1915 case CRYPTO_SHA1_HMAC: 1916 case CRYPTO_SHA2_256_HMAC: 1917 case CRYPTO_SHA2_384_HMAC: 1918 case CRYPTO_SHA2_512_HMAC: 1919 case CRYPTO_AES_128_NIST_GMAC: 1920 case CRYPTO_AES_192_NIST_GMAC: 1921 case CRYPTO_AES_256_NIST_GMAC: 1922 if (hash) 1923 return (EINVAL); 1924 hash = c; 1925 switch (c->cri_alg) { 1926 case CRYPTO_SHA1_HMAC: 1927 auth_hash = &auth_hash_hmac_sha1; 1928 auth_mode = CHCR_SCMD_AUTH_MODE_SHA1; 1929 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_160; 1930 partial_digest_len = SHA1_HASH_LEN; 1931 break; 1932 case CRYPTO_SHA2_256_HMAC: 1933 auth_hash = &auth_hash_hmac_sha2_256; 1934 auth_mode = CHCR_SCMD_AUTH_MODE_SHA256; 1935 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_256; 1936 partial_digest_len = SHA2_256_HASH_LEN; 1937 break; 1938 case CRYPTO_SHA2_384_HMAC: 1939 auth_hash = &auth_hash_hmac_sha2_384; 1940 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_384; 1941 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512; 1942 partial_digest_len = SHA2_512_HASH_LEN; 1943 break; 1944 case CRYPTO_SHA2_512_HMAC: 1945 auth_hash = &auth_hash_hmac_sha2_512; 1946 auth_mode = CHCR_SCMD_AUTH_MODE_SHA512_512; 1947 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_512; 1948 partial_digest_len = SHA2_512_HASH_LEN; 1949 break; 1950 case CRYPTO_AES_128_NIST_GMAC: 1951 case CRYPTO_AES_192_NIST_GMAC: 1952 case CRYPTO_AES_256_NIST_GMAC: 1953 gcm_hash = true; 1954 auth_mode = CHCR_SCMD_AUTH_MODE_GHASH; 1955 mk_size = CHCR_KEYCTX_MAC_KEY_SIZE_128; 1956 break; 1957 } 1958 break; 1959 case CRYPTO_AES_CBC: 1960 case CRYPTO_AES_ICM: 1961 case CRYPTO_AES_NIST_GCM_16: 1962 case CRYPTO_AES_XTS: 1963 if (cipher) 1964 return (EINVAL); 1965 cipher = c; 1966 switch (c->cri_alg) { 1967 case CRYPTO_AES_CBC: 1968 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CBC; 1969 iv_len = AES_BLOCK_LEN; 1970 break; 1971 case CRYPTO_AES_ICM: 1972 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_CTR; 1973 iv_len = AES_BLOCK_LEN; 1974 break; 1975 case CRYPTO_AES_NIST_GCM_16: 1976 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_GCM; 1977 iv_len = AES_GCM_IV_LEN; 1978 break; 1979 case CRYPTO_AES_XTS: 1980 cipher_mode = CHCR_SCMD_CIPHER_MODE_AES_XTS; 1981 iv_len = AES_BLOCK_LEN; 1982 break; 1983 } 1984 if (c->cri_key != NULL) { 1985 error = ccr_aes_check_keylen(c->cri_alg, 1986 c->cri_klen); 1987 if (error) 1988 return (error); 1989 } 1990 break; 1991 default: 1992 return (EINVAL); 1993 } 1994 } 1995 if (gcm_hash != (cipher_mode == CHCR_SCMD_CIPHER_MODE_AES_GCM)) 1996 return (EINVAL); 1997 if (hash == NULL && cipher == NULL) 1998 return (EINVAL); 1999 if (hash != NULL && hash->cri_key == NULL) 2000 return (EINVAL); 2001 2002 sc = device_get_softc(dev); 2003 mtx_lock(&sc->lock); 2004 if (sc->detaching) { 2005 mtx_unlock(&sc->lock); 2006 return (ENXIO); 2007 } 2008 sess = -1; 2009 for (i = 0; i < sc->nsessions; i++) { 2010 if (!sc->sessions[i].active && sc->sessions[i].pending == 0) { 2011 sess = i; 2012 break; 2013 } 2014 } 2015 if (sess == -1) { 2016 s = malloc(sizeof(*s) * (sc->nsessions + 1), M_CCR, 2017 M_NOWAIT | M_ZERO); 2018 if (s == NULL) { 2019 mtx_unlock(&sc->lock); 2020 return (ENOMEM); 2021 } 2022 if (sc->sessions != NULL) 2023 memcpy(s, sc->sessions, sizeof(*s) * sc->nsessions); 2024 sess = sc->nsessions; 2025 free(sc->sessions, M_CCR); 2026 sc->sessions = s; 2027 sc->nsessions++; 2028 } 2029 2030 s = &sc->sessions[sess]; 2031 2032 if (gcm_hash) 2033 s->mode = GCM; 2034 else if (hash != NULL && cipher != NULL) 2035 s->mode = AUTHENC; 2036 else if (hash != NULL) 2037 s->mode = HMAC; 2038 else { 2039 MPASS(cipher != NULL); 2040 s->mode = BLKCIPHER; 2041 } 2042 if (gcm_hash) { 2043 if (hash->cri_mlen == 0) 2044 s->gmac.hash_len = AES_GMAC_HASH_LEN; 2045 else 2046 s->gmac.hash_len = hash->cri_mlen; 2047 ccr_init_gmac_hash(s, hash->cri_key, hash->cri_klen); 2048 } else if (hash != NULL) { 2049 s->hmac.auth_hash = auth_hash; 2050 s->hmac.auth_mode = auth_mode; 2051 s->hmac.mk_size = mk_size; 2052 s->hmac.partial_digest_len = partial_digest_len; 2053 if (hash->cri_mlen == 0) 2054 s->hmac.hash_len = auth_hash->hashsize; 2055 else 2056 s->hmac.hash_len = hash->cri_mlen; 2057 ccr_init_hmac_digest(s, hash->cri_alg, hash->cri_key, 2058 hash->cri_klen); 2059 } 2060 if (cipher != NULL) { 2061 s->blkcipher.cipher_mode = cipher_mode; 2062 s->blkcipher.iv_len = iv_len; 2063 if (cipher->cri_key != NULL) 2064 ccr_aes_setkey(s, cipher->cri_alg, cipher->cri_key, 2065 cipher->cri_klen); 2066 } 2067 2068 s->active = true; 2069 mtx_unlock(&sc->lock); 2070 2071 *sidp = sess; 2072 return (0); 2073 } 2074 2075 static int 2076 ccr_freesession(device_t dev, uint64_t tid) 2077 { 2078 struct ccr_softc *sc; 2079 uint32_t sid; 2080 int error; 2081 2082 sc = device_get_softc(dev); 2083 sid = CRYPTO_SESID2LID(tid); 2084 mtx_lock(&sc->lock); 2085 if (sid >= sc->nsessions || !sc->sessions[sid].active) 2086 error = EINVAL; 2087 else { 2088 if (sc->sessions[sid].pending != 0) 2089 device_printf(dev, 2090 "session %d freed with %d pending requests\n", sid, 2091 sc->sessions[sid].pending); 2092 sc->sessions[sid].active = false; 2093 error = 0; 2094 } 2095 mtx_unlock(&sc->lock); 2096 return (error); 2097 } 2098 2099 static int 2100 ccr_process(device_t dev, struct cryptop *crp, int hint) 2101 { 2102 struct ccr_softc *sc; 2103 struct ccr_session *s; 2104 struct cryptodesc *crd, *crda, *crde; 2105 uint32_t sid; 2106 int error; 2107 2108 if (crp == NULL) 2109 return (EINVAL); 2110 2111 crd = crp->crp_desc; 2112 sid = CRYPTO_SESID2LID(crp->crp_sid); 2113 sc = device_get_softc(dev); 2114 mtx_lock(&sc->lock); 2115 if (sid >= sc->nsessions || !sc->sessions[sid].active) { 2116 sc->stats_bad_session++; 2117 error = EINVAL; 2118 goto out; 2119 } 2120 2121 error = ccr_populate_sglist(sc->sg_crp, crp); 2122 if (error) { 2123 sc->stats_sglist_error++; 2124 goto out; 2125 } 2126 2127 s = &sc->sessions[sid]; 2128 switch (s->mode) { 2129 case HMAC: 2130 if (crd->crd_flags & CRD_F_KEY_EXPLICIT) 2131 ccr_init_hmac_digest(s, crd->crd_alg, crd->crd_key, 2132 crd->crd_klen); 2133 error = ccr_hmac(sc, sid, s, crp); 2134 if (error == 0) 2135 sc->stats_hmac++; 2136 break; 2137 case BLKCIPHER: 2138 if (crd->crd_flags & CRD_F_KEY_EXPLICIT) { 2139 error = ccr_aes_check_keylen(crd->crd_alg, 2140 crd->crd_klen); 2141 if (error) 2142 break; 2143 ccr_aes_setkey(s, crd->crd_alg, crd->crd_key, 2144 crd->crd_klen); 2145 } 2146 error = ccr_blkcipher(sc, sid, s, crp); 2147 if (error == 0) { 2148 if (crd->crd_flags & CRD_F_ENCRYPT) 2149 sc->stats_blkcipher_encrypt++; 2150 else 2151 sc->stats_blkcipher_decrypt++; 2152 } 2153 break; 2154 case AUTHENC: 2155 error = 0; 2156 switch (crd->crd_alg) { 2157 case CRYPTO_AES_CBC: 2158 case CRYPTO_AES_ICM: 2159 case CRYPTO_AES_XTS: 2160 /* Only encrypt-then-authenticate supported. */ 2161 crde = crd; 2162 crda = crd->crd_next; 2163 if (!(crde->crd_flags & CRD_F_ENCRYPT)) { 2164 error = EINVAL; 2165 break; 2166 } 2167 break; 2168 default: 2169 crda = crd; 2170 crde = crd->crd_next; 2171 if (crde->crd_flags & CRD_F_ENCRYPT) { 2172 error = EINVAL; 2173 break; 2174 } 2175 break; 2176 } 2177 if (error) 2178 break; 2179 if (crda->crd_flags & CRD_F_KEY_EXPLICIT) 2180 ccr_init_hmac_digest(s, crda->crd_alg, crda->crd_key, 2181 crda->crd_klen); 2182 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) { 2183 error = ccr_aes_check_keylen(crde->crd_alg, 2184 crde->crd_klen); 2185 if (error) 2186 break; 2187 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key, 2188 crde->crd_klen); 2189 } 2190 error = ccr_authenc(sc, sid, s, crp, crda, crde); 2191 if (error == 0) { 2192 if (crde->crd_flags & CRD_F_ENCRYPT) 2193 sc->stats_authenc_encrypt++; 2194 else 2195 sc->stats_authenc_decrypt++; 2196 } 2197 break; 2198 case GCM: 2199 error = 0; 2200 if (crd->crd_alg == CRYPTO_AES_NIST_GCM_16) { 2201 crde = crd; 2202 crda = crd->crd_next; 2203 } else { 2204 crda = crd; 2205 crde = crd->crd_next; 2206 } 2207 if (crda->crd_flags & CRD_F_KEY_EXPLICIT) 2208 ccr_init_gmac_hash(s, crda->crd_key, crda->crd_klen); 2209 if (crde->crd_flags & CRD_F_KEY_EXPLICIT) { 2210 error = ccr_aes_check_keylen(crde->crd_alg, 2211 crde->crd_klen); 2212 if (error) 2213 break; 2214 ccr_aes_setkey(s, crde->crd_alg, crde->crd_key, 2215 crde->crd_klen); 2216 } 2217 if (crde->crd_len == 0) { 2218 mtx_unlock(&sc->lock); 2219 ccr_gcm_soft(s, crp, crda, crde); 2220 return (0); 2221 } 2222 error = ccr_gcm(sc, sid, s, crp, crda, crde); 2223 if (error == EMSGSIZE) { 2224 sc->stats_sw_fallback++; 2225 mtx_unlock(&sc->lock); 2226 ccr_gcm_soft(s, crp, crda, crde); 2227 return (0); 2228 } 2229 if (error == 0) { 2230 if (crde->crd_flags & CRD_F_ENCRYPT) 2231 sc->stats_gcm_encrypt++; 2232 else 2233 sc->stats_gcm_decrypt++; 2234 } 2235 break; 2236 } 2237 2238 if (error == 0) { 2239 s->pending++; 2240 sc->stats_inflight++; 2241 } else 2242 sc->stats_process_error++; 2243 2244 out: 2245 mtx_unlock(&sc->lock); 2246 2247 if (error) { 2248 crp->crp_etype = error; 2249 crypto_done(crp); 2250 } 2251 2252 return (0); 2253 } 2254 2255 static int 2256 do_cpl6_fw_pld(struct sge_iq *iq, const struct rss_header *rss, 2257 struct mbuf *m) 2258 { 2259 struct ccr_softc *sc = iq->adapter->ccr_softc; 2260 struct ccr_session *s; 2261 const struct cpl_fw6_pld *cpl; 2262 struct cryptop *crp; 2263 uint32_t sid, status; 2264 int error; 2265 2266 if (m != NULL) 2267 cpl = mtod(m, const void *); 2268 else 2269 cpl = (const void *)(rss + 1); 2270 2271 crp = (struct cryptop *)(uintptr_t)be64toh(cpl->data[1]); 2272 sid = CRYPTO_SESID2LID(crp->crp_sid); 2273 status = be64toh(cpl->data[0]); 2274 if (CHK_MAC_ERR_BIT(status) || CHK_PAD_ERR_BIT(status)) 2275 error = EBADMSG; 2276 else 2277 error = 0; 2278 2279 mtx_lock(&sc->lock); 2280 MPASS(sid < sc->nsessions); 2281 s = &sc->sessions[sid]; 2282 s->pending--; 2283 sc->stats_inflight--; 2284 2285 switch (s->mode) { 2286 case HMAC: 2287 error = ccr_hmac_done(sc, s, crp, cpl, error); 2288 break; 2289 case BLKCIPHER: 2290 error = ccr_blkcipher_done(sc, s, crp, cpl, error); 2291 break; 2292 case AUTHENC: 2293 error = ccr_authenc_done(sc, s, crp, cpl, error); 2294 break; 2295 case GCM: 2296 error = ccr_gcm_done(sc, s, crp, cpl, error); 2297 break; 2298 } 2299 2300 if (error == EBADMSG) { 2301 if (CHK_MAC_ERR_BIT(status)) 2302 sc->stats_mac_error++; 2303 if (CHK_PAD_ERR_BIT(status)) 2304 sc->stats_pad_error++; 2305 } 2306 mtx_unlock(&sc->lock); 2307 crp->crp_etype = error; 2308 crypto_done(crp); 2309 m_freem(m); 2310 return (0); 2311 } 2312 2313 static int 2314 ccr_modevent(module_t mod, int cmd, void *arg) 2315 { 2316 2317 switch (cmd) { 2318 case MOD_LOAD: 2319 t4_register_cpl_handler(CPL_FW6_PLD, do_cpl6_fw_pld); 2320 return (0); 2321 case MOD_UNLOAD: 2322 t4_register_cpl_handler(CPL_FW6_PLD, NULL); 2323 return (0); 2324 default: 2325 return (EOPNOTSUPP); 2326 } 2327 } 2328 2329 static device_method_t ccr_methods[] = { 2330 DEVMETHOD(device_identify, ccr_identify), 2331 DEVMETHOD(device_probe, ccr_probe), 2332 DEVMETHOD(device_attach, ccr_attach), 2333 DEVMETHOD(device_detach, ccr_detach), 2334 2335 DEVMETHOD(cryptodev_newsession, ccr_newsession), 2336 DEVMETHOD(cryptodev_freesession, ccr_freesession), 2337 DEVMETHOD(cryptodev_process, ccr_process), 2338 2339 DEVMETHOD_END 2340 }; 2341 2342 static driver_t ccr_driver = { 2343 "ccr", 2344 ccr_methods, 2345 sizeof(struct ccr_softc) 2346 }; 2347 2348 static devclass_t ccr_devclass; 2349 2350 DRIVER_MODULE(ccr, t6nex, ccr_driver, ccr_devclass, ccr_modevent, NULL); 2351 MODULE_VERSION(ccr, 1); 2352 MODULE_DEPEND(ccr, crypto, 1, 1, 1); 2353 MODULE_DEPEND(ccr, t6nex, 1, 1, 1); 2354