1 /*- 2 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 /* This file is automatically generated --- changes will be lost */ 31 32 #ifndef _T4_TCB_DEFS_H 33 #define _T4_TCB_DEFS_H 34 35 /* 3:0 */ 36 #define W_TCB_ULP_TYPE 0 37 #define S_TCB_ULP_TYPE 0 38 #define M_TCB_ULP_TYPE 0xfULL 39 #define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) 40 41 /* 11:4 */ 42 #define W_TCB_ULP_RAW 0 43 #define S_TCB_ULP_RAW 4 44 #define M_TCB_ULP_RAW 0xffULL 45 #define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) 46 47 /* 23:12 */ 48 #define W_TCB_L2T_IX 0 49 #define S_TCB_L2T_IX 12 50 #define M_TCB_L2T_IX 0xfffULL 51 #define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) 52 53 /* 31:24 */ 54 #define W_TCB_SMAC_SEL 0 55 #define S_TCB_SMAC_SEL 24 56 #define M_TCB_SMAC_SEL 0xffULL 57 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) 58 59 /* 95:32 */ 60 #define W_TCB_T_FLAGS 1 61 #define S_TCB_T_FLAGS 0 62 #define M_TCB_T_FLAGS 0xffffffffffffffffULL 63 #define V_TCB_T_FLAGS(x) ((__u64)(x) << S_TCB_T_FLAGS) 64 65 /* 105:96 */ 66 #define W_TCB_RSS_INFO 3 67 #define S_TCB_RSS_INFO 0 68 #define M_TCB_RSS_INFO 0x3ffULL 69 #define V_TCB_RSS_INFO(x) ((x) << S_TCB_RSS_INFO) 70 71 /* 111:106 */ 72 #define W_TCB_TOS 3 73 #define S_TCB_TOS 10 74 #define M_TCB_TOS 0x3fULL 75 #define V_TCB_TOS(x) ((x) << S_TCB_TOS) 76 77 /* 115:112 */ 78 #define W_TCB_T_STATE 3 79 #define S_TCB_T_STATE 16 80 #define M_TCB_T_STATE 0xfULL 81 #define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) 82 83 /* 119:116 */ 84 #define W_TCB_MAX_RT 3 85 #define S_TCB_MAX_RT 20 86 #define M_TCB_MAX_RT 0xfULL 87 #define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) 88 89 /* 123:120 */ 90 #define W_TCB_T_MAXSEG 3 91 #define S_TCB_T_MAXSEG 24 92 #define M_TCB_T_MAXSEG 0xfULL 93 #define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) 94 95 /* 127:124 */ 96 #define W_TCB_SND_SCALE 3 97 #define S_TCB_SND_SCALE 28 98 #define M_TCB_SND_SCALE 0xfULL 99 #define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) 100 101 /* 131:128 */ 102 #define W_TCB_RCV_SCALE 4 103 #define S_TCB_RCV_SCALE 0 104 #define M_TCB_RCV_SCALE 0xfULL 105 #define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) 106 107 /* 135:132 */ 108 #define W_TCB_T_RXTSHIFT 4 109 #define S_TCB_T_RXTSHIFT 4 110 #define M_TCB_T_RXTSHIFT 0xfULL 111 #define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) 112 113 /* 139:136 */ 114 #define W_TCB_T_DUPACKS 4 115 #define S_TCB_T_DUPACKS 8 116 #define M_TCB_T_DUPACKS 0xfULL 117 #define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) 118 119 /* 143:140 */ 120 #define W_TCB_TIMESTAMP_OFFSET 4 121 #define S_TCB_TIMESTAMP_OFFSET 12 122 #define M_TCB_TIMESTAMP_OFFSET 0xfULL 123 #define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) 124 125 /* 159:144 */ 126 #define W_TCB_RCV_ADV 4 127 #define S_TCB_RCV_ADV 16 128 #define M_TCB_RCV_ADV 0xffffULL 129 #define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) 130 131 /* 191:160 */ 132 #define W_TCB_TIMESTAMP 5 133 #define S_TCB_TIMESTAMP 0 134 #define M_TCB_TIMESTAMP 0xffffffffULL 135 #define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) 136 137 /* 223:192 */ 138 #define W_TCB_T_RTT_TS_RECENT_AGE 6 139 #define S_TCB_T_RTT_TS_RECENT_AGE 0 140 #define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL 141 #define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) 142 143 /* 255:224 */ 144 #define W_TCB_T_RTSEQ_RECENT 7 145 #define S_TCB_T_RTSEQ_RECENT 0 146 #define M_TCB_T_RTSEQ_RECENT 0xffffffffULL 147 #define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) 148 149 /* 271:256 */ 150 #define W_TCB_T_SRTT 8 151 #define S_TCB_T_SRTT 0 152 #define M_TCB_T_SRTT 0xffffULL 153 #define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) 154 155 /* 287:272 */ 156 #define W_TCB_T_RTTVAR 8 157 #define S_TCB_T_RTTVAR 16 158 #define M_TCB_T_RTTVAR 0xffffULL 159 #define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) 160 161 /* 319:288 */ 162 #define W_TCB_TX_MAX 9 163 #define S_TCB_TX_MAX 0 164 #define M_TCB_TX_MAX 0xffffffffULL 165 #define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) 166 167 /* 347:320 */ 168 #define W_TCB_SND_UNA_RAW 10 169 #define S_TCB_SND_UNA_RAW 0 170 #define M_TCB_SND_UNA_RAW 0xfffffffULL 171 #define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) 172 173 /* 375:348 */ 174 #define W_TCB_SND_NXT_RAW 10 175 #define S_TCB_SND_NXT_RAW 28 176 #define M_TCB_SND_NXT_RAW 0xfffffffULL 177 #define V_TCB_SND_NXT_RAW(x) ((__u64)(x) << S_TCB_SND_NXT_RAW) 178 179 /* 403:376 */ 180 #define W_TCB_SND_MAX_RAW 11 181 #define S_TCB_SND_MAX_RAW 24 182 #define M_TCB_SND_MAX_RAW 0xfffffffULL 183 #define V_TCB_SND_MAX_RAW(x) ((__u64)(x) << S_TCB_SND_MAX_RAW) 184 185 /* 431:404 */ 186 #define W_TCB_SND_REC_RAW 12 187 #define S_TCB_SND_REC_RAW 20 188 #define M_TCB_SND_REC_RAW 0xfffffffULL 189 #define V_TCB_SND_REC_RAW(x) ((__u64)(x) << S_TCB_SND_REC_RAW) 190 191 /* 459:432 */ 192 #define W_TCB_SND_CWND 13 193 #define S_TCB_SND_CWND 16 194 #define M_TCB_SND_CWND 0xfffffffULL 195 #define V_TCB_SND_CWND(x) ((__u64)(x) << S_TCB_SND_CWND) 196 197 /* 487:460 */ 198 #define W_TCB_SND_SSTHRESH 14 199 #define S_TCB_SND_SSTHRESH 12 200 #define M_TCB_SND_SSTHRESH 0xfffffffULL 201 #define V_TCB_SND_SSTHRESH(x) ((__u64)(x) << S_TCB_SND_SSTHRESH) 202 203 /* 504:488 */ 204 #define W_TCB_TX_HDR_PTR_RAW 15 205 #define S_TCB_TX_HDR_PTR_RAW 8 206 #define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL 207 #define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) 208 209 /* 521:505 */ 210 #define W_TCB_TX_LAST_PTR_RAW 15 211 #define S_TCB_TX_LAST_PTR_RAW 25 212 #define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL 213 #define V_TCB_TX_LAST_PTR_RAW(x) ((__u64)(x) << S_TCB_TX_LAST_PTR_RAW) 214 215 /* 553:522 */ 216 #define W_TCB_RCV_NXT 16 217 #define S_TCB_RCV_NXT 10 218 #define M_TCB_RCV_NXT 0xffffffffULL 219 #define V_TCB_RCV_NXT(x) ((__u64)(x) << S_TCB_RCV_NXT) 220 221 /* 581:554 */ 222 #define W_TCB_RCV_WND 17 223 #define S_TCB_RCV_WND 10 224 #define M_TCB_RCV_WND 0xfffffffULL 225 #define V_TCB_RCV_WND(x) ((__u64)(x) << S_TCB_RCV_WND) 226 227 /* 609:582 */ 228 #define W_TCB_RX_HDR_OFFSET 18 229 #define S_TCB_RX_HDR_OFFSET 6 230 #define M_TCB_RX_HDR_OFFSET 0xfffffffULL 231 #define V_TCB_RX_HDR_OFFSET(x) ((__u64)(x) << S_TCB_RX_HDR_OFFSET) 232 233 /* 637:610 */ 234 #define W_TCB_TS_LAST_ACK_SENT_RAW 19 235 #define S_TCB_TS_LAST_ACK_SENT_RAW 2 236 #define M_TCB_TS_LAST_ACK_SENT_RAW 0xfffffffULL 237 #define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) 238 239 /* 665:638 */ 240 #define W_TCB_RX_FRAG0_START_IDX_RAW 19 241 #define S_TCB_RX_FRAG0_START_IDX_RAW 30 242 #define M_TCB_RX_FRAG0_START_IDX_RAW 0xfffffffULL 243 #define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG0_START_IDX_RAW) 244 245 /* 693:666 */ 246 #define W_TCB_RX_FRAG1_START_IDX_OFFSET 20 247 #define S_TCB_RX_FRAG1_START_IDX_OFFSET 26 248 #define M_TCB_RX_FRAG1_START_IDX_OFFSET 0xfffffffULL 249 #define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((__u64)(x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) 250 251 /* 721:694 */ 252 #define W_TCB_RX_FRAG0_LEN 21 253 #define S_TCB_RX_FRAG0_LEN 22 254 #define M_TCB_RX_FRAG0_LEN 0xfffffffULL 255 #define V_TCB_RX_FRAG0_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG0_LEN) 256 257 /* 749:722 */ 258 #define W_TCB_RX_FRAG1_LEN 22 259 #define S_TCB_RX_FRAG1_LEN 18 260 #define M_TCB_RX_FRAG1_LEN 0xfffffffULL 261 #define V_TCB_RX_FRAG1_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG1_LEN) 262 263 /* 765:750 */ 264 #define W_TCB_PDU_LEN 23 265 #define S_TCB_PDU_LEN 14 266 #define M_TCB_PDU_LEN 0xffffULL 267 #define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) 268 269 /* 782:766 */ 270 #define W_TCB_RX_PTR_RAW 23 271 #define S_TCB_RX_PTR_RAW 30 272 #define M_TCB_RX_PTR_RAW 0x1ffffULL 273 #define V_TCB_RX_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_PTR_RAW) 274 275 /* 799:783 */ 276 #define W_TCB_RX_FRAG1_PTR_RAW 24 277 #define S_TCB_RX_FRAG1_PTR_RAW 15 278 #define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL 279 #define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) 280 281 /* 831:800 */ 282 #define W_TCB_MAIN_SLUSH 25 283 #define S_TCB_MAIN_SLUSH 0 284 #define M_TCB_MAIN_SLUSH 0xffffffffULL 285 #define V_TCB_MAIN_SLUSH(x) ((x) << S_TCB_MAIN_SLUSH) 286 287 /* 846:832 */ 288 #define W_TCB_AUX1_SLUSH0 26 289 #define S_TCB_AUX1_SLUSH0 0 290 #define M_TCB_AUX1_SLUSH0 0x7fffULL 291 #define V_TCB_AUX1_SLUSH0(x) ((x) << S_TCB_AUX1_SLUSH0) 292 293 /* 874:847 */ 294 #define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 295 #define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 296 #define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0xfffffffULL 297 #define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) 298 299 /* 891:875 */ 300 #define W_TCB_RX_FRAG2_PTR_RAW 27 301 #define S_TCB_RX_FRAG2_PTR_RAW 11 302 #define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL 303 #define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) 304 305 /* 919:892 */ 306 #define W_TCB_RX_FRAG2_LEN_RAW 27 307 #define S_TCB_RX_FRAG2_LEN_RAW 28 308 #define M_TCB_RX_FRAG2_LEN_RAW 0xfffffffULL 309 #define V_TCB_RX_FRAG2_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_LEN_RAW) 310 311 /* 936:920 */ 312 #define W_TCB_RX_FRAG3_PTR_RAW 28 313 #define S_TCB_RX_FRAG3_PTR_RAW 24 314 #define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL 315 #define V_TCB_RX_FRAG3_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_PTR_RAW) 316 317 /* 964:937 */ 318 #define W_TCB_RX_FRAG3_LEN_RAW 29 319 #define S_TCB_RX_FRAG3_LEN_RAW 9 320 #define M_TCB_RX_FRAG3_LEN_RAW 0xfffffffULL 321 #define V_TCB_RX_FRAG3_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_LEN_RAW) 322 323 /* 992:965 */ 324 #define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 325 #define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 5 326 #define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0xfffffffULL 327 #define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) 328 329 /* 1000:993 */ 330 #define W_TCB_PDU_HDR_LEN 31 331 #define S_TCB_PDU_HDR_LEN 1 332 #define M_TCB_PDU_HDR_LEN 0xffULL 333 #define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) 334 335 /* 1019:1001 */ 336 #define W_TCB_AUX1_SLUSH1 31 337 #define S_TCB_AUX1_SLUSH1 9 338 #define M_TCB_AUX1_SLUSH1 0x7ffffULL 339 #define V_TCB_AUX1_SLUSH1(x) ((x) << S_TCB_AUX1_SLUSH1) 340 341 /* 1023:1020 */ 342 #define W_TCB_ULP_EXT 31 343 #define S_TCP_ULP_EXT 28 344 #define M_TCB_ULP_EXT 0xfULL 345 #define V_TCB_ULP_EXT(x) ((x) << S_TCP_ULP_EXT) 346 347 348 /* 840:832 */ 349 #define W_TCB_IRS_ULP 26 350 #define S_TCB_IRS_ULP 0 351 #define M_TCB_IRS_ULP 0x1ffULL 352 #define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) 353 354 /* 849:841 */ 355 #define W_TCB_ISS_ULP 26 356 #define S_TCB_ISS_ULP 9 357 #define M_TCB_ISS_ULP 0x1ffULL 358 #define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) 359 360 /* 863:850 */ 361 #define W_TCB_TX_PDU_LEN 26 362 #define S_TCB_TX_PDU_LEN 18 363 #define M_TCB_TX_PDU_LEN 0x3fffULL 364 #define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) 365 366 /* 879:864 */ 367 #define W_TCB_CQ_IDX_SQ 27 368 #define S_TCB_CQ_IDX_SQ 0 369 #define M_TCB_CQ_IDX_SQ 0xffffULL 370 #define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) 371 372 /* 895:880 */ 373 #define W_TCB_CQ_IDX_RQ 27 374 #define S_TCB_CQ_IDX_RQ 16 375 #define M_TCB_CQ_IDX_RQ 0xffffULL 376 #define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) 377 378 /* 911:896 */ 379 #define W_TCB_QP_ID 28 380 #define S_TCB_QP_ID 0 381 #define M_TCB_QP_ID 0xffffULL 382 #define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) 383 384 /* 927:912 */ 385 #define W_TCB_PD_ID 28 386 #define S_TCB_PD_ID 16 387 #define M_TCB_PD_ID 0xffffULL 388 #define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) 389 390 /* 959:928 */ 391 #define W_TCB_STAG 29 392 #define S_TCB_STAG 0 393 #define M_TCB_STAG 0xffffffffULL 394 #define V_TCB_STAG(x) ((x) << S_TCB_STAG) 395 396 /* 985:960 */ 397 #define W_TCB_RQ_START 30 398 #define S_TCB_RQ_START 0 399 #define M_TCB_RQ_START 0x3ffffffULL 400 #define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) 401 402 /* 998:986 */ 403 #define W_TCB_RQ_MSN 30 404 #define S_TCB_RQ_MSN 26 405 #define M_TCB_RQ_MSN 0x1fffULL 406 #define V_TCB_RQ_MSN(x) ((__u64)(x) << S_TCB_RQ_MSN) 407 408 /* 1002:999 */ 409 #define W_TCB_RQ_MAX_OFFSET 31 410 #define S_TCB_RQ_MAX_OFFSET 7 411 #define M_TCB_RQ_MAX_OFFSET 0xfULL 412 #define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) 413 414 /* 1015:1003 */ 415 #define W_TCB_RQ_WRITE_PTR 31 416 #define S_TCB_RQ_WRITE_PTR 11 417 #define M_TCB_RQ_WRITE_PTR 0x1fffULL 418 #define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) 419 420 /* 1019:1016 */ 421 #define W_TCB_RDMAP_OPCODE 31 422 #define S_TCB_RDMAP_OPCODE 24 423 #define M_TCB_RDMAP_OPCODE 0xfULL 424 #define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) 425 426 /* 1020:1020 */ 427 #define W_TCB_ORD_L_BIT_VLD 31 428 #define S_TCB_ORD_L_BIT_VLD 28 429 #define M_TCB_ORD_L_BIT_VLD 0x1ULL 430 #define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) 431 432 /* 1021:1021 */ 433 #define W_TCB_TX_FLUSH 31 434 #define S_TCB_TX_FLUSH 29 435 #define M_TCB_TX_FLUSH 0x1ULL 436 #define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) 437 438 /* 1022:1022 */ 439 #define W_TCB_TX_OOS_RXMT 31 440 #define S_TCB_TX_OOS_RXMT 30 441 #define M_TCB_TX_OOS_RXMT 0x1ULL 442 #define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) 443 444 /* 1023:1023 */ 445 #define W_TCB_TX_OOS_TXMT 31 446 #define S_TCB_TX_OOS_TXMT 31 447 #define M_TCB_TX_OOS_TXMT 0x1ULL 448 #define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) 449 450 /* 855:832 */ 451 #define W_TCB_RX_DDP_BUF0_OFFSET 26 452 #define S_TCB_RX_DDP_BUF0_OFFSET 0 453 #define M_TCB_RX_DDP_BUF0_OFFSET 0xffffffULL 454 #define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) 455 456 /* 879:856 */ 457 #define W_TCB_RX_DDP_BUF0_LEN 26 458 #define S_TCB_RX_DDP_BUF0_LEN 24 459 #define M_TCB_RX_DDP_BUF0_LEN 0xffffffULL 460 #define V_TCB_RX_DDP_BUF0_LEN(x) ((__u64)(x) << S_TCB_RX_DDP_BUF0_LEN) 461 462 /* 903:880 */ 463 #define W_TCB_RX_DDP_FLAGS 27 464 #define S_TCB_RX_DDP_FLAGS 16 465 #define M_TCB_RX_DDP_FLAGS 0xffffffULL 466 #define V_TCB_RX_DDP_FLAGS(x) ((__u64)(x) << S_TCB_RX_DDP_FLAGS) 467 468 /* 927:904 */ 469 #define W_TCB_RX_DDP_BUF1_OFFSET 28 470 #define S_TCB_RX_DDP_BUF1_OFFSET 8 471 #define M_TCB_RX_DDP_BUF1_OFFSET 0xffffffULL 472 #define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) 473 474 /* 951:928 */ 475 #define W_TCB_RX_DDP_BUF1_LEN 29 476 #define S_TCB_RX_DDP_BUF1_LEN 0 477 #define M_TCB_RX_DDP_BUF1_LEN 0xffffffULL 478 #define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) 479 480 /* 959:952 */ 481 #define W_TCB_AUX3_SLUSH 29 482 #define S_TCB_AUX3_SLUSH 24 483 #define M_TCB_AUX3_SLUSH 0xffULL 484 #define V_TCB_AUX3_SLUSH(x) ((x) << S_TCB_AUX3_SLUSH) 485 486 /* 991:960 */ 487 #define W_TCB_RX_DDP_BUF0_TAG 30 488 #define S_TCB_RX_DDP_BUF0_TAG 0 489 #define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL 490 #define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) 491 492 /* 1023:992 */ 493 #define W_TCB_RX_DDP_BUF1_TAG 31 494 #define S_TCB_RX_DDP_BUF1_TAG 0 495 #define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL 496 #define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) 497 498 #define S_TF_MIGRATING 0 499 #define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) 500 501 #define S_TF_NON_OFFLOAD 1 502 #define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) 503 504 #define S_TF_LOCK_TID 2 505 #define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) 506 507 #define S_TF_KEEPALIVE 3 508 #define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) 509 510 #define S_TF_DACK 4 511 #define V_TF_DACK(x) ((x) << S_TF_DACK) 512 513 #define S_TF_DACK_MSS 5 514 #define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) 515 516 #define S_TF_DACK_NOT_ACKED 6 517 #define V_TF_DACK_NOT_ACKED(x) ((x) << S_TF_DACK_NOT_ACKED) 518 519 #define S_TF_NAGLE 7 520 #define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) 521 522 #define S_TF_SSWS_DISABLED 8 523 #define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) 524 525 #define S_TF_RX_FLOW_CONTROL_DDP 9 526 #define V_TF_RX_FLOW_CONTROL_DDP(x) ((x) << S_TF_RX_FLOW_CONTROL_DDP) 527 528 #define S_TF_RX_FLOW_CONTROL_DISABLE 10 529 #define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) 530 531 #define S_TF_RX_CHANNEL 11 532 #define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) 533 534 #define S_TF_TX_CHANNEL0 12 535 #define V_TF_TX_CHANNEL0(x) ((x) << S_TF_TX_CHANNEL0) 536 537 #define S_TF_TX_CHANNEL1 13 538 #define V_TF_TX_CHANNEL1(x) ((x) << S_TF_TX_CHANNEL1) 539 540 #define S_TF_TX_QUIESCE 14 541 #define V_TF_TX_QUIESCE(x) ((x) << S_TF_TX_QUIESCE) 542 543 #define S_TF_RX_QUIESCE 15 544 #define V_TF_RX_QUIESCE(x) ((x) << S_TF_RX_QUIESCE) 545 546 #define S_TF_TX_PACE_AUTO 16 547 #define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) 548 549 #define S_TF_MASK_HASH 16 550 #define V_TF_MASK_HASH(x) ((x) << S_TF_MASK_HASH) 551 552 #define S_TF_TX_PACE_FIXED 17 553 #define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) 554 555 #define S_TF_DIRECT_STEER_HASH 17 556 #define V_TF_DIRECT_STEER_HASH(x) ((x) << S_TF_DIRECT_STEER_HASH) 557 558 #define S_TF_TX_QUEUE 18 559 #define M_TF_TX_QUEUE 0x7ULL 560 #define V_TF_TX_QUEUE(x) ((x) << S_TF_TX_QUEUE) 561 562 #define S_TF_TURBO 21 563 #define V_TF_TURBO(x) ((x) << S_TF_TURBO) 564 565 #define S_TF_REPORT_TID 21 566 #define V_TF_REPORT_TID(x) ((x) << S_TF_REPORT_TID) 567 568 #define S_TF_CCTRL_SEL0 22 569 #define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) 570 571 #define S_TF_DROP 22 572 #define V_TF_DROP(x) ((x) << S_TF_DROP) 573 574 #define S_TF_CCTRL_SEL1 23 575 #define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) 576 577 #define S_TF_DIRECT_STEER 23 578 #define V_TF_DIRECT_STEER(x) ((x) << S_TF_DIRECT_STEER) 579 580 #define S_TF_CORE_FIN 24 581 #define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) 582 583 #define S_TF_CORE_URG 25 584 #define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) 585 586 #define S_TF_CORE_MORE 26 587 #define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) 588 589 #define S_TF_CORE_PUSH 27 590 #define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) 591 592 #define S_TF_CORE_FLUSH 28 593 #define V_TF_CORE_FLUSH(x) ((x) << S_TF_CORE_FLUSH) 594 595 #define S_TF_RCV_COALESCE_ENABLE 29 596 #define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) 597 598 #define S_TF_RCV_COALESCE_PUSH 30 599 #define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) 600 601 #define S_TF_RCV_COALESCE_LAST_PSH 31 602 #define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) 603 604 #define S_TF_RCV_COALESCE_HEARTBEAT 32 605 #define V_TF_RCV_COALESCE_HEARTBEAT(x) ((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT) 606 607 #define S_TF_INIT 33 608 #define V_TF_INIT(x) ((__u64)(x) << S_TF_INIT) 609 610 #define S_TF_ACTIVE_OPEN 34 611 #define V_TF_ACTIVE_OPEN(x) ((__u64)(x) << S_TF_ACTIVE_OPEN) 612 613 #define S_TF_ASK_MODE 35 614 #define V_TF_ASK_MODE(x) ((__u64)(x) << S_TF_ASK_MODE) 615 616 #define S_TF_MOD_SCHD_REASON0 36 617 #define V_TF_MOD_SCHD_REASON0(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON0) 618 619 #define S_TF_MOD_SCHD_REASON1 37 620 #define V_TF_MOD_SCHD_REASON1(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON1) 621 622 #define S_TF_MOD_SCHD_REASON2 38 623 #define V_TF_MOD_SCHD_REASON2(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON2) 624 625 #define S_TF_MOD_SCHD_TX 39 626 #define V_TF_MOD_SCHD_TX(x) ((__u64)(x) << S_TF_MOD_SCHD_TX) 627 628 #define S_TF_MOD_SCHD_RX 40 629 #define V_TF_MOD_SCHD_RX(x) ((__u64)(x) << S_TF_MOD_SCHD_RX) 630 631 #define S_TF_TIMER 41 632 #define V_TF_TIMER(x) ((__u64)(x) << S_TF_TIMER) 633 634 #define S_TF_DACK_TIMER 42 635 #define V_TF_DACK_TIMER(x) ((__u64)(x) << S_TF_DACK_TIMER) 636 637 #define S_TF_PEER_FIN 43 638 #define V_TF_PEER_FIN(x) ((__u64)(x) << S_TF_PEER_FIN) 639 640 #define S_TF_TX_COMPACT 44 641 #define V_TF_TX_COMPACT(x) ((__u64)(x) << S_TF_TX_COMPACT) 642 643 #define S_TF_RX_COMPACT 45 644 #define V_TF_RX_COMPACT(x) ((__u64)(x) << S_TF_RX_COMPACT) 645 646 #define S_TF_RDMA_ERROR 46 647 #define V_TF_RDMA_ERROR(x) ((__u64)(x) << S_TF_RDMA_ERROR) 648 649 #define S_TF_RDMA_FLM_ERROR 47 650 #define V_TF_RDMA_FLM_ERROR(x) ((__u64)(x) << S_TF_RDMA_FLM_ERROR) 651 652 #define S_TF_TX_PDU_OUT 48 653 #define V_TF_TX_PDU_OUT(x) ((__u64)(x) << S_TF_TX_PDU_OUT) 654 655 #define S_TF_RX_PDU_OUT 49 656 #define V_TF_RX_PDU_OUT(x) ((__u64)(x) << S_TF_RX_PDU_OUT) 657 658 #define S_TF_DUPACK_COUNT_ODD 50 659 #define V_TF_DUPACK_COUNT_ODD(x) ((__u64)(x) << S_TF_DUPACK_COUNT_ODD) 660 661 #define S_TF_FAST_RECOVERY 51 662 #define V_TF_FAST_RECOVERY(x) ((__u64)(x) << S_TF_FAST_RECOVERY) 663 664 #define S_TF_RECV_SCALE 52 665 #define V_TF_RECV_SCALE(x) ((__u64)(x) << S_TF_RECV_SCALE) 666 667 #define S_TF_RECV_TSTMP 53 668 #define V_TF_RECV_TSTMP(x) ((__u64)(x) << S_TF_RECV_TSTMP) 669 670 #define S_TF_RECV_SACK 54 671 #define V_TF_RECV_SACK(x) ((__u64)(x) << S_TF_RECV_SACK) 672 673 #define S_TF_PEND_CTL0 55 674 #define V_TF_PEND_CTL0(x) ((__u64)(x) << S_TF_PEND_CTL0) 675 676 #define S_TF_PEND_CTL1 56 677 #define V_TF_PEND_CTL1(x) ((__u64)(x) << S_TF_PEND_CTL1) 678 679 #define S_TF_PEND_CTL2 57 680 #define V_TF_PEND_CTL2(x) ((__u64)(x) << S_TF_PEND_CTL2) 681 682 #define S_TF_IP_VERSION 58 683 #define V_TF_IP_VERSION(x) ((__u64)(x) << S_TF_IP_VERSION) 684 685 #define S_TF_CCTRL_ECN 59 686 #define V_TF_CCTRL_ECN(x) ((__u64)(x) << S_TF_CCTRL_ECN) 687 688 #define S_TF_LPBK 59 689 #define V_TF_LPBK(x) ((__u64)(x) << S_TF_LPBK) 690 691 #define S_TF_CCTRL_ECE 60 692 #define V_TF_CCTRL_ECE(x) ((__u64)(x) << S_TF_CCTRL_ECE) 693 694 #define S_TF_REWRITE_DMAC 60 695 #define V_TF_REWRITE_DMAC(x) ((__u64)(x) << S_TF_REWRITE_DMAC) 696 697 #define S_TF_CCTRL_CWR 61 698 #define V_TF_CCTRL_CWR(x) ((__u64)(x) << S_TF_CCTRL_CWR) 699 700 #define S_TF_REWRITE_SMAC 61 701 #define V_TF_REWRITE_SMAC(x) ((__u64)(x) << S_TF_REWRITE_SMAC) 702 703 #define S_TF_CCTRL_RFR 62 704 #define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR) 705 706 #define S_TF_DDP_INDICATE_OUT 16 707 #define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) 708 709 #define S_TF_DDP_ACTIVE_BUF 17 710 #define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) 711 712 #define S_TF_DDP_OFF 18 713 #define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) 714 715 #define S_TF_DDP_WAIT_FRAG 19 716 #define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) 717 718 #define S_TF_DDP_BUF_INF 20 719 #define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) 720 721 #define S_TF_DDP_RX2TX 21 722 #define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) 723 724 #define S_TF_DDP_BUF0_VALID 24 725 #define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) 726 727 #define S_TF_DDP_BUF0_INDICATE 25 728 #define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) 729 730 #define S_TF_DDP_BUF0_FLUSH 26 731 #define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) 732 733 #define S_TF_DDP_PSHF_ENABLE_0 27 734 #define V_TF_DDP_PSHF_ENABLE_0(x) ((x) << S_TF_DDP_PSHF_ENABLE_0) 735 736 #define S_TF_DDP_PUSH_DISABLE_0 28 737 #define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) 738 739 #define S_TF_DDP_PSH_NO_INVALIDATE0 29 740 #define V_TF_DDP_PSH_NO_INVALIDATE0(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE0) 741 742 #define S_TF_DDP_BUF1_VALID 32 743 #define V_TF_DDP_BUF1_VALID(x) ((__u64)(x) << S_TF_DDP_BUF1_VALID) 744 745 #define S_TF_DDP_BUF1_INDICATE 33 746 #define V_TF_DDP_BUF1_INDICATE(x) ((__u64)(x) << S_TF_DDP_BUF1_INDICATE) 747 748 #define S_TF_DDP_BUF1_FLUSH 34 749 #define V_TF_DDP_BUF1_FLUSH(x) ((__u64)(x) << S_TF_DDP_BUF1_FLUSH) 750 751 #define S_TF_DDP_PSHF_ENABLE_1 35 752 #define V_TF_DDP_PSHF_ENABLE_1(x) ((__u64)(x) << S_TF_DDP_PSHF_ENABLE_1) 753 754 #define S_TF_DDP_PUSH_DISABLE_1 36 755 #define V_TF_DDP_PUSH_DISABLE_1(x) ((__u64)(x) << S_TF_DDP_PUSH_DISABLE_1) 756 757 #define S_TF_DDP_PSH_NO_INVALIDATE1 37 758 #define V_TF_DDP_PSH_NO_INVALIDATE1(x) ((__u64)(x) << S_TF_DDP_PSH_NO_INVALIDATE1) 759 760 #endif /* _T4_TCB_DEFS_H */ 761