xref: /freebsd/sys/dev/cxgbe/common/t4_regs_values.h (revision 4f52dfbb8d6c4d446500c5b097e3806ec219fbd4)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2011, 2016 Chelsio Communications, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  *
30  */
31 
32 #ifndef __T4_REGS_VALUES_H__
33 #define __T4_REGS_VALUES_H__
34 
35 /*
36  * This file contains definitions for various T4 register value hardware
37  * constants.  The types of values encoded here are predominantly those for
38  * register fields which control "modal" behavior.  For the most part, we do
39  * not include definitions for register fields which are simple numeric
40  * metrics, etc.
41  *
42  * These new "modal values" use a naming convention which matches the
43  * currently existing macros in t4_reg.h.  For register field FOO which would
44  * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE}
45  * definitions.  These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) ==
46  * X_FOO_MODE).
47  *
48  * Note that this should all be part of t4_regs.h but the toolset used to
49  * generate that file doesn't [yet] have the capability of collecting these
50  * constants.
51  */
52 
53 /*
54  * SGE definitions.
55  * ================
56  */
57 
58 /*
59  * SGE register field values.
60  */
61 
62 /* CONTROL register */
63 #define X_FLSPLITMODE_FLSPLITMIN	0
64 #define X_FLSPLITMODE_ETHHDR		1
65 #define X_FLSPLITMODE_IPHDR		2
66 #define X_FLSPLITMODE_TCPHDR		3
67 
68 #define X_DCASYSTYPE_FSB		0
69 #define X_DCASYSTYPE_CSI		1
70 
71 #define X_EGSTATPAGESIZE_64B		0
72 #define X_EGSTATPAGESIZE_128B		1
73 
74 #define X_RXPKTCPLMODE_DATA		0
75 #define X_RXPKTCPLMODE_SPLIT		1
76 
77 #define X_INGPCIEBOUNDARY_SHIFT		5
78 #define X_INGPCIEBOUNDARY_32B		0
79 #define X_INGPCIEBOUNDARY_64B		1
80 #define X_INGPCIEBOUNDARY_128B		2
81 #define X_INGPCIEBOUNDARY_256B		3
82 #define X_INGPCIEBOUNDARY_512B		4
83 #define X_INGPCIEBOUNDARY_1024B		5
84 #define X_INGPCIEBOUNDARY_2048B		6
85 #define X_INGPCIEBOUNDARY_4096B		7
86 
87 #define X_T6_INGPADBOUNDARY_SHIFT	3
88 #define X_T6_INGPADBOUNDARY_8B		0
89 #define X_T6_INGPADBOUNDARY_16B		1
90 #define X_T6_INGPADBOUNDARY_32B		2
91 #define X_T6_INGPADBOUNDARY_64B		3
92 #define X_T6_INGPADBOUNDARY_128B	4
93 #define X_T6_INGPADBOUNDARY_256B	5
94 #define X_T6_INGPADBOUNDARY_512B	6
95 #define X_T6_INGPADBOUNDARY_1024B	7
96 
97 #define X_INGPADBOUNDARY_SHIFT		5
98 #define X_INGPADBOUNDARY_32B		0
99 #define X_INGPADBOUNDARY_64B		1
100 #define X_INGPADBOUNDARY_128B		2
101 #define X_INGPADBOUNDARY_256B		3
102 #define X_INGPADBOUNDARY_512B		4
103 #define X_INGPADBOUNDARY_1024B		5
104 #define X_INGPADBOUNDARY_2048B		6
105 #define X_INGPADBOUNDARY_4096B		7
106 
107 #define X_EGRPCIEBOUNDARY_SHIFT		5
108 #define X_EGRPCIEBOUNDARY_32B		0
109 #define X_EGRPCIEBOUNDARY_64B		1
110 #define X_EGRPCIEBOUNDARY_128B		2
111 #define X_EGRPCIEBOUNDARY_256B		3
112 #define X_EGRPCIEBOUNDARY_512B		4
113 #define X_EGRPCIEBOUNDARY_1024B		5
114 #define X_EGRPCIEBOUNDARY_2048B		6
115 #define X_EGRPCIEBOUNDARY_4096B		7
116 
117 /* CONTROL2 register */
118 #define X_INGPACKBOUNDARY_SHIFT		5	// *most* of the values ...
119 #define X_INGPACKBOUNDARY_16B		0	// Note weird value!
120 #define X_INGPACKBOUNDARY_64B		1
121 #define X_INGPACKBOUNDARY_128B		2
122 #define X_INGPACKBOUNDARY_256B		3
123 #define X_INGPACKBOUNDARY_512B		4
124 #define X_INGPACKBOUNDARY_1024B		5
125 #define X_INGPACKBOUNDARY_2048B		6
126 #define X_INGPACKBOUNDARY_4096B		7
127 
128 /* GTS register */
129 #define SGE_TIMERREGS			6
130 #define X_TIMERREG_COUNTER0		0
131 #define X_TIMERREG_COUNTER1		1
132 #define X_TIMERREG_COUNTER2		2
133 #define X_TIMERREG_COUNTER3		3
134 #define X_TIMERREG_COUNTER4		4
135 #define X_TIMERREG_COUNTER5		5
136 #define X_TIMERREG_RESTART_COUNTER	6
137 #define X_TIMERREG_UPDATE_CIDX		7
138 
139 /*
140  * Egress Context field values
141  */
142 #define EC_WR_UNITS			16
143 
144 #define X_FETCHBURSTMIN_SHIFT		4
145 #define X_FETCHBURSTMIN_16B		0
146 #define X_FETCHBURSTMIN_32B		1
147 #define X_FETCHBURSTMIN_64B		2
148 #define X_FETCHBURSTMIN_128B		3
149 
150 #define X_FETCHBURSTMAX_SHIFT		6
151 #define X_FETCHBURSTMAX_64B		0
152 #define X_FETCHBURSTMAX_128B		1
153 #define X_FETCHBURSTMAX_256B		2
154 #define X_FETCHBURSTMAX_512B		3
155 
156 #define X_HOSTFCMODE_NONE		0
157 #define X_HOSTFCMODE_INGRESS_QUEUE	1
158 #define X_HOSTFCMODE_STATUS_PAGE	2
159 #define X_HOSTFCMODE_BOTH		3
160 
161 #define X_HOSTFCOWNER_UP		0
162 #define X_HOSTFCOWNER_SGE		1
163 
164 #define X_CIDXFLUSHTHRESH_1		0
165 #define X_CIDXFLUSHTHRESH_2		1
166 #define X_CIDXFLUSHTHRESH_4		2
167 #define X_CIDXFLUSHTHRESH_8		3
168 #define X_CIDXFLUSHTHRESH_16		4
169 #define X_CIDXFLUSHTHRESH_32		5
170 #define X_CIDXFLUSHTHRESH_64		6
171 #define X_CIDXFLUSHTHRESH_128		7
172 
173 #define X_IDXSIZE_UNIT			64
174 
175 #define X_BASEADDRESS_ALIGN		512
176 
177 /*
178  * Ingress Context field values
179  */
180 #define X_UPDATESCHEDULING_TIMER	0
181 #define X_UPDATESCHEDULING_COUNTER_OPTTIMER	1
182 
183 #define X_UPDATEDELIVERY_NONE		0
184 #define X_UPDATEDELIVERY_INTERRUPT	1
185 #define X_UPDATEDELIVERY_STATUS_PAGE	2
186 #define X_UPDATEDELIVERY_BOTH		3
187 
188 #define X_INTERRUPTDESTINATION_PCIE	0
189 #define X_INTERRUPTDESTINATION_IQ	1
190 
191 #define X_QUEUEENTRYSIZE_16B		0
192 #define X_QUEUEENTRYSIZE_32B		1
193 #define X_QUEUEENTRYSIZE_64B		2
194 #define X_QUEUEENTRYSIZE_128B		3
195 
196 #define IC_SIZE_UNIT			16
197 #define IC_BASEADDRESS_ALIGN		512
198 
199 #define X_RSPD_TYPE_FLBUF		0
200 #define X_RSPD_TYPE_CPL			1
201 #define X_RSPD_TYPE_INTR		2
202 
203 /*
204  * Context field definitions.  This is by no means a complete list of SGE
205  * Context fields.  In the vast majority of cases the firmware initializes
206  * things the way they need to be set up.  But in a few small cases, we need
207  * to compute new values and ship them off to the firmware to be applied to
208  * the SGE Conexts ...
209  */
210 
211 /*
212  * Congestion Manager Definitions.
213  */
214 #define S_CONMCTXT_CNGTPMODE		19
215 #define M_CONMCTXT_CNGTPMODE		0x3
216 #define V_CONMCTXT_CNGTPMODE(x)		((x) << S_CONMCTXT_CNGTPMODE)
217 #define G_CONMCTXT_CNGTPMODE(x)  \
218 	(((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE)
219 #define S_CONMCTXT_CNGCHMAP		0
220 #define M_CONMCTXT_CNGCHMAP		0xffff
221 #define V_CONMCTXT_CNGCHMAP(x)		((x) << S_CONMCTXT_CNGCHMAP)
222 #define G_CONMCTXT_CNGCHMAP(x)   \
223 	(((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP)
224 
225 #define X_CONMCTXT_CNGTPMODE_DISABLE	0
226 #define X_CONMCTXT_CNGTPMODE_QUEUE	1
227 #define X_CONMCTXT_CNGTPMODE_CHANNEL	2
228 #define X_CONMCTXT_CNGTPMODE_BOTH	3
229 
230 /*
231  * T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
232  * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
233  * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
234  * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64.  For Ingress Queues,
235  * we have a Going To Sleep register at offsets 8x+4.
236  *
237  * As noted above, we have many instances of the Simple Doorbell and Going To
238  * Sleep registers at offsets 8x and 8x+4, respectively.  We want to use a
239  * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
240  * avoid buffering of the writes to the Simple Doorbell and we want to use a
241  * non-contiguous offset for the Going To Sleep writes in order to avoid
242  * possible combining between them.
243  */
244 #define SGE_UDB_SIZE		128
245 #define SGE_UDB_KDOORBELL	8
246 #define SGE_UDB_GTS		20
247 #define SGE_UDB_WCDOORBELL	64
248 
249 /*
250  * CIM definitions.
251  * ================
252  */
253 
254 /*
255  * CIM register field values.
256  */
257 #define X_MBOWNER_NONE			0
258 #define X_MBOWNER_FW			1
259 #define X_MBOWNER_PL			2
260 #define X_MBOWNER_FW_DEFERRED		3
261 
262 /*
263  * PCI-E definitions.
264  * ==================
265  */
266 
267 #define X_WINDOW_SHIFT			10
268 #define X_PCIEOFST_SHIFT		10
269 
270 /*
271  * TP definitions.
272  * ===============
273  */
274 
275 /*
276  * TP_VLAN_PRI_MAP controls which subset of fields will be present in the
277  * Compressed Filter Tuple for LE filters.  Each bit set in TP_VLAN_PRI_MAP
278  * selects for a particular field being present.  These fields, when present
279  * in the Compressed Filter Tuple, have the following widths in bits.
280  */
281 #define S_FT_FIRST			S_FCOE
282 #define S_FT_LAST			S_FRAGMENTATION
283 
284 #define W_FT_FCOE			1
285 #define W_FT_PORT			3
286 #define W_FT_VNIC_ID			17
287 #define W_FT_VLAN			17
288 #define W_FT_TOS			8
289 #define W_FT_PROTOCOL			8
290 #define W_FT_ETHERTYPE			16
291 #define W_FT_MACMATCH			9
292 #define W_FT_MPSHITTYPE			3
293 #define W_FT_FRAGMENTATION		1
294 
295 /*
296  * Some of the Compressed Filter Tuple fields have internal structure.  These
297  * bit shifts/masks describe those structures.  All shifts are relative to the
298  * base position of the fields within the Compressed Filter Tuple
299  */
300 #define S_FT_VLAN_VLD			16
301 #define V_FT_VLAN_VLD(x)		((x) << S_FT_VLAN_VLD)
302 #define F_FT_VLAN_VLD			V_FT_VLAN_VLD(1U)
303 
304 #define S_FT_VNID_ID_VF			0
305 #define M_FT_VNID_ID_VF			0x7fU
306 #define V_FT_VNID_ID_VF(x)		((x) << S_FT_VNID_ID_VF)
307 #define G_FT_VNID_ID_VF(x)		(((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF)
308 
309 #define S_FT_VNID_ID_PF			7
310 #define M_FT_VNID_ID_PF			0x7U
311 #define V_FT_VNID_ID_PF(x)		((x) << S_FT_VNID_ID_PF)
312 #define G_FT_VNID_ID_PF(x)		(((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF)
313 
314 #define S_FT_VNID_ID_VLD		16
315 #define V_FT_VNID_ID_VLD(x)		((x) << S_FT_VNID_ID_VLD)
316 #define F_FT_VNID_ID_VLD(x)		V_FT_VNID_ID_VLD(1U)
317 
318 #endif /* __T4_REGS_VALUES_H__ */
319