154e4ee71SNavdeep Parhar /*- 254e4ee71SNavdeep Parhar * Copyright (c) 2011 Chelsio Communications, Inc. 354e4ee71SNavdeep Parhar * All rights reserved. 454e4ee71SNavdeep Parhar * 554e4ee71SNavdeep Parhar * Redistribution and use in source and binary forms, with or without 654e4ee71SNavdeep Parhar * modification, are permitted provided that the following conditions 754e4ee71SNavdeep Parhar * are met: 854e4ee71SNavdeep Parhar * 1. Redistributions of source code must retain the above copyright 954e4ee71SNavdeep Parhar * notice, this list of conditions and the following disclaimer. 1054e4ee71SNavdeep Parhar * 2. Redistributions in binary form must reproduce the above copyright 1154e4ee71SNavdeep Parhar * notice, this list of conditions and the following disclaimer in the 1254e4ee71SNavdeep Parhar * documentation and/or other materials provided with the distribution. 1354e4ee71SNavdeep Parhar * 1454e4ee71SNavdeep Parhar * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1554e4ee71SNavdeep Parhar * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1654e4ee71SNavdeep Parhar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1754e4ee71SNavdeep Parhar * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1854e4ee71SNavdeep Parhar * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1954e4ee71SNavdeep Parhar * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2054e4ee71SNavdeep Parhar * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2154e4ee71SNavdeep Parhar * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2254e4ee71SNavdeep Parhar * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2354e4ee71SNavdeep Parhar * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2454e4ee71SNavdeep Parhar * SUCH DAMAGE. 2554e4ee71SNavdeep Parhar * 2654e4ee71SNavdeep Parhar * $FreeBSD$ 2754e4ee71SNavdeep Parhar * 2854e4ee71SNavdeep Parhar */ 2954e4ee71SNavdeep Parhar 3054e4ee71SNavdeep Parhar #ifndef __T4_REGS_VALUES_H__ 3154e4ee71SNavdeep Parhar #define __T4_REGS_VALUES_H__ 3254e4ee71SNavdeep Parhar 3354e4ee71SNavdeep Parhar /* 3454e4ee71SNavdeep Parhar * This file contains definitions for various T4 register value hardware 3554e4ee71SNavdeep Parhar * constants. The types of values encoded here are predominantly those for 3654e4ee71SNavdeep Parhar * register fields which control "modal" behavior. For the most part, we do 3754e4ee71SNavdeep Parhar * not include definitions for register fields which are simple numeric 3854e4ee71SNavdeep Parhar * metrics, etc. 3954e4ee71SNavdeep Parhar * 4054e4ee71SNavdeep Parhar * These new "modal values" use a naming convention which matches the 4154e4ee71SNavdeep Parhar * currently existing macros in t4_reg.h. For register field FOO which would 4254e4ee71SNavdeep Parhar * have S_FOO, M_FOO, V_FOO() and G_FOO() macros, we introduce X_FOO_{MODE} 4354e4ee71SNavdeep Parhar * definitions. These can be used as V_FOO(X_FOO_MODE) or as (G_FOO(x) == 4454e4ee71SNavdeep Parhar * X_FOO_MODE). 4554e4ee71SNavdeep Parhar * 4654e4ee71SNavdeep Parhar * Note that this should all be part of t4_regs.h but the toolset used to 4754e4ee71SNavdeep Parhar * generate that file doesn't [yet] have the capability of collecting these 4854e4ee71SNavdeep Parhar * constants. 4954e4ee71SNavdeep Parhar */ 5054e4ee71SNavdeep Parhar 5154e4ee71SNavdeep Parhar /* 5254e4ee71SNavdeep Parhar * SGE definitions. 5354e4ee71SNavdeep Parhar * ================ 5454e4ee71SNavdeep Parhar */ 5554e4ee71SNavdeep Parhar 5654e4ee71SNavdeep Parhar /* 5754e4ee71SNavdeep Parhar * SGE register field values. 5854e4ee71SNavdeep Parhar */ 5954e4ee71SNavdeep Parhar 6054e4ee71SNavdeep Parhar /* CONTROL register */ 6154e4ee71SNavdeep Parhar #define X_FLSPLITMODE_FLSPLITMIN 0 6254e4ee71SNavdeep Parhar #define X_FLSPLITMODE_ETHHDR 1 6354e4ee71SNavdeep Parhar #define X_FLSPLITMODE_IPHDR 2 6454e4ee71SNavdeep Parhar #define X_FLSPLITMODE_TCPHDR 3 6554e4ee71SNavdeep Parhar 6654e4ee71SNavdeep Parhar #define X_DCASYSTYPE_FSB 0 6754e4ee71SNavdeep Parhar #define X_DCASYSTYPE_CSI 1 6854e4ee71SNavdeep Parhar 6954e4ee71SNavdeep Parhar #define X_EGSTATPAGESIZE_64B 0 7054e4ee71SNavdeep Parhar #define X_EGSTATPAGESIZE_128B 1 7154e4ee71SNavdeep Parhar 7254e4ee71SNavdeep Parhar #define X_RXPKTCPLMODE_DATA 0 7354e4ee71SNavdeep Parhar #define X_RXPKTCPLMODE_SPLIT 1 7454e4ee71SNavdeep Parhar 7554e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_SHIFT 5 7654e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_32B 0 7754e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_64B 1 7854e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_128B 2 7954e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_256B 3 8054e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_512B 4 8154e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_1024B 5 8254e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_2048B 6 8354e4ee71SNavdeep Parhar #define X_INGPCIEBOUNDARY_4096B 7 8454e4ee71SNavdeep Parhar 8554e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_SHIFT 5 8654e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_32B 0 8754e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_64B 1 8854e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_128B 2 8954e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_256B 3 9054e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_512B 4 9154e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_1024B 5 9254e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_2048B 6 9354e4ee71SNavdeep Parhar #define X_INGPADBOUNDARY_4096B 7 9454e4ee71SNavdeep Parhar 9554e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_SHIFT 5 9654e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_32B 0 9754e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_64B 1 9854e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_128B 2 9954e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_256B 3 10054e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_512B 4 10154e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_1024B 5 10254e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_2048B 6 10354e4ee71SNavdeep Parhar #define X_EGRPCIEBOUNDARY_4096B 7 10454e4ee71SNavdeep Parhar 10554e4ee71SNavdeep Parhar /* GTS register */ 10654e4ee71SNavdeep Parhar #define SGE_TIMERREGS 6 10754e4ee71SNavdeep Parhar #define X_TIMERREG_COUNTER0 0 10854e4ee71SNavdeep Parhar #define X_TIMERREG_COUNTER1 1 10954e4ee71SNavdeep Parhar #define X_TIMERREG_COUNTER2 2 11054e4ee71SNavdeep Parhar #define X_TIMERREG_COUNTER3 3 11154e4ee71SNavdeep Parhar #define X_TIMERREG_COUNTER4 4 11254e4ee71SNavdeep Parhar #define X_TIMERREG_COUNTER5 5 11354e4ee71SNavdeep Parhar #define X_TIMERREG_RESTART_COUNTER 6 11454e4ee71SNavdeep Parhar #define X_TIMERREG_UPDATE_CIDX 7 11554e4ee71SNavdeep Parhar 11654e4ee71SNavdeep Parhar /* 11754e4ee71SNavdeep Parhar * Egress Context field values 11854e4ee71SNavdeep Parhar */ 11954e4ee71SNavdeep Parhar #define EC_WR_UNITS 16 12054e4ee71SNavdeep Parhar 12154e4ee71SNavdeep Parhar #define X_FETCHBURSTMIN_SHIFT 4 12254e4ee71SNavdeep Parhar #define X_FETCHBURSTMIN_16B 0 12354e4ee71SNavdeep Parhar #define X_FETCHBURSTMIN_32B 1 12454e4ee71SNavdeep Parhar #define X_FETCHBURSTMIN_64B 2 12554e4ee71SNavdeep Parhar #define X_FETCHBURSTMIN_128B 3 12654e4ee71SNavdeep Parhar 12754e4ee71SNavdeep Parhar #define X_FETCHBURSTMAX_SHIFT 6 12854e4ee71SNavdeep Parhar #define X_FETCHBURSTMAX_64B 0 12954e4ee71SNavdeep Parhar #define X_FETCHBURSTMAX_128B 1 13054e4ee71SNavdeep Parhar #define X_FETCHBURSTMAX_256B 2 13154e4ee71SNavdeep Parhar #define X_FETCHBURSTMAX_512B 3 13254e4ee71SNavdeep Parhar 13354e4ee71SNavdeep Parhar #define X_HOSTFCMODE_NONE 0 13454e4ee71SNavdeep Parhar #define X_HOSTFCMODE_INGRESS_QUEUE 1 13554e4ee71SNavdeep Parhar #define X_HOSTFCMODE_STATUS_PAGE 2 13654e4ee71SNavdeep Parhar #define X_HOSTFCMODE_BOTH 3 13754e4ee71SNavdeep Parhar 13854e4ee71SNavdeep Parhar #define X_HOSTFCOWNER_UP 0 13954e4ee71SNavdeep Parhar #define X_HOSTFCOWNER_SGE 1 14054e4ee71SNavdeep Parhar 14154e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_1 0 14254e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_2 1 14354e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_4 2 14454e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_8 3 14554e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_16 4 14654e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_32 5 14754e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_64 6 14854e4ee71SNavdeep Parhar #define X_CIDXFLUSHTHRESH_128 7 14954e4ee71SNavdeep Parhar 15054e4ee71SNavdeep Parhar #define X_IDXSIZE_UNIT 64 15154e4ee71SNavdeep Parhar 15254e4ee71SNavdeep Parhar #define X_BASEADDRESS_ALIGN 512 15354e4ee71SNavdeep Parhar 15454e4ee71SNavdeep Parhar /* 15554e4ee71SNavdeep Parhar * Ingress Context field values 15654e4ee71SNavdeep Parhar */ 15754e4ee71SNavdeep Parhar #define X_UPDATESCHEDULING_TIMER 0 15854e4ee71SNavdeep Parhar #define X_UPDATESCHEDULING_COUNTER_OPTTIMER 1 15954e4ee71SNavdeep Parhar 16054e4ee71SNavdeep Parhar #define X_UPDATEDELIVERY_NONE 0 16154e4ee71SNavdeep Parhar #define X_UPDATEDELIVERY_INTERRUPT 1 16254e4ee71SNavdeep Parhar #define X_UPDATEDELIVERY_STATUS_PAGE 2 16354e4ee71SNavdeep Parhar #define X_UPDATEDELIVERY_BOTH 3 16454e4ee71SNavdeep Parhar 16554e4ee71SNavdeep Parhar #define X_INTERRUPTDESTINATION_PCIE 0 16654e4ee71SNavdeep Parhar #define X_INTERRUPTDESTINATION_IQ 1 16754e4ee71SNavdeep Parhar 16854e4ee71SNavdeep Parhar #define X_QUEUEENTRYSIZE_16B 0 16954e4ee71SNavdeep Parhar #define X_QUEUEENTRYSIZE_32B 1 17054e4ee71SNavdeep Parhar #define X_QUEUEENTRYSIZE_64B 2 17154e4ee71SNavdeep Parhar #define X_QUEUEENTRYSIZE_128B 3 17254e4ee71SNavdeep Parhar 17354e4ee71SNavdeep Parhar #define IC_SIZE_UNIT 16 17454e4ee71SNavdeep Parhar #define IC_BASEADDRESS_ALIGN 512 17554e4ee71SNavdeep Parhar 17654e4ee71SNavdeep Parhar #define X_RSPD_TYPE_FLBUF 0 17754e4ee71SNavdeep Parhar #define X_RSPD_TYPE_CPL 1 17854e4ee71SNavdeep Parhar #define X_RSPD_TYPE_INTR 2 17954e4ee71SNavdeep Parhar 18054e4ee71SNavdeep Parhar /* 18154e4ee71SNavdeep Parhar * CIM definitions. 18254e4ee71SNavdeep Parhar * ================ 18354e4ee71SNavdeep Parhar */ 18454e4ee71SNavdeep Parhar 18554e4ee71SNavdeep Parhar /* 18654e4ee71SNavdeep Parhar * CIM register field values. 18754e4ee71SNavdeep Parhar */ 18854e4ee71SNavdeep Parhar #define X_MBOWNER_NONE 0 18954e4ee71SNavdeep Parhar #define X_MBOWNER_FW 1 19054e4ee71SNavdeep Parhar #define X_MBOWNER_PL 2 19154e4ee71SNavdeep Parhar 192*c337fa30SNavdeep Parhar /* 193*c337fa30SNavdeep Parhar * PCI-E definitions. 194*c337fa30SNavdeep Parhar * ================== 195*c337fa30SNavdeep Parhar */ 196*c337fa30SNavdeep Parhar 197*c337fa30SNavdeep Parhar #define X_WINDOW_SHIFT 10 198*c337fa30SNavdeep Parhar #define X_PCIEOFST_SHIFT 10 199*c337fa30SNavdeep Parhar 200*c337fa30SNavdeep Parhar /* 201*c337fa30SNavdeep Parhar * TP definitions. 202*c337fa30SNavdeep Parhar * =============== 203*c337fa30SNavdeep Parhar */ 204*c337fa30SNavdeep Parhar 205*c337fa30SNavdeep Parhar /* 206*c337fa30SNavdeep Parhar * TP_VLAN_PRI_MAP controls which subset of fields will be present in the 207*c337fa30SNavdeep Parhar * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 208*c337fa30SNavdeep Parhar * selects for a particular field being present. These fields, when present 209*c337fa30SNavdeep Parhar * in the Compressed Filter Tuple, have the following widths in bits. 210*c337fa30SNavdeep Parhar */ 211*c337fa30SNavdeep Parhar #define W_FT_FCOE 1 212*c337fa30SNavdeep Parhar #define W_FT_PORT 3 213*c337fa30SNavdeep Parhar #define W_FT_VNIC_ID 17 214*c337fa30SNavdeep Parhar #define W_FT_VLAN 17 215*c337fa30SNavdeep Parhar #define W_FT_TOS 8 216*c337fa30SNavdeep Parhar #define W_FT_PROTOCOL 8 217*c337fa30SNavdeep Parhar #define W_FT_ETHERTYPE 16 218*c337fa30SNavdeep Parhar #define W_FT_MACMATCH 9 219*c337fa30SNavdeep Parhar #define W_FT_MPSHITTYPE 3 220*c337fa30SNavdeep Parhar #define W_FT_FRAGMENTATION 1 221*c337fa30SNavdeep Parhar 222*c337fa30SNavdeep Parhar /* 223*c337fa30SNavdeep Parhar * Some of the Compressed Filter Tuple fields have internal structure. These 224*c337fa30SNavdeep Parhar * bit shifts/masks describe those structures. All shifts are relative to the 225*c337fa30SNavdeep Parhar * base position of the fields within the Compressed Filter Tuple 226*c337fa30SNavdeep Parhar */ 227*c337fa30SNavdeep Parhar #define S_FT_VLAN_VLD 16 228*c337fa30SNavdeep Parhar #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD) 229*c337fa30SNavdeep Parhar #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U) 230*c337fa30SNavdeep Parhar 231*c337fa30SNavdeep Parhar #define S_FT_VNID_ID_VF 0 232*c337fa30SNavdeep Parhar #define M_FT_VNID_ID_VF 0x7fU 233*c337fa30SNavdeep Parhar #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF) 234*c337fa30SNavdeep Parhar #define G_FT_VNID_ID_VF(x) (((x) >> S_FT_VNID_ID_VF) & M_FT_VNID_ID_VF) 235*c337fa30SNavdeep Parhar 236*c337fa30SNavdeep Parhar #define S_FT_VNID_ID_PF 7 237*c337fa30SNavdeep Parhar #define M_FT_VNID_ID_PF 0x7U 238*c337fa30SNavdeep Parhar #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF) 239*c337fa30SNavdeep Parhar #define G_FT_VNID_ID_PF(x) (((x) >> S_FT_VNID_ID_PF) & M_FT_VNID_ID_PF) 240*c337fa30SNavdeep Parhar 241*c337fa30SNavdeep Parhar #define S_FT_VNID_ID_VLD 16 242*c337fa30SNavdeep Parhar #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD) 243*c337fa30SNavdeep Parhar #define F_FT_VNID_ID_VLD(x) V_FT_VNID_ID_VLD(1U) 244*c337fa30SNavdeep Parhar 24554e4ee71SNavdeep Parhar #endif /* __T4_REGS_VALUES_H__ */ 246