1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef T4_MSG_H 33 #define T4_MSG_H 34 35 enum { 36 CPL_PASS_OPEN_REQ = 0x1, 37 CPL_PASS_ACCEPT_RPL = 0x2, 38 CPL_ACT_OPEN_REQ = 0x3, 39 CPL_SET_TCB = 0x4, 40 CPL_SET_TCB_FIELD = 0x5, 41 CPL_GET_TCB = 0x6, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TAG_WRITE_REQ = 0x16, 57 CPL_BARRIER = 0x18, 58 CPL_TID_RELEASE = 0x1A, 59 CPL_TAG_READ_REQ = 0x1B, 60 CPL_SRQ_TABLE_REQ = 0x1C, 61 CPL_TX_PKT_FSO = 0x1E, 62 CPL_TX_DATA_ISO = 0x1F, 63 64 CPL_CLOSE_LISTSRV_RPL = 0x20, 65 CPL_ERROR = 0x21, 66 CPL_GET_TCB_RPL = 0x22, 67 CPL_L2T_WRITE_RPL = 0x23, 68 CPL_PASS_OPEN_RPL = 0x24, 69 CPL_ACT_OPEN_RPL = 0x25, 70 CPL_PEER_CLOSE = 0x26, 71 CPL_RTE_DELETE_RPL = 0x27, 72 CPL_RTE_WRITE_RPL = 0x28, 73 CPL_RX_URG_PKT = 0x29, 74 CPL_TAG_WRITE_RPL = 0x2A, 75 CPL_ABORT_REQ_RSS = 0x2B, 76 CPL_RX_URG_NOTIFY = 0x2C, 77 CPL_ABORT_RPL_RSS = 0x2D, 78 CPL_SMT_WRITE_RPL = 0x2E, 79 CPL_TX_DATA_ACK = 0x2F, 80 81 CPL_RX_PHYS_ADDR = 0x30, 82 CPL_PCMD_READ_RPL = 0x31, 83 CPL_CLOSE_CON_RPL = 0x32, 84 CPL_ISCSI_HDR = 0x33, 85 CPL_L2T_READ_RPL = 0x34, 86 CPL_RDMA_CQE = 0x35, 87 CPL_RDMA_CQE_READ_RSP = 0x36, 88 CPL_RDMA_CQE_ERR = 0x37, 89 CPL_RTE_READ_RPL = 0x38, 90 CPL_RX_DATA = 0x39, 91 CPL_SET_TCB_RPL = 0x3A, 92 CPL_RX_PKT = 0x3B, 93 CPL_TAG_READ_RPL = 0x3C, 94 CPL_HIT_NOTIFY = 0x3D, 95 CPL_PKT_NOTIFY = 0x3E, 96 CPL_RX_DDP_COMPLETE = 0x3F, 97 98 CPL_ACT_ESTABLISH = 0x40, 99 CPL_PASS_ESTABLISH = 0x41, 100 CPL_RX_DATA_DDP = 0x42, 101 CPL_SMT_READ_RPL = 0x43, 102 CPL_PASS_ACCEPT_REQ = 0x44, 103 CPL_RX_ISCSI_CMP = 0x45, 104 CPL_RX_FCOE_DDP = 0x46, 105 CPL_FCOE_HDR = 0x47, 106 CPL_T5_TRACE_PKT = 0x48, 107 CPL_RX_ISCSI_DDP = 0x49, 108 CPL_RX_FCOE_DIF = 0x4A, 109 CPL_RX_DATA_DIF = 0x4B, 110 CPL_ERR_NOTIFY = 0x4D, 111 CPL_RX_TLS_CMP = 0x4E, 112 113 CPL_RDMA_READ_REQ = 0x60, 114 CPL_RX_ISCSI_DIF = 0x60, 115 116 CPL_SET_LE_REQ = 0x80, 117 CPL_PASS_OPEN_REQ6 = 0x81, 118 CPL_ACT_OPEN_REQ6 = 0x83, 119 CPL_TX_TLS_PDU = 0x88, 120 CPL_TX_TLS_SFO = 0x89, 121 122 CPL_TX_SEC_PDU = 0x8A, 123 CPL_TX_TLS_ACK = 0x8B, 124 125 CPL_RDMA_TERMINATE = 0xA2, 126 CPL_RDMA_WRITE = 0xA4, 127 CPL_SGE_EGR_UPDATE = 0xA5, 128 CPL_SET_LE_RPL = 0xA6, 129 CPL_FW2_MSG = 0xA7, 130 CPL_FW2_PLD = 0xA8, 131 CPL_T5_RDMA_READ_REQ = 0xA9, 132 CPL_RDMA_ATOMIC_REQ = 0xAA, 133 CPL_RDMA_ATOMIC_RPL = 0xAB, 134 CPL_RDMA_IMM_DATA = 0xAC, 135 CPL_RDMA_IMM_DATA_SE = 0xAD, 136 CPL_RX_MPS_PKT = 0xAF, 137 138 CPL_TRACE_PKT = 0xB0, 139 CPL_RX2TX_DATA = 0xB1, 140 CPL_TLS_DATA = 0xB1, 141 CPL_ISCSI_DATA = 0xB2, 142 CPL_FCOE_DATA = 0xB3, 143 144 CPL_FW4_MSG = 0xC0, 145 CPL_FW4_PLD = 0xC1, 146 CPL_FW4_ACK = 0xC3, 147 CPL_SRQ_TABLE_RPL = 0xCC, 148 CPL_RX_PHYS_DSGL = 0xD0, 149 150 CPL_FW6_MSG = 0xE0, 151 CPL_FW6_PLD = 0xE1, 152 CPL_TX_TNL_LSO = 0xEC, 153 CPL_TX_PKT_LSO = 0xED, 154 CPL_TX_PKT_XT = 0xEE, 155 156 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 157 }; 158 159 enum CPL_error { 160 CPL_ERR_NONE = 0, 161 CPL_ERR_TCAM_PARITY = 1, 162 CPL_ERR_TCAM_MISS = 2, 163 CPL_ERR_TCAM_FULL = 3, 164 CPL_ERR_BAD_LENGTH = 15, 165 CPL_ERR_BAD_ROUTE = 18, 166 CPL_ERR_CONN_RESET = 20, 167 CPL_ERR_CONN_EXIST_SYNRECV = 21, 168 CPL_ERR_CONN_EXIST = 22, 169 CPL_ERR_ARP_MISS = 23, 170 CPL_ERR_BAD_SYN = 24, 171 CPL_ERR_CONN_TIMEDOUT = 30, 172 CPL_ERR_XMIT_TIMEDOUT = 31, 173 CPL_ERR_PERSIST_TIMEDOUT = 32, 174 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 175 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 176 CPL_ERR_RTX_NEG_ADVICE = 35, 177 CPL_ERR_PERSIST_NEG_ADVICE = 36, 178 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 179 CPL_ERR_WAIT_ARP_RPL = 41, 180 CPL_ERR_ABORT_FAILED = 42, 181 CPL_ERR_IWARP_FLM = 50, 182 CPL_CONTAINS_READ_RPL = 60, 183 CPL_CONTAINS_WRITE_RPL = 61, 184 }; 185 186 /* 187 * Some of the error codes above implicitly indicate that there is no TID 188 * allocated with the result of an ACT_OPEN. We use this predicate to make 189 * that explicit. 190 */ 191 static inline int act_open_has_tid(int status) 192 { 193 return (status != CPL_ERR_TCAM_PARITY && 194 status != CPL_ERR_TCAM_MISS && 195 status != CPL_ERR_TCAM_FULL && 196 status != CPL_ERR_CONN_EXIST_SYNRECV && 197 status != CPL_ERR_CONN_EXIST); 198 } 199 200 enum { 201 CPL_CONN_POLICY_AUTO = 0, 202 CPL_CONN_POLICY_ASK = 1, 203 CPL_CONN_POLICY_FILTER = 2, 204 CPL_CONN_POLICY_DENY = 3 205 }; 206 207 enum { 208 ULP_MODE_NONE = 0, 209 ULP_MODE_ISCSI = 2, 210 ULP_MODE_RDMA = 4, 211 ULP_MODE_TCPDDP = 5, 212 ULP_MODE_FCOE = 6, 213 ULP_MODE_TLS = 8, 214 }; 215 216 enum { 217 ULP_CRC_HEADER = 1 << 0, 218 ULP_CRC_DATA = 1 << 1 219 }; 220 221 enum { 222 CPL_PASS_OPEN_ACCEPT, 223 CPL_PASS_OPEN_REJECT, 224 CPL_PASS_OPEN_ACCEPT_TNL 225 }; 226 227 enum { 228 CPL_ABORT_SEND_RST = 0, 229 CPL_ABORT_NO_RST, 230 }; 231 232 enum { /* TX_PKT_XT checksum types */ 233 TX_CSUM_TCP = 0, 234 TX_CSUM_UDP = 1, 235 TX_CSUM_CRC16 = 4, 236 TX_CSUM_CRC32 = 5, 237 TX_CSUM_CRC32C = 6, 238 TX_CSUM_FCOE = 7, 239 TX_CSUM_TCPIP = 8, 240 TX_CSUM_UDPIP = 9, 241 TX_CSUM_TCPIP6 = 10, 242 TX_CSUM_UDPIP6 = 11, 243 TX_CSUM_IP = 12, 244 }; 245 246 enum { /* packet type in CPL_RX_PKT */ 247 PKTYPE_XACT_UCAST = 0, 248 PKTYPE_HASH_UCAST = 1, 249 PKTYPE_XACT_MCAST = 2, 250 PKTYPE_HASH_MCAST = 3, 251 PKTYPE_PROMISC = 4, 252 PKTYPE_HPROMISC = 5, 253 PKTYPE_BCAST = 6 254 }; 255 256 enum { /* DMAC type in CPL_RX_PKT */ 257 DATYPE_UCAST, 258 DATYPE_MCAST, 259 DATYPE_BCAST 260 }; 261 262 enum { /* TCP congestion control algorithms */ 263 CONG_ALG_RENO, 264 CONG_ALG_TAHOE, 265 CONG_ALG_NEWRENO, 266 CONG_ALG_HIGHSPEED 267 }; 268 269 enum { /* RSS hash type */ 270 RSS_HASH_NONE = 0, /* no hash computed */ 271 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 272 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 273 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 274 }; 275 276 enum { /* LE commands */ 277 LE_CMD_READ = 0x4, 278 LE_CMD_WRITE = 0xb 279 }; 280 281 enum { /* LE request size */ 282 LE_SZ_NONE = 0, 283 LE_SZ_33 = 1, 284 LE_SZ_66 = 2, 285 LE_SZ_132 = 3, 286 LE_SZ_264 = 4, 287 LE_SZ_528 = 5 288 }; 289 290 union opcode_tid { 291 __be32 opcode_tid; 292 __u8 opcode; 293 }; 294 295 #define S_CPL_OPCODE 24 296 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 297 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 298 #define G_TID(x) ((x) & 0xFFFFFF) 299 300 /* tid is assumed to be 24-bits */ 301 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 302 303 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 304 305 /* extract the TID from a CPL command */ 306 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 307 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 308 309 /* partitioning of TID fields that also carry a queue id */ 310 #define S_TID_TID 0 311 #define M_TID_TID 0x7ff 312 #define V_TID_TID(x) ((x) << S_TID_TID) 313 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 314 315 #define S_TID_COOKIE 11 316 #define M_TID_COOKIE 0x7 317 #define V_TID_COOKIE(x) ((x) << S_TID_COOKIE) 318 #define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE) 319 320 #define S_TID_QID 14 321 #define M_TID_QID 0x3ff 322 #define V_TID_QID(x) ((x) << S_TID_QID) 323 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 324 325 union opcode_info { 326 __be64 opcode_info; 327 __u8 opcode; 328 }; 329 330 struct tcp_options { 331 __be16 mss; 332 __u8 wsf; 333 #if defined(__LITTLE_ENDIAN_BITFIELD) 334 __u8 :4; 335 __u8 unknown:1; 336 __u8 ecn:1; 337 __u8 sack:1; 338 __u8 tstamp:1; 339 #else 340 __u8 tstamp:1; 341 __u8 sack:1; 342 __u8 ecn:1; 343 __u8 unknown:1; 344 __u8 :4; 345 #endif 346 }; 347 348 struct rss_header { 349 __u8 opcode; 350 #if defined(__LITTLE_ENDIAN_BITFIELD) 351 __u8 channel:2; 352 __u8 filter_hit:1; 353 __u8 filter_tid:1; 354 __u8 hash_type:2; 355 __u8 ipv6:1; 356 __u8 send2fw:1; 357 #else 358 __u8 send2fw:1; 359 __u8 ipv6:1; 360 __u8 hash_type:2; 361 __u8 filter_tid:1; 362 __u8 filter_hit:1; 363 __u8 channel:2; 364 #endif 365 __be16 qid; 366 __be32 hash_val; 367 }; 368 369 #define S_HASHTYPE 20 370 #define M_HASHTYPE 0x3 371 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 372 373 #define S_QNUM 0 374 #define M_QNUM 0xFFFF 375 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 376 377 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 378 # define RSS_HDR struct rss_header rss_hdr; 379 #else 380 # define RSS_HDR 381 #endif 382 383 #ifndef CHELSIO_FW 384 struct work_request_hdr { 385 __be32 wr_hi; 386 __be32 wr_mid; 387 __be64 wr_lo; 388 }; 389 390 /* wr_mid fields */ 391 #define S_WR_LEN16 0 392 #define M_WR_LEN16 0xFF 393 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 394 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 395 396 /* wr_hi fields */ 397 #define S_WR_OP 24 398 #define M_WR_OP 0xFF 399 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 400 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 401 402 # define WR_HDR struct work_request_hdr wr 403 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 404 #else 405 # define WR_HDR 406 # define WR_HDR_SIZE 0 407 #endif 408 409 /* option 0 fields */ 410 #define S_ACCEPT_MODE 0 411 #define M_ACCEPT_MODE 0x3 412 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 413 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 414 415 #define S_TX_CHAN 2 416 #define M_TX_CHAN 0x3 417 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 418 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 419 420 #define S_NO_CONG 4 421 #define V_NO_CONG(x) ((x) << S_NO_CONG) 422 #define F_NO_CONG V_NO_CONG(1U) 423 424 #define S_DELACK 5 425 #define V_DELACK(x) ((x) << S_DELACK) 426 #define F_DELACK V_DELACK(1U) 427 428 #define S_INJECT_TIMER 6 429 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 430 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 431 432 #define S_NON_OFFLOAD 7 433 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 434 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 435 436 #define S_ULP_MODE 8 437 #define M_ULP_MODE 0xF 438 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 439 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 440 441 #define S_RCV_BUFSIZ 12 442 #define M_RCV_BUFSIZ 0x3FFU 443 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 444 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 445 446 #define S_DSCP 22 447 #define M_DSCP 0x3F 448 #define V_DSCP(x) ((x) << S_DSCP) 449 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 450 451 #define S_SMAC_SEL 28 452 #define M_SMAC_SEL 0xFF 453 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 454 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 455 456 #define S_L2T_IDX 36 457 #define M_L2T_IDX 0xFFF 458 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 459 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 460 461 #define S_TCAM_BYPASS 48 462 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 463 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 464 465 #define S_NAGLE 49 466 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 467 #define F_NAGLE V_NAGLE(1ULL) 468 469 #define S_WND_SCALE 50 470 #define M_WND_SCALE 0xF 471 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 472 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 473 474 #define S_KEEP_ALIVE 54 475 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 476 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 477 478 #define S_MAX_RT 55 479 #define M_MAX_RT 0xF 480 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 481 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 482 483 #define S_MAX_RT_OVERRIDE 59 484 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 485 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 486 487 #define S_MSS_IDX 60 488 #define M_MSS_IDX 0xF 489 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 490 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 491 492 /* option 1 fields */ 493 #define S_SYN_RSS_ENABLE 0 494 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 495 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 496 497 #define S_SYN_RSS_USE_HASH 1 498 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 499 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 500 501 #define S_SYN_RSS_QUEUE 2 502 #define M_SYN_RSS_QUEUE 0x3FF 503 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 504 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 505 506 #define S_LISTEN_INTF 12 507 #define M_LISTEN_INTF 0xFF 508 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 509 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 510 511 #define S_LISTEN_FILTER 20 512 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 513 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 514 515 #define S_SYN_DEFENSE 21 516 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 517 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 518 519 #define S_CONN_POLICY 22 520 #define M_CONN_POLICY 0x3 521 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 522 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 523 524 #define S_T5_FILT_INFO 24 525 #define M_T5_FILT_INFO 0xffffffffffULL 526 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 527 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 528 529 #define S_FILT_INFO 28 530 #define M_FILT_INFO 0xfffffffffULL 531 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 532 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 533 534 /* option 2 fields */ 535 #define S_RSS_QUEUE 0 536 #define M_RSS_QUEUE 0x3FF 537 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 538 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 539 540 #define S_RSS_QUEUE_VALID 10 541 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 542 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 543 544 #define S_RX_COALESCE_VALID 11 545 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 546 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 547 548 #define S_RX_COALESCE 12 549 #define M_RX_COALESCE 0x3 550 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 551 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 552 553 #define S_CONG_CNTRL 14 554 #define M_CONG_CNTRL 0x3 555 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 556 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 557 558 #define S_PACE 16 559 #define M_PACE 0x3 560 #define V_PACE(x) ((x) << S_PACE) 561 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 562 563 #define S_CONG_CNTRL_VALID 18 564 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 565 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 566 567 #define S_T5_ISS 18 568 #define V_T5_ISS(x) ((x) << S_T5_ISS) 569 #define F_T5_ISS V_T5_ISS(1U) 570 571 #define S_PACE_VALID 19 572 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 573 #define F_PACE_VALID V_PACE_VALID(1U) 574 575 #define S_RX_FC_DISABLE 20 576 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 577 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 578 579 #define S_RX_FC_DDP 21 580 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 581 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 582 583 #define S_RX_FC_VALID 22 584 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 585 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 586 587 #define S_TX_QUEUE 23 588 #define M_TX_QUEUE 0x7 589 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 590 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 591 592 #define S_RX_CHANNEL 26 593 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 594 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 595 596 #define S_CCTRL_ECN 27 597 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 598 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 599 600 #define S_WND_SCALE_EN 28 601 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 602 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 603 604 #define S_TSTAMPS_EN 29 605 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 606 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 607 608 #define S_SACK_EN 30 609 #define V_SACK_EN(x) ((x) << S_SACK_EN) 610 #define F_SACK_EN V_SACK_EN(1U) 611 612 #define S_T5_OPT_2_VALID 31 613 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 614 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 615 616 struct cpl_pass_open_req { 617 WR_HDR; 618 union opcode_tid ot; 619 __be16 local_port; 620 __be16 peer_port; 621 __be32 local_ip; 622 __be32 peer_ip; 623 __be64 opt0; 624 __be64 opt1; 625 }; 626 627 struct cpl_pass_open_req6 { 628 WR_HDR; 629 union opcode_tid ot; 630 __be16 local_port; 631 __be16 peer_port; 632 __be64 local_ip_hi; 633 __be64 local_ip_lo; 634 __be64 peer_ip_hi; 635 __be64 peer_ip_lo; 636 __be64 opt0; 637 __be64 opt1; 638 }; 639 640 struct cpl_pass_open_rpl { 641 RSS_HDR 642 union opcode_tid ot; 643 __u8 rsvd[3]; 644 __u8 status; 645 }; 646 647 struct cpl_pass_establish { 648 RSS_HDR 649 union opcode_tid ot; 650 __be32 rsvd; 651 __be32 tos_stid; 652 __be16 mac_idx; 653 __be16 tcp_opt; 654 __be32 snd_isn; 655 __be32 rcv_isn; 656 }; 657 658 /* cpl_pass_establish.tos_stid fields */ 659 #define S_PASS_OPEN_TID 0 660 #define M_PASS_OPEN_TID 0xFFFFFF 661 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 662 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 663 664 #define S_PASS_OPEN_TOS 24 665 #define M_PASS_OPEN_TOS 0xFF 666 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 667 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 668 669 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 670 #define S_TCPOPT_WSCALE_OK 5 671 #define M_TCPOPT_WSCALE_OK 0x1 672 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 673 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 674 675 #define S_TCPOPT_SACK 6 676 #define M_TCPOPT_SACK 0x1 677 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 678 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 679 680 #define S_TCPOPT_TSTAMP 7 681 #define M_TCPOPT_TSTAMP 0x1 682 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 683 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 684 685 #define S_TCPOPT_SND_WSCALE 8 686 #define M_TCPOPT_SND_WSCALE 0xF 687 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 688 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 689 690 #define S_TCPOPT_MSS 12 691 #define M_TCPOPT_MSS 0xF 692 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 693 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 694 695 struct cpl_pass_accept_req { 696 RSS_HDR 697 union opcode_tid ot; 698 __be16 rsvd; 699 __be16 len; 700 __be32 hdr_len; 701 __be16 vlan; 702 __be16 l2info; 703 __be32 tos_stid; 704 struct tcp_options tcpopt; 705 }; 706 707 /* cpl_pass_accept_req.hdr_len fields */ 708 #define S_SYN_RX_CHAN 0 709 #define M_SYN_RX_CHAN 0xF 710 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 711 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 712 713 #define S_TCP_HDR_LEN 10 714 #define M_TCP_HDR_LEN 0x3F 715 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 716 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 717 718 #define S_T6_TCP_HDR_LEN 8 719 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 720 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 721 722 #define S_IP_HDR_LEN 16 723 #define M_IP_HDR_LEN 0x3FF 724 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 725 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 726 727 #define S_T6_IP_HDR_LEN 14 728 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 729 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 730 731 #define S_ETH_HDR_LEN 26 732 #define M_ETH_HDR_LEN 0x3F 733 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 734 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 735 736 #define S_T6_ETH_HDR_LEN 24 737 #define M_T6_ETH_HDR_LEN 0xFF 738 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 739 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 740 741 /* cpl_pass_accept_req.l2info fields */ 742 #define S_SYN_MAC_IDX 0 743 #define M_SYN_MAC_IDX 0x1FF 744 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 745 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 746 747 #define S_SYN_XACT_MATCH 9 748 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 749 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 750 751 #define S_SYN_INTF 12 752 #define M_SYN_INTF 0xF 753 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 754 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 755 756 struct cpl_pass_accept_rpl { 757 WR_HDR; 758 union opcode_tid ot; 759 __be32 opt2; 760 __be64 opt0; 761 }; 762 763 struct cpl_t5_pass_accept_rpl { 764 WR_HDR; 765 union opcode_tid ot; 766 __be32 opt2; 767 __be64 opt0; 768 __be32 iss; 769 union { 770 __be32 rsvd; /* T5 */ 771 __be32 opt3; /* T6 */ 772 } u; 773 }; 774 775 struct cpl_act_open_req { 776 WR_HDR; 777 union opcode_tid ot; 778 __be16 local_port; 779 __be16 peer_port; 780 __be32 local_ip; 781 __be32 peer_ip; 782 __be64 opt0; 783 __be32 params; 784 __be32 opt2; 785 }; 786 787 #define S_FILTER_TUPLE 24 788 #define M_FILTER_TUPLE 0xFFFFFFFFFF 789 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 790 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 791 struct cpl_t5_act_open_req { 792 WR_HDR; 793 union opcode_tid ot; 794 __be16 local_port; 795 __be16 peer_port; 796 __be32 local_ip; 797 __be32 peer_ip; 798 __be64 opt0; 799 __be32 iss; 800 __be32 opt2; 801 __be64 params; 802 }; 803 804 struct cpl_t6_act_open_req { 805 WR_HDR; 806 union opcode_tid ot; 807 __be16 local_port; 808 __be16 peer_port; 809 __be32 local_ip; 810 __be32 peer_ip; 811 __be64 opt0; 812 __be32 iss; 813 __be32 opt2; 814 __be64 params; 815 __be32 rsvd2; 816 __be32 opt3; 817 }; 818 819 /* cpl_{t5,t6}_act_open_req.params field */ 820 #define S_AOPEN_FCOEMASK 0 821 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 822 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 823 824 struct cpl_act_open_req6 { 825 WR_HDR; 826 union opcode_tid ot; 827 __be16 local_port; 828 __be16 peer_port; 829 __be64 local_ip_hi; 830 __be64 local_ip_lo; 831 __be64 peer_ip_hi; 832 __be64 peer_ip_lo; 833 __be64 opt0; 834 __be32 params; 835 __be32 opt2; 836 }; 837 838 struct cpl_t5_act_open_req6 { 839 WR_HDR; 840 union opcode_tid ot; 841 __be16 local_port; 842 __be16 peer_port; 843 __be64 local_ip_hi; 844 __be64 local_ip_lo; 845 __be64 peer_ip_hi; 846 __be64 peer_ip_lo; 847 __be64 opt0; 848 __be32 iss; 849 __be32 opt2; 850 __be64 params; 851 }; 852 853 struct cpl_t6_act_open_req6 { 854 WR_HDR; 855 union opcode_tid ot; 856 __be16 local_port; 857 __be16 peer_port; 858 __be64 local_ip_hi; 859 __be64 local_ip_lo; 860 __be64 peer_ip_hi; 861 __be64 peer_ip_lo; 862 __be64 opt0; 863 __be32 iss; 864 __be32 opt2; 865 __be64 params; 866 __be32 rsvd2; 867 __be32 opt3; 868 }; 869 870 struct cpl_act_open_rpl { 871 RSS_HDR 872 union opcode_tid ot; 873 __be32 atid_status; 874 }; 875 876 /* cpl_act_open_rpl.atid_status fields */ 877 #define S_AOPEN_STATUS 0 878 #define M_AOPEN_STATUS 0xFF 879 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 880 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 881 882 #define S_AOPEN_ATID 8 883 #define M_AOPEN_ATID 0xFFFFFF 884 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 885 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 886 887 struct cpl_act_establish { 888 RSS_HDR 889 union opcode_tid ot; 890 __be32 rsvd; 891 __be32 tos_atid; 892 __be16 mac_idx; 893 __be16 tcp_opt; 894 __be32 snd_isn; 895 __be32 rcv_isn; 896 }; 897 898 struct cpl_get_tcb { 899 WR_HDR; 900 union opcode_tid ot; 901 __be16 reply_ctrl; 902 __be16 cookie; 903 }; 904 905 /* cpl_get_tcb.reply_ctrl fields */ 906 #define S_QUEUENO 0 907 #define M_QUEUENO 0x3FF 908 #define V_QUEUENO(x) ((x) << S_QUEUENO) 909 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 910 911 #define S_REPLY_CHAN 14 912 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 913 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 914 915 #define S_NO_REPLY 15 916 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 917 #define F_NO_REPLY V_NO_REPLY(1U) 918 919 struct cpl_get_tcb_rpl { 920 RSS_HDR 921 union opcode_tid ot; 922 __u8 cookie; 923 __u8 status; 924 __be16 len; 925 }; 926 927 struct cpl_set_tcb { 928 WR_HDR; 929 union opcode_tid ot; 930 __be16 reply_ctrl; 931 __be16 cookie; 932 }; 933 934 struct cpl_set_tcb_field { 935 WR_HDR; 936 union opcode_tid ot; 937 __be16 reply_ctrl; 938 __be16 word_cookie; 939 __be64 mask; 940 __be64 val; 941 }; 942 943 struct cpl_set_tcb_field_core { 944 union opcode_tid ot; 945 __be16 reply_ctrl; 946 __be16 word_cookie; 947 __be64 mask; 948 __be64 val; 949 }; 950 951 /* cpl_set_tcb_field.word_cookie fields */ 952 #define S_WORD 0 953 #define M_WORD 0x1F 954 #define V_WORD(x) ((x) << S_WORD) 955 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 956 957 #define S_COOKIE 5 958 #define M_COOKIE 0x7 959 #define V_COOKIE(x) ((x) << S_COOKIE) 960 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 961 962 struct cpl_set_tcb_rpl { 963 RSS_HDR 964 union opcode_tid ot; 965 __be16 rsvd; 966 __u8 cookie; 967 __u8 status; 968 __be64 oldval; 969 }; 970 971 struct cpl_close_con_req { 972 WR_HDR; 973 union opcode_tid ot; 974 __be32 rsvd; 975 }; 976 977 struct cpl_close_con_rpl { 978 RSS_HDR 979 union opcode_tid ot; 980 __u8 rsvd[3]; 981 __u8 status; 982 __be32 snd_nxt; 983 __be32 rcv_nxt; 984 }; 985 986 struct cpl_close_listsvr_req { 987 WR_HDR; 988 union opcode_tid ot; 989 __be16 reply_ctrl; 990 __be16 rsvd; 991 }; 992 993 /* additional cpl_close_listsvr_req.reply_ctrl field */ 994 #define S_LISTSVR_IPV6 14 995 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 996 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 997 998 struct cpl_close_listsvr_rpl { 999 RSS_HDR 1000 union opcode_tid ot; 1001 __u8 rsvd[3]; 1002 __u8 status; 1003 }; 1004 1005 struct cpl_abort_req_rss { 1006 RSS_HDR 1007 union opcode_tid ot; 1008 __u8 rsvd[3]; 1009 __u8 status; 1010 }; 1011 1012 struct cpl_abort_req_rss6 { 1013 RSS_HDR 1014 union opcode_tid ot; 1015 __u32 srqidx_status; 1016 }; 1017 1018 #define S_ABORT_RSS_STATUS 0 1019 #define M_ABORT_RSS_STATUS 0xff 1020 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1021 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1022 1023 #define S_ABORT_RSS_SRQIDX 8 1024 #define M_ABORT_RSS_SRQIDX 0xffffff 1025 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1026 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1027 1028 1029 /* cpl_abort_req status command code in case of T6, 1030 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1031 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1032 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1033 */ 1034 struct cpl_abort_req { 1035 WR_HDR; 1036 union opcode_tid ot; 1037 __be32 rsvd0; 1038 __u8 rsvd1; 1039 __u8 cmd; 1040 __u8 rsvd2[6]; 1041 }; 1042 1043 struct cpl_abort_rpl_rss { 1044 RSS_HDR 1045 union opcode_tid ot; 1046 __u8 rsvd[3]; 1047 __u8 status; 1048 }; 1049 1050 struct cpl_abort_rpl_rss6 { 1051 RSS_HDR 1052 union opcode_tid ot; 1053 __u32 srqidx_status; 1054 }; 1055 1056 struct cpl_abort_rpl { 1057 WR_HDR; 1058 union opcode_tid ot; 1059 __be32 rsvd0; 1060 __u8 rsvd1; 1061 __u8 cmd; 1062 __u8 rsvd2[6]; 1063 }; 1064 1065 struct cpl_peer_close { 1066 RSS_HDR 1067 union opcode_tid ot; 1068 __be32 rcv_nxt; 1069 }; 1070 1071 struct cpl_tid_release { 1072 WR_HDR; 1073 union opcode_tid ot; 1074 __be32 rsvd; 1075 }; 1076 1077 struct tx_data_wr { 1078 __be32 wr_hi; 1079 __be32 wr_lo; 1080 __be32 len; 1081 __be32 flags; 1082 __be32 sndseq; 1083 __be32 param; 1084 }; 1085 1086 /* tx_data_wr.flags fields */ 1087 #define S_TX_ACK_PAGES 21 1088 #define M_TX_ACK_PAGES 0x7 1089 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1090 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1091 1092 /* tx_data_wr.param fields */ 1093 #define S_TX_PORT 0 1094 #define M_TX_PORT 0x7 1095 #define V_TX_PORT(x) ((x) << S_TX_PORT) 1096 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1097 1098 #define S_TX_MSS 4 1099 #define M_TX_MSS 0xF 1100 #define V_TX_MSS(x) ((x) << S_TX_MSS) 1101 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1102 1103 #define S_TX_QOS 8 1104 #define M_TX_QOS 0xFF 1105 #define V_TX_QOS(x) ((x) << S_TX_QOS) 1106 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1107 1108 #define S_TX_SNDBUF 16 1109 #define M_TX_SNDBUF 0xFFFF 1110 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1111 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1112 1113 struct cpl_tx_data { 1114 union opcode_tid ot; 1115 __be32 len; 1116 __be32 rsvd; 1117 __be32 flags; 1118 }; 1119 1120 /* cpl_tx_data.flags fields */ 1121 #define S_TX_PROXY 5 1122 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1123 #define F_TX_PROXY V_TX_PROXY(1U) 1124 1125 #define S_TX_ULP_SUBMODE 6 1126 #define M_TX_ULP_SUBMODE 0xF 1127 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1128 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1129 1130 #define S_TX_ULP_MODE 10 1131 #define M_TX_ULP_MODE 0x7 1132 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1133 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1134 1135 #define S_TX_FORCE 13 1136 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1137 #define F_TX_FORCE V_TX_FORCE(1U) 1138 1139 #define S_TX_SHOVE 14 1140 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1141 #define F_TX_SHOVE V_TX_SHOVE(1U) 1142 1143 #define S_TX_MORE 15 1144 #define V_TX_MORE(x) ((x) << S_TX_MORE) 1145 #define F_TX_MORE V_TX_MORE(1U) 1146 1147 #define S_TX_URG 16 1148 #define V_TX_URG(x) ((x) << S_TX_URG) 1149 #define F_TX_URG V_TX_URG(1U) 1150 1151 #define S_TX_FLUSH 17 1152 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1153 #define F_TX_FLUSH V_TX_FLUSH(1U) 1154 1155 #define S_TX_SAVE 18 1156 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1157 #define F_TX_SAVE V_TX_SAVE(1U) 1158 1159 #define S_TX_TNL 19 1160 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1161 #define F_TX_TNL V_TX_TNL(1U) 1162 1163 #define S_T6_TX_FORCE 20 1164 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1165 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1166 1167 /* additional tx_data_wr.flags fields */ 1168 #define S_TX_CPU_IDX 0 1169 #define M_TX_CPU_IDX 0x3F 1170 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1171 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1172 1173 #define S_TX_CLOSE 17 1174 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1175 #define F_TX_CLOSE V_TX_CLOSE(1U) 1176 1177 #define S_TX_INIT 18 1178 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1179 #define F_TX_INIT V_TX_INIT(1U) 1180 1181 #define S_TX_IMM_ACK 19 1182 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1183 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1184 1185 #define S_TX_IMM_DMA 20 1186 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1187 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1188 1189 struct cpl_tx_data_ack { 1190 RSS_HDR 1191 union opcode_tid ot; 1192 __be32 snd_una; 1193 }; 1194 1195 struct cpl_wr_ack { /* XXX */ 1196 RSS_HDR 1197 union opcode_tid ot; 1198 __be16 credits; 1199 __be16 rsvd; 1200 __be32 snd_nxt; 1201 __be32 snd_una; 1202 }; 1203 1204 struct cpl_tx_pkt_core { 1205 __be32 ctrl0; 1206 __be16 pack; 1207 __be16 len; 1208 __be64 ctrl1; 1209 }; 1210 1211 struct cpl_tx_pkt { 1212 WR_HDR; 1213 struct cpl_tx_pkt_core c; 1214 }; 1215 1216 #define cpl_tx_pkt_xt cpl_tx_pkt 1217 1218 /* cpl_tx_pkt_core.ctrl0 fields */ 1219 #define S_TXPKT_VF 0 1220 #define M_TXPKT_VF 0xFF 1221 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1222 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1223 1224 #define S_TXPKT_PF 8 1225 #define M_TXPKT_PF 0x7 1226 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1227 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1228 1229 #define S_TXPKT_VF_VLD 11 1230 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1231 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1232 1233 #define S_TXPKT_OVLAN_IDX 12 1234 #define M_TXPKT_OVLAN_IDX 0xF 1235 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1236 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1237 1238 #define S_TXPKT_T5_OVLAN_IDX 12 1239 #define M_TXPKT_T5_OVLAN_IDX 0x7 1240 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1241 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1242 M_TXPKT_T5_OVLAN_IDX) 1243 1244 #define S_TXPKT_INTF 16 1245 #define M_TXPKT_INTF 0xF 1246 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1247 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1248 1249 #define S_TXPKT_SPECIAL_STAT 20 1250 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1251 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1252 1253 #define S_TXPKT_T5_FCS_DIS 21 1254 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1255 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1256 1257 #define S_TXPKT_INS_OVLAN 21 1258 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1259 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1260 1261 #define S_TXPKT_T5_INS_OVLAN 15 1262 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1263 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1264 1265 #define S_TXPKT_STAT_DIS 22 1266 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1267 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1268 1269 #define S_TXPKT_LOOPBACK 23 1270 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1271 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1272 1273 #define S_TXPKT_TSTAMP 23 1274 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1275 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1276 1277 #define S_TXPKT_OPCODE 24 1278 #define M_TXPKT_OPCODE 0xFF 1279 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1280 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1281 1282 /* cpl_tx_pkt_core.ctrl1 fields */ 1283 #define S_TXPKT_SA_IDX 0 1284 #define M_TXPKT_SA_IDX 0xFFF 1285 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1286 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1287 1288 #define S_TXPKT_CSUM_END 12 1289 #define M_TXPKT_CSUM_END 0xFF 1290 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1291 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1292 1293 #define S_TXPKT_CSUM_START 20 1294 #define M_TXPKT_CSUM_START 0x3FF 1295 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1296 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1297 1298 #define S_TXPKT_IPHDR_LEN 20 1299 #define M_TXPKT_IPHDR_LEN 0x3FFF 1300 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1301 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1302 1303 #define M_T6_TXPKT_IPHDR_LEN 0xFFF 1304 #define G_T6_TXPKT_IPHDR_LEN(x) \ 1305 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1306 1307 #define S_TXPKT_CSUM_LOC 30 1308 #define M_TXPKT_CSUM_LOC 0x3FF 1309 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1310 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1311 1312 #define S_TXPKT_ETHHDR_LEN 34 1313 #define M_TXPKT_ETHHDR_LEN 0x3F 1314 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1315 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1316 1317 #define S_T6_TXPKT_ETHHDR_LEN 32 1318 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 1319 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1320 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 1321 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1322 1323 #define S_TXPKT_CSUM_TYPE 40 1324 #define M_TXPKT_CSUM_TYPE 0xF 1325 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1326 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1327 1328 #define S_TXPKT_VLAN 44 1329 #define M_TXPKT_VLAN 0xFFFF 1330 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1331 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1332 1333 #define S_TXPKT_VLAN_VLD 60 1334 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1335 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1336 1337 #define S_TXPKT_IPSEC 61 1338 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1339 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1340 1341 #define S_TXPKT_IPCSUM_DIS 62 1342 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1343 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1344 1345 #define S_TXPKT_L4CSUM_DIS 63 1346 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1347 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1348 1349 struct cpl_tx_pkt_lso_core { 1350 __be32 lso_ctrl; 1351 __be16 ipid_ofst; 1352 __be16 mss; 1353 __be32 seqno_offset; 1354 __be32 len; 1355 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1356 }; 1357 1358 struct cpl_tx_pkt_lso { 1359 WR_HDR; 1360 struct cpl_tx_pkt_lso_core c; 1361 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1362 }; 1363 1364 struct cpl_tx_pkt_ufo_core { 1365 __be16 ethlen; 1366 __be16 iplen; 1367 __be16 udplen; 1368 __be16 mss; 1369 __be32 len; 1370 __be32 r1; 1371 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1372 }; 1373 1374 struct cpl_tx_pkt_ufo { 1375 WR_HDR; 1376 struct cpl_tx_pkt_ufo_core c; 1377 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1378 }; 1379 1380 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1381 #define S_LSO_TCPHDR_LEN 0 1382 #define M_LSO_TCPHDR_LEN 0xF 1383 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1384 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1385 1386 #define S_LSO_IPHDR_LEN 4 1387 #define M_LSO_IPHDR_LEN 0xFFF 1388 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1389 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1390 1391 #define S_LSO_ETHHDR_LEN 16 1392 #define M_LSO_ETHHDR_LEN 0xF 1393 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1394 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1395 1396 #define S_LSO_IPV6 20 1397 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1398 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1399 1400 #define S_LSO_OFLD_ENCAP 21 1401 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1402 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1403 1404 #define S_LSO_LAST_SLICE 22 1405 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1406 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1407 1408 #define S_LSO_FIRST_SLICE 23 1409 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1410 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1411 1412 #define S_LSO_OPCODE 24 1413 #define M_LSO_OPCODE 0xFF 1414 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1415 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1416 1417 #define S_LSO_T5_XFER_SIZE 0 1418 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1419 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1420 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1421 1422 /* cpl_tx_pkt_lso_core.mss fields */ 1423 #define S_LSO_MSS 0 1424 #define M_LSO_MSS 0x3FFF 1425 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1426 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1427 1428 #define S_LSO_IPID_SPLIT 15 1429 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1430 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1431 1432 struct cpl_tx_pkt_fso { 1433 WR_HDR; 1434 __be32 fso_ctrl; 1435 __be16 seqcnt_ofst; 1436 __be16 mtu; 1437 __be32 param_offset; 1438 __be32 len; 1439 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1440 }; 1441 1442 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1443 #define S_FSO_XCHG_CLASS 21 1444 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1445 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1446 1447 #define S_FSO_INITIATOR 20 1448 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1449 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1450 1451 #define S_FSO_FCHDR_LEN 12 1452 #define M_FSO_FCHDR_LEN 0xF 1453 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1454 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1455 1456 struct cpl_iscsi_hdr_no_rss { 1457 union opcode_tid ot; 1458 __be16 pdu_len_ddp; 1459 __be16 len; 1460 __be32 seq; 1461 __be16 urg; 1462 __u8 rsvd; 1463 __u8 status; 1464 }; 1465 1466 struct cpl_tx_data_iso { 1467 __be32 op_to_scsi; 1468 __u8 reserved1; 1469 __u8 ahs_len; 1470 __be16 mpdu; 1471 __be32 burst_size; 1472 __be32 len; 1473 __be32 reserved2_seglen_offset; 1474 __be32 datasn_offset; 1475 __be32 buffer_offset; 1476 __be32 reserved3; 1477 1478 /* encapsulated CPL_TX_DATA follows here */ 1479 }; 1480 1481 /* cpl_tx_data_iso.op_to_scsi fields */ 1482 #define S_CPL_TX_DATA_ISO_OP 24 1483 #define M_CPL_TX_DATA_ISO_OP 0xff 1484 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 1485 #define G_CPL_TX_DATA_ISO_OP(x) \ 1486 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 1487 1488 #define S_CPL_TX_DATA_ISO_FIRST 23 1489 #define M_CPL_TX_DATA_ISO_FIRST 0x1 1490 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 1491 #define G_CPL_TX_DATA_ISO_FIRST(x) \ 1492 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 1493 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 1494 1495 #define S_CPL_TX_DATA_ISO_LAST 22 1496 #define M_CPL_TX_DATA_ISO_LAST 0x1 1497 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 1498 #define G_CPL_TX_DATA_ISO_LAST(x) \ 1499 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 1500 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 1501 1502 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 1503 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 1504 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 1505 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 1506 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 1507 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 1508 1509 #define S_CPL_TX_DATA_ISO_HDRCRC 20 1510 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1 1511 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 1512 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 1513 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 1514 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 1515 1516 #define S_CPL_TX_DATA_ISO_PLDCRC 19 1517 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1 1518 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 1519 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 1520 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 1521 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 1522 1523 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18 1524 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 1525 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 1526 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 1527 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 1528 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 1529 1530 #define S_CPL_TX_DATA_ISO_SCSI 16 1531 #define M_CPL_TX_DATA_ISO_SCSI 0x3 1532 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 1533 #define G_CPL_TX_DATA_ISO_SCSI(x) \ 1534 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 1535 1536 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1537 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 1538 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 1539 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1540 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1541 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1542 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 1543 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1544 1545 struct cpl_iscsi_hdr { 1546 RSS_HDR 1547 union opcode_tid ot; 1548 __be16 pdu_len_ddp; 1549 __be16 len; 1550 __be32 seq; 1551 __be16 urg; 1552 __u8 rsvd; 1553 __u8 status; 1554 }; 1555 1556 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1557 #define S_ISCSI_PDU_LEN 0 1558 #define M_ISCSI_PDU_LEN 0x7FFF 1559 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1560 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1561 1562 #define S_ISCSI_DDP 15 1563 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1564 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1565 1566 struct cpl_iscsi_data { 1567 RSS_HDR 1568 union opcode_tid ot; 1569 __u8 rsvd0[2]; 1570 __be16 len; 1571 __be32 seq; 1572 __be16 urg; 1573 __u8 rsvd1; 1574 __u8 status; 1575 }; 1576 1577 struct cpl_rx_data { 1578 RSS_HDR 1579 union opcode_tid ot; 1580 __be16 rsvd; 1581 __be16 len; 1582 __be32 seq; 1583 __be16 urg; 1584 #if defined(__LITTLE_ENDIAN_BITFIELD) 1585 __u8 dack_mode:2; 1586 __u8 psh:1; 1587 __u8 heartbeat:1; 1588 __u8 ddp_off:1; 1589 __u8 :3; 1590 #else 1591 __u8 :3; 1592 __u8 ddp_off:1; 1593 __u8 heartbeat:1; 1594 __u8 psh:1; 1595 __u8 dack_mode:2; 1596 #endif 1597 __u8 status; 1598 }; 1599 1600 struct cpl_fcoe_hdr { 1601 RSS_HDR 1602 union opcode_tid ot; 1603 __be16 oxid; 1604 __be16 len; 1605 __be32 rctl_fctl; 1606 __u8 cs_ctl; 1607 __u8 df_ctl; 1608 __u8 sof; 1609 __u8 eof; 1610 __be16 seq_cnt; 1611 __u8 seq_id; 1612 __u8 type; 1613 __be32 param; 1614 }; 1615 1616 /* cpl_fcoe_hdr.rctl_fctl fields */ 1617 #define S_FCOE_FCHDR_RCTL 24 1618 #define M_FCOE_FCHDR_RCTL 0xff 1619 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 1620 #define G_FCOE_FCHDR_RCTL(x) \ 1621 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 1622 1623 #define S_FCOE_FCHDR_FCTL 0 1624 #define M_FCOE_FCHDR_FCTL 0xffffff 1625 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 1626 #define G_FCOE_FCHDR_FCTL(x) \ 1627 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 1628 1629 struct cpl_fcoe_data { 1630 RSS_HDR 1631 union opcode_tid ot; 1632 __u8 rsvd0[2]; 1633 __be16 len; 1634 __be32 seq; 1635 __u8 rsvd1[3]; 1636 __u8 status; 1637 }; 1638 1639 struct cpl_rx_urg_notify { 1640 RSS_HDR 1641 union opcode_tid ot; 1642 __be32 seq; 1643 }; 1644 1645 struct cpl_rx_urg_pkt { 1646 RSS_HDR 1647 union opcode_tid ot; 1648 __be16 rsvd; 1649 __be16 len; 1650 }; 1651 1652 struct cpl_rx_data_ack { 1653 WR_HDR; 1654 union opcode_tid ot; 1655 __be32 credit_dack; 1656 }; 1657 1658 struct cpl_rx_data_ack_core { 1659 union opcode_tid ot; 1660 __be32 credit_dack; 1661 }; 1662 1663 /* cpl_rx_data_ack.ack_seq fields */ 1664 #define S_RX_CREDITS 0 1665 #define M_RX_CREDITS 0x3FFFFFF 1666 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1667 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1668 1669 #define S_RX_MODULATE_TX 26 1670 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1671 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1672 1673 #define S_RX_MODULATE_RX 27 1674 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1675 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1676 1677 #define S_RX_FORCE_ACK 28 1678 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1679 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1680 1681 #define S_RX_DACK_MODE 29 1682 #define M_RX_DACK_MODE 0x3 1683 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1684 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1685 1686 #define S_RX_DACK_CHANGE 31 1687 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1688 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1689 1690 struct cpl_rx_ddp_complete { 1691 RSS_HDR 1692 union opcode_tid ot; 1693 __be32 ddp_report; 1694 __be32 rcv_nxt; 1695 __be32 rsvd; 1696 }; 1697 1698 struct cpl_rx_data_ddp { 1699 RSS_HDR 1700 union opcode_tid ot; 1701 __be16 urg; 1702 __be16 len; 1703 __be32 seq; 1704 union { 1705 __be32 nxt_seq; 1706 __be32 ddp_report; 1707 } u; 1708 __be32 ulp_crc; 1709 __be32 ddpvld; 1710 }; 1711 1712 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1713 1714 struct cpl_rx_fcoe_ddp { 1715 RSS_HDR 1716 union opcode_tid ot; 1717 __be16 rsvd; 1718 __be16 len; 1719 __be32 seq; 1720 __be32 ddp_report; 1721 __be32 ulp_crc; 1722 __be32 ddpvld; 1723 }; 1724 1725 struct cpl_rx_data_dif { 1726 RSS_HDR 1727 union opcode_tid ot; 1728 __be16 ddp_len; 1729 __be16 msg_len; 1730 __be32 seq; 1731 union { 1732 __be32 nxt_seq; 1733 __be32 ddp_report; 1734 } u; 1735 __be32 err_vec; 1736 __be32 ddpvld; 1737 }; 1738 1739 struct cpl_rx_iscsi_dif { 1740 RSS_HDR 1741 union opcode_tid ot; 1742 __be16 ddp_len; 1743 __be16 msg_len; 1744 __be32 seq; 1745 union { 1746 __be32 nxt_seq; 1747 __be32 ddp_report; 1748 } u; 1749 __be32 ulp_crc; 1750 __be32 ddpvld; 1751 __u8 rsvd0[8]; 1752 __be32 err_vec; 1753 __u8 rsvd1[4]; 1754 }; 1755 1756 struct cpl_rx_iscsi_cmp { 1757 RSS_HDR 1758 union opcode_tid ot; 1759 __be16 pdu_len_ddp; 1760 __be16 len; 1761 __be32 seq; 1762 __be16 urg; 1763 __u8 rsvd; 1764 __u8 status; 1765 __be32 ulp_crc; 1766 __be32 ddpvld; 1767 }; 1768 1769 struct cpl_rx_fcoe_dif { 1770 RSS_HDR 1771 union opcode_tid ot; 1772 __be16 ddp_len; 1773 __be16 msg_len; 1774 __be32 seq; 1775 __be32 ddp_report; 1776 __be32 err_vec; 1777 __be32 ddpvld; 1778 }; 1779 1780 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1781 #define S_DDP_VALID 15 1782 #define M_DDP_VALID 0x1FFFF 1783 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1784 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1785 1786 #define S_DDP_PPOD_MISMATCH 15 1787 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1788 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1789 1790 #define S_DDP_PDU 16 1791 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1792 #define F_DDP_PDU V_DDP_PDU(1U) 1793 1794 #define S_DDP_LLIMIT_ERR 17 1795 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1796 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1797 1798 #define S_DDP_PPOD_PARITY_ERR 18 1799 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1800 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1801 1802 #define S_DDP_PADDING_ERR 19 1803 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1804 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1805 1806 #define S_DDP_HDRCRC_ERR 20 1807 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1808 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1809 1810 #define S_DDP_DATACRC_ERR 21 1811 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1812 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1813 1814 #define S_DDP_INVALID_TAG 22 1815 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1816 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1817 1818 #define S_DDP_ULIMIT_ERR 23 1819 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1820 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1821 1822 #define S_DDP_OFFSET_ERR 24 1823 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1824 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1825 1826 #define S_DDP_COLOR_ERR 25 1827 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1828 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1829 1830 #define S_DDP_TID_MISMATCH 26 1831 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1832 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1833 1834 #define S_DDP_INVALID_PPOD 27 1835 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1836 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1837 1838 #define S_DDP_ULP_MODE 28 1839 #define M_DDP_ULP_MODE 0xF 1840 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1841 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1842 1843 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1844 #define S_DDP_OFFSET 0 1845 #define M_DDP_OFFSET 0xFFFFFF 1846 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1847 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1848 1849 #define S_DDP_DACK_MODE 24 1850 #define M_DDP_DACK_MODE 0x3 1851 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1852 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1853 1854 #define S_DDP_BUF_IDX 26 1855 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1856 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1857 1858 #define S_DDP_URG 27 1859 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1860 #define F_DDP_URG V_DDP_URG(1U) 1861 1862 #define S_DDP_PSH 28 1863 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1864 #define F_DDP_PSH V_DDP_PSH(1U) 1865 1866 #define S_DDP_BUF_COMPLETE 29 1867 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1868 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1869 1870 #define S_DDP_BUF_TIMED_OUT 30 1871 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1872 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1873 1874 #define S_DDP_INV 31 1875 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1876 #define F_DDP_INV V_DDP_INV(1U) 1877 1878 struct cpl_rx_pkt { 1879 RSS_HDR 1880 __u8 opcode; 1881 #if defined(__LITTLE_ENDIAN_BITFIELD) 1882 __u8 iff:4; 1883 __u8 csum_calc:1; 1884 __u8 ipmi_pkt:1; 1885 __u8 vlan_ex:1; 1886 __u8 ip_frag:1; 1887 #else 1888 __u8 ip_frag:1; 1889 __u8 vlan_ex:1; 1890 __u8 ipmi_pkt:1; 1891 __u8 csum_calc:1; 1892 __u8 iff:4; 1893 #endif 1894 __be16 csum; 1895 __be16 vlan; 1896 __be16 len; 1897 __be32 l2info; 1898 __be16 hdr_len; 1899 __be16 err_vec; 1900 }; 1901 1902 /* rx_pkt.l2info fields */ 1903 #define S_RX_ETHHDR_LEN 0 1904 #define M_RX_ETHHDR_LEN 0x1F 1905 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1906 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1907 1908 #define S_RX_T5_ETHHDR_LEN 0 1909 #define M_RX_T5_ETHHDR_LEN 0x3F 1910 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1911 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1912 1913 #define M_RX_T6_ETHHDR_LEN 0xFF 1914 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 1915 1916 #define S_RX_PKTYPE 5 1917 #define M_RX_PKTYPE 0x7 1918 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1919 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1920 1921 #define S_RX_T5_DATYPE 6 1922 #define M_RX_T5_DATYPE 0x3 1923 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1924 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1925 1926 #define S_RX_MACIDX 8 1927 #define M_RX_MACIDX 0x1FF 1928 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1929 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1930 1931 #define S_RX_T5_PKTYPE 17 1932 #define M_RX_T5_PKTYPE 0x7 1933 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1934 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1935 1936 #define S_RX_DATYPE 18 1937 #define M_RX_DATYPE 0x3 1938 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1939 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1940 1941 #define S_RXF_PSH 20 1942 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1943 #define F_RXF_PSH V_RXF_PSH(1U) 1944 1945 #define S_RXF_SYN 21 1946 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1947 #define F_RXF_SYN V_RXF_SYN(1U) 1948 1949 #define S_RXF_UDP 22 1950 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1951 #define F_RXF_UDP V_RXF_UDP(1U) 1952 1953 #define S_RXF_TCP 23 1954 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1955 #define F_RXF_TCP V_RXF_TCP(1U) 1956 1957 #define S_RXF_IP 24 1958 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1959 #define F_RXF_IP V_RXF_IP(1U) 1960 1961 #define S_RXF_IP6 25 1962 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1963 #define F_RXF_IP6 V_RXF_IP6(1U) 1964 1965 #define S_RXF_SYN_COOKIE 26 1966 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1967 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1968 1969 #define S_RXF_FCOE 26 1970 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1971 #define F_RXF_FCOE V_RXF_FCOE(1U) 1972 1973 #define S_RXF_LRO 27 1974 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1975 #define F_RXF_LRO V_RXF_LRO(1U) 1976 1977 #define S_RX_CHAN 28 1978 #define M_RX_CHAN 0xF 1979 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1980 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1981 1982 /* rx_pkt.hdr_len fields */ 1983 #define S_RX_TCPHDR_LEN 0 1984 #define M_RX_TCPHDR_LEN 0x3F 1985 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1986 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1987 1988 #define S_RX_IPHDR_LEN 6 1989 #define M_RX_IPHDR_LEN 0x3FF 1990 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1991 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1992 1993 /* rx_pkt.err_vec fields */ 1994 #define S_RXERR_OR 0 1995 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1996 #define F_RXERR_OR V_RXERR_OR(1U) 1997 1998 #define S_RXERR_MAC 1 1999 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 2000 #define F_RXERR_MAC V_RXERR_MAC(1U) 2001 2002 #define S_RXERR_IPVERS 2 2003 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 2004 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2005 2006 #define S_RXERR_FRAG 3 2007 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2008 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 2009 2010 #define S_RXERR_ATTACK 4 2011 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2012 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2013 2014 #define S_RXERR_ETHHDR_LEN 5 2015 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2016 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2017 2018 #define S_RXERR_IPHDR_LEN 6 2019 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2020 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2021 2022 #define S_RXERR_TCPHDR_LEN 7 2023 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2024 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2025 2026 #define S_RXERR_PKT_LEN 8 2027 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2028 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2029 2030 #define S_RXERR_TCP_OPT 9 2031 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2032 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2033 2034 #define S_RXERR_IPCSUM 12 2035 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2036 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2037 2038 #define S_RXERR_CSUM 13 2039 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2040 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 2041 2042 #define S_RXERR_PING 14 2043 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2044 #define F_RXERR_PING V_RXERR_PING(1U) 2045 2046 /* In T6, rx_pkt.err_vec indicates 2047 * RxError Error vector (16b) or 2048 * Encapsulating header length (8b), 2049 * Outer encapsulation type (2b) and 2050 * compressed error vector (6b) if CRxPktEnc is 2051 * enabled in TP_OUT_CONFIG 2052 */ 2053 2054 #define S_T6_COMPR_RXERR_VEC 0 2055 #define M_T6_COMPR_RXERR_VEC 0x3F 2056 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2057 #define G_T6_COMPR_RXERR_VEC(x) \ 2058 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2059 2060 #define S_T6_COMPR_RXERR_MAC 0 2061 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2062 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2063 2064 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2065 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2066 */ 2067 #define S_T6_COMPR_RXERR_LEN 1 2068 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2069 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2070 2071 #define S_T6_COMPR_RXERR_TCP_OPT 2 2072 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2073 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2074 2075 #define S_T6_COMPR_RXERR_IPV6_EXT 3 2076 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2077 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2078 2079 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2080 #define S_T6_COMPR_RXERR_SUM 4 2081 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2082 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2083 2084 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2085 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2086 */ 2087 #define S_T6_COMPR_RXERR_MISC 5 2088 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2089 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2090 2091 #define S_T6_RX_TNL_TYPE 6 2092 #define M_T6_RX_TNL_TYPE 0x3 2093 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2094 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2095 2096 #define RX_PKT_TNL_TYPE_NVGRE 1 2097 #define RX_PKT_TNL_TYPE_VXLAN 2 2098 #define RX_PKT_TNL_TYPE_GENEVE 3 2099 2100 #define S_T6_RX_TNLHDR_LEN 8 2101 #define M_T6_RX_TNLHDR_LEN 0xFF 2102 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2103 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2104 2105 struct cpl_trace_pkt { 2106 RSS_HDR 2107 __u8 opcode; 2108 __u8 intf; 2109 #if defined(__LITTLE_ENDIAN_BITFIELD) 2110 __u8 runt:4; 2111 __u8 filter_hit:4; 2112 __u8 :6; 2113 __u8 err:1; 2114 __u8 trunc:1; 2115 #else 2116 __u8 filter_hit:4; 2117 __u8 runt:4; 2118 __u8 trunc:1; 2119 __u8 err:1; 2120 __u8 :6; 2121 #endif 2122 __be16 rsvd; 2123 __be16 len; 2124 __be64 tstamp; 2125 }; 2126 2127 struct cpl_t5_trace_pkt { 2128 RSS_HDR 2129 __u8 opcode; 2130 __u8 intf; 2131 #if defined(__LITTLE_ENDIAN_BITFIELD) 2132 __u8 runt:4; 2133 __u8 filter_hit:4; 2134 __u8 :6; 2135 __u8 err:1; 2136 __u8 trunc:1; 2137 #else 2138 __u8 filter_hit:4; 2139 __u8 runt:4; 2140 __u8 trunc:1; 2141 __u8 err:1; 2142 __u8 :6; 2143 #endif 2144 __be16 rsvd; 2145 __be16 len; 2146 __be64 tstamp; 2147 __be64 rsvd1; 2148 }; 2149 2150 struct cpl_rte_delete_req { 2151 WR_HDR; 2152 union opcode_tid ot; 2153 __be32 params; 2154 }; 2155 2156 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2157 #define S_RTE_REQ_LUT_IX 8 2158 #define M_RTE_REQ_LUT_IX 0x7FF 2159 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2160 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2161 2162 #define S_RTE_REQ_LUT_BASE 19 2163 #define M_RTE_REQ_LUT_BASE 0x7FF 2164 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2165 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2166 2167 #define S_RTE_READ_REQ_SELECT 31 2168 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2169 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2170 2171 struct cpl_rte_delete_rpl { 2172 RSS_HDR 2173 union opcode_tid ot; 2174 __u8 status; 2175 __u8 rsvd[3]; 2176 }; 2177 2178 struct cpl_rte_write_req { 2179 WR_HDR; 2180 union opcode_tid ot; 2181 __u32 write_sel; 2182 __be32 lut_params; 2183 __be32 l2t_idx; 2184 __be32 netmask; 2185 __be32 faddr; 2186 }; 2187 2188 /* cpl_rte_write_req.write_sel fields */ 2189 #define S_RTE_WR_L2TIDX 31 2190 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2191 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2192 2193 #define S_RTE_WR_FADDR 30 2194 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2195 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2196 2197 /* cpl_rte_write_req.lut_params fields */ 2198 #define S_RTE_WR_LUT_IX 10 2199 #define M_RTE_WR_LUT_IX 0x7FF 2200 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2201 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2202 2203 #define S_RTE_WR_LUT_BASE 21 2204 #define M_RTE_WR_LUT_BASE 0x7FF 2205 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2206 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2207 2208 struct cpl_rte_write_rpl { 2209 RSS_HDR 2210 union opcode_tid ot; 2211 __u8 status; 2212 __u8 rsvd[3]; 2213 }; 2214 2215 struct cpl_rte_read_req { 2216 WR_HDR; 2217 union opcode_tid ot; 2218 __be32 params; 2219 }; 2220 2221 struct cpl_rte_read_rpl { 2222 RSS_HDR 2223 union opcode_tid ot; 2224 __u8 status; 2225 __u8 rsvd; 2226 __be16 l2t_idx; 2227 #if defined(__LITTLE_ENDIAN_BITFIELD) 2228 __u32 :30; 2229 __u32 select:1; 2230 #else 2231 __u32 select:1; 2232 __u32 :30; 2233 #endif 2234 __be32 addr; 2235 }; 2236 2237 struct cpl_l2t_write_req { 2238 WR_HDR; 2239 union opcode_tid ot; 2240 __be16 params; 2241 __be16 l2t_idx; 2242 __be16 vlan; 2243 __u8 dst_mac[6]; 2244 }; 2245 2246 /* cpl_l2t_write_req.params fields */ 2247 #define S_L2T_W_INFO 2 2248 #define M_L2T_W_INFO 0x3F 2249 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2250 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2251 2252 #define S_L2T_W_PORT 8 2253 #define M_L2T_W_PORT 0x3 2254 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2255 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2256 2257 #define S_L2T_W_LPBK 10 2258 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2259 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2260 2261 #define S_L2T_W_ARPMISS 11 2262 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2263 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2264 2265 #define S_L2T_W_NOREPLY 15 2266 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2267 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 2268 2269 #define CPL_L2T_VLAN_NONE 0xfff 2270 2271 struct cpl_l2t_write_rpl { 2272 RSS_HDR 2273 union opcode_tid ot; 2274 __u8 status; 2275 __u8 rsvd[3]; 2276 }; 2277 2278 struct cpl_l2t_read_req { 2279 WR_HDR; 2280 union opcode_tid ot; 2281 __be32 l2t_idx; 2282 }; 2283 2284 struct cpl_l2t_read_rpl { 2285 RSS_HDR 2286 union opcode_tid ot; 2287 __u8 status; 2288 #if defined(__LITTLE_ENDIAN_BITFIELD) 2289 __u8 :4; 2290 __u8 iff:4; 2291 #else 2292 __u8 iff:4; 2293 __u8 :4; 2294 #endif 2295 __be16 vlan; 2296 __be16 info; 2297 __u8 dst_mac[6]; 2298 }; 2299 2300 struct cpl_srq_table_req { 2301 WR_HDR; 2302 union opcode_tid ot; 2303 __u8 status; 2304 __u8 rsvd[2]; 2305 __u8 idx; 2306 __be64 rsvd_pdid; 2307 __be32 qlen_qbase; 2308 __be16 cur_msn; 2309 __be16 max_msn; 2310 }; 2311 2312 struct cpl_srq_table_rpl { 2313 RSS_HDR 2314 union opcode_tid ot; 2315 __u8 status; 2316 __u8 rsvd[2]; 2317 __u8 idx; 2318 __be64 rsvd_pdid; 2319 __be32 qlen_qbase; 2320 __be16 cur_msn; 2321 __be16 max_msn; 2322 }; 2323 2324 /* cpl_srq_table_{req,rpl}.params fields */ 2325 #define S_SRQT_QLEN 28 2326 #define M_SRQT_QLEN 0xF 2327 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 2328 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 2329 2330 #define S_SRQT_QBASE 0 2331 #define M_SRQT_QBASE 0x3FFFFFF 2332 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 2333 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 2334 2335 #define S_SRQT_PDID 0 2336 #define M_SRQT_PDID 0xFF 2337 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 2338 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 2339 2340 #define S_SRQT_IDX 0 2341 #define M_SRQT_IDX 0xF 2342 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 2343 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 2344 2345 struct cpl_smt_write_req { 2346 WR_HDR; 2347 union opcode_tid ot; 2348 __be32 params; 2349 __be16 pfvf1; 2350 __u8 src_mac1[6]; 2351 __be16 pfvf0; 2352 __u8 src_mac0[6]; 2353 }; 2354 2355 struct cpl_t6_smt_write_req { 2356 WR_HDR; 2357 union opcode_tid ot; 2358 __be32 params; 2359 __be64 tag; 2360 __be16 pfvf0; 2361 __u8 src_mac0[6]; 2362 __be32 local_ip; 2363 __be32 rsvd; 2364 }; 2365 2366 struct cpl_smt_write_rpl { 2367 RSS_HDR 2368 union opcode_tid ot; 2369 __u8 status; 2370 __u8 rsvd[3]; 2371 }; 2372 2373 struct cpl_smt_read_req { 2374 WR_HDR; 2375 union opcode_tid ot; 2376 __be32 params; 2377 }; 2378 2379 struct cpl_smt_read_rpl { 2380 RSS_HDR 2381 union opcode_tid ot; 2382 __u8 status; 2383 __u8 ovlan_idx; 2384 __be16 rsvd; 2385 __be16 pfvf1; 2386 __u8 src_mac1[6]; 2387 __be16 pfvf0; 2388 __u8 src_mac0[6]; 2389 }; 2390 2391 /* cpl_smt_{read,write}_req.params fields */ 2392 #define S_SMTW_OVLAN_IDX 16 2393 #define M_SMTW_OVLAN_IDX 0xF 2394 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2395 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2396 2397 #define S_SMTW_IDX 20 2398 #define M_SMTW_IDX 0x7F 2399 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2400 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2401 2402 #define M_T6_SMTW_IDX 0xFF 2403 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 2404 2405 #define S_SMTW_NORPL 31 2406 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2407 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2408 2409 /* cpl_smt_{read,write}_req.pfvf? fields */ 2410 #define S_SMTW_VF 0 2411 #define M_SMTW_VF 0xFF 2412 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2413 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2414 2415 #define S_SMTW_PF 8 2416 #define M_SMTW_PF 0x7 2417 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2418 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2419 2420 #define S_SMTW_VF_VLD 11 2421 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2422 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2423 2424 struct cpl_tag_write_req { 2425 WR_HDR; 2426 union opcode_tid ot; 2427 __be32 params; 2428 __be64 tag_val; 2429 }; 2430 2431 struct cpl_tag_write_rpl { 2432 RSS_HDR 2433 union opcode_tid ot; 2434 __u8 status; 2435 __u8 rsvd[2]; 2436 __u8 idx; 2437 }; 2438 2439 struct cpl_tag_read_req { 2440 WR_HDR; 2441 union opcode_tid ot; 2442 __be32 params; 2443 }; 2444 2445 struct cpl_tag_read_rpl { 2446 RSS_HDR 2447 union opcode_tid ot; 2448 __u8 status; 2449 #if defined(__LITTLE_ENDIAN_BITFIELD) 2450 __u8 :4; 2451 __u8 tag_len:1; 2452 __u8 :2; 2453 __u8 ins_enable:1; 2454 #else 2455 __u8 ins_enable:1; 2456 __u8 :2; 2457 __u8 tag_len:1; 2458 __u8 :4; 2459 #endif 2460 __u8 rsvd; 2461 __u8 tag_idx; 2462 __be64 tag_val; 2463 }; 2464 2465 /* cpl_tag{read,write}_req.params fields */ 2466 #define S_TAGW_IDX 0 2467 #define M_TAGW_IDX 0x7F 2468 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2469 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2470 2471 #define S_TAGW_LEN 20 2472 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2473 #define F_TAGW_LEN V_TAGW_LEN(1U) 2474 2475 #define S_TAGW_INS_ENABLE 23 2476 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2477 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2478 2479 #define S_TAGW_NORPL 31 2480 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2481 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2482 2483 struct cpl_barrier { 2484 WR_HDR; 2485 __u8 opcode; 2486 __u8 chan_map; 2487 __be16 rsvd0; 2488 __be32 rsvd1; 2489 }; 2490 2491 /* cpl_barrier.chan_map fields */ 2492 #define S_CHAN_MAP 4 2493 #define M_CHAN_MAP 0xF 2494 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2495 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2496 2497 struct cpl_error { 2498 RSS_HDR 2499 union opcode_tid ot; 2500 __be32 error; 2501 }; 2502 2503 struct cpl_hit_notify { 2504 RSS_HDR 2505 union opcode_tid ot; 2506 __be32 rsvd; 2507 __be32 info; 2508 __be32 reason; 2509 }; 2510 2511 struct cpl_pkt_notify { 2512 RSS_HDR 2513 union opcode_tid ot; 2514 __be16 rsvd; 2515 __be16 len; 2516 __be32 info; 2517 __be32 reason; 2518 }; 2519 2520 /* cpl_{hit,pkt}_notify.info fields */ 2521 #define S_NTFY_MAC_IDX 0 2522 #define M_NTFY_MAC_IDX 0x1FF 2523 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2524 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2525 2526 #define S_NTFY_INTF 10 2527 #define M_NTFY_INTF 0xF 2528 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2529 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2530 2531 #define S_NTFY_TCPHDR_LEN 14 2532 #define M_NTFY_TCPHDR_LEN 0xF 2533 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2534 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2535 2536 #define S_NTFY_IPHDR_LEN 18 2537 #define M_NTFY_IPHDR_LEN 0x1FF 2538 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2539 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2540 2541 #define S_NTFY_ETHHDR_LEN 27 2542 #define M_NTFY_ETHHDR_LEN 0x1F 2543 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2544 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2545 2546 #define S_NTFY_T5_IPHDR_LEN 18 2547 #define M_NTFY_T5_IPHDR_LEN 0xFF 2548 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2549 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2550 2551 #define S_NTFY_T5_ETHHDR_LEN 26 2552 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2553 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2554 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2555 2556 struct cpl_rdma_terminate { 2557 RSS_HDR 2558 union opcode_tid ot; 2559 __be16 rsvd; 2560 __be16 len; 2561 }; 2562 2563 struct cpl_set_le_req { 2564 WR_HDR; 2565 union opcode_tid ot; 2566 __be16 reply_ctrl; 2567 __be16 params; 2568 __be64 mask_hi; 2569 __be64 mask_lo; 2570 __be64 val_hi; 2571 __be64 val_lo; 2572 }; 2573 2574 /* cpl_set_le_req.reply_ctrl additional fields */ 2575 #define S_LE_REQ_IP6 13 2576 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2577 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2578 2579 /* cpl_set_le_req.params fields */ 2580 #define S_LE_CHAN 0 2581 #define M_LE_CHAN 0x3 2582 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2583 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2584 2585 #define S_LE_OFFSET 5 2586 #define M_LE_OFFSET 0x7 2587 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2588 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2589 2590 #define S_LE_MORE 8 2591 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2592 #define F_LE_MORE V_LE_MORE(1U) 2593 2594 #define S_LE_REQSIZE 9 2595 #define M_LE_REQSIZE 0x7 2596 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2597 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2598 2599 #define S_LE_REQCMD 12 2600 #define M_LE_REQCMD 0xF 2601 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2602 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2603 2604 struct cpl_set_le_rpl { 2605 RSS_HDR 2606 union opcode_tid ot; 2607 __u8 chan; 2608 __u8 info; 2609 __be16 len; 2610 }; 2611 2612 /* cpl_set_le_rpl.info fields */ 2613 #define S_LE_RSPCMD 0 2614 #define M_LE_RSPCMD 0xF 2615 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2616 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2617 2618 #define S_LE_RSPSIZE 4 2619 #define M_LE_RSPSIZE 0x7 2620 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2621 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2622 2623 #define S_LE_RSPTYPE 7 2624 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2625 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2626 2627 struct cpl_sge_egr_update { 2628 RSS_HDR 2629 __be32 opcode_qid; 2630 __be16 cidx; 2631 __be16 pidx; 2632 }; 2633 2634 /* cpl_sge_egr_update.ot fields */ 2635 #define S_AUTOEQU 22 2636 #define M_AUTOEQU 0x1 2637 #define V_AUTOEQU(x) ((x) << S_AUTOEQU) 2638 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 2639 2640 #define S_EGR_QID 0 2641 #define M_EGR_QID 0x1FFFF 2642 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2643 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2644 2645 /* cpl_fw*.type values */ 2646 enum { 2647 FW_TYPE_CMD_RPL = 0, 2648 FW_TYPE_WR_RPL = 1, 2649 FW_TYPE_CQE = 2, 2650 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2651 FW_TYPE_RSSCPL = 4, 2652 FW_TYPE_WRERR_RPL = 5, 2653 FW_TYPE_PI_ERR = 6, 2654 FW_TYPE_TLS_KEY = 7, 2655 }; 2656 2657 struct cpl_fw2_pld { 2658 RSS_HDR 2659 u8 opcode; 2660 u8 rsvd[5]; 2661 __be16 len; 2662 }; 2663 2664 struct cpl_fw4_pld { 2665 RSS_HDR 2666 u8 opcode; 2667 u8 rsvd0[3]; 2668 u8 type; 2669 u8 rsvd1; 2670 __be16 len; 2671 __be64 data; 2672 __be64 rsvd2; 2673 }; 2674 2675 struct cpl_fw6_pld { 2676 RSS_HDR 2677 u8 opcode; 2678 u8 rsvd[5]; 2679 __be16 len; 2680 __be64 data[4]; 2681 }; 2682 2683 struct cpl_fw2_msg { 2684 RSS_HDR 2685 union opcode_info oi; 2686 }; 2687 2688 struct cpl_fw4_msg { 2689 RSS_HDR 2690 u8 opcode; 2691 u8 type; 2692 __be16 rsvd0; 2693 __be32 rsvd1; 2694 __be64 data[2]; 2695 }; 2696 2697 struct cpl_fw4_ack { 2698 RSS_HDR 2699 union opcode_tid ot; 2700 u8 credits; 2701 u8 rsvd0[2]; 2702 u8 flags; 2703 __be32 snd_nxt; 2704 __be32 snd_una; 2705 __be64 rsvd1; 2706 }; 2707 2708 enum { 2709 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2710 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2711 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2712 }; 2713 2714 struct cpl_fw6_msg { 2715 RSS_HDR 2716 u8 opcode; 2717 u8 type; 2718 __be16 rsvd0; 2719 __be32 rsvd1; 2720 __be64 data[4]; 2721 }; 2722 2723 /* cpl_fw6_msg.type values */ 2724 enum { 2725 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2726 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2727 FW6_TYPE_CQE = FW_TYPE_CQE, 2728 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2729 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2730 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 2731 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 2732 NUM_FW6_TYPES 2733 }; 2734 2735 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2736 __u64 cookie; 2737 __be32 tid; /* or atid in case of active failure */ 2738 __u8 t_state; 2739 __u8 retval; 2740 __u8 rsvd[2]; 2741 }; 2742 2743 /* ULP_TX opcodes */ 2744 enum { 2745 ULP_TX_MEM_READ = 2, 2746 ULP_TX_MEM_WRITE = 3, 2747 ULP_TX_PKT = 4 2748 }; 2749 2750 enum { 2751 ULP_TX_SC_NOOP = 0x80, 2752 ULP_TX_SC_IMM = 0x81, 2753 ULP_TX_SC_DSGL = 0x82, 2754 ULP_TX_SC_ISGL = 0x83, 2755 ULP_TX_SC_PICTRL = 0x84, 2756 ULP_TX_SC_MEMRD = 0x86 2757 }; 2758 2759 #define S_ULPTX_CMD 24 2760 #define M_ULPTX_CMD 0xFF 2761 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2762 2763 #define S_ULPTX_LEN16 0 2764 #define M_ULPTX_LEN16 0xFF 2765 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2766 2767 #define S_ULP_TX_SC_MORE 23 2768 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2769 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2770 2771 struct ulptx_sge_pair { 2772 __be32 len[2]; 2773 __be64 addr[2]; 2774 }; 2775 2776 struct ulptx_sgl { 2777 __be32 cmd_nsge; 2778 __be32 len0; 2779 __be64 addr0; 2780 #if !(defined C99_NOT_SUPPORTED) 2781 struct ulptx_sge_pair sge[0]; 2782 #endif 2783 }; 2784 2785 struct ulptx_isge { 2786 __be32 stag; 2787 __be32 len; 2788 __be64 target_ofst; 2789 }; 2790 2791 struct ulptx_isgl { 2792 __be32 cmd_nisge; 2793 __be32 rsvd; 2794 #if !(defined C99_NOT_SUPPORTED) 2795 struct ulptx_isge sge[0]; 2796 #endif 2797 }; 2798 2799 struct ulptx_idata { 2800 __be32 cmd_more; 2801 __be32 len; 2802 }; 2803 2804 #define S_ULPTX_NSGE 0 2805 #define M_ULPTX_NSGE 0xFFFF 2806 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2807 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 2808 2809 struct ulptx_sc_memrd { 2810 __be32 cmd_to_len; 2811 __be32 addr; 2812 }; 2813 2814 struct ulp_mem_io { 2815 WR_HDR; 2816 __be32 cmd; 2817 __be32 len16; /* command length */ 2818 __be32 dlen; /* data length in 32-byte units */ 2819 __be32 lock_addr; 2820 }; 2821 2822 /* additional ulp_mem_io.cmd fields */ 2823 #define S_ULP_MEMIO_ORDER 23 2824 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2825 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2826 2827 #define S_T5_ULP_MEMIO_IMM 23 2828 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2829 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2830 2831 #define S_T5_ULP_MEMIO_ORDER 22 2832 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2833 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2834 2835 #define S_T5_ULP_MEMIO_FID 4 2836 #define M_T5_ULP_MEMIO_FID 0x7ff 2837 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 2838 2839 /* ulp_mem_io.lock_addr fields */ 2840 #define S_ULP_MEMIO_ADDR 0 2841 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2842 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2843 2844 #define S_ULP_MEMIO_LOCK 31 2845 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2846 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2847 2848 /* ulp_mem_io.dlen fields */ 2849 #define S_ULP_MEMIO_DATA_LEN 0 2850 #define M_ULP_MEMIO_DATA_LEN 0x1F 2851 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2852 2853 /* ULP_TXPKT field values */ 2854 enum { 2855 ULP_TXPKT_DEST_TP = 0, 2856 ULP_TXPKT_DEST_SGE, 2857 ULP_TXPKT_DEST_UP, 2858 ULP_TXPKT_DEST_DEVNULL, 2859 }; 2860 2861 struct ulp_txpkt { 2862 __be32 cmd_dest; 2863 __be32 len; 2864 }; 2865 2866 /* ulp_txpkt.cmd_dest fields */ 2867 #define S_ULP_TXPKT_DATAMODIFY 23 2868 #define M_ULP_TXPKT_DATAMODIFY 0x1 2869 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 2870 #define G_ULP_TXPKT_DATAMODIFY(x) \ 2871 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 2872 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 2873 2874 #define S_ULP_TXPKT_CHANNELID 22 2875 #define M_ULP_TXPKT_CHANNELID 0x1 2876 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 2877 #define G_ULP_TXPKT_CHANNELID(x) \ 2878 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 2879 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 2880 2881 /* ulp_txpkt.cmd_dest fields */ 2882 #define S_ULP_TXPKT_DEST 16 2883 #define M_ULP_TXPKT_DEST 0x3 2884 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2885 2886 #define S_ULP_TXPKT_FID 4 2887 #define M_ULP_TXPKT_FID 0x7ff 2888 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2889 2890 #define S_ULP_TXPKT_RO 3 2891 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2892 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2893 2894 enum cpl_tx_tnl_lso_type { 2895 TX_TNL_TYPE_OPAQUE, 2896 TX_TNL_TYPE_NVGRE, 2897 TX_TNL_TYPE_VXLAN, 2898 TX_TNL_TYPE_GENEVE, 2899 }; 2900 2901 struct cpl_tx_tnl_lso { 2902 __be32 op_to_IpIdSplitOut; 2903 __be16 IpIdOffsetOut; 2904 __be16 UdpLenSetOut_to_TnlHdrLen; 2905 __be64 r1; 2906 __be32 Flow_to_TcpHdrLen; 2907 __be16 IpIdOffset; 2908 __be16 IpIdSplit_to_Mss; 2909 __be32 TCPSeqOffset; 2910 __be32 EthLenOffset_Size; 2911 /* encapsulated CPL (TX_PKT_XT) follows here */ 2912 }; 2913 2914 #define S_CPL_TX_TNL_LSO_OPCODE 24 2915 #define M_CPL_TX_TNL_LSO_OPCODE 0xff 2916 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 2917 #define G_CPL_TX_TNL_LSO_OPCODE(x) \ 2918 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 2919 2920 #define S_CPL_TX_TNL_LSO_FIRST 23 2921 #define M_CPL_TX_TNL_LSO_FIRST 0x1 2922 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 2923 #define G_CPL_TX_TNL_LSO_FIRST(x) \ 2924 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 2925 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 2926 2927 #define S_CPL_TX_TNL_LSO_LAST 22 2928 #define M_CPL_TX_TNL_LSO_LAST 0x1 2929 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 2930 #define G_CPL_TX_TNL_LSO_LAST(x) \ 2931 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 2932 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 2933 2934 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 2935 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 2936 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 2937 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 2938 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 2939 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 2940 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 2941 2942 #define S_CPL_TX_TNL_LSO_IPV6OUT 20 2943 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 2944 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 2945 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 2946 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 2947 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 2948 2949 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 2950 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 2951 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 2952 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 2953 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 2954 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 2955 2956 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 2957 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 2958 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 2959 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 2960 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 2961 2962 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 2963 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 2964 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 2965 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 2966 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 2967 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 2968 2969 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 2970 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 2971 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 2972 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 2973 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 2974 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 2975 2976 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 2977 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 2978 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 2979 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 2980 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 2981 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 2982 2983 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 2984 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 2985 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 2986 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 2987 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 2988 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 2989 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 2990 2991 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 2992 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 2993 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 2994 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 2995 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 2996 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 2997 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 2998 2999 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 3000 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 3001 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3002 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3003 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3004 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3005 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 3006 3007 #define S_CPL_TX_TNL_LSO_TNLTYPE 12 3008 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 3009 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 3010 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 3011 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 3012 3013 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 3014 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 3015 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 3016 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 3017 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 3018 3019 #define S_CPL_TX_TNL_LSO_FLOW 21 3020 #define M_CPL_TX_TNL_LSO_FLOW 0x1 3021 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 3022 #define G_CPL_TX_TNL_LSO_FLOW(x) \ 3023 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 3024 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 3025 3026 #define S_CPL_TX_TNL_LSO_IPV6 20 3027 #define M_CPL_TX_TNL_LSO_IPV6 0x1 3028 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 3029 #define G_CPL_TX_TNL_LSO_IPV6(x) \ 3030 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 3031 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 3032 3033 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 3034 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 3035 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 3036 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 3037 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 3038 3039 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4 3040 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 3041 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 3042 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 3043 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 3044 3045 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 3046 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 3047 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 3048 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 3049 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 3050 3051 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 3052 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 3053 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 3054 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 3055 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 3056 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 3057 3058 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 3059 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 3060 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 3061 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 3062 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 3063 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 3064 3065 #define S_CPL_TX_TNL_LSO_MSS 0 3066 #define M_CPL_TX_TNL_LSO_MSS 0x3fff 3067 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 3068 #define G_CPL_TX_TNL_LSO_MSS(x) \ 3069 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 3070 3071 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 3072 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 3073 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3074 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 3075 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3076 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 3077 3078 #define S_CPL_TX_TNL_LSO_SIZE 0 3079 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 3080 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 3081 #define G_CPL_TX_TNL_LSO_SIZE(x) \ 3082 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 3083 3084 struct cpl_rx_mps_pkt { 3085 __be32 op_to_r1_hi; 3086 __be32 r1_lo_length; 3087 }; 3088 3089 #define S_CPL_RX_MPS_PKT_OP 24 3090 #define M_CPL_RX_MPS_PKT_OP 0xff 3091 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 3092 #define G_CPL_RX_MPS_PKT_OP(x) \ 3093 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 3094 3095 #define S_CPL_RX_MPS_PKT_TYPE 20 3096 #define M_CPL_RX_MPS_PKT_TYPE 0xf 3097 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 3098 #define G_CPL_RX_MPS_PKT_TYPE(x) \ 3099 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 3100 3101 /* 3102 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 3103 */ 3104 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 3105 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 3106 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 3107 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 3108 3109 struct cpl_tx_tls_sfo { 3110 __be32 op_to_seg_len; 3111 __be32 pld_len; 3112 __be32 type_protover; 3113 __be32 r1_lo; 3114 __be32 seqno_numivs; 3115 __be32 ivgen_hdrlen; 3116 __be64 scmd1; 3117 }; 3118 3119 /* cpl_tx_tls_sfo macros */ 3120 #define S_CPL_TX_TLS_SFO_OPCODE 24 3121 #define M_CPL_TX_TLS_SFO_OPCODE 0xff 3122 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 3123 #define G_CPL_TX_TLS_SFO_OPCODE(x) \ 3124 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 3125 3126 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20 3127 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 3128 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 3129 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 3130 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 3131 3132 #define S_CPL_TX_TLS_SFO_CPL_LEN 16 3133 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 3134 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 3135 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 3136 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 3137 3138 #define S_CPL_TX_TLS_SFO_SEG_LEN 0 3139 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 3140 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 3141 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 3142 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 3143 3144 #define S_CPL_TX_TLS_SFO_TYPE 24 3145 #define M_CPL_TX_TLS_SFO_TYPE 0xff 3146 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE) 3147 #define G_CPL_TX_TLS_SFO_TYPE(x) \ 3148 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE) 3149 3150 #define S_CPL_TX_TLS_SFO_PROTOVER 8 3151 #define M_CPL_TX_TLS_SFO_PROTOVER 0xffff 3152 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER) 3153 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \ 3154 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER) 3155 3156 struct cpl_tls_data { 3157 RSS_HDR 3158 union opcode_tid ot; 3159 __be32 length_pkd; 3160 __be32 seq; 3161 __be32 r1; 3162 }; 3163 3164 #define S_CPL_TLS_DATA_OPCODE 24 3165 #define M_CPL_TLS_DATA_OPCODE 0xff 3166 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 3167 #define G_CPL_TLS_DATA_OPCODE(x) \ 3168 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 3169 3170 #define S_CPL_TLS_DATA_TID 0 3171 #define M_CPL_TLS_DATA_TID 0xffffff 3172 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 3173 #define G_CPL_TLS_DATA_TID(x) \ 3174 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 3175 3176 #define S_CPL_TLS_DATA_LENGTH 0 3177 #define M_CPL_TLS_DATA_LENGTH 0xffff 3178 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 3179 #define G_CPL_TLS_DATA_LENGTH(x) \ 3180 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 3181 3182 struct cpl_rx_tls_cmp { 3183 RSS_HDR 3184 union opcode_tid ot; 3185 __be32 pdulength_length; 3186 __be32 seq; 3187 __be32 ddp_report; 3188 __be32 r; 3189 __be32 ddp_valid; 3190 }; 3191 3192 #define S_CPL_RX_TLS_CMP_OPCODE 24 3193 #define M_CPL_RX_TLS_CMP_OPCODE 0xff 3194 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 3195 #define G_CPL_RX_TLS_CMP_OPCODE(x) \ 3196 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 3197 3198 #define S_CPL_RX_TLS_CMP_TID 0 3199 #define M_CPL_RX_TLS_CMP_TID 0xffffff 3200 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 3201 #define G_CPL_RX_TLS_CMP_TID(x) \ 3202 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 3203 3204 #define S_CPL_RX_TLS_CMP_PDULENGTH 16 3205 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 3206 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 3207 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 3208 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 3209 3210 #define S_CPL_RX_TLS_CMP_LENGTH 0 3211 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff 3212 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 3213 #define G_CPL_RX_TLS_CMP_LENGTH(x) \ 3214 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 3215 3216 #define S_SCMD_SEQ_NO_CTRL 29 3217 #define M_SCMD_SEQ_NO_CTRL 0x3 3218 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 3219 #define G_SCMD_SEQ_NO_CTRL(x) \ 3220 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 3221 3222 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 3223 #define S_SCMD_STATUS_PRESENT 28 3224 #define M_SCMD_STATUS_PRESENT 0x1 3225 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 3226 #define G_SCMD_STATUS_PRESENT(x) \ 3227 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 3228 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 3229 3230 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 3231 * 3-15: Reserved. */ 3232 #define S_SCMD_PROTO_VERSION 24 3233 #define M_SCMD_PROTO_VERSION 0xf 3234 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 3235 #define G_SCMD_PROTO_VERSION(x) \ 3236 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 3237 3238 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 3239 #define S_SCMD_ENC_DEC_CTRL 23 3240 #define M_SCMD_ENC_DEC_CTRL 0x1 3241 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 3242 #define G_SCMD_ENC_DEC_CTRL(x) \ 3243 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 3244 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 3245 3246 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 3247 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 3248 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 3249 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3250 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 3251 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3252 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 3253 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 3254 3255 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 3256 * 4:Generic-AES, 5-15: Reserved. */ 3257 #define S_SCMD_CIPH_MODE 18 3258 #define M_SCMD_CIPH_MODE 0xf 3259 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 3260 #define G_SCMD_CIPH_MODE(x) \ 3261 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 3262 3263 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 3264 * 4-15: Reserved */ 3265 #define S_SCMD_AUTH_MODE 14 3266 #define M_SCMD_AUTH_MODE 0xf 3267 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 3268 #define G_SCMD_AUTH_MODE(x) \ 3269 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 3270 3271 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 3272 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 3273 */ 3274 #define S_SCMD_HMAC_CTRL 11 3275 #define M_SCMD_HMAC_CTRL 0x7 3276 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 3277 #define G_SCMD_HMAC_CTRL(x) \ 3278 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 3279 3280 /* IvSize - IV size in units of 2 bytes */ 3281 #define S_SCMD_IV_SIZE 7 3282 #define M_SCMD_IV_SIZE 0xf 3283 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 3284 #define G_SCMD_IV_SIZE(x) \ 3285 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 3286 3287 /* NumIVs - Number of IVs */ 3288 #define S_SCMD_NUM_IVS 0 3289 #define M_SCMD_NUM_IVS 0x7f 3290 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 3291 #define G_SCMD_NUM_IVS(x) \ 3292 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 3293 3294 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 3295 * (below) are used as Cid (connection id for debug status), these 3296 * bits are padded to zero for forming the 64 bit 3297 * sequence number for TLS 3298 */ 3299 #define S_SCMD_ENB_DBGID 31 3300 #define M_SCMD_ENB_DBGID 0x1 3301 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 3302 #define G_SCMD_ENB_DBGID(x) \ 3303 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 3304 3305 /* IV generation in SW. */ 3306 #define S_SCMD_IV_GEN_CTRL 30 3307 #define M_SCMD_IV_GEN_CTRL 0x1 3308 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 3309 #define G_SCMD_IV_GEN_CTRL(x) \ 3310 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 3311 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 3312 3313 /* More frags */ 3314 #define S_SCMD_MORE_FRAGS 20 3315 #define M_SCMD_MORE_FRAGS 0x1 3316 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 3317 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 3318 3319 /*last frag */ 3320 #define S_SCMD_LAST_FRAG 19 3321 #define M_SCMD_LAST_FRAG 0x1 3322 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 3323 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 3324 3325 /* TlsCompPdu */ 3326 #define S_SCMD_TLS_COMPPDU 18 3327 #define M_SCMD_TLS_COMPPDU 0x1 3328 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 3329 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 3330 3331 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 3332 #define S_SCMD_KEY_CTX_INLINE 17 3333 #define M_SCMD_KEY_CTX_INLINE 0x1 3334 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 3335 #define G_SCMD_KEY_CTX_INLINE(x) \ 3336 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 3337 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 3338 3339 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 3340 #define S_SCMD_TLS_FRAG_ENABLE 16 3341 #define M_SCMD_TLS_FRAG_ENABLE 0x1 3342 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 3343 #define G_SCMD_TLS_FRAG_ENABLE(x) \ 3344 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 3345 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 3346 3347 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 3348 * modes, in this case TLS_TX will drop the PDU and only 3349 * send back the MAC bytes. */ 3350 #define S_SCMD_MAC_ONLY 15 3351 #define M_SCMD_MAC_ONLY 0x1 3352 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 3353 #define G_SCMD_MAC_ONLY(x) \ 3354 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 3355 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 3356 3357 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 3358 * which have complex AAD and IV formations Eg:AES-CCM 3359 */ 3360 #define S_SCMD_AADIVDROP 14 3361 #define M_SCMD_AADIVDROP 0x1 3362 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 3363 #define G_SCMD_AADIVDROP(x) \ 3364 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 3365 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 3366 3367 /* HdrLength - Length of all headers excluding TLS header 3368 * present before start of crypto PDU/payload. */ 3369 #define S_SCMD_HDR_LEN 0 3370 #define M_SCMD_HDR_LEN 0x3fff 3371 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 3372 #define G_SCMD_HDR_LEN(x) \ 3373 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 3374 3375 struct cpl_tx_sec_pdu { 3376 __be32 op_ivinsrtofst; 3377 __be32 pldlen; 3378 __be32 aadstart_cipherstop_hi; 3379 __be32 cipherstop_lo_authinsert; 3380 __be32 seqno_numivs; 3381 __be32 ivgen_hdrlen; 3382 __be64 scmd1; 3383 }; 3384 3385 #define S_CPL_TX_SEC_PDU_OPCODE 24 3386 #define M_CPL_TX_SEC_PDU_OPCODE 0xff 3387 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 3388 #define G_CPL_TX_SEC_PDU_OPCODE(x) \ 3389 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 3390 3391 /* RX Channel Id */ 3392 #define S_CPL_TX_SEC_PDU_RXCHID 22 3393 #define M_CPL_TX_SEC_PDU_RXCHID 0x1 3394 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 3395 #define G_CPL_TX_SEC_PDU_RXCHID(x) \ 3396 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 3397 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 3398 3399 /* Ack Follows */ 3400 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 3401 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 3402 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 3403 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 3404 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 3405 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 3406 3407 /* Loopback bit in cpl_tx_sec_pdu */ 3408 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 3409 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 3410 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 3411 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 3412 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 3413 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 3414 3415 /* Length of cpl header encapsulated */ 3416 #define S_CPL_TX_SEC_PDU_CPLLEN 16 3417 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf 3418 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 3419 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 3420 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 3421 3422 /* PlaceHolder */ 3423 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 3424 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 3425 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 3426 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 3427 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 3428 M_CPL_TX_SEC_PDU_PLACEHOLDER) 3429 3430 /* IvInsrtOffset: Insertion location for IV */ 3431 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 3432 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 3433 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 3434 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 3435 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 3436 M_CPL_TX_SEC_PDU_IVINSRTOFST) 3437 3438 /* AadStartOffset: Offset in bytes for AAD start from 3439 * the first byte following 3440 * the pkt headers (0-255 3441 * bytes) */ 3442 #define S_CPL_TX_SEC_PDU_AADSTART 24 3443 #define M_CPL_TX_SEC_PDU_AADSTART 0xff 3444 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 3445 #define G_CPL_TX_SEC_PDU_AADSTART(x) \ 3446 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 3447 M_CPL_TX_SEC_PDU_AADSTART) 3448 3449 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 3450 * the pkt headers (0-511 bytes) */ 3451 #define S_CPL_TX_SEC_PDU_AADSTOP 15 3452 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 3453 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 3454 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 3455 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 3456 3457 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 3458 * first byte following the pkt headers (0-1023 3459 * bytes) */ 3460 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5 3461 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 3462 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 3463 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 3464 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 3465 M_CPL_TX_SEC_PDU_CIPHERSTART) 3466 3467 /* CipherStopOffset: offset in bytes for encryption/decryption end 3468 * from end of the payload of this command (0-511 bytes) */ 3469 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 3470 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 3471 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3472 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3473 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3474 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 3475 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3476 3477 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 3478 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 3479 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3480 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3481 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3482 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 3483 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3484 3485 /* AuthStartOffset: offset in bytes for authentication start from 3486 * the first byte following the pkt headers (0-1023) 3487 * */ 3488 #define S_CPL_TX_SEC_PDU_AUTHSTART 18 3489 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 3490 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 3491 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 3492 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 3493 M_CPL_TX_SEC_PDU_AUTHSTART) 3494 3495 /* AuthStopOffset: offset in bytes for authentication 3496 * end from end of the payload of this command (0-511 Bytes) */ 3497 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9 3498 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 3499 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 3500 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 3501 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 3502 M_CPL_TX_SEC_PDU_AUTHSTOP) 3503 3504 /* AuthInsrtOffset: offset in bytes for authentication insertion 3505 * from end of the payload of this command (0-511 bytes) */ 3506 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0 3507 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 3508 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 3509 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 3510 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 3511 M_CPL_TX_SEC_PDU_AUTHINSERT) 3512 3513 struct cpl_rx_phys_dsgl { 3514 __be32 op_to_tid; 3515 __be32 pcirlxorder_to_noofsgentr; 3516 struct rss_header rss_hdr_int; 3517 }; 3518 3519 #define S_CPL_RX_PHYS_DSGL_OPCODE 24 3520 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 3521 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 3522 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 3523 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 3524 3525 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23 3526 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 3527 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 3528 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 3529 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 3530 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 3531 3532 #define S_CPL_RX_PHYS_DSGL_RSVD1 20 3533 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 3534 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 3535 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 3536 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 3537 3538 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 3539 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 3540 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3541 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3542 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3543 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 3544 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3545 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 3546 3547 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 3548 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 3549 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3550 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3551 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3552 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 3553 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3554 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 3555 3556 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 3557 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 3558 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3559 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3560 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3561 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 3562 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3563 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 3564 3565 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 3566 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 3567 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 3568 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 3569 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 3570 M_CPL_RX_PHYS_DSGL_PCITPHNT) 3571 3572 #define S_CPL_RX_PHYS_DSGL_DCAID 16 3573 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 3574 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 3575 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 3576 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 3577 M_CPL_RX_PHYS_DSGL_DCAID) 3578 3579 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 3580 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 3581 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3582 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3583 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3584 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 3585 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3586 3587 /* CPL_TX_TLS_ACK */ 3588 struct cpl_tx_tls_ack { 3589 __be32 op_to_Rsvd2; 3590 __be32 PldLen; 3591 __be64 Rsvd3; 3592 }; 3593 3594 #define S_CPL_TX_TLS_ACK_OPCODE 24 3595 #define M_CPL_TX_TLS_ACK_OPCODE 0xff 3596 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 3597 #define G_CPL_TX_TLS_ACK_OPCODE(x) \ 3598 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 3599 3600 #define S_CPL_TX_TLS_ACK_RSVD1 23 3601 #define M_CPL_TX_TLS_ACK_RSVD1 0x1 3602 #define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1) 3603 #define G_CPL_TX_TLS_ACK_RSVD1(x) \ 3604 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1) 3605 #define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U) 3606 3607 #define S_CPL_TX_TLS_ACK_RXCHID 22 3608 #define M_CPL_TX_TLS_ACK_RXCHID 0x1 3609 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 3610 #define G_CPL_TX_TLS_ACK_RXCHID(x) \ 3611 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 3612 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 3613 3614 #define S_CPL_TX_TLS_ACK_FWMSG 21 3615 #define M_CPL_TX_TLS_ACK_FWMSG 0x1 3616 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 3617 #define G_CPL_TX_TLS_ACK_FWMSG(x) \ 3618 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 3619 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 3620 3621 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 3622 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 3623 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 3624 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 3625 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 3626 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 3627 3628 #define S_CPL_TX_TLS_ACK_CPLLEN 16 3629 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf 3630 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 3631 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 3632 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 3633 3634 #define S_CPL_TX_TLS_ACK_COMPLONERR 15 3635 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 3636 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 3637 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 3638 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 3639 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 3640 3641 #define S_CPL_TX_TLS_ACK_LCB 14 3642 #define M_CPL_TX_TLS_ACK_LCB 0x1 3643 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 3644 #define G_CPL_TX_TLS_ACK_LCB(x) \ 3645 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 3646 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 3647 3648 #define S_CPL_TX_TLS_ACK_PHASH 13 3649 #define M_CPL_TX_TLS_ACK_PHASH 0x1 3650 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 3651 #define G_CPL_TX_TLS_ACK_PHASH(x) \ 3652 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 3653 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 3654 3655 #define S_CPL_TX_TLS_ACK_RSVD2 0 3656 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 3657 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 3658 #define G_CPL_TX_TLS_ACK_RSVD2(x) \ 3659 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 3660 3661 #endif /* T4_MSG_H */ 3662