1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_PKT_ISO = 0x1F, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_URG_PKT = 0x29, 71 CPL_TAG_WRITE_RPL = 0x2A, 72 CPL_ABORT_REQ_RSS = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_ABORT_RPL_RSS = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_RX_PHYS_ADDR = 0x30, 79 CPL_PCMD_READ_RPL = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 CPL_SET_TCB_RPL = 0x3A, 89 CPL_RX_PKT = 0x3B, 90 CPL_TAG_READ_RPL = 0x3C, 91 CPL_HIT_NOTIFY = 0x3D, 92 CPL_PKT_NOTIFY = 0x3E, 93 CPL_RX_DDP_COMPLETE = 0x3F, 94 95 CPL_ACT_ESTABLISH = 0x40, 96 CPL_PASS_ESTABLISH = 0x41, 97 CPL_RX_DATA_DDP = 0x42, 98 CPL_SMT_READ_RPL = 0x43, 99 CPL_PASS_ACCEPT_REQ = 0x44, 100 CPL_RX2TX_PKT = 0x45, 101 CPL_RX_FCOE_DDP = 0x46, 102 CPL_FCOE_HDR = 0x47, 103 CPL_T5_TRACE_PKT = 0x48, 104 CPL_RX_ISCSI_DDP = 0x49, 105 CPL_RX_FCOE_DIF = 0x4A, 106 CPL_RX_DATA_DIF = 0x4B, 107 CPL_ERR_NOTIFY = 0x4D, 108 109 CPL_RDMA_READ_REQ = 0x60, 110 CPL_RX_ISCSI_DIF = 0x60, 111 112 CPL_SET_LE_REQ = 0x80, 113 CPL_PASS_OPEN_REQ6 = 0x81, 114 CPL_ACT_OPEN_REQ6 = 0x83, 115 116 CPL_RDMA_TERMINATE = 0xA2, 117 CPL_RDMA_WRITE = 0xA4, 118 CPL_SGE_EGR_UPDATE = 0xA5, 119 CPL_SET_LE_RPL = 0xA6, 120 CPL_FW2_MSG = 0xA7, 121 CPL_FW2_PLD = 0xA8, 122 CPL_T5_RDMA_READ_REQ = 0xA9, 123 CPL_RDMA_ATOMIC_REQ = 0xAA, 124 CPL_RDMA_ATOMIC_RPL = 0xAB, 125 CPL_RDMA_IMM_DATA = 0xAC, 126 CPL_RDMA_IMM_DATA_SE = 0xAD, 127 128 CPL_TRACE_PKT = 0xB0, 129 CPL_TRACE_PKT_T5 = 0x48, 130 CPL_RX2TX_DATA = 0xB1, 131 CPL_ISCSI_DATA = 0xB2, 132 CPL_FCOE_DATA = 0xB3, 133 134 CPL_FW4_MSG = 0xC0, 135 CPL_FW4_PLD = 0xC1, 136 CPL_FW4_ACK = 0xC3, 137 138 CPL_FW6_MSG = 0xE0, 139 CPL_FW6_PLD = 0xE1, 140 CPL_TX_PKT_LSO = 0xED, 141 CPL_TX_PKT_XT = 0xEE, 142 143 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 144 }; 145 146 enum CPL_error { 147 CPL_ERR_NONE = 0, 148 CPL_ERR_TCAM_PARITY = 1, 149 CPL_ERR_TCAM_FULL = 3, 150 CPL_ERR_BAD_LENGTH = 15, 151 CPL_ERR_BAD_ROUTE = 18, 152 CPL_ERR_CONN_RESET = 20, 153 CPL_ERR_CONN_EXIST_SYNRECV = 21, 154 CPL_ERR_CONN_EXIST = 22, 155 CPL_ERR_ARP_MISS = 23, 156 CPL_ERR_BAD_SYN = 24, 157 CPL_ERR_CONN_TIMEDOUT = 30, 158 CPL_ERR_XMIT_TIMEDOUT = 31, 159 CPL_ERR_PERSIST_TIMEDOUT = 32, 160 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 161 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 162 CPL_ERR_RTX_NEG_ADVICE = 35, 163 CPL_ERR_PERSIST_NEG_ADVICE = 36, 164 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 165 CPL_ERR_WAIT_ARP_RPL = 41, 166 CPL_ERR_ABORT_FAILED = 42, 167 CPL_ERR_IWARP_FLM = 50, 168 }; 169 170 enum { 171 CPL_CONN_POLICY_AUTO = 0, 172 CPL_CONN_POLICY_ASK = 1, 173 CPL_CONN_POLICY_FILTER = 2, 174 CPL_CONN_POLICY_DENY = 3 175 }; 176 177 enum { 178 ULP_MODE_NONE = 0, 179 ULP_MODE_ISCSI = 2, 180 ULP_MODE_RDMA = 4, 181 ULP_MODE_TCPDDP = 5, 182 ULP_MODE_FCOE = 6, 183 }; 184 185 enum { 186 ULP_CRC_HEADER = 1 << 0, 187 ULP_CRC_DATA = 1 << 1 188 }; 189 190 enum { 191 CPL_PASS_OPEN_ACCEPT, 192 CPL_PASS_OPEN_REJECT, 193 CPL_PASS_OPEN_ACCEPT_TNL 194 }; 195 196 enum { 197 CPL_ABORT_SEND_RST = 0, 198 CPL_ABORT_NO_RST, 199 }; 200 201 enum { /* TX_PKT_XT checksum types */ 202 TX_CSUM_TCP = 0, 203 TX_CSUM_UDP = 1, 204 TX_CSUM_CRC16 = 4, 205 TX_CSUM_CRC32 = 5, 206 TX_CSUM_CRC32C = 6, 207 TX_CSUM_FCOE = 7, 208 TX_CSUM_TCPIP = 8, 209 TX_CSUM_UDPIP = 9, 210 TX_CSUM_TCPIP6 = 10, 211 TX_CSUM_UDPIP6 = 11, 212 TX_CSUM_IP = 12, 213 }; 214 215 enum { /* packet type in CPL_RX_PKT */ 216 PKTYPE_XACT_UCAST = 0, 217 PKTYPE_HASH_UCAST = 1, 218 PKTYPE_XACT_MCAST = 2, 219 PKTYPE_HASH_MCAST = 3, 220 PKTYPE_PROMISC = 4, 221 PKTYPE_HPROMISC = 5, 222 PKTYPE_BCAST = 6 223 }; 224 225 enum { /* DMAC type in CPL_RX_PKT */ 226 DATYPE_UCAST, 227 DATYPE_MCAST, 228 DATYPE_BCAST 229 }; 230 231 enum { /* TCP congestion control algorithms */ 232 CONG_ALG_RENO, 233 CONG_ALG_TAHOE, 234 CONG_ALG_NEWRENO, 235 CONG_ALG_HIGHSPEED 236 }; 237 238 enum { /* RSS hash type */ 239 RSS_HASH_NONE = 0, /* no hash computed */ 240 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 241 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 242 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 243 }; 244 245 enum { /* LE commands */ 246 LE_CMD_READ = 0x4, 247 LE_CMD_WRITE = 0xb 248 }; 249 250 enum { /* LE request size */ 251 LE_SZ_NONE = 0, 252 LE_SZ_33 = 1, 253 LE_SZ_66 = 2, 254 LE_SZ_132 = 3, 255 LE_SZ_264 = 4, 256 LE_SZ_528 = 5 257 }; 258 259 union opcode_tid { 260 __be32 opcode_tid; 261 __u8 opcode; 262 }; 263 264 #define S_CPL_OPCODE 24 265 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 266 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 267 #define G_TID(x) ((x) & 0xFFFFFF) 268 269 /* tid is assumed to be 24-bits */ 270 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 271 272 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 273 274 /* extract the TID from a CPL command */ 275 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 276 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 277 278 /* partitioning of TID fields that also carry a queue id */ 279 #define S_TID_TID 0 280 #define M_TID_TID 0x3fff 281 #define V_TID_TID(x) ((x) << S_TID_TID) 282 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 283 284 #define S_TID_QID 14 285 #define M_TID_QID 0x3ff 286 #define V_TID_QID(x) ((x) << S_TID_QID) 287 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 288 289 union opcode_info { 290 __be64 opcode_info; 291 __u8 opcode; 292 }; 293 294 struct tcp_options { 295 __be16 mss; 296 __u8 wsf; 297 #if defined(__LITTLE_ENDIAN_BITFIELD) 298 __u8 :4; 299 __u8 unknown:1; 300 __u8 ecn:1; 301 __u8 sack:1; 302 __u8 tstamp:1; 303 #else 304 __u8 tstamp:1; 305 __u8 sack:1; 306 __u8 ecn:1; 307 __u8 unknown:1; 308 __u8 :4; 309 #endif 310 }; 311 312 struct rss_header { 313 __u8 opcode; 314 #if defined(__LITTLE_ENDIAN_BITFIELD) 315 __u8 channel:2; 316 __u8 filter_hit:1; 317 __u8 filter_tid:1; 318 __u8 hash_type:2; 319 __u8 ipv6:1; 320 __u8 send2fw:1; 321 #else 322 __u8 send2fw:1; 323 __u8 ipv6:1; 324 __u8 hash_type:2; 325 __u8 filter_tid:1; 326 __u8 filter_hit:1; 327 __u8 channel:2; 328 #endif 329 __be16 qid; 330 __be32 hash_val; 331 }; 332 333 #define S_HASHTYPE 20 334 #define M_HASHTYPE 0x3 335 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 336 337 #define S_QNUM 0 338 #define M_QNUM 0xFFFF 339 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 340 341 #ifndef CHELSIO_FW 342 struct work_request_hdr { 343 __be32 wr_hi; 344 __be32 wr_mid; 345 __be64 wr_lo; 346 }; 347 348 /* wr_mid fields */ 349 #define S_WR_LEN16 0 350 #define M_WR_LEN16 0xFF 351 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 352 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 353 354 /* wr_hi fields */ 355 #define S_WR_OP 24 356 #define M_WR_OP 0xFF 357 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 358 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 359 360 # define WR_HDR struct work_request_hdr wr 361 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 362 # define RSS_HDR 363 #else 364 # define WR_HDR 365 # define WR_HDR_SIZE 0 366 # define RSS_HDR struct rss_header rss_hdr; 367 #endif 368 369 /* option 0 fields */ 370 #define S_ACCEPT_MODE 0 371 #define M_ACCEPT_MODE 0x3 372 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 373 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 374 375 #define S_TX_CHAN 2 376 #define M_TX_CHAN 0x3 377 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 378 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 379 380 #define S_NO_CONG 4 381 #define V_NO_CONG(x) ((x) << S_NO_CONG) 382 #define F_NO_CONG V_NO_CONG(1U) 383 384 #define S_DELACK 5 385 #define V_DELACK(x) ((x) << S_DELACK) 386 #define F_DELACK V_DELACK(1U) 387 388 #define S_INJECT_TIMER 6 389 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 390 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 391 392 #define S_NON_OFFLOAD 7 393 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 394 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 395 396 #define S_ULP_MODE 8 397 #define M_ULP_MODE 0xF 398 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 399 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 400 401 #define S_RCV_BUFSIZ 12 402 #define M_RCV_BUFSIZ 0x3FFU 403 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 404 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 405 406 #define S_DSCP 22 407 #define M_DSCP 0x3F 408 #define V_DSCP(x) ((x) << S_DSCP) 409 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 410 411 #define S_SMAC_SEL 28 412 #define M_SMAC_SEL 0xFF 413 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 414 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 415 416 #define S_L2T_IDX 36 417 #define M_L2T_IDX 0xFFF 418 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 419 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 420 421 #define S_TCAM_BYPASS 48 422 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 423 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 424 425 #define S_NAGLE 49 426 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 427 #define F_NAGLE V_NAGLE(1ULL) 428 429 #define S_WND_SCALE 50 430 #define M_WND_SCALE 0xF 431 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 432 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 433 434 #define S_KEEP_ALIVE 54 435 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 436 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 437 438 #define S_MAX_RT 55 439 #define M_MAX_RT 0xF 440 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 441 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 442 443 #define S_MAX_RT_OVERRIDE 59 444 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 445 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 446 447 #define S_MSS_IDX 60 448 #define M_MSS_IDX 0xF 449 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 450 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 451 452 /* option 1 fields */ 453 #define S_SYN_RSS_ENABLE 0 454 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 455 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 456 457 #define S_SYN_RSS_USE_HASH 1 458 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 459 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 460 461 #define S_SYN_RSS_QUEUE 2 462 #define M_SYN_RSS_QUEUE 0x3FF 463 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 464 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 465 466 #define S_LISTEN_INTF 12 467 #define M_LISTEN_INTF 0xFF 468 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 469 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 470 471 #define S_LISTEN_FILTER 20 472 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 473 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 474 475 #define S_SYN_DEFENSE 21 476 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 477 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 478 479 #define S_CONN_POLICY 22 480 #define M_CONN_POLICY 0x3 481 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 482 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 483 484 #define S_FILT_INFO 28 485 #define M_FILT_INFO 0xfffffffffULL 486 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 487 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 488 489 /* option 2 fields */ 490 #define S_RSS_QUEUE 0 491 #define M_RSS_QUEUE 0x3FF 492 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 493 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 494 495 #define S_RSS_QUEUE_VALID 10 496 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 497 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 498 499 #define S_RX_COALESCE_VALID 11 500 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 501 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 502 503 #define S_RX_COALESCE 12 504 #define M_RX_COALESCE 0x3 505 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 506 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 507 508 #define S_CONG_CNTRL 14 509 #define M_CONG_CNTRL 0x3 510 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 511 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 512 513 #define S_PACE 16 514 #define M_PACE 0x3 515 #define V_PACE(x) ((x) << S_PACE) 516 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 517 518 #define S_CONG_CNTRL_VALID 18 519 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 520 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 521 522 #define S_PACE_VALID 19 523 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 524 #define F_PACE_VALID V_PACE_VALID(1U) 525 526 #define S_RX_FC_DISABLE 20 527 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 528 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 529 530 #define S_RX_FC_DDP 21 531 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 532 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 533 534 #define S_RX_FC_VALID 22 535 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 536 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 537 538 #define S_TX_QUEUE 23 539 #define M_TX_QUEUE 0x7 540 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 541 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 542 543 #define S_RX_CHANNEL 26 544 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 545 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 546 547 #define S_CCTRL_ECN 27 548 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 549 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 550 551 #define S_WND_SCALE_EN 28 552 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 553 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 554 555 #define S_TSTAMPS_EN 29 556 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 557 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 558 559 #define S_SACK_EN 30 560 #define V_SACK_EN(x) ((x) << S_SACK_EN) 561 #define F_SACK_EN V_SACK_EN(1U) 562 563 #define S_T5_OPT_2_VALID 31 564 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 565 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 566 567 struct cpl_pass_open_req { 568 WR_HDR; 569 union opcode_tid ot; 570 __be16 local_port; 571 __be16 peer_port; 572 __be32 local_ip; 573 __be32 peer_ip; 574 __be64 opt0; 575 __be64 opt1; 576 }; 577 578 struct cpl_pass_open_req6 { 579 WR_HDR; 580 union opcode_tid ot; 581 __be16 local_port; 582 __be16 peer_port; 583 __be64 local_ip_hi; 584 __be64 local_ip_lo; 585 __be64 peer_ip_hi; 586 __be64 peer_ip_lo; 587 __be64 opt0; 588 __be64 opt1; 589 }; 590 591 struct cpl_pass_open_rpl { 592 RSS_HDR 593 union opcode_tid ot; 594 __u8 rsvd[3]; 595 __u8 status; 596 }; 597 598 struct cpl_pass_establish { 599 RSS_HDR 600 union opcode_tid ot; 601 __be32 rsvd; 602 __be32 tos_stid; 603 __be16 mac_idx; 604 __be16 tcp_opt; 605 __be32 snd_isn; 606 __be32 rcv_isn; 607 }; 608 609 /* cpl_pass_establish.tos_stid fields */ 610 #define S_PASS_OPEN_TID 0 611 #define M_PASS_OPEN_TID 0xFFFFFF 612 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 613 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 614 615 #define S_PASS_OPEN_TOS 24 616 #define M_PASS_OPEN_TOS 0xFF 617 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 618 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 619 620 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 621 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 622 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 623 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 624 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 625 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 626 627 struct cpl_pass_accept_req { 628 RSS_HDR 629 union opcode_tid ot; 630 __be16 rsvd; 631 __be16 len; 632 __be32 hdr_len; 633 __be16 vlan; 634 __be16 l2info; 635 __be32 tos_stid; 636 struct tcp_options tcpopt; 637 }; 638 639 /* cpl_pass_accept_req.hdr_len fields */ 640 #define S_SYN_RX_CHAN 0 641 #define M_SYN_RX_CHAN 0xF 642 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 643 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 644 645 #define S_TCP_HDR_LEN 10 646 #define M_TCP_HDR_LEN 0x3F 647 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 648 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 649 650 #define S_IP_HDR_LEN 16 651 #define M_IP_HDR_LEN 0x3FF 652 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 653 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 654 655 #define S_ETH_HDR_LEN 26 656 #define M_ETH_HDR_LEN 0x3F 657 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 658 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 659 660 /* cpl_pass_accept_req.l2info fields */ 661 #define S_SYN_MAC_IDX 0 662 #define M_SYN_MAC_IDX 0x1FF 663 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 664 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 665 666 #define S_SYN_XACT_MATCH 9 667 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 668 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 669 670 #define S_SYN_INTF 12 671 #define M_SYN_INTF 0xF 672 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 673 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 674 675 struct cpl_pass_accept_rpl { 676 WR_HDR; 677 union opcode_tid ot; 678 __be32 opt2; 679 __be64 opt0; 680 }; 681 682 struct cpl_t5_pass_accept_rpl { 683 WR_HDR; 684 union opcode_tid ot; 685 __be32 opt2; 686 __be64 opt0; 687 __be32 iss; 688 __be32 rsvd; 689 }; 690 691 struct cpl_act_open_req { 692 WR_HDR; 693 union opcode_tid ot; 694 __be16 local_port; 695 __be16 peer_port; 696 __be32 local_ip; 697 __be32 peer_ip; 698 __be64 opt0; 699 __be32 params; 700 __be32 opt2; 701 }; 702 703 #define S_FILTER_TUPLE 24 704 #define M_FILTER_TUPLE 0xFFFFFFFFFF 705 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 706 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 707 struct cpl_t5_act_open_req { 708 WR_HDR; 709 union opcode_tid ot; 710 __be16 local_port; 711 __be16 peer_port; 712 __be32 local_ip; 713 __be32 peer_ip; 714 __be64 opt0; 715 __be32 iss; 716 __be32 opt2; 717 __be64 params; 718 }; 719 720 struct cpl_act_open_req6 { 721 WR_HDR; 722 union opcode_tid ot; 723 __be16 local_port; 724 __be16 peer_port; 725 __be64 local_ip_hi; 726 __be64 local_ip_lo; 727 __be64 peer_ip_hi; 728 __be64 peer_ip_lo; 729 __be64 opt0; 730 __be32 params; 731 __be32 opt2; 732 }; 733 734 struct cpl_t5_act_open_req6 { 735 WR_HDR; 736 union opcode_tid ot; 737 __be16 local_port; 738 __be16 peer_port; 739 __be64 local_ip_hi; 740 __be64 local_ip_lo; 741 __be64 peer_ip_hi; 742 __be64 peer_ip_lo; 743 __be64 opt0; 744 __be32 iss; 745 __be32 opt2; 746 __be64 params; 747 }; 748 749 struct cpl_act_open_rpl { 750 RSS_HDR 751 union opcode_tid ot; 752 __be32 atid_status; 753 }; 754 755 /* cpl_act_open_rpl.atid_status fields */ 756 #define S_AOPEN_STATUS 0 757 #define M_AOPEN_STATUS 0xFF 758 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 759 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 760 761 #define S_AOPEN_ATID 8 762 #define M_AOPEN_ATID 0xFFFFFF 763 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 764 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 765 766 struct cpl_act_establish { 767 RSS_HDR 768 union opcode_tid ot; 769 __be32 rsvd; 770 __be32 tos_atid; 771 __be16 mac_idx; 772 __be16 tcp_opt; 773 __be32 snd_isn; 774 __be32 rcv_isn; 775 }; 776 777 struct cpl_get_tcb { 778 WR_HDR; 779 union opcode_tid ot; 780 __be16 reply_ctrl; 781 __be16 cookie; 782 }; 783 784 /* cpl_get_tcb.reply_ctrl fields */ 785 #define S_QUEUENO 0 786 #define M_QUEUENO 0x3FF 787 #define V_QUEUENO(x) ((x) << S_QUEUENO) 788 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 789 790 #define S_REPLY_CHAN 14 791 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 792 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 793 794 #define S_NO_REPLY 15 795 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 796 #define F_NO_REPLY V_NO_REPLY(1U) 797 798 struct cpl_get_tcb_rpl { 799 RSS_HDR 800 union opcode_tid ot; 801 __u8 cookie; 802 __u8 status; 803 __be16 len; 804 }; 805 806 struct cpl_set_tcb { 807 WR_HDR; 808 union opcode_tid ot; 809 __be16 reply_ctrl; 810 __be16 cookie; 811 }; 812 813 struct cpl_set_tcb_field { 814 WR_HDR; 815 union opcode_tid ot; 816 __be16 reply_ctrl; 817 __be16 word_cookie; 818 __be64 mask; 819 __be64 val; 820 }; 821 822 struct cpl_set_tcb_field_core { 823 union opcode_tid ot; 824 __be16 reply_ctrl; 825 __be16 word_cookie; 826 __be64 mask; 827 __be64 val; 828 }; 829 830 /* cpl_set_tcb_field.word_cookie fields */ 831 #define S_WORD 0 832 #define M_WORD 0x1F 833 #define V_WORD(x) ((x) << S_WORD) 834 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 835 836 #define S_COOKIE 5 837 #define M_COOKIE 0x7 838 #define V_COOKIE(x) ((x) << S_COOKIE) 839 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 840 841 struct cpl_set_tcb_rpl { 842 RSS_HDR 843 union opcode_tid ot; 844 __be16 rsvd; 845 __u8 cookie; 846 __u8 status; 847 __be64 oldval; 848 }; 849 850 struct cpl_close_con_req { 851 WR_HDR; 852 union opcode_tid ot; 853 __be32 rsvd; 854 }; 855 856 struct cpl_close_con_rpl { 857 RSS_HDR 858 union opcode_tid ot; 859 __u8 rsvd[3]; 860 __u8 status; 861 __be32 snd_nxt; 862 __be32 rcv_nxt; 863 }; 864 865 struct cpl_close_listsvr_req { 866 WR_HDR; 867 union opcode_tid ot; 868 __be16 reply_ctrl; 869 __be16 rsvd; 870 }; 871 872 /* additional cpl_close_listsvr_req.reply_ctrl field */ 873 #define S_LISTSVR_IPV6 14 874 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 875 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 876 877 struct cpl_close_listsvr_rpl { 878 RSS_HDR 879 union opcode_tid ot; 880 __u8 rsvd[3]; 881 __u8 status; 882 }; 883 884 struct cpl_abort_req_rss { 885 RSS_HDR 886 union opcode_tid ot; 887 __u8 rsvd[3]; 888 __u8 status; 889 }; 890 891 struct cpl_abort_req { 892 WR_HDR; 893 union opcode_tid ot; 894 __be32 rsvd0; 895 __u8 rsvd1; 896 __u8 cmd; 897 __u8 rsvd2[6]; 898 }; 899 900 struct cpl_abort_rpl_rss { 901 RSS_HDR 902 union opcode_tid ot; 903 __u8 rsvd[3]; 904 __u8 status; 905 }; 906 907 struct cpl_abort_rpl { 908 WR_HDR; 909 union opcode_tid ot; 910 __be32 rsvd0; 911 __u8 rsvd1; 912 __u8 cmd; 913 __u8 rsvd2[6]; 914 }; 915 916 struct cpl_peer_close { 917 RSS_HDR 918 union opcode_tid ot; 919 __be32 rcv_nxt; 920 }; 921 922 struct cpl_tid_release { 923 WR_HDR; 924 union opcode_tid ot; 925 __be32 rsvd; 926 }; 927 928 struct tx_data_wr { 929 __be32 wr_hi; 930 __be32 wr_lo; 931 __be32 len; 932 __be32 flags; 933 __be32 sndseq; 934 __be32 param; 935 }; 936 937 /* tx_data_wr.flags fields */ 938 #define S_TX_ACK_PAGES 21 939 #define M_TX_ACK_PAGES 0x7 940 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 941 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 942 943 /* tx_data_wr.param fields */ 944 #define S_TX_PORT 0 945 #define M_TX_PORT 0x7 946 #define V_TX_PORT(x) ((x) << S_TX_PORT) 947 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 948 949 #define S_TX_MSS 4 950 #define M_TX_MSS 0xF 951 #define V_TX_MSS(x) ((x) << S_TX_MSS) 952 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 953 954 #define S_TX_QOS 8 955 #define M_TX_QOS 0xFF 956 #define V_TX_QOS(x) ((x) << S_TX_QOS) 957 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 958 959 #define S_TX_SNDBUF 16 960 #define M_TX_SNDBUF 0xFFFF 961 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 962 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 963 964 struct cpl_tx_data { 965 union opcode_tid ot; 966 __be32 len; 967 __be32 rsvd; 968 __be32 flags; 969 }; 970 971 /* cpl_tx_data.flags fields */ 972 #define S_TX_PROXY 5 973 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 974 #define F_TX_PROXY V_TX_PROXY(1U) 975 976 #define S_TX_ULP_SUBMODE 6 977 #define M_TX_ULP_SUBMODE 0xF 978 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 979 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 980 981 #define S_TX_ULP_MODE 10 982 #define M_TX_ULP_MODE 0xF 983 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 984 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 985 986 #define S_TX_SHOVE 14 987 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 988 #define F_TX_SHOVE V_TX_SHOVE(1U) 989 990 #define S_TX_MORE 15 991 #define V_TX_MORE(x) ((x) << S_TX_MORE) 992 #define F_TX_MORE V_TX_MORE(1U) 993 994 #define S_TX_URG 16 995 #define V_TX_URG(x) ((x) << S_TX_URG) 996 #define F_TX_URG V_TX_URG(1U) 997 998 #define S_TX_FLUSH 17 999 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1000 #define F_TX_FLUSH V_TX_FLUSH(1U) 1001 1002 #define S_TX_SAVE 18 1003 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1004 #define F_TX_SAVE V_TX_SAVE(1U) 1005 1006 #define S_TX_TNL 19 1007 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1008 #define F_TX_TNL V_TX_TNL(1U) 1009 1010 /* additional tx_data_wr.flags fields */ 1011 #define S_TX_CPU_IDX 0 1012 #define M_TX_CPU_IDX 0x3F 1013 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1014 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1015 1016 #define S_TX_CLOSE 17 1017 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1018 #define F_TX_CLOSE V_TX_CLOSE(1U) 1019 1020 #define S_TX_INIT 18 1021 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1022 #define F_TX_INIT V_TX_INIT(1U) 1023 1024 #define S_TX_IMM_ACK 19 1025 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1026 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1027 1028 #define S_TX_IMM_DMA 20 1029 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1030 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1031 1032 struct cpl_tx_data_ack { 1033 RSS_HDR 1034 union opcode_tid ot; 1035 __be32 snd_una; 1036 }; 1037 1038 struct cpl_wr_ack { /* XXX */ 1039 RSS_HDR 1040 union opcode_tid ot; 1041 __be16 credits; 1042 __be16 rsvd; 1043 __be32 snd_nxt; 1044 __be32 snd_una; 1045 }; 1046 1047 struct cpl_tx_pkt_core { 1048 __be32 ctrl0; 1049 __be16 pack; 1050 __be16 len; 1051 __be64 ctrl1; 1052 }; 1053 1054 struct cpl_tx_pkt { 1055 WR_HDR; 1056 struct cpl_tx_pkt_core c; 1057 }; 1058 1059 #define cpl_tx_pkt_xt cpl_tx_pkt 1060 1061 /* cpl_tx_pkt_core.ctrl0 fields */ 1062 #define S_TXPKT_VF 0 1063 #define M_TXPKT_VF 0xFF 1064 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1065 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1066 1067 #define S_TXPKT_PF 8 1068 #define M_TXPKT_PF 0x7 1069 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1070 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1071 1072 #define S_TXPKT_VF_VLD 11 1073 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1074 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1075 1076 #define S_TXPKT_OVLAN_IDX 12 1077 #define M_TXPKT_OVLAN_IDX 0xF 1078 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1079 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1080 1081 #define S_TXPKT_T5_OVLAN_IDX 12 1082 #define M_TXPKT_T5_OVLAN_IDX 0x7 1083 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1084 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1085 M_TXPKT_T5_OVLAN_IDX) 1086 1087 #define S_TXPKT_INTF 16 1088 #define M_TXPKT_INTF 0xF 1089 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1090 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1091 1092 #define S_TXPKT_SPECIAL_STAT 20 1093 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1094 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1095 1096 #define S_TXPKT_T5_FCS_DIS 21 1097 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1098 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1099 1100 #define S_TXPKT_INS_OVLAN 21 1101 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1102 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1103 1104 #define S_TXPKT_T5_INS_OVLAN 15 1105 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1106 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1107 1108 #define S_TXPKT_STAT_DIS 22 1109 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1110 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1111 1112 #define S_TXPKT_LOOPBACK 23 1113 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1114 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1115 1116 #define S_TXPKT_TSTAMP 23 1117 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1118 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1119 1120 #define S_TXPKT_OPCODE 24 1121 #define M_TXPKT_OPCODE 0xFF 1122 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1123 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1124 1125 /* cpl_tx_pkt_core.ctrl1 fields */ 1126 #define S_TXPKT_SA_IDX 0 1127 #define M_TXPKT_SA_IDX 0xFFF 1128 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1129 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1130 1131 #define S_TXPKT_CSUM_END 12 1132 #define M_TXPKT_CSUM_END 0xFF 1133 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1134 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1135 1136 #define S_TXPKT_CSUM_START 20 1137 #define M_TXPKT_CSUM_START 0x3FF 1138 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1139 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1140 1141 #define S_TXPKT_IPHDR_LEN 20 1142 #define M_TXPKT_IPHDR_LEN 0x3FFF 1143 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1144 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1145 1146 #define S_TXPKT_CSUM_LOC 30 1147 #define M_TXPKT_CSUM_LOC 0x3FF 1148 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1149 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1150 1151 #define S_TXPKT_ETHHDR_LEN 34 1152 #define M_TXPKT_ETHHDR_LEN 0x3F 1153 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1154 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1155 1156 #define S_TXPKT_CSUM_TYPE 40 1157 #define M_TXPKT_CSUM_TYPE 0xF 1158 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1159 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1160 1161 #define S_TXPKT_VLAN 44 1162 #define M_TXPKT_VLAN 0xFFFF 1163 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1164 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1165 1166 #define S_TXPKT_VLAN_VLD 60 1167 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1168 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1169 1170 #define S_TXPKT_IPSEC 61 1171 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1172 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1173 1174 #define S_TXPKT_IPCSUM_DIS 62 1175 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1176 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1177 1178 #define S_TXPKT_L4CSUM_DIS 63 1179 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1180 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1181 1182 struct cpl_tx_pkt_lso_core { 1183 __be32 lso_ctrl; 1184 __be16 ipid_ofst; 1185 __be16 mss; 1186 __be32 seqno_offset; 1187 __be32 len; 1188 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1189 }; 1190 1191 struct cpl_tx_pkt_lso { 1192 WR_HDR; 1193 struct cpl_tx_pkt_lso_core c; 1194 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1195 }; 1196 1197 struct cpl_tx_pkt_ufo_core { 1198 __be16 ethlen; 1199 __be16 iplen; 1200 __be16 udplen; 1201 __be16 mss; 1202 __be32 len; 1203 __be32 r1; 1204 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1205 }; 1206 1207 struct cpl_tx_pkt_ufo { 1208 WR_HDR; 1209 struct cpl_tx_pkt_ufo_core c; 1210 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1211 }; 1212 1213 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1214 #define S_LSO_TCPHDR_LEN 0 1215 #define M_LSO_TCPHDR_LEN 0xF 1216 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1217 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1218 1219 #define S_LSO_IPHDR_LEN 4 1220 #define M_LSO_IPHDR_LEN 0xFFF 1221 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1222 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1223 1224 #define S_LSO_ETHHDR_LEN 16 1225 #define M_LSO_ETHHDR_LEN 0xF 1226 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1227 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1228 1229 #define S_LSO_IPV6 20 1230 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1231 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1232 1233 #define S_LSO_OFLD_ENCAP 21 1234 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1235 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1236 1237 #define S_LSO_LAST_SLICE 22 1238 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1239 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1240 1241 #define S_LSO_FIRST_SLICE 23 1242 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1243 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1244 1245 #define S_LSO_OPCODE 24 1246 #define M_LSO_OPCODE 0xFF 1247 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1248 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1249 1250 #define S_LSO_T5_XFER_SIZE 0 1251 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1252 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1253 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1254 1255 /* cpl_tx_pkt_lso_core.mss fields */ 1256 #define S_LSO_MSS 0 1257 #define M_LSO_MSS 0x3FFF 1258 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1259 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1260 1261 #define S_LSO_IPID_SPLIT 15 1262 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1263 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1264 1265 struct cpl_tx_pkt_fso { 1266 WR_HDR; 1267 __be32 fso_ctrl; 1268 __be16 seqcnt_ofst; 1269 __be16 mtu; 1270 __be32 param_offset; 1271 __be32 len; 1272 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1273 }; 1274 1275 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1276 #define S_FSO_XCHG_CLASS 21 1277 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1278 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1279 1280 #define S_FSO_INITIATOR 20 1281 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1282 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1283 1284 #define S_FSO_FCHDR_LEN 12 1285 #define M_FSO_FCHDR_LEN 0xF 1286 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1287 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1288 1289 struct cpl_iscsi_hdr_no_rss { 1290 union opcode_tid ot; 1291 __be16 pdu_len_ddp; 1292 __be16 len; 1293 __be32 seq; 1294 __be16 urg; 1295 __u8 rsvd; 1296 __u8 status; 1297 }; 1298 1299 struct cpl_tx_data_iso { 1300 WR_HDR; 1301 __be32 iso_ctrl; 1302 __u8 rsvd; 1303 __u8 ahs_len; 1304 __be16 mss; 1305 __be32 burst_size; 1306 __be32 len; 1307 /* encapsulated CPL_TX_DATA follows here */ 1308 }; 1309 1310 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1311 #define S_ISO_CPLHDR_LEN 18 1312 #define M_ISO_CPLHDR_LEN 0xF 1313 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1314 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1315 1316 #define S_ISO_HDR_CRC 17 1317 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1318 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1319 1320 #define S_ISO_DATA_CRC 16 1321 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1322 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1323 1324 #define S_ISO_IMD_DATA_EN 15 1325 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1326 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1327 1328 #define S_ISO_PDU_TYPE 13 1329 #define M_ISO_PDU_TYPE 0x3 1330 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1331 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1332 1333 struct cpl_iscsi_hdr { 1334 RSS_HDR 1335 union opcode_tid ot; 1336 __be16 pdu_len_ddp; 1337 __be16 len; 1338 __be32 seq; 1339 __be16 urg; 1340 __u8 rsvd; 1341 __u8 status; 1342 }; 1343 1344 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1345 #define S_ISCSI_PDU_LEN 0 1346 #define M_ISCSI_PDU_LEN 0x7FFF 1347 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1348 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1349 1350 #define S_ISCSI_DDP 15 1351 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1352 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1353 1354 struct cpl_iscsi_data { 1355 RSS_HDR 1356 union opcode_tid ot; 1357 __u8 rsvd0[2]; 1358 __be16 len; 1359 __be32 seq; 1360 __be16 urg; 1361 __u8 rsvd1; 1362 __u8 status; 1363 }; 1364 1365 struct cpl_rx_data { 1366 RSS_HDR 1367 union opcode_tid ot; 1368 __be16 rsvd; 1369 __be16 len; 1370 __be32 seq; 1371 __be16 urg; 1372 #if defined(__LITTLE_ENDIAN_BITFIELD) 1373 __u8 dack_mode:2; 1374 __u8 psh:1; 1375 __u8 heartbeat:1; 1376 __u8 ddp_off:1; 1377 __u8 :3; 1378 #else 1379 __u8 :3; 1380 __u8 ddp_off:1; 1381 __u8 heartbeat:1; 1382 __u8 psh:1; 1383 __u8 dack_mode:2; 1384 #endif 1385 __u8 status; 1386 }; 1387 1388 struct cpl_fcoe_hdr { 1389 RSS_HDR 1390 union opcode_tid ot; 1391 __be16 oxid; 1392 __be16 len; 1393 __be32 rctl_fctl; 1394 __u8 cs_ctl; 1395 __u8 df_ctl; 1396 __u8 sof; 1397 __u8 eof; 1398 __be16 seq_cnt; 1399 __u8 seq_id; 1400 __u8 type; 1401 __be32 param; 1402 }; 1403 1404 struct cpl_fcoe_data { 1405 RSS_HDR 1406 union opcode_tid ot; 1407 __u8 rsvd0[2]; 1408 __be16 len; 1409 __be32 seq; 1410 __u8 rsvd1[3]; 1411 __u8 status; 1412 }; 1413 1414 struct cpl_rx_urg_notify { 1415 RSS_HDR 1416 union opcode_tid ot; 1417 __be32 seq; 1418 }; 1419 1420 struct cpl_rx_urg_pkt { 1421 RSS_HDR 1422 union opcode_tid ot; 1423 __be16 rsvd; 1424 __be16 len; 1425 }; 1426 1427 struct cpl_rx_data_ack { 1428 WR_HDR; 1429 union opcode_tid ot; 1430 __be32 credit_dack; 1431 }; 1432 1433 struct cpl_rx_data_ack_core { 1434 union opcode_tid ot; 1435 __be32 credit_dack; 1436 }; 1437 1438 /* cpl_rx_data_ack.ack_seq fields */ 1439 #define S_RX_CREDITS 0 1440 #define M_RX_CREDITS 0x3FFFFFF 1441 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1442 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1443 1444 #define S_RX_MODULATE_TX 26 1445 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1446 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1447 1448 #define S_RX_MODULATE_RX 27 1449 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1450 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1451 1452 #define S_RX_FORCE_ACK 28 1453 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1454 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1455 1456 #define S_RX_DACK_MODE 29 1457 #define M_RX_DACK_MODE 0x3 1458 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1459 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1460 1461 #define S_RX_DACK_CHANGE 31 1462 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1463 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1464 1465 struct cpl_rx_ddp_complete { 1466 RSS_HDR 1467 union opcode_tid ot; 1468 __be32 ddp_report; 1469 __be32 rcv_nxt; 1470 __be32 rsvd; 1471 }; 1472 1473 struct cpl_rx_data_ddp { 1474 RSS_HDR 1475 union opcode_tid ot; 1476 __be16 urg; 1477 __be16 len; 1478 __be32 seq; 1479 union { 1480 __be32 nxt_seq; 1481 __be32 ddp_report; 1482 } u; 1483 __be32 ulp_crc; 1484 __be32 ddpvld; 1485 }; 1486 1487 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1488 1489 struct cpl_rx_fcoe_ddp { 1490 RSS_HDR 1491 union opcode_tid ot; 1492 __be16 rsvd; 1493 __be16 len; 1494 __be32 seq; 1495 __be32 ddp_report; 1496 __be32 ulp_crc; 1497 __be32 ddpvld; 1498 }; 1499 1500 struct cpl_rx_data_dif { 1501 RSS_HDR 1502 union opcode_tid ot; 1503 __be16 ddp_len; 1504 __be16 msg_len; 1505 __be32 seq; 1506 union { 1507 __be32 nxt_seq; 1508 __be32 ddp_report; 1509 } u; 1510 __be32 err_vec; 1511 __be32 ddpvld; 1512 }; 1513 1514 struct cpl_rx_iscsi_dif { 1515 RSS_HDR 1516 union opcode_tid ot; 1517 __be16 ddp_len; 1518 __be16 msg_len; 1519 __be32 seq; 1520 union { 1521 __be32 nxt_seq; 1522 __be32 ddp_report; 1523 } u; 1524 __be32 ulp_crc; 1525 __be32 ddpvld; 1526 __u8 rsvd0[8]; 1527 __be32 err_vec; 1528 __u8 rsvd1[4]; 1529 }; 1530 1531 struct cpl_rx_fcoe_dif { 1532 RSS_HDR 1533 union opcode_tid ot; 1534 __be16 ddp_len; 1535 __be16 msg_len; 1536 __be32 seq; 1537 __be32 ddp_report; 1538 __be32 err_vec; 1539 __be32 ddpvld; 1540 }; 1541 1542 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1543 #define S_DDP_VALID 15 1544 #define M_DDP_VALID 0x1FFFF 1545 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1546 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1547 1548 #define S_DDP_PPOD_MISMATCH 15 1549 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1550 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1551 1552 #define S_DDP_PDU 16 1553 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1554 #define F_DDP_PDU V_DDP_PDU(1U) 1555 1556 #define S_DDP_LLIMIT_ERR 17 1557 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1558 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1559 1560 #define S_DDP_PPOD_PARITY_ERR 18 1561 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1562 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1563 1564 #define S_DDP_PADDING_ERR 19 1565 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1566 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1567 1568 #define S_DDP_HDRCRC_ERR 20 1569 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1570 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1571 1572 #define S_DDP_DATACRC_ERR 21 1573 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1574 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1575 1576 #define S_DDP_INVALID_TAG 22 1577 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1578 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1579 1580 #define S_DDP_ULIMIT_ERR 23 1581 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1582 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1583 1584 #define S_DDP_OFFSET_ERR 24 1585 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1586 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1587 1588 #define S_DDP_COLOR_ERR 25 1589 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1590 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1591 1592 #define S_DDP_TID_MISMATCH 26 1593 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1594 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1595 1596 #define S_DDP_INVALID_PPOD 27 1597 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1598 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1599 1600 #define S_DDP_ULP_MODE 28 1601 #define M_DDP_ULP_MODE 0xF 1602 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1603 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1604 1605 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1606 #define S_DDP_OFFSET 0 1607 #define M_DDP_OFFSET 0xFFFFFF 1608 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1609 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1610 1611 #define S_DDP_DACK_MODE 24 1612 #define M_DDP_DACK_MODE 0x3 1613 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1614 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1615 1616 #define S_DDP_BUF_IDX 26 1617 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1618 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1619 1620 #define S_DDP_URG 27 1621 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1622 #define F_DDP_URG V_DDP_URG(1U) 1623 1624 #define S_DDP_PSH 28 1625 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1626 #define F_DDP_PSH V_DDP_PSH(1U) 1627 1628 #define S_DDP_BUF_COMPLETE 29 1629 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1630 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1631 1632 #define S_DDP_BUF_TIMED_OUT 30 1633 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1634 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1635 1636 #define S_DDP_INV 31 1637 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1638 #define F_DDP_INV V_DDP_INV(1U) 1639 1640 struct cpl_rx_pkt { 1641 RSS_HDR 1642 __u8 opcode; 1643 #if defined(__LITTLE_ENDIAN_BITFIELD) 1644 __u8 iff:4; 1645 __u8 csum_calc:1; 1646 __u8 ipmi_pkt:1; 1647 __u8 vlan_ex:1; 1648 __u8 ip_frag:1; 1649 #else 1650 __u8 ip_frag:1; 1651 __u8 vlan_ex:1; 1652 __u8 ipmi_pkt:1; 1653 __u8 csum_calc:1; 1654 __u8 iff:4; 1655 #endif 1656 __be16 csum; 1657 __be16 vlan; 1658 __be16 len; 1659 __be32 l2info; 1660 __be16 hdr_len; 1661 __be16 err_vec; 1662 }; 1663 1664 /* rx_pkt.l2info fields */ 1665 #define S_RX_ETHHDR_LEN 0 1666 #define M_RX_ETHHDR_LEN 0x1F 1667 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1668 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1669 1670 #define S_RX_T5_ETHHDR_LEN 0 1671 #define M_RX_T5_ETHHDR_LEN 0x3F 1672 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1673 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1674 1675 #define S_RX_PKTYPE 5 1676 #define M_RX_PKTYPE 0x7 1677 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1678 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1679 1680 #define S_RX_T5_DATYPE 6 1681 #define M_RX_T5_DATYPE 0x3 1682 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1683 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1684 1685 #define S_RX_MACIDX 8 1686 #define M_RX_MACIDX 0x1FF 1687 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1688 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1689 1690 #define S_RX_T5_PKTYPE 17 1691 #define M_RX_T5_PKTYPE 0x7 1692 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1693 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1694 1695 #define S_RX_DATYPE 18 1696 #define M_RX_DATYPE 0x3 1697 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1698 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1699 1700 #define S_RXF_PSH 20 1701 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1702 #define F_RXF_PSH V_RXF_PSH(1U) 1703 1704 #define S_RXF_SYN 21 1705 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1706 #define F_RXF_SYN V_RXF_SYN(1U) 1707 1708 #define S_RXF_UDP 22 1709 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1710 #define F_RXF_UDP V_RXF_UDP(1U) 1711 1712 #define S_RXF_TCP 23 1713 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1714 #define F_RXF_TCP V_RXF_TCP(1U) 1715 1716 #define S_RXF_IP 24 1717 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1718 #define F_RXF_IP V_RXF_IP(1U) 1719 1720 #define S_RXF_IP6 25 1721 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1722 #define F_RXF_IP6 V_RXF_IP6(1U) 1723 1724 #define S_RXF_SYN_COOKIE 26 1725 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1726 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1727 1728 #define S_RXF_FCOE 26 1729 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1730 #define F_RXF_FCOE V_RXF_FCOE(1U) 1731 1732 #define S_RXF_LRO 27 1733 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1734 #define F_RXF_LRO V_RXF_LRO(1U) 1735 1736 #define S_RX_CHAN 28 1737 #define M_RX_CHAN 0xF 1738 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1739 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1740 1741 /* rx_pkt.hdr_len fields */ 1742 #define S_RX_TCPHDR_LEN 0 1743 #define M_RX_TCPHDR_LEN 0x3F 1744 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1745 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1746 1747 #define S_RX_IPHDR_LEN 6 1748 #define M_RX_IPHDR_LEN 0x3FF 1749 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1750 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1751 1752 /* rx_pkt.err_vec fields */ 1753 #define S_RXERR_OR 0 1754 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1755 #define F_RXERR_OR V_RXERR_OR(1U) 1756 1757 #define S_RXERR_MAC 1 1758 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1759 #define F_RXERR_MAC V_RXERR_MAC(1U) 1760 1761 #define S_RXERR_IPVERS 2 1762 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1763 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1764 1765 #define S_RXERR_FRAG 3 1766 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1767 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1768 1769 #define S_RXERR_ATTACK 4 1770 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1771 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1772 1773 #define S_RXERR_ETHHDR_LEN 5 1774 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1775 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1776 1777 #define S_RXERR_IPHDR_LEN 6 1778 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1779 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1780 1781 #define S_RXERR_TCPHDR_LEN 7 1782 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1783 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1784 1785 #define S_RXERR_PKT_LEN 8 1786 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1787 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1788 1789 #define S_RXERR_TCP_OPT 9 1790 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1791 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1792 1793 #define S_RXERR_IPCSUM 12 1794 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1795 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1796 1797 #define S_RXERR_CSUM 13 1798 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1799 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1800 1801 #define S_RXERR_PING 14 1802 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1803 #define F_RXERR_PING V_RXERR_PING(1U) 1804 1805 struct cpl_trace_pkt { 1806 RSS_HDR 1807 __u8 opcode; 1808 __u8 intf; 1809 #if defined(__LITTLE_ENDIAN_BITFIELD) 1810 __u8 runt:4; 1811 __u8 filter_hit:4; 1812 __u8 :6; 1813 __u8 err:1; 1814 __u8 trunc:1; 1815 #else 1816 __u8 filter_hit:4; 1817 __u8 runt:4; 1818 __u8 trunc:1; 1819 __u8 err:1; 1820 __u8 :6; 1821 #endif 1822 __be16 rsvd; 1823 __be16 len; 1824 __be64 tstamp; 1825 }; 1826 1827 struct cpl_t5_trace_pkt { 1828 RSS_HDR 1829 __u8 opcode; 1830 __u8 intf; 1831 #if defined(__LITTLE_ENDIAN_BITFIELD) 1832 __u8 runt:4; 1833 __u8 filter_hit:4; 1834 __u8 :6; 1835 __u8 err:1; 1836 __u8 trunc:1; 1837 #else 1838 __u8 filter_hit:4; 1839 __u8 runt:4; 1840 __u8 trunc:1; 1841 __u8 err:1; 1842 __u8 :6; 1843 #endif 1844 __be16 rsvd; 1845 __be16 len; 1846 __be64 tstamp; 1847 __be64 rsvd1; 1848 }; 1849 1850 struct cpl_rte_delete_req { 1851 WR_HDR; 1852 union opcode_tid ot; 1853 __be32 params; 1854 }; 1855 1856 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1857 #define S_RTE_REQ_LUT_IX 8 1858 #define M_RTE_REQ_LUT_IX 0x7FF 1859 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1860 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1861 1862 #define S_RTE_REQ_LUT_BASE 19 1863 #define M_RTE_REQ_LUT_BASE 0x7FF 1864 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1865 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1866 1867 #define S_RTE_READ_REQ_SELECT 31 1868 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1869 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1870 1871 struct cpl_rte_delete_rpl { 1872 RSS_HDR 1873 union opcode_tid ot; 1874 __u8 status; 1875 __u8 rsvd[3]; 1876 }; 1877 1878 struct cpl_rte_write_req { 1879 WR_HDR; 1880 union opcode_tid ot; 1881 __u32 write_sel; 1882 __be32 lut_params; 1883 __be32 l2t_idx; 1884 __be32 netmask; 1885 __be32 faddr; 1886 }; 1887 1888 /* cpl_rte_write_req.write_sel fields */ 1889 #define S_RTE_WR_L2TIDX 31 1890 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1891 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1892 1893 #define S_RTE_WR_FADDR 30 1894 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1895 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1896 1897 /* cpl_rte_write_req.lut_params fields */ 1898 #define S_RTE_WR_LUT_IX 10 1899 #define M_RTE_WR_LUT_IX 0x7FF 1900 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1901 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1902 1903 #define S_RTE_WR_LUT_BASE 21 1904 #define M_RTE_WR_LUT_BASE 0x7FF 1905 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1906 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1907 1908 struct cpl_rte_write_rpl { 1909 RSS_HDR 1910 union opcode_tid ot; 1911 __u8 status; 1912 __u8 rsvd[3]; 1913 }; 1914 1915 struct cpl_rte_read_req { 1916 WR_HDR; 1917 union opcode_tid ot; 1918 __be32 params; 1919 }; 1920 1921 struct cpl_rte_read_rpl { 1922 RSS_HDR 1923 union opcode_tid ot; 1924 __u8 status; 1925 __u8 rsvd; 1926 __be16 l2t_idx; 1927 #if defined(__LITTLE_ENDIAN_BITFIELD) 1928 __u32 :30; 1929 __u32 select:1; 1930 #else 1931 __u32 select:1; 1932 __u32 :30; 1933 #endif 1934 __be32 addr; 1935 }; 1936 1937 struct cpl_l2t_write_req { 1938 WR_HDR; 1939 union opcode_tid ot; 1940 __be16 params; 1941 __be16 l2t_idx; 1942 __be16 vlan; 1943 __u8 dst_mac[6]; 1944 }; 1945 1946 /* cpl_l2t_write_req.params fields */ 1947 #define S_L2T_W_INFO 2 1948 #define M_L2T_W_INFO 0x3F 1949 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1950 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1951 1952 #define S_L2T_W_PORT 8 1953 #define M_L2T_W_PORT 0x3 1954 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1955 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1956 1957 #define S_L2T_W_LPBK 10 1958 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 1959 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 1960 1961 #define S_L2T_W_ARPMISS 11 1962 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 1963 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 1964 1965 #define S_L2T_W_NOREPLY 15 1966 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1967 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1968 1969 #define CPL_L2T_VLAN_NONE 0xfff 1970 1971 struct cpl_l2t_write_rpl { 1972 RSS_HDR 1973 union opcode_tid ot; 1974 __u8 status; 1975 __u8 rsvd[3]; 1976 }; 1977 1978 struct cpl_l2t_read_req { 1979 WR_HDR; 1980 union opcode_tid ot; 1981 __be32 l2t_idx; 1982 }; 1983 1984 struct cpl_l2t_read_rpl { 1985 RSS_HDR 1986 union opcode_tid ot; 1987 __u8 status; 1988 #if defined(__LITTLE_ENDIAN_BITFIELD) 1989 __u8 :4; 1990 __u8 iff:4; 1991 #else 1992 __u8 iff:4; 1993 __u8 :4; 1994 #endif 1995 __be16 vlan; 1996 __be16 info; 1997 __u8 dst_mac[6]; 1998 }; 1999 2000 struct cpl_smt_write_req { 2001 WR_HDR; 2002 union opcode_tid ot; 2003 __be32 params; 2004 __be16 pfvf1; 2005 __u8 src_mac1[6]; 2006 __be16 pfvf0; 2007 __u8 src_mac0[6]; 2008 }; 2009 2010 struct cpl_smt_write_rpl { 2011 RSS_HDR 2012 union opcode_tid ot; 2013 __u8 status; 2014 __u8 rsvd[3]; 2015 }; 2016 2017 struct cpl_smt_read_req { 2018 WR_HDR; 2019 union opcode_tid ot; 2020 __be32 params; 2021 }; 2022 2023 struct cpl_smt_read_rpl { 2024 RSS_HDR 2025 union opcode_tid ot; 2026 __u8 status; 2027 __u8 ovlan_idx; 2028 __be16 rsvd; 2029 __be16 pfvf1; 2030 __u8 src_mac1[6]; 2031 __be16 pfvf0; 2032 __u8 src_mac0[6]; 2033 }; 2034 2035 /* cpl_smt_{read,write}_req.params fields */ 2036 #define S_SMTW_OVLAN_IDX 16 2037 #define M_SMTW_OVLAN_IDX 0xF 2038 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2039 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2040 2041 #define S_SMTW_IDX 20 2042 #define M_SMTW_IDX 0x7F 2043 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2044 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2045 2046 #define S_SMTW_NORPL 31 2047 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2048 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2049 2050 /* cpl_smt_{read,write}_req.pfvf? fields */ 2051 #define S_SMTW_VF 0 2052 #define M_SMTW_VF 0xFF 2053 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2054 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2055 2056 #define S_SMTW_PF 8 2057 #define M_SMTW_PF 0x7 2058 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2059 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2060 2061 #define S_SMTW_VF_VLD 11 2062 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2063 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2064 2065 struct cpl_tag_write_req { 2066 WR_HDR; 2067 union opcode_tid ot; 2068 __be32 params; 2069 __be64 tag_val; 2070 }; 2071 2072 struct cpl_tag_write_rpl { 2073 RSS_HDR 2074 union opcode_tid ot; 2075 __u8 status; 2076 __u8 rsvd[2]; 2077 __u8 idx; 2078 }; 2079 2080 struct cpl_tag_read_req { 2081 WR_HDR; 2082 union opcode_tid ot; 2083 __be32 params; 2084 }; 2085 2086 struct cpl_tag_read_rpl { 2087 RSS_HDR 2088 union opcode_tid ot; 2089 __u8 status; 2090 #if defined(__LITTLE_ENDIAN_BITFIELD) 2091 __u8 :4; 2092 __u8 tag_len:1; 2093 __u8 :2; 2094 __u8 ins_enable:1; 2095 #else 2096 __u8 ins_enable:1; 2097 __u8 :2; 2098 __u8 tag_len:1; 2099 __u8 :4; 2100 #endif 2101 __u8 rsvd; 2102 __u8 tag_idx; 2103 __be64 tag_val; 2104 }; 2105 2106 /* cpl_tag{read,write}_req.params fields */ 2107 #define S_TAGW_IDX 0 2108 #define M_TAGW_IDX 0x7F 2109 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2110 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2111 2112 #define S_TAGW_LEN 20 2113 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2114 #define F_TAGW_LEN V_TAGW_LEN(1U) 2115 2116 #define S_TAGW_INS_ENABLE 23 2117 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2118 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2119 2120 #define S_TAGW_NORPL 31 2121 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2122 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2123 2124 struct cpl_barrier { 2125 WR_HDR; 2126 __u8 opcode; 2127 __u8 chan_map; 2128 __be16 rsvd0; 2129 __be32 rsvd1; 2130 }; 2131 2132 /* cpl_barrier.chan_map fields */ 2133 #define S_CHAN_MAP 4 2134 #define M_CHAN_MAP 0xF 2135 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2136 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2137 2138 struct cpl_error { 2139 RSS_HDR 2140 union opcode_tid ot; 2141 __be32 error; 2142 }; 2143 2144 struct cpl_hit_notify { 2145 RSS_HDR 2146 union opcode_tid ot; 2147 __be32 rsvd; 2148 __be32 info; 2149 __be32 reason; 2150 }; 2151 2152 struct cpl_pkt_notify { 2153 RSS_HDR 2154 union opcode_tid ot; 2155 __be16 rsvd; 2156 __be16 len; 2157 __be32 info; 2158 __be32 reason; 2159 }; 2160 2161 /* cpl_{hit,pkt}_notify.info fields */ 2162 #define S_NTFY_MAC_IDX 0 2163 #define M_NTFY_MAC_IDX 0x1FF 2164 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2165 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2166 2167 #define S_NTFY_INTF 10 2168 #define M_NTFY_INTF 0xF 2169 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2170 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2171 2172 #define S_NTFY_TCPHDR_LEN 14 2173 #define M_NTFY_TCPHDR_LEN 0xF 2174 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2175 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2176 2177 #define S_NTFY_IPHDR_LEN 18 2178 #define M_NTFY_IPHDR_LEN 0x1FF 2179 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2180 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2181 2182 #define S_NTFY_ETHHDR_LEN 27 2183 #define M_NTFY_ETHHDR_LEN 0x1F 2184 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2185 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2186 2187 #define S_NTFY_T5_IPHDR_LEN 18 2188 #define M_NTFY_T5_IPHDR_LEN 0xFF 2189 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2190 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2191 2192 #define S_NTFY_T5_ETHHDR_LEN 26 2193 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2194 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2195 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2196 2197 struct cpl_rdma_terminate { 2198 RSS_HDR 2199 union opcode_tid ot; 2200 __be16 rsvd; 2201 __be16 len; 2202 }; 2203 2204 struct cpl_set_le_req { 2205 WR_HDR; 2206 union opcode_tid ot; 2207 __be16 reply_ctrl; 2208 __be16 params; 2209 __be64 mask_hi; 2210 __be64 mask_lo; 2211 __be64 val_hi; 2212 __be64 val_lo; 2213 }; 2214 2215 /* cpl_set_le_req.reply_ctrl additional fields */ 2216 #define S_LE_REQ_IP6 13 2217 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2218 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2219 2220 /* cpl_set_le_req.params fields */ 2221 #define S_LE_CHAN 0 2222 #define M_LE_CHAN 0x3 2223 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2224 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2225 2226 #define S_LE_OFFSET 5 2227 #define M_LE_OFFSET 0x7 2228 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2229 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2230 2231 #define S_LE_MORE 8 2232 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2233 #define F_LE_MORE V_LE_MORE(1U) 2234 2235 #define S_LE_REQSIZE 9 2236 #define M_LE_REQSIZE 0x7 2237 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2238 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2239 2240 #define S_LE_REQCMD 12 2241 #define M_LE_REQCMD 0xF 2242 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2243 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2244 2245 struct cpl_set_le_rpl { 2246 RSS_HDR 2247 union opcode_tid ot; 2248 __u8 chan; 2249 __u8 info; 2250 __be16 len; 2251 }; 2252 2253 /* cpl_set_le_rpl.info fields */ 2254 #define S_LE_RSPCMD 0 2255 #define M_LE_RSPCMD 0xF 2256 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2257 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2258 2259 #define S_LE_RSPSIZE 4 2260 #define M_LE_RSPSIZE 0x7 2261 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2262 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2263 2264 #define S_LE_RSPTYPE 7 2265 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2266 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2267 2268 struct cpl_sge_egr_update { 2269 RSS_HDR 2270 __be32 opcode_qid; 2271 __be16 cidx; 2272 __be16 pidx; 2273 }; 2274 2275 /* cpl_sge_egr_update.ot fields */ 2276 #define S_EGR_QID 0 2277 #define M_EGR_QID 0x1FFFF 2278 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2279 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2280 2281 /* cpl_fw*.type values */ 2282 enum { 2283 FW_TYPE_CMD_RPL = 0, 2284 FW_TYPE_WR_RPL = 1, 2285 FW_TYPE_CQE = 2, 2286 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2287 FW_TYPE_RSSCPL = 4, 2288 }; 2289 2290 struct cpl_fw2_pld { 2291 RSS_HDR 2292 u8 opcode; 2293 u8 rsvd[5]; 2294 __be16 len; 2295 }; 2296 2297 struct cpl_fw4_pld { 2298 RSS_HDR 2299 u8 opcode; 2300 u8 rsvd0[3]; 2301 u8 type; 2302 u8 rsvd1; 2303 __be16 len; 2304 __be64 data; 2305 __be64 rsvd2; 2306 }; 2307 2308 struct cpl_fw6_pld { 2309 RSS_HDR 2310 u8 opcode; 2311 u8 rsvd[5]; 2312 __be16 len; 2313 __be64 data[4]; 2314 }; 2315 2316 struct cpl_fw2_msg { 2317 RSS_HDR 2318 union opcode_info oi; 2319 }; 2320 2321 struct cpl_fw4_msg { 2322 RSS_HDR 2323 u8 opcode; 2324 u8 type; 2325 __be16 rsvd0; 2326 __be32 rsvd1; 2327 __be64 data[2]; 2328 }; 2329 2330 struct cpl_fw4_ack { 2331 RSS_HDR 2332 union opcode_tid ot; 2333 u8 credits; 2334 u8 rsvd0[2]; 2335 u8 flags; 2336 __be32 snd_nxt; 2337 __be32 snd_una; 2338 __be64 rsvd1; 2339 }; 2340 2341 enum { 2342 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2343 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2344 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2345 }; 2346 2347 struct cpl_fw6_msg { 2348 RSS_HDR 2349 u8 opcode; 2350 u8 type; 2351 __be16 rsvd0; 2352 __be32 rsvd1; 2353 __be64 data[4]; 2354 }; 2355 2356 /* cpl_fw6_msg.type values */ 2357 enum { 2358 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2359 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2360 FW6_TYPE_CQE = FW_TYPE_CQE, 2361 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2362 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2363 2364 NUM_FW6_TYPES 2365 }; 2366 2367 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2368 __u64 cookie; 2369 __be32 tid; /* or atid in case of active failure */ 2370 __u8 t_state; 2371 __u8 retval; 2372 __u8 rsvd[2]; 2373 }; 2374 2375 /* ULP_TX opcodes */ 2376 enum { 2377 ULP_TX_MEM_READ = 2, 2378 ULP_TX_MEM_WRITE = 3, 2379 ULP_TX_PKT = 4 2380 }; 2381 2382 enum { 2383 ULP_TX_SC_NOOP = 0x80, 2384 ULP_TX_SC_IMM = 0x81, 2385 ULP_TX_SC_DSGL = 0x82, 2386 ULP_TX_SC_ISGL = 0x83 2387 }; 2388 2389 #define S_ULPTX_CMD 24 2390 #define M_ULPTX_CMD 0xFF 2391 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2392 2393 #define S_ULPTX_LEN16 0 2394 #define M_ULPTX_LEN16 0xFF 2395 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2396 2397 #define S_ULP_TX_SC_MORE 23 2398 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2399 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2400 2401 struct ulptx_sge_pair { 2402 __be32 len[2]; 2403 __be64 addr[2]; 2404 }; 2405 2406 struct ulptx_sgl { 2407 __be32 cmd_nsge; 2408 __be32 len0; 2409 __be64 addr0; 2410 #if !(defined C99_NOT_SUPPORTED) 2411 struct ulptx_sge_pair sge[0]; 2412 #endif 2413 }; 2414 2415 struct ulptx_isge { 2416 __be32 stag; 2417 __be32 len; 2418 __be64 target_ofst; 2419 }; 2420 2421 struct ulptx_isgl { 2422 __be32 cmd_nisge; 2423 __be32 rsvd; 2424 #if !(defined C99_NOT_SUPPORTED) 2425 struct ulptx_isge sge[0]; 2426 #endif 2427 }; 2428 2429 struct ulptx_idata { 2430 __be32 cmd_more; 2431 __be32 len; 2432 }; 2433 2434 #define S_ULPTX_NSGE 0 2435 #define M_ULPTX_NSGE 0xFFFF 2436 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2437 2438 struct ulp_mem_io { 2439 WR_HDR; 2440 __be32 cmd; 2441 __be32 len16; /* command length */ 2442 __be32 dlen; /* data length in 32-byte units */ 2443 __be32 lock_addr; 2444 }; 2445 2446 /* additional ulp_mem_io.cmd fields */ 2447 #define S_ULP_MEMIO_ORDER 23 2448 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2449 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2450 2451 #define S_T5_ULP_MEMIO_IMM 23 2452 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2453 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2454 2455 #define S_T5_ULP_MEMIO_ORDER 22 2456 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2457 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2458 2459 /* ulp_mem_io.lock_addr fields */ 2460 #define S_ULP_MEMIO_ADDR 0 2461 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2462 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2463 2464 #define S_ULP_MEMIO_LOCK 31 2465 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2466 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2467 2468 /* ulp_mem_io.dlen fields */ 2469 #define S_ULP_MEMIO_DATA_LEN 0 2470 #define M_ULP_MEMIO_DATA_LEN 0x1F 2471 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2472 2473 /* ULP_TXPKT field values */ 2474 enum { 2475 ULP_TXPKT_DEST_TP = 0, 2476 ULP_TXPKT_DEST_SGE, 2477 ULP_TXPKT_DEST_UP, 2478 ULP_TXPKT_DEST_DEVNULL, 2479 }; 2480 2481 struct ulp_txpkt { 2482 __be32 cmd_dest; 2483 __be32 len; 2484 }; 2485 2486 /* ulp_txpkt.cmd_dest fields */ 2487 #define S_ULP_TXPKT_DEST 16 2488 #define M_ULP_TXPKT_DEST 0x3 2489 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2490 2491 #define S_ULP_TXPKT_FID 4 2492 #define M_ULP_TXPKT_FID 0x7ff 2493 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2494 2495 #define S_ULP_TXPKT_RO 3 2496 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2497 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2498 2499 #endif /* T4_MSG_H */ 2500