1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_PKT_ISO = 0x1F, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_URG_PKT = 0x29, 71 CPL_TAG_WRITE_RPL = 0x2A, 72 CPL_ABORT_REQ_RSS = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_ABORT_RPL_RSS = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_RX_PHYS_ADDR = 0x30, 79 CPL_PCMD_READ_RPL = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 CPL_SET_TCB_RPL = 0x3A, 89 CPL_RX_PKT = 0x3B, 90 CPL_TAG_READ_RPL = 0x3C, 91 CPL_HIT_NOTIFY = 0x3D, 92 CPL_PKT_NOTIFY = 0x3E, 93 CPL_RX_DDP_COMPLETE = 0x3F, 94 95 CPL_ACT_ESTABLISH = 0x40, 96 CPL_PASS_ESTABLISH = 0x41, 97 CPL_RX_DATA_DDP = 0x42, 98 CPL_SMT_READ_RPL = 0x43, 99 CPL_PASS_ACCEPT_REQ = 0x44, 100 CPL_RX2TX_PKT = 0x45, 101 CPL_RX_FCOE_DDP = 0x46, 102 CPL_FCOE_HDR = 0x47, 103 CPL_T5_TRACE_PKT = 0x48, 104 CPL_RX_ISCSI_DDP = 0x49, 105 CPL_RX_FCOE_DIF = 0x4A, 106 CPL_RX_DATA_DIF = 0x4B, 107 CPL_ERR_NOTIFY = 0x4D, 108 109 CPL_RDMA_READ_REQ = 0x60, 110 CPL_RX_ISCSI_DIF = 0x60, 111 112 CPL_SET_LE_REQ = 0x80, 113 CPL_PASS_OPEN_REQ6 = 0x81, 114 CPL_ACT_OPEN_REQ6 = 0x83, 115 116 CPL_RDMA_TERMINATE = 0xA2, 117 CPL_RDMA_WRITE = 0xA4, 118 CPL_SGE_EGR_UPDATE = 0xA5, 119 CPL_SET_LE_RPL = 0xA6, 120 CPL_FW2_MSG = 0xA7, 121 CPL_FW2_PLD = 0xA8, 122 CPL_T5_RDMA_READ_REQ = 0xA9, 123 CPL_RDMA_ATOMIC_REQ = 0xAA, 124 CPL_RDMA_ATOMIC_RPL = 0xAB, 125 CPL_RDMA_IMM_DATA = 0xAC, 126 CPL_RDMA_IMM_DATA_SE = 0xAD, 127 128 CPL_TRACE_PKT = 0xB0, 129 CPL_TRACE_PKT_T5 = 0x48, 130 CPL_RX2TX_DATA = 0xB1, 131 CPL_ISCSI_DATA = 0xB2, 132 CPL_FCOE_DATA = 0xB3, 133 134 CPL_FW4_MSG = 0xC0, 135 CPL_FW4_PLD = 0xC1, 136 CPL_FW4_ACK = 0xC3, 137 138 CPL_FW6_MSG = 0xE0, 139 CPL_FW6_PLD = 0xE1, 140 CPL_TX_PKT_LSO = 0xED, 141 CPL_TX_PKT_XT = 0xEE, 142 143 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 144 }; 145 146 enum CPL_error { 147 CPL_ERR_NONE = 0, 148 CPL_ERR_TCAM_PARITY = 1, 149 CPL_ERR_TCAM_FULL = 3, 150 CPL_ERR_BAD_LENGTH = 15, 151 CPL_ERR_BAD_ROUTE = 18, 152 CPL_ERR_CONN_RESET = 20, 153 CPL_ERR_CONN_EXIST_SYNRECV = 21, 154 CPL_ERR_CONN_EXIST = 22, 155 CPL_ERR_ARP_MISS = 23, 156 CPL_ERR_BAD_SYN = 24, 157 CPL_ERR_CONN_TIMEDOUT = 30, 158 CPL_ERR_XMIT_TIMEDOUT = 31, 159 CPL_ERR_PERSIST_TIMEDOUT = 32, 160 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 161 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 162 CPL_ERR_RTX_NEG_ADVICE = 35, 163 CPL_ERR_PERSIST_NEG_ADVICE = 36, 164 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 165 CPL_ERR_WAIT_ARP_RPL = 41, 166 CPL_ERR_ABORT_FAILED = 42, 167 CPL_ERR_IWARP_FLM = 50, 168 }; 169 170 enum { 171 CPL_CONN_POLICY_AUTO = 0, 172 CPL_CONN_POLICY_ASK = 1, 173 CPL_CONN_POLICY_FILTER = 2, 174 CPL_CONN_POLICY_DENY = 3 175 }; 176 177 enum { 178 ULP_MODE_NONE = 0, 179 ULP_MODE_ISCSI = 2, 180 ULP_MODE_RDMA = 4, 181 ULP_MODE_TCPDDP = 5, 182 ULP_MODE_FCOE = 6, 183 }; 184 185 enum { 186 ULP_CRC_HEADER = 1 << 0, 187 ULP_CRC_DATA = 1 << 1 188 }; 189 190 enum { 191 CPL_PASS_OPEN_ACCEPT, 192 CPL_PASS_OPEN_REJECT, 193 CPL_PASS_OPEN_ACCEPT_TNL 194 }; 195 196 enum { 197 CPL_ABORT_SEND_RST = 0, 198 CPL_ABORT_NO_RST, 199 }; 200 201 enum { /* TX_PKT_XT checksum types */ 202 TX_CSUM_TCP = 0, 203 TX_CSUM_UDP = 1, 204 TX_CSUM_CRC16 = 4, 205 TX_CSUM_CRC32 = 5, 206 TX_CSUM_CRC32C = 6, 207 TX_CSUM_FCOE = 7, 208 TX_CSUM_TCPIP = 8, 209 TX_CSUM_UDPIP = 9, 210 TX_CSUM_TCPIP6 = 10, 211 TX_CSUM_UDPIP6 = 11, 212 TX_CSUM_IP = 12, 213 }; 214 215 enum { /* packet type in CPL_RX_PKT */ 216 PKTYPE_XACT_UCAST = 0, 217 PKTYPE_HASH_UCAST = 1, 218 PKTYPE_XACT_MCAST = 2, 219 PKTYPE_HASH_MCAST = 3, 220 PKTYPE_PROMISC = 4, 221 PKTYPE_HPROMISC = 5, 222 PKTYPE_BCAST = 6 223 }; 224 225 enum { /* DMAC type in CPL_RX_PKT */ 226 DATYPE_UCAST, 227 DATYPE_MCAST, 228 DATYPE_BCAST 229 }; 230 231 enum { /* TCP congestion control algorithms */ 232 CONG_ALG_RENO, 233 CONG_ALG_TAHOE, 234 CONG_ALG_NEWRENO, 235 CONG_ALG_HIGHSPEED 236 }; 237 238 enum { /* RSS hash type */ 239 RSS_HASH_NONE = 0, /* no hash computed */ 240 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 241 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 242 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 243 }; 244 245 enum { /* LE commands */ 246 LE_CMD_READ = 0x4, 247 LE_CMD_WRITE = 0xb 248 }; 249 250 enum { /* LE request size */ 251 LE_SZ_NONE = 0, 252 LE_SZ_33 = 1, 253 LE_SZ_66 = 2, 254 LE_SZ_132 = 3, 255 LE_SZ_264 = 4, 256 LE_SZ_528 = 5 257 }; 258 259 union opcode_tid { 260 __be32 opcode_tid; 261 __u8 opcode; 262 }; 263 264 #define S_CPL_OPCODE 24 265 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 266 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 267 #define G_TID(x) ((x) & 0xFFFFFF) 268 269 /* tid is assumed to be 24-bits */ 270 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 271 272 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 273 274 /* extract the TID from a CPL command */ 275 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 276 277 /* partitioning of TID fields that also carry a queue id */ 278 #define S_TID_TID 0 279 #define M_TID_TID 0x3fff 280 #define V_TID_TID(x) ((x) << S_TID_TID) 281 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 282 283 #define S_TID_QID 14 284 #define M_TID_QID 0x3ff 285 #define V_TID_QID(x) ((x) << S_TID_QID) 286 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 287 288 union opcode_info { 289 __be64 opcode_info; 290 __u8 opcode; 291 }; 292 293 struct tcp_options { 294 __be16 mss; 295 __u8 wsf; 296 #if defined(__LITTLE_ENDIAN_BITFIELD) 297 __u8 :4; 298 __u8 unknown:1; 299 __u8 ecn:1; 300 __u8 sack:1; 301 __u8 tstamp:1; 302 #else 303 __u8 tstamp:1; 304 __u8 sack:1; 305 __u8 ecn:1; 306 __u8 unknown:1; 307 __u8 :4; 308 #endif 309 }; 310 311 struct rss_header { 312 __u8 opcode; 313 #if defined(__LITTLE_ENDIAN_BITFIELD) 314 __u8 channel:2; 315 __u8 filter_hit:1; 316 __u8 filter_tid:1; 317 __u8 hash_type:2; 318 __u8 ipv6:1; 319 __u8 send2fw:1; 320 #else 321 __u8 send2fw:1; 322 __u8 ipv6:1; 323 __u8 hash_type:2; 324 __u8 filter_tid:1; 325 __u8 filter_hit:1; 326 __u8 channel:2; 327 #endif 328 __be16 qid; 329 __be32 hash_val; 330 }; 331 332 #define S_HASHTYPE 20 333 #define M_HASHTYPE 0x3 334 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 335 336 #define S_QNUM 0 337 #define M_QNUM 0xFFFF 338 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 339 340 #ifndef CHELSIO_FW 341 struct work_request_hdr { 342 __be32 wr_hi; 343 __be32 wr_mid; 344 __be64 wr_lo; 345 }; 346 347 /* wr_mid fields */ 348 #define S_WR_LEN16 0 349 #define M_WR_LEN16 0xFF 350 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 351 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 352 353 /* wr_hi fields */ 354 #define S_WR_OP 24 355 #define M_WR_OP 0xFF 356 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 357 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 358 359 # define WR_HDR struct work_request_hdr wr 360 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 361 # define RSS_HDR 362 #else 363 # define WR_HDR 364 # define WR_HDR_SIZE 0 365 # define RSS_HDR struct rss_header rss_hdr; 366 #endif 367 368 /* option 0 fields */ 369 #define S_ACCEPT_MODE 0 370 #define M_ACCEPT_MODE 0x3 371 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 372 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 373 374 #define S_TX_CHAN 2 375 #define M_TX_CHAN 0x3 376 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 377 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 378 379 #define S_NO_CONG 4 380 #define V_NO_CONG(x) ((x) << S_NO_CONG) 381 #define F_NO_CONG V_NO_CONG(1U) 382 383 #define S_DELACK 5 384 #define V_DELACK(x) ((x) << S_DELACK) 385 #define F_DELACK V_DELACK(1U) 386 387 #define S_INJECT_TIMER 6 388 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 389 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 390 391 #define S_NON_OFFLOAD 7 392 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 393 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 394 395 #define S_ULP_MODE 8 396 #define M_ULP_MODE 0xF 397 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 398 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 399 400 #define S_RCV_BUFSIZ 12 401 #define M_RCV_BUFSIZ 0x3FFU 402 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 403 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 404 405 #define S_DSCP 22 406 #define M_DSCP 0x3F 407 #define V_DSCP(x) ((x) << S_DSCP) 408 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 409 410 #define S_SMAC_SEL 28 411 #define M_SMAC_SEL 0xFF 412 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 413 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 414 415 #define S_L2T_IDX 36 416 #define M_L2T_IDX 0xFFF 417 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 418 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 419 420 #define S_TCAM_BYPASS 48 421 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 422 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 423 424 #define S_NAGLE 49 425 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 426 #define F_NAGLE V_NAGLE(1ULL) 427 428 #define S_WND_SCALE 50 429 #define M_WND_SCALE 0xF 430 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 431 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 432 433 #define S_KEEP_ALIVE 54 434 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 435 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 436 437 #define S_MAX_RT 55 438 #define M_MAX_RT 0xF 439 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 440 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 441 442 #define S_MAX_RT_OVERRIDE 59 443 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 444 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 445 446 #define S_MSS_IDX 60 447 #define M_MSS_IDX 0xF 448 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 449 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 450 451 /* option 1 fields */ 452 #define S_SYN_RSS_ENABLE 0 453 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 454 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 455 456 #define S_SYN_RSS_USE_HASH 1 457 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 458 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 459 460 #define S_SYN_RSS_QUEUE 2 461 #define M_SYN_RSS_QUEUE 0x3FF 462 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 463 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 464 465 #define S_LISTEN_INTF 12 466 #define M_LISTEN_INTF 0xFF 467 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 468 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 469 470 #define S_LISTEN_FILTER 20 471 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 472 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 473 474 #define S_SYN_DEFENSE 21 475 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 476 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 477 478 #define S_CONN_POLICY 22 479 #define M_CONN_POLICY 0x3 480 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 481 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 482 483 #define S_FILT_INFO 28 484 #define M_FILT_INFO 0xfffffffffULL 485 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 486 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 487 488 /* option 2 fields */ 489 #define S_RSS_QUEUE 0 490 #define M_RSS_QUEUE 0x3FF 491 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 492 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 493 494 #define S_RSS_QUEUE_VALID 10 495 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 496 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 497 498 #define S_RX_COALESCE_VALID 11 499 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 500 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 501 502 #define S_RX_COALESCE 12 503 #define M_RX_COALESCE 0x3 504 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 505 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 506 507 #define S_CONG_CNTRL 14 508 #define M_CONG_CNTRL 0x3 509 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 510 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 511 512 #define S_PACE 16 513 #define M_PACE 0x3 514 #define V_PACE(x) ((x) << S_PACE) 515 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 516 517 #define S_CONG_CNTRL_VALID 18 518 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 519 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 520 521 #define S_PACE_VALID 19 522 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 523 #define F_PACE_VALID V_PACE_VALID(1U) 524 525 #define S_RX_FC_DISABLE 20 526 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 527 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 528 529 #define S_RX_FC_DDP 21 530 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 531 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 532 533 #define S_RX_FC_VALID 22 534 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 535 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 536 537 #define S_TX_QUEUE 23 538 #define M_TX_QUEUE 0x7 539 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 540 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 541 542 #define S_RX_CHANNEL 26 543 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 544 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 545 546 #define S_CCTRL_ECN 27 547 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 548 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 549 550 #define S_WND_SCALE_EN 28 551 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 552 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 553 554 #define S_TSTAMPS_EN 29 555 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 556 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 557 558 #define S_SACK_EN 30 559 #define V_SACK_EN(x) ((x) << S_SACK_EN) 560 #define F_SACK_EN V_SACK_EN(1U) 561 562 #define S_T5_OPT_2_VALID 31 563 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 564 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 565 566 struct cpl_pass_open_req { 567 WR_HDR; 568 union opcode_tid ot; 569 __be16 local_port; 570 __be16 peer_port; 571 __be32 local_ip; 572 __be32 peer_ip; 573 __be64 opt0; 574 __be64 opt1; 575 }; 576 577 struct cpl_pass_open_req6 { 578 WR_HDR; 579 union opcode_tid ot; 580 __be16 local_port; 581 __be16 peer_port; 582 __be64 local_ip_hi; 583 __be64 local_ip_lo; 584 __be64 peer_ip_hi; 585 __be64 peer_ip_lo; 586 __be64 opt0; 587 __be64 opt1; 588 }; 589 590 struct cpl_pass_open_rpl { 591 RSS_HDR 592 union opcode_tid ot; 593 __u8 rsvd[3]; 594 __u8 status; 595 }; 596 597 struct cpl_pass_establish { 598 RSS_HDR 599 union opcode_tid ot; 600 __be32 rsvd; 601 __be32 tos_stid; 602 __be16 mac_idx; 603 __be16 tcp_opt; 604 __be32 snd_isn; 605 __be32 rcv_isn; 606 }; 607 608 /* cpl_pass_establish.tos_stid fields */ 609 #define S_PASS_OPEN_TID 0 610 #define M_PASS_OPEN_TID 0xFFFFFF 611 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 612 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 613 614 #define S_PASS_OPEN_TOS 24 615 #define M_PASS_OPEN_TOS 0xFF 616 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 617 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 618 619 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 620 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 621 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 622 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 623 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 624 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 625 626 struct cpl_pass_accept_req { 627 RSS_HDR 628 union opcode_tid ot; 629 __be16 rsvd; 630 __be16 len; 631 __be32 hdr_len; 632 __be16 vlan; 633 __be16 l2info; 634 __be32 tos_stid; 635 struct tcp_options tcpopt; 636 }; 637 638 /* cpl_pass_accept_req.hdr_len fields */ 639 #define S_SYN_RX_CHAN 0 640 #define M_SYN_RX_CHAN 0xF 641 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 642 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 643 644 #define S_TCP_HDR_LEN 10 645 #define M_TCP_HDR_LEN 0x3F 646 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 647 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 648 649 #define S_IP_HDR_LEN 16 650 #define M_IP_HDR_LEN 0x3FF 651 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 652 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 653 654 #define S_ETH_HDR_LEN 26 655 #define M_ETH_HDR_LEN 0x3F 656 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 657 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 658 659 /* cpl_pass_accept_req.l2info fields */ 660 #define S_SYN_MAC_IDX 0 661 #define M_SYN_MAC_IDX 0x1FF 662 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 663 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 664 665 #define S_SYN_XACT_MATCH 9 666 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 667 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 668 669 #define S_SYN_INTF 12 670 #define M_SYN_INTF 0xF 671 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 672 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 673 674 struct cpl_pass_accept_rpl { 675 WR_HDR; 676 union opcode_tid ot; 677 __be32 opt2; 678 __be64 opt0; 679 }; 680 681 struct cpl_act_open_req { 682 WR_HDR; 683 union opcode_tid ot; 684 __be16 local_port; 685 __be16 peer_port; 686 __be32 local_ip; 687 __be32 peer_ip; 688 __be64 opt0; 689 __be32 params; 690 __be32 opt2; 691 }; 692 693 #define S_FILTER_TUPLE 24 694 #define M_FILTER_TUPLE 0xFFFFFFFFFF 695 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 696 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 697 struct cpl_t5_act_open_req { 698 WR_HDR; 699 union opcode_tid ot; 700 __be16 local_port; 701 __be16 peer_port; 702 __be32 local_ip; 703 __be32 peer_ip; 704 __be64 opt0; 705 __be32 rsvd; 706 __be32 opt2; 707 __be64 params; 708 }; 709 710 struct cpl_act_open_req6 { 711 WR_HDR; 712 union opcode_tid ot; 713 __be16 local_port; 714 __be16 peer_port; 715 __be64 local_ip_hi; 716 __be64 local_ip_lo; 717 __be64 peer_ip_hi; 718 __be64 peer_ip_lo; 719 __be64 opt0; 720 __be32 params; 721 __be32 opt2; 722 }; 723 724 struct cpl_t5_act_open_req6 { 725 WR_HDR; 726 union opcode_tid ot; 727 __be16 local_port; 728 __be16 peer_port; 729 __be64 local_ip_hi; 730 __be64 local_ip_lo; 731 __be64 peer_ip_hi; 732 __be64 peer_ip_lo; 733 __be64 opt0; 734 __be32 rsvd; 735 __be32 opt2; 736 __be64 params; 737 }; 738 739 struct cpl_act_open_rpl { 740 RSS_HDR 741 union opcode_tid ot; 742 __be32 atid_status; 743 }; 744 745 /* cpl_act_open_rpl.atid_status fields */ 746 #define S_AOPEN_STATUS 0 747 #define M_AOPEN_STATUS 0xFF 748 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 749 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 750 751 #define S_AOPEN_ATID 8 752 #define M_AOPEN_ATID 0xFFFFFF 753 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 754 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 755 756 struct cpl_act_establish { 757 RSS_HDR 758 union opcode_tid ot; 759 __be32 rsvd; 760 __be32 tos_atid; 761 __be16 mac_idx; 762 __be16 tcp_opt; 763 __be32 snd_isn; 764 __be32 rcv_isn; 765 }; 766 767 struct cpl_get_tcb { 768 WR_HDR; 769 union opcode_tid ot; 770 __be16 reply_ctrl; 771 __be16 cookie; 772 }; 773 774 /* cpl_get_tcb.reply_ctrl fields */ 775 #define S_QUEUENO 0 776 #define M_QUEUENO 0x3FF 777 #define V_QUEUENO(x) ((x) << S_QUEUENO) 778 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 779 780 #define S_REPLY_CHAN 14 781 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 782 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 783 784 #define S_NO_REPLY 15 785 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 786 #define F_NO_REPLY V_NO_REPLY(1U) 787 788 struct cpl_get_tcb_rpl { 789 RSS_HDR 790 union opcode_tid ot; 791 __u8 cookie; 792 __u8 status; 793 __be16 len; 794 }; 795 796 struct cpl_set_tcb { 797 WR_HDR; 798 union opcode_tid ot; 799 __be16 reply_ctrl; 800 __be16 cookie; 801 }; 802 803 struct cpl_set_tcb_field { 804 WR_HDR; 805 union opcode_tid ot; 806 __be16 reply_ctrl; 807 __be16 word_cookie; 808 __be64 mask; 809 __be64 val; 810 }; 811 812 struct cpl_set_tcb_field_core { 813 union opcode_tid ot; 814 __be16 reply_ctrl; 815 __be16 word_cookie; 816 __be64 mask; 817 __be64 val; 818 }; 819 820 /* cpl_set_tcb_field.word_cookie fields */ 821 #define S_WORD 0 822 #define M_WORD 0x1F 823 #define V_WORD(x) ((x) << S_WORD) 824 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 825 826 #define S_COOKIE 5 827 #define M_COOKIE 0x7 828 #define V_COOKIE(x) ((x) << S_COOKIE) 829 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 830 831 struct cpl_set_tcb_rpl { 832 RSS_HDR 833 union opcode_tid ot; 834 __be16 rsvd; 835 __u8 cookie; 836 __u8 status; 837 __be64 oldval; 838 }; 839 840 struct cpl_close_con_req { 841 WR_HDR; 842 union opcode_tid ot; 843 __be32 rsvd; 844 }; 845 846 struct cpl_close_con_rpl { 847 RSS_HDR 848 union opcode_tid ot; 849 __u8 rsvd[3]; 850 __u8 status; 851 __be32 snd_nxt; 852 __be32 rcv_nxt; 853 }; 854 855 struct cpl_close_listsvr_req { 856 WR_HDR; 857 union opcode_tid ot; 858 __be16 reply_ctrl; 859 __be16 rsvd; 860 }; 861 862 /* additional cpl_close_listsvr_req.reply_ctrl field */ 863 #define S_LISTSVR_IPV6 14 864 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 865 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 866 867 struct cpl_close_listsvr_rpl { 868 RSS_HDR 869 union opcode_tid ot; 870 __u8 rsvd[3]; 871 __u8 status; 872 }; 873 874 struct cpl_abort_req_rss { 875 RSS_HDR 876 union opcode_tid ot; 877 __u8 rsvd[3]; 878 __u8 status; 879 }; 880 881 struct cpl_abort_req { 882 WR_HDR; 883 union opcode_tid ot; 884 __be32 rsvd0; 885 __u8 rsvd1; 886 __u8 cmd; 887 __u8 rsvd2[6]; 888 }; 889 890 struct cpl_abort_rpl_rss { 891 RSS_HDR 892 union opcode_tid ot; 893 __u8 rsvd[3]; 894 __u8 status; 895 }; 896 897 struct cpl_abort_rpl { 898 WR_HDR; 899 union opcode_tid ot; 900 __be32 rsvd0; 901 __u8 rsvd1; 902 __u8 cmd; 903 __u8 rsvd2[6]; 904 }; 905 906 struct cpl_peer_close { 907 RSS_HDR 908 union opcode_tid ot; 909 __be32 rcv_nxt; 910 }; 911 912 struct cpl_tid_release { 913 WR_HDR; 914 union opcode_tid ot; 915 __be32 rsvd; 916 }; 917 918 struct tx_data_wr { 919 __be32 wr_hi; 920 __be32 wr_lo; 921 __be32 len; 922 __be32 flags; 923 __be32 sndseq; 924 __be32 param; 925 }; 926 927 /* tx_data_wr.flags fields */ 928 #define S_TX_ACK_PAGES 21 929 #define M_TX_ACK_PAGES 0x7 930 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 931 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 932 933 /* tx_data_wr.param fields */ 934 #define S_TX_PORT 0 935 #define M_TX_PORT 0x7 936 #define V_TX_PORT(x) ((x) << S_TX_PORT) 937 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 938 939 #define S_TX_MSS 4 940 #define M_TX_MSS 0xF 941 #define V_TX_MSS(x) ((x) << S_TX_MSS) 942 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 943 944 #define S_TX_QOS 8 945 #define M_TX_QOS 0xFF 946 #define V_TX_QOS(x) ((x) << S_TX_QOS) 947 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 948 949 #define S_TX_SNDBUF 16 950 #define M_TX_SNDBUF 0xFFFF 951 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 952 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 953 954 struct cpl_tx_data { 955 union opcode_tid ot; 956 __be32 len; 957 __be32 rsvd; 958 __be32 flags; 959 }; 960 961 /* cpl_tx_data.flags fields */ 962 #define S_TX_PROXY 5 963 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 964 #define F_TX_PROXY V_TX_PROXY(1U) 965 966 #define S_TX_ULP_SUBMODE 6 967 #define M_TX_ULP_SUBMODE 0xF 968 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 969 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 970 971 #define S_TX_ULP_MODE 10 972 #define M_TX_ULP_MODE 0xF 973 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 974 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 975 976 #define S_TX_SHOVE 14 977 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 978 #define F_TX_SHOVE V_TX_SHOVE(1U) 979 980 #define S_TX_MORE 15 981 #define V_TX_MORE(x) ((x) << S_TX_MORE) 982 #define F_TX_MORE V_TX_MORE(1U) 983 984 #define S_TX_URG 16 985 #define V_TX_URG(x) ((x) << S_TX_URG) 986 #define F_TX_URG V_TX_URG(1U) 987 988 #define S_TX_FLUSH 17 989 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 990 #define F_TX_FLUSH V_TX_FLUSH(1U) 991 992 #define S_TX_SAVE 18 993 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 994 #define F_TX_SAVE V_TX_SAVE(1U) 995 996 #define S_TX_TNL 19 997 #define V_TX_TNL(x) ((x) << S_TX_TNL) 998 #define F_TX_TNL V_TX_TNL(1U) 999 1000 /* additional tx_data_wr.flags fields */ 1001 #define S_TX_CPU_IDX 0 1002 #define M_TX_CPU_IDX 0x3F 1003 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1004 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1005 1006 #define S_TX_CLOSE 17 1007 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1008 #define F_TX_CLOSE V_TX_CLOSE(1U) 1009 1010 #define S_TX_INIT 18 1011 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1012 #define F_TX_INIT V_TX_INIT(1U) 1013 1014 #define S_TX_IMM_ACK 19 1015 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1016 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1017 1018 #define S_TX_IMM_DMA 20 1019 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1020 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1021 1022 struct cpl_tx_data_ack { 1023 RSS_HDR 1024 union opcode_tid ot; 1025 __be32 snd_una; 1026 }; 1027 1028 struct cpl_wr_ack { /* XXX */ 1029 RSS_HDR 1030 union opcode_tid ot; 1031 __be16 credits; 1032 __be16 rsvd; 1033 __be32 snd_nxt; 1034 __be32 snd_una; 1035 }; 1036 1037 struct cpl_tx_pkt_core { 1038 __be32 ctrl0; 1039 __be16 pack; 1040 __be16 len; 1041 __be64 ctrl1; 1042 }; 1043 1044 struct cpl_tx_pkt { 1045 WR_HDR; 1046 struct cpl_tx_pkt_core c; 1047 }; 1048 1049 #define cpl_tx_pkt_xt cpl_tx_pkt 1050 1051 /* cpl_tx_pkt_core.ctrl0 fields */ 1052 #define S_TXPKT_VF 0 1053 #define M_TXPKT_VF 0xFF 1054 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1055 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1056 1057 #define S_TXPKT_PF 8 1058 #define M_TXPKT_PF 0x7 1059 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1060 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1061 1062 #define S_TXPKT_VF_VLD 11 1063 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1064 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1065 1066 #define S_TXPKT_OVLAN_IDX 12 1067 #define M_TXPKT_OVLAN_IDX 0xF 1068 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1069 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1070 1071 #define S_TXPKT_T5_OVLAN_IDX 12 1072 #define M_TXPKT_T5_OVLAN_IDX 0x7 1073 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1074 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1075 M_TXPKT_T5_OVLAN_IDX) 1076 1077 #define S_TXPKT_INTF 16 1078 #define M_TXPKT_INTF 0xF 1079 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1080 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1081 1082 #define S_TXPKT_SPECIAL_STAT 20 1083 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1084 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1085 1086 #define S_TXPKT_T5_FCS_DIS 21 1087 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1088 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1089 1090 #define S_TXPKT_INS_OVLAN 21 1091 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1092 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1093 1094 #define S_TXPKT_T5_INS_OVLAN 15 1095 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1096 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1097 1098 #define S_TXPKT_STAT_DIS 22 1099 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1100 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1101 1102 #define S_TXPKT_LOOPBACK 23 1103 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1104 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1105 1106 #define S_TXPKT_TSTAMP 23 1107 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1108 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1109 1110 #define S_TXPKT_OPCODE 24 1111 #define M_TXPKT_OPCODE 0xFF 1112 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1113 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1114 1115 /* cpl_tx_pkt_core.ctrl1 fields */ 1116 #define S_TXPKT_SA_IDX 0 1117 #define M_TXPKT_SA_IDX 0xFFF 1118 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1119 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1120 1121 #define S_TXPKT_CSUM_END 12 1122 #define M_TXPKT_CSUM_END 0xFF 1123 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1124 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1125 1126 #define S_TXPKT_CSUM_START 20 1127 #define M_TXPKT_CSUM_START 0x3FF 1128 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1129 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1130 1131 #define S_TXPKT_IPHDR_LEN 20 1132 #define M_TXPKT_IPHDR_LEN 0x3FFF 1133 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1134 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1135 1136 #define S_TXPKT_CSUM_LOC 30 1137 #define M_TXPKT_CSUM_LOC 0x3FF 1138 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1139 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1140 1141 #define S_TXPKT_ETHHDR_LEN 34 1142 #define M_TXPKT_ETHHDR_LEN 0x3F 1143 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1144 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1145 1146 #define S_TXPKT_CSUM_TYPE 40 1147 #define M_TXPKT_CSUM_TYPE 0xF 1148 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1149 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1150 1151 #define S_TXPKT_VLAN 44 1152 #define M_TXPKT_VLAN 0xFFFF 1153 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1154 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1155 1156 #define S_TXPKT_VLAN_VLD 60 1157 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1158 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1159 1160 #define S_TXPKT_IPSEC 61 1161 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1162 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1163 1164 #define S_TXPKT_IPCSUM_DIS 62 1165 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1166 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1167 1168 #define S_TXPKT_L4CSUM_DIS 63 1169 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1170 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1171 1172 struct cpl_tx_pkt_lso_core { 1173 __be32 lso_ctrl; 1174 __be16 ipid_ofst; 1175 __be16 mss; 1176 __be32 seqno_offset; 1177 __be32 len; 1178 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1179 }; 1180 1181 struct cpl_tx_pkt_lso { 1182 WR_HDR; 1183 struct cpl_tx_pkt_lso_core c; 1184 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1185 }; 1186 1187 struct cpl_tx_pkt_ufo_core { 1188 __be16 ethlen; 1189 __be16 iplen; 1190 __be16 udplen; 1191 __be16 mss; 1192 __be32 len; 1193 __be32 r1; 1194 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1195 }; 1196 1197 struct cpl_tx_pkt_ufo { 1198 WR_HDR; 1199 struct cpl_tx_pkt_ufo_core c; 1200 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1201 }; 1202 1203 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1204 #define S_LSO_TCPHDR_LEN 0 1205 #define M_LSO_TCPHDR_LEN 0xF 1206 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1207 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1208 1209 #define S_LSO_IPHDR_LEN 4 1210 #define M_LSO_IPHDR_LEN 0xFFF 1211 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1212 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1213 1214 #define S_LSO_ETHHDR_LEN 16 1215 #define M_LSO_ETHHDR_LEN 0xF 1216 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1217 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1218 1219 #define S_LSO_IPV6 20 1220 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1221 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1222 1223 #define S_LSO_OFLD_ENCAP 21 1224 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1225 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1226 1227 #define S_LSO_LAST_SLICE 22 1228 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1229 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1230 1231 #define S_LSO_FIRST_SLICE 23 1232 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1233 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1234 1235 #define S_LSO_OPCODE 24 1236 #define M_LSO_OPCODE 0xFF 1237 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1238 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1239 1240 #define S_LSO_T5_XFER_SIZE 0 1241 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1242 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1243 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1244 1245 /* cpl_tx_pkt_lso_core.mss fields */ 1246 #define S_LSO_MSS 0 1247 #define M_LSO_MSS 0x3FFF 1248 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1249 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1250 1251 #define S_LSO_IPID_SPLIT 15 1252 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1253 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1254 1255 struct cpl_tx_pkt_fso { 1256 WR_HDR; 1257 __be32 fso_ctrl; 1258 __be16 seqcnt_ofst; 1259 __be16 mtu; 1260 __be32 param_offset; 1261 __be32 len; 1262 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1263 }; 1264 1265 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1266 #define S_FSO_XCHG_CLASS 21 1267 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1268 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1269 1270 #define S_FSO_INITIATOR 20 1271 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1272 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1273 1274 #define S_FSO_FCHDR_LEN 12 1275 #define M_FSO_FCHDR_LEN 0xF 1276 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1277 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1278 1279 struct cpl_iscsi_hdr_no_rss { 1280 union opcode_tid ot; 1281 __be16 pdu_len_ddp; 1282 __be16 len; 1283 __be32 seq; 1284 __be16 urg; 1285 __u8 rsvd; 1286 __u8 status; 1287 }; 1288 1289 struct cpl_tx_data_iso { 1290 WR_HDR; 1291 __be32 iso_ctrl; 1292 __u8 rsvd; 1293 __u8 ahs_len; 1294 __be16 mss; 1295 __be32 burst_size; 1296 __be32 len; 1297 /* encapsulated CPL_TX_DATA follows here */ 1298 }; 1299 1300 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1301 #define S_ISO_CPLHDR_LEN 18 1302 #define M_ISO_CPLHDR_LEN 0xF 1303 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1304 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1305 1306 #define S_ISO_HDR_CRC 17 1307 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1308 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1309 1310 #define S_ISO_DATA_CRC 16 1311 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1312 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1313 1314 #define S_ISO_IMD_DATA_EN 15 1315 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1316 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1317 1318 #define S_ISO_PDU_TYPE 13 1319 #define M_ISO_PDU_TYPE 0x3 1320 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1321 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1322 1323 struct cpl_iscsi_hdr { 1324 RSS_HDR 1325 union opcode_tid ot; 1326 __be16 pdu_len_ddp; 1327 __be16 len; 1328 __be32 seq; 1329 __be16 urg; 1330 __u8 rsvd; 1331 __u8 status; 1332 }; 1333 1334 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1335 #define S_ISCSI_PDU_LEN 0 1336 #define M_ISCSI_PDU_LEN 0x7FFF 1337 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1338 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1339 1340 #define S_ISCSI_DDP 15 1341 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1342 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1343 1344 struct cpl_iscsi_data { 1345 RSS_HDR 1346 union opcode_tid ot; 1347 __u8 rsvd0[2]; 1348 __be16 len; 1349 __be32 seq; 1350 __be16 urg; 1351 __u8 rsvd1; 1352 __u8 status; 1353 }; 1354 1355 struct cpl_rx_data { 1356 RSS_HDR 1357 union opcode_tid ot; 1358 __be16 rsvd; 1359 __be16 len; 1360 __be32 seq; 1361 __be16 urg; 1362 #if defined(__LITTLE_ENDIAN_BITFIELD) 1363 __u8 dack_mode:2; 1364 __u8 psh:1; 1365 __u8 heartbeat:1; 1366 __u8 ddp_off:1; 1367 __u8 :3; 1368 #else 1369 __u8 :3; 1370 __u8 ddp_off:1; 1371 __u8 heartbeat:1; 1372 __u8 psh:1; 1373 __u8 dack_mode:2; 1374 #endif 1375 __u8 status; 1376 }; 1377 1378 struct cpl_fcoe_hdr { 1379 RSS_HDR 1380 union opcode_tid ot; 1381 __be16 oxid; 1382 __be16 len; 1383 __be32 rctl_fctl; 1384 __u8 cs_ctl; 1385 __u8 df_ctl; 1386 __u8 sof; 1387 __u8 eof; 1388 __be16 seq_cnt; 1389 __u8 seq_id; 1390 __u8 type; 1391 __be32 param; 1392 }; 1393 1394 struct cpl_fcoe_data { 1395 RSS_HDR 1396 union opcode_tid ot; 1397 __u8 rsvd0[2]; 1398 __be16 len; 1399 __be32 seq; 1400 __u8 rsvd1[3]; 1401 __u8 status; 1402 }; 1403 1404 struct cpl_rx_urg_notify { 1405 RSS_HDR 1406 union opcode_tid ot; 1407 __be32 seq; 1408 }; 1409 1410 struct cpl_rx_urg_pkt { 1411 RSS_HDR 1412 union opcode_tid ot; 1413 __be16 rsvd; 1414 __be16 len; 1415 }; 1416 1417 struct cpl_rx_data_ack { 1418 WR_HDR; 1419 union opcode_tid ot; 1420 __be32 credit_dack; 1421 }; 1422 1423 struct cpl_rx_data_ack_core { 1424 union opcode_tid ot; 1425 __be32 credit_dack; 1426 }; 1427 1428 /* cpl_rx_data_ack.ack_seq fields */ 1429 #define S_RX_CREDITS 0 1430 #define M_RX_CREDITS 0x3FFFFFF 1431 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1432 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1433 1434 #define S_RX_MODULATE_TX 26 1435 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1436 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1437 1438 #define S_RX_MODULATE_RX 27 1439 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1440 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1441 1442 #define S_RX_FORCE_ACK 28 1443 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1444 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1445 1446 #define S_RX_DACK_MODE 29 1447 #define M_RX_DACK_MODE 0x3 1448 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1449 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1450 1451 #define S_RX_DACK_CHANGE 31 1452 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1453 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1454 1455 struct cpl_rx_ddp_complete { 1456 RSS_HDR 1457 union opcode_tid ot; 1458 __be32 ddp_report; 1459 __be32 rcv_nxt; 1460 __be32 rsvd; 1461 }; 1462 1463 struct cpl_rx_data_ddp { 1464 RSS_HDR 1465 union opcode_tid ot; 1466 __be16 urg; 1467 __be16 len; 1468 __be32 seq; 1469 union { 1470 __be32 nxt_seq; 1471 __be32 ddp_report; 1472 } u; 1473 __be32 ulp_crc; 1474 __be32 ddpvld; 1475 }; 1476 1477 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1478 1479 struct cpl_rx_fcoe_ddp { 1480 RSS_HDR 1481 union opcode_tid ot; 1482 __be16 rsvd; 1483 __be16 len; 1484 __be32 seq; 1485 __be32 ddp_report; 1486 __be32 ulp_crc; 1487 __be32 ddpvld; 1488 }; 1489 1490 struct cpl_rx_data_dif { 1491 RSS_HDR 1492 union opcode_tid ot; 1493 __be16 ddp_len; 1494 __be16 msg_len; 1495 __be32 seq; 1496 union { 1497 __be32 nxt_seq; 1498 __be32 ddp_report; 1499 } u; 1500 __be32 err_vec; 1501 __be32 ddpvld; 1502 }; 1503 1504 struct cpl_rx_iscsi_dif { 1505 RSS_HDR 1506 union opcode_tid ot; 1507 __be16 ddp_len; 1508 __be16 msg_len; 1509 __be32 seq; 1510 union { 1511 __be32 nxt_seq; 1512 __be32 ddp_report; 1513 } u; 1514 __be32 ulp_crc; 1515 __be32 ddpvld; 1516 __u8 rsvd0[8]; 1517 __be32 err_vec; 1518 __u8 rsvd1[4]; 1519 }; 1520 1521 struct cpl_rx_fcoe_dif { 1522 RSS_HDR 1523 union opcode_tid ot; 1524 __be16 ddp_len; 1525 __be16 msg_len; 1526 __be32 seq; 1527 __be32 ddp_report; 1528 __be32 err_vec; 1529 __be32 ddpvld; 1530 }; 1531 1532 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1533 #define S_DDP_VALID 15 1534 #define M_DDP_VALID 0x1FFFF 1535 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1536 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1537 1538 #define S_DDP_PPOD_MISMATCH 15 1539 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1540 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1541 1542 #define S_DDP_PDU 16 1543 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1544 #define F_DDP_PDU V_DDP_PDU(1U) 1545 1546 #define S_DDP_LLIMIT_ERR 17 1547 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1548 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1549 1550 #define S_DDP_PPOD_PARITY_ERR 18 1551 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1552 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1553 1554 #define S_DDP_PADDING_ERR 19 1555 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1556 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1557 1558 #define S_DDP_HDRCRC_ERR 20 1559 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1560 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1561 1562 #define S_DDP_DATACRC_ERR 21 1563 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1564 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1565 1566 #define S_DDP_INVALID_TAG 22 1567 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1568 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1569 1570 #define S_DDP_ULIMIT_ERR 23 1571 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1572 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1573 1574 #define S_DDP_OFFSET_ERR 24 1575 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1576 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1577 1578 #define S_DDP_COLOR_ERR 25 1579 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1580 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1581 1582 #define S_DDP_TID_MISMATCH 26 1583 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1584 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1585 1586 #define S_DDP_INVALID_PPOD 27 1587 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1588 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1589 1590 #define S_DDP_ULP_MODE 28 1591 #define M_DDP_ULP_MODE 0xF 1592 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1593 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1594 1595 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1596 #define S_DDP_OFFSET 0 1597 #define M_DDP_OFFSET 0xFFFFFF 1598 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1599 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1600 1601 #define S_DDP_DACK_MODE 24 1602 #define M_DDP_DACK_MODE 0x3 1603 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1604 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1605 1606 #define S_DDP_BUF_IDX 26 1607 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1608 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1609 1610 #define S_DDP_URG 27 1611 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1612 #define F_DDP_URG V_DDP_URG(1U) 1613 1614 #define S_DDP_PSH 28 1615 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1616 #define F_DDP_PSH V_DDP_PSH(1U) 1617 1618 #define S_DDP_BUF_COMPLETE 29 1619 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1620 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1621 1622 #define S_DDP_BUF_TIMED_OUT 30 1623 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1624 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1625 1626 #define S_DDP_INV 31 1627 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1628 #define F_DDP_INV V_DDP_INV(1U) 1629 1630 struct cpl_rx_pkt { 1631 RSS_HDR 1632 __u8 opcode; 1633 #if defined(__LITTLE_ENDIAN_BITFIELD) 1634 __u8 iff:4; 1635 __u8 csum_calc:1; 1636 __u8 ipmi_pkt:1; 1637 __u8 vlan_ex:1; 1638 __u8 ip_frag:1; 1639 #else 1640 __u8 ip_frag:1; 1641 __u8 vlan_ex:1; 1642 __u8 ipmi_pkt:1; 1643 __u8 csum_calc:1; 1644 __u8 iff:4; 1645 #endif 1646 __be16 csum; 1647 __be16 vlan; 1648 __be16 len; 1649 __be32 l2info; 1650 __be16 hdr_len; 1651 __be16 err_vec; 1652 }; 1653 1654 /* rx_pkt.l2info fields */ 1655 #define S_RX_ETHHDR_LEN 0 1656 #define M_RX_ETHHDR_LEN 0x1F 1657 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1658 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1659 1660 #define S_RX_T5_ETHHDR_LEN 0 1661 #define M_RX_T5_ETHHDR_LEN 0x3F 1662 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1663 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1664 1665 #define S_RX_PKTYPE 5 1666 #define M_RX_PKTYPE 0x7 1667 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1668 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1669 1670 #define S_RX_T5_DATYPE 6 1671 #define M_RX_T5_DATYPE 0x3 1672 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1673 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1674 1675 #define S_RX_MACIDX 8 1676 #define M_RX_MACIDX 0x1FF 1677 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1678 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1679 1680 #define S_RX_T5_PKTYPE 17 1681 #define M_RX_T5_PKTYPE 0x7 1682 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1683 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1684 1685 #define S_RX_DATYPE 18 1686 #define M_RX_DATYPE 0x3 1687 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1688 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1689 1690 #define S_RXF_PSH 20 1691 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1692 #define F_RXF_PSH V_RXF_PSH(1U) 1693 1694 #define S_RXF_SYN 21 1695 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1696 #define F_RXF_SYN V_RXF_SYN(1U) 1697 1698 #define S_RXF_UDP 22 1699 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1700 #define F_RXF_UDP V_RXF_UDP(1U) 1701 1702 #define S_RXF_TCP 23 1703 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1704 #define F_RXF_TCP V_RXF_TCP(1U) 1705 1706 #define S_RXF_IP 24 1707 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1708 #define F_RXF_IP V_RXF_IP(1U) 1709 1710 #define S_RXF_IP6 25 1711 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1712 #define F_RXF_IP6 V_RXF_IP6(1U) 1713 1714 #define S_RXF_SYN_COOKIE 26 1715 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1716 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1717 1718 #define S_RXF_FCOE 26 1719 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1720 #define F_RXF_FCOE V_RXF_FCOE(1U) 1721 1722 #define S_RXF_LRO 27 1723 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1724 #define F_RXF_LRO V_RXF_LRO(1U) 1725 1726 #define S_RX_CHAN 28 1727 #define M_RX_CHAN 0xF 1728 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1729 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1730 1731 /* rx_pkt.hdr_len fields */ 1732 #define S_RX_TCPHDR_LEN 0 1733 #define M_RX_TCPHDR_LEN 0x3F 1734 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1735 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1736 1737 #define S_RX_IPHDR_LEN 6 1738 #define M_RX_IPHDR_LEN 0x3FF 1739 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1740 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1741 1742 /* rx_pkt.err_vec fields */ 1743 #define S_RXERR_OR 0 1744 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1745 #define F_RXERR_OR V_RXERR_OR(1U) 1746 1747 #define S_RXERR_MAC 1 1748 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1749 #define F_RXERR_MAC V_RXERR_MAC(1U) 1750 1751 #define S_RXERR_IPVERS 2 1752 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1753 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1754 1755 #define S_RXERR_FRAG 3 1756 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1757 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1758 1759 #define S_RXERR_ATTACK 4 1760 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1761 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1762 1763 #define S_RXERR_ETHHDR_LEN 5 1764 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1765 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1766 1767 #define S_RXERR_IPHDR_LEN 6 1768 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1769 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1770 1771 #define S_RXERR_TCPHDR_LEN 7 1772 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1773 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1774 1775 #define S_RXERR_PKT_LEN 8 1776 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1777 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1778 1779 #define S_RXERR_TCP_OPT 9 1780 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1781 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1782 1783 #define S_RXERR_IPCSUM 12 1784 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1785 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1786 1787 #define S_RXERR_CSUM 13 1788 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1789 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1790 1791 #define S_RXERR_PING 14 1792 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1793 #define F_RXERR_PING V_RXERR_PING(1U) 1794 1795 struct cpl_trace_pkt { 1796 RSS_HDR 1797 __u8 opcode; 1798 __u8 intf; 1799 #if defined(__LITTLE_ENDIAN_BITFIELD) 1800 __u8 runt:4; 1801 __u8 filter_hit:4; 1802 __u8 :6; 1803 __u8 err:1; 1804 __u8 trunc:1; 1805 #else 1806 __u8 filter_hit:4; 1807 __u8 runt:4; 1808 __u8 trunc:1; 1809 __u8 err:1; 1810 __u8 :6; 1811 #endif 1812 __be16 rsvd; 1813 __be16 len; 1814 __be64 tstamp; 1815 }; 1816 1817 struct cpl_t5_trace_pkt { 1818 RSS_HDR 1819 __u8 opcode; 1820 __u8 intf; 1821 #if defined(__LITTLE_ENDIAN_BITFIELD) 1822 __u8 runt:4; 1823 __u8 filter_hit:4; 1824 __u8 :6; 1825 __u8 err:1; 1826 __u8 trunc:1; 1827 #else 1828 __u8 filter_hit:4; 1829 __u8 runt:4; 1830 __u8 trunc:1; 1831 __u8 err:1; 1832 __u8 :6; 1833 #endif 1834 __be16 rsvd; 1835 __be16 len; 1836 __be64 tstamp; 1837 __be64 rsvd1; 1838 }; 1839 1840 struct cpl_rte_delete_req { 1841 WR_HDR; 1842 union opcode_tid ot; 1843 __be32 params; 1844 }; 1845 1846 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1847 #define S_RTE_REQ_LUT_IX 8 1848 #define M_RTE_REQ_LUT_IX 0x7FF 1849 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1850 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1851 1852 #define S_RTE_REQ_LUT_BASE 19 1853 #define M_RTE_REQ_LUT_BASE 0x7FF 1854 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1855 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1856 1857 #define S_RTE_READ_REQ_SELECT 31 1858 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1859 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1860 1861 struct cpl_rte_delete_rpl { 1862 RSS_HDR 1863 union opcode_tid ot; 1864 __u8 status; 1865 __u8 rsvd[3]; 1866 }; 1867 1868 struct cpl_rte_write_req { 1869 WR_HDR; 1870 union opcode_tid ot; 1871 __u32 write_sel; 1872 __be32 lut_params; 1873 __be32 l2t_idx; 1874 __be32 netmask; 1875 __be32 faddr; 1876 }; 1877 1878 /* cpl_rte_write_req.write_sel fields */ 1879 #define S_RTE_WR_L2TIDX 31 1880 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1881 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1882 1883 #define S_RTE_WR_FADDR 30 1884 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1885 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1886 1887 /* cpl_rte_write_req.lut_params fields */ 1888 #define S_RTE_WR_LUT_IX 10 1889 #define M_RTE_WR_LUT_IX 0x7FF 1890 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1891 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1892 1893 #define S_RTE_WR_LUT_BASE 21 1894 #define M_RTE_WR_LUT_BASE 0x7FF 1895 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1896 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1897 1898 struct cpl_rte_write_rpl { 1899 RSS_HDR 1900 union opcode_tid ot; 1901 __u8 status; 1902 __u8 rsvd[3]; 1903 }; 1904 1905 struct cpl_rte_read_req { 1906 WR_HDR; 1907 union opcode_tid ot; 1908 __be32 params; 1909 }; 1910 1911 struct cpl_rte_read_rpl { 1912 RSS_HDR 1913 union opcode_tid ot; 1914 __u8 status; 1915 __u8 rsvd; 1916 __be16 l2t_idx; 1917 #if defined(__LITTLE_ENDIAN_BITFIELD) 1918 __u32 :30; 1919 __u32 select:1; 1920 #else 1921 __u32 select:1; 1922 __u32 :30; 1923 #endif 1924 __be32 addr; 1925 }; 1926 1927 struct cpl_l2t_write_req { 1928 WR_HDR; 1929 union opcode_tid ot; 1930 __be16 params; 1931 __be16 l2t_idx; 1932 __be16 vlan; 1933 __u8 dst_mac[6]; 1934 }; 1935 1936 /* cpl_l2t_write_req.params fields */ 1937 #define S_L2T_W_INFO 2 1938 #define M_L2T_W_INFO 0x3F 1939 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1940 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1941 1942 #define S_L2T_W_PORT 8 1943 #define M_L2T_W_PORT 0x3 1944 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1945 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1946 1947 #define S_L2T_W_LPBK 10 1948 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 1949 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 1950 1951 #define S_L2T_W_ARPMISS 11 1952 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 1953 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 1954 1955 #define S_L2T_W_NOREPLY 15 1956 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1957 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1958 1959 #define CPL_L2T_VLAN_NONE 0xfff 1960 1961 struct cpl_l2t_write_rpl { 1962 RSS_HDR 1963 union opcode_tid ot; 1964 __u8 status; 1965 __u8 rsvd[3]; 1966 }; 1967 1968 struct cpl_l2t_read_req { 1969 WR_HDR; 1970 union opcode_tid ot; 1971 __be32 l2t_idx; 1972 }; 1973 1974 struct cpl_l2t_read_rpl { 1975 RSS_HDR 1976 union opcode_tid ot; 1977 __u8 status; 1978 #if defined(__LITTLE_ENDIAN_BITFIELD) 1979 __u8 :4; 1980 __u8 iff:4; 1981 #else 1982 __u8 iff:4; 1983 __u8 :4; 1984 #endif 1985 __be16 vlan; 1986 __be16 info; 1987 __u8 dst_mac[6]; 1988 }; 1989 1990 struct cpl_smt_write_req { 1991 WR_HDR; 1992 union opcode_tid ot; 1993 __be32 params; 1994 __be16 pfvf1; 1995 __u8 src_mac1[6]; 1996 __be16 pfvf0; 1997 __u8 src_mac0[6]; 1998 }; 1999 2000 struct cpl_smt_write_rpl { 2001 RSS_HDR 2002 union opcode_tid ot; 2003 __u8 status; 2004 __u8 rsvd[3]; 2005 }; 2006 2007 struct cpl_smt_read_req { 2008 WR_HDR; 2009 union opcode_tid ot; 2010 __be32 params; 2011 }; 2012 2013 struct cpl_smt_read_rpl { 2014 RSS_HDR 2015 union opcode_tid ot; 2016 __u8 status; 2017 __u8 ovlan_idx; 2018 __be16 rsvd; 2019 __be16 pfvf1; 2020 __u8 src_mac1[6]; 2021 __be16 pfvf0; 2022 __u8 src_mac0[6]; 2023 }; 2024 2025 /* cpl_smt_{read,write}_req.params fields */ 2026 #define S_SMTW_OVLAN_IDX 16 2027 #define M_SMTW_OVLAN_IDX 0xF 2028 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2029 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2030 2031 #define S_SMTW_IDX 20 2032 #define M_SMTW_IDX 0x7F 2033 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2034 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2035 2036 #define S_SMTW_NORPL 31 2037 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2038 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2039 2040 /* cpl_smt_{read,write}_req.pfvf? fields */ 2041 #define S_SMTW_VF 0 2042 #define M_SMTW_VF 0xFF 2043 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2044 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2045 2046 #define S_SMTW_PF 8 2047 #define M_SMTW_PF 0x7 2048 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2049 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2050 2051 #define S_SMTW_VF_VLD 11 2052 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2053 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2054 2055 struct cpl_tag_write_req { 2056 WR_HDR; 2057 union opcode_tid ot; 2058 __be32 params; 2059 __be64 tag_val; 2060 }; 2061 2062 struct cpl_tag_write_rpl { 2063 RSS_HDR 2064 union opcode_tid ot; 2065 __u8 status; 2066 __u8 rsvd[2]; 2067 __u8 idx; 2068 }; 2069 2070 struct cpl_tag_read_req { 2071 WR_HDR; 2072 union opcode_tid ot; 2073 __be32 params; 2074 }; 2075 2076 struct cpl_tag_read_rpl { 2077 RSS_HDR 2078 union opcode_tid ot; 2079 __u8 status; 2080 #if defined(__LITTLE_ENDIAN_BITFIELD) 2081 __u8 :4; 2082 __u8 tag_len:1; 2083 __u8 :2; 2084 __u8 ins_enable:1; 2085 #else 2086 __u8 ins_enable:1; 2087 __u8 :2; 2088 __u8 tag_len:1; 2089 __u8 :4; 2090 #endif 2091 __u8 rsvd; 2092 __u8 tag_idx; 2093 __be64 tag_val; 2094 }; 2095 2096 /* cpl_tag{read,write}_req.params fields */ 2097 #define S_TAGW_IDX 0 2098 #define M_TAGW_IDX 0x7F 2099 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2100 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2101 2102 #define S_TAGW_LEN 20 2103 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2104 #define F_TAGW_LEN V_TAGW_LEN(1U) 2105 2106 #define S_TAGW_INS_ENABLE 23 2107 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2108 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2109 2110 #define S_TAGW_NORPL 31 2111 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2112 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2113 2114 struct cpl_barrier { 2115 WR_HDR; 2116 __u8 opcode; 2117 __u8 chan_map; 2118 __be16 rsvd0; 2119 __be32 rsvd1; 2120 }; 2121 2122 /* cpl_barrier.chan_map fields */ 2123 #define S_CHAN_MAP 4 2124 #define M_CHAN_MAP 0xF 2125 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2126 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2127 2128 struct cpl_error { 2129 RSS_HDR 2130 union opcode_tid ot; 2131 __be32 error; 2132 }; 2133 2134 struct cpl_hit_notify { 2135 RSS_HDR 2136 union opcode_tid ot; 2137 __be32 rsvd; 2138 __be32 info; 2139 __be32 reason; 2140 }; 2141 2142 struct cpl_pkt_notify { 2143 RSS_HDR 2144 union opcode_tid ot; 2145 __be16 rsvd; 2146 __be16 len; 2147 __be32 info; 2148 __be32 reason; 2149 }; 2150 2151 /* cpl_{hit,pkt}_notify.info fields */ 2152 #define S_NTFY_MAC_IDX 0 2153 #define M_NTFY_MAC_IDX 0x1FF 2154 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2155 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2156 2157 #define S_NTFY_INTF 10 2158 #define M_NTFY_INTF 0xF 2159 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2160 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2161 2162 #define S_NTFY_TCPHDR_LEN 14 2163 #define M_NTFY_TCPHDR_LEN 0xF 2164 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2165 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2166 2167 #define S_NTFY_IPHDR_LEN 18 2168 #define M_NTFY_IPHDR_LEN 0x1FF 2169 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2170 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2171 2172 #define S_NTFY_ETHHDR_LEN 27 2173 #define M_NTFY_ETHHDR_LEN 0x1F 2174 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2175 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2176 2177 #define S_NTFY_T5_IPHDR_LEN 18 2178 #define M_NTFY_T5_IPHDR_LEN 0xFF 2179 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2180 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2181 2182 #define S_NTFY_T5_ETHHDR_LEN 26 2183 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2184 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2185 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2186 2187 struct cpl_rdma_terminate { 2188 RSS_HDR 2189 union opcode_tid ot; 2190 __be16 rsvd; 2191 __be16 len; 2192 }; 2193 2194 struct cpl_set_le_req { 2195 WR_HDR; 2196 union opcode_tid ot; 2197 __be16 reply_ctrl; 2198 __be16 params; 2199 __be64 mask_hi; 2200 __be64 mask_lo; 2201 __be64 val_hi; 2202 __be64 val_lo; 2203 }; 2204 2205 /* cpl_set_le_req.reply_ctrl additional fields */ 2206 #define S_LE_REQ_IP6 13 2207 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2208 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2209 2210 /* cpl_set_le_req.params fields */ 2211 #define S_LE_CHAN 0 2212 #define M_LE_CHAN 0x3 2213 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2214 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2215 2216 #define S_LE_OFFSET 5 2217 #define M_LE_OFFSET 0x7 2218 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2219 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2220 2221 #define S_LE_MORE 8 2222 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2223 #define F_LE_MORE V_LE_MORE(1U) 2224 2225 #define S_LE_REQSIZE 9 2226 #define M_LE_REQSIZE 0x7 2227 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2228 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2229 2230 #define S_LE_REQCMD 12 2231 #define M_LE_REQCMD 0xF 2232 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2233 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2234 2235 struct cpl_set_le_rpl { 2236 RSS_HDR 2237 union opcode_tid ot; 2238 __u8 chan; 2239 __u8 info; 2240 __be16 len; 2241 }; 2242 2243 /* cpl_set_le_rpl.info fields */ 2244 #define S_LE_RSPCMD 0 2245 #define M_LE_RSPCMD 0xF 2246 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2247 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2248 2249 #define S_LE_RSPSIZE 4 2250 #define M_LE_RSPSIZE 0x7 2251 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2252 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2253 2254 #define S_LE_RSPTYPE 7 2255 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2256 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2257 2258 struct cpl_sge_egr_update { 2259 RSS_HDR 2260 __be32 opcode_qid; 2261 __be16 cidx; 2262 __be16 pidx; 2263 }; 2264 2265 /* cpl_sge_egr_update.ot fields */ 2266 #define S_EGR_QID 0 2267 #define M_EGR_QID 0x1FFFF 2268 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2269 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2270 2271 /* cpl_fw*.type values */ 2272 enum { 2273 FW_TYPE_CMD_RPL = 0, 2274 FW_TYPE_WR_RPL = 1, 2275 FW_TYPE_CQE = 2, 2276 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2277 FW_TYPE_RSSCPL = 4, 2278 }; 2279 2280 struct cpl_fw2_pld { 2281 RSS_HDR 2282 u8 opcode; 2283 u8 rsvd[5]; 2284 __be16 len; 2285 }; 2286 2287 struct cpl_fw4_pld { 2288 RSS_HDR 2289 u8 opcode; 2290 u8 rsvd0[3]; 2291 u8 type; 2292 u8 rsvd1; 2293 __be16 len; 2294 __be64 data; 2295 __be64 rsvd2; 2296 }; 2297 2298 struct cpl_fw6_pld { 2299 RSS_HDR 2300 u8 opcode; 2301 u8 rsvd[5]; 2302 __be16 len; 2303 __be64 data[4]; 2304 }; 2305 2306 struct cpl_fw2_msg { 2307 RSS_HDR 2308 union opcode_info oi; 2309 }; 2310 2311 struct cpl_fw4_msg { 2312 RSS_HDR 2313 u8 opcode; 2314 u8 type; 2315 __be16 rsvd0; 2316 __be32 rsvd1; 2317 __be64 data[2]; 2318 }; 2319 2320 struct cpl_fw4_ack { 2321 RSS_HDR 2322 union opcode_tid ot; 2323 u8 credits; 2324 u8 rsvd0[2]; 2325 u8 flags; 2326 __be32 snd_nxt; 2327 __be32 snd_una; 2328 __be64 rsvd1; 2329 }; 2330 2331 enum { 2332 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2333 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2334 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2335 }; 2336 2337 struct cpl_fw6_msg { 2338 RSS_HDR 2339 u8 opcode; 2340 u8 type; 2341 __be16 rsvd0; 2342 __be32 rsvd1; 2343 __be64 data[4]; 2344 }; 2345 2346 /* cpl_fw6_msg.type values */ 2347 enum { 2348 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2349 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2350 FW6_TYPE_CQE = FW_TYPE_CQE, 2351 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2352 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2353 2354 NUM_FW6_TYPES 2355 }; 2356 2357 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2358 __u64 cookie; 2359 __be32 tid; /* or atid in case of active failure */ 2360 __u8 t_state; 2361 __u8 retval; 2362 __u8 rsvd[2]; 2363 }; 2364 2365 /* ULP_TX opcodes */ 2366 enum { 2367 ULP_TX_MEM_READ = 2, 2368 ULP_TX_MEM_WRITE = 3, 2369 ULP_TX_PKT = 4 2370 }; 2371 2372 enum { 2373 ULP_TX_SC_NOOP = 0x80, 2374 ULP_TX_SC_IMM = 0x81, 2375 ULP_TX_SC_DSGL = 0x82, 2376 ULP_TX_SC_ISGL = 0x83 2377 }; 2378 2379 #define S_ULPTX_CMD 24 2380 #define M_ULPTX_CMD 0xFF 2381 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2382 2383 #define S_ULPTX_LEN16 0 2384 #define M_ULPTX_LEN16 0xFF 2385 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2386 2387 #define S_ULP_TX_SC_MORE 23 2388 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2389 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2390 2391 struct ulptx_sge_pair { 2392 __be32 len[2]; 2393 __be64 addr[2]; 2394 }; 2395 2396 struct ulptx_sgl { 2397 __be32 cmd_nsge; 2398 __be32 len0; 2399 __be64 addr0; 2400 #if !(defined C99_NOT_SUPPORTED) 2401 struct ulptx_sge_pair sge[0]; 2402 #endif 2403 }; 2404 2405 struct ulptx_isge { 2406 __be32 stag; 2407 __be32 len; 2408 __be64 target_ofst; 2409 }; 2410 2411 struct ulptx_isgl { 2412 __be32 cmd_nisge; 2413 __be32 rsvd; 2414 #if !(defined C99_NOT_SUPPORTED) 2415 struct ulptx_isge sge[0]; 2416 #endif 2417 }; 2418 2419 struct ulptx_idata { 2420 __be32 cmd_more; 2421 __be32 len; 2422 }; 2423 2424 #define S_ULPTX_NSGE 0 2425 #define M_ULPTX_NSGE 0xFFFF 2426 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2427 2428 struct ulp_mem_io { 2429 WR_HDR; 2430 __be32 cmd; 2431 __be32 len16; /* command length */ 2432 __be32 dlen; /* data length in 32-byte units */ 2433 __be32 lock_addr; 2434 }; 2435 2436 /* additional ulp_mem_io.cmd fields */ 2437 #define S_ULP_MEMIO_ORDER 23 2438 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2439 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2440 2441 #define S_T5_ULP_MEMIO_IMM 23 2442 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2443 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2444 2445 #define S_T5_ULP_MEMIO_ORDER 22 2446 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2447 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2448 2449 /* ulp_mem_io.lock_addr fields */ 2450 #define S_ULP_MEMIO_ADDR 0 2451 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2452 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2453 2454 #define S_ULP_MEMIO_LOCK 31 2455 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2456 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2457 2458 /* ulp_mem_io.dlen fields */ 2459 #define S_ULP_MEMIO_DATA_LEN 0 2460 #define M_ULP_MEMIO_DATA_LEN 0x1F 2461 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2462 2463 /* ULP_TXPKT field values */ 2464 enum { 2465 ULP_TXPKT_DEST_TP = 0, 2466 ULP_TXPKT_DEST_SGE, 2467 ULP_TXPKT_DEST_UP, 2468 ULP_TXPKT_DEST_DEVNULL, 2469 }; 2470 2471 struct ulp_txpkt { 2472 __be32 cmd_dest; 2473 __be32 len; 2474 }; 2475 2476 /* ulp_txpkt.cmd_dest fields */ 2477 #define S_ULP_TXPKT_DEST 16 2478 #define M_ULP_TXPKT_DEST 0x3 2479 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2480 2481 #define S_ULP_TXPKT_FID 4 2482 #define M_ULP_TXPKT_FID 0x7ff 2483 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2484 2485 #define S_ULP_TXPKT_RO 3 2486 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2487 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2488 2489 #endif /* T4_MSG_H */ 2490