1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_PKT_ISO = 0x1F, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_URG_PKT = 0x29, 71 CPL_TAG_WRITE_RPL = 0x2A, 72 CPL_ABORT_REQ_RSS = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_ABORT_RPL_RSS = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_RX_PHYS_ADDR = 0x30, 79 CPL_PCMD_READ_RPL = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 CPL_SET_TCB_RPL = 0x3A, 89 CPL_RX_PKT = 0x3B, 90 CPL_TAG_READ_RPL = 0x3C, 91 CPL_HIT_NOTIFY = 0x3D, 92 CPL_PKT_NOTIFY = 0x3E, 93 CPL_RX_DDP_COMPLETE = 0x3F, 94 95 CPL_ACT_ESTABLISH = 0x40, 96 CPL_PASS_ESTABLISH = 0x41, 97 CPL_RX_DATA_DDP = 0x42, 98 CPL_SMT_READ_RPL = 0x43, 99 CPL_PASS_ACCEPT_REQ = 0x44, 100 CPL_RX2TX_PKT = 0x45, 101 CPL_RX_FCOE_DDP = 0x46, 102 CPL_FCOE_HDR = 0x47, 103 CPL_T5_TRACE_PKT = 0x48, 104 CPL_RX_ISCSI_DDP = 0x49, 105 CPL_RX_FCOE_DIF = 0x4A, 106 CPL_RX_DATA_DIF = 0x4B, 107 108 CPL_RDMA_READ_REQ = 0x60, 109 CPL_RX_ISCSI_DIF = 0x60, 110 111 CPL_SET_LE_REQ = 0x80, 112 CPL_PASS_OPEN_REQ6 = 0x81, 113 CPL_ACT_OPEN_REQ6 = 0x83, 114 115 CPL_RDMA_TERMINATE = 0xA2, 116 CPL_RDMA_WRITE = 0xA4, 117 CPL_SGE_EGR_UPDATE = 0xA5, 118 CPL_SET_LE_RPL = 0xA6, 119 CPL_FW2_MSG = 0xA7, 120 CPL_FW2_PLD = 0xA8, 121 CPL_T5_RDMA_READ_REQ = 0xA9, 122 CPL_RDMA_ATOMIC_REQ = 0xAA, 123 CPL_RDMA_ATOMIC_RPL = 0xAB, 124 CPL_RDMA_IMM_DATA = 0xAC, 125 CPL_RDMA_IMM_DATA_SE = 0xAD, 126 127 CPL_TRACE_PKT = 0xB0, 128 CPL_RX2TX_DATA = 0xB1, 129 CPL_ISCSI_DATA = 0xB2, 130 CPL_FCOE_DATA = 0xB3, 131 132 CPL_FW4_MSG = 0xC0, 133 CPL_FW4_PLD = 0xC1, 134 CPL_FW4_ACK = 0xC3, 135 136 CPL_FW6_MSG = 0xE0, 137 CPL_FW6_PLD = 0xE1, 138 CPL_TX_PKT_LSO = 0xED, 139 CPL_TX_PKT_XT = 0xEE, 140 141 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 142 }; 143 144 enum CPL_error { 145 CPL_ERR_NONE = 0, 146 CPL_ERR_TCAM_PARITY = 1, 147 CPL_ERR_TCAM_FULL = 3, 148 CPL_ERR_BAD_LENGTH = 15, 149 CPL_ERR_BAD_ROUTE = 18, 150 CPL_ERR_CONN_RESET = 20, 151 CPL_ERR_CONN_EXIST_SYNRECV = 21, 152 CPL_ERR_CONN_EXIST = 22, 153 CPL_ERR_ARP_MISS = 23, 154 CPL_ERR_BAD_SYN = 24, 155 CPL_ERR_CONN_TIMEDOUT = 30, 156 CPL_ERR_XMIT_TIMEDOUT = 31, 157 CPL_ERR_PERSIST_TIMEDOUT = 32, 158 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 159 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 160 CPL_ERR_RTX_NEG_ADVICE = 35, 161 CPL_ERR_PERSIST_NEG_ADVICE = 36, 162 CPL_ERR_ABORT_FAILED = 42, 163 CPL_ERR_IWARP_FLM = 50, 164 }; 165 166 enum { 167 CPL_CONN_POLICY_AUTO = 0, 168 CPL_CONN_POLICY_ASK = 1, 169 CPL_CONN_POLICY_FILTER = 2, 170 CPL_CONN_POLICY_DENY = 3 171 }; 172 173 enum { 174 ULP_MODE_NONE = 0, 175 ULP_MODE_ISCSI = 2, 176 ULP_MODE_RDMA = 4, 177 ULP_MODE_TCPDDP = 5, 178 ULP_MODE_FCOE = 6, 179 }; 180 181 enum { 182 ULP_CRC_HEADER = 1 << 0, 183 ULP_CRC_DATA = 1 << 1 184 }; 185 186 enum { 187 CPL_PASS_OPEN_ACCEPT, 188 CPL_PASS_OPEN_REJECT, 189 CPL_PASS_OPEN_ACCEPT_TNL 190 }; 191 192 enum { 193 CPL_ABORT_SEND_RST = 0, 194 CPL_ABORT_NO_RST, 195 }; 196 197 enum { /* TX_PKT_XT checksum types */ 198 TX_CSUM_TCP = 0, 199 TX_CSUM_UDP = 1, 200 TX_CSUM_CRC16 = 4, 201 TX_CSUM_CRC32 = 5, 202 TX_CSUM_CRC32C = 6, 203 TX_CSUM_FCOE = 7, 204 TX_CSUM_TCPIP = 8, 205 TX_CSUM_UDPIP = 9, 206 TX_CSUM_TCPIP6 = 10, 207 TX_CSUM_UDPIP6 = 11, 208 TX_CSUM_IP = 12, 209 }; 210 211 enum { /* packet type in CPL_RX_PKT */ 212 PKTYPE_XACT_UCAST = 0, 213 PKTYPE_HASH_UCAST = 1, 214 PKTYPE_XACT_MCAST = 2, 215 PKTYPE_HASH_MCAST = 3, 216 PKTYPE_PROMISC = 4, 217 PKTYPE_HPROMISC = 5, 218 PKTYPE_BCAST = 6 219 }; 220 221 enum { /* DMAC type in CPL_RX_PKT */ 222 DATYPE_UCAST, 223 DATYPE_MCAST, 224 DATYPE_BCAST 225 }; 226 227 enum { /* TCP congestion control algorithms */ 228 CONG_ALG_RENO, 229 CONG_ALG_TAHOE, 230 CONG_ALG_NEWRENO, 231 CONG_ALG_HIGHSPEED 232 }; 233 234 enum { /* RSS hash type */ 235 RSS_HASH_NONE = 0, /* no hash computed */ 236 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 237 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 238 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 239 }; 240 241 enum { /* LE commands */ 242 LE_CMD_READ = 0x4, 243 LE_CMD_WRITE = 0xb 244 }; 245 246 enum { /* LE request size */ 247 LE_SZ_NONE = 0, 248 LE_SZ_33 = 1, 249 LE_SZ_66 = 2, 250 LE_SZ_132 = 3, 251 LE_SZ_264 = 4, 252 LE_SZ_528 = 5 253 }; 254 255 union opcode_tid { 256 __be32 opcode_tid; 257 __u8 opcode; 258 }; 259 260 #define S_CPL_OPCODE 24 261 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 262 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 263 #define G_TID(x) ((x) & 0xFFFFFF) 264 265 /* tid is assumed to be 24-bits */ 266 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 267 268 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 269 270 /* extract the TID from a CPL command */ 271 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 272 273 /* partitioning of TID fields that also carry a queue id */ 274 #define S_TID_TID 0 275 #define M_TID_TID 0x3fff 276 #define V_TID_TID(x) ((x) << S_TID_TID) 277 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 278 279 #define S_TID_QID 14 280 #define M_TID_QID 0x3ff 281 #define V_TID_QID(x) ((x) << S_TID_QID) 282 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 283 284 union opcode_info { 285 __be64 opcode_info; 286 __u8 opcode; 287 }; 288 289 struct tcp_options { 290 __be16 mss; 291 __u8 wsf; 292 #if defined(__LITTLE_ENDIAN_BITFIELD) 293 __u8 :4; 294 __u8 unknown:1; 295 __u8 ecn:1; 296 __u8 sack:1; 297 __u8 tstamp:1; 298 #else 299 __u8 tstamp:1; 300 __u8 sack:1; 301 __u8 ecn:1; 302 __u8 unknown:1; 303 __u8 :4; 304 #endif 305 }; 306 307 struct rss_header { 308 __u8 opcode; 309 #if defined(__LITTLE_ENDIAN_BITFIELD) 310 __u8 channel:2; 311 __u8 filter_hit:1; 312 __u8 filter_tid:1; 313 __u8 hash_type:2; 314 __u8 ipv6:1; 315 __u8 send2fw:1; 316 #else 317 __u8 send2fw:1; 318 __u8 ipv6:1; 319 __u8 hash_type:2; 320 __u8 filter_tid:1; 321 __u8 filter_hit:1; 322 __u8 channel:2; 323 #endif 324 __be16 qid; 325 __be32 hash_val; 326 }; 327 328 #define S_HASHTYPE 20 329 #define M_HASHTYPE 0x3 330 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 331 332 #define S_QNUM 0 333 #define M_QNUM 0xFFFF 334 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 335 336 #ifndef CHELSIO_FW 337 struct work_request_hdr { 338 __be32 wr_hi; 339 __be32 wr_mid; 340 __be64 wr_lo; 341 }; 342 343 /* wr_mid fields */ 344 #define S_WR_LEN16 0 345 #define M_WR_LEN16 0xFF 346 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 347 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 348 349 /* wr_hi fields */ 350 #define S_WR_OP 24 351 #define M_WR_OP 0xFF 352 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 353 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 354 355 # define WR_HDR struct work_request_hdr wr 356 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 357 # define RSS_HDR 358 #else 359 # define WR_HDR 360 # define WR_HDR_SIZE 0 361 # define RSS_HDR struct rss_header rss_hdr; 362 #endif 363 364 /* option 0 fields */ 365 #define S_ACCEPT_MODE 0 366 #define M_ACCEPT_MODE 0x3 367 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 368 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 369 370 #define S_TX_CHAN 2 371 #define M_TX_CHAN 0x3 372 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 373 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 374 375 #define S_NO_CONG 4 376 #define V_NO_CONG(x) ((x) << S_NO_CONG) 377 #define F_NO_CONG V_NO_CONG(1U) 378 379 #define S_DELACK 5 380 #define V_DELACK(x) ((x) << S_DELACK) 381 #define F_DELACK V_DELACK(1U) 382 383 #define S_INJECT_TIMER 6 384 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 385 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 386 387 #define S_NON_OFFLOAD 7 388 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 389 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 390 391 #define S_ULP_MODE 8 392 #define M_ULP_MODE 0xF 393 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 394 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 395 396 #define S_RCV_BUFSIZ 12 397 #define M_RCV_BUFSIZ 0x3FFU 398 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 399 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 400 401 #define S_DSCP 22 402 #define M_DSCP 0x3F 403 #define V_DSCP(x) ((x) << S_DSCP) 404 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 405 406 #define S_SMAC_SEL 28 407 #define M_SMAC_SEL 0xFF 408 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 409 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 410 411 #define S_L2T_IDX 36 412 #define M_L2T_IDX 0xFFF 413 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 414 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 415 416 #define S_TCAM_BYPASS 48 417 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 418 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 419 420 #define S_NAGLE 49 421 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 422 #define F_NAGLE V_NAGLE(1ULL) 423 424 #define S_WND_SCALE 50 425 #define M_WND_SCALE 0xF 426 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 427 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 428 429 #define S_KEEP_ALIVE 54 430 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 431 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 432 433 #define S_MAX_RT 55 434 #define M_MAX_RT 0xF 435 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 436 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 437 438 #define S_MAX_RT_OVERRIDE 59 439 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 440 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 441 442 #define S_MSS_IDX 60 443 #define M_MSS_IDX 0xF 444 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 445 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 446 447 /* option 1 fields */ 448 #define S_SYN_RSS_ENABLE 0 449 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 450 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 451 452 #define S_SYN_RSS_USE_HASH 1 453 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 454 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 455 456 #define S_SYN_RSS_QUEUE 2 457 #define M_SYN_RSS_QUEUE 0x3FF 458 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 459 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 460 461 #define S_LISTEN_INTF 12 462 #define M_LISTEN_INTF 0xFF 463 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 464 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 465 466 #define S_LISTEN_FILTER 20 467 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 468 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 469 470 #define S_SYN_DEFENSE 21 471 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 472 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 473 474 #define S_CONN_POLICY 22 475 #define M_CONN_POLICY 0x3 476 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 477 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 478 479 /* option 2 fields */ 480 #define S_RSS_QUEUE 0 481 #define M_RSS_QUEUE 0x3FF 482 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 483 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 484 485 #define S_RSS_QUEUE_VALID 10 486 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 487 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 488 489 #define S_RX_COALESCE_VALID 11 490 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 491 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 492 493 #define S_RX_COALESCE 12 494 #define M_RX_COALESCE 0x3 495 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 496 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 497 498 #define S_CONG_CNTRL 14 499 #define M_CONG_CNTRL 0x3 500 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 501 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 502 503 #define S_PACE 16 504 #define M_PACE 0x3 505 #define V_PACE(x) ((x) << S_PACE) 506 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 507 508 #define S_CONG_CNTRL_VALID 18 509 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 510 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 511 512 #define S_PACE_VALID 19 513 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 514 #define F_PACE_VALID V_PACE_VALID(1U) 515 516 #define S_RX_FC_DISABLE 20 517 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 518 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 519 520 #define S_RX_FC_DDP 21 521 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 522 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 523 524 #define S_RX_FC_VALID 22 525 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 526 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 527 528 #define S_TX_QUEUE 23 529 #define M_TX_QUEUE 0x7 530 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 531 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 532 533 #define S_RX_CHANNEL 26 534 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 535 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 536 537 #define S_CCTRL_ECN 27 538 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 539 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 540 541 #define S_WND_SCALE_EN 28 542 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 543 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 544 545 #define S_TSTAMPS_EN 29 546 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 547 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 548 549 #define S_SACK_EN 30 550 #define V_SACK_EN(x) ((x) << S_SACK_EN) 551 #define F_SACK_EN V_SACK_EN(1U) 552 553 struct cpl_pass_open_req { 554 WR_HDR; 555 union opcode_tid ot; 556 __be16 local_port; 557 __be16 peer_port; 558 __be32 local_ip; 559 __be32 peer_ip; 560 __be64 opt0; 561 __be64 opt1; 562 }; 563 564 struct cpl_pass_open_req6 { 565 WR_HDR; 566 union opcode_tid ot; 567 __be16 local_port; 568 __be16 peer_port; 569 __be64 local_ip_hi; 570 __be64 local_ip_lo; 571 __be64 peer_ip_hi; 572 __be64 peer_ip_lo; 573 __be64 opt0; 574 __be64 opt1; 575 }; 576 577 struct cpl_pass_open_rpl { 578 RSS_HDR 579 union opcode_tid ot; 580 __u8 rsvd[3]; 581 __u8 status; 582 }; 583 584 struct cpl_pass_establish { 585 RSS_HDR 586 union opcode_tid ot; 587 __be32 rsvd; 588 __be32 tos_stid; 589 __be16 mac_idx; 590 __be16 tcp_opt; 591 __be32 snd_isn; 592 __be32 rcv_isn; 593 }; 594 595 /* cpl_pass_establish.tos_stid fields */ 596 #define S_PASS_OPEN_TID 0 597 #define M_PASS_OPEN_TID 0xFFFFFF 598 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 599 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 600 601 #define S_PASS_OPEN_TOS 24 602 #define M_PASS_OPEN_TOS 0xFF 603 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 604 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 605 606 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 607 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 608 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 609 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 610 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 611 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 612 613 struct cpl_pass_accept_req { 614 RSS_HDR 615 union opcode_tid ot; 616 __be16 rsvd; 617 __be16 len; 618 __be32 hdr_len; 619 __be16 vlan; 620 __be16 l2info; 621 __be32 tos_stid; 622 struct tcp_options tcpopt; 623 }; 624 625 /* cpl_pass_accept_req.hdr_len fields */ 626 #define S_SYN_RX_CHAN 0 627 #define M_SYN_RX_CHAN 0xF 628 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 629 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 630 631 #define S_TCP_HDR_LEN 10 632 #define M_TCP_HDR_LEN 0x3F 633 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 634 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 635 636 #define S_IP_HDR_LEN 16 637 #define M_IP_HDR_LEN 0x3FF 638 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 639 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 640 641 #define S_ETH_HDR_LEN 26 642 #define M_ETH_HDR_LEN 0x3F 643 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 644 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 645 646 /* cpl_pass_accept_req.l2info fields */ 647 #define S_SYN_MAC_IDX 0 648 #define M_SYN_MAC_IDX 0x1FF 649 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 650 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 651 652 #define S_SYN_XACT_MATCH 9 653 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 654 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 655 656 #define S_SYN_INTF 12 657 #define M_SYN_INTF 0xF 658 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 659 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 660 661 struct cpl_pass_accept_rpl { 662 WR_HDR; 663 union opcode_tid ot; 664 __be32 opt2; 665 __be64 opt0; 666 }; 667 668 struct cpl_act_open_req { 669 WR_HDR; 670 union opcode_tid ot; 671 __be16 local_port; 672 __be16 peer_port; 673 __be32 local_ip; 674 __be32 peer_ip; 675 __be64 opt0; 676 __be32 params; 677 __be32 opt2; 678 }; 679 680 struct cpl_t5_act_open_req { 681 WR_HDR; 682 union opcode_tid ot; 683 __be16 local_port; 684 __be16 peer_port; 685 __be32 local_ip; 686 __be32 peer_ip; 687 __be64 opt0; 688 __be32 rsvd; 689 __be32 opt2; 690 __be64 params; 691 }; 692 693 struct cpl_act_open_req6 { 694 WR_HDR; 695 union opcode_tid ot; 696 __be16 local_port; 697 __be16 peer_port; 698 __be64 local_ip_hi; 699 __be64 local_ip_lo; 700 __be64 peer_ip_hi; 701 __be64 peer_ip_lo; 702 __be64 opt0; 703 __be32 params; 704 __be32 opt2; 705 }; 706 707 struct cpl_t5_act_open_req6 { 708 WR_HDR; 709 union opcode_tid ot; 710 __be16 local_port; 711 __be16 peer_port; 712 __be64 local_ip_hi; 713 __be64 local_ip_lo; 714 __be64 peer_ip_hi; 715 __be64 peer_ip_lo; 716 __be64 opt0; 717 __be32 rsvd; 718 __be32 opt2; 719 __be64 params; 720 }; 721 722 struct cpl_act_open_rpl { 723 RSS_HDR 724 union opcode_tid ot; 725 __be32 atid_status; 726 }; 727 728 /* cpl_act_open_rpl.atid_status fields */ 729 #define S_AOPEN_STATUS 0 730 #define M_AOPEN_STATUS 0xFF 731 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 732 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 733 734 #define S_AOPEN_ATID 8 735 #define M_AOPEN_ATID 0xFFFFFF 736 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 737 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 738 739 struct cpl_act_establish { 740 RSS_HDR 741 union opcode_tid ot; 742 __be32 rsvd; 743 __be32 tos_atid; 744 __be16 mac_idx; 745 __be16 tcp_opt; 746 __be32 snd_isn; 747 __be32 rcv_isn; 748 }; 749 750 struct cpl_get_tcb { 751 WR_HDR; 752 union opcode_tid ot; 753 __be16 reply_ctrl; 754 __be16 cookie; 755 }; 756 757 /* cpl_get_tcb.reply_ctrl fields */ 758 #define S_QUEUENO 0 759 #define M_QUEUENO 0x3FF 760 #define V_QUEUENO(x) ((x) << S_QUEUENO) 761 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 762 763 #define S_REPLY_CHAN 14 764 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 765 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 766 767 #define S_NO_REPLY 15 768 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 769 #define F_NO_REPLY V_NO_REPLY(1U) 770 771 struct cpl_get_tcb_rpl { 772 RSS_HDR 773 union opcode_tid ot; 774 __u8 cookie; 775 __u8 status; 776 __be16 len; 777 }; 778 779 struct cpl_set_tcb { 780 WR_HDR; 781 union opcode_tid ot; 782 __be16 reply_ctrl; 783 __be16 cookie; 784 }; 785 786 struct cpl_set_tcb_field { 787 WR_HDR; 788 union opcode_tid ot; 789 __be16 reply_ctrl; 790 __be16 word_cookie; 791 __be64 mask; 792 __be64 val; 793 }; 794 795 /* cpl_set_tcb_field.word_cookie fields */ 796 #define S_WORD 0 797 #define M_WORD 0x1F 798 #define V_WORD(x) ((x) << S_WORD) 799 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 800 801 #define S_COOKIE 5 802 #define M_COOKIE 0x7 803 #define V_COOKIE(x) ((x) << S_COOKIE) 804 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 805 806 struct cpl_set_tcb_rpl { 807 RSS_HDR 808 union opcode_tid ot; 809 __be16 rsvd; 810 __u8 cookie; 811 __u8 status; 812 __be64 oldval; 813 }; 814 815 struct cpl_close_con_req { 816 WR_HDR; 817 union opcode_tid ot; 818 __be32 rsvd; 819 }; 820 821 struct cpl_close_con_rpl { 822 RSS_HDR 823 union opcode_tid ot; 824 __u8 rsvd[3]; 825 __u8 status; 826 __be32 snd_nxt; 827 __be32 rcv_nxt; 828 }; 829 830 struct cpl_close_listsvr_req { 831 WR_HDR; 832 union opcode_tid ot; 833 __be16 reply_ctrl; 834 __be16 rsvd; 835 }; 836 837 /* additional cpl_close_listsvr_req.reply_ctrl field */ 838 #define S_LISTSVR_IPV6 14 839 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 840 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 841 842 struct cpl_close_listsvr_rpl { 843 RSS_HDR 844 union opcode_tid ot; 845 __u8 rsvd[3]; 846 __u8 status; 847 }; 848 849 struct cpl_abort_req_rss { 850 RSS_HDR 851 union opcode_tid ot; 852 __u8 rsvd[3]; 853 __u8 status; 854 }; 855 856 struct cpl_abort_req { 857 WR_HDR; 858 union opcode_tid ot; 859 __be32 rsvd0; 860 __u8 rsvd1; 861 __u8 cmd; 862 __u8 rsvd2[6]; 863 }; 864 865 struct cpl_abort_rpl_rss { 866 RSS_HDR 867 union opcode_tid ot; 868 __u8 rsvd[3]; 869 __u8 status; 870 }; 871 872 struct cpl_abort_rpl { 873 WR_HDR; 874 union opcode_tid ot; 875 __be32 rsvd0; 876 __u8 rsvd1; 877 __u8 cmd; 878 __u8 rsvd2[6]; 879 }; 880 881 struct cpl_peer_close { 882 RSS_HDR 883 union opcode_tid ot; 884 __be32 rcv_nxt; 885 }; 886 887 struct cpl_tid_release { 888 WR_HDR; 889 union opcode_tid ot; 890 __be32 rsvd; 891 }; 892 893 struct tx_data_wr { 894 __be32 wr_hi; 895 __be32 wr_lo; 896 __be32 len; 897 __be32 flags; 898 __be32 sndseq; 899 __be32 param; 900 }; 901 902 /* tx_data_wr.flags fields */ 903 #define S_TX_ACK_PAGES 21 904 #define M_TX_ACK_PAGES 0x7 905 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 906 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 907 908 /* tx_data_wr.param fields */ 909 #define S_TX_PORT 0 910 #define M_TX_PORT 0x7 911 #define V_TX_PORT(x) ((x) << S_TX_PORT) 912 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 913 914 #define S_TX_MSS 4 915 #define M_TX_MSS 0xF 916 #define V_TX_MSS(x) ((x) << S_TX_MSS) 917 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 918 919 #define S_TX_QOS 8 920 #define M_TX_QOS 0xFF 921 #define V_TX_QOS(x) ((x) << S_TX_QOS) 922 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 923 924 #define S_TX_SNDBUF 16 925 #define M_TX_SNDBUF 0xFFFF 926 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 927 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 928 929 struct cpl_tx_data { 930 union opcode_tid ot; 931 __be32 len; 932 __be32 rsvd; 933 __be32 flags; 934 }; 935 936 /* cpl_tx_data.flags fields */ 937 #define S_TX_PROXY 5 938 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 939 #define F_TX_PROXY V_TX_PROXY(1U) 940 941 #define S_TX_ULP_SUBMODE 6 942 #define M_TX_ULP_SUBMODE 0xF 943 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 944 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 945 946 #define S_TX_ULP_MODE 10 947 #define M_TX_ULP_MODE 0xF 948 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 949 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 950 951 #define S_TX_SHOVE 14 952 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 953 #define F_TX_SHOVE V_TX_SHOVE(1U) 954 955 #define S_TX_MORE 15 956 #define V_TX_MORE(x) ((x) << S_TX_MORE) 957 #define F_TX_MORE V_TX_MORE(1U) 958 959 #define S_TX_URG 16 960 #define V_TX_URG(x) ((x) << S_TX_URG) 961 #define F_TX_URG V_TX_URG(1U) 962 963 #define S_TX_FLUSH 17 964 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 965 #define F_TX_FLUSH V_TX_FLUSH(1U) 966 967 #define S_TX_SAVE 18 968 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 969 #define F_TX_SAVE V_TX_SAVE(1U) 970 971 #define S_TX_TNL 19 972 #define V_TX_TNL(x) ((x) << S_TX_TNL) 973 #define F_TX_TNL V_TX_TNL(1U) 974 975 /* additional tx_data_wr.flags fields */ 976 #define S_TX_CPU_IDX 0 977 #define M_TX_CPU_IDX 0x3F 978 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 979 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 980 981 #define S_TX_CLOSE 17 982 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 983 #define F_TX_CLOSE V_TX_CLOSE(1U) 984 985 #define S_TX_INIT 18 986 #define V_TX_INIT(x) ((x) << S_TX_INIT) 987 #define F_TX_INIT V_TX_INIT(1U) 988 989 #define S_TX_IMM_ACK 19 990 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 991 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 992 993 #define S_TX_IMM_DMA 20 994 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 995 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 996 997 struct cpl_tx_data_ack { 998 RSS_HDR 999 union opcode_tid ot; 1000 __be32 snd_una; 1001 }; 1002 1003 struct cpl_wr_ack { /* XXX */ 1004 RSS_HDR 1005 union opcode_tid ot; 1006 __be16 credits; 1007 __be16 rsvd; 1008 __be32 snd_nxt; 1009 __be32 snd_una; 1010 }; 1011 1012 struct cpl_tx_pkt_core { 1013 __be32 ctrl0; 1014 __be16 pack; 1015 __be16 len; 1016 __be64 ctrl1; 1017 }; 1018 1019 struct cpl_tx_pkt { 1020 WR_HDR; 1021 struct cpl_tx_pkt_core c; 1022 }; 1023 1024 #define cpl_tx_pkt_xt cpl_tx_pkt 1025 1026 /* cpl_tx_pkt_core.ctrl0 fields */ 1027 #define S_TXPKT_VF 0 1028 #define M_TXPKT_VF 0xFF 1029 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1030 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1031 1032 #define S_TXPKT_PF 8 1033 #define M_TXPKT_PF 0x7 1034 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1035 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1036 1037 #define S_TXPKT_VF_VLD 11 1038 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1039 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1040 1041 #define S_TXPKT_OVLAN_IDX 12 1042 #define M_TXPKT_OVLAN_IDX 0xF 1043 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1044 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1045 1046 #define S_TXPKT_INTF 16 1047 #define M_TXPKT_INTF 0xF 1048 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1049 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1050 1051 #define S_TXPKT_SPECIAL_STAT 20 1052 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1053 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1054 1055 #define S_TXPKT_INS_OVLAN 21 1056 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1057 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1058 1059 #define S_TXPKT_STAT_DIS 22 1060 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1061 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1062 1063 #define S_TXPKT_LOOPBACK 23 1064 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1065 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1066 1067 #define S_TXPKT_TSTAMP 23 1068 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1069 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1070 1071 #define S_TXPKT_OPCODE 24 1072 #define M_TXPKT_OPCODE 0xFF 1073 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1074 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1075 1076 /* cpl_tx_pkt_core.ctrl1 fields */ 1077 #define S_TXPKT_SA_IDX 0 1078 #define M_TXPKT_SA_IDX 0xFFF 1079 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1080 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1081 1082 #define S_TXPKT_CSUM_END 12 1083 #define M_TXPKT_CSUM_END 0xFF 1084 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1085 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1086 1087 #define S_TXPKT_CSUM_START 20 1088 #define M_TXPKT_CSUM_START 0x3FF 1089 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1090 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1091 1092 #define S_TXPKT_IPHDR_LEN 20 1093 #define M_TXPKT_IPHDR_LEN 0x3FFF 1094 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1095 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1096 1097 #define S_TXPKT_CSUM_LOC 30 1098 #define M_TXPKT_CSUM_LOC 0x3FF 1099 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1100 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1101 1102 #define S_TXPKT_ETHHDR_LEN 34 1103 #define M_TXPKT_ETHHDR_LEN 0x3F 1104 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1105 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1106 1107 #define S_TXPKT_CSUM_TYPE 40 1108 #define M_TXPKT_CSUM_TYPE 0xF 1109 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1110 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1111 1112 #define S_TXPKT_VLAN 44 1113 #define M_TXPKT_VLAN 0xFFFF 1114 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1115 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1116 1117 #define S_TXPKT_VLAN_VLD 60 1118 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1119 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1120 1121 #define S_TXPKT_IPSEC 61 1122 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1123 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1124 1125 #define S_TXPKT_IPCSUM_DIS 62 1126 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1127 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1128 1129 #define S_TXPKT_L4CSUM_DIS 63 1130 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1131 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1132 1133 struct cpl_tx_pkt_lso_core { 1134 __be32 lso_ctrl; 1135 __be16 ipid_ofst; 1136 __be16 mss; 1137 __be32 seqno_offset; 1138 __be32 len; 1139 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1140 }; 1141 1142 struct cpl_tx_pkt_lso { 1143 WR_HDR; 1144 struct cpl_tx_pkt_lso_core c; 1145 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1146 }; 1147 1148 struct cpl_tx_pkt_ufo_core { 1149 __be16 ethlen; 1150 __be16 iplen; 1151 __be16 udplen; 1152 __be16 mss; 1153 __be32 len; 1154 __be32 r1; 1155 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1156 }; 1157 1158 struct cpl_tx_pkt_ufo { 1159 WR_HDR; 1160 struct cpl_tx_pkt_ufo_core c; 1161 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1162 }; 1163 1164 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1165 #define S_LSO_TCPHDR_LEN 0 1166 #define M_LSO_TCPHDR_LEN 0xF 1167 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1168 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1169 1170 #define S_LSO_IPHDR_LEN 4 1171 #define M_LSO_IPHDR_LEN 0xFFF 1172 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1173 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1174 1175 #define S_LSO_ETHHDR_LEN 16 1176 #define M_LSO_ETHHDR_LEN 0xF 1177 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1178 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1179 1180 #define S_LSO_IPV6 20 1181 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1182 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1183 1184 #define S_LSO_OFLD_ENCAP 21 1185 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1186 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1187 1188 #define S_LSO_LAST_SLICE 22 1189 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1190 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1191 1192 #define S_LSO_FIRST_SLICE 23 1193 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1194 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1195 1196 #define S_LSO_OPCODE 24 1197 #define M_LSO_OPCODE 0xFF 1198 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1199 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1200 1201 /* cpl_tx_pkt_lso_core.mss fields */ 1202 #define S_LSO_MSS 0 1203 #define M_LSO_MSS 0x3FFF 1204 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1205 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1206 1207 #define S_LSO_IPID_SPLIT 15 1208 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1209 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1210 1211 struct cpl_tx_pkt_fso { 1212 WR_HDR; 1213 __be32 fso_ctrl; 1214 __be16 seqcnt_ofst; 1215 __be16 mtu; 1216 __be32 param_offset; 1217 __be32 len; 1218 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1219 }; 1220 1221 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1222 #define S_FSO_XCHG_CLASS 21 1223 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1224 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1225 1226 #define S_FSO_INITIATOR 20 1227 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1228 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1229 1230 #define S_FSO_FCHDR_LEN 12 1231 #define M_FSO_FCHDR_LEN 0xF 1232 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1233 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1234 1235 struct cpl_iscsi_hdr_no_rss { 1236 union opcode_tid ot; 1237 __be16 pdu_len_ddp; 1238 __be16 len; 1239 __be32 seq; 1240 __be16 urg; 1241 __u8 rsvd; 1242 __u8 status; 1243 }; 1244 1245 struct cpl_tx_data_iso { 1246 WR_HDR; 1247 __be32 iso_ctrl; 1248 __u8 rsvd; 1249 __u8 ahs_len; 1250 __be16 mss; 1251 __be32 burst_size; 1252 __be32 len; 1253 /* encapsulated CPL_TX_DATA follows here */ 1254 }; 1255 1256 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1257 #define S_ISO_CPLHDR_LEN 18 1258 #define M_ISO_CPLHDR_LEN 0xF 1259 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1260 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1261 1262 #define S_ISO_HDR_CRC 17 1263 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1264 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1265 1266 #define S_ISO_DATA_CRC 16 1267 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1268 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1269 1270 #define S_ISO_IMD_DATA_EN 15 1271 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1272 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1273 1274 #define S_ISO_PDU_TYPE 13 1275 #define M_ISO_PDU_TYPE 0x3 1276 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1277 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1278 1279 struct cpl_iscsi_hdr { 1280 RSS_HDR 1281 union opcode_tid ot; 1282 __be16 pdu_len_ddp; 1283 __be16 len; 1284 __be32 seq; 1285 __be16 urg; 1286 __u8 rsvd; 1287 __u8 status; 1288 }; 1289 1290 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1291 #define S_ISCSI_PDU_LEN 0 1292 #define M_ISCSI_PDU_LEN 0x7FFF 1293 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1294 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1295 1296 #define S_ISCSI_DDP 15 1297 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1298 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1299 1300 struct cpl_iscsi_data { 1301 RSS_HDR 1302 union opcode_tid ot; 1303 __u8 rsvd0[2]; 1304 __be16 len; 1305 __be32 seq; 1306 __be16 urg; 1307 __u8 rsvd1; 1308 __u8 status; 1309 }; 1310 1311 struct cpl_rx_data { 1312 RSS_HDR 1313 union opcode_tid ot; 1314 __be16 rsvd; 1315 __be16 len; 1316 __be32 seq; 1317 __be16 urg; 1318 #if defined(__LITTLE_ENDIAN_BITFIELD) 1319 __u8 dack_mode:2; 1320 __u8 psh:1; 1321 __u8 heartbeat:1; 1322 __u8 ddp_off:1; 1323 __u8 :3; 1324 #else 1325 __u8 :3; 1326 __u8 ddp_off:1; 1327 __u8 heartbeat:1; 1328 __u8 psh:1; 1329 __u8 dack_mode:2; 1330 #endif 1331 __u8 status; 1332 }; 1333 1334 struct cpl_fcoe_hdr { 1335 RSS_HDR 1336 union opcode_tid ot; 1337 __be16 oxid; 1338 __be16 len; 1339 __be32 rctl_fctl; 1340 __u8 cs_ctl; 1341 __u8 df_ctl; 1342 __u8 sof; 1343 __u8 eof; 1344 __be16 seq_cnt; 1345 __u8 seq_id; 1346 __u8 type; 1347 __be32 param; 1348 }; 1349 1350 struct cpl_fcoe_data { 1351 RSS_HDR 1352 union opcode_tid ot; 1353 __u8 rsvd0[2]; 1354 __be16 len; 1355 __be32 seq; 1356 __u8 rsvd1[3]; 1357 __u8 status; 1358 }; 1359 1360 struct cpl_rx_urg_notify { 1361 RSS_HDR 1362 union opcode_tid ot; 1363 __be32 seq; 1364 }; 1365 1366 struct cpl_rx_urg_pkt { 1367 RSS_HDR 1368 union opcode_tid ot; 1369 __be16 rsvd; 1370 __be16 len; 1371 }; 1372 1373 struct cpl_rx_data_ack { 1374 WR_HDR; 1375 union opcode_tid ot; 1376 __be32 credit_dack; 1377 }; 1378 1379 /* cpl_rx_data_ack.ack_seq fields */ 1380 #define S_RX_CREDITS 0 1381 #define M_RX_CREDITS 0x3FFFFFF 1382 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1383 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1384 1385 #define S_RX_MODULATE_TX 26 1386 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1387 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1388 1389 #define S_RX_MODULATE_RX 27 1390 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1391 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1392 1393 #define S_RX_FORCE_ACK 28 1394 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1395 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1396 1397 #define S_RX_DACK_MODE 29 1398 #define M_RX_DACK_MODE 0x3 1399 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1400 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1401 1402 #define S_RX_DACK_CHANGE 31 1403 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1404 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1405 1406 struct cpl_rx_ddp_complete { 1407 RSS_HDR 1408 union opcode_tid ot; 1409 __be32 ddp_report; 1410 __be32 rcv_nxt; 1411 __be32 rsvd; 1412 }; 1413 1414 struct cpl_rx_data_ddp { 1415 RSS_HDR 1416 union opcode_tid ot; 1417 __be16 urg; 1418 __be16 len; 1419 __be32 seq; 1420 union { 1421 __be32 nxt_seq; 1422 __be32 ddp_report; 1423 } u; 1424 __be32 ulp_crc; 1425 __be32 ddpvld; 1426 }; 1427 1428 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1429 1430 struct cpl_rx_fcoe_ddp { 1431 RSS_HDR 1432 union opcode_tid ot; 1433 __be16 rsvd; 1434 __be16 len; 1435 __be32 seq; 1436 __be32 ddp_report; 1437 __be32 ulp_crc; 1438 __be32 ddpvld; 1439 }; 1440 1441 struct cpl_rx_data_dif { 1442 RSS_HDR 1443 union opcode_tid ot; 1444 __be16 ddp_len; 1445 __be16 msg_len; 1446 __be32 seq; 1447 union { 1448 __be32 nxt_seq; 1449 __be32 ddp_report; 1450 } u; 1451 __be32 err_vec; 1452 __be32 ddpvld; 1453 }; 1454 1455 struct cpl_rx_iscsi_dif { 1456 RSS_HDR 1457 union opcode_tid ot; 1458 __be16 ddp_len; 1459 __be16 msg_len; 1460 __be32 seq; 1461 union { 1462 __be32 nxt_seq; 1463 __be32 ddp_report; 1464 } u; 1465 __be32 ulp_crc; 1466 __be32 ddpvld; 1467 __u8 rsvd0[8]; 1468 __be32 err_vec; 1469 __u8 rsvd1[4]; 1470 }; 1471 1472 struct cpl_rx_fcoe_dif { 1473 RSS_HDR 1474 union opcode_tid ot; 1475 __be16 ddp_len; 1476 __be16 msg_len; 1477 __be32 seq; 1478 __be32 ddp_report; 1479 __be32 err_vec; 1480 __be32 ddpvld; 1481 }; 1482 1483 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1484 #define S_DDP_VALID 15 1485 #define M_DDP_VALID 0x1FFFF 1486 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1487 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1488 1489 #define S_DDP_PPOD_MISMATCH 15 1490 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1491 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1492 1493 #define S_DDP_PDU 16 1494 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1495 #define F_DDP_PDU V_DDP_PDU(1U) 1496 1497 #define S_DDP_LLIMIT_ERR 17 1498 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1499 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1500 1501 #define S_DDP_PPOD_PARITY_ERR 18 1502 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1503 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1504 1505 #define S_DDP_PADDING_ERR 19 1506 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1507 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1508 1509 #define S_DDP_HDRCRC_ERR 20 1510 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1511 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1512 1513 #define S_DDP_DATACRC_ERR 21 1514 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1515 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1516 1517 #define S_DDP_INVALID_TAG 22 1518 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1519 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1520 1521 #define S_DDP_ULIMIT_ERR 23 1522 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1523 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1524 1525 #define S_DDP_OFFSET_ERR 24 1526 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1527 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1528 1529 #define S_DDP_COLOR_ERR 25 1530 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1531 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1532 1533 #define S_DDP_TID_MISMATCH 26 1534 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1535 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1536 1537 #define S_DDP_INVALID_PPOD 27 1538 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1539 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1540 1541 #define S_DDP_ULP_MODE 28 1542 #define M_DDP_ULP_MODE 0xF 1543 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1544 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1545 1546 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1547 #define S_DDP_OFFSET 0 1548 #define M_DDP_OFFSET 0xFFFFFF 1549 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1550 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1551 1552 #define S_DDP_DACK_MODE 24 1553 #define M_DDP_DACK_MODE 0x3 1554 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1555 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1556 1557 #define S_DDP_BUF_IDX 26 1558 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1559 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1560 1561 #define S_DDP_URG 27 1562 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1563 #define F_DDP_URG V_DDP_URG(1U) 1564 1565 #define S_DDP_PSH 28 1566 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1567 #define F_DDP_PSH V_DDP_PSH(1U) 1568 1569 #define S_DDP_BUF_COMPLETE 29 1570 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1571 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1572 1573 #define S_DDP_BUF_TIMED_OUT 30 1574 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1575 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1576 1577 #define S_DDP_INV 31 1578 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1579 #define F_DDP_INV V_DDP_INV(1U) 1580 1581 struct cpl_rx_pkt { 1582 RSS_HDR 1583 __u8 opcode; 1584 #if defined(__LITTLE_ENDIAN_BITFIELD) 1585 __u8 iff:4; 1586 __u8 csum_calc:1; 1587 __u8 ipmi_pkt:1; 1588 __u8 vlan_ex:1; 1589 __u8 ip_frag:1; 1590 #else 1591 __u8 ip_frag:1; 1592 __u8 vlan_ex:1; 1593 __u8 ipmi_pkt:1; 1594 __u8 csum_calc:1; 1595 __u8 iff:4; 1596 #endif 1597 __be16 csum; 1598 __be16 vlan; 1599 __be16 len; 1600 __be32 l2info; 1601 __be16 hdr_len; 1602 __be16 err_vec; 1603 }; 1604 1605 /* rx_pkt.l2info fields */ 1606 #define S_RX_ETHHDR_LEN 0 1607 #define M_RX_ETHHDR_LEN 0x1F 1608 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1609 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1610 1611 #define S_RX_T5_ETHHDR_LEN 0 1612 #define M_RX_T5_ETHHDR_LEN 0x3F 1613 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1614 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1615 1616 #define S_RX_PKTYPE 5 1617 #define M_RX_PKTYPE 0x7 1618 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1619 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1620 1621 #define S_RX_T5_DATYPE 6 1622 #define M_RX_T5_DATYPE 0x3 1623 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1624 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1625 1626 #define S_RX_MACIDX 8 1627 #define M_RX_MACIDX 0x1FF 1628 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1629 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1630 1631 #define S_RX_T5_PKTYPE 17 1632 #define M_RX_T5_PKTYPE 0x7 1633 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1634 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1635 1636 #define S_RX_DATYPE 18 1637 #define M_RX_DATYPE 0x3 1638 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1639 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1640 1641 #define S_RXF_PSH 20 1642 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1643 #define F_RXF_PSH V_RXF_PSH(1U) 1644 1645 #define S_RXF_SYN 21 1646 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1647 #define F_RXF_SYN V_RXF_SYN(1U) 1648 1649 #define S_RXF_UDP 22 1650 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1651 #define F_RXF_UDP V_RXF_UDP(1U) 1652 1653 #define S_RXF_TCP 23 1654 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1655 #define F_RXF_TCP V_RXF_TCP(1U) 1656 1657 #define S_RXF_IP 24 1658 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1659 #define F_RXF_IP V_RXF_IP(1U) 1660 1661 #define S_RXF_IP6 25 1662 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1663 #define F_RXF_IP6 V_RXF_IP6(1U) 1664 1665 #define S_RXF_SYN_COOKIE 26 1666 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1667 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1668 1669 #define S_RXF_FCOE 26 1670 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1671 #define F_RXF_FCOE V_RXF_FCOE(1U) 1672 1673 #define S_RXF_LRO 27 1674 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1675 #define F_RXF_LRO V_RXF_LRO(1U) 1676 1677 #define S_RX_CHAN 28 1678 #define M_RX_CHAN 0xF 1679 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1680 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1681 1682 /* rx_pkt.hdr_len fields */ 1683 #define S_RX_TCPHDR_LEN 0 1684 #define M_RX_TCPHDR_LEN 0x3F 1685 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1686 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1687 1688 #define S_RX_IPHDR_LEN 6 1689 #define M_RX_IPHDR_LEN 0x3FF 1690 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1691 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1692 1693 /* rx_pkt.err_vec fields */ 1694 #define S_RXERR_OR 0 1695 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1696 #define F_RXERR_OR V_RXERR_OR(1U) 1697 1698 #define S_RXERR_MAC 1 1699 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1700 #define F_RXERR_MAC V_RXERR_MAC(1U) 1701 1702 #define S_RXERR_IPVERS 2 1703 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1704 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1705 1706 #define S_RXERR_FRAG 3 1707 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1708 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1709 1710 #define S_RXERR_ATTACK 4 1711 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1712 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1713 1714 #define S_RXERR_ETHHDR_LEN 5 1715 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1716 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1717 1718 #define S_RXERR_IPHDR_LEN 6 1719 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1720 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1721 1722 #define S_RXERR_TCPHDR_LEN 7 1723 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1724 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1725 1726 #define S_RXERR_PKT_LEN 8 1727 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1728 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1729 1730 #define S_RXERR_TCP_OPT 9 1731 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1732 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1733 1734 #define S_RXERR_IPCSUM 12 1735 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1736 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1737 1738 #define S_RXERR_CSUM 13 1739 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1740 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1741 1742 #define S_RXERR_PING 14 1743 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1744 #define F_RXERR_PING V_RXERR_PING(1U) 1745 1746 struct cpl_trace_pkt { 1747 RSS_HDR 1748 __u8 opcode; 1749 __u8 intf; 1750 #if defined(__LITTLE_ENDIAN_BITFIELD) 1751 __u8 runt:4; 1752 __u8 filter_hit:4; 1753 __u8 :6; 1754 __u8 err:1; 1755 __u8 trunc:1; 1756 #else 1757 __u8 filter_hit:4; 1758 __u8 runt:4; 1759 __u8 trunc:1; 1760 __u8 err:1; 1761 __u8 :6; 1762 #endif 1763 __be16 rsvd; 1764 __be16 len; 1765 __be64 tstamp; 1766 }; 1767 1768 struct cpl_t5_trace_pkt { 1769 RSS_HDR 1770 __u8 opcode; 1771 __u8 intf; 1772 #if defined(__LITTLE_ENDIAN_BITFIELD) 1773 __u8 runt:4; 1774 __u8 filter_hit:4; 1775 __u8 :6; 1776 __u8 err:1; 1777 __u8 trunc:1; 1778 #else 1779 __u8 filter_hit:4; 1780 __u8 runt:4; 1781 __u8 trunc:1; 1782 __u8 err:1; 1783 __u8 :6; 1784 #endif 1785 __be16 rsvd; 1786 __be16 len; 1787 __be64 tstamp; 1788 __be64 rsvd1; 1789 }; 1790 1791 struct cpl_rte_delete_req { 1792 WR_HDR; 1793 union opcode_tid ot; 1794 __be32 params; 1795 }; 1796 1797 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1798 #define S_RTE_REQ_LUT_IX 8 1799 #define M_RTE_REQ_LUT_IX 0x7FF 1800 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1801 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1802 1803 #define S_RTE_REQ_LUT_BASE 19 1804 #define M_RTE_REQ_LUT_BASE 0x7FF 1805 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1806 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1807 1808 #define S_RTE_READ_REQ_SELECT 31 1809 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1810 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1811 1812 struct cpl_rte_delete_rpl { 1813 RSS_HDR 1814 union opcode_tid ot; 1815 __u8 status; 1816 __u8 rsvd[3]; 1817 }; 1818 1819 struct cpl_rte_write_req { 1820 WR_HDR; 1821 union opcode_tid ot; 1822 __u32 write_sel; 1823 __be32 lut_params; 1824 __be32 l2t_idx; 1825 __be32 netmask; 1826 __be32 faddr; 1827 }; 1828 1829 /* cpl_rte_write_req.write_sel fields */ 1830 #define S_RTE_WR_L2TIDX 31 1831 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1832 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1833 1834 #define S_RTE_WR_FADDR 30 1835 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1836 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1837 1838 /* cpl_rte_write_req.lut_params fields */ 1839 #define S_RTE_WR_LUT_IX 10 1840 #define M_RTE_WR_LUT_IX 0x7FF 1841 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1842 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1843 1844 #define S_RTE_WR_LUT_BASE 21 1845 #define M_RTE_WR_LUT_BASE 0x7FF 1846 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1847 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1848 1849 struct cpl_rte_write_rpl { 1850 RSS_HDR 1851 union opcode_tid ot; 1852 __u8 status; 1853 __u8 rsvd[3]; 1854 }; 1855 1856 struct cpl_rte_read_req { 1857 WR_HDR; 1858 union opcode_tid ot; 1859 __be32 params; 1860 }; 1861 1862 struct cpl_rte_read_rpl { 1863 RSS_HDR 1864 union opcode_tid ot; 1865 __u8 status; 1866 __u8 rsvd; 1867 __be16 l2t_idx; 1868 #if defined(__LITTLE_ENDIAN_BITFIELD) 1869 __u32 :30; 1870 __u32 select:1; 1871 #else 1872 __u32 select:1; 1873 __u32 :30; 1874 #endif 1875 __be32 addr; 1876 }; 1877 1878 struct cpl_l2t_write_req { 1879 WR_HDR; 1880 union opcode_tid ot; 1881 __be16 params; 1882 __be16 l2t_idx; 1883 __be16 vlan; 1884 __u8 dst_mac[6]; 1885 }; 1886 1887 /* cpl_l2t_write_req.params fields */ 1888 #define S_L2T_W_INFO 2 1889 #define M_L2T_W_INFO 0x3F 1890 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1891 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1892 1893 #define S_L2T_W_PORT 8 1894 #define M_L2T_W_PORT 0xF 1895 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1896 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1897 1898 #define S_L2T_W_NOREPLY 15 1899 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1900 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1901 1902 struct cpl_l2t_write_rpl { 1903 RSS_HDR 1904 union opcode_tid ot; 1905 __u8 status; 1906 __u8 rsvd[3]; 1907 }; 1908 1909 struct cpl_l2t_read_req { 1910 WR_HDR; 1911 union opcode_tid ot; 1912 __be32 l2t_idx; 1913 }; 1914 1915 struct cpl_l2t_read_rpl { 1916 RSS_HDR 1917 union opcode_tid ot; 1918 __u8 status; 1919 #if defined(__LITTLE_ENDIAN_BITFIELD) 1920 __u8 :4; 1921 __u8 iff:4; 1922 #else 1923 __u8 iff:4; 1924 __u8 :4; 1925 #endif 1926 __be16 vlan; 1927 __be16 info; 1928 __u8 dst_mac[6]; 1929 }; 1930 1931 struct cpl_smt_write_req { 1932 WR_HDR; 1933 union opcode_tid ot; 1934 __be32 params; 1935 __be16 pfvf1; 1936 __u8 src_mac1[6]; 1937 __be16 pfvf0; 1938 __u8 src_mac0[6]; 1939 }; 1940 1941 struct cpl_smt_write_rpl { 1942 RSS_HDR 1943 union opcode_tid ot; 1944 __u8 status; 1945 __u8 rsvd[3]; 1946 }; 1947 1948 struct cpl_smt_read_req { 1949 WR_HDR; 1950 union opcode_tid ot; 1951 __be32 params; 1952 }; 1953 1954 struct cpl_smt_read_rpl { 1955 RSS_HDR 1956 union opcode_tid ot; 1957 __u8 status; 1958 __u8 ovlan_idx; 1959 __be16 rsvd; 1960 __be16 pfvf1; 1961 __u8 src_mac1[6]; 1962 __be16 pfvf0; 1963 __u8 src_mac0[6]; 1964 }; 1965 1966 /* cpl_smt_{read,write}_req.params fields */ 1967 #define S_SMTW_OVLAN_IDX 16 1968 #define M_SMTW_OVLAN_IDX 0xF 1969 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1970 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1971 1972 #define S_SMTW_IDX 20 1973 #define M_SMTW_IDX 0x7F 1974 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 1975 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 1976 1977 #define S_SMTW_NORPL 31 1978 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 1979 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 1980 1981 /* cpl_smt_{read,write}_req.pfvf? fields */ 1982 #define S_SMTW_VF 0 1983 #define M_SMTW_VF 0xFF 1984 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 1985 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 1986 1987 #define S_SMTW_PF 8 1988 #define M_SMTW_PF 0x7 1989 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 1990 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 1991 1992 #define S_SMTW_VF_VLD 11 1993 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 1994 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 1995 1996 struct cpl_tag_write_req { 1997 WR_HDR; 1998 union opcode_tid ot; 1999 __be32 params; 2000 __be64 tag_val; 2001 }; 2002 2003 struct cpl_tag_write_rpl { 2004 RSS_HDR 2005 union opcode_tid ot; 2006 __u8 status; 2007 __u8 rsvd[2]; 2008 __u8 idx; 2009 }; 2010 2011 struct cpl_tag_read_req { 2012 WR_HDR; 2013 union opcode_tid ot; 2014 __be32 params; 2015 }; 2016 2017 struct cpl_tag_read_rpl { 2018 RSS_HDR 2019 union opcode_tid ot; 2020 __u8 status; 2021 #if defined(__LITTLE_ENDIAN_BITFIELD) 2022 __u8 :4; 2023 __u8 tag_len:1; 2024 __u8 :2; 2025 __u8 ins_enable:1; 2026 #else 2027 __u8 ins_enable:1; 2028 __u8 :2; 2029 __u8 tag_len:1; 2030 __u8 :4; 2031 #endif 2032 __u8 rsvd; 2033 __u8 tag_idx; 2034 __be64 tag_val; 2035 }; 2036 2037 /* cpl_tag{read,write}_req.params fields */ 2038 #define S_TAGW_IDX 0 2039 #define M_TAGW_IDX 0x7F 2040 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2041 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2042 2043 #define S_TAGW_LEN 20 2044 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2045 #define F_TAGW_LEN V_TAGW_LEN(1U) 2046 2047 #define S_TAGW_INS_ENABLE 23 2048 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2049 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2050 2051 #define S_TAGW_NORPL 31 2052 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2053 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2054 2055 struct cpl_barrier { 2056 WR_HDR; 2057 __u8 opcode; 2058 __u8 chan_map; 2059 __be16 rsvd0; 2060 __be32 rsvd1; 2061 }; 2062 2063 /* cpl_barrier.chan_map fields */ 2064 #define S_CHAN_MAP 4 2065 #define M_CHAN_MAP 0xF 2066 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2067 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2068 2069 struct cpl_error { 2070 RSS_HDR 2071 union opcode_tid ot; 2072 __be32 error; 2073 }; 2074 2075 struct cpl_hit_notify { 2076 RSS_HDR 2077 union opcode_tid ot; 2078 __be32 rsvd; 2079 __be32 info; 2080 __be32 reason; 2081 }; 2082 2083 struct cpl_pkt_notify { 2084 RSS_HDR 2085 union opcode_tid ot; 2086 __be16 rsvd; 2087 __be16 len; 2088 __be32 info; 2089 __be32 reason; 2090 }; 2091 2092 /* cpl_{hit,pkt}_notify.info fields */ 2093 #define S_NTFY_MAC_IDX 0 2094 #define M_NTFY_MAC_IDX 0x1FF 2095 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2096 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2097 2098 #define S_NTFY_INTF 10 2099 #define M_NTFY_INTF 0xF 2100 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2101 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2102 2103 #define S_NTFY_TCPHDR_LEN 14 2104 #define M_NTFY_TCPHDR_LEN 0xF 2105 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2106 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2107 2108 #define S_NTFY_IPHDR_LEN 18 2109 #define M_NTFY_IPHDR_LEN 0x1FF 2110 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2111 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2112 2113 #define S_NTFY_ETHHDR_LEN 27 2114 #define M_NTFY_ETHHDR_LEN 0x1F 2115 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2116 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2117 2118 #define S_NTFY_T5_IPHDR_LEN 18 2119 #define M_NTFY_T5_IPHDR_LEN 0xFF 2120 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2121 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2122 2123 #define S_NTFY_T5_ETHHDR_LEN 26 2124 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2125 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2126 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2127 2128 struct cpl_rdma_terminate { 2129 RSS_HDR 2130 union opcode_tid ot; 2131 __be16 rsvd; 2132 __be16 len; 2133 }; 2134 2135 struct cpl_set_le_req { 2136 WR_HDR; 2137 union opcode_tid ot; 2138 __be16 reply_ctrl; 2139 __be16 params; 2140 __be64 mask_hi; 2141 __be64 mask_lo; 2142 __be64 val_hi; 2143 __be64 val_lo; 2144 }; 2145 2146 /* cpl_set_le_req.reply_ctrl additional fields */ 2147 #define S_LE_REQ_IP6 13 2148 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2149 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2150 2151 /* cpl_set_le_req.params fields */ 2152 #define S_LE_CHAN 0 2153 #define M_LE_CHAN 0x3 2154 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2155 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2156 2157 #define S_LE_OFFSET 5 2158 #define M_LE_OFFSET 0x7 2159 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2160 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2161 2162 #define S_LE_MORE 8 2163 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2164 #define F_LE_MORE V_LE_MORE(1U) 2165 2166 #define S_LE_REQSIZE 9 2167 #define M_LE_REQSIZE 0x7 2168 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2169 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2170 2171 #define S_LE_REQCMD 12 2172 #define M_LE_REQCMD 0xF 2173 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2174 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2175 2176 struct cpl_set_le_rpl { 2177 RSS_HDR 2178 union opcode_tid ot; 2179 __u8 chan; 2180 __u8 info; 2181 __be16 len; 2182 }; 2183 2184 /* cpl_set_le_rpl.info fields */ 2185 #define S_LE_RSPCMD 0 2186 #define M_LE_RSPCMD 0xF 2187 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2188 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2189 2190 #define S_LE_RSPSIZE 4 2191 #define M_LE_RSPSIZE 0x7 2192 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2193 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2194 2195 #define S_LE_RSPTYPE 7 2196 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2197 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2198 2199 struct cpl_sge_egr_update { 2200 RSS_HDR 2201 __be32 opcode_qid; 2202 __be16 cidx; 2203 __be16 pidx; 2204 }; 2205 2206 /* cpl_sge_egr_update.ot fields */ 2207 #define S_EGR_QID 0 2208 #define M_EGR_QID 0x1FFFF 2209 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2210 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2211 2212 struct cpl_fw2_pld { 2213 RSS_HDR 2214 u8 opcode; 2215 u8 rsvd[5]; 2216 __be16 len; 2217 }; 2218 2219 struct cpl_fw4_pld { 2220 RSS_HDR 2221 u8 opcode; 2222 u8 rsvd0[3]; 2223 u8 type; 2224 u8 rsvd1; 2225 __be16 len; 2226 __be64 data; 2227 __be64 rsvd2; 2228 }; 2229 2230 struct cpl_fw6_pld { 2231 RSS_HDR 2232 u8 opcode; 2233 u8 rsvd[5]; 2234 __be16 len; 2235 __be64 data[4]; 2236 }; 2237 2238 struct cpl_fw2_msg { 2239 RSS_HDR 2240 union opcode_info oi; 2241 }; 2242 2243 struct cpl_fw4_msg { 2244 RSS_HDR 2245 u8 opcode; 2246 u8 type; 2247 __be16 rsvd0; 2248 __be32 rsvd1; 2249 __be64 data[2]; 2250 }; 2251 2252 struct cpl_fw4_ack { 2253 RSS_HDR 2254 union opcode_tid ot; 2255 u8 credits; 2256 u8 rsvd0[2]; 2257 u8 flags; 2258 __be32 snd_nxt; 2259 __be32 snd_una; 2260 __be64 rsvd1; 2261 }; 2262 2263 enum { 2264 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2265 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2266 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2267 }; 2268 2269 struct cpl_fw6_msg { 2270 RSS_HDR 2271 u8 opcode; 2272 u8 type; 2273 __be16 rsvd0; 2274 __be32 rsvd1; 2275 __be64 data[4]; 2276 }; 2277 2278 /* cpl_fw6_msg.type values */ 2279 enum { 2280 FW6_TYPE_CMD_RPL = 0, 2281 FW6_TYPE_WR_RPL = 1, 2282 FW6_TYPE_CQE = 2, 2283 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2284 }; 2285 2286 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2287 __u64 cookie; 2288 __be32 tid; /* or atid in case of active failure */ 2289 __u8 t_state; 2290 __u8 retval; 2291 __u8 rsvd[2]; 2292 }; 2293 2294 /* ULP_TX opcodes */ 2295 enum { 2296 ULP_TX_MEM_READ = 2, 2297 ULP_TX_MEM_WRITE = 3, 2298 ULP_TX_PKT = 4 2299 }; 2300 2301 enum { 2302 ULP_TX_SC_NOOP = 0x80, 2303 ULP_TX_SC_IMM = 0x81, 2304 ULP_TX_SC_DSGL = 0x82, 2305 ULP_TX_SC_ISGL = 0x83 2306 }; 2307 2308 #define S_ULPTX_CMD 24 2309 #define M_ULPTX_CMD 0xFF 2310 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2311 2312 #define S_ULPTX_LEN16 0 2313 #define M_ULPTX_LEN16 0xFF 2314 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2315 2316 #define S_ULP_TX_SC_MORE 23 2317 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2318 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2319 2320 struct ulptx_sge_pair { 2321 __be32 len[2]; 2322 __be64 addr[2]; 2323 }; 2324 2325 struct ulptx_sgl { 2326 __be32 cmd_nsge; 2327 __be32 len0; 2328 __be64 addr0; 2329 #if !(defined C99_NOT_SUPPORTED) 2330 struct ulptx_sge_pair sge[0]; 2331 #endif 2332 }; 2333 2334 struct ulptx_isge { 2335 __be32 stag; 2336 __be32 len; 2337 __be64 target_ofst; 2338 }; 2339 2340 struct ulptx_isgl { 2341 __be32 cmd_nisge; 2342 __be32 rsvd; 2343 #if !(defined C99_NOT_SUPPORTED) 2344 struct ulptx_isge sge[0]; 2345 #endif 2346 }; 2347 2348 struct ulptx_idata { 2349 __be32 cmd_more; 2350 __be32 len; 2351 }; 2352 2353 #define S_ULPTX_NSGE 0 2354 #define M_ULPTX_NSGE 0xFFFF 2355 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2356 2357 struct ulp_mem_io { 2358 WR_HDR; 2359 __be32 cmd; 2360 __be32 len16; /* command length */ 2361 __be32 dlen; /* data length in 32-byte units */ 2362 __be32 lock_addr; 2363 }; 2364 2365 /* additional ulp_mem_io.cmd fields */ 2366 #define S_ULP_MEMIO_ORDER 23 2367 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2368 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2369 2370 /* ulp_mem_io.lock_addr fields */ 2371 #define S_ULP_MEMIO_ADDR 0 2372 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2373 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2374 2375 #define S_ULP_MEMIO_LOCK 31 2376 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2377 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2378 2379 /* ulp_mem_io.dlen fields */ 2380 #define S_ULP_MEMIO_DATA_LEN 0 2381 #define M_ULP_MEMIO_DATA_LEN 0x1F 2382 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2383 2384 struct ulp_txpkt { 2385 __be32 cmd_dest; 2386 __be32 len; 2387 }; 2388 2389 /* ulp_txpkt.cmd_dest fields */ 2390 #define S_ULP_TXPKT_DEST 16 2391 #define M_ULP_TXPKT_DEST 0x3 2392 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2393 2394 #define S_ULP_TXPKT_FID 4 2395 #define M_ULP_TXPKT_FID 0x7ff 2396 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2397 2398 #define S_ULP_TXPKT_RO 3 2399 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2400 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2401 2402 #endif /* T4_MSG_H */ 2403