1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_PKT_ISO = 0x1F, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_URG_PKT = 0x29, 71 CPL_TAG_WRITE_RPL = 0x2A, 72 CPL_ABORT_REQ_RSS = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_ABORT_RPL_RSS = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_RX_PHYS_ADDR = 0x30, 79 CPL_PCMD_READ_RPL = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 CPL_SET_TCB_RPL = 0x3A, 89 CPL_RX_PKT = 0x3B, 90 CPL_TAG_READ_RPL = 0x3C, 91 CPL_HIT_NOTIFY = 0x3D, 92 CPL_PKT_NOTIFY = 0x3E, 93 CPL_RX_DDP_COMPLETE = 0x3F, 94 95 CPL_ACT_ESTABLISH = 0x40, 96 CPL_PASS_ESTABLISH = 0x41, 97 CPL_RX_DATA_DDP = 0x42, 98 CPL_SMT_READ_RPL = 0x43, 99 CPL_PASS_ACCEPT_REQ = 0x44, 100 CPL_RX2TX_PKT = 0x45, 101 CPL_RX_FCOE_DDP = 0x46, 102 CPL_FCOE_HDR = 0x47, 103 CPL_T5_TRACE_PKT = 0x48, 104 CPL_RX_ISCSI_DDP = 0x49, 105 CPL_RX_FCOE_DIF = 0x4A, 106 CPL_RX_DATA_DIF = 0x4B, 107 108 CPL_RDMA_READ_REQ = 0x60, 109 CPL_RX_ISCSI_DIF = 0x60, 110 111 CPL_SET_LE_REQ = 0x80, 112 CPL_PASS_OPEN_REQ6 = 0x81, 113 CPL_ACT_OPEN_REQ6 = 0x83, 114 115 CPL_RDMA_TERMINATE = 0xA2, 116 CPL_RDMA_WRITE = 0xA4, 117 CPL_SGE_EGR_UPDATE = 0xA5, 118 CPL_SET_LE_RPL = 0xA6, 119 CPL_FW2_MSG = 0xA7, 120 CPL_FW2_PLD = 0xA8, 121 CPL_T5_RDMA_READ_REQ = 0xA9, 122 CPL_RDMA_ATOMIC_REQ = 0xAA, 123 CPL_RDMA_ATOMIC_RPL = 0xAB, 124 CPL_RDMA_IMM_DATA = 0xAC, 125 CPL_RDMA_IMM_DATA_SE = 0xAD, 126 127 CPL_TRACE_PKT = 0xB0, 128 CPL_RX2TX_DATA = 0xB1, 129 CPL_ISCSI_DATA = 0xB2, 130 CPL_FCOE_DATA = 0xB3, 131 132 CPL_FW4_MSG = 0xC0, 133 CPL_FW4_PLD = 0xC1, 134 CPL_FW4_ACK = 0xC3, 135 136 CPL_FW6_MSG = 0xE0, 137 CPL_FW6_PLD = 0xE1, 138 CPL_TX_PKT_LSO = 0xED, 139 CPL_TX_PKT_XT = 0xEE, 140 141 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 142 }; 143 144 enum CPL_error { 145 CPL_ERR_NONE = 0, 146 CPL_ERR_TCAM_PARITY = 1, 147 CPL_ERR_TCAM_FULL = 3, 148 CPL_ERR_BAD_LENGTH = 15, 149 CPL_ERR_BAD_ROUTE = 18, 150 CPL_ERR_CONN_RESET = 20, 151 CPL_ERR_CONN_EXIST_SYNRECV = 21, 152 CPL_ERR_CONN_EXIST = 22, 153 CPL_ERR_ARP_MISS = 23, 154 CPL_ERR_BAD_SYN = 24, 155 CPL_ERR_CONN_TIMEDOUT = 30, 156 CPL_ERR_XMIT_TIMEDOUT = 31, 157 CPL_ERR_PERSIST_TIMEDOUT = 32, 158 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 159 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 160 CPL_ERR_RTX_NEG_ADVICE = 35, 161 CPL_ERR_PERSIST_NEG_ADVICE = 36, 162 CPL_ERR_ABORT_FAILED = 42, 163 CPL_ERR_IWARP_FLM = 50, 164 }; 165 166 enum { 167 CPL_CONN_POLICY_AUTO = 0, 168 CPL_CONN_POLICY_ASK = 1, 169 CPL_CONN_POLICY_FILTER = 2, 170 CPL_CONN_POLICY_DENY = 3 171 }; 172 173 enum { 174 ULP_MODE_NONE = 0, 175 ULP_MODE_ISCSI = 2, 176 ULP_MODE_RDMA = 4, 177 ULP_MODE_TCPDDP = 5, 178 ULP_MODE_FCOE = 6, 179 }; 180 181 enum { 182 ULP_CRC_HEADER = 1 << 0, 183 ULP_CRC_DATA = 1 << 1 184 }; 185 186 enum { 187 CPL_PASS_OPEN_ACCEPT, 188 CPL_PASS_OPEN_REJECT, 189 CPL_PASS_OPEN_ACCEPT_TNL 190 }; 191 192 enum { 193 CPL_ABORT_SEND_RST = 0, 194 CPL_ABORT_NO_RST, 195 }; 196 197 enum { /* TX_PKT_XT checksum types */ 198 TX_CSUM_TCP = 0, 199 TX_CSUM_UDP = 1, 200 TX_CSUM_CRC16 = 4, 201 TX_CSUM_CRC32 = 5, 202 TX_CSUM_CRC32C = 6, 203 TX_CSUM_FCOE = 7, 204 TX_CSUM_TCPIP = 8, 205 TX_CSUM_UDPIP = 9, 206 TX_CSUM_TCPIP6 = 10, 207 TX_CSUM_UDPIP6 = 11, 208 TX_CSUM_IP = 12, 209 }; 210 211 enum { /* packet type in CPL_RX_PKT */ 212 PKTYPE_XACT_UCAST = 0, 213 PKTYPE_HASH_UCAST = 1, 214 PKTYPE_XACT_MCAST = 2, 215 PKTYPE_HASH_MCAST = 3, 216 PKTYPE_PROMISC = 4, 217 PKTYPE_HPROMISC = 5, 218 PKTYPE_BCAST = 6 219 }; 220 221 enum { /* DMAC type in CPL_RX_PKT */ 222 DATYPE_UCAST, 223 DATYPE_MCAST, 224 DATYPE_BCAST 225 }; 226 227 enum { /* TCP congestion control algorithms */ 228 CONG_ALG_RENO, 229 CONG_ALG_TAHOE, 230 CONG_ALG_NEWRENO, 231 CONG_ALG_HIGHSPEED 232 }; 233 234 enum { /* RSS hash type */ 235 RSS_HASH_NONE = 0, /* no hash computed */ 236 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 237 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 238 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 239 }; 240 241 enum { /* LE commands */ 242 LE_CMD_READ = 0x4, 243 LE_CMD_WRITE = 0xb 244 }; 245 246 enum { /* LE request size */ 247 LE_SZ_NONE = 0, 248 LE_SZ_33 = 1, 249 LE_SZ_66 = 2, 250 LE_SZ_132 = 3, 251 LE_SZ_264 = 4, 252 LE_SZ_528 = 5 253 }; 254 255 union opcode_tid { 256 __be32 opcode_tid; 257 __u8 opcode; 258 }; 259 260 #define S_CPL_OPCODE 24 261 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 262 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 263 #define G_TID(x) ((x) & 0xFFFFFF) 264 265 /* tid is assumed to be 24-bits */ 266 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 267 268 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 269 270 /* extract the TID from a CPL command */ 271 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 272 273 /* partitioning of TID fields that also carry a queue id */ 274 #define S_TID_TID 0 275 #define M_TID_TID 0x3fff 276 #define V_TID_TID(x) ((x) << S_TID_TID) 277 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 278 279 #define S_TID_QID 14 280 #define M_TID_QID 0x3ff 281 #define V_TID_QID(x) ((x) << S_TID_QID) 282 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 283 284 union opcode_info { 285 __be64 opcode_info; 286 __u8 opcode; 287 }; 288 289 struct tcp_options { 290 __be16 mss; 291 __u8 wsf; 292 #if defined(__LITTLE_ENDIAN_BITFIELD) 293 __u8 :4; 294 __u8 unknown:1; 295 __u8 ecn:1; 296 __u8 sack:1; 297 __u8 tstamp:1; 298 #else 299 __u8 tstamp:1; 300 __u8 sack:1; 301 __u8 ecn:1; 302 __u8 unknown:1; 303 __u8 :4; 304 #endif 305 }; 306 307 struct rss_header { 308 __u8 opcode; 309 #if defined(__LITTLE_ENDIAN_BITFIELD) 310 __u8 channel:2; 311 __u8 filter_hit:1; 312 __u8 filter_tid:1; 313 __u8 hash_type:2; 314 __u8 ipv6:1; 315 __u8 send2fw:1; 316 #else 317 __u8 send2fw:1; 318 __u8 ipv6:1; 319 __u8 hash_type:2; 320 __u8 filter_tid:1; 321 __u8 filter_hit:1; 322 __u8 channel:2; 323 #endif 324 __be16 qid; 325 __be32 hash_val; 326 }; 327 328 #define S_HASHTYPE 20 329 #define M_HASHTYPE 0x3 330 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 331 332 #define S_QNUM 0 333 #define M_QNUM 0xFFFF 334 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 335 336 #ifndef CHELSIO_FW 337 struct work_request_hdr { 338 __be32 wr_hi; 339 __be32 wr_mid; 340 __be64 wr_lo; 341 }; 342 343 /* wr_mid fields */ 344 #define S_WR_LEN16 0 345 #define M_WR_LEN16 0xFF 346 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 347 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 348 349 /* wr_hi fields */ 350 #define S_WR_OP 24 351 #define M_WR_OP 0xFF 352 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 353 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 354 355 # define WR_HDR struct work_request_hdr wr 356 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 357 # define RSS_HDR 358 #else 359 # define WR_HDR 360 # define WR_HDR_SIZE 0 361 # define RSS_HDR struct rss_header rss_hdr; 362 #endif 363 364 /* option 0 fields */ 365 #define S_ACCEPT_MODE 0 366 #define M_ACCEPT_MODE 0x3 367 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 368 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 369 370 #define S_TX_CHAN 2 371 #define M_TX_CHAN 0x3 372 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 373 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 374 375 #define S_NO_CONG 4 376 #define V_NO_CONG(x) ((x) << S_NO_CONG) 377 #define F_NO_CONG V_NO_CONG(1U) 378 379 #define S_DELACK 5 380 #define V_DELACK(x) ((x) << S_DELACK) 381 #define F_DELACK V_DELACK(1U) 382 383 #define S_INJECT_TIMER 6 384 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 385 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 386 387 #define S_NON_OFFLOAD 7 388 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 389 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 390 391 #define S_ULP_MODE 8 392 #define M_ULP_MODE 0xF 393 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 394 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 395 396 #define S_RCV_BUFSIZ 12 397 #define M_RCV_BUFSIZ 0x3FFU 398 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 399 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 400 401 #define S_DSCP 22 402 #define M_DSCP 0x3F 403 #define V_DSCP(x) ((x) << S_DSCP) 404 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 405 406 #define S_SMAC_SEL 28 407 #define M_SMAC_SEL 0xFF 408 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 409 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 410 411 #define S_L2T_IDX 36 412 #define M_L2T_IDX 0xFFF 413 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 414 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 415 416 #define S_TCAM_BYPASS 48 417 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 418 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 419 420 #define S_NAGLE 49 421 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 422 #define F_NAGLE V_NAGLE(1ULL) 423 424 #define S_WND_SCALE 50 425 #define M_WND_SCALE 0xF 426 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 427 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 428 429 #define S_KEEP_ALIVE 54 430 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 431 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 432 433 #define S_MAX_RT 55 434 #define M_MAX_RT 0xF 435 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 436 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 437 438 #define S_MAX_RT_OVERRIDE 59 439 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 440 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 441 442 #define S_MSS_IDX 60 443 #define M_MSS_IDX 0xF 444 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 445 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 446 447 /* option 1 fields */ 448 #define S_SYN_RSS_ENABLE 0 449 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 450 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 451 452 #define S_SYN_RSS_USE_HASH 1 453 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 454 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 455 456 #define S_SYN_RSS_QUEUE 2 457 #define M_SYN_RSS_QUEUE 0x3FF 458 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 459 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 460 461 #define S_LISTEN_INTF 12 462 #define M_LISTEN_INTF 0xFF 463 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 464 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 465 466 #define S_LISTEN_FILTER 20 467 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 468 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 469 470 #define S_SYN_DEFENSE 21 471 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 472 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 473 474 #define S_CONN_POLICY 22 475 #define M_CONN_POLICY 0x3 476 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 477 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 478 479 /* option 2 fields */ 480 #define S_RSS_QUEUE 0 481 #define M_RSS_QUEUE 0x3FF 482 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 483 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 484 485 #define S_RSS_QUEUE_VALID 10 486 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 487 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 488 489 #define S_RX_COALESCE_VALID 11 490 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 491 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 492 493 #define S_RX_COALESCE 12 494 #define M_RX_COALESCE 0x3 495 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 496 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 497 498 #define S_CONG_CNTRL 14 499 #define M_CONG_CNTRL 0x3 500 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 501 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 502 503 #define S_PACE 16 504 #define M_PACE 0x3 505 #define V_PACE(x) ((x) << S_PACE) 506 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 507 508 #define S_CONG_CNTRL_VALID 18 509 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 510 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 511 512 #define S_PACE_VALID 19 513 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 514 #define F_PACE_VALID V_PACE_VALID(1U) 515 516 #define S_RX_FC_DISABLE 20 517 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 518 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 519 520 #define S_RX_FC_DDP 21 521 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 522 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 523 524 #define S_RX_FC_VALID 22 525 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 526 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 527 528 #define S_TX_QUEUE 23 529 #define M_TX_QUEUE 0x7 530 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 531 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 532 533 #define S_RX_CHANNEL 26 534 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 535 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 536 537 #define S_CCTRL_ECN 27 538 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 539 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 540 541 #define S_WND_SCALE_EN 28 542 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 543 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 544 545 #define S_TSTAMPS_EN 29 546 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 547 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 548 549 #define S_SACK_EN 30 550 #define V_SACK_EN(x) ((x) << S_SACK_EN) 551 #define F_SACK_EN V_SACK_EN(1U) 552 553 struct cpl_pass_open_req { 554 WR_HDR; 555 union opcode_tid ot; 556 __be16 local_port; 557 __be16 peer_port; 558 __be32 local_ip; 559 __be32 peer_ip; 560 __be64 opt0; 561 __be64 opt1; 562 }; 563 564 struct cpl_pass_open_req6 { 565 WR_HDR; 566 union opcode_tid ot; 567 __be16 local_port; 568 __be16 peer_port; 569 __be64 local_ip_hi; 570 __be64 local_ip_lo; 571 __be64 peer_ip_hi; 572 __be64 peer_ip_lo; 573 __be64 opt0; 574 __be64 opt1; 575 }; 576 577 struct cpl_pass_open_rpl { 578 RSS_HDR 579 union opcode_tid ot; 580 __u8 rsvd[3]; 581 __u8 status; 582 }; 583 584 struct cpl_pass_establish { 585 RSS_HDR 586 union opcode_tid ot; 587 __be32 rsvd; 588 __be32 tos_stid; 589 __be16 mac_idx; 590 __be16 tcp_opt; 591 __be32 snd_isn; 592 __be32 rcv_isn; 593 }; 594 595 /* cpl_pass_establish.tos_stid fields */ 596 #define S_PASS_OPEN_TID 0 597 #define M_PASS_OPEN_TID 0xFFFFFF 598 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 599 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 600 601 #define S_PASS_OPEN_TOS 24 602 #define M_PASS_OPEN_TOS 0xFF 603 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 604 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 605 606 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 607 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 608 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 609 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 610 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 611 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 612 613 struct cpl_pass_accept_req { 614 RSS_HDR 615 union opcode_tid ot; 616 __be16 rsvd; 617 __be16 len; 618 __be32 hdr_len; 619 __be16 vlan; 620 __be16 l2info; 621 __be32 tos_stid; 622 struct tcp_options tcpopt; 623 }; 624 625 /* cpl_pass_accept_req.hdr_len fields */ 626 #define S_SYN_RX_CHAN 0 627 #define M_SYN_RX_CHAN 0xF 628 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 629 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 630 631 #define S_TCP_HDR_LEN 10 632 #define M_TCP_HDR_LEN 0x3F 633 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 634 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 635 636 #define S_IP_HDR_LEN 16 637 #define M_IP_HDR_LEN 0x3FF 638 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 639 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 640 641 #define S_ETH_HDR_LEN 26 642 #define M_ETH_HDR_LEN 0x3F 643 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 644 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 645 646 /* cpl_pass_accept_req.l2info fields */ 647 #define S_SYN_MAC_IDX 0 648 #define M_SYN_MAC_IDX 0x1FF 649 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 650 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 651 652 #define S_SYN_XACT_MATCH 9 653 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 654 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 655 656 #define S_SYN_INTF 12 657 #define M_SYN_INTF 0xF 658 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 659 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 660 661 struct cpl_pass_accept_rpl { 662 WR_HDR; 663 union opcode_tid ot; 664 __be32 opt2; 665 __be64 opt0; 666 }; 667 668 struct cpl_act_open_req { 669 WR_HDR; 670 union opcode_tid ot; 671 __be16 local_port; 672 __be16 peer_port; 673 __be32 local_ip; 674 __be32 peer_ip; 675 __be64 opt0; 676 __be32 params; 677 __be32 opt2; 678 }; 679 680 struct cpl_t5_act_open_req { 681 WR_HDR; 682 union opcode_tid ot; 683 __be16 local_port; 684 __be16 peer_port; 685 __be32 local_ip; 686 __be32 peer_ip; 687 __be64 opt0; 688 __be32 rsvd; 689 __be32 opt2; 690 __be64 params; 691 }; 692 693 struct cpl_act_open_req6 { 694 WR_HDR; 695 union opcode_tid ot; 696 __be16 local_port; 697 __be16 peer_port; 698 __be64 local_ip_hi; 699 __be64 local_ip_lo; 700 __be64 peer_ip_hi; 701 __be64 peer_ip_lo; 702 __be64 opt0; 703 __be32 params; 704 __be32 opt2; 705 }; 706 707 struct cpl_t5_act_open_req6 { 708 WR_HDR; 709 union opcode_tid ot; 710 __be16 local_port; 711 __be16 peer_port; 712 __be64 local_ip_hi; 713 __be64 local_ip_lo; 714 __be64 peer_ip_hi; 715 __be64 peer_ip_lo; 716 __be64 opt0; 717 __be32 rsvd; 718 __be32 opt2; 719 __be64 params; 720 }; 721 722 struct cpl_act_open_rpl { 723 RSS_HDR 724 union opcode_tid ot; 725 __be32 atid_status; 726 }; 727 728 /* cpl_act_open_rpl.atid_status fields */ 729 #define S_AOPEN_STATUS 0 730 #define M_AOPEN_STATUS 0xFF 731 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 732 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 733 734 #define S_AOPEN_ATID 8 735 #define M_AOPEN_ATID 0xFFFFFF 736 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 737 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 738 739 struct cpl_act_establish { 740 RSS_HDR 741 union opcode_tid ot; 742 __be32 rsvd; 743 __be32 tos_atid; 744 __be16 mac_idx; 745 __be16 tcp_opt; 746 __be32 snd_isn; 747 __be32 rcv_isn; 748 }; 749 750 struct cpl_get_tcb { 751 WR_HDR; 752 union opcode_tid ot; 753 __be16 reply_ctrl; 754 __be16 cookie; 755 }; 756 757 /* cpl_get_tcb.reply_ctrl fields */ 758 #define S_QUEUENO 0 759 #define M_QUEUENO 0x3FF 760 #define V_QUEUENO(x) ((x) << S_QUEUENO) 761 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 762 763 #define S_REPLY_CHAN 14 764 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 765 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 766 767 #define S_NO_REPLY 15 768 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 769 #define F_NO_REPLY V_NO_REPLY(1U) 770 771 struct cpl_get_tcb_rpl { 772 RSS_HDR 773 union opcode_tid ot; 774 __u8 cookie; 775 __u8 status; 776 __be16 len; 777 }; 778 779 struct cpl_set_tcb { 780 WR_HDR; 781 union opcode_tid ot; 782 __be16 reply_ctrl; 783 __be16 cookie; 784 }; 785 786 struct cpl_set_tcb_field { 787 WR_HDR; 788 union opcode_tid ot; 789 __be16 reply_ctrl; 790 __be16 word_cookie; 791 __be64 mask; 792 __be64 val; 793 }; 794 795 struct cpl_set_tcb_field_core { 796 union opcode_tid ot; 797 __be16 reply_ctrl; 798 __be16 word_cookie; 799 __be64 mask; 800 __be64 val; 801 }; 802 803 /* cpl_set_tcb_field.word_cookie fields */ 804 #define S_WORD 0 805 #define M_WORD 0x1F 806 #define V_WORD(x) ((x) << S_WORD) 807 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 808 809 #define S_COOKIE 5 810 #define M_COOKIE 0x7 811 #define V_COOKIE(x) ((x) << S_COOKIE) 812 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 813 814 struct cpl_set_tcb_rpl { 815 RSS_HDR 816 union opcode_tid ot; 817 __be16 rsvd; 818 __u8 cookie; 819 __u8 status; 820 __be64 oldval; 821 }; 822 823 struct cpl_close_con_req { 824 WR_HDR; 825 union opcode_tid ot; 826 __be32 rsvd; 827 }; 828 829 struct cpl_close_con_rpl { 830 RSS_HDR 831 union opcode_tid ot; 832 __u8 rsvd[3]; 833 __u8 status; 834 __be32 snd_nxt; 835 __be32 rcv_nxt; 836 }; 837 838 struct cpl_close_listsvr_req { 839 WR_HDR; 840 union opcode_tid ot; 841 __be16 reply_ctrl; 842 __be16 rsvd; 843 }; 844 845 /* additional cpl_close_listsvr_req.reply_ctrl field */ 846 #define S_LISTSVR_IPV6 14 847 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 848 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 849 850 struct cpl_close_listsvr_rpl { 851 RSS_HDR 852 union opcode_tid ot; 853 __u8 rsvd[3]; 854 __u8 status; 855 }; 856 857 struct cpl_abort_req_rss { 858 RSS_HDR 859 union opcode_tid ot; 860 __u8 rsvd[3]; 861 __u8 status; 862 }; 863 864 struct cpl_abort_req { 865 WR_HDR; 866 union opcode_tid ot; 867 __be32 rsvd0; 868 __u8 rsvd1; 869 __u8 cmd; 870 __u8 rsvd2[6]; 871 }; 872 873 struct cpl_abort_rpl_rss { 874 RSS_HDR 875 union opcode_tid ot; 876 __u8 rsvd[3]; 877 __u8 status; 878 }; 879 880 struct cpl_abort_rpl { 881 WR_HDR; 882 union opcode_tid ot; 883 __be32 rsvd0; 884 __u8 rsvd1; 885 __u8 cmd; 886 __u8 rsvd2[6]; 887 }; 888 889 struct cpl_peer_close { 890 RSS_HDR 891 union opcode_tid ot; 892 __be32 rcv_nxt; 893 }; 894 895 struct cpl_tid_release { 896 WR_HDR; 897 union opcode_tid ot; 898 __be32 rsvd; 899 }; 900 901 struct tx_data_wr { 902 __be32 wr_hi; 903 __be32 wr_lo; 904 __be32 len; 905 __be32 flags; 906 __be32 sndseq; 907 __be32 param; 908 }; 909 910 /* tx_data_wr.flags fields */ 911 #define S_TX_ACK_PAGES 21 912 #define M_TX_ACK_PAGES 0x7 913 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 914 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 915 916 /* tx_data_wr.param fields */ 917 #define S_TX_PORT 0 918 #define M_TX_PORT 0x7 919 #define V_TX_PORT(x) ((x) << S_TX_PORT) 920 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 921 922 #define S_TX_MSS 4 923 #define M_TX_MSS 0xF 924 #define V_TX_MSS(x) ((x) << S_TX_MSS) 925 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 926 927 #define S_TX_QOS 8 928 #define M_TX_QOS 0xFF 929 #define V_TX_QOS(x) ((x) << S_TX_QOS) 930 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 931 932 #define S_TX_SNDBUF 16 933 #define M_TX_SNDBUF 0xFFFF 934 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 935 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 936 937 struct cpl_tx_data { 938 union opcode_tid ot; 939 __be32 len; 940 __be32 rsvd; 941 __be32 flags; 942 }; 943 944 /* cpl_tx_data.flags fields */ 945 #define S_TX_PROXY 5 946 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 947 #define F_TX_PROXY V_TX_PROXY(1U) 948 949 #define S_TX_ULP_SUBMODE 6 950 #define M_TX_ULP_SUBMODE 0xF 951 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 952 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 953 954 #define S_TX_ULP_MODE 10 955 #define M_TX_ULP_MODE 0xF 956 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 957 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 958 959 #define S_TX_SHOVE 14 960 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 961 #define F_TX_SHOVE V_TX_SHOVE(1U) 962 963 #define S_TX_MORE 15 964 #define V_TX_MORE(x) ((x) << S_TX_MORE) 965 #define F_TX_MORE V_TX_MORE(1U) 966 967 #define S_TX_URG 16 968 #define V_TX_URG(x) ((x) << S_TX_URG) 969 #define F_TX_URG V_TX_URG(1U) 970 971 #define S_TX_FLUSH 17 972 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 973 #define F_TX_FLUSH V_TX_FLUSH(1U) 974 975 #define S_TX_SAVE 18 976 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 977 #define F_TX_SAVE V_TX_SAVE(1U) 978 979 #define S_TX_TNL 19 980 #define V_TX_TNL(x) ((x) << S_TX_TNL) 981 #define F_TX_TNL V_TX_TNL(1U) 982 983 /* additional tx_data_wr.flags fields */ 984 #define S_TX_CPU_IDX 0 985 #define M_TX_CPU_IDX 0x3F 986 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 987 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 988 989 #define S_TX_CLOSE 17 990 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 991 #define F_TX_CLOSE V_TX_CLOSE(1U) 992 993 #define S_TX_INIT 18 994 #define V_TX_INIT(x) ((x) << S_TX_INIT) 995 #define F_TX_INIT V_TX_INIT(1U) 996 997 #define S_TX_IMM_ACK 19 998 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 999 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1000 1001 #define S_TX_IMM_DMA 20 1002 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1003 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1004 1005 struct cpl_tx_data_ack { 1006 RSS_HDR 1007 union opcode_tid ot; 1008 __be32 snd_una; 1009 }; 1010 1011 struct cpl_wr_ack { /* XXX */ 1012 RSS_HDR 1013 union opcode_tid ot; 1014 __be16 credits; 1015 __be16 rsvd; 1016 __be32 snd_nxt; 1017 __be32 snd_una; 1018 }; 1019 1020 struct cpl_tx_pkt_core { 1021 __be32 ctrl0; 1022 __be16 pack; 1023 __be16 len; 1024 __be64 ctrl1; 1025 }; 1026 1027 struct cpl_tx_pkt { 1028 WR_HDR; 1029 struct cpl_tx_pkt_core c; 1030 }; 1031 1032 #define cpl_tx_pkt_xt cpl_tx_pkt 1033 1034 /* cpl_tx_pkt_core.ctrl0 fields */ 1035 #define S_TXPKT_VF 0 1036 #define M_TXPKT_VF 0xFF 1037 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1038 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1039 1040 #define S_TXPKT_PF 8 1041 #define M_TXPKT_PF 0x7 1042 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1043 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1044 1045 #define S_TXPKT_VF_VLD 11 1046 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1047 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1048 1049 #define S_TXPKT_OVLAN_IDX 12 1050 #define M_TXPKT_OVLAN_IDX 0xF 1051 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1052 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1053 1054 #define S_TXPKT_INTF 16 1055 #define M_TXPKT_INTF 0xF 1056 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1057 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1058 1059 #define S_TXPKT_SPECIAL_STAT 20 1060 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1061 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1062 1063 #define S_TXPKT_INS_OVLAN 21 1064 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1065 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1066 1067 #define S_TXPKT_STAT_DIS 22 1068 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1069 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1070 1071 #define S_TXPKT_LOOPBACK 23 1072 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1073 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1074 1075 #define S_TXPKT_TSTAMP 23 1076 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1077 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1078 1079 #define S_TXPKT_OPCODE 24 1080 #define M_TXPKT_OPCODE 0xFF 1081 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1082 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1083 1084 /* cpl_tx_pkt_core.ctrl1 fields */ 1085 #define S_TXPKT_SA_IDX 0 1086 #define M_TXPKT_SA_IDX 0xFFF 1087 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1088 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1089 1090 #define S_TXPKT_CSUM_END 12 1091 #define M_TXPKT_CSUM_END 0xFF 1092 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1093 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1094 1095 #define S_TXPKT_CSUM_START 20 1096 #define M_TXPKT_CSUM_START 0x3FF 1097 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1098 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1099 1100 #define S_TXPKT_IPHDR_LEN 20 1101 #define M_TXPKT_IPHDR_LEN 0x3FFF 1102 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1103 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1104 1105 #define S_TXPKT_CSUM_LOC 30 1106 #define M_TXPKT_CSUM_LOC 0x3FF 1107 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1108 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1109 1110 #define S_TXPKT_ETHHDR_LEN 34 1111 #define M_TXPKT_ETHHDR_LEN 0x3F 1112 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1113 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1114 1115 #define S_TXPKT_CSUM_TYPE 40 1116 #define M_TXPKT_CSUM_TYPE 0xF 1117 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1118 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1119 1120 #define S_TXPKT_VLAN 44 1121 #define M_TXPKT_VLAN 0xFFFF 1122 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1123 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1124 1125 #define S_TXPKT_VLAN_VLD 60 1126 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1127 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1128 1129 #define S_TXPKT_IPSEC 61 1130 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1131 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1132 1133 #define S_TXPKT_IPCSUM_DIS 62 1134 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1135 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1136 1137 #define S_TXPKT_L4CSUM_DIS 63 1138 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1139 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1140 1141 struct cpl_tx_pkt_lso_core { 1142 __be32 lso_ctrl; 1143 __be16 ipid_ofst; 1144 __be16 mss; 1145 __be32 seqno_offset; 1146 __be32 len; 1147 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1148 }; 1149 1150 struct cpl_tx_pkt_lso { 1151 WR_HDR; 1152 struct cpl_tx_pkt_lso_core c; 1153 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1154 }; 1155 1156 struct cpl_tx_pkt_ufo_core { 1157 __be16 ethlen; 1158 __be16 iplen; 1159 __be16 udplen; 1160 __be16 mss; 1161 __be32 len; 1162 __be32 r1; 1163 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1164 }; 1165 1166 struct cpl_tx_pkt_ufo { 1167 WR_HDR; 1168 struct cpl_tx_pkt_ufo_core c; 1169 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1170 }; 1171 1172 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1173 #define S_LSO_TCPHDR_LEN 0 1174 #define M_LSO_TCPHDR_LEN 0xF 1175 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1176 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1177 1178 #define S_LSO_IPHDR_LEN 4 1179 #define M_LSO_IPHDR_LEN 0xFFF 1180 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1181 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1182 1183 #define S_LSO_ETHHDR_LEN 16 1184 #define M_LSO_ETHHDR_LEN 0xF 1185 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1186 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1187 1188 #define S_LSO_IPV6 20 1189 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1190 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1191 1192 #define S_LSO_OFLD_ENCAP 21 1193 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1194 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1195 1196 #define S_LSO_LAST_SLICE 22 1197 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1198 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1199 1200 #define S_LSO_FIRST_SLICE 23 1201 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1202 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1203 1204 #define S_LSO_OPCODE 24 1205 #define M_LSO_OPCODE 0xFF 1206 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1207 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1208 1209 /* cpl_tx_pkt_lso_core.mss fields */ 1210 #define S_LSO_MSS 0 1211 #define M_LSO_MSS 0x3FFF 1212 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1213 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1214 1215 #define S_LSO_IPID_SPLIT 15 1216 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1217 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1218 1219 struct cpl_tx_pkt_fso { 1220 WR_HDR; 1221 __be32 fso_ctrl; 1222 __be16 seqcnt_ofst; 1223 __be16 mtu; 1224 __be32 param_offset; 1225 __be32 len; 1226 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1227 }; 1228 1229 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1230 #define S_FSO_XCHG_CLASS 21 1231 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1232 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1233 1234 #define S_FSO_INITIATOR 20 1235 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1236 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1237 1238 #define S_FSO_FCHDR_LEN 12 1239 #define M_FSO_FCHDR_LEN 0xF 1240 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1241 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1242 1243 struct cpl_iscsi_hdr_no_rss { 1244 union opcode_tid ot; 1245 __be16 pdu_len_ddp; 1246 __be16 len; 1247 __be32 seq; 1248 __be16 urg; 1249 __u8 rsvd; 1250 __u8 status; 1251 }; 1252 1253 struct cpl_tx_data_iso { 1254 WR_HDR; 1255 __be32 iso_ctrl; 1256 __u8 rsvd; 1257 __u8 ahs_len; 1258 __be16 mss; 1259 __be32 burst_size; 1260 __be32 len; 1261 /* encapsulated CPL_TX_DATA follows here */ 1262 }; 1263 1264 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1265 #define S_ISO_CPLHDR_LEN 18 1266 #define M_ISO_CPLHDR_LEN 0xF 1267 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1268 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1269 1270 #define S_ISO_HDR_CRC 17 1271 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1272 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1273 1274 #define S_ISO_DATA_CRC 16 1275 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1276 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1277 1278 #define S_ISO_IMD_DATA_EN 15 1279 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1280 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1281 1282 #define S_ISO_PDU_TYPE 13 1283 #define M_ISO_PDU_TYPE 0x3 1284 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1285 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1286 1287 struct cpl_iscsi_hdr { 1288 RSS_HDR 1289 union opcode_tid ot; 1290 __be16 pdu_len_ddp; 1291 __be16 len; 1292 __be32 seq; 1293 __be16 urg; 1294 __u8 rsvd; 1295 __u8 status; 1296 }; 1297 1298 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1299 #define S_ISCSI_PDU_LEN 0 1300 #define M_ISCSI_PDU_LEN 0x7FFF 1301 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1302 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1303 1304 #define S_ISCSI_DDP 15 1305 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1306 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1307 1308 struct cpl_iscsi_data { 1309 RSS_HDR 1310 union opcode_tid ot; 1311 __u8 rsvd0[2]; 1312 __be16 len; 1313 __be32 seq; 1314 __be16 urg; 1315 __u8 rsvd1; 1316 __u8 status; 1317 }; 1318 1319 struct cpl_rx_data { 1320 RSS_HDR 1321 union opcode_tid ot; 1322 __be16 rsvd; 1323 __be16 len; 1324 __be32 seq; 1325 __be16 urg; 1326 #if defined(__LITTLE_ENDIAN_BITFIELD) 1327 __u8 dack_mode:2; 1328 __u8 psh:1; 1329 __u8 heartbeat:1; 1330 __u8 ddp_off:1; 1331 __u8 :3; 1332 #else 1333 __u8 :3; 1334 __u8 ddp_off:1; 1335 __u8 heartbeat:1; 1336 __u8 psh:1; 1337 __u8 dack_mode:2; 1338 #endif 1339 __u8 status; 1340 }; 1341 1342 struct cpl_fcoe_hdr { 1343 RSS_HDR 1344 union opcode_tid ot; 1345 __be16 oxid; 1346 __be16 len; 1347 __be32 rctl_fctl; 1348 __u8 cs_ctl; 1349 __u8 df_ctl; 1350 __u8 sof; 1351 __u8 eof; 1352 __be16 seq_cnt; 1353 __u8 seq_id; 1354 __u8 type; 1355 __be32 param; 1356 }; 1357 1358 struct cpl_fcoe_data { 1359 RSS_HDR 1360 union opcode_tid ot; 1361 __u8 rsvd0[2]; 1362 __be16 len; 1363 __be32 seq; 1364 __u8 rsvd1[3]; 1365 __u8 status; 1366 }; 1367 1368 struct cpl_rx_urg_notify { 1369 RSS_HDR 1370 union opcode_tid ot; 1371 __be32 seq; 1372 }; 1373 1374 struct cpl_rx_urg_pkt { 1375 RSS_HDR 1376 union opcode_tid ot; 1377 __be16 rsvd; 1378 __be16 len; 1379 }; 1380 1381 struct cpl_rx_data_ack { 1382 WR_HDR; 1383 union opcode_tid ot; 1384 __be32 credit_dack; 1385 }; 1386 1387 struct cpl_rx_data_ack_core { 1388 union opcode_tid ot; 1389 __be32 credit_dack; 1390 }; 1391 1392 /* cpl_rx_data_ack.ack_seq fields */ 1393 #define S_RX_CREDITS 0 1394 #define M_RX_CREDITS 0x3FFFFFF 1395 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1396 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1397 1398 #define S_RX_MODULATE_TX 26 1399 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1400 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1401 1402 #define S_RX_MODULATE_RX 27 1403 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1404 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1405 1406 #define S_RX_FORCE_ACK 28 1407 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1408 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1409 1410 #define S_RX_DACK_MODE 29 1411 #define M_RX_DACK_MODE 0x3 1412 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1413 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1414 1415 #define S_RX_DACK_CHANGE 31 1416 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1417 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1418 1419 struct cpl_rx_ddp_complete { 1420 RSS_HDR 1421 union opcode_tid ot; 1422 __be32 ddp_report; 1423 __be32 rcv_nxt; 1424 __be32 rsvd; 1425 }; 1426 1427 struct cpl_rx_data_ddp { 1428 RSS_HDR 1429 union opcode_tid ot; 1430 __be16 urg; 1431 __be16 len; 1432 __be32 seq; 1433 union { 1434 __be32 nxt_seq; 1435 __be32 ddp_report; 1436 } u; 1437 __be32 ulp_crc; 1438 __be32 ddpvld; 1439 }; 1440 1441 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1442 1443 struct cpl_rx_fcoe_ddp { 1444 RSS_HDR 1445 union opcode_tid ot; 1446 __be16 rsvd; 1447 __be16 len; 1448 __be32 seq; 1449 __be32 ddp_report; 1450 __be32 ulp_crc; 1451 __be32 ddpvld; 1452 }; 1453 1454 struct cpl_rx_data_dif { 1455 RSS_HDR 1456 union opcode_tid ot; 1457 __be16 ddp_len; 1458 __be16 msg_len; 1459 __be32 seq; 1460 union { 1461 __be32 nxt_seq; 1462 __be32 ddp_report; 1463 } u; 1464 __be32 err_vec; 1465 __be32 ddpvld; 1466 }; 1467 1468 struct cpl_rx_iscsi_dif { 1469 RSS_HDR 1470 union opcode_tid ot; 1471 __be16 ddp_len; 1472 __be16 msg_len; 1473 __be32 seq; 1474 union { 1475 __be32 nxt_seq; 1476 __be32 ddp_report; 1477 } u; 1478 __be32 ulp_crc; 1479 __be32 ddpvld; 1480 __u8 rsvd0[8]; 1481 __be32 err_vec; 1482 __u8 rsvd1[4]; 1483 }; 1484 1485 struct cpl_rx_fcoe_dif { 1486 RSS_HDR 1487 union opcode_tid ot; 1488 __be16 ddp_len; 1489 __be16 msg_len; 1490 __be32 seq; 1491 __be32 ddp_report; 1492 __be32 err_vec; 1493 __be32 ddpvld; 1494 }; 1495 1496 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1497 #define S_DDP_VALID 15 1498 #define M_DDP_VALID 0x1FFFF 1499 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1500 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1501 1502 #define S_DDP_PPOD_MISMATCH 15 1503 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1504 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1505 1506 #define S_DDP_PDU 16 1507 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1508 #define F_DDP_PDU V_DDP_PDU(1U) 1509 1510 #define S_DDP_LLIMIT_ERR 17 1511 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1512 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1513 1514 #define S_DDP_PPOD_PARITY_ERR 18 1515 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1516 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1517 1518 #define S_DDP_PADDING_ERR 19 1519 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1520 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1521 1522 #define S_DDP_HDRCRC_ERR 20 1523 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1524 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1525 1526 #define S_DDP_DATACRC_ERR 21 1527 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1528 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1529 1530 #define S_DDP_INVALID_TAG 22 1531 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1532 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1533 1534 #define S_DDP_ULIMIT_ERR 23 1535 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1536 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1537 1538 #define S_DDP_OFFSET_ERR 24 1539 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1540 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1541 1542 #define S_DDP_COLOR_ERR 25 1543 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1544 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1545 1546 #define S_DDP_TID_MISMATCH 26 1547 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1548 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1549 1550 #define S_DDP_INVALID_PPOD 27 1551 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1552 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1553 1554 #define S_DDP_ULP_MODE 28 1555 #define M_DDP_ULP_MODE 0xF 1556 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1557 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1558 1559 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1560 #define S_DDP_OFFSET 0 1561 #define M_DDP_OFFSET 0xFFFFFF 1562 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1563 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1564 1565 #define S_DDP_DACK_MODE 24 1566 #define M_DDP_DACK_MODE 0x3 1567 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1568 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1569 1570 #define S_DDP_BUF_IDX 26 1571 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1572 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1573 1574 #define S_DDP_URG 27 1575 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1576 #define F_DDP_URG V_DDP_URG(1U) 1577 1578 #define S_DDP_PSH 28 1579 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1580 #define F_DDP_PSH V_DDP_PSH(1U) 1581 1582 #define S_DDP_BUF_COMPLETE 29 1583 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1584 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1585 1586 #define S_DDP_BUF_TIMED_OUT 30 1587 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1588 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1589 1590 #define S_DDP_INV 31 1591 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1592 #define F_DDP_INV V_DDP_INV(1U) 1593 1594 struct cpl_rx_pkt { 1595 RSS_HDR 1596 __u8 opcode; 1597 #if defined(__LITTLE_ENDIAN_BITFIELD) 1598 __u8 iff:4; 1599 __u8 csum_calc:1; 1600 __u8 ipmi_pkt:1; 1601 __u8 vlan_ex:1; 1602 __u8 ip_frag:1; 1603 #else 1604 __u8 ip_frag:1; 1605 __u8 vlan_ex:1; 1606 __u8 ipmi_pkt:1; 1607 __u8 csum_calc:1; 1608 __u8 iff:4; 1609 #endif 1610 __be16 csum; 1611 __be16 vlan; 1612 __be16 len; 1613 __be32 l2info; 1614 __be16 hdr_len; 1615 __be16 err_vec; 1616 }; 1617 1618 /* rx_pkt.l2info fields */ 1619 #define S_RX_ETHHDR_LEN 0 1620 #define M_RX_ETHHDR_LEN 0x1F 1621 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1622 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1623 1624 #define S_RX_T5_ETHHDR_LEN 0 1625 #define M_RX_T5_ETHHDR_LEN 0x3F 1626 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1627 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1628 1629 #define S_RX_PKTYPE 5 1630 #define M_RX_PKTYPE 0x7 1631 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1632 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1633 1634 #define S_RX_T5_DATYPE 6 1635 #define M_RX_T5_DATYPE 0x3 1636 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1637 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1638 1639 #define S_RX_MACIDX 8 1640 #define M_RX_MACIDX 0x1FF 1641 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1642 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1643 1644 #define S_RX_T5_PKTYPE 17 1645 #define M_RX_T5_PKTYPE 0x7 1646 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1647 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1648 1649 #define S_RX_DATYPE 18 1650 #define M_RX_DATYPE 0x3 1651 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1652 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1653 1654 #define S_RXF_PSH 20 1655 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1656 #define F_RXF_PSH V_RXF_PSH(1U) 1657 1658 #define S_RXF_SYN 21 1659 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1660 #define F_RXF_SYN V_RXF_SYN(1U) 1661 1662 #define S_RXF_UDP 22 1663 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1664 #define F_RXF_UDP V_RXF_UDP(1U) 1665 1666 #define S_RXF_TCP 23 1667 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1668 #define F_RXF_TCP V_RXF_TCP(1U) 1669 1670 #define S_RXF_IP 24 1671 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1672 #define F_RXF_IP V_RXF_IP(1U) 1673 1674 #define S_RXF_IP6 25 1675 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1676 #define F_RXF_IP6 V_RXF_IP6(1U) 1677 1678 #define S_RXF_SYN_COOKIE 26 1679 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1680 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1681 1682 #define S_RXF_FCOE 26 1683 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1684 #define F_RXF_FCOE V_RXF_FCOE(1U) 1685 1686 #define S_RXF_LRO 27 1687 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1688 #define F_RXF_LRO V_RXF_LRO(1U) 1689 1690 #define S_RX_CHAN 28 1691 #define M_RX_CHAN 0xF 1692 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1693 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1694 1695 /* rx_pkt.hdr_len fields */ 1696 #define S_RX_TCPHDR_LEN 0 1697 #define M_RX_TCPHDR_LEN 0x3F 1698 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1699 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1700 1701 #define S_RX_IPHDR_LEN 6 1702 #define M_RX_IPHDR_LEN 0x3FF 1703 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1704 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1705 1706 /* rx_pkt.err_vec fields */ 1707 #define S_RXERR_OR 0 1708 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1709 #define F_RXERR_OR V_RXERR_OR(1U) 1710 1711 #define S_RXERR_MAC 1 1712 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1713 #define F_RXERR_MAC V_RXERR_MAC(1U) 1714 1715 #define S_RXERR_IPVERS 2 1716 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1717 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1718 1719 #define S_RXERR_FRAG 3 1720 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1721 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1722 1723 #define S_RXERR_ATTACK 4 1724 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1725 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1726 1727 #define S_RXERR_ETHHDR_LEN 5 1728 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1729 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1730 1731 #define S_RXERR_IPHDR_LEN 6 1732 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1733 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1734 1735 #define S_RXERR_TCPHDR_LEN 7 1736 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1737 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1738 1739 #define S_RXERR_PKT_LEN 8 1740 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1741 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1742 1743 #define S_RXERR_TCP_OPT 9 1744 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1745 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1746 1747 #define S_RXERR_IPCSUM 12 1748 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1749 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1750 1751 #define S_RXERR_CSUM 13 1752 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1753 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1754 1755 #define S_RXERR_PING 14 1756 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1757 #define F_RXERR_PING V_RXERR_PING(1U) 1758 1759 struct cpl_trace_pkt { 1760 RSS_HDR 1761 __u8 opcode; 1762 __u8 intf; 1763 #if defined(__LITTLE_ENDIAN_BITFIELD) 1764 __u8 runt:4; 1765 __u8 filter_hit:4; 1766 __u8 :6; 1767 __u8 err:1; 1768 __u8 trunc:1; 1769 #else 1770 __u8 filter_hit:4; 1771 __u8 runt:4; 1772 __u8 trunc:1; 1773 __u8 err:1; 1774 __u8 :6; 1775 #endif 1776 __be16 rsvd; 1777 __be16 len; 1778 __be64 tstamp; 1779 }; 1780 1781 struct cpl_t5_trace_pkt { 1782 RSS_HDR 1783 __u8 opcode; 1784 __u8 intf; 1785 #if defined(__LITTLE_ENDIAN_BITFIELD) 1786 __u8 runt:4; 1787 __u8 filter_hit:4; 1788 __u8 :6; 1789 __u8 err:1; 1790 __u8 trunc:1; 1791 #else 1792 __u8 filter_hit:4; 1793 __u8 runt:4; 1794 __u8 trunc:1; 1795 __u8 err:1; 1796 __u8 :6; 1797 #endif 1798 __be16 rsvd; 1799 __be16 len; 1800 __be64 tstamp; 1801 __be64 rsvd1; 1802 }; 1803 1804 struct cpl_rte_delete_req { 1805 WR_HDR; 1806 union opcode_tid ot; 1807 __be32 params; 1808 }; 1809 1810 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1811 #define S_RTE_REQ_LUT_IX 8 1812 #define M_RTE_REQ_LUT_IX 0x7FF 1813 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1814 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1815 1816 #define S_RTE_REQ_LUT_BASE 19 1817 #define M_RTE_REQ_LUT_BASE 0x7FF 1818 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1819 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1820 1821 #define S_RTE_READ_REQ_SELECT 31 1822 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1823 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1824 1825 struct cpl_rte_delete_rpl { 1826 RSS_HDR 1827 union opcode_tid ot; 1828 __u8 status; 1829 __u8 rsvd[3]; 1830 }; 1831 1832 struct cpl_rte_write_req { 1833 WR_HDR; 1834 union opcode_tid ot; 1835 __u32 write_sel; 1836 __be32 lut_params; 1837 __be32 l2t_idx; 1838 __be32 netmask; 1839 __be32 faddr; 1840 }; 1841 1842 /* cpl_rte_write_req.write_sel fields */ 1843 #define S_RTE_WR_L2TIDX 31 1844 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1845 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1846 1847 #define S_RTE_WR_FADDR 30 1848 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1849 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1850 1851 /* cpl_rte_write_req.lut_params fields */ 1852 #define S_RTE_WR_LUT_IX 10 1853 #define M_RTE_WR_LUT_IX 0x7FF 1854 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1855 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1856 1857 #define S_RTE_WR_LUT_BASE 21 1858 #define M_RTE_WR_LUT_BASE 0x7FF 1859 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1860 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1861 1862 struct cpl_rte_write_rpl { 1863 RSS_HDR 1864 union opcode_tid ot; 1865 __u8 status; 1866 __u8 rsvd[3]; 1867 }; 1868 1869 struct cpl_rte_read_req { 1870 WR_HDR; 1871 union opcode_tid ot; 1872 __be32 params; 1873 }; 1874 1875 struct cpl_rte_read_rpl { 1876 RSS_HDR 1877 union opcode_tid ot; 1878 __u8 status; 1879 __u8 rsvd; 1880 __be16 l2t_idx; 1881 #if defined(__LITTLE_ENDIAN_BITFIELD) 1882 __u32 :30; 1883 __u32 select:1; 1884 #else 1885 __u32 select:1; 1886 __u32 :30; 1887 #endif 1888 __be32 addr; 1889 }; 1890 1891 struct cpl_l2t_write_req { 1892 WR_HDR; 1893 union opcode_tid ot; 1894 __be16 params; 1895 __be16 l2t_idx; 1896 __be16 vlan; 1897 __u8 dst_mac[6]; 1898 }; 1899 1900 /* cpl_l2t_write_req.params fields */ 1901 #define S_L2T_W_INFO 2 1902 #define M_L2T_W_INFO 0x3F 1903 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1904 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1905 1906 #define S_L2T_W_PORT 8 1907 #define M_L2T_W_PORT 0xF 1908 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1909 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1910 1911 #define S_L2T_W_NOREPLY 15 1912 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1913 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1914 1915 struct cpl_l2t_write_rpl { 1916 RSS_HDR 1917 union opcode_tid ot; 1918 __u8 status; 1919 __u8 rsvd[3]; 1920 }; 1921 1922 struct cpl_l2t_read_req { 1923 WR_HDR; 1924 union opcode_tid ot; 1925 __be32 l2t_idx; 1926 }; 1927 1928 struct cpl_l2t_read_rpl { 1929 RSS_HDR 1930 union opcode_tid ot; 1931 __u8 status; 1932 #if defined(__LITTLE_ENDIAN_BITFIELD) 1933 __u8 :4; 1934 __u8 iff:4; 1935 #else 1936 __u8 iff:4; 1937 __u8 :4; 1938 #endif 1939 __be16 vlan; 1940 __be16 info; 1941 __u8 dst_mac[6]; 1942 }; 1943 1944 struct cpl_smt_write_req { 1945 WR_HDR; 1946 union opcode_tid ot; 1947 __be32 params; 1948 __be16 pfvf1; 1949 __u8 src_mac1[6]; 1950 __be16 pfvf0; 1951 __u8 src_mac0[6]; 1952 }; 1953 1954 struct cpl_smt_write_rpl { 1955 RSS_HDR 1956 union opcode_tid ot; 1957 __u8 status; 1958 __u8 rsvd[3]; 1959 }; 1960 1961 struct cpl_smt_read_req { 1962 WR_HDR; 1963 union opcode_tid ot; 1964 __be32 params; 1965 }; 1966 1967 struct cpl_smt_read_rpl { 1968 RSS_HDR 1969 union opcode_tid ot; 1970 __u8 status; 1971 __u8 ovlan_idx; 1972 __be16 rsvd; 1973 __be16 pfvf1; 1974 __u8 src_mac1[6]; 1975 __be16 pfvf0; 1976 __u8 src_mac0[6]; 1977 }; 1978 1979 /* cpl_smt_{read,write}_req.params fields */ 1980 #define S_SMTW_OVLAN_IDX 16 1981 #define M_SMTW_OVLAN_IDX 0xF 1982 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1983 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1984 1985 #define S_SMTW_IDX 20 1986 #define M_SMTW_IDX 0x7F 1987 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 1988 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 1989 1990 #define S_SMTW_NORPL 31 1991 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 1992 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 1993 1994 /* cpl_smt_{read,write}_req.pfvf? fields */ 1995 #define S_SMTW_VF 0 1996 #define M_SMTW_VF 0xFF 1997 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 1998 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 1999 2000 #define S_SMTW_PF 8 2001 #define M_SMTW_PF 0x7 2002 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2003 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2004 2005 #define S_SMTW_VF_VLD 11 2006 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2007 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2008 2009 struct cpl_tag_write_req { 2010 WR_HDR; 2011 union opcode_tid ot; 2012 __be32 params; 2013 __be64 tag_val; 2014 }; 2015 2016 struct cpl_tag_write_rpl { 2017 RSS_HDR 2018 union opcode_tid ot; 2019 __u8 status; 2020 __u8 rsvd[2]; 2021 __u8 idx; 2022 }; 2023 2024 struct cpl_tag_read_req { 2025 WR_HDR; 2026 union opcode_tid ot; 2027 __be32 params; 2028 }; 2029 2030 struct cpl_tag_read_rpl { 2031 RSS_HDR 2032 union opcode_tid ot; 2033 __u8 status; 2034 #if defined(__LITTLE_ENDIAN_BITFIELD) 2035 __u8 :4; 2036 __u8 tag_len:1; 2037 __u8 :2; 2038 __u8 ins_enable:1; 2039 #else 2040 __u8 ins_enable:1; 2041 __u8 :2; 2042 __u8 tag_len:1; 2043 __u8 :4; 2044 #endif 2045 __u8 rsvd; 2046 __u8 tag_idx; 2047 __be64 tag_val; 2048 }; 2049 2050 /* cpl_tag{read,write}_req.params fields */ 2051 #define S_TAGW_IDX 0 2052 #define M_TAGW_IDX 0x7F 2053 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2054 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2055 2056 #define S_TAGW_LEN 20 2057 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2058 #define F_TAGW_LEN V_TAGW_LEN(1U) 2059 2060 #define S_TAGW_INS_ENABLE 23 2061 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2062 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2063 2064 #define S_TAGW_NORPL 31 2065 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2066 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2067 2068 struct cpl_barrier { 2069 WR_HDR; 2070 __u8 opcode; 2071 __u8 chan_map; 2072 __be16 rsvd0; 2073 __be32 rsvd1; 2074 }; 2075 2076 /* cpl_barrier.chan_map fields */ 2077 #define S_CHAN_MAP 4 2078 #define M_CHAN_MAP 0xF 2079 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2080 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2081 2082 struct cpl_error { 2083 RSS_HDR 2084 union opcode_tid ot; 2085 __be32 error; 2086 }; 2087 2088 struct cpl_hit_notify { 2089 RSS_HDR 2090 union opcode_tid ot; 2091 __be32 rsvd; 2092 __be32 info; 2093 __be32 reason; 2094 }; 2095 2096 struct cpl_pkt_notify { 2097 RSS_HDR 2098 union opcode_tid ot; 2099 __be16 rsvd; 2100 __be16 len; 2101 __be32 info; 2102 __be32 reason; 2103 }; 2104 2105 /* cpl_{hit,pkt}_notify.info fields */ 2106 #define S_NTFY_MAC_IDX 0 2107 #define M_NTFY_MAC_IDX 0x1FF 2108 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2109 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2110 2111 #define S_NTFY_INTF 10 2112 #define M_NTFY_INTF 0xF 2113 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2114 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2115 2116 #define S_NTFY_TCPHDR_LEN 14 2117 #define M_NTFY_TCPHDR_LEN 0xF 2118 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2119 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2120 2121 #define S_NTFY_IPHDR_LEN 18 2122 #define M_NTFY_IPHDR_LEN 0x1FF 2123 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2124 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2125 2126 #define S_NTFY_ETHHDR_LEN 27 2127 #define M_NTFY_ETHHDR_LEN 0x1F 2128 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2129 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2130 2131 #define S_NTFY_T5_IPHDR_LEN 18 2132 #define M_NTFY_T5_IPHDR_LEN 0xFF 2133 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2134 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2135 2136 #define S_NTFY_T5_ETHHDR_LEN 26 2137 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2138 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2139 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2140 2141 struct cpl_rdma_terminate { 2142 RSS_HDR 2143 union opcode_tid ot; 2144 __be16 rsvd; 2145 __be16 len; 2146 }; 2147 2148 struct cpl_set_le_req { 2149 WR_HDR; 2150 union opcode_tid ot; 2151 __be16 reply_ctrl; 2152 __be16 params; 2153 __be64 mask_hi; 2154 __be64 mask_lo; 2155 __be64 val_hi; 2156 __be64 val_lo; 2157 }; 2158 2159 /* cpl_set_le_req.reply_ctrl additional fields */ 2160 #define S_LE_REQ_IP6 13 2161 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2162 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2163 2164 /* cpl_set_le_req.params fields */ 2165 #define S_LE_CHAN 0 2166 #define M_LE_CHAN 0x3 2167 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2168 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2169 2170 #define S_LE_OFFSET 5 2171 #define M_LE_OFFSET 0x7 2172 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2173 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2174 2175 #define S_LE_MORE 8 2176 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2177 #define F_LE_MORE V_LE_MORE(1U) 2178 2179 #define S_LE_REQSIZE 9 2180 #define M_LE_REQSIZE 0x7 2181 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2182 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2183 2184 #define S_LE_REQCMD 12 2185 #define M_LE_REQCMD 0xF 2186 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2187 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2188 2189 struct cpl_set_le_rpl { 2190 RSS_HDR 2191 union opcode_tid ot; 2192 __u8 chan; 2193 __u8 info; 2194 __be16 len; 2195 }; 2196 2197 /* cpl_set_le_rpl.info fields */ 2198 #define S_LE_RSPCMD 0 2199 #define M_LE_RSPCMD 0xF 2200 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2201 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2202 2203 #define S_LE_RSPSIZE 4 2204 #define M_LE_RSPSIZE 0x7 2205 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2206 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2207 2208 #define S_LE_RSPTYPE 7 2209 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2210 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2211 2212 struct cpl_sge_egr_update { 2213 RSS_HDR 2214 __be32 opcode_qid; 2215 __be16 cidx; 2216 __be16 pidx; 2217 }; 2218 2219 /* cpl_sge_egr_update.ot fields */ 2220 #define S_EGR_QID 0 2221 #define M_EGR_QID 0x1FFFF 2222 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2223 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2224 2225 struct cpl_fw2_pld { 2226 RSS_HDR 2227 u8 opcode; 2228 u8 rsvd[5]; 2229 __be16 len; 2230 }; 2231 2232 struct cpl_fw4_pld { 2233 RSS_HDR 2234 u8 opcode; 2235 u8 rsvd0[3]; 2236 u8 type; 2237 u8 rsvd1; 2238 __be16 len; 2239 __be64 data; 2240 __be64 rsvd2; 2241 }; 2242 2243 struct cpl_fw6_pld { 2244 RSS_HDR 2245 u8 opcode; 2246 u8 rsvd[5]; 2247 __be16 len; 2248 __be64 data[4]; 2249 }; 2250 2251 struct cpl_fw2_msg { 2252 RSS_HDR 2253 union opcode_info oi; 2254 }; 2255 2256 struct cpl_fw4_msg { 2257 RSS_HDR 2258 u8 opcode; 2259 u8 type; 2260 __be16 rsvd0; 2261 __be32 rsvd1; 2262 __be64 data[2]; 2263 }; 2264 2265 struct cpl_fw4_ack { 2266 RSS_HDR 2267 union opcode_tid ot; 2268 u8 credits; 2269 u8 rsvd0[2]; 2270 u8 flags; 2271 __be32 snd_nxt; 2272 __be32 snd_una; 2273 __be64 rsvd1; 2274 }; 2275 2276 enum { 2277 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2278 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2279 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2280 }; 2281 2282 struct cpl_fw6_msg { 2283 RSS_HDR 2284 u8 opcode; 2285 u8 type; 2286 __be16 rsvd0; 2287 __be32 rsvd1; 2288 __be64 data[4]; 2289 }; 2290 2291 /* cpl_fw6_msg.type values */ 2292 enum { 2293 FW6_TYPE_CMD_RPL = 0, 2294 FW6_TYPE_WR_RPL = 1, 2295 FW6_TYPE_CQE = 2, 2296 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2297 2298 NUM_FW6_TYPES 2299 }; 2300 2301 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2302 __u64 cookie; 2303 __be32 tid; /* or atid in case of active failure */ 2304 __u8 t_state; 2305 __u8 retval; 2306 __u8 rsvd[2]; 2307 }; 2308 2309 /* ULP_TX opcodes */ 2310 enum { 2311 ULP_TX_MEM_READ = 2, 2312 ULP_TX_MEM_WRITE = 3, 2313 ULP_TX_PKT = 4 2314 }; 2315 2316 enum { 2317 ULP_TX_SC_NOOP = 0x80, 2318 ULP_TX_SC_IMM = 0x81, 2319 ULP_TX_SC_DSGL = 0x82, 2320 ULP_TX_SC_ISGL = 0x83 2321 }; 2322 2323 #define S_ULPTX_CMD 24 2324 #define M_ULPTX_CMD 0xFF 2325 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2326 2327 #define S_ULPTX_LEN16 0 2328 #define M_ULPTX_LEN16 0xFF 2329 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2330 2331 #define S_ULP_TX_SC_MORE 23 2332 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2333 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2334 2335 struct ulptx_sge_pair { 2336 __be32 len[2]; 2337 __be64 addr[2]; 2338 }; 2339 2340 struct ulptx_sgl { 2341 __be32 cmd_nsge; 2342 __be32 len0; 2343 __be64 addr0; 2344 #if !(defined C99_NOT_SUPPORTED) 2345 struct ulptx_sge_pair sge[0]; 2346 #endif 2347 }; 2348 2349 struct ulptx_isge { 2350 __be32 stag; 2351 __be32 len; 2352 __be64 target_ofst; 2353 }; 2354 2355 struct ulptx_isgl { 2356 __be32 cmd_nisge; 2357 __be32 rsvd; 2358 #if !(defined C99_NOT_SUPPORTED) 2359 struct ulptx_isge sge[0]; 2360 #endif 2361 }; 2362 2363 struct ulptx_idata { 2364 __be32 cmd_more; 2365 __be32 len; 2366 }; 2367 2368 #define S_ULPTX_NSGE 0 2369 #define M_ULPTX_NSGE 0xFFFF 2370 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2371 2372 struct ulp_mem_io { 2373 WR_HDR; 2374 __be32 cmd; 2375 __be32 len16; /* command length */ 2376 __be32 dlen; /* data length in 32-byte units */ 2377 __be32 lock_addr; 2378 }; 2379 2380 /* additional ulp_mem_io.cmd fields */ 2381 #define S_ULP_MEMIO_ORDER 23 2382 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2383 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2384 2385 /* ulp_mem_io.lock_addr fields */ 2386 #define S_ULP_MEMIO_ADDR 0 2387 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2388 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2389 2390 #define S_ULP_MEMIO_LOCK 31 2391 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2392 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2393 2394 /* ulp_mem_io.dlen fields */ 2395 #define S_ULP_MEMIO_DATA_LEN 0 2396 #define M_ULP_MEMIO_DATA_LEN 0x1F 2397 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2398 2399 struct ulp_txpkt { 2400 __be32 cmd_dest; 2401 __be32 len; 2402 }; 2403 2404 /* ulp_txpkt.cmd_dest fields */ 2405 #define S_ULP_TXPKT_DEST 16 2406 #define M_ULP_TXPKT_DEST 0x3 2407 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2408 2409 #define S_ULP_TXPKT_FID 4 2410 #define M_ULP_TXPKT_FID 0x7ff 2411 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2412 2413 #define S_ULP_TXPKT_RO 3 2414 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2415 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2416 2417 #endif /* T4_MSG_H */ 2418