1 /*- 2 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_SRQ_TABLE_REQ = 0x1C, 59 CPL_TX_PKT_FSO = 0x1E, 60 CPL_TX_DATA_ISO = 0x1F, 61 62 CPL_CLOSE_LISTSRV_RPL = 0x20, 63 CPL_ERROR = 0x21, 64 CPL_GET_TCB_RPL = 0x22, 65 CPL_L2T_WRITE_RPL = 0x23, 66 CPL_PASS_OPEN_RPL = 0x24, 67 CPL_ACT_OPEN_RPL = 0x25, 68 CPL_PEER_CLOSE = 0x26, 69 CPL_RTE_DELETE_RPL = 0x27, 70 CPL_RTE_WRITE_RPL = 0x28, 71 CPL_RX_URG_PKT = 0x29, 72 CPL_TAG_WRITE_RPL = 0x2A, 73 CPL_ABORT_REQ_RSS = 0x2B, 74 CPL_RX_URG_NOTIFY = 0x2C, 75 CPL_ABORT_RPL_RSS = 0x2D, 76 CPL_SMT_WRITE_RPL = 0x2E, 77 CPL_TX_DATA_ACK = 0x2F, 78 79 CPL_RX_PHYS_ADDR = 0x30, 80 CPL_PCMD_READ_RPL = 0x31, 81 CPL_CLOSE_CON_RPL = 0x32, 82 CPL_ISCSI_HDR = 0x33, 83 CPL_L2T_READ_RPL = 0x34, 84 CPL_RDMA_CQE = 0x35, 85 CPL_RDMA_CQE_READ_RSP = 0x36, 86 CPL_RDMA_CQE_ERR = 0x37, 87 CPL_RTE_READ_RPL = 0x38, 88 CPL_RX_DATA = 0x39, 89 CPL_SET_TCB_RPL = 0x3A, 90 CPL_RX_PKT = 0x3B, 91 CPL_TAG_READ_RPL = 0x3C, 92 CPL_HIT_NOTIFY = 0x3D, 93 CPL_PKT_NOTIFY = 0x3E, 94 CPL_RX_DDP_COMPLETE = 0x3F, 95 96 CPL_ACT_ESTABLISH = 0x40, 97 CPL_PASS_ESTABLISH = 0x41, 98 CPL_RX_DATA_DDP = 0x42, 99 CPL_SMT_READ_RPL = 0x43, 100 CPL_PASS_ACCEPT_REQ = 0x44, 101 CPL_RX_ISCSI_CMP = 0x45, 102 CPL_RX_FCOE_DDP = 0x46, 103 CPL_FCOE_HDR = 0x47, 104 CPL_T5_TRACE_PKT = 0x48, 105 CPL_RX_ISCSI_DDP = 0x49, 106 CPL_RX_FCOE_DIF = 0x4A, 107 CPL_RX_DATA_DIF = 0x4B, 108 CPL_ERR_NOTIFY = 0x4D, 109 CPL_RX_TLS_CMP = 0x4E, 110 111 CPL_RDMA_READ_REQ = 0x60, 112 CPL_RX_ISCSI_DIF = 0x60, 113 114 CPL_SET_LE_REQ = 0x80, 115 CPL_PASS_OPEN_REQ6 = 0x81, 116 CPL_ACT_OPEN_REQ6 = 0x83, 117 CPL_TX_TLS_PDU = 0x88, 118 CPL_TX_TLS_SFO = 0x89, 119 120 CPL_TX_SEC_PDU = 0x8A, 121 CPL_TX_TLS_ACK = 0x8B, 122 123 CPL_RDMA_TERMINATE = 0xA2, 124 CPL_RDMA_WRITE = 0xA4, 125 CPL_SGE_EGR_UPDATE = 0xA5, 126 CPL_SET_LE_RPL = 0xA6, 127 CPL_FW2_MSG = 0xA7, 128 CPL_FW2_PLD = 0xA8, 129 CPL_T5_RDMA_READ_REQ = 0xA9, 130 CPL_RDMA_ATOMIC_REQ = 0xAA, 131 CPL_RDMA_ATOMIC_RPL = 0xAB, 132 CPL_RDMA_IMM_DATA = 0xAC, 133 CPL_RDMA_IMM_DATA_SE = 0xAD, 134 CPL_RX_MPS_PKT = 0xAF, 135 136 CPL_TRACE_PKT = 0xB0, 137 CPL_RX2TX_DATA = 0xB1, 138 CPL_TLS_DATA = 0xB1, 139 CPL_ISCSI_DATA = 0xB2, 140 CPL_FCOE_DATA = 0xB3, 141 142 CPL_FW4_MSG = 0xC0, 143 CPL_FW4_PLD = 0xC1, 144 CPL_FW4_ACK = 0xC3, 145 CPL_SRQ_TABLE_RPL = 0xCC, 146 CPL_RX_PHYS_DSGL = 0xD0, 147 148 CPL_FW6_MSG = 0xE0, 149 CPL_FW6_PLD = 0xE1, 150 CPL_TX_TNL_LSO = 0xEC, 151 CPL_TX_PKT_LSO = 0xED, 152 CPL_TX_PKT_XT = 0xEE, 153 154 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 155 }; 156 157 enum CPL_error { 158 CPL_ERR_NONE = 0, 159 CPL_ERR_TCAM_PARITY = 1, 160 CPL_ERR_TCAM_MISS = 2, 161 CPL_ERR_TCAM_FULL = 3, 162 CPL_ERR_BAD_LENGTH = 15, 163 CPL_ERR_BAD_ROUTE = 18, 164 CPL_ERR_CONN_RESET = 20, 165 CPL_ERR_CONN_EXIST_SYNRECV = 21, 166 CPL_ERR_CONN_EXIST = 22, 167 CPL_ERR_ARP_MISS = 23, 168 CPL_ERR_BAD_SYN = 24, 169 CPL_ERR_CONN_TIMEDOUT = 30, 170 CPL_ERR_XMIT_TIMEDOUT = 31, 171 CPL_ERR_PERSIST_TIMEDOUT = 32, 172 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 173 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 174 CPL_ERR_RTX_NEG_ADVICE = 35, 175 CPL_ERR_PERSIST_NEG_ADVICE = 36, 176 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 177 CPL_ERR_WAIT_ARP_RPL = 41, 178 CPL_ERR_ABORT_FAILED = 42, 179 CPL_ERR_IWARP_FLM = 50, 180 CPL_CONTAINS_READ_RPL = 60, 181 CPL_CONTAINS_WRITE_RPL = 61, 182 }; 183 184 /* 185 * Some of the error codes above implicitly indicate that there is no TID 186 * allocated with the result of an ACT_OPEN. We use this predicate to make 187 * that explicit. 188 */ 189 static inline int act_open_has_tid(int status) 190 { 191 return (status != CPL_ERR_TCAM_PARITY && 192 status != CPL_ERR_TCAM_MISS && 193 status != CPL_ERR_TCAM_FULL && 194 status != CPL_ERR_CONN_EXIST_SYNRECV && 195 status != CPL_ERR_CONN_EXIST); 196 } 197 198 enum { 199 CPL_CONN_POLICY_AUTO = 0, 200 CPL_CONN_POLICY_ASK = 1, 201 CPL_CONN_POLICY_FILTER = 2, 202 CPL_CONN_POLICY_DENY = 3 203 }; 204 205 enum { 206 ULP_MODE_NONE = 0, 207 ULP_MODE_ISCSI = 2, 208 ULP_MODE_RDMA = 4, 209 ULP_MODE_TCPDDP = 5, 210 ULP_MODE_FCOE = 6, 211 ULP_MODE_TLS = 8, 212 }; 213 214 enum { 215 ULP_CRC_HEADER = 1 << 0, 216 ULP_CRC_DATA = 1 << 1 217 }; 218 219 enum { 220 CPL_PASS_OPEN_ACCEPT, 221 CPL_PASS_OPEN_REJECT, 222 CPL_PASS_OPEN_ACCEPT_TNL 223 }; 224 225 enum { 226 CPL_ABORT_SEND_RST = 0, 227 CPL_ABORT_NO_RST, 228 }; 229 230 enum { /* TX_PKT_XT checksum types */ 231 TX_CSUM_TCP = 0, 232 TX_CSUM_UDP = 1, 233 TX_CSUM_CRC16 = 4, 234 TX_CSUM_CRC32 = 5, 235 TX_CSUM_CRC32C = 6, 236 TX_CSUM_FCOE = 7, 237 TX_CSUM_TCPIP = 8, 238 TX_CSUM_UDPIP = 9, 239 TX_CSUM_TCPIP6 = 10, 240 TX_CSUM_UDPIP6 = 11, 241 TX_CSUM_IP = 12, 242 }; 243 244 enum { /* packet type in CPL_RX_PKT */ 245 PKTYPE_XACT_UCAST = 0, 246 PKTYPE_HASH_UCAST = 1, 247 PKTYPE_XACT_MCAST = 2, 248 PKTYPE_HASH_MCAST = 3, 249 PKTYPE_PROMISC = 4, 250 PKTYPE_HPROMISC = 5, 251 PKTYPE_BCAST = 6 252 }; 253 254 enum { /* DMAC type in CPL_RX_PKT */ 255 DATYPE_UCAST, 256 DATYPE_MCAST, 257 DATYPE_BCAST 258 }; 259 260 enum { /* TCP congestion control algorithms */ 261 CONG_ALG_RENO, 262 CONG_ALG_TAHOE, 263 CONG_ALG_NEWRENO, 264 CONG_ALG_HIGHSPEED 265 }; 266 267 enum { /* RSS hash type */ 268 RSS_HASH_NONE = 0, /* no hash computed */ 269 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 270 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 271 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 272 }; 273 274 enum { /* LE commands */ 275 LE_CMD_READ = 0x4, 276 LE_CMD_WRITE = 0xb 277 }; 278 279 enum { /* LE request size */ 280 LE_SZ_NONE = 0, 281 LE_SZ_33 = 1, 282 LE_SZ_66 = 2, 283 LE_SZ_132 = 3, 284 LE_SZ_264 = 4, 285 LE_SZ_528 = 5 286 }; 287 288 union opcode_tid { 289 __be32 opcode_tid; 290 __u8 opcode; 291 }; 292 293 #define S_CPL_OPCODE 24 294 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 295 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 296 #define G_TID(x) ((x) & 0xFFFFFF) 297 298 /* tid is assumed to be 24-bits */ 299 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 300 301 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 302 303 /* extract the TID from a CPL command */ 304 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 305 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 306 307 /* partitioning of TID fields that also carry a queue id */ 308 #define S_TID_TID 0 309 #define M_TID_TID 0x3fff 310 #define V_TID_TID(x) ((x) << S_TID_TID) 311 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 312 313 #define S_TID_QID 14 314 #define M_TID_QID 0x3ff 315 #define V_TID_QID(x) ((x) << S_TID_QID) 316 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 317 318 union opcode_info { 319 __be64 opcode_info; 320 __u8 opcode; 321 }; 322 323 struct tcp_options { 324 __be16 mss; 325 __u8 wsf; 326 #if defined(__LITTLE_ENDIAN_BITFIELD) 327 __u8 :4; 328 __u8 unknown:1; 329 __u8 ecn:1; 330 __u8 sack:1; 331 __u8 tstamp:1; 332 #else 333 __u8 tstamp:1; 334 __u8 sack:1; 335 __u8 ecn:1; 336 __u8 unknown:1; 337 __u8 :4; 338 #endif 339 }; 340 341 struct rss_header { 342 __u8 opcode; 343 #if defined(__LITTLE_ENDIAN_BITFIELD) 344 __u8 channel:2; 345 __u8 filter_hit:1; 346 __u8 filter_tid:1; 347 __u8 hash_type:2; 348 __u8 ipv6:1; 349 __u8 send2fw:1; 350 #else 351 __u8 send2fw:1; 352 __u8 ipv6:1; 353 __u8 hash_type:2; 354 __u8 filter_tid:1; 355 __u8 filter_hit:1; 356 __u8 channel:2; 357 #endif 358 __be16 qid; 359 __be32 hash_val; 360 }; 361 362 #define S_HASHTYPE 20 363 #define M_HASHTYPE 0x3 364 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 365 366 #define S_QNUM 0 367 #define M_QNUM 0xFFFF 368 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 369 370 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 371 # define RSS_HDR struct rss_header rss_hdr; 372 #else 373 # define RSS_HDR 374 #endif 375 376 #ifndef CHELSIO_FW 377 struct work_request_hdr { 378 __be32 wr_hi; 379 __be32 wr_mid; 380 __be64 wr_lo; 381 }; 382 383 /* wr_mid fields */ 384 #define S_WR_LEN16 0 385 #define M_WR_LEN16 0xFF 386 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 387 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 388 389 /* wr_hi fields */ 390 #define S_WR_OP 24 391 #define M_WR_OP 0xFF 392 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 393 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 394 395 # define WR_HDR struct work_request_hdr wr 396 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 397 #else 398 # define WR_HDR 399 # define WR_HDR_SIZE 0 400 #endif 401 402 /* option 0 fields */ 403 #define S_ACCEPT_MODE 0 404 #define M_ACCEPT_MODE 0x3 405 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 406 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 407 408 #define S_TX_CHAN 2 409 #define M_TX_CHAN 0x3 410 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 411 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 412 413 #define S_NO_CONG 4 414 #define V_NO_CONG(x) ((x) << S_NO_CONG) 415 #define F_NO_CONG V_NO_CONG(1U) 416 417 #define S_DELACK 5 418 #define V_DELACK(x) ((x) << S_DELACK) 419 #define F_DELACK V_DELACK(1U) 420 421 #define S_INJECT_TIMER 6 422 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 423 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 424 425 #define S_NON_OFFLOAD 7 426 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 427 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 428 429 #define S_ULP_MODE 8 430 #define M_ULP_MODE 0xF 431 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 432 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 433 434 #define S_RCV_BUFSIZ 12 435 #define M_RCV_BUFSIZ 0x3FFU 436 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 437 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 438 439 #define S_DSCP 22 440 #define M_DSCP 0x3F 441 #define V_DSCP(x) ((x) << S_DSCP) 442 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 443 444 #define S_SMAC_SEL 28 445 #define M_SMAC_SEL 0xFF 446 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 447 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 448 449 #define S_L2T_IDX 36 450 #define M_L2T_IDX 0xFFF 451 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 452 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 453 454 #define S_TCAM_BYPASS 48 455 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 456 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 457 458 #define S_NAGLE 49 459 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 460 #define F_NAGLE V_NAGLE(1ULL) 461 462 #define S_WND_SCALE 50 463 #define M_WND_SCALE 0xF 464 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 465 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 466 467 #define S_KEEP_ALIVE 54 468 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 469 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 470 471 #define S_MAX_RT 55 472 #define M_MAX_RT 0xF 473 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 474 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 475 476 #define S_MAX_RT_OVERRIDE 59 477 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 478 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 479 480 #define S_MSS_IDX 60 481 #define M_MSS_IDX 0xF 482 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 483 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 484 485 /* option 1 fields */ 486 #define S_SYN_RSS_ENABLE 0 487 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 488 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 489 490 #define S_SYN_RSS_USE_HASH 1 491 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 492 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 493 494 #define S_SYN_RSS_QUEUE 2 495 #define M_SYN_RSS_QUEUE 0x3FF 496 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 497 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 498 499 #define S_LISTEN_INTF 12 500 #define M_LISTEN_INTF 0xFF 501 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 502 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 503 504 #define S_LISTEN_FILTER 20 505 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 506 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 507 508 #define S_SYN_DEFENSE 21 509 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 510 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 511 512 #define S_CONN_POLICY 22 513 #define M_CONN_POLICY 0x3 514 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 515 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 516 517 #define S_T5_FILT_INFO 24 518 #define M_T5_FILT_INFO 0xffffffffffULL 519 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 520 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 521 522 #define S_FILT_INFO 28 523 #define M_FILT_INFO 0xfffffffffULL 524 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 525 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 526 527 /* option 2 fields */ 528 #define S_RSS_QUEUE 0 529 #define M_RSS_QUEUE 0x3FF 530 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 531 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 532 533 #define S_RSS_QUEUE_VALID 10 534 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 535 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 536 537 #define S_RX_COALESCE_VALID 11 538 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 539 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 540 541 #define S_RX_COALESCE 12 542 #define M_RX_COALESCE 0x3 543 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 544 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 545 546 #define S_CONG_CNTRL 14 547 #define M_CONG_CNTRL 0x3 548 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 549 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 550 551 #define S_PACE 16 552 #define M_PACE 0x3 553 #define V_PACE(x) ((x) << S_PACE) 554 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 555 556 #define S_CONG_CNTRL_VALID 18 557 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 558 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 559 560 #define S_T5_ISS 18 561 #define V_T5_ISS(x) ((x) << S_T5_ISS) 562 #define F_T5_ISS V_T5_ISS(1U) 563 564 #define S_PACE_VALID 19 565 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 566 #define F_PACE_VALID V_PACE_VALID(1U) 567 568 #define S_RX_FC_DISABLE 20 569 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 570 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 571 572 #define S_RX_FC_DDP 21 573 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 574 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 575 576 #define S_RX_FC_VALID 22 577 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 578 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 579 580 #define S_TX_QUEUE 23 581 #define M_TX_QUEUE 0x7 582 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 583 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 584 585 #define S_RX_CHANNEL 26 586 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 587 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 588 589 #define S_CCTRL_ECN 27 590 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 591 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 592 593 #define S_WND_SCALE_EN 28 594 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 595 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 596 597 #define S_TSTAMPS_EN 29 598 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 599 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 600 601 #define S_SACK_EN 30 602 #define V_SACK_EN(x) ((x) << S_SACK_EN) 603 #define F_SACK_EN V_SACK_EN(1U) 604 605 #define S_T5_OPT_2_VALID 31 606 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 607 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 608 609 struct cpl_pass_open_req { 610 WR_HDR; 611 union opcode_tid ot; 612 __be16 local_port; 613 __be16 peer_port; 614 __be32 local_ip; 615 __be32 peer_ip; 616 __be64 opt0; 617 __be64 opt1; 618 }; 619 620 struct cpl_pass_open_req6 { 621 WR_HDR; 622 union opcode_tid ot; 623 __be16 local_port; 624 __be16 peer_port; 625 __be64 local_ip_hi; 626 __be64 local_ip_lo; 627 __be64 peer_ip_hi; 628 __be64 peer_ip_lo; 629 __be64 opt0; 630 __be64 opt1; 631 }; 632 633 struct cpl_pass_open_rpl { 634 RSS_HDR 635 union opcode_tid ot; 636 __u8 rsvd[3]; 637 __u8 status; 638 }; 639 640 struct cpl_pass_establish { 641 RSS_HDR 642 union opcode_tid ot; 643 __be32 rsvd; 644 __be32 tos_stid; 645 __be16 mac_idx; 646 __be16 tcp_opt; 647 __be32 snd_isn; 648 __be32 rcv_isn; 649 }; 650 651 /* cpl_pass_establish.tos_stid fields */ 652 #define S_PASS_OPEN_TID 0 653 #define M_PASS_OPEN_TID 0xFFFFFF 654 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 655 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 656 657 #define S_PASS_OPEN_TOS 24 658 #define M_PASS_OPEN_TOS 0xFF 659 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 660 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 661 662 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 663 #define S_TCPOPT_WSCALE_OK 5 664 #define M_TCPOPT_WSCALE_OK 0x1 665 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 666 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 667 668 #define S_TCPOPT_SACK 6 669 #define M_TCPOPT_SACK 0x1 670 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 671 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 672 673 #define S_TCPOPT_TSTAMP 7 674 #define M_TCPOPT_TSTAMP 0x1 675 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 676 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 677 678 #define S_TCPOPT_SND_WSCALE 8 679 #define M_TCPOPT_SND_WSCALE 0xF 680 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 681 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 682 683 #define S_TCPOPT_MSS 12 684 #define M_TCPOPT_MSS 0xF 685 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 686 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 687 688 struct cpl_pass_accept_req { 689 RSS_HDR 690 union opcode_tid ot; 691 __be16 rsvd; 692 __be16 len; 693 __be32 hdr_len; 694 __be16 vlan; 695 __be16 l2info; 696 __be32 tos_stid; 697 struct tcp_options tcpopt; 698 }; 699 700 /* cpl_pass_accept_req.hdr_len fields */ 701 #define S_SYN_RX_CHAN 0 702 #define M_SYN_RX_CHAN 0xF 703 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 704 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 705 706 #define S_TCP_HDR_LEN 10 707 #define M_TCP_HDR_LEN 0x3F 708 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 709 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 710 711 #define S_T6_TCP_HDR_LEN 8 712 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 713 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 714 715 #define S_IP_HDR_LEN 16 716 #define M_IP_HDR_LEN 0x3FF 717 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 718 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 719 720 #define S_T6_IP_HDR_LEN 14 721 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 722 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 723 724 #define S_ETH_HDR_LEN 26 725 #define M_ETH_HDR_LEN 0x3F 726 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 727 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 728 729 #define S_T6_ETH_HDR_LEN 24 730 #define M_T6_ETH_HDR_LEN 0xFF 731 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 732 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 733 734 /* cpl_pass_accept_req.l2info fields */ 735 #define S_SYN_MAC_IDX 0 736 #define M_SYN_MAC_IDX 0x1FF 737 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 738 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 739 740 #define S_SYN_XACT_MATCH 9 741 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 742 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 743 744 #define S_SYN_INTF 12 745 #define M_SYN_INTF 0xF 746 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 747 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 748 749 struct cpl_pass_accept_rpl { 750 WR_HDR; 751 union opcode_tid ot; 752 __be32 opt2; 753 __be64 opt0; 754 }; 755 756 struct cpl_t5_pass_accept_rpl { 757 WR_HDR; 758 union opcode_tid ot; 759 __be32 opt2; 760 __be64 opt0; 761 __be32 iss; 762 union { 763 __be32 rsvd; /* T5 */ 764 __be32 opt3; /* T6 */ 765 } u; 766 }; 767 768 struct cpl_act_open_req { 769 WR_HDR; 770 union opcode_tid ot; 771 __be16 local_port; 772 __be16 peer_port; 773 __be32 local_ip; 774 __be32 peer_ip; 775 __be64 opt0; 776 __be32 params; 777 __be32 opt2; 778 }; 779 780 #define S_FILTER_TUPLE 24 781 #define M_FILTER_TUPLE 0xFFFFFFFFFF 782 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 783 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 784 struct cpl_t5_act_open_req { 785 WR_HDR; 786 union opcode_tid ot; 787 __be16 local_port; 788 __be16 peer_port; 789 __be32 local_ip; 790 __be32 peer_ip; 791 __be64 opt0; 792 __be32 iss; 793 __be32 opt2; 794 __be64 params; 795 }; 796 797 struct cpl_t6_act_open_req { 798 WR_HDR; 799 union opcode_tid ot; 800 __be16 local_port; 801 __be16 peer_port; 802 __be32 local_ip; 803 __be32 peer_ip; 804 __be64 opt0; 805 __be32 iss; 806 __be32 opt2; 807 __be64 params; 808 __be32 rsvd2; 809 __be32 opt3; 810 }; 811 812 /* cpl_{t5,t6}_act_open_req.params field */ 813 #define S_AOPEN_FCOEMASK 0 814 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 815 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 816 817 struct cpl_act_open_req6 { 818 WR_HDR; 819 union opcode_tid ot; 820 __be16 local_port; 821 __be16 peer_port; 822 __be64 local_ip_hi; 823 __be64 local_ip_lo; 824 __be64 peer_ip_hi; 825 __be64 peer_ip_lo; 826 __be64 opt0; 827 __be32 params; 828 __be32 opt2; 829 }; 830 831 struct cpl_t5_act_open_req6 { 832 WR_HDR; 833 union opcode_tid ot; 834 __be16 local_port; 835 __be16 peer_port; 836 __be64 local_ip_hi; 837 __be64 local_ip_lo; 838 __be64 peer_ip_hi; 839 __be64 peer_ip_lo; 840 __be64 opt0; 841 __be32 iss; 842 __be32 opt2; 843 __be64 params; 844 }; 845 846 struct cpl_t6_act_open_req6 { 847 WR_HDR; 848 union opcode_tid ot; 849 __be16 local_port; 850 __be16 peer_port; 851 __be64 local_ip_hi; 852 __be64 local_ip_lo; 853 __be64 peer_ip_hi; 854 __be64 peer_ip_lo; 855 __be64 opt0; 856 __be32 iss; 857 __be32 opt2; 858 __be64 params; 859 __be32 rsvd2; 860 __be32 opt3; 861 }; 862 863 struct cpl_act_open_rpl { 864 RSS_HDR 865 union opcode_tid ot; 866 __be32 atid_status; 867 }; 868 869 /* cpl_act_open_rpl.atid_status fields */ 870 #define S_AOPEN_STATUS 0 871 #define M_AOPEN_STATUS 0xFF 872 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 873 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 874 875 #define S_AOPEN_ATID 8 876 #define M_AOPEN_ATID 0xFFFFFF 877 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 878 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 879 880 struct cpl_act_establish { 881 RSS_HDR 882 union opcode_tid ot; 883 __be32 rsvd; 884 __be32 tos_atid; 885 __be16 mac_idx; 886 __be16 tcp_opt; 887 __be32 snd_isn; 888 __be32 rcv_isn; 889 }; 890 891 struct cpl_get_tcb { 892 WR_HDR; 893 union opcode_tid ot; 894 __be16 reply_ctrl; 895 __be16 cookie; 896 }; 897 898 /* cpl_get_tcb.reply_ctrl fields */ 899 #define S_QUEUENO 0 900 #define M_QUEUENO 0x3FF 901 #define V_QUEUENO(x) ((x) << S_QUEUENO) 902 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 903 904 #define S_REPLY_CHAN 14 905 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 906 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 907 908 #define S_NO_REPLY 15 909 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 910 #define F_NO_REPLY V_NO_REPLY(1U) 911 912 struct cpl_get_tcb_rpl { 913 RSS_HDR 914 union opcode_tid ot; 915 __u8 cookie; 916 __u8 status; 917 __be16 len; 918 }; 919 920 struct cpl_set_tcb { 921 WR_HDR; 922 union opcode_tid ot; 923 __be16 reply_ctrl; 924 __be16 cookie; 925 }; 926 927 struct cpl_set_tcb_field { 928 WR_HDR; 929 union opcode_tid ot; 930 __be16 reply_ctrl; 931 __be16 word_cookie; 932 __be64 mask; 933 __be64 val; 934 }; 935 936 struct cpl_set_tcb_field_core { 937 union opcode_tid ot; 938 __be16 reply_ctrl; 939 __be16 word_cookie; 940 __be64 mask; 941 __be64 val; 942 }; 943 944 /* cpl_set_tcb_field.word_cookie fields */ 945 #define S_WORD 0 946 #define M_WORD 0x1F 947 #define V_WORD(x) ((x) << S_WORD) 948 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 949 950 #define S_COOKIE 5 951 #define M_COOKIE 0x7 952 #define V_COOKIE(x) ((x) << S_COOKIE) 953 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 954 955 struct cpl_set_tcb_rpl { 956 RSS_HDR 957 union opcode_tid ot; 958 __be16 rsvd; 959 __u8 cookie; 960 __u8 status; 961 __be64 oldval; 962 }; 963 964 struct cpl_close_con_req { 965 WR_HDR; 966 union opcode_tid ot; 967 __be32 rsvd; 968 }; 969 970 struct cpl_close_con_rpl { 971 RSS_HDR 972 union opcode_tid ot; 973 __u8 rsvd[3]; 974 __u8 status; 975 __be32 snd_nxt; 976 __be32 rcv_nxt; 977 }; 978 979 struct cpl_close_listsvr_req { 980 WR_HDR; 981 union opcode_tid ot; 982 __be16 reply_ctrl; 983 __be16 rsvd; 984 }; 985 986 /* additional cpl_close_listsvr_req.reply_ctrl field */ 987 #define S_LISTSVR_IPV6 14 988 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 989 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 990 991 struct cpl_close_listsvr_rpl { 992 RSS_HDR 993 union opcode_tid ot; 994 __u8 rsvd[3]; 995 __u8 status; 996 }; 997 998 struct cpl_abort_req_rss { 999 RSS_HDR 1000 union opcode_tid ot; 1001 __u8 rsvd[3]; 1002 __u8 status; 1003 }; 1004 1005 struct cpl_abort_req_rss6 { 1006 RSS_HDR 1007 union opcode_tid ot; 1008 __u32 srqidx_status; 1009 }; 1010 1011 #define S_ABORT_RSS_STATUS 0 1012 #define M_ABORT_RSS_STATUS 0xff 1013 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1014 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1015 1016 #define S_ABORT_RSS_SRQIDX 8 1017 #define M_ABORT_RSS_SRQIDX 0xffffff 1018 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1019 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1020 1021 1022 /* cpl_abort_req status command code in case of T6, 1023 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1024 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1025 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1026 */ 1027 struct cpl_abort_req { 1028 WR_HDR; 1029 union opcode_tid ot; 1030 __be32 rsvd0; 1031 __u8 rsvd1; 1032 __u8 cmd; 1033 __u8 rsvd2[6]; 1034 }; 1035 1036 struct cpl_abort_rpl_rss { 1037 RSS_HDR 1038 union opcode_tid ot; 1039 __u8 rsvd[3]; 1040 __u8 status; 1041 }; 1042 1043 struct cpl_abort_rpl_rss6 { 1044 RSS_HDR 1045 union opcode_tid ot; 1046 __u32 srqidx_status; 1047 }; 1048 1049 struct cpl_abort_rpl { 1050 WR_HDR; 1051 union opcode_tid ot; 1052 __be32 rsvd0; 1053 __u8 rsvd1; 1054 __u8 cmd; 1055 __u8 rsvd2[6]; 1056 }; 1057 1058 struct cpl_peer_close { 1059 RSS_HDR 1060 union opcode_tid ot; 1061 __be32 rcv_nxt; 1062 }; 1063 1064 struct cpl_tid_release { 1065 WR_HDR; 1066 union opcode_tid ot; 1067 __be32 rsvd; 1068 }; 1069 1070 struct tx_data_wr { 1071 __be32 wr_hi; 1072 __be32 wr_lo; 1073 __be32 len; 1074 __be32 flags; 1075 __be32 sndseq; 1076 __be32 param; 1077 }; 1078 1079 /* tx_data_wr.flags fields */ 1080 #define S_TX_ACK_PAGES 21 1081 #define M_TX_ACK_PAGES 0x7 1082 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1083 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1084 1085 /* tx_data_wr.param fields */ 1086 #define S_TX_PORT 0 1087 #define M_TX_PORT 0x7 1088 #define V_TX_PORT(x) ((x) << S_TX_PORT) 1089 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1090 1091 #define S_TX_MSS 4 1092 #define M_TX_MSS 0xF 1093 #define V_TX_MSS(x) ((x) << S_TX_MSS) 1094 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1095 1096 #define S_TX_QOS 8 1097 #define M_TX_QOS 0xFF 1098 #define V_TX_QOS(x) ((x) << S_TX_QOS) 1099 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1100 1101 #define S_TX_SNDBUF 16 1102 #define M_TX_SNDBUF 0xFFFF 1103 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1104 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1105 1106 struct cpl_tx_data { 1107 union opcode_tid ot; 1108 __be32 len; 1109 __be32 rsvd; 1110 __be32 flags; 1111 }; 1112 1113 /* cpl_tx_data.flags fields */ 1114 #define S_TX_PROXY 5 1115 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1116 #define F_TX_PROXY V_TX_PROXY(1U) 1117 1118 #define S_TX_ULP_SUBMODE 6 1119 #define M_TX_ULP_SUBMODE 0xF 1120 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1121 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1122 1123 #define S_TX_ULP_MODE 10 1124 #define M_TX_ULP_MODE 0x7 1125 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1126 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1127 1128 #define S_TX_FORCE 13 1129 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1130 #define F_TX_FORCE V_TX_FORCE(1U) 1131 1132 #define S_TX_SHOVE 14 1133 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1134 #define F_TX_SHOVE V_TX_SHOVE(1U) 1135 1136 #define S_TX_MORE 15 1137 #define V_TX_MORE(x) ((x) << S_TX_MORE) 1138 #define F_TX_MORE V_TX_MORE(1U) 1139 1140 #define S_TX_URG 16 1141 #define V_TX_URG(x) ((x) << S_TX_URG) 1142 #define F_TX_URG V_TX_URG(1U) 1143 1144 #define S_TX_FLUSH 17 1145 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1146 #define F_TX_FLUSH V_TX_FLUSH(1U) 1147 1148 #define S_TX_SAVE 18 1149 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1150 #define F_TX_SAVE V_TX_SAVE(1U) 1151 1152 #define S_TX_TNL 19 1153 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1154 #define F_TX_TNL V_TX_TNL(1U) 1155 1156 #define S_T6_TX_FORCE 20 1157 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1158 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1159 1160 /* additional tx_data_wr.flags fields */ 1161 #define S_TX_CPU_IDX 0 1162 #define M_TX_CPU_IDX 0x3F 1163 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1164 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1165 1166 #define S_TX_CLOSE 17 1167 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1168 #define F_TX_CLOSE V_TX_CLOSE(1U) 1169 1170 #define S_TX_INIT 18 1171 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1172 #define F_TX_INIT V_TX_INIT(1U) 1173 1174 #define S_TX_IMM_ACK 19 1175 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1176 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1177 1178 #define S_TX_IMM_DMA 20 1179 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1180 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1181 1182 struct cpl_tx_data_ack { 1183 RSS_HDR 1184 union opcode_tid ot; 1185 __be32 snd_una; 1186 }; 1187 1188 struct cpl_wr_ack { /* XXX */ 1189 RSS_HDR 1190 union opcode_tid ot; 1191 __be16 credits; 1192 __be16 rsvd; 1193 __be32 snd_nxt; 1194 __be32 snd_una; 1195 }; 1196 1197 struct cpl_tx_pkt_core { 1198 __be32 ctrl0; 1199 __be16 pack; 1200 __be16 len; 1201 __be64 ctrl1; 1202 }; 1203 1204 struct cpl_tx_pkt { 1205 WR_HDR; 1206 struct cpl_tx_pkt_core c; 1207 }; 1208 1209 #define cpl_tx_pkt_xt cpl_tx_pkt 1210 1211 /* cpl_tx_pkt_core.ctrl0 fields */ 1212 #define S_TXPKT_VF 0 1213 #define M_TXPKT_VF 0xFF 1214 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1215 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1216 1217 #define S_TXPKT_PF 8 1218 #define M_TXPKT_PF 0x7 1219 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1220 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1221 1222 #define S_TXPKT_VF_VLD 11 1223 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1224 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1225 1226 #define S_TXPKT_OVLAN_IDX 12 1227 #define M_TXPKT_OVLAN_IDX 0xF 1228 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1229 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1230 1231 #define S_TXPKT_T5_OVLAN_IDX 12 1232 #define M_TXPKT_T5_OVLAN_IDX 0x7 1233 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1234 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1235 M_TXPKT_T5_OVLAN_IDX) 1236 1237 #define S_TXPKT_INTF 16 1238 #define M_TXPKT_INTF 0xF 1239 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1240 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1241 1242 #define S_TXPKT_SPECIAL_STAT 20 1243 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1244 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1245 1246 #define S_TXPKT_T5_FCS_DIS 21 1247 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1248 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1249 1250 #define S_TXPKT_INS_OVLAN 21 1251 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1252 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1253 1254 #define S_TXPKT_T5_INS_OVLAN 15 1255 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1256 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1257 1258 #define S_TXPKT_STAT_DIS 22 1259 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1260 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1261 1262 #define S_TXPKT_LOOPBACK 23 1263 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1264 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1265 1266 #define S_TXPKT_TSTAMP 23 1267 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1268 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1269 1270 #define S_TXPKT_OPCODE 24 1271 #define M_TXPKT_OPCODE 0xFF 1272 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1273 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1274 1275 /* cpl_tx_pkt_core.ctrl1 fields */ 1276 #define S_TXPKT_SA_IDX 0 1277 #define M_TXPKT_SA_IDX 0xFFF 1278 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1279 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1280 1281 #define S_TXPKT_CSUM_END 12 1282 #define M_TXPKT_CSUM_END 0xFF 1283 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1284 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1285 1286 #define S_TXPKT_CSUM_START 20 1287 #define M_TXPKT_CSUM_START 0x3FF 1288 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1289 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1290 1291 #define S_TXPKT_IPHDR_LEN 20 1292 #define M_TXPKT_IPHDR_LEN 0x3FFF 1293 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1294 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1295 1296 #define M_T6_TXPKT_IPHDR_LEN 0xFFF 1297 #define G_T6_TXPKT_IPHDR_LEN(x) \ 1298 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1299 1300 #define S_TXPKT_CSUM_LOC 30 1301 #define M_TXPKT_CSUM_LOC 0x3FF 1302 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1303 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1304 1305 #define S_TXPKT_ETHHDR_LEN 34 1306 #define M_TXPKT_ETHHDR_LEN 0x3F 1307 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1308 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1309 1310 #define S_T6_TXPKT_ETHHDR_LEN 32 1311 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 1312 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1313 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 1314 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1315 1316 #define S_TXPKT_CSUM_TYPE 40 1317 #define M_TXPKT_CSUM_TYPE 0xF 1318 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1319 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1320 1321 #define S_TXPKT_VLAN 44 1322 #define M_TXPKT_VLAN 0xFFFF 1323 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1324 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1325 1326 #define S_TXPKT_VLAN_VLD 60 1327 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1328 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1329 1330 #define S_TXPKT_IPSEC 61 1331 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1332 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1333 1334 #define S_TXPKT_IPCSUM_DIS 62 1335 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1336 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1337 1338 #define S_TXPKT_L4CSUM_DIS 63 1339 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1340 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1341 1342 struct cpl_tx_pkt_lso_core { 1343 __be32 lso_ctrl; 1344 __be16 ipid_ofst; 1345 __be16 mss; 1346 __be32 seqno_offset; 1347 __be32 len; 1348 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1349 }; 1350 1351 struct cpl_tx_pkt_lso { 1352 WR_HDR; 1353 struct cpl_tx_pkt_lso_core c; 1354 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1355 }; 1356 1357 struct cpl_tx_pkt_ufo_core { 1358 __be16 ethlen; 1359 __be16 iplen; 1360 __be16 udplen; 1361 __be16 mss; 1362 __be32 len; 1363 __be32 r1; 1364 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1365 }; 1366 1367 struct cpl_tx_pkt_ufo { 1368 WR_HDR; 1369 struct cpl_tx_pkt_ufo_core c; 1370 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1371 }; 1372 1373 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1374 #define S_LSO_TCPHDR_LEN 0 1375 #define M_LSO_TCPHDR_LEN 0xF 1376 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1377 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1378 1379 #define S_LSO_IPHDR_LEN 4 1380 #define M_LSO_IPHDR_LEN 0xFFF 1381 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1382 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1383 1384 #define S_LSO_ETHHDR_LEN 16 1385 #define M_LSO_ETHHDR_LEN 0xF 1386 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1387 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1388 1389 #define S_LSO_IPV6 20 1390 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1391 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1392 1393 #define S_LSO_OFLD_ENCAP 21 1394 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1395 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1396 1397 #define S_LSO_LAST_SLICE 22 1398 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1399 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1400 1401 #define S_LSO_FIRST_SLICE 23 1402 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1403 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1404 1405 #define S_LSO_OPCODE 24 1406 #define M_LSO_OPCODE 0xFF 1407 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1408 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1409 1410 #define S_LSO_T5_XFER_SIZE 0 1411 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1412 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1413 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1414 1415 /* cpl_tx_pkt_lso_core.mss fields */ 1416 #define S_LSO_MSS 0 1417 #define M_LSO_MSS 0x3FFF 1418 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1419 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1420 1421 #define S_LSO_IPID_SPLIT 15 1422 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1423 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1424 1425 struct cpl_tx_pkt_fso { 1426 WR_HDR; 1427 __be32 fso_ctrl; 1428 __be16 seqcnt_ofst; 1429 __be16 mtu; 1430 __be32 param_offset; 1431 __be32 len; 1432 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1433 }; 1434 1435 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1436 #define S_FSO_XCHG_CLASS 21 1437 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1438 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1439 1440 #define S_FSO_INITIATOR 20 1441 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1442 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1443 1444 #define S_FSO_FCHDR_LEN 12 1445 #define M_FSO_FCHDR_LEN 0xF 1446 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1447 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1448 1449 struct cpl_iscsi_hdr_no_rss { 1450 union opcode_tid ot; 1451 __be16 pdu_len_ddp; 1452 __be16 len; 1453 __be32 seq; 1454 __be16 urg; 1455 __u8 rsvd; 1456 __u8 status; 1457 }; 1458 1459 struct cpl_tx_data_iso { 1460 __be32 op_to_scsi; 1461 __u8 reserved1; 1462 __u8 ahs_len; 1463 __be16 mpdu; 1464 __be32 burst_size; 1465 __be32 len; 1466 __be32 reserved2_seglen_offset; 1467 __be32 datasn_offset; 1468 __be32 buffer_offset; 1469 __be32 reserved3; 1470 1471 /* encapsulated CPL_TX_DATA follows here */ 1472 }; 1473 1474 /* cpl_tx_data_iso.op_to_scsi fields */ 1475 #define S_CPL_TX_DATA_ISO_OP 24 1476 #define M_CPL_TX_DATA_ISO_OP 0xff 1477 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 1478 #define G_CPL_TX_DATA_ISO_OP(x) \ 1479 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 1480 1481 #define S_CPL_TX_DATA_ISO_FIRST 23 1482 #define M_CPL_TX_DATA_ISO_FIRST 0x1 1483 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 1484 #define G_CPL_TX_DATA_ISO_FIRST(x) \ 1485 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 1486 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 1487 1488 #define S_CPL_TX_DATA_ISO_LAST 22 1489 #define M_CPL_TX_DATA_ISO_LAST 0x1 1490 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 1491 #define G_CPL_TX_DATA_ISO_LAST(x) \ 1492 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 1493 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 1494 1495 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 1496 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 1497 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 1498 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 1499 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 1500 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 1501 1502 #define S_CPL_TX_DATA_ISO_HDRCRC 20 1503 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1 1504 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 1505 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 1506 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 1507 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 1508 1509 #define S_CPL_TX_DATA_ISO_PLDCRC 19 1510 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1 1511 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 1512 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 1513 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 1514 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 1515 1516 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18 1517 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 1518 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 1519 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 1520 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 1521 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 1522 1523 #define S_CPL_TX_DATA_ISO_SCSI 16 1524 #define M_CPL_TX_DATA_ISO_SCSI 0x3 1525 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 1526 #define G_CPL_TX_DATA_ISO_SCSI(x) \ 1527 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 1528 1529 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1530 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 1531 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 1532 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1533 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1534 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1535 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 1536 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1537 1538 struct cpl_iscsi_hdr { 1539 RSS_HDR 1540 union opcode_tid ot; 1541 __be16 pdu_len_ddp; 1542 __be16 len; 1543 __be32 seq; 1544 __be16 urg; 1545 __u8 rsvd; 1546 __u8 status; 1547 }; 1548 1549 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1550 #define S_ISCSI_PDU_LEN 0 1551 #define M_ISCSI_PDU_LEN 0x7FFF 1552 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1553 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1554 1555 #define S_ISCSI_DDP 15 1556 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1557 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1558 1559 struct cpl_iscsi_data { 1560 RSS_HDR 1561 union opcode_tid ot; 1562 __u8 rsvd0[2]; 1563 __be16 len; 1564 __be32 seq; 1565 __be16 urg; 1566 __u8 rsvd1; 1567 __u8 status; 1568 }; 1569 1570 struct cpl_rx_data { 1571 RSS_HDR 1572 union opcode_tid ot; 1573 __be16 rsvd; 1574 __be16 len; 1575 __be32 seq; 1576 __be16 urg; 1577 #if defined(__LITTLE_ENDIAN_BITFIELD) 1578 __u8 dack_mode:2; 1579 __u8 psh:1; 1580 __u8 heartbeat:1; 1581 __u8 ddp_off:1; 1582 __u8 :3; 1583 #else 1584 __u8 :3; 1585 __u8 ddp_off:1; 1586 __u8 heartbeat:1; 1587 __u8 psh:1; 1588 __u8 dack_mode:2; 1589 #endif 1590 __u8 status; 1591 }; 1592 1593 struct cpl_fcoe_hdr { 1594 RSS_HDR 1595 union opcode_tid ot; 1596 __be16 oxid; 1597 __be16 len; 1598 __be32 rctl_fctl; 1599 __u8 cs_ctl; 1600 __u8 df_ctl; 1601 __u8 sof; 1602 __u8 eof; 1603 __be16 seq_cnt; 1604 __u8 seq_id; 1605 __u8 type; 1606 __be32 param; 1607 }; 1608 1609 /* cpl_fcoe_hdr.rctl_fctl fields */ 1610 #define S_FCOE_FCHDR_RCTL 24 1611 #define M_FCOE_FCHDR_RCTL 0xff 1612 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 1613 #define G_FCOE_FCHDR_RCTL(x) \ 1614 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 1615 1616 #define S_FCOE_FCHDR_FCTL 0 1617 #define M_FCOE_FCHDR_FCTL 0xffffff 1618 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 1619 #define G_FCOE_FCHDR_FCTL(x) \ 1620 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 1621 1622 struct cpl_fcoe_data { 1623 RSS_HDR 1624 union opcode_tid ot; 1625 __u8 rsvd0[2]; 1626 __be16 len; 1627 __be32 seq; 1628 __u8 rsvd1[3]; 1629 __u8 status; 1630 }; 1631 1632 struct cpl_rx_urg_notify { 1633 RSS_HDR 1634 union opcode_tid ot; 1635 __be32 seq; 1636 }; 1637 1638 struct cpl_rx_urg_pkt { 1639 RSS_HDR 1640 union opcode_tid ot; 1641 __be16 rsvd; 1642 __be16 len; 1643 }; 1644 1645 struct cpl_rx_data_ack { 1646 WR_HDR; 1647 union opcode_tid ot; 1648 __be32 credit_dack; 1649 }; 1650 1651 struct cpl_rx_data_ack_core { 1652 union opcode_tid ot; 1653 __be32 credit_dack; 1654 }; 1655 1656 /* cpl_rx_data_ack.ack_seq fields */ 1657 #define S_RX_CREDITS 0 1658 #define M_RX_CREDITS 0x3FFFFFF 1659 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1660 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1661 1662 #define S_RX_MODULATE_TX 26 1663 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1664 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1665 1666 #define S_RX_MODULATE_RX 27 1667 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1668 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1669 1670 #define S_RX_FORCE_ACK 28 1671 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1672 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1673 1674 #define S_RX_DACK_MODE 29 1675 #define M_RX_DACK_MODE 0x3 1676 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1677 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1678 1679 #define S_RX_DACK_CHANGE 31 1680 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1681 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1682 1683 struct cpl_rx_ddp_complete { 1684 RSS_HDR 1685 union opcode_tid ot; 1686 __be32 ddp_report; 1687 __be32 rcv_nxt; 1688 __be32 rsvd; 1689 }; 1690 1691 struct cpl_rx_data_ddp { 1692 RSS_HDR 1693 union opcode_tid ot; 1694 __be16 urg; 1695 __be16 len; 1696 __be32 seq; 1697 union { 1698 __be32 nxt_seq; 1699 __be32 ddp_report; 1700 } u; 1701 __be32 ulp_crc; 1702 __be32 ddpvld; 1703 }; 1704 1705 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1706 1707 struct cpl_rx_fcoe_ddp { 1708 RSS_HDR 1709 union opcode_tid ot; 1710 __be16 rsvd; 1711 __be16 len; 1712 __be32 seq; 1713 __be32 ddp_report; 1714 __be32 ulp_crc; 1715 __be32 ddpvld; 1716 }; 1717 1718 struct cpl_rx_data_dif { 1719 RSS_HDR 1720 union opcode_tid ot; 1721 __be16 ddp_len; 1722 __be16 msg_len; 1723 __be32 seq; 1724 union { 1725 __be32 nxt_seq; 1726 __be32 ddp_report; 1727 } u; 1728 __be32 err_vec; 1729 __be32 ddpvld; 1730 }; 1731 1732 struct cpl_rx_iscsi_dif { 1733 RSS_HDR 1734 union opcode_tid ot; 1735 __be16 ddp_len; 1736 __be16 msg_len; 1737 __be32 seq; 1738 union { 1739 __be32 nxt_seq; 1740 __be32 ddp_report; 1741 } u; 1742 __be32 ulp_crc; 1743 __be32 ddpvld; 1744 __u8 rsvd0[8]; 1745 __be32 err_vec; 1746 __u8 rsvd1[4]; 1747 }; 1748 1749 struct cpl_rx_iscsi_cmp { 1750 RSS_HDR 1751 union opcode_tid ot; 1752 __be16 pdu_len_ddp; 1753 __be16 len; 1754 __be32 seq; 1755 __be16 urg; 1756 __u8 rsvd; 1757 __u8 status; 1758 __be32 ulp_crc; 1759 __be32 ddpvld; 1760 }; 1761 1762 struct cpl_rx_fcoe_dif { 1763 RSS_HDR 1764 union opcode_tid ot; 1765 __be16 ddp_len; 1766 __be16 msg_len; 1767 __be32 seq; 1768 __be32 ddp_report; 1769 __be32 err_vec; 1770 __be32 ddpvld; 1771 }; 1772 1773 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1774 #define S_DDP_VALID 15 1775 #define M_DDP_VALID 0x1FFFF 1776 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1777 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1778 1779 #define S_DDP_PPOD_MISMATCH 15 1780 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1781 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1782 1783 #define S_DDP_PDU 16 1784 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1785 #define F_DDP_PDU V_DDP_PDU(1U) 1786 1787 #define S_DDP_LLIMIT_ERR 17 1788 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1789 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1790 1791 #define S_DDP_PPOD_PARITY_ERR 18 1792 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1793 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1794 1795 #define S_DDP_PADDING_ERR 19 1796 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1797 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1798 1799 #define S_DDP_HDRCRC_ERR 20 1800 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1801 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1802 1803 #define S_DDP_DATACRC_ERR 21 1804 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1805 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1806 1807 #define S_DDP_INVALID_TAG 22 1808 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1809 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1810 1811 #define S_DDP_ULIMIT_ERR 23 1812 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1813 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1814 1815 #define S_DDP_OFFSET_ERR 24 1816 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1817 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1818 1819 #define S_DDP_COLOR_ERR 25 1820 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1821 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1822 1823 #define S_DDP_TID_MISMATCH 26 1824 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1825 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1826 1827 #define S_DDP_INVALID_PPOD 27 1828 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1829 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1830 1831 #define S_DDP_ULP_MODE 28 1832 #define M_DDP_ULP_MODE 0xF 1833 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1834 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1835 1836 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1837 #define S_DDP_OFFSET 0 1838 #define M_DDP_OFFSET 0xFFFFFF 1839 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1840 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1841 1842 #define S_DDP_DACK_MODE 24 1843 #define M_DDP_DACK_MODE 0x3 1844 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1845 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1846 1847 #define S_DDP_BUF_IDX 26 1848 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1849 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1850 1851 #define S_DDP_URG 27 1852 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1853 #define F_DDP_URG V_DDP_URG(1U) 1854 1855 #define S_DDP_PSH 28 1856 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1857 #define F_DDP_PSH V_DDP_PSH(1U) 1858 1859 #define S_DDP_BUF_COMPLETE 29 1860 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1861 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1862 1863 #define S_DDP_BUF_TIMED_OUT 30 1864 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1865 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1866 1867 #define S_DDP_INV 31 1868 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1869 #define F_DDP_INV V_DDP_INV(1U) 1870 1871 struct cpl_rx_pkt { 1872 RSS_HDR 1873 __u8 opcode; 1874 #if defined(__LITTLE_ENDIAN_BITFIELD) 1875 __u8 iff:4; 1876 __u8 csum_calc:1; 1877 __u8 ipmi_pkt:1; 1878 __u8 vlan_ex:1; 1879 __u8 ip_frag:1; 1880 #else 1881 __u8 ip_frag:1; 1882 __u8 vlan_ex:1; 1883 __u8 ipmi_pkt:1; 1884 __u8 csum_calc:1; 1885 __u8 iff:4; 1886 #endif 1887 __be16 csum; 1888 __be16 vlan; 1889 __be16 len; 1890 __be32 l2info; 1891 __be16 hdr_len; 1892 __be16 err_vec; 1893 }; 1894 1895 /* rx_pkt.l2info fields */ 1896 #define S_RX_ETHHDR_LEN 0 1897 #define M_RX_ETHHDR_LEN 0x1F 1898 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1899 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1900 1901 #define S_RX_T5_ETHHDR_LEN 0 1902 #define M_RX_T5_ETHHDR_LEN 0x3F 1903 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1904 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1905 1906 #define M_RX_T6_ETHHDR_LEN 0xFF 1907 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 1908 1909 #define S_RX_PKTYPE 5 1910 #define M_RX_PKTYPE 0x7 1911 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1912 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1913 1914 #define S_RX_T5_DATYPE 6 1915 #define M_RX_T5_DATYPE 0x3 1916 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1917 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1918 1919 #define S_RX_MACIDX 8 1920 #define M_RX_MACIDX 0x1FF 1921 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1922 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1923 1924 #define S_RX_T5_PKTYPE 17 1925 #define M_RX_T5_PKTYPE 0x7 1926 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1927 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1928 1929 #define S_RX_DATYPE 18 1930 #define M_RX_DATYPE 0x3 1931 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1932 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1933 1934 #define S_RXF_PSH 20 1935 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1936 #define F_RXF_PSH V_RXF_PSH(1U) 1937 1938 #define S_RXF_SYN 21 1939 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1940 #define F_RXF_SYN V_RXF_SYN(1U) 1941 1942 #define S_RXF_UDP 22 1943 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1944 #define F_RXF_UDP V_RXF_UDP(1U) 1945 1946 #define S_RXF_TCP 23 1947 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1948 #define F_RXF_TCP V_RXF_TCP(1U) 1949 1950 #define S_RXF_IP 24 1951 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1952 #define F_RXF_IP V_RXF_IP(1U) 1953 1954 #define S_RXF_IP6 25 1955 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1956 #define F_RXF_IP6 V_RXF_IP6(1U) 1957 1958 #define S_RXF_SYN_COOKIE 26 1959 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1960 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1961 1962 #define S_RXF_FCOE 26 1963 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1964 #define F_RXF_FCOE V_RXF_FCOE(1U) 1965 1966 #define S_RXF_LRO 27 1967 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1968 #define F_RXF_LRO V_RXF_LRO(1U) 1969 1970 #define S_RX_CHAN 28 1971 #define M_RX_CHAN 0xF 1972 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1973 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1974 1975 /* rx_pkt.hdr_len fields */ 1976 #define S_RX_TCPHDR_LEN 0 1977 #define M_RX_TCPHDR_LEN 0x3F 1978 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1979 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1980 1981 #define S_RX_IPHDR_LEN 6 1982 #define M_RX_IPHDR_LEN 0x3FF 1983 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1984 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1985 1986 /* rx_pkt.err_vec fields */ 1987 #define S_RXERR_OR 0 1988 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1989 #define F_RXERR_OR V_RXERR_OR(1U) 1990 1991 #define S_RXERR_MAC 1 1992 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1993 #define F_RXERR_MAC V_RXERR_MAC(1U) 1994 1995 #define S_RXERR_IPVERS 2 1996 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1997 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1998 1999 #define S_RXERR_FRAG 3 2000 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2001 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 2002 2003 #define S_RXERR_ATTACK 4 2004 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2005 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2006 2007 #define S_RXERR_ETHHDR_LEN 5 2008 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2009 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2010 2011 #define S_RXERR_IPHDR_LEN 6 2012 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2013 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2014 2015 #define S_RXERR_TCPHDR_LEN 7 2016 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2017 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2018 2019 #define S_RXERR_PKT_LEN 8 2020 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2021 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2022 2023 #define S_RXERR_TCP_OPT 9 2024 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2025 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2026 2027 #define S_RXERR_IPCSUM 12 2028 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2029 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2030 2031 #define S_RXERR_CSUM 13 2032 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2033 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 2034 2035 #define S_RXERR_PING 14 2036 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2037 #define F_RXERR_PING V_RXERR_PING(1U) 2038 2039 /* In T6, rx_pkt.err_vec indicates 2040 * RxError Error vector (16b) or 2041 * Encapsulating header length (8b), 2042 * Outer encapsulation type (2b) and 2043 * compressed error vector (6b) if CRxPktEnc is 2044 * enabled in TP_OUT_CONFIG 2045 */ 2046 2047 #define S_T6_COMPR_RXERR_VEC 0 2048 #define M_T6_COMPR_RXERR_VEC 0x3F 2049 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2050 #define G_T6_COMPR_RXERR_VEC(x) \ 2051 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2052 2053 #define S_T6_COMPR_RXERR_MAC 0 2054 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2055 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2056 2057 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2058 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2059 */ 2060 #define S_T6_COMPR_RXERR_LEN 1 2061 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2062 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2063 2064 #define S_T6_COMPR_RXERR_TCP_OPT 2 2065 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2066 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2067 2068 #define S_T6_COMPR_RXERR_IPV6_EXT 3 2069 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2070 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2071 2072 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2073 #define S_T6_COMPR_RXERR_SUM 4 2074 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2075 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2076 2077 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2078 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2079 */ 2080 #define S_T6_COMPR_RXERR_MISC 5 2081 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2082 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2083 2084 #define S_T6_RX_TNL_TYPE 6 2085 #define M_T6_RX_TNL_TYPE 0x3 2086 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2087 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2088 2089 #define RX_PKT_TNL_TYPE_NVGRE 1 2090 #define RX_PKT_TNL_TYPE_VXLAN 2 2091 #define RX_PKT_TNL_TYPE_GENEVE 3 2092 2093 #define S_T6_RX_TNLHDR_LEN 8 2094 #define M_T6_RX_TNLHDR_LEN 0xFF 2095 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2096 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2097 2098 struct cpl_trace_pkt { 2099 RSS_HDR 2100 __u8 opcode; 2101 __u8 intf; 2102 #if defined(__LITTLE_ENDIAN_BITFIELD) 2103 __u8 runt:4; 2104 __u8 filter_hit:4; 2105 __u8 :6; 2106 __u8 err:1; 2107 __u8 trunc:1; 2108 #else 2109 __u8 filter_hit:4; 2110 __u8 runt:4; 2111 __u8 trunc:1; 2112 __u8 err:1; 2113 __u8 :6; 2114 #endif 2115 __be16 rsvd; 2116 __be16 len; 2117 __be64 tstamp; 2118 }; 2119 2120 struct cpl_t5_trace_pkt { 2121 RSS_HDR 2122 __u8 opcode; 2123 __u8 intf; 2124 #if defined(__LITTLE_ENDIAN_BITFIELD) 2125 __u8 runt:4; 2126 __u8 filter_hit:4; 2127 __u8 :6; 2128 __u8 err:1; 2129 __u8 trunc:1; 2130 #else 2131 __u8 filter_hit:4; 2132 __u8 runt:4; 2133 __u8 trunc:1; 2134 __u8 err:1; 2135 __u8 :6; 2136 #endif 2137 __be16 rsvd; 2138 __be16 len; 2139 __be64 tstamp; 2140 __be64 rsvd1; 2141 }; 2142 2143 struct cpl_rte_delete_req { 2144 WR_HDR; 2145 union opcode_tid ot; 2146 __be32 params; 2147 }; 2148 2149 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2150 #define S_RTE_REQ_LUT_IX 8 2151 #define M_RTE_REQ_LUT_IX 0x7FF 2152 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2153 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2154 2155 #define S_RTE_REQ_LUT_BASE 19 2156 #define M_RTE_REQ_LUT_BASE 0x7FF 2157 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2158 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2159 2160 #define S_RTE_READ_REQ_SELECT 31 2161 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2162 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2163 2164 struct cpl_rte_delete_rpl { 2165 RSS_HDR 2166 union opcode_tid ot; 2167 __u8 status; 2168 __u8 rsvd[3]; 2169 }; 2170 2171 struct cpl_rte_write_req { 2172 WR_HDR; 2173 union opcode_tid ot; 2174 __u32 write_sel; 2175 __be32 lut_params; 2176 __be32 l2t_idx; 2177 __be32 netmask; 2178 __be32 faddr; 2179 }; 2180 2181 /* cpl_rte_write_req.write_sel fields */ 2182 #define S_RTE_WR_L2TIDX 31 2183 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2184 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2185 2186 #define S_RTE_WR_FADDR 30 2187 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2188 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2189 2190 /* cpl_rte_write_req.lut_params fields */ 2191 #define S_RTE_WR_LUT_IX 10 2192 #define M_RTE_WR_LUT_IX 0x7FF 2193 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2194 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2195 2196 #define S_RTE_WR_LUT_BASE 21 2197 #define M_RTE_WR_LUT_BASE 0x7FF 2198 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2199 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2200 2201 struct cpl_rte_write_rpl { 2202 RSS_HDR 2203 union opcode_tid ot; 2204 __u8 status; 2205 __u8 rsvd[3]; 2206 }; 2207 2208 struct cpl_rte_read_req { 2209 WR_HDR; 2210 union opcode_tid ot; 2211 __be32 params; 2212 }; 2213 2214 struct cpl_rte_read_rpl { 2215 RSS_HDR 2216 union opcode_tid ot; 2217 __u8 status; 2218 __u8 rsvd; 2219 __be16 l2t_idx; 2220 #if defined(__LITTLE_ENDIAN_BITFIELD) 2221 __u32 :30; 2222 __u32 select:1; 2223 #else 2224 __u32 select:1; 2225 __u32 :30; 2226 #endif 2227 __be32 addr; 2228 }; 2229 2230 struct cpl_l2t_write_req { 2231 WR_HDR; 2232 union opcode_tid ot; 2233 __be16 params; 2234 __be16 l2t_idx; 2235 __be16 vlan; 2236 __u8 dst_mac[6]; 2237 }; 2238 2239 /* cpl_l2t_write_req.params fields */ 2240 #define S_L2T_W_INFO 2 2241 #define M_L2T_W_INFO 0x3F 2242 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2243 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2244 2245 #define S_L2T_W_PORT 8 2246 #define M_L2T_W_PORT 0x3 2247 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2248 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2249 2250 #define S_L2T_W_LPBK 10 2251 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2252 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2253 2254 #define S_L2T_W_ARPMISS 11 2255 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2256 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2257 2258 #define S_L2T_W_NOREPLY 15 2259 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2260 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 2261 2262 #define CPL_L2T_VLAN_NONE 0xfff 2263 2264 struct cpl_l2t_write_rpl { 2265 RSS_HDR 2266 union opcode_tid ot; 2267 __u8 status; 2268 __u8 rsvd[3]; 2269 }; 2270 2271 struct cpl_l2t_read_req { 2272 WR_HDR; 2273 union opcode_tid ot; 2274 __be32 l2t_idx; 2275 }; 2276 2277 struct cpl_l2t_read_rpl { 2278 RSS_HDR 2279 union opcode_tid ot; 2280 __u8 status; 2281 #if defined(__LITTLE_ENDIAN_BITFIELD) 2282 __u8 :4; 2283 __u8 iff:4; 2284 #else 2285 __u8 iff:4; 2286 __u8 :4; 2287 #endif 2288 __be16 vlan; 2289 __be16 info; 2290 __u8 dst_mac[6]; 2291 }; 2292 2293 struct cpl_srq_table_req { 2294 WR_HDR; 2295 union opcode_tid ot; 2296 __u8 status; 2297 __u8 rsvd[2]; 2298 __u8 idx; 2299 __be64 rsvd_pdid; 2300 __be32 qlen_qbase; 2301 __be16 cur_msn; 2302 __be16 max_msn; 2303 }; 2304 2305 struct cpl_srq_table_rpl { 2306 RSS_HDR 2307 union opcode_tid ot; 2308 __u8 status; 2309 __u8 rsvd[2]; 2310 __u8 idx; 2311 __be64 rsvd_pdid; 2312 __be32 qlen_qbase; 2313 __be16 cur_msn; 2314 __be16 max_msn; 2315 }; 2316 2317 /* cpl_srq_table_{req,rpl}.params fields */ 2318 #define S_SRQT_QLEN 28 2319 #define M_SRQT_QLEN 0xF 2320 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 2321 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 2322 2323 #define S_SRQT_QBASE 0 2324 #define M_SRQT_QBASE 0x3FFFFFF 2325 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 2326 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 2327 2328 #define S_SRQT_PDID 0 2329 #define M_SRQT_PDID 0xFF 2330 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 2331 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 2332 2333 #define S_SRQT_IDX 0 2334 #define M_SRQT_IDX 0xF 2335 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 2336 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 2337 2338 struct cpl_smt_write_req { 2339 WR_HDR; 2340 union opcode_tid ot; 2341 __be32 params; 2342 __be16 pfvf1; 2343 __u8 src_mac1[6]; 2344 __be16 pfvf0; 2345 __u8 src_mac0[6]; 2346 }; 2347 2348 struct cpl_t6_smt_write_req { 2349 WR_HDR; 2350 union opcode_tid ot; 2351 __be32 params; 2352 __be64 tag; 2353 __be16 pfvf0; 2354 __u8 src_mac0[6]; 2355 __be32 local_ip; 2356 __be32 rsvd; 2357 }; 2358 2359 struct cpl_smt_write_rpl { 2360 RSS_HDR 2361 union opcode_tid ot; 2362 __u8 status; 2363 __u8 rsvd[3]; 2364 }; 2365 2366 struct cpl_smt_read_req { 2367 WR_HDR; 2368 union opcode_tid ot; 2369 __be32 params; 2370 }; 2371 2372 struct cpl_smt_read_rpl { 2373 RSS_HDR 2374 union opcode_tid ot; 2375 __u8 status; 2376 __u8 ovlan_idx; 2377 __be16 rsvd; 2378 __be16 pfvf1; 2379 __u8 src_mac1[6]; 2380 __be16 pfvf0; 2381 __u8 src_mac0[6]; 2382 }; 2383 2384 /* cpl_smt_{read,write}_req.params fields */ 2385 #define S_SMTW_OVLAN_IDX 16 2386 #define M_SMTW_OVLAN_IDX 0xF 2387 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2388 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2389 2390 #define S_SMTW_IDX 20 2391 #define M_SMTW_IDX 0x7F 2392 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2393 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2394 2395 #define M_T6_SMTW_IDX 0xFF 2396 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 2397 2398 #define S_SMTW_NORPL 31 2399 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2400 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2401 2402 /* cpl_smt_{read,write}_req.pfvf? fields */ 2403 #define S_SMTW_VF 0 2404 #define M_SMTW_VF 0xFF 2405 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2406 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2407 2408 #define S_SMTW_PF 8 2409 #define M_SMTW_PF 0x7 2410 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2411 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2412 2413 #define S_SMTW_VF_VLD 11 2414 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2415 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2416 2417 struct cpl_tag_write_req { 2418 WR_HDR; 2419 union opcode_tid ot; 2420 __be32 params; 2421 __be64 tag_val; 2422 }; 2423 2424 struct cpl_tag_write_rpl { 2425 RSS_HDR 2426 union opcode_tid ot; 2427 __u8 status; 2428 __u8 rsvd[2]; 2429 __u8 idx; 2430 }; 2431 2432 struct cpl_tag_read_req { 2433 WR_HDR; 2434 union opcode_tid ot; 2435 __be32 params; 2436 }; 2437 2438 struct cpl_tag_read_rpl { 2439 RSS_HDR 2440 union opcode_tid ot; 2441 __u8 status; 2442 #if defined(__LITTLE_ENDIAN_BITFIELD) 2443 __u8 :4; 2444 __u8 tag_len:1; 2445 __u8 :2; 2446 __u8 ins_enable:1; 2447 #else 2448 __u8 ins_enable:1; 2449 __u8 :2; 2450 __u8 tag_len:1; 2451 __u8 :4; 2452 #endif 2453 __u8 rsvd; 2454 __u8 tag_idx; 2455 __be64 tag_val; 2456 }; 2457 2458 /* cpl_tag{read,write}_req.params fields */ 2459 #define S_TAGW_IDX 0 2460 #define M_TAGW_IDX 0x7F 2461 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2462 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2463 2464 #define S_TAGW_LEN 20 2465 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2466 #define F_TAGW_LEN V_TAGW_LEN(1U) 2467 2468 #define S_TAGW_INS_ENABLE 23 2469 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2470 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2471 2472 #define S_TAGW_NORPL 31 2473 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2474 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2475 2476 struct cpl_barrier { 2477 WR_HDR; 2478 __u8 opcode; 2479 __u8 chan_map; 2480 __be16 rsvd0; 2481 __be32 rsvd1; 2482 }; 2483 2484 /* cpl_barrier.chan_map fields */ 2485 #define S_CHAN_MAP 4 2486 #define M_CHAN_MAP 0xF 2487 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2488 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2489 2490 struct cpl_error { 2491 RSS_HDR 2492 union opcode_tid ot; 2493 __be32 error; 2494 }; 2495 2496 struct cpl_hit_notify { 2497 RSS_HDR 2498 union opcode_tid ot; 2499 __be32 rsvd; 2500 __be32 info; 2501 __be32 reason; 2502 }; 2503 2504 struct cpl_pkt_notify { 2505 RSS_HDR 2506 union opcode_tid ot; 2507 __be16 rsvd; 2508 __be16 len; 2509 __be32 info; 2510 __be32 reason; 2511 }; 2512 2513 /* cpl_{hit,pkt}_notify.info fields */ 2514 #define S_NTFY_MAC_IDX 0 2515 #define M_NTFY_MAC_IDX 0x1FF 2516 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2517 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2518 2519 #define S_NTFY_INTF 10 2520 #define M_NTFY_INTF 0xF 2521 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2522 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2523 2524 #define S_NTFY_TCPHDR_LEN 14 2525 #define M_NTFY_TCPHDR_LEN 0xF 2526 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2527 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2528 2529 #define S_NTFY_IPHDR_LEN 18 2530 #define M_NTFY_IPHDR_LEN 0x1FF 2531 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2532 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2533 2534 #define S_NTFY_ETHHDR_LEN 27 2535 #define M_NTFY_ETHHDR_LEN 0x1F 2536 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2537 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2538 2539 #define S_NTFY_T5_IPHDR_LEN 18 2540 #define M_NTFY_T5_IPHDR_LEN 0xFF 2541 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2542 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2543 2544 #define S_NTFY_T5_ETHHDR_LEN 26 2545 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2546 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2547 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2548 2549 struct cpl_rdma_terminate { 2550 RSS_HDR 2551 union opcode_tid ot; 2552 __be16 rsvd; 2553 __be16 len; 2554 }; 2555 2556 struct cpl_set_le_req { 2557 WR_HDR; 2558 union opcode_tid ot; 2559 __be16 reply_ctrl; 2560 __be16 params; 2561 __be64 mask_hi; 2562 __be64 mask_lo; 2563 __be64 val_hi; 2564 __be64 val_lo; 2565 }; 2566 2567 /* cpl_set_le_req.reply_ctrl additional fields */ 2568 #define S_LE_REQ_IP6 13 2569 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2570 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2571 2572 /* cpl_set_le_req.params fields */ 2573 #define S_LE_CHAN 0 2574 #define M_LE_CHAN 0x3 2575 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2576 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2577 2578 #define S_LE_OFFSET 5 2579 #define M_LE_OFFSET 0x7 2580 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2581 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2582 2583 #define S_LE_MORE 8 2584 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2585 #define F_LE_MORE V_LE_MORE(1U) 2586 2587 #define S_LE_REQSIZE 9 2588 #define M_LE_REQSIZE 0x7 2589 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2590 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2591 2592 #define S_LE_REQCMD 12 2593 #define M_LE_REQCMD 0xF 2594 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2595 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2596 2597 struct cpl_set_le_rpl { 2598 RSS_HDR 2599 union opcode_tid ot; 2600 __u8 chan; 2601 __u8 info; 2602 __be16 len; 2603 }; 2604 2605 /* cpl_set_le_rpl.info fields */ 2606 #define S_LE_RSPCMD 0 2607 #define M_LE_RSPCMD 0xF 2608 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2609 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2610 2611 #define S_LE_RSPSIZE 4 2612 #define M_LE_RSPSIZE 0x7 2613 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2614 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2615 2616 #define S_LE_RSPTYPE 7 2617 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2618 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2619 2620 struct cpl_sge_egr_update { 2621 RSS_HDR 2622 __be32 opcode_qid; 2623 __be16 cidx; 2624 __be16 pidx; 2625 }; 2626 2627 /* cpl_sge_egr_update.ot fields */ 2628 #define S_AUTOEQU 22 2629 #define M_AUTOEQU 0x1 2630 #define V_AUTOEQU(x) ((x) << S_AUTOEQU) 2631 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 2632 2633 #define S_EGR_QID 0 2634 #define M_EGR_QID 0x1FFFF 2635 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2636 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2637 2638 /* cpl_fw*.type values */ 2639 enum { 2640 FW_TYPE_CMD_RPL = 0, 2641 FW_TYPE_WR_RPL = 1, 2642 FW_TYPE_CQE = 2, 2643 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2644 FW_TYPE_RSSCPL = 4, 2645 FW_TYPE_WRERR_RPL = 5, 2646 FW_TYPE_PI_ERR = 6, 2647 FW_TYPE_TLS_KEY = 7, 2648 }; 2649 2650 struct cpl_fw2_pld { 2651 RSS_HDR 2652 u8 opcode; 2653 u8 rsvd[5]; 2654 __be16 len; 2655 }; 2656 2657 struct cpl_fw4_pld { 2658 RSS_HDR 2659 u8 opcode; 2660 u8 rsvd0[3]; 2661 u8 type; 2662 u8 rsvd1; 2663 __be16 len; 2664 __be64 data; 2665 __be64 rsvd2; 2666 }; 2667 2668 struct cpl_fw6_pld { 2669 RSS_HDR 2670 u8 opcode; 2671 u8 rsvd[5]; 2672 __be16 len; 2673 __be64 data[4]; 2674 }; 2675 2676 struct cpl_fw2_msg { 2677 RSS_HDR 2678 union opcode_info oi; 2679 }; 2680 2681 struct cpl_fw4_msg { 2682 RSS_HDR 2683 u8 opcode; 2684 u8 type; 2685 __be16 rsvd0; 2686 __be32 rsvd1; 2687 __be64 data[2]; 2688 }; 2689 2690 struct cpl_fw4_ack { 2691 RSS_HDR 2692 union opcode_tid ot; 2693 u8 credits; 2694 u8 rsvd0[2]; 2695 u8 flags; 2696 __be32 snd_nxt; 2697 __be32 snd_una; 2698 __be64 rsvd1; 2699 }; 2700 2701 enum { 2702 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2703 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2704 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2705 }; 2706 2707 struct cpl_fw6_msg { 2708 RSS_HDR 2709 u8 opcode; 2710 u8 type; 2711 __be16 rsvd0; 2712 __be32 rsvd1; 2713 __be64 data[4]; 2714 }; 2715 2716 /* cpl_fw6_msg.type values */ 2717 enum { 2718 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2719 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2720 FW6_TYPE_CQE = FW_TYPE_CQE, 2721 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2722 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2723 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 2724 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 2725 NUM_FW6_TYPES 2726 }; 2727 2728 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2729 __u64 cookie; 2730 __be32 tid; /* or atid in case of active failure */ 2731 __u8 t_state; 2732 __u8 retval; 2733 __u8 rsvd[2]; 2734 }; 2735 2736 /* ULP_TX opcodes */ 2737 enum { 2738 ULP_TX_MEM_READ = 2, 2739 ULP_TX_MEM_WRITE = 3, 2740 ULP_TX_PKT = 4 2741 }; 2742 2743 enum { 2744 ULP_TX_SC_NOOP = 0x80, 2745 ULP_TX_SC_IMM = 0x81, 2746 ULP_TX_SC_DSGL = 0x82, 2747 ULP_TX_SC_ISGL = 0x83, 2748 ULP_TX_SC_PICTRL = 0x84, 2749 ULP_TX_SC_MEMRD = 0x86 2750 }; 2751 2752 #define S_ULPTX_CMD 24 2753 #define M_ULPTX_CMD 0xFF 2754 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2755 2756 #define S_ULPTX_LEN16 0 2757 #define M_ULPTX_LEN16 0xFF 2758 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2759 2760 #define S_ULP_TX_SC_MORE 23 2761 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2762 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2763 2764 struct ulptx_sge_pair { 2765 __be32 len[2]; 2766 __be64 addr[2]; 2767 }; 2768 2769 struct ulptx_sgl { 2770 __be32 cmd_nsge; 2771 __be32 len0; 2772 __be64 addr0; 2773 #if !(defined C99_NOT_SUPPORTED) 2774 struct ulptx_sge_pair sge[0]; 2775 #endif 2776 }; 2777 2778 struct ulptx_isge { 2779 __be32 stag; 2780 __be32 len; 2781 __be64 target_ofst; 2782 }; 2783 2784 struct ulptx_isgl { 2785 __be32 cmd_nisge; 2786 __be32 rsvd; 2787 #if !(defined C99_NOT_SUPPORTED) 2788 struct ulptx_isge sge[0]; 2789 #endif 2790 }; 2791 2792 struct ulptx_idata { 2793 __be32 cmd_more; 2794 __be32 len; 2795 }; 2796 2797 #define S_ULPTX_NSGE 0 2798 #define M_ULPTX_NSGE 0xFFFF 2799 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2800 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 2801 2802 struct ulptx_sc_memrd { 2803 __be32 cmd_to_len; 2804 __be32 addr; 2805 }; 2806 2807 struct ulp_mem_io { 2808 WR_HDR; 2809 __be32 cmd; 2810 __be32 len16; /* command length */ 2811 __be32 dlen; /* data length in 32-byte units */ 2812 __be32 lock_addr; 2813 }; 2814 2815 /* additional ulp_mem_io.cmd fields */ 2816 #define S_ULP_MEMIO_ORDER 23 2817 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2818 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2819 2820 #define S_T5_ULP_MEMIO_IMM 23 2821 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2822 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2823 2824 #define S_T5_ULP_MEMIO_ORDER 22 2825 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2826 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2827 2828 #define S_T5_ULP_MEMIO_FID 4 2829 #define M_T5_ULP_MEMIO_FID 0x7ff 2830 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 2831 2832 /* ulp_mem_io.lock_addr fields */ 2833 #define S_ULP_MEMIO_ADDR 0 2834 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2835 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2836 2837 #define S_ULP_MEMIO_LOCK 31 2838 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2839 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2840 2841 /* ulp_mem_io.dlen fields */ 2842 #define S_ULP_MEMIO_DATA_LEN 0 2843 #define M_ULP_MEMIO_DATA_LEN 0x1F 2844 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2845 2846 /* ULP_TXPKT field values */ 2847 enum { 2848 ULP_TXPKT_DEST_TP = 0, 2849 ULP_TXPKT_DEST_SGE, 2850 ULP_TXPKT_DEST_UP, 2851 ULP_TXPKT_DEST_DEVNULL, 2852 }; 2853 2854 struct ulp_txpkt { 2855 __be32 cmd_dest; 2856 __be32 len; 2857 }; 2858 2859 /* ulp_txpkt.cmd_dest fields */ 2860 #define S_ULP_TXPKT_DATAMODIFY 23 2861 #define M_ULP_TXPKT_DATAMODIFY 0x1 2862 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 2863 #define G_ULP_TXPKT_DATAMODIFY(x) \ 2864 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 2865 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 2866 2867 #define S_ULP_TXPKT_CHANNELID 22 2868 #define M_ULP_TXPKT_CHANNELID 0x1 2869 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 2870 #define G_ULP_TXPKT_CHANNELID(x) \ 2871 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 2872 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 2873 2874 /* ulp_txpkt.cmd_dest fields */ 2875 #define S_ULP_TXPKT_DEST 16 2876 #define M_ULP_TXPKT_DEST 0x3 2877 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2878 2879 #define S_ULP_TXPKT_FID 4 2880 #define M_ULP_TXPKT_FID 0x7ff 2881 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2882 2883 #define S_ULP_TXPKT_RO 3 2884 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2885 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2886 2887 enum cpl_tx_tnl_lso_type { 2888 TX_TNL_TYPE_OPAQUE, 2889 TX_TNL_TYPE_NVGRE, 2890 TX_TNL_TYPE_VXLAN, 2891 TX_TNL_TYPE_GENEVE, 2892 }; 2893 2894 struct cpl_tx_tnl_lso { 2895 __be32 op_to_IpIdSplitOut; 2896 __be16 IpIdOffsetOut; 2897 __be16 UdpLenSetOut_to_TnlHdrLen; 2898 __be64 r1; 2899 __be32 Flow_to_TcpHdrLen; 2900 __be16 IpIdOffset; 2901 __be16 IpIdSplit_to_Mss; 2902 __be32 TCPSeqOffset; 2903 __be32 EthLenOffset_Size; 2904 /* encapsulated CPL (TX_PKT_XT) follows here */ 2905 }; 2906 2907 #define S_CPL_TX_TNL_LSO_OPCODE 24 2908 #define M_CPL_TX_TNL_LSO_OPCODE 0xff 2909 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 2910 #define G_CPL_TX_TNL_LSO_OPCODE(x) \ 2911 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 2912 2913 #define S_CPL_TX_TNL_LSO_FIRST 23 2914 #define M_CPL_TX_TNL_LSO_FIRST 0x1 2915 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 2916 #define G_CPL_TX_TNL_LSO_FIRST(x) \ 2917 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 2918 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 2919 2920 #define S_CPL_TX_TNL_LSO_LAST 22 2921 #define M_CPL_TX_TNL_LSO_LAST 0x1 2922 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 2923 #define G_CPL_TX_TNL_LSO_LAST(x) \ 2924 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 2925 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 2926 2927 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 2928 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 2929 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 2930 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 2931 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 2932 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 2933 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 2934 2935 #define S_CPL_TX_TNL_LSO_IPV6OUT 20 2936 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 2937 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 2938 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 2939 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 2940 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 2941 2942 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 2943 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 2944 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 2945 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 2946 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 2947 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 2948 2949 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 2950 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 2951 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 2952 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 2953 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 2954 2955 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 2956 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 2957 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 2958 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 2959 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 2960 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 2961 2962 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 2963 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 2964 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 2965 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 2966 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 2967 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 2968 2969 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 2970 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 2971 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 2972 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 2973 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 2974 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 2975 2976 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 2977 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 2978 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 2979 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 2980 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 2981 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 2982 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 2983 2984 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 2985 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 2986 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 2987 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 2988 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 2989 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 2990 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 2991 2992 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 2993 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 2994 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 2995 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 2996 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 2997 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 2998 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 2999 3000 #define S_CPL_TX_TNL_LSO_TNLTYPE 12 3001 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 3002 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 3003 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 3004 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 3005 3006 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 3007 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 3008 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 3009 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 3010 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 3011 3012 #define S_CPL_TX_TNL_LSO_FLOW 21 3013 #define M_CPL_TX_TNL_LSO_FLOW 0x1 3014 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 3015 #define G_CPL_TX_TNL_LSO_FLOW(x) \ 3016 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 3017 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 3018 3019 #define S_CPL_TX_TNL_LSO_IPV6 20 3020 #define M_CPL_TX_TNL_LSO_IPV6 0x1 3021 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 3022 #define G_CPL_TX_TNL_LSO_IPV6(x) \ 3023 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 3024 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 3025 3026 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 3027 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 3028 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 3029 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 3030 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 3031 3032 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4 3033 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 3034 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 3035 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 3036 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 3037 3038 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 3039 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 3040 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 3041 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 3042 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 3043 3044 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 3045 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 3046 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 3047 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 3048 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 3049 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 3050 3051 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 3052 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 3053 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 3054 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 3055 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 3056 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 3057 3058 #define S_CPL_TX_TNL_LSO_MSS 0 3059 #define M_CPL_TX_TNL_LSO_MSS 0x3fff 3060 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 3061 #define G_CPL_TX_TNL_LSO_MSS(x) \ 3062 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 3063 3064 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 3065 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 3066 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3067 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 3068 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3069 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 3070 3071 #define S_CPL_TX_TNL_LSO_SIZE 0 3072 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 3073 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 3074 #define G_CPL_TX_TNL_LSO_SIZE(x) \ 3075 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 3076 3077 struct cpl_rx_mps_pkt { 3078 __be32 op_to_r1_hi; 3079 __be32 r1_lo_length; 3080 }; 3081 3082 #define S_CPL_RX_MPS_PKT_OP 24 3083 #define M_CPL_RX_MPS_PKT_OP 0xff 3084 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 3085 #define G_CPL_RX_MPS_PKT_OP(x) \ 3086 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 3087 3088 #define S_CPL_RX_MPS_PKT_TYPE 20 3089 #define M_CPL_RX_MPS_PKT_TYPE 0xf 3090 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 3091 #define G_CPL_RX_MPS_PKT_TYPE(x) \ 3092 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 3093 3094 /* 3095 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 3096 */ 3097 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 3098 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 3099 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 3100 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 3101 3102 struct cpl_tx_tls_sfo { 3103 __be32 op_to_seg_len; 3104 __be32 pld_len; 3105 __be64 rsvd; 3106 __be32 seqno_numivs; 3107 __be32 ivgen_hdrlen; 3108 __be64 scmd1; 3109 }; 3110 3111 /* cpl_tx_tls_sfo macros */ 3112 #define S_CPL_TX_TLS_SFO_OPCODE 24 3113 #define M_CPL_TX_TLS_SFO_OPCODE 0xff 3114 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 3115 #define G_CPL_TX_TLS_SFO_OPCODE(x) \ 3116 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 3117 3118 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20 3119 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 3120 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 3121 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 3122 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 3123 3124 #define S_CPL_TX_TLS_SFO_CPL_LEN 16 3125 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 3126 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 3127 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 3128 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 3129 #define S_CPL_TX_TLS_SFO_SEG_LEN 0 3130 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 3131 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 3132 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 3133 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 3134 3135 struct cpl_tls_data { 3136 RSS_HDR 3137 __be32 op_tid; 3138 __be32 length_pkd; 3139 __be32 seq; 3140 __be32 r1; 3141 }; 3142 3143 #define S_CPL_TLS_DATA_OPCODE 24 3144 #define M_CPL_TLS_DATA_OPCODE 0xff 3145 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 3146 #define G_CPL_TLS_DATA_OPCODE(x) \ 3147 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 3148 3149 #define S_CPL_TLS_DATA_TID 0 3150 #define M_CPL_TLS_DATA_TID 0xffffff 3151 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 3152 #define G_CPL_TLS_DATA_TID(x) \ 3153 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 3154 3155 #define S_CPL_TLS_DATA_LENGTH 0 3156 #define M_CPL_TLS_DATA_LENGTH 0xffff 3157 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 3158 #define G_CPL_TLS_DATA_LENGTH(x) \ 3159 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 3160 3161 struct cpl_rx_tls_cmp { 3162 RSS_HDR 3163 __be32 op_tid; 3164 __be32 pdulength_length; 3165 __be32 seq; 3166 __be32 ddp_report; 3167 __be32 r; 3168 __be32 ddp_valid; 3169 }; 3170 3171 #define S_CPL_RX_TLS_CMP_OPCODE 24 3172 #define M_CPL_RX_TLS_CMP_OPCODE 0xff 3173 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 3174 #define G_CPL_RX_TLS_CMP_OPCODE(x) \ 3175 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 3176 3177 #define S_CPL_RX_TLS_CMP_TID 0 3178 #define M_CPL_RX_TLS_CMP_TID 0xffffff 3179 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 3180 #define G_CPL_RX_TLS_CMP_TID(x) \ 3181 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 3182 3183 #define S_CPL_RX_TLS_CMP_PDULENGTH 16 3184 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 3185 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 3186 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 3187 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 3188 3189 #define S_CPL_RX_TLS_CMP_LENGTH 0 3190 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff 3191 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 3192 #define G_CPL_RX_TLS_CMP_LENGTH(x) \ 3193 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 3194 3195 #define S_SCMD_SEQ_NO_CTRL 29 3196 #define M_SCMD_SEQ_NO_CTRL 0x3 3197 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 3198 #define G_SCMD_SEQ_NO_CTRL(x) \ 3199 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 3200 3201 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 3202 #define S_SCMD_STATUS_PRESENT 28 3203 #define M_SCMD_STATUS_PRESENT 0x1 3204 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 3205 #define G_SCMD_STATUS_PRESENT(x) \ 3206 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 3207 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 3208 3209 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 3210 * 3-15: Reserved. */ 3211 #define S_SCMD_PROTO_VERSION 24 3212 #define M_SCMD_PROTO_VERSION 0xf 3213 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 3214 #define G_SCMD_PROTO_VERSION(x) \ 3215 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 3216 3217 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 3218 #define S_SCMD_ENC_DEC_CTRL 23 3219 #define M_SCMD_ENC_DEC_CTRL 0x1 3220 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 3221 #define G_SCMD_ENC_DEC_CTRL(x) \ 3222 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 3223 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 3224 3225 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 3226 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 3227 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 3228 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3229 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 3230 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3231 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 3232 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 3233 3234 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 3235 * 4:Generic-AES, 5-15: Reserved. */ 3236 #define S_SCMD_CIPH_MODE 18 3237 #define M_SCMD_CIPH_MODE 0xf 3238 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 3239 #define G_SCMD_CIPH_MODE(x) \ 3240 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 3241 3242 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 3243 * 4-15: Reserved */ 3244 #define S_SCMD_AUTH_MODE 14 3245 #define M_SCMD_AUTH_MODE 0xf 3246 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 3247 #define G_SCMD_AUTH_MODE(x) \ 3248 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 3249 3250 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 3251 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 3252 */ 3253 #define S_SCMD_HMAC_CTRL 11 3254 #define M_SCMD_HMAC_CTRL 0x7 3255 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 3256 #define G_SCMD_HMAC_CTRL(x) \ 3257 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 3258 3259 /* IvSize - IV size in units of 2 bytes */ 3260 #define S_SCMD_IV_SIZE 7 3261 #define M_SCMD_IV_SIZE 0xf 3262 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 3263 #define G_SCMD_IV_SIZE(x) \ 3264 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 3265 3266 /* NumIVs - Number of IVs */ 3267 #define S_SCMD_NUM_IVS 0 3268 #define M_SCMD_NUM_IVS 0x7f 3269 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 3270 #define G_SCMD_NUM_IVS(x) \ 3271 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 3272 3273 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 3274 * (below) are used as Cid (connection id for debug status), these 3275 * bits are padded to zero for forming the 64 bit 3276 * sequence number for TLS 3277 */ 3278 #define S_SCMD_ENB_DBGID 31 3279 #define M_SCMD_ENB_DBGID 0x1 3280 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 3281 #define G_SCMD_ENB_DBGID(x) \ 3282 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 3283 3284 /* IV generation in SW. */ 3285 #define S_SCMD_IV_GEN_CTRL 30 3286 #define M_SCMD_IV_GEN_CTRL 0x1 3287 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 3288 #define G_SCMD_IV_GEN_CTRL(x) \ 3289 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 3290 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 3291 3292 /* More frags */ 3293 #define S_SCMD_MORE_FRAGS 20 3294 #define M_SCMD_MORE_FRAGS 0x1 3295 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 3296 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 3297 3298 /*last frag */ 3299 #define S_SCMD_LAST_FRAG 19 3300 #define M_SCMD_LAST_FRAG 0x1 3301 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 3302 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 3303 3304 /* TlsCompPdu */ 3305 #define S_SCMD_TLS_COMPPDU 18 3306 #define M_SCMD_TLS_COMPPDU 0x1 3307 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 3308 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 3309 3310 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 3311 #define S_SCMD_KEY_CTX_INLINE 17 3312 #define M_SCMD_KEY_CTX_INLINE 0x1 3313 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 3314 #define G_SCMD_KEY_CTX_INLINE(x) \ 3315 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 3316 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 3317 3318 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 3319 #define S_SCMD_TLS_FRAG_ENABLE 16 3320 #define M_SCMD_TLS_FRAG_ENABLE 0x1 3321 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 3322 #define G_SCMD_TLS_FRAG_ENABLE(x) \ 3323 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 3324 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 3325 3326 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 3327 * modes, in this case TLS_TX will drop the PDU and only 3328 * send back the MAC bytes. */ 3329 #define S_SCMD_MAC_ONLY 15 3330 #define M_SCMD_MAC_ONLY 0x1 3331 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 3332 #define G_SCMD_MAC_ONLY(x) \ 3333 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 3334 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 3335 3336 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 3337 * which have complex AAD and IV formations Eg:AES-CCM 3338 */ 3339 #define S_SCMD_AADIVDROP 14 3340 #define M_SCMD_AADIVDROP 0x1 3341 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 3342 #define G_SCMD_AADIVDROP(x) \ 3343 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 3344 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 3345 3346 /* HdrLength - Length of all headers excluding TLS header 3347 * present before start of crypto PDU/payload. */ 3348 #define S_SCMD_HDR_LEN 0 3349 #define M_SCMD_HDR_LEN 0x3fff 3350 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 3351 #define G_SCMD_HDR_LEN(x) \ 3352 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 3353 3354 struct cpl_tx_sec_pdu { 3355 __be32 op_ivinsrtofst; 3356 __be32 pldlen; 3357 __be32 aadstart_cipherstop_hi; 3358 __be32 cipherstop_lo_authinsert; 3359 __be32 seqno_numivs; 3360 __be32 ivgen_hdrlen; 3361 __be64 scmd1; 3362 }; 3363 3364 #define S_CPL_TX_SEC_PDU_OPCODE 24 3365 #define M_CPL_TX_SEC_PDU_OPCODE 0xff 3366 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 3367 #define G_CPL_TX_SEC_PDU_OPCODE(x) \ 3368 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 3369 3370 /* RX Channel Id */ 3371 #define S_CPL_TX_SEC_PDU_RXCHID 22 3372 #define M_CPL_TX_SEC_PDU_RXCHID 0x1 3373 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 3374 #define G_CPL_TX_SEC_PDU_RXCHID(x) \ 3375 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 3376 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 3377 3378 /* Ack Follows */ 3379 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 3380 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 3381 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 3382 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 3383 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 3384 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 3385 3386 /* Loopback bit in cpl_tx_sec_pdu */ 3387 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 3388 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 3389 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 3390 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 3391 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 3392 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 3393 3394 /* Length of cpl header encapsulated */ 3395 #define S_CPL_TX_SEC_PDU_CPLLEN 16 3396 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf 3397 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 3398 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 3399 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 3400 3401 /* PlaceHolder */ 3402 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 3403 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 3404 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 3405 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 3406 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 3407 M_CPL_TX_SEC_PDU_PLACEHOLDER) 3408 3409 /* IvInsrtOffset: Insertion location for IV */ 3410 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 3411 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 3412 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 3413 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 3414 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 3415 M_CPL_TX_SEC_PDU_IVINSRTOFST) 3416 3417 /* AadStartOffset: Offset in bytes for AAD start from 3418 * the first byte following 3419 * the pkt headers (0-255 3420 * bytes) */ 3421 #define S_CPL_TX_SEC_PDU_AADSTART 24 3422 #define M_CPL_TX_SEC_PDU_AADSTART 0xff 3423 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 3424 #define G_CPL_TX_SEC_PDU_AADSTART(x) \ 3425 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 3426 M_CPL_TX_SEC_PDU_AADSTART) 3427 3428 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 3429 * the pkt headers (0-511 bytes) */ 3430 #define S_CPL_TX_SEC_PDU_AADSTOP 15 3431 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 3432 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 3433 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 3434 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 3435 3436 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 3437 * first byte following the pkt headers (0-1023 3438 * bytes) */ 3439 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5 3440 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 3441 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 3442 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 3443 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 3444 M_CPL_TX_SEC_PDU_CIPHERSTART) 3445 3446 /* CipherStopOffset: offset in bytes for encryption/decryption end 3447 * from end of the payload of this command (0-511 bytes) */ 3448 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 3449 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 3450 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3451 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3452 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3453 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 3454 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3455 3456 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 3457 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 3458 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3459 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3460 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3461 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 3462 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3463 3464 /* AuthStartOffset: offset in bytes for authentication start from 3465 * the first byte following the pkt headers (0-1023) 3466 * */ 3467 #define S_CPL_TX_SEC_PDU_AUTHSTART 18 3468 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 3469 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 3470 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 3471 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 3472 M_CPL_TX_SEC_PDU_AUTHSTART) 3473 3474 /* AuthStopOffset: offset in bytes for authentication 3475 * end from end of the payload of this command (0-511 Bytes) */ 3476 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9 3477 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 3478 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 3479 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 3480 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 3481 M_CPL_TX_SEC_PDU_AUTHSTOP) 3482 3483 /* AuthInsrtOffset: offset in bytes for authentication insertion 3484 * from end of the payload of this command (0-511 bytes) */ 3485 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0 3486 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 3487 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 3488 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 3489 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 3490 M_CPL_TX_SEC_PDU_AUTHINSERT) 3491 3492 struct cpl_rx_phys_dsgl { 3493 __be32 op_to_tid; 3494 __be32 pcirlxorder_to_noofsgentr; 3495 struct rss_header rss_hdr_int; 3496 }; 3497 3498 #define S_CPL_RX_PHYS_DSGL_OPCODE 24 3499 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 3500 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 3501 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 3502 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 3503 3504 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23 3505 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 3506 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 3507 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 3508 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 3509 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 3510 3511 #define S_CPL_RX_PHYS_DSGL_RSVD1 20 3512 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 3513 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 3514 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 3515 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 3516 3517 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 3518 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 3519 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3520 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3521 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3522 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 3523 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3524 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 3525 3526 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 3527 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 3528 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3529 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3530 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3531 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 3532 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3533 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 3534 3535 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 3536 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 3537 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3538 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3539 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3540 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 3541 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3542 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 3543 3544 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 3545 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 3546 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 3547 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 3548 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 3549 M_CPL_RX_PHYS_DSGL_PCITPHNT) 3550 3551 #define S_CPL_RX_PHYS_DSGL_DCAID 16 3552 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 3553 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 3554 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 3555 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 3556 M_CPL_RX_PHYS_DSGL_DCAID) 3557 3558 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 3559 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 3560 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3561 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3562 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3563 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 3564 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3565 3566 /* CPL_TX_TLS_ACK */ 3567 struct cpl_tx_tls_ack { 3568 __be32 op_to_Rsvd2; 3569 __be32 PldLen; 3570 __be64 Rsvd3; 3571 }; 3572 3573 #define S_CPL_TX_TLS_ACK_OPCODE 24 3574 #define M_CPL_TX_TLS_ACK_OPCODE 0xff 3575 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 3576 #define G_CPL_TX_TLS_ACK_OPCODE(x) \ 3577 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 3578 3579 #define S_CPL_TX_TLS_ACK_RSVD1 23 3580 #define M_CPL_TX_TLS_ACK_RSVD1 0x1 3581 #define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1) 3582 #define G_CPL_TX_TLS_ACK_RSVD1(x) \ 3583 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1) 3584 #define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U) 3585 3586 #define S_CPL_TX_TLS_ACK_RXCHID 22 3587 #define M_CPL_TX_TLS_ACK_RXCHID 0x1 3588 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 3589 #define G_CPL_TX_TLS_ACK_RXCHID(x) \ 3590 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 3591 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 3592 3593 #define S_CPL_TX_TLS_ACK_FWMSG 21 3594 #define M_CPL_TX_TLS_ACK_FWMSG 0x1 3595 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 3596 #define G_CPL_TX_TLS_ACK_FWMSG(x) \ 3597 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 3598 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 3599 3600 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 3601 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 3602 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 3603 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 3604 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 3605 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 3606 3607 #define S_CPL_TX_TLS_ACK_CPLLEN 16 3608 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf 3609 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 3610 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 3611 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 3612 3613 #define S_CPL_TX_TLS_ACK_COMPLONERR 15 3614 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 3615 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 3616 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 3617 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 3618 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 3619 3620 #define S_CPL_TX_TLS_ACK_LCB 14 3621 #define M_CPL_TX_TLS_ACK_LCB 0x1 3622 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 3623 #define G_CPL_TX_TLS_ACK_LCB(x) \ 3624 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 3625 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 3626 3627 #define S_CPL_TX_TLS_ACK_PHASH 13 3628 #define M_CPL_TX_TLS_ACK_PHASH 0x1 3629 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 3630 #define G_CPL_TX_TLS_ACK_PHASH(x) \ 3631 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 3632 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 3633 3634 #define S_CPL_TX_TLS_ACK_RSVD2 0 3635 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 3636 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 3637 #define G_CPL_TX_TLS_ACK_RSVD2(x) \ 3638 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 3639 3640 #endif /* T4_MSG_H */ 3641