1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_PKT_ISO = 0x1F, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_URG_PKT = 0x29, 71 CPL_TAG_WRITE_RPL = 0x2A, 72 CPL_ABORT_REQ_RSS = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_ABORT_RPL_RSS = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_RX_PHYS_ADDR = 0x30, 79 CPL_PCMD_READ_RPL = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 CPL_SET_TCB_RPL = 0x3A, 89 CPL_RX_PKT = 0x3B, 90 CPL_TAG_READ_RPL = 0x3C, 91 CPL_HIT_NOTIFY = 0x3D, 92 CPL_PKT_NOTIFY = 0x3E, 93 CPL_RX_DDP_COMPLETE = 0x3F, 94 95 CPL_ACT_ESTABLISH = 0x40, 96 CPL_PASS_ESTABLISH = 0x41, 97 CPL_RX_DATA_DDP = 0x42, 98 CPL_SMT_READ_RPL = 0x43, 99 CPL_PASS_ACCEPT_REQ = 0x44, 100 CPL_RX2TX_PKT = 0x45, 101 CPL_RX_FCOE_DDP = 0x46, 102 CPL_FCOE_HDR = 0x47, 103 CPL_T5_TRACE_PKT = 0x48, 104 CPL_RX_ISCSI_DDP = 0x49, 105 CPL_RX_FCOE_DIF = 0x4A, 106 CPL_RX_DATA_DIF = 0x4B, 107 CPL_ERR_NOTIFY = 0x4D, 108 109 CPL_RDMA_READ_REQ = 0x60, 110 CPL_RX_ISCSI_DIF = 0x60, 111 112 CPL_SET_LE_REQ = 0x80, 113 CPL_PASS_OPEN_REQ6 = 0x81, 114 CPL_ACT_OPEN_REQ6 = 0x83, 115 116 CPL_RDMA_TERMINATE = 0xA2, 117 CPL_RDMA_WRITE = 0xA4, 118 CPL_SGE_EGR_UPDATE = 0xA5, 119 CPL_SET_LE_RPL = 0xA6, 120 CPL_FW2_MSG = 0xA7, 121 CPL_FW2_PLD = 0xA8, 122 CPL_T5_RDMA_READ_REQ = 0xA9, 123 CPL_RDMA_ATOMIC_REQ = 0xAA, 124 CPL_RDMA_ATOMIC_RPL = 0xAB, 125 CPL_RDMA_IMM_DATA = 0xAC, 126 CPL_RDMA_IMM_DATA_SE = 0xAD, 127 128 CPL_TRACE_PKT = 0xB0, 129 CPL_TRACE_PKT_T5 = 0x48, 130 CPL_RX2TX_DATA = 0xB1, 131 CPL_ISCSI_DATA = 0xB2, 132 CPL_FCOE_DATA = 0xB3, 133 134 CPL_FW4_MSG = 0xC0, 135 CPL_FW4_PLD = 0xC1, 136 CPL_FW4_ACK = 0xC3, 137 138 CPL_FW6_MSG = 0xE0, 139 CPL_FW6_PLD = 0xE1, 140 CPL_TX_PKT_LSO = 0xED, 141 CPL_TX_PKT_XT = 0xEE, 142 143 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 144 }; 145 146 enum CPL_error { 147 CPL_ERR_NONE = 0, 148 CPL_ERR_TCAM_PARITY = 1, 149 CPL_ERR_TCAM_FULL = 3, 150 CPL_ERR_BAD_LENGTH = 15, 151 CPL_ERR_BAD_ROUTE = 18, 152 CPL_ERR_CONN_RESET = 20, 153 CPL_ERR_CONN_EXIST_SYNRECV = 21, 154 CPL_ERR_CONN_EXIST = 22, 155 CPL_ERR_ARP_MISS = 23, 156 CPL_ERR_BAD_SYN = 24, 157 CPL_ERR_CONN_TIMEDOUT = 30, 158 CPL_ERR_XMIT_TIMEDOUT = 31, 159 CPL_ERR_PERSIST_TIMEDOUT = 32, 160 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 161 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 162 CPL_ERR_RTX_NEG_ADVICE = 35, 163 CPL_ERR_PERSIST_NEG_ADVICE = 36, 164 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 165 CPL_ERR_WAIT_ARP_RPL = 41, 166 CPL_ERR_ABORT_FAILED = 42, 167 CPL_ERR_IWARP_FLM = 50, 168 }; 169 170 enum { 171 CPL_CONN_POLICY_AUTO = 0, 172 CPL_CONN_POLICY_ASK = 1, 173 CPL_CONN_POLICY_FILTER = 2, 174 CPL_CONN_POLICY_DENY = 3 175 }; 176 177 enum { 178 ULP_MODE_NONE = 0, 179 ULP_MODE_ISCSI = 2, 180 ULP_MODE_RDMA = 4, 181 ULP_MODE_TCPDDP = 5, 182 ULP_MODE_FCOE = 6, 183 }; 184 185 enum { 186 ULP_CRC_HEADER = 1 << 0, 187 ULP_CRC_DATA = 1 << 1 188 }; 189 190 enum { 191 CPL_PASS_OPEN_ACCEPT, 192 CPL_PASS_OPEN_REJECT, 193 CPL_PASS_OPEN_ACCEPT_TNL 194 }; 195 196 enum { 197 CPL_ABORT_SEND_RST = 0, 198 CPL_ABORT_NO_RST, 199 }; 200 201 enum { /* TX_PKT_XT checksum types */ 202 TX_CSUM_TCP = 0, 203 TX_CSUM_UDP = 1, 204 TX_CSUM_CRC16 = 4, 205 TX_CSUM_CRC32 = 5, 206 TX_CSUM_CRC32C = 6, 207 TX_CSUM_FCOE = 7, 208 TX_CSUM_TCPIP = 8, 209 TX_CSUM_UDPIP = 9, 210 TX_CSUM_TCPIP6 = 10, 211 TX_CSUM_UDPIP6 = 11, 212 TX_CSUM_IP = 12, 213 }; 214 215 enum { /* packet type in CPL_RX_PKT */ 216 PKTYPE_XACT_UCAST = 0, 217 PKTYPE_HASH_UCAST = 1, 218 PKTYPE_XACT_MCAST = 2, 219 PKTYPE_HASH_MCAST = 3, 220 PKTYPE_PROMISC = 4, 221 PKTYPE_HPROMISC = 5, 222 PKTYPE_BCAST = 6 223 }; 224 225 enum { /* DMAC type in CPL_RX_PKT */ 226 DATYPE_UCAST, 227 DATYPE_MCAST, 228 DATYPE_BCAST 229 }; 230 231 enum { /* TCP congestion control algorithms */ 232 CONG_ALG_RENO, 233 CONG_ALG_TAHOE, 234 CONG_ALG_NEWRENO, 235 CONG_ALG_HIGHSPEED 236 }; 237 238 enum { /* RSS hash type */ 239 RSS_HASH_NONE = 0, /* no hash computed */ 240 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 241 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 242 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 243 }; 244 245 enum { /* LE commands */ 246 LE_CMD_READ = 0x4, 247 LE_CMD_WRITE = 0xb 248 }; 249 250 enum { /* LE request size */ 251 LE_SZ_NONE = 0, 252 LE_SZ_33 = 1, 253 LE_SZ_66 = 2, 254 LE_SZ_132 = 3, 255 LE_SZ_264 = 4, 256 LE_SZ_528 = 5 257 }; 258 259 union opcode_tid { 260 __be32 opcode_tid; 261 __u8 opcode; 262 }; 263 264 #define S_CPL_OPCODE 24 265 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 266 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 267 #define G_TID(x) ((x) & 0xFFFFFF) 268 269 /* tid is assumed to be 24-bits */ 270 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 271 272 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 273 274 /* extract the TID from a CPL command */ 275 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 276 277 /* partitioning of TID fields that also carry a queue id */ 278 #define S_TID_TID 0 279 #define M_TID_TID 0x3fff 280 #define V_TID_TID(x) ((x) << S_TID_TID) 281 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 282 283 #define S_TID_QID 14 284 #define M_TID_QID 0x3ff 285 #define V_TID_QID(x) ((x) << S_TID_QID) 286 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 287 288 union opcode_info { 289 __be64 opcode_info; 290 __u8 opcode; 291 }; 292 293 struct tcp_options { 294 __be16 mss; 295 __u8 wsf; 296 #if defined(__LITTLE_ENDIAN_BITFIELD) 297 __u8 :4; 298 __u8 unknown:1; 299 __u8 ecn:1; 300 __u8 sack:1; 301 __u8 tstamp:1; 302 #else 303 __u8 tstamp:1; 304 __u8 sack:1; 305 __u8 ecn:1; 306 __u8 unknown:1; 307 __u8 :4; 308 #endif 309 }; 310 311 struct rss_header { 312 __u8 opcode; 313 #if defined(__LITTLE_ENDIAN_BITFIELD) 314 __u8 channel:2; 315 __u8 filter_hit:1; 316 __u8 filter_tid:1; 317 __u8 hash_type:2; 318 __u8 ipv6:1; 319 __u8 send2fw:1; 320 #else 321 __u8 send2fw:1; 322 __u8 ipv6:1; 323 __u8 hash_type:2; 324 __u8 filter_tid:1; 325 __u8 filter_hit:1; 326 __u8 channel:2; 327 #endif 328 __be16 qid; 329 __be32 hash_val; 330 }; 331 332 #define S_HASHTYPE 20 333 #define M_HASHTYPE 0x3 334 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 335 336 #define S_QNUM 0 337 #define M_QNUM 0xFFFF 338 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 339 340 #ifndef CHELSIO_FW 341 struct work_request_hdr { 342 __be32 wr_hi; 343 __be32 wr_mid; 344 __be64 wr_lo; 345 }; 346 347 /* wr_mid fields */ 348 #define S_WR_LEN16 0 349 #define M_WR_LEN16 0xFF 350 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 351 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 352 353 /* wr_hi fields */ 354 #define S_WR_OP 24 355 #define M_WR_OP 0xFF 356 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 357 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 358 359 # define WR_HDR struct work_request_hdr wr 360 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 361 # define RSS_HDR 362 #else 363 # define WR_HDR 364 # define WR_HDR_SIZE 0 365 # define RSS_HDR struct rss_header rss_hdr; 366 #endif 367 368 /* option 0 fields */ 369 #define S_ACCEPT_MODE 0 370 #define M_ACCEPT_MODE 0x3 371 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 372 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 373 374 #define S_TX_CHAN 2 375 #define M_TX_CHAN 0x3 376 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 377 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 378 379 #define S_NO_CONG 4 380 #define V_NO_CONG(x) ((x) << S_NO_CONG) 381 #define F_NO_CONG V_NO_CONG(1U) 382 383 #define S_DELACK 5 384 #define V_DELACK(x) ((x) << S_DELACK) 385 #define F_DELACK V_DELACK(1U) 386 387 #define S_INJECT_TIMER 6 388 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 389 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 390 391 #define S_NON_OFFLOAD 7 392 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 393 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 394 395 #define S_ULP_MODE 8 396 #define M_ULP_MODE 0xF 397 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 398 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 399 400 #define S_RCV_BUFSIZ 12 401 #define M_RCV_BUFSIZ 0x3FFU 402 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 403 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 404 405 #define S_DSCP 22 406 #define M_DSCP 0x3F 407 #define V_DSCP(x) ((x) << S_DSCP) 408 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 409 410 #define S_SMAC_SEL 28 411 #define M_SMAC_SEL 0xFF 412 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 413 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 414 415 #define S_L2T_IDX 36 416 #define M_L2T_IDX 0xFFF 417 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 418 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 419 420 #define S_TCAM_BYPASS 48 421 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 422 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 423 424 #define S_NAGLE 49 425 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 426 #define F_NAGLE V_NAGLE(1ULL) 427 428 #define S_WND_SCALE 50 429 #define M_WND_SCALE 0xF 430 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 431 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 432 433 #define S_KEEP_ALIVE 54 434 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 435 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 436 437 #define S_MAX_RT 55 438 #define M_MAX_RT 0xF 439 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 440 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 441 442 #define S_MAX_RT_OVERRIDE 59 443 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 444 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 445 446 #define S_MSS_IDX 60 447 #define M_MSS_IDX 0xF 448 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 449 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 450 451 /* option 1 fields */ 452 #define S_SYN_RSS_ENABLE 0 453 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 454 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 455 456 #define S_SYN_RSS_USE_HASH 1 457 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 458 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 459 460 #define S_SYN_RSS_QUEUE 2 461 #define M_SYN_RSS_QUEUE 0x3FF 462 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 463 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 464 465 #define S_LISTEN_INTF 12 466 #define M_LISTEN_INTF 0xFF 467 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 468 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 469 470 #define S_LISTEN_FILTER 20 471 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 472 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 473 474 #define S_SYN_DEFENSE 21 475 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 476 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 477 478 #define S_CONN_POLICY 22 479 #define M_CONN_POLICY 0x3 480 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 481 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 482 483 #define S_FILT_INFO 28 484 #define M_FILT_INFO 0xfffffffffULL 485 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 486 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 487 488 /* option 2 fields */ 489 #define S_RSS_QUEUE 0 490 #define M_RSS_QUEUE 0x3FF 491 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 492 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 493 494 #define S_RSS_QUEUE_VALID 10 495 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 496 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 497 498 #define S_RX_COALESCE_VALID 11 499 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 500 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 501 502 #define S_RX_COALESCE 12 503 #define M_RX_COALESCE 0x3 504 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 505 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 506 507 #define S_CONG_CNTRL 14 508 #define M_CONG_CNTRL 0x3 509 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 510 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 511 512 #define S_PACE 16 513 #define M_PACE 0x3 514 #define V_PACE(x) ((x) << S_PACE) 515 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 516 517 #define S_CONG_CNTRL_VALID 18 518 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 519 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 520 521 #define S_PACE_VALID 19 522 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 523 #define F_PACE_VALID V_PACE_VALID(1U) 524 525 #define S_RX_FC_DISABLE 20 526 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 527 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 528 529 #define S_RX_FC_DDP 21 530 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 531 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 532 533 #define S_RX_FC_VALID 22 534 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 535 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 536 537 #define S_TX_QUEUE 23 538 #define M_TX_QUEUE 0x7 539 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 540 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 541 542 #define S_RX_CHANNEL 26 543 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 544 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 545 546 #define S_CCTRL_ECN 27 547 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 548 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 549 550 #define S_WND_SCALE_EN 28 551 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 552 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 553 554 #define S_TSTAMPS_EN 29 555 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 556 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 557 558 #define S_SACK_EN 30 559 #define V_SACK_EN(x) ((x) << S_SACK_EN) 560 #define F_SACK_EN V_SACK_EN(1U) 561 562 #define S_T5_OPT_2_VALID 31 563 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 564 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 565 566 struct cpl_pass_open_req { 567 WR_HDR; 568 union opcode_tid ot; 569 __be16 local_port; 570 __be16 peer_port; 571 __be32 local_ip; 572 __be32 peer_ip; 573 __be64 opt0; 574 __be64 opt1; 575 }; 576 577 struct cpl_pass_open_req6 { 578 WR_HDR; 579 union opcode_tid ot; 580 __be16 local_port; 581 __be16 peer_port; 582 __be64 local_ip_hi; 583 __be64 local_ip_lo; 584 __be64 peer_ip_hi; 585 __be64 peer_ip_lo; 586 __be64 opt0; 587 __be64 opt1; 588 }; 589 590 struct cpl_pass_open_rpl { 591 RSS_HDR 592 union opcode_tid ot; 593 __u8 rsvd[3]; 594 __u8 status; 595 }; 596 597 struct cpl_pass_establish { 598 RSS_HDR 599 union opcode_tid ot; 600 __be32 rsvd; 601 __be32 tos_stid; 602 __be16 mac_idx; 603 __be16 tcp_opt; 604 __be32 snd_isn; 605 __be32 rcv_isn; 606 }; 607 608 /* cpl_pass_establish.tos_stid fields */ 609 #define S_PASS_OPEN_TID 0 610 #define M_PASS_OPEN_TID 0xFFFFFF 611 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 612 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 613 614 #define S_PASS_OPEN_TOS 24 615 #define M_PASS_OPEN_TOS 0xFF 616 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 617 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 618 619 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 620 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 621 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 622 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 623 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 624 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 625 626 struct cpl_pass_accept_req { 627 RSS_HDR 628 union opcode_tid ot; 629 __be16 rsvd; 630 __be16 len; 631 __be32 hdr_len; 632 __be16 vlan; 633 __be16 l2info; 634 __be32 tos_stid; 635 struct tcp_options tcpopt; 636 }; 637 638 /* cpl_pass_accept_req.hdr_len fields */ 639 #define S_SYN_RX_CHAN 0 640 #define M_SYN_RX_CHAN 0xF 641 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 642 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 643 644 #define S_TCP_HDR_LEN 10 645 #define M_TCP_HDR_LEN 0x3F 646 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 647 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 648 649 #define S_IP_HDR_LEN 16 650 #define M_IP_HDR_LEN 0x3FF 651 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 652 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 653 654 #define S_ETH_HDR_LEN 26 655 #define M_ETH_HDR_LEN 0x3F 656 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 657 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 658 659 /* cpl_pass_accept_req.l2info fields */ 660 #define S_SYN_MAC_IDX 0 661 #define M_SYN_MAC_IDX 0x1FF 662 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 663 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 664 665 #define S_SYN_XACT_MATCH 9 666 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 667 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 668 669 #define S_SYN_INTF 12 670 #define M_SYN_INTF 0xF 671 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 672 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 673 674 struct cpl_pass_accept_rpl { 675 WR_HDR; 676 union opcode_tid ot; 677 __be32 opt2; 678 __be64 opt0; 679 }; 680 681 struct cpl_t5_pass_accept_rpl { 682 WR_HDR; 683 union opcode_tid ot; 684 __be32 opt2; 685 __be64 opt0; 686 __be32 iss; 687 __be32 rsvd; 688 }; 689 690 struct cpl_act_open_req { 691 WR_HDR; 692 union opcode_tid ot; 693 __be16 local_port; 694 __be16 peer_port; 695 __be32 local_ip; 696 __be32 peer_ip; 697 __be64 opt0; 698 __be32 params; 699 __be32 opt2; 700 }; 701 702 #define S_FILTER_TUPLE 24 703 #define M_FILTER_TUPLE 0xFFFFFFFFFF 704 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 705 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 706 struct cpl_t5_act_open_req { 707 WR_HDR; 708 union opcode_tid ot; 709 __be16 local_port; 710 __be16 peer_port; 711 __be32 local_ip; 712 __be32 peer_ip; 713 __be64 opt0; 714 __be32 iss; 715 __be32 opt2; 716 __be64 params; 717 }; 718 719 struct cpl_act_open_req6 { 720 WR_HDR; 721 union opcode_tid ot; 722 __be16 local_port; 723 __be16 peer_port; 724 __be64 local_ip_hi; 725 __be64 local_ip_lo; 726 __be64 peer_ip_hi; 727 __be64 peer_ip_lo; 728 __be64 opt0; 729 __be32 params; 730 __be32 opt2; 731 }; 732 733 struct cpl_t5_act_open_req6 { 734 WR_HDR; 735 union opcode_tid ot; 736 __be16 local_port; 737 __be16 peer_port; 738 __be64 local_ip_hi; 739 __be64 local_ip_lo; 740 __be64 peer_ip_hi; 741 __be64 peer_ip_lo; 742 __be64 opt0; 743 __be32 iss; 744 __be32 opt2; 745 __be64 params; 746 }; 747 748 struct cpl_act_open_rpl { 749 RSS_HDR 750 union opcode_tid ot; 751 __be32 atid_status; 752 }; 753 754 /* cpl_act_open_rpl.atid_status fields */ 755 #define S_AOPEN_STATUS 0 756 #define M_AOPEN_STATUS 0xFF 757 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 758 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 759 760 #define S_AOPEN_ATID 8 761 #define M_AOPEN_ATID 0xFFFFFF 762 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 763 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 764 765 struct cpl_act_establish { 766 RSS_HDR 767 union opcode_tid ot; 768 __be32 rsvd; 769 __be32 tos_atid; 770 __be16 mac_idx; 771 __be16 tcp_opt; 772 __be32 snd_isn; 773 __be32 rcv_isn; 774 }; 775 776 struct cpl_get_tcb { 777 WR_HDR; 778 union opcode_tid ot; 779 __be16 reply_ctrl; 780 __be16 cookie; 781 }; 782 783 /* cpl_get_tcb.reply_ctrl fields */ 784 #define S_QUEUENO 0 785 #define M_QUEUENO 0x3FF 786 #define V_QUEUENO(x) ((x) << S_QUEUENO) 787 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 788 789 #define S_REPLY_CHAN 14 790 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 791 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 792 793 #define S_NO_REPLY 15 794 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 795 #define F_NO_REPLY V_NO_REPLY(1U) 796 797 struct cpl_get_tcb_rpl { 798 RSS_HDR 799 union opcode_tid ot; 800 __u8 cookie; 801 __u8 status; 802 __be16 len; 803 }; 804 805 struct cpl_set_tcb { 806 WR_HDR; 807 union opcode_tid ot; 808 __be16 reply_ctrl; 809 __be16 cookie; 810 }; 811 812 struct cpl_set_tcb_field { 813 WR_HDR; 814 union opcode_tid ot; 815 __be16 reply_ctrl; 816 __be16 word_cookie; 817 __be64 mask; 818 __be64 val; 819 }; 820 821 struct cpl_set_tcb_field_core { 822 union opcode_tid ot; 823 __be16 reply_ctrl; 824 __be16 word_cookie; 825 __be64 mask; 826 __be64 val; 827 }; 828 829 /* cpl_set_tcb_field.word_cookie fields */ 830 #define S_WORD 0 831 #define M_WORD 0x1F 832 #define V_WORD(x) ((x) << S_WORD) 833 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 834 835 #define S_COOKIE 5 836 #define M_COOKIE 0x7 837 #define V_COOKIE(x) ((x) << S_COOKIE) 838 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 839 840 struct cpl_set_tcb_rpl { 841 RSS_HDR 842 union opcode_tid ot; 843 __be16 rsvd; 844 __u8 cookie; 845 __u8 status; 846 __be64 oldval; 847 }; 848 849 struct cpl_close_con_req { 850 WR_HDR; 851 union opcode_tid ot; 852 __be32 rsvd; 853 }; 854 855 struct cpl_close_con_rpl { 856 RSS_HDR 857 union opcode_tid ot; 858 __u8 rsvd[3]; 859 __u8 status; 860 __be32 snd_nxt; 861 __be32 rcv_nxt; 862 }; 863 864 struct cpl_close_listsvr_req { 865 WR_HDR; 866 union opcode_tid ot; 867 __be16 reply_ctrl; 868 __be16 rsvd; 869 }; 870 871 /* additional cpl_close_listsvr_req.reply_ctrl field */ 872 #define S_LISTSVR_IPV6 14 873 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 874 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 875 876 struct cpl_close_listsvr_rpl { 877 RSS_HDR 878 union opcode_tid ot; 879 __u8 rsvd[3]; 880 __u8 status; 881 }; 882 883 struct cpl_abort_req_rss { 884 RSS_HDR 885 union opcode_tid ot; 886 __u8 rsvd[3]; 887 __u8 status; 888 }; 889 890 struct cpl_abort_req { 891 WR_HDR; 892 union opcode_tid ot; 893 __be32 rsvd0; 894 __u8 rsvd1; 895 __u8 cmd; 896 __u8 rsvd2[6]; 897 }; 898 899 struct cpl_abort_rpl_rss { 900 RSS_HDR 901 union opcode_tid ot; 902 __u8 rsvd[3]; 903 __u8 status; 904 }; 905 906 struct cpl_abort_rpl { 907 WR_HDR; 908 union opcode_tid ot; 909 __be32 rsvd0; 910 __u8 rsvd1; 911 __u8 cmd; 912 __u8 rsvd2[6]; 913 }; 914 915 struct cpl_peer_close { 916 RSS_HDR 917 union opcode_tid ot; 918 __be32 rcv_nxt; 919 }; 920 921 struct cpl_tid_release { 922 WR_HDR; 923 union opcode_tid ot; 924 __be32 rsvd; 925 }; 926 927 struct tx_data_wr { 928 __be32 wr_hi; 929 __be32 wr_lo; 930 __be32 len; 931 __be32 flags; 932 __be32 sndseq; 933 __be32 param; 934 }; 935 936 /* tx_data_wr.flags fields */ 937 #define S_TX_ACK_PAGES 21 938 #define M_TX_ACK_PAGES 0x7 939 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 940 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 941 942 /* tx_data_wr.param fields */ 943 #define S_TX_PORT 0 944 #define M_TX_PORT 0x7 945 #define V_TX_PORT(x) ((x) << S_TX_PORT) 946 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 947 948 #define S_TX_MSS 4 949 #define M_TX_MSS 0xF 950 #define V_TX_MSS(x) ((x) << S_TX_MSS) 951 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 952 953 #define S_TX_QOS 8 954 #define M_TX_QOS 0xFF 955 #define V_TX_QOS(x) ((x) << S_TX_QOS) 956 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 957 958 #define S_TX_SNDBUF 16 959 #define M_TX_SNDBUF 0xFFFF 960 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 961 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 962 963 struct cpl_tx_data { 964 union opcode_tid ot; 965 __be32 len; 966 __be32 rsvd; 967 __be32 flags; 968 }; 969 970 /* cpl_tx_data.flags fields */ 971 #define S_TX_PROXY 5 972 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 973 #define F_TX_PROXY V_TX_PROXY(1U) 974 975 #define S_TX_ULP_SUBMODE 6 976 #define M_TX_ULP_SUBMODE 0xF 977 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 978 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 979 980 #define S_TX_ULP_MODE 10 981 #define M_TX_ULP_MODE 0xF 982 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 983 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 984 985 #define S_TX_SHOVE 14 986 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 987 #define F_TX_SHOVE V_TX_SHOVE(1U) 988 989 #define S_TX_MORE 15 990 #define V_TX_MORE(x) ((x) << S_TX_MORE) 991 #define F_TX_MORE V_TX_MORE(1U) 992 993 #define S_TX_URG 16 994 #define V_TX_URG(x) ((x) << S_TX_URG) 995 #define F_TX_URG V_TX_URG(1U) 996 997 #define S_TX_FLUSH 17 998 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 999 #define F_TX_FLUSH V_TX_FLUSH(1U) 1000 1001 #define S_TX_SAVE 18 1002 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1003 #define F_TX_SAVE V_TX_SAVE(1U) 1004 1005 #define S_TX_TNL 19 1006 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1007 #define F_TX_TNL V_TX_TNL(1U) 1008 1009 /* additional tx_data_wr.flags fields */ 1010 #define S_TX_CPU_IDX 0 1011 #define M_TX_CPU_IDX 0x3F 1012 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1013 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1014 1015 #define S_TX_CLOSE 17 1016 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1017 #define F_TX_CLOSE V_TX_CLOSE(1U) 1018 1019 #define S_TX_INIT 18 1020 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1021 #define F_TX_INIT V_TX_INIT(1U) 1022 1023 #define S_TX_IMM_ACK 19 1024 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1025 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1026 1027 #define S_TX_IMM_DMA 20 1028 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1029 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1030 1031 struct cpl_tx_data_ack { 1032 RSS_HDR 1033 union opcode_tid ot; 1034 __be32 snd_una; 1035 }; 1036 1037 struct cpl_wr_ack { /* XXX */ 1038 RSS_HDR 1039 union opcode_tid ot; 1040 __be16 credits; 1041 __be16 rsvd; 1042 __be32 snd_nxt; 1043 __be32 snd_una; 1044 }; 1045 1046 struct cpl_tx_pkt_core { 1047 __be32 ctrl0; 1048 __be16 pack; 1049 __be16 len; 1050 __be64 ctrl1; 1051 }; 1052 1053 struct cpl_tx_pkt { 1054 WR_HDR; 1055 struct cpl_tx_pkt_core c; 1056 }; 1057 1058 #define cpl_tx_pkt_xt cpl_tx_pkt 1059 1060 /* cpl_tx_pkt_core.ctrl0 fields */ 1061 #define S_TXPKT_VF 0 1062 #define M_TXPKT_VF 0xFF 1063 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1064 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1065 1066 #define S_TXPKT_PF 8 1067 #define M_TXPKT_PF 0x7 1068 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1069 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1070 1071 #define S_TXPKT_VF_VLD 11 1072 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1073 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1074 1075 #define S_TXPKT_OVLAN_IDX 12 1076 #define M_TXPKT_OVLAN_IDX 0xF 1077 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1078 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1079 1080 #define S_TXPKT_T5_OVLAN_IDX 12 1081 #define M_TXPKT_T5_OVLAN_IDX 0x7 1082 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1083 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1084 M_TXPKT_T5_OVLAN_IDX) 1085 1086 #define S_TXPKT_INTF 16 1087 #define M_TXPKT_INTF 0xF 1088 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1089 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1090 1091 #define S_TXPKT_SPECIAL_STAT 20 1092 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1093 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1094 1095 #define S_TXPKT_T5_FCS_DIS 21 1096 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1097 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1098 1099 #define S_TXPKT_INS_OVLAN 21 1100 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1101 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1102 1103 #define S_TXPKT_T5_INS_OVLAN 15 1104 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1105 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1106 1107 #define S_TXPKT_STAT_DIS 22 1108 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1109 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1110 1111 #define S_TXPKT_LOOPBACK 23 1112 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1113 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1114 1115 #define S_TXPKT_TSTAMP 23 1116 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1117 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1118 1119 #define S_TXPKT_OPCODE 24 1120 #define M_TXPKT_OPCODE 0xFF 1121 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1122 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1123 1124 /* cpl_tx_pkt_core.ctrl1 fields */ 1125 #define S_TXPKT_SA_IDX 0 1126 #define M_TXPKT_SA_IDX 0xFFF 1127 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1128 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1129 1130 #define S_TXPKT_CSUM_END 12 1131 #define M_TXPKT_CSUM_END 0xFF 1132 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1133 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1134 1135 #define S_TXPKT_CSUM_START 20 1136 #define M_TXPKT_CSUM_START 0x3FF 1137 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1138 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1139 1140 #define S_TXPKT_IPHDR_LEN 20 1141 #define M_TXPKT_IPHDR_LEN 0x3FFF 1142 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1143 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1144 1145 #define S_TXPKT_CSUM_LOC 30 1146 #define M_TXPKT_CSUM_LOC 0x3FF 1147 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1148 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1149 1150 #define S_TXPKT_ETHHDR_LEN 34 1151 #define M_TXPKT_ETHHDR_LEN 0x3F 1152 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1153 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1154 1155 #define S_TXPKT_CSUM_TYPE 40 1156 #define M_TXPKT_CSUM_TYPE 0xF 1157 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1158 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1159 1160 #define S_TXPKT_VLAN 44 1161 #define M_TXPKT_VLAN 0xFFFF 1162 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1163 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1164 1165 #define S_TXPKT_VLAN_VLD 60 1166 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1167 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1168 1169 #define S_TXPKT_IPSEC 61 1170 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1171 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1172 1173 #define S_TXPKT_IPCSUM_DIS 62 1174 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1175 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1176 1177 #define S_TXPKT_L4CSUM_DIS 63 1178 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1179 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1180 1181 struct cpl_tx_pkt_lso_core { 1182 __be32 lso_ctrl; 1183 __be16 ipid_ofst; 1184 __be16 mss; 1185 __be32 seqno_offset; 1186 __be32 len; 1187 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1188 }; 1189 1190 struct cpl_tx_pkt_lso { 1191 WR_HDR; 1192 struct cpl_tx_pkt_lso_core c; 1193 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1194 }; 1195 1196 struct cpl_tx_pkt_ufo_core { 1197 __be16 ethlen; 1198 __be16 iplen; 1199 __be16 udplen; 1200 __be16 mss; 1201 __be32 len; 1202 __be32 r1; 1203 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1204 }; 1205 1206 struct cpl_tx_pkt_ufo { 1207 WR_HDR; 1208 struct cpl_tx_pkt_ufo_core c; 1209 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1210 }; 1211 1212 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1213 #define S_LSO_TCPHDR_LEN 0 1214 #define M_LSO_TCPHDR_LEN 0xF 1215 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1216 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1217 1218 #define S_LSO_IPHDR_LEN 4 1219 #define M_LSO_IPHDR_LEN 0xFFF 1220 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1221 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1222 1223 #define S_LSO_ETHHDR_LEN 16 1224 #define M_LSO_ETHHDR_LEN 0xF 1225 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1226 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1227 1228 #define S_LSO_IPV6 20 1229 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1230 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1231 1232 #define S_LSO_OFLD_ENCAP 21 1233 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1234 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1235 1236 #define S_LSO_LAST_SLICE 22 1237 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1238 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1239 1240 #define S_LSO_FIRST_SLICE 23 1241 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1242 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1243 1244 #define S_LSO_OPCODE 24 1245 #define M_LSO_OPCODE 0xFF 1246 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1247 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1248 1249 #define S_LSO_T5_XFER_SIZE 0 1250 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1251 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1252 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1253 1254 /* cpl_tx_pkt_lso_core.mss fields */ 1255 #define S_LSO_MSS 0 1256 #define M_LSO_MSS 0x3FFF 1257 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1258 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1259 1260 #define S_LSO_IPID_SPLIT 15 1261 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1262 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1263 1264 struct cpl_tx_pkt_fso { 1265 WR_HDR; 1266 __be32 fso_ctrl; 1267 __be16 seqcnt_ofst; 1268 __be16 mtu; 1269 __be32 param_offset; 1270 __be32 len; 1271 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1272 }; 1273 1274 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1275 #define S_FSO_XCHG_CLASS 21 1276 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1277 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1278 1279 #define S_FSO_INITIATOR 20 1280 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1281 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1282 1283 #define S_FSO_FCHDR_LEN 12 1284 #define M_FSO_FCHDR_LEN 0xF 1285 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1286 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1287 1288 struct cpl_iscsi_hdr_no_rss { 1289 union opcode_tid ot; 1290 __be16 pdu_len_ddp; 1291 __be16 len; 1292 __be32 seq; 1293 __be16 urg; 1294 __u8 rsvd; 1295 __u8 status; 1296 }; 1297 1298 struct cpl_tx_data_iso { 1299 WR_HDR; 1300 __be32 iso_ctrl; 1301 __u8 rsvd; 1302 __u8 ahs_len; 1303 __be16 mss; 1304 __be32 burst_size; 1305 __be32 len; 1306 /* encapsulated CPL_TX_DATA follows here */ 1307 }; 1308 1309 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1310 #define S_ISO_CPLHDR_LEN 18 1311 #define M_ISO_CPLHDR_LEN 0xF 1312 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1313 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1314 1315 #define S_ISO_HDR_CRC 17 1316 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1317 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1318 1319 #define S_ISO_DATA_CRC 16 1320 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1321 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1322 1323 #define S_ISO_IMD_DATA_EN 15 1324 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1325 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1326 1327 #define S_ISO_PDU_TYPE 13 1328 #define M_ISO_PDU_TYPE 0x3 1329 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1330 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1331 1332 struct cpl_iscsi_hdr { 1333 RSS_HDR 1334 union opcode_tid ot; 1335 __be16 pdu_len_ddp; 1336 __be16 len; 1337 __be32 seq; 1338 __be16 urg; 1339 __u8 rsvd; 1340 __u8 status; 1341 }; 1342 1343 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1344 #define S_ISCSI_PDU_LEN 0 1345 #define M_ISCSI_PDU_LEN 0x7FFF 1346 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1347 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1348 1349 #define S_ISCSI_DDP 15 1350 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1351 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1352 1353 struct cpl_iscsi_data { 1354 RSS_HDR 1355 union opcode_tid ot; 1356 __u8 rsvd0[2]; 1357 __be16 len; 1358 __be32 seq; 1359 __be16 urg; 1360 __u8 rsvd1; 1361 __u8 status; 1362 }; 1363 1364 struct cpl_rx_data { 1365 RSS_HDR 1366 union opcode_tid ot; 1367 __be16 rsvd; 1368 __be16 len; 1369 __be32 seq; 1370 __be16 urg; 1371 #if defined(__LITTLE_ENDIAN_BITFIELD) 1372 __u8 dack_mode:2; 1373 __u8 psh:1; 1374 __u8 heartbeat:1; 1375 __u8 ddp_off:1; 1376 __u8 :3; 1377 #else 1378 __u8 :3; 1379 __u8 ddp_off:1; 1380 __u8 heartbeat:1; 1381 __u8 psh:1; 1382 __u8 dack_mode:2; 1383 #endif 1384 __u8 status; 1385 }; 1386 1387 struct cpl_fcoe_hdr { 1388 RSS_HDR 1389 union opcode_tid ot; 1390 __be16 oxid; 1391 __be16 len; 1392 __be32 rctl_fctl; 1393 __u8 cs_ctl; 1394 __u8 df_ctl; 1395 __u8 sof; 1396 __u8 eof; 1397 __be16 seq_cnt; 1398 __u8 seq_id; 1399 __u8 type; 1400 __be32 param; 1401 }; 1402 1403 struct cpl_fcoe_data { 1404 RSS_HDR 1405 union opcode_tid ot; 1406 __u8 rsvd0[2]; 1407 __be16 len; 1408 __be32 seq; 1409 __u8 rsvd1[3]; 1410 __u8 status; 1411 }; 1412 1413 struct cpl_rx_urg_notify { 1414 RSS_HDR 1415 union opcode_tid ot; 1416 __be32 seq; 1417 }; 1418 1419 struct cpl_rx_urg_pkt { 1420 RSS_HDR 1421 union opcode_tid ot; 1422 __be16 rsvd; 1423 __be16 len; 1424 }; 1425 1426 struct cpl_rx_data_ack { 1427 WR_HDR; 1428 union opcode_tid ot; 1429 __be32 credit_dack; 1430 }; 1431 1432 struct cpl_rx_data_ack_core { 1433 union opcode_tid ot; 1434 __be32 credit_dack; 1435 }; 1436 1437 /* cpl_rx_data_ack.ack_seq fields */ 1438 #define S_RX_CREDITS 0 1439 #define M_RX_CREDITS 0x3FFFFFF 1440 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1441 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1442 1443 #define S_RX_MODULATE_TX 26 1444 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1445 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1446 1447 #define S_RX_MODULATE_RX 27 1448 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1449 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1450 1451 #define S_RX_FORCE_ACK 28 1452 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1453 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1454 1455 #define S_RX_DACK_MODE 29 1456 #define M_RX_DACK_MODE 0x3 1457 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1458 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1459 1460 #define S_RX_DACK_CHANGE 31 1461 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1462 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1463 1464 struct cpl_rx_ddp_complete { 1465 RSS_HDR 1466 union opcode_tid ot; 1467 __be32 ddp_report; 1468 __be32 rcv_nxt; 1469 __be32 rsvd; 1470 }; 1471 1472 struct cpl_rx_data_ddp { 1473 RSS_HDR 1474 union opcode_tid ot; 1475 __be16 urg; 1476 __be16 len; 1477 __be32 seq; 1478 union { 1479 __be32 nxt_seq; 1480 __be32 ddp_report; 1481 } u; 1482 __be32 ulp_crc; 1483 __be32 ddpvld; 1484 }; 1485 1486 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1487 1488 struct cpl_rx_fcoe_ddp { 1489 RSS_HDR 1490 union opcode_tid ot; 1491 __be16 rsvd; 1492 __be16 len; 1493 __be32 seq; 1494 __be32 ddp_report; 1495 __be32 ulp_crc; 1496 __be32 ddpvld; 1497 }; 1498 1499 struct cpl_rx_data_dif { 1500 RSS_HDR 1501 union opcode_tid ot; 1502 __be16 ddp_len; 1503 __be16 msg_len; 1504 __be32 seq; 1505 union { 1506 __be32 nxt_seq; 1507 __be32 ddp_report; 1508 } u; 1509 __be32 err_vec; 1510 __be32 ddpvld; 1511 }; 1512 1513 struct cpl_rx_iscsi_dif { 1514 RSS_HDR 1515 union opcode_tid ot; 1516 __be16 ddp_len; 1517 __be16 msg_len; 1518 __be32 seq; 1519 union { 1520 __be32 nxt_seq; 1521 __be32 ddp_report; 1522 } u; 1523 __be32 ulp_crc; 1524 __be32 ddpvld; 1525 __u8 rsvd0[8]; 1526 __be32 err_vec; 1527 __u8 rsvd1[4]; 1528 }; 1529 1530 struct cpl_rx_fcoe_dif { 1531 RSS_HDR 1532 union opcode_tid ot; 1533 __be16 ddp_len; 1534 __be16 msg_len; 1535 __be32 seq; 1536 __be32 ddp_report; 1537 __be32 err_vec; 1538 __be32 ddpvld; 1539 }; 1540 1541 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1542 #define S_DDP_VALID 15 1543 #define M_DDP_VALID 0x1FFFF 1544 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1545 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1546 1547 #define S_DDP_PPOD_MISMATCH 15 1548 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1549 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1550 1551 #define S_DDP_PDU 16 1552 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1553 #define F_DDP_PDU V_DDP_PDU(1U) 1554 1555 #define S_DDP_LLIMIT_ERR 17 1556 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1557 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1558 1559 #define S_DDP_PPOD_PARITY_ERR 18 1560 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1561 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1562 1563 #define S_DDP_PADDING_ERR 19 1564 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1565 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1566 1567 #define S_DDP_HDRCRC_ERR 20 1568 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1569 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1570 1571 #define S_DDP_DATACRC_ERR 21 1572 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1573 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1574 1575 #define S_DDP_INVALID_TAG 22 1576 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1577 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1578 1579 #define S_DDP_ULIMIT_ERR 23 1580 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1581 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1582 1583 #define S_DDP_OFFSET_ERR 24 1584 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1585 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1586 1587 #define S_DDP_COLOR_ERR 25 1588 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1589 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1590 1591 #define S_DDP_TID_MISMATCH 26 1592 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1593 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1594 1595 #define S_DDP_INVALID_PPOD 27 1596 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1597 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1598 1599 #define S_DDP_ULP_MODE 28 1600 #define M_DDP_ULP_MODE 0xF 1601 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1602 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1603 1604 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1605 #define S_DDP_OFFSET 0 1606 #define M_DDP_OFFSET 0xFFFFFF 1607 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1608 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1609 1610 #define S_DDP_DACK_MODE 24 1611 #define M_DDP_DACK_MODE 0x3 1612 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1613 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1614 1615 #define S_DDP_BUF_IDX 26 1616 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1617 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1618 1619 #define S_DDP_URG 27 1620 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1621 #define F_DDP_URG V_DDP_URG(1U) 1622 1623 #define S_DDP_PSH 28 1624 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1625 #define F_DDP_PSH V_DDP_PSH(1U) 1626 1627 #define S_DDP_BUF_COMPLETE 29 1628 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1629 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1630 1631 #define S_DDP_BUF_TIMED_OUT 30 1632 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1633 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1634 1635 #define S_DDP_INV 31 1636 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1637 #define F_DDP_INV V_DDP_INV(1U) 1638 1639 struct cpl_rx_pkt { 1640 RSS_HDR 1641 __u8 opcode; 1642 #if defined(__LITTLE_ENDIAN_BITFIELD) 1643 __u8 iff:4; 1644 __u8 csum_calc:1; 1645 __u8 ipmi_pkt:1; 1646 __u8 vlan_ex:1; 1647 __u8 ip_frag:1; 1648 #else 1649 __u8 ip_frag:1; 1650 __u8 vlan_ex:1; 1651 __u8 ipmi_pkt:1; 1652 __u8 csum_calc:1; 1653 __u8 iff:4; 1654 #endif 1655 __be16 csum; 1656 __be16 vlan; 1657 __be16 len; 1658 __be32 l2info; 1659 __be16 hdr_len; 1660 __be16 err_vec; 1661 }; 1662 1663 /* rx_pkt.l2info fields */ 1664 #define S_RX_ETHHDR_LEN 0 1665 #define M_RX_ETHHDR_LEN 0x1F 1666 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1667 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1668 1669 #define S_RX_T5_ETHHDR_LEN 0 1670 #define M_RX_T5_ETHHDR_LEN 0x3F 1671 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1672 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1673 1674 #define S_RX_PKTYPE 5 1675 #define M_RX_PKTYPE 0x7 1676 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1677 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1678 1679 #define S_RX_T5_DATYPE 6 1680 #define M_RX_T5_DATYPE 0x3 1681 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1682 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1683 1684 #define S_RX_MACIDX 8 1685 #define M_RX_MACIDX 0x1FF 1686 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1687 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1688 1689 #define S_RX_T5_PKTYPE 17 1690 #define M_RX_T5_PKTYPE 0x7 1691 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1692 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1693 1694 #define S_RX_DATYPE 18 1695 #define M_RX_DATYPE 0x3 1696 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1697 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1698 1699 #define S_RXF_PSH 20 1700 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1701 #define F_RXF_PSH V_RXF_PSH(1U) 1702 1703 #define S_RXF_SYN 21 1704 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1705 #define F_RXF_SYN V_RXF_SYN(1U) 1706 1707 #define S_RXF_UDP 22 1708 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1709 #define F_RXF_UDP V_RXF_UDP(1U) 1710 1711 #define S_RXF_TCP 23 1712 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1713 #define F_RXF_TCP V_RXF_TCP(1U) 1714 1715 #define S_RXF_IP 24 1716 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1717 #define F_RXF_IP V_RXF_IP(1U) 1718 1719 #define S_RXF_IP6 25 1720 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1721 #define F_RXF_IP6 V_RXF_IP6(1U) 1722 1723 #define S_RXF_SYN_COOKIE 26 1724 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1725 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1726 1727 #define S_RXF_FCOE 26 1728 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1729 #define F_RXF_FCOE V_RXF_FCOE(1U) 1730 1731 #define S_RXF_LRO 27 1732 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1733 #define F_RXF_LRO V_RXF_LRO(1U) 1734 1735 #define S_RX_CHAN 28 1736 #define M_RX_CHAN 0xF 1737 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1738 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1739 1740 /* rx_pkt.hdr_len fields */ 1741 #define S_RX_TCPHDR_LEN 0 1742 #define M_RX_TCPHDR_LEN 0x3F 1743 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1744 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1745 1746 #define S_RX_IPHDR_LEN 6 1747 #define M_RX_IPHDR_LEN 0x3FF 1748 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1749 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1750 1751 /* rx_pkt.err_vec fields */ 1752 #define S_RXERR_OR 0 1753 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1754 #define F_RXERR_OR V_RXERR_OR(1U) 1755 1756 #define S_RXERR_MAC 1 1757 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1758 #define F_RXERR_MAC V_RXERR_MAC(1U) 1759 1760 #define S_RXERR_IPVERS 2 1761 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1762 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1763 1764 #define S_RXERR_FRAG 3 1765 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1766 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1767 1768 #define S_RXERR_ATTACK 4 1769 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1770 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1771 1772 #define S_RXERR_ETHHDR_LEN 5 1773 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1774 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1775 1776 #define S_RXERR_IPHDR_LEN 6 1777 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1778 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1779 1780 #define S_RXERR_TCPHDR_LEN 7 1781 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1782 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1783 1784 #define S_RXERR_PKT_LEN 8 1785 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1786 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1787 1788 #define S_RXERR_TCP_OPT 9 1789 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1790 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1791 1792 #define S_RXERR_IPCSUM 12 1793 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1794 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1795 1796 #define S_RXERR_CSUM 13 1797 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1798 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1799 1800 #define S_RXERR_PING 14 1801 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1802 #define F_RXERR_PING V_RXERR_PING(1U) 1803 1804 struct cpl_trace_pkt { 1805 RSS_HDR 1806 __u8 opcode; 1807 __u8 intf; 1808 #if defined(__LITTLE_ENDIAN_BITFIELD) 1809 __u8 runt:4; 1810 __u8 filter_hit:4; 1811 __u8 :6; 1812 __u8 err:1; 1813 __u8 trunc:1; 1814 #else 1815 __u8 filter_hit:4; 1816 __u8 runt:4; 1817 __u8 trunc:1; 1818 __u8 err:1; 1819 __u8 :6; 1820 #endif 1821 __be16 rsvd; 1822 __be16 len; 1823 __be64 tstamp; 1824 }; 1825 1826 struct cpl_t5_trace_pkt { 1827 RSS_HDR 1828 __u8 opcode; 1829 __u8 intf; 1830 #if defined(__LITTLE_ENDIAN_BITFIELD) 1831 __u8 runt:4; 1832 __u8 filter_hit:4; 1833 __u8 :6; 1834 __u8 err:1; 1835 __u8 trunc:1; 1836 #else 1837 __u8 filter_hit:4; 1838 __u8 runt:4; 1839 __u8 trunc:1; 1840 __u8 err:1; 1841 __u8 :6; 1842 #endif 1843 __be16 rsvd; 1844 __be16 len; 1845 __be64 tstamp; 1846 __be64 rsvd1; 1847 }; 1848 1849 struct cpl_rte_delete_req { 1850 WR_HDR; 1851 union opcode_tid ot; 1852 __be32 params; 1853 }; 1854 1855 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1856 #define S_RTE_REQ_LUT_IX 8 1857 #define M_RTE_REQ_LUT_IX 0x7FF 1858 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1859 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1860 1861 #define S_RTE_REQ_LUT_BASE 19 1862 #define M_RTE_REQ_LUT_BASE 0x7FF 1863 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1864 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1865 1866 #define S_RTE_READ_REQ_SELECT 31 1867 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1868 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1869 1870 struct cpl_rte_delete_rpl { 1871 RSS_HDR 1872 union opcode_tid ot; 1873 __u8 status; 1874 __u8 rsvd[3]; 1875 }; 1876 1877 struct cpl_rte_write_req { 1878 WR_HDR; 1879 union opcode_tid ot; 1880 __u32 write_sel; 1881 __be32 lut_params; 1882 __be32 l2t_idx; 1883 __be32 netmask; 1884 __be32 faddr; 1885 }; 1886 1887 /* cpl_rte_write_req.write_sel fields */ 1888 #define S_RTE_WR_L2TIDX 31 1889 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1890 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1891 1892 #define S_RTE_WR_FADDR 30 1893 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1894 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1895 1896 /* cpl_rte_write_req.lut_params fields */ 1897 #define S_RTE_WR_LUT_IX 10 1898 #define M_RTE_WR_LUT_IX 0x7FF 1899 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1900 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1901 1902 #define S_RTE_WR_LUT_BASE 21 1903 #define M_RTE_WR_LUT_BASE 0x7FF 1904 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1905 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1906 1907 struct cpl_rte_write_rpl { 1908 RSS_HDR 1909 union opcode_tid ot; 1910 __u8 status; 1911 __u8 rsvd[3]; 1912 }; 1913 1914 struct cpl_rte_read_req { 1915 WR_HDR; 1916 union opcode_tid ot; 1917 __be32 params; 1918 }; 1919 1920 struct cpl_rte_read_rpl { 1921 RSS_HDR 1922 union opcode_tid ot; 1923 __u8 status; 1924 __u8 rsvd; 1925 __be16 l2t_idx; 1926 #if defined(__LITTLE_ENDIAN_BITFIELD) 1927 __u32 :30; 1928 __u32 select:1; 1929 #else 1930 __u32 select:1; 1931 __u32 :30; 1932 #endif 1933 __be32 addr; 1934 }; 1935 1936 struct cpl_l2t_write_req { 1937 WR_HDR; 1938 union opcode_tid ot; 1939 __be16 params; 1940 __be16 l2t_idx; 1941 __be16 vlan; 1942 __u8 dst_mac[6]; 1943 }; 1944 1945 /* cpl_l2t_write_req.params fields */ 1946 #define S_L2T_W_INFO 2 1947 #define M_L2T_W_INFO 0x3F 1948 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1949 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1950 1951 #define S_L2T_W_PORT 8 1952 #define M_L2T_W_PORT 0x3 1953 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1954 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1955 1956 #define S_L2T_W_LPBK 10 1957 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 1958 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 1959 1960 #define S_L2T_W_ARPMISS 11 1961 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 1962 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 1963 1964 #define S_L2T_W_NOREPLY 15 1965 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1966 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1967 1968 #define CPL_L2T_VLAN_NONE 0xfff 1969 1970 struct cpl_l2t_write_rpl { 1971 RSS_HDR 1972 union opcode_tid ot; 1973 __u8 status; 1974 __u8 rsvd[3]; 1975 }; 1976 1977 struct cpl_l2t_read_req { 1978 WR_HDR; 1979 union opcode_tid ot; 1980 __be32 l2t_idx; 1981 }; 1982 1983 struct cpl_l2t_read_rpl { 1984 RSS_HDR 1985 union opcode_tid ot; 1986 __u8 status; 1987 #if defined(__LITTLE_ENDIAN_BITFIELD) 1988 __u8 :4; 1989 __u8 iff:4; 1990 #else 1991 __u8 iff:4; 1992 __u8 :4; 1993 #endif 1994 __be16 vlan; 1995 __be16 info; 1996 __u8 dst_mac[6]; 1997 }; 1998 1999 struct cpl_smt_write_req { 2000 WR_HDR; 2001 union opcode_tid ot; 2002 __be32 params; 2003 __be16 pfvf1; 2004 __u8 src_mac1[6]; 2005 __be16 pfvf0; 2006 __u8 src_mac0[6]; 2007 }; 2008 2009 struct cpl_smt_write_rpl { 2010 RSS_HDR 2011 union opcode_tid ot; 2012 __u8 status; 2013 __u8 rsvd[3]; 2014 }; 2015 2016 struct cpl_smt_read_req { 2017 WR_HDR; 2018 union opcode_tid ot; 2019 __be32 params; 2020 }; 2021 2022 struct cpl_smt_read_rpl { 2023 RSS_HDR 2024 union opcode_tid ot; 2025 __u8 status; 2026 __u8 ovlan_idx; 2027 __be16 rsvd; 2028 __be16 pfvf1; 2029 __u8 src_mac1[6]; 2030 __be16 pfvf0; 2031 __u8 src_mac0[6]; 2032 }; 2033 2034 /* cpl_smt_{read,write}_req.params fields */ 2035 #define S_SMTW_OVLAN_IDX 16 2036 #define M_SMTW_OVLAN_IDX 0xF 2037 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2038 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2039 2040 #define S_SMTW_IDX 20 2041 #define M_SMTW_IDX 0x7F 2042 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2043 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2044 2045 #define S_SMTW_NORPL 31 2046 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2047 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2048 2049 /* cpl_smt_{read,write}_req.pfvf? fields */ 2050 #define S_SMTW_VF 0 2051 #define M_SMTW_VF 0xFF 2052 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2053 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2054 2055 #define S_SMTW_PF 8 2056 #define M_SMTW_PF 0x7 2057 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2058 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2059 2060 #define S_SMTW_VF_VLD 11 2061 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2062 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2063 2064 struct cpl_tag_write_req { 2065 WR_HDR; 2066 union opcode_tid ot; 2067 __be32 params; 2068 __be64 tag_val; 2069 }; 2070 2071 struct cpl_tag_write_rpl { 2072 RSS_HDR 2073 union opcode_tid ot; 2074 __u8 status; 2075 __u8 rsvd[2]; 2076 __u8 idx; 2077 }; 2078 2079 struct cpl_tag_read_req { 2080 WR_HDR; 2081 union opcode_tid ot; 2082 __be32 params; 2083 }; 2084 2085 struct cpl_tag_read_rpl { 2086 RSS_HDR 2087 union opcode_tid ot; 2088 __u8 status; 2089 #if defined(__LITTLE_ENDIAN_BITFIELD) 2090 __u8 :4; 2091 __u8 tag_len:1; 2092 __u8 :2; 2093 __u8 ins_enable:1; 2094 #else 2095 __u8 ins_enable:1; 2096 __u8 :2; 2097 __u8 tag_len:1; 2098 __u8 :4; 2099 #endif 2100 __u8 rsvd; 2101 __u8 tag_idx; 2102 __be64 tag_val; 2103 }; 2104 2105 /* cpl_tag{read,write}_req.params fields */ 2106 #define S_TAGW_IDX 0 2107 #define M_TAGW_IDX 0x7F 2108 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2109 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2110 2111 #define S_TAGW_LEN 20 2112 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2113 #define F_TAGW_LEN V_TAGW_LEN(1U) 2114 2115 #define S_TAGW_INS_ENABLE 23 2116 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2117 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2118 2119 #define S_TAGW_NORPL 31 2120 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2121 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2122 2123 struct cpl_barrier { 2124 WR_HDR; 2125 __u8 opcode; 2126 __u8 chan_map; 2127 __be16 rsvd0; 2128 __be32 rsvd1; 2129 }; 2130 2131 /* cpl_barrier.chan_map fields */ 2132 #define S_CHAN_MAP 4 2133 #define M_CHAN_MAP 0xF 2134 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2135 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2136 2137 struct cpl_error { 2138 RSS_HDR 2139 union opcode_tid ot; 2140 __be32 error; 2141 }; 2142 2143 struct cpl_hit_notify { 2144 RSS_HDR 2145 union opcode_tid ot; 2146 __be32 rsvd; 2147 __be32 info; 2148 __be32 reason; 2149 }; 2150 2151 struct cpl_pkt_notify { 2152 RSS_HDR 2153 union opcode_tid ot; 2154 __be16 rsvd; 2155 __be16 len; 2156 __be32 info; 2157 __be32 reason; 2158 }; 2159 2160 /* cpl_{hit,pkt}_notify.info fields */ 2161 #define S_NTFY_MAC_IDX 0 2162 #define M_NTFY_MAC_IDX 0x1FF 2163 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2164 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2165 2166 #define S_NTFY_INTF 10 2167 #define M_NTFY_INTF 0xF 2168 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2169 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2170 2171 #define S_NTFY_TCPHDR_LEN 14 2172 #define M_NTFY_TCPHDR_LEN 0xF 2173 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2174 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2175 2176 #define S_NTFY_IPHDR_LEN 18 2177 #define M_NTFY_IPHDR_LEN 0x1FF 2178 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2179 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2180 2181 #define S_NTFY_ETHHDR_LEN 27 2182 #define M_NTFY_ETHHDR_LEN 0x1F 2183 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2184 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2185 2186 #define S_NTFY_T5_IPHDR_LEN 18 2187 #define M_NTFY_T5_IPHDR_LEN 0xFF 2188 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2189 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2190 2191 #define S_NTFY_T5_ETHHDR_LEN 26 2192 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2193 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2194 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2195 2196 struct cpl_rdma_terminate { 2197 RSS_HDR 2198 union opcode_tid ot; 2199 __be16 rsvd; 2200 __be16 len; 2201 }; 2202 2203 struct cpl_set_le_req { 2204 WR_HDR; 2205 union opcode_tid ot; 2206 __be16 reply_ctrl; 2207 __be16 params; 2208 __be64 mask_hi; 2209 __be64 mask_lo; 2210 __be64 val_hi; 2211 __be64 val_lo; 2212 }; 2213 2214 /* cpl_set_le_req.reply_ctrl additional fields */ 2215 #define S_LE_REQ_IP6 13 2216 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2217 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2218 2219 /* cpl_set_le_req.params fields */ 2220 #define S_LE_CHAN 0 2221 #define M_LE_CHAN 0x3 2222 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2223 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2224 2225 #define S_LE_OFFSET 5 2226 #define M_LE_OFFSET 0x7 2227 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2228 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2229 2230 #define S_LE_MORE 8 2231 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2232 #define F_LE_MORE V_LE_MORE(1U) 2233 2234 #define S_LE_REQSIZE 9 2235 #define M_LE_REQSIZE 0x7 2236 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2237 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2238 2239 #define S_LE_REQCMD 12 2240 #define M_LE_REQCMD 0xF 2241 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2242 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2243 2244 struct cpl_set_le_rpl { 2245 RSS_HDR 2246 union opcode_tid ot; 2247 __u8 chan; 2248 __u8 info; 2249 __be16 len; 2250 }; 2251 2252 /* cpl_set_le_rpl.info fields */ 2253 #define S_LE_RSPCMD 0 2254 #define M_LE_RSPCMD 0xF 2255 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2256 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2257 2258 #define S_LE_RSPSIZE 4 2259 #define M_LE_RSPSIZE 0x7 2260 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2261 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2262 2263 #define S_LE_RSPTYPE 7 2264 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2265 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2266 2267 struct cpl_sge_egr_update { 2268 RSS_HDR 2269 __be32 opcode_qid; 2270 __be16 cidx; 2271 __be16 pidx; 2272 }; 2273 2274 /* cpl_sge_egr_update.ot fields */ 2275 #define S_EGR_QID 0 2276 #define M_EGR_QID 0x1FFFF 2277 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2278 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2279 2280 /* cpl_fw*.type values */ 2281 enum { 2282 FW_TYPE_CMD_RPL = 0, 2283 FW_TYPE_WR_RPL = 1, 2284 FW_TYPE_CQE = 2, 2285 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2286 FW_TYPE_RSSCPL = 4, 2287 }; 2288 2289 struct cpl_fw2_pld { 2290 RSS_HDR 2291 u8 opcode; 2292 u8 rsvd[5]; 2293 __be16 len; 2294 }; 2295 2296 struct cpl_fw4_pld { 2297 RSS_HDR 2298 u8 opcode; 2299 u8 rsvd0[3]; 2300 u8 type; 2301 u8 rsvd1; 2302 __be16 len; 2303 __be64 data; 2304 __be64 rsvd2; 2305 }; 2306 2307 struct cpl_fw6_pld { 2308 RSS_HDR 2309 u8 opcode; 2310 u8 rsvd[5]; 2311 __be16 len; 2312 __be64 data[4]; 2313 }; 2314 2315 struct cpl_fw2_msg { 2316 RSS_HDR 2317 union opcode_info oi; 2318 }; 2319 2320 struct cpl_fw4_msg { 2321 RSS_HDR 2322 u8 opcode; 2323 u8 type; 2324 __be16 rsvd0; 2325 __be32 rsvd1; 2326 __be64 data[2]; 2327 }; 2328 2329 struct cpl_fw4_ack { 2330 RSS_HDR 2331 union opcode_tid ot; 2332 u8 credits; 2333 u8 rsvd0[2]; 2334 u8 flags; 2335 __be32 snd_nxt; 2336 __be32 snd_una; 2337 __be64 rsvd1; 2338 }; 2339 2340 enum { 2341 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2342 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2343 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2344 }; 2345 2346 struct cpl_fw6_msg { 2347 RSS_HDR 2348 u8 opcode; 2349 u8 type; 2350 __be16 rsvd0; 2351 __be32 rsvd1; 2352 __be64 data[4]; 2353 }; 2354 2355 /* cpl_fw6_msg.type values */ 2356 enum { 2357 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2358 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2359 FW6_TYPE_CQE = FW_TYPE_CQE, 2360 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2361 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2362 2363 NUM_FW6_TYPES 2364 }; 2365 2366 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2367 __u64 cookie; 2368 __be32 tid; /* or atid in case of active failure */ 2369 __u8 t_state; 2370 __u8 retval; 2371 __u8 rsvd[2]; 2372 }; 2373 2374 /* ULP_TX opcodes */ 2375 enum { 2376 ULP_TX_MEM_READ = 2, 2377 ULP_TX_MEM_WRITE = 3, 2378 ULP_TX_PKT = 4 2379 }; 2380 2381 enum { 2382 ULP_TX_SC_NOOP = 0x80, 2383 ULP_TX_SC_IMM = 0x81, 2384 ULP_TX_SC_DSGL = 0x82, 2385 ULP_TX_SC_ISGL = 0x83 2386 }; 2387 2388 #define S_ULPTX_CMD 24 2389 #define M_ULPTX_CMD 0xFF 2390 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2391 2392 #define S_ULPTX_LEN16 0 2393 #define M_ULPTX_LEN16 0xFF 2394 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2395 2396 #define S_ULP_TX_SC_MORE 23 2397 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2398 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2399 2400 struct ulptx_sge_pair { 2401 __be32 len[2]; 2402 __be64 addr[2]; 2403 }; 2404 2405 struct ulptx_sgl { 2406 __be32 cmd_nsge; 2407 __be32 len0; 2408 __be64 addr0; 2409 #if !(defined C99_NOT_SUPPORTED) 2410 struct ulptx_sge_pair sge[0]; 2411 #endif 2412 }; 2413 2414 struct ulptx_isge { 2415 __be32 stag; 2416 __be32 len; 2417 __be64 target_ofst; 2418 }; 2419 2420 struct ulptx_isgl { 2421 __be32 cmd_nisge; 2422 __be32 rsvd; 2423 #if !(defined C99_NOT_SUPPORTED) 2424 struct ulptx_isge sge[0]; 2425 #endif 2426 }; 2427 2428 struct ulptx_idata { 2429 __be32 cmd_more; 2430 __be32 len; 2431 }; 2432 2433 #define S_ULPTX_NSGE 0 2434 #define M_ULPTX_NSGE 0xFFFF 2435 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2436 2437 struct ulp_mem_io { 2438 WR_HDR; 2439 __be32 cmd; 2440 __be32 len16; /* command length */ 2441 __be32 dlen; /* data length in 32-byte units */ 2442 __be32 lock_addr; 2443 }; 2444 2445 /* additional ulp_mem_io.cmd fields */ 2446 #define S_ULP_MEMIO_ORDER 23 2447 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2448 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2449 2450 #define S_T5_ULP_MEMIO_IMM 23 2451 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2452 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2453 2454 #define S_T5_ULP_MEMIO_ORDER 22 2455 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2456 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2457 2458 /* ulp_mem_io.lock_addr fields */ 2459 #define S_ULP_MEMIO_ADDR 0 2460 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2461 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2462 2463 #define S_ULP_MEMIO_LOCK 31 2464 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2465 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2466 2467 /* ulp_mem_io.dlen fields */ 2468 #define S_ULP_MEMIO_DATA_LEN 0 2469 #define M_ULP_MEMIO_DATA_LEN 0x1F 2470 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2471 2472 /* ULP_TXPKT field values */ 2473 enum { 2474 ULP_TXPKT_DEST_TP = 0, 2475 ULP_TXPKT_DEST_SGE, 2476 ULP_TXPKT_DEST_UP, 2477 ULP_TXPKT_DEST_DEVNULL, 2478 }; 2479 2480 struct ulp_txpkt { 2481 __be32 cmd_dest; 2482 __be32 len; 2483 }; 2484 2485 /* ulp_txpkt.cmd_dest fields */ 2486 #define S_ULP_TXPKT_DEST 16 2487 #define M_ULP_TXPKT_DEST 0x3 2488 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2489 2490 #define S_ULP_TXPKT_FID 4 2491 #define M_ULP_TXPKT_FID 0x7ff 2492 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2493 2494 #define S_ULP_TXPKT_RO 3 2495 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2496 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2497 2498 #endif /* T4_MSG_H */ 2499