1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2016, 2025 Chelsio Communications. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef T4_MSG_H 30 #define T4_MSG_H 31 32 enum cpl_opcodes { 33 CPL_TLS_TX_SCMD_FMT = 0x0, 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_GRE_TABLE_REQ = 0x1b, 53 CPL_GRE_TABLE_RPL = 0xbb, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TAG_WRITE_REQ = 0x16, 57 CPL_BARRIER = 0x18, 58 CPL_TID_RELEASE = 0x1A, 59 CPL_TAG_READ_REQ = 0x1B, 60 CPL_SRQ_TABLE_REQ = 0x1C, 61 CPL_TX_PKT_FSO = 0x1E, 62 CPL_TX_DATA_ISO = 0x1F, 63 64 CPL_CLOSE_LISTSRV_RPL = 0x20, 65 CPL_ERROR = 0x21, 66 CPL_GET_TCB_RPL = 0x22, 67 CPL_L2T_WRITE_RPL = 0x23, 68 CPL_PASS_OPEN_RPL = 0x24, 69 CPL_ACT_OPEN_RPL = 0x25, 70 CPL_PEER_CLOSE = 0x26, 71 CPL_RTE_DELETE_RPL = 0x27, 72 CPL_RTE_WRITE_RPL = 0x28, 73 CPL_ROCE_FW_NOTIFY = 0x28, 74 CPL_RX_URG_PKT = 0x29, 75 CPL_TAG_WRITE_RPL = 0x2A, 76 CPL_RDMA_ASYNC_EVENT = 0x2A, 77 CPL_ABORT_REQ_RSS = 0x2B, 78 CPL_RX_URG_NOTIFY = 0x2C, 79 CPL_ABORT_RPL_RSS = 0x2D, 80 CPL_SMT_WRITE_RPL = 0x2E, 81 CPL_TX_DATA_ACK = 0x2F, 82 CPL_RDMA_INV_REQ = 0x2F, 83 84 CPL_RX_PHYS_ADDR = 0x30, 85 CPL_PCMD_READ_RPL = 0x31, 86 CPL_CLOSE_CON_RPL = 0x32, 87 CPL_ISCSI_HDR = 0x33, 88 CPL_L2T_READ_RPL = 0x34, 89 CPL_RDMA_CQE = 0x35, 90 CPL_RDMA_CQE_READ_RSP = 0x36, 91 CPL_RDMA_CQE_ERR = 0x37, 92 CPL_RTE_READ_RPL = 0x38, 93 CPL_RX_DATA = 0x39, 94 CPL_SET_TCB_RPL = 0x3A, 95 CPL_RX_PKT = 0x3B, 96 CPL_TAG_READ_RPL = 0x3C, 97 CPL_HIT_NOTIFY = 0x3D, 98 CPL_PKT_NOTIFY = 0x3E, 99 CPL_RX_DDP_COMPLETE = 0x3F, 100 101 CPL_ACT_ESTABLISH = 0x40, 102 CPL_PASS_ESTABLISH = 0x41, 103 CPL_RX_DATA_DDP = 0x42, 104 CPL_SMT_READ_RPL = 0x43, 105 CPL_PASS_ACCEPT_REQ = 0x44, 106 CPL_RX_ISCSI_CMP = 0x45, 107 CPL_RX_FCOE_DDP = 0x46, 108 CPL_FCOE_HDR = 0x47, 109 CPL_T5_TRACE_PKT = 0x48, 110 CPL_RX_ISCSI_DDP = 0x49, 111 CPL_RX_FCOE_DIF = 0x4A, 112 CPL_RX_DATA_DIF = 0x4B, 113 CPL_ERR_NOTIFY = 0x4D, 114 CPL_RX_TLS_CMP = 0x4E, 115 CPL_T6_TX_DATA_ACK = 0x4F, 116 117 CPL_RDMA_READ_REQ = 0x60, 118 CPL_RX_ISCSI_DIF = 0x60, 119 CPL_RDMA_CQE_EXT = 0x61, 120 CPL_RDMA_CQE_FW_EXT = 0x62, 121 CPL_RDMA_CQE_ERR_EXT = 0x63, 122 CPL_TX_DATA_ACK_XT = 0x64, 123 CPL_ROCE_CQE = 0x68, 124 CPL_ROCE_CQE_FW = 0x69, 125 CPL_ROCE_CQE_ERR = 0x6A, 126 127 CPL_SACK_REQ = 0x70, 128 129 CPL_SET_LE_REQ = 0x80, 130 CPL_PASS_OPEN_REQ6 = 0x81, 131 CPL_ACT_OPEN_REQ6 = 0x83, 132 CPL_TX_TLS_PDU = 0x88, 133 CPL_TX_TLS_SFO = 0x89, 134 CPL_TX_SEC_PDU = 0x8A, 135 CPL_TX_TLS_ACK = 0x8B, 136 CPL_TX_QUIC_ENC = 0x8d, 137 CPL_RCB_UPD = 0x8C, 138 139 CPL_SGE_FLR_FLUSH = 0xA0, 140 CPL_RDMA_TERMINATE = 0xA2, 141 CPL_RDMA_WRITE = 0xA4, 142 CPL_SGE_EGR_UPDATE = 0xA5, 143 CPL_SET_LE_RPL = 0xA6, 144 CPL_FW2_MSG = 0xA7, 145 CPL_FW2_PLD = 0xA8, 146 CPL_T5_RDMA_READ_REQ = 0xA9, 147 CPL_RDMA_ATOMIC_REQ = 0xAA, 148 CPL_RDMA_ATOMIC_RPL = 0xAB, 149 CPL_RDMA_IMM_DATA = 0xAC, 150 CPL_RDMA_IMM_DATA_SE = 0xAD, 151 CPL_RX_MPS_PKT = 0xAF, 152 153 CPL_TRACE_PKT = 0xB0, 154 CPL_RX2TX_DATA = 0xB1, 155 CPL_TLS_DATA = 0xB1, 156 CPL_ISCSI_DATA = 0xB2, 157 CPL_FCOE_DATA = 0xB3, 158 CPL_NVMT_DATA = 0xB4, 159 CPL_NVMT_CMP = 0xB5, 160 CPL_NVMT_CMP_IMM = 0xB6, 161 CPL_NVMT_CMP_SRQ = 0xB7, 162 CPL_ROCE_ACK_NAK_REQ = 0xBC, 163 CPL_ROCE_ACK_NAK = 0xBD, 164 165 CPL_FW4_MSG = 0xC0, 166 CPL_FW4_PLD = 0xC1, 167 CPL_RDMA_CQE_SRQ = 0xC2, 168 CPL_ACCELERATOR_ACK = 0xC4, 169 CPL_FW4_ACK = 0xC3, 170 CPL_RX_PKT_IPSEC = 0xC6, 171 CPL_SRQ_TABLE_RPL = 0xCC, 172 CPL_TX_DATA_REQ = 0xCF, 173 174 CPL_RX_PHYS_DSGL = 0xD0, 175 176 CPL_FW6_MSG = 0xE0, 177 CPL_FW6_PLD = 0xE1, 178 CPL_ACCELERATOR_HDR = 0xE8, 179 CPL_TX_TNL_LSO = 0xEC, 180 CPL_TX_PKT_LSO = 0xED, 181 CPL_TX_PKT_XT = 0xEE, 182 183 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 184 }; 185 186 enum CPL_error { 187 CPL_ERR_NONE = 0, 188 CPL_ERR_TCAM_PARITY = 1, 189 CPL_ERR_TCAM_MISS = 2, 190 CPL_ERR_TCAM_FULL = 3, 191 CPL_ERR_BAD_LENGTH = 15, 192 CPL_ERR_BAD_ROUTE = 18, 193 CPL_ERR_CONN_RESET = 20, 194 CPL_ERR_CONN_EXIST_SYNRECV = 21, 195 CPL_ERR_CONN_EXIST = 22, 196 CPL_ERR_ARP_MISS = 23, 197 CPL_ERR_BAD_SYN = 24, 198 CPL_ERR_CONN_TIMEDOUT = 30, 199 CPL_ERR_XMIT_TIMEDOUT = 31, 200 CPL_ERR_PERSIST_TIMEDOUT = 32, 201 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 202 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 203 CPL_ERR_RTX_NEG_ADVICE = 35, 204 CPL_ERR_PERSIST_NEG_ADVICE = 36, 205 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 206 CPL_ERR_WAIT_ARP_RPL = 41, 207 CPL_ERR_ABORT_FAILED = 42, 208 CPL_ERR_IWARP_FLM = 50, 209 CPL_CONTAINS_READ_RPL = 60, 210 CPL_CONTAINS_WRITE_RPL = 61, 211 }; 212 213 /* 214 * Some of the error codes above implicitly indicate that there is no TID 215 * allocated with the result of an ACT_OPEN. We use this predicate to make 216 * that explicit. 217 */ 218 static inline int act_open_has_tid(int status) 219 { 220 return (status != CPL_ERR_TCAM_PARITY && 221 status != CPL_ERR_TCAM_MISS && 222 status != CPL_ERR_TCAM_FULL && 223 status != CPL_ERR_CONN_EXIST_SYNRECV && 224 status != CPL_ERR_CONN_EXIST); 225 } 226 227 /* 228 * Convert an ACT_OPEN_RPL status to an errno. 229 */ 230 static inline int 231 act_open_rpl_status_to_errno(int status) 232 { 233 234 switch (status) { 235 case CPL_ERR_CONN_RESET: 236 return (ECONNREFUSED); 237 case CPL_ERR_ARP_MISS: 238 return (EHOSTUNREACH); 239 case CPL_ERR_CONN_TIMEDOUT: 240 return (ETIMEDOUT); 241 case CPL_ERR_TCAM_FULL: 242 return (EAGAIN); 243 case CPL_ERR_CONN_EXIST: 244 return (EAGAIN); 245 default: 246 return (EIO); 247 } 248 } 249 250 251 enum { 252 CPL_CONN_POLICY_AUTO = 0, 253 CPL_CONN_POLICY_ASK = 1, 254 CPL_CONN_POLICY_FILTER = 2, 255 CPL_CONN_POLICY_DENY = 3 256 }; 257 258 enum { 259 ULP_MODE_NONE = 0, 260 ULP_MODE_ISCSI = 2, 261 ULP_MODE_RDMA = 4, 262 ULP_MODE_TCPDDP = 5, 263 ULP_MODE_FCOE = 6, 264 ULP_MODE_TLS = 8, 265 ULP_MODE_DTLS = 9, 266 ULP_MODE_RDMA_V2 = 10, 267 ULP_MODE_NVMET = 11, 268 }; 269 270 enum { 271 ULP_CRC_HEADER = 1 << 0, 272 ULP_CRC_DATA = 1 << 1 273 }; 274 275 enum { 276 CPL_PASS_OPEN_ACCEPT, 277 CPL_PASS_OPEN_REJECT, 278 CPL_PASS_OPEN_ACCEPT_TNL 279 }; 280 281 enum { 282 CPL_ABORT_SEND_RST = 0, 283 CPL_ABORT_NO_RST, 284 }; 285 286 enum { /* TX_PKT_XT checksum types */ 287 TX_CSUM_TCP = 0, 288 TX_CSUM_UDP = 1, 289 TX_CSUM_CRC16 = 4, 290 TX_CSUM_CRC32 = 5, 291 TX_CSUM_CRC32C = 6, 292 TX_CSUM_FCOE = 7, 293 TX_CSUM_TCPIP = 8, 294 TX_CSUM_UDPIP = 9, 295 TX_CSUM_TCPIP6 = 10, 296 TX_CSUM_UDPIP6 = 11, 297 TX_CSUM_IP = 12, 298 }; 299 300 enum { /* packet type in CPL_RX_PKT */ 301 PKTYPE_XACT_UCAST = 0, 302 PKTYPE_HASH_UCAST = 1, 303 PKTYPE_XACT_MCAST = 2, 304 PKTYPE_HASH_MCAST = 3, 305 PKTYPE_PROMISC = 4, 306 PKTYPE_HPROMISC = 5, 307 PKTYPE_BCAST = 6 308 }; 309 310 enum { /* DMAC type in CPL_RX_PKT */ 311 DATYPE_UCAST, 312 DATYPE_MCAST, 313 DATYPE_BCAST 314 }; 315 316 enum { /* TCP congestion control algorithms */ 317 CONG_ALG_RENO, 318 CONG_ALG_TAHOE, 319 CONG_ALG_NEWRENO, 320 CONG_ALG_HIGHSPEED 321 }; 322 323 enum { /* RSS hash type */ 324 RSS_HASH_NONE = 0, /* no hash computed */ 325 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 326 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 327 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 328 }; 329 330 enum { /* LE commands */ 331 LE_CMD_READ = 0x4, 332 LE_CMD_WRITE = 0xb 333 }; 334 335 enum { /* LE request size */ 336 LE_SZ_NONE = 0, 337 LE_SZ_33 = 1, 338 LE_SZ_66 = 2, 339 LE_SZ_132 = 3, 340 LE_SZ_264 = 4, 341 LE_SZ_528 = 5 342 }; 343 344 union opcode_tid { 345 __be32 opcode_tid; 346 __u8 opcode; 347 }; 348 349 #define S_CPL_OPCODE 24 350 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 351 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 352 #define G_TID(x) ((x) & 0xFFFFFF) 353 354 /* tid is assumed to be 24-bits */ 355 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 356 357 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 358 359 /* extract the TID from a CPL command */ 360 #define GET_TID(cmd) (G_TID(be32toh(OPCODE_TID(cmd)))) 361 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 362 363 364 /* 365 * Note that this driver splits the 14b opaque atid into an 11b atid and a 3b 366 * cookie that is used to demux replies for shared CPLs. 367 */ 368 /* partitioning of TID fields that also carry a queue id */ 369 #define S_TID_TID 0 370 #define M_TID_TID 0x7ff 371 #define V_TID_TID(x) ((x) << S_TID_TID) 372 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 373 374 #define S_TID_COOKIE 11 375 #define M_TID_COOKIE 0x7 376 #define V_TID_COOKIE(x) ((x) << S_TID_COOKIE) 377 #define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE) 378 379 #define S_TID_QID 14 380 #define M_TID_QID 0x3ff 381 #define V_TID_QID(x) ((x) << S_TID_QID) 382 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 383 384 union opcode_info { 385 __be64 opcode_info; 386 __u8 opcode; 387 }; 388 389 struct tcp_options { 390 __be16 mss; 391 __u8 wsf; 392 #if defined(__LITTLE_ENDIAN_BITFIELD) 393 __u8 :4; 394 __u8 unknown:1; 395 __u8 ecn:1; 396 __u8 sack:1; 397 __u8 tstamp:1; 398 #else 399 __u8 tstamp:1; 400 __u8 sack:1; 401 __u8 ecn:1; 402 __u8 unknown:1; 403 __u8 :4; 404 #endif 405 }; 406 407 struct rss_header { 408 __u8 opcode; 409 #if defined(__LITTLE_ENDIAN_BITFIELD) 410 __u8 channel:2; 411 __u8 filter_hit:1; 412 __u8 filter_tid:1; 413 __u8 hash_type:2; 414 __u8 ipv6:1; 415 __u8 send2fw:1; 416 #else 417 __u8 send2fw:1; 418 __u8 ipv6:1; 419 __u8 hash_type:2; 420 __u8 filter_tid:1; 421 __u8 filter_hit:1; 422 __u8 channel:2; 423 #endif 424 __be16 qid; 425 __be32 hash_val; 426 }; 427 428 #define S_HASHTYPE 20 429 #define M_HASHTYPE 0x3 430 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 431 432 #define S_QNUM 0 433 #define M_QNUM 0xFFFF 434 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 435 436 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 437 # define RSS_HDR struct rss_header rss_hdr; 438 #else 439 # define RSS_HDR 440 #endif 441 442 #ifndef CHELSIO_FW 443 struct work_request_hdr { 444 __be32 wr_hi; 445 __be32 wr_mid; 446 __be64 wr_lo; 447 }; 448 449 /* wr_mid fields */ 450 #define S_WR_LEN16 0 451 #define M_WR_LEN16 0xFF 452 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 453 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 454 455 /* wr_hi fields */ 456 #define S_WR_OP 24 457 #define M_WR_OP 0xFF 458 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 459 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 460 461 # define WR_HDR struct work_request_hdr wr 462 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 463 #else 464 # define WR_HDR 465 # define WR_HDR_SIZE 0 466 #endif 467 468 /* option 0 fields */ 469 #define S_ACCEPT_MODE 0 470 #define M_ACCEPT_MODE 0x3 471 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 472 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 473 474 #define S_TX_CHAN 2 475 #define M_TX_CHAN 0x3 476 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 477 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 478 479 #define S_NO_CONG 4 480 #define V_NO_CONG(x) ((x) << S_NO_CONG) 481 #define F_NO_CONG V_NO_CONG(1U) 482 483 #define S_DELACK 5 484 #define V_DELACK(x) ((x) << S_DELACK) 485 #define F_DELACK V_DELACK(1U) 486 487 #define S_INJECT_TIMER 6 488 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 489 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 490 491 #define S_NON_OFFLOAD 7 492 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 493 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 494 495 #define S_ULP_MODE 8 496 #define M_ULP_MODE 0xF 497 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 498 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 499 500 #define S_RCV_BUFSIZ 12 501 #define M_RCV_BUFSIZ 0x3FFU 502 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 503 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 504 505 #define S_DSCP 22 506 #define M_DSCP 0x3F 507 #define V_DSCP(x) ((x) << S_DSCP) 508 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 509 510 #define S_SMAC_SEL 28 511 #define M_SMAC_SEL 0xFF 512 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 513 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 514 515 #define S_L2T_IDX 36 516 #define M_L2T_IDX 0xFFF 517 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 518 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 519 520 #define S_TCAM_BYPASS 48 521 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 522 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 523 524 #define S_NAGLE 49 525 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 526 #define F_NAGLE V_NAGLE(1ULL) 527 528 #define S_WND_SCALE 50 529 #define M_WND_SCALE 0xF 530 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 531 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 532 533 #define S_KEEP_ALIVE 54 534 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 535 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 536 537 #define S_MAX_RT 55 538 #define M_MAX_RT 0xF 539 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 540 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 541 542 #define S_MAX_RT_OVERRIDE 59 543 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 544 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 545 546 #define S_MSS_IDX 60 547 #define M_MSS_IDX 0xF 548 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 549 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 550 551 /* option 1 fields */ 552 #define S_SYN_RSS_ENABLE 0 553 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 554 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 555 556 #define S_SYN_RSS_USE_HASH 1 557 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 558 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 559 560 #define S_SYN_RSS_QUEUE 2 561 #define M_SYN_RSS_QUEUE 0x3FF 562 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 563 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 564 565 #define S_LISTEN_INTF 12 566 #define M_LISTEN_INTF 0xFF 567 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 568 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 569 570 #define S_LISTEN_FILTER 20 571 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 572 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 573 574 #define S_SYN_DEFENSE 21 575 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 576 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 577 578 #define S_CONN_POLICY 22 579 #define M_CONN_POLICY 0x3 580 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 581 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 582 583 #define S_T5_FILT_INFO 24 584 #define M_T5_FILT_INFO 0xffffffffffULL 585 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 586 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 587 588 #define S_FILT_INFO 28 589 #define M_FILT_INFO 0xfffffffffULL 590 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 591 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 592 593 /* option 2 fields */ 594 #define S_RSS_QUEUE 0 595 #define M_RSS_QUEUE 0x3FF 596 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 597 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 598 599 #define S_RSS_QUEUE_VALID 10 600 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 601 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 602 603 #define S_RX_COALESCE_VALID 11 604 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 605 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 606 607 #define S_RX_COALESCE 12 608 #define M_RX_COALESCE 0x3 609 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 610 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 611 612 #define S_CONG_CNTRL 14 613 #define M_CONG_CNTRL 0x3 614 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 615 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 616 617 #define S_PACE 16 618 #define M_PACE 0x3 619 #define V_PACE(x) ((x) << S_PACE) 620 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 621 622 #define S_CONG_CNTRL_VALID 18 623 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 624 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 625 626 #define S_T5_ISS 18 627 #define V_T5_ISS(x) ((x) << S_T5_ISS) 628 #define F_T5_ISS V_T5_ISS(1U) 629 630 #define S_PACE_VALID 19 631 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 632 #define F_PACE_VALID V_PACE_VALID(1U) 633 634 #define S_RX_FC_DISABLE 20 635 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 636 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 637 638 #define S_RX_FC_DDP 21 639 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 640 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 641 642 #define S_RX_FC_VALID 22 643 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 644 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 645 646 #define S_TX_QUEUE 23 647 #define M_TX_QUEUE 0x7 648 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 649 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 650 651 #define S_RX_CHANNEL 26 652 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 653 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 654 655 #define S_CCTRL_ECN 27 656 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 657 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 658 659 #define S_WND_SCALE_EN 28 660 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 661 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 662 663 #define S_TSTAMPS_EN 29 664 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 665 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 666 667 #define S_SACK_EN 30 668 #define V_SACK_EN(x) ((x) << S_SACK_EN) 669 #define F_SACK_EN V_SACK_EN(1U) 670 671 #define S_T5_OPT_2_VALID 31 672 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 673 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 674 675 struct cpl_pass_open_req { 676 WR_HDR; 677 union opcode_tid ot; 678 __be16 local_port; 679 __be16 peer_port; 680 __be32 local_ip; 681 __be32 peer_ip; 682 __be64 opt0; 683 __be64 opt1; 684 }; 685 686 struct cpl_pass_open_req6 { 687 WR_HDR; 688 union opcode_tid ot; 689 __be16 local_port; 690 __be16 peer_port; 691 __be64 local_ip_hi; 692 __be64 local_ip_lo; 693 __be64 peer_ip_hi; 694 __be64 peer_ip_lo; 695 __be64 opt0; 696 __be64 opt1; 697 }; 698 699 struct cpl_pass_open_rpl { 700 RSS_HDR 701 union opcode_tid ot; 702 __u8 rsvd[3]; 703 __u8 status; 704 }; 705 706 struct cpl_pass_establish { 707 RSS_HDR 708 union opcode_tid ot; 709 __be32 rsvd; 710 __be32 tos_stid; 711 __be16 mac_idx; 712 __be16 tcp_opt; 713 __be32 snd_isn; 714 __be32 rcv_isn; 715 }; 716 717 /* cpl_pass_establish.tos_stid fields */ 718 #define S_PASS_OPEN_TID 0 719 #define M_PASS_OPEN_TID 0xFFFFFF 720 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 721 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 722 723 #define S_PASS_OPEN_TOS 24 724 #define M_PASS_OPEN_TOS 0xFF 725 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 726 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 727 728 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 729 #define S_TCPOPT_WSCALE_OK 5 730 #define M_TCPOPT_WSCALE_OK 0x1 731 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 732 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 733 734 #define S_TCPOPT_SACK 6 735 #define M_TCPOPT_SACK 0x1 736 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 737 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 738 739 #define S_TCPOPT_TSTAMP 7 740 #define M_TCPOPT_TSTAMP 0x1 741 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 742 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 743 744 #define S_TCPOPT_SND_WSCALE 8 745 #define M_TCPOPT_SND_WSCALE 0xF 746 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 747 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 748 749 #define S_TCPOPT_MSS 12 750 #define M_TCPOPT_MSS 0xF 751 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 752 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 753 754 struct cpl_pass_accept_req { 755 RSS_HDR 756 union opcode_tid ot; 757 __be16 ipsecen_outiphdrlen; 758 __be16 len; 759 __be32 hdr_len; 760 __be16 vlan; 761 __be16 l2info; 762 __be32 tos_stid; 763 struct tcp_options tcpopt; 764 }; 765 766 /* cpl_pass_accept_req.hdr_len fields */ 767 #define S_SYN_RX_CHAN 0 768 #define M_SYN_RX_CHAN 0xF 769 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 770 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 771 772 #define S_TCP_HDR_LEN 10 773 #define M_TCP_HDR_LEN 0x3F 774 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 775 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 776 777 #define S_T6_TCP_HDR_LEN 8 778 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 779 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 780 781 #define S_IP_HDR_LEN 16 782 #define M_IP_HDR_LEN 0x3FF 783 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 784 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 785 786 #define S_T6_IP_HDR_LEN 14 787 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 788 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 789 790 #define S_ETH_HDR_LEN 26 791 #define M_ETH_HDR_LEN 0x3F 792 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 793 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 794 795 #define S_T6_ETH_HDR_LEN 24 796 #define M_T6_ETH_HDR_LEN 0xFF 797 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 798 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 799 800 /* cpl_pass_accept_req.l2info fields */ 801 #define S_SYN_MAC_IDX 0 802 #define M_SYN_MAC_IDX 0x1FF 803 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 804 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 805 806 #define S_SYN_XACT_MATCH 9 807 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 808 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 809 810 #define S_SYN_INTF 12 811 #define M_SYN_INTF 0xF 812 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 813 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 814 815 struct cpl_t7_pass_accept_req { 816 RSS_HDR 817 union opcode_tid ot; 818 __be16 ipsecen_to_outiphdrlen; 819 __be16 length; 820 __be32 ethhdrlen_to_rxchannel; 821 __be16 vlantag; 822 __be16 interface_to_mac_ix; 823 __be32 tos_ptid; 824 __be16 tcpmss; 825 __u8 tcpwsc; 826 __u8 tcptmstp_to_tcpunkn; 827 }; 828 829 #define S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN 12 830 #define M_CPL_T7_PASS_ACCEPT_REQ_IPSECEN 0x1 831 #define V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x) \ 832 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) 833 #define G_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(x) \ 834 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) & \ 835 M_CPL_T7_PASS_ACCEPT_REQ_IPSECEN) 836 #define F_CPL_PASS_T7_ACCEPT_REQ_IPSECEN \ 837 V_CPL_T7_PASS_ACCEPT_REQ_IPSECEN(1U) 838 839 #define S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE 10 840 #define M_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE 0x3 841 #define V_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x) \ 842 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) 843 #define G_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE(x) \ 844 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) & \ 845 M_CPL_T7_PASS_ACCEPT_REQ_IPSECTYPE) 846 847 #define S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN 0 848 #define M_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN 0x3ff 849 #define V_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \ 850 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) 851 #define G_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN(x) \ 852 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) & \ 853 M_CPL_T7_PASS_ACCEPT_REQ_OUTIPHDRLEN) 854 855 #define S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN 24 856 #define M_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN 0xff 857 #define V_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x) \ 858 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) 859 #define G_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN(x) \ 860 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) & \ 861 M_CPL_T7_PASS_ACCEPT_REQ_ETHHDRLEN) 862 863 #define S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN 14 864 #define M_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN 0x3ff 865 #define V_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x) \ 866 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) 867 #define G_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN(x) \ 868 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) & \ 869 M_CPL_T7_PASS_ACCEPT_REQ_IPHDRLEN) 870 871 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN 8 872 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN 0x3f 873 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x) \ 874 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) 875 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN(x) \ 876 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) & \ 877 M_CPL_T7_PASS_ACCEPT_REQ_TCPHDRLEN) 878 879 #define S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL 0 880 #define M_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL 0xf 881 #define V_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x) \ 882 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) 883 #define G_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL(x) \ 884 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) & \ 885 M_CPL_T7_PASS_ACCEPT_REQ_RXCHANNEL) 886 887 #define S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE 12 888 #define M_CPL_T7_PASS_ACCEPT_REQ_INTERFACE 0xf 889 #define V_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x) \ 890 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) 891 #define G_CPL_T7_PASS_ACCEPT_REQ_INTERFACE(x) \ 892 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) & \ 893 M_CPL_T7_PASS_ACCEPT_REQ_INTERFACE) 894 895 #define S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH 9 896 #define M_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH 0x1 897 #define V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x) \ 898 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) 899 #define G_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(x) \ 900 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) & \ 901 M_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH) 902 #define F_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH \ 903 V_CPL_T7_PASS_ACCEPT_REQ_MAC_MATCH(1U) 904 905 #define S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX 0 906 #define M_CPL_T7_PASS_ACCEPT_REQ_MAC_IX 0x1ff 907 #define V_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x) \ 908 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) 909 #define G_CPL_T7_PASS_ACCEPT_REQ_MAC_IX(x) \ 910 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) & M_CPL_T7_PASS_ACCEPT_REQ_MAC_IX) 911 912 #define S_CPL_T7_PASS_ACCEPT_REQ_TOS 24 913 #define M_CPL_T7_PASS_ACCEPT_REQ_TOS 0xff 914 #define V_CPL_T7_PASS_ACCEPT_REQ_TOS(x) ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TOS) 915 #define G_CPL_T7_PASS_ACCEPT_REQ_TOS(x) \ 916 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TOS) & M_CPL_T7_PASS_ACCEPT_REQ_TOS) 917 918 #define S_CPL_T7_PASS_ACCEPT_REQ_PTID 0 919 #define M_CPL_T7_PASS_ACCEPT_REQ_PTID 0xffffff 920 #define V_CPL_T7_PASS_ACCEPT_REQ_PTID(x) \ 921 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_PTID) 922 #define G_CPL_T7_PASS_ACCEPT_REQ_PTID(x) \ 923 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_PTID) & M_CPL_T7_PASS_ACCEPT_REQ_PTID) 924 925 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP 7 926 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP 0x1 927 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x) \ 928 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) 929 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(x) \ 930 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) & \ 931 M_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP) 932 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP \ 933 V_CPL_T7_PASS_ACCEPT_REQ_TCPTMSTP(1U) 934 935 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK 6 936 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPSACK 0x1 937 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x) \ 938 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) 939 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(x) \ 940 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) & \ 941 M_CPL_T7_PASS_ACCEPT_REQ_TCPSACK) 942 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPSACK \ 943 V_CPL_T7_PASS_ACCEPT_REQ_TCPSACK(1U) 944 945 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPECN 5 946 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPECN 0x1 947 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x) \ 948 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPECN) 949 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPECN(x) \ 950 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPECN) & M_CPL_T7_PASS_ACCEPT_REQ_TCPECN) 951 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPECN \ 952 V_CPL_T7_PASS_ACCEPT_REQ_TCPECN(1U) 953 954 #define S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN 4 955 #define M_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN 0x1 956 #define V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x) \ 957 ((x) << S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) 958 #define G_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(x) \ 959 (((x) >> S_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) & \ 960 M_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN) 961 #define F_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN \ 962 V_CPL_T7_PASS_ACCEPT_REQ_TCPUNKN(1U) 963 964 struct cpl_pass_accept_rpl { 965 WR_HDR; 966 union opcode_tid ot; 967 __be32 opt2; 968 __be64 opt0; 969 }; 970 971 struct cpl_t5_pass_accept_rpl { 972 WR_HDR; 973 union opcode_tid ot; 974 __be32 opt2; 975 __be64 opt0; 976 __be32 iss; 977 union { 978 __be32 rsvd; /* T5 */ 979 __be32 opt3; /* T6 */ 980 } u; 981 }; 982 983 struct cpl_act_open_req { 984 WR_HDR; 985 union opcode_tid ot; 986 __be16 local_port; 987 __be16 peer_port; 988 __be32 local_ip; 989 __be32 peer_ip; 990 __be64 opt0; 991 __be32 params; 992 __be32 opt2; 993 }; 994 995 #define S_FILTER_TUPLE 24 996 #define M_FILTER_TUPLE 0xFFFFFFFFFF 997 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 998 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 999 1000 struct cpl_t5_act_open_req { 1001 WR_HDR; 1002 union opcode_tid ot; 1003 __be16 local_port; 1004 __be16 peer_port; 1005 __be32 local_ip; 1006 __be32 peer_ip; 1007 __be64 opt0; 1008 __be32 iss; 1009 __be32 opt2; 1010 __be64 params; 1011 }; 1012 1013 struct cpl_t6_act_open_req { 1014 WR_HDR; 1015 union opcode_tid ot; 1016 __be16 local_port; 1017 __be16 peer_port; 1018 __be32 local_ip; 1019 __be32 peer_ip; 1020 __be64 opt0; 1021 __be32 iss; 1022 __be32 opt2; 1023 __be64 params; 1024 __be32 rsvd2; 1025 __be32 opt3; 1026 }; 1027 1028 /* cpl_{t5,t6}_act_open_req.params field */ 1029 #define S_AOPEN_FCOEMASK 0 1030 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 1031 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 1032 1033 struct cpl_t7_act_open_req { 1034 WR_HDR; 1035 union opcode_tid ot; 1036 __be16 local_port; 1037 __be16 peer_port; 1038 __be32 local_ip; 1039 __be32 peer_ip; 1040 __be64 opt0; 1041 __be32 iss; 1042 __be32 opt2; 1043 __be64 params; 1044 __be32 rsvd2; 1045 __be32 opt3; 1046 }; 1047 1048 #define S_T7_FILTER_TUPLE 1 1049 #define M_T7_FILTER_TUPLE 0x7FFFFFFFFFFFFFFFULL 1050 #define V_T7_FILTER_TUPLE(x) ((x) << S_T7_FILTER_TUPLE) 1051 #define G_T7_FILTER_TUPLE(x) (((x) >> S_T7_FILTER_TUPLE) & M_T7_FILTER_TUPLE) 1052 1053 struct cpl_act_open_req6 { 1054 WR_HDR; 1055 union opcode_tid ot; 1056 __be16 local_port; 1057 __be16 peer_port; 1058 __be64 local_ip_hi; 1059 __be64 local_ip_lo; 1060 __be64 peer_ip_hi; 1061 __be64 peer_ip_lo; 1062 __be64 opt0; 1063 __be32 params; 1064 __be32 opt2; 1065 }; 1066 1067 struct cpl_t5_act_open_req6 { 1068 WR_HDR; 1069 union opcode_tid ot; 1070 __be16 local_port; 1071 __be16 peer_port; 1072 __be64 local_ip_hi; 1073 __be64 local_ip_lo; 1074 __be64 peer_ip_hi; 1075 __be64 peer_ip_lo; 1076 __be64 opt0; 1077 __be32 iss; 1078 __be32 opt2; 1079 __be64 params; 1080 }; 1081 1082 struct cpl_t6_act_open_req6 { 1083 WR_HDR; 1084 union opcode_tid ot; 1085 __be16 local_port; 1086 __be16 peer_port; 1087 __be64 local_ip_hi; 1088 __be64 local_ip_lo; 1089 __be64 peer_ip_hi; 1090 __be64 peer_ip_lo; 1091 __be64 opt0; 1092 __be32 iss; 1093 __be32 opt2; 1094 __be64 params; 1095 __be32 rsvd2; 1096 __be32 opt3; 1097 }; 1098 1099 struct cpl_t7_act_open_req6 { 1100 WR_HDR; 1101 union opcode_tid ot; 1102 __be16 local_port; 1103 __be16 peer_port; 1104 __be64 local_ip_hi; 1105 __be64 local_ip_lo; 1106 __be64 peer_ip_hi; 1107 __be64 peer_ip_lo; 1108 __be64 opt0; 1109 __be32 iss; 1110 __be32 opt2; 1111 __be64 params; 1112 __be32 rsvd2; 1113 __be32 opt3; 1114 }; 1115 1116 struct cpl_act_open_rpl { 1117 RSS_HDR 1118 union opcode_tid ot; 1119 __be32 atid_status; 1120 }; 1121 1122 /* cpl_act_open_rpl.atid_status fields */ 1123 #define S_AOPEN_STATUS 0 1124 #define M_AOPEN_STATUS 0xFF 1125 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 1126 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 1127 1128 #define S_AOPEN_ATID 8 1129 #define M_AOPEN_ATID 0xFFFFFF 1130 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 1131 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 1132 1133 struct cpl_act_establish { 1134 RSS_HDR 1135 union opcode_tid ot; 1136 __be32 rsvd; 1137 __be32 tos_atid; 1138 __be16 mac_idx; 1139 __be16 tcp_opt; 1140 __be32 snd_isn; 1141 __be32 rcv_isn; 1142 }; 1143 1144 struct cpl_get_tcb { 1145 WR_HDR; 1146 union opcode_tid ot; 1147 __be16 reply_ctrl; 1148 __be16 cookie; 1149 }; 1150 1151 /* cpl_get_tcb.reply_ctrl fields */ 1152 #define S_QUEUENO 0 1153 #define M_QUEUENO 0x3FF 1154 #define V_QUEUENO(x) ((x) << S_QUEUENO) 1155 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 1156 1157 #define S_REPLY_CHAN 14 1158 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 1159 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 1160 1161 #define S_NO_REPLY 15 1162 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 1163 #define F_NO_REPLY V_NO_REPLY(1U) 1164 1165 struct cpl_t7_get_tcb { 1166 WR_HDR; 1167 union opcode_tid ot; 1168 __be16 rxchan_queue; 1169 __be16 cookie_pkd; 1170 }; 1171 1172 #define S_T7_REPLY_CHAN 12 1173 #define M_T7_REPLY_CHAN 0x7 1174 #define V_T7_REPLY_CHAN(x) ((x) << S_T7_REPLY_CHAN) 1175 #define G_T7_REPLY_CHAN(x) (((x) >> S_T7_REPLY_CHAN) & M_T7_REPLY_CHAN) 1176 1177 #define S_T7_QUEUENO 0 1178 #define M_T7_QUEUENO 0xFFF 1179 #define V_T7_QUEUENO(x) ((x) << S_T7_QUEUENO) 1180 #define G_T7_QUEUENO(x) (((x) >> S_T7_QUEUENO) & M_T7_QUEUENO) 1181 1182 #define S_CPL_GET_TCB_COOKIE 0 1183 #define M_CPL_GET_TCB_COOKIE 0xff 1184 #define V_CPL_GET_TCB_COOKIE(x) ((x) << S_CPL_GET_TCB_COOKIE) 1185 #define G_CPL_GET_TCB_COOKIE(x) \ 1186 (((x) >> S_CPL_GET_TCB_COOKIE) & M_CPL_GET_TCB_COOKIE) 1187 1188 struct cpl_get_tcb_rpl { 1189 RSS_HDR 1190 union opcode_tid ot; 1191 __u8 cookie; 1192 __u8 status; 1193 __be16 len; 1194 }; 1195 1196 struct cpl_set_tcb { 1197 WR_HDR; 1198 union opcode_tid ot; 1199 __be16 reply_ctrl; 1200 __be16 cookie; 1201 }; 1202 1203 struct cpl_set_tcb_field { 1204 WR_HDR; 1205 union opcode_tid ot; 1206 __be16 reply_ctrl; 1207 __be16 word_cookie; 1208 __be64 mask; 1209 __be64 val; 1210 }; 1211 1212 struct cpl_set_tcb_field_core { 1213 union opcode_tid ot; 1214 __be16 reply_ctrl; 1215 __be16 word_cookie; 1216 __be64 mask; 1217 __be64 val; 1218 }; 1219 1220 /* cpl_set_tcb_field.word_cookie fields */ 1221 #define S_WORD 0 1222 #define M_WORD 0x1F 1223 #define V_WORD(x) ((x) << S_WORD) 1224 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 1225 1226 #define S_COOKIE 5 1227 #define M_COOKIE 0x7 1228 #define V_COOKIE(x) ((x) << S_COOKIE) 1229 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 1230 1231 struct cpl_set_tcb_rpl { 1232 RSS_HDR 1233 union opcode_tid ot; 1234 __be16 rsvd; 1235 __u8 cookie; 1236 __u8 status; 1237 __be64 oldval; 1238 }; 1239 1240 struct cpl_close_con_req { 1241 WR_HDR; 1242 union opcode_tid ot; 1243 __be32 rsvd; 1244 }; 1245 1246 struct cpl_close_con_rpl { 1247 RSS_HDR 1248 union opcode_tid ot; 1249 __u8 rsvd[3]; 1250 __u8 status; 1251 __be32 snd_nxt; 1252 __be32 rcv_nxt; 1253 }; 1254 1255 struct cpl_t7_close_con_rpl { 1256 RSS_HDR 1257 union opcode_tid ot; 1258 __be16 rto; 1259 __u8 rsvd; 1260 __u8 status; 1261 __be32 snd_nxt; 1262 __be32 rcv_nxt; 1263 }; 1264 1265 struct cpl_close_listsvr_req { 1266 WR_HDR; 1267 union opcode_tid ot; 1268 __be16 reply_ctrl; 1269 __be16 rsvd; 1270 }; 1271 1272 /* additional cpl_close_listsvr_req.reply_ctrl field */ 1273 #define S_LISTSVR_IPV6 14 1274 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 1275 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 1276 1277 struct cpl_t7_close_listsvr_req { 1278 WR_HDR; 1279 union opcode_tid ot; 1280 __be16 noreply_to_queue; 1281 __be16 r2; 1282 }; 1283 1284 #define S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY 15 1285 #define M_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY 0x1 1286 #define V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x) \ 1287 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) 1288 #define G_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(x) \ 1289 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) & \ 1290 M_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY) 1291 #define F_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY \ 1292 V_CPL_T7_CLOSE_LISTSVR_REQ_NOREPLY(1U) 1293 1294 #define S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6 14 1295 #define M_CPL_T7_CLOSE_LISTSVR_REQ_IPV6 0x1 1296 #define V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x) \ 1297 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) 1298 #define G_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(x) \ 1299 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) & M_CPL_T7_CLOSE_LISTSVR_REQ_IPV6) 1300 #define F_CPL_T7_CLOSE_LISTSVR_REQ_IPV6 \ 1301 V_CPL_T7_CLOSE_LISTSVR_REQ_IPV6(1U) 1302 1303 #define S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE 0 1304 #define M_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE 0xfff 1305 #define V_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x) \ 1306 ((x) << S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) 1307 #define G_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE(x) \ 1308 (((x) >> S_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) & \ 1309 M_CPL_T7_CLOSE_LISTSVR_REQ_QUEUE) 1310 1311 struct cpl_close_listsvr_rpl { 1312 RSS_HDR 1313 union opcode_tid ot; 1314 __u8 rsvd[3]; 1315 __u8 status; 1316 }; 1317 1318 struct cpl_abort_req_rss { 1319 RSS_HDR 1320 union opcode_tid ot; 1321 __u8 rsvd[3]; 1322 __u8 status; 1323 }; 1324 1325 struct cpl_abort_req_rss6 { 1326 RSS_HDR 1327 union opcode_tid ot; 1328 __u32 srqidx_status; 1329 }; 1330 1331 #define S_ABORT_RSS_STATUS 0 1332 #define M_ABORT_RSS_STATUS 0xff 1333 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1334 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1335 1336 #define S_ABORT_RSS_SRQIDX 8 1337 #define M_ABORT_RSS_SRQIDX 0xffffff 1338 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1339 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1340 1341 1342 /* cpl_abort_req status command code in case of T6, 1343 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1344 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1345 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1346 */ 1347 struct cpl_abort_req { 1348 WR_HDR; 1349 union opcode_tid ot; 1350 __be32 rsvd0; 1351 __u8 rsvd1; 1352 __u8 cmd; 1353 __u8 rsvd2[6]; 1354 }; 1355 1356 struct cpl_abort_req_core { 1357 union opcode_tid ot; 1358 __be32 rsvd0; 1359 __u8 rsvd1; 1360 __u8 cmd; 1361 __u8 rsvd2[6]; 1362 }; 1363 1364 struct cpl_abort_rpl_rss { 1365 RSS_HDR 1366 union opcode_tid ot; 1367 __u8 rsvd[3]; 1368 __u8 status; 1369 }; 1370 1371 struct cpl_t7_abort_rpl_rss { 1372 RSS_HDR 1373 union opcode_tid ot; 1374 __be32 idx_status; 1375 }; 1376 1377 #define S_CPL_ABORT_RPL_RSS_IDX 8 1378 #define M_CPL_ABORT_RPL_RSS_IDX 0xffffff 1379 #define V_CPL_ABORT_RPL_RSS_IDX(x) ((x) << S_CPL_ABORT_RPL_RSS_IDX) 1380 #define G_CPL_ABORT_RPL_RSS_IDX(x) \ 1381 (((x) >> S_CPL_ABORT_RPL_RSS_IDX) & M_CPL_ABORT_RPL_RSS_IDX) 1382 1383 #define S_CPL_ABORT_RPL_RSS_STATUS 0 1384 #define M_CPL_ABORT_RPL_RSS_STATUS 0xff 1385 #define V_CPL_ABORT_RPL_RSS_STATUS(x) ((x) << S_CPL_ABORT_RPL_RSS_STATUS) 1386 #define G_CPL_ABORT_RPL_RSS_STATUS(x) \ 1387 (((x) >> S_CPL_ABORT_RPL_RSS_STATUS) & M_CPL_ABORT_RPL_RSS_STATUS) 1388 1389 struct cpl_abort_rpl_rss6 { 1390 RSS_HDR 1391 union opcode_tid ot; 1392 __u32 srqidx_status; 1393 }; 1394 1395 struct cpl_abort_rpl { 1396 WR_HDR; 1397 union opcode_tid ot; 1398 __be32 rsvd0; 1399 __u8 rsvd1; 1400 __u8 cmd; 1401 __u8 rsvd2[6]; 1402 }; 1403 1404 struct cpl_abort_rpl_core { 1405 union opcode_tid ot; 1406 __be32 rsvd0; 1407 __u8 rsvd1; 1408 __u8 cmd; 1409 __u8 rsvd2[6]; 1410 }; 1411 1412 struct cpl_peer_close { 1413 RSS_HDR 1414 union opcode_tid ot; 1415 __be32 rcv_nxt; 1416 }; 1417 1418 struct cpl_tid_release { 1419 WR_HDR; 1420 union opcode_tid ot; 1421 __be32 rsvd; 1422 }; 1423 1424 struct tx_data_wr { 1425 __be32 wr_hi; 1426 __be32 wr_lo; 1427 __be32 len; 1428 __be32 flags; 1429 __be32 sndseq; 1430 __be32 param; 1431 }; 1432 1433 /* tx_data_wr.flags fields */ 1434 #define S_TX_ACK_PAGES 21 1435 #define M_TX_ACK_PAGES 0x7 1436 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1437 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1438 1439 /* tx_data_wr.param fields */ 1440 #define S_TX_PORT 0 1441 #define M_TX_PORT 0x7 1442 #define V_TX_PORT(x) ((x) << S_TX_PORT) 1443 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1444 1445 #define S_TX_MSS 4 1446 #define M_TX_MSS 0xF 1447 #define V_TX_MSS(x) ((x) << S_TX_MSS) 1448 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1449 1450 #define S_TX_QOS 8 1451 #define M_TX_QOS 0xFF 1452 #define V_TX_QOS(x) ((x) << S_TX_QOS) 1453 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1454 1455 #define S_TX_SNDBUF 16 1456 #define M_TX_SNDBUF 0xFFFF 1457 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1458 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1459 1460 struct cpl_tx_data { 1461 union opcode_tid ot; 1462 __be32 len; 1463 __be32 rsvd; 1464 __be32 flags; 1465 }; 1466 1467 /* cpl_tx_data.len fields */ 1468 #define S_TX_DATA_MSS 16 1469 #define M_TX_DATA_MSS 0xFFFF 1470 #define V_TX_DATA_MSS(x) ((x) << S_TX_DATA_MSS) 1471 #define G_TX_DATA_MSS(x) (((x) >> S_TX_DATA_MSS) & M_TX_DATA_MSS) 1472 1473 #define S_TX_LENGTH 0 1474 #define M_TX_LENGTH 0xFFFF 1475 #define V_TX_LENGTH(x) ((x) << S_TX_LENGTH) 1476 #define G_TX_LENGTH(x) (((x) >> S_TX_LENGTH) & M_TX_LENGTH) 1477 1478 /* cpl_tx_data.flags fields */ 1479 #define S_TX_PROXY 5 1480 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1481 #define F_TX_PROXY V_TX_PROXY(1U) 1482 1483 #define S_TX_ULP_SUBMODE 6 1484 #define M_TX_ULP_SUBMODE 0xF 1485 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1486 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1487 1488 #define S_TX_ULP_MODE 10 1489 #define M_TX_ULP_MODE 0x7 1490 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1491 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1492 1493 #define S_T7_TX_ULP_MODE 10 1494 #define M_T7_TX_ULP_MODE 0xf 1495 #define V_T7_TX_ULP_MODE(x) ((x) << S_T7_TX_ULP_MODE) 1496 #define G_T7_TX_ULP_MODE(x) (((x) >> S_T7_TX_ULP_MODE) & M_T7_TX_ULP_MODE) 1497 1498 #define S_TX_FORCE 13 1499 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1500 #define F_TX_FORCE V_TX_FORCE(1U) 1501 1502 #define S_TX_SHOVE 14 1503 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1504 #define F_TX_SHOVE V_TX_SHOVE(1U) 1505 1506 #define S_TX_MORE 15 1507 #define V_TX_MORE(x) ((x) << S_TX_MORE) 1508 #define F_TX_MORE V_TX_MORE(1U) 1509 1510 #define S_TX_URG 16 1511 #define V_TX_URG(x) ((x) << S_TX_URG) 1512 #define F_TX_URG V_TX_URG(1U) 1513 1514 #define S_TX_FLUSH 17 1515 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1516 #define F_TX_FLUSH V_TX_FLUSH(1U) 1517 1518 #define S_TX_SAVE 18 1519 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1520 #define F_TX_SAVE V_TX_SAVE(1U) 1521 1522 #define S_TX_TNL 19 1523 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1524 #define F_TX_TNL V_TX_TNL(1U) 1525 1526 #define S_T6_TX_FORCE 20 1527 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1528 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1529 1530 #define S_TX_BYPASS 21 1531 #define V_TX_BYPASS(x) ((x) << S_TX_BYPASS) 1532 #define F_TX_BYPASS V_TX_BYPASS(1U) 1533 1534 #define S_TX_PUSH 22 1535 #define V_TX_PUSH(x) ((x) << S_TX_PUSH) 1536 #define F_TX_PUSH V_TX_PUSH(1U) 1537 1538 /* additional tx_data_wr.flags fields */ 1539 #define S_TX_CPU_IDX 0 1540 #define M_TX_CPU_IDX 0x3F 1541 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1542 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1543 1544 #define S_TX_CLOSE 17 1545 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1546 #define F_TX_CLOSE V_TX_CLOSE(1U) 1547 1548 #define S_TX_INIT 18 1549 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1550 #define F_TX_INIT V_TX_INIT(1U) 1551 1552 #define S_TX_IMM_ACK 19 1553 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1554 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1555 1556 #define S_TX_IMM_DMA 20 1557 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1558 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1559 1560 struct cpl_tx_data_ack { 1561 RSS_HDR 1562 union opcode_tid ot; 1563 __be32 snd_una; 1564 }; 1565 1566 struct cpl_tx_data_ack_xt { 1567 RSS_HDR 1568 union opcode_tid ot; 1569 __be32 snd_una; 1570 __be32 snd_end; 1571 __be32 snd_nxt; 1572 __be32 snd_adv; 1573 __be16 rttvar; 1574 __be16 srtt; 1575 __be32 extinfoh[2]; 1576 __be32 extinfol[2]; 1577 }; 1578 1579 struct cpl_tx_data_req { 1580 RSS_HDR 1581 union opcode_tid ot; 1582 __be32 snd_una; 1583 __be32 snd_end; 1584 __be32 snd_nxt; 1585 __be32 snd_adv; 1586 __be16 rttvar; 1587 __be16 srtt; 1588 }; 1589 1590 #define S_CPL_TX_DATA_REQ_TID 0 1591 #define M_CPL_TX_DATA_REQ_TID 0xffffff 1592 #define V_CPL_TX_DATA_REQ_TID(x) ((x) << S_CPL_TX_DATA_REQ_TID) 1593 #define G_CPL_TX_DATA_REQ_TID(x) \ 1594 (((x) >> S_CPL_TX_DATA_REQ_TID) & M_CPL_TX_DATA_REQ_TID) 1595 1596 struct cpl_sack_req { 1597 RSS_HDR 1598 union opcode_tid ot; 1599 __be32 snd_una; 1600 __be32 snd_end; 1601 __be32 snd_nxt; 1602 __be32 snd_adv; 1603 __be16 rttvar; 1604 __be16 srtt; 1605 __be32 block1[2]; 1606 __be32 block2[2]; 1607 __be32 block3[2]; 1608 }; 1609 1610 struct cpl_sge_flr_flush { 1611 RSS_HDR 1612 union opcode_tid ot; 1613 __be32 cookievalue_cookiesel; 1614 }; 1615 1616 #define S_CPL_SGE_FLR_FLUSH_COOKIEVALUE 4 1617 #define M_CPL_SGE_FLR_FLUSH_COOKIEVALUE 0x3ff 1618 #define V_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \ 1619 ((x) << S_CPL_SGE_FLR_FLUSH_COOKIEVALUE) 1620 #define G_CPL_SGE_FLR_FLUSH_COOKIEVALUE(x) \ 1621 (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIEVALUE) & \ 1622 M_CPL_SGE_FLR_FLUSH_COOKIEVALUE) 1623 1624 #define S_CPL_SGE_FLR_FLUSH_COOKIESEL 0 1625 #define M_CPL_SGE_FLR_FLUSH_COOKIESEL 0xf 1626 #define V_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \ 1627 ((x) << S_CPL_SGE_FLR_FLUSH_COOKIESEL) 1628 #define G_CPL_SGE_FLR_FLUSH_COOKIESEL(x) \ 1629 (((x) >> S_CPL_SGE_FLR_FLUSH_COOKIESEL) & M_CPL_SGE_FLR_FLUSH_COOKIESEL) 1630 1631 struct cpl_wr_ack { /* XXX */ 1632 RSS_HDR 1633 union opcode_tid ot; 1634 __be16 credits; 1635 __be16 rsvd; 1636 __be32 snd_nxt; 1637 __be32 snd_una; 1638 }; 1639 1640 struct cpl_tx_pkt_core { 1641 __be32 ctrl0; 1642 __be16 pack; 1643 __be16 len; 1644 __be64 ctrl1; 1645 }; 1646 1647 struct cpl_tx_pkt { 1648 WR_HDR; 1649 struct cpl_tx_pkt_core c; 1650 }; 1651 1652 /* cpl_tx_pkt_core.ctrl0 fields */ 1653 #define S_TXPKT_VF 0 1654 #define M_TXPKT_VF 0xFF 1655 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1656 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1657 1658 #define S_TXPKT_PF 8 1659 #define M_TXPKT_PF 0x7 1660 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1661 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1662 1663 #define S_TXPKT_VF_VLD 11 1664 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1665 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1666 1667 #define S_TXPKT_OVLAN_IDX 12 1668 #define M_TXPKT_OVLAN_IDX 0xF 1669 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1670 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1671 1672 #define S_TXPKT_T5_OVLAN_IDX 12 1673 #define M_TXPKT_T5_OVLAN_IDX 0x7 1674 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1675 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1676 M_TXPKT_T5_OVLAN_IDX) 1677 1678 #define S_TXPKT_INTF 16 1679 #define M_TXPKT_INTF 0xF 1680 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1681 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1682 1683 #define S_TXPKT_SPECIAL_STAT 20 1684 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1685 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1686 1687 #define S_TXPKT_T5_FCS_DIS 21 1688 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1689 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1690 1691 #define S_TXPKT_INS_OVLAN 21 1692 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1693 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1694 1695 #define S_TXPKT_T5_INS_OVLAN 15 1696 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1697 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1698 1699 #define S_TXPKT_STAT_DIS 22 1700 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1701 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1702 1703 #define S_TXPKT_LOOPBACK 23 1704 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1705 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1706 1707 #define S_TXPKT_TSTAMP 23 1708 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1709 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1710 1711 #define S_TXPKT_OPCODE 24 1712 #define M_TXPKT_OPCODE 0xFF 1713 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1714 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1715 1716 /* cpl_tx_pkt_core.ctrl1 fields */ 1717 #define S_TXPKT_SA_IDX 0 1718 #define M_TXPKT_SA_IDX 0xFFF 1719 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1720 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1721 1722 #define S_TXPKT_CSUM_END 12 1723 #define M_TXPKT_CSUM_END 0xFF 1724 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1725 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1726 1727 #define S_TXPKT_CSUM_START 20 1728 #define M_TXPKT_CSUM_START 0x3FF 1729 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1730 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1731 1732 #define S_TXPKT_IPHDR_LEN 20 1733 #define M_TXPKT_IPHDR_LEN 0x3FFF 1734 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1735 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1736 1737 #define M_T6_TXPKT_IPHDR_LEN 0xFFF 1738 #define G_T6_TXPKT_IPHDR_LEN(x) \ 1739 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1740 1741 #define S_TXPKT_CSUM_LOC 30 1742 #define M_TXPKT_CSUM_LOC 0x3FF 1743 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1744 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1745 1746 #define S_TXPKT_ETHHDR_LEN 34 1747 #define M_TXPKT_ETHHDR_LEN 0x3F 1748 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1749 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1750 1751 #define S_T6_TXPKT_ETHHDR_LEN 32 1752 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 1753 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1754 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 1755 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1756 1757 #define S_TXPKT_CSUM_TYPE 40 1758 #define M_TXPKT_CSUM_TYPE 0xF 1759 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1760 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1761 1762 #define S_TXPKT_VLAN 44 1763 #define M_TXPKT_VLAN 0xFFFF 1764 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1765 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1766 1767 #define S_TXPKT_VLAN_VLD 60 1768 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1769 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1770 1771 #define S_TXPKT_IPSEC 61 1772 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1773 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1774 1775 #define S_TXPKT_IPCSUM_DIS 62 1776 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1777 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1778 1779 #define S_TXPKT_L4CSUM_DIS 63 1780 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1781 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1782 1783 struct cpl_tx_pkt_xt { 1784 WR_HDR; 1785 __be32 ctrl0; 1786 __be16 pack; 1787 __be16 len; 1788 __be32 ctrl1; 1789 __be32 ctrl2; 1790 }; 1791 1792 /* cpl_tx_pkt_xt.core.ctrl0 fields */ 1793 #define S_CPL_TX_PKT_XT_OPCODE 24 1794 #define M_CPL_TX_PKT_XT_OPCODE 0xff 1795 #define V_CPL_TX_PKT_XT_OPCODE(x) ((x) << S_CPL_TX_PKT_XT_OPCODE) 1796 #define G_CPL_TX_PKT_XT_OPCODE(x) \ 1797 (((x) >> S_CPL_TX_PKT_XT_OPCODE) & M_CPL_TX_PKT_XT_OPCODE) 1798 1799 #define S_CPL_TX_PKT_XT_TIMESTAMP 23 1800 #define M_CPL_TX_PKT_XT_TIMESTAMP 0x1 1801 #define V_CPL_TX_PKT_XT_TIMESTAMP(x) ((x) << S_CPL_TX_PKT_XT_TIMESTAMP) 1802 #define G_CPL_TX_PKT_XT_TIMESTAMP(x) \ 1803 (((x) >> S_CPL_TX_PKT_XT_TIMESTAMP) & M_CPL_TX_PKT_XT_TIMESTAMP) 1804 #define F_CPL_TX_PKT_XT_TIMESTAMP V_CPL_TX_PKT_XT_TIMESTAMP(1U) 1805 1806 #define S_CPL_TX_PKT_XT_STATDISABLE 22 1807 #define M_CPL_TX_PKT_XT_STATDISABLE 0x1 1808 #define V_CPL_TX_PKT_XT_STATDISABLE(x) ((x) << S_CPL_TX_PKT_XT_STATDISABLE) 1809 #define G_CPL_TX_PKT_XT_STATDISABLE(x) \ 1810 (((x) >> S_CPL_TX_PKT_XT_STATDISABLE) & M_CPL_TX_PKT_XT_STATDISABLE) 1811 #define F_CPL_TX_PKT_XT_STATDISABLE V_CPL_TX_PKT_XT_STATDISABLE(1U) 1812 1813 #define S_CPL_TX_PKT_XT_FCSDIS 21 1814 #define M_CPL_TX_PKT_XT_FCSDIS 0x1 1815 #define V_CPL_TX_PKT_XT_FCSDIS(x) ((x) << S_CPL_TX_PKT_XT_FCSDIS) 1816 #define G_CPL_TX_PKT_XT_FCSDIS(x) \ 1817 (((x) >> S_CPL_TX_PKT_XT_FCSDIS) & M_CPL_TX_PKT_XT_FCSDIS) 1818 #define F_CPL_TX_PKT_XT_FCSDIS V_CPL_TX_PKT_XT_FCSDIS(1U) 1819 1820 #define S_CPL_TX_PKT_XT_STATSPECIAL 20 1821 #define M_CPL_TX_PKT_XT_STATSPECIAL 0x1 1822 #define V_CPL_TX_PKT_XT_STATSPECIAL(x) ((x) << S_CPL_TX_PKT_XT_STATSPECIAL) 1823 #define G_CPL_TX_PKT_XT_STATSPECIAL(x) \ 1824 (((x) >> S_CPL_TX_PKT_XT_STATSPECIAL) & M_CPL_TX_PKT_XT_STATSPECIAL) 1825 #define F_CPL_TX_PKT_XT_STATSPECIAL V_CPL_TX_PKT_XT_STATSPECIAL(1U) 1826 1827 #define S_CPL_TX_PKT_XT_INTERFACE 16 1828 #define M_CPL_TX_PKT_XT_INTERFACE 0xf 1829 #define V_CPL_TX_PKT_XT_INTERFACE(x) ((x) << S_CPL_TX_PKT_XT_INTERFACE) 1830 #define G_CPL_TX_PKT_XT_INTERFACE(x) \ 1831 (((x) >> S_CPL_TX_PKT_XT_INTERFACE) & M_CPL_TX_PKT_XT_INTERFACE) 1832 1833 #define S_CPL_TX_PKT_XT_OVLAN 15 1834 #define M_CPL_TX_PKT_XT_OVLAN 0x1 1835 #define V_CPL_TX_PKT_XT_OVLAN(x) ((x) << S_CPL_TX_PKT_XT_OVLAN) 1836 #define G_CPL_TX_PKT_XT_OVLAN(x) \ 1837 (((x) >> S_CPL_TX_PKT_XT_OVLAN) & M_CPL_TX_PKT_XT_OVLAN) 1838 #define F_CPL_TX_PKT_XT_OVLAN V_CPL_TX_PKT_XT_OVLAN(1U) 1839 1840 #define S_CPL_TX_PKT_XT_OVLANIDX 12 1841 #define M_CPL_TX_PKT_XT_OVLANIDX 0x7 1842 #define V_CPL_TX_PKT_XT_OVLANIDX(x) ((x) << S_CPL_TX_PKT_XT_OVLANIDX) 1843 #define G_CPL_TX_PKT_XT_OVLANIDX(x) \ 1844 (((x) >> S_CPL_TX_PKT_XT_OVLANIDX) & M_CPL_TX_PKT_XT_OVLANIDX) 1845 1846 #define S_CPL_TX_PKT_XT_VFVALID 11 1847 #define M_CPL_TX_PKT_XT_VFVALID 0x1 1848 #define V_CPL_TX_PKT_XT_VFVALID(x) ((x) << S_CPL_TX_PKT_XT_VFVALID) 1849 #define G_CPL_TX_PKT_XT_VFVALID(x) \ 1850 (((x) >> S_CPL_TX_PKT_XT_VFVALID) & M_CPL_TX_PKT_XT_VFVALID) 1851 #define F_CPL_TX_PKT_XT_VFVALID V_CPL_TX_PKT_XT_VFVALID(1U) 1852 1853 #define S_CPL_TX_PKT_XT_PF 8 1854 #define M_CPL_TX_PKT_XT_PF 0x7 1855 #define V_CPL_TX_PKT_XT_PF(x) ((x) << S_CPL_TX_PKT_XT_PF) 1856 #define G_CPL_TX_PKT_XT_PF(x) \ 1857 (((x) >> S_CPL_TX_PKT_XT_PF) & M_CPL_TX_PKT_XT_PF) 1858 1859 #define S_CPL_TX_PKT_XT_VF 0 1860 #define M_CPL_TX_PKT_XT_VF 0xff 1861 #define V_CPL_TX_PKT_XT_VF(x) ((x) << S_CPL_TX_PKT_XT_VF) 1862 #define G_CPL_TX_PKT_XT_VF(x) \ 1863 (((x) >> S_CPL_TX_PKT_XT_VF) & M_CPL_TX_PKT_XT_VF) 1864 1865 /* cpl_tx_pkt_xt.core.ctrl1 fields */ 1866 #define S_CPL_TX_PKT_XT_L4CHKDISABLE 31 1867 #define M_CPL_TX_PKT_XT_L4CHKDISABLE 0x1 1868 #define V_CPL_TX_PKT_XT_L4CHKDISABLE(x) ((x) << S_CPL_TX_PKT_XT_L4CHKDISABLE) 1869 #define G_CPL_TX_PKT_XT_L4CHKDISABLE(x) \ 1870 (((x) >> S_CPL_TX_PKT_XT_L4CHKDISABLE) & M_CPL_TX_PKT_XT_L4CHKDISABLE) 1871 #define F_CPL_TX_PKT_XT_L4CHKDISABLE V_CPL_TX_PKT_XT_L4CHKDISABLE(1U) 1872 1873 #define S_CPL_TX_PKT_XT_L3CHKDISABLE 30 1874 #define M_CPL_TX_PKT_XT_L3CHKDISABLE 0x1 1875 #define V_CPL_TX_PKT_XT_L3CHKDISABLE(x) ((x) << S_CPL_TX_PKT_XT_L3CHKDISABLE) 1876 #define G_CPL_TX_PKT_XT_L3CHKDISABLE(x) \ 1877 (((x) >> S_CPL_TX_PKT_XT_L3CHKDISABLE) & M_CPL_TX_PKT_XT_L3CHKDISABLE) 1878 #define F_CPL_TX_PKT_XT_L3CHKDISABLE V_CPL_TX_PKT_XT_L3CHKDISABLE(1U) 1879 1880 #define S_CPL_TX_PKT_XT_OUTL4CHKEN 29 1881 #define M_CPL_TX_PKT_XT_OUTL4CHKEN 0x1 1882 #define V_CPL_TX_PKT_XT_OUTL4CHKEN(x) ((x) << S_CPL_TX_PKT_XT_OUTL4CHKEN) 1883 #define G_CPL_TX_PKT_XT_OUTL4CHKEN(x) \ 1884 (((x) >> S_CPL_TX_PKT_XT_OUTL4CHKEN) & M_CPL_TX_PKT_XT_OUTL4CHKEN) 1885 #define F_CPL_TX_PKT_XT_OUTL4CHKEN V_CPL_TX_PKT_XT_OUTL4CHKEN(1U) 1886 1887 #define S_CPL_TX_PKT_XT_IVLAN 28 1888 #define M_CPL_TX_PKT_XT_IVLAN 0x1 1889 #define V_CPL_TX_PKT_XT_IVLAN(x) ((x) << S_CPL_TX_PKT_XT_IVLAN) 1890 #define G_CPL_TX_PKT_XT_IVLAN(x) \ 1891 (((x) >> S_CPL_TX_PKT_XT_IVLAN) & M_CPL_TX_PKT_XT_IVLAN) 1892 #define F_CPL_TX_PKT_XT_IVLAN V_CPL_TX_PKT_XT_IVLAN(1U) 1893 1894 #define S_CPL_TX_PKT_XT_IVLANTAG 12 1895 #define M_CPL_TX_PKT_XT_IVLANTAG 0xffff 1896 #define V_CPL_TX_PKT_XT_IVLANTAG(x) ((x) << S_CPL_TX_PKT_XT_IVLANTAG) 1897 #define G_CPL_TX_PKT_XT_IVLANTAG(x) \ 1898 (((x) >> S_CPL_TX_PKT_XT_IVLANTAG) & M_CPL_TX_PKT_XT_IVLANTAG) 1899 1900 #define S_CPL_TX_PKT_XT_CHKTYPE 8 1901 #define M_CPL_TX_PKT_XT_CHKTYPE 0xf 1902 #define V_CPL_TX_PKT_XT_CHKTYPE(x) ((x) << S_CPL_TX_PKT_XT_CHKTYPE) 1903 #define G_CPL_TX_PKT_XT_CHKTYPE(x) \ 1904 (((x) >> S_CPL_TX_PKT_XT_CHKTYPE) & M_CPL_TX_PKT_XT_CHKTYPE) 1905 1906 #define S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI 0 1907 #define M_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI 0xff 1908 #define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \ 1909 ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) 1910 #define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI(x) \ 1911 (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) & \ 1912 M_CPL_TX_PKT_XT_CHKINSRTOFFSET_HI) 1913 1914 #define S_CPL_TX_PKT_XT_ETHHDRLEN 0 1915 #define M_CPL_TX_PKT_XT_ETHHDRLEN 0xff 1916 #define V_CPL_TX_PKT_XT_ETHHDRLEN(x) ((x) << S_CPL_TX_PKT_XT_ETHHDRLEN) 1917 #define G_CPL_TX_PKT_XT_ETHHDRLEN(x) \ 1918 (((x) >> S_CPL_TX_PKT_XT_ETHHDRLEN) & M_CPL_TX_PKT_XT_ETHHDRLEN) 1919 1920 #define S_CPL_TX_PKT_XT_ROCECHKINSMODE 6 1921 #define M_CPL_TX_PKT_XT_ROCECHKINSMODE 0x3 1922 #define V_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \ 1923 ((x) << S_CPL_TX_PKT_XT_ROCECHKINSMODE) 1924 #define G_CPL_TX_PKT_XT_ROCECHKINSMODE(x) \ 1925 (((x) >> S_CPL_TX_PKT_XT_ROCECHKINSMODE) & M_CPL_TX_PKT_XT_ROCECHKINSMODE) 1926 1927 #define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI 0 1928 #define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI 0x3f 1929 #define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \ 1930 ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) 1931 #define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI(x) \ 1932 (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) & \ 1933 M_CPL_TX_PKT_XT_ROCEIPHDRLEN_HI) 1934 1935 /* cpl_tx_pkt_xt.core.ctrl2 fields */ 1936 #define S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 30 1937 #define M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO 0x3 1938 #define V_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \ 1939 ((x) << S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) 1940 #define G_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO(x) \ 1941 (((x) >> S_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) & \ 1942 M_CPL_TX_PKT_XT_CHKINSRTOFFSET_LO) 1943 1944 #define S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 30 1945 #define M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO 0x3 1946 #define V_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ 1947 ((x) << S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) 1948 #define G_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO(x) \ 1949 (((x) >> S_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) & \ 1950 M_CPL_TX_PKT_XT_ROCEIPHDRLEN_LO) 1951 1952 #define S_CPL_TX_PKT_XT_CHKSTARTOFFSET 20 1953 #define M_CPL_TX_PKT_XT_CHKSTARTOFFSET 0x3ff 1954 #define V_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \ 1955 ((x) << S_CPL_TX_PKT_XT_CHKSTARTOFFSET) 1956 #define G_CPL_TX_PKT_XT_CHKSTARTOFFSET(x) \ 1957 (((x) >> S_CPL_TX_PKT_XT_CHKSTARTOFFSET) & M_CPL_TX_PKT_XT_CHKSTARTOFFSET) 1958 1959 #define S_CPL_TX_PKT_XT_IPHDRLEN 20 1960 #define M_CPL_TX_PKT_XT_IPHDRLEN 0xfff 1961 #define V_CPL_TX_PKT_XT_IPHDRLEN(x) ((x) << S_CPL_TX_PKT_XT_IPHDRLEN) 1962 #define G_CPL_TX_PKT_XT_IPHDRLEN(x) \ 1963 (((x) >> S_CPL_TX_PKT_XT_IPHDRLEN) & M_CPL_TX_PKT_XT_IPHDRLEN) 1964 1965 #define S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET 20 1966 #define M_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET 0x3ff 1967 #define V_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \ 1968 ((x) << S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) 1969 #define G_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET(x) \ 1970 (((x) >> S_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) & \ 1971 M_CPL_TX_PKT_XT_ROCECHKSTARTOFFSET) 1972 1973 #define S_CPL_TX_PKT_XT_CHKSTOPOFFSET 12 1974 #define M_CPL_TX_PKT_XT_CHKSTOPOFFSET 0xff 1975 #define V_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \ 1976 ((x) << S_CPL_TX_PKT_XT_CHKSTOPOFFSET) 1977 #define G_CPL_TX_PKT_XT_CHKSTOPOFFSET(x) \ 1978 (((x) >> S_CPL_TX_PKT_XT_CHKSTOPOFFSET) & M_CPL_TX_PKT_XT_CHKSTOPOFFSET) 1979 1980 #define S_CPL_TX_PKT_XT_IPSECIDX 0 1981 #define M_CPL_TX_PKT_XT_IPSECIDX 0xfff 1982 #define V_CPL_TX_PKT_XT_IPSECIDX(x) ((x) << S_CPL_TX_PKT_XT_IPSECIDX) 1983 #define G_CPL_TX_PKT_XT_IPSECIDX(x) \ 1984 (((x) >> S_CPL_TX_PKT_XT_IPSECIDX) & M_CPL_TX_PKT_XT_IPSECIDX) 1985 1986 #define S_CPL_TX_TNL_LSO_BTH_OPCODE 24 1987 #define M_CPL_TX_TNL_LSO_BTH_OPCODE 0xff 1988 #define V_CPL_TX_TNL_LSO_BTH_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_BTH_OPCODE) 1989 #define G_CPL_TX_TNL_LSO_BTH_OPCODE(x) \ 1990 (((x) >> S_CPL_TX_TNL_LSO_BTH_OPCODE) & \ 1991 M_CPL_TX_TNL_LSO_BTH_OPCODE) 1992 1993 #define S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0 1994 #define M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0xffffff 1995 #define V_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ 1996 ((x) << S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) 1997 #define G_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ 1998 (((x) >> S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) & \ 1999 M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) 2000 2001 #define S_CPL_TX_TNL_LSO_MSS_TVER 8 2002 #define M_CPL_TX_TNL_LSO_MSS_TVER 0xf 2003 #define V_CPL_TX_TNL_LSO_MSS_TVER(x) ((x) << S_CPL_TX_TNL_LSO_MSS_TVER) 2004 #define G_CPL_TX_TNL_LSO_MSS_TVER(x) \ 2005 (((x) >> S_CPL_TX_TNL_LSO_MSS_TVER) & M_CPL_TX_TNL_LSO_MSS_TVER) 2006 2007 #define S_CPL_TX_TNL_LSO_MSS_M 7 2008 #define M_CPL_TX_TNL_LSO_MSS_M 0x1 2009 #define V_CPL_TX_TNL_LSO_MSS_M(x) ((x) << S_CPL_TX_TNL_LSO_MSS_M) 2010 #define G_CPL_TX_TNL_LSO_MSS_M(x) \ 2011 (((x) >> S_CPL_TX_TNL_LSO_MSS_M) & M_CPL_TX_TNL_LSO_MSS_M) 2012 2013 #define S_CPL_TX_TNL_LSO_MSS_PMTU 4 2014 #define M_CPL_TX_TNL_LSO_MSS_PMTU 0x7 2015 #define V_CPL_TX_TNL_LSO_MSS_PMTU(x) ((x) << S_CPL_TX_TNL_LSO_MSS_PMTU) 2016 #define G_CPL_TX_TNL_LSO_MSS_PMTU(x) \ 2017 (((x) >> S_CPL_TX_TNL_LSO_MSS_PMTU) & M_CPL_TX_TNL_LSO_MSS_PMTU) 2018 2019 #define S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 3 2020 #define M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 0x1 2021 #define V_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ 2022 ((x) << S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) 2023 #define G_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ 2024 (((x) >> S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) & M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) 2025 2026 #define S_CPL_TX_TNL_LSO_MSS_ACKREQ 1 2027 #define M_CPL_TX_TNL_LSO_MSS_ACKREQ 0x3 2028 #define V_CPL_TX_TNL_LSO_MSS_ACKREQ(x) ((x) << S_CPL_TX_TNL_LSO_MSS_ACKREQ) 2029 #define G_CPL_TX_TNL_LSO_MSS_ACKREQ(x) \ 2030 (((x) >> S_CPL_TX_TNL_LSO_MSS_ACKREQ) & M_CPL_TX_TNL_LSO_MSS_ACKREQ) 2031 2032 #define S_CPL_TX_TNL_LSO_MSS_SE 0 2033 #define M_CPL_TX_TNL_LSO_MSS_SE 0x1 2034 #define V_CPL_TX_TNL_LSO_MSS_SE(x) ((x) << S_CPL_TX_TNL_LSO_MSS_SE) 2035 #define G_CPL_TX_TNL_LSO_MSS_SE(x) \ 2036 (((x) >> S_CPL_TX_TNL_LSO_MSS_SE) & M_CPL_TX_TNL_LSO_MSS_SE) 2037 2038 struct cpl_tx_pkt_lso_core { 2039 __be32 lso_ctrl; 2040 __be16 ipid_ofst; 2041 __be16 mss; 2042 __be32 seqno_offset; 2043 __be32 len; 2044 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 2045 }; 2046 2047 struct cpl_tx_pkt_lso { 2048 WR_HDR; 2049 struct cpl_tx_pkt_lso_core c; 2050 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 2051 }; 2052 2053 struct cpl_tx_pkt_ufo_core { 2054 __be16 ethlen; 2055 __be16 iplen; 2056 __be16 udplen; 2057 __be16 mss; 2058 __be32 len; 2059 __be32 r1; 2060 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 2061 }; 2062 2063 struct cpl_tx_pkt_ufo { 2064 WR_HDR; 2065 struct cpl_tx_pkt_ufo_core c; 2066 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 2067 }; 2068 2069 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 2070 #define S_LSO_TCPHDR_LEN 0 2071 #define M_LSO_TCPHDR_LEN 0xF 2072 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 2073 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 2074 2075 #define S_LSO_IPHDR_LEN 4 2076 #define M_LSO_IPHDR_LEN 0xFFF 2077 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 2078 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 2079 2080 #define S_LSO_ETHHDR_LEN 16 2081 #define M_LSO_ETHHDR_LEN 0xF 2082 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 2083 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 2084 2085 #define S_LSO_IPV6 20 2086 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 2087 #define F_LSO_IPV6 V_LSO_IPV6(1U) 2088 2089 #define S_LSO_OFLD_ENCAP 21 2090 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 2091 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 2092 2093 #define S_LSO_LAST_SLICE 22 2094 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 2095 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 2096 2097 #define S_LSO_FIRST_SLICE 23 2098 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 2099 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 2100 2101 #define S_LSO_OPCODE 24 2102 #define M_LSO_OPCODE 0xFF 2103 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 2104 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 2105 2106 #define S_LSO_T5_XFER_SIZE 0 2107 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 2108 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 2109 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 2110 2111 /* cpl_tx_pkt_lso_core.mss fields */ 2112 #define S_LSO_MSS 0 2113 #define M_LSO_MSS 0x3FFF 2114 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 2115 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 2116 2117 #define S_LSO_IPID_SPLIT 15 2118 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 2119 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 2120 2121 struct cpl_tx_pkt_fso { 2122 WR_HDR; 2123 __be32 fso_ctrl; 2124 __be16 seqcnt_ofst; 2125 __be16 mtu; 2126 __be32 param_offset; 2127 __be32 len; 2128 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 2129 }; 2130 2131 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 2132 #define S_FSO_XCHG_CLASS 21 2133 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 2134 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 2135 2136 #define S_FSO_INITIATOR 20 2137 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 2138 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 2139 2140 #define S_FSO_FCHDR_LEN 12 2141 #define M_FSO_FCHDR_LEN 0xF 2142 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 2143 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 2144 2145 struct cpl_iscsi_hdr_no_rss { 2146 union opcode_tid ot; 2147 __be16 pdu_len_ddp; 2148 __be16 len; 2149 __be32 seq; 2150 __be16 urg; 2151 __u8 rsvd; 2152 __u8 status; 2153 }; 2154 2155 struct cpl_tx_data_iso { 2156 __be32 op_to_scsi; 2157 __u8 reserved1; 2158 __u8 ahs_len; 2159 __be16 mpdu; 2160 __be32 burst_size; 2161 __be32 len; 2162 __be32 reserved2_seglen_offset; 2163 __be32 datasn_offset; 2164 __be32 buffer_offset; 2165 __be32 reserved3; 2166 2167 /* encapsulated CPL_TX_DATA follows here */ 2168 }; 2169 2170 /* cpl_tx_data_iso.op_to_scsi fields */ 2171 #define S_CPL_TX_DATA_ISO_OP 24 2172 #define M_CPL_TX_DATA_ISO_OP 0xff 2173 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 2174 #define G_CPL_TX_DATA_ISO_OP(x) \ 2175 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 2176 2177 #define S_CPL_TX_DATA_ISO_FIRST 23 2178 #define M_CPL_TX_DATA_ISO_FIRST 0x1 2179 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 2180 #define G_CPL_TX_DATA_ISO_FIRST(x) \ 2181 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 2182 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 2183 2184 #define S_CPL_TX_DATA_ISO_LAST 22 2185 #define M_CPL_TX_DATA_ISO_LAST 0x1 2186 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 2187 #define G_CPL_TX_DATA_ISO_LAST(x) \ 2188 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 2189 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 2190 2191 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 2192 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 2193 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 2194 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 2195 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 2196 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 2197 2198 #define S_CPL_TX_DATA_ISO_HDRCRC 20 2199 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1 2200 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 2201 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 2202 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 2203 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 2204 2205 #define S_CPL_TX_DATA_ISO_PLDCRC 19 2206 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1 2207 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 2208 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 2209 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 2210 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 2211 2212 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18 2213 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 2214 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 2215 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 2216 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 2217 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 2218 2219 #define S_CPL_TX_DATA_ISO_SCSI 16 2220 #define M_CPL_TX_DATA_ISO_SCSI 0x3 2221 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 2222 #define G_CPL_TX_DATA_ISO_SCSI(x) \ 2223 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 2224 2225 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 2226 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 2227 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 2228 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 2229 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 2230 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 2231 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 2232 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 2233 2234 struct cpl_t7_tx_data_iso { 2235 __be32 op_to_scsi; 2236 __u8 nvme_tcp_pkd; 2237 __u8 ahs; 2238 __be16 mpdu; 2239 __be32 burst; 2240 __be32 size; 2241 __be32 num_pi_bytes_seglen_offset; 2242 __be32 datasn_offset; 2243 __be32 buffer_offset; 2244 __be32 pdo_pkd; 2245 /* encapsulated CPL_TX_DATA follows here */ 2246 }; 2247 2248 #define S_CPL_T7_TX_DATA_ISO_OPCODE 24 2249 #define M_CPL_T7_TX_DATA_ISO_OPCODE 0xff 2250 #define V_CPL_T7_TX_DATA_ISO_OPCODE(x) ((x) << S_CPL_T7_TX_DATA_ISO_OPCODE) 2251 #define G_CPL_T7_TX_DATA_ISO_OPCODE(x) \ 2252 (((x) >> S_CPL_T7_TX_DATA_ISO_OPCODE) & M_CPL_T7_TX_DATA_ISO_OPCODE) 2253 2254 #define S_CPL_T7_TX_DATA_ISO_FIRST 23 2255 #define M_CPL_T7_TX_DATA_ISO_FIRST 0x1 2256 #define V_CPL_T7_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_T7_TX_DATA_ISO_FIRST) 2257 #define G_CPL_T7_TX_DATA_ISO_FIRST(x) \ 2258 (((x) >> S_CPL_T7_TX_DATA_ISO_FIRST) & M_CPL_T7_TX_DATA_ISO_FIRST) 2259 #define F_CPL_T7_TX_DATA_ISO_FIRST V_CPL_T7_TX_DATA_ISO_FIRST(1U) 2260 2261 #define S_CPL_T7_TX_DATA_ISO_LAST 22 2262 #define M_CPL_T7_TX_DATA_ISO_LAST 0x1 2263 #define V_CPL_T7_TX_DATA_ISO_LAST(x) ((x) << S_CPL_T7_TX_DATA_ISO_LAST) 2264 #define G_CPL_T7_TX_DATA_ISO_LAST(x) \ 2265 (((x) >> S_CPL_T7_TX_DATA_ISO_LAST) & M_CPL_T7_TX_DATA_ISO_LAST) 2266 #define F_CPL_T7_TX_DATA_ISO_LAST V_CPL_T7_TX_DATA_ISO_LAST(1U) 2267 2268 #define S_CPL_T7_TX_DATA_ISO_CPLHDRLEN 21 2269 #define M_CPL_T7_TX_DATA_ISO_CPLHDRLEN 0x1 2270 #define V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x) \ 2271 ((x) << S_CPL_T7_TX_DATA_ISO_CPLHDRLEN) 2272 #define G_CPL_T7_TX_DATA_ISO_CPLHDRLEN(x) \ 2273 (((x) >> S_CPL_T7_TX_DATA_ISO_CPLHDRLEN) & M_CPL_T7_TX_DATA_ISO_CPLHDRLEN) 2274 #define F_CPL_T7_TX_DATA_ISO_CPLHDRLEN V_CPL_T7_TX_DATA_ISO_CPLHDRLEN(1U) 2275 2276 #define S_CPL_T7_TX_DATA_ISO_HDRCRC 20 2277 #define M_CPL_T7_TX_DATA_ISO_HDRCRC 0x1 2278 #define V_CPL_T7_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_T7_TX_DATA_ISO_HDRCRC) 2279 #define G_CPL_T7_TX_DATA_ISO_HDRCRC(x) \ 2280 (((x) >> S_CPL_T7_TX_DATA_ISO_HDRCRC) & M_CPL_T7_TX_DATA_ISO_HDRCRC) 2281 #define F_CPL_T7_TX_DATA_ISO_HDRCRC V_CPL_T7_TX_DATA_ISO_HDRCRC(1U) 2282 2283 #define S_CPL_T7_TX_DATA_ISO_PLDCRC 19 2284 #define M_CPL_T7_TX_DATA_ISO_PLDCRC 0x1 2285 #define V_CPL_T7_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_T7_TX_DATA_ISO_PLDCRC) 2286 #define G_CPL_T7_TX_DATA_ISO_PLDCRC(x) \ 2287 (((x) >> S_CPL_T7_TX_DATA_ISO_PLDCRC) & M_CPL_T7_TX_DATA_ISO_PLDCRC) 2288 #define F_CPL_T7_TX_DATA_ISO_PLDCRC V_CPL_T7_TX_DATA_ISO_PLDCRC(1U) 2289 2290 #define S_CPL_T7_TX_DATA_ISO_IMMEDIATE 18 2291 #define M_CPL_T7_TX_DATA_ISO_IMMEDIATE 0x1 2292 #define V_CPL_T7_TX_DATA_ISO_IMMEDIATE(x) \ 2293 ((x) << S_CPL_T7_TX_DATA_ISO_IMMEDIATE) 2294 #define G_CPL_T7_TX_DATA_ISO_IMMEDIATE(x) \ 2295 (((x) >> S_CPL_T7_TX_DATA_ISO_IMMEDIATE) & M_CPL_T7_TX_DATA_ISO_IMMEDIATE) 2296 #define F_CPL_T7_TX_DATA_ISO_IMMEDIATE \ 2297 V_CPL_T7_TX_DATA_ISO_IMMEDIATE(1U) 2298 2299 #define S_CPL_T7_TX_DATA_ISO_SCSI 16 2300 #define M_CPL_T7_TX_DATA_ISO_SCSI 0x3 2301 #define V_CPL_T7_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_T7_TX_DATA_ISO_SCSI) 2302 #define G_CPL_T7_TX_DATA_ISO_SCSI(x) \ 2303 (((x) >> S_CPL_T7_TX_DATA_ISO_SCSI) & M_CPL_T7_TX_DATA_ISO_SCSI) 2304 2305 #define S_CPL_T7_TX_DATA_ISO_NVME_TCP 0 2306 #define M_CPL_T7_TX_DATA_ISO_NVME_TCP 0x1 2307 #define V_CPL_T7_TX_DATA_ISO_NVME_TCP(x) \ 2308 ((x) << S_CPL_T7_TX_DATA_ISO_NVME_TCP) 2309 #define G_CPL_T7_TX_DATA_ISO_NVME_TCP(x) \ 2310 (((x) >> S_CPL_T7_TX_DATA_ISO_NVME_TCP) & M_CPL_T7_TX_DATA_ISO_NVME_TCP) 2311 #define F_CPL_T7_TX_DATA_ISO_NVME_TCP \ 2312 V_CPL_T7_TX_DATA_ISO_NVME_TCP(1U) 2313 2314 #define S_CPL_T7_TX_DATA_ISO_NUMPIBYTES 24 2315 #define M_CPL_T7_TX_DATA_ISO_NUMPIBYTES 0xff 2316 #define V_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x) \ 2317 ((x) << S_CPL_T7_TX_DATA_ISO_NUMPIBYTES) 2318 #define G_CPL_T7_TX_DATA_ISO_NUMPIBYTES(x) \ 2319 (((x) >> S_CPL_T7_TX_DATA_ISO_NUMPIBYTES) & M_CPL_T7_TX_DATA_ISO_NUMPIBYTES) 2320 2321 #define S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET 0 2322 #define M_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET 0xffffff 2323 #define V_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \ 2324 ((x) << S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) 2325 #define G_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET(x) \ 2326 (((x) >> S_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) & \ 2327 M_CPL_T7_TX_DATA_ISO_DATASEGLENOFFSET) 2328 2329 #define S_CPL_TX_DATA_ISO_PDO 0 2330 #define M_CPL_TX_DATA_ISO_PDO 0xff 2331 #define V_CPL_TX_DATA_ISO_PDO(x) ((x) << S_CPL_TX_DATA_ISO_PDO) 2332 #define G_CPL_TX_DATA_ISO_PDO(x) \ 2333 (((x) >> S_CPL_TX_DATA_ISO_PDO) & M_CPL_TX_DATA_ISO_PDO) 2334 2335 struct cpl_iscsi_hdr { 2336 RSS_HDR 2337 union opcode_tid ot; 2338 __be16 pdu_len_ddp; 2339 __be16 len; 2340 __be32 seq; 2341 __be16 urg; 2342 __u8 rsvd; 2343 __u8 status; 2344 }; 2345 2346 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 2347 #define S_ISCSI_PDU_LEN 0 2348 #define M_ISCSI_PDU_LEN 0x7FFF 2349 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 2350 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 2351 2352 #define S_ISCSI_DDP 15 2353 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 2354 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 2355 2356 struct cpl_iscsi_data { 2357 RSS_HDR 2358 union opcode_tid ot; 2359 __u8 rsvd0[2]; 2360 __be16 len; 2361 __be32 seq; 2362 __be16 urg; 2363 __u8 rsvd1; 2364 __u8 status; 2365 }; 2366 2367 struct cpl_rx_data { 2368 RSS_HDR 2369 union opcode_tid ot; 2370 __be16 rsvd; 2371 __be16 len; 2372 __be32 seq; 2373 __be16 urg; 2374 #if defined(__LITTLE_ENDIAN_BITFIELD) 2375 __u8 dack_mode:2; 2376 __u8 psh:1; 2377 __u8 heartbeat:1; 2378 __u8 ddp_off:1; 2379 __u8 :3; 2380 #else 2381 __u8 :3; 2382 __u8 ddp_off:1; 2383 __u8 heartbeat:1; 2384 __u8 psh:1; 2385 __u8 dack_mode:2; 2386 #endif 2387 __u8 status; 2388 }; 2389 2390 struct cpl_fcoe_hdr { 2391 RSS_HDR 2392 union opcode_tid ot; 2393 __be16 oxid; 2394 __be16 len; 2395 __be32 rctl_fctl; 2396 __u8 cs_ctl; 2397 __u8 df_ctl; 2398 __u8 sof; 2399 __u8 eof; 2400 __be16 seq_cnt; 2401 __u8 seq_id; 2402 __u8 type; 2403 __be32 param; 2404 }; 2405 2406 /* cpl_fcoe_hdr.rctl_fctl fields */ 2407 #define S_FCOE_FCHDR_RCTL 24 2408 #define M_FCOE_FCHDR_RCTL 0xff 2409 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 2410 #define G_FCOE_FCHDR_RCTL(x) \ 2411 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 2412 2413 #define S_FCOE_FCHDR_FCTL 0 2414 #define M_FCOE_FCHDR_FCTL 0xffffff 2415 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 2416 #define G_FCOE_FCHDR_FCTL(x) \ 2417 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 2418 2419 struct cpl_fcoe_data { 2420 RSS_HDR 2421 union opcode_tid ot; 2422 __u8 rsvd0[2]; 2423 __be16 len; 2424 __be32 seq; 2425 __u8 rsvd1[3]; 2426 __u8 status; 2427 }; 2428 2429 struct cpl_rx_urg_notify { 2430 RSS_HDR 2431 union opcode_tid ot; 2432 __be32 seq; 2433 }; 2434 2435 struct cpl_rx_urg_pkt { 2436 RSS_HDR 2437 union opcode_tid ot; 2438 __be16 rsvd; 2439 __be16 len; 2440 }; 2441 2442 struct cpl_rx_data_ack { 2443 WR_HDR; 2444 union opcode_tid ot; 2445 __be32 credit_dack; 2446 }; 2447 2448 struct cpl_rx_data_ack_core { 2449 union opcode_tid ot; 2450 __be32 credit_dack; 2451 }; 2452 2453 /* cpl_rx_data_ack.ack_seq fields */ 2454 #define S_RX_CREDITS 0 2455 #define M_RX_CREDITS 0x3FFFFFF 2456 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 2457 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 2458 2459 #define S_RX_MODULATE_TX 26 2460 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 2461 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 2462 2463 #define S_RX_MODULATE_RX 27 2464 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 2465 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 2466 2467 #define S_RX_FORCE_ACK 28 2468 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 2469 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 2470 2471 #define S_RX_DACK_MODE 29 2472 #define M_RX_DACK_MODE 0x3 2473 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 2474 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 2475 2476 #define S_RX_DACK_CHANGE 31 2477 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 2478 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 2479 2480 struct cpl_rx_phys_addr { 2481 __be32 RSS[2]; 2482 __be32 op_to_tid; 2483 __be32 pci_rlx_order_to_len; 2484 __be64 phys_addr; 2485 }; 2486 2487 #define S_CPL_RX_PHYS_ADDR_OPCODE 24 2488 #define M_CPL_RX_PHYS_ADDR_OPCODE 0xff 2489 #define V_CPL_RX_PHYS_ADDR_OPCODE(x) ((x) << S_CPL_RX_PHYS_ADDR_OPCODE) 2490 #define G_CPL_RX_PHYS_ADDR_OPCODE(x) \ 2491 (((x) >> S_CPL_RX_PHYS_ADDR_OPCODE) & M_CPL_RX_PHYS_ADDR_OPCODE) 2492 2493 #define S_CPL_RX_PHYS_ADDR_ISRDMA 23 2494 #define M_CPL_RX_PHYS_ADDR_ISRDMA 0x1 2495 #define V_CPL_RX_PHYS_ADDR_ISRDMA(x) ((x) << S_CPL_RX_PHYS_ADDR_ISRDMA) 2496 #define G_CPL_RX_PHYS_ADDR_ISRDMA(x) \ 2497 (((x) >> S_CPL_RX_PHYS_ADDR_ISRDMA) & M_CPL_RX_PHYS_ADDR_ISRDMA) 2498 #define F_CPL_RX_PHYS_ADDR_ISRDMA V_CPL_RX_PHYS_ADDR_ISRDMA(1U) 2499 2500 #define S_CPL_RX_PHYS_ADDR_TID 0 2501 #define M_CPL_RX_PHYS_ADDR_TID 0xfffff 2502 #define V_CPL_RX_PHYS_ADDR_TID(x) ((x) << S_CPL_RX_PHYS_ADDR_TID) 2503 #define G_CPL_RX_PHYS_ADDR_TID(x) \ 2504 (((x) >> S_CPL_RX_PHYS_ADDR_TID) & M_CPL_RX_PHYS_ADDR_TID) 2505 2506 #define S_CPL_RX_PHYS_ADDR_PCIRLXORDER 31 2507 #define M_CPL_RX_PHYS_ADDR_PCIRLXORDER 0x1 2508 #define V_CPL_RX_PHYS_ADDR_PCIRLXORDER(x) \ 2509 ((x) << S_CPL_RX_PHYS_ADDR_PCIRLXORDER) 2510 #define G_CPL_RX_PHYS_ADDR_PCIRLXORDER(x) \ 2511 (((x) >> S_CPL_RX_PHYS_ADDR_PCIRLXORDER) & M_CPL_RX_PHYS_ADDR_PCIRLXORDER) 2512 #define F_CPL_RX_PHYS_ADDR_PCIRLXORDER V_CPL_RX_PHYS_ADDR_PCIRLXORDER(1U) 2513 2514 #define S_CPL_RX_PHYS_ADDR_PCINOSNOOP 30 2515 #define M_CPL_RX_PHYS_ADDR_PCINOSNOOP 0x1 2516 #define V_CPL_RX_PHYS_ADDR_PCINOSNOOP(x) \ 2517 ((x) << S_CPL_RX_PHYS_ADDR_PCINOSNOOP) 2518 #define G_CPL_RX_PHYS_ADDR_PCINOSNOOP(x) \ 2519 (((x) >> S_CPL_RX_PHYS_ADDR_PCINOSNOOP) & M_CPL_RX_PHYS_ADDR_PCINOSNOOP) 2520 #define F_CPL_RX_PHYS_ADDR_PCINOSNOOP V_CPL_RX_PHYS_ADDR_PCINOSNOOP(1U) 2521 2522 #define S_CPL_RX_PHYS_ADDR_PCITPHINTEN 29 2523 #define M_CPL_RX_PHYS_ADDR_PCITPHINTEN 0x1 2524 #define V_CPL_RX_PHYS_ADDR_PCITPHINTEN(x) \ 2525 ((x) << S_CPL_RX_PHYS_ADDR_PCITPHINTEN) 2526 #define G_CPL_RX_PHYS_ADDR_PCITPHINTEN(x) \ 2527 (((x) >> S_CPL_RX_PHYS_ADDR_PCITPHINTEN) & M_CPL_RX_PHYS_ADDR_PCITPHINTEN) 2528 #define F_CPL_RX_PHYS_ADDR_PCITPHINTEN V_CPL_RX_PHYS_ADDR_PCITPHINTEN(1U) 2529 2530 #define S_CPL_RX_PHYS_ADDR_PCITPHINT 27 2531 #define M_CPL_RX_PHYS_ADDR_PCITPHINT 0x3 2532 #define V_CPL_RX_PHYS_ADDR_PCITPHINT(x) ((x) << S_CPL_RX_PHYS_ADDR_PCITPHINT) 2533 #define G_CPL_RX_PHYS_ADDR_PCITPHINT(x) \ 2534 (((x) >> S_CPL_RX_PHYS_ADDR_PCITPHINT) & M_CPL_RX_PHYS_ADDR_PCITPHINT) 2535 2536 #define S_CPL_RX_PHYS_ADDR_DCAID 16 2537 #define M_CPL_RX_PHYS_ADDR_DCAID 0x7ff 2538 #define V_CPL_RX_PHYS_ADDR_DCAID(x) ((x) << S_CPL_RX_PHYS_ADDR_DCAID) 2539 #define G_CPL_RX_PHYS_ADDR_DCAID(x) \ 2540 (((x) >> S_CPL_RX_PHYS_ADDR_DCAID) & M_CPL_RX_PHYS_ADDR_DCAID) 2541 2542 #define S_CPL_RX_PHYS_ADDR_LEN 0 2543 #define M_CPL_RX_PHYS_ADDR_LEN 0xffff 2544 #define V_CPL_RX_PHYS_ADDR_LEN(x) ((x) << S_CPL_RX_PHYS_ADDR_LEN) 2545 #define G_CPL_RX_PHYS_ADDR_LEN(x) \ 2546 (((x) >> S_CPL_RX_PHYS_ADDR_LEN) & M_CPL_RX_PHYS_ADDR_LEN) 2547 2548 struct cpl_rx_ddp_complete { 2549 RSS_HDR 2550 union opcode_tid ot; 2551 __be32 ddp_report; 2552 __be32 rcv_nxt; 2553 __be32 rsvd; 2554 }; 2555 2556 struct cpl_rx_data_ddp { 2557 RSS_HDR 2558 union opcode_tid ot; 2559 __be16 urg; 2560 __be16 len; 2561 __be32 seq; 2562 union { 2563 __be32 nxt_seq; 2564 __be32 ddp_report; 2565 } u; 2566 __be32 ulp_crc; 2567 __be32 ddpvld; 2568 }; 2569 2570 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 2571 2572 struct cpl_rx_fcoe_ddp { 2573 RSS_HDR 2574 union opcode_tid ot; 2575 __be16 rsvd; 2576 __be16 len; 2577 __be32 seq; 2578 __be32 ddp_report; 2579 __be32 ulp_crc; 2580 __be32 ddpvld; 2581 }; 2582 2583 struct cpl_rx_data_dif { 2584 RSS_HDR 2585 union opcode_tid ot; 2586 __be16 ddp_len; 2587 __be16 msg_len; 2588 __be32 seq; 2589 union { 2590 __be32 nxt_seq; 2591 __be32 ddp_report; 2592 } u; 2593 __be32 err_vec; 2594 __be32 ddpvld; 2595 }; 2596 2597 struct cpl_rx_iscsi_dif { 2598 RSS_HDR 2599 union opcode_tid ot; 2600 __be16 ddp_len; 2601 __be16 msg_len; 2602 __be32 seq; 2603 union { 2604 __be32 nxt_seq; 2605 __be32 ddp_report; 2606 } u; 2607 __be32 ulp_crc; 2608 __be32 ddpvld; 2609 __u8 rsvd0[8]; 2610 __be32 err_vec; 2611 __u8 rsvd1[4]; 2612 }; 2613 2614 struct cpl_rx_iscsi_cmp { 2615 RSS_HDR 2616 union opcode_tid ot; 2617 __be16 pdu_len_ddp; 2618 __be16 len; 2619 __be32 seq; 2620 __be16 urg; 2621 __u8 rsvd; 2622 __u8 status; 2623 __be32 ulp_crc; 2624 __be32 ddpvld; 2625 }; 2626 2627 struct cpl_rx_fcoe_dif { 2628 RSS_HDR 2629 union opcode_tid ot; 2630 __be16 ddp_len; 2631 __be16 msg_len; 2632 __be32 seq; 2633 __be32 ddp_report; 2634 __be32 err_vec; 2635 __be32 ddpvld; 2636 }; 2637 2638 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 2639 #define S_DDP_VALID 15 2640 #define M_DDP_VALID 0x1FFFF 2641 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 2642 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 2643 2644 #define S_DDP_PPOD_MISMATCH 15 2645 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 2646 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 2647 2648 #define S_DDP_PDU 16 2649 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 2650 #define F_DDP_PDU V_DDP_PDU(1U) 2651 2652 #define S_DDP_LLIMIT_ERR 17 2653 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 2654 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 2655 2656 #define S_DDP_PPOD_PARITY_ERR 18 2657 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 2658 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 2659 2660 #define S_DDP_PADDING_ERR 19 2661 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 2662 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 2663 2664 #define S_DDP_HDRCRC_ERR 20 2665 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 2666 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 2667 2668 #define S_DDP_DATACRC_ERR 21 2669 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 2670 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 2671 2672 #define S_DDP_INVALID_TAG 22 2673 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 2674 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 2675 2676 #define S_DDP_ULIMIT_ERR 23 2677 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 2678 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 2679 2680 #define S_DDP_OFFSET_ERR 24 2681 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 2682 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 2683 2684 #define S_DDP_COLOR_ERR 25 2685 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 2686 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 2687 2688 #define S_DDP_TID_MISMATCH 26 2689 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 2690 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 2691 2692 #define S_DDP_INVALID_PPOD 27 2693 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 2694 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 2695 2696 #define S_DDP_ULP_MODE 28 2697 #define M_DDP_ULP_MODE 0xF 2698 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 2699 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 2700 2701 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 2702 #define S_DDP_OFFSET 0 2703 #define M_DDP_OFFSET 0xFFFFFF 2704 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 2705 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 2706 2707 #define S_DDP_DACK_MODE 24 2708 #define M_DDP_DACK_MODE 0x3 2709 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 2710 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 2711 2712 #define S_DDP_BUF_IDX 26 2713 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 2714 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 2715 2716 #define S_DDP_URG 27 2717 #define V_DDP_URG(x) ((x) << S_DDP_URG) 2718 #define F_DDP_URG V_DDP_URG(1U) 2719 2720 #define S_DDP_PSH 28 2721 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 2722 #define F_DDP_PSH V_DDP_PSH(1U) 2723 2724 #define S_DDP_BUF_COMPLETE 29 2725 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 2726 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 2727 2728 #define S_DDP_BUF_TIMED_OUT 30 2729 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 2730 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 2731 2732 #define S_DDP_INV 31 2733 #define V_DDP_INV(x) ((x) << S_DDP_INV) 2734 #define F_DDP_INV V_DDP_INV(1U) 2735 2736 struct cpl_rx_pkt { 2737 RSS_HDR 2738 __u8 opcode; 2739 #if defined(__LITTLE_ENDIAN_BITFIELD) 2740 __u8 iff:4; 2741 __u8 csum_calc:1; 2742 __u8 ipmi_pkt:1; 2743 __u8 vlan_ex:1; 2744 __u8 ip_frag:1; 2745 #else 2746 __u8 ip_frag:1; 2747 __u8 vlan_ex:1; 2748 __u8 ipmi_pkt:1; 2749 __u8 csum_calc:1; 2750 __u8 iff:4; 2751 #endif 2752 __be16 csum; 2753 __be16 vlan; 2754 __be16 len; 2755 __be32 l2info; 2756 __be16 hdr_len; 2757 __be16 err_vec; 2758 }; 2759 2760 /* rx_pkt.l2info fields */ 2761 #define S_RX_ETHHDR_LEN 0 2762 #define M_RX_ETHHDR_LEN 0x1F 2763 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 2764 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 2765 2766 #define S_RX_T5_ETHHDR_LEN 0 2767 #define M_RX_T5_ETHHDR_LEN 0x3F 2768 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 2769 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 2770 2771 #define M_RX_T6_ETHHDR_LEN 0xFF 2772 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 2773 2774 #define S_RX_PKTYPE 5 2775 #define M_RX_PKTYPE 0x7 2776 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 2777 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 2778 2779 #define S_RX_T5_DATYPE 6 2780 #define M_RX_T5_DATYPE 0x3 2781 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 2782 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 2783 2784 #define S_RX_MACIDX 8 2785 #define M_RX_MACIDX 0x1FF 2786 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 2787 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 2788 2789 #define S_RX_T5_PKTYPE 17 2790 #define M_RX_T5_PKTYPE 0x7 2791 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 2792 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 2793 2794 #define S_RX_DATYPE 18 2795 #define M_RX_DATYPE 0x3 2796 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 2797 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 2798 2799 #define S_RXF_PSH 20 2800 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 2801 #define F_RXF_PSH V_RXF_PSH(1U) 2802 2803 #define S_RXF_SYN 21 2804 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 2805 #define F_RXF_SYN V_RXF_SYN(1U) 2806 2807 #define S_RXF_UDP 22 2808 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 2809 #define F_RXF_UDP V_RXF_UDP(1U) 2810 2811 #define S_RXF_TCP 23 2812 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 2813 #define F_RXF_TCP V_RXF_TCP(1U) 2814 2815 #define S_RXF_IP 24 2816 #define V_RXF_IP(x) ((x) << S_RXF_IP) 2817 #define F_RXF_IP V_RXF_IP(1U) 2818 2819 #define S_RXF_IP6 25 2820 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 2821 #define F_RXF_IP6 V_RXF_IP6(1U) 2822 2823 #define S_RXF_SYN_COOKIE 26 2824 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 2825 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 2826 2827 #define S_RXF_FCOE 26 2828 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 2829 #define F_RXF_FCOE V_RXF_FCOE(1U) 2830 2831 #define S_RXF_LRO 27 2832 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 2833 #define F_RXF_LRO V_RXF_LRO(1U) 2834 2835 #define S_RX_CHAN 28 2836 #define M_RX_CHAN 0xF 2837 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 2838 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 2839 2840 /* rx_pkt.hdr_len fields */ 2841 #define S_RX_TCPHDR_LEN 0 2842 #define M_RX_TCPHDR_LEN 0x3F 2843 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 2844 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 2845 2846 #define S_RX_IPHDR_LEN 6 2847 #define M_RX_IPHDR_LEN 0x3FF 2848 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 2849 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 2850 2851 /* rx_pkt.err_vec fields */ 2852 #define S_RXERR_OR 0 2853 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 2854 #define F_RXERR_OR V_RXERR_OR(1U) 2855 2856 #define S_RXERR_MAC 1 2857 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 2858 #define F_RXERR_MAC V_RXERR_MAC(1U) 2859 2860 #define S_RXERR_IPVERS 2 2861 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 2862 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2863 2864 #define S_RXERR_FRAG 3 2865 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2866 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 2867 2868 #define S_RXERR_ATTACK 4 2869 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2870 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2871 2872 #define S_RXERR_ETHHDR_LEN 5 2873 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2874 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2875 2876 #define S_RXERR_IPHDR_LEN 6 2877 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2878 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2879 2880 #define S_RXERR_TCPHDR_LEN 7 2881 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2882 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2883 2884 #define S_RXERR_PKT_LEN 8 2885 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2886 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2887 2888 #define S_RXERR_TCP_OPT 9 2889 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2890 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2891 2892 #define S_RXERR_IPCSUM 12 2893 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2894 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2895 2896 #define S_RXERR_CSUM 13 2897 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2898 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 2899 2900 #define S_RXERR_PING 14 2901 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2902 #define F_RXERR_PING V_RXERR_PING(1U) 2903 2904 /* In T6, rx_pkt.err_vec indicates 2905 * RxError Error vector (16b) or 2906 * Encapsulating header length (8b), 2907 * Outer encapsulation type (2b) and 2908 * compressed error vector (6b) if CRxPktEnc is 2909 * enabled in TP_OUT_CONFIG 2910 */ 2911 2912 #define S_T6_COMPR_RXERR_VEC 0 2913 #define M_T6_COMPR_RXERR_VEC 0x3F 2914 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2915 #define G_T6_COMPR_RXERR_VEC(x) \ 2916 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2917 2918 #define S_T6_COMPR_RXERR_MAC 0 2919 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2920 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2921 2922 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2923 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2924 */ 2925 #define S_T6_COMPR_RXERR_LEN 1 2926 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2927 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2928 2929 #define S_T6_COMPR_RXERR_TCP_OPT 2 2930 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2931 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2932 2933 #define S_T6_COMPR_RXERR_IPV6_EXT 3 2934 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2935 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2936 2937 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2938 #define S_T6_COMPR_RXERR_SUM 4 2939 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2940 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2941 2942 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2943 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2944 */ 2945 #define S_T6_COMPR_RXERR_MISC 5 2946 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2947 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2948 2949 #define S_T6_RX_TNL_TYPE 6 2950 #define M_T6_RX_TNL_TYPE 0x3 2951 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2952 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2953 2954 #define RX_PKT_TNL_TYPE_NVGRE 1 2955 #define RX_PKT_TNL_TYPE_VXLAN 2 2956 #define RX_PKT_TNL_TYPE_GENEVE 3 2957 2958 #define S_T6_RX_TNLHDR_LEN 8 2959 #define M_T6_RX_TNLHDR_LEN 0xFF 2960 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2961 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2962 2963 struct cpl_trace_pkt { 2964 RSS_HDR 2965 __u8 opcode; 2966 __u8 intf; 2967 #if defined(__LITTLE_ENDIAN_BITFIELD) 2968 __u8 runt:4; 2969 __u8 filter_hit:4; 2970 __u8 :6; 2971 __u8 err:1; 2972 __u8 trunc:1; 2973 #else 2974 __u8 filter_hit:4; 2975 __u8 runt:4; 2976 __u8 trunc:1; 2977 __u8 err:1; 2978 __u8 :6; 2979 #endif 2980 __be16 rsvd; 2981 __be16 len; 2982 __be64 tstamp; 2983 }; 2984 2985 struct cpl_t5_trace_pkt { 2986 RSS_HDR 2987 __u8 opcode; 2988 __u8 intf; 2989 #if defined(__LITTLE_ENDIAN_BITFIELD) 2990 __u8 runt:4; 2991 __u8 filter_hit:4; 2992 __u8 :6; 2993 __u8 err:1; 2994 __u8 trunc:1; 2995 #else 2996 __u8 filter_hit:4; 2997 __u8 runt:4; 2998 __u8 trunc:1; 2999 __u8 err:1; 3000 __u8 :6; 3001 #endif 3002 __be16 rsvd; 3003 __be16 len; 3004 __be64 tstamp; 3005 __be64 rsvd1; 3006 }; 3007 3008 struct cpl_rte_delete_req { 3009 WR_HDR; 3010 union opcode_tid ot; 3011 __be32 params; 3012 }; 3013 3014 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 3015 #define S_RTE_REQ_LUT_IX 8 3016 #define M_RTE_REQ_LUT_IX 0x7FF 3017 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 3018 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 3019 3020 #define S_RTE_REQ_LUT_BASE 19 3021 #define M_RTE_REQ_LUT_BASE 0x7FF 3022 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 3023 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 3024 3025 #define S_RTE_READ_REQ_SELECT 31 3026 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 3027 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 3028 3029 struct cpl_rte_delete_rpl { 3030 RSS_HDR 3031 union opcode_tid ot; 3032 __u8 status; 3033 __u8 rsvd[3]; 3034 }; 3035 3036 struct cpl_rte_write_req { 3037 WR_HDR; 3038 union opcode_tid ot; 3039 __u32 write_sel; 3040 __be32 lut_params; 3041 __be32 l2t_idx; 3042 __be32 netmask; 3043 __be32 faddr; 3044 }; 3045 3046 /* cpl_rte_write_req.write_sel fields */ 3047 #define S_RTE_WR_L2TIDX 31 3048 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 3049 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 3050 3051 #define S_RTE_WR_FADDR 30 3052 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 3053 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 3054 3055 /* cpl_rte_write_req.lut_params fields */ 3056 #define S_RTE_WR_LUT_IX 10 3057 #define M_RTE_WR_LUT_IX 0x7FF 3058 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 3059 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 3060 3061 #define S_RTE_WR_LUT_BASE 21 3062 #define M_RTE_WR_LUT_BASE 0x7FF 3063 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 3064 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 3065 3066 struct cpl_rte_write_rpl { 3067 RSS_HDR 3068 union opcode_tid ot; 3069 __u8 status; 3070 __u8 rsvd[3]; 3071 }; 3072 3073 struct cpl_rte_read_req { 3074 WR_HDR; 3075 union opcode_tid ot; 3076 __be32 params; 3077 }; 3078 3079 struct cpl_rte_read_rpl { 3080 RSS_HDR 3081 union opcode_tid ot; 3082 __u8 status; 3083 __u8 rsvd; 3084 __be16 l2t_idx; 3085 #if defined(__LITTLE_ENDIAN_BITFIELD) 3086 __u32 :30; 3087 __u32 select:1; 3088 #else 3089 __u32 select:1; 3090 __u32 :30; 3091 #endif 3092 __be32 addr; 3093 }; 3094 3095 struct cpl_l2t_write_req { 3096 WR_HDR; 3097 union opcode_tid ot; 3098 __be16 params; 3099 __be16 l2t_idx; 3100 __be16 vlan; 3101 __u8 dst_mac[6]; 3102 }; 3103 3104 /* cpl_l2t_write_req.params fields */ 3105 #define S_L2T_W_INFO 2 3106 #define M_L2T_W_INFO 0x3F 3107 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 3108 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 3109 3110 #define S_L2T_W_PORT 8 3111 #define M_L2T_W_PORT 0x3 3112 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 3113 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 3114 3115 #define S_L2T_W_LPBK 10 3116 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 3117 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 3118 3119 #define S_L2T_W_ARPMISS 11 3120 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 3121 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 3122 3123 #define S_L2T_W_NOREPLY 15 3124 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 3125 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 3126 3127 3128 /* cpl_l2t_write_req.vlan fields */ 3129 #define S_L2T_VLANTAG 0 3130 #define M_L2T_VLANTAG 0xFFF 3131 #define V_L2T_VLANTAG(x) ((x) << S_L2T_VLANTAG) 3132 #define G_L2T_VLANTAG(x) (((x) >> S_L2T_VLANTAG) & M_L2T_VLANTAG) 3133 3134 #define S_L2T_VLANPRIO 13 3135 #define M_L2T_VLANPRIO 0x7 3136 #define V_L2T_VLANPRIO(x) ((x) << S_L2T_VLANPRIO) 3137 #define G_L2T_VLANPRIO(x) (((x) >> S_L2T_VLANPRIO) & M_L2T_VLANPRIO) 3138 3139 #define CPL_L2T_VLAN_NONE 0xfff 3140 3141 struct cpl_l2t_write_rpl { 3142 RSS_HDR 3143 union opcode_tid ot; 3144 __u8 status; 3145 __u8 rsvd[3]; 3146 }; 3147 3148 struct cpl_l2t_read_req { 3149 WR_HDR; 3150 union opcode_tid ot; 3151 __be32 l2t_idx; 3152 }; 3153 3154 struct cpl_l2t_read_rpl { 3155 RSS_HDR 3156 union opcode_tid ot; 3157 __u8 status; 3158 #if defined(__LITTLE_ENDIAN_BITFIELD) 3159 __u8 :4; 3160 __u8 iff:4; 3161 #else 3162 __u8 iff:4; 3163 __u8 :4; 3164 #endif 3165 __be16 vlan; 3166 __be16 info; 3167 __u8 dst_mac[6]; 3168 }; 3169 3170 struct cpl_srq_table_req { 3171 WR_HDR; 3172 union opcode_tid ot; 3173 __u8 status; 3174 __u8 rsvd[2]; 3175 __u8 idx; 3176 __be64 rsvd_pdid; 3177 __be32 qlen_qbase; 3178 __be16 cur_msn; 3179 __be16 max_msn; 3180 }; 3181 3182 struct cpl_srq_table_rpl { 3183 RSS_HDR 3184 union opcode_tid ot; 3185 __u8 status; 3186 __u8 rsvd[2]; 3187 __u8 idx; 3188 __be64 rsvd_pdid; 3189 __be32 qlen_qbase; 3190 __be16 cur_msn; 3191 __be16 max_msn; 3192 }; 3193 3194 /* cpl_srq_table_{req,rpl}.params fields */ 3195 #define S_SRQT_QLEN 28 3196 #define M_SRQT_QLEN 0xF 3197 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 3198 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 3199 3200 #define S_SRQT_QBASE 0 3201 #define M_SRQT_QBASE 0x3FFFFFF 3202 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 3203 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 3204 3205 #define S_SRQT_PDID 0 3206 #define M_SRQT_PDID 0xFF 3207 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 3208 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 3209 3210 #define S_SRQT_IDX 0 3211 #define M_SRQT_IDX 0xF 3212 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 3213 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 3214 3215 struct cpl_t7_srq_table_req { 3216 WR_HDR; 3217 union opcode_tid ot; 3218 __be32 noreply_to_index; 3219 __be16 srqlimit_pkd; 3220 __be16 cqid; 3221 __be16 xdid; 3222 __be16 pdid; 3223 __be32 quelen_quebase; 3224 __be32 curmsn_maxmsn; 3225 }; 3226 3227 #define S_CPL_T7_SRQ_TABLE_REQ_NOREPLY 31 3228 #define M_CPL_T7_SRQ_TABLE_REQ_NOREPLY 0x1 3229 #define V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x) \ 3230 ((x) << S_CPL_T7_SRQ_TABLE_REQ_NOREPLY) 3231 #define G_CPL_T7_SRQ_TABLE_REQ_NOREPLY(x) \ 3232 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_NOREPLY) & M_CPL_T7_SRQ_TABLE_REQ_NOREPLY) 3233 #define F_CPL_T7_SRQ_TABLE_REQ_NOREPLY \ 3234 V_CPL_T7_SRQ_TABLE_REQ_NOREPLY(1U) 3235 3236 #define S_CPL_T7_SRQ_TABLE_REQ_WRITE 30 3237 #define M_CPL_T7_SRQ_TABLE_REQ_WRITE 0x1 3238 #define V_CPL_T7_SRQ_TABLE_REQ_WRITE(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_WRITE) 3239 #define G_CPL_T7_SRQ_TABLE_REQ_WRITE(x) \ 3240 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_WRITE) & M_CPL_T7_SRQ_TABLE_REQ_WRITE) 3241 #define F_CPL_T7_SRQ_TABLE_REQ_WRITE V_CPL_T7_SRQ_TABLE_REQ_WRITE(1U) 3242 3243 #define S_CPL_T7_SRQ_TABLE_REQ_INCR 28 3244 #define M_CPL_T7_SRQ_TABLE_REQ_INCR 0x3 3245 #define V_CPL_T7_SRQ_TABLE_REQ_INCR(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_INCR) 3246 #define G_CPL_T7_SRQ_TABLE_REQ_INCR(x) \ 3247 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INCR) & M_CPL_T7_SRQ_TABLE_REQ_INCR) 3248 3249 #define S_CPL_T7_SRQ_TABLE_REQ_OVER 24 3250 #define M_CPL_T7_SRQ_TABLE_REQ_OVER 0xf 3251 #define V_CPL_T7_SRQ_TABLE_REQ_OVER(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_OVER) 3252 #define G_CPL_T7_SRQ_TABLE_REQ_OVER(x) \ 3253 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_OVER) & M_CPL_T7_SRQ_TABLE_REQ_OVER) 3254 3255 #define S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD 23 3256 #define M_CPL_T7_SRQ_TABLE_REQ_LIMITUPD 0x1 3257 #define V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x) \ 3258 ((x) << S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) 3259 #define G_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(x) \ 3260 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) & M_CPL_T7_SRQ_TABLE_REQ_LIMITUPD) 3261 #define F_CPL_T7_SRQ_TABLE_REQ_LIMITUPD V_CPL_T7_SRQ_TABLE_REQ_LIMITUPD(1U) 3262 3263 #define S_CPL_T7_SRQ_TABLE_REQ_INDEX 0 3264 #define M_CPL_T7_SRQ_TABLE_REQ_INDEX 0x3ff 3265 #define V_CPL_T7_SRQ_TABLE_REQ_INDEX(x) ((x) << S_CPL_T7_SRQ_TABLE_REQ_INDEX) 3266 #define G_CPL_T7_SRQ_TABLE_REQ_INDEX(x) \ 3267 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_INDEX) & M_CPL_T7_SRQ_TABLE_REQ_INDEX) 3268 3269 #define S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT 0 3270 #define M_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT 0x3f 3271 #define V_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x) \ 3272 ((x) << S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) 3273 #define G_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT(x) \ 3274 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_REQ_SRQLIMIT) 3275 3276 #define S_CPL_T7_SRQ_TABLE_REQ_QUELEN 28 3277 #define M_CPL_T7_SRQ_TABLE_REQ_QUELEN 0xf 3278 #define V_CPL_T7_SRQ_TABLE_REQ_QUELEN(x) \ 3279 ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUELEN) 3280 #define G_CPL_T7_SRQ_TABLE_REQ_QUELEN(x) \ 3281 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUELEN) & M_CPL_T7_SRQ_TABLE_REQ_QUELEN) 3282 3283 #define S_CPL_T7_SRQ_TABLE_REQ_QUEBASE 0 3284 #define M_CPL_T7_SRQ_TABLE_REQ_QUEBASE 0x3ffffff 3285 #define V_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x) \ 3286 ((x) << S_CPL_T7_SRQ_TABLE_REQ_QUEBASE) 3287 #define G_CPL_T7_SRQ_TABLE_REQ_QUEBASE(x) \ 3288 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_QUEBASE) & M_CPL_T7_SRQ_TABLE_REQ_QUEBASE) 3289 3290 #define S_CPL_T7_SRQ_TABLE_REQ_CURMSN 16 3291 #define M_CPL_T7_SRQ_TABLE_REQ_CURMSN 0xffff 3292 #define V_CPL_T7_SRQ_TABLE_REQ_CURMSN(x) \ 3293 ((x) << S_CPL_T7_SRQ_TABLE_REQ_CURMSN) 3294 #define G_CPL_T7_SRQ_TABLE_REQ_CURMSN(x) \ 3295 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_CURMSN) & M_CPL_T7_SRQ_TABLE_REQ_CURMSN) 3296 3297 #define S_CPL_T7_SRQ_TABLE_REQ_MAXMSN 0 3298 #define M_CPL_T7_SRQ_TABLE_REQ_MAXMSN 0xffff 3299 #define V_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x) \ 3300 ((x) << S_CPL_T7_SRQ_TABLE_REQ_MAXMSN) 3301 #define G_CPL_T7_SRQ_TABLE_REQ_MAXMSN(x) \ 3302 (((x) >> S_CPL_T7_SRQ_TABLE_REQ_MAXMSN) & M_CPL_T7_SRQ_TABLE_REQ_MAXMSN) 3303 3304 struct cpl_t7_srq_table_rpl { 3305 RSS_HDR 3306 union opcode_tid ot; 3307 __be32 status_index; 3308 __be16 srqlimit_pkd; 3309 __be16 cqid; 3310 __be16 xdid; 3311 __be16 pdid; 3312 __be32 quelen_quebase; 3313 __be32 curmsn_maxmsn; 3314 }; 3315 3316 #define S_CPL_T7_SRQ_TABLE_RPL_STATUS 24 3317 #define M_CPL_T7_SRQ_TABLE_RPL_STATUS 0xff 3318 #define V_CPL_T7_SRQ_TABLE_RPL_STATUS(x) \ 3319 ((x) << S_CPL_T7_SRQ_TABLE_RPL_STATUS) 3320 #define G_CPL_T7_SRQ_TABLE_RPL_STATUS(x) \ 3321 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_STATUS) & M_CPL_T7_SRQ_TABLE_RPL_STATUS) 3322 3323 #define S_CPL_T7_SRQ_TABLE_RPL_INDEX 0 3324 #define M_CPL_T7_SRQ_TABLE_RPL_INDEX 0x3ff 3325 #define V_CPL_T7_SRQ_TABLE_RPL_INDEX(x) ((x) << S_CPL_T7_SRQ_TABLE_RPL_INDEX) 3326 #define G_CPL_T7_SRQ_TABLE_RPL_INDEX(x) \ 3327 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_INDEX) & M_CPL_T7_SRQ_TABLE_RPL_INDEX) 3328 3329 #define S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT 0 3330 #define M_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT 0x3f 3331 #define V_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x) \ 3332 ((x) << S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) 3333 #define G_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT(x) \ 3334 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) & M_CPL_T7_SRQ_TABLE_RPL_SRQLIMIT) 3335 3336 #define S_CPL_T7_SRQ_TABLE_RPL_QUELEN 28 3337 #define M_CPL_T7_SRQ_TABLE_RPL_QUELEN 0xf 3338 #define V_CPL_T7_SRQ_TABLE_RPL_QUELEN(x) \ 3339 ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUELEN) 3340 #define G_CPL_T7_SRQ_TABLE_RPL_QUELEN(x) \ 3341 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUELEN) & M_CPL_T7_SRQ_TABLE_RPL_QUELEN) 3342 3343 #define S_CPL_T7_SRQ_TABLE_RPL_QUEBASE 0 3344 #define M_CPL_T7_SRQ_TABLE_RPL_QUEBASE 0x3ffffff 3345 #define V_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x) \ 3346 ((x) << S_CPL_T7_SRQ_TABLE_RPL_QUEBASE) 3347 #define G_CPL_T7_SRQ_TABLE_RPL_QUEBASE(x) \ 3348 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_QUEBASE) & M_CPL_T7_SRQ_TABLE_RPL_QUEBASE) 3349 3350 #define S_CPL_T7_SRQ_TABLE_RPL_CURMSN 16 3351 #define M_CPL_T7_SRQ_TABLE_RPL_CURMSN 0xffff 3352 #define V_CPL_T7_SRQ_TABLE_RPL_CURMSN(x) \ 3353 ((x) << S_CPL_T7_SRQ_TABLE_RPL_CURMSN) 3354 #define G_CPL_T7_SRQ_TABLE_RPL_CURMSN(x) \ 3355 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_CURMSN) & M_CPL_T7_SRQ_TABLE_RPL_CURMSN) 3356 3357 #define S_CPL_T7_SRQ_TABLE_RPL_MAXMSN 0 3358 #define M_CPL_T7_SRQ_TABLE_RPL_MAXMSN 0xffff 3359 #define V_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x) \ 3360 ((x) << S_CPL_T7_SRQ_TABLE_RPL_MAXMSN) 3361 #define G_CPL_T7_SRQ_TABLE_RPL_MAXMSN(x) \ 3362 (((x) >> S_CPL_T7_SRQ_TABLE_RPL_MAXMSN) & M_CPL_T7_SRQ_TABLE_RPL_MAXMSN) 3363 3364 struct cpl_rdma_async_event { 3365 RSS_HDR 3366 union opcode_tid ot; 3367 __be32 EventInfo; 3368 }; 3369 3370 #define S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE 16 3371 #define M_CPL_RDMA_ASYNC_EVENT_EVENTTYPE 0xf 3372 #define V_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \ 3373 ((x) << S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) 3374 #define G_CPL_RDMA_ASYNC_EVENT_EVENTTYPE(x) \ 3375 (((x) >> S_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) & \ 3376 M_CPL_RDMA_ASYNC_EVENT_EVENTTYPE) 3377 3378 #define S_CPL_RDMA_ASYNC_EVENT_INDEX 0 3379 #define M_CPL_RDMA_ASYNC_EVENT_INDEX 0xffff 3380 #define V_CPL_RDMA_ASYNC_EVENT_INDEX(x) ((x) << S_CPL_RDMA_ASYNC_EVENT_INDEX) 3381 #define G_CPL_RDMA_ASYNC_EVENT_INDEX(x) \ 3382 (((x) >> S_CPL_RDMA_ASYNC_EVENT_INDEX) & M_CPL_RDMA_ASYNC_EVENT_INDEX) 3383 3384 struct cpl_smt_write_req { 3385 WR_HDR; 3386 union opcode_tid ot; 3387 __be32 params; 3388 __be16 pfvf1; 3389 __u8 src_mac1[6]; 3390 __be16 pfvf0; 3391 __u8 src_mac0[6]; 3392 }; 3393 3394 struct cpl_t6_smt_write_req { 3395 WR_HDR; 3396 union opcode_tid ot; 3397 __be32 params; 3398 __be64 tag; 3399 __be16 pfvf0; 3400 __u8 src_mac0[6]; 3401 __be32 local_ip; 3402 __be32 rsvd; 3403 }; 3404 3405 struct cpl_smt_write_rpl { 3406 RSS_HDR 3407 union opcode_tid ot; 3408 __u8 status; 3409 __u8 rsvd[3]; 3410 }; 3411 3412 struct cpl_smt_read_req { 3413 WR_HDR; 3414 union opcode_tid ot; 3415 __be32 params; 3416 }; 3417 3418 struct cpl_smt_read_rpl { 3419 RSS_HDR 3420 union opcode_tid ot; 3421 __u8 status; 3422 __u8 ovlan_idx; 3423 __be16 rsvd; 3424 __be16 pfvf1; 3425 __u8 src_mac1[6]; 3426 __be16 pfvf0; 3427 __u8 src_mac0[6]; 3428 }; 3429 3430 /* cpl_smt_{read,write}_req.params fields */ 3431 #define S_SMTW_OVLAN_IDX 16 3432 #define M_SMTW_OVLAN_IDX 0xF 3433 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 3434 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 3435 3436 #define S_SMTW_IDX 20 3437 #define M_SMTW_IDX 0x7F 3438 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 3439 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 3440 3441 #define M_T6_SMTW_IDX 0xFF 3442 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 3443 3444 #define S_SMTW_NORPL 31 3445 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 3446 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 3447 3448 /* cpl_smt_{read,write}_req.pfvf? fields */ 3449 #define S_SMTW_VF 0 3450 #define M_SMTW_VF 0xFF 3451 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 3452 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 3453 3454 #define S_SMTW_PF 8 3455 #define M_SMTW_PF 0x7 3456 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 3457 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 3458 3459 #define S_SMTW_VF_VLD 11 3460 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 3461 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 3462 3463 struct cpl_t7_smt_write_req { 3464 WR_HDR; 3465 union opcode_tid ot; 3466 __be32 noreply_to_mtu; 3467 union smt_write_req { 3468 struct smt_write_req_pfvf { 3469 __be64 tagvalue; 3470 __be32 pfvf_smac_hi; 3471 __be32 smac_lo; 3472 __be64 tagext; 3473 } pfvf; 3474 struct smt_write_req_ipv4 { 3475 __be32 srcipv4; 3476 __be32 destipv4; 3477 } ipv4; 3478 struct smt_write_req_ipv6 { 3479 __be64 ipv6ms; 3480 __be64 ipv6ls; 3481 } ipv6; 3482 } u; 3483 }; 3484 3485 #define S_CPL_T7_SMT_WRITE_REQ_NOREPLY 31 3486 #define M_CPL_T7_SMT_WRITE_REQ_NOREPLY 0x1 3487 #define V_CPL_T7_SMT_WRITE_REQ_NOREPLY(x) \ 3488 ((x) << S_CPL_T7_SMT_WRITE_REQ_NOREPLY) 3489 #define G_CPL_T7_SMT_WRITE_REQ_NOREPLY(x) \ 3490 (((x) >> S_CPL_T7_SMT_WRITE_REQ_NOREPLY) & M_CPL_T7_SMT_WRITE_REQ_NOREPLY) 3491 #define F_CPL_T7_SMT_WRITE_REQ_NOREPLY \ 3492 V_CPL_T7_SMT_WRITE_REQ_NOREPLY(1U) 3493 3494 #define S_CPL_T7_SMT_WRITE_REQ_TAGINSERT 30 3495 #define M_CPL_T7_SMT_WRITE_REQ_TAGINSERT 0x1 3496 #define V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x) \ 3497 ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGINSERT) 3498 #define G_CPL_T7_SMT_WRITE_REQ_TAGINSERT(x) \ 3499 (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGINSERT) & \ 3500 M_CPL_T7_SMT_WRITE_REQ_TAGINSERT) 3501 #define F_CPL_T7_SMT_WRITE_REQ_TAGINSERT \ 3502 V_CPL_T7_SMT_WRITE_REQ_TAGINSERT(1U) 3503 3504 #define S_CPL_T7_SMT_WRITE_REQ_TAGTYPE 28 3505 #define M_CPL_T7_SMT_WRITE_REQ_TAGTYPE 0x3 3506 #define V_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x) \ 3507 ((x) << S_CPL_T7_SMT_WRITE_REQ_TAGTYPE) 3508 #define G_CPL_T7_SMT_WRITE_REQ_TAGTYPE(x) \ 3509 (((x) >> S_CPL_T7_SMT_WRITE_REQ_TAGTYPE) & M_CPL_T7_SMT_WRITE_REQ_TAGTYPE) 3510 3511 #define S_CPL_T7_SMT_WRITE_REQ_INDEX 20 3512 #define M_CPL_T7_SMT_WRITE_REQ_INDEX 0xff 3513 #define V_CPL_T7_SMT_WRITE_REQ_INDEX(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_INDEX) 3514 #define G_CPL_T7_SMT_WRITE_REQ_INDEX(x) \ 3515 (((x) >> S_CPL_T7_SMT_WRITE_REQ_INDEX) & M_CPL_T7_SMT_WRITE_REQ_INDEX) 3516 3517 #define S_CPL_T7_SMT_WRITE_REQ_OVLAN 16 3518 #define M_CPL_T7_SMT_WRITE_REQ_OVLAN 0xf 3519 #define V_CPL_T7_SMT_WRITE_REQ_OVLAN(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_OVLAN) 3520 #define G_CPL_T7_SMT_WRITE_REQ_OVLAN(x) \ 3521 (((x) >> S_CPL_T7_SMT_WRITE_REQ_OVLAN) & M_CPL_T7_SMT_WRITE_REQ_OVLAN) 3522 3523 #define S_CPL_T7_SMT_WRITE_REQ_IPSEC 14 3524 #define M_CPL_T7_SMT_WRITE_REQ_IPSEC 0x1 3525 #define V_CPL_T7_SMT_WRITE_REQ_IPSEC(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_IPSEC) 3526 #define G_CPL_T7_SMT_WRITE_REQ_IPSEC(x) \ 3527 (((x) >> S_CPL_T7_SMT_WRITE_REQ_IPSEC) & M_CPL_T7_SMT_WRITE_REQ_IPSEC) 3528 #define F_CPL_T7_SMT_WRITE_REQ_IPSEC V_CPL_T7_SMT_WRITE_REQ_IPSEC(1U) 3529 3530 #define S_CPL_T7_SMT_WRITE_REQ_MTU 0 3531 #define M_CPL_T7_SMT_WRITE_REQ_MTU 0x3fff 3532 #define V_CPL_T7_SMT_WRITE_REQ_MTU(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_MTU) 3533 #define G_CPL_T7_SMT_WRITE_REQ_MTU(x) \ 3534 (((x) >> S_CPL_T7_SMT_WRITE_REQ_MTU) & M_CPL_T7_SMT_WRITE_REQ_MTU) 3535 3536 #define S_CPL_T7_SMT_WRITE_REQ_PFVF 16 3537 #define M_CPL_T7_SMT_WRITE_REQ_PFVF 0xfff 3538 #define V_CPL_T7_SMT_WRITE_REQ_PFVF(x) ((x) << S_CPL_T7_SMT_WRITE_REQ_PFVF) 3539 #define G_CPL_T7_SMT_WRITE_REQ_PFVF(x) \ 3540 (((x) >> S_CPL_T7_SMT_WRITE_REQ_PFVF) & M_CPL_T7_SMT_WRITE_REQ_PFVF) 3541 3542 #define S_CPL_T7_SMT_WRITE_REQ_SMAC_HI 0 3543 #define M_CPL_T7_SMT_WRITE_REQ_SMAC_HI 0xffff 3544 #define V_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x) \ 3545 ((x) << S_CPL_T7_SMT_WRITE_REQ_SMAC_HI) 3546 #define G_CPL_T7_SMT_WRITE_REQ_SMAC_HI(x) \ 3547 (((x) >> S_CPL_T7_SMT_WRITE_REQ_SMAC_HI) & M_CPL_T7_SMT_WRITE_REQ_SMAC_HI) 3548 3549 struct cpl_t7_smt_read_req { 3550 WR_HDR; 3551 union opcode_tid ot; 3552 __be32 index_to_ipsecidx; 3553 }; 3554 3555 #define S_CPL_T7_SMT_READ_REQ_INDEX 20 3556 #define M_CPL_T7_SMT_READ_REQ_INDEX 0xff 3557 #define V_CPL_T7_SMT_READ_REQ_INDEX(x) ((x) << S_CPL_T7_SMT_READ_REQ_INDEX) 3558 #define G_CPL_T7_SMT_READ_REQ_INDEX(x) \ 3559 (((x) >> S_CPL_SMT_READ_REQ_INDEX) & M_CPL_T7_SMT_READ_REQ_INDEX) 3560 3561 #define S_CPL_T7_SMT_READ_REQ_IPSEC 14 3562 #define M_CPL_T7_SMT_READ_REQ_IPSEC 0x1 3563 #define V_CPL_T7_SMT_READ_REQ_IPSEC(x) ((x) << S_CPL_T7_SMT_READ_REQ_IPSEC) 3564 #define G_CPL_T7_SMT_READ_REQ_IPSEC(x) \ 3565 (((x) >> S_CPL_T7_SMT_READ_REQ_IPSEC) & M_CPL_T7_SMT_READ_REQ_IPSEC) 3566 #define F_CPL_T7_SMT_READ_REQ_IPSEC V_CPL_T7_SMT_READ_REQ_IPSEC(1U) 3567 3568 #define S_CPL_T7_SMT_READ_REQ_IPSECIDX 0 3569 #define M_CPL_T7_SMT_READ_REQ_IPSECIDX 0x1fff 3570 #define V_CPL_T7_SMT_READ_REQ_IPSECIDX(x) \ 3571 ((x) << S_CPL_T7_SMT_READ_REQ_IPSECIDX) 3572 #define G_CPL_T7_SMT_READ_REQ_IPSECIDX(x) \ 3573 (((x) >> S_CPL_T7_SMT_READ_REQ_IPSECIDX) & M_CPL_T7_SMT_READ_REQ_IPSECIDX) 3574 3575 struct cpl_tag_write_req { 3576 WR_HDR; 3577 union opcode_tid ot; 3578 __be32 params; 3579 __be64 tag_val; 3580 }; 3581 3582 struct cpl_tag_write_rpl { 3583 RSS_HDR 3584 union opcode_tid ot; 3585 __u8 status; 3586 __u8 rsvd[2]; 3587 __u8 idx; 3588 }; 3589 3590 struct cpl_tag_read_req { 3591 WR_HDR; 3592 union opcode_tid ot; 3593 __be32 params; 3594 }; 3595 3596 struct cpl_tag_read_rpl { 3597 RSS_HDR 3598 union opcode_tid ot; 3599 __u8 status; 3600 #if defined(__LITTLE_ENDIAN_BITFIELD) 3601 __u8 :4; 3602 __u8 tag_len:1; 3603 __u8 :2; 3604 __u8 ins_enable:1; 3605 #else 3606 __u8 ins_enable:1; 3607 __u8 :2; 3608 __u8 tag_len:1; 3609 __u8 :4; 3610 #endif 3611 __u8 rsvd; 3612 __u8 tag_idx; 3613 __be64 tag_val; 3614 }; 3615 3616 /* cpl_tag{read,write}_req.params fields */ 3617 #define S_TAGW_IDX 0 3618 #define M_TAGW_IDX 0x7F 3619 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 3620 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 3621 3622 #define S_TAGW_LEN 20 3623 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 3624 #define F_TAGW_LEN V_TAGW_LEN(1U) 3625 3626 #define S_TAGW_INS_ENABLE 23 3627 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 3628 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 3629 3630 #define S_TAGW_NORPL 31 3631 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 3632 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 3633 3634 struct cpl_barrier { 3635 WR_HDR; 3636 __u8 opcode; 3637 __u8 chan_map; 3638 __be16 rsvd0; 3639 __be32 rsvd1; 3640 }; 3641 3642 /* cpl_barrier.chan_map fields */ 3643 #define S_CHAN_MAP 4 3644 #define M_CHAN_MAP 0xF 3645 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 3646 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 3647 3648 struct cpl_error { 3649 RSS_HDR 3650 union opcode_tid ot; 3651 __be32 error; 3652 }; 3653 3654 struct cpl_hit_notify { 3655 RSS_HDR 3656 union opcode_tid ot; 3657 __be32 rsvd; 3658 __be32 info; 3659 __be32 reason; 3660 }; 3661 3662 struct cpl_pkt_notify { 3663 RSS_HDR 3664 union opcode_tid ot; 3665 __be16 rsvd; 3666 __be16 len; 3667 __be32 info; 3668 __be32 reason; 3669 }; 3670 3671 /* cpl_{hit,pkt}_notify.info fields */ 3672 #define S_NTFY_MAC_IDX 0 3673 #define M_NTFY_MAC_IDX 0x1FF 3674 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 3675 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 3676 3677 #define S_NTFY_INTF 10 3678 #define M_NTFY_INTF 0xF 3679 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 3680 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 3681 3682 #define S_NTFY_TCPHDR_LEN 14 3683 #define M_NTFY_TCPHDR_LEN 0xF 3684 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 3685 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 3686 3687 #define S_NTFY_IPHDR_LEN 18 3688 #define M_NTFY_IPHDR_LEN 0x1FF 3689 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 3690 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 3691 3692 #define S_NTFY_ETHHDR_LEN 27 3693 #define M_NTFY_ETHHDR_LEN 0x1F 3694 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 3695 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 3696 3697 #define S_NTFY_T5_IPHDR_LEN 18 3698 #define M_NTFY_T5_IPHDR_LEN 0xFF 3699 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 3700 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 3701 3702 #define S_NTFY_T5_ETHHDR_LEN 26 3703 #define M_NTFY_T5_ETHHDR_LEN 0x3F 3704 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 3705 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 3706 3707 struct cpl_t7_pkt_notify { 3708 RSS_HDR 3709 union opcode_tid ot; 3710 __be16 r1; 3711 __be16 length; 3712 __be32 ethhdrlen_to_macindex; 3713 __be32 lineinfo; 3714 }; 3715 3716 #define S_CPL_T7_PKT_NOTIFY_ETHHDRLEN 24 3717 #define M_CPL_T7_PKT_NOTIFY_ETHHDRLEN 0xff 3718 #define V_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x) \ 3719 ((x) << S_CPL_T7_PKT_NOTIFY_ETHHDRLEN) 3720 #define G_CPL_T7_PKT_NOTIFY_ETHHDRLEN(x) \ 3721 (((x) >> S_CPL_T7_PKT_NOTIFY_ETHHDRLEN) & M_CPL_T7_PKT_NOTIFY_ETHHDRLEN) 3722 3723 #define S_CPL_T7_PKT_NOTIFY_IPHDRLEN 18 3724 #define M_CPL_T7_PKT_NOTIFY_IPHDRLEN 0x3f 3725 #define V_CPL_T7_PKT_NOTIFY_IPHDRLEN(x) ((x) << S_CPL_T7_PKT_NOTIFY_IPHDRLEN) 3726 #define G_CPL_T7_PKT_NOTIFY_IPHDRLEN(x) \ 3727 (((x) >> S_CPL_T7_PKT_NOTIFY_IPHDRLEN) & M_CPL_T7_PKT_NOTIFY_IPHDRLEN) 3728 3729 #define S_CPL_T7_PKT_NOTIFY_TCPHDRLEN 14 3730 #define M_CPL_T7_PKT_NOTIFY_TCPHDRLEN 0xf 3731 #define V_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x) \ 3732 ((x) << S_CPL_T7_PKT_NOTIFY_TCPHDRLEN) 3733 #define G_CPL_T7_PKT_NOTIFY_TCPHDRLEN(x) \ 3734 (((x) >> S_CPL_T7_PKT_NOTIFY_TCPHDRLEN) & M_CPL_T7_PKT_NOTIFY_TCPHDRLEN) 3735 3736 #define S_CPL_T7_PKT_NOTIFY_INTERFACE 10 3737 #define M_CPL_T7_PKT_NOTIFY_INTERFACE 0xf 3738 #define V_CPL_T7_PKT_NOTIFY_INTERFACE(x) \ 3739 ((x) << S_CPL_T7_PKT_NOTIFY_INTERFACE) 3740 #define G_CPL_T7_PKT_NOTIFY_INTERFACE(x) \ 3741 (((x) >> S_CPL_T7_PKT_NOTIFY_INTERFACE) & M_CPL_T7_PKT_NOTIFY_INTERFACE) 3742 3743 #define S_CPL_T7_PKT_NOTIFY_MACINDEX 0 3744 #define M_CPL_T7_PKT_NOTIFY_MACINDEX 0x1ff 3745 #define V_CPL_T7_PKT_NOTIFY_MACINDEX(x) ((x) << S_CPL_T7_PKT_NOTIFY_MACINDEX) 3746 #define G_CPL_T7_PKT_NOTIFY_MACINDEX(x) \ 3747 (((x) >> S_CPL_T7_PKT_NOTIFY_MACINDEX) & M_CPL_T7_PKT_NOTIFY_MACINDEX) 3748 3749 struct cpl_rdma_cqe { 3750 WR_HDR; 3751 union opcode_tid ot; 3752 __be32 tid_flitcnt; 3753 __be32 qpid_to_wr_type; 3754 __be32 length; 3755 __be32 tag; 3756 __be32 msn; 3757 }; 3758 3759 #define S_CPL_RDMA_CQE_RSSCTRL 16 3760 #define M_CPL_RDMA_CQE_RSSCTRL 0xff 3761 #define V_CPL_RDMA_CQE_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_RSSCTRL) 3762 #define G_CPL_RDMA_CQE_RSSCTRL(x) \ 3763 (((x) >> S_CPL_RDMA_CQE_RSSCTRL) & M_CPL_RDMA_CQE_RSSCTRL) 3764 3765 #define S_CPL_RDMA_CQE_CQID 0 3766 #define M_CPL_RDMA_CQE_CQID 0xffff 3767 #define V_CPL_RDMA_CQE_CQID(x) ((x) << S_CPL_RDMA_CQE_CQID) 3768 #define G_CPL_RDMA_CQE_CQID(x) \ 3769 (((x) >> S_CPL_RDMA_CQE_CQID) & M_CPL_RDMA_CQE_CQID) 3770 3771 #define S_CPL_RDMA_CQE_TID 8 3772 #define M_CPL_RDMA_CQE_TID 0xfffff 3773 #define V_CPL_RDMA_CQE_TID(x) ((x) << S_CPL_RDMA_CQE_TID) 3774 #define G_CPL_RDMA_CQE_TID(x) \ 3775 (((x) >> S_CPL_RDMA_CQE_TID) & M_CPL_RDMA_CQE_TID) 3776 3777 #define S_CPL_RDMA_CQE_FLITCNT 0 3778 #define M_CPL_RDMA_CQE_FLITCNT 0xff 3779 #define V_CPL_RDMA_CQE_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_FLITCNT) 3780 #define G_CPL_RDMA_CQE_FLITCNT(x) \ 3781 (((x) >> S_CPL_RDMA_CQE_FLITCNT) & M_CPL_RDMA_CQE_FLITCNT) 3782 3783 #define S_CPL_RDMA_CQE_QPID 12 3784 #define M_CPL_RDMA_CQE_QPID 0xfffff 3785 #define V_CPL_RDMA_CQE_QPID(x) ((x) << S_CPL_RDMA_CQE_QPID) 3786 #define G_CPL_RDMA_CQE_QPID(x) \ 3787 (((x) >> S_CPL_RDMA_CQE_QPID) & M_CPL_RDMA_CQE_QPID) 3788 3789 #define S_CPL_RDMA_CQE_GENERATION_BIT 10 3790 #define M_CPL_RDMA_CQE_GENERATION_BIT 0x1 3791 #define V_CPL_RDMA_CQE_GENERATION_BIT(x) \ 3792 ((x) << S_CPL_RDMA_CQE_GENERATION_BIT) 3793 #define G_CPL_RDMA_CQE_GENERATION_BIT(x) \ 3794 (((x) >> S_CPL_RDMA_CQE_GENERATION_BIT) & M_CPL_RDMA_CQE_GENERATION_BIT) 3795 #define F_CPL_RDMA_CQE_GENERATION_BIT V_CPL_RDMA_CQE_GENERATION_BIT(1U) 3796 3797 #define S_CPL_RDMA_CQE_STATUS 5 3798 #define M_CPL_RDMA_CQE_STATUS 0x1f 3799 #define V_CPL_RDMA_CQE_STATUS(x) ((x) << S_CPL_RDMA_CQE_STATUS) 3800 #define G_CPL_RDMA_CQE_STATUS(x) \ 3801 (((x) >> S_CPL_RDMA_CQE_STATUS) & M_CPL_RDMA_CQE_STATUS) 3802 3803 #define S_CPL_RDMA_CQE_CQE_TYPE 4 3804 #define M_CPL_RDMA_CQE_CQE_TYPE 0x1 3805 #define V_CPL_RDMA_CQE_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_CQE_TYPE) 3806 #define G_CPL_RDMA_CQE_CQE_TYPE(x) \ 3807 (((x) >> S_CPL_RDMA_CQE_CQE_TYPE) & M_CPL_RDMA_CQE_CQE_TYPE) 3808 #define F_CPL_RDMA_CQE_CQE_TYPE V_CPL_RDMA_CQE_CQE_TYPE(1U) 3809 3810 #define S_CPL_RDMA_CQE_WR_TYPE 0 3811 #define M_CPL_RDMA_CQE_WR_TYPE 0xf 3812 #define V_CPL_RDMA_CQE_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_WR_TYPE) 3813 #define G_CPL_RDMA_CQE_WR_TYPE(x) \ 3814 (((x) >> S_CPL_RDMA_CQE_WR_TYPE) & M_CPL_RDMA_CQE_WR_TYPE) 3815 3816 struct cpl_rdma_cqe_srq { 3817 WR_HDR; 3818 union opcode_tid ot; 3819 __be32 tid_flitcnt; 3820 __be32 qpid_to_wr_type; 3821 __be32 length; 3822 __be32 tag; 3823 __be32 msn; 3824 __be32 r3; 3825 __be32 rqe; 3826 }; 3827 3828 #define S_CPL_RDMA_CQE_SRQ_OPCODE 24 3829 #define M_CPL_RDMA_CQE_SRQ_OPCODE 0xff 3830 #define V_CPL_RDMA_CQE_SRQ_OPCODE(x) ((x) << S_CPL_RDMA_CQE_SRQ_OPCODE) 3831 #define G_CPL_RDMA_CQE_SRQ_OPCODE(x) \ 3832 (((x) >> S_CPL_RDMA_CQE_SRQ_OPCODE) & M_CPL_RDMA_CQE_SRQ_OPCODE) 3833 3834 #define S_CPL_RDMA_CQE_SRQ_RSSCTRL 16 3835 #define M_CPL_RDMA_CQE_SRQ_RSSCTRL 0xff 3836 #define V_CPL_RDMA_CQE_SRQ_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_SRQ_RSSCTRL) 3837 #define G_CPL_RDMA_CQE_SRQ_RSSCTRL(x) \ 3838 (((x) >> S_CPL_RDMA_CQE_SRQ_RSSCTRL) & M_CPL_RDMA_CQE_SRQ_RSSCTRL) 3839 3840 #define S_CPL_RDMA_CQE_SRQ_CQID 0 3841 #define M_CPL_RDMA_CQE_SRQ_CQID 0xffff 3842 #define V_CPL_RDMA_CQE_SRQ_CQID(x) ((x) << S_CPL_RDMA_CQE_SRQ_CQID) 3843 #define G_CPL_RDMA_CQE_SRQ_CQID(x) \ 3844 (((x) >> S_CPL_RDMA_CQE_SRQ_CQID) & M_CPL_RDMA_CQE_SRQ_CQID) 3845 3846 #define S_CPL_RDMA_CQE_SRQ_TID 8 3847 #define M_CPL_RDMA_CQE_SRQ_TID 0xfffff 3848 #define V_CPL_RDMA_CQE_SRQ_TID(x) ((x) << S_CPL_RDMA_CQE_SRQ_TID) 3849 #define G_CPL_RDMA_CQE_SRQ_TID(x) \ 3850 (((x) >> S_CPL_RDMA_CQE_SRQ_TID) & M_CPL_RDMA_CQE_SRQ_TID) 3851 3852 #define S_CPL_RDMA_CQE_SRQ_FLITCNT 0 3853 #define M_CPL_RDMA_CQE_SRQ_FLITCNT 0xff 3854 #define V_CPL_RDMA_CQE_SRQ_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_SRQ_FLITCNT) 3855 #define G_CPL_RDMA_CQE_SRQ_FLITCNT(x) \ 3856 (((x) >> S_CPL_RDMA_CQE_SRQ_FLITCNT) & M_CPL_RDMA_CQE_SRQ_FLITCNT) 3857 3858 #define S_CPL_RDMA_CQE_SRQ_QPID 12 3859 #define M_CPL_RDMA_CQE_SRQ_QPID 0xfffff 3860 #define V_CPL_RDMA_CQE_SRQ_QPID(x) ((x) << S_CPL_RDMA_CQE_SRQ_QPID) 3861 #define G_CPL_RDMA_CQE_SRQ_QPID(x) \ 3862 (((x) >> S_CPL_RDMA_CQE_SRQ_QPID) & M_CPL_RDMA_CQE_SRQ_QPID) 3863 3864 #define S_CPL_RDMA_CQE_SRQ_GENERATION_BIT 10 3865 #define M_CPL_RDMA_CQE_SRQ_GENERATION_BIT 0x1 3866 #define V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \ 3867 ((x) << S_CPL_RDMA_CQE_SRQ_GENERATION_BIT) 3868 #define G_CPL_RDMA_CQE_SRQ_GENERATION_BIT(x) \ 3869 (((x) >> S_CPL_RDMA_CQE_SRQ_GENERATION_BIT) & \ 3870 M_CPL_RDMA_CQE_SRQ_GENERATION_BIT) 3871 #define F_CPL_RDMA_CQE_SRQ_GENERATION_BIT \ 3872 V_CPL_RDMA_CQE_SRQ_GENERATION_BIT(1U) 3873 3874 #define S_CPL_RDMA_CQE_SRQ_STATUS 5 3875 #define M_CPL_RDMA_CQE_SRQ_STATUS 0x1f 3876 #define V_CPL_RDMA_CQE_SRQ_STATUS(x) ((x) << S_CPL_RDMA_CQE_SRQ_STATUS) 3877 #define G_CPL_RDMA_CQE_SRQ_STATUS(x) \ 3878 (((x) >> S_CPL_RDMA_CQE_SRQ_STATUS) & M_CPL_RDMA_CQE_SRQ_STATUS) 3879 3880 #define S_CPL_RDMA_CQE_SRQ_CQE_TYPE 4 3881 #define M_CPL_RDMA_CQE_SRQ_CQE_TYPE 0x1 3882 #define V_CPL_RDMA_CQE_SRQ_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_SRQ_CQE_TYPE) 3883 #define G_CPL_RDMA_CQE_SRQ_CQE_TYPE(x) \ 3884 (((x) >> S_CPL_RDMA_CQE_SRQ_CQE_TYPE) & M_CPL_RDMA_CQE_SRQ_CQE_TYPE) 3885 #define F_CPL_RDMA_CQE_SRQ_CQE_TYPE V_CPL_RDMA_CQE_SRQ_CQE_TYPE(1U) 3886 3887 #define S_CPL_RDMA_CQE_SRQ_WR_TYPE 0 3888 #define M_CPL_RDMA_CQE_SRQ_WR_TYPE 0xf 3889 #define V_CPL_RDMA_CQE_SRQ_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_SRQ_WR_TYPE) 3890 #define G_CPL_RDMA_CQE_SRQ_WR_TYPE(x) \ 3891 (((x) >> S_CPL_RDMA_CQE_SRQ_WR_TYPE) & M_CPL_RDMA_CQE_SRQ_WR_TYPE) 3892 3893 struct cpl_rdma_cqe_read_rsp { 3894 WR_HDR; 3895 union opcode_tid ot; 3896 __be32 tid_flitcnt; 3897 __be32 qpid_to_wr_type; 3898 __be32 length; 3899 __be32 tag; 3900 __be32 msn; 3901 }; 3902 3903 #define S_CPL_RDMA_CQE_READ_RSP_RSSCTRL 16 3904 #define M_CPL_RDMA_CQE_READ_RSP_RSSCTRL 0xff 3905 #define V_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \ 3906 ((x) << S_CPL_RDMA_CQE_READ_RSP_RSSCTRL) 3907 #define G_CPL_RDMA_CQE_READ_RSP_RSSCTRL(x) \ 3908 (((x) >> S_CPL_RDMA_CQE_READ_RSP_RSSCTRL) & \ 3909 M_CPL_RDMA_CQE_READ_RSP_RSSCTRL) 3910 3911 #define S_CPL_RDMA_CQE_READ_RSP_CQID 0 3912 #define M_CPL_RDMA_CQE_READ_RSP_CQID 0xffff 3913 #define V_CPL_RDMA_CQE_READ_RSP_CQID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_CQID) 3914 #define G_CPL_RDMA_CQE_READ_RSP_CQID(x) \ 3915 (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQID) & M_CPL_RDMA_CQE_READ_RSP_CQID) 3916 3917 #define S_CPL_RDMA_CQE_READ_RSP_TID 8 3918 #define M_CPL_RDMA_CQE_READ_RSP_TID 0xfffff 3919 #define V_CPL_RDMA_CQE_READ_RSP_TID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_TID) 3920 #define G_CPL_RDMA_CQE_READ_RSP_TID(x) \ 3921 (((x) >> S_CPL_RDMA_CQE_READ_RSP_TID) & M_CPL_RDMA_CQE_READ_RSP_TID) 3922 3923 #define S_CPL_RDMA_CQE_READ_RSP_FLITCNT 0 3924 #define M_CPL_RDMA_CQE_READ_RSP_FLITCNT 0xff 3925 #define V_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \ 3926 ((x) << S_CPL_RDMA_CQE_READ_RSP_FLITCNT) 3927 #define G_CPL_RDMA_CQE_READ_RSP_FLITCNT(x) \ 3928 (((x) >> S_CPL_RDMA_CQE_READ_RSP_FLITCNT) & \ 3929 M_CPL_RDMA_CQE_READ_RSP_FLITCNT) 3930 3931 #define S_CPL_RDMA_CQE_READ_RSP_QPID 12 3932 #define M_CPL_RDMA_CQE_READ_RSP_QPID 0xfffff 3933 #define V_CPL_RDMA_CQE_READ_RSP_QPID(x) ((x) << S_CPL_RDMA_CQE_READ_RSP_QPID) 3934 #define G_CPL_RDMA_CQE_READ_RSP_QPID(x) \ 3935 (((x) >> S_CPL_RDMA_CQE_READ_RSP_QPID) & M_CPL_RDMA_CQE_READ_RSP_QPID) 3936 3937 #define S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT 10 3938 #define M_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT 0x1 3939 #define V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \ 3940 ((x) << S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) 3941 #define G_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(x) \ 3942 (((x) >> S_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) & \ 3943 M_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT) 3944 #define F_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT \ 3945 V_CPL_RDMA_CQE_READ_RSP_GENERATION_BIT(1U) 3946 3947 #define S_CPL_RDMA_CQE_READ_RSP_STATUS 5 3948 #define M_CPL_RDMA_CQE_READ_RSP_STATUS 0x1f 3949 #define V_CPL_RDMA_CQE_READ_RSP_STATUS(x) \ 3950 ((x) << S_CPL_RDMA_CQE_READ_RSP_STATUS) 3951 #define G_CPL_RDMA_CQE_READ_RSP_STATUS(x) \ 3952 (((x) >> S_CPL_RDMA_CQE_READ_RSP_STATUS) & M_CPL_RDMA_CQE_READ_RSP_STATUS) 3953 3954 #define S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE 4 3955 #define M_CPL_RDMA_CQE_READ_RSP_CQE_TYPE 0x1 3956 #define V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \ 3957 ((x) << S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) 3958 #define G_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(x) \ 3959 (((x) >> S_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) & \ 3960 M_CPL_RDMA_CQE_READ_RSP_CQE_TYPE) 3961 #define F_CPL_RDMA_CQE_READ_RSP_CQE_TYPE V_CPL_RDMA_CQE_READ_RSP_CQE_TYPE(1U) 3962 3963 #define S_CPL_RDMA_CQE_READ_RSP_WR_TYPE 0 3964 #define M_CPL_RDMA_CQE_READ_RSP_WR_TYPE 0xf 3965 #define V_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \ 3966 ((x) << S_CPL_RDMA_CQE_READ_RSP_WR_TYPE) 3967 #define G_CPL_RDMA_CQE_READ_RSP_WR_TYPE(x) \ 3968 (((x) >> S_CPL_RDMA_CQE_READ_RSP_WR_TYPE) & \ 3969 M_CPL_RDMA_CQE_READ_RSP_WR_TYPE) 3970 3971 struct cpl_rdma_cqe_err { 3972 WR_HDR; 3973 union opcode_tid ot; 3974 __be32 tid_flitcnt; 3975 __be32 qpid_to_wr_type; 3976 __be32 length; 3977 __be32 tag; 3978 __be32 msn; 3979 }; 3980 3981 #define S_CPL_RDMA_CQE_ERR_RSSCTRL 16 3982 #define M_CPL_RDMA_CQE_ERR_RSSCTRL 0xff 3983 #define V_CPL_RDMA_CQE_ERR_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_ERR_RSSCTRL) 3984 #define G_CPL_RDMA_CQE_ERR_RSSCTRL(x) \ 3985 (((x) >> S_CPL_RDMA_CQE_ERR_RSSCTRL) & M_CPL_RDMA_CQE_ERR_RSSCTRL) 3986 3987 #define S_CPL_RDMA_CQE_ERR_CQID 0 3988 #define M_CPL_RDMA_CQE_ERR_CQID 0xffff 3989 #define V_CPL_RDMA_CQE_ERR_CQID(x) ((x) << S_CPL_RDMA_CQE_ERR_CQID) 3990 #define G_CPL_RDMA_CQE_ERR_CQID(x) \ 3991 (((x) >> S_CPL_RDMA_CQE_ERR_CQID) & M_CPL_RDMA_CQE_ERR_CQID) 3992 3993 #define S_CPL_RDMA_CQE_ERR_TID 8 3994 #define M_CPL_RDMA_CQE_ERR_TID 0xfffff 3995 #define V_CPL_RDMA_CQE_ERR_TID(x) ((x) << S_CPL_RDMA_CQE_ERR_TID) 3996 #define G_CPL_RDMA_CQE_ERR_TID(x) \ 3997 (((x) >> S_CPL_RDMA_CQE_ERR_TID) & M_CPL_RDMA_CQE_ERR_TID) 3998 3999 #define S_CPL_RDMA_CQE_ERR_FLITCNT 0 4000 #define M_CPL_RDMA_CQE_ERR_FLITCNT 0xff 4001 #define V_CPL_RDMA_CQE_ERR_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_ERR_FLITCNT) 4002 #define G_CPL_RDMA_CQE_ERR_FLITCNT(x) \ 4003 (((x) >> S_CPL_RDMA_CQE_ERR_FLITCNT) & M_CPL_RDMA_CQE_ERR_FLITCNT) 4004 4005 #define S_CPL_RDMA_CQE_ERR_QPID 12 4006 #define M_CPL_RDMA_CQE_ERR_QPID 0xfffff 4007 #define V_CPL_RDMA_CQE_ERR_QPID(x) ((x) << S_CPL_RDMA_CQE_ERR_QPID) 4008 #define G_CPL_RDMA_CQE_ERR_QPID(x) \ 4009 (((x) >> S_CPL_RDMA_CQE_ERR_QPID) & M_CPL_RDMA_CQE_ERR_QPID) 4010 4011 #define S_CPL_RDMA_CQE_ERR_GENERATION_BIT 10 4012 #define M_CPL_RDMA_CQE_ERR_GENERATION_BIT 0x1 4013 #define V_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \ 4014 ((x) << S_CPL_RDMA_CQE_ERR_GENERATION_BIT) 4015 #define G_CPL_RDMA_CQE_ERR_GENERATION_BIT(x) \ 4016 (((x) >> S_CPL_RDMA_CQE_ERR_GENERATION_BIT) & \ 4017 M_CPL_RDMA_CQE_ERR_GENERATION_BIT) 4018 #define F_CPL_RDMA_CQE_ERR_GENERATION_BIT \ 4019 V_CPL_RDMA_CQE_ERR_GENERATION_BIT(1U) 4020 4021 #define S_CPL_RDMA_CQE_ERR_STATUS 5 4022 #define M_CPL_RDMA_CQE_ERR_STATUS 0x1f 4023 #define V_CPL_RDMA_CQE_ERR_STATUS(x) ((x) << S_CPL_RDMA_CQE_ERR_STATUS) 4024 #define G_CPL_RDMA_CQE_ERR_STATUS(x) \ 4025 (((x) >> S_CPL_RDMA_CQE_ERR_STATUS) & M_CPL_RDMA_CQE_ERR_STATUS) 4026 4027 #define S_CPL_RDMA_CQE_ERR_CQE_TYPE 4 4028 #define M_CPL_RDMA_CQE_ERR_CQE_TYPE 0x1 4029 #define V_CPL_RDMA_CQE_ERR_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_ERR_CQE_TYPE) 4030 #define G_CPL_RDMA_CQE_ERR_CQE_TYPE(x) \ 4031 (((x) >> S_CPL_RDMA_CQE_ERR_CQE_TYPE) & M_CPL_RDMA_CQE_ERR_CQE_TYPE) 4032 #define F_CPL_RDMA_CQE_ERR_CQE_TYPE V_CPL_RDMA_CQE_ERR_CQE_TYPE(1U) 4033 4034 #define S_CPL_RDMA_CQE_ERR_WR_TYPE 0 4035 #define M_CPL_RDMA_CQE_ERR_WR_TYPE 0xf 4036 #define V_CPL_RDMA_CQE_ERR_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_ERR_WR_TYPE) 4037 #define G_CPL_RDMA_CQE_ERR_WR_TYPE(x) \ 4038 (((x) >> S_CPL_RDMA_CQE_ERR_WR_TYPE) & M_CPL_RDMA_CQE_ERR_WR_TYPE) 4039 4040 struct cpl_rdma_read_req { 4041 WR_HDR; 4042 union opcode_tid ot; 4043 __be16 srq_pkd; 4044 __be16 length; 4045 }; 4046 4047 #define S_CPL_RDMA_READ_REQ_SRQ 0 4048 #define M_CPL_RDMA_READ_REQ_SRQ 0xfff 4049 #define V_CPL_RDMA_READ_REQ_SRQ(x) ((x) << S_CPL_RDMA_READ_REQ_SRQ) 4050 #define G_CPL_RDMA_READ_REQ_SRQ(x) \ 4051 (((x) >> S_CPL_RDMA_READ_REQ_SRQ) & M_CPL_RDMA_READ_REQ_SRQ) 4052 4053 struct cpl_rdma_terminate { 4054 RSS_HDR 4055 union opcode_tid ot; 4056 __be16 rsvd; 4057 __be16 len; 4058 }; 4059 4060 struct cpl_rdma_atomic_req { 4061 RSS_HDR 4062 union opcode_tid ot; 4063 __be16 opcode_srq; 4064 __be16 length; 4065 }; 4066 4067 #define S_CPL_RDMA_ATOMIC_REQ_OPCODE 12 4068 #define M_CPL_RDMA_ATOMIC_REQ_OPCODE 0xf 4069 #define V_CPL_RDMA_ATOMIC_REQ_OPCODE(x) ((x) << S_CPL_RDMA_ATOMIC_REQ_OPCODE) 4070 #define G_CPL_RDMA_ATOMIC_REQ_OPCODE(x) \ 4071 (((x) >> S_CPL_RDMA_ATOMIC_REQ_OPCODE) & M_CPL_RDMA_ATOMIC_REQ_OPCODE) 4072 4073 #define S_CPL_RDMA_ATOMIC_REQ_SRQ 0 4074 #define M_CPL_RDMA_ATOMIC_REQ_SRQ 0xfff 4075 #define V_CPL_RDMA_ATOMIC_REQ_SRQ(x) ((x) << S_CPL_RDMA_ATOMIC_REQ_SRQ) 4076 #define G_CPL_RDMA_ATOMIC_REQ_SRQ(x) \ 4077 (((x) >> S_CPL_RDMA_ATOMIC_REQ_SRQ) & M_CPL_RDMA_ATOMIC_REQ_SRQ) 4078 4079 struct cpl_rdma_atomic_rpl { 4080 RSS_HDR 4081 union opcode_tid ot; 4082 __be16 opcode_srq; 4083 __be16 length; 4084 }; 4085 4086 #define S_CPL_RDMA_ATOMIC_RPL_OPCODE 12 4087 #define M_CPL_RDMA_ATOMIC_RPL_OPCODE 0xf 4088 #define V_CPL_RDMA_ATOMIC_RPL_OPCODE(x) ((x) << S_CPL_RDMA_ATOMIC_RPL_OPCODE) 4089 #define G_CPL_RDMA_ATOMIC_RPL_OPCODE(x) \ 4090 (((x) >> S_CPL_RDMA_ATOMIC_RPL_OPCODE) & M_CPL_RDMA_ATOMIC_RPL_OPCODE) 4091 4092 #define S_CPL_RDMA_ATOMIC_RPL_SRQ 0 4093 #define M_CPL_RDMA_ATOMIC_RPL_SRQ 0xfff 4094 #define V_CPL_RDMA_ATOMIC_RPL_SRQ(x) ((x) << S_CPL_RDMA_ATOMIC_RPL_SRQ) 4095 #define G_CPL_RDMA_ATOMIC_RPL_SRQ(x) \ 4096 (((x) >> S_CPL_RDMA_ATOMIC_RPL_SRQ) & M_CPL_RDMA_ATOMIC_RPL_SRQ) 4097 4098 struct cpl_rdma_imm_data { 4099 RSS_HDR 4100 union opcode_tid ot; 4101 __be16 r; 4102 __be16 Length; 4103 }; 4104 4105 struct cpl_rdma_imm_data_se { 4106 RSS_HDR 4107 union opcode_tid ot; 4108 __be16 r; 4109 __be16 Length; 4110 }; 4111 4112 struct cpl_rdma_inv_req { 4113 WR_HDR; 4114 union opcode_tid ot; 4115 __be32 stag; 4116 __be32 cqid_pdid_hi; 4117 __be32 pdid_lo_qpid; 4118 }; 4119 4120 #define S_CPL_RDMA_INV_REQ_CQID 8 4121 #define M_CPL_RDMA_INV_REQ_CQID 0xfffff 4122 #define V_CPL_RDMA_INV_REQ_CQID(x) ((x) << S_CPL_RDMA_INV_REQ_CQID) 4123 #define G_CPL_RDMA_INV_REQ_CQID(x) \ 4124 (((x) >> S_CPL_RDMA_INV_REQ_CQID) & M_CPL_RDMA_INV_REQ_CQID) 4125 4126 #define S_CPL_RDMA_INV_REQ_PDID_HI 0 4127 #define M_CPL_RDMA_INV_REQ_PDID_HI 0xff 4128 #define V_CPL_RDMA_INV_REQ_PDID_HI(x) ((x) << S_CPL_RDMA_INV_REQ_PDID_HI) 4129 #define G_CPL_RDMA_INV_REQ_PDID_HI(x) \ 4130 (((x) >> S_CPL_RDMA_INV_REQ_PDID_HI) & M_CPL_RDMA_INV_REQ_PDID_HI) 4131 4132 #define S_CPL_RDMA_INV_REQ_PDID_LO 20 4133 #define M_CPL_RDMA_INV_REQ_PDID_LO 0xfff 4134 #define V_CPL_RDMA_INV_REQ_PDID_LO(x) ((x) << S_CPL_RDMA_INV_REQ_PDID_LO) 4135 #define G_CPL_RDMA_INV_REQ_PDID_LO(x) \ 4136 (((x) >> S_CPL_RDMA_INV_REQ_PDID_LO) & M_CPL_RDMA_INV_REQ_PDID_LO) 4137 4138 #define S_CPL_RDMA_INV_REQ_QPID 0 4139 #define M_CPL_RDMA_INV_REQ_QPID 0xfffff 4140 #define V_CPL_RDMA_INV_REQ_QPID(x) ((x) << S_CPL_RDMA_INV_REQ_QPID) 4141 #define G_CPL_RDMA_INV_REQ_QPID(x) \ 4142 (((x) >> S_CPL_RDMA_INV_REQ_QPID) & M_CPL_RDMA_INV_REQ_QPID) 4143 4144 struct cpl_rdma_cqe_ext { 4145 WR_HDR; 4146 union opcode_tid ot; 4147 __be32 tid_flitcnt; 4148 __be32 qpid_to_wr_type; 4149 __be32 length; 4150 __be32 tag; 4151 __be32 msn; 4152 __be32 se_to_srq; 4153 __be32 rqe; 4154 __be32 extinfoms[2]; 4155 __be32 extinfols[2]; 4156 }; 4157 4158 #define S_CPL_RDMA_CQE_EXT_RSSCTRL 16 4159 #define M_CPL_RDMA_CQE_EXT_RSSCTRL 0xff 4160 #define V_CPL_RDMA_CQE_EXT_RSSCTRL(x) ((x) << S_CPL_RDMA_CQE_EXT_RSSCTRL) 4161 #define G_CPL_RDMA_CQE_EXT_RSSCTRL(x) \ 4162 (((x) >> S_CPL_RDMA_CQE_EXT_RSSCTRL) & M_CPL_RDMA_CQE_EXT_RSSCTRL) 4163 4164 #define S_CPL_RDMA_CQE_EXT_CQID 0 4165 #define M_CPL_RDMA_CQE_EXT_CQID 0xffff 4166 #define V_CPL_RDMA_CQE_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_EXT_CQID) 4167 #define G_CPL_RDMA_CQE_EXT_CQID(x) \ 4168 (((x) >> S_CPL_RDMA_CQE_EXT_CQID) & M_CPL_RDMA_CQE_EXT_CQID) 4169 4170 #define S_CPL_RDMA_CQE_EXT_TID 8 4171 #define M_CPL_RDMA_CQE_EXT_TID 0xfffff 4172 #define V_CPL_RDMA_CQE_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_EXT_TID) 4173 #define G_CPL_RDMA_CQE_EXT_TID(x) \ 4174 (((x) >> S_CPL_RDMA_CQE_EXT_TID) & M_CPL_RDMA_CQE_EXT_TID) 4175 4176 #define S_CPL_RDMA_CQE_EXT_FLITCNT 0 4177 #define M_CPL_RDMA_CQE_EXT_FLITCNT 0xff 4178 #define V_CPL_RDMA_CQE_EXT_FLITCNT(x) ((x) << S_CPL_RDMA_CQE_EXT_FLITCNT) 4179 #define G_CPL_RDMA_CQE_EXT_FLITCNT(x) \ 4180 (((x) >> S_CPL_RDMA_CQE_EXT_FLITCNT) & M_CPL_RDMA_CQE_EXT_FLITCNT) 4181 4182 #define S_CPL_RDMA_CQE_EXT_QPID 12 4183 #define M_CPL_RDMA_CQE_EXT_QPID 0xfffff 4184 #define V_CPL_RDMA_CQE_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_EXT_QPID) 4185 #define G_CPL_RDMA_CQE_EXT_QPID(x) \ 4186 (((x) >> S_CPL_RDMA_CQE_EXT_QPID) & M_CPL_RDMA_CQE_EXT_QPID) 4187 4188 #define S_CPL_RDMA_CQE_EXT_GENERATION_BIT 10 4189 #define M_CPL_RDMA_CQE_EXT_GENERATION_BIT 0x1 4190 #define V_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \ 4191 ((x) << S_CPL_RDMA_CQE_EXT_GENERATION_BIT) 4192 #define G_CPL_RDMA_CQE_EXT_GENERATION_BIT(x) \ 4193 (((x) >> S_CPL_RDMA_CQE_EXT_GENERATION_BIT) & \ 4194 M_CPL_RDMA_CQE_EXT_GENERATION_BIT) 4195 #define F_CPL_RDMA_CQE_EXT_GENERATION_BIT \ 4196 V_CPL_RDMA_CQE_EXT_GENERATION_BIT(1U) 4197 4198 #define S_CPL_RDMA_CQE_EXT_STATUS 5 4199 #define M_CPL_RDMA_CQE_EXT_STATUS 0x1f 4200 #define V_CPL_RDMA_CQE_EXT_STATUS(x) ((x) << S_CPL_RDMA_CQE_EXT_STATUS) 4201 #define G_CPL_RDMA_CQE_EXT_STATUS(x) \ 4202 (((x) >> S_CPL_RDMA_CQE_EXT_STATUS) & M_CPL_RDMA_CQE_EXT_STATUS) 4203 4204 #define S_CPL_RDMA_CQE_EXT_CQE_TYPE 4 4205 #define M_CPL_RDMA_CQE_EXT_CQE_TYPE 0x1 4206 #define V_CPL_RDMA_CQE_EXT_CQE_TYPE(x) ((x) << S_CPL_RDMA_CQE_EXT_CQE_TYPE) 4207 #define G_CPL_RDMA_CQE_EXT_CQE_TYPE(x) \ 4208 (((x) >> S_CPL_RDMA_CQE_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_EXT_CQE_TYPE) 4209 #define F_CPL_RDMA_CQE_EXT_CQE_TYPE V_CPL_RDMA_CQE_EXT_CQE_TYPE(1U) 4210 4211 #define S_CPL_RDMA_CQE_EXT_WR_TYPE 0 4212 #define M_CPL_RDMA_CQE_EXT_WR_TYPE 0xf 4213 #define V_CPL_RDMA_CQE_EXT_WR_TYPE(x) ((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE) 4214 #define G_CPL_RDMA_CQE_EXT_WR_TYPE(x) \ 4215 (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE) & M_CPL_RDMA_CQE_EXT_WR_TYPE) 4216 4217 #define S_CPL_RDMA_CQE_EXT_SE 31 4218 #define M_CPL_RDMA_CQE_EXT_SE 0x1 4219 #define V_CPL_RDMA_CQE_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_EXT_SE) 4220 #define G_CPL_RDMA_CQE_EXT_SE(x) \ 4221 (((x) >> S_CPL_RDMA_CQE_EXT_SE) & M_CPL_RDMA_CQE_EXT_SE) 4222 #define F_CPL_RDMA_CQE_EXT_SE V_CPL_RDMA_CQE_EXT_SE(1U) 4223 4224 #define S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT 24 4225 #define M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT 0x7f 4226 #define V_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \ 4227 ((x) << S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) 4228 #define G_CPL_RDMA_CQE_EXT_WR_TYPE_EXT(x) \ 4229 (((x) >> S_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) & M_CPL_RDMA_CQE_EXT_WR_TYPE_EXT) 4230 4231 #define S_CPL_RDMA_CQE_EXT_EXTMODE 23 4232 #define M_CPL_RDMA_CQE_EXT_EXTMODE 0x1 4233 #define V_CPL_RDMA_CQE_EXT_EXTMODE(x) ((x) << S_CPL_RDMA_CQE_EXT_EXTMODE) 4234 #define G_CPL_RDMA_CQE_EXT_EXTMODE(x) \ 4235 (((x) >> S_CPL_RDMA_CQE_EXT_EXTMODE) & M_CPL_RDMA_CQE_EXT_EXTMODE) 4236 #define F_CPL_RDMA_CQE_EXT_EXTMODE V_CPL_RDMA_CQE_EXT_EXTMODE(1U) 4237 4238 #define S_CPL_RDMA_CQE_EXT_SRQ 0 4239 #define M_CPL_RDMA_CQE_EXT_SRQ 0xfff 4240 #define V_CPL_RDMA_CQE_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_EXT_SRQ) 4241 #define G_CPL_RDMA_CQE_EXT_SRQ(x) \ 4242 (((x) >> S_CPL_RDMA_CQE_EXT_SRQ) & M_CPL_RDMA_CQE_EXT_SRQ) 4243 4244 struct cpl_rdma_cqe_fw_ext { 4245 WR_HDR; 4246 union opcode_tid ot; 4247 __be32 tid_flitcnt; 4248 __be32 qpid_to_wr_type; 4249 __be32 length; 4250 __be32 tag; 4251 __be32 msn; 4252 __be32 se_to_srq; 4253 __be32 rqe; 4254 __be32 extinfoms[2]; 4255 __be32 extinfols[2]; 4256 }; 4257 4258 #define S_CPL_RDMA_CQE_FW_EXT_RSSCTRL 16 4259 #define M_CPL_RDMA_CQE_FW_EXT_RSSCTRL 0xff 4260 #define V_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \ 4261 ((x) << S_CPL_RDMA_CQE_FW_EXT_RSSCTRL) 4262 #define G_CPL_RDMA_CQE_FW_EXT_RSSCTRL(x) \ 4263 (((x) >> S_CPL_RDMA_CQE_FW_EXT_RSSCTRL) & M_CPL_RDMA_CQE_FW_EXT_RSSCTRL) 4264 4265 #define S_CPL_RDMA_CQE_FW_EXT_CQID 0 4266 #define M_CPL_RDMA_CQE_FW_EXT_CQID 0xffff 4267 #define V_CPL_RDMA_CQE_FW_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_CQID) 4268 #define G_CPL_RDMA_CQE_FW_EXT_CQID(x) \ 4269 (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQID) & M_CPL_RDMA_CQE_FW_EXT_CQID) 4270 4271 #define S_CPL_RDMA_CQE_FW_EXT_TID 8 4272 #define M_CPL_RDMA_CQE_FW_EXT_TID 0xfffff 4273 #define V_CPL_RDMA_CQE_FW_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_TID) 4274 #define G_CPL_RDMA_CQE_FW_EXT_TID(x) \ 4275 (((x) >> S_CPL_RDMA_CQE_FW_EXT_TID) & M_CPL_RDMA_CQE_FW_EXT_TID) 4276 4277 #define S_CPL_RDMA_CQE_FW_EXT_FLITCNT 0 4278 #define M_CPL_RDMA_CQE_FW_EXT_FLITCNT 0xff 4279 #define V_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \ 4280 ((x) << S_CPL_RDMA_CQE_FW_EXT_FLITCNT) 4281 #define G_CPL_RDMA_CQE_FW_EXT_FLITCNT(x) \ 4282 (((x) >> S_CPL_RDMA_CQE_FW_EXT_FLITCNT) & M_CPL_RDMA_CQE_FW_EXT_FLITCNT) 4283 4284 #define S_CPL_RDMA_CQE_FW_EXT_QPID 12 4285 #define M_CPL_RDMA_CQE_FW_EXT_QPID 0xfffff 4286 #define V_CPL_RDMA_CQE_FW_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_QPID) 4287 #define G_CPL_RDMA_CQE_FW_EXT_QPID(x) \ 4288 (((x) >> S_CPL_RDMA_CQE_FW_EXT_QPID) & M_CPL_RDMA_CQE_FW_EXT_QPID) 4289 4290 #define S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 10 4291 #define M_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT 0x1 4292 #define V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \ 4293 ((x) << S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) 4294 #define G_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(x) \ 4295 (((x) >> S_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) & \ 4296 M_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT) 4297 #define F_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT \ 4298 V_CPL_RDMA_CQE_FW_EXT_GENERATION_BIT(1U) 4299 4300 #define S_CPL_RDMA_CQE_FW_EXT_STATUS 5 4301 #define M_CPL_RDMA_CQE_FW_EXT_STATUS 0x1f 4302 #define V_CPL_RDMA_CQE_FW_EXT_STATUS(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_STATUS) 4303 #define G_CPL_RDMA_CQE_FW_EXT_STATUS(x) \ 4304 (((x) >> S_CPL_RDMA_CQE_FW_EXT_STATUS) & M_CPL_RDMA_CQE_FW_EXT_STATUS) 4305 4306 #define S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE 4 4307 #define M_CPL_RDMA_CQE_FW_EXT_CQE_TYPE 0x1 4308 #define V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \ 4309 ((x) << S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) 4310 #define G_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(x) \ 4311 (((x) >> S_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) & M_CPL_RDMA_CQE_FW_EXT_CQE_TYPE) 4312 #define F_CPL_RDMA_CQE_FW_EXT_CQE_TYPE V_CPL_RDMA_CQE_FW_EXT_CQE_TYPE(1U) 4313 4314 #define S_CPL_RDMA_CQE_FW_EXT_WR_TYPE 0 4315 #define M_CPL_RDMA_CQE_FW_EXT_WR_TYPE 0xf 4316 #define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \ 4317 ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE) 4318 #define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE(x) \ 4319 (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE) & M_CPL_RDMA_CQE_FW_EXT_WR_TYPE) 4320 4321 #define S_CPL_RDMA_CQE_FW_EXT_SE 31 4322 #define M_CPL_RDMA_CQE_FW_EXT_SE 0x1 4323 #define V_CPL_RDMA_CQE_FW_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_SE) 4324 #define G_CPL_RDMA_CQE_FW_EXT_SE(x) \ 4325 (((x) >> S_CPL_RDMA_CQE_FW_EXT_SE) & M_CPL_RDMA_CQE_FW_EXT_SE) 4326 #define F_CPL_RDMA_CQE_FW_EXT_SE V_CPL_RDMA_CQE_FW_EXT_SE(1U) 4327 4328 #define S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT 24 4329 #define M_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT 0x7f 4330 #define V_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \ 4331 ((x) << S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) 4332 #define G_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT(x) \ 4333 (((x) >> S_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) & \ 4334 M_CPL_RDMA_CQE_FW_EXT_WR_TYPE_EXT) 4335 4336 #define S_CPL_RDMA_CQE_FW_EXT_EXTMODE 23 4337 #define M_CPL_RDMA_CQE_FW_EXT_EXTMODE 0x1 4338 #define V_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ 4339 ((x) << S_CPL_RDMA_CQE_FW_EXT_EXTMODE) 4340 #define G_CPL_RDMA_CQE_FW_EXT_EXTMODE(x) \ 4341 (((x) >> S_CPL_RDMA_CQE_FW_EXT_EXTMODE) & M_CPL_RDMA_CQE_FW_EXT_EXTMODE) 4342 #define F_CPL_RDMA_CQE_FW_EXT_EXTMODE V_CPL_RDMA_CQE_FW_EXT_EXTMODE(1U) 4343 4344 #define S_CPL_RDMA_CQE_FW_EXT_SRQ 0 4345 #define M_CPL_RDMA_CQE_FW_EXT_SRQ 0xfff 4346 #define V_CPL_RDMA_CQE_FW_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_FW_EXT_SRQ) 4347 #define G_CPL_RDMA_CQE_FW_EXT_SRQ(x) \ 4348 (((x) >> S_CPL_RDMA_CQE_FW_EXT_SRQ) & M_CPL_RDMA_CQE_FW_EXT_SRQ) 4349 4350 struct cpl_rdma_cqe_err_ext { 4351 WR_HDR; 4352 union opcode_tid ot; 4353 __be32 tid_flitcnt; 4354 __be32 qpid_to_wr_type; 4355 __be32 length; 4356 __be32 tag; 4357 __be32 msn; 4358 __be32 se_to_srq; 4359 __be32 rqe; 4360 __be32 extinfoms[2]; 4361 __be32 extinfols[2]; 4362 }; 4363 4364 #define S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL 16 4365 #define M_CPL_RDMA_CQE_ERR_EXT_RSSCTRL 0xff 4366 #define V_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \ 4367 ((x) << S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) 4368 #define G_CPL_RDMA_CQE_ERR_EXT_RSSCTRL(x) \ 4369 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) & M_CPL_RDMA_CQE_ERR_EXT_RSSCTRL) 4370 4371 #define S_CPL_RDMA_CQE_ERR_EXT_CQID 0 4372 #define M_CPL_RDMA_CQE_ERR_EXT_CQID 0xffff 4373 #define V_CPL_RDMA_CQE_ERR_EXT_CQID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_CQID) 4374 #define G_CPL_RDMA_CQE_ERR_EXT_CQID(x) \ 4375 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQID) & M_CPL_RDMA_CQE_ERR_EXT_CQID) 4376 4377 #define S_CPL_RDMA_CQE_ERR_EXT_TID 8 4378 #define M_CPL_RDMA_CQE_ERR_EXT_TID 0xfffff 4379 #define V_CPL_RDMA_CQE_ERR_EXT_TID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_TID) 4380 #define G_CPL_RDMA_CQE_ERR_EXT_TID(x) \ 4381 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_TID) & M_CPL_RDMA_CQE_ERR_EXT_TID) 4382 4383 #define S_CPL_RDMA_CQE_ERR_EXT_FLITCNT 0 4384 #define M_CPL_RDMA_CQE_ERR_EXT_FLITCNT 0xff 4385 #define V_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \ 4386 ((x) << S_CPL_RDMA_CQE_ERR_EXT_FLITCNT) 4387 #define G_CPL_RDMA_CQE_ERR_EXT_FLITCNT(x) \ 4388 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_FLITCNT) & M_CPL_RDMA_CQE_ERR_EXT_FLITCNT) 4389 4390 #define S_CPL_RDMA_CQE_ERR_EXT_QPID 12 4391 #define M_CPL_RDMA_CQE_ERR_EXT_QPID 0xfffff 4392 #define V_CPL_RDMA_CQE_ERR_EXT_QPID(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_QPID) 4393 #define G_CPL_RDMA_CQE_ERR_EXT_QPID(x) \ 4394 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_QPID) & M_CPL_RDMA_CQE_ERR_EXT_QPID) 4395 4396 #define S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 10 4397 #define M_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT 0x1 4398 #define V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \ 4399 ((x) << S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) 4400 #define G_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(x) \ 4401 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) & \ 4402 M_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT) 4403 #define F_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT \ 4404 V_CPL_RDMA_CQE_ERR_EXT_GENERATION_BIT(1U) 4405 4406 #define S_CPL_RDMA_CQE_ERR_EXT_STATUS 5 4407 #define M_CPL_RDMA_CQE_ERR_EXT_STATUS 0x1f 4408 #define V_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \ 4409 ((x) << S_CPL_RDMA_CQE_ERR_EXT_STATUS) 4410 #define G_CPL_RDMA_CQE_ERR_EXT_STATUS(x) \ 4411 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_STATUS) & M_CPL_RDMA_CQE_ERR_EXT_STATUS) 4412 4413 #define S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE 4 4414 #define M_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE 0x1 4415 #define V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \ 4416 ((x) << S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) 4417 #define G_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(x) \ 4418 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) & \ 4419 M_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE) 4420 #define F_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE V_CPL_RDMA_CQE_ERR_EXT_CQE_TYPE(1U) 4421 4422 #define S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE 0 4423 #define M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE 0xf 4424 #define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \ 4425 ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) 4426 #define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE(x) \ 4427 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) & M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE) 4428 4429 #define S_CPL_RDMA_CQE_ERR_EXT_SE 31 4430 #define M_CPL_RDMA_CQE_ERR_EXT_SE 0x1 4431 #define V_CPL_RDMA_CQE_ERR_EXT_SE(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_SE) 4432 #define G_CPL_RDMA_CQE_ERR_EXT_SE(x) \ 4433 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SE) & M_CPL_RDMA_CQE_ERR_EXT_SE) 4434 #define F_CPL_RDMA_CQE_ERR_EXT_SE V_CPL_RDMA_CQE_ERR_EXT_SE(1U) 4435 4436 #define S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT 24 4437 #define M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT 0x7f 4438 #define V_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \ 4439 ((x) << S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) 4440 #define G_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT(x) \ 4441 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) & \ 4442 M_CPL_RDMA_CQE_ERR_EXT_WR_TYPE_EXT) 4443 4444 #define S_CPL_RDMA_CQE_ERR_EXT_EXTMODE 23 4445 #define M_CPL_RDMA_CQE_ERR_EXT_EXTMODE 0x1 4446 #define V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ 4447 ((x) << S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) 4448 #define G_CPL_RDMA_CQE_ERR_EXT_EXTMODE(x) \ 4449 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_EXTMODE) & M_CPL_RDMA_CQE_ERR_EXT_EXTMODE) 4450 #define F_CPL_RDMA_CQE_ERR_EXT_EXTMODE V_CPL_RDMA_CQE_ERR_EXT_EXTMODE(1U) 4451 4452 #define S_CPL_RDMA_CQE_ERR_EXT_SRQ 0 4453 #define M_CPL_RDMA_CQE_ERR_EXT_SRQ 0xfff 4454 #define V_CPL_RDMA_CQE_ERR_EXT_SRQ(x) ((x) << S_CPL_RDMA_CQE_ERR_EXT_SRQ) 4455 #define G_CPL_RDMA_CQE_ERR_EXT_SRQ(x) \ 4456 (((x) >> S_CPL_RDMA_CQE_ERR_EXT_SRQ) & M_CPL_RDMA_CQE_ERR_EXT_SRQ) 4457 4458 struct cpl_set_le_req { 4459 WR_HDR; 4460 union opcode_tid ot; 4461 __be16 reply_ctrl; 4462 __be16 params; 4463 __be64 mask_hi; 4464 __be64 mask_lo; 4465 __be64 val_hi; 4466 __be64 val_lo; 4467 }; 4468 4469 /* cpl_set_le_req.reply_ctrl additional fields */ 4470 #define S_LE_REQ_RXCHANNEL 14 4471 #define M_LE_REQ_RXCHANNEL 0x1 4472 #define V_LE_REQ_RXCHANNEL(x) ((x) << S_LE_REQ_RXCHANNEL) 4473 #define G_LE_REQ_RXCHANNEL(x) \ 4474 (((x) >> S_LE_REQ_RXCHANNEL) & M_LE_REQ_RXCHANNEL) 4475 #define F_LE_REQ_RXCHANNEL V_LE_REQ_RXCHANNEL(1U) 4476 4477 #define S_LE_REQ_IP6 13 4478 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 4479 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 4480 4481 /* cpl_set_le_req.params fields */ 4482 #define S_LE_CHAN 0 4483 #define M_LE_CHAN 0x3 4484 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 4485 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 4486 4487 #define S_LE_OFFSET 5 4488 #define M_LE_OFFSET 0x7 4489 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 4490 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 4491 4492 #define S_LE_MORE 8 4493 #define V_LE_MORE(x) ((x) << S_LE_MORE) 4494 #define F_LE_MORE V_LE_MORE(1U) 4495 4496 #define S_LE_REQSIZE 9 4497 #define M_LE_REQSIZE 0x7 4498 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 4499 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 4500 4501 #define S_LE_REQCMD 12 4502 #define M_LE_REQCMD 0xF 4503 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 4504 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 4505 4506 struct cpl_t7_set_le_req { 4507 WR_HDR; 4508 union opcode_tid ot; 4509 __be32 noreply_to_channel; 4510 __be32 mask1[2]; 4511 __be32 mask0[2]; 4512 __be32 value1[2]; 4513 __be32 value0[2]; 4514 }; 4515 4516 #define S_CPL_T7_SET_LE_REQ_INDEX 0 4517 #define M_CPL_T7_SET_LE_REQ_INDEX 0xffffff 4518 #define V_CPL_T7_SET_LE_REQ_INDEX(x) ((x) << S_CPL_T7_SET_LE_REQ_INDEX) 4519 #define G_CPL_T7_SET_LE_REQ_INDEX(x) \ 4520 (((x) >> S_CPL_T7_SET_LE_REQ_INDEX) & M_CPL_T7_SET_LE_REQ_INDEX) 4521 4522 #define S_CPL_T7_SET_LE_REQ_NOREPLY 31 4523 #define M_CPL_T7_SET_LE_REQ_NOREPLY 0x1 4524 #define V_CPL_T7_SET_LE_REQ_NOREPLY(x) ((x) << S_CPL_T7_SET_LE_REQ_NOREPLY) 4525 #define G_CPL_T7_SET_LE_REQ_NOREPLY(x) \ 4526 (((x) >> S_CPL_T7_SET_LE_REQ_NOREPLY) & M_CPL_T7_SET_LE_REQ_NOREPLY) 4527 #define F_CPL_T7_SET_LE_REQ_NOREPLY V_CPL_T7_SET_LE_REQ_NOREPLY(1U) 4528 4529 #define S_CPL_T7_SET_LE_REQ_RXCHANNEL 28 4530 #define M_CPL_T7_SET_LE_REQ_RXCHANNEL 0x7 4531 #define V_CPL_T7_SET_LE_REQ_RXCHANNEL(x) \ 4532 ((x) << S_CPL_T7_SET_LE_REQ_RXCHANNEL) 4533 #define G_CPL_T7_SET_LE_REQ_RXCHANNEL(x) \ 4534 (((x) >> S_CPL_T7_SET_LE_REQ_RXCHANNEL) & M_CPL_T7_SET_LE_REQ_RXCHANNEL) 4535 4536 #define S_CPL_T7_SET_LE_REQ_QUEUE 16 4537 #define M_CPL_T7_SET_LE_REQ_QUEUE 0xfff 4538 #define V_CPL_T7_SET_LE_REQ_QUEUE(x) ((x) << S_CPL_T7_SET_LE_REQ_QUEUE) 4539 #define G_CPL_T7_SET_LE_REQ_QUEUE(x) \ 4540 (((x) >> S_CPL_T7_SET_LE_REQ_QUEUE) & M_CPL_T7_SET_LE_REQ_QUEUE) 4541 4542 #define S_CPL_T7_SET_LE_REQ_REQCMD 12 4543 #define M_CPL_T7_SET_LE_REQ_REQCMD 0xf 4544 #define V_CPL_T7_SET_LE_REQ_REQCMD(x) ((x) << S_CPL_T7_SET_LE_REQ_REQCMD) 4545 #define G_CPL_T7_SET_LE_REQ_REQCMD(x) \ 4546 (((x) >> S_CPL_T7_SET_LE_REQ_REQCMD) & M_CPL_T7_SET_LE_REQ_REQCMD) 4547 4548 #define S_CPL_T7_SET_LE_REQ_REQSIZE 9 4549 #define M_CPL_T7_SET_LE_REQ_REQSIZE 0x7 4550 #define V_CPL_T7_SET_LE_REQ_REQSIZE(x) ((x) << S_CPL_T7_SET_LE_REQ_REQSIZE) 4551 #define G_CPL_T7_SET_LE_REQ_REQSIZE(x) \ 4552 (((x) >> S_CPL_T7_SET_LE_REQ_REQSIZE) & M_CPL_T7_SET_LE_REQ_REQSIZE) 4553 4554 #define S_CPL_T7_SET_LE_REQ_MORE 8 4555 #define M_CPL_T7_SET_LE_REQ_MORE 0x1 4556 #define V_CPL_T7_SET_LE_REQ_MORE(x) ((x) << S_CPL_T7_SET_LE_REQ_MORE) 4557 #define G_CPL_T7_SET_LE_REQ_MORE(x) \ 4558 (((x) >> S_CPL_T7_SET_LE_REQ_MORE) & M_CPL_T7_SET_LE_REQ_MORE) 4559 #define F_CPL_T7_SET_LE_REQ_MORE V_CPL_T7_SET_LE_REQ_MORE(1U) 4560 4561 #define S_CPL_T7_SET_LE_REQ_OFFSET 5 4562 #define M_CPL_T7_SET_LE_REQ_OFFSET 0x7 4563 #define V_CPL_T7_SET_LE_REQ_OFFSET(x) ((x) << S_CPL_T7_SET_LE_REQ_OFFSET) 4564 #define G_CPL_T7_SET_LE_REQ_OFFSET(x) \ 4565 (((x) >> S_CPL_T7_SET_LE_REQ_OFFSET) & M_CPL_T7_SET_LE_REQ_OFFSET) 4566 4567 #define S_CPL_T7_SET_LE_REQ_REQTYPE 4 4568 #define M_CPL_T7_SET_LE_REQ_REQTYPE 0x1 4569 #define V_CPL_T7_SET_LE_REQ_REQTYPE(x) ((x) << S_CPL_T7_SET_LE_REQ_REQTYPE) 4570 #define G_CPL_T7_SET_LE_REQ_REQTYPE(x) \ 4571 (((x) >> S_CPL_T7_SET_LE_REQ_REQTYPE) & M_CPL_T7_SET_LE_REQ_REQTYPE) 4572 #define F_CPL_T7_SET_LE_REQ_REQTYPE V_CPL_T7_SET_LE_REQ_REQTYPE(1U) 4573 4574 #define S_CPL_T7_SET_LE_REQ_CHANNEL 0 4575 #define M_CPL_T7_SET_LE_REQ_CHANNEL 0x3 4576 #define V_CPL_T7_SET_LE_REQ_CHANNEL(x) ((x) << S_CPL_T7_SET_LE_REQ_CHANNEL) 4577 #define G_CPL_T7_SET_LE_REQ_CHANNEL(x) \ 4578 (((x) >> S_CPL_T7_SET_LE_REQ_CHANNEL) & M_CPL_T7_SET_LE_REQ_CHANNEL) 4579 4580 struct cpl_set_le_rpl { 4581 RSS_HDR 4582 union opcode_tid ot; 4583 __u8 chan; 4584 __u8 info; 4585 __be16 len; 4586 }; 4587 4588 /* cpl_set_le_rpl.info fields */ 4589 #define S_LE_RSPCMD 0 4590 #define M_LE_RSPCMD 0xF 4591 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 4592 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 4593 4594 #define S_LE_RSPSIZE 4 4595 #define M_LE_RSPSIZE 0x7 4596 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 4597 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 4598 4599 #define S_LE_RSPTYPE 7 4600 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 4601 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 4602 4603 struct cpl_sge_egr_update { 4604 RSS_HDR 4605 __be32 opcode_qid; 4606 __be16 cidx; 4607 __be16 pidx; 4608 }; 4609 4610 /* cpl_sge_egr_update.ot fields */ 4611 #define S_AUTOEQU 22 4612 #define M_AUTOEQU 0x1 4613 #define V_AUTOEQU(x) ((x) << S_AUTOEQU) 4614 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 4615 4616 #define S_EGR_QID 0 4617 #define M_EGR_QID 0x1FFFF 4618 #define V_EGR_QID(x) ((x) << S_EGR_QID) 4619 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 4620 4621 /* cpl_fw*.type values */ 4622 enum { 4623 FW_TYPE_CMD_RPL = 0, 4624 FW_TYPE_WR_RPL = 1, 4625 FW_TYPE_CQE = 2, 4626 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 4627 FW_TYPE_RSSCPL = 4, 4628 FW_TYPE_WRERR_RPL = 5, 4629 FW_TYPE_PI_ERR = 6, 4630 FW_TYPE_TLS_KEY = 7, 4631 FW_TYPE_IPSEC_SA = 8, 4632 }; 4633 4634 struct cpl_fw2_pld { 4635 RSS_HDR 4636 u8 opcode; 4637 u8 rsvd[5]; 4638 __be16 len; 4639 }; 4640 4641 struct cpl_fw4_pld { 4642 RSS_HDR 4643 u8 opcode; 4644 u8 rsvd0[3]; 4645 u8 type; 4646 u8 rsvd1; 4647 __be16 len; 4648 __be64 data; 4649 __be64 rsvd2; 4650 }; 4651 4652 struct cpl_fw6_pld { 4653 RSS_HDR 4654 u8 opcode; 4655 u8 rsvd[5]; 4656 __be16 len; 4657 __be64 data[4]; 4658 }; 4659 4660 struct cpl_fw2_msg { 4661 RSS_HDR 4662 union opcode_info oi; 4663 }; 4664 4665 struct cpl_fw4_msg { 4666 RSS_HDR 4667 u8 opcode; 4668 u8 type; 4669 __be16 rsvd0; 4670 __be32 rsvd1; 4671 __be64 data[2]; 4672 }; 4673 4674 struct cpl_fw4_ack { 4675 RSS_HDR 4676 union opcode_tid ot; 4677 u8 credits; 4678 u8 rsvd0[2]; 4679 u8 flags; 4680 __be32 snd_nxt; 4681 __be32 snd_una; 4682 __be64 rsvd1; 4683 }; 4684 4685 enum { 4686 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 4687 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 4688 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 4689 }; 4690 4691 #define S_CPL_FW4_ACK_OPCODE 24 4692 #define M_CPL_FW4_ACK_OPCODE 0xff 4693 #define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE) 4694 #define G_CPL_FW4_ACK_OPCODE(x) \ 4695 (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE) 4696 4697 #define S_CPL_FW4_ACK_FLOWID 0 4698 #define M_CPL_FW4_ACK_FLOWID 0xffffff 4699 #define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID) 4700 #define G_CPL_FW4_ACK_FLOWID(x) \ 4701 (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID) 4702 4703 #define S_CPL_FW4_ACK_CR 24 4704 #define M_CPL_FW4_ACK_CR 0xff 4705 #define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR) 4706 #define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR) 4707 4708 #define S_CPL_FW4_ACK_SEQVAL 0 4709 #define M_CPL_FW4_ACK_SEQVAL 0x1 4710 #define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL) 4711 #define G_CPL_FW4_ACK_SEQVAL(x) \ 4712 (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL) 4713 #define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U) 4714 4715 struct cpl_fw6_msg { 4716 RSS_HDR 4717 u8 opcode; 4718 u8 type; 4719 __be16 rsvd0; 4720 __be32 rsvd1; 4721 __be64 data[4]; 4722 }; 4723 4724 /* cpl_fw6_msg.type values */ 4725 enum { 4726 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 4727 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 4728 FW6_TYPE_CQE = FW_TYPE_CQE, 4729 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 4730 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 4731 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 4732 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 4733 FW6_TYPE_TLS_KEY = FW_TYPE_TLS_KEY, 4734 FW6_TYPE_IPSEC_SA = FW_TYPE_IPSEC_SA, 4735 NUM_FW6_TYPES 4736 }; 4737 4738 struct cpl_fw6_msg_ofld_connection_wr_rpl { 4739 __u64 cookie; 4740 __be32 tid; /* or atid in case of active failure */ 4741 __u8 t_state; 4742 __u8 retval; 4743 __u8 rsvd[2]; 4744 }; 4745 4746 /* ULP_TX opcodes */ 4747 enum { 4748 ULP_TX_MEM_READ = 2, 4749 ULP_TX_MEM_WRITE = 3, 4750 ULP_TX_PKT = 4 4751 }; 4752 4753 enum { 4754 ULP_TX_SC_NOOP = 0x80, 4755 ULP_TX_SC_IMM = 0x81, 4756 ULP_TX_SC_DSGL = 0x82, 4757 ULP_TX_SC_ISGL = 0x83, 4758 ULP_TX_SC_PICTRL = 0x84, 4759 ULP_TX_SC_MEMRD = 0x86 4760 }; 4761 4762 #define S_ULPTX_CMD 24 4763 #define M_ULPTX_CMD 0xFF 4764 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 4765 4766 #define S_ULPTX_LEN16 0 4767 #define M_ULPTX_LEN16 0xFF 4768 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 4769 4770 #define S_ULP_TX_SC_MORE 23 4771 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 4772 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 4773 4774 struct ulptx_sge_pair { 4775 __be32 len[2]; 4776 __be64 addr[2]; 4777 }; 4778 4779 struct ulptx_sgl { 4780 __be32 cmd_nsge; 4781 __be32 len0; 4782 __be64 addr0; 4783 #if !(defined C99_NOT_SUPPORTED) 4784 struct ulptx_sge_pair sge[]; 4785 #endif 4786 }; 4787 4788 struct ulptx_isge { 4789 __be32 stag; 4790 __be32 len; 4791 __be64 target_ofst; 4792 }; 4793 4794 struct ulptx_isgl { 4795 __be32 cmd_nisge; 4796 __be32 rsvd; 4797 #if !(defined C99_NOT_SUPPORTED) 4798 struct ulptx_isge sge[]; 4799 #endif 4800 }; 4801 4802 struct ulptx_idata { 4803 __be32 cmd_more; 4804 __be32 len; 4805 }; 4806 4807 #define S_ULPTX_NSGE 0 4808 #define M_ULPTX_NSGE 0xFFFF 4809 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 4810 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 4811 4812 struct ulptx_sc_memrd { 4813 __be32 cmd_to_len; 4814 __be32 addr; 4815 }; 4816 4817 struct ulp_mem_io { 4818 WR_HDR; 4819 __be32 cmd; 4820 __be32 len16; /* command length */ 4821 __be32 dlen; /* data length in 32-byte units */ 4822 __be32 lock_addr; 4823 }; 4824 4825 /* additional ulp_mem_io.cmd fields */ 4826 #define S_ULP_MEMIO_ORDER 23 4827 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 4828 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 4829 4830 #define S_T5_ULP_MEMIO_IMM 23 4831 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 4832 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 4833 4834 #define S_T5_ULP_MEMIO_ORDER 22 4835 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 4836 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 4837 4838 #define S_T5_ULP_MEMIO_FID 4 4839 #define M_T5_ULP_MEMIO_FID 0x7ff 4840 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 4841 4842 /* ulp_mem_io.lock_addr fields */ 4843 #define S_ULP_MEMIO_ADDR 0 4844 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 4845 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 4846 4847 #define S_ULP_MEMIO_LOCK 31 4848 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 4849 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 4850 4851 /* ulp_mem_io.dlen fields */ 4852 #define S_ULP_MEMIO_DATA_LEN 0 4853 #define M_ULP_MEMIO_DATA_LEN 0x1F 4854 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 4855 4856 #define S_T7_ULP_MEMIO_DATA_LEN 0 4857 #define M_T7_ULP_MEMIO_DATA_LEN 0x7FF 4858 #define V_T7_ULP_MEMIO_DATA_LEN(x) ((x) << S_T7_ULP_MEMIO_DATA_LEN) 4859 4860 /* ULP_TXPKT field values */ 4861 enum { 4862 ULP_TXPKT_DEST_TP = 0, 4863 ULP_TXPKT_DEST_SGE, 4864 ULP_TXPKT_DEST_UP, 4865 ULP_TXPKT_DEST_DEVNULL, 4866 }; 4867 4868 struct ulp_txpkt { 4869 __be32 cmd_dest; 4870 __be32 len; 4871 }; 4872 4873 /* ulp_txpkt.cmd_dest fields */ 4874 #define S_ULP_TXPKT_DATAMODIFY 23 4875 #define M_ULP_TXPKT_DATAMODIFY 0x1 4876 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 4877 #define G_ULP_TXPKT_DATAMODIFY(x) \ 4878 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 4879 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 4880 4881 #define S_ULP_TXPKT_CHANNELID 22 4882 #define M_ULP_TXPKT_CHANNELID 0x1 4883 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 4884 #define G_ULP_TXPKT_CHANNELID(x) \ 4885 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 4886 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 4887 4888 #define S_T7_ULP_TXPKT_CHANNELID 22 4889 #define M_T7_ULP_TXPKT_CHANNELID 0x3 4890 #define V_T7_ULP_TXPKT_CHANNELID(x) ((x) << S_T7_ULP_TXPKT_CHANNELID) 4891 #define G_T7_ULP_TXPKT_CHANNELID(x) \ 4892 (((x) >> S_T7_ULP_TXPKT_CHANNELID) & M_T7_ULP_TXPKT_CHANNELID) 4893 #define F_T7_ULP_TXPKT_CHANNELID V_T7_ULP_TXPKT_CHANNELID(1U) 4894 4895 /* ulp_txpkt.cmd_dest fields */ 4896 #define S_ULP_TXPKT_DEST 16 4897 #define M_ULP_TXPKT_DEST 0x3 4898 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 4899 4900 #define S_ULP_TXPKT_CMDMORE 15 4901 #define M_ULP_TXPKT_CMDMORE 0x1 4902 #define V_ULP_TXPKT_CMDMORE(x) ((x) << S_ULP_TXPKT_CMDMORE) 4903 #define G_ULP_TXPKT_CMDMORE(x) \ 4904 (((x) >> S_ULP_TXPKT_CMDMORE) & M_ULP_TXPKT_CMDMORE) 4905 #define F_ULP_TXPKT_CMDMORE V_ULP_TXPKT_CMDMORE(1U) 4906 4907 #define S_ULP_TXPKT_FID 4 4908 #define M_ULP_TXPKT_FID 0x7ff 4909 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 4910 4911 #define S_ULP_TXPKT_RO 3 4912 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 4913 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 4914 4915 enum cpl_tx_tnl_lso_type { 4916 TX_TNL_TYPE_OPAQUE, 4917 TX_TNL_TYPE_NVGRE, 4918 TX_TNL_TYPE_VXLAN, 4919 TX_TNL_TYPE_GENEVE, 4920 TX_TNL_TYPE_IPSEC, 4921 }; 4922 4923 struct cpl_tx_tnl_lso { 4924 __be32 op_to_IpIdSplitOut; 4925 __be16 IpIdOffsetOut; 4926 __be16 UdpLenSetOut_to_TnlHdrLen; 4927 __be32 ipsecen_to_rocev2; 4928 __be32 roce_eth; 4929 __be32 Flow_to_TcpHdrLen; 4930 __be16 IpIdOffset; 4931 __be16 IpIdSplit_to_Mss; 4932 __be32 TCPSeqOffset; 4933 __be32 EthLenOffset_Size; 4934 /* encapsulated CPL (TX_PKT_XT) follows here */ 4935 }; 4936 4937 #define S_CPL_TX_TNL_LSO_OPCODE 24 4938 #define M_CPL_TX_TNL_LSO_OPCODE 0xff 4939 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 4940 #define G_CPL_TX_TNL_LSO_OPCODE(x) \ 4941 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 4942 4943 #define S_CPL_TX_TNL_LSO_FIRST 23 4944 #define M_CPL_TX_TNL_LSO_FIRST 0x1 4945 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 4946 #define G_CPL_TX_TNL_LSO_FIRST(x) \ 4947 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 4948 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 4949 4950 #define S_CPL_TX_TNL_LSO_LAST 22 4951 #define M_CPL_TX_TNL_LSO_LAST 0x1 4952 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 4953 #define G_CPL_TX_TNL_LSO_LAST(x) \ 4954 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 4955 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 4956 4957 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 4958 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 4959 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 4960 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 4961 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 4962 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 4963 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 4964 4965 #define S_CPL_TX_TNL_LSO_IPV6OUT 20 4966 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 4967 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 4968 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 4969 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 4970 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 4971 4972 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 4973 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 4974 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 4975 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 4976 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 4977 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 4978 4979 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 4980 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 4981 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 4982 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 4983 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 4984 4985 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 4986 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 4987 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 4988 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 4989 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 4990 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 4991 4992 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 4993 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 4994 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 4995 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 4996 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 4997 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 4998 4999 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 5000 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 5001 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 5002 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 5003 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 5004 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 5005 5006 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 5007 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 5008 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 5009 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 5010 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 5011 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 5012 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 5013 5014 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 5015 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 5016 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 5017 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 5018 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 5019 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 5020 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 5021 5022 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 5023 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 5024 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 5025 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 5026 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 5027 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 5028 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 5029 5030 #define S_CPL_TX_TNL_LSO_TNLTYPE 12 5031 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 5032 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 5033 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 5034 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 5035 5036 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 5037 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 5038 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 5039 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 5040 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 5041 5042 #define S_CPL_TX_TNL_LSO_IPSECEN 31 5043 #define M_CPL_TX_TNL_LSO_IPSECEN 0x1 5044 #define V_CPL_TX_TNL_LSO_IPSECEN(x) ((x) << S_CPL_TX_TNL_LSO_IPSECEN) 5045 #define G_CPL_TX_TNL_LSO_IPSECEN(x) \ 5046 (((x) >> S_CPL_TX_TNL_LSO_IPSECEN) & M_CPL_TX_TNL_LSO_IPSECEN) 5047 #define F_CPL_TX_TNL_LSO_IPSECEN V_CPL_TX_TNL_LSO_IPSECEN(1U) 5048 5049 #define S_CPL_TX_TNL_LSO_ENCAPDIS 30 5050 #define M_CPL_TX_TNL_LSO_ENCAPDIS 0x1 5051 #define V_CPL_TX_TNL_LSO_ENCAPDIS(x) ((x) << S_CPL_TX_TNL_LSO_ENCAPDIS) 5052 #define G_CPL_TX_TNL_LSO_ENCAPDIS(x) \ 5053 (((x) >> S_CPL_TX_TNL_LSO_ENCAPDIS) & M_CPL_TX_TNL_LSO_ENCAPDIS) 5054 #define F_CPL_TX_TNL_LSO_ENCAPDIS V_CPL_TX_TNL_LSO_ENCAPDIS(1U) 5055 5056 #define S_CPL_TX_TNL_LSO_IPSECMODE 29 5057 #define M_CPL_TX_TNL_LSO_IPSECMODE 0x1 5058 #define V_CPL_TX_TNL_LSO_IPSECMODE(x) ((x) << S_CPL_TX_TNL_LSO_IPSECMODE) 5059 #define G_CPL_TX_TNL_LSO_IPSECMODE(x) \ 5060 (((x) >> S_CPL_TX_TNL_LSO_IPSECMODE) & M_CPL_TX_TNL_LSO_IPSECMODE) 5061 #define F_CPL_TX_TNL_LSO_IPSECMODE V_CPL_TX_TNL_LSO_IPSECMODE(1U) 5062 5063 #define S_CPL_TX_TNL_LSO_IPSECTNLIPV6 28 5064 #define M_CPL_TX_TNL_LSO_IPSECTNLIPV6 0x1 5065 #define V_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \ 5066 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPV6) 5067 #define G_CPL_TX_TNL_LSO_IPSECTNLIPV6(x) \ 5068 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPV6) & M_CPL_TX_TNL_LSO_IPSECTNLIPV6) 5069 #define F_CPL_TX_TNL_LSO_IPSECTNLIPV6 V_CPL_TX_TNL_LSO_IPSECTNLIPV6(1U) 5070 5071 #define S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN 20 5072 #define M_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN 0xff 5073 #define V_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \ 5074 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) 5075 #define G_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN(x) \ 5076 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) & \ 5077 M_CPL_TX_TNL_LSO_IPSECTNLIPHDRLEN) 5078 5079 #define S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT 19 5080 #define M_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT 0x1 5081 #define V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \ 5082 ((x) << S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) 5083 #define G_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(x) \ 5084 (((x) >> S_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) & \ 5085 M_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT) 5086 #define F_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT \ 5087 V_CPL_TX_TNL_LSO_IPSECTNLIPIDSPLIT(1U) 5088 5089 #define S_CPL_TX_TNL_LSO_ROCEV2 18 5090 #define M_CPL_TX_TNL_LSO_ROCEV2 0x1 5091 #define V_CPL_TX_TNL_LSO_ROCEV2(x) ((x) << S_CPL_TX_TNL_LSO_ROCEV2) 5092 #define G_CPL_TX_TNL_LSO_ROCEV2(x) \ 5093 (((x) >> S_CPL_TX_TNL_LSO_ROCEV2) & M_CPL_TX_TNL_LSO_ROCEV2) 5094 #define F_CPL_TX_TNL_LSO_ROCEV2 V_CPL_TX_TNL_LSO_ROCEV2(1U) 5095 5096 #define S_CPL_TX_TNL_LSO_UDPCHKUPDOUT 17 5097 #define M_CPL_TX_TNL_LSO_UDPCHKUPDOUT 0x1 5098 #define V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \ 5099 ((x) << S_CPL_TX_TNL_LSO_UDPCHKUPDOUT) 5100 #define G_CPL_TX_TNL_LSO_UDPCHKUPDOUT(x) \ 5101 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKUPDOUT) & M_CPL_TX_TNL_LSO_UDPCHKUPDOUT) 5102 #define F_CPL_TX_TNL_LSO_UDPCHKUPDOUT V_CPL_TX_TNL_LSO_UDPCHKUPDOUT(1U) 5103 5104 #define S_CPL_TX_TNL_LSO_FLOW 21 5105 #define M_CPL_TX_TNL_LSO_FLOW 0x1 5106 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 5107 #define G_CPL_TX_TNL_LSO_FLOW(x) \ 5108 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 5109 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 5110 5111 #define S_CPL_TX_TNL_LSO_IPV6 20 5112 #define M_CPL_TX_TNL_LSO_IPV6 0x1 5113 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 5114 #define G_CPL_TX_TNL_LSO_IPV6(x) \ 5115 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 5116 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 5117 5118 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 5119 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 5120 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 5121 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 5122 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 5123 5124 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4 5125 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 5126 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 5127 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 5128 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 5129 5130 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 5131 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 5132 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 5133 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 5134 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 5135 5136 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 5137 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 5138 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 5139 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 5140 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 5141 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 5142 5143 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 5144 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 5145 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 5146 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 5147 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 5148 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 5149 5150 #define S_CPL_TX_TNL_LSO_MSS 0 5151 #define M_CPL_TX_TNL_LSO_MSS 0x3fff 5152 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 5153 #define G_CPL_TX_TNL_LSO_MSS(x) \ 5154 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 5155 5156 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 5157 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 5158 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 5159 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 5160 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 5161 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 5162 5163 #define S_CPL_TX_TNL_LSO_SIZE 0 5164 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 5165 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 5166 #define G_CPL_TX_TNL_LSO_SIZE(x) \ 5167 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 5168 5169 #define S_CPL_TX_TNL_LSO_BTH_OPCODE 24 5170 #define M_CPL_TX_TNL_LSO_BTH_OPCODE 0xff 5171 #define V_CPL_TX_TNL_LSO_BTH_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_BTH_OPCODE) 5172 #define G_CPL_TX_TNL_LSO_BTH_OPCODE(x) \ 5173 (((x) >> S_CPL_TX_TNL_LSO_BTH_OPCODE) & \ 5174 M_CPL_TX_TNL_LSO_BTH_OPCODE) 5175 5176 #define S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0 5177 #define M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN 0xffffff 5178 #define V_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ 5179 ((x) << S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) 5180 #define G_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN(x) \ 5181 (((x) >> S_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) & \ 5182 M_CPL_TX_TNL_LSO_TCPSEQOFFSET_PSN) 5183 5184 #define S_CPL_TX_TNL_LSO_MSS_TVER 8 5185 #define M_CPL_TX_TNL_LSO_MSS_TVER 0xf 5186 #define V_CPL_TX_TNL_LSO_MSS_TVER(x) ((x) << S_CPL_TX_TNL_LSO_MSS_TVER) 5187 #define G_CPL_TX_TNL_LSO_MSS_TVER(x) \ 5188 (((x) >> S_CPL_TX_TNL_LSO_MSS_TVER) & M_CPL_TX_TNL_LSO_MSS_TVER) 5189 5190 #define S_CPL_TX_TNL_LSO_MSS_M 7 5191 #define M_CPL_TX_TNL_LSO_MSS_M 0x1 5192 #define V_CPL_TX_TNL_LSO_MSS_M(x) ((x) << S_CPL_TX_TNL_LSO_MSS_M) 5193 #define G_CPL_TX_TNL_LSO_MSS_M(x) \ 5194 (((x) >> S_CPL_TX_TNL_LSO_MSS_M) & M_CPL_TX_TNL_LSO_MSS_M) 5195 5196 #define S_CPL_TX_TNL_LSO_MSS_PMTU 4 5197 #define M_CPL_TX_TNL_LSO_MSS_PMTU 0x7 5198 #define V_CPL_TX_TNL_LSO_MSS_PMTU(x) ((x) << S_CPL_TX_TNL_LSO_MSS_PMTU) 5199 #define G_CPL_TX_TNL_LSO_MSS_PMTU(x) \ 5200 (((x) >> S_CPL_TX_TNL_LSO_MSS_PMTU) & M_CPL_TX_TNL_LSO_MSS_PMTU) 5201 5202 #define S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 3 5203 #define M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR 0x1 5204 #define V_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ 5205 ((x) << S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) 5206 #define G_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR(x) \ 5207 (((x) >> S_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) & M_CPL_TX_TNL_LSO_MSS_RR_MSN_INCR) 5208 5209 #define S_CPL_TX_TNL_LSO_MSS_ACKREQ 1 5210 #define M_CPL_TX_TNL_LSO_MSS_ACKREQ 0x3 5211 #define V_CPL_TX_TNL_LSO_MSS_ACKREQ(x) ((x) << S_CPL_TX_TNL_LSO_MSS_ACKREQ) 5212 #define G_CPL_TX_TNL_LSO_MSS_ACKREQ(x) \ 5213 (((x) >> S_CPL_TX_TNL_LSO_MSS_ACKREQ) & M_CPL_TX_TNL_LSO_MSS_ACKREQ) 5214 5215 #define S_CPL_TX_TNL_LSO_MSS_SE 0 5216 #define M_CPL_TX_TNL_LSO_MSS_SE 0x1 5217 #define V_CPL_TX_TNL_LSO_MSS_SE(x) ((x) << S_CPL_TX_TNL_LSO_MSS_SE) 5218 #define G_CPL_TX_TNL_LSO_MSS_SE(x) \ 5219 (((x) >> S_CPL_TX_TNL_LSO_MSS_SE) & M_CPL_TX_TNL_LSO_MSS_SE) 5220 5221 struct cpl_rx_mps_pkt { 5222 __be32 op_to_r1_hi; 5223 __be32 r1_lo_length; 5224 }; 5225 5226 #define S_CPL_RX_MPS_PKT_OP 24 5227 #define M_CPL_RX_MPS_PKT_OP 0xff 5228 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 5229 #define G_CPL_RX_MPS_PKT_OP(x) \ 5230 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 5231 5232 #define S_CPL_RX_MPS_PKT_TYPE 20 5233 #define M_CPL_RX_MPS_PKT_TYPE 0xf 5234 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 5235 #define G_CPL_RX_MPS_PKT_TYPE(x) \ 5236 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 5237 5238 #define S_CPL_RX_MPS_PKT_LENGTH 0 5239 #define M_CPL_RX_MPS_PKT_LENGTH 0xffff 5240 #define V_CPL_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_RX_MPS_PKT_LENGTH) 5241 #define G_CPL_RX_MPS_PKT_LENGTH(x) \ 5242 (((x) >> S_CPL_RX_MPS_PKT_LENGTH) & M_CPL_RX_MPS_PKT_LENGTH) 5243 5244 /* 5245 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 5246 */ 5247 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 5248 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 5249 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 5250 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 5251 5252 struct cpl_t7_rx_mps_pkt { 5253 RSS_HDR 5254 union opcode_tid ot; 5255 __be32 length_pkd; 5256 }; 5257 5258 #define S_CPL_T7_RX_MPS_PKT_TYPE 20 5259 #define M_CPL_T7_RX_MPS_PKT_TYPE 0xf 5260 #define V_CPL_T7_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_T7_RX_MPS_PKT_TYPE) 5261 #define G_CPL_T7_RX_MPS_PKT_TYPE(x) \ 5262 (((x) >> S_CPL_T7_RX_MPS_PKT_TYPE) & M_CPL_T7_RX_MPS_PKT_TYPE) 5263 5264 #define S_CPL_T7_RX_MPS_PKT_INTERFACE 16 5265 #define M_CPL_T7_RX_MPS_PKT_INTERFACE 0xf 5266 #define V_CPL_T7_RX_MPS_PKT_INTERFACE(x) \ 5267 ((x) << S_CPL_T7_RX_MPS_PKT_INTERFACE) 5268 #define G_CPL_T7_RX_MPS_PKT_INTERFACE(x) \ 5269 (((x) >> S_CPL_T7_RX_MPS_PKT_INTERFACE) & M_CPL_T7_RX_MPS_PKT_INTERFACE) 5270 5271 #define S_CPL_T7_RX_MPS_PKT_TRUNCATED 7 5272 #define M_CPL_T7_RX_MPS_PKT_TRUNCATED 0x1 5273 #define V_CPL_T7_RX_MPS_PKT_TRUNCATED(x) \ 5274 ((x) << S_CPL_T7_RX_MPS_PKT_TRUNCATED) 5275 #define G_CPL_T7_RX_MPS_PKT_TRUNCATED(x) \ 5276 (((x) >> S_CPL_T7_RX_MPS_PKT_TRUNCATED) & M_CPL_T7_RX_MPS_PKT_TRUNCATED) 5277 #define F_CPL_T7_RX_MPS_PKT_TRUNCATED V_CPL_T7_RX_MPS_PKT_TRUNCATED(1U) 5278 5279 #define S_CPL_T7_RX_MPS_PKT_PKTERR 6 5280 #define M_CPL_T7_RX_MPS_PKT_PKTERR 0x1 5281 #define V_CPL_T7_RX_MPS_PKT_PKTERR(x) ((x) << S_CPL_T7_RX_MPS_PKT_PKTERR) 5282 #define G_CPL_T7_RX_MPS_PKT_PKTERR(x) \ 5283 (((x) >> S_CPL_T7_RX_MPS_PKT_PKTERR) & M_CPL_T7_RX_MPS_PKT_PKTERR) 5284 #define F_CPL_T7_RX_MPS_PKT_PKTERR V_CPL_T7_RX_MPS_PKT_PKTERR(1U) 5285 5286 #define S_CPL_T7_RX_MPS_PKT_LENGTH 0 5287 #define M_CPL_T7_RX_MPS_PKT_LENGTH 0xffff 5288 #define V_CPL_T7_RX_MPS_PKT_LENGTH(x) ((x) << S_CPL_T7_RX_MPS_PKT_LENGTH) 5289 #define G_CPL_T7_RX_MPS_PKT_LENGTH(x) \ 5290 (((x) >> S_CPL_T7_RX_MPS_PKT_LENGTH) & M_CPL_T7_RX_MPS_PKT_LENGTH) 5291 5292 struct cpl_tx_tls_pdu { 5293 WR_HDR; 5294 union opcode_tid ot; 5295 __be32 pldlen_pkd; 5296 __be32 customtype_customprotover; 5297 __be32 r2_lo; 5298 __be32 scmd0[2]; 5299 __be32 scmd1[2]; 5300 }; 5301 5302 #define S_CPL_TX_TLS_PDU_DATATYPE 20 5303 #define M_CPL_TX_TLS_PDU_DATATYPE 0xf 5304 #define V_CPL_TX_TLS_PDU_DATATYPE(x) ((x) << S_CPL_TX_TLS_PDU_DATATYPE) 5305 #define G_CPL_TX_TLS_PDU_DATATYPE(x) \ 5306 (((x) >> S_CPL_TX_TLS_PDU_DATATYPE) & M_CPL_TX_TLS_PDU_DATATYPE) 5307 5308 #define S_CPL_TX_TLS_PDU_CPLLEN 16 5309 #define M_CPL_TX_TLS_PDU_CPLLEN 0xf 5310 #define V_CPL_TX_TLS_PDU_CPLLEN(x) ((x) << S_CPL_TX_TLS_PDU_CPLLEN) 5311 #define G_CPL_TX_TLS_PDU_CPLLEN(x) \ 5312 (((x) >> S_CPL_TX_TLS_PDU_CPLLEN) & M_CPL_TX_TLS_PDU_CPLLEN) 5313 5314 #define S_CPL_TX_TLS_PDU_PLDLEN 0 5315 #define M_CPL_TX_TLS_PDU_PLDLEN 0xfffff 5316 #define V_CPL_TX_TLS_PDU_PLDLEN(x) ((x) << S_CPL_TX_TLS_PDU_PLDLEN) 5317 #define G_CPL_TX_TLS_PDU_PLDLEN(x) \ 5318 (((x) >> S_CPL_TX_TLS_PDU_PLDLEN) & M_CPL_TX_TLS_PDU_PLDLEN) 5319 5320 #define S_CPL_TX_TLS_PDU_CUSTOMTYPE 24 5321 #define M_CPL_TX_TLS_PDU_CUSTOMTYPE 0xff 5322 #define V_CPL_TX_TLS_PDU_CUSTOMTYPE(x) ((x) << S_CPL_TX_TLS_PDU_CUSTOMTYPE) 5323 #define G_CPL_TX_TLS_PDU_CUSTOMTYPE(x) \ 5324 (((x) >> S_CPL_TX_TLS_PDU_CUSTOMTYPE) & M_CPL_TX_TLS_PDU_CUSTOMTYPE) 5325 5326 #define S_CPL_TX_TLS_PDU_CUSTOMPROTOVER 8 5327 #define M_CPL_TX_TLS_PDU_CUSTOMPROTOVER 0xffff 5328 #define V_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \ 5329 ((x) << S_CPL_TX_TLS_PDU_CUSTOMPROTOVER) 5330 #define G_CPL_TX_TLS_PDU_CUSTOMPROTOVER(x) \ 5331 (((x) >> S_CPL_TX_TLS_PDU_CUSTOMPROTOVER) & \ 5332 M_CPL_TX_TLS_PDU_CUSTOMPROTOVER) 5333 5334 struct cpl_tx_tls_sfo { 5335 __be32 op_to_seg_len; 5336 __be32 pld_len; 5337 __be32 type_protover; 5338 __be32 r1_lo; 5339 __be32 seqno_numivs; 5340 __be32 ivgen_hdrlen; 5341 __be64 scmd1; 5342 }; 5343 5344 /* cpl_tx_tls_sfo macros */ 5345 #define S_CPL_TX_TLS_SFO_OPCODE 24 5346 #define M_CPL_TX_TLS_SFO_OPCODE 0xff 5347 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 5348 #define G_CPL_TX_TLS_SFO_OPCODE(x) \ 5349 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 5350 5351 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20 5352 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 5353 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 5354 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 5355 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 5356 5357 #define S_CPL_TX_TLS_SFO_CPL_LEN 16 5358 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 5359 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 5360 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 5361 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 5362 5363 #define S_CPL_TX_TLS_SFO_SEG_LEN 0 5364 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 5365 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 5366 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 5367 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 5368 5369 #define S_CPL_TX_TLS_SFO_PLDLEN 0 5370 #define M_CPL_TX_TLS_SFO_PLDLEN 0xfffff 5371 #define V_CPL_TX_TLS_SFO_PLDLEN(x) ((x) << S_CPL_TX_TLS_SFO_PLDLEN) 5372 #define G_CPL_TX_TLS_SFO_PLDLEN(x) \ 5373 (((x) >> S_CPL_TX_TLS_SFO_PLDLEN) & M_CPL_TX_TLS_SFO_PLDLEN) 5374 5375 #define S_CPL_TX_TLS_SFO_TYPE 24 5376 #define M_CPL_TX_TLS_SFO_TYPE 0xff 5377 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE) 5378 #define G_CPL_TX_TLS_SFO_TYPE(x) \ 5379 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE) 5380 5381 #define S_CPL_TX_TLS_SFO_PROTOVER 8 5382 #define M_CPL_TX_TLS_SFO_PROTOVER 0xffff 5383 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER) 5384 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \ 5385 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER) 5386 5387 struct cpl_tls_data { 5388 RSS_HDR 5389 union opcode_tid ot; 5390 __be32 length_pkd; 5391 __be32 seq; 5392 __be32 r1; 5393 }; 5394 5395 #define S_CPL_TLS_DATA_OPCODE 24 5396 #define M_CPL_TLS_DATA_OPCODE 0xff 5397 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 5398 #define G_CPL_TLS_DATA_OPCODE(x) \ 5399 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 5400 5401 #define S_CPL_TLS_DATA_TID 0 5402 #define M_CPL_TLS_DATA_TID 0xffffff 5403 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 5404 #define G_CPL_TLS_DATA_TID(x) \ 5405 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 5406 5407 #define S_CPL_TLS_DATA_LENGTH 0 5408 #define M_CPL_TLS_DATA_LENGTH 0xffff 5409 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 5410 #define G_CPL_TLS_DATA_LENGTH(x) \ 5411 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 5412 5413 struct cpl_rx_tls_cmp { 5414 RSS_HDR 5415 union opcode_tid ot; 5416 __be32 pdulength_length; 5417 __be32 seq; 5418 __be32 ddp_report; 5419 __be32 r; 5420 __be32 ddp_valid; 5421 }; 5422 5423 #define S_CPL_RX_TLS_CMP_OPCODE 24 5424 #define M_CPL_RX_TLS_CMP_OPCODE 0xff 5425 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 5426 #define G_CPL_RX_TLS_CMP_OPCODE(x) \ 5427 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 5428 5429 #define S_CPL_RX_TLS_CMP_TID 0 5430 #define M_CPL_RX_TLS_CMP_TID 0xffffff 5431 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 5432 #define G_CPL_RX_TLS_CMP_TID(x) \ 5433 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 5434 5435 #define S_CPL_RX_TLS_CMP_PDULENGTH 16 5436 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 5437 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 5438 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 5439 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 5440 5441 #define S_CPL_RX_TLS_CMP_LENGTH 0 5442 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff 5443 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 5444 #define G_CPL_RX_TLS_CMP_LENGTH(x) \ 5445 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 5446 5447 #define S_SCMD_SEQ_NO_CTRL 29 5448 #define M_SCMD_SEQ_NO_CTRL 0x3 5449 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 5450 #define G_SCMD_SEQ_NO_CTRL(x) \ 5451 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 5452 5453 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 5454 #define S_SCMD_STATUS_PRESENT 28 5455 #define M_SCMD_STATUS_PRESENT 0x1 5456 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 5457 #define G_SCMD_STATUS_PRESENT(x) \ 5458 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 5459 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 5460 5461 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 5462 * 3-15: Reserved. */ 5463 #define S_SCMD_PROTO_VERSION 24 5464 #define M_SCMD_PROTO_VERSION 0xf 5465 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 5466 #define G_SCMD_PROTO_VERSION(x) \ 5467 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 5468 5469 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 5470 #define S_SCMD_ENC_DEC_CTRL 23 5471 #define M_SCMD_ENC_DEC_CTRL 0x1 5472 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 5473 #define G_SCMD_ENC_DEC_CTRL(x) \ 5474 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 5475 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 5476 5477 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 5478 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 5479 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 5480 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 5481 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 5482 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 5483 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 5484 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 5485 5486 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 5487 * 4:Generic-AES, 5-15: Reserved. */ 5488 #define S_SCMD_CIPH_MODE 18 5489 #define M_SCMD_CIPH_MODE 0xf 5490 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 5491 #define G_SCMD_CIPH_MODE(x) \ 5492 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 5493 5494 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 5495 * 4-15: Reserved */ 5496 #define S_SCMD_AUTH_MODE 14 5497 #define M_SCMD_AUTH_MODE 0xf 5498 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 5499 #define G_SCMD_AUTH_MODE(x) \ 5500 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 5501 5502 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 5503 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 5504 */ 5505 #define S_SCMD_HMAC_CTRL 11 5506 #define M_SCMD_HMAC_CTRL 0x7 5507 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 5508 #define G_SCMD_HMAC_CTRL(x) \ 5509 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 5510 5511 /* IvSize - IV size in units of 2 bytes */ 5512 #define S_SCMD_IV_SIZE 7 5513 #define M_SCMD_IV_SIZE 0xf 5514 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 5515 #define G_SCMD_IV_SIZE(x) \ 5516 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 5517 5518 /* NumIVs - Number of IVs */ 5519 #define S_SCMD_NUM_IVS 0 5520 #define M_SCMD_NUM_IVS 0x7f 5521 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 5522 #define G_SCMD_NUM_IVS(x) \ 5523 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 5524 5525 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 5526 * (below) are used as Cid (connection id for debug status), these 5527 * bits are padded to zero for forming the 64 bit 5528 * sequence number for TLS 5529 */ 5530 #define S_SCMD_ENB_DBGID 31 5531 #define M_SCMD_ENB_DBGID 0x1 5532 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 5533 #define G_SCMD_ENB_DBGID(x) \ 5534 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 5535 5536 /* IV generation in SW. */ 5537 #define S_SCMD_IV_GEN_CTRL 30 5538 #define M_SCMD_IV_GEN_CTRL 0x1 5539 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 5540 #define G_SCMD_IV_GEN_CTRL(x) \ 5541 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 5542 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 5543 5544 /* More frags */ 5545 #define S_SCMD_MORE_FRAGS 20 5546 #define M_SCMD_MORE_FRAGS 0x1 5547 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 5548 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 5549 5550 /*last frag */ 5551 #define S_SCMD_LAST_FRAG 19 5552 #define M_SCMD_LAST_FRAG 0x1 5553 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 5554 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 5555 5556 /* TlsCompPdu */ 5557 #define S_SCMD_TLS_COMPPDU 18 5558 #define M_SCMD_TLS_COMPPDU 0x1 5559 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 5560 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 5561 5562 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 5563 #define S_SCMD_KEY_CTX_INLINE 17 5564 #define M_SCMD_KEY_CTX_INLINE 0x1 5565 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 5566 #define G_SCMD_KEY_CTX_INLINE(x) \ 5567 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 5568 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 5569 5570 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 5571 #define S_SCMD_TLS_FRAG_ENABLE 16 5572 #define M_SCMD_TLS_FRAG_ENABLE 0x1 5573 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 5574 #define G_SCMD_TLS_FRAG_ENABLE(x) \ 5575 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 5576 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 5577 5578 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 5579 * modes, in this case TLS_TX will drop the PDU and only 5580 * send back the MAC bytes. */ 5581 #define S_SCMD_MAC_ONLY 15 5582 #define M_SCMD_MAC_ONLY 0x1 5583 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 5584 #define G_SCMD_MAC_ONLY(x) \ 5585 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 5586 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 5587 5588 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 5589 * which have complex AAD and IV formations Eg:AES-CCM 5590 */ 5591 #define S_SCMD_AADIVDROP 14 5592 #define M_SCMD_AADIVDROP 0x1 5593 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 5594 #define G_SCMD_AADIVDROP(x) \ 5595 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 5596 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 5597 5598 /* HdrLength - Length of all headers excluding TLS header 5599 * present before start of crypto PDU/payload. */ 5600 #define S_SCMD_HDR_LEN 0 5601 #define M_SCMD_HDR_LEN 0x3fff 5602 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 5603 #define G_SCMD_HDR_LEN(x) \ 5604 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 5605 5606 struct cpl_rx_pkt_ipsec { 5607 RSS_HDR 5608 union opcode_tid ot; 5609 __be16 vlan; 5610 __be16 length; 5611 __be32 rxchannel_to_ethhdrlen; 5612 __be32 iphdrlen_to_rxerror; 5613 __be64 timestamp; 5614 }; 5615 5616 #define S_CPL_RX_PKT_IPSEC_OPCODE 24 5617 #define M_CPL_RX_PKT_IPSEC_OPCODE 0xff 5618 #define V_CPL_RX_PKT_IPSEC_OPCODE(x) ((x) << S_CPL_RX_PKT_IPSEC_OPCODE) 5619 #define G_CPL_RX_PKT_IPSEC_OPCODE(x) \ 5620 (((x) >> S_CPL_RX_PKT_IPSEC_OPCODE) & M_CPL_RX_PKT_IPSEC_OPCODE) 5621 5622 #define S_CPL_RX_PKT_IPSEC_IPFRAG 23 5623 #define M_CPL_RX_PKT_IPSEC_IPFRAG 0x1 5624 #define V_CPL_RX_PKT_IPSEC_IPFRAG(x) ((x) << S_CPL_RX_PKT_IPSEC_IPFRAG) 5625 #define G_CPL_RX_PKT_IPSEC_IPFRAG(x) \ 5626 (((x) >> S_CPL_RX_PKT_IPSEC_IPFRAG) & M_CPL_RX_PKT_IPSEC_IPFRAG) 5627 #define F_CPL_RX_PKT_IPSEC_IPFRAG V_CPL_RX_PKT_IPSEC_IPFRAG(1U) 5628 5629 #define S_CPL_RX_PKT_IPSEC_VLAN_EX 22 5630 #define M_CPL_RX_PKT_IPSEC_VLAN_EX 0x1 5631 #define V_CPL_RX_PKT_IPSEC_VLAN_EX(x) ((x) << S_CPL_RX_PKT_IPSEC_VLAN_EX) 5632 #define G_CPL_RX_PKT_IPSEC_VLAN_EX(x) \ 5633 (((x) >> S_CPL_RX_PKT_IPSEC_VLAN_EX) & M_CPL_RX_PKT_IPSEC_VLAN_EX) 5634 #define F_CPL_RX_PKT_IPSEC_VLAN_EX V_CPL_RX_PKT_IPSEC_VLAN_EX(1U) 5635 5636 #define S_CPL_RX_PKT_IPSEC_IPMI 21 5637 #define M_CPL_RX_PKT_IPSEC_IPMI 0x1 5638 #define V_CPL_RX_PKT_IPSEC_IPMI(x) ((x) << S_CPL_RX_PKT_IPSEC_IPMI) 5639 #define G_CPL_RX_PKT_IPSEC_IPMI(x) \ 5640 (((x) >> S_CPL_RX_PKT_IPSEC_IPMI) & M_CPL_RX_PKT_IPSEC_IPMI) 5641 #define F_CPL_RX_PKT_IPSEC_IPMI V_CPL_RX_PKT_IPSEC_IPMI(1U) 5642 5643 #define S_CPL_RX_PKT_IPSEC_INTERFACE 16 5644 #define M_CPL_RX_PKT_IPSEC_INTERFACE 0xf 5645 #define V_CPL_RX_PKT_IPSEC_INTERFACE(x) ((x) << S_CPL_RX_PKT_IPSEC_INTERFACE) 5646 #define G_CPL_RX_PKT_IPSEC_INTERFACE(x) \ 5647 (((x) >> S_CPL_RX_PKT_IPSEC_INTERFACE) & M_CPL_RX_PKT_IPSEC_INTERFACE) 5648 5649 #define S_CPL_RX_PKT_IPSEC_IPSECEXTERR 12 5650 #define M_CPL_RX_PKT_IPSEC_IPSECEXTERR 0xf 5651 #define V_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \ 5652 ((x) << S_CPL_RX_PKT_IPSEC_IPSECEXTERR) 5653 #define G_CPL_RX_PKT_IPSEC_IPSECEXTERR(x) \ 5654 (((x) >> S_CPL_RX_PKT_IPSEC_IPSECEXTERR) & M_CPL_RX_PKT_IPSEC_IPSECEXTERR) 5655 5656 #define S_CPL_RX_PKT_IPSEC_IPSECTYPE 10 5657 #define M_CPL_RX_PKT_IPSEC_IPSECTYPE 0x3 5658 #define V_CPL_RX_PKT_IPSEC_IPSECTYPE(x) ((x) << S_CPL_RX_PKT_IPSEC_IPSECTYPE) 5659 #define G_CPL_RX_PKT_IPSEC_IPSECTYPE(x) \ 5660 (((x) >> S_CPL_RX_PKT_IPSEC_IPSECTYPE) & M_CPL_RX_PKT_IPSEC_IPSECTYPE) 5661 5662 #define S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN 0 5663 #define M_CPL_RX_PKT_IPSEC_OUTIPHDRLEN 0x3ff 5664 #define V_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \ 5665 ((x) << S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) 5666 #define G_CPL_RX_PKT_IPSEC_OUTIPHDRLEN(x) \ 5667 (((x) >> S_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) & M_CPL_RX_PKT_IPSEC_OUTIPHDRLEN) 5668 5669 #define S_CPL_RX_PKT_IPSEC_RXCHANNEL 28 5670 #define M_CPL_RX_PKT_IPSEC_RXCHANNEL 0xf 5671 #define V_CPL_RX_PKT_IPSEC_RXCHANNEL(x) ((x) << S_CPL_RX_PKT_IPSEC_RXCHANNEL) 5672 #define G_CPL_RX_PKT_IPSEC_RXCHANNEL(x) \ 5673 (((x) >> S_CPL_RX_PKT_IPSEC_RXCHANNEL) & M_CPL_RX_PKT_IPSEC_RXCHANNEL) 5674 5675 #define S_CPL_RX_PKT_IPSEC_FLAGS 20 5676 #define M_CPL_RX_PKT_IPSEC_FLAGS 0xff 5677 #define V_CPL_RX_PKT_IPSEC_FLAGS(x) ((x) << S_CPL_RX_PKT_IPSEC_FLAGS) 5678 #define G_CPL_RX_PKT_IPSEC_FLAGS(x) \ 5679 (((x) >> S_CPL_RX_PKT_IPSEC_FLAGS) & M_CPL_RX_PKT_IPSEC_FLAGS) 5680 5681 #define S_CPL_RX_PKT_IPSEC_MACMATCHTYPE 17 5682 #define M_CPL_RX_PKT_IPSEC_MACMATCHTYPE 0x7 5683 #define V_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \ 5684 ((x) << S_CPL_RX_PKT_IPSEC_MACMATCHTYPE) 5685 #define G_CPL_RX_PKT_IPSEC_MACMATCHTYPE(x) \ 5686 (((x) >> S_CPL_RX_PKT_IPSEC_MACMATCHTYPE) & \ 5687 M_CPL_RX_PKT_IPSEC_MACMATCHTYPE) 5688 5689 #define S_CPL_RX_PKT_IPSEC_MACINDEX 8 5690 #define M_CPL_RX_PKT_IPSEC_MACINDEX 0x1ff 5691 #define V_CPL_RX_PKT_IPSEC_MACINDEX(x) ((x) << S_CPL_RX_PKT_IPSEC_MACINDEX) 5692 #define G_CPL_RX_PKT_IPSEC_MACINDEX(x) \ 5693 (((x) >> S_CPL_RX_PKT_IPSEC_MACINDEX) & M_CPL_RX_PKT_IPSEC_MACINDEX) 5694 5695 #define S_CPL_RX_PKT_IPSEC_ETHHDRLEN 0 5696 #define M_CPL_RX_PKT_IPSEC_ETHHDRLEN 0xff 5697 #define V_CPL_RX_PKT_IPSEC_ETHHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_ETHHDRLEN) 5698 #define G_CPL_RX_PKT_IPSEC_ETHHDRLEN(x) \ 5699 (((x) >> S_CPL_RX_PKT_IPSEC_ETHHDRLEN) & M_CPL_RX_PKT_IPSEC_ETHHDRLEN) 5700 5701 #define S_CPL_RX_PKT_IPSEC_IPHDRLEN 22 5702 #define M_CPL_RX_PKT_IPSEC_IPHDRLEN 0x3ff 5703 #define V_CPL_RX_PKT_IPSEC_IPHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_IPHDRLEN) 5704 #define G_CPL_RX_PKT_IPSEC_IPHDRLEN(x) \ 5705 (((x) >> S_CPL_RX_PKT_IPSEC_IPHDRLEN) & M_CPL_RX_PKT_IPSEC_IPHDRLEN) 5706 5707 #define S_CPL_RX_PKT_IPSEC_TCPHDRLEN 16 5708 #define M_CPL_RX_PKT_IPSEC_TCPHDRLEN 0x3f 5709 #define V_CPL_RX_PKT_IPSEC_TCPHDRLEN(x) ((x) << S_CPL_RX_PKT_IPSEC_TCPHDRLEN) 5710 #define G_CPL_RX_PKT_IPSEC_TCPHDRLEN(x) \ 5711 (((x) >> S_CPL_RX_PKT_IPSEC_TCPHDRLEN) & M_CPL_RX_PKT_IPSEC_TCPHDRLEN) 5712 5713 #define S_CPL_RX_PKT_IPSEC_RXERROR 0 5714 #define M_CPL_RX_PKT_IPSEC_RXERROR 0xffff 5715 #define V_CPL_RX_PKT_IPSEC_RXERROR(x) ((x) << S_CPL_RX_PKT_IPSEC_RXERROR) 5716 #define G_CPL_RX_PKT_IPSEC_RXERROR(x) \ 5717 (((x) >> S_CPL_RX_PKT_IPSEC_RXERROR) & M_CPL_RX_PKT_IPSEC_RXERROR) 5718 5719 struct cpl_tx_sec_pdu { 5720 __be32 op_ivinsrtofst; 5721 __be32 pldlen; 5722 __be32 aadstart_cipherstop_hi; 5723 __be32 cipherstop_lo_authinsert; 5724 __be32 seqno_numivs; 5725 __be32 ivgen_hdrlen; 5726 __be64 scmd1; 5727 }; 5728 5729 #define S_CPL_TX_SEC_PDU_OPCODE 24 5730 #define M_CPL_TX_SEC_PDU_OPCODE 0xff 5731 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 5732 #define G_CPL_TX_SEC_PDU_OPCODE(x) \ 5733 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 5734 5735 /* RX Channel Id */ 5736 #define S_CPL_TX_SEC_PDU_RXCHID 22 5737 #define M_CPL_TX_SEC_PDU_RXCHID 0x1 5738 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 5739 #define G_CPL_TX_SEC_PDU_RXCHID(x) \ 5740 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 5741 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 5742 5743 #define S_T7_CPL_TX_SEC_PDU_RXCHID 22 5744 #define M_T7_CPL_TX_SEC_PDU_RXCHID 0x3 5745 #define V_T7_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_T7_CPL_TX_SEC_PDU_RXCHID) 5746 #define G_T7_CPL_TX_SEC_PDU_RXCHID(x) \ 5747 (((x) >> S_T7_CPL_TX_SEC_PDU_RXCHID) & M_T7_CPL_TX_SEC_PDU_RXCHID) 5748 #define F_T7_CPL_TX_SEC_PDU_RXCHID V_T7_CPL_TX_SEC_PDU_RXCHID(1U) 5749 5750 /* Ack Follows */ 5751 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 5752 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 5753 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 5754 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 5755 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 5756 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 5757 5758 /* Loopback bit in cpl_tx_sec_pdu */ 5759 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 5760 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 5761 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 5762 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 5763 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 5764 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 5765 5766 /* Length of cpl header encapsulated */ 5767 #define S_CPL_TX_SEC_PDU_CPLLEN 16 5768 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf 5769 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 5770 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 5771 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 5772 5773 #define S_CPL_TX_SEC_PDU_ACKNEXT 15 5774 #define M_CPL_TX_SEC_PDU_ACKNEXT 0x1 5775 #define V_CPL_TX_SEC_PDU_ACKNEXT(x) ((x) << S_CPL_TX_SEC_PDU_ACKNEXT) 5776 #define G_CPL_TX_SEC_PDU_ACKNEXT(x) \ 5777 (((x) >> S_CPL_TX_SEC_PDU_ACKNEXT) & M_CPL_TX_SEC_PDU_ACKNEXT) 5778 #define F_CPL_TX_SEC_PDU_ACKNEXT V_CPL_TX_SEC_PDU_ACKNEXT(1U) 5779 5780 /* PlaceHolder */ 5781 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 5782 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 5783 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 5784 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 5785 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 5786 M_CPL_TX_SEC_PDU_PLACEHOLDER) 5787 5788 /* IvInsrtOffset: Insertion location for IV */ 5789 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 5790 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 5791 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 5792 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 5793 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 5794 M_CPL_TX_SEC_PDU_IVINSRTOFST) 5795 5796 #define S_CPL_TX_SEC_PDU_PLDLEN 0 5797 #define M_CPL_TX_SEC_PDU_PLDLEN 0xfffff 5798 #define V_CPL_TX_SEC_PDU_PLDLEN(x) ((x) << S_CPL_TX_SEC_PDU_PLDLEN) 5799 #define G_CPL_TX_SEC_PDU_PLDLEN(x) \ 5800 (((x) >> S_CPL_TX_SEC_PDU_PLDLEN) & M_CPL_TX_SEC_PDU_PLDLEN) 5801 5802 /* AadStartOffset: Offset in bytes for AAD start from 5803 * the first byte following 5804 * the pkt headers (0-255 5805 * bytes) */ 5806 #define S_CPL_TX_SEC_PDU_AADSTART 24 5807 #define M_CPL_TX_SEC_PDU_AADSTART 0xff 5808 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 5809 #define G_CPL_TX_SEC_PDU_AADSTART(x) \ 5810 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 5811 M_CPL_TX_SEC_PDU_AADSTART) 5812 5813 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 5814 * the pkt headers (0-511 bytes) */ 5815 #define S_CPL_TX_SEC_PDU_AADSTOP 15 5816 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 5817 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 5818 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 5819 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 5820 5821 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 5822 * first byte following the pkt headers (0-1023 5823 * bytes) */ 5824 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5 5825 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 5826 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 5827 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 5828 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 5829 M_CPL_TX_SEC_PDU_CIPHERSTART) 5830 5831 /* CipherStopOffset: offset in bytes for encryption/decryption end 5832 * from end of the payload of this command (0-511 bytes) */ 5833 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 5834 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 5835 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 5836 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 5837 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 5838 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 5839 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 5840 5841 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 5842 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 5843 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 5844 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 5845 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 5846 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 5847 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 5848 5849 /* AuthStartOffset: offset in bytes for authentication start from 5850 * the first byte following the pkt headers (0-1023) 5851 * */ 5852 #define S_CPL_TX_SEC_PDU_AUTHSTART 18 5853 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 5854 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 5855 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 5856 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 5857 M_CPL_TX_SEC_PDU_AUTHSTART) 5858 5859 /* AuthStopOffset: offset in bytes for authentication 5860 * end from end of the payload of this command (0-511 Bytes) */ 5861 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9 5862 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 5863 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 5864 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 5865 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 5866 M_CPL_TX_SEC_PDU_AUTHSTOP) 5867 5868 /* AuthInsrtOffset: offset in bytes for authentication insertion 5869 * from end of the payload of this command (0-511 bytes) */ 5870 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0 5871 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 5872 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 5873 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 5874 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 5875 M_CPL_TX_SEC_PDU_AUTHINSERT) 5876 5877 struct cpl_rx_phys_dsgl { 5878 __be32 op_to_tid; 5879 __be32 pcirlxorder_to_noofsgentr; 5880 struct rss_header rss_hdr_int; 5881 }; 5882 5883 #define S_CPL_RX_PHYS_DSGL_OPCODE 24 5884 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 5885 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 5886 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 5887 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 5888 5889 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23 5890 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 5891 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 5892 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 5893 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 5894 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 5895 5896 #define S_CPL_RX_PHYS_DSGL_RSVD1 20 5897 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 5898 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 5899 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 5900 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 5901 5902 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 5903 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 5904 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 5905 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 5906 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 5907 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 5908 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 5909 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 5910 5911 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 5912 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 5913 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 5914 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 5915 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 5916 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 5917 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 5918 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 5919 5920 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 5921 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 5922 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 5923 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 5924 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 5925 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 5926 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 5927 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 5928 5929 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 5930 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 5931 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 5932 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 5933 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 5934 M_CPL_RX_PHYS_DSGL_PCITPHNT) 5935 5936 #define S_CPL_RX_PHYS_DSGL_DCAID 16 5937 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 5938 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 5939 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 5940 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 5941 M_CPL_RX_PHYS_DSGL_DCAID) 5942 5943 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 5944 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 5945 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 5946 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 5947 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 5948 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 5949 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 5950 5951 struct cpl_t7_rx_phys_dsgl { 5952 RSS_HDR 5953 union opcode_tid ot; 5954 __be32 PhysAddrFields_lo_to_NumSGE; 5955 __be32 RSSCopy[2]; 5956 }; 5957 5958 #define S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI 0 5959 #define M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI 0xffffff 5960 #define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \ 5961 ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) 5962 #define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI(x) \ 5963 (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) & \ 5964 M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_HI) 5965 5966 #define S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO 16 5967 #define M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO 0xffff 5968 #define V_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \ 5969 ((x) << S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) 5970 #define G_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO(x) \ 5971 (((x) >> S_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) & \ 5972 M_CPL_T7_RX_PHYS_DSGL_PHYSADDRFIELDS_LO) 5973 5974 #define S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR 11 5975 #define M_CPL_T7_RX_PHYS_DSGL_NUMSGEERR 0x1 5976 #define V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x) \ 5977 ((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) 5978 #define G_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(x) \ 5979 (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) & M_CPL_T7_RX_PHYS_DSGL_NUMSGEERR) 5980 #define F_CPL_T7_RX_PHYS_DSGL_NUMSGEERR V_CPL_T7_RX_PHYS_DSGL_NUMSGEERR(1U) 5981 5982 #define S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE 10 5983 #define M_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE 0x1 5984 #define V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x) \ 5985 ((x) << S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) 5986 #define G_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(x) \ 5987 (((x) >> S_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) & \ 5988 M_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE) 5989 #define F_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE \ 5990 V_CPL_T7_RX_PHYS_DSGL_FIXEDSGEMODE(1U) 5991 5992 #define S_CPL_T7_RX_PHYS_DSGL_SPLITMODE 9 5993 #define M_CPL_T7_RX_PHYS_DSGL_SPLITMODE 0x1 5994 #define V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x) \ 5995 ((x) << S_CPL_T7_RX_PHYS_DSGL_SPLITMODE) 5996 #define G_CPL_T7_RX_PHYS_DSGL_SPLITMODE(x) \ 5997 (((x) >> S_CPL_T7_RX_PHYS_DSGL_SPLITMODE) & M_CPL_T7_RX_PHYS_DSGL_SPLITMODE) 5998 #define F_CPL_T7_RX_PHYS_DSGL_SPLITMODE \ 5999 V_CPL_T7_RX_PHYS_DSGL_SPLITMODE(1U) 6000 6001 #define S_CPL_T7_RX_PHYS_DSGL_NUMSGE 0 6002 #define M_CPL_T7_RX_PHYS_DSGL_NUMSGE 0x1ff 6003 #define V_CPL_T7_RX_PHYS_DSGL_NUMSGE(x) ((x) << S_CPL_T7_RX_PHYS_DSGL_NUMSGE) 6004 #define G_CPL_T7_RX_PHYS_DSGL_NUMSGE(x) \ 6005 (((x) >> S_CPL_T7_RX_PHYS_DSGL_NUMSGE) & M_CPL_T7_RX_PHYS_DSGL_NUMSGE) 6006 6007 /* CPL_TX_TLS_ACK */ 6008 struct cpl_tx_tls_ack { 6009 __be32 op_to_Rsvd2; 6010 __be32 PldLen; 6011 __be64 Rsvd3; 6012 }; 6013 6014 #define S_CPL_TX_TLS_ACK_OPCODE 24 6015 #define M_CPL_TX_TLS_ACK_OPCODE 0xff 6016 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 6017 #define G_CPL_TX_TLS_ACK_OPCODE(x) \ 6018 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 6019 6020 #define S_T7_CPL_TX_TLS_ACK_RXCHID 22 6021 #define M_T7_CPL_TX_TLS_ACK_RXCHID 0x3 6022 #define V_T7_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_T7_CPL_TX_TLS_ACK_RXCHID) 6023 #define G_T7_CPL_TX_TLS_ACK_RXCHID(x) \ 6024 (((x) >> S_T7_CPL_TX_TLS_ACK_RXCHID) & M_T7_CPL_TX_TLS_ACK_RXCHID) 6025 6026 #define S_CPL_TX_TLS_ACK_RXCHID 22 6027 #define M_CPL_TX_TLS_ACK_RXCHID 0x1 6028 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 6029 #define G_CPL_TX_TLS_ACK_RXCHID(x) \ 6030 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 6031 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 6032 6033 #define S_CPL_TX_TLS_ACK_FWMSG 21 6034 #define M_CPL_TX_TLS_ACK_FWMSG 0x1 6035 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 6036 #define G_CPL_TX_TLS_ACK_FWMSG(x) \ 6037 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 6038 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 6039 6040 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 6041 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 6042 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 6043 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 6044 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 6045 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 6046 6047 #define S_CPL_TX_TLS_ACK_CPLLEN 16 6048 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf 6049 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 6050 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 6051 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 6052 6053 #define S_CPL_TX_TLS_ACK_COMPLONERR 15 6054 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 6055 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 6056 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 6057 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 6058 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 6059 6060 #define S_CPL_TX_TLS_ACK_LCB 14 6061 #define M_CPL_TX_TLS_ACK_LCB 0x1 6062 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 6063 #define G_CPL_TX_TLS_ACK_LCB(x) \ 6064 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 6065 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 6066 6067 #define S_CPL_TX_TLS_ACK_PHASH 13 6068 #define M_CPL_TX_TLS_ACK_PHASH 0x1 6069 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 6070 #define G_CPL_TX_TLS_ACK_PHASH(x) \ 6071 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 6072 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 6073 6074 #define S_CPL_TX_TLS_ACK_RSVD2 0 6075 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 6076 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 6077 #define G_CPL_TX_TLS_ACK_RSVD2(x) \ 6078 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 6079 6080 #define S_CPL_TX_TLS_ACK_PLDLEN 0 6081 #define M_CPL_TX_TLS_ACK_PLDLEN 0xfffff 6082 #define V_CPL_TX_TLS_ACK_PLDLEN(x) ((x) << S_CPL_TX_TLS_ACK_PLDLEN) 6083 #define G_CPL_TX_TLS_ACK_PLDLEN(x) \ 6084 (((x) >> S_CPL_TX_TLS_ACK_PLDLEN) & M_CPL_TX_TLS_ACK_PLDLEN) 6085 6086 struct cpl_tx_quic_enc { 6087 __be32 op_to_hdrlen; 6088 __be32 hdrlen_to_pktlen; 6089 __be32 r4[2]; 6090 }; 6091 6092 #define S_CPL_TX_QUIC_ENC_OPCODE 24 6093 #define M_CPL_TX_QUIC_ENC_OPCODE 0xff 6094 #define V_CPL_TX_QUIC_ENC_OPCODE(x) ((x) << S_CPL_TX_QUIC_ENC_OPCODE) 6095 #define G_CPL_TX_QUIC_ENC_OPCODE(x) \ 6096 (((x) >> S_CPL_TX_QUIC_ENC_OPCODE) & M_CPL_TX_QUIC_ENC_OPCODE) 6097 6098 #define S_CPL_TX_QUIC_ENC_KEYSIZE 22 6099 #define M_CPL_TX_QUIC_ENC_KEYSIZE 0x3 6100 #define V_CPL_TX_QUIC_ENC_KEYSIZE(x) ((x) << S_CPL_TX_QUIC_ENC_KEYSIZE) 6101 #define G_CPL_TX_QUIC_ENC_KEYSIZE(x) \ 6102 (((x) >> S_CPL_TX_QUIC_ENC_KEYSIZE) & M_CPL_TX_QUIC_ENC_KEYSIZE) 6103 6104 #define S_CPL_TX_QUIC_ENC_PKTNUMSIZE 20 6105 #define M_CPL_TX_QUIC_ENC_PKTNUMSIZE 0x3 6106 #define V_CPL_TX_QUIC_ENC_PKTNUMSIZE(x) ((x) << S_CPL_TX_QUIC_ENC_PKTNUMSIZE) 6107 #define G_CPL_TX_QUIC_ENC_PKTNUMSIZE(x) \ 6108 (((x) >> S_CPL_TX_QUIC_ENC_PKTNUMSIZE) & M_CPL_TX_QUIC_ENC_PKTNUMSIZE) 6109 6110 #define S_CPL_TX_QUIC_ENC_HDRTYPE 19 6111 #define M_CPL_TX_QUIC_ENC_HDRTYPE 0x1 6112 #define V_CPL_TX_QUIC_ENC_HDRTYPE(x) ((x) << S_CPL_TX_QUIC_ENC_HDRTYPE) 6113 #define G_CPL_TX_QUIC_ENC_HDRTYPE(x) \ 6114 (((x) >> S_CPL_TX_QUIC_ENC_HDRTYPE) & M_CPL_TX_QUIC_ENC_HDRTYPE) 6115 #define F_CPL_TX_QUIC_ENC_HDRTYPE V_CPL_TX_QUIC_ENC_HDRTYPE(1U) 6116 6117 #define S_CPL_TX_QUIC_ENC_HDRSTARTOFFSET 4 6118 #define M_CPL_TX_QUIC_ENC_HDRSTARTOFFSET 0xfff 6119 #define V_CPL_TX_QUIC_ENC_HDRSTARTOFFSET(x) \ 6120 ((x) << S_CPL_TX_QUIC_ENC_HDRSTARTOFFSET) 6121 #define G_CPL_TX_QUIC_ENC_HDRSTARTOFFSET(x) \ 6122 (((x) >> S_CPL_TX_QUIC_ENC_HDRSTARTOFFSET) & \ 6123 M_CPL_TX_QUIC_ENC_HDRSTARTOFFSET) 6124 6125 #define S_CPL_TX_QUIC_ENC_HDRLENGTH_HI 0 6126 #define M_CPL_TX_QUIC_ENC_HDRLENGTH_HI 0x3 6127 #define V_CPL_TX_QUIC_ENC_HDRLENGTH_HI(x) \ 6128 ((x) << S_CPL_TX_QUIC_ENC_HDRLENGTH_HI) 6129 #define G_CPL_TX_QUIC_ENC_HDRLENGTH_HI(x) \ 6130 (((x) >> S_CPL_TX_QUIC_ENC_HDRLENGTH_HI) & M_CPL_TX_QUIC_ENC_HDRLENGTH_HI) 6131 6132 #define S_CPL_TX_QUIC_ENC_HDRLENGTH_LO 24 6133 #define M_CPL_TX_QUIC_ENC_HDRLENGTH_LO 0xff 6134 #define V_CPL_TX_QUIC_ENC_HDRLENGTH_LO(x) \ 6135 ((x) << S_CPL_TX_QUIC_ENC_HDRLENGTH_LO) 6136 #define G_CPL_TX_QUIC_ENC_HDRLENGTH_LO(x) \ 6137 (((x) >> S_CPL_TX_QUIC_ENC_HDRLENGTH_LO) & M_CPL_TX_QUIC_ENC_HDRLENGTH_LO) 6138 6139 #define S_CPL_TX_QUIC_ENC_NUMPKT 16 6140 #define M_CPL_TX_QUIC_ENC_NUMPKT 0xff 6141 #define V_CPL_TX_QUIC_ENC_NUMPKT(x) ((x) << S_CPL_TX_QUIC_ENC_NUMPKT) 6142 #define G_CPL_TX_QUIC_ENC_NUMPKT(x) \ 6143 (((x) >> S_CPL_TX_QUIC_ENC_NUMPKT) & M_CPL_TX_QUIC_ENC_NUMPKT) 6144 6145 #define S_CPL_TX_QUIC_ENC_PKTLEN 0 6146 #define M_CPL_TX_QUIC_ENC_PKTLEN 0xffff 6147 #define V_CPL_TX_QUIC_ENC_PKTLEN(x) ((x) << S_CPL_TX_QUIC_ENC_PKTLEN) 6148 #define G_CPL_TX_QUIC_ENC_PKTLEN(x) \ 6149 (((x) >> S_CPL_TX_QUIC_ENC_PKTLEN) & M_CPL_TX_QUIC_ENC_PKTLEN) 6150 6151 struct cpl_tls_tx_scmd_fmt { 6152 __be32 op_to_num_ivs; 6153 __be32 enb_dbgId_to_hdrlen; 6154 __be32 seq_num[2]; 6155 }; 6156 6157 #define S_CPL_TLS_TX_SCMD_FMT_OPCODE 31 6158 #define M_CPL_TLS_TX_SCMD_FMT_OPCODE 0x1 6159 #define V_CPL_TLS_TX_SCMD_FMT_OPCODE(x) ((x) << S_CPL_TLS_TX_SCMD_FMT_OPCODE) 6160 #define G_CPL_TLS_TX_SCMD_FMT_OPCODE(x) \ 6161 (((x) >> S_CPL_TLS_TX_SCMD_FMT_OPCODE) & M_CPL_TLS_TX_SCMD_FMT_OPCODE) 6162 #define F_CPL_TLS_TX_SCMD_FMT_OPCODE V_CPL_TLS_TX_SCMD_FMT_OPCODE(1U) 6163 6164 #define S_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL 29 6165 #define M_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL 0x3 6166 #define V_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL(x) \ 6167 ((x) << S_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL) 6168 #define G_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL(x) \ 6169 (((x) >> S_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL) & \ 6170 M_CPL_TLS_TX_SCMD_FMT_SEQNUMBERCTRL) 6171 6172 #define S_CPL_TLS_TX_SCMD_FMT_PROTOVERSION 24 6173 #define M_CPL_TLS_TX_SCMD_FMT_PROTOVERSION 0xf 6174 #define V_CPL_TLS_TX_SCMD_FMT_PROTOVERSION(x) \ 6175 ((x) << S_CPL_TLS_TX_SCMD_FMT_PROTOVERSION) 6176 #define G_CPL_TLS_TX_SCMD_FMT_PROTOVERSION(x) \ 6177 (((x) >> S_CPL_TLS_TX_SCMD_FMT_PROTOVERSION) & \ 6178 M_CPL_TLS_TX_SCMD_FMT_PROTOVERSION) 6179 6180 #define S_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL 23 6181 #define M_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL 0x1 6182 #define V_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL(x) \ 6183 ((x) << S_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL) 6184 #define G_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL(x) \ 6185 (((x) >> S_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL) & \ 6186 M_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL) 6187 #define F_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL V_CPL_TLS_TX_SCMD_FMT_ENCDECCTRL(1U) 6188 6189 #define S_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL 22 6190 #define M_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL 0x1 6191 #define V_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL(x) \ 6192 ((x) << S_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL) 6193 #define G_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL(x) \ 6194 (((x) >> S_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL) & \ 6195 M_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL) 6196 #define F_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL \ 6197 V_CPL_TLS_TX_SCMD_FMT_CIPHAUTHSEQCTRL(1U) 6198 6199 #define S_CPL_TLS_TX_SCMD_FMT_CIPHMODE 18 6200 #define M_CPL_TLS_TX_SCMD_FMT_CIPHMODE 0xf 6201 #define V_CPL_TLS_TX_SCMD_FMT_CIPHMODE(x) \ 6202 ((x) << S_CPL_TLS_TX_SCMD_FMT_CIPHMODE) 6203 #define G_CPL_TLS_TX_SCMD_FMT_CIPHMODE(x) \ 6204 (((x) >> S_CPL_TLS_TX_SCMD_FMT_CIPHMODE) & M_CPL_TLS_TX_SCMD_FMT_CIPHMODE) 6205 6206 #define S_CPL_TLS_TX_SCMD_FMT_AUTHMODE 14 6207 #define M_CPL_TLS_TX_SCMD_FMT_AUTHMODE 0xf 6208 #define V_CPL_TLS_TX_SCMD_FMT_AUTHMODE(x) \ 6209 ((x) << S_CPL_TLS_TX_SCMD_FMT_AUTHMODE) 6210 #define G_CPL_TLS_TX_SCMD_FMT_AUTHMODE(x) \ 6211 (((x) >> S_CPL_TLS_TX_SCMD_FMT_AUTHMODE) & M_CPL_TLS_TX_SCMD_FMT_AUTHMODE) 6212 6213 #define S_CPL_TLS_TX_SCMD_FMT_HMACCTRL 11 6214 #define M_CPL_TLS_TX_SCMD_FMT_HMACCTRL 0x7 6215 #define V_CPL_TLS_TX_SCMD_FMT_HMACCTRL(x) \ 6216 ((x) << S_CPL_TLS_TX_SCMD_FMT_HMACCTRL) 6217 #define G_CPL_TLS_TX_SCMD_FMT_HMACCTRL(x) \ 6218 (((x) >> S_CPL_TLS_TX_SCMD_FMT_HMACCTRL) & M_CPL_TLS_TX_SCMD_FMT_HMACCTRL) 6219 6220 #define S_CPL_TLS_TX_SCMD_FMT_IVSIZE 7 6221 #define M_CPL_TLS_TX_SCMD_FMT_IVSIZE 0xf 6222 #define V_CPL_TLS_TX_SCMD_FMT_IVSIZE(x) ((x) << S_CPL_TLS_TX_SCMD_FMT_IVSIZE) 6223 #define G_CPL_TLS_TX_SCMD_FMT_IVSIZE(x) \ 6224 (((x) >> S_CPL_TLS_TX_SCMD_FMT_IVSIZE) & M_CPL_TLS_TX_SCMD_FMT_IVSIZE) 6225 6226 #define S_CPL_TLS_TX_SCMD_FMT_NUMIVS 0 6227 #define M_CPL_TLS_TX_SCMD_FMT_NUMIVS 0x7f 6228 #define V_CPL_TLS_TX_SCMD_FMT_NUMIVS(x) ((x) << S_CPL_TLS_TX_SCMD_FMT_NUMIVS) 6229 #define G_CPL_TLS_TX_SCMD_FMT_NUMIVS(x) \ 6230 (((x) >> S_CPL_TLS_TX_SCMD_FMT_NUMIVS) & M_CPL_TLS_TX_SCMD_FMT_NUMIVS) 6231 6232 #define S_CPL_TLS_TX_SCMD_FMT_ENBDBGID 31 6233 #define M_CPL_TLS_TX_SCMD_FMT_ENBDBGID 0x1 6234 #define V_CPL_TLS_TX_SCMD_FMT_ENBDBGID(x) \ 6235 ((x) << S_CPL_TLS_TX_SCMD_FMT_ENBDBGID) 6236 #define G_CPL_TLS_TX_SCMD_FMT_ENBDBGID(x) \ 6237 (((x) >> S_CPL_TLS_TX_SCMD_FMT_ENBDBGID) & M_CPL_TLS_TX_SCMD_FMT_ENBDBGID) 6238 #define F_CPL_TLS_TX_SCMD_FMT_ENBDBGID V_CPL_TLS_TX_SCMD_FMT_ENBDBGID(1U) 6239 6240 #define S_CPL_TLS_TX_SCMD_FMT_IVGENCTRL 30 6241 #define M_CPL_TLS_TX_SCMD_FMT_IVGENCTRL 0x1 6242 #define V_CPL_TLS_TX_SCMD_FMT_IVGENCTRL(x) \ 6243 ((x) << S_CPL_TLS_TX_SCMD_FMT_IVGENCTRL) 6244 #define G_CPL_TLS_TX_SCMD_FMT_IVGENCTRL(x) \ 6245 (((x) >> S_CPL_TLS_TX_SCMD_FMT_IVGENCTRL) & \ 6246 M_CPL_TLS_TX_SCMD_FMT_IVGENCTRL) 6247 6248 #define S_CPL_TLS_TX_SCMD_FMT_MOREFRAGS 20 6249 #define M_CPL_TLS_TX_SCMD_FMT_MOREFRAGS 0x1 6250 #define V_CPL_TLS_TX_SCMD_FMT_MOREFRAGS(x) \ 6251 ((x) << S_CPL_TLS_TX_SCMD_FMT_MOREFRAGS) 6252 #define G_CPL_TLS_TX_SCMD_FMT_MOREFRAGS(x) \ 6253 (((x) >> S_CPL_TLS_TX_SCMD_FMT_MOREFRAGS) & \ 6254 M_CPL_TLS_TX_SCMD_FMT_MOREFRAGS) 6255 #define F_CPL_TLS_TX_SCMD_FMT_MOREFRAGS V_CPL_TLS_TX_SCMD_FMT_MOREFRAGS(1U) 6256 6257 #define S_CPL_TLS_TX_SCMD_FMT_LASTFRAGS 19 6258 #define M_CPL_TLS_TX_SCMD_FMT_LASTFRAGS 0x1 6259 #define V_CPL_TLS_TX_SCMD_FMT_LASTFRAGS(x) \ 6260 ((x) << S_CPL_TLS_TX_SCMD_FMT_LASTFRAGS) 6261 #define G_CPL_TLS_TX_SCMD_FMT_LASTFRAGS(x) \ 6262 (((x) >> S_CPL_TLS_TX_SCMD_FMT_LASTFRAGS) & \ 6263 M_CPL_TLS_TX_SCMD_FMT_LASTFRAGS) 6264 #define F_CPL_TLS_TX_SCMD_FMT_LASTFRAGS V_CPL_TLS_TX_SCMD_FMT_LASTFRAGS(1U) 6265 6266 #define S_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU 18 6267 #define M_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU 0x1 6268 #define V_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU(x) \ 6269 ((x) << S_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU) 6270 #define G_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU(x) \ 6271 (((x) >> S_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU) & \ 6272 M_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU) 6273 #define F_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU V_CPL_TLS_TX_SCMD_FMT_TLSCOMPPDU(1U) 6274 6275 #define S_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY 17 6276 #define M_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY 0x1 6277 #define V_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY(x) \ 6278 ((x) << S_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY) 6279 #define G_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY(x) \ 6280 (((x) >> S_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY) & \ 6281 M_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY) 6282 #define F_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY \ 6283 V_CPL_TLS_TX_SCMD_FMT_PAYLOADONLY(1U) 6284 6285 #define S_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE 16 6286 #define M_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE 0x1 6287 #define V_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE(x) \ 6288 ((x) << S_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE) 6289 #define G_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE(x) \ 6290 (((x) >> S_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE) & \ 6291 M_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE) 6292 #define F_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE \ 6293 V_CPL_TLS_TX_SCMD_FMT_TLSFRAGENABLE(1U) 6294 6295 #define S_CPL_TLS_TX_SCMD_FMT_MACONLY 15 6296 #define M_CPL_TLS_TX_SCMD_FMT_MACONLY 0x1 6297 #define V_CPL_TLS_TX_SCMD_FMT_MACONLY(x) \ 6298 ((x) << S_CPL_TLS_TX_SCMD_FMT_MACONLY) 6299 #define G_CPL_TLS_TX_SCMD_FMT_MACONLY(x) \ 6300 (((x) >> S_CPL_TLS_TX_SCMD_FMT_MACONLY) & M_CPL_TLS_TX_SCMD_FMT_MACONLY) 6301 #define F_CPL_TLS_TX_SCMD_FMT_MACONLY V_CPL_TLS_TX_SCMD_FMT_MACONLY(1U) 6302 6303 #define S_CPL_TLS_TX_SCMD_FMT_AADIVDROP 14 6304 #define M_CPL_TLS_TX_SCMD_FMT_AADIVDROP 0x1 6305 #define V_CPL_TLS_TX_SCMD_FMT_AADIVDROP(x) \ 6306 ((x) << S_CPL_TLS_TX_SCMD_FMT_AADIVDROP) 6307 #define G_CPL_TLS_TX_SCMD_FMT_AADIVDROP(x) \ 6308 (((x) >> S_CPL_TLS_TX_SCMD_FMT_AADIVDROP) & \ 6309 M_CPL_TLS_TX_SCMD_FMT_AADIVDROP) 6310 #define F_CPL_TLS_TX_SCMD_FMT_AADIVDROP V_CPL_TLS_TX_SCMD_FMT_AADIVDROP(1U) 6311 6312 #define S_CPL_TLS_TX_SCMD_FMT_HDRLENGTH 0 6313 #define M_CPL_TLS_TX_SCMD_FMT_HDRLENGTH 0x3fff 6314 #define V_CPL_TLS_TX_SCMD_FMT_HDRLENGTH(x) \ 6315 ((x) << S_CPL_TLS_TX_SCMD_FMT_HDRLENGTH) 6316 #define G_CPL_TLS_TX_SCMD_FMT_HDRLENGTH(x) \ 6317 (((x) >> S_CPL_TLS_TX_SCMD_FMT_HDRLENGTH) & \ 6318 M_CPL_TLS_TX_SCMD_FMT_HDRLENGTH) 6319 6320 struct cpl_rcb_upd { 6321 __be32 op_to_tid; 6322 __be32 opcode_psn; 6323 __u8 nodata_to_cnprepclr; 6324 __u8 rsp_nak_seqclr_pkd; 6325 __be16 wrptr; 6326 __be32 length; 6327 }; 6328 6329 #define S_CPL_RCB_UPD_OPCODE 24 6330 #define M_CPL_RCB_UPD_OPCODE 0xff 6331 #define V_CPL_RCB_UPD_OPCODE(x) ((x) << S_CPL_RCB_UPD_OPCODE) 6332 #define G_CPL_RCB_UPD_OPCODE(x) \ 6333 (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE) 6334 6335 #define S_CPL_RCB_UPD_TID 0 6336 #define M_CPL_RCB_UPD_TID 0xffffff 6337 #define V_CPL_RCB_UPD_TID(x) ((x) << S_CPL_RCB_UPD_TID) 6338 #define G_CPL_RCB_UPD_TID(x) \ 6339 (((x) >> S_CPL_RCB_UPD_TID) & M_CPL_RCB_UPD_TID) 6340 6341 #define S_CPL_RCB_UPD_OPCODE 24 6342 #define M_CPL_RCB_UPD_OPCODE 0xff 6343 #define V_CPL_RCB_UPD_OPCODE(x) ((x) << S_CPL_RCB_UPD_OPCODE) 6344 #define G_CPL_RCB_UPD_OPCODE(x) \ 6345 (((x) >> S_CPL_RCB_UPD_OPCODE) & M_CPL_RCB_UPD_OPCODE) 6346 6347 #define S_CPL_RCB_UPD_PSN 0 6348 #define M_CPL_RCB_UPD_PSN 0xffffff 6349 #define V_CPL_RCB_UPD_PSN(x) ((x) << S_CPL_RCB_UPD_PSN) 6350 #define G_CPL_RCB_UPD_PSN(x) \ 6351 (((x) >> S_CPL_RCB_UPD_PSN) & M_CPL_RCB_UPD_PSN) 6352 6353 #define S_CPL_RCB_UPD_NODATA 7 6354 #define M_CPL_RCB_UPD_NODATA 0x1 6355 #define V_CPL_RCB_UPD_NODATA(x) ((x) << S_CPL_RCB_UPD_NODATA) 6356 #define G_CPL_RCB_UPD_NODATA(x) \ 6357 (((x) >> S_CPL_RCB_UPD_NODATA) & M_CPL_RCB_UPD_NODATA) 6358 #define F_CPL_RCB_UPD_NODATA V_CPL_RCB_UPD_NODATA(1U) 6359 6360 #define S_CPL_RCB_UPD_RTTSTAMP 6 6361 #define M_CPL_RCB_UPD_RTTSTAMP 0x1 6362 #define V_CPL_RCB_UPD_RTTSTAMP(x) ((x) << S_CPL_RCB_UPD_RTTSTAMP) 6363 #define G_CPL_RCB_UPD_RTTSTAMP(x) \ 6364 (((x) >> S_CPL_RCB_UPD_RTTSTAMP) & M_CPL_RCB_UPD_RTTSTAMP) 6365 #define F_CPL_RCB_UPD_RTTSTAMP V_CPL_RCB_UPD_RTTSTAMP(1U) 6366 6367 #define S_CPL_RCB_UPD_ECNREPCLR 5 6368 #define M_CPL_RCB_UPD_ECNREPCLR 0x1 6369 #define V_CPL_RCB_UPD_ECNREPCLR(x) ((x) << S_CPL_RCB_UPD_ECNREPCLR) 6370 #define G_CPL_RCB_UPD_ECNREPCLR(x) \ 6371 (((x) >> S_CPL_RCB_UPD_ECNREPCLR) & M_CPL_RCB_UPD_ECNREPCLR) 6372 #define F_CPL_RCB_UPD_ECNREPCLR V_CPL_RCB_UPD_ECNREPCLR(1U) 6373 6374 #define S_CPL_RCB_UPD_NAKSEQCLR 4 6375 #define M_CPL_RCB_UPD_NAKSEQCLR 0x1 6376 #define V_CPL_RCB_UPD_NAKSEQCLR(x) ((x) << S_CPL_RCB_UPD_NAKSEQCLR) 6377 #define G_CPL_RCB_UPD_NAKSEQCLR(x) \ 6378 (((x) >> S_CPL_RCB_UPD_NAKSEQCLR) & M_CPL_RCB_UPD_NAKSEQCLR) 6379 #define F_CPL_RCB_UPD_NAKSEQCLR V_CPL_RCB_UPD_NAKSEQCLR(1U) 6380 6381 #define S_CPL_RCB_UPD_QPERRSET 3 6382 #define M_CPL_RCB_UPD_QPERRSET 0x1 6383 #define V_CPL_RCB_UPD_QPERRSET(x) ((x) << S_CPL_RCB_UPD_QPERRSET) 6384 #define G_CPL_RCB_UPD_QPERRSET(x) \ 6385 (((x) >> S_CPL_RCB_UPD_QPERRSET) & M_CPL_RCB_UPD_QPERRSET) 6386 #define F_CPL_RCB_UPD_QPERRSET V_CPL_RCB_UPD_QPERRSET(1U) 6387 6388 #define S_CPL_RCB_UPD_RRQUPDEN 2 6389 #define M_CPL_RCB_UPD_RRQUPDEN 0x1 6390 #define V_CPL_RCB_UPD_RRQUPDEN(x) ((x) << S_CPL_RCB_UPD_RRQUPDEN) 6391 #define G_CPL_RCB_UPD_RRQUPDEN(x) \ 6392 (((x) >> S_CPL_RCB_UPD_RRQUPDEN) & M_CPL_RCB_UPD_RRQUPDEN) 6393 #define F_CPL_RCB_UPD_RRQUPDEN V_CPL_RCB_UPD_RRQUPDEN(1U) 6394 6395 #define S_CPL_RCB_UPD_RQUPDEN 1 6396 #define M_CPL_RCB_UPD_RQUPDEN 0x1 6397 #define V_CPL_RCB_UPD_RQUPDEN(x) ((x) << S_CPL_RCB_UPD_RQUPDEN) 6398 #define G_CPL_RCB_UPD_RQUPDEN(x) \ 6399 (((x) >> S_CPL_RCB_UPD_RQUPDEN) & M_CPL_RCB_UPD_RQUPDEN) 6400 #define F_CPL_RCB_UPD_RQUPDEN V_CPL_RCB_UPD_RQUPDEN(1U) 6401 6402 #define S_CPL_RCB_UPD_CNPREPCLR 0 6403 #define M_CPL_RCB_UPD_CNPREPCLR 0x1 6404 #define V_CPL_RCB_UPD_CNPREPCLR(x) ((x) << S_CPL_RCB_UPD_CNPREPCLR) 6405 #define G_CPL_RCB_UPD_CNPREPCLR(x) \ 6406 (((x) >> S_CPL_RCB_UPD_CNPREPCLR) & M_CPL_RCB_UPD_CNPREPCLR) 6407 #define F_CPL_RCB_UPD_CNPREPCLR V_CPL_RCB_UPD_CNPREPCLR(1U) 6408 6409 #define S_CPL_RCB_UPD_RSPNAKSEQCLR 7 6410 #define M_CPL_RCB_UPD_RSPNAKSEQCLR 0x1 6411 #define V_CPL_RCB_UPD_RSPNAKSEQCLR(x) ((x) << S_CPL_RCB_UPD_RSPNAKSEQCLR) 6412 #define G_CPL_RCB_UPD_RSPNAKSEQCLR(x) \ 6413 (((x) >> S_CPL_RCB_UPD_RSPNAKSEQCLR) & M_CPL_RCB_UPD_RSPNAKSEQCLR) 6414 #define F_CPL_RCB_UPD_RSPNAKSEQCLR V_CPL_RCB_UPD_RSPNAKSEQCLR(1U) 6415 6416 struct cpl_roce_fw_notify { 6417 RSS_HDR 6418 union opcode_tid ot; 6419 __be32 type_pkd; 6420 }; 6421 6422 #define S_CPL_ROCE_FW_NOTIFY_OPCODE 24 6423 #define M_CPL_ROCE_FW_NOTIFY_OPCODE 0xff 6424 #define V_CPL_ROCE_FW_NOTIFY_OPCODE(x) ((x) << S_CPL_ROCE_FW_NOTIFY_OPCODE) 6425 #define G_CPL_ROCE_FW_NOTIFY_OPCODE(x) \ 6426 (((x) >> S_CPL_ROCE_FW_NOTIFY_OPCODE) & M_CPL_ROCE_FW_NOTIFY_OPCODE) 6427 6428 #define S_CPL_ROCE_FW_NOTIFY_TID 0 6429 #define M_CPL_ROCE_FW_NOTIFY_TID 0xffffff 6430 #define V_CPL_ROCE_FW_NOTIFY_TID(x) ((x) << S_CPL_ROCE_FW_NOTIFY_TID) 6431 #define G_CPL_ROCE_FW_NOTIFY_TID(x) \ 6432 (((x) >> S_CPL_ROCE_FW_NOTIFY_TID) & M_CPL_ROCE_FW_NOTIFY_TID) 6433 6434 #define S_CPL_ROCE_FW_NOTIFY_TYPE 28 6435 #define M_CPL_ROCE_FW_NOTIFY_TYPE 0xf 6436 #define V_CPL_ROCE_FW_NOTIFY_TYPE(x) ((x) << S_CPL_ROCE_FW_NOTIFY_TYPE) 6437 #define G_CPL_ROCE_FW_NOTIFY_TYPE(x) \ 6438 (((x) >> S_CPL_ROCE_FW_NOTIFY_TYPE) & M_CPL_ROCE_FW_NOTIFY_TYPE) 6439 6440 struct cpl_roce_ack_nak_req { 6441 RSS_HDR 6442 union opcode_tid ot; 6443 __be16 type_to_opcode; 6444 __be16 length; 6445 __be32 psn_msn_hi; 6446 __be32 msn_lo_pkd; 6447 }; 6448 6449 #define S_CPL_ROCE_ACK_NAK_REQ_OPCODE 24 6450 #define M_CPL_ROCE_ACK_NAK_REQ_OPCODE 0xff 6451 #define V_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \ 6452 ((x) << S_CPL_ROCE_ACK_NAK_REQ_OPCODE) 6453 #define G_CPL_ROCE_ACK_NAK_REQ_OPCODE(x) \ 6454 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_OPCODE) 6455 6456 #define S_CPL_ROCE_ACK_NAK_REQ_TID 0 6457 #define M_CPL_ROCE_ACK_NAK_REQ_TID 0xffffff 6458 #define V_CPL_ROCE_ACK_NAK_REQ_TID(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_TID) 6459 #define G_CPL_ROCE_ACK_NAK_REQ_TID(x) \ 6460 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TID) & M_CPL_ROCE_ACK_NAK_REQ_TID) 6461 6462 #define S_CPL_ROCE_ACK_NAK_REQ_TYPE 12 6463 #define M_CPL_ROCE_ACK_NAK_REQ_TYPE 0xf 6464 #define V_CPL_ROCE_ACK_NAK_REQ_TYPE(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_TYPE) 6465 #define G_CPL_ROCE_ACK_NAK_REQ_TYPE(x) \ 6466 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_TYPE) & M_CPL_ROCE_ACK_NAK_REQ_TYPE) 6467 6468 #define S_CPL_ROCE_ACK_NAK_REQ_STATUS 8 6469 #define M_CPL_ROCE_ACK_NAK_REQ_STATUS 0xf 6470 #define V_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \ 6471 ((x) << S_CPL_ROCE_ACK_NAK_REQ_STATUS) 6472 #define G_CPL_ROCE_ACK_NAK_REQ_STATUS(x) \ 6473 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_STATUS) & M_CPL_ROCE_ACK_NAK_REQ_STATUS) 6474 6475 #define S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE 0 6476 #define M_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE 0xff 6477 #define V_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \ 6478 ((x) << S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) 6479 #define G_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE(x) \ 6480 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_REQ_WIRE_OPCODE) 6481 6482 #define S_CPL_ROCE_ACK_NAK_REQ_PSN 8 6483 #define M_CPL_ROCE_ACK_NAK_REQ_PSN 0xffffff 6484 #define V_CPL_ROCE_ACK_NAK_REQ_PSN(x) ((x) << S_CPL_ROCE_ACK_NAK_REQ_PSN) 6485 #define G_CPL_ROCE_ACK_NAK_REQ_PSN(x) \ 6486 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_PSN) & M_CPL_ROCE_ACK_NAK_REQ_PSN) 6487 6488 #define S_CPL_ROCE_ACK_NAK_REQ_MSN_HI 0 6489 #define M_CPL_ROCE_ACK_NAK_REQ_MSN_HI 0xff 6490 #define V_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \ 6491 ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_HI) 6492 #define G_CPL_ROCE_ACK_NAK_REQ_MSN_HI(x) \ 6493 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_HI) & M_CPL_ROCE_ACK_NAK_REQ_MSN_HI) 6494 6495 #define S_CPL_ROCE_ACK_NAK_REQ_MSN_LO 16 6496 #define M_CPL_ROCE_ACK_NAK_REQ_MSN_LO 0xffff 6497 #define V_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \ 6498 ((x) << S_CPL_ROCE_ACK_NAK_REQ_MSN_LO) 6499 #define G_CPL_ROCE_ACK_NAK_REQ_MSN_LO(x) \ 6500 (((x) >> S_CPL_ROCE_ACK_NAK_REQ_MSN_LO) & M_CPL_ROCE_ACK_NAK_REQ_MSN_LO) 6501 6502 struct cpl_roce_ack_nak { 6503 RSS_HDR 6504 union opcode_tid ot; 6505 __be16 type_to_opcode; 6506 __be16 length; 6507 __be32 psn_rtt_hi; 6508 __be32 rtt_lo_to_rttbad; 6509 }; 6510 6511 #define S_CPL_ROCE_ACK_NAK_OPCODE 24 6512 #define M_CPL_ROCE_ACK_NAK_OPCODE 0xff 6513 #define V_CPL_ROCE_ACK_NAK_OPCODE(x) ((x) << S_CPL_ROCE_ACK_NAK_OPCODE) 6514 #define G_CPL_ROCE_ACK_NAK_OPCODE(x) \ 6515 (((x) >> S_CPL_ROCE_ACK_NAK_OPCODE) & M_CPL_ROCE_ACK_NAK_OPCODE) 6516 6517 #define S_CPL_ROCE_ACK_NAK_TID 0 6518 #define M_CPL_ROCE_ACK_NAK_TID 0xffffff 6519 #define V_CPL_ROCE_ACK_NAK_TID(x) ((x) << S_CPL_ROCE_ACK_NAK_TID) 6520 #define G_CPL_ROCE_ACK_NAK_TID(x) \ 6521 (((x) >> S_CPL_ROCE_ACK_NAK_TID) & M_CPL_ROCE_ACK_NAK_TID) 6522 6523 #define S_CPL_ROCE_ACK_NAK_TYPE 12 6524 #define M_CPL_ROCE_ACK_NAK_TYPE 0xf 6525 #define V_CPL_ROCE_ACK_NAK_TYPE(x) ((x) << S_CPL_ROCE_ACK_NAK_TYPE) 6526 #define G_CPL_ROCE_ACK_NAK_TYPE(x) \ 6527 (((x) >> S_CPL_ROCE_ACK_NAK_TYPE) & M_CPL_ROCE_ACK_NAK_TYPE) 6528 6529 #define S_CPL_ROCE_ACK_NAK_STATUS 8 6530 #define M_CPL_ROCE_ACK_NAK_STATUS 0xf 6531 #define V_CPL_ROCE_ACK_NAK_STATUS(x) ((x) << S_CPL_ROCE_ACK_NAK_STATUS) 6532 #define G_CPL_ROCE_ACK_NAK_STATUS(x) \ 6533 (((x) >> S_CPL_ROCE_ACK_NAK_STATUS) & M_CPL_ROCE_ACK_NAK_STATUS) 6534 6535 #define S_CPL_ROCE_ACK_NAK_WIRE_OPCODE 0 6536 #define M_CPL_ROCE_ACK_NAK_WIRE_OPCODE 0xff 6537 #define V_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x) ((x) << S_CPL_ROCE_ACK_NAK_WIRE_OPCODE) 6538 #define G_CPL_ROCE_ACK_NAK_WIRE_OPCODE(x) \ 6539 (((x) >> S_CPL_ROCE_ACK_NAK_WIRE_OPCODE) & M_CPL_ROCE_ACK_NAK_WIRE_OPCODE) 6540 6541 #define S_CPL_ROCE_ACK_NAK_PSN 8 6542 #define M_CPL_ROCE_ACK_NAK_PSN 0xffffff 6543 #define V_CPL_ROCE_ACK_NAK_PSN(x) ((x) << S_CPL_ROCE_ACK_NAK_PSN) 6544 #define G_CPL_ROCE_ACK_NAK_PSN(x) \ 6545 (((x) >> S_CPL_ROCE_ACK_NAK_PSN) & M_CPL_ROCE_ACK_NAK_PSN) 6546 6547 #define S_CPL_ROCE_ACK_NAK_RTT_HI 0 6548 #define M_CPL_ROCE_ACK_NAK_RTT_HI 0xff 6549 #define V_CPL_ROCE_ACK_NAK_RTT_HI(x) ((x) << S_CPL_ROCE_ACK_NAK_RTT_HI) 6550 #define G_CPL_ROCE_ACK_NAK_RTT_HI(x) \ 6551 (((x) >> S_CPL_ROCE_ACK_NAK_RTT_HI) & M_CPL_ROCE_ACK_NAK_RTT_HI) 6552 6553 #define S_CPL_ROCE_ACK_NAK_RTT_LO 24 6554 #define M_CPL_ROCE_ACK_NAK_RTT_LO 0xff 6555 #define V_CPL_ROCE_ACK_NAK_RTT_LO(x) ((x) << S_CPL_ROCE_ACK_NAK_RTT_LO) 6556 #define G_CPL_ROCE_ACK_NAK_RTT_LO(x) \ 6557 (((x) >> S_CPL_ROCE_ACK_NAK_RTT_LO) & M_CPL_ROCE_ACK_NAK_RTT_LO) 6558 6559 #define S_CPL_ROCE_ACK_NAK_RTTVALID 23 6560 #define M_CPL_ROCE_ACK_NAK_RTTVALID 0x1 6561 #define V_CPL_ROCE_ACK_NAK_RTTVALID(x) ((x) << S_CPL_ROCE_ACK_NAK_RTTVALID) 6562 #define G_CPL_ROCE_ACK_NAK_RTTVALID(x) \ 6563 (((x) >> S_CPL_ROCE_ACK_NAK_RTTVALID) & M_CPL_ROCE_ACK_NAK_RTTVALID) 6564 #define F_CPL_ROCE_ACK_NAK_RTTVALID V_CPL_ROCE_ACK_NAK_RTTVALID(1U) 6565 6566 #define S_CPL_ROCE_ACK_NAK_RTTBAD 22 6567 #define M_CPL_ROCE_ACK_NAK_RTTBAD 0x1 6568 #define V_CPL_ROCE_ACK_NAK_RTTBAD(x) ((x) << S_CPL_ROCE_ACK_NAK_RTTBAD) 6569 #define G_CPL_ROCE_ACK_NAK_RTTBAD(x) \ 6570 (((x) >> S_CPL_ROCE_ACK_NAK_RTTBAD) & M_CPL_ROCE_ACK_NAK_RTTBAD) 6571 #define F_CPL_ROCE_ACK_NAK_RTTBAD V_CPL_ROCE_ACK_NAK_RTTBAD(1U) 6572 6573 struct cpl_roce_cqe { 6574 __be16 op_rssctrl; 6575 __be16 cqid; 6576 __be32 tid_flitcnt; 6577 __be32 qpid_to_wr_type; 6578 __be32 length; 6579 __be32 tag; 6580 __be32 msn; 6581 __be32 se_to_srq; 6582 __be32 rqe; 6583 __be32 extinfoms[2]; 6584 __be32 extinfols[2]; 6585 }; 6586 6587 #define S_CPL_ROCE_CQE_OPCODE 8 6588 #define M_CPL_ROCE_CQE_OPCODE 0xff 6589 #define V_CPL_ROCE_CQE_OPCODE(x) ((x) << S_CPL_ROCE_CQE_OPCODE) 6590 #define G_CPL_ROCE_CQE_OPCODE(x) \ 6591 (((x) >> S_CPL_ROCE_CQE_OPCODE) & M_CPL_ROCE_CQE_OPCODE) 6592 6593 #define S_CPL_ROCE_CQE_RSSCTRL 0 6594 #define M_CPL_ROCE_CQE_RSSCTRL 0xff 6595 #define V_CPL_ROCE_CQE_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_RSSCTRL) 6596 #define G_CPL_ROCE_CQE_RSSCTRL(x) \ 6597 (((x) >> S_CPL_ROCE_CQE_RSSCTRL) & M_CPL_ROCE_CQE_RSSCTRL) 6598 6599 #define S_CPL_ROCE_CQE_TID 8 6600 #define M_CPL_ROCE_CQE_TID 0xfffff 6601 #define V_CPL_ROCE_CQE_TID(x) ((x) << S_CPL_ROCE_CQE_TID) 6602 #define G_CPL_ROCE_CQE_TID(x) \ 6603 (((x) >> S_CPL_ROCE_CQE_TID) & M_CPL_ROCE_CQE_TID) 6604 6605 #define S_CPL_ROCE_CQE_FLITCNT 0 6606 #define M_CPL_ROCE_CQE_FLITCNT 0xff 6607 #define V_CPL_ROCE_CQE_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_FLITCNT) 6608 #define G_CPL_ROCE_CQE_FLITCNT(x) \ 6609 (((x) >> S_CPL_ROCE_CQE_FLITCNT) & M_CPL_ROCE_CQE_FLITCNT) 6610 6611 #define S_CPL_ROCE_CQE_QPID 12 6612 #define M_CPL_ROCE_CQE_QPID 0xfffff 6613 #define V_CPL_ROCE_CQE_QPID(x) ((x) << S_CPL_ROCE_CQE_QPID) 6614 #define G_CPL_ROCE_CQE_QPID(x) \ 6615 (((x) >> S_CPL_ROCE_CQE_QPID) & M_CPL_ROCE_CQE_QPID) 6616 6617 #define S_CPL_ROCE_CQE_GENERATION_BIT 10 6618 #define M_CPL_ROCE_CQE_GENERATION_BIT 0x1 6619 #define V_CPL_ROCE_CQE_GENERATION_BIT(x) \ 6620 ((x) << S_CPL_ROCE_CQE_GENERATION_BIT) 6621 #define G_CPL_ROCE_CQE_GENERATION_BIT(x) \ 6622 (((x) >> S_CPL_ROCE_CQE_GENERATION_BIT) & M_CPL_ROCE_CQE_GENERATION_BIT) 6623 #define F_CPL_ROCE_CQE_GENERATION_BIT V_CPL_ROCE_CQE_GENERATION_BIT(1U) 6624 6625 #define S_CPL_ROCE_CQE_STATUS 5 6626 #define M_CPL_ROCE_CQE_STATUS 0x1f 6627 #define V_CPL_ROCE_CQE_STATUS(x) ((x) << S_CPL_ROCE_CQE_STATUS) 6628 #define G_CPL_ROCE_CQE_STATUS(x) \ 6629 (((x) >> S_CPL_ROCE_CQE_STATUS) & M_CPL_ROCE_CQE_STATUS) 6630 6631 #define S_CPL_ROCE_CQE_CQE_TYPE 4 6632 #define M_CPL_ROCE_CQE_CQE_TYPE 0x1 6633 #define V_CPL_ROCE_CQE_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_CQE_TYPE) 6634 #define G_CPL_ROCE_CQE_CQE_TYPE(x) \ 6635 (((x) >> S_CPL_ROCE_CQE_CQE_TYPE) & M_CPL_ROCE_CQE_CQE_TYPE) 6636 #define F_CPL_ROCE_CQE_CQE_TYPE V_CPL_ROCE_CQE_CQE_TYPE(1U) 6637 6638 #define S_CPL_ROCE_CQE_WR_TYPE 0 6639 #define M_CPL_ROCE_CQE_WR_TYPE 0xf 6640 #define V_CPL_ROCE_CQE_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_WR_TYPE) 6641 #define G_CPL_ROCE_CQE_WR_TYPE(x) \ 6642 (((x) >> S_CPL_ROCE_CQE_WR_TYPE) & M_CPL_ROCE_CQE_WR_TYPE) 6643 6644 #define S_CPL_ROCE_CQE_SE 31 6645 #define M_CPL_ROCE_CQE_SE 0x1 6646 #define V_CPL_ROCE_CQE_SE(x) ((x) << S_CPL_ROCE_CQE_SE) 6647 #define G_CPL_ROCE_CQE_SE(x) \ 6648 (((x) >> S_CPL_ROCE_CQE_SE) & M_CPL_ROCE_CQE_SE) 6649 #define F_CPL_ROCE_CQE_SE V_CPL_ROCE_CQE_SE(1U) 6650 6651 #define S_CPL_ROCE_CQE_WR_TYPE_EXT 24 6652 #define M_CPL_ROCE_CQE_WR_TYPE_EXT 0x7f 6653 #define V_CPL_ROCE_CQE_WR_TYPE_EXT(x) ((x) << S_CPL_ROCE_CQE_WR_TYPE_EXT) 6654 #define G_CPL_ROCE_CQE_WR_TYPE_EXT(x) \ 6655 (((x) >> S_CPL_ROCE_CQE_WR_TYPE_EXT) & M_CPL_ROCE_CQE_WR_TYPE_EXT) 6656 6657 #define S_CPL_ROCE_CQE_EXTMODE 23 6658 #define M_CPL_ROCE_CQE_EXTMODE 0x1 6659 #define V_CPL_ROCE_CQE_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_EXTMODE) 6660 #define G_CPL_ROCE_CQE_EXTMODE(x) \ 6661 (((x) >> S_CPL_ROCE_CQE_EXTMODE) & M_CPL_ROCE_CQE_EXTMODE) 6662 #define F_CPL_ROCE_CQE_EXTMODE V_CPL_ROCE_CQE_EXTMODE(1U) 6663 6664 #define S_CPL_ROCE_CQE_SRQ 0 6665 #define M_CPL_ROCE_CQE_SRQ 0xfff 6666 #define V_CPL_ROCE_CQE_SRQ(x) ((x) << S_CPL_ROCE_CQE_SRQ) 6667 #define G_CPL_ROCE_CQE_SRQ(x) \ 6668 (((x) >> S_CPL_ROCE_CQE_SRQ) & M_CPL_ROCE_CQE_SRQ) 6669 6670 struct cpl_roce_cqe_fw { 6671 __be32 op_to_cqid; 6672 __be32 tid_flitcnt; 6673 __be32 qpid_to_wr_type; 6674 __be32 length; 6675 __be32 tag; 6676 __be32 msn; 6677 __be32 se_to_srq; 6678 __be32 rqe; 6679 __be32 extinfoms[2]; 6680 __be32 extinfols[2]; 6681 }; 6682 6683 #define S_CPL_ROCE_CQE_FW_OPCODE 24 6684 #define M_CPL_ROCE_CQE_FW_OPCODE 0xff 6685 #define V_CPL_ROCE_CQE_FW_OPCODE(x) ((x) << S_CPL_ROCE_CQE_FW_OPCODE) 6686 #define G_CPL_ROCE_CQE_FW_OPCODE(x) \ 6687 (((x) >> S_CPL_ROCE_CQE_FW_OPCODE) & M_CPL_ROCE_CQE_FW_OPCODE) 6688 6689 #define S_CPL_ROCE_CQE_FW_RSSCTRL 16 6690 #define M_CPL_ROCE_CQE_FW_RSSCTRL 0xff 6691 #define V_CPL_ROCE_CQE_FW_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_FW_RSSCTRL) 6692 #define G_CPL_ROCE_CQE_FW_RSSCTRL(x) \ 6693 (((x) >> S_CPL_ROCE_CQE_FW_RSSCTRL) & M_CPL_ROCE_CQE_FW_RSSCTRL) 6694 6695 #define S_CPL_ROCE_CQE_FW_CQID 0 6696 #define M_CPL_ROCE_CQE_FW_CQID 0xffff 6697 #define V_CPL_ROCE_CQE_FW_CQID(x) ((x) << S_CPL_ROCE_CQE_FW_CQID) 6698 #define G_CPL_ROCE_CQE_FW_CQID(x) \ 6699 (((x) >> S_CPL_ROCE_CQE_FW_CQID) & M_CPL_ROCE_CQE_FW_CQID) 6700 6701 #define S_CPL_ROCE_CQE_FW_TID 8 6702 #define M_CPL_ROCE_CQE_FW_TID 0xfffff 6703 #define V_CPL_ROCE_CQE_FW_TID(x) ((x) << S_CPL_ROCE_CQE_FW_TID) 6704 #define G_CPL_ROCE_CQE_FW_TID(x) \ 6705 (((x) >> S_CPL_ROCE_CQE_FW_TID) & M_CPL_ROCE_CQE_FW_TID) 6706 6707 #define S_CPL_ROCE_CQE_FW_FLITCNT 0 6708 #define M_CPL_ROCE_CQE_FW_FLITCNT 0xff 6709 #define V_CPL_ROCE_CQE_FW_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_FW_FLITCNT) 6710 #define G_CPL_ROCE_CQE_FW_FLITCNT(x) \ 6711 (((x) >> S_CPL_ROCE_CQE_FW_FLITCNT) & M_CPL_ROCE_CQE_FW_FLITCNT) 6712 6713 #define S_CPL_ROCE_CQE_FW_QPID 12 6714 #define M_CPL_ROCE_CQE_FW_QPID 0xfffff 6715 #define V_CPL_ROCE_CQE_FW_QPID(x) ((x) << S_CPL_ROCE_CQE_FW_QPID) 6716 #define G_CPL_ROCE_CQE_FW_QPID(x) \ 6717 (((x) >> S_CPL_ROCE_CQE_FW_QPID) & M_CPL_ROCE_CQE_FW_QPID) 6718 6719 #define S_CPL_ROCE_CQE_FW_GENERATION_BIT 10 6720 #define M_CPL_ROCE_CQE_FW_GENERATION_BIT 0x1 6721 #define V_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \ 6722 ((x) << S_CPL_ROCE_CQE_FW_GENERATION_BIT) 6723 #define G_CPL_ROCE_CQE_FW_GENERATION_BIT(x) \ 6724 (((x) >> S_CPL_ROCE_CQE_FW_GENERATION_BIT) & \ 6725 M_CPL_ROCE_CQE_FW_GENERATION_BIT) 6726 #define F_CPL_ROCE_CQE_FW_GENERATION_BIT V_CPL_ROCE_CQE_FW_GENERATION_BIT(1U) 6727 6728 #define S_CPL_ROCE_CQE_FW_STATUS 5 6729 #define M_CPL_ROCE_CQE_FW_STATUS 0x1f 6730 #define V_CPL_ROCE_CQE_FW_STATUS(x) ((x) << S_CPL_ROCE_CQE_FW_STATUS) 6731 #define G_CPL_ROCE_CQE_FW_STATUS(x) \ 6732 (((x) >> S_CPL_ROCE_CQE_FW_STATUS) & M_CPL_ROCE_CQE_FW_STATUS) 6733 6734 #define S_CPL_ROCE_CQE_FW_CQE_TYPE 4 6735 #define M_CPL_ROCE_CQE_FW_CQE_TYPE 0x1 6736 #define V_CPL_ROCE_CQE_FW_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_FW_CQE_TYPE) 6737 #define G_CPL_ROCE_CQE_FW_CQE_TYPE(x) \ 6738 (((x) >> S_CPL_ROCE_CQE_FW_CQE_TYPE) & M_CPL_ROCE_CQE_FW_CQE_TYPE) 6739 #define F_CPL_ROCE_CQE_FW_CQE_TYPE V_CPL_ROCE_CQE_FW_CQE_TYPE(1U) 6740 6741 #define S_CPL_ROCE_CQE_FW_WR_TYPE 0 6742 #define M_CPL_ROCE_CQE_FW_WR_TYPE 0xf 6743 #define V_CPL_ROCE_CQE_FW_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_FW_WR_TYPE) 6744 #define G_CPL_ROCE_CQE_FW_WR_TYPE(x) \ 6745 (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE) & M_CPL_ROCE_CQE_FW_WR_TYPE) 6746 6747 #define S_CPL_ROCE_CQE_FW_SE 31 6748 #define M_CPL_ROCE_CQE_FW_SE 0x1 6749 #define V_CPL_ROCE_CQE_FW_SE(x) ((x) << S_CPL_ROCE_CQE_FW_SE) 6750 #define G_CPL_ROCE_CQE_FW_SE(x) \ 6751 (((x) >> S_CPL_ROCE_CQE_FW_SE) & M_CPL_ROCE_CQE_FW_SE) 6752 #define F_CPL_ROCE_CQE_FW_SE V_CPL_ROCE_CQE_FW_SE(1U) 6753 6754 #define S_CPL_ROCE_CQE_FW_WR_TYPE_EXT 24 6755 #define M_CPL_ROCE_CQE_FW_WR_TYPE_EXT 0x7f 6756 #define V_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \ 6757 ((x) << S_CPL_ROCE_CQE_FW_WR_TYPE_EXT) 6758 #define G_CPL_ROCE_CQE_FW_WR_TYPE_EXT(x) \ 6759 (((x) >> S_CPL_ROCE_CQE_FW_WR_TYPE_EXT) & M_CPL_ROCE_CQE_FW_WR_TYPE_EXT) 6760 6761 #define S_CPL_ROCE_CQE_FW_EXTMODE 23 6762 #define M_CPL_ROCE_CQE_FW_EXTMODE 0x1 6763 #define V_CPL_ROCE_CQE_FW_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_FW_EXTMODE) 6764 #define G_CPL_ROCE_CQE_FW_EXTMODE(x) \ 6765 (((x) >> S_CPL_ROCE_CQE_FW_EXTMODE) & M_CPL_ROCE_CQE_FW_EXTMODE) 6766 #define F_CPL_ROCE_CQE_FW_EXTMODE V_CPL_ROCE_CQE_FW_EXTMODE(1U) 6767 6768 6769 #define S_CPL_ROCE_CQE_FW_SRQ 0 6770 #define M_CPL_ROCE_CQE_FW_SRQ 0xfff 6771 #define V_CPL_ROCE_CQE_FW_SRQ(x) ((x) << S_CPL_ROCE_CQE_FW_SRQ) 6772 #define G_CPL_ROCE_CQE_FW_SRQ(x) \ 6773 (((x) >> S_CPL_ROCE_CQE_FW_SRQ) & M_CPL_ROCE_CQE_FW_SRQ) 6774 6775 struct cpl_roce_cqe_err { 6776 __be32 op_to_cqid; 6777 __be32 tid_flitcnt; 6778 __be32 qpid_to_wr_type; 6779 __be32 length; 6780 __be32 tag; 6781 __be32 msn; 6782 __be32 se_to_srq; 6783 __be32 rqe; 6784 __be32 extinfoms[2]; 6785 __be32 extinfols[2]; 6786 }; 6787 6788 #define S_CPL_ROCE_CQE_ERR_OPCODE 24 6789 #define M_CPL_ROCE_CQE_ERR_OPCODE 0xff 6790 #define V_CPL_ROCE_CQE_ERR_OPCODE(x) ((x) << S_CPL_ROCE_CQE_ERR_OPCODE) 6791 #define G_CPL_ROCE_CQE_ERR_OPCODE(x) \ 6792 (((x) >> S_CPL_ROCE_CQE_ERR_OPCODE) & M_CPL_ROCE_CQE_ERR_OPCODE) 6793 6794 #define S_CPL_ROCE_CQE_ERR_RSSCTRL 16 6795 #define M_CPL_ROCE_CQE_ERR_RSSCTRL 0xff 6796 #define V_CPL_ROCE_CQE_ERR_RSSCTRL(x) ((x) << S_CPL_ROCE_CQE_ERR_RSSCTRL) 6797 #define G_CPL_ROCE_CQE_ERR_RSSCTRL(x) \ 6798 (((x) >> S_CPL_ROCE_CQE_ERR_RSSCTRL) & M_CPL_ROCE_CQE_ERR_RSSCTRL) 6799 6800 #define S_CPL_ROCE_CQE_ERR_CQID 0 6801 #define M_CPL_ROCE_CQE_ERR_CQID 0xffff 6802 #define V_CPL_ROCE_CQE_ERR_CQID(x) ((x) << S_CPL_ROCE_CQE_ERR_CQID) 6803 #define G_CPL_ROCE_CQE_ERR_CQID(x) \ 6804 (((x) >> S_CPL_ROCE_CQE_ERR_CQID) & M_CPL_ROCE_CQE_ERR_CQID) 6805 6806 #define S_CPL_ROCE_CQE_ERR_TID 8 6807 #define M_CPL_ROCE_CQE_ERR_TID 0xfffff 6808 #define V_CPL_ROCE_CQE_ERR_TID(x) ((x) << S_CPL_ROCE_CQE_ERR_TID) 6809 #define G_CPL_ROCE_CQE_ERR_TID(x) \ 6810 (((x) >> S_CPL_ROCE_CQE_ERR_TID) & M_CPL_ROCE_CQE_ERR_TID) 6811 6812 #define S_CPL_ROCE_CQE_ERR_FLITCNT 0 6813 #define M_CPL_ROCE_CQE_ERR_FLITCNT 0xff 6814 #define V_CPL_ROCE_CQE_ERR_FLITCNT(x) ((x) << S_CPL_ROCE_CQE_ERR_FLITCNT) 6815 #define G_CPL_ROCE_CQE_ERR_FLITCNT(x) \ 6816 (((x) >> S_CPL_ROCE_CQE_ERR_FLITCNT) & M_CPL_ROCE_CQE_ERR_FLITCNT) 6817 6818 #define S_CPL_ROCE_CQE_ERR_QPID 12 6819 #define M_CPL_ROCE_CQE_ERR_QPID 0xfffff 6820 #define V_CPL_ROCE_CQE_ERR_QPID(x) ((x) << S_CPL_ROCE_CQE_ERR_QPID) 6821 #define G_CPL_ROCE_CQE_ERR_QPID(x) \ 6822 (((x) >> S_CPL_ROCE_CQE_ERR_QPID) & M_CPL_ROCE_CQE_ERR_QPID) 6823 6824 #define S_CPL_ROCE_CQE_ERR_GENERATION_BIT 10 6825 #define M_CPL_ROCE_CQE_ERR_GENERATION_BIT 0x1 6826 #define V_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \ 6827 ((x) << S_CPL_ROCE_CQE_ERR_GENERATION_BIT) 6828 #define G_CPL_ROCE_CQE_ERR_GENERATION_BIT(x) \ 6829 (((x) >> S_CPL_ROCE_CQE_ERR_GENERATION_BIT) & \ 6830 M_CPL_ROCE_CQE_ERR_GENERATION_BIT) 6831 #define F_CPL_ROCE_CQE_ERR_GENERATION_BIT \ 6832 V_CPL_ROCE_CQE_ERR_GENERATION_BIT(1U) 6833 6834 #define S_CPL_ROCE_CQE_ERR_STATUS 5 6835 #define M_CPL_ROCE_CQE_ERR_STATUS 0x1f 6836 #define V_CPL_ROCE_CQE_ERR_STATUS(x) ((x) << S_CPL_ROCE_CQE_ERR_STATUS) 6837 #define G_CPL_ROCE_CQE_ERR_STATUS(x) \ 6838 (((x) >> S_CPL_ROCE_CQE_ERR_STATUS) & M_CPL_ROCE_CQE_ERR_STATUS) 6839 6840 #define S_CPL_ROCE_CQE_ERR_CQE_TYPE 4 6841 #define M_CPL_ROCE_CQE_ERR_CQE_TYPE 0x1 6842 #define V_CPL_ROCE_CQE_ERR_CQE_TYPE(x) ((x) << S_CPL_ROCE_CQE_ERR_CQE_TYPE) 6843 #define G_CPL_ROCE_CQE_ERR_CQE_TYPE(x) \ 6844 (((x) >> S_CPL_ROCE_CQE_ERR_CQE_TYPE) & M_CPL_ROCE_CQE_ERR_CQE_TYPE) 6845 #define F_CPL_ROCE_CQE_ERR_CQE_TYPE V_CPL_ROCE_CQE_ERR_CQE_TYPE(1U) 6846 6847 #define S_CPL_ROCE_CQE_ERR_WR_TYPE 0 6848 #define M_CPL_ROCE_CQE_ERR_WR_TYPE 0xf 6849 #define V_CPL_ROCE_CQE_ERR_WR_TYPE(x) ((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE) 6850 #define G_CPL_ROCE_CQE_ERR_WR_TYPE(x) \ 6851 (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE) & M_CPL_ROCE_CQE_ERR_WR_TYPE) 6852 6853 #define S_CPL_ROCE_CQE_ERR_SE 31 6854 #define M_CPL_ROCE_CQE_ERR_SE 0x1 6855 #define V_CPL_ROCE_CQE_ERR_SE(x) ((x) << S_CPL_ROCE_CQE_ERR_SE) 6856 #define G_CPL_ROCE_CQE_ERR_SE(x) \ 6857 (((x) >> S_CPL_ROCE_CQE_ERR_SE) & M_CPL_ROCE_CQE_ERR_SE) 6858 #define F_CPL_ROCE_CQE_ERR_SE V_CPL_ROCE_CQE_ERR_SE(1U) 6859 6860 #define S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT 24 6861 #define M_CPL_ROCE_CQE_ERR_WR_TYPE_EXT 0x7f 6862 #define V_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \ 6863 ((x) << S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) 6864 #define G_CPL_ROCE_CQE_ERR_WR_TYPE_EXT(x) \ 6865 (((x) >> S_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) & M_CPL_ROCE_CQE_ERR_WR_TYPE_EXT) 6866 6867 #define S_CPL_ROCE_CQE_ERR_EXTMODE 23 6868 #define M_CPL_ROCE_CQE_ERR_EXTMODE 0x1 6869 #define V_CPL_ROCE_CQE_ERR_EXTMODE(x) ((x) << S_CPL_ROCE_CQE_ERR_EXTMODE) 6870 #define G_CPL_ROCE_CQE_ERR_EXTMODE(x) \ 6871 (((x) >> S_CPL_ROCE_CQE_ERR_EXTMODE) & M_CPL_ROCE_CQE_ERR_EXTMODE) 6872 #define F_CPL_ROCE_CQE_ERR_EXTMODE V_CPL_ROCE_CQE_ERR_EXTMODE(1U) 6873 6874 6875 #define S_CPL_ROCE_CQE_ERR_SRQ 0 6876 #define M_CPL_ROCE_CQE_ERR_SRQ 0xfff 6877 #define V_CPL_ROCE_CQE_ERR_SRQ(x) ((x) << S_CPL_ROCE_CQE_ERR_SRQ) 6878 #define G_CPL_ROCE_CQE_ERR_SRQ(x) \ 6879 (((x) >> S_CPL_ROCE_CQE_ERR_SRQ) & M_CPL_ROCE_CQE_ERR_SRQ) 6880 6881 struct cpl_accelerator_hdr { 6882 __be16 op_accelerator_id; 6883 __be16 rxchid_payload_to_inner_cpl_length_ack; 6884 __be32 inner_cpl_length_payload_status_loc; 6885 }; 6886 6887 #define S_CPL_ACCELERATOR_HDR_OPCODE 8 6888 #define M_CPL_ACCELERATOR_HDR_OPCODE 0xff 6889 #define V_CPL_ACCELERATOR_HDR_OPCODE(x) ((x) << S_CPL_ACCELERATOR_HDR_OPCODE) 6890 #define G_CPL_ACCELERATOR_HDR_OPCODE(x) \ 6891 (((x) >> S_CPL_ACCELERATOR_HDR_OPCODE) & M_CPL_ACCELERATOR_HDR_OPCODE) 6892 6893 #define S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID 0 6894 #define M_CPL_ACCELERATOR_HDR_ACCELERATOR_ID 0xff 6895 #define V_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \ 6896 ((x) << S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) 6897 #define G_CPL_ACCELERATOR_HDR_ACCELERATOR_ID(x) \ 6898 (((x) >> S_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) & \ 6899 M_CPL_ACCELERATOR_HDR_ACCELERATOR_ID) 6900 6901 #define S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD 14 6902 #define M_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD 0x3 6903 #define V_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \ 6904 ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) 6905 #define G_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD(x) \ 6906 (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) & \ 6907 M_CPL_ACCELERATOR_HDR_RXCHID_PAYLOAD) 6908 6909 #define S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD 12 6910 #define M_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD 0x3 6911 #define V_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \ 6912 ((x) << S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) 6913 #define G_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD(x) \ 6914 (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) & \ 6915 M_CPL_ACCELERATOR_HDR_DESTID_PAYLOAD) 6916 6917 #define S_CPL_ACCELERATOR_HDR_RXCHID_ACK 10 6918 #define M_CPL_ACCELERATOR_HDR_RXCHID_ACK 0x3 6919 #define V_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \ 6920 ((x) << S_CPL_ACCELERATOR_HDR_RXCHID_ACK) 6921 #define G_CPL_ACCELERATOR_HDR_RXCHID_ACK(x) \ 6922 (((x) >> S_CPL_ACCELERATOR_HDR_RXCHID_ACK) & \ 6923 M_CPL_ACCELERATOR_HDR_RXCHID_ACK) 6924 6925 #define S_CPL_ACCELERATOR_HDR_DESTID_ACK 8 6926 #define M_CPL_ACCELERATOR_HDR_DESTID_ACK 0x3 6927 #define V_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \ 6928 ((x) << S_CPL_ACCELERATOR_HDR_DESTID_ACK) 6929 #define G_CPL_ACCELERATOR_HDR_DESTID_ACK(x) \ 6930 (((x) >> S_CPL_ACCELERATOR_HDR_DESTID_ACK) & \ 6931 M_CPL_ACCELERATOR_HDR_DESTID_ACK) 6932 6933 #define S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK 0 6934 #define M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK 0xff 6935 #define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \ 6936 ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) 6937 #define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK(x) \ 6938 (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) & \ 6939 M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_ACK) 6940 6941 #define S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD 24 6942 #define M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD 0xff 6943 #define V_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \ 6944 ((x) << S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) 6945 #define G_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD(x) \ 6946 (((x) >> S_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) & \ 6947 M_CPL_ACCELERATOR_HDR_INNER_CPL_LENGTH_PAYLOAD) 6948 6949 #define S_CPL_ACCELERATOR_HDR_STATUS_LOC 22 6950 #define M_CPL_ACCELERATOR_HDR_STATUS_LOC 0x3 6951 #define V_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \ 6952 ((x) << S_CPL_ACCELERATOR_HDR_STATUS_LOC) 6953 #define G_CPL_ACCELERATOR_HDR_STATUS_LOC(x) \ 6954 (((x) >> S_CPL_ACCELERATOR_HDR_STATUS_LOC) & \ 6955 M_CPL_ACCELERATOR_HDR_STATUS_LOC) 6956 6957 struct cpl_accelerator_ack { 6958 RSS_HDR 6959 __be16 op_accelerator_id; 6960 __be16 r0; 6961 __be32 status; 6962 __be64 r1; 6963 __be64 r2; 6964 }; 6965 6966 #define S_CPL_ACCELERATOR_ACK_OPCODE 8 6967 #define M_CPL_ACCELERATOR_ACK_OPCODE 0xff 6968 #define V_CPL_ACCELERATOR_ACK_OPCODE(x) ((x) << S_CPL_ACCELERATOR_ACK_OPCODE) 6969 #define G_CPL_ACCELERATOR_ACK_OPCODE(x) \ 6970 (((x) >> S_CPL_ACCELERATOR_ACK_OPCODE) & M_CPL_ACCELERATOR_ACK_OPCODE) 6971 6972 #define S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID 0 6973 #define M_CPL_ACCELERATOR_ACK_ACCELERATOR_ID 0xff 6974 #define V_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \ 6975 ((x) << S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) 6976 #define G_CPL_ACCELERATOR_ACK_ACCELERATOR_ID(x) \ 6977 (((x) >> S_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) & \ 6978 M_CPL_ACCELERATOR_ACK_ACCELERATOR_ID) 6979 6980 struct cpl_nvmt_data { 6981 RSS_HDR 6982 union opcode_tid ot; 6983 __be16 r0; 6984 __be16 length; 6985 __be32 seq; 6986 __be32 status_pkd; 6987 }; 6988 6989 #define S_CPL_NVMT_DATA_OPCODE 24 6990 #define M_CPL_NVMT_DATA_OPCODE 0xff 6991 #define V_CPL_NVMT_DATA_OPCODE(x) ((x) << S_CPL_NVMT_DATA_OPCODE) 6992 #define G_CPL_NVMT_DATA_OPCODE(x) \ 6993 (((x) >> S_CPL_NVMT_DATA_OPCODE) & M_CPL_NVMT_DATA_OPCODE) 6994 6995 #define S_CPL_NVMT_DATA_TID 0 6996 #define M_CPL_NVMT_DATA_TID 0xffffff 6997 #define V_CPL_NVMT_DATA_TID(x) ((x) << S_CPL_NVMT_DATA_TID) 6998 #define G_CPL_NVMT_DATA_TID(x) \ 6999 (((x) >> S_CPL_NVMT_DATA_TID) & M_CPL_NVMT_DATA_TID) 7000 7001 #define S_CPL_NVMT_DATA_STATUS 0 7002 #define M_CPL_NVMT_DATA_STATUS 0xff 7003 #define V_CPL_NVMT_DATA_STATUS(x) ((x) << S_CPL_NVMT_DATA_STATUS) 7004 #define G_CPL_NVMT_DATA_STATUS(x) \ 7005 (((x) >> S_CPL_NVMT_DATA_STATUS) & M_CPL_NVMT_DATA_STATUS) 7006 7007 struct cpl_nvmt_cmp { 7008 RSS_HDR 7009 union opcode_tid ot; 7010 __be16 crch; 7011 __be16 length; 7012 __be32 seq; 7013 __u8 t10status; 7014 __u8 status; 7015 __be16 crcl; 7016 }; 7017 7018 #define S_CPL_NVMT_CMP_OPCODE 24 7019 #define M_CPL_NVMT_CMP_OPCODE 0xff 7020 #define V_CPL_NVMT_CMP_OPCODE(x) ((x) << S_CPL_NVMT_CMP_OPCODE) 7021 #define G_CPL_NVMT_CMP_OPCODE(x) \ 7022 (((x) >> S_CPL_NVMT_CMP_OPCODE) & M_CPL_NVMT_CMP_OPCODE) 7023 7024 #define S_CPL_NVMT_CMP_TID 0 7025 #define M_CPL_NVMT_CMP_TID 0xffffff 7026 #define V_CPL_NVMT_CMP_TID(x) ((x) << S_CPL_NVMT_CMP_TID) 7027 #define G_CPL_NVMT_CMP_TID(x) \ 7028 (((x) >> S_CPL_NVMT_CMP_TID) & M_CPL_NVMT_CMP_TID) 7029 7030 struct cpl_nvmt_cmp_imm { 7031 __be32 op_to_cqid; 7032 __be32 generation_bit_to_oprqinc; 7033 __be32 seq; 7034 __be16 crch; 7035 __be16 length; 7036 __be16 crcl; 7037 __u8 t10status; 7038 __u8 status; 7039 __be32 r1; 7040 }; 7041 7042 #define S_CPL_NVMT_CMP_IMM_OPCODE 24 7043 #define M_CPL_NVMT_CMP_IMM_OPCODE 0xff 7044 #define V_CPL_NVMT_CMP_IMM_OPCODE(x) ((x) << S_CPL_NVMT_CMP_IMM_OPCODE) 7045 #define G_CPL_NVMT_CMP_IMM_OPCODE(x) \ 7046 (((x) >> S_CPL_NVMT_CMP_IMM_OPCODE) & M_CPL_NVMT_CMP_IMM_OPCODE) 7047 7048 #define S_CPL_NVMT_CMP_IMM_RSSCTRL 16 7049 #define M_CPL_NVMT_CMP_IMM_RSSCTRL 0xff 7050 #define V_CPL_NVMT_CMP_IMM_RSSCTRL(x) ((x) << S_CPL_NVMT_CMP_IMM_RSSCTRL) 7051 #define G_CPL_NVMT_CMP_IMM_RSSCTRL(x) \ 7052 (((x) >> S_CPL_NVMT_CMP_IMM_RSSCTRL) & M_CPL_NVMT_CMP_IMM_RSSCTRL) 7053 7054 #define S_CPL_NVMT_CMP_IMM_CQID 0 7055 #define M_CPL_NVMT_CMP_IMM_CQID 0xffff 7056 #define V_CPL_NVMT_CMP_IMM_CQID(x) ((x) << S_CPL_NVMT_CMP_IMM_CQID) 7057 #define G_CPL_NVMT_CMP_IMM_CQID(x) \ 7058 (((x) >> S_CPL_NVMT_CMP_IMM_CQID) & M_CPL_NVMT_CMP_IMM_CQID) 7059 7060 #define S_CPL_NVMT_CMP_IMM_GENERATION_BIT 31 7061 #define M_CPL_NVMT_CMP_IMM_GENERATION_BIT 0x1 7062 #define V_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \ 7063 ((x) << S_CPL_NVMT_CMP_IMM_GENERATION_BIT) 7064 #define G_CPL_NVMT_CMP_IMM_GENERATION_BIT(x) \ 7065 (((x) >> S_CPL_NVMT_CMP_IMM_GENERATION_BIT) & \ 7066 M_CPL_NVMT_CMP_IMM_GENERATION_BIT) 7067 #define F_CPL_NVMT_CMP_IMM_GENERATION_BIT \ 7068 V_CPL_NVMT_CMP_IMM_GENERATION_BIT(1U) 7069 7070 #define S_CPL_NVMT_CMP_IMM_TID 8 7071 #define M_CPL_NVMT_CMP_IMM_TID 0xfffff 7072 #define V_CPL_NVMT_CMP_IMM_TID(x) ((x) << S_CPL_NVMT_CMP_IMM_TID) 7073 #define G_CPL_NVMT_CMP_IMM_TID(x) \ 7074 (((x) >> S_CPL_NVMT_CMP_IMM_TID) & M_CPL_NVMT_CMP_IMM_TID) 7075 7076 #define S_CPL_NVMT_CMP_IMM_OPRQINC 0 7077 #define M_CPL_NVMT_CMP_IMM_OPRQINC 0xff 7078 #define V_CPL_NVMT_CMP_IMM_OPRQINC(x) ((x) << S_CPL_NVMT_CMP_IMM_OPRQINC) 7079 #define G_CPL_NVMT_CMP_IMM_OPRQINC(x) \ 7080 (((x) >> S_CPL_NVMT_CMP_IMM_OPRQINC) & M_CPL_NVMT_CMP_IMM_OPRQINC) 7081 7082 struct cpl_nvmt_cmp_srq { 7083 __be32 op_to_cqid; 7084 __be32 generation_bit_to_oprqinc; 7085 __be32 seq; 7086 __be16 crch; 7087 __be16 length; 7088 __be16 crcl; 7089 __u8 t10status; 7090 __u8 status; 7091 __be32 rqe; 7092 }; 7093 7094 #define S_CPL_NVMT_CMP_SRQ_OPCODE 24 7095 #define M_CPL_NVMT_CMP_SRQ_OPCODE 0xff 7096 #define V_CPL_NVMT_CMP_SRQ_OPCODE(x) ((x) << S_CPL_NVMT_CMP_SRQ_OPCODE) 7097 #define G_CPL_NVMT_CMP_SRQ_OPCODE(x) \ 7098 (((x) >> S_CPL_NVMT_CMP_SRQ_OPCODE) & M_CPL_NVMT_CMP_SRQ_OPCODE) 7099 7100 #define S_CPL_NVMT_CMP_SRQ_RSSCTRL 16 7101 #define M_CPL_NVMT_CMP_SRQ_RSSCTRL 0xff 7102 #define V_CPL_NVMT_CMP_SRQ_RSSCTRL(x) ((x) << S_CPL_NVMT_CMP_SRQ_RSSCTRL) 7103 #define G_CPL_NVMT_CMP_SRQ_RSSCTRL(x) \ 7104 (((x) >> S_CPL_NVMT_CMP_SRQ_RSSCTRL) & M_CPL_NVMT_CMP_SRQ_RSSCTRL) 7105 7106 #define S_CPL_NVMT_CMP_SRQ_CQID 0 7107 #define M_CPL_NVMT_CMP_SRQ_CQID 0xffff 7108 #define V_CPL_NVMT_CMP_SRQ_CQID(x) ((x) << S_CPL_NVMT_CMP_SRQ_CQID) 7109 #define G_CPL_NVMT_CMP_SRQ_CQID(x) \ 7110 (((x) >> S_CPL_NVMT_CMP_SRQ_CQID) & M_CPL_NVMT_CMP_SRQ_CQID) 7111 7112 #define S_CPL_NVMT_CMP_SRQ_GENERATION_BIT 31 7113 #define M_CPL_NVMT_CMP_SRQ_GENERATION_BIT 0x1 7114 #define V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \ 7115 ((x) << S_CPL_NVMT_CMP_SRQ_GENERATION_BIT) 7116 #define G_CPL_NVMT_CMP_SRQ_GENERATION_BIT(x) \ 7117 (((x) >> S_CPL_NVMT_CMP_SRQ_GENERATION_BIT) & \ 7118 M_CPL_NVMT_CMP_SRQ_GENERATION_BIT) 7119 #define F_CPL_NVMT_CMP_SRQ_GENERATION_BIT \ 7120 V_CPL_NVMT_CMP_SRQ_GENERATION_BIT(1U) 7121 7122 #define S_CPL_NVMT_CMP_SRQ_TID 8 7123 #define M_CPL_NVMT_CMP_SRQ_TID 0xfffff 7124 #define V_CPL_NVMT_CMP_SRQ_TID(x) ((x) << S_CPL_NVMT_CMP_SRQ_TID) 7125 #define G_CPL_NVMT_CMP_SRQ_TID(x) \ 7126 (((x) >> S_CPL_NVMT_CMP_SRQ_TID) & M_CPL_NVMT_CMP_SRQ_TID) 7127 7128 #define S_CPL_NVMT_CMP_SRQ_OPRQINC 0 7129 #define M_CPL_NVMT_CMP_SRQ_OPRQINC 0xff 7130 #define V_CPL_NVMT_CMP_SRQ_OPRQINC(x) ((x) << S_CPL_NVMT_CMP_SRQ_OPRQINC) 7131 #define G_CPL_NVMT_CMP_SRQ_OPRQINC(x) \ 7132 (((x) >> S_CPL_NVMT_CMP_SRQ_OPRQINC) & M_CPL_NVMT_CMP_SRQ_OPRQINC) 7133 7134 #endif /* T4_MSG_H */ 7135