1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_TX_PKT_FSO = 0x1E, 59 CPL_TX_PKT_ISO = 0x1F, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PASS_OPEN_RPL = 0x24, 66 CPL_ACT_OPEN_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_URG_PKT = 0x29, 71 CPL_TAG_WRITE_RPL = 0x2A, 72 CPL_ABORT_REQ_RSS = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_ABORT_RPL_RSS = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_RX_PHYS_ADDR = 0x30, 79 CPL_PCMD_READ_RPL = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 CPL_SET_TCB_RPL = 0x3A, 89 CPL_RX_PKT = 0x3B, 90 CPL_TAG_READ_RPL = 0x3C, 91 CPL_HIT_NOTIFY = 0x3D, 92 CPL_PKT_NOTIFY = 0x3E, 93 CPL_RX_DDP_COMPLETE = 0x3F, 94 95 CPL_ACT_ESTABLISH = 0x40, 96 CPL_PASS_ESTABLISH = 0x41, 97 CPL_RX_DATA_DDP = 0x42, 98 CPL_SMT_READ_RPL = 0x43, 99 CPL_PASS_ACCEPT_REQ = 0x44, 100 CPL_RX2TX_PKT = 0x45, 101 CPL_RX_FCOE_DDP = 0x46, 102 CPL_FCOE_HDR = 0x47, 103 CPL_T5_TRACE_PKT = 0x48, 104 CPL_RX_ISCSI_DDP = 0x49, 105 CPL_RX_FCOE_DIF = 0x4A, 106 CPL_RX_DATA_DIF = 0x4B, 107 108 CPL_RDMA_READ_REQ = 0x60, 109 CPL_RX_ISCSI_DIF = 0x60, 110 111 CPL_SET_LE_REQ = 0x80, 112 CPL_PASS_OPEN_REQ6 = 0x81, 113 CPL_ACT_OPEN_REQ6 = 0x83, 114 115 CPL_RDMA_TERMINATE = 0xA2, 116 CPL_RDMA_WRITE = 0xA4, 117 CPL_SGE_EGR_UPDATE = 0xA5, 118 CPL_SET_LE_RPL = 0xA6, 119 CPL_FW2_MSG = 0xA7, 120 CPL_FW2_PLD = 0xA8, 121 CPL_T5_RDMA_READ_REQ = 0xA9, 122 CPL_RDMA_ATOMIC_REQ = 0xAA, 123 CPL_RDMA_ATOMIC_RPL = 0xAB, 124 CPL_RDMA_IMM_DATA = 0xAC, 125 CPL_RDMA_IMM_DATA_SE = 0xAD, 126 127 CPL_TRACE_PKT = 0xB0, 128 CPL_RX2TX_DATA = 0xB1, 129 CPL_ISCSI_DATA = 0xB2, 130 CPL_FCOE_DATA = 0xB3, 131 132 CPL_FW4_MSG = 0xC0, 133 CPL_FW4_PLD = 0xC1, 134 CPL_FW4_ACK = 0xC3, 135 136 CPL_FW6_MSG = 0xE0, 137 CPL_FW6_PLD = 0xE1, 138 CPL_TX_PKT_LSO = 0xED, 139 CPL_TX_PKT_XT = 0xEE, 140 141 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 142 }; 143 144 enum CPL_error { 145 CPL_ERR_NONE = 0, 146 CPL_ERR_TCAM_PARITY = 1, 147 CPL_ERR_TCAM_FULL = 3, 148 CPL_ERR_BAD_LENGTH = 15, 149 CPL_ERR_BAD_ROUTE = 18, 150 CPL_ERR_CONN_RESET = 20, 151 CPL_ERR_CONN_EXIST_SYNRECV = 21, 152 CPL_ERR_CONN_EXIST = 22, 153 CPL_ERR_ARP_MISS = 23, 154 CPL_ERR_BAD_SYN = 24, 155 CPL_ERR_CONN_TIMEDOUT = 30, 156 CPL_ERR_XMIT_TIMEDOUT = 31, 157 CPL_ERR_PERSIST_TIMEDOUT = 32, 158 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 159 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 160 CPL_ERR_RTX_NEG_ADVICE = 35, 161 CPL_ERR_PERSIST_NEG_ADVICE = 36, 162 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 163 CPL_ERR_WAIT_ARP_RPL = 41, 164 CPL_ERR_ABORT_FAILED = 42, 165 CPL_ERR_IWARP_FLM = 50, 166 }; 167 168 enum { 169 CPL_CONN_POLICY_AUTO = 0, 170 CPL_CONN_POLICY_ASK = 1, 171 CPL_CONN_POLICY_FILTER = 2, 172 CPL_CONN_POLICY_DENY = 3 173 }; 174 175 enum { 176 ULP_MODE_NONE = 0, 177 ULP_MODE_ISCSI = 2, 178 ULP_MODE_RDMA = 4, 179 ULP_MODE_TCPDDP = 5, 180 ULP_MODE_FCOE = 6, 181 }; 182 183 enum { 184 ULP_CRC_HEADER = 1 << 0, 185 ULP_CRC_DATA = 1 << 1 186 }; 187 188 enum { 189 CPL_PASS_OPEN_ACCEPT, 190 CPL_PASS_OPEN_REJECT, 191 CPL_PASS_OPEN_ACCEPT_TNL 192 }; 193 194 enum { 195 CPL_ABORT_SEND_RST = 0, 196 CPL_ABORT_NO_RST, 197 }; 198 199 enum { /* TX_PKT_XT checksum types */ 200 TX_CSUM_TCP = 0, 201 TX_CSUM_UDP = 1, 202 TX_CSUM_CRC16 = 4, 203 TX_CSUM_CRC32 = 5, 204 TX_CSUM_CRC32C = 6, 205 TX_CSUM_FCOE = 7, 206 TX_CSUM_TCPIP = 8, 207 TX_CSUM_UDPIP = 9, 208 TX_CSUM_TCPIP6 = 10, 209 TX_CSUM_UDPIP6 = 11, 210 TX_CSUM_IP = 12, 211 }; 212 213 enum { /* packet type in CPL_RX_PKT */ 214 PKTYPE_XACT_UCAST = 0, 215 PKTYPE_HASH_UCAST = 1, 216 PKTYPE_XACT_MCAST = 2, 217 PKTYPE_HASH_MCAST = 3, 218 PKTYPE_PROMISC = 4, 219 PKTYPE_HPROMISC = 5, 220 PKTYPE_BCAST = 6 221 }; 222 223 enum { /* DMAC type in CPL_RX_PKT */ 224 DATYPE_UCAST, 225 DATYPE_MCAST, 226 DATYPE_BCAST 227 }; 228 229 enum { /* TCP congestion control algorithms */ 230 CONG_ALG_RENO, 231 CONG_ALG_TAHOE, 232 CONG_ALG_NEWRENO, 233 CONG_ALG_HIGHSPEED 234 }; 235 236 enum { /* RSS hash type */ 237 RSS_HASH_NONE = 0, /* no hash computed */ 238 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 239 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 240 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 241 }; 242 243 enum { /* LE commands */ 244 LE_CMD_READ = 0x4, 245 LE_CMD_WRITE = 0xb 246 }; 247 248 enum { /* LE request size */ 249 LE_SZ_NONE = 0, 250 LE_SZ_33 = 1, 251 LE_SZ_66 = 2, 252 LE_SZ_132 = 3, 253 LE_SZ_264 = 4, 254 LE_SZ_528 = 5 255 }; 256 257 union opcode_tid { 258 __be32 opcode_tid; 259 __u8 opcode; 260 }; 261 262 #define S_CPL_OPCODE 24 263 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 264 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 265 #define G_TID(x) ((x) & 0xFFFFFF) 266 267 /* tid is assumed to be 24-bits */ 268 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 269 270 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 271 272 /* extract the TID from a CPL command */ 273 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 274 275 /* partitioning of TID fields that also carry a queue id */ 276 #define S_TID_TID 0 277 #define M_TID_TID 0x3fff 278 #define V_TID_TID(x) ((x) << S_TID_TID) 279 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 280 281 #define S_TID_QID 14 282 #define M_TID_QID 0x3ff 283 #define V_TID_QID(x) ((x) << S_TID_QID) 284 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 285 286 union opcode_info { 287 __be64 opcode_info; 288 __u8 opcode; 289 }; 290 291 struct tcp_options { 292 __be16 mss; 293 __u8 wsf; 294 #if defined(__LITTLE_ENDIAN_BITFIELD) 295 __u8 :4; 296 __u8 unknown:1; 297 __u8 ecn:1; 298 __u8 sack:1; 299 __u8 tstamp:1; 300 #else 301 __u8 tstamp:1; 302 __u8 sack:1; 303 __u8 ecn:1; 304 __u8 unknown:1; 305 __u8 :4; 306 #endif 307 }; 308 309 struct rss_header { 310 __u8 opcode; 311 #if defined(__LITTLE_ENDIAN_BITFIELD) 312 __u8 channel:2; 313 __u8 filter_hit:1; 314 __u8 filter_tid:1; 315 __u8 hash_type:2; 316 __u8 ipv6:1; 317 __u8 send2fw:1; 318 #else 319 __u8 send2fw:1; 320 __u8 ipv6:1; 321 __u8 hash_type:2; 322 __u8 filter_tid:1; 323 __u8 filter_hit:1; 324 __u8 channel:2; 325 #endif 326 __be16 qid; 327 __be32 hash_val; 328 }; 329 330 #define S_HASHTYPE 20 331 #define M_HASHTYPE 0x3 332 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 333 334 #define S_QNUM 0 335 #define M_QNUM 0xFFFF 336 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 337 338 #ifndef CHELSIO_FW 339 struct work_request_hdr { 340 __be32 wr_hi; 341 __be32 wr_mid; 342 __be64 wr_lo; 343 }; 344 345 /* wr_mid fields */ 346 #define S_WR_LEN16 0 347 #define M_WR_LEN16 0xFF 348 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 349 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 350 351 /* wr_hi fields */ 352 #define S_WR_OP 24 353 #define M_WR_OP 0xFF 354 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 355 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 356 357 # define WR_HDR struct work_request_hdr wr 358 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 359 # define RSS_HDR 360 #else 361 # define WR_HDR 362 # define WR_HDR_SIZE 0 363 # define RSS_HDR struct rss_header rss_hdr; 364 #endif 365 366 /* option 0 fields */ 367 #define S_ACCEPT_MODE 0 368 #define M_ACCEPT_MODE 0x3 369 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 370 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 371 372 #define S_TX_CHAN 2 373 #define M_TX_CHAN 0x3 374 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 375 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 376 377 #define S_NO_CONG 4 378 #define V_NO_CONG(x) ((x) << S_NO_CONG) 379 #define F_NO_CONG V_NO_CONG(1U) 380 381 #define S_DELACK 5 382 #define V_DELACK(x) ((x) << S_DELACK) 383 #define F_DELACK V_DELACK(1U) 384 385 #define S_INJECT_TIMER 6 386 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 387 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 388 389 #define S_NON_OFFLOAD 7 390 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 391 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 392 393 #define S_ULP_MODE 8 394 #define M_ULP_MODE 0xF 395 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 396 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 397 398 #define S_RCV_BUFSIZ 12 399 #define M_RCV_BUFSIZ 0x3FFU 400 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 401 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 402 403 #define S_DSCP 22 404 #define M_DSCP 0x3F 405 #define V_DSCP(x) ((x) << S_DSCP) 406 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 407 408 #define S_SMAC_SEL 28 409 #define M_SMAC_SEL 0xFF 410 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 411 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 412 413 #define S_L2T_IDX 36 414 #define M_L2T_IDX 0xFFF 415 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 416 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 417 418 #define S_TCAM_BYPASS 48 419 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 420 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 421 422 #define S_NAGLE 49 423 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 424 #define F_NAGLE V_NAGLE(1ULL) 425 426 #define S_WND_SCALE 50 427 #define M_WND_SCALE 0xF 428 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 429 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 430 431 #define S_KEEP_ALIVE 54 432 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 433 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 434 435 #define S_MAX_RT 55 436 #define M_MAX_RT 0xF 437 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 438 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 439 440 #define S_MAX_RT_OVERRIDE 59 441 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 442 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 443 444 #define S_MSS_IDX 60 445 #define M_MSS_IDX 0xF 446 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 447 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 448 449 /* option 1 fields */ 450 #define S_SYN_RSS_ENABLE 0 451 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 452 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 453 454 #define S_SYN_RSS_USE_HASH 1 455 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 456 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 457 458 #define S_SYN_RSS_QUEUE 2 459 #define M_SYN_RSS_QUEUE 0x3FF 460 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 461 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 462 463 #define S_LISTEN_INTF 12 464 #define M_LISTEN_INTF 0xFF 465 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 466 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 467 468 #define S_LISTEN_FILTER 20 469 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 470 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 471 472 #define S_SYN_DEFENSE 21 473 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 474 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 475 476 #define S_CONN_POLICY 22 477 #define M_CONN_POLICY 0x3 478 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 479 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 480 481 /* option 2 fields */ 482 #define S_RSS_QUEUE 0 483 #define M_RSS_QUEUE 0x3FF 484 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 485 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 486 487 #define S_RSS_QUEUE_VALID 10 488 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 489 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 490 491 #define S_RX_COALESCE_VALID 11 492 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 493 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 494 495 #define S_RX_COALESCE 12 496 #define M_RX_COALESCE 0x3 497 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 498 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 499 500 #define S_CONG_CNTRL 14 501 #define M_CONG_CNTRL 0x3 502 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 503 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 504 505 #define S_PACE 16 506 #define M_PACE 0x3 507 #define V_PACE(x) ((x) << S_PACE) 508 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 509 510 #define S_CONG_CNTRL_VALID 18 511 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 512 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 513 514 #define S_PACE_VALID 19 515 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 516 #define F_PACE_VALID V_PACE_VALID(1U) 517 518 #define S_RX_FC_DISABLE 20 519 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 520 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 521 522 #define S_RX_FC_DDP 21 523 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 524 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 525 526 #define S_RX_FC_VALID 22 527 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 528 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 529 530 #define S_TX_QUEUE 23 531 #define M_TX_QUEUE 0x7 532 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 533 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 534 535 #define S_RX_CHANNEL 26 536 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 537 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 538 539 #define S_CCTRL_ECN 27 540 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 541 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 542 543 #define S_WND_SCALE_EN 28 544 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 545 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 546 547 #define S_TSTAMPS_EN 29 548 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 549 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 550 551 #define S_SACK_EN 30 552 #define V_SACK_EN(x) ((x) << S_SACK_EN) 553 #define F_SACK_EN V_SACK_EN(1U) 554 555 struct cpl_pass_open_req { 556 WR_HDR; 557 union opcode_tid ot; 558 __be16 local_port; 559 __be16 peer_port; 560 __be32 local_ip; 561 __be32 peer_ip; 562 __be64 opt0; 563 __be64 opt1; 564 }; 565 566 struct cpl_pass_open_req6 { 567 WR_HDR; 568 union opcode_tid ot; 569 __be16 local_port; 570 __be16 peer_port; 571 __be64 local_ip_hi; 572 __be64 local_ip_lo; 573 __be64 peer_ip_hi; 574 __be64 peer_ip_lo; 575 __be64 opt0; 576 __be64 opt1; 577 }; 578 579 struct cpl_pass_open_rpl { 580 RSS_HDR 581 union opcode_tid ot; 582 __u8 rsvd[3]; 583 __u8 status; 584 }; 585 586 struct cpl_pass_establish { 587 RSS_HDR 588 union opcode_tid ot; 589 __be32 rsvd; 590 __be32 tos_stid; 591 __be16 mac_idx; 592 __be16 tcp_opt; 593 __be32 snd_isn; 594 __be32 rcv_isn; 595 }; 596 597 /* cpl_pass_establish.tos_stid fields */ 598 #define S_PASS_OPEN_TID 0 599 #define M_PASS_OPEN_TID 0xFFFFFF 600 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 601 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 602 603 #define S_PASS_OPEN_TOS 24 604 #define M_PASS_OPEN_TOS 0xFF 605 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 606 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 607 608 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 609 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 610 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 611 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 612 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 613 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 614 615 struct cpl_pass_accept_req { 616 RSS_HDR 617 union opcode_tid ot; 618 __be16 rsvd; 619 __be16 len; 620 __be32 hdr_len; 621 __be16 vlan; 622 __be16 l2info; 623 __be32 tos_stid; 624 struct tcp_options tcpopt; 625 }; 626 627 /* cpl_pass_accept_req.hdr_len fields */ 628 #define S_SYN_RX_CHAN 0 629 #define M_SYN_RX_CHAN 0xF 630 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 631 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 632 633 #define S_TCP_HDR_LEN 10 634 #define M_TCP_HDR_LEN 0x3F 635 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 636 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 637 638 #define S_IP_HDR_LEN 16 639 #define M_IP_HDR_LEN 0x3FF 640 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 641 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 642 643 #define S_ETH_HDR_LEN 26 644 #define M_ETH_HDR_LEN 0x3F 645 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 646 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 647 648 /* cpl_pass_accept_req.l2info fields */ 649 #define S_SYN_MAC_IDX 0 650 #define M_SYN_MAC_IDX 0x1FF 651 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 652 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 653 654 #define S_SYN_XACT_MATCH 9 655 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 656 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 657 658 #define S_SYN_INTF 12 659 #define M_SYN_INTF 0xF 660 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 661 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 662 663 struct cpl_pass_accept_rpl { 664 WR_HDR; 665 union opcode_tid ot; 666 __be32 opt2; 667 __be64 opt0; 668 }; 669 670 struct cpl_act_open_req { 671 WR_HDR; 672 union opcode_tid ot; 673 __be16 local_port; 674 __be16 peer_port; 675 __be32 local_ip; 676 __be32 peer_ip; 677 __be64 opt0; 678 __be32 params; 679 __be32 opt2; 680 }; 681 682 struct cpl_t5_act_open_req { 683 WR_HDR; 684 union opcode_tid ot; 685 __be16 local_port; 686 __be16 peer_port; 687 __be32 local_ip; 688 __be32 peer_ip; 689 __be64 opt0; 690 __be32 rsvd; 691 __be32 opt2; 692 __be64 params; 693 }; 694 695 struct cpl_act_open_req6 { 696 WR_HDR; 697 union opcode_tid ot; 698 __be16 local_port; 699 __be16 peer_port; 700 __be64 local_ip_hi; 701 __be64 local_ip_lo; 702 __be64 peer_ip_hi; 703 __be64 peer_ip_lo; 704 __be64 opt0; 705 __be32 params; 706 __be32 opt2; 707 }; 708 709 struct cpl_t5_act_open_req6 { 710 WR_HDR; 711 union opcode_tid ot; 712 __be16 local_port; 713 __be16 peer_port; 714 __be64 local_ip_hi; 715 __be64 local_ip_lo; 716 __be64 peer_ip_hi; 717 __be64 peer_ip_lo; 718 __be64 opt0; 719 __be32 rsvd; 720 __be32 opt2; 721 __be64 params; 722 }; 723 724 struct cpl_act_open_rpl { 725 RSS_HDR 726 union opcode_tid ot; 727 __be32 atid_status; 728 }; 729 730 /* cpl_act_open_rpl.atid_status fields */ 731 #define S_AOPEN_STATUS 0 732 #define M_AOPEN_STATUS 0xFF 733 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 734 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 735 736 #define S_AOPEN_ATID 8 737 #define M_AOPEN_ATID 0xFFFFFF 738 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 739 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 740 741 struct cpl_act_establish { 742 RSS_HDR 743 union opcode_tid ot; 744 __be32 rsvd; 745 __be32 tos_atid; 746 __be16 mac_idx; 747 __be16 tcp_opt; 748 __be32 snd_isn; 749 __be32 rcv_isn; 750 }; 751 752 struct cpl_get_tcb { 753 WR_HDR; 754 union opcode_tid ot; 755 __be16 reply_ctrl; 756 __be16 cookie; 757 }; 758 759 /* cpl_get_tcb.reply_ctrl fields */ 760 #define S_QUEUENO 0 761 #define M_QUEUENO 0x3FF 762 #define V_QUEUENO(x) ((x) << S_QUEUENO) 763 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 764 765 #define S_REPLY_CHAN 14 766 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 767 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 768 769 #define S_NO_REPLY 15 770 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 771 #define F_NO_REPLY V_NO_REPLY(1U) 772 773 struct cpl_get_tcb_rpl { 774 RSS_HDR 775 union opcode_tid ot; 776 __u8 cookie; 777 __u8 status; 778 __be16 len; 779 }; 780 781 struct cpl_set_tcb { 782 WR_HDR; 783 union opcode_tid ot; 784 __be16 reply_ctrl; 785 __be16 cookie; 786 }; 787 788 struct cpl_set_tcb_field { 789 WR_HDR; 790 union opcode_tid ot; 791 __be16 reply_ctrl; 792 __be16 word_cookie; 793 __be64 mask; 794 __be64 val; 795 }; 796 797 struct cpl_set_tcb_field_core { 798 union opcode_tid ot; 799 __be16 reply_ctrl; 800 __be16 word_cookie; 801 __be64 mask; 802 __be64 val; 803 }; 804 805 /* cpl_set_tcb_field.word_cookie fields */ 806 #define S_WORD 0 807 #define M_WORD 0x1F 808 #define V_WORD(x) ((x) << S_WORD) 809 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 810 811 #define S_COOKIE 5 812 #define M_COOKIE 0x7 813 #define V_COOKIE(x) ((x) << S_COOKIE) 814 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 815 816 struct cpl_set_tcb_rpl { 817 RSS_HDR 818 union opcode_tid ot; 819 __be16 rsvd; 820 __u8 cookie; 821 __u8 status; 822 __be64 oldval; 823 }; 824 825 struct cpl_close_con_req { 826 WR_HDR; 827 union opcode_tid ot; 828 __be32 rsvd; 829 }; 830 831 struct cpl_close_con_rpl { 832 RSS_HDR 833 union opcode_tid ot; 834 __u8 rsvd[3]; 835 __u8 status; 836 __be32 snd_nxt; 837 __be32 rcv_nxt; 838 }; 839 840 struct cpl_close_listsvr_req { 841 WR_HDR; 842 union opcode_tid ot; 843 __be16 reply_ctrl; 844 __be16 rsvd; 845 }; 846 847 /* additional cpl_close_listsvr_req.reply_ctrl field */ 848 #define S_LISTSVR_IPV6 14 849 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 850 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 851 852 struct cpl_close_listsvr_rpl { 853 RSS_HDR 854 union opcode_tid ot; 855 __u8 rsvd[3]; 856 __u8 status; 857 }; 858 859 struct cpl_abort_req_rss { 860 RSS_HDR 861 union opcode_tid ot; 862 __u8 rsvd[3]; 863 __u8 status; 864 }; 865 866 struct cpl_abort_req { 867 WR_HDR; 868 union opcode_tid ot; 869 __be32 rsvd0; 870 __u8 rsvd1; 871 __u8 cmd; 872 __u8 rsvd2[6]; 873 }; 874 875 struct cpl_abort_rpl_rss { 876 RSS_HDR 877 union opcode_tid ot; 878 __u8 rsvd[3]; 879 __u8 status; 880 }; 881 882 struct cpl_abort_rpl { 883 WR_HDR; 884 union opcode_tid ot; 885 __be32 rsvd0; 886 __u8 rsvd1; 887 __u8 cmd; 888 __u8 rsvd2[6]; 889 }; 890 891 struct cpl_peer_close { 892 RSS_HDR 893 union opcode_tid ot; 894 __be32 rcv_nxt; 895 }; 896 897 struct cpl_tid_release { 898 WR_HDR; 899 union opcode_tid ot; 900 __be32 rsvd; 901 }; 902 903 struct tx_data_wr { 904 __be32 wr_hi; 905 __be32 wr_lo; 906 __be32 len; 907 __be32 flags; 908 __be32 sndseq; 909 __be32 param; 910 }; 911 912 /* tx_data_wr.flags fields */ 913 #define S_TX_ACK_PAGES 21 914 #define M_TX_ACK_PAGES 0x7 915 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 916 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 917 918 /* tx_data_wr.param fields */ 919 #define S_TX_PORT 0 920 #define M_TX_PORT 0x7 921 #define V_TX_PORT(x) ((x) << S_TX_PORT) 922 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 923 924 #define S_TX_MSS 4 925 #define M_TX_MSS 0xF 926 #define V_TX_MSS(x) ((x) << S_TX_MSS) 927 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 928 929 #define S_TX_QOS 8 930 #define M_TX_QOS 0xFF 931 #define V_TX_QOS(x) ((x) << S_TX_QOS) 932 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 933 934 #define S_TX_SNDBUF 16 935 #define M_TX_SNDBUF 0xFFFF 936 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 937 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 938 939 struct cpl_tx_data { 940 union opcode_tid ot; 941 __be32 len; 942 __be32 rsvd; 943 __be32 flags; 944 }; 945 946 /* cpl_tx_data.flags fields */ 947 #define S_TX_PROXY 5 948 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 949 #define F_TX_PROXY V_TX_PROXY(1U) 950 951 #define S_TX_ULP_SUBMODE 6 952 #define M_TX_ULP_SUBMODE 0xF 953 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 954 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 955 956 #define S_TX_ULP_MODE 10 957 #define M_TX_ULP_MODE 0xF 958 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 959 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 960 961 #define S_TX_SHOVE 14 962 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 963 #define F_TX_SHOVE V_TX_SHOVE(1U) 964 965 #define S_TX_MORE 15 966 #define V_TX_MORE(x) ((x) << S_TX_MORE) 967 #define F_TX_MORE V_TX_MORE(1U) 968 969 #define S_TX_URG 16 970 #define V_TX_URG(x) ((x) << S_TX_URG) 971 #define F_TX_URG V_TX_URG(1U) 972 973 #define S_TX_FLUSH 17 974 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 975 #define F_TX_FLUSH V_TX_FLUSH(1U) 976 977 #define S_TX_SAVE 18 978 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 979 #define F_TX_SAVE V_TX_SAVE(1U) 980 981 #define S_TX_TNL 19 982 #define V_TX_TNL(x) ((x) << S_TX_TNL) 983 #define F_TX_TNL V_TX_TNL(1U) 984 985 /* additional tx_data_wr.flags fields */ 986 #define S_TX_CPU_IDX 0 987 #define M_TX_CPU_IDX 0x3F 988 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 989 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 990 991 #define S_TX_CLOSE 17 992 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 993 #define F_TX_CLOSE V_TX_CLOSE(1U) 994 995 #define S_TX_INIT 18 996 #define V_TX_INIT(x) ((x) << S_TX_INIT) 997 #define F_TX_INIT V_TX_INIT(1U) 998 999 #define S_TX_IMM_ACK 19 1000 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1001 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1002 1003 #define S_TX_IMM_DMA 20 1004 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1005 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1006 1007 struct cpl_tx_data_ack { 1008 RSS_HDR 1009 union opcode_tid ot; 1010 __be32 snd_una; 1011 }; 1012 1013 struct cpl_wr_ack { /* XXX */ 1014 RSS_HDR 1015 union opcode_tid ot; 1016 __be16 credits; 1017 __be16 rsvd; 1018 __be32 snd_nxt; 1019 __be32 snd_una; 1020 }; 1021 1022 struct cpl_tx_pkt_core { 1023 __be32 ctrl0; 1024 __be16 pack; 1025 __be16 len; 1026 __be64 ctrl1; 1027 }; 1028 1029 struct cpl_tx_pkt { 1030 WR_HDR; 1031 struct cpl_tx_pkt_core c; 1032 }; 1033 1034 #define cpl_tx_pkt_xt cpl_tx_pkt 1035 1036 /* cpl_tx_pkt_core.ctrl0 fields */ 1037 #define S_TXPKT_VF 0 1038 #define M_TXPKT_VF 0xFF 1039 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1040 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1041 1042 #define S_TXPKT_PF 8 1043 #define M_TXPKT_PF 0x7 1044 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1045 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1046 1047 #define S_TXPKT_VF_VLD 11 1048 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1049 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1050 1051 #define S_TXPKT_OVLAN_IDX 12 1052 #define M_TXPKT_OVLAN_IDX 0xF 1053 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1054 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1055 1056 #define S_TXPKT_INTF 16 1057 #define M_TXPKT_INTF 0xF 1058 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1059 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1060 1061 #define S_TXPKT_SPECIAL_STAT 20 1062 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1063 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1064 1065 #define S_TXPKT_INS_OVLAN 21 1066 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1067 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1068 1069 #define S_TXPKT_STAT_DIS 22 1070 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1071 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1072 1073 #define S_TXPKT_LOOPBACK 23 1074 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1075 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1076 1077 #define S_TXPKT_TSTAMP 23 1078 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1079 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1080 1081 #define S_TXPKT_OPCODE 24 1082 #define M_TXPKT_OPCODE 0xFF 1083 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1084 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1085 1086 /* cpl_tx_pkt_core.ctrl1 fields */ 1087 #define S_TXPKT_SA_IDX 0 1088 #define M_TXPKT_SA_IDX 0xFFF 1089 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1090 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1091 1092 #define S_TXPKT_CSUM_END 12 1093 #define M_TXPKT_CSUM_END 0xFF 1094 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1095 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1096 1097 #define S_TXPKT_CSUM_START 20 1098 #define M_TXPKT_CSUM_START 0x3FF 1099 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1100 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1101 1102 #define S_TXPKT_IPHDR_LEN 20 1103 #define M_TXPKT_IPHDR_LEN 0x3FFF 1104 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1105 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1106 1107 #define S_TXPKT_CSUM_LOC 30 1108 #define M_TXPKT_CSUM_LOC 0x3FF 1109 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1110 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1111 1112 #define S_TXPKT_ETHHDR_LEN 34 1113 #define M_TXPKT_ETHHDR_LEN 0x3F 1114 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1115 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1116 1117 #define S_TXPKT_CSUM_TYPE 40 1118 #define M_TXPKT_CSUM_TYPE 0xF 1119 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1120 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1121 1122 #define S_TXPKT_VLAN 44 1123 #define M_TXPKT_VLAN 0xFFFF 1124 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1125 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1126 1127 #define S_TXPKT_VLAN_VLD 60 1128 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1129 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1130 1131 #define S_TXPKT_IPSEC 61 1132 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1133 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1134 1135 #define S_TXPKT_IPCSUM_DIS 62 1136 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1137 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1138 1139 #define S_TXPKT_L4CSUM_DIS 63 1140 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1141 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1142 1143 struct cpl_tx_pkt_lso_core { 1144 __be32 lso_ctrl; 1145 __be16 ipid_ofst; 1146 __be16 mss; 1147 __be32 seqno_offset; 1148 __be32 len; 1149 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1150 }; 1151 1152 struct cpl_tx_pkt_lso { 1153 WR_HDR; 1154 struct cpl_tx_pkt_lso_core c; 1155 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1156 }; 1157 1158 struct cpl_tx_pkt_ufo_core { 1159 __be16 ethlen; 1160 __be16 iplen; 1161 __be16 udplen; 1162 __be16 mss; 1163 __be32 len; 1164 __be32 r1; 1165 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1166 }; 1167 1168 struct cpl_tx_pkt_ufo { 1169 WR_HDR; 1170 struct cpl_tx_pkt_ufo_core c; 1171 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1172 }; 1173 1174 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1175 #define S_LSO_TCPHDR_LEN 0 1176 #define M_LSO_TCPHDR_LEN 0xF 1177 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1178 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1179 1180 #define S_LSO_IPHDR_LEN 4 1181 #define M_LSO_IPHDR_LEN 0xFFF 1182 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1183 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1184 1185 #define S_LSO_ETHHDR_LEN 16 1186 #define M_LSO_ETHHDR_LEN 0xF 1187 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1188 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1189 1190 #define S_LSO_IPV6 20 1191 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1192 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1193 1194 #define S_LSO_OFLD_ENCAP 21 1195 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1196 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1197 1198 #define S_LSO_LAST_SLICE 22 1199 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1200 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1201 1202 #define S_LSO_FIRST_SLICE 23 1203 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1204 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1205 1206 #define S_LSO_OPCODE 24 1207 #define M_LSO_OPCODE 0xFF 1208 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1209 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1210 1211 /* cpl_tx_pkt_lso_core.mss fields */ 1212 #define S_LSO_MSS 0 1213 #define M_LSO_MSS 0x3FFF 1214 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1215 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1216 1217 #define S_LSO_IPID_SPLIT 15 1218 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1219 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1220 1221 struct cpl_tx_pkt_fso { 1222 WR_HDR; 1223 __be32 fso_ctrl; 1224 __be16 seqcnt_ofst; 1225 __be16 mtu; 1226 __be32 param_offset; 1227 __be32 len; 1228 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1229 }; 1230 1231 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1232 #define S_FSO_XCHG_CLASS 21 1233 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1234 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1235 1236 #define S_FSO_INITIATOR 20 1237 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1238 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1239 1240 #define S_FSO_FCHDR_LEN 12 1241 #define M_FSO_FCHDR_LEN 0xF 1242 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1243 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1244 1245 struct cpl_iscsi_hdr_no_rss { 1246 union opcode_tid ot; 1247 __be16 pdu_len_ddp; 1248 __be16 len; 1249 __be32 seq; 1250 __be16 urg; 1251 __u8 rsvd; 1252 __u8 status; 1253 }; 1254 1255 struct cpl_tx_data_iso { 1256 WR_HDR; 1257 __be32 iso_ctrl; 1258 __u8 rsvd; 1259 __u8 ahs_len; 1260 __be16 mss; 1261 __be32 burst_size; 1262 __be32 len; 1263 /* encapsulated CPL_TX_DATA follows here */ 1264 }; 1265 1266 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1267 #define S_ISO_CPLHDR_LEN 18 1268 #define M_ISO_CPLHDR_LEN 0xF 1269 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN) 1270 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN) 1271 1272 #define S_ISO_HDR_CRC 17 1273 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC) 1274 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U) 1275 1276 #define S_ISO_DATA_CRC 16 1277 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC) 1278 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U) 1279 1280 #define S_ISO_IMD_DATA_EN 15 1281 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN) 1282 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U) 1283 1284 #define S_ISO_PDU_TYPE 13 1285 #define M_ISO_PDU_TYPE 0x3 1286 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE) 1287 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE) 1288 1289 struct cpl_iscsi_hdr { 1290 RSS_HDR 1291 union opcode_tid ot; 1292 __be16 pdu_len_ddp; 1293 __be16 len; 1294 __be32 seq; 1295 __be16 urg; 1296 __u8 rsvd; 1297 __u8 status; 1298 }; 1299 1300 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1301 #define S_ISCSI_PDU_LEN 0 1302 #define M_ISCSI_PDU_LEN 0x7FFF 1303 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1304 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1305 1306 #define S_ISCSI_DDP 15 1307 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1308 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1309 1310 struct cpl_iscsi_data { 1311 RSS_HDR 1312 union opcode_tid ot; 1313 __u8 rsvd0[2]; 1314 __be16 len; 1315 __be32 seq; 1316 __be16 urg; 1317 __u8 rsvd1; 1318 __u8 status; 1319 }; 1320 1321 struct cpl_rx_data { 1322 RSS_HDR 1323 union opcode_tid ot; 1324 __be16 rsvd; 1325 __be16 len; 1326 __be32 seq; 1327 __be16 urg; 1328 #if defined(__LITTLE_ENDIAN_BITFIELD) 1329 __u8 dack_mode:2; 1330 __u8 psh:1; 1331 __u8 heartbeat:1; 1332 __u8 ddp_off:1; 1333 __u8 :3; 1334 #else 1335 __u8 :3; 1336 __u8 ddp_off:1; 1337 __u8 heartbeat:1; 1338 __u8 psh:1; 1339 __u8 dack_mode:2; 1340 #endif 1341 __u8 status; 1342 }; 1343 1344 struct cpl_fcoe_hdr { 1345 RSS_HDR 1346 union opcode_tid ot; 1347 __be16 oxid; 1348 __be16 len; 1349 __be32 rctl_fctl; 1350 __u8 cs_ctl; 1351 __u8 df_ctl; 1352 __u8 sof; 1353 __u8 eof; 1354 __be16 seq_cnt; 1355 __u8 seq_id; 1356 __u8 type; 1357 __be32 param; 1358 }; 1359 1360 struct cpl_fcoe_data { 1361 RSS_HDR 1362 union opcode_tid ot; 1363 __u8 rsvd0[2]; 1364 __be16 len; 1365 __be32 seq; 1366 __u8 rsvd1[3]; 1367 __u8 status; 1368 }; 1369 1370 struct cpl_rx_urg_notify { 1371 RSS_HDR 1372 union opcode_tid ot; 1373 __be32 seq; 1374 }; 1375 1376 struct cpl_rx_urg_pkt { 1377 RSS_HDR 1378 union opcode_tid ot; 1379 __be16 rsvd; 1380 __be16 len; 1381 }; 1382 1383 struct cpl_rx_data_ack { 1384 WR_HDR; 1385 union opcode_tid ot; 1386 __be32 credit_dack; 1387 }; 1388 1389 struct cpl_rx_data_ack_core { 1390 union opcode_tid ot; 1391 __be32 credit_dack; 1392 }; 1393 1394 /* cpl_rx_data_ack.ack_seq fields */ 1395 #define S_RX_CREDITS 0 1396 #define M_RX_CREDITS 0x3FFFFFF 1397 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1398 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1399 1400 #define S_RX_MODULATE_TX 26 1401 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1402 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1403 1404 #define S_RX_MODULATE_RX 27 1405 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1406 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1407 1408 #define S_RX_FORCE_ACK 28 1409 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1410 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1411 1412 #define S_RX_DACK_MODE 29 1413 #define M_RX_DACK_MODE 0x3 1414 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1415 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1416 1417 #define S_RX_DACK_CHANGE 31 1418 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1419 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1420 1421 struct cpl_rx_ddp_complete { 1422 RSS_HDR 1423 union opcode_tid ot; 1424 __be32 ddp_report; 1425 __be32 rcv_nxt; 1426 __be32 rsvd; 1427 }; 1428 1429 struct cpl_rx_data_ddp { 1430 RSS_HDR 1431 union opcode_tid ot; 1432 __be16 urg; 1433 __be16 len; 1434 __be32 seq; 1435 union { 1436 __be32 nxt_seq; 1437 __be32 ddp_report; 1438 } u; 1439 __be32 ulp_crc; 1440 __be32 ddpvld; 1441 }; 1442 1443 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1444 1445 struct cpl_rx_fcoe_ddp { 1446 RSS_HDR 1447 union opcode_tid ot; 1448 __be16 rsvd; 1449 __be16 len; 1450 __be32 seq; 1451 __be32 ddp_report; 1452 __be32 ulp_crc; 1453 __be32 ddpvld; 1454 }; 1455 1456 struct cpl_rx_data_dif { 1457 RSS_HDR 1458 union opcode_tid ot; 1459 __be16 ddp_len; 1460 __be16 msg_len; 1461 __be32 seq; 1462 union { 1463 __be32 nxt_seq; 1464 __be32 ddp_report; 1465 } u; 1466 __be32 err_vec; 1467 __be32 ddpvld; 1468 }; 1469 1470 struct cpl_rx_iscsi_dif { 1471 RSS_HDR 1472 union opcode_tid ot; 1473 __be16 ddp_len; 1474 __be16 msg_len; 1475 __be32 seq; 1476 union { 1477 __be32 nxt_seq; 1478 __be32 ddp_report; 1479 } u; 1480 __be32 ulp_crc; 1481 __be32 ddpvld; 1482 __u8 rsvd0[8]; 1483 __be32 err_vec; 1484 __u8 rsvd1[4]; 1485 }; 1486 1487 struct cpl_rx_fcoe_dif { 1488 RSS_HDR 1489 union opcode_tid ot; 1490 __be16 ddp_len; 1491 __be16 msg_len; 1492 __be32 seq; 1493 __be32 ddp_report; 1494 __be32 err_vec; 1495 __be32 ddpvld; 1496 }; 1497 1498 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1499 #define S_DDP_VALID 15 1500 #define M_DDP_VALID 0x1FFFF 1501 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1502 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1503 1504 #define S_DDP_PPOD_MISMATCH 15 1505 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1506 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1507 1508 #define S_DDP_PDU 16 1509 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1510 #define F_DDP_PDU V_DDP_PDU(1U) 1511 1512 #define S_DDP_LLIMIT_ERR 17 1513 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1514 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1515 1516 #define S_DDP_PPOD_PARITY_ERR 18 1517 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1518 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1519 1520 #define S_DDP_PADDING_ERR 19 1521 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1522 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1523 1524 #define S_DDP_HDRCRC_ERR 20 1525 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1526 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1527 1528 #define S_DDP_DATACRC_ERR 21 1529 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1530 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1531 1532 #define S_DDP_INVALID_TAG 22 1533 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1534 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1535 1536 #define S_DDP_ULIMIT_ERR 23 1537 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1538 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1539 1540 #define S_DDP_OFFSET_ERR 24 1541 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1542 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1543 1544 #define S_DDP_COLOR_ERR 25 1545 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1546 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1547 1548 #define S_DDP_TID_MISMATCH 26 1549 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1550 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1551 1552 #define S_DDP_INVALID_PPOD 27 1553 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1554 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1555 1556 #define S_DDP_ULP_MODE 28 1557 #define M_DDP_ULP_MODE 0xF 1558 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1559 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1560 1561 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1562 #define S_DDP_OFFSET 0 1563 #define M_DDP_OFFSET 0xFFFFFF 1564 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1565 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1566 1567 #define S_DDP_DACK_MODE 24 1568 #define M_DDP_DACK_MODE 0x3 1569 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1570 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1571 1572 #define S_DDP_BUF_IDX 26 1573 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1574 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1575 1576 #define S_DDP_URG 27 1577 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1578 #define F_DDP_URG V_DDP_URG(1U) 1579 1580 #define S_DDP_PSH 28 1581 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1582 #define F_DDP_PSH V_DDP_PSH(1U) 1583 1584 #define S_DDP_BUF_COMPLETE 29 1585 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1586 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1587 1588 #define S_DDP_BUF_TIMED_OUT 30 1589 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1590 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1591 1592 #define S_DDP_INV 31 1593 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1594 #define F_DDP_INV V_DDP_INV(1U) 1595 1596 struct cpl_rx_pkt { 1597 RSS_HDR 1598 __u8 opcode; 1599 #if defined(__LITTLE_ENDIAN_BITFIELD) 1600 __u8 iff:4; 1601 __u8 csum_calc:1; 1602 __u8 ipmi_pkt:1; 1603 __u8 vlan_ex:1; 1604 __u8 ip_frag:1; 1605 #else 1606 __u8 ip_frag:1; 1607 __u8 vlan_ex:1; 1608 __u8 ipmi_pkt:1; 1609 __u8 csum_calc:1; 1610 __u8 iff:4; 1611 #endif 1612 __be16 csum; 1613 __be16 vlan; 1614 __be16 len; 1615 __be32 l2info; 1616 __be16 hdr_len; 1617 __be16 err_vec; 1618 }; 1619 1620 /* rx_pkt.l2info fields */ 1621 #define S_RX_ETHHDR_LEN 0 1622 #define M_RX_ETHHDR_LEN 0x1F 1623 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1624 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1625 1626 #define S_RX_T5_ETHHDR_LEN 0 1627 #define M_RX_T5_ETHHDR_LEN 0x3F 1628 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1629 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1630 1631 #define S_RX_PKTYPE 5 1632 #define M_RX_PKTYPE 0x7 1633 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1634 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1635 1636 #define S_RX_T5_DATYPE 6 1637 #define M_RX_T5_DATYPE 0x3 1638 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1639 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1640 1641 #define S_RX_MACIDX 8 1642 #define M_RX_MACIDX 0x1FF 1643 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1644 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1645 1646 #define S_RX_T5_PKTYPE 17 1647 #define M_RX_T5_PKTYPE 0x7 1648 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1649 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1650 1651 #define S_RX_DATYPE 18 1652 #define M_RX_DATYPE 0x3 1653 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1654 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1655 1656 #define S_RXF_PSH 20 1657 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1658 #define F_RXF_PSH V_RXF_PSH(1U) 1659 1660 #define S_RXF_SYN 21 1661 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1662 #define F_RXF_SYN V_RXF_SYN(1U) 1663 1664 #define S_RXF_UDP 22 1665 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1666 #define F_RXF_UDP V_RXF_UDP(1U) 1667 1668 #define S_RXF_TCP 23 1669 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1670 #define F_RXF_TCP V_RXF_TCP(1U) 1671 1672 #define S_RXF_IP 24 1673 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1674 #define F_RXF_IP V_RXF_IP(1U) 1675 1676 #define S_RXF_IP6 25 1677 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1678 #define F_RXF_IP6 V_RXF_IP6(1U) 1679 1680 #define S_RXF_SYN_COOKIE 26 1681 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1682 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1683 1684 #define S_RXF_FCOE 26 1685 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1686 #define F_RXF_FCOE V_RXF_FCOE(1U) 1687 1688 #define S_RXF_LRO 27 1689 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1690 #define F_RXF_LRO V_RXF_LRO(1U) 1691 1692 #define S_RX_CHAN 28 1693 #define M_RX_CHAN 0xF 1694 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1695 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1696 1697 /* rx_pkt.hdr_len fields */ 1698 #define S_RX_TCPHDR_LEN 0 1699 #define M_RX_TCPHDR_LEN 0x3F 1700 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1701 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1702 1703 #define S_RX_IPHDR_LEN 6 1704 #define M_RX_IPHDR_LEN 0x3FF 1705 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1706 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1707 1708 /* rx_pkt.err_vec fields */ 1709 #define S_RXERR_OR 0 1710 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1711 #define F_RXERR_OR V_RXERR_OR(1U) 1712 1713 #define S_RXERR_MAC 1 1714 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1715 #define F_RXERR_MAC V_RXERR_MAC(1U) 1716 1717 #define S_RXERR_IPVERS 2 1718 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1719 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1720 1721 #define S_RXERR_FRAG 3 1722 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1723 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1724 1725 #define S_RXERR_ATTACK 4 1726 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1727 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1728 1729 #define S_RXERR_ETHHDR_LEN 5 1730 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1731 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1732 1733 #define S_RXERR_IPHDR_LEN 6 1734 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1735 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1736 1737 #define S_RXERR_TCPHDR_LEN 7 1738 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1739 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1740 1741 #define S_RXERR_PKT_LEN 8 1742 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1743 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1744 1745 #define S_RXERR_TCP_OPT 9 1746 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1747 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1748 1749 #define S_RXERR_IPCSUM 12 1750 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1751 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1752 1753 #define S_RXERR_CSUM 13 1754 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1755 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1756 1757 #define S_RXERR_PING 14 1758 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1759 #define F_RXERR_PING V_RXERR_PING(1U) 1760 1761 struct cpl_trace_pkt { 1762 RSS_HDR 1763 __u8 opcode; 1764 __u8 intf; 1765 #if defined(__LITTLE_ENDIAN_BITFIELD) 1766 __u8 runt:4; 1767 __u8 filter_hit:4; 1768 __u8 :6; 1769 __u8 err:1; 1770 __u8 trunc:1; 1771 #else 1772 __u8 filter_hit:4; 1773 __u8 runt:4; 1774 __u8 trunc:1; 1775 __u8 err:1; 1776 __u8 :6; 1777 #endif 1778 __be16 rsvd; 1779 __be16 len; 1780 __be64 tstamp; 1781 }; 1782 1783 struct cpl_t5_trace_pkt { 1784 RSS_HDR 1785 __u8 opcode; 1786 __u8 intf; 1787 #if defined(__LITTLE_ENDIAN_BITFIELD) 1788 __u8 runt:4; 1789 __u8 filter_hit:4; 1790 __u8 :6; 1791 __u8 err:1; 1792 __u8 trunc:1; 1793 #else 1794 __u8 filter_hit:4; 1795 __u8 runt:4; 1796 __u8 trunc:1; 1797 __u8 err:1; 1798 __u8 :6; 1799 #endif 1800 __be16 rsvd; 1801 __be16 len; 1802 __be64 tstamp; 1803 __be64 rsvd1; 1804 }; 1805 1806 struct cpl_rte_delete_req { 1807 WR_HDR; 1808 union opcode_tid ot; 1809 __be32 params; 1810 }; 1811 1812 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1813 #define S_RTE_REQ_LUT_IX 8 1814 #define M_RTE_REQ_LUT_IX 0x7FF 1815 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1816 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1817 1818 #define S_RTE_REQ_LUT_BASE 19 1819 #define M_RTE_REQ_LUT_BASE 0x7FF 1820 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1821 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1822 1823 #define S_RTE_READ_REQ_SELECT 31 1824 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1825 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1826 1827 struct cpl_rte_delete_rpl { 1828 RSS_HDR 1829 union opcode_tid ot; 1830 __u8 status; 1831 __u8 rsvd[3]; 1832 }; 1833 1834 struct cpl_rte_write_req { 1835 WR_HDR; 1836 union opcode_tid ot; 1837 __u32 write_sel; 1838 __be32 lut_params; 1839 __be32 l2t_idx; 1840 __be32 netmask; 1841 __be32 faddr; 1842 }; 1843 1844 /* cpl_rte_write_req.write_sel fields */ 1845 #define S_RTE_WR_L2TIDX 31 1846 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1847 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1848 1849 #define S_RTE_WR_FADDR 30 1850 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1851 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1852 1853 /* cpl_rte_write_req.lut_params fields */ 1854 #define S_RTE_WR_LUT_IX 10 1855 #define M_RTE_WR_LUT_IX 0x7FF 1856 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1857 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1858 1859 #define S_RTE_WR_LUT_BASE 21 1860 #define M_RTE_WR_LUT_BASE 0x7FF 1861 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1862 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1863 1864 struct cpl_rte_write_rpl { 1865 RSS_HDR 1866 union opcode_tid ot; 1867 __u8 status; 1868 __u8 rsvd[3]; 1869 }; 1870 1871 struct cpl_rte_read_req { 1872 WR_HDR; 1873 union opcode_tid ot; 1874 __be32 params; 1875 }; 1876 1877 struct cpl_rte_read_rpl { 1878 RSS_HDR 1879 union opcode_tid ot; 1880 __u8 status; 1881 __u8 rsvd; 1882 __be16 l2t_idx; 1883 #if defined(__LITTLE_ENDIAN_BITFIELD) 1884 __u32 :30; 1885 __u32 select:1; 1886 #else 1887 __u32 select:1; 1888 __u32 :30; 1889 #endif 1890 __be32 addr; 1891 }; 1892 1893 struct cpl_l2t_write_req { 1894 WR_HDR; 1895 union opcode_tid ot; 1896 __be16 params; 1897 __be16 l2t_idx; 1898 __be16 vlan; 1899 __u8 dst_mac[6]; 1900 }; 1901 1902 /* cpl_l2t_write_req.params fields */ 1903 #define S_L2T_W_INFO 2 1904 #define M_L2T_W_INFO 0x3F 1905 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1906 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1907 1908 #define S_L2T_W_PORT 8 1909 #define M_L2T_W_PORT 0xF 1910 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1911 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1912 1913 #define S_L2T_W_NOREPLY 15 1914 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1915 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1916 1917 struct cpl_l2t_write_rpl { 1918 RSS_HDR 1919 union opcode_tid ot; 1920 __u8 status; 1921 __u8 rsvd[3]; 1922 }; 1923 1924 struct cpl_l2t_read_req { 1925 WR_HDR; 1926 union opcode_tid ot; 1927 __be32 l2t_idx; 1928 }; 1929 1930 struct cpl_l2t_read_rpl { 1931 RSS_HDR 1932 union opcode_tid ot; 1933 __u8 status; 1934 #if defined(__LITTLE_ENDIAN_BITFIELD) 1935 __u8 :4; 1936 __u8 iff:4; 1937 #else 1938 __u8 iff:4; 1939 __u8 :4; 1940 #endif 1941 __be16 vlan; 1942 __be16 info; 1943 __u8 dst_mac[6]; 1944 }; 1945 1946 struct cpl_smt_write_req { 1947 WR_HDR; 1948 union opcode_tid ot; 1949 __be32 params; 1950 __be16 pfvf1; 1951 __u8 src_mac1[6]; 1952 __be16 pfvf0; 1953 __u8 src_mac0[6]; 1954 }; 1955 1956 struct cpl_smt_write_rpl { 1957 RSS_HDR 1958 union opcode_tid ot; 1959 __u8 status; 1960 __u8 rsvd[3]; 1961 }; 1962 1963 struct cpl_smt_read_req { 1964 WR_HDR; 1965 union opcode_tid ot; 1966 __be32 params; 1967 }; 1968 1969 struct cpl_smt_read_rpl { 1970 RSS_HDR 1971 union opcode_tid ot; 1972 __u8 status; 1973 __u8 ovlan_idx; 1974 __be16 rsvd; 1975 __be16 pfvf1; 1976 __u8 src_mac1[6]; 1977 __be16 pfvf0; 1978 __u8 src_mac0[6]; 1979 }; 1980 1981 /* cpl_smt_{read,write}_req.params fields */ 1982 #define S_SMTW_OVLAN_IDX 16 1983 #define M_SMTW_OVLAN_IDX 0xF 1984 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1985 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1986 1987 #define S_SMTW_IDX 20 1988 #define M_SMTW_IDX 0x7F 1989 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 1990 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 1991 1992 #define S_SMTW_NORPL 31 1993 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 1994 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 1995 1996 /* cpl_smt_{read,write}_req.pfvf? fields */ 1997 #define S_SMTW_VF 0 1998 #define M_SMTW_VF 0xFF 1999 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2000 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2001 2002 #define S_SMTW_PF 8 2003 #define M_SMTW_PF 0x7 2004 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2005 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2006 2007 #define S_SMTW_VF_VLD 11 2008 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2009 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2010 2011 struct cpl_tag_write_req { 2012 WR_HDR; 2013 union opcode_tid ot; 2014 __be32 params; 2015 __be64 tag_val; 2016 }; 2017 2018 struct cpl_tag_write_rpl { 2019 RSS_HDR 2020 union opcode_tid ot; 2021 __u8 status; 2022 __u8 rsvd[2]; 2023 __u8 idx; 2024 }; 2025 2026 struct cpl_tag_read_req { 2027 WR_HDR; 2028 union opcode_tid ot; 2029 __be32 params; 2030 }; 2031 2032 struct cpl_tag_read_rpl { 2033 RSS_HDR 2034 union opcode_tid ot; 2035 __u8 status; 2036 #if defined(__LITTLE_ENDIAN_BITFIELD) 2037 __u8 :4; 2038 __u8 tag_len:1; 2039 __u8 :2; 2040 __u8 ins_enable:1; 2041 #else 2042 __u8 ins_enable:1; 2043 __u8 :2; 2044 __u8 tag_len:1; 2045 __u8 :4; 2046 #endif 2047 __u8 rsvd; 2048 __u8 tag_idx; 2049 __be64 tag_val; 2050 }; 2051 2052 /* cpl_tag{read,write}_req.params fields */ 2053 #define S_TAGW_IDX 0 2054 #define M_TAGW_IDX 0x7F 2055 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2056 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2057 2058 #define S_TAGW_LEN 20 2059 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2060 #define F_TAGW_LEN V_TAGW_LEN(1U) 2061 2062 #define S_TAGW_INS_ENABLE 23 2063 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2064 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2065 2066 #define S_TAGW_NORPL 31 2067 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2068 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2069 2070 struct cpl_barrier { 2071 WR_HDR; 2072 __u8 opcode; 2073 __u8 chan_map; 2074 __be16 rsvd0; 2075 __be32 rsvd1; 2076 }; 2077 2078 /* cpl_barrier.chan_map fields */ 2079 #define S_CHAN_MAP 4 2080 #define M_CHAN_MAP 0xF 2081 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2082 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2083 2084 struct cpl_error { 2085 RSS_HDR 2086 union opcode_tid ot; 2087 __be32 error; 2088 }; 2089 2090 struct cpl_hit_notify { 2091 RSS_HDR 2092 union opcode_tid ot; 2093 __be32 rsvd; 2094 __be32 info; 2095 __be32 reason; 2096 }; 2097 2098 struct cpl_pkt_notify { 2099 RSS_HDR 2100 union opcode_tid ot; 2101 __be16 rsvd; 2102 __be16 len; 2103 __be32 info; 2104 __be32 reason; 2105 }; 2106 2107 /* cpl_{hit,pkt}_notify.info fields */ 2108 #define S_NTFY_MAC_IDX 0 2109 #define M_NTFY_MAC_IDX 0x1FF 2110 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2111 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2112 2113 #define S_NTFY_INTF 10 2114 #define M_NTFY_INTF 0xF 2115 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2116 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2117 2118 #define S_NTFY_TCPHDR_LEN 14 2119 #define M_NTFY_TCPHDR_LEN 0xF 2120 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2121 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2122 2123 #define S_NTFY_IPHDR_LEN 18 2124 #define M_NTFY_IPHDR_LEN 0x1FF 2125 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2126 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2127 2128 #define S_NTFY_ETHHDR_LEN 27 2129 #define M_NTFY_ETHHDR_LEN 0x1F 2130 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2131 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2132 2133 #define S_NTFY_T5_IPHDR_LEN 18 2134 #define M_NTFY_T5_IPHDR_LEN 0xFF 2135 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2136 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2137 2138 #define S_NTFY_T5_ETHHDR_LEN 26 2139 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2140 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2141 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2142 2143 struct cpl_rdma_terminate { 2144 RSS_HDR 2145 union opcode_tid ot; 2146 __be16 rsvd; 2147 __be16 len; 2148 }; 2149 2150 struct cpl_set_le_req { 2151 WR_HDR; 2152 union opcode_tid ot; 2153 __be16 reply_ctrl; 2154 __be16 params; 2155 __be64 mask_hi; 2156 __be64 mask_lo; 2157 __be64 val_hi; 2158 __be64 val_lo; 2159 }; 2160 2161 /* cpl_set_le_req.reply_ctrl additional fields */ 2162 #define S_LE_REQ_IP6 13 2163 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2164 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2165 2166 /* cpl_set_le_req.params fields */ 2167 #define S_LE_CHAN 0 2168 #define M_LE_CHAN 0x3 2169 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2170 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2171 2172 #define S_LE_OFFSET 5 2173 #define M_LE_OFFSET 0x7 2174 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2175 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2176 2177 #define S_LE_MORE 8 2178 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2179 #define F_LE_MORE V_LE_MORE(1U) 2180 2181 #define S_LE_REQSIZE 9 2182 #define M_LE_REQSIZE 0x7 2183 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2184 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2185 2186 #define S_LE_REQCMD 12 2187 #define M_LE_REQCMD 0xF 2188 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2189 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2190 2191 struct cpl_set_le_rpl { 2192 RSS_HDR 2193 union opcode_tid ot; 2194 __u8 chan; 2195 __u8 info; 2196 __be16 len; 2197 }; 2198 2199 /* cpl_set_le_rpl.info fields */ 2200 #define S_LE_RSPCMD 0 2201 #define M_LE_RSPCMD 0xF 2202 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2203 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2204 2205 #define S_LE_RSPSIZE 4 2206 #define M_LE_RSPSIZE 0x7 2207 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2208 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2209 2210 #define S_LE_RSPTYPE 7 2211 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2212 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2213 2214 struct cpl_sge_egr_update { 2215 RSS_HDR 2216 __be32 opcode_qid; 2217 __be16 cidx; 2218 __be16 pidx; 2219 }; 2220 2221 /* cpl_sge_egr_update.ot fields */ 2222 #define S_EGR_QID 0 2223 #define M_EGR_QID 0x1FFFF 2224 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2225 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2226 2227 struct cpl_fw2_pld { 2228 RSS_HDR 2229 u8 opcode; 2230 u8 rsvd[5]; 2231 __be16 len; 2232 }; 2233 2234 struct cpl_fw4_pld { 2235 RSS_HDR 2236 u8 opcode; 2237 u8 rsvd0[3]; 2238 u8 type; 2239 u8 rsvd1; 2240 __be16 len; 2241 __be64 data; 2242 __be64 rsvd2; 2243 }; 2244 2245 struct cpl_fw6_pld { 2246 RSS_HDR 2247 u8 opcode; 2248 u8 rsvd[5]; 2249 __be16 len; 2250 __be64 data[4]; 2251 }; 2252 2253 struct cpl_fw2_msg { 2254 RSS_HDR 2255 union opcode_info oi; 2256 }; 2257 2258 struct cpl_fw4_msg { 2259 RSS_HDR 2260 u8 opcode; 2261 u8 type; 2262 __be16 rsvd0; 2263 __be32 rsvd1; 2264 __be64 data[2]; 2265 }; 2266 2267 struct cpl_fw4_ack { 2268 RSS_HDR 2269 union opcode_tid ot; 2270 u8 credits; 2271 u8 rsvd0[2]; 2272 u8 flags; 2273 __be32 snd_nxt; 2274 __be32 snd_una; 2275 __be64 rsvd1; 2276 }; 2277 2278 enum { 2279 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2280 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2281 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2282 }; 2283 2284 struct cpl_fw6_msg { 2285 RSS_HDR 2286 u8 opcode; 2287 u8 type; 2288 __be16 rsvd0; 2289 __be32 rsvd1; 2290 __be64 data[4]; 2291 }; 2292 2293 /* cpl_fw6_msg.type values */ 2294 enum { 2295 FW6_TYPE_CMD_RPL = 0, 2296 FW6_TYPE_WR_RPL = 1, 2297 FW6_TYPE_CQE = 2, 2298 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2299 2300 NUM_FW6_TYPES 2301 }; 2302 2303 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2304 __u64 cookie; 2305 __be32 tid; /* or atid in case of active failure */ 2306 __u8 t_state; 2307 __u8 retval; 2308 __u8 rsvd[2]; 2309 }; 2310 2311 /* ULP_TX opcodes */ 2312 enum { 2313 ULP_TX_MEM_READ = 2, 2314 ULP_TX_MEM_WRITE = 3, 2315 ULP_TX_PKT = 4 2316 }; 2317 2318 enum { 2319 ULP_TX_SC_NOOP = 0x80, 2320 ULP_TX_SC_IMM = 0x81, 2321 ULP_TX_SC_DSGL = 0x82, 2322 ULP_TX_SC_ISGL = 0x83 2323 }; 2324 2325 #define S_ULPTX_CMD 24 2326 #define M_ULPTX_CMD 0xFF 2327 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2328 2329 #define S_ULPTX_LEN16 0 2330 #define M_ULPTX_LEN16 0xFF 2331 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2332 2333 #define S_ULP_TX_SC_MORE 23 2334 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2335 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2336 2337 struct ulptx_sge_pair { 2338 __be32 len[2]; 2339 __be64 addr[2]; 2340 }; 2341 2342 struct ulptx_sgl { 2343 __be32 cmd_nsge; 2344 __be32 len0; 2345 __be64 addr0; 2346 #if !(defined C99_NOT_SUPPORTED) 2347 struct ulptx_sge_pair sge[0]; 2348 #endif 2349 }; 2350 2351 struct ulptx_isge { 2352 __be32 stag; 2353 __be32 len; 2354 __be64 target_ofst; 2355 }; 2356 2357 struct ulptx_isgl { 2358 __be32 cmd_nisge; 2359 __be32 rsvd; 2360 #if !(defined C99_NOT_SUPPORTED) 2361 struct ulptx_isge sge[0]; 2362 #endif 2363 }; 2364 2365 struct ulptx_idata { 2366 __be32 cmd_more; 2367 __be32 len; 2368 }; 2369 2370 #define S_ULPTX_NSGE 0 2371 #define M_ULPTX_NSGE 0xFFFF 2372 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2373 2374 struct ulp_mem_io { 2375 WR_HDR; 2376 __be32 cmd; 2377 __be32 len16; /* command length */ 2378 __be32 dlen; /* data length in 32-byte units */ 2379 __be32 lock_addr; 2380 }; 2381 2382 /* additional ulp_mem_io.cmd fields */ 2383 #define S_ULP_MEMIO_ORDER 23 2384 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2385 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2386 2387 /* ulp_mem_io.lock_addr fields */ 2388 #define S_ULP_MEMIO_ADDR 0 2389 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2390 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2391 2392 #define S_ULP_MEMIO_LOCK 31 2393 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2394 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2395 2396 /* ulp_mem_io.dlen fields */ 2397 #define S_ULP_MEMIO_DATA_LEN 0 2398 #define M_ULP_MEMIO_DATA_LEN 0x1F 2399 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2400 2401 struct ulp_txpkt { 2402 __be32 cmd_dest; 2403 __be32 len; 2404 }; 2405 2406 /* ulp_txpkt.cmd_dest fields */ 2407 #define S_ULP_TXPKT_DEST 16 2408 #define M_ULP_TXPKT_DEST 0x3 2409 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2410 2411 #define S_ULP_TXPKT_FID 4 2412 #define M_ULP_TXPKT_FID 0x7ff 2413 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2414 2415 #define S_ULP_TXPKT_RO 3 2416 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2417 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2418 2419 #endif /* T4_MSG_H */ 2420