1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_CLOSE_CON_REQ = 0x8, 41 CPL_CLOSE_LISTSRV_REQ = 0x9, 42 CPL_ABORT_REQ = 0xA, 43 CPL_ABORT_RPL = 0xB, 44 CPL_TX_DATA = 0xC, 45 CPL_RX_DATA_ACK = 0xD, 46 CPL_TX_PKT = 0xE, 47 CPL_RTE_DELETE_REQ = 0xF, 48 CPL_RTE_WRITE_REQ = 0x10, 49 CPL_RTE_READ_REQ = 0x11, 50 CPL_L2T_WRITE_REQ = 0x12, 51 CPL_L2T_READ_REQ = 0x13, 52 CPL_SMT_WRITE_REQ = 0x14, 53 CPL_SMT_READ_REQ = 0x15, 54 CPL_TAG_WRITE_REQ = 0x16, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_TAG_READ_REQ = 0x1B, 58 CPL_SRQ_TABLE_REQ = 0x1C, 59 CPL_TX_PKT_FSO = 0x1E, 60 CPL_TX_DATA_ISO = 0x1F, 61 62 CPL_CLOSE_LISTSRV_RPL = 0x20, 63 CPL_ERROR = 0x21, 64 CPL_GET_TCB_RPL = 0x22, 65 CPL_L2T_WRITE_RPL = 0x23, 66 CPL_PASS_OPEN_RPL = 0x24, 67 CPL_ACT_OPEN_RPL = 0x25, 68 CPL_PEER_CLOSE = 0x26, 69 CPL_RTE_DELETE_RPL = 0x27, 70 CPL_RTE_WRITE_RPL = 0x28, 71 CPL_RX_URG_PKT = 0x29, 72 CPL_TAG_WRITE_RPL = 0x2A, 73 CPL_ABORT_REQ_RSS = 0x2B, 74 CPL_RX_URG_NOTIFY = 0x2C, 75 CPL_ABORT_RPL_RSS = 0x2D, 76 CPL_SMT_WRITE_RPL = 0x2E, 77 CPL_TX_DATA_ACK = 0x2F, 78 79 CPL_RX_PHYS_ADDR = 0x30, 80 CPL_PCMD_READ_RPL = 0x31, 81 CPL_CLOSE_CON_RPL = 0x32, 82 CPL_ISCSI_HDR = 0x33, 83 CPL_L2T_READ_RPL = 0x34, 84 CPL_RDMA_CQE = 0x35, 85 CPL_RDMA_CQE_READ_RSP = 0x36, 86 CPL_RDMA_CQE_ERR = 0x37, 87 CPL_RTE_READ_RPL = 0x38, 88 CPL_RX_DATA = 0x39, 89 CPL_SET_TCB_RPL = 0x3A, 90 CPL_RX_PKT = 0x3B, 91 CPL_TAG_READ_RPL = 0x3C, 92 CPL_HIT_NOTIFY = 0x3D, 93 CPL_PKT_NOTIFY = 0x3E, 94 CPL_RX_DDP_COMPLETE = 0x3F, 95 96 CPL_ACT_ESTABLISH = 0x40, 97 CPL_PASS_ESTABLISH = 0x41, 98 CPL_RX_DATA_DDP = 0x42, 99 CPL_SMT_READ_RPL = 0x43, 100 CPL_PASS_ACCEPT_REQ = 0x44, 101 CPL_RX_ISCSI_CMP = 0x45, 102 CPL_RX_FCOE_DDP = 0x46, 103 CPL_FCOE_HDR = 0x47, 104 CPL_T5_TRACE_PKT = 0x48, 105 CPL_RX_ISCSI_DDP = 0x49, 106 CPL_RX_FCOE_DIF = 0x4A, 107 CPL_RX_DATA_DIF = 0x4B, 108 CPL_ERR_NOTIFY = 0x4D, 109 CPL_RX_TLS_CMP = 0x4E, 110 111 CPL_RDMA_READ_REQ = 0x60, 112 CPL_RX_ISCSI_DIF = 0x60, 113 114 CPL_SET_LE_REQ = 0x80, 115 CPL_PASS_OPEN_REQ6 = 0x81, 116 CPL_ACT_OPEN_REQ6 = 0x83, 117 CPL_TX_TLS_PDU = 0x88, 118 CPL_TX_TLS_SFO = 0x89, 119 120 CPL_TX_SEC_PDU = 0x8A, 121 CPL_TX_TLS_ACK = 0x8B, 122 123 CPL_RDMA_TERMINATE = 0xA2, 124 CPL_RDMA_WRITE = 0xA4, 125 CPL_SGE_EGR_UPDATE = 0xA5, 126 CPL_SET_LE_RPL = 0xA6, 127 CPL_FW2_MSG = 0xA7, 128 CPL_FW2_PLD = 0xA8, 129 CPL_T5_RDMA_READ_REQ = 0xA9, 130 CPL_RDMA_ATOMIC_REQ = 0xAA, 131 CPL_RDMA_ATOMIC_RPL = 0xAB, 132 CPL_RDMA_IMM_DATA = 0xAC, 133 CPL_RDMA_IMM_DATA_SE = 0xAD, 134 CPL_RX_MPS_PKT = 0xAF, 135 136 CPL_TRACE_PKT = 0xB0, 137 CPL_RX2TX_DATA = 0xB1, 138 CPL_TLS_DATA = 0xB1, 139 CPL_ISCSI_DATA = 0xB2, 140 CPL_FCOE_DATA = 0xB3, 141 142 CPL_FW4_MSG = 0xC0, 143 CPL_FW4_PLD = 0xC1, 144 CPL_FW4_ACK = 0xC3, 145 CPL_SRQ_TABLE_RPL = 0xCC, 146 CPL_RX_PHYS_DSGL = 0xD0, 147 148 CPL_FW6_MSG = 0xE0, 149 CPL_FW6_PLD = 0xE1, 150 CPL_TX_TNL_LSO = 0xEC, 151 CPL_TX_PKT_LSO = 0xED, 152 CPL_TX_PKT_XT = 0xEE, 153 154 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 155 }; 156 157 enum CPL_error { 158 CPL_ERR_NONE = 0, 159 CPL_ERR_TCAM_PARITY = 1, 160 CPL_ERR_TCAM_MISS = 2, 161 CPL_ERR_TCAM_FULL = 3, 162 CPL_ERR_BAD_LENGTH = 15, 163 CPL_ERR_BAD_ROUTE = 18, 164 CPL_ERR_CONN_RESET = 20, 165 CPL_ERR_CONN_EXIST_SYNRECV = 21, 166 CPL_ERR_CONN_EXIST = 22, 167 CPL_ERR_ARP_MISS = 23, 168 CPL_ERR_BAD_SYN = 24, 169 CPL_ERR_CONN_TIMEDOUT = 30, 170 CPL_ERR_XMIT_TIMEDOUT = 31, 171 CPL_ERR_PERSIST_TIMEDOUT = 32, 172 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 173 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 174 CPL_ERR_RTX_NEG_ADVICE = 35, 175 CPL_ERR_PERSIST_NEG_ADVICE = 36, 176 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 177 CPL_ERR_WAIT_ARP_RPL = 41, 178 CPL_ERR_ABORT_FAILED = 42, 179 CPL_ERR_IWARP_FLM = 50, 180 CPL_CONTAINS_READ_RPL = 60, 181 CPL_CONTAINS_WRITE_RPL = 61, 182 }; 183 184 /* 185 * Some of the error codes above implicitly indicate that there is no TID 186 * allocated with the result of an ACT_OPEN. We use this predicate to make 187 * that explicit. 188 */ 189 static inline int act_open_has_tid(int status) 190 { 191 return (status != CPL_ERR_TCAM_PARITY && 192 status != CPL_ERR_TCAM_MISS && 193 status != CPL_ERR_TCAM_FULL && 194 status != CPL_ERR_CONN_EXIST_SYNRECV && 195 status != CPL_ERR_CONN_EXIST); 196 } 197 198 /* 199 * Convert an ACT_OPEN_RPL status to an errno. 200 */ 201 static inline int 202 act_open_rpl_status_to_errno(int status) 203 { 204 205 switch (status) { 206 case CPL_ERR_CONN_RESET: 207 return (ECONNREFUSED); 208 case CPL_ERR_ARP_MISS: 209 return (EHOSTUNREACH); 210 case CPL_ERR_CONN_TIMEDOUT: 211 return (ETIMEDOUT); 212 case CPL_ERR_TCAM_FULL: 213 return (EAGAIN); 214 case CPL_ERR_CONN_EXIST: 215 return (EAGAIN); 216 default: 217 return (EIO); 218 } 219 } 220 221 222 enum { 223 CPL_CONN_POLICY_AUTO = 0, 224 CPL_CONN_POLICY_ASK = 1, 225 CPL_CONN_POLICY_FILTER = 2, 226 CPL_CONN_POLICY_DENY = 3 227 }; 228 229 enum { 230 ULP_MODE_NONE = 0, 231 ULP_MODE_ISCSI = 2, 232 ULP_MODE_RDMA = 4, 233 ULP_MODE_TCPDDP = 5, 234 ULP_MODE_FCOE = 6, 235 ULP_MODE_TLS = 8, 236 }; 237 238 enum { 239 ULP_CRC_HEADER = 1 << 0, 240 ULP_CRC_DATA = 1 << 1 241 }; 242 243 enum { 244 CPL_PASS_OPEN_ACCEPT, 245 CPL_PASS_OPEN_REJECT, 246 CPL_PASS_OPEN_ACCEPT_TNL 247 }; 248 249 enum { 250 CPL_ABORT_SEND_RST = 0, 251 CPL_ABORT_NO_RST, 252 }; 253 254 enum { /* TX_PKT_XT checksum types */ 255 TX_CSUM_TCP = 0, 256 TX_CSUM_UDP = 1, 257 TX_CSUM_CRC16 = 4, 258 TX_CSUM_CRC32 = 5, 259 TX_CSUM_CRC32C = 6, 260 TX_CSUM_FCOE = 7, 261 TX_CSUM_TCPIP = 8, 262 TX_CSUM_UDPIP = 9, 263 TX_CSUM_TCPIP6 = 10, 264 TX_CSUM_UDPIP6 = 11, 265 TX_CSUM_IP = 12, 266 }; 267 268 enum { /* packet type in CPL_RX_PKT */ 269 PKTYPE_XACT_UCAST = 0, 270 PKTYPE_HASH_UCAST = 1, 271 PKTYPE_XACT_MCAST = 2, 272 PKTYPE_HASH_MCAST = 3, 273 PKTYPE_PROMISC = 4, 274 PKTYPE_HPROMISC = 5, 275 PKTYPE_BCAST = 6 276 }; 277 278 enum { /* DMAC type in CPL_RX_PKT */ 279 DATYPE_UCAST, 280 DATYPE_MCAST, 281 DATYPE_BCAST 282 }; 283 284 enum { /* TCP congestion control algorithms */ 285 CONG_ALG_RENO, 286 CONG_ALG_TAHOE, 287 CONG_ALG_NEWRENO, 288 CONG_ALG_HIGHSPEED 289 }; 290 291 enum { /* RSS hash type */ 292 RSS_HASH_NONE = 0, /* no hash computed */ 293 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 294 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 295 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 296 }; 297 298 enum { /* LE commands */ 299 LE_CMD_READ = 0x4, 300 LE_CMD_WRITE = 0xb 301 }; 302 303 enum { /* LE request size */ 304 LE_SZ_NONE = 0, 305 LE_SZ_33 = 1, 306 LE_SZ_66 = 2, 307 LE_SZ_132 = 3, 308 LE_SZ_264 = 4, 309 LE_SZ_528 = 5 310 }; 311 312 union opcode_tid { 313 __be32 opcode_tid; 314 __u8 opcode; 315 }; 316 317 #define S_CPL_OPCODE 24 318 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 319 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 320 #define G_TID(x) ((x) & 0xFFFFFF) 321 322 /* tid is assumed to be 24-bits */ 323 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 324 325 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 326 327 /* extract the TID from a CPL command */ 328 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 329 #define GET_OPCODE(cmd) ((cmd)->ot.opcode) 330 331 /* partitioning of TID fields that also carry a queue id */ 332 #define S_TID_TID 0 333 #define M_TID_TID 0x7ff 334 #define V_TID_TID(x) ((x) << S_TID_TID) 335 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 336 337 #define S_TID_COOKIE 11 338 #define M_TID_COOKIE 0x7 339 #define V_TID_COOKIE(x) ((x) << S_TID_COOKIE) 340 #define G_TID_COOKIE(x) (((x) >> S_TID_COOKIE) & M_TID_COOKIE) 341 342 #define S_TID_QID 14 343 #define M_TID_QID 0x3ff 344 #define V_TID_QID(x) ((x) << S_TID_QID) 345 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 346 347 union opcode_info { 348 __be64 opcode_info; 349 __u8 opcode; 350 }; 351 352 struct tcp_options { 353 __be16 mss; 354 __u8 wsf; 355 #if defined(__LITTLE_ENDIAN_BITFIELD) 356 __u8 :4; 357 __u8 unknown:1; 358 __u8 ecn:1; 359 __u8 sack:1; 360 __u8 tstamp:1; 361 #else 362 __u8 tstamp:1; 363 __u8 sack:1; 364 __u8 ecn:1; 365 __u8 unknown:1; 366 __u8 :4; 367 #endif 368 }; 369 370 struct rss_header { 371 __u8 opcode; 372 #if defined(__LITTLE_ENDIAN_BITFIELD) 373 __u8 channel:2; 374 __u8 filter_hit:1; 375 __u8 filter_tid:1; 376 __u8 hash_type:2; 377 __u8 ipv6:1; 378 __u8 send2fw:1; 379 #else 380 __u8 send2fw:1; 381 __u8 ipv6:1; 382 __u8 hash_type:2; 383 __u8 filter_tid:1; 384 __u8 filter_hit:1; 385 __u8 channel:2; 386 #endif 387 __be16 qid; 388 __be32 hash_val; 389 }; 390 391 #define S_HASHTYPE 20 392 #define M_HASHTYPE 0x3 393 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 394 395 #define S_QNUM 0 396 #define M_QNUM 0xFFFF 397 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 398 399 #if defined(RSS_HDR_VLD) || defined(CHELSIO_FW) 400 # define RSS_HDR struct rss_header rss_hdr; 401 #else 402 # define RSS_HDR 403 #endif 404 405 #ifndef CHELSIO_FW 406 struct work_request_hdr { 407 __be32 wr_hi; 408 __be32 wr_mid; 409 __be64 wr_lo; 410 }; 411 412 /* wr_mid fields */ 413 #define S_WR_LEN16 0 414 #define M_WR_LEN16 0xFF 415 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 416 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 417 418 /* wr_hi fields */ 419 #define S_WR_OP 24 420 #define M_WR_OP 0xFF 421 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 422 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 423 424 # define WR_HDR struct work_request_hdr wr 425 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 426 #else 427 # define WR_HDR 428 # define WR_HDR_SIZE 0 429 #endif 430 431 /* option 0 fields */ 432 #define S_ACCEPT_MODE 0 433 #define M_ACCEPT_MODE 0x3 434 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 435 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 436 437 #define S_TX_CHAN 2 438 #define M_TX_CHAN 0x3 439 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 440 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 441 442 #define S_NO_CONG 4 443 #define V_NO_CONG(x) ((x) << S_NO_CONG) 444 #define F_NO_CONG V_NO_CONG(1U) 445 446 #define S_DELACK 5 447 #define V_DELACK(x) ((x) << S_DELACK) 448 #define F_DELACK V_DELACK(1U) 449 450 #define S_INJECT_TIMER 6 451 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 452 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 453 454 #define S_NON_OFFLOAD 7 455 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 456 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 457 458 #define S_ULP_MODE 8 459 #define M_ULP_MODE 0xF 460 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 461 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 462 463 #define S_RCV_BUFSIZ 12 464 #define M_RCV_BUFSIZ 0x3FFU 465 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 466 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 467 468 #define S_DSCP 22 469 #define M_DSCP 0x3F 470 #define V_DSCP(x) ((x) << S_DSCP) 471 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 472 473 #define S_SMAC_SEL 28 474 #define M_SMAC_SEL 0xFF 475 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 476 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 477 478 #define S_L2T_IDX 36 479 #define M_L2T_IDX 0xFFF 480 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 481 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 482 483 #define S_TCAM_BYPASS 48 484 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 485 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 486 487 #define S_NAGLE 49 488 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 489 #define F_NAGLE V_NAGLE(1ULL) 490 491 #define S_WND_SCALE 50 492 #define M_WND_SCALE 0xF 493 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 494 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 495 496 #define S_KEEP_ALIVE 54 497 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 498 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 499 500 #define S_MAX_RT 55 501 #define M_MAX_RT 0xF 502 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 503 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 504 505 #define S_MAX_RT_OVERRIDE 59 506 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 507 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 508 509 #define S_MSS_IDX 60 510 #define M_MSS_IDX 0xF 511 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 512 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 513 514 /* option 1 fields */ 515 #define S_SYN_RSS_ENABLE 0 516 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 517 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 518 519 #define S_SYN_RSS_USE_HASH 1 520 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 521 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 522 523 #define S_SYN_RSS_QUEUE 2 524 #define M_SYN_RSS_QUEUE 0x3FF 525 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 526 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 527 528 #define S_LISTEN_INTF 12 529 #define M_LISTEN_INTF 0xFF 530 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 531 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 532 533 #define S_LISTEN_FILTER 20 534 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 535 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 536 537 #define S_SYN_DEFENSE 21 538 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 539 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 540 541 #define S_CONN_POLICY 22 542 #define M_CONN_POLICY 0x3 543 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 544 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 545 546 #define S_T5_FILT_INFO 24 547 #define M_T5_FILT_INFO 0xffffffffffULL 548 #define V_T5_FILT_INFO(x) ((x) << S_T5_FILT_INFO) 549 #define G_T5_FILT_INFO(x) (((x) >> S_T5_FILT_INFO) & M_T5_FILT_INFO) 550 551 #define S_FILT_INFO 28 552 #define M_FILT_INFO 0xfffffffffULL 553 #define V_FILT_INFO(x) ((x) << S_FILT_INFO) 554 #define G_FILT_INFO(x) (((x) >> S_FILT_INFO) & M_FILT_INFO) 555 556 /* option 2 fields */ 557 #define S_RSS_QUEUE 0 558 #define M_RSS_QUEUE 0x3FF 559 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 560 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 561 562 #define S_RSS_QUEUE_VALID 10 563 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 564 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 565 566 #define S_RX_COALESCE_VALID 11 567 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 568 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 569 570 #define S_RX_COALESCE 12 571 #define M_RX_COALESCE 0x3 572 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 573 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 574 575 #define S_CONG_CNTRL 14 576 #define M_CONG_CNTRL 0x3 577 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 578 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 579 580 #define S_PACE 16 581 #define M_PACE 0x3 582 #define V_PACE(x) ((x) << S_PACE) 583 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 584 585 #define S_CONG_CNTRL_VALID 18 586 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 587 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 588 589 #define S_T5_ISS 18 590 #define V_T5_ISS(x) ((x) << S_T5_ISS) 591 #define F_T5_ISS V_T5_ISS(1U) 592 593 #define S_PACE_VALID 19 594 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 595 #define F_PACE_VALID V_PACE_VALID(1U) 596 597 #define S_RX_FC_DISABLE 20 598 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 599 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 600 601 #define S_RX_FC_DDP 21 602 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 603 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 604 605 #define S_RX_FC_VALID 22 606 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 607 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 608 609 #define S_TX_QUEUE 23 610 #define M_TX_QUEUE 0x7 611 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 612 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 613 614 #define S_RX_CHANNEL 26 615 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 616 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 617 618 #define S_CCTRL_ECN 27 619 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 620 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 621 622 #define S_WND_SCALE_EN 28 623 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 624 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 625 626 #define S_TSTAMPS_EN 29 627 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 628 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 629 630 #define S_SACK_EN 30 631 #define V_SACK_EN(x) ((x) << S_SACK_EN) 632 #define F_SACK_EN V_SACK_EN(1U) 633 634 #define S_T5_OPT_2_VALID 31 635 #define V_T5_OPT_2_VALID(x) ((x) << S_T5_OPT_2_VALID) 636 #define F_T5_OPT_2_VALID V_T5_OPT_2_VALID(1U) 637 638 struct cpl_pass_open_req { 639 WR_HDR; 640 union opcode_tid ot; 641 __be16 local_port; 642 __be16 peer_port; 643 __be32 local_ip; 644 __be32 peer_ip; 645 __be64 opt0; 646 __be64 opt1; 647 }; 648 649 struct cpl_pass_open_req6 { 650 WR_HDR; 651 union opcode_tid ot; 652 __be16 local_port; 653 __be16 peer_port; 654 __be64 local_ip_hi; 655 __be64 local_ip_lo; 656 __be64 peer_ip_hi; 657 __be64 peer_ip_lo; 658 __be64 opt0; 659 __be64 opt1; 660 }; 661 662 struct cpl_pass_open_rpl { 663 RSS_HDR 664 union opcode_tid ot; 665 __u8 rsvd[3]; 666 __u8 status; 667 }; 668 669 struct cpl_pass_establish { 670 RSS_HDR 671 union opcode_tid ot; 672 __be32 rsvd; 673 __be32 tos_stid; 674 __be16 mac_idx; 675 __be16 tcp_opt; 676 __be32 snd_isn; 677 __be32 rcv_isn; 678 }; 679 680 /* cpl_pass_establish.tos_stid fields */ 681 #define S_PASS_OPEN_TID 0 682 #define M_PASS_OPEN_TID 0xFFFFFF 683 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 684 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 685 686 #define S_PASS_OPEN_TOS 24 687 #define M_PASS_OPEN_TOS 0xFF 688 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 689 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 690 691 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 692 #define S_TCPOPT_WSCALE_OK 5 693 #define M_TCPOPT_WSCALE_OK 0x1 694 #define V_TCPOPT_WSCALE_OK(x) ((x) << S_TCPOPT_WSCALE_OK) 695 #define G_TCPOPT_WSCALE_OK(x) (((x) >> S_TCPOPT_WSCALE_OK) & M_TCPOPT_WSCALE_OK) 696 697 #define S_TCPOPT_SACK 6 698 #define M_TCPOPT_SACK 0x1 699 #define V_TCPOPT_SACK(x) ((x) << S_TCPOPT_SACK) 700 #define G_TCPOPT_SACK(x) (((x) >> S_TCPOPT_SACK) & M_TCPOPT_SACK) 701 702 #define S_TCPOPT_TSTAMP 7 703 #define M_TCPOPT_TSTAMP 0x1 704 #define V_TCPOPT_TSTAMP(x) ((x) << S_TCPOPT_TSTAMP) 705 #define G_TCPOPT_TSTAMP(x) (((x) >> S_TCPOPT_TSTAMP) & M_TCPOPT_TSTAMP) 706 707 #define S_TCPOPT_SND_WSCALE 8 708 #define M_TCPOPT_SND_WSCALE 0xF 709 #define V_TCPOPT_SND_WSCALE(x) ((x) << S_TCPOPT_SND_WSCALE) 710 #define G_TCPOPT_SND_WSCALE(x) (((x) >> S_TCPOPT_SND_WSCALE) & M_TCPOPT_SND_WSCALE) 711 712 #define S_TCPOPT_MSS 12 713 #define M_TCPOPT_MSS 0xF 714 #define V_TCPOPT_MSS(x) ((x) << S_TCPOPT_MSS) 715 #define G_TCPOPT_MSS(x) (((x) >> S_TCPOPT_MSS) & M_TCPOPT_MSS) 716 717 struct cpl_pass_accept_req { 718 RSS_HDR 719 union opcode_tid ot; 720 __be16 rsvd; 721 __be16 len; 722 __be32 hdr_len; 723 __be16 vlan; 724 __be16 l2info; 725 __be32 tos_stid; 726 struct tcp_options tcpopt; 727 }; 728 729 /* cpl_pass_accept_req.hdr_len fields */ 730 #define S_SYN_RX_CHAN 0 731 #define M_SYN_RX_CHAN 0xF 732 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 733 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 734 735 #define S_TCP_HDR_LEN 10 736 #define M_TCP_HDR_LEN 0x3F 737 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 738 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 739 740 #define S_T6_TCP_HDR_LEN 8 741 #define V_T6_TCP_HDR_LEN(x) ((x) << S_T6_TCP_HDR_LEN) 742 #define G_T6_TCP_HDR_LEN(x) (((x) >> S_T6_TCP_HDR_LEN) & M_TCP_HDR_LEN) 743 744 #define S_IP_HDR_LEN 16 745 #define M_IP_HDR_LEN 0x3FF 746 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 747 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 748 749 #define S_T6_IP_HDR_LEN 14 750 #define V_T6_IP_HDR_LEN(x) ((x) << S_T6_IP_HDR_LEN) 751 #define G_T6_IP_HDR_LEN(x) (((x) >> S_T6_IP_HDR_LEN) & M_IP_HDR_LEN) 752 753 #define S_ETH_HDR_LEN 26 754 #define M_ETH_HDR_LEN 0x3F 755 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 756 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 757 758 #define S_T6_ETH_HDR_LEN 24 759 #define M_T6_ETH_HDR_LEN 0xFF 760 #define V_T6_ETH_HDR_LEN(x) ((x) << S_T6_ETH_HDR_LEN) 761 #define G_T6_ETH_HDR_LEN(x) (((x) >> S_T6_ETH_HDR_LEN) & M_T6_ETH_HDR_LEN) 762 763 /* cpl_pass_accept_req.l2info fields */ 764 #define S_SYN_MAC_IDX 0 765 #define M_SYN_MAC_IDX 0x1FF 766 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 767 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 768 769 #define S_SYN_XACT_MATCH 9 770 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 771 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 772 773 #define S_SYN_INTF 12 774 #define M_SYN_INTF 0xF 775 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 776 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 777 778 struct cpl_pass_accept_rpl { 779 WR_HDR; 780 union opcode_tid ot; 781 __be32 opt2; 782 __be64 opt0; 783 }; 784 785 struct cpl_t5_pass_accept_rpl { 786 WR_HDR; 787 union opcode_tid ot; 788 __be32 opt2; 789 __be64 opt0; 790 __be32 iss; 791 union { 792 __be32 rsvd; /* T5 */ 793 __be32 opt3; /* T6 */ 794 } u; 795 }; 796 797 struct cpl_act_open_req { 798 WR_HDR; 799 union opcode_tid ot; 800 __be16 local_port; 801 __be16 peer_port; 802 __be32 local_ip; 803 __be32 peer_ip; 804 __be64 opt0; 805 __be32 params; 806 __be32 opt2; 807 }; 808 809 #define S_FILTER_TUPLE 24 810 #define M_FILTER_TUPLE 0xFFFFFFFFFF 811 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE) 812 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE) 813 struct cpl_t5_act_open_req { 814 WR_HDR; 815 union opcode_tid ot; 816 __be16 local_port; 817 __be16 peer_port; 818 __be32 local_ip; 819 __be32 peer_ip; 820 __be64 opt0; 821 __be32 iss; 822 __be32 opt2; 823 __be64 params; 824 }; 825 826 struct cpl_t6_act_open_req { 827 WR_HDR; 828 union opcode_tid ot; 829 __be16 local_port; 830 __be16 peer_port; 831 __be32 local_ip; 832 __be32 peer_ip; 833 __be64 opt0; 834 __be32 iss; 835 __be32 opt2; 836 __be64 params; 837 __be32 rsvd2; 838 __be32 opt3; 839 }; 840 841 /* cpl_{t5,t6}_act_open_req.params field */ 842 #define S_AOPEN_FCOEMASK 0 843 #define V_AOPEN_FCOEMASK(x) ((x) << S_AOPEN_FCOEMASK) 844 #define F_AOPEN_FCOEMASK V_AOPEN_FCOEMASK(1U) 845 846 struct cpl_act_open_req6 { 847 WR_HDR; 848 union opcode_tid ot; 849 __be16 local_port; 850 __be16 peer_port; 851 __be64 local_ip_hi; 852 __be64 local_ip_lo; 853 __be64 peer_ip_hi; 854 __be64 peer_ip_lo; 855 __be64 opt0; 856 __be32 params; 857 __be32 opt2; 858 }; 859 860 struct cpl_t5_act_open_req6 { 861 WR_HDR; 862 union opcode_tid ot; 863 __be16 local_port; 864 __be16 peer_port; 865 __be64 local_ip_hi; 866 __be64 local_ip_lo; 867 __be64 peer_ip_hi; 868 __be64 peer_ip_lo; 869 __be64 opt0; 870 __be32 iss; 871 __be32 opt2; 872 __be64 params; 873 }; 874 875 struct cpl_t6_act_open_req6 { 876 WR_HDR; 877 union opcode_tid ot; 878 __be16 local_port; 879 __be16 peer_port; 880 __be64 local_ip_hi; 881 __be64 local_ip_lo; 882 __be64 peer_ip_hi; 883 __be64 peer_ip_lo; 884 __be64 opt0; 885 __be32 iss; 886 __be32 opt2; 887 __be64 params; 888 __be32 rsvd2; 889 __be32 opt3; 890 }; 891 892 struct cpl_act_open_rpl { 893 RSS_HDR 894 union opcode_tid ot; 895 __be32 atid_status; 896 }; 897 898 /* cpl_act_open_rpl.atid_status fields */ 899 #define S_AOPEN_STATUS 0 900 #define M_AOPEN_STATUS 0xFF 901 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 902 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 903 904 #define S_AOPEN_ATID 8 905 #define M_AOPEN_ATID 0xFFFFFF 906 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 907 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 908 909 struct cpl_act_establish { 910 RSS_HDR 911 union opcode_tid ot; 912 __be32 rsvd; 913 __be32 tos_atid; 914 __be16 mac_idx; 915 __be16 tcp_opt; 916 __be32 snd_isn; 917 __be32 rcv_isn; 918 }; 919 920 struct cpl_get_tcb { 921 WR_HDR; 922 union opcode_tid ot; 923 __be16 reply_ctrl; 924 __u8 rsvd; 925 __u8 cookie; 926 }; 927 928 /* cpl_get_tcb.reply_ctrl fields */ 929 #define S_QUEUENO 0 930 #define M_QUEUENO 0x3FF 931 #define V_QUEUENO(x) ((x) << S_QUEUENO) 932 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 933 934 #define S_REPLY_CHAN 14 935 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 936 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 937 938 #define S_NO_REPLY 15 939 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 940 #define F_NO_REPLY V_NO_REPLY(1U) 941 942 struct cpl_get_tcb_rpl { 943 RSS_HDR 944 union opcode_tid ot; 945 __u8 cookie; 946 __u8 status; 947 __be16 len; 948 }; 949 950 struct cpl_set_tcb { 951 WR_HDR; 952 union opcode_tid ot; 953 __be16 reply_ctrl; 954 __be16 cookie; 955 }; 956 957 struct cpl_set_tcb_field { 958 WR_HDR; 959 union opcode_tid ot; 960 __be16 reply_ctrl; 961 __be16 word_cookie; 962 __be64 mask; 963 __be64 val; 964 }; 965 966 struct cpl_set_tcb_field_core { 967 union opcode_tid ot; 968 __be16 reply_ctrl; 969 __be16 word_cookie; 970 __be64 mask; 971 __be64 val; 972 }; 973 974 /* cpl_set_tcb_field.word_cookie fields */ 975 #define S_WORD 0 976 #define M_WORD 0x1F 977 #define V_WORD(x) ((x) << S_WORD) 978 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 979 980 #define S_COOKIE 5 981 #define M_COOKIE 0x7 982 #define V_COOKIE(x) ((x) << S_COOKIE) 983 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 984 985 struct cpl_set_tcb_rpl { 986 RSS_HDR 987 union opcode_tid ot; 988 __be16 rsvd; 989 __u8 cookie; 990 __u8 status; 991 __be64 oldval; 992 }; 993 994 struct cpl_close_con_req { 995 WR_HDR; 996 union opcode_tid ot; 997 __be32 rsvd; 998 }; 999 1000 struct cpl_close_con_rpl { 1001 RSS_HDR 1002 union opcode_tid ot; 1003 __u8 rsvd[3]; 1004 __u8 status; 1005 __be32 snd_nxt; 1006 __be32 rcv_nxt; 1007 }; 1008 1009 struct cpl_close_listsvr_req { 1010 WR_HDR; 1011 union opcode_tid ot; 1012 __be16 reply_ctrl; 1013 __be16 rsvd; 1014 }; 1015 1016 /* additional cpl_close_listsvr_req.reply_ctrl field */ 1017 #define S_LISTSVR_IPV6 14 1018 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 1019 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 1020 1021 struct cpl_close_listsvr_rpl { 1022 RSS_HDR 1023 union opcode_tid ot; 1024 __u8 rsvd[3]; 1025 __u8 status; 1026 }; 1027 1028 struct cpl_abort_req_rss { 1029 RSS_HDR 1030 union opcode_tid ot; 1031 __u8 rsvd[3]; 1032 __u8 status; 1033 }; 1034 1035 struct cpl_abort_req_rss6 { 1036 RSS_HDR 1037 union opcode_tid ot; 1038 __u32 srqidx_status; 1039 }; 1040 1041 #define S_ABORT_RSS_STATUS 0 1042 #define M_ABORT_RSS_STATUS 0xff 1043 #define V_ABORT_RSS_STATUS(x) ((x) << S_ABORT_RSS_STATUS) 1044 #define G_ABORT_RSS_STATUS(x) (((x) >> S_ABORT_RSS_STATUS) & M_ABORT_RSS_STATUS) 1045 1046 #define S_ABORT_RSS_SRQIDX 8 1047 #define M_ABORT_RSS_SRQIDX 0xffffff 1048 #define V_ABORT_RSS_SRQIDX(x) ((x) << S_ABORT_RSS_SRQIDX) 1049 #define G_ABORT_RSS_SRQIDX(x) (((x) >> S_ABORT_RSS_SRQIDX) & M_ABORT_RSS_SRQIDX) 1050 1051 1052 /* cpl_abort_req status command code in case of T6, 1053 * bit[0] specifies whether to send RST (0) to remote peer or suppress it (1) 1054 * bit[1] indicates ABORT_REQ was sent after a CLOSE_CON_REQ 1055 * bit[2] specifies whether to disable the mmgr (1) or not (0) 1056 */ 1057 struct cpl_abort_req { 1058 WR_HDR; 1059 union opcode_tid ot; 1060 __be32 rsvd0; 1061 __u8 rsvd1; 1062 __u8 cmd; 1063 __u8 rsvd2[6]; 1064 }; 1065 1066 struct cpl_abort_req_core { 1067 union opcode_tid ot; 1068 __be32 rsvd0; 1069 __u8 rsvd1; 1070 __u8 cmd; 1071 __u8 rsvd2[6]; 1072 }; 1073 1074 struct cpl_abort_rpl_rss { 1075 RSS_HDR 1076 union opcode_tid ot; 1077 __u8 rsvd[3]; 1078 __u8 status; 1079 }; 1080 1081 struct cpl_abort_rpl_rss6 { 1082 RSS_HDR 1083 union opcode_tid ot; 1084 __u32 srqidx_status; 1085 }; 1086 1087 struct cpl_abort_rpl { 1088 WR_HDR; 1089 union opcode_tid ot; 1090 __be32 rsvd0; 1091 __u8 rsvd1; 1092 __u8 cmd; 1093 __u8 rsvd2[6]; 1094 }; 1095 1096 struct cpl_abort_rpl_core { 1097 union opcode_tid ot; 1098 __be32 rsvd0; 1099 __u8 rsvd1; 1100 __u8 cmd; 1101 __u8 rsvd2[6]; 1102 }; 1103 1104 struct cpl_peer_close { 1105 RSS_HDR 1106 union opcode_tid ot; 1107 __be32 rcv_nxt; 1108 }; 1109 1110 struct cpl_tid_release { 1111 WR_HDR; 1112 union opcode_tid ot; 1113 __be32 rsvd; 1114 }; 1115 1116 struct tx_data_wr { 1117 __be32 wr_hi; 1118 __be32 wr_lo; 1119 __be32 len; 1120 __be32 flags; 1121 __be32 sndseq; 1122 __be32 param; 1123 }; 1124 1125 /* tx_data_wr.flags fields */ 1126 #define S_TX_ACK_PAGES 21 1127 #define M_TX_ACK_PAGES 0x7 1128 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 1129 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 1130 1131 /* tx_data_wr.param fields */ 1132 #define S_TX_PORT 0 1133 #define M_TX_PORT 0x7 1134 #define V_TX_PORT(x) ((x) << S_TX_PORT) 1135 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 1136 1137 #define S_TX_MSS 4 1138 #define M_TX_MSS 0xF 1139 #define V_TX_MSS(x) ((x) << S_TX_MSS) 1140 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 1141 1142 #define S_TX_QOS 8 1143 #define M_TX_QOS 0xFF 1144 #define V_TX_QOS(x) ((x) << S_TX_QOS) 1145 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 1146 1147 #define S_TX_SNDBUF 16 1148 #define M_TX_SNDBUF 0xFFFF 1149 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 1150 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 1151 1152 struct cpl_tx_data { 1153 union opcode_tid ot; 1154 __be32 len; 1155 __be32 rsvd; 1156 __be32 flags; 1157 }; 1158 1159 /* cpl_tx_data.len fields */ 1160 #define S_TX_DATA_MSS 16 1161 #define M_TX_DATA_MSS 0xFFFF 1162 #define V_TX_DATA_MSS(x) ((x) << S_TX_DATA_MSS) 1163 #define G_TX_DATA_MSS(x) (((x) >> S_TX_DATA_MSS) & M_TX_DATA_MSS) 1164 1165 #define S_TX_LENGTH 0 1166 #define M_TX_LENGTH 0xFFFF 1167 #define V_TX_LENGTH(x) ((x) << S_TX_LENGTH) 1168 #define G_TX_LENGTH(x) (((x) >> S_TX_LENGTH) & M_TX_LENGTH) 1169 1170 /* cpl_tx_data.flags fields */ 1171 #define S_TX_PROXY 5 1172 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 1173 #define F_TX_PROXY V_TX_PROXY(1U) 1174 1175 #define S_TX_ULP_SUBMODE 6 1176 #define M_TX_ULP_SUBMODE 0xF 1177 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 1178 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 1179 1180 #define S_TX_ULP_MODE 10 1181 #define M_TX_ULP_MODE 0x7 1182 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 1183 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 1184 1185 #define S_TX_FORCE 13 1186 #define V_TX_FORCE(x) ((x) << S_TX_FORCE) 1187 #define F_TX_FORCE V_TX_FORCE(1U) 1188 1189 #define S_TX_SHOVE 14 1190 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 1191 #define F_TX_SHOVE V_TX_SHOVE(1U) 1192 1193 #define S_TX_MORE 15 1194 #define V_TX_MORE(x) ((x) << S_TX_MORE) 1195 #define F_TX_MORE V_TX_MORE(1U) 1196 1197 #define S_TX_URG 16 1198 #define V_TX_URG(x) ((x) << S_TX_URG) 1199 #define F_TX_URG V_TX_URG(1U) 1200 1201 #define S_TX_FLUSH 17 1202 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 1203 #define F_TX_FLUSH V_TX_FLUSH(1U) 1204 1205 #define S_TX_SAVE 18 1206 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 1207 #define F_TX_SAVE V_TX_SAVE(1U) 1208 1209 #define S_TX_TNL 19 1210 #define V_TX_TNL(x) ((x) << S_TX_TNL) 1211 #define F_TX_TNL V_TX_TNL(1U) 1212 1213 #define S_T6_TX_FORCE 20 1214 #define V_T6_TX_FORCE(x) ((x) << S_T6_TX_FORCE) 1215 #define F_T6_TX_FORCE V_T6_TX_FORCE(1U) 1216 1217 #define S_TX_BYPASS 21 1218 #define V_TX_BYPASS(x) ((x) << S_TX_BYPASS) 1219 #define F_TX_BYPASS V_TX_BYPASS(1U) 1220 1221 #define S_TX_PUSH 22 1222 #define V_TX_PUSH(x) ((x) << S_TX_PUSH) 1223 #define F_TX_PUSH V_TX_PUSH(1U) 1224 1225 /* additional tx_data_wr.flags fields */ 1226 #define S_TX_CPU_IDX 0 1227 #define M_TX_CPU_IDX 0x3F 1228 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 1229 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 1230 1231 #define S_TX_CLOSE 17 1232 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 1233 #define F_TX_CLOSE V_TX_CLOSE(1U) 1234 1235 #define S_TX_INIT 18 1236 #define V_TX_INIT(x) ((x) << S_TX_INIT) 1237 #define F_TX_INIT V_TX_INIT(1U) 1238 1239 #define S_TX_IMM_ACK 19 1240 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 1241 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 1242 1243 #define S_TX_IMM_DMA 20 1244 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 1245 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 1246 1247 struct cpl_tx_data_ack { 1248 RSS_HDR 1249 union opcode_tid ot; 1250 __be32 snd_una; 1251 }; 1252 1253 struct cpl_wr_ack { /* XXX */ 1254 RSS_HDR 1255 union opcode_tid ot; 1256 __be16 credits; 1257 __be16 rsvd; 1258 __be32 snd_nxt; 1259 __be32 snd_una; 1260 }; 1261 1262 struct cpl_tx_pkt_core { 1263 __be32 ctrl0; 1264 __be16 pack; 1265 __be16 len; 1266 __be64 ctrl1; 1267 }; 1268 1269 struct cpl_tx_pkt { 1270 WR_HDR; 1271 struct cpl_tx_pkt_core c; 1272 }; 1273 1274 #define cpl_tx_pkt_xt cpl_tx_pkt 1275 1276 /* cpl_tx_pkt_core.ctrl0 fields */ 1277 #define S_TXPKT_VF 0 1278 #define M_TXPKT_VF 0xFF 1279 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1280 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1281 1282 #define S_TXPKT_PF 8 1283 #define M_TXPKT_PF 0x7 1284 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1285 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1286 1287 #define S_TXPKT_VF_VLD 11 1288 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1289 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1290 1291 #define S_TXPKT_OVLAN_IDX 12 1292 #define M_TXPKT_OVLAN_IDX 0xF 1293 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1294 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1295 1296 #define S_TXPKT_T5_OVLAN_IDX 12 1297 #define M_TXPKT_T5_OVLAN_IDX 0x7 1298 #define V_TXPKT_T5_OVLAN_IDX(x) ((x) << S_TXPKT_T5_OVLAN_IDX) 1299 #define G_TXPKT_T5_OVLAN_IDX(x) (((x) >> S_TXPKT_T5_OVLAN_IDX) & \ 1300 M_TXPKT_T5_OVLAN_IDX) 1301 1302 #define S_TXPKT_INTF 16 1303 #define M_TXPKT_INTF 0xF 1304 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1305 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1306 1307 #define S_TXPKT_SPECIAL_STAT 20 1308 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1309 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1310 1311 #define S_TXPKT_T5_FCS_DIS 21 1312 #define V_TXPKT_T5_FCS_DIS(x) ((x) << S_TXPKT_T5_FCS_DIS) 1313 #define F_TXPKT_T5_FCS_DIS V_TXPKT_T5_FCS_DIS(1U) 1314 1315 #define S_TXPKT_INS_OVLAN 21 1316 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1317 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1318 1319 #define S_TXPKT_T5_INS_OVLAN 15 1320 #define V_TXPKT_T5_INS_OVLAN(x) ((x) << S_TXPKT_T5_INS_OVLAN) 1321 #define F_TXPKT_T5_INS_OVLAN V_TXPKT_T5_INS_OVLAN(1U) 1322 1323 #define S_TXPKT_STAT_DIS 22 1324 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1325 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1326 1327 #define S_TXPKT_LOOPBACK 23 1328 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1329 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1330 1331 #define S_TXPKT_TSTAMP 23 1332 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP) 1333 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U) 1334 1335 #define S_TXPKT_OPCODE 24 1336 #define M_TXPKT_OPCODE 0xFF 1337 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1338 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1339 1340 /* cpl_tx_pkt_core.ctrl1 fields */ 1341 #define S_TXPKT_SA_IDX 0 1342 #define M_TXPKT_SA_IDX 0xFFF 1343 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1344 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1345 1346 #define S_TXPKT_CSUM_END 12 1347 #define M_TXPKT_CSUM_END 0xFF 1348 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1349 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1350 1351 #define S_TXPKT_CSUM_START 20 1352 #define M_TXPKT_CSUM_START 0x3FF 1353 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1354 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1355 1356 #define S_TXPKT_IPHDR_LEN 20 1357 #define M_TXPKT_IPHDR_LEN 0x3FFF 1358 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1359 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1360 1361 #define M_T6_TXPKT_IPHDR_LEN 0xFFF 1362 #define G_T6_TXPKT_IPHDR_LEN(x) \ 1363 (((x) >> S_TXPKT_IPHDR_LEN) & M_T6_TXPKT_IPHDR_LEN) 1364 1365 #define S_TXPKT_CSUM_LOC 30 1366 #define M_TXPKT_CSUM_LOC 0x3FF 1367 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1368 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1369 1370 #define S_TXPKT_ETHHDR_LEN 34 1371 #define M_TXPKT_ETHHDR_LEN 0x3F 1372 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1373 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1374 1375 #define S_T6_TXPKT_ETHHDR_LEN 32 1376 #define M_T6_TXPKT_ETHHDR_LEN 0xFF 1377 #define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN) 1378 #define G_T6_TXPKT_ETHHDR_LEN(x) \ 1379 (((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN) 1380 1381 #define S_TXPKT_CSUM_TYPE 40 1382 #define M_TXPKT_CSUM_TYPE 0xF 1383 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1384 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1385 1386 #define S_TXPKT_VLAN 44 1387 #define M_TXPKT_VLAN 0xFFFF 1388 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1389 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1390 1391 #define S_TXPKT_VLAN_VLD 60 1392 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1393 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1394 1395 #define S_TXPKT_IPSEC 61 1396 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1397 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1398 1399 #define S_TXPKT_IPCSUM_DIS 62 1400 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1401 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1402 1403 #define S_TXPKT_L4CSUM_DIS 63 1404 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1405 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1406 1407 struct cpl_tx_pkt_lso_core { 1408 __be32 lso_ctrl; 1409 __be16 ipid_ofst; 1410 __be16 mss; 1411 __be32 seqno_offset; 1412 __be32 len; 1413 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1414 }; 1415 1416 struct cpl_tx_pkt_lso { 1417 WR_HDR; 1418 struct cpl_tx_pkt_lso_core c; 1419 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1420 }; 1421 1422 struct cpl_tx_pkt_ufo_core { 1423 __be16 ethlen; 1424 __be16 iplen; 1425 __be16 udplen; 1426 __be16 mss; 1427 __be32 len; 1428 __be32 r1; 1429 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1430 }; 1431 1432 struct cpl_tx_pkt_ufo { 1433 WR_HDR; 1434 struct cpl_tx_pkt_ufo_core c; 1435 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1436 }; 1437 1438 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 1439 #define S_LSO_TCPHDR_LEN 0 1440 #define M_LSO_TCPHDR_LEN 0xF 1441 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1442 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1443 1444 #define S_LSO_IPHDR_LEN 4 1445 #define M_LSO_IPHDR_LEN 0xFFF 1446 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1447 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1448 1449 #define S_LSO_ETHHDR_LEN 16 1450 #define M_LSO_ETHHDR_LEN 0xF 1451 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1452 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1453 1454 #define S_LSO_IPV6 20 1455 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1456 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1457 1458 #define S_LSO_OFLD_ENCAP 21 1459 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1460 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1461 1462 #define S_LSO_LAST_SLICE 22 1463 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1464 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1465 1466 #define S_LSO_FIRST_SLICE 23 1467 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1468 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1469 1470 #define S_LSO_OPCODE 24 1471 #define M_LSO_OPCODE 0xFF 1472 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1473 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1474 1475 #define S_LSO_T5_XFER_SIZE 0 1476 #define M_LSO_T5_XFER_SIZE 0xFFFFFFF 1477 #define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE) 1478 #define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE) 1479 1480 /* cpl_tx_pkt_lso_core.mss fields */ 1481 #define S_LSO_MSS 0 1482 #define M_LSO_MSS 0x3FFF 1483 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1484 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1485 1486 #define S_LSO_IPID_SPLIT 15 1487 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1488 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1489 1490 struct cpl_tx_pkt_fso { 1491 WR_HDR; 1492 __be32 fso_ctrl; 1493 __be16 seqcnt_ofst; 1494 __be16 mtu; 1495 __be32 param_offset; 1496 __be32 len; 1497 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */ 1498 }; 1499 1500 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */ 1501 #define S_FSO_XCHG_CLASS 21 1502 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS) 1503 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U) 1504 1505 #define S_FSO_INITIATOR 20 1506 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR) 1507 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U) 1508 1509 #define S_FSO_FCHDR_LEN 12 1510 #define M_FSO_FCHDR_LEN 0xF 1511 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN) 1512 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN) 1513 1514 struct cpl_iscsi_hdr_no_rss { 1515 union opcode_tid ot; 1516 __be16 pdu_len_ddp; 1517 __be16 len; 1518 __be32 seq; 1519 __be16 urg; 1520 __u8 rsvd; 1521 __u8 status; 1522 }; 1523 1524 struct cpl_tx_data_iso { 1525 __be32 op_to_scsi; 1526 __u8 reserved1; 1527 __u8 ahs_len; 1528 __be16 mpdu; 1529 __be32 burst_size; 1530 __be32 len; 1531 __be32 reserved2_seglen_offset; 1532 __be32 datasn_offset; 1533 __be32 buffer_offset; 1534 __be32 reserved3; 1535 1536 /* encapsulated CPL_TX_DATA follows here */ 1537 }; 1538 1539 /* cpl_tx_data_iso.op_to_scsi fields */ 1540 #define S_CPL_TX_DATA_ISO_OP 24 1541 #define M_CPL_TX_DATA_ISO_OP 0xff 1542 #define V_CPL_TX_DATA_ISO_OP(x) ((x) << S_CPL_TX_DATA_ISO_OP) 1543 #define G_CPL_TX_DATA_ISO_OP(x) \ 1544 (((x) >> S_CPL_TX_DATA_ISO_OP) & M_CPL_TX_DATA_ISO_OP) 1545 1546 #define S_CPL_TX_DATA_ISO_FIRST 23 1547 #define M_CPL_TX_DATA_ISO_FIRST 0x1 1548 #define V_CPL_TX_DATA_ISO_FIRST(x) ((x) << S_CPL_TX_DATA_ISO_FIRST) 1549 #define G_CPL_TX_DATA_ISO_FIRST(x) \ 1550 (((x) >> S_CPL_TX_DATA_ISO_FIRST) & M_CPL_TX_DATA_ISO_FIRST) 1551 #define F_CPL_TX_DATA_ISO_FIRST V_CPL_TX_DATA_ISO_FIRST(1U) 1552 1553 #define S_CPL_TX_DATA_ISO_LAST 22 1554 #define M_CPL_TX_DATA_ISO_LAST 0x1 1555 #define V_CPL_TX_DATA_ISO_LAST(x) ((x) << S_CPL_TX_DATA_ISO_LAST) 1556 #define G_CPL_TX_DATA_ISO_LAST(x) \ 1557 (((x) >> S_CPL_TX_DATA_ISO_LAST) & M_CPL_TX_DATA_ISO_LAST) 1558 #define F_CPL_TX_DATA_ISO_LAST V_CPL_TX_DATA_ISO_LAST(1U) 1559 1560 #define S_CPL_TX_DATA_ISO_CPLHDRLEN 21 1561 #define M_CPL_TX_DATA_ISO_CPLHDRLEN 0x1 1562 #define V_CPL_TX_DATA_ISO_CPLHDRLEN(x) ((x) << S_CPL_TX_DATA_ISO_CPLHDRLEN) 1563 #define G_CPL_TX_DATA_ISO_CPLHDRLEN(x) \ 1564 (((x) >> S_CPL_TX_DATA_ISO_CPLHDRLEN) & M_CPL_TX_DATA_ISO_CPLHDRLEN) 1565 #define F_CPL_TX_DATA_ISO_CPLHDRLEN V_CPL_TX_DATA_ISO_CPLHDRLEN(1U) 1566 1567 #define S_CPL_TX_DATA_ISO_HDRCRC 20 1568 #define M_CPL_TX_DATA_ISO_HDRCRC 0x1 1569 #define V_CPL_TX_DATA_ISO_HDRCRC(x) ((x) << S_CPL_TX_DATA_ISO_HDRCRC) 1570 #define G_CPL_TX_DATA_ISO_HDRCRC(x) \ 1571 (((x) >> S_CPL_TX_DATA_ISO_HDRCRC) & M_CPL_TX_DATA_ISO_HDRCRC) 1572 #define F_CPL_TX_DATA_ISO_HDRCRC V_CPL_TX_DATA_ISO_HDRCRC(1U) 1573 1574 #define S_CPL_TX_DATA_ISO_PLDCRC 19 1575 #define M_CPL_TX_DATA_ISO_PLDCRC 0x1 1576 #define V_CPL_TX_DATA_ISO_PLDCRC(x) ((x) << S_CPL_TX_DATA_ISO_PLDCRC) 1577 #define G_CPL_TX_DATA_ISO_PLDCRC(x) \ 1578 (((x) >> S_CPL_TX_DATA_ISO_PLDCRC) & M_CPL_TX_DATA_ISO_PLDCRC) 1579 #define F_CPL_TX_DATA_ISO_PLDCRC V_CPL_TX_DATA_ISO_PLDCRC(1U) 1580 1581 #define S_CPL_TX_DATA_ISO_IMMEDIATE 18 1582 #define M_CPL_TX_DATA_ISO_IMMEDIATE 0x1 1583 #define V_CPL_TX_DATA_ISO_IMMEDIATE(x) ((x) << S_CPL_TX_DATA_ISO_IMMEDIATE) 1584 #define G_CPL_TX_DATA_ISO_IMMEDIATE(x) \ 1585 (((x) >> S_CPL_TX_DATA_ISO_IMMEDIATE) & M_CPL_TX_DATA_ISO_IMMEDIATE) 1586 #define F_CPL_TX_DATA_ISO_IMMEDIATE V_CPL_TX_DATA_ISO_IMMEDIATE(1U) 1587 1588 #define S_CPL_TX_DATA_ISO_SCSI 16 1589 #define M_CPL_TX_DATA_ISO_SCSI 0x3 1590 #define V_CPL_TX_DATA_ISO_SCSI(x) ((x) << S_CPL_TX_DATA_ISO_SCSI) 1591 #define G_CPL_TX_DATA_ISO_SCSI(x) \ 1592 (((x) >> S_CPL_TX_DATA_ISO_SCSI) & M_CPL_TX_DATA_ISO_SCSI) 1593 1594 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1595 #define S_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0 1596 #define M_CPL_TX_DATA_ISO_SEGLEN_OFFSET 0xffffff 1597 #define V_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1598 ((x) << S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1599 #define G_CPL_TX_DATA_ISO_SEGLEN_OFFSET(x) \ 1600 (((x) >> S_CPL_TX_DATA_ISO_SEGLEN_OFFSET) & \ 1601 M_CPL_TX_DATA_ISO_SEGLEN_OFFSET) 1602 1603 struct cpl_iscsi_hdr { 1604 RSS_HDR 1605 union opcode_tid ot; 1606 __be16 pdu_len_ddp; 1607 __be16 len; 1608 __be32 seq; 1609 __be16 urg; 1610 __u8 rsvd; 1611 __u8 status; 1612 }; 1613 1614 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1615 #define S_ISCSI_PDU_LEN 0 1616 #define M_ISCSI_PDU_LEN 0x7FFF 1617 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1618 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1619 1620 #define S_ISCSI_DDP 15 1621 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1622 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1623 1624 struct cpl_iscsi_data { 1625 RSS_HDR 1626 union opcode_tid ot; 1627 __u8 rsvd0[2]; 1628 __be16 len; 1629 __be32 seq; 1630 __be16 urg; 1631 __u8 rsvd1; 1632 __u8 status; 1633 }; 1634 1635 struct cpl_rx_data { 1636 RSS_HDR 1637 union opcode_tid ot; 1638 __be16 rsvd; 1639 __be16 len; 1640 __be32 seq; 1641 __be16 urg; 1642 #if defined(__LITTLE_ENDIAN_BITFIELD) 1643 __u8 dack_mode:2; 1644 __u8 psh:1; 1645 __u8 heartbeat:1; 1646 __u8 ddp_off:1; 1647 __u8 :3; 1648 #else 1649 __u8 :3; 1650 __u8 ddp_off:1; 1651 __u8 heartbeat:1; 1652 __u8 psh:1; 1653 __u8 dack_mode:2; 1654 #endif 1655 __u8 status; 1656 }; 1657 1658 struct cpl_fcoe_hdr { 1659 RSS_HDR 1660 union opcode_tid ot; 1661 __be16 oxid; 1662 __be16 len; 1663 __be32 rctl_fctl; 1664 __u8 cs_ctl; 1665 __u8 df_ctl; 1666 __u8 sof; 1667 __u8 eof; 1668 __be16 seq_cnt; 1669 __u8 seq_id; 1670 __u8 type; 1671 __be32 param; 1672 }; 1673 1674 /* cpl_fcoe_hdr.rctl_fctl fields */ 1675 #define S_FCOE_FCHDR_RCTL 24 1676 #define M_FCOE_FCHDR_RCTL 0xff 1677 #define V_FCOE_FCHDR_RCTL(x) ((x) << S_FCOE_FCHDR_RCTL) 1678 #define G_FCOE_FCHDR_RCTL(x) \ 1679 (((x) >> S_FCOE_FCHDR_RCTL) & M_FCOE_FCHDR_RCTL) 1680 1681 #define S_FCOE_FCHDR_FCTL 0 1682 #define M_FCOE_FCHDR_FCTL 0xffffff 1683 #define V_FCOE_FCHDR_FCTL(x) ((x) << S_FCOE_FCHDR_FCTL) 1684 #define G_FCOE_FCHDR_FCTL(x) \ 1685 (((x) >> S_FCOE_FCHDR_FCTL) & M_FCOE_FCHDR_FCTL) 1686 1687 struct cpl_fcoe_data { 1688 RSS_HDR 1689 union opcode_tid ot; 1690 __u8 rsvd0[2]; 1691 __be16 len; 1692 __be32 seq; 1693 __u8 rsvd1[3]; 1694 __u8 status; 1695 }; 1696 1697 struct cpl_rx_urg_notify { 1698 RSS_HDR 1699 union opcode_tid ot; 1700 __be32 seq; 1701 }; 1702 1703 struct cpl_rx_urg_pkt { 1704 RSS_HDR 1705 union opcode_tid ot; 1706 __be16 rsvd; 1707 __be16 len; 1708 }; 1709 1710 struct cpl_rx_data_ack { 1711 WR_HDR; 1712 union opcode_tid ot; 1713 __be32 credit_dack; 1714 }; 1715 1716 struct cpl_rx_data_ack_core { 1717 union opcode_tid ot; 1718 __be32 credit_dack; 1719 }; 1720 1721 /* cpl_rx_data_ack.ack_seq fields */ 1722 #define S_RX_CREDITS 0 1723 #define M_RX_CREDITS 0x3FFFFFF 1724 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1725 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1726 1727 #define S_RX_MODULATE_TX 26 1728 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1729 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1730 1731 #define S_RX_MODULATE_RX 27 1732 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1733 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1734 1735 #define S_RX_FORCE_ACK 28 1736 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1737 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1738 1739 #define S_RX_DACK_MODE 29 1740 #define M_RX_DACK_MODE 0x3 1741 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1742 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1743 1744 #define S_RX_DACK_CHANGE 31 1745 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1746 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1747 1748 struct cpl_rx_ddp_complete { 1749 RSS_HDR 1750 union opcode_tid ot; 1751 __be32 ddp_report; 1752 __be32 rcv_nxt; 1753 __be32 rsvd; 1754 }; 1755 1756 struct cpl_rx_data_ddp { 1757 RSS_HDR 1758 union opcode_tid ot; 1759 __be16 urg; 1760 __be16 len; 1761 __be32 seq; 1762 union { 1763 __be32 nxt_seq; 1764 __be32 ddp_report; 1765 } u; 1766 __be32 ulp_crc; 1767 __be32 ddpvld; 1768 }; 1769 1770 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 1771 1772 struct cpl_rx_fcoe_ddp { 1773 RSS_HDR 1774 union opcode_tid ot; 1775 __be16 rsvd; 1776 __be16 len; 1777 __be32 seq; 1778 __be32 ddp_report; 1779 __be32 ulp_crc; 1780 __be32 ddpvld; 1781 }; 1782 1783 struct cpl_rx_data_dif { 1784 RSS_HDR 1785 union opcode_tid ot; 1786 __be16 ddp_len; 1787 __be16 msg_len; 1788 __be32 seq; 1789 union { 1790 __be32 nxt_seq; 1791 __be32 ddp_report; 1792 } u; 1793 __be32 err_vec; 1794 __be32 ddpvld; 1795 }; 1796 1797 struct cpl_rx_iscsi_dif { 1798 RSS_HDR 1799 union opcode_tid ot; 1800 __be16 ddp_len; 1801 __be16 msg_len; 1802 __be32 seq; 1803 union { 1804 __be32 nxt_seq; 1805 __be32 ddp_report; 1806 } u; 1807 __be32 ulp_crc; 1808 __be32 ddpvld; 1809 __u8 rsvd0[8]; 1810 __be32 err_vec; 1811 __u8 rsvd1[4]; 1812 }; 1813 1814 struct cpl_rx_iscsi_cmp { 1815 RSS_HDR 1816 union opcode_tid ot; 1817 __be16 pdu_len_ddp; 1818 __be16 len; 1819 __be32 seq; 1820 __be16 urg; 1821 __u8 rsvd; 1822 __u8 status; 1823 __be32 ulp_crc; 1824 __be32 ddpvld; 1825 }; 1826 1827 struct cpl_rx_fcoe_dif { 1828 RSS_HDR 1829 union opcode_tid ot; 1830 __be16 ddp_len; 1831 __be16 msg_len; 1832 __be32 seq; 1833 __be32 ddp_report; 1834 __be32 err_vec; 1835 __be32 ddpvld; 1836 }; 1837 1838 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */ 1839 #define S_DDP_VALID 15 1840 #define M_DDP_VALID 0x1FFFF 1841 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1842 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1843 1844 #define S_DDP_PPOD_MISMATCH 15 1845 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1846 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1847 1848 #define S_DDP_PDU 16 1849 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1850 #define F_DDP_PDU V_DDP_PDU(1U) 1851 1852 #define S_DDP_LLIMIT_ERR 17 1853 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1854 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1855 1856 #define S_DDP_PPOD_PARITY_ERR 18 1857 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1858 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1859 1860 #define S_DDP_PADDING_ERR 19 1861 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1862 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1863 1864 #define S_DDP_HDRCRC_ERR 20 1865 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1866 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1867 1868 #define S_DDP_DATACRC_ERR 21 1869 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1870 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1871 1872 #define S_DDP_INVALID_TAG 22 1873 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1874 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1875 1876 #define S_DDP_ULIMIT_ERR 23 1877 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1878 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1879 1880 #define S_DDP_OFFSET_ERR 24 1881 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1882 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1883 1884 #define S_DDP_COLOR_ERR 25 1885 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1886 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1887 1888 #define S_DDP_TID_MISMATCH 26 1889 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1890 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1891 1892 #define S_DDP_INVALID_PPOD 27 1893 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1894 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1895 1896 #define S_DDP_ULP_MODE 28 1897 #define M_DDP_ULP_MODE 0xF 1898 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1899 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1900 1901 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */ 1902 #define S_DDP_OFFSET 0 1903 #define M_DDP_OFFSET 0xFFFFFF 1904 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1905 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1906 1907 #define S_DDP_DACK_MODE 24 1908 #define M_DDP_DACK_MODE 0x3 1909 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1910 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1911 1912 #define S_DDP_BUF_IDX 26 1913 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1914 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1915 1916 #define S_DDP_URG 27 1917 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1918 #define F_DDP_URG V_DDP_URG(1U) 1919 1920 #define S_DDP_PSH 28 1921 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1922 #define F_DDP_PSH V_DDP_PSH(1U) 1923 1924 #define S_DDP_BUF_COMPLETE 29 1925 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1926 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1927 1928 #define S_DDP_BUF_TIMED_OUT 30 1929 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1930 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1931 1932 #define S_DDP_INV 31 1933 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1934 #define F_DDP_INV V_DDP_INV(1U) 1935 1936 struct cpl_rx_pkt { 1937 RSS_HDR 1938 __u8 opcode; 1939 #if defined(__LITTLE_ENDIAN_BITFIELD) 1940 __u8 iff:4; 1941 __u8 csum_calc:1; 1942 __u8 ipmi_pkt:1; 1943 __u8 vlan_ex:1; 1944 __u8 ip_frag:1; 1945 #else 1946 __u8 ip_frag:1; 1947 __u8 vlan_ex:1; 1948 __u8 ipmi_pkt:1; 1949 __u8 csum_calc:1; 1950 __u8 iff:4; 1951 #endif 1952 __be16 csum; 1953 __be16 vlan; 1954 __be16 len; 1955 __be32 l2info; 1956 __be16 hdr_len; 1957 __be16 err_vec; 1958 }; 1959 1960 /* rx_pkt.l2info fields */ 1961 #define S_RX_ETHHDR_LEN 0 1962 #define M_RX_ETHHDR_LEN 0x1F 1963 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1964 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1965 1966 #define S_RX_T5_ETHHDR_LEN 0 1967 #define M_RX_T5_ETHHDR_LEN 0x3F 1968 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN) 1969 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN) 1970 1971 #define M_RX_T6_ETHHDR_LEN 0xFF 1972 #define G_RX_T6_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_T6_ETHHDR_LEN) 1973 1974 #define S_RX_PKTYPE 5 1975 #define M_RX_PKTYPE 0x7 1976 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1977 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1978 1979 #define S_RX_T5_DATYPE 6 1980 #define M_RX_T5_DATYPE 0x3 1981 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE) 1982 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE) 1983 1984 #define S_RX_MACIDX 8 1985 #define M_RX_MACIDX 0x1FF 1986 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1987 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1988 1989 #define S_RX_T5_PKTYPE 17 1990 #define M_RX_T5_PKTYPE 0x7 1991 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE) 1992 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE) 1993 1994 #define S_RX_DATYPE 18 1995 #define M_RX_DATYPE 0x3 1996 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1997 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1998 1999 #define S_RXF_PSH 20 2000 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 2001 #define F_RXF_PSH V_RXF_PSH(1U) 2002 2003 #define S_RXF_SYN 21 2004 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 2005 #define F_RXF_SYN V_RXF_SYN(1U) 2006 2007 #define S_RXF_UDP 22 2008 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 2009 #define F_RXF_UDP V_RXF_UDP(1U) 2010 2011 #define S_RXF_TCP 23 2012 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 2013 #define F_RXF_TCP V_RXF_TCP(1U) 2014 2015 #define S_RXF_IP 24 2016 #define V_RXF_IP(x) ((x) << S_RXF_IP) 2017 #define F_RXF_IP V_RXF_IP(1U) 2018 2019 #define S_RXF_IP6 25 2020 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 2021 #define F_RXF_IP6 V_RXF_IP6(1U) 2022 2023 #define S_RXF_SYN_COOKIE 26 2024 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 2025 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 2026 2027 #define S_RXF_FCOE 26 2028 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 2029 #define F_RXF_FCOE V_RXF_FCOE(1U) 2030 2031 #define S_RXF_LRO 27 2032 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 2033 #define F_RXF_LRO V_RXF_LRO(1U) 2034 2035 #define S_RX_CHAN 28 2036 #define M_RX_CHAN 0xF 2037 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 2038 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 2039 2040 /* rx_pkt.hdr_len fields */ 2041 #define S_RX_TCPHDR_LEN 0 2042 #define M_RX_TCPHDR_LEN 0x3F 2043 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 2044 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 2045 2046 #define S_RX_IPHDR_LEN 6 2047 #define M_RX_IPHDR_LEN 0x3FF 2048 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 2049 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 2050 2051 /* rx_pkt.err_vec fields */ 2052 #define S_RXERR_OR 0 2053 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 2054 #define F_RXERR_OR V_RXERR_OR(1U) 2055 2056 #define S_RXERR_MAC 1 2057 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 2058 #define F_RXERR_MAC V_RXERR_MAC(1U) 2059 2060 #define S_RXERR_IPVERS 2 2061 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 2062 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 2063 2064 #define S_RXERR_FRAG 3 2065 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 2066 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 2067 2068 #define S_RXERR_ATTACK 4 2069 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 2070 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 2071 2072 #define S_RXERR_ETHHDR_LEN 5 2073 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 2074 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 2075 2076 #define S_RXERR_IPHDR_LEN 6 2077 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 2078 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 2079 2080 #define S_RXERR_TCPHDR_LEN 7 2081 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 2082 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 2083 2084 #define S_RXERR_PKT_LEN 8 2085 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 2086 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 2087 2088 #define S_RXERR_TCP_OPT 9 2089 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 2090 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 2091 2092 #define S_RXERR_IPCSUM 12 2093 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 2094 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 2095 2096 #define S_RXERR_CSUM 13 2097 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 2098 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 2099 2100 #define S_RXERR_PING 14 2101 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 2102 #define F_RXERR_PING V_RXERR_PING(1U) 2103 2104 /* In T6, rx_pkt.err_vec indicates 2105 * RxError Error vector (16b) or 2106 * Encapsulating header length (8b), 2107 * Outer encapsulation type (2b) and 2108 * compressed error vector (6b) if CRxPktEnc is 2109 * enabled in TP_OUT_CONFIG 2110 */ 2111 2112 #define S_T6_COMPR_RXERR_VEC 0 2113 #define M_T6_COMPR_RXERR_VEC 0x3F 2114 #define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC) 2115 #define G_T6_COMPR_RXERR_VEC(x) \ 2116 (((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC) 2117 2118 #define S_T6_COMPR_RXERR_MAC 0 2119 #define V_T6_COMPR_RXERR_MAC(x) ((x) << S_T6_COMPR_RXERR_MAC) 2120 #define F_T6_COMPR_RXERR_MAC V_T6_COMPR_RXERR_MAC(1U) 2121 2122 /* Logical OR of RX_ERROR_PKT_LEN, RX_ERROR_TCP_HDR_LEN 2123 * RX_ERROR_IP_HDR_LEN, RX_ERROR_ETH_HDR_LEN 2124 */ 2125 #define S_T6_COMPR_RXERR_LEN 1 2126 #define V_T6_COMPR_RXERR_LEN(x) ((x) << S_T6_COMPR_RXERR_LEN) 2127 #define F_T6_COMPR_RXERR_LEN V_COMPR_T6_RXERR_LEN(1U) 2128 2129 #define S_T6_COMPR_RXERR_TCP_OPT 2 2130 #define V_T6_COMPR_RXERR_TCP_OPT(x) ((x) << S_T6_COMPR_RXERR_TCP_OPT) 2131 #define F_T6_COMPR_RXERR_TCP_OPT V_T6_COMPR_RXERR_TCP_OPT(1U) 2132 2133 #define S_T6_COMPR_RXERR_IPV6_EXT 3 2134 #define V_T6_COMPR_RXERR_IPV6_EXT(x) ((x) << S_T6_COMPR_RXERR_IPV6_EXT) 2135 #define F_T6_COMPR_RXERR_IPV6_EXT V_T6_COMPR_RXERR_IPV6_EXT(1U) 2136 2137 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 2138 #define S_T6_COMPR_RXERR_SUM 4 2139 #define V_T6_COMPR_RXERR_SUM(x) ((x) << S_T6_COMPR_RXERR_SUM) 2140 #define F_T6_COMPR_RXERR_SUM V_T6_COMPR_RXERR_SUM(1U) 2141 2142 /* Logical OR of RX_ERROR_FPMA, RX_ERROR_PING_DROP, 2143 * RX_ERROR_ATTACK, RX_ERROR_FRAG,RX_ERROR_IPVERSION 2144 */ 2145 #define S_T6_COMPR_RXERR_MISC 5 2146 #define V_T6_COMPR_RXERR_MISC(x) ((x) << S_T6_COMPR_RXERR_MISC) 2147 #define F_T6_COMPR_RXERR_MISC V_T6_COMPR_RXERR_MISC(1U) 2148 2149 #define S_T6_RX_TNL_TYPE 6 2150 #define M_T6_RX_TNL_TYPE 0x3 2151 #define V_T6_RX_TNL_TYPE(x) ((x) << S_T6_RX_TNL_TYPE) 2152 #define G_T6_RX_TNL_TYPE(x) (((x) >> S_T6_RX_TNL_TYPE) & M_T6_RX_TNL_TYPE) 2153 2154 #define RX_PKT_TNL_TYPE_NVGRE 1 2155 #define RX_PKT_TNL_TYPE_VXLAN 2 2156 #define RX_PKT_TNL_TYPE_GENEVE 3 2157 2158 #define S_T6_RX_TNLHDR_LEN 8 2159 #define M_T6_RX_TNLHDR_LEN 0xFF 2160 #define V_T6_RX_TNLHDR_LEN(x) ((x) << S_T6_RX_TNLHDR_LEN) 2161 #define G_T6_RX_TNLHDR_LEN(x) (((x) >> S_T6_RX_TNLHDR_LEN) & M_T6_RX_TNLHDR_LEN) 2162 2163 struct cpl_trace_pkt { 2164 RSS_HDR 2165 __u8 opcode; 2166 __u8 intf; 2167 #if defined(__LITTLE_ENDIAN_BITFIELD) 2168 __u8 runt:4; 2169 __u8 filter_hit:4; 2170 __u8 :6; 2171 __u8 err:1; 2172 __u8 trunc:1; 2173 #else 2174 __u8 filter_hit:4; 2175 __u8 runt:4; 2176 __u8 trunc:1; 2177 __u8 err:1; 2178 __u8 :6; 2179 #endif 2180 __be16 rsvd; 2181 __be16 len; 2182 __be64 tstamp; 2183 }; 2184 2185 struct cpl_t5_trace_pkt { 2186 RSS_HDR 2187 __u8 opcode; 2188 __u8 intf; 2189 #if defined(__LITTLE_ENDIAN_BITFIELD) 2190 __u8 runt:4; 2191 __u8 filter_hit:4; 2192 __u8 :6; 2193 __u8 err:1; 2194 __u8 trunc:1; 2195 #else 2196 __u8 filter_hit:4; 2197 __u8 runt:4; 2198 __u8 trunc:1; 2199 __u8 err:1; 2200 __u8 :6; 2201 #endif 2202 __be16 rsvd; 2203 __be16 len; 2204 __be64 tstamp; 2205 __be64 rsvd1; 2206 }; 2207 2208 struct cpl_rte_delete_req { 2209 WR_HDR; 2210 union opcode_tid ot; 2211 __be32 params; 2212 }; 2213 2214 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 2215 #define S_RTE_REQ_LUT_IX 8 2216 #define M_RTE_REQ_LUT_IX 0x7FF 2217 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 2218 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 2219 2220 #define S_RTE_REQ_LUT_BASE 19 2221 #define M_RTE_REQ_LUT_BASE 0x7FF 2222 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 2223 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 2224 2225 #define S_RTE_READ_REQ_SELECT 31 2226 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 2227 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 2228 2229 struct cpl_rte_delete_rpl { 2230 RSS_HDR 2231 union opcode_tid ot; 2232 __u8 status; 2233 __u8 rsvd[3]; 2234 }; 2235 2236 struct cpl_rte_write_req { 2237 WR_HDR; 2238 union opcode_tid ot; 2239 __u32 write_sel; 2240 __be32 lut_params; 2241 __be32 l2t_idx; 2242 __be32 netmask; 2243 __be32 faddr; 2244 }; 2245 2246 /* cpl_rte_write_req.write_sel fields */ 2247 #define S_RTE_WR_L2TIDX 31 2248 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 2249 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 2250 2251 #define S_RTE_WR_FADDR 30 2252 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 2253 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 2254 2255 /* cpl_rte_write_req.lut_params fields */ 2256 #define S_RTE_WR_LUT_IX 10 2257 #define M_RTE_WR_LUT_IX 0x7FF 2258 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 2259 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 2260 2261 #define S_RTE_WR_LUT_BASE 21 2262 #define M_RTE_WR_LUT_BASE 0x7FF 2263 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 2264 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 2265 2266 struct cpl_rte_write_rpl { 2267 RSS_HDR 2268 union opcode_tid ot; 2269 __u8 status; 2270 __u8 rsvd[3]; 2271 }; 2272 2273 struct cpl_rte_read_req { 2274 WR_HDR; 2275 union opcode_tid ot; 2276 __be32 params; 2277 }; 2278 2279 struct cpl_rte_read_rpl { 2280 RSS_HDR 2281 union opcode_tid ot; 2282 __u8 status; 2283 __u8 rsvd; 2284 __be16 l2t_idx; 2285 #if defined(__LITTLE_ENDIAN_BITFIELD) 2286 __u32 :30; 2287 __u32 select:1; 2288 #else 2289 __u32 select:1; 2290 __u32 :30; 2291 #endif 2292 __be32 addr; 2293 }; 2294 2295 struct cpl_l2t_write_req { 2296 WR_HDR; 2297 union opcode_tid ot; 2298 __be16 params; 2299 __be16 l2t_idx; 2300 __be16 vlan; 2301 __u8 dst_mac[6]; 2302 }; 2303 2304 /* cpl_l2t_write_req.params fields */ 2305 #define S_L2T_W_INFO 2 2306 #define M_L2T_W_INFO 0x3F 2307 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 2308 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 2309 2310 #define S_L2T_W_PORT 8 2311 #define M_L2T_W_PORT 0x3 2312 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 2313 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 2314 2315 #define S_L2T_W_LPBK 10 2316 #define V_L2T_W_LPBK(x) ((x) << S_L2T_W_LPBK) 2317 #define F_L2T_W_PKBK V_L2T_W_LPBK(1U) 2318 2319 #define S_L2T_W_ARPMISS 11 2320 #define V_L2T_W_ARPMISS(x) ((x) << S_L2T_W_ARPMISS) 2321 #define F_L2T_W_ARPMISS V_L2T_W_ARPMISS(1U) 2322 2323 #define S_L2T_W_NOREPLY 15 2324 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 2325 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 2326 2327 #define CPL_L2T_VLAN_NONE 0xfff 2328 2329 struct cpl_l2t_write_rpl { 2330 RSS_HDR 2331 union opcode_tid ot; 2332 __u8 status; 2333 __u8 rsvd[3]; 2334 }; 2335 2336 struct cpl_l2t_read_req { 2337 WR_HDR; 2338 union opcode_tid ot; 2339 __be32 l2t_idx; 2340 }; 2341 2342 struct cpl_l2t_read_rpl { 2343 RSS_HDR 2344 union opcode_tid ot; 2345 __u8 status; 2346 #if defined(__LITTLE_ENDIAN_BITFIELD) 2347 __u8 :4; 2348 __u8 iff:4; 2349 #else 2350 __u8 iff:4; 2351 __u8 :4; 2352 #endif 2353 __be16 vlan; 2354 __be16 info; 2355 __u8 dst_mac[6]; 2356 }; 2357 2358 struct cpl_srq_table_req { 2359 WR_HDR; 2360 union opcode_tid ot; 2361 __u8 status; 2362 __u8 rsvd[2]; 2363 __u8 idx; 2364 __be64 rsvd_pdid; 2365 __be32 qlen_qbase; 2366 __be16 cur_msn; 2367 __be16 max_msn; 2368 }; 2369 2370 struct cpl_srq_table_rpl { 2371 RSS_HDR 2372 union opcode_tid ot; 2373 __u8 status; 2374 __u8 rsvd[2]; 2375 __u8 idx; 2376 __be64 rsvd_pdid; 2377 __be32 qlen_qbase; 2378 __be16 cur_msn; 2379 __be16 max_msn; 2380 }; 2381 2382 /* cpl_srq_table_{req,rpl}.params fields */ 2383 #define S_SRQT_QLEN 28 2384 #define M_SRQT_QLEN 0xF 2385 #define V_SRQT_QLEN(x) ((x) << S_SRQT_QLEN) 2386 #define G_SRQT_QLEN(x) (((x) >> S_SRQT_QLEN) & M_SRQT_QLEN) 2387 2388 #define S_SRQT_QBASE 0 2389 #define M_SRQT_QBASE 0x3FFFFFF 2390 #define V_SRQT_QBASE(x) ((x) << S_SRQT_QBASE) 2391 #define G_SRQT_QBASE(x) (((x) >> S_SRQT_QBASE) & M_SRQT_QBASE) 2392 2393 #define S_SRQT_PDID 0 2394 #define M_SRQT_PDID 0xFF 2395 #define V_SRQT_PDID(x) ((x) << S_SRQT_PDID) 2396 #define G_SRQT_PDID(x) (((x) >> S_SRQT_PDID) & M_SRQT_PDID) 2397 2398 #define S_SRQT_IDX 0 2399 #define M_SRQT_IDX 0xF 2400 #define V_SRQT_IDX(x) ((x) << S_SRQT_IDX) 2401 #define G_SRQT_IDX(x) (((x) >> S_SRQT_IDX) & M_SRQT_IDX) 2402 2403 struct cpl_smt_write_req { 2404 WR_HDR; 2405 union opcode_tid ot; 2406 __be32 params; 2407 __be16 pfvf1; 2408 __u8 src_mac1[6]; 2409 __be16 pfvf0; 2410 __u8 src_mac0[6]; 2411 }; 2412 2413 struct cpl_t6_smt_write_req { 2414 WR_HDR; 2415 union opcode_tid ot; 2416 __be32 params; 2417 __be64 tag; 2418 __be16 pfvf0; 2419 __u8 src_mac0[6]; 2420 __be32 local_ip; 2421 __be32 rsvd; 2422 }; 2423 2424 struct cpl_smt_write_rpl { 2425 RSS_HDR 2426 union opcode_tid ot; 2427 __u8 status; 2428 __u8 rsvd[3]; 2429 }; 2430 2431 struct cpl_smt_read_req { 2432 WR_HDR; 2433 union opcode_tid ot; 2434 __be32 params; 2435 }; 2436 2437 struct cpl_smt_read_rpl { 2438 RSS_HDR 2439 union opcode_tid ot; 2440 __u8 status; 2441 __u8 ovlan_idx; 2442 __be16 rsvd; 2443 __be16 pfvf1; 2444 __u8 src_mac1[6]; 2445 __be16 pfvf0; 2446 __u8 src_mac0[6]; 2447 }; 2448 2449 /* cpl_smt_{read,write}_req.params fields */ 2450 #define S_SMTW_OVLAN_IDX 16 2451 #define M_SMTW_OVLAN_IDX 0xF 2452 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 2453 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 2454 2455 #define S_SMTW_IDX 20 2456 #define M_SMTW_IDX 0x7F 2457 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 2458 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 2459 2460 #define M_T6_SMTW_IDX 0xFF 2461 #define G_T6_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_T6_SMTW_IDX) 2462 2463 #define S_SMTW_NORPL 31 2464 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 2465 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 2466 2467 /* cpl_smt_{read,write}_req.pfvf? fields */ 2468 #define S_SMTW_VF 0 2469 #define M_SMTW_VF 0xFF 2470 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 2471 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 2472 2473 #define S_SMTW_PF 8 2474 #define M_SMTW_PF 0x7 2475 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 2476 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 2477 2478 #define S_SMTW_VF_VLD 11 2479 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 2480 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 2481 2482 struct cpl_tag_write_req { 2483 WR_HDR; 2484 union opcode_tid ot; 2485 __be32 params; 2486 __be64 tag_val; 2487 }; 2488 2489 struct cpl_tag_write_rpl { 2490 RSS_HDR 2491 union opcode_tid ot; 2492 __u8 status; 2493 __u8 rsvd[2]; 2494 __u8 idx; 2495 }; 2496 2497 struct cpl_tag_read_req { 2498 WR_HDR; 2499 union opcode_tid ot; 2500 __be32 params; 2501 }; 2502 2503 struct cpl_tag_read_rpl { 2504 RSS_HDR 2505 union opcode_tid ot; 2506 __u8 status; 2507 #if defined(__LITTLE_ENDIAN_BITFIELD) 2508 __u8 :4; 2509 __u8 tag_len:1; 2510 __u8 :2; 2511 __u8 ins_enable:1; 2512 #else 2513 __u8 ins_enable:1; 2514 __u8 :2; 2515 __u8 tag_len:1; 2516 __u8 :4; 2517 #endif 2518 __u8 rsvd; 2519 __u8 tag_idx; 2520 __be64 tag_val; 2521 }; 2522 2523 /* cpl_tag{read,write}_req.params fields */ 2524 #define S_TAGW_IDX 0 2525 #define M_TAGW_IDX 0x7F 2526 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX) 2527 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX) 2528 2529 #define S_TAGW_LEN 20 2530 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN) 2531 #define F_TAGW_LEN V_TAGW_LEN(1U) 2532 2533 #define S_TAGW_INS_ENABLE 23 2534 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE) 2535 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U) 2536 2537 #define S_TAGW_NORPL 31 2538 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL) 2539 #define F_TAGW_NORPL V_TAGW_NORPL(1U) 2540 2541 struct cpl_barrier { 2542 WR_HDR; 2543 __u8 opcode; 2544 __u8 chan_map; 2545 __be16 rsvd0; 2546 __be32 rsvd1; 2547 }; 2548 2549 /* cpl_barrier.chan_map fields */ 2550 #define S_CHAN_MAP 4 2551 #define M_CHAN_MAP 0xF 2552 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 2553 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 2554 2555 struct cpl_error { 2556 RSS_HDR 2557 union opcode_tid ot; 2558 __be32 error; 2559 }; 2560 2561 struct cpl_hit_notify { 2562 RSS_HDR 2563 union opcode_tid ot; 2564 __be32 rsvd; 2565 __be32 info; 2566 __be32 reason; 2567 }; 2568 2569 struct cpl_pkt_notify { 2570 RSS_HDR 2571 union opcode_tid ot; 2572 __be16 rsvd; 2573 __be16 len; 2574 __be32 info; 2575 __be32 reason; 2576 }; 2577 2578 /* cpl_{hit,pkt}_notify.info fields */ 2579 #define S_NTFY_MAC_IDX 0 2580 #define M_NTFY_MAC_IDX 0x1FF 2581 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 2582 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 2583 2584 #define S_NTFY_INTF 10 2585 #define M_NTFY_INTF 0xF 2586 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 2587 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 2588 2589 #define S_NTFY_TCPHDR_LEN 14 2590 #define M_NTFY_TCPHDR_LEN 0xF 2591 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 2592 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 2593 2594 #define S_NTFY_IPHDR_LEN 18 2595 #define M_NTFY_IPHDR_LEN 0x1FF 2596 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 2597 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 2598 2599 #define S_NTFY_ETHHDR_LEN 27 2600 #define M_NTFY_ETHHDR_LEN 0x1F 2601 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 2602 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 2603 2604 #define S_NTFY_T5_IPHDR_LEN 18 2605 #define M_NTFY_T5_IPHDR_LEN 0xFF 2606 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN) 2607 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN) 2608 2609 #define S_NTFY_T5_ETHHDR_LEN 26 2610 #define M_NTFY_T5_ETHHDR_LEN 0x3F 2611 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN) 2612 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN) 2613 2614 struct cpl_rdma_terminate { 2615 RSS_HDR 2616 union opcode_tid ot; 2617 __be16 rsvd; 2618 __be16 len; 2619 }; 2620 2621 struct cpl_set_le_req { 2622 WR_HDR; 2623 union opcode_tid ot; 2624 __be16 reply_ctrl; 2625 __be16 params; 2626 __be64 mask_hi; 2627 __be64 mask_lo; 2628 __be64 val_hi; 2629 __be64 val_lo; 2630 }; 2631 2632 /* cpl_set_le_req.reply_ctrl additional fields */ 2633 #define S_LE_REQ_IP6 13 2634 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 2635 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 2636 2637 /* cpl_set_le_req.params fields */ 2638 #define S_LE_CHAN 0 2639 #define M_LE_CHAN 0x3 2640 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 2641 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 2642 2643 #define S_LE_OFFSET 5 2644 #define M_LE_OFFSET 0x7 2645 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 2646 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 2647 2648 #define S_LE_MORE 8 2649 #define V_LE_MORE(x) ((x) << S_LE_MORE) 2650 #define F_LE_MORE V_LE_MORE(1U) 2651 2652 #define S_LE_REQSIZE 9 2653 #define M_LE_REQSIZE 0x7 2654 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 2655 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 2656 2657 #define S_LE_REQCMD 12 2658 #define M_LE_REQCMD 0xF 2659 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 2660 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 2661 2662 struct cpl_set_le_rpl { 2663 RSS_HDR 2664 union opcode_tid ot; 2665 __u8 chan; 2666 __u8 info; 2667 __be16 len; 2668 }; 2669 2670 /* cpl_set_le_rpl.info fields */ 2671 #define S_LE_RSPCMD 0 2672 #define M_LE_RSPCMD 0xF 2673 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 2674 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 2675 2676 #define S_LE_RSPSIZE 4 2677 #define M_LE_RSPSIZE 0x7 2678 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 2679 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 2680 2681 #define S_LE_RSPTYPE 7 2682 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 2683 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 2684 2685 struct cpl_sge_egr_update { 2686 RSS_HDR 2687 __be32 opcode_qid; 2688 __be16 cidx; 2689 __be16 pidx; 2690 }; 2691 2692 /* cpl_sge_egr_update.ot fields */ 2693 #define S_AUTOEQU 22 2694 #define M_AUTOEQU 0x1 2695 #define V_AUTOEQU(x) ((x) << S_AUTOEQU) 2696 #define G_AUTOEQU(x) (((x) >> S_AUTOEQU) & M_AUTOEQU) 2697 2698 #define S_EGR_QID 0 2699 #define M_EGR_QID 0x1FFFF 2700 #define V_EGR_QID(x) ((x) << S_EGR_QID) 2701 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 2702 2703 /* cpl_fw*.type values */ 2704 enum { 2705 FW_TYPE_CMD_RPL = 0, 2706 FW_TYPE_WR_RPL = 1, 2707 FW_TYPE_CQE = 2, 2708 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 2709 FW_TYPE_RSSCPL = 4, 2710 FW_TYPE_WRERR_RPL = 5, 2711 FW_TYPE_PI_ERR = 6, 2712 FW_TYPE_TLS_KEY = 7, 2713 }; 2714 2715 struct cpl_fw2_pld { 2716 RSS_HDR 2717 u8 opcode; 2718 u8 rsvd[5]; 2719 __be16 len; 2720 }; 2721 2722 struct cpl_fw4_pld { 2723 RSS_HDR 2724 u8 opcode; 2725 u8 rsvd0[3]; 2726 u8 type; 2727 u8 rsvd1; 2728 __be16 len; 2729 __be64 data; 2730 __be64 rsvd2; 2731 }; 2732 2733 struct cpl_fw6_pld { 2734 RSS_HDR 2735 u8 opcode; 2736 u8 rsvd[5]; 2737 __be16 len; 2738 __be64 data[4]; 2739 }; 2740 2741 struct cpl_fw2_msg { 2742 RSS_HDR 2743 union opcode_info oi; 2744 }; 2745 2746 struct cpl_fw4_msg { 2747 RSS_HDR 2748 u8 opcode; 2749 u8 type; 2750 __be16 rsvd0; 2751 __be32 rsvd1; 2752 __be64 data[2]; 2753 }; 2754 2755 struct cpl_fw4_ack { 2756 RSS_HDR 2757 union opcode_tid ot; 2758 u8 credits; 2759 u8 rsvd0[2]; 2760 u8 flags; 2761 __be32 snd_nxt; 2762 __be32 snd_una; 2763 __be64 rsvd1; 2764 }; 2765 2766 enum { 2767 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 2768 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 2769 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 2770 }; 2771 2772 #define S_CPL_FW4_ACK_OPCODE 24 2773 #define M_CPL_FW4_ACK_OPCODE 0xff 2774 #define V_CPL_FW4_ACK_OPCODE(x) ((x) << S_CPL_FW4_ACK_OPCODE) 2775 #define G_CPL_FW4_ACK_OPCODE(x) \ 2776 (((x) >> S_CPL_FW4_ACK_OPCODE) & M_CPL_FW4_ACK_OPCODE) 2777 2778 #define S_CPL_FW4_ACK_FLOWID 0 2779 #define M_CPL_FW4_ACK_FLOWID 0xffffff 2780 #define V_CPL_FW4_ACK_FLOWID(x) ((x) << S_CPL_FW4_ACK_FLOWID) 2781 #define G_CPL_FW4_ACK_FLOWID(x) \ 2782 (((x) >> S_CPL_FW4_ACK_FLOWID) & M_CPL_FW4_ACK_FLOWID) 2783 2784 #define S_CPL_FW4_ACK_CR 24 2785 #define M_CPL_FW4_ACK_CR 0xff 2786 #define V_CPL_FW4_ACK_CR(x) ((x) << S_CPL_FW4_ACK_CR) 2787 #define G_CPL_FW4_ACK_CR(x) (((x) >> S_CPL_FW4_ACK_CR) & M_CPL_FW4_ACK_CR) 2788 2789 #define S_CPL_FW4_ACK_SEQVAL 0 2790 #define M_CPL_FW4_ACK_SEQVAL 0x1 2791 #define V_CPL_FW4_ACK_SEQVAL(x) ((x) << S_CPL_FW4_ACK_SEQVAL) 2792 #define G_CPL_FW4_ACK_SEQVAL(x) \ 2793 (((x) >> S_CPL_FW4_ACK_SEQVAL) & M_CPL_FW4_ACK_SEQVAL) 2794 #define F_CPL_FW4_ACK_SEQVAL V_CPL_FW4_ACK_SEQVAL(1U) 2795 2796 struct cpl_fw6_msg { 2797 RSS_HDR 2798 u8 opcode; 2799 u8 type; 2800 __be16 rsvd0; 2801 __be32 rsvd1; 2802 __be64 data[4]; 2803 }; 2804 2805 /* cpl_fw6_msg.type values */ 2806 enum { 2807 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL, 2808 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL, 2809 FW6_TYPE_CQE = FW_TYPE_CQE, 2810 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL, 2811 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 2812 FW6_TYPE_WRERR_RPL = FW_TYPE_WRERR_RPL, 2813 FW6_TYPE_PI_ERR = FW_TYPE_PI_ERR, 2814 NUM_FW6_TYPES 2815 }; 2816 2817 struct cpl_fw6_msg_ofld_connection_wr_rpl { 2818 __u64 cookie; 2819 __be32 tid; /* or atid in case of active failure */ 2820 __u8 t_state; 2821 __u8 retval; 2822 __u8 rsvd[2]; 2823 }; 2824 2825 /* ULP_TX opcodes */ 2826 enum { 2827 ULP_TX_MEM_READ = 2, 2828 ULP_TX_MEM_WRITE = 3, 2829 ULP_TX_PKT = 4 2830 }; 2831 2832 enum { 2833 ULP_TX_SC_NOOP = 0x80, 2834 ULP_TX_SC_IMM = 0x81, 2835 ULP_TX_SC_DSGL = 0x82, 2836 ULP_TX_SC_ISGL = 0x83, 2837 ULP_TX_SC_PICTRL = 0x84, 2838 ULP_TX_SC_MEMRD = 0x86 2839 }; 2840 2841 #define S_ULPTX_CMD 24 2842 #define M_ULPTX_CMD 0xFF 2843 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2844 2845 #define S_ULPTX_LEN16 0 2846 #define M_ULPTX_LEN16 0xFF 2847 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2848 2849 #define S_ULP_TX_SC_MORE 23 2850 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2851 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2852 2853 struct ulptx_sge_pair { 2854 __be32 len[2]; 2855 __be64 addr[2]; 2856 }; 2857 2858 struct ulptx_sgl { 2859 __be32 cmd_nsge; 2860 __be32 len0; 2861 __be64 addr0; 2862 #if !(defined C99_NOT_SUPPORTED) 2863 struct ulptx_sge_pair sge[]; 2864 #endif 2865 }; 2866 2867 struct ulptx_isge { 2868 __be32 stag; 2869 __be32 len; 2870 __be64 target_ofst; 2871 }; 2872 2873 struct ulptx_isgl { 2874 __be32 cmd_nisge; 2875 __be32 rsvd; 2876 #if !(defined C99_NOT_SUPPORTED) 2877 struct ulptx_isge sge[]; 2878 #endif 2879 }; 2880 2881 struct ulptx_idata { 2882 __be32 cmd_more; 2883 __be32 len; 2884 }; 2885 2886 #define S_ULPTX_NSGE 0 2887 #define M_ULPTX_NSGE 0xFFFF 2888 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2889 #define G_ULPTX_NSGE(x) (((x) >> S_ULPTX_NSGE) & M_ULPTX_NSGE) 2890 2891 struct ulptx_sc_memrd { 2892 __be32 cmd_to_len; 2893 __be32 addr; 2894 }; 2895 2896 struct ulp_mem_io { 2897 WR_HDR; 2898 __be32 cmd; 2899 __be32 len16; /* command length */ 2900 __be32 dlen; /* data length in 32-byte units */ 2901 __be32 lock_addr; 2902 }; 2903 2904 /* additional ulp_mem_io.cmd fields */ 2905 #define S_ULP_MEMIO_ORDER 23 2906 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2907 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2908 2909 #define S_T5_ULP_MEMIO_IMM 23 2910 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM) 2911 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U) 2912 2913 #define S_T5_ULP_MEMIO_ORDER 22 2914 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER) 2915 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U) 2916 2917 #define S_T5_ULP_MEMIO_FID 4 2918 #define M_T5_ULP_MEMIO_FID 0x7ff 2919 #define V_T5_ULP_MEMIO_FID(x) ((x) << S_T5_ULP_MEMIO_FID) 2920 2921 /* ulp_mem_io.lock_addr fields */ 2922 #define S_ULP_MEMIO_ADDR 0 2923 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2924 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2925 2926 #define S_ULP_MEMIO_LOCK 31 2927 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2928 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2929 2930 /* ulp_mem_io.dlen fields */ 2931 #define S_ULP_MEMIO_DATA_LEN 0 2932 #define M_ULP_MEMIO_DATA_LEN 0x1F 2933 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2934 2935 /* ULP_TXPKT field values */ 2936 enum { 2937 ULP_TXPKT_DEST_TP = 0, 2938 ULP_TXPKT_DEST_SGE, 2939 ULP_TXPKT_DEST_UP, 2940 ULP_TXPKT_DEST_DEVNULL, 2941 }; 2942 2943 struct ulp_txpkt { 2944 __be32 cmd_dest; 2945 __be32 len; 2946 }; 2947 2948 /* ulp_txpkt.cmd_dest fields */ 2949 #define S_ULP_TXPKT_DATAMODIFY 23 2950 #define M_ULP_TXPKT_DATAMODIFY 0x1 2951 #define V_ULP_TXPKT_DATAMODIFY(x) ((x) << S_ULP_TXPKT_DATAMODIFY) 2952 #define G_ULP_TXPKT_DATAMODIFY(x) \ 2953 (((x) >> S_ULP_TXPKT_DATAMODIFY) & M_ULP_TXPKT_DATAMODIFY_) 2954 #define F_ULP_TXPKT_DATAMODIFY V_ULP_TXPKT_DATAMODIFY(1U) 2955 2956 #define S_ULP_TXPKT_CHANNELID 22 2957 #define M_ULP_TXPKT_CHANNELID 0x1 2958 #define V_ULP_TXPKT_CHANNELID(x) ((x) << S_ULP_TXPKT_CHANNELID) 2959 #define G_ULP_TXPKT_CHANNELID(x) \ 2960 (((x) >> S_ULP_TXPKT_CHANNELID) & M_ULP_TXPKT_CHANNELID) 2961 #define F_ULP_TXPKT_CHANNELID V_ULP_TXPKT_CHANNELID(1U) 2962 2963 /* ulp_txpkt.cmd_dest fields */ 2964 #define S_ULP_TXPKT_DEST 16 2965 #define M_ULP_TXPKT_DEST 0x3 2966 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2967 2968 #define S_ULP_TXPKT_FID 4 2969 #define M_ULP_TXPKT_FID 0x7ff 2970 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2971 2972 #define S_ULP_TXPKT_RO 3 2973 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO) 2974 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U) 2975 2976 enum cpl_tx_tnl_lso_type { 2977 TX_TNL_TYPE_OPAQUE, 2978 TX_TNL_TYPE_NVGRE, 2979 TX_TNL_TYPE_VXLAN, 2980 TX_TNL_TYPE_GENEVE, 2981 }; 2982 2983 struct cpl_tx_tnl_lso { 2984 __be32 op_to_IpIdSplitOut; 2985 __be16 IpIdOffsetOut; 2986 __be16 UdpLenSetOut_to_TnlHdrLen; 2987 __be64 r1; 2988 __be32 Flow_to_TcpHdrLen; 2989 __be16 IpIdOffset; 2990 __be16 IpIdSplit_to_Mss; 2991 __be32 TCPSeqOffset; 2992 __be32 EthLenOffset_Size; 2993 /* encapsulated CPL (TX_PKT_XT) follows here */ 2994 }; 2995 2996 #define S_CPL_TX_TNL_LSO_OPCODE 24 2997 #define M_CPL_TX_TNL_LSO_OPCODE 0xff 2998 #define V_CPL_TX_TNL_LSO_OPCODE(x) ((x) << S_CPL_TX_TNL_LSO_OPCODE) 2999 #define G_CPL_TX_TNL_LSO_OPCODE(x) \ 3000 (((x) >> S_CPL_TX_TNL_LSO_OPCODE) & M_CPL_TX_TNL_LSO_OPCODE) 3001 3002 #define S_CPL_TX_TNL_LSO_FIRST 23 3003 #define M_CPL_TX_TNL_LSO_FIRST 0x1 3004 #define V_CPL_TX_TNL_LSO_FIRST(x) ((x) << S_CPL_TX_TNL_LSO_FIRST) 3005 #define G_CPL_TX_TNL_LSO_FIRST(x) \ 3006 (((x) >> S_CPL_TX_TNL_LSO_FIRST) & M_CPL_TX_TNL_LSO_FIRST) 3007 #define F_CPL_TX_TNL_LSO_FIRST V_CPL_TX_TNL_LSO_FIRST(1U) 3008 3009 #define S_CPL_TX_TNL_LSO_LAST 22 3010 #define M_CPL_TX_TNL_LSO_LAST 0x1 3011 #define V_CPL_TX_TNL_LSO_LAST(x) ((x) << S_CPL_TX_TNL_LSO_LAST) 3012 #define G_CPL_TX_TNL_LSO_LAST(x) \ 3013 (((x) >> S_CPL_TX_TNL_LSO_LAST) & M_CPL_TX_TNL_LSO_LAST) 3014 #define F_CPL_TX_TNL_LSO_LAST V_CPL_TX_TNL_LSO_LAST(1U) 3015 3016 #define S_CPL_TX_TNL_LSO_ETHHDRLENXOUT 21 3017 #define M_CPL_TX_TNL_LSO_ETHHDRLENXOUT 0x1 3018 #define V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 3019 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3020 #define G_CPL_TX_TNL_LSO_ETHHDRLENXOUT(x) \ 3021 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENXOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENXOUT) 3022 #define F_CPL_TX_TNL_LSO_ETHHDRLENXOUT V_CPL_TX_TNL_LSO_ETHHDRLENXOUT(1U) 3023 3024 #define S_CPL_TX_TNL_LSO_IPV6OUT 20 3025 #define M_CPL_TX_TNL_LSO_IPV6OUT 0x1 3026 #define V_CPL_TX_TNL_LSO_IPV6OUT(x) ((x) << S_CPL_TX_TNL_LSO_IPV6OUT) 3027 #define G_CPL_TX_TNL_LSO_IPV6OUT(x) \ 3028 (((x) >> S_CPL_TX_TNL_LSO_IPV6OUT) & M_CPL_TX_TNL_LSO_IPV6OUT) 3029 #define F_CPL_TX_TNL_LSO_IPV6OUT V_CPL_TX_TNL_LSO_IPV6OUT(1U) 3030 3031 #define S_CPL_TX_TNL_LSO_ETHHDRLENOUT 16 3032 #define M_CPL_TX_TNL_LSO_ETHHDRLENOUT 0xf 3033 #define V_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3034 ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3035 #define G_CPL_TX_TNL_LSO_ETHHDRLENOUT(x) \ 3036 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENOUT) & M_CPL_TX_TNL_LSO_ETHHDRLENOUT) 3037 3038 #define S_CPL_TX_TNL_LSO_IPHDRLENOUT 4 3039 #define M_CPL_TX_TNL_LSO_IPHDRLENOUT 0xfff 3040 #define V_CPL_TX_TNL_LSO_IPHDRLENOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLENOUT) 3041 #define G_CPL_TX_TNL_LSO_IPHDRLENOUT(x) \ 3042 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLENOUT) & M_CPL_TX_TNL_LSO_IPHDRLENOUT) 3043 3044 #define S_CPL_TX_TNL_LSO_IPHDRCHKOUT 3 3045 #define M_CPL_TX_TNL_LSO_IPHDRCHKOUT 0x1 3046 #define V_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3047 #define G_CPL_TX_TNL_LSO_IPHDRCHKOUT(x) \ 3048 (((x) >> S_CPL_TX_TNL_LSO_IPHDRCHKOUT) & M_CPL_TX_TNL_LSO_IPHDRCHKOUT) 3049 #define F_CPL_TX_TNL_LSO_IPHDRCHKOUT V_CPL_TX_TNL_LSO_IPHDRCHKOUT(1U) 3050 3051 #define S_CPL_TX_TNL_LSO_IPLENSETOUT 2 3052 #define M_CPL_TX_TNL_LSO_IPLENSETOUT 0x1 3053 #define V_CPL_TX_TNL_LSO_IPLENSETOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPLENSETOUT) 3054 #define G_CPL_TX_TNL_LSO_IPLENSETOUT(x) \ 3055 (((x) >> S_CPL_TX_TNL_LSO_IPLENSETOUT) & M_CPL_TX_TNL_LSO_IPLENSETOUT) 3056 #define F_CPL_TX_TNL_LSO_IPLENSETOUT V_CPL_TX_TNL_LSO_IPLENSETOUT(1U) 3057 3058 #define S_CPL_TX_TNL_LSO_IPIDINCOUT 1 3059 #define M_CPL_TX_TNL_LSO_IPIDINCOUT 0x1 3060 #define V_CPL_TX_TNL_LSO_IPIDINCOUT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDINCOUT) 3061 #define G_CPL_TX_TNL_LSO_IPIDINCOUT(x) \ 3062 (((x) >> S_CPL_TX_TNL_LSO_IPIDINCOUT) & M_CPL_TX_TNL_LSO_IPIDINCOUT) 3063 #define F_CPL_TX_TNL_LSO_IPIDINCOUT V_CPL_TX_TNL_LSO_IPIDINCOUT(1U) 3064 3065 #define S_CPL_TX_TNL_LSO_IPIDSPLITOUT 0 3066 #define M_CPL_TX_TNL_LSO_IPIDSPLITOUT 0x1 3067 #define V_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3068 ((x) << S_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3069 #define G_CPL_TX_TNL_LSO_IPIDSPLITOUT(x) \ 3070 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLITOUT) & M_CPL_TX_TNL_LSO_IPIDSPLITOUT) 3071 #define F_CPL_TX_TNL_LSO_IPIDSPLITOUT V_CPL_TX_TNL_LSO_IPIDSPLITOUT(1U) 3072 3073 #define S_CPL_TX_TNL_LSO_UDPLENSETOUT 15 3074 #define M_CPL_TX_TNL_LSO_UDPLENSETOUT 0x1 3075 #define V_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3076 ((x) << S_CPL_TX_TNL_LSO_UDPLENSETOUT) 3077 #define G_CPL_TX_TNL_LSO_UDPLENSETOUT(x) \ 3078 (((x) >> S_CPL_TX_TNL_LSO_UDPLENSETOUT) & M_CPL_TX_TNL_LSO_UDPLENSETOUT) 3079 #define F_CPL_TX_TNL_LSO_UDPLENSETOUT V_CPL_TX_TNL_LSO_UDPLENSETOUT(1U) 3080 3081 #define S_CPL_TX_TNL_LSO_UDPCHKCLROUT 14 3082 #define M_CPL_TX_TNL_LSO_UDPCHKCLROUT 0x1 3083 #define V_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3084 ((x) << S_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3085 #define G_CPL_TX_TNL_LSO_UDPCHKCLROUT(x) \ 3086 (((x) >> S_CPL_TX_TNL_LSO_UDPCHKCLROUT) & M_CPL_TX_TNL_LSO_UDPCHKCLROUT) 3087 #define F_CPL_TX_TNL_LSO_UDPCHKCLROUT V_CPL_TX_TNL_LSO_UDPCHKCLROUT(1U) 3088 3089 #define S_CPL_TX_TNL_LSO_TNLTYPE 12 3090 #define M_CPL_TX_TNL_LSO_TNLTYPE 0x3 3091 #define V_CPL_TX_TNL_LSO_TNLTYPE(x) ((x) << S_CPL_TX_TNL_LSO_TNLTYPE) 3092 #define G_CPL_TX_TNL_LSO_TNLTYPE(x) \ 3093 (((x) >> S_CPL_TX_TNL_LSO_TNLTYPE) & M_CPL_TX_TNL_LSO_TNLTYPE) 3094 3095 #define S_CPL_TX_TNL_LSO_TNLHDRLEN 0 3096 #define M_CPL_TX_TNL_LSO_TNLHDRLEN 0xfff 3097 #define V_CPL_TX_TNL_LSO_TNLHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TNLHDRLEN) 3098 #define G_CPL_TX_TNL_LSO_TNLHDRLEN(x) \ 3099 (((x) >> S_CPL_TX_TNL_LSO_TNLHDRLEN) & M_CPL_TX_TNL_LSO_TNLHDRLEN) 3100 3101 #define S_CPL_TX_TNL_LSO_FLOW 21 3102 #define M_CPL_TX_TNL_LSO_FLOW 0x1 3103 #define V_CPL_TX_TNL_LSO_FLOW(x) ((x) << S_CPL_TX_TNL_LSO_FLOW) 3104 #define G_CPL_TX_TNL_LSO_FLOW(x) \ 3105 (((x) >> S_CPL_TX_TNL_LSO_FLOW) & M_CPL_TX_TNL_LSO_FLOW) 3106 #define F_CPL_TX_TNL_LSO_FLOW V_CPL_TX_TNL_LSO_FLOW(1U) 3107 3108 #define S_CPL_TX_TNL_LSO_IPV6 20 3109 #define M_CPL_TX_TNL_LSO_IPV6 0x1 3110 #define V_CPL_TX_TNL_LSO_IPV6(x) ((x) << S_CPL_TX_TNL_LSO_IPV6) 3111 #define G_CPL_TX_TNL_LSO_IPV6(x) \ 3112 (((x) >> S_CPL_TX_TNL_LSO_IPV6) & M_CPL_TX_TNL_LSO_IPV6) 3113 #define F_CPL_TX_TNL_LSO_IPV6 V_CPL_TX_TNL_LSO_IPV6(1U) 3114 3115 #define S_CPL_TX_TNL_LSO_ETHHDRLEN 16 3116 #define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf 3117 #define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN) 3118 #define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \ 3119 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN) 3120 3121 #define S_CPL_TX_TNL_LSO_IPHDRLEN 4 3122 #define M_CPL_TX_TNL_LSO_IPHDRLEN 0xfff 3123 #define V_CPL_TX_TNL_LSO_IPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_IPHDRLEN) 3124 #define G_CPL_TX_TNL_LSO_IPHDRLEN(x) \ 3125 (((x) >> S_CPL_TX_TNL_LSO_IPHDRLEN) & M_CPL_TX_TNL_LSO_IPHDRLEN) 3126 3127 #define S_CPL_TX_TNL_LSO_TCPHDRLEN 0 3128 #define M_CPL_TX_TNL_LSO_TCPHDRLEN 0xf 3129 #define V_CPL_TX_TNL_LSO_TCPHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_TCPHDRLEN) 3130 #define G_CPL_TX_TNL_LSO_TCPHDRLEN(x) \ 3131 (((x) >> S_CPL_TX_TNL_LSO_TCPHDRLEN) & M_CPL_TX_TNL_LSO_TCPHDRLEN) 3132 3133 #define S_CPL_TX_TNL_LSO_IPIDSPLIT 15 3134 #define M_CPL_TX_TNL_LSO_IPIDSPLIT 0x1 3135 #define V_CPL_TX_TNL_LSO_IPIDSPLIT(x) ((x) << S_CPL_TX_TNL_LSO_IPIDSPLIT) 3136 #define G_CPL_TX_TNL_LSO_IPIDSPLIT(x) \ 3137 (((x) >> S_CPL_TX_TNL_LSO_IPIDSPLIT) & M_CPL_TX_TNL_LSO_IPIDSPLIT) 3138 #define F_CPL_TX_TNL_LSO_IPIDSPLIT V_CPL_TX_TNL_LSO_IPIDSPLIT(1U) 3139 3140 #define S_CPL_TX_TNL_LSO_ETHHDRLENX 14 3141 #define M_CPL_TX_TNL_LSO_ETHHDRLENX 0x1 3142 #define V_CPL_TX_TNL_LSO_ETHHDRLENX(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLENX) 3143 #define G_CPL_TX_TNL_LSO_ETHHDRLENX(x) \ 3144 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLENX) & M_CPL_TX_TNL_LSO_ETHHDRLENX) 3145 #define F_CPL_TX_TNL_LSO_ETHHDRLENX V_CPL_TX_TNL_LSO_ETHHDRLENX(1U) 3146 3147 #define S_CPL_TX_TNL_LSO_MSS 0 3148 #define M_CPL_TX_TNL_LSO_MSS 0x3fff 3149 #define V_CPL_TX_TNL_LSO_MSS(x) ((x) << S_CPL_TX_TNL_LSO_MSS) 3150 #define G_CPL_TX_TNL_LSO_MSS(x) \ 3151 (((x) >> S_CPL_TX_TNL_LSO_MSS) & M_CPL_TX_TNL_LSO_MSS) 3152 3153 #define S_CPL_TX_TNL_LSO_ETHLENOFFSET 28 3154 #define M_CPL_TX_TNL_LSO_ETHLENOFFSET 0xf 3155 #define V_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3156 ((x) << S_CPL_TX_TNL_LSO_ETHLENOFFSET) 3157 #define G_CPL_TX_TNL_LSO_ETHLENOFFSET(x) \ 3158 (((x) >> S_CPL_TX_TNL_LSO_ETHLENOFFSET) & M_CPL_TX_TNL_LSO_ETHLENOFFSET) 3159 3160 #define S_CPL_TX_TNL_LSO_SIZE 0 3161 #define M_CPL_TX_TNL_LSO_SIZE 0xfffffff 3162 #define V_CPL_TX_TNL_LSO_SIZE(x) ((x) << S_CPL_TX_TNL_LSO_SIZE) 3163 #define G_CPL_TX_TNL_LSO_SIZE(x) \ 3164 (((x) >> S_CPL_TX_TNL_LSO_SIZE) & M_CPL_TX_TNL_LSO_SIZE) 3165 3166 struct cpl_rx_mps_pkt { 3167 __be32 op_to_r1_hi; 3168 __be32 r1_lo_length; 3169 }; 3170 3171 #define S_CPL_RX_MPS_PKT_OP 24 3172 #define M_CPL_RX_MPS_PKT_OP 0xff 3173 #define V_CPL_RX_MPS_PKT_OP(x) ((x) << S_CPL_RX_MPS_PKT_OP) 3174 #define G_CPL_RX_MPS_PKT_OP(x) \ 3175 (((x) >> S_CPL_RX_MPS_PKT_OP) & M_CPL_RX_MPS_PKT_OP) 3176 3177 #define S_CPL_RX_MPS_PKT_TYPE 20 3178 #define M_CPL_RX_MPS_PKT_TYPE 0xf 3179 #define V_CPL_RX_MPS_PKT_TYPE(x) ((x) << S_CPL_RX_MPS_PKT_TYPE) 3180 #define G_CPL_RX_MPS_PKT_TYPE(x) \ 3181 (((x) >> S_CPL_RX_MPS_PKT_TYPE) & M_CPL_RX_MPS_PKT_TYPE) 3182 3183 /* 3184 * Values for CPL_RX_MPS_PKT_TYPE, a bit-wise orthogonal field. 3185 */ 3186 #define X_CPL_RX_MPS_PKT_TYPE_PAUSE (1 << 0) 3187 #define X_CPL_RX_MPS_PKT_TYPE_PPP (1 << 1) 3188 #define X_CPL_RX_MPS_PKT_TYPE_QFC (1 << 2) 3189 #define X_CPL_RX_MPS_PKT_TYPE_PTP (1 << 3) 3190 3191 struct cpl_tx_tls_sfo { 3192 __be32 op_to_seg_len; 3193 __be32 pld_len; 3194 __be32 type_protover; 3195 __be32 r1_lo; 3196 __be32 seqno_numivs; 3197 __be32 ivgen_hdrlen; 3198 __be64 scmd1; 3199 }; 3200 3201 /* cpl_tx_tls_sfo macros */ 3202 #define S_CPL_TX_TLS_SFO_OPCODE 24 3203 #define M_CPL_TX_TLS_SFO_OPCODE 0xff 3204 #define V_CPL_TX_TLS_SFO_OPCODE(x) ((x) << S_CPL_TX_TLS_SFO_OPCODE) 3205 #define G_CPL_TX_TLS_SFO_OPCODE(x) \ 3206 (((x) >> S_CPL_TX_TLS_SFO_OPCODE) & M_CPL_TX_TLS_SFO_OPCODE) 3207 3208 #define S_CPL_TX_TLS_SFO_DATA_TYPE 20 3209 #define M_CPL_TX_TLS_SFO_DATA_TYPE 0xf 3210 #define V_CPL_TX_TLS_SFO_DATA_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_DATA_TYPE) 3211 #define G_CPL_TX_TLS_SFO_DATA_TYPE(x) \ 3212 (((x) >> S_CPL_TX_TLS_SFO_DATA_TYPE) & M_CPL_TX_TLS_SFO_DATA_TYPE) 3213 3214 #define S_CPL_TX_TLS_SFO_CPL_LEN 16 3215 #define M_CPL_TX_TLS_SFO_CPL_LEN 0xf 3216 #define V_CPL_TX_TLS_SFO_CPL_LEN(x) ((x) << S_CPL_TX_TLS_SFO_CPL_LEN) 3217 #define G_CPL_TX_TLS_SFO_CPL_LEN(x) \ 3218 (((x) >> S_CPL_TX_TLS_SFO_CPL_LEN) & M_CPL_TX_TLS_SFO_CPL_LEN) 3219 3220 #define S_CPL_TX_TLS_SFO_SEG_LEN 0 3221 #define M_CPL_TX_TLS_SFO_SEG_LEN 0xffff 3222 #define V_CPL_TX_TLS_SFO_SEG_LEN(x) ((x) << S_CPL_TX_TLS_SFO_SEG_LEN) 3223 #define G_CPL_TX_TLS_SFO_SEG_LEN(x) \ 3224 (((x) >> S_CPL_TX_TLS_SFO_SEG_LEN) & M_CPL_TX_TLS_SFO_SEG_LEN) 3225 3226 #define S_CPL_TX_TLS_SFO_TYPE 24 3227 #define M_CPL_TX_TLS_SFO_TYPE 0xff 3228 #define V_CPL_TX_TLS_SFO_TYPE(x) ((x) << S_CPL_TX_TLS_SFO_TYPE) 3229 #define G_CPL_TX_TLS_SFO_TYPE(x) \ 3230 (((x) >> S_CPL_TX_TLS_SFO_TYPE) & M_CPL_TX_TLS_SFO_TYPE) 3231 3232 #define S_CPL_TX_TLS_SFO_PROTOVER 8 3233 #define M_CPL_TX_TLS_SFO_PROTOVER 0xffff 3234 #define V_CPL_TX_TLS_SFO_PROTOVER(x) ((x) << S_CPL_TX_TLS_SFO_PROTOVER) 3235 #define G_CPL_TX_TLS_SFO_PROTOVER(x) \ 3236 (((x) >> S_CPL_TX_TLS_SFO_PROTOVER) & M_CPL_TX_TLS_SFO_PROTOVER) 3237 3238 struct cpl_tls_data { 3239 RSS_HDR 3240 union opcode_tid ot; 3241 __be32 length_pkd; 3242 __be32 seq; 3243 __be32 r1; 3244 }; 3245 3246 #define S_CPL_TLS_DATA_OPCODE 24 3247 #define M_CPL_TLS_DATA_OPCODE 0xff 3248 #define V_CPL_TLS_DATA_OPCODE(x) ((x) << S_CPL_TLS_DATA_OPCODE) 3249 #define G_CPL_TLS_DATA_OPCODE(x) \ 3250 (((x) >> S_CPL_TLS_DATA_OPCODE) & M_CPL_TLS_DATA_OPCODE) 3251 3252 #define S_CPL_TLS_DATA_TID 0 3253 #define M_CPL_TLS_DATA_TID 0xffffff 3254 #define V_CPL_TLS_DATA_TID(x) ((x) << S_CPL_TLS_DATA_TID) 3255 #define G_CPL_TLS_DATA_TID(x) \ 3256 (((x) >> S_CPL_TLS_DATA_TID) & M_CPL_TLS_DATA_TID) 3257 3258 #define S_CPL_TLS_DATA_LENGTH 0 3259 #define M_CPL_TLS_DATA_LENGTH 0xffff 3260 #define V_CPL_TLS_DATA_LENGTH(x) ((x) << S_CPL_TLS_DATA_LENGTH) 3261 #define G_CPL_TLS_DATA_LENGTH(x) \ 3262 (((x) >> S_CPL_TLS_DATA_LENGTH) & M_CPL_TLS_DATA_LENGTH) 3263 3264 struct cpl_rx_tls_cmp { 3265 RSS_HDR 3266 union opcode_tid ot; 3267 __be32 pdulength_length; 3268 __be32 seq; 3269 __be32 ddp_report; 3270 __be32 r; 3271 __be32 ddp_valid; 3272 }; 3273 3274 #define S_CPL_RX_TLS_CMP_OPCODE 24 3275 #define M_CPL_RX_TLS_CMP_OPCODE 0xff 3276 #define V_CPL_RX_TLS_CMP_OPCODE(x) ((x) << S_CPL_RX_TLS_CMP_OPCODE) 3277 #define G_CPL_RX_TLS_CMP_OPCODE(x) \ 3278 (((x) >> S_CPL_RX_TLS_CMP_OPCODE) & M_CPL_RX_TLS_CMP_OPCODE) 3279 3280 #define S_CPL_RX_TLS_CMP_TID 0 3281 #define M_CPL_RX_TLS_CMP_TID 0xffffff 3282 #define V_CPL_RX_TLS_CMP_TID(x) ((x) << S_CPL_RX_TLS_CMP_TID) 3283 #define G_CPL_RX_TLS_CMP_TID(x) \ 3284 (((x) >> S_CPL_RX_TLS_CMP_TID) & M_CPL_RX_TLS_CMP_TID) 3285 3286 #define S_CPL_RX_TLS_CMP_PDULENGTH 16 3287 #define M_CPL_RX_TLS_CMP_PDULENGTH 0xffff 3288 #define V_CPL_RX_TLS_CMP_PDULENGTH(x) ((x) << S_CPL_RX_TLS_CMP_PDULENGTH) 3289 #define G_CPL_RX_TLS_CMP_PDULENGTH(x) \ 3290 (((x) >> S_CPL_RX_TLS_CMP_PDULENGTH) & M_CPL_RX_TLS_CMP_PDULENGTH) 3291 3292 #define S_CPL_RX_TLS_CMP_LENGTH 0 3293 #define M_CPL_RX_TLS_CMP_LENGTH 0xffff 3294 #define V_CPL_RX_TLS_CMP_LENGTH(x) ((x) << S_CPL_RX_TLS_CMP_LENGTH) 3295 #define G_CPL_RX_TLS_CMP_LENGTH(x) \ 3296 (((x) >> S_CPL_RX_TLS_CMP_LENGTH) & M_CPL_RX_TLS_CMP_LENGTH) 3297 3298 #define S_SCMD_SEQ_NO_CTRL 29 3299 #define M_SCMD_SEQ_NO_CTRL 0x3 3300 #define V_SCMD_SEQ_NO_CTRL(x) ((x) << S_SCMD_SEQ_NO_CTRL) 3301 #define G_SCMD_SEQ_NO_CTRL(x) \ 3302 (((x) >> S_SCMD_SEQ_NO_CTRL) & M_SCMD_SEQ_NO_CTRL) 3303 3304 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 3305 #define S_SCMD_STATUS_PRESENT 28 3306 #define M_SCMD_STATUS_PRESENT 0x1 3307 #define V_SCMD_STATUS_PRESENT(x) ((x) << S_SCMD_STATUS_PRESENT) 3308 #define G_SCMD_STATUS_PRESENT(x) \ 3309 (((x) >> S_SCMD_STATUS_PRESENT) & M_SCMD_STATUS_PRESENT) 3310 #define F_SCMD_STATUS_PRESENT V_SCMD_STATUS_PRESENT(1U) 3311 3312 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 3313 * 3-15: Reserved. */ 3314 #define S_SCMD_PROTO_VERSION 24 3315 #define M_SCMD_PROTO_VERSION 0xf 3316 #define V_SCMD_PROTO_VERSION(x) ((x) << S_SCMD_PROTO_VERSION) 3317 #define G_SCMD_PROTO_VERSION(x) \ 3318 (((x) >> S_SCMD_PROTO_VERSION) & M_SCMD_PROTO_VERSION) 3319 3320 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 3321 #define S_SCMD_ENC_DEC_CTRL 23 3322 #define M_SCMD_ENC_DEC_CTRL 0x1 3323 #define V_SCMD_ENC_DEC_CTRL(x) ((x) << S_SCMD_ENC_DEC_CTRL) 3324 #define G_SCMD_ENC_DEC_CTRL(x) \ 3325 (((x) >> S_SCMD_ENC_DEC_CTRL) & M_SCMD_ENC_DEC_CTRL) 3326 #define F_SCMD_ENC_DEC_CTRL V_SCMD_ENC_DEC_CTRL(1U) 3327 3328 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 3329 #define S_SCMD_CIPH_AUTH_SEQ_CTRL 22 3330 #define M_SCMD_CIPH_AUTH_SEQ_CTRL 0x1 3331 #define V_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3332 ((x) << S_SCMD_CIPH_AUTH_SEQ_CTRL) 3333 #define G_SCMD_CIPH_AUTH_SEQ_CTRL(x) \ 3334 (((x) >> S_SCMD_CIPH_AUTH_SEQ_CTRL) & M_SCMD_CIPH_AUTH_SEQ_CTRL) 3335 #define F_SCMD_CIPH_AUTH_SEQ_CTRL V_SCMD_CIPH_AUTH_SEQ_CTRL(1U) 3336 3337 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 3338 * 4:Generic-AES, 5-15: Reserved. */ 3339 #define S_SCMD_CIPH_MODE 18 3340 #define M_SCMD_CIPH_MODE 0xf 3341 #define V_SCMD_CIPH_MODE(x) ((x) << S_SCMD_CIPH_MODE) 3342 #define G_SCMD_CIPH_MODE(x) \ 3343 (((x) >> S_SCMD_CIPH_MODE) & M_SCMD_CIPH_MODE) 3344 3345 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 3346 * 4-15: Reserved */ 3347 #define S_SCMD_AUTH_MODE 14 3348 #define M_SCMD_AUTH_MODE 0xf 3349 #define V_SCMD_AUTH_MODE(x) ((x) << S_SCMD_AUTH_MODE) 3350 #define G_SCMD_AUTH_MODE(x) \ 3351 (((x) >> S_SCMD_AUTH_MODE) & M_SCMD_AUTH_MODE) 3352 3353 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 3354 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 3355 */ 3356 #define S_SCMD_HMAC_CTRL 11 3357 #define M_SCMD_HMAC_CTRL 0x7 3358 #define V_SCMD_HMAC_CTRL(x) ((x) << S_SCMD_HMAC_CTRL) 3359 #define G_SCMD_HMAC_CTRL(x) \ 3360 (((x) >> S_SCMD_HMAC_CTRL) & M_SCMD_HMAC_CTRL) 3361 3362 /* IvSize - IV size in units of 2 bytes */ 3363 #define S_SCMD_IV_SIZE 7 3364 #define M_SCMD_IV_SIZE 0xf 3365 #define V_SCMD_IV_SIZE(x) ((x) << S_SCMD_IV_SIZE) 3366 #define G_SCMD_IV_SIZE(x) \ 3367 (((x) >> S_SCMD_IV_SIZE) & M_SCMD_IV_SIZE) 3368 3369 /* NumIVs - Number of IVs */ 3370 #define S_SCMD_NUM_IVS 0 3371 #define M_SCMD_NUM_IVS 0x7f 3372 #define V_SCMD_NUM_IVS(x) ((x) << S_SCMD_NUM_IVS) 3373 #define G_SCMD_NUM_IVS(x) \ 3374 (((x) >> S_SCMD_NUM_IVS) & M_SCMD_NUM_IVS) 3375 3376 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 3377 * (below) are used as Cid (connection id for debug status), these 3378 * bits are padded to zero for forming the 64 bit 3379 * sequence number for TLS 3380 */ 3381 #define S_SCMD_ENB_DBGID 31 3382 #define M_SCMD_ENB_DBGID 0x1 3383 #define V_SCMD_ENB_DBGID(x) ((x) << S_SCMD_ENB_DBGID) 3384 #define G_SCMD_ENB_DBGID(x) \ 3385 (((x) >> S_SCMD_ENB_DBGID) & M_SCMD_ENB_DBGID) 3386 3387 /* IV generation in SW. */ 3388 #define S_SCMD_IV_GEN_CTRL 30 3389 #define M_SCMD_IV_GEN_CTRL 0x1 3390 #define V_SCMD_IV_GEN_CTRL(x) ((x) << S_SCMD_IV_GEN_CTRL) 3391 #define G_SCMD_IV_GEN_CTRL(x) \ 3392 (((x) >> S_SCMD_IV_GEN_CTRL) & M_SCMD_IV_GEN_CTRL) 3393 #define F_SCMD_IV_GEN_CTRL V_SCMD_IV_GEN_CTRL(1U) 3394 3395 /* More frags */ 3396 #define S_SCMD_MORE_FRAGS 20 3397 #define M_SCMD_MORE_FRAGS 0x1 3398 #define V_SCMD_MORE_FRAGS(x) ((x) << S_SCMD_MORE_FRAGS) 3399 #define G_SCMD_MORE_FRAGS(x) (((x) >> S_SCMD_MORE_FRAGS) & M_SCMD_MORE_FRAGS) 3400 3401 /*last frag */ 3402 #define S_SCMD_LAST_FRAG 19 3403 #define M_SCMD_LAST_FRAG 0x1 3404 #define V_SCMD_LAST_FRAG(x) ((x) << S_SCMD_LAST_FRAG) 3405 #define G_SCMD_LAST_FRAG(x) (((x) >> S_SCMD_LAST_FRAG) & M_SCMD_LAST_FRAG) 3406 3407 /* TlsCompPdu */ 3408 #define S_SCMD_TLS_COMPPDU 18 3409 #define M_SCMD_TLS_COMPPDU 0x1 3410 #define V_SCMD_TLS_COMPPDU(x) ((x) << S_SCMD_TLS_COMPPDU) 3411 #define G_SCMD_TLS_COMPPDU(x) (((x) >> S_SCMD_TLS_COMPPDU) & M_SCMD_TLS_COMPPDU) 3412 3413 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 3414 #define S_SCMD_KEY_CTX_INLINE 17 3415 #define M_SCMD_KEY_CTX_INLINE 0x1 3416 #define V_SCMD_KEY_CTX_INLINE(x) ((x) << S_SCMD_KEY_CTX_INLINE) 3417 #define G_SCMD_KEY_CTX_INLINE(x) \ 3418 (((x) >> S_SCMD_KEY_CTX_INLINE) & M_SCMD_KEY_CTX_INLINE) 3419 #define F_SCMD_KEY_CTX_INLINE V_SCMD_KEY_CTX_INLINE(1U) 3420 3421 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 3422 #define S_SCMD_TLS_FRAG_ENABLE 16 3423 #define M_SCMD_TLS_FRAG_ENABLE 0x1 3424 #define V_SCMD_TLS_FRAG_ENABLE(x) ((x) << S_SCMD_TLS_FRAG_ENABLE) 3425 #define G_SCMD_TLS_FRAG_ENABLE(x) \ 3426 (((x) >> S_SCMD_TLS_FRAG_ENABLE) & M_SCMD_TLS_FRAG_ENABLE) 3427 #define F_SCMD_TLS_FRAG_ENABLE V_SCMD_TLS_FRAG_ENABLE(1U) 3428 3429 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 3430 * modes, in this case TLS_TX will drop the PDU and only 3431 * send back the MAC bytes. */ 3432 #define S_SCMD_MAC_ONLY 15 3433 #define M_SCMD_MAC_ONLY 0x1 3434 #define V_SCMD_MAC_ONLY(x) ((x) << S_SCMD_MAC_ONLY) 3435 #define G_SCMD_MAC_ONLY(x) \ 3436 (((x) >> S_SCMD_MAC_ONLY) & M_SCMD_MAC_ONLY) 3437 #define F_SCMD_MAC_ONLY V_SCMD_MAC_ONLY(1U) 3438 3439 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 3440 * which have complex AAD and IV formations Eg:AES-CCM 3441 */ 3442 #define S_SCMD_AADIVDROP 14 3443 #define M_SCMD_AADIVDROP 0x1 3444 #define V_SCMD_AADIVDROP(x) ((x) << S_SCMD_AADIVDROP) 3445 #define G_SCMD_AADIVDROP(x) \ 3446 (((x) >> S_SCMD_AADIVDROP) & M_SCMD_AADIVDROP) 3447 #define F_SCMD_AADIVDROP V_SCMD_AADIVDROP(1U) 3448 3449 /* HdrLength - Length of all headers excluding TLS header 3450 * present before start of crypto PDU/payload. */ 3451 #define S_SCMD_HDR_LEN 0 3452 #define M_SCMD_HDR_LEN 0x3fff 3453 #define V_SCMD_HDR_LEN(x) ((x) << S_SCMD_HDR_LEN) 3454 #define G_SCMD_HDR_LEN(x) \ 3455 (((x) >> S_SCMD_HDR_LEN) & M_SCMD_HDR_LEN) 3456 3457 struct cpl_tx_sec_pdu { 3458 __be32 op_ivinsrtofst; 3459 __be32 pldlen; 3460 __be32 aadstart_cipherstop_hi; 3461 __be32 cipherstop_lo_authinsert; 3462 __be32 seqno_numivs; 3463 __be32 ivgen_hdrlen; 3464 __be64 scmd1; 3465 }; 3466 3467 #define S_CPL_TX_SEC_PDU_OPCODE 24 3468 #define M_CPL_TX_SEC_PDU_OPCODE 0xff 3469 #define V_CPL_TX_SEC_PDU_OPCODE(x) ((x) << S_CPL_TX_SEC_PDU_OPCODE) 3470 #define G_CPL_TX_SEC_PDU_OPCODE(x) \ 3471 (((x) >> S_CPL_TX_SEC_PDU_OPCODE) & M_CPL_TX_SEC_PDU_OPCODE) 3472 3473 /* RX Channel Id */ 3474 #define S_CPL_TX_SEC_PDU_RXCHID 22 3475 #define M_CPL_TX_SEC_PDU_RXCHID 0x1 3476 #define V_CPL_TX_SEC_PDU_RXCHID(x) ((x) << S_CPL_TX_SEC_PDU_RXCHID) 3477 #define G_CPL_TX_SEC_PDU_RXCHID(x) \ 3478 (((x) >> S_CPL_TX_SEC_PDU_RXCHID) & M_CPL_TX_SEC_PDU_RXCHID) 3479 #define F_CPL_TX_SEC_PDU_RXCHID V_CPL_TX_SEC_PDU_RXCHID(1U) 3480 3481 /* Ack Follows */ 3482 #define S_CPL_TX_SEC_PDU_ACKFOLLOWS 21 3483 #define M_CPL_TX_SEC_PDU_ACKFOLLOWS 0x1 3484 #define V_CPL_TX_SEC_PDU_ACKFOLLOWS(x) ((x) << S_CPL_TX_SEC_PDU_ACKFOLLOWS) 3485 #define G_CPL_TX_SEC_PDU_ACKFOLLOWS(x) \ 3486 (((x) >> S_CPL_TX_SEC_PDU_ACKFOLLOWS) & M_CPL_TX_SEC_PDU_ACKFOLLOWS) 3487 #define F_CPL_TX_SEC_PDU_ACKFOLLOWS V_CPL_TX_SEC_PDU_ACKFOLLOWS(1U) 3488 3489 /* Loopback bit in cpl_tx_sec_pdu */ 3490 #define S_CPL_TX_SEC_PDU_ULPTXLPBK 20 3491 #define M_CPL_TX_SEC_PDU_ULPTXLPBK 0x1 3492 #define V_CPL_TX_SEC_PDU_ULPTXLPBK(x) ((x) << S_CPL_TX_SEC_PDU_ULPTXLPBK) 3493 #define G_CPL_TX_SEC_PDU_ULPTXLPBK(x) \ 3494 (((x) >> S_CPL_TX_SEC_PDU_ULPTXLPBK) & M_CPL_TX_SEC_PDU_ULPTXLPBK) 3495 #define F_CPL_TX_SEC_PDU_ULPTXLPBK V_CPL_TX_SEC_PDU_ULPTXLPBK(1U) 3496 3497 /* Length of cpl header encapsulated */ 3498 #define S_CPL_TX_SEC_PDU_CPLLEN 16 3499 #define M_CPL_TX_SEC_PDU_CPLLEN 0xf 3500 #define V_CPL_TX_SEC_PDU_CPLLEN(x) ((x) << S_CPL_TX_SEC_PDU_CPLLEN) 3501 #define G_CPL_TX_SEC_PDU_CPLLEN(x) \ 3502 (((x) >> S_CPL_TX_SEC_PDU_CPLLEN) & M_CPL_TX_SEC_PDU_CPLLEN) 3503 3504 /* PlaceHolder */ 3505 #define S_CPL_TX_SEC_PDU_PLACEHOLDER 10 3506 #define M_CPL_TX_SEC_PDU_PLACEHOLDER 0x1 3507 #define V_CPL_TX_SEC_PDU_PLACEHOLDER(x) ((x) << S_CPL_TX_SEC_PDU_PLACEHOLDER) 3508 #define G_CPL_TX_SEC_PDU_PLACEHOLDER(x) \ 3509 (((x) >> S_CPL_TX_SEC_PDU_PLACEHOLDER) & \ 3510 M_CPL_TX_SEC_PDU_PLACEHOLDER) 3511 3512 /* IvInsrtOffset: Insertion location for IV */ 3513 #define S_CPL_TX_SEC_PDU_IVINSRTOFST 0 3514 #define M_CPL_TX_SEC_PDU_IVINSRTOFST 0x3ff 3515 #define V_CPL_TX_SEC_PDU_IVINSRTOFST(x) ((x) << S_CPL_TX_SEC_PDU_IVINSRTOFST) 3516 #define G_CPL_TX_SEC_PDU_IVINSRTOFST(x) \ 3517 (((x) >> S_CPL_TX_SEC_PDU_IVINSRTOFST) & \ 3518 M_CPL_TX_SEC_PDU_IVINSRTOFST) 3519 3520 /* AadStartOffset: Offset in bytes for AAD start from 3521 * the first byte following 3522 * the pkt headers (0-255 3523 * bytes) */ 3524 #define S_CPL_TX_SEC_PDU_AADSTART 24 3525 #define M_CPL_TX_SEC_PDU_AADSTART 0xff 3526 #define V_CPL_TX_SEC_PDU_AADSTART(x) ((x) << S_CPL_TX_SEC_PDU_AADSTART) 3527 #define G_CPL_TX_SEC_PDU_AADSTART(x) \ 3528 (((x) >> S_CPL_TX_SEC_PDU_AADSTART) & \ 3529 M_CPL_TX_SEC_PDU_AADSTART) 3530 3531 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 3532 * the pkt headers (0-511 bytes) */ 3533 #define S_CPL_TX_SEC_PDU_AADSTOP 15 3534 #define M_CPL_TX_SEC_PDU_AADSTOP 0x1ff 3535 #define V_CPL_TX_SEC_PDU_AADSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AADSTOP) 3536 #define G_CPL_TX_SEC_PDU_AADSTOP(x) \ 3537 (((x) >> S_CPL_TX_SEC_PDU_AADSTOP) & M_CPL_TX_SEC_PDU_AADSTOP) 3538 3539 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 3540 * first byte following the pkt headers (0-1023 3541 * bytes) */ 3542 #define S_CPL_TX_SEC_PDU_CIPHERSTART 5 3543 #define M_CPL_TX_SEC_PDU_CIPHERSTART 0x3ff 3544 #define V_CPL_TX_SEC_PDU_CIPHERSTART(x) ((x) << S_CPL_TX_SEC_PDU_CIPHERSTART) 3545 #define G_CPL_TX_SEC_PDU_CIPHERSTART(x) \ 3546 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTART) & \ 3547 M_CPL_TX_SEC_PDU_CIPHERSTART) 3548 3549 /* CipherStopOffset: offset in bytes for encryption/decryption end 3550 * from end of the payload of this command (0-511 bytes) */ 3551 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0 3552 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_HI 0x1f 3553 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3554 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3555 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_HI(x) \ 3556 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_HI) & \ 3557 M_CPL_TX_SEC_PDU_CIPHERSTOP_HI) 3558 3559 #define S_CPL_TX_SEC_PDU_CIPHERSTOP_LO 28 3560 #define M_CPL_TX_SEC_PDU_CIPHERSTOP_LO 0xf 3561 #define V_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3562 ((x) << S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3563 #define G_CPL_TX_SEC_PDU_CIPHERSTOP_LO(x) \ 3564 (((x) >> S_CPL_TX_SEC_PDU_CIPHERSTOP_LO) & \ 3565 M_CPL_TX_SEC_PDU_CIPHERSTOP_LO) 3566 3567 /* AuthStartOffset: offset in bytes for authentication start from 3568 * the first byte following the pkt headers (0-1023) 3569 * */ 3570 #define S_CPL_TX_SEC_PDU_AUTHSTART 18 3571 #define M_CPL_TX_SEC_PDU_AUTHSTART 0x3ff 3572 #define V_CPL_TX_SEC_PDU_AUTHSTART(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTART) 3573 #define G_CPL_TX_SEC_PDU_AUTHSTART(x) \ 3574 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTART) & \ 3575 M_CPL_TX_SEC_PDU_AUTHSTART) 3576 3577 /* AuthStopOffset: offset in bytes for authentication 3578 * end from end of the payload of this command (0-511 Bytes) */ 3579 #define S_CPL_TX_SEC_PDU_AUTHSTOP 9 3580 #define M_CPL_TX_SEC_PDU_AUTHSTOP 0x1ff 3581 #define V_CPL_TX_SEC_PDU_AUTHSTOP(x) ((x) << S_CPL_TX_SEC_PDU_AUTHSTOP) 3582 #define G_CPL_TX_SEC_PDU_AUTHSTOP(x) \ 3583 (((x) >> S_CPL_TX_SEC_PDU_AUTHSTOP) & \ 3584 M_CPL_TX_SEC_PDU_AUTHSTOP) 3585 3586 /* AuthInsrtOffset: offset in bytes for authentication insertion 3587 * from end of the payload of this command (0-511 bytes) */ 3588 #define S_CPL_TX_SEC_PDU_AUTHINSERT 0 3589 #define M_CPL_TX_SEC_PDU_AUTHINSERT 0x1ff 3590 #define V_CPL_TX_SEC_PDU_AUTHINSERT(x) ((x) << S_CPL_TX_SEC_PDU_AUTHINSERT) 3591 #define G_CPL_TX_SEC_PDU_AUTHINSERT(x) \ 3592 (((x) >> S_CPL_TX_SEC_PDU_AUTHINSERT) & \ 3593 M_CPL_TX_SEC_PDU_AUTHINSERT) 3594 3595 struct cpl_rx_phys_dsgl { 3596 __be32 op_to_tid; 3597 __be32 pcirlxorder_to_noofsgentr; 3598 struct rss_header rss_hdr_int; 3599 }; 3600 3601 #define S_CPL_RX_PHYS_DSGL_OPCODE 24 3602 #define M_CPL_RX_PHYS_DSGL_OPCODE 0xff 3603 #define V_CPL_RX_PHYS_DSGL_OPCODE(x) ((x) << S_CPL_RX_PHYS_DSGL_OPCODE) 3604 #define G_CPL_RX_PHYS_DSGL_OPCODE(x) \ 3605 (((x) >> S_CPL_RX_PHYS_DSGL_OPCODE) & M_CPL_RX_PHYS_DSGL_OPCODE) 3606 3607 #define S_CPL_RX_PHYS_DSGL_ISRDMA 23 3608 #define M_CPL_RX_PHYS_DSGL_ISRDMA 0x1 3609 #define V_CPL_RX_PHYS_DSGL_ISRDMA(x) ((x) << S_CPL_RX_PHYS_DSGL_ISRDMA) 3610 #define G_CPL_RX_PHYS_DSGL_ISRDMA(x) \ 3611 (((x) >> S_CPL_RX_PHYS_DSGL_ISRDMA) & M_CPL_RX_PHYS_DSGL_ISRDMA) 3612 #define F_CPL_RX_PHYS_DSGL_ISRDMA V_CPL_RX_PHYS_DSGL_ISRDMA(1U) 3613 3614 #define S_CPL_RX_PHYS_DSGL_RSVD1 20 3615 #define M_CPL_RX_PHYS_DSGL_RSVD1 0x7 3616 #define V_CPL_RX_PHYS_DSGL_RSVD1(x) ((x) << S_CPL_RX_PHYS_DSGL_RSVD1) 3617 #define G_CPL_RX_PHYS_DSGL_RSVD1(x) \ 3618 (((x) >> S_CPL_RX_PHYS_DSGL_RSVD1) & M_CPL_RX_PHYS_DSGL_RSVD1) 3619 3620 #define S_CPL_RX_PHYS_DSGL_PCIRLXORDER 31 3621 #define M_CPL_RX_PHYS_DSGL_PCIRLXORDER 0x1 3622 #define V_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3623 ((x) << S_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3624 #define G_CPL_RX_PHYS_DSGL_PCIRLXORDER(x) \ 3625 (((x) >> S_CPL_RX_PHYS_DSGL_PCIRLXORDER) & \ 3626 M_CPL_RX_PHYS_DSGL_PCIRLXORDER) 3627 #define F_CPL_RX_PHYS_DSGL_PCIRLXORDER V_CPL_RX_PHYS_DSGL_PCIRLXORDER(1U) 3628 3629 #define S_CPL_RX_PHYS_DSGL_PCINOSNOOP 30 3630 #define M_CPL_RX_PHYS_DSGL_PCINOSNOOP 0x1 3631 #define V_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3632 ((x) << S_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3633 #define G_CPL_RX_PHYS_DSGL_PCINOSNOOP(x) \ 3634 (((x) >> S_CPL_RX_PHYS_DSGL_PCINOSNOOP) & \ 3635 M_CPL_RX_PHYS_DSGL_PCINOSNOOP) 3636 #define F_CPL_RX_PHYS_DSGL_PCINOSNOOP V_CPL_RX_PHYS_DSGL_PCINOSNOOP(1U) 3637 3638 #define S_CPL_RX_PHYS_DSGL_PCITPHNTENB 29 3639 #define M_CPL_RX_PHYS_DSGL_PCITPHNTENB 0x1 3640 #define V_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3641 ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3642 #define G_CPL_RX_PHYS_DSGL_PCITPHNTENB(x) \ 3643 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNTENB) & \ 3644 M_CPL_RX_PHYS_DSGL_PCITPHNTENB) 3645 #define F_CPL_RX_PHYS_DSGL_PCITPHNTENB V_CPL_RX_PHYS_DSGL_PCITPHNTENB(1U) 3646 3647 #define S_CPL_RX_PHYS_DSGL_PCITPHNT 27 3648 #define M_CPL_RX_PHYS_DSGL_PCITPHNT 0x3 3649 #define V_CPL_RX_PHYS_DSGL_PCITPHNT(x) ((x) << S_CPL_RX_PHYS_DSGL_PCITPHNT) 3650 #define G_CPL_RX_PHYS_DSGL_PCITPHNT(x) \ 3651 (((x) >> S_CPL_RX_PHYS_DSGL_PCITPHNT) & \ 3652 M_CPL_RX_PHYS_DSGL_PCITPHNT) 3653 3654 #define S_CPL_RX_PHYS_DSGL_DCAID 16 3655 #define M_CPL_RX_PHYS_DSGL_DCAID 0x7ff 3656 #define V_CPL_RX_PHYS_DSGL_DCAID(x) ((x) << S_CPL_RX_PHYS_DSGL_DCAID) 3657 #define G_CPL_RX_PHYS_DSGL_DCAID(x) \ 3658 (((x) >> S_CPL_RX_PHYS_DSGL_DCAID) & \ 3659 M_CPL_RX_PHYS_DSGL_DCAID) 3660 3661 #define S_CPL_RX_PHYS_DSGL_NOOFSGENTR 0 3662 #define M_CPL_RX_PHYS_DSGL_NOOFSGENTR 0xffff 3663 #define V_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3664 ((x) << S_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3665 #define G_CPL_RX_PHYS_DSGL_NOOFSGENTR(x) \ 3666 (((x) >> S_CPL_RX_PHYS_DSGL_NOOFSGENTR) & \ 3667 M_CPL_RX_PHYS_DSGL_NOOFSGENTR) 3668 3669 /* CPL_TX_TLS_ACK */ 3670 struct cpl_tx_tls_ack { 3671 __be32 op_to_Rsvd2; 3672 __be32 PldLen; 3673 __be64 Rsvd3; 3674 }; 3675 3676 #define S_CPL_TX_TLS_ACK_OPCODE 24 3677 #define M_CPL_TX_TLS_ACK_OPCODE 0xff 3678 #define V_CPL_TX_TLS_ACK_OPCODE(x) ((x) << S_CPL_TX_TLS_ACK_OPCODE) 3679 #define G_CPL_TX_TLS_ACK_OPCODE(x) \ 3680 (((x) >> S_CPL_TX_TLS_ACK_OPCODE) & M_CPL_TX_TLS_ACK_OPCODE) 3681 3682 #define S_CPL_TX_TLS_ACK_RSVD1 23 3683 #define M_CPL_TX_TLS_ACK_RSVD1 0x1 3684 #define V_CPL_TX_TLS_ACK_RSVD1(x) ((x) << S_CPL_TX_TLS_ACK_RSVD1) 3685 #define G_CPL_TX_TLS_ACK_RSVD1(x) \ 3686 (((x) >> S_CPL_TX_TLS_ACK_RSVD1) & M_CPL_TX_TLS_ACK_RSVD1) 3687 #define F_CPL_TX_TLS_ACK_RSVD1 V_CPL_TX_TLS_ACK_RSVD1(1U) 3688 3689 #define S_CPL_TX_TLS_ACK_RXCHID 22 3690 #define M_CPL_TX_TLS_ACK_RXCHID 0x1 3691 #define V_CPL_TX_TLS_ACK_RXCHID(x) ((x) << S_CPL_TX_TLS_ACK_RXCHID) 3692 #define G_CPL_TX_TLS_ACK_RXCHID(x) \ 3693 (((x) >> S_CPL_TX_TLS_ACK_RXCHID) & M_CPL_TX_TLS_ACK_RXCHID) 3694 #define F_CPL_TX_TLS_ACK_RXCHID V_CPL_TX_TLS_ACK_RXCHID(1U) 3695 3696 #define S_CPL_TX_TLS_ACK_FWMSG 21 3697 #define M_CPL_TX_TLS_ACK_FWMSG 0x1 3698 #define V_CPL_TX_TLS_ACK_FWMSG(x) ((x) << S_CPL_TX_TLS_ACK_FWMSG) 3699 #define G_CPL_TX_TLS_ACK_FWMSG(x) \ 3700 (((x) >> S_CPL_TX_TLS_ACK_FWMSG) & M_CPL_TX_TLS_ACK_FWMSG) 3701 #define F_CPL_TX_TLS_ACK_FWMSG V_CPL_TX_TLS_ACK_FWMSG(1U) 3702 3703 #define S_CPL_TX_TLS_ACK_ULPTXLPBK 20 3704 #define M_CPL_TX_TLS_ACK_ULPTXLPBK 0x1 3705 #define V_CPL_TX_TLS_ACK_ULPTXLPBK(x) ((x) << S_CPL_TX_TLS_ACK_ULPTXLPBK) 3706 #define G_CPL_TX_TLS_ACK_ULPTXLPBK(x) \ 3707 (((x) >> S_CPL_TX_TLS_ACK_ULPTXLPBK) & M_CPL_TX_TLS_ACK_ULPTXLPBK) 3708 #define F_CPL_TX_TLS_ACK_ULPTXLPBK V_CPL_TX_TLS_ACK_ULPTXLPBK(1U) 3709 3710 #define S_CPL_TX_TLS_ACK_CPLLEN 16 3711 #define M_CPL_TX_TLS_ACK_CPLLEN 0xf 3712 #define V_CPL_TX_TLS_ACK_CPLLEN(x) ((x) << S_CPL_TX_TLS_ACK_CPLLEN) 3713 #define G_CPL_TX_TLS_ACK_CPLLEN(x) \ 3714 (((x) >> S_CPL_TX_TLS_ACK_CPLLEN) & M_CPL_TX_TLS_ACK_CPLLEN) 3715 3716 #define S_CPL_TX_TLS_ACK_COMPLONERR 15 3717 #define M_CPL_TX_TLS_ACK_COMPLONERR 0x1 3718 #define V_CPL_TX_TLS_ACK_COMPLONERR(x) ((x) << S_CPL_TX_TLS_ACK_COMPLONERR) 3719 #define G_CPL_TX_TLS_ACK_COMPLONERR(x) \ 3720 (((x) >> S_CPL_TX_TLS_ACK_COMPLONERR) & M_CPL_TX_TLS_ACK_COMPLONERR) 3721 #define F_CPL_TX_TLS_ACK_COMPLONERR V_CPL_TX_TLS_ACK_COMPLONERR(1U) 3722 3723 #define S_CPL_TX_TLS_ACK_LCB 14 3724 #define M_CPL_TX_TLS_ACK_LCB 0x1 3725 #define V_CPL_TX_TLS_ACK_LCB(x) ((x) << S_CPL_TX_TLS_ACK_LCB) 3726 #define G_CPL_TX_TLS_ACK_LCB(x) \ 3727 (((x) >> S_CPL_TX_TLS_ACK_LCB) & M_CPL_TX_TLS_ACK_LCB) 3728 #define F_CPL_TX_TLS_ACK_LCB V_CPL_TX_TLS_ACK_LCB(1U) 3729 3730 #define S_CPL_TX_TLS_ACK_PHASH 13 3731 #define M_CPL_TX_TLS_ACK_PHASH 0x1 3732 #define V_CPL_TX_TLS_ACK_PHASH(x) ((x) << S_CPL_TX_TLS_ACK_PHASH) 3733 #define G_CPL_TX_TLS_ACK_PHASH(x) \ 3734 (((x) >> S_CPL_TX_TLS_ACK_PHASH) & M_CPL_TX_TLS_ACK_PHASH) 3735 #define F_CPL_TX_TLS_ACK_PHASH V_CPL_TX_TLS_ACK_PHASH(1U) 3736 3737 #define S_CPL_TX_TLS_ACK_RSVD2 0 3738 #define M_CPL_TX_TLS_ACK_RSVD2 0x1fff 3739 #define V_CPL_TX_TLS_ACK_RSVD2(x) ((x) << S_CPL_TX_TLS_ACK_RSVD2) 3740 #define G_CPL_TX_TLS_ACK_RSVD2(x) \ 3741 (((x) >> S_CPL_TX_TLS_ACK_RSVD2) & M_CPL_TX_TLS_ACK_RSVD2) 3742 3743 #endif /* T4_MSG_H */ 3744