1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef T4_MSG_H 31 #define T4_MSG_H 32 33 enum { 34 CPL_PASS_OPEN_REQ = 0x1, 35 CPL_PASS_ACCEPT_RPL = 0x2, 36 CPL_ACT_OPEN_REQ = 0x3, 37 CPL_SET_TCB = 0x4, 38 CPL_SET_TCB_FIELD = 0x5, 39 CPL_GET_TCB = 0x6, 40 CPL_PCMD = 0x7, 41 CPL_CLOSE_CON_REQ = 0x8, 42 CPL_CLOSE_LISTSRV_REQ = 0x9, 43 CPL_ABORT_REQ = 0xA, 44 CPL_ABORT_RPL = 0xB, 45 CPL_TX_DATA = 0xC, 46 CPL_RX_DATA_ACK = 0xD, 47 CPL_TX_PKT = 0xE, 48 CPL_RTE_DELETE_REQ = 0xF, 49 CPL_RTE_WRITE_REQ = 0x10, 50 CPL_RTE_READ_REQ = 0x11, 51 CPL_L2T_WRITE_REQ = 0x12, 52 CPL_L2T_READ_REQ = 0x13, 53 CPL_SMT_WRITE_REQ = 0x14, 54 CPL_SMT_READ_REQ = 0x15, 55 CPL_BARRIER = 0x18, 56 CPL_TID_RELEASE = 0x1A, 57 CPL_RX_MPS_PKT = 0x1B, 58 59 CPL_CLOSE_LISTSRV_RPL = 0x20, 60 CPL_ERROR = 0x21, 61 CPL_GET_TCB_RPL = 0x22, 62 CPL_L2T_WRITE_RPL = 0x23, 63 CPL_PASS_OPEN_RPL = 0x24, 64 CPL_ACT_OPEN_RPL = 0x25, 65 CPL_PEER_CLOSE = 0x26, 66 CPL_RTE_DELETE_RPL = 0x27, 67 CPL_RTE_WRITE_RPL = 0x28, 68 CPL_RX_URG_PKT = 0x29, 69 CPL_ABORT_REQ_RSS = 0x2B, 70 CPL_RX_URG_NOTIFY = 0x2C, 71 CPL_ABORT_RPL_RSS = 0x2D, 72 CPL_SMT_WRITE_RPL = 0x2E, 73 CPL_TX_DATA_ACK = 0x2F, 74 75 CPL_RX_PHYS_ADDR = 0x30, 76 CPL_PCMD_READ_RPL = 0x31, 77 CPL_CLOSE_CON_RPL = 0x32, 78 CPL_ISCSI_HDR = 0x33, 79 CPL_L2T_READ_RPL = 0x34, 80 CPL_RDMA_CQE = 0x35, 81 CPL_RDMA_CQE_READ_RSP = 0x36, 82 CPL_RDMA_CQE_ERR = 0x37, 83 CPL_RTE_READ_RPL = 0x38, 84 CPL_RX_DATA = 0x39, 85 CPL_SET_TCB_RPL = 0x3A, 86 CPL_RX_PKT = 0x3B, 87 CPL_PCMD_RPL = 0x3C, 88 CPL_HIT_NOTIFY = 0x3D, 89 CPL_PKT_NOTIFY = 0x3E, 90 CPL_RX_DDP_COMPLETE = 0x3F, 91 92 CPL_ACT_ESTABLISH = 0x40, 93 CPL_PASS_ESTABLISH = 0x41, 94 CPL_RX_DATA_DDP = 0x42, 95 CPL_SMT_READ_RPL = 0x43, 96 CPL_PASS_ACCEPT_REQ = 0x44, 97 CPL_RX2TX_PKT = 0x45, 98 CPL_RX_FCOE_DDP = 0x46, 99 CPL_FCOE_HDR = 0x47, 100 101 CPL_RDMA_READ_REQ = 0x60, 102 103 CPL_SET_LE_REQ = 0x80, 104 CPL_PASS_OPEN_REQ6 = 0x81, 105 CPL_ACT_OPEN_REQ6 = 0x83, 106 107 CPL_TX_DMA_ACK = 0xA0, 108 CPL_RDMA_TERMINATE = 0xA2, 109 CPL_RDMA_WRITE = 0xA4, 110 CPL_SGE_EGR_UPDATE = 0xA5, 111 CPL_SET_LE_RPL = 0xA6, 112 CPL_FW2_MSG = 0xA7, 113 CPL_FW2_PLD = 0xA8, 114 115 CPL_TRACE_PKT = 0xB0, 116 CPL_RX2TX_DATA = 0xB1, 117 118 CPL_FW4_MSG = 0xC0, 119 CPL_FW4_PLD = 0xC1, 120 CPL_FW4_ACK = 0xC3, 121 122 CPL_FW6_MSG = 0xE0, 123 CPL_FW6_PLD = 0xE1, 124 CPL_TX_PKT_LSO = 0xED, 125 CPL_TX_PKT_XT = 0xEE, 126 127 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 128 }; 129 130 enum CPL_error { 131 CPL_ERR_NONE = 0, 132 CPL_ERR_TCAM_PARITY = 1, 133 CPL_ERR_TCAM_FULL = 3, 134 CPL_ERR_BAD_LENGTH = 15, 135 CPL_ERR_BAD_ROUTE = 18, 136 CPL_ERR_CONN_RESET = 20, 137 CPL_ERR_CONN_EXIST_SYNRECV = 21, 138 CPL_ERR_CONN_EXIST = 22, 139 CPL_ERR_ARP_MISS = 23, 140 CPL_ERR_BAD_SYN = 24, 141 CPL_ERR_CONN_TIMEDOUT = 30, 142 CPL_ERR_XMIT_TIMEDOUT = 31, 143 CPL_ERR_PERSIST_TIMEDOUT = 32, 144 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 145 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 146 CPL_ERR_RTX_NEG_ADVICE = 35, 147 CPL_ERR_PERSIST_NEG_ADVICE = 36, 148 CPL_ERR_ABORT_FAILED = 42, 149 CPL_ERR_IWARP_FLM = 50, 150 }; 151 152 enum { 153 CPL_CONN_POLICY_AUTO = 0, 154 CPL_CONN_POLICY_ASK = 1, 155 CPL_CONN_POLICY_FILTER = 2, 156 CPL_CONN_POLICY_DENY = 3 157 }; 158 159 enum { 160 ULP_MODE_NONE = 0, 161 ULP_MODE_ISCSI = 2, 162 ULP_MODE_RDMA = 4, 163 ULP_MODE_TCPDDP = 5, 164 ULP_MODE_FCOE = 6, 165 }; 166 167 enum { 168 ULP_CRC_HEADER = 1 << 0, 169 ULP_CRC_DATA = 1 << 1 170 }; 171 172 enum { 173 CPL_PASS_OPEN_ACCEPT, 174 CPL_PASS_OPEN_REJECT, 175 CPL_PASS_OPEN_ACCEPT_TNL 176 }; 177 178 enum { 179 CPL_ABORT_SEND_RST = 0, 180 CPL_ABORT_NO_RST, 181 }; 182 183 enum { /* TX_PKT_XT checksum types */ 184 TX_CSUM_TCP = 0, 185 TX_CSUM_UDP = 1, 186 TX_CSUM_CRC16 = 4, 187 TX_CSUM_CRC32 = 5, 188 TX_CSUM_CRC32C = 6, 189 TX_CSUM_FCOE = 7, 190 TX_CSUM_TCPIP = 8, 191 TX_CSUM_UDPIP = 9, 192 TX_CSUM_TCPIP6 = 10, 193 TX_CSUM_UDPIP6 = 11, 194 TX_CSUM_IP = 12, 195 }; 196 197 enum { /* packet type in CPL_RX_PKT */ 198 PKTYPE_XACT_UCAST = 0, 199 PKTYPE_HASH_UCAST = 1, 200 PKTYPE_XACT_MCAST = 2, 201 PKTYPE_HASH_MCAST = 3, 202 PKTYPE_PROMISC = 4, 203 PKTYPE_HPROMISC = 5, 204 PKTYPE_BCAST = 6 205 }; 206 207 enum { /* DMAC type in CPL_RX_PKT */ 208 DATYPE_UCAST, 209 DATYPE_MCAST, 210 DATYPE_BCAST 211 }; 212 213 enum { /* TCP congestion control algorithms */ 214 CONG_ALG_RENO, 215 CONG_ALG_TAHOE, 216 CONG_ALG_NEWRENO, 217 CONG_ALG_HIGHSPEED 218 }; 219 220 enum { /* RSS hash type */ 221 RSS_HASH_NONE = 0, /* no hash computed */ 222 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */ 223 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */ 224 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */ 225 }; 226 227 enum { /* LE commands */ 228 LE_CMD_READ = 0x4, 229 LE_CMD_WRITE = 0xb 230 }; 231 232 enum { /* LE request size */ 233 LE_SZ_NONE = 0, 234 LE_SZ_33 = 1, 235 LE_SZ_66 = 2, 236 LE_SZ_132 = 3, 237 LE_SZ_264 = 4, 238 LE_SZ_528 = 5 239 }; 240 241 union opcode_tid { 242 __be32 opcode_tid; 243 __u8 opcode; 244 }; 245 246 #define S_CPL_OPCODE 24 247 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE) 248 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF) 249 #define G_TID(x) ((x) & 0xFFFFFF) 250 251 /* tid is assumed to be 24-bits */ 252 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid)) 253 254 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 255 256 /* extract the TID from a CPL command */ 257 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 258 259 /* partitioning of TID fields that also carry a queue id */ 260 #define S_TID_TID 0 261 #define M_TID_TID 0x3fff 262 #define V_TID_TID(x) ((x) << S_TID_TID) 263 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID) 264 265 #define S_TID_QID 14 266 #define M_TID_QID 0x3ff 267 #define V_TID_QID(x) ((x) << S_TID_QID) 268 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID) 269 270 union opcode_info { 271 __be64 opcode_info; 272 __u8 opcode; 273 }; 274 275 struct tcp_options { 276 __be16 mss; 277 __u8 wsf; 278 #if defined(__LITTLE_ENDIAN_BITFIELD) 279 __u8 :4; 280 __u8 unknown:1; 281 __u8 :1; 282 __u8 sack:1; 283 __u8 tstamp:1; 284 #else 285 __u8 tstamp:1; 286 __u8 sack:1; 287 __u8 :1; 288 __u8 unknown:1; 289 __u8 :4; 290 #endif 291 }; 292 293 struct rss_header { 294 __u8 opcode; 295 #if defined(__LITTLE_ENDIAN_BITFIELD) 296 __u8 channel:2; 297 __u8 filter_hit:1; 298 __u8 filter_tid:1; 299 __u8 hash_type:2; 300 __u8 ipv6:1; 301 __u8 send2fw:1; 302 #else 303 __u8 send2fw:1; 304 __u8 ipv6:1; 305 __u8 hash_type:2; 306 __u8 filter_tid:1; 307 __u8 filter_hit:1; 308 __u8 channel:2; 309 #endif 310 __be16 qid; 311 __be32 hash_val; 312 }; 313 314 #define S_HASHTYPE 20 315 #define M_HASHTYPE 0x3 316 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 317 318 #define S_QNUM 0 319 #define M_QNUM 0xFFFF 320 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 321 322 #ifndef CHELSIO_FW 323 struct work_request_hdr { 324 __be32 wr_hi; 325 __be32 wr_mid; 326 __be64 wr_lo; 327 }; 328 329 /* wr_mid fields */ 330 #define S_WR_LEN16 0 331 #define M_WR_LEN16 0xFF 332 #define V_WR_LEN16(x) ((x) << S_WR_LEN16) 333 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16) 334 335 /* wr_hi fields */ 336 #define S_WR_OP 24 337 #define M_WR_OP 0xFF 338 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP) 339 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 340 341 # define WR_HDR struct work_request_hdr wr 342 # define WR_HDR_SIZE sizeof(struct work_request_hdr) 343 # define RSS_HDR 344 #else 345 # define WR_HDR 346 # define WR_HDR_SIZE 0 347 # define RSS_HDR struct rss_header rss_hdr; 348 #endif 349 350 /* option 0 fields */ 351 #define S_ACCEPT_MODE 0 352 #define M_ACCEPT_MODE 0x3 353 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE) 354 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE) 355 356 #define S_TX_CHAN 2 357 #define M_TX_CHAN 0x3 358 #define V_TX_CHAN(x) ((x) << S_TX_CHAN) 359 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN) 360 361 #define S_NO_CONG 4 362 #define V_NO_CONG(x) ((x) << S_NO_CONG) 363 #define F_NO_CONG V_NO_CONG(1U) 364 365 #define S_DELACK 5 366 #define V_DELACK(x) ((x) << S_DELACK) 367 #define F_DELACK V_DELACK(1U) 368 369 #define S_INJECT_TIMER 6 370 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 371 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 372 373 #define S_NON_OFFLOAD 7 374 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD) 375 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U) 376 377 #define S_ULP_MODE 8 378 #define M_ULP_MODE 0xF 379 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 380 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 381 382 #define S_RCV_BUFSIZ 12 383 #define M_RCV_BUFSIZ 0x3FFU 384 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 385 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 386 387 #define S_DSCP 22 388 #define M_DSCP 0x3F 389 #define V_DSCP(x) ((x) << S_DSCP) 390 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP) 391 392 #define S_SMAC_SEL 28 393 #define M_SMAC_SEL 0xFF 394 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL) 395 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL) 396 397 #define S_L2T_IDX 36 398 #define M_L2T_IDX 0xFFF 399 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX) 400 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 401 402 #define S_TCAM_BYPASS 48 403 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS) 404 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL) 405 406 #define S_NAGLE 49 407 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE) 408 #define F_NAGLE V_NAGLE(1ULL) 409 410 #define S_WND_SCALE 50 411 #define M_WND_SCALE 0xF 412 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE) 413 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 414 415 #define S_KEEP_ALIVE 54 416 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE) 417 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL) 418 419 #define S_MAX_RT 55 420 #define M_MAX_RT 0xF 421 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT) 422 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT) 423 424 #define S_MAX_RT_OVERRIDE 59 425 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE) 426 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL) 427 428 #define S_MSS_IDX 60 429 #define M_MSS_IDX 0xF 430 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX) 431 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 432 433 /* option 1 fields */ 434 #define S_SYN_RSS_ENABLE 0 435 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE) 436 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U) 437 438 #define S_SYN_RSS_USE_HASH 1 439 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH) 440 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U) 441 442 #define S_SYN_RSS_QUEUE 2 443 #define M_SYN_RSS_QUEUE 0x3FF 444 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE) 445 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE) 446 447 #define S_LISTEN_INTF 12 448 #define M_LISTEN_INTF 0xFF 449 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF) 450 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF) 451 452 #define S_LISTEN_FILTER 20 453 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER) 454 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U) 455 456 #define S_SYN_DEFENSE 21 457 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 458 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 459 460 #define S_CONN_POLICY 22 461 #define M_CONN_POLICY 0x3 462 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 463 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 464 465 /* option 2 fields */ 466 #define S_RSS_QUEUE 0 467 #define M_RSS_QUEUE 0x3FF 468 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE) 469 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE) 470 471 #define S_RSS_QUEUE_VALID 10 472 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID) 473 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U) 474 475 #define S_RX_COALESCE_VALID 11 476 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 477 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 478 479 #define S_RX_COALESCE 12 480 #define M_RX_COALESCE 0x3 481 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 482 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 483 484 #define S_CONG_CNTRL 14 485 #define M_CONG_CNTRL 0x3 486 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL) 487 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL) 488 489 #define S_PACE 16 490 #define M_PACE 0x3 491 #define V_PACE(x) ((x) << S_PACE) 492 #define G_PACE(x) (((x) >> S_PACE) & M_PACE) 493 494 #define S_CONG_CNTRL_VALID 18 495 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID) 496 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U) 497 498 #define S_PACE_VALID 19 499 #define V_PACE_VALID(x) ((x) << S_PACE_VALID) 500 #define F_PACE_VALID V_PACE_VALID(1U) 501 502 #define S_RX_FC_DISABLE 20 503 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 504 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 505 506 #define S_RX_FC_DDP 21 507 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP) 508 #define F_RX_FC_DDP V_RX_FC_DDP(1U) 509 510 #define S_RX_FC_VALID 22 511 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 512 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 513 514 #define S_TX_QUEUE 23 515 #define M_TX_QUEUE 0x7 516 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE) 517 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE) 518 519 #define S_RX_CHANNEL 26 520 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL) 521 #define F_RX_CHANNEL V_RX_CHANNEL(1U) 522 523 #define S_CCTRL_ECN 27 524 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN) 525 #define F_CCTRL_ECN V_CCTRL_ECN(1U) 526 527 #define S_WND_SCALE_EN 28 528 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN) 529 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U) 530 531 #define S_TSTAMPS_EN 29 532 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN) 533 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U) 534 535 #define S_SACK_EN 30 536 #define V_SACK_EN(x) ((x) << S_SACK_EN) 537 #define F_SACK_EN V_SACK_EN(1U) 538 539 struct cpl_pass_open_req { 540 WR_HDR; 541 union opcode_tid ot; 542 __be16 local_port; 543 __be16 peer_port; 544 __be32 local_ip; 545 __be32 peer_ip; 546 __be64 opt0; 547 __be64 opt1; 548 }; 549 550 struct cpl_pass_open_req6 { 551 WR_HDR; 552 union opcode_tid ot; 553 __be16 local_port; 554 __be16 peer_port; 555 __be64 local_ip_hi; 556 __be64 local_ip_lo; 557 __be64 peer_ip_hi; 558 __be64 peer_ip_lo; 559 __be64 opt0; 560 __be64 opt1; 561 }; 562 563 struct cpl_pass_open_rpl { 564 RSS_HDR 565 union opcode_tid ot; 566 __u8 rsvd[3]; 567 __u8 status; 568 }; 569 570 struct cpl_pass_establish { 571 RSS_HDR 572 union opcode_tid ot; 573 __be32 rsvd; 574 __be32 tos_stid; 575 __be16 mac_idx; 576 __be16 tcp_opt; 577 __be32 snd_isn; 578 __be32 rcv_isn; 579 }; 580 581 /* cpl_pass_establish.tos_stid fields */ 582 #define S_PASS_OPEN_TID 0 583 #define M_PASS_OPEN_TID 0xFFFFFF 584 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 585 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 586 587 #define S_PASS_OPEN_TOS 24 588 #define M_PASS_OPEN_TOS 0xFF 589 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 590 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 591 592 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 593 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 594 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 595 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 596 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 597 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 598 599 struct cpl_pass_accept_req { 600 RSS_HDR 601 union opcode_tid ot; 602 __be16 rsvd; 603 __be16 len; 604 __be32 hdr_len; 605 __be16 vlan; 606 __be16 l2info; 607 __be32 tos_stid; 608 struct tcp_options tcpopt; 609 }; 610 611 /* cpl_pass_accept_req.hdr_len fields */ 612 #define S_SYN_RX_CHAN 0 613 #define M_SYN_RX_CHAN 0xF 614 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN) 615 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN) 616 617 #define S_TCP_HDR_LEN 10 618 #define M_TCP_HDR_LEN 0x3F 619 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN) 620 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN) 621 622 #define S_IP_HDR_LEN 16 623 #define M_IP_HDR_LEN 0x3FF 624 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN) 625 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN) 626 627 #define S_ETH_HDR_LEN 26 628 #define M_ETH_HDR_LEN 0x1F 629 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN) 630 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN) 631 632 /* cpl_pass_accept_req.l2info fields */ 633 #define S_SYN_MAC_IDX 0 634 #define M_SYN_MAC_IDX 0x1FF 635 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX) 636 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX) 637 638 #define S_SYN_XACT_MATCH 9 639 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH) 640 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U) 641 642 #define S_SYN_INTF 12 643 #define M_SYN_INTF 0xF 644 #define V_SYN_INTF(x) ((x) << S_SYN_INTF) 645 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF) 646 647 struct cpl_pass_accept_rpl { 648 WR_HDR; 649 union opcode_tid ot; 650 __be32 opt2; 651 __be64 opt0; 652 }; 653 654 struct cpl_act_open_req { 655 WR_HDR; 656 union opcode_tid ot; 657 __be16 local_port; 658 __be16 peer_port; 659 __be32 local_ip; 660 __be32 peer_ip; 661 __be64 opt0; 662 __be32 params; 663 __be32 opt2; 664 }; 665 666 /* cpl_act_open_req.params fields XXX */ 667 #define S_AOPEN_VLAN_PRI 9 668 #define M_AOPEN_VLAN_PRI 0x3 669 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 670 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 671 672 #define S_AOPEN_VLAN_PRI_VALID 11 673 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 674 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 675 676 #define S_AOPEN_PKT_TYPE 12 677 #define M_AOPEN_PKT_TYPE 0x3 678 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 679 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 680 681 #define S_AOPEN_MAC_MATCH 14 682 #define M_AOPEN_MAC_MATCH 0x1F 683 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 684 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 685 686 #define S_AOPEN_MAC_MATCH_VALID 19 687 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 688 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 689 690 #define S_AOPEN_IFF_VLAN 20 691 #define M_AOPEN_IFF_VLAN 0xFFF 692 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 693 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 694 695 struct cpl_act_open_req6 { 696 WR_HDR; 697 union opcode_tid ot; 698 __be16 local_port; 699 __be16 peer_port; 700 __be64 local_ip_hi; 701 __be64 local_ip_lo; 702 __be64 peer_ip_hi; 703 __be64 peer_ip_lo; 704 __be64 opt0; 705 __be32 params; 706 __be32 opt2; 707 }; 708 709 struct cpl_act_open_rpl { 710 RSS_HDR 711 union opcode_tid ot; 712 __be32 atid_status; 713 }; 714 715 /* cpl_act_open_rpl.atid_status fields */ 716 #define S_AOPEN_STATUS 0 717 #define M_AOPEN_STATUS 0xFF 718 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS) 719 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS) 720 721 #define S_AOPEN_ATID 8 722 #define M_AOPEN_ATID 0xFFFFFF 723 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID) 724 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID) 725 726 struct cpl_act_establish { 727 RSS_HDR 728 union opcode_tid ot; 729 __be32 rsvd; 730 __be32 tos_atid; 731 __be16 mac_idx; 732 __be16 tcp_opt; 733 __be32 snd_isn; 734 __be32 rcv_isn; 735 }; 736 737 struct cpl_get_tcb { 738 WR_HDR; 739 union opcode_tid ot; 740 __be16 reply_ctrl; 741 __be16 cookie; 742 }; 743 744 /* cpl_get_tcb.reply_ctrl fields */ 745 #define S_QUEUENO 0 746 #define M_QUEUENO 0x3FF 747 #define V_QUEUENO(x) ((x) << S_QUEUENO) 748 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO) 749 750 #define S_REPLY_CHAN 14 751 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN) 752 #define F_REPLY_CHAN V_REPLY_CHAN(1U) 753 754 #define S_NO_REPLY 15 755 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 756 #define F_NO_REPLY V_NO_REPLY(1U) 757 758 struct cpl_get_tcb_rpl { 759 RSS_HDR 760 union opcode_tid ot; 761 __u8 cookie; 762 __u8 status; 763 __be16 len; 764 }; 765 766 struct cpl_set_tcb { 767 WR_HDR; 768 union opcode_tid ot; 769 __be16 reply_ctrl; 770 __be16 cookie; 771 }; 772 773 struct cpl_set_tcb_field { 774 WR_HDR; 775 union opcode_tid ot; 776 __be16 reply_ctrl; 777 __be16 word_cookie; 778 __be64 mask; 779 __be64 val; 780 }; 781 782 /* cpl_set_tcb_field.word_cookie fields */ 783 #define S_WORD 0 784 #define M_WORD 0x1F 785 #define V_WORD(x) ((x) << S_WORD) 786 #define G_WORD(x) (((x) >> S_WORD) & M_WORD) 787 788 #define S_COOKIE 5 789 #define M_COOKIE 0x7 790 #define V_COOKIE(x) ((x) << S_COOKIE) 791 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE) 792 793 struct cpl_set_tcb_rpl { 794 RSS_HDR 795 union opcode_tid ot; 796 __be16 rsvd; 797 __u8 cookie; 798 __u8 status; 799 __be64 oldval; 800 }; 801 802 struct cpl_close_con_req { 803 WR_HDR; 804 union opcode_tid ot; 805 __be32 rsvd; 806 }; 807 808 struct cpl_close_con_rpl { 809 RSS_HDR 810 union opcode_tid ot; 811 __u8 rsvd[3]; 812 __u8 status; 813 __be32 snd_nxt; 814 __be32 rcv_nxt; 815 }; 816 817 struct cpl_close_listsvr_req { 818 WR_HDR; 819 union opcode_tid ot; 820 __be16 reply_ctrl; 821 __be16 rsvd; 822 }; 823 824 /* additional cpl_close_listsvr_req.reply_ctrl field */ 825 #define S_LISTSVR_IPV6 14 826 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6) 827 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U) 828 829 struct cpl_close_listsvr_rpl { 830 RSS_HDR 831 union opcode_tid ot; 832 __u8 rsvd[3]; 833 __u8 status; 834 }; 835 836 struct cpl_abort_req_rss { 837 RSS_HDR 838 union opcode_tid ot; 839 __u8 rsvd[3]; 840 __u8 status; 841 }; 842 843 struct cpl_abort_req { 844 WR_HDR; 845 union opcode_tid ot; 846 __be32 rsvd0; 847 __u8 rsvd1; 848 __u8 cmd; 849 __u8 rsvd2[6]; 850 }; 851 852 struct cpl_abort_rpl_rss { 853 RSS_HDR 854 union opcode_tid ot; 855 __u8 rsvd[3]; 856 __u8 status; 857 }; 858 859 struct cpl_abort_rpl { 860 WR_HDR; 861 union opcode_tid ot; 862 __be32 rsvd0; 863 __u8 rsvd1; 864 __u8 cmd; 865 __u8 rsvd2[6]; 866 }; 867 868 struct cpl_peer_close { 869 RSS_HDR 870 union opcode_tid ot; 871 __be32 rcv_nxt; 872 }; 873 874 struct cpl_tid_release { 875 WR_HDR; 876 union opcode_tid ot; 877 __be32 rsvd; 878 }; 879 880 struct tx_data_wr { 881 __be32 wr_hi; 882 __be32 wr_lo; 883 __be32 len; 884 __be32 flags; 885 __be32 sndseq; 886 __be32 param; 887 }; 888 889 /* tx_data_wr.flags fields */ 890 #define S_TX_ACK_PAGES 21 891 #define M_TX_ACK_PAGES 0x7 892 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 893 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 894 895 /* tx_data_wr.param fields */ 896 #define S_TX_PORT 0 897 #define M_TX_PORT 0x7 898 #define V_TX_PORT(x) ((x) << S_TX_PORT) 899 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 900 901 #define S_TX_MSS 4 902 #define M_TX_MSS 0xF 903 #define V_TX_MSS(x) ((x) << S_TX_MSS) 904 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 905 906 #define S_TX_QOS 8 907 #define M_TX_QOS 0xFF 908 #define V_TX_QOS(x) ((x) << S_TX_QOS) 909 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 910 911 #define S_TX_SNDBUF 16 912 #define M_TX_SNDBUF 0xFFFF 913 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 914 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 915 916 struct cpl_tx_data { 917 union opcode_tid ot; 918 __be32 len; 919 __be32 rsvd; 920 __be32 flags; 921 }; 922 923 /* cpl_tx_data.flags fields */ 924 #define S_TX_PROXY 5 925 #define V_TX_PROXY(x) ((x) << S_TX_PROXY) 926 #define F_TX_PROXY V_TX_PROXY(1U) 927 928 #define S_TX_ULP_SUBMODE 6 929 #define M_TX_ULP_SUBMODE 0xF 930 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 931 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 932 933 #define S_TX_ULP_MODE 10 934 #define M_TX_ULP_MODE 0xF 935 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 936 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 937 938 #define S_TX_SHOVE 14 939 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 940 #define F_TX_SHOVE V_TX_SHOVE(1U) 941 942 #define S_TX_MORE 15 943 #define V_TX_MORE(x) ((x) << S_TX_MORE) 944 #define F_TX_MORE V_TX_MORE(1U) 945 946 #define S_TX_URG 16 947 #define V_TX_URG(x) ((x) << S_TX_URG) 948 #define F_TX_URG V_TX_URG(1U) 949 950 #define S_TX_FLUSH 17 951 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH) 952 #define F_TX_FLUSH V_TX_FLUSH(1U) 953 954 #define S_TX_SAVE 18 955 #define V_TX_SAVE(x) ((x) << S_TX_SAVE) 956 #define F_TX_SAVE V_TX_SAVE(1U) 957 958 #define S_TX_TNL 19 959 #define V_TX_TNL(x) ((x) << S_TX_TNL) 960 #define F_TX_TNL V_TX_TNL(1U) 961 962 /* additional tx_data_wr.flags fields */ 963 #define S_TX_CPU_IDX 0 964 #define M_TX_CPU_IDX 0x3F 965 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 966 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 967 968 #define S_TX_CLOSE 17 969 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 970 #define F_TX_CLOSE V_TX_CLOSE(1U) 971 972 #define S_TX_INIT 18 973 #define V_TX_INIT(x) ((x) << S_TX_INIT) 974 #define F_TX_INIT V_TX_INIT(1U) 975 976 #define S_TX_IMM_ACK 19 977 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 978 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 979 980 #define S_TX_IMM_DMA 20 981 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 982 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 983 984 struct cpl_tx_data_ack { 985 RSS_HDR 986 union opcode_tid ot; 987 __be32 snd_una; 988 }; 989 990 struct cpl_wr_ack { /* XXX */ 991 RSS_HDR 992 union opcode_tid ot; 993 __be16 credits; 994 __be16 rsvd; 995 __be32 snd_nxt; 996 __be32 snd_una; 997 }; 998 999 struct cpl_tx_pkt_core { 1000 __be32 ctrl0; 1001 __be16 pack; 1002 __be16 len; 1003 __be64 ctrl1; 1004 }; 1005 1006 struct cpl_tx_pkt { 1007 WR_HDR; 1008 struct cpl_tx_pkt_core c; 1009 }; 1010 1011 #define cpl_tx_pkt_xt cpl_tx_pkt 1012 1013 /* cpl_tx_pkt_core.ctrl0 fields */ 1014 #define S_TXPKT_VF 0 1015 #define M_TXPKT_VF 0xFF 1016 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF) 1017 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF) 1018 1019 #define S_TXPKT_PF 8 1020 #define M_TXPKT_PF 0x7 1021 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF) 1022 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF) 1023 1024 #define S_TXPKT_VF_VLD 11 1025 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD) 1026 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U) 1027 1028 #define S_TXPKT_OVLAN_IDX 12 1029 #define M_TXPKT_OVLAN_IDX 0xF 1030 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX) 1031 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX) 1032 1033 #define S_TXPKT_INTF 16 1034 #define M_TXPKT_INTF 0xF 1035 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1036 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1037 1038 #define S_TXPKT_SPECIAL_STAT 20 1039 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT) 1040 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U) 1041 1042 #define S_TXPKT_INS_OVLAN 21 1043 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN) 1044 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U) 1045 1046 #define S_TXPKT_STAT_DIS 22 1047 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS) 1048 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U) 1049 1050 #define S_TXPKT_LOOPBACK 23 1051 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1052 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1053 1054 #define S_TXPKT_OPCODE 24 1055 #define M_TXPKT_OPCODE 0xFF 1056 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1057 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1058 1059 /* cpl_tx_pkt_core.ctrl1 fields */ 1060 #define S_TXPKT_SA_IDX 0 1061 #define M_TXPKT_SA_IDX 0xFFF 1062 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX) 1063 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX) 1064 1065 #define S_TXPKT_CSUM_END 12 1066 #define M_TXPKT_CSUM_END 0xFF 1067 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END) 1068 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END) 1069 1070 #define S_TXPKT_CSUM_START 20 1071 #define M_TXPKT_CSUM_START 0x3FF 1072 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START) 1073 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START) 1074 1075 #define S_TXPKT_IPHDR_LEN 20 1076 #define M_TXPKT_IPHDR_LEN 0x3FFF 1077 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN) 1078 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN) 1079 1080 #define S_TXPKT_CSUM_LOC 30 1081 #define M_TXPKT_CSUM_LOC 0x3FF 1082 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC) 1083 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC) 1084 1085 #define S_TXPKT_ETHHDR_LEN 34 1086 #define M_TXPKT_ETHHDR_LEN 0x3F 1087 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN) 1088 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN) 1089 1090 #define S_TXPKT_CSUM_TYPE 40 1091 #define M_TXPKT_CSUM_TYPE 0xF 1092 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE) 1093 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE) 1094 1095 #define S_TXPKT_VLAN 44 1096 #define M_TXPKT_VLAN 0xFFFF 1097 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN) 1098 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1099 1100 #define S_TXPKT_VLAN_VLD 60 1101 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD) 1102 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL) 1103 1104 #define S_TXPKT_IPSEC 61 1105 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC) 1106 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL) 1107 1108 #define S_TXPKT_IPCSUM_DIS 62 1109 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS) 1110 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL) 1111 1112 #define S_TXPKT_L4CSUM_DIS 63 1113 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS) 1114 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL) 1115 1116 struct cpl_tx_pkt_lso { 1117 __be32 lso_ctrl; 1118 __be16 ipid_ofst; 1119 __be16 mss; 1120 __be32 seqno_offset; 1121 __be32 len; 1122 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 1123 }; 1124 1125 /* cpl_tx_pkt_lso.lso_ctrl fields */ 1126 #define S_LSO_TCPHDR_LEN 0 1127 #define M_LSO_TCPHDR_LEN 0xF 1128 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN) 1129 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN) 1130 1131 #define S_LSO_IPHDR_LEN 4 1132 #define M_LSO_IPHDR_LEN 0xFFF 1133 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN) 1134 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN) 1135 1136 #define S_LSO_ETHHDR_LEN 16 1137 #define M_LSO_ETHHDR_LEN 0xF 1138 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN) 1139 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN) 1140 1141 #define S_LSO_IPV6 20 1142 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1143 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1144 1145 #define S_LSO_OFLD_ENCAP 21 1146 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP) 1147 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U) 1148 1149 #define S_LSO_LAST_SLICE 22 1150 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE) 1151 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U) 1152 1153 #define S_LSO_FIRST_SLICE 23 1154 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE) 1155 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U) 1156 1157 #define S_LSO_OPCODE 24 1158 #define M_LSO_OPCODE 0xFF 1159 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE) 1160 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE) 1161 1162 /* cpl_tx_pkt_lso.mss fields */ 1163 #define S_LSO_MSS 0 1164 #define M_LSO_MSS 0x3FFF 1165 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1166 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1167 1168 #define S_LSO_IPID_SPLIT 15 1169 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT) 1170 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U) 1171 1172 struct cpl_tx_pkt_coalesce { 1173 __be32 cntrl; 1174 __be32 len; 1175 __be64 addr; 1176 }; 1177 1178 struct tx_pkt_coalesce_wr { 1179 WR_HDR; 1180 #if !(defined C99_NOT_SUPPORTED) 1181 struct cpl_tx_pkt_coalesce cpl[0]; 1182 #endif 1183 }; 1184 1185 struct mngt_pktsched_wr { 1186 __be32 wr_hi; 1187 __be32 wr_lo; 1188 __u8 mngt_opcode; 1189 __u8 rsvd[7]; 1190 __u8 sched; 1191 __u8 idx; 1192 __u8 min; 1193 __u8 max; 1194 __u8 binding; 1195 __u8 rsvd1[3]; 1196 }; 1197 1198 struct cpl_iscsi_hdr_no_rss { 1199 union opcode_tid ot; 1200 __be16 pdu_len_ddp; 1201 __be16 len; 1202 __be32 seq; 1203 __be16 urg; 1204 __u8 rsvd; 1205 __u8 status; 1206 }; 1207 1208 struct cpl_iscsi_hdr { 1209 RSS_HDR 1210 union opcode_tid ot; 1211 __be16 pdu_len_ddp; 1212 __be16 len; 1213 __be32 seq; 1214 __be16 urg; 1215 __u8 rsvd; 1216 __u8 status; 1217 }; 1218 1219 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 1220 #define S_ISCSI_PDU_LEN 0 1221 #define M_ISCSI_PDU_LEN 0x7FFF 1222 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 1223 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 1224 1225 #define S_ISCSI_DDP 15 1226 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 1227 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 1228 1229 struct cpl_rx_data { 1230 RSS_HDR 1231 union opcode_tid ot; 1232 __be16 rsvd; 1233 __be16 len; 1234 __be32 seq; 1235 __be16 urg; 1236 #if defined(__LITTLE_ENDIAN_BITFIELD) 1237 __u8 dack_mode:2; 1238 __u8 psh:1; 1239 __u8 heartbeat:1; 1240 __u8 ddp_off:1; 1241 __u8 :3; 1242 #else 1243 __u8 :3; 1244 __u8 ddp_off:1; 1245 __u8 heartbeat:1; 1246 __u8 psh:1; 1247 __u8 dack_mode:2; 1248 #endif 1249 __u8 status; 1250 }; 1251 1252 struct cpl_fcoe_hdr { 1253 RSS_HDR 1254 union opcode_tid ot; 1255 __be16 oxid; 1256 __be16 len; 1257 __be32 rctl_fctl; 1258 __u8 cs_ctl; 1259 __u8 df_ctl; 1260 __u8 sof; 1261 __u8 eof; 1262 __be16 seq_cnt; 1263 __u8 seq_id; 1264 __u8 type; 1265 __be32 param; 1266 }; 1267 1268 struct cpl_rx_urg_notify { 1269 RSS_HDR 1270 union opcode_tid ot; 1271 __be32 seq; 1272 }; 1273 1274 struct cpl_rx_urg_pkt { 1275 RSS_HDR 1276 union opcode_tid ot; 1277 __be16 rsvd; 1278 __be16 len; 1279 }; 1280 1281 struct cpl_rx_data_ack { 1282 WR_HDR; 1283 union opcode_tid ot; 1284 __be32 credit_dack; 1285 }; 1286 1287 /* cpl_rx_data_ack.ack_seq fields */ 1288 #define S_RX_CREDITS 0 1289 #define M_RX_CREDITS 0x3FFFFFF 1290 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1291 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1292 1293 #define S_RX_MODULATE_TX 26 1294 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX) 1295 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U) 1296 1297 #define S_RX_MODULATE_RX 27 1298 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX) 1299 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U) 1300 1301 #define S_RX_FORCE_ACK 28 1302 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1303 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1304 1305 #define S_RX_DACK_MODE 29 1306 #define M_RX_DACK_MODE 0x3 1307 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1308 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1309 1310 #define S_RX_DACK_CHANGE 31 1311 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1312 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1313 1314 struct cpl_rx_ddp_complete { 1315 RSS_HDR 1316 union opcode_tid ot; 1317 __be32 ddp_report; 1318 __be32 rcv_nxt; 1319 __be32 rsvd; 1320 }; 1321 1322 struct cpl_rx_data_ddp { 1323 RSS_HDR 1324 union opcode_tid ot; 1325 __be16 urg; 1326 __be16 len; 1327 __be32 seq; 1328 union { 1329 __be32 nxt_seq; 1330 __be32 ddp_report; 1331 } u; 1332 __be32 ulp_crc; 1333 __be32 ddpvld; 1334 }; 1335 1336 struct cpl_rx_fcoe_ddp { 1337 RSS_HDR 1338 union opcode_tid ot; 1339 __be16 rsvd; 1340 __be16 len; 1341 __be32 seq; 1342 __be32 ddp_report; 1343 __be32 ulp_crc; 1344 __be32 ddpvld; 1345 }; 1346 1347 /* cpl_rx_{data,fcoe}_ddp.ddpvld fields */ 1348 #define S_DDP_VALID 15 1349 #define M_DDP_VALID 0x1FFFF 1350 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1351 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1352 1353 #define S_DDP_PPOD_MISMATCH 15 1354 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1355 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1356 1357 #define S_DDP_PDU 16 1358 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1359 #define F_DDP_PDU V_DDP_PDU(1U) 1360 1361 #define S_DDP_LLIMIT_ERR 17 1362 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1363 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1364 1365 #define S_DDP_PPOD_PARITY_ERR 18 1366 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1367 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1368 1369 #define S_DDP_PADDING_ERR 19 1370 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1371 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1372 1373 #define S_DDP_HDRCRC_ERR 20 1374 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1375 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1376 1377 #define S_DDP_DATACRC_ERR 21 1378 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1379 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1380 1381 #define S_DDP_INVALID_TAG 22 1382 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1383 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1384 1385 #define S_DDP_ULIMIT_ERR 23 1386 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1387 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1388 1389 #define S_DDP_OFFSET_ERR 24 1390 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1391 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1392 1393 #define S_DDP_COLOR_ERR 25 1394 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1395 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1396 1397 #define S_DDP_TID_MISMATCH 26 1398 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1399 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1400 1401 #define S_DDP_INVALID_PPOD 27 1402 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1403 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1404 1405 #define S_DDP_ULP_MODE 28 1406 #define M_DDP_ULP_MODE 0xF 1407 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1408 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1409 1410 /* cpl_rx_{data,fcoe}_ddp.ddp_report fields */ 1411 #define S_DDP_OFFSET 0 1412 #define M_DDP_OFFSET 0xFFFFFF 1413 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1414 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1415 1416 #define S_DDP_DACK_MODE 24 1417 #define M_DDP_DACK_MODE 0x3 1418 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1419 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1420 1421 #define S_DDP_BUF_IDX 26 1422 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1423 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1424 1425 #define S_DDP_URG 27 1426 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1427 #define F_DDP_URG V_DDP_URG(1U) 1428 1429 #define S_DDP_PSH 28 1430 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1431 #define F_DDP_PSH V_DDP_PSH(1U) 1432 1433 #define S_DDP_BUF_COMPLETE 29 1434 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1435 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1436 1437 #define S_DDP_BUF_TIMED_OUT 30 1438 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1439 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1440 1441 #define S_DDP_INV 31 1442 #define V_DDP_INV(x) ((x) << S_DDP_INV) 1443 #define F_DDP_INV V_DDP_INV(1U) 1444 1445 struct cpl_rx_pkt { 1446 RSS_HDR 1447 __u8 opcode; 1448 #if defined(__LITTLE_ENDIAN_BITFIELD) 1449 __u8 iff:4; 1450 __u8 csum_calc:1; 1451 __u8 ipmi_pkt:1; 1452 __u8 vlan_ex:1; 1453 __u8 ip_frag:1; 1454 #else 1455 __u8 ip_frag:1; 1456 __u8 vlan_ex:1; 1457 __u8 ipmi_pkt:1; 1458 __u8 csum_calc:1; 1459 __u8 iff:4; 1460 #endif 1461 __be16 csum; 1462 __be16 vlan; 1463 __be16 len; 1464 __be32 l2info; 1465 __be16 hdr_len; 1466 __be16 err_vec; 1467 }; 1468 1469 /* rx_pkt.l2info fields */ 1470 #define S_RX_ETHHDR_LEN 0 1471 #define M_RX_ETHHDR_LEN 0x1F 1472 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN) 1473 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN) 1474 1475 #define S_RX_PKTYPE 5 1476 #define M_RX_PKTYPE 0x7 1477 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE) 1478 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE) 1479 1480 #define S_RX_MACIDX 8 1481 #define M_RX_MACIDX 0x1FF 1482 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX) 1483 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX) 1484 1485 #define S_RX_DATYPE 18 1486 #define M_RX_DATYPE 0x3 1487 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE) 1488 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE) 1489 1490 #define S_RXF_PSH 20 1491 #define V_RXF_PSH(x) ((x) << S_RXF_PSH) 1492 #define F_RXF_PSH V_RXF_PSH(1U) 1493 1494 #define S_RXF_SYN 21 1495 #define V_RXF_SYN(x) ((x) << S_RXF_SYN) 1496 #define F_RXF_SYN V_RXF_SYN(1U) 1497 1498 #define S_RXF_UDP 22 1499 #define V_RXF_UDP(x) ((x) << S_RXF_UDP) 1500 #define F_RXF_UDP V_RXF_UDP(1U) 1501 1502 #define S_RXF_TCP 23 1503 #define V_RXF_TCP(x) ((x) << S_RXF_TCP) 1504 #define F_RXF_TCP V_RXF_TCP(1U) 1505 1506 #define S_RXF_IP 24 1507 #define V_RXF_IP(x) ((x) << S_RXF_IP) 1508 #define F_RXF_IP V_RXF_IP(1U) 1509 1510 #define S_RXF_IP6 25 1511 #define V_RXF_IP6(x) ((x) << S_RXF_IP6) 1512 #define F_RXF_IP6 V_RXF_IP6(1U) 1513 1514 #define S_RXF_SYN_COOKIE 26 1515 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE) 1516 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U) 1517 1518 #define S_RXF_FCOE 26 1519 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE) 1520 #define F_RXF_FCOE V_RXF_FCOE(1U) 1521 1522 #define S_RXF_LRO 27 1523 #define V_RXF_LRO(x) ((x) << S_RXF_LRO) 1524 #define F_RXF_LRO V_RXF_LRO(1U) 1525 1526 #define S_RX_CHAN 28 1527 #define M_RX_CHAN 0xF 1528 #define V_RX_CHAN(x) ((x) << S_RX_CHAN) 1529 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN) 1530 1531 /* rx_pkt.hdr_len fields */ 1532 #define S_RX_TCPHDR_LEN 0 1533 #define M_RX_TCPHDR_LEN 0x3F 1534 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN) 1535 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN) 1536 1537 #define S_RX_IPHDR_LEN 6 1538 #define M_RX_IPHDR_LEN 0x3FF 1539 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN) 1540 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN) 1541 1542 /* rx_pkt.err_vec fields */ 1543 #define S_RXERR_OR 0 1544 #define V_RXERR_OR(x) ((x) << S_RXERR_OR) 1545 #define F_RXERR_OR V_RXERR_OR(1U) 1546 1547 #define S_RXERR_MAC 1 1548 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC) 1549 #define F_RXERR_MAC V_RXERR_MAC(1U) 1550 1551 #define S_RXERR_IPVERS 2 1552 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS) 1553 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U) 1554 1555 #define S_RXERR_FRAG 3 1556 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG) 1557 #define F_RXERR_FRAG V_RXERR_FRAG(1U) 1558 1559 #define S_RXERR_ATTACK 4 1560 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK) 1561 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U) 1562 1563 #define S_RXERR_ETHHDR_LEN 5 1564 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN) 1565 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U) 1566 1567 #define S_RXERR_IPHDR_LEN 6 1568 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN) 1569 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U) 1570 1571 #define S_RXERR_TCPHDR_LEN 7 1572 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN) 1573 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U) 1574 1575 #define S_RXERR_PKT_LEN 8 1576 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN) 1577 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U) 1578 1579 #define S_RXERR_TCP_OPT 9 1580 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT) 1581 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U) 1582 1583 #define S_RXERR_IPCSUM 12 1584 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM) 1585 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U) 1586 1587 #define S_RXERR_CSUM 13 1588 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM) 1589 #define F_RXERR_CSUM V_RXERR_CSUM(1U) 1590 1591 #define S_RXERR_PING 14 1592 #define V_RXERR_PING(x) ((x) << S_RXERR_PING) 1593 #define F_RXERR_PING V_RXERR_PING(1U) 1594 1595 struct cpl_trace_pkt { 1596 RSS_HDR 1597 __u8 opcode; 1598 __u8 intf; 1599 #if defined(__LITTLE_ENDIAN_BITFIELD) 1600 __u8 runt:4; 1601 __u8 filter_hit:4; 1602 __u8 :6; 1603 __u8 err:1; 1604 __u8 trunc:1; 1605 #else 1606 __u8 filter_hit:4; 1607 __u8 runt:4; 1608 __u8 trunc:1; 1609 __u8 err:1; 1610 __u8 :6; 1611 #endif 1612 __be16 rsvd; 1613 __be16 len; 1614 __be64 tstamp; 1615 }; 1616 1617 struct cpl_rte_delete_req { 1618 WR_HDR; 1619 union opcode_tid ot; 1620 __be32 params; 1621 }; 1622 1623 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */ 1624 #define S_RTE_REQ_LUT_IX 8 1625 #define M_RTE_REQ_LUT_IX 0x7FF 1626 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1627 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1628 1629 #define S_RTE_REQ_LUT_BASE 19 1630 #define M_RTE_REQ_LUT_BASE 0x7FF 1631 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1632 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1633 1634 #define S_RTE_READ_REQ_SELECT 31 1635 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1636 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1637 1638 struct cpl_rte_delete_rpl { 1639 RSS_HDR 1640 union opcode_tid ot; 1641 __u8 status; 1642 __u8 rsvd[3]; 1643 }; 1644 1645 struct cpl_rte_write_req { 1646 WR_HDR; 1647 union opcode_tid ot; 1648 __u32 write_sel; 1649 __be32 lut_params; 1650 __be32 l2t_idx; 1651 __be32 netmask; 1652 __be32 faddr; 1653 }; 1654 1655 /* cpl_rte_write_req.write_sel fields */ 1656 #define S_RTE_WR_L2TIDX 31 1657 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX) 1658 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U) 1659 1660 #define S_RTE_WR_FADDR 30 1661 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR) 1662 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U) 1663 1664 /* cpl_rte_write_req.lut_params fields */ 1665 #define S_RTE_WR_LUT_IX 10 1666 #define M_RTE_WR_LUT_IX 0x7FF 1667 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX) 1668 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX) 1669 1670 #define S_RTE_WR_LUT_BASE 21 1671 #define M_RTE_WR_LUT_BASE 0x7FF 1672 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE) 1673 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE) 1674 1675 struct cpl_rte_write_rpl { 1676 RSS_HDR 1677 union opcode_tid ot; 1678 __u8 status; 1679 __u8 rsvd[3]; 1680 }; 1681 1682 struct cpl_rte_read_req { 1683 WR_HDR; 1684 union opcode_tid ot; 1685 __be32 params; 1686 }; 1687 1688 struct cpl_rte_read_rpl { 1689 RSS_HDR 1690 union opcode_tid ot; 1691 __u8 status; 1692 __u8 rsvd; 1693 __be16 l2t_idx; 1694 #if defined(__LITTLE_ENDIAN_BITFIELD) 1695 __u32 :30; 1696 __u32 select:1; 1697 #else 1698 __u32 select:1; 1699 __u32 :30; 1700 #endif 1701 __be32 addr; 1702 }; 1703 1704 struct cpl_l2t_write_req { 1705 WR_HDR; 1706 union opcode_tid ot; 1707 __be16 params; 1708 __be16 l2t_idx; 1709 __be16 vlan; 1710 __u8 dst_mac[6]; 1711 }; 1712 1713 /* cpl_l2t_write_req.params fields */ 1714 #define S_L2T_W_INFO 2 1715 #define M_L2T_W_INFO 0x3F 1716 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO) 1717 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO) 1718 1719 #define S_L2T_W_PORT 8 1720 #define M_L2T_W_PORT 0xF 1721 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT) 1722 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT) 1723 1724 #define S_L2T_W_NOREPLY 15 1725 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY) 1726 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U) 1727 1728 struct cpl_l2t_write_rpl { 1729 RSS_HDR 1730 union opcode_tid ot; 1731 __u8 status; 1732 __u8 rsvd[3]; 1733 }; 1734 1735 struct cpl_l2t_read_req { 1736 WR_HDR; 1737 union opcode_tid ot; 1738 __be32 l2t_idx; 1739 }; 1740 1741 struct cpl_l2t_read_rpl { 1742 RSS_HDR 1743 union opcode_tid ot; 1744 __u8 status; 1745 #if defined(__LITTLE_ENDIAN_BITFIELD) 1746 __u8 :4; 1747 __u8 iff:4; 1748 #else 1749 __u8 iff:4; 1750 __u8 :4; 1751 #endif 1752 __be16 vlan; 1753 __be16 info; 1754 __u8 dst_mac[6]; 1755 }; 1756 1757 struct cpl_smt_write_req { 1758 WR_HDR; 1759 union opcode_tid ot; 1760 __be32 params; 1761 __be16 pfvf1; 1762 __u8 src_mac1[6]; 1763 __be16 pfvf0; 1764 __u8 src_mac0[6]; 1765 }; 1766 1767 /* cpl_smt_{read,write}_req.params fields */ 1768 #define S_SMTW_OVLAN_IDX 16 1769 #define M_SMTW_OVLAN_IDX 0xF 1770 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX) 1771 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX) 1772 1773 #define S_SMTW_IDX 20 1774 #define M_SMTW_IDX 0x7F 1775 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX) 1776 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX) 1777 1778 #define S_SMTW_NORPL 31 1779 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL) 1780 #define F_SMTW_NORPL V_SMTW_NORPL(1U) 1781 1782 /* cpl_smt_{read,write}_req.pfvf? fields */ 1783 #define S_SMTW_VF 0 1784 #define M_SMTW_VF 0xFF 1785 #define V_SMTW_VF(x) ((x) << S_SMTW_VF) 1786 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF) 1787 1788 #define S_SMTW_PF 8 1789 #define M_SMTW_PF 0x7 1790 #define V_SMTW_PF(x) ((x) << S_SMTW_PF) 1791 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF) 1792 1793 #define S_SMTW_VF_VLD 11 1794 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD) 1795 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U) 1796 1797 struct cpl_smt_write_rpl { 1798 RSS_HDR 1799 union opcode_tid ot; 1800 __u8 status; 1801 __u8 rsvd[3]; 1802 }; 1803 1804 struct cpl_smt_read_req { 1805 WR_HDR; 1806 union opcode_tid ot; 1807 __be32 params; 1808 }; 1809 1810 struct cpl_smt_read_rpl { 1811 RSS_HDR 1812 union opcode_tid ot; 1813 __u8 status; 1814 __u8 ovlan_idx; 1815 __be16 rsvd; 1816 __be16 pfvf1; 1817 __u8 src_mac1[6]; 1818 __be16 pfvf0; 1819 __u8 src_mac0[6]; 1820 }; 1821 1822 struct cpl_barrier { 1823 WR_HDR; 1824 __u8 opcode; 1825 __u8 chan_map; 1826 __be16 rsvd0; 1827 __be32 rsvd1; 1828 }; 1829 1830 /* cpl_barrier.chan_map fields */ 1831 #define S_CHAN_MAP 4 1832 #define M_CHAN_MAP 0xF 1833 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP) 1834 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP) 1835 1836 struct cpl_error { 1837 RSS_HDR 1838 union opcode_tid ot; 1839 __be32 error; 1840 }; 1841 1842 struct cpl_hit_notify { 1843 RSS_HDR 1844 union opcode_tid ot; 1845 __be32 rsvd; 1846 __be32 info; 1847 __be32 reason; 1848 }; 1849 1850 struct cpl_pkt_notify { 1851 RSS_HDR 1852 union opcode_tid ot; 1853 __be16 rsvd; 1854 __be16 len; 1855 __be32 info; 1856 __be32 reason; 1857 }; 1858 1859 /* cpl_{hit,pkt}_notify.info fields */ 1860 #define S_NTFY_MAC_IDX 0 1861 #define M_NTFY_MAC_IDX 0x1FF 1862 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX) 1863 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX) 1864 1865 #define S_NTFY_INTF 10 1866 #define M_NTFY_INTF 0xF 1867 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF) 1868 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF) 1869 1870 #define S_NTFY_TCPHDR_LEN 14 1871 #define M_NTFY_TCPHDR_LEN 0xF 1872 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN) 1873 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN) 1874 1875 #define S_NTFY_IPHDR_LEN 18 1876 #define M_NTFY_IPHDR_LEN 0x1FF 1877 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN) 1878 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN) 1879 1880 #define S_NTFY_ETHHDR_LEN 27 1881 #define M_NTFY_ETHHDR_LEN 0x1F 1882 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN) 1883 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN) 1884 1885 struct cpl_rdma_terminate { 1886 RSS_HDR 1887 union opcode_tid ot; 1888 __be16 rsvd; 1889 __be16 len; 1890 }; 1891 1892 struct cpl_set_le_req { 1893 WR_HDR; 1894 union opcode_tid ot; 1895 __be16 reply_ctrl; 1896 __be16 params; 1897 __be64 mask_hi; 1898 __be64 mask_lo; 1899 __be64 val_hi; 1900 __be64 val_lo; 1901 }; 1902 1903 /* cpl_set_le_req.reply_ctrl additional fields */ 1904 #define S_LE_REQ_IP6 13 1905 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6) 1906 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U) 1907 1908 /* cpl_set_le_req.params fields */ 1909 #define S_LE_CHAN 0 1910 #define M_LE_CHAN 0x3 1911 #define V_LE_CHAN(x) ((x) << S_LE_CHAN) 1912 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN) 1913 1914 #define S_LE_OFFSET 5 1915 #define M_LE_OFFSET 0x7 1916 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET) 1917 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET) 1918 1919 #define S_LE_MORE 8 1920 #define V_LE_MORE(x) ((x) << S_LE_MORE) 1921 #define F_LE_MORE V_LE_MORE(1U) 1922 1923 #define S_LE_REQSIZE 9 1924 #define M_LE_REQSIZE 0x7 1925 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE) 1926 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE) 1927 1928 #define S_LE_REQCMD 12 1929 #define M_LE_REQCMD 0xF 1930 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD) 1931 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD) 1932 1933 struct cpl_set_le_rpl { 1934 RSS_HDR 1935 union opcode_tid ot; 1936 __u8 chan; 1937 __u8 info; 1938 __be16 len; 1939 }; 1940 1941 /* cpl_set_le_rpl.info fields */ 1942 #define S_LE_RSPCMD 0 1943 #define M_LE_RSPCMD 0xF 1944 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD) 1945 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD) 1946 1947 #define S_LE_RSPSIZE 4 1948 #define M_LE_RSPSIZE 0x7 1949 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE) 1950 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE) 1951 1952 #define S_LE_RSPTYPE 7 1953 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE) 1954 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U) 1955 1956 struct cpl_sge_egr_update { 1957 RSS_HDR 1958 __be32 opcode_qid; 1959 __be16 cidx; 1960 __be16 pidx; 1961 }; 1962 1963 /* cpl_sge_egr_update.ot fields */ 1964 #define S_EGR_QID 0 1965 #define M_EGR_QID 0x1FFFF 1966 #define V_EGR_QID(x) ((x) << S_EGR_QID) 1967 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID) 1968 1969 struct cpl_fw2_pld { 1970 RSS_HDR 1971 u8 opcode; 1972 u8 rsvd[5]; 1973 __be16 len; 1974 }; 1975 1976 struct cpl_fw4_pld { 1977 RSS_HDR 1978 u8 opcode; 1979 u8 rsvd0[3]; 1980 u8 type; 1981 u8 rsvd1; 1982 __be16 len; 1983 __be64 data; 1984 __be64 rsvd2; 1985 }; 1986 1987 struct cpl_fw6_pld { 1988 RSS_HDR 1989 u8 opcode; 1990 u8 rsvd[5]; 1991 __be16 len; 1992 __be64 data[4]; 1993 }; 1994 1995 struct cpl_fw2_msg { 1996 RSS_HDR 1997 union opcode_info oi; 1998 }; 1999 2000 struct cpl_fw4_msg { 2001 RSS_HDR 2002 u8 opcode; 2003 u8 type; 2004 __be16 rsvd0; 2005 __be32 rsvd1; 2006 __be64 data[2]; 2007 }; 2008 2009 struct cpl_fw4_ack { 2010 RSS_HDR 2011 union opcode_tid ot; 2012 u8 credits; 2013 u8 rsvd0[2]; 2014 u8 seq_vld; 2015 __be32 snd_nxt; 2016 __be32 snd_una; 2017 __be64 rsvd1; 2018 }; 2019 2020 struct cpl_fw6_msg { 2021 RSS_HDR 2022 u8 opcode; 2023 u8 type; 2024 __be16 rsvd0; 2025 __be32 rsvd1; 2026 __be64 data[4]; 2027 }; 2028 2029 /* cpl_fw6_msg.type values */ 2030 enum { 2031 FW6_TYPE_CMD_RPL = 0, 2032 }; 2033 2034 /* ULP_TX opcodes */ 2035 enum { 2036 ULP_TX_MEM_READ = 2, 2037 ULP_TX_MEM_WRITE = 3, 2038 ULP_TX_PKT = 4 2039 }; 2040 2041 enum { 2042 ULP_TX_SC_NOOP = 0x80, 2043 ULP_TX_SC_IMM = 0x81, 2044 ULP_TX_SC_DSGL = 0x82, 2045 ULP_TX_SC_ISGL = 0x83 2046 }; 2047 2048 #define S_ULPTX_CMD 24 2049 #define M_ULPTX_CMD 0xFF 2050 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 2051 2052 #define S_ULPTX_LEN16 0 2053 #define M_ULPTX_LEN16 0xFF 2054 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16) 2055 2056 #define S_ULP_TX_SC_MORE 23 2057 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE) 2058 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U) 2059 2060 struct ulptx_sge_pair { 2061 __be32 len[2]; 2062 __be64 addr[2]; 2063 }; 2064 2065 struct ulptx_sgl { 2066 __be32 cmd_nsge; 2067 __be32 len0; 2068 __be64 addr0; 2069 #if !(defined C99_NOT_SUPPORTED) 2070 struct ulptx_sge_pair sge[0]; 2071 #endif 2072 }; 2073 2074 struct ulptx_isge { 2075 __be32 stag; 2076 __be32 len; 2077 __be64 target_ofst; 2078 }; 2079 2080 struct ulptx_isgl { 2081 __be32 cmd_nisge; 2082 __be32 rsvd; 2083 #if !(defined C99_NOT_SUPPORTED) 2084 struct ulptx_isge sge[0]; 2085 #endif 2086 }; 2087 2088 struct ulptx_idata { 2089 __be32 cmd_more; 2090 __be32 len; 2091 }; 2092 2093 #define S_ULPTX_NSGE 0 2094 #define M_ULPTX_NSGE 0xFFFF 2095 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE) 2096 2097 struct ulp_mem_io { 2098 WR_HDR; 2099 __be32 cmd; 2100 __be32 len16; /* command length */ 2101 __be32 dlen; /* data length in 32-byte units */ 2102 __be32 lock_addr; 2103 }; 2104 2105 /* additional ulp_mem_io.cmd fields */ 2106 #define S_ULP_MEMIO_ORDER 23 2107 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER) 2108 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U) 2109 2110 /* ulp_mem_io.lock_addr fields */ 2111 #define S_ULP_MEMIO_ADDR 0 2112 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 2113 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 2114 2115 #define S_ULP_MEMIO_LOCK 31 2116 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 2117 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 2118 2119 /* ulp_mem_io.dlen fields */ 2120 #define S_ULP_MEMIO_DATA_LEN 0 2121 #define M_ULP_MEMIO_DATA_LEN 0x1F 2122 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 2123 2124 struct ulp_txpkt { 2125 __be32 cmd_dest; 2126 __be32 len; 2127 }; 2128 2129 /* ulp_txpkt.cmd_dest fields */ 2130 #define S_ULP_TXPKT_DEST 16 2131 #define M_ULP_TXPKT_DEST 0x3 2132 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 2133 2134 #define S_ULP_TXPKT_FID 4 2135 #define M_ULP_TXPKT_FID 0x7ff 2136 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID) 2137 2138 #endif /* T4_MSG_H */ 2139