1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef __T4_HW_H 33 #define __T4_HW_H 34 35 #include "osdep.h" 36 37 enum { 38 NCHAN = 4, /* # of HW channels */ 39 T6_NCHAN = 2, 40 MAX_NCHAN = 4, 41 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 42 EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 43 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 44 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 45 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 46 TCB_SIZE = 128, /* TCB size */ 47 NMTUS = 16, /* size of MTU table */ 48 NCCTRL_WIN = 32, /* # of congestion control windows */ 49 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 50 PM_NSTATS = 5, /* # of PM stats */ 51 T6_PM_NSTATS = 7, 52 MAX_PM_NSTATS = 7, 53 MBOX_LEN = 64, /* mailbox size in bytes */ 54 NTRACE = 4, /* # of tracing filters */ 55 TRACE_LEN = 112, /* length of trace data and mask */ 56 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ 57 NWOL_PAT = 8, /* # of WoL patterns */ 58 WOL_PAT_LEN = 128, /* length of WoL patterns */ 59 UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ 60 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 61 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 62 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 63 }; 64 65 enum { 66 CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 67 CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 68 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 69 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 70 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 71 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 72 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 73 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 74 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 75 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 76 }; 77 78 enum { 79 SF_PAGE_SIZE = 256, /* serial flash page size */ 80 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 81 }; 82 83 /* SGE context types */ 84 enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM }; 85 86 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 87 88 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 89 90 enum { 91 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 92 SGE_CTXT_SIZE = 24, /* size of SGE context */ 93 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 94 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 95 SGE_MAX_IQ_SIZE = 65520, 96 SGE_FLBUF_SIZES = 16, 97 }; 98 99 struct sge_qstat { /* data written to SGE queue status entries */ 100 volatile __be32 qid; 101 volatile __be16 cidx; 102 volatile __be16 pidx; 103 }; 104 105 #define S_QSTAT_PIDX 0 106 #define M_QSTAT_PIDX 0xffff 107 #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX) 108 109 #define S_QSTAT_CIDX 16 110 #define M_QSTAT_CIDX 0xffff 111 #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX) 112 113 /* 114 * Structure for last 128 bits of response descriptors 115 */ 116 struct rsp_ctrl { 117 __be32 hdrbuflen_pidx; 118 __be32 pldbuflen_qid; 119 union { 120 u8 type_gen; 121 __be64 last_flit; 122 } u; 123 }; 124 125 #define S_RSPD_NEWBUF 31 126 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) 127 #define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U) 128 129 #define S_RSPD_LEN 0 130 #define M_RSPD_LEN 0x7fffffff 131 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) 132 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) 133 134 #define S_RSPD_QID S_RSPD_LEN 135 #define M_RSPD_QID M_RSPD_LEN 136 #define V_RSPD_QID(x) V_RSPD_LEN(x) 137 #define G_RSPD_QID(x) G_RSPD_LEN(x) 138 139 #define S_RSPD_GEN 7 140 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) 141 #define F_RSPD_GEN V_RSPD_GEN(1U) 142 143 #define S_RSPD_QOVFL 6 144 #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL) 145 #define F_RSPD_QOVFL V_RSPD_QOVFL(1U) 146 147 #define S_RSPD_TYPE 4 148 #define M_RSPD_TYPE 0x3 149 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) 150 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) 151 152 /* Rx queue interrupt deferral fields: counter enable and timer index */ 153 #define S_QINTR_CNT_EN 0 154 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) 155 #define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U) 156 157 #define S_QINTR_TIMER_IDX 1 158 #define M_QINTR_TIMER_IDX 0x7 159 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) 160 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) 161 162 /* # of pages a pagepod can hold without needing another pagepod */ 163 #define PPOD_PAGES 4U 164 165 struct pagepod { 166 __be64 vld_tid_pgsz_tag_color; 167 __be64 len_offset; 168 __be64 rsvd; 169 __be64 addr[PPOD_PAGES + 1]; 170 }; 171 172 #define S_PPOD_COLOR 0 173 #define M_PPOD_COLOR 0x3F 174 #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR) 175 176 #define S_PPOD_TAG 6 177 #define M_PPOD_TAG 0xFFFFFF 178 #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG) 179 #define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) 180 181 #define S_PPOD_PGSZ 30 182 #define M_PPOD_PGSZ 0x3 183 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ) 184 #define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ) 185 186 #define S_PPOD_TID 32 187 #define M_PPOD_TID 0xFFFFFF 188 #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID) 189 190 #define S_PPOD_VALID 56 191 #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID) 192 #define F_PPOD_VALID V_PPOD_VALID(1ULL) 193 194 #define S_PPOD_LEN 32 195 #define M_PPOD_LEN 0xFFFFFFFF 196 #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN) 197 198 #define S_PPOD_OFST 0 199 #define M_PPOD_OFST 0xFFFFFFFF 200 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST) 201 202 /* 203 * Flash layout. 204 */ 205 #define FLASH_START(start) ((start) * SF_SEC_SIZE) 206 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 207 208 enum { 209 /* 210 * Various Expansion-ROM boot images, etc. 211 */ 212 FLASH_EXP_ROM_START_SEC = 0, 213 FLASH_EXP_ROM_NSECS = 6, 214 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 215 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 216 217 /* 218 * iSCSI Boot Firmware Table (iBFT) and other driver-related 219 * parameters ... 220 */ 221 FLASH_IBFT_START_SEC = 6, 222 FLASH_IBFT_NSECS = 1, 223 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 224 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 225 226 /* 227 * Boot configuration data. 228 */ 229 FLASH_BOOTCFG_START_SEC = 7, 230 FLASH_BOOTCFG_NSECS = 1, 231 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 232 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 233 234 /* 235 * Location of firmware image in FLASH. 236 */ 237 FLASH_FW_START_SEC = 8, 238 FLASH_FW_NSECS = 16, 239 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 240 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 241 242 /* 243 * Location of bootstrap firmware image in FLASH. 244 */ 245 FLASH_FWBOOTSTRAP_START_SEC = 27, 246 FLASH_FWBOOTSTRAP_NSECS = 1, 247 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 248 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 249 250 /* 251 * iSCSI persistent/crash information. 252 */ 253 FLASH_ISCSI_CRASH_START_SEC = 29, 254 FLASH_ISCSI_CRASH_NSECS = 1, 255 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 256 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 257 258 /* 259 * FCoE persistent/crash information. 260 */ 261 FLASH_FCOE_CRASH_START_SEC = 30, 262 FLASH_FCOE_CRASH_NSECS = 1, 263 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 264 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 265 266 /* 267 * Location of Firmware Configuration File in FLASH. 268 */ 269 FLASH_CFG_START_SEC = 31, 270 FLASH_CFG_NSECS = 1, 271 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 272 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 273 274 /* 275 * We don't support FLASH devices which can't support the full 276 * standard set of sections which we need for normal operations. 277 */ 278 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE, 279 280 /* 281 * Sectors 32-63 for CUDBG. 282 */ 283 FLASH_CUDBG_START_SEC = 32, 284 FLASH_CUDBG_NSECS = 32, 285 FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC), 286 FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS), 287 288 /* 289 * Size of defined FLASH regions. 290 */ 291 FLASH_END_SEC = 64, 292 }; 293 294 #undef FLASH_START 295 #undef FLASH_MAX_SIZE 296 297 #define S_SGE_TIMESTAMP 0 298 #define M_SGE_TIMESTAMP 0xfffffffffffffffULL 299 #define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP) 300 #define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP) 301 302 #endif /* __T4_HW_H */ 303