1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #ifndef __T4_HW_H 31 #define __T4_HW_H 32 33 #include "osdep.h" 34 35 enum { 36 NCHAN = 4, /* # of HW channels */ 37 T6_NCHAN = 2, 38 MAX_NCHAN = 4, 39 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */ 40 EEPROMSIZE = 17408, /* Serial EEPROM physical size */ 41 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */ 42 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */ 43 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */ 44 T6_RSS_NENTRIES = 4096, 45 TCB_SIZE = 128, /* TCB size */ 46 NMTUS = 16, /* size of MTU table */ 47 NCCTRL_WIN = 32, /* # of congestion control windows */ 48 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 49 PM_NSTATS = 5, /* # of PM stats */ 50 T6_PM_NSTATS = 7, 51 MAX_PM_NSTATS = 7, 52 MBOX_LEN = 64, /* mailbox size in bytes */ 53 NTRACE = 4, /* # of tracing filters */ 54 TRACE_LEN = 112, /* length of trace data and mask */ 55 FILTER_OPT_LEN = 36, /* filter tuple width of optional components */ 56 T5_FILTER_OPT_LEN = 40, 57 NWOL_PAT = 8, /* # of WoL patterns */ 58 WOL_PAT_LEN = 128, /* length of WoL patterns */ 59 UDBS_SEG_SIZE = 128, /* Segment size of BAR2 doorbells */ 60 UDBS_SEG_SHIFT = 7, /* log2(UDBS_SEG_SIZE) */ 61 UDBS_DB_OFFSET = 8, /* offset of the 4B doorbell in a segment */ 62 UDBS_WR_OFFSET = 64, /* offset of the work request in a segment */ 63 }; 64 65 enum { 66 CIM_NUM_IBQ = 6, /* # of CIM IBQs */ 67 CIM_NUM_OBQ = 6, /* # of CIM OBQs */ 68 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */ 69 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */ 70 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */ 71 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */ 72 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */ 73 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */ 74 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */ 75 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */ 76 }; 77 78 enum { 79 SF_PAGE_SIZE = 256, /* serial flash page size */ 80 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 81 }; 82 83 /* SGE context types */ 84 enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM }; 85 86 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */ 87 88 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */ 89 90 enum { 91 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */ 92 SGE_CTXT_SIZE = 24, /* size of SGE context */ 93 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */ 94 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */ 95 SGE_NDBQTIMERS = 8, /* # of Doorbell Queue Timer values */ 96 SGE_MAX_IQ_SIZE = 65520, 97 SGE_FLBUF_SIZES = 16, 98 }; 99 100 struct sge_qstat { /* data written to SGE queue status entries */ 101 volatile __be32 qid; 102 volatile __be16 cidx; 103 volatile __be16 pidx; 104 }; 105 106 #define S_QSTAT_PIDX 0 107 #define M_QSTAT_PIDX 0xffff 108 #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX) 109 110 #define S_QSTAT_CIDX 16 111 #define M_QSTAT_CIDX 0xffff 112 #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX) 113 114 /* 115 * Structure for last 128 bits of response descriptors 116 */ 117 struct rsp_ctrl { 118 __be32 hdrbuflen_pidx; 119 __be32 pldbuflen_qid; 120 union { 121 u8 type_gen; 122 __be64 last_flit; 123 } u; 124 }; 125 126 #define S_RSPD_NEWBUF 31 127 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF) 128 #define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U) 129 130 #define S_RSPD_LEN 0 131 #define M_RSPD_LEN 0x7fffffff 132 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN) 133 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN) 134 135 #define S_RSPD_QID S_RSPD_LEN 136 #define M_RSPD_QID M_RSPD_LEN 137 #define V_RSPD_QID(x) V_RSPD_LEN(x) 138 #define G_RSPD_QID(x) G_RSPD_LEN(x) 139 140 #define S_RSPD_GEN 7 141 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN) 142 #define F_RSPD_GEN V_RSPD_GEN(1U) 143 144 #define S_RSPD_QOVFL 6 145 #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL) 146 #define F_RSPD_QOVFL V_RSPD_QOVFL(1U) 147 148 #define S_RSPD_TYPE 4 149 #define M_RSPD_TYPE 0x3 150 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE) 151 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE) 152 153 /* Rx queue interrupt deferral fields: counter enable and timer index */ 154 #define S_QINTR_CNT_EN 0 155 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN) 156 #define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U) 157 158 #define S_QINTR_TIMER_IDX 1 159 #define M_QINTR_TIMER_IDX 0x7 160 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX) 161 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX) 162 163 /* # of pages a pagepod can hold without needing another pagepod */ 164 #define PPOD_PAGES 4U 165 166 struct pagepod { 167 __be64 vld_tid_pgsz_tag_color; 168 __be64 len_offset; 169 __be64 rsvd; 170 __be64 addr[PPOD_PAGES + 1]; 171 }; 172 173 #define S_PPOD_COLOR 0 174 #define M_PPOD_COLOR 0x3F 175 #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR) 176 177 #define S_PPOD_TAG 6 178 #define M_PPOD_TAG 0xFFFFFF 179 #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG) 180 #define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG) 181 182 #define S_PPOD_PGSZ 30 183 #define M_PPOD_PGSZ 0x3 184 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ) 185 #define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ) 186 187 #define S_PPOD_TID 32 188 #define M_PPOD_TID 0xFFFFFF 189 #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID) 190 191 #define S_PPOD_VALID 56 192 #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID) 193 #define F_PPOD_VALID V_PPOD_VALID(1ULL) 194 195 #define S_PPOD_LEN 32 196 #define M_PPOD_LEN 0xFFFFFFFF 197 #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN) 198 199 #define S_PPOD_OFST 0 200 #define M_PPOD_OFST 0xFFFFFFFF 201 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST) 202 203 /* 204 * Flash layout. 205 */ 206 #define FLASH_START(start) ((start) * SF_SEC_SIZE) 207 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE) 208 209 enum { 210 /* 211 * Various Expansion-ROM boot images, etc. 212 */ 213 FLASH_EXP_ROM_START_SEC = 0, 214 FLASH_EXP_ROM_NSECS = 6, 215 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC), 216 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS), 217 218 /* 219 * iSCSI Boot Firmware Table (iBFT) and other driver-related 220 * parameters ... 221 */ 222 FLASH_IBFT_START_SEC = 6, 223 FLASH_IBFT_NSECS = 1, 224 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC), 225 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS), 226 227 /* 228 * Boot configuration data. 229 */ 230 FLASH_BOOTCFG_START_SEC = 7, 231 FLASH_BOOTCFG_NSECS = 1, 232 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC), 233 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS), 234 235 /* 236 * Location of firmware image in FLASH. 237 */ 238 FLASH_FW_START_SEC = 8, 239 FLASH_FW_NSECS = 16, 240 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), 241 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), 242 243 /* 244 * Location of bootstrap firmware image in FLASH. 245 */ 246 FLASH_FWBOOTSTRAP_START_SEC = 27, 247 FLASH_FWBOOTSTRAP_NSECS = 1, 248 FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC), 249 FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS), 250 251 /* 252 * iSCSI persistent/crash information. 253 */ 254 FLASH_ISCSI_CRASH_START_SEC = 29, 255 FLASH_ISCSI_CRASH_NSECS = 1, 256 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC), 257 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS), 258 259 /* 260 * FCoE persistent/crash information. 261 */ 262 FLASH_FCOE_CRASH_START_SEC = 30, 263 FLASH_FCOE_CRASH_NSECS = 1, 264 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC), 265 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS), 266 267 /* 268 * Location of Firmware Configuration File in FLASH. 269 */ 270 FLASH_CFG_START_SEC = 31, 271 FLASH_CFG_NSECS = 1, 272 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC), 273 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS), 274 275 /* 276 * We don't support FLASH devices which can't support the full 277 * standard set of sections which we need for normal operations. 278 */ 279 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE, 280 281 /* 282 * Sectors 32-63 for CUDBG. 283 */ 284 FLASH_CUDBG_START_SEC = 32, 285 FLASH_CUDBG_NSECS = 32, 286 FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC), 287 FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS), 288 289 /* 290 * Size of defined FLASH regions. 291 */ 292 FLASH_END_SEC = 64, 293 }; 294 295 #undef FLASH_START 296 #undef FLASH_MAX_SIZE 297 298 #define S_SGE_TIMESTAMP 0 299 #define M_SGE_TIMESTAMP 0xfffffffffffffffULL 300 #define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP) 301 #define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP) 302 303 #define I2C_DEV_ADDR_A0 0xa0 304 #define I2C_DEV_ADDR_A2 0xa2 305 #define I2C_PAGE_SIZE 0x100 306 #define SFP_DIAG_TYPE_ADDR 0x5c 307 #define SFP_DIAG_TYPE_LEN 0x1 308 #define SFF_8472_COMP_ADDR 0x5e 309 #define SFF_8472_COMP_LEN 0x1 310 #define SFF_REV_ADDR 0x1 311 #define SFF_REV_LEN 0x1 312 313 #endif /* __T4_HW_H */ 314