1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include "opt_inet.h" 31 32 #include <sys/param.h> 33 #include <sys/eventhandler.h> 34 35 #include "common.h" 36 #include "t4_regs.h" 37 #include "t4_regs_values.h" 38 #include "firmware/t4fw_interface.h" 39 40 #undef msleep 41 #define msleep(x) do { \ 42 if (cold) \ 43 DELAY((x) * 1000); \ 44 else \ 45 pause("t4hw", (x) * hz / 1000); \ 46 } while (0) 47 48 /** 49 * t4_wait_op_done_val - wait until an operation is completed 50 * @adapter: the adapter performing the operation 51 * @reg: the register to check for completion 52 * @mask: a single-bit field within @reg that indicates completion 53 * @polarity: the value of the field when the operation is completed 54 * @attempts: number of check iterations 55 * @delay: delay in usecs between iterations 56 * @valp: where to store the value of the register at completion time 57 * 58 * Wait until an operation is completed by checking a bit in a register 59 * up to @attempts times. If @valp is not NULL the value of the register 60 * at the time it indicated completion is stored there. Returns 0 if the 61 * operation completes and -EAGAIN otherwise. 62 */ 63 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 64 int polarity, int attempts, int delay, u32 *valp) 65 { 66 while (1) { 67 u32 val = t4_read_reg(adapter, reg); 68 69 if (!!(val & mask) == polarity) { 70 if (valp) 71 *valp = val; 72 return 0; 73 } 74 if (--attempts == 0) 75 return -EAGAIN; 76 if (delay) 77 udelay(delay); 78 } 79 } 80 81 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 82 int polarity, int attempts, int delay) 83 { 84 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 85 delay, NULL); 86 } 87 88 /** 89 * t4_set_reg_field - set a register field to a value 90 * @adapter: the adapter to program 91 * @addr: the register address 92 * @mask: specifies the portion of the register to modify 93 * @val: the new value for the register field 94 * 95 * Sets a register field specified by the supplied mask to the 96 * given value. 97 */ 98 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 99 u32 val) 100 { 101 u32 v = t4_read_reg(adapter, addr) & ~mask; 102 103 t4_write_reg(adapter, addr, v | val); 104 (void) t4_read_reg(adapter, addr); /* flush */ 105 } 106 107 /** 108 * t4_read_indirect - read indirectly addressed registers 109 * @adap: the adapter 110 * @addr_reg: register holding the indirect address 111 * @data_reg: register holding the value of the indirect register 112 * @vals: where the read register values are stored 113 * @nregs: how many indirect registers to read 114 * @start_idx: index of first indirect register to read 115 * 116 * Reads registers that are accessed indirectly through an address/data 117 * register pair. 118 */ 119 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 120 unsigned int data_reg, u32 *vals, 121 unsigned int nregs, unsigned int start_idx) 122 { 123 while (nregs--) { 124 t4_write_reg(adap, addr_reg, start_idx); 125 *vals++ = t4_read_reg(adap, data_reg); 126 start_idx++; 127 } 128 } 129 130 /** 131 * t4_write_indirect - write indirectly addressed registers 132 * @adap: the adapter 133 * @addr_reg: register holding the indirect addresses 134 * @data_reg: register holding the value for the indirect registers 135 * @vals: values to write 136 * @nregs: how many indirect registers to write 137 * @start_idx: address of first indirect register to write 138 * 139 * Writes a sequential block of registers that are accessed indirectly 140 * through an address/data register pair. 141 */ 142 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 143 unsigned int data_reg, const u32 *vals, 144 unsigned int nregs, unsigned int start_idx) 145 { 146 while (nregs--) { 147 t4_write_reg(adap, addr_reg, start_idx++); 148 t4_write_reg(adap, data_reg, *vals++); 149 } 150 } 151 152 /* 153 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 154 * mechanism. This guarantees that we get the real value even if we're 155 * operating within a Virtual Machine and the Hypervisor is trapping our 156 * Configuration Space accesses. 157 * 158 * N.B. This routine should only be used as a last resort: the firmware uses 159 * the backdoor registers on a regular basis and we can end up 160 * conflicting with it's uses! 161 */ 162 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 163 { 164 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 165 u32 val; 166 167 if (chip_id(adap) <= CHELSIO_T5) 168 req |= F_ENABLE; 169 else 170 req |= F_T6_ENABLE; 171 172 if (is_t4(adap)) 173 req |= F_LOCALCFG; 174 175 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 176 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 177 178 /* 179 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 180 * Configuration Space read. (None of the other fields matter when 181 * F_ENABLE is 0 so a simple register write is easier than a 182 * read-modify-write via t4_set_reg_field().) 183 */ 184 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 185 186 return val; 187 } 188 189 /* 190 * t4_report_fw_error - report firmware error 191 * @adap: the adapter 192 * 193 * The adapter firmware can indicate error conditions to the host. 194 * If the firmware has indicated an error, print out the reason for 195 * the firmware error. 196 */ 197 void t4_report_fw_error(struct adapter *adap) 198 { 199 static const char *const reason[] = { 200 "Crash", /* PCIE_FW_EVAL_CRASH */ 201 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 202 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 203 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 204 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 205 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 206 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 207 "Reserved", /* reserved */ 208 }; 209 u32 pcie_fw; 210 211 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 212 if (pcie_fw & F_PCIE_FW_ERR) { 213 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 214 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 215 } 216 } 217 218 /* 219 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 220 */ 221 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 222 u32 mbox_addr) 223 { 224 for ( ; nflit; nflit--, mbox_addr += 8) 225 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 226 } 227 228 /* 229 * Handle a FW assertion reported in a mailbox. 230 */ 231 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 232 { 233 CH_ALERT(adap, 234 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 235 asrt->u.assert.filename_0_7, 236 be32_to_cpu(asrt->u.assert.line), 237 be32_to_cpu(asrt->u.assert.x), 238 be32_to_cpu(asrt->u.assert.y)); 239 } 240 241 struct port_tx_state { 242 uint64_t rx_pause; 243 uint64_t tx_frames; 244 }; 245 246 static void 247 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 248 { 249 uint32_t rx_pause_reg, tx_frames_reg; 250 251 if (is_t4(sc)) { 252 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 253 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 254 } else { 255 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 256 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 257 } 258 259 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 260 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 261 } 262 263 static void 264 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 265 { 266 int i; 267 268 for_each_port(sc, i) 269 read_tx_state_one(sc, i, &tx_state[i]); 270 } 271 272 static void 273 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 274 { 275 uint32_t port_ctl_reg; 276 uint64_t tx_frames, rx_pause; 277 int i; 278 279 for_each_port(sc, i) { 280 rx_pause = tx_state[i].rx_pause; 281 tx_frames = tx_state[i].tx_frames; 282 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 283 284 if (is_t4(sc)) 285 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 286 else 287 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 288 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 289 rx_pause != tx_state[i].rx_pause && 290 tx_frames == tx_state[i].tx_frames) { 291 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 292 mdelay(1); 293 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 294 } 295 } 296 } 297 298 #define X_CIM_PF_NOACCESS 0xeeeeeeee 299 /** 300 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 301 * @adap: the adapter 302 * @mbox: index of the mailbox to use 303 * @cmd: the command to write 304 * @size: command length in bytes 305 * @rpl: where to optionally store the reply 306 * @sleep_ok: if true we may sleep while awaiting command completion 307 * @timeout: time to wait for command to finish before timing out 308 * (negative implies @sleep_ok=false) 309 * 310 * Sends the given command to FW through the selected mailbox and waits 311 * for the FW to execute the command. If @rpl is not %NULL it is used to 312 * store the FW's reply to the command. The command and its optional 313 * reply are of the same length. Some FW commands like RESET and 314 * INITIALIZE can take a considerable amount of time to execute. 315 * @sleep_ok determines whether we may sleep while awaiting the response. 316 * If sleeping is allowed we use progressive backoff otherwise we spin. 317 * Note that passing in a negative @timeout is an alternate mechanism 318 * for specifying @sleep_ok=false. This is useful when a higher level 319 * interface allows for specification of @timeout but not @sleep_ok ... 320 * 321 * The return value is 0 on success or a negative errno on failure. A 322 * failure can happen either because we are not able to execute the 323 * command or FW executes it but signals an error. In the latter case 324 * the return value is the error code indicated by FW (negated). 325 */ 326 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 327 int size, void *rpl, bool sleep_ok, int timeout) 328 { 329 /* 330 * We delay in small increments at first in an effort to maintain 331 * responsiveness for simple, fast executing commands but then back 332 * off to larger delays to a maximum retry delay. 333 */ 334 static const int delay[] = { 335 1, 1, 3, 5, 10, 10, 20, 50, 100 336 }; 337 u32 v; 338 u64 res; 339 int i, ms, delay_idx, ret, next_tx_check; 340 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 341 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 342 u32 ctl; 343 __be64 cmd_rpl[MBOX_LEN/8]; 344 u32 pcie_fw; 345 struct port_tx_state tx_state[MAX_NPORTS]; 346 347 if (adap->flags & CHK_MBOX_ACCESS) 348 ASSERT_SYNCHRONIZED_OP(adap); 349 350 if (size <= 0 || (size & 15) || size > MBOX_LEN) 351 return -EINVAL; 352 353 if (adap->flags & IS_VF) { 354 if (is_t6(adap)) 355 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 356 else 357 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 358 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 359 } 360 361 /* 362 * If we have a negative timeout, that implies that we can't sleep. 363 */ 364 if (timeout < 0) { 365 sleep_ok = false; 366 timeout = -timeout; 367 } 368 369 /* 370 * Attempt to gain access to the mailbox. 371 */ 372 pcie_fw = 0; 373 if (!(adap->flags & IS_VF)) { 374 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 375 if (pcie_fw & F_PCIE_FW_ERR) 376 goto failed; 377 } 378 for (i = 0; i < 4; i++) { 379 ctl = t4_read_reg(adap, ctl_reg); 380 v = G_MBOWNER(ctl); 381 if (v != X_MBOWNER_NONE) 382 break; 383 } 384 385 /* 386 * If we were unable to gain access, report the error to our caller. 387 */ 388 if (v != X_MBOWNER_PL) { 389 if (!(adap->flags & IS_VF)) { 390 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 391 if (pcie_fw & F_PCIE_FW_ERR) 392 goto failed; 393 } 394 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 395 return ret; 396 } 397 398 /* 399 * If we gain ownership of the mailbox and there's a "valid" message 400 * in it, this is likely an asynchronous error message from the 401 * firmware. So we'll report that and then proceed on with attempting 402 * to issue our own command ... which may well fail if the error 403 * presaged the firmware crashing ... 404 */ 405 if (ctl & F_MBMSGVALID) { 406 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 407 } 408 409 /* 410 * Copy in the new mailbox command and send it on its way ... 411 */ 412 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 413 memcpy(cmd_rpl, cmd, size); 414 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 415 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 416 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 417 418 if (adap->flags & IS_VF) { 419 /* 420 * For the VFs, the Mailbox Data "registers" are 421 * actually backed by T4's "MA" interface rather than 422 * PL Registers (as is the case for the PFs). Because 423 * these are in different coherency domains, the write 424 * to the VF's PL-register-backed Mailbox Control can 425 * race in front of the writes to the MA-backed VF 426 * Mailbox Data "registers". So we need to do a 427 * read-back on at least one byte of the VF Mailbox 428 * Data registers before doing the write to the VF 429 * Mailbox Control register. 430 */ 431 t4_read_reg(adap, data_reg); 432 } 433 434 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 435 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 436 next_tx_check = 1000; 437 delay_idx = 0; 438 ms = delay[0]; 439 440 /* 441 * Loop waiting for the reply; bail out if we time out or the firmware 442 * reports an error. 443 */ 444 for (i = 0; i < timeout; i += ms) { 445 if (!(adap->flags & IS_VF)) { 446 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 447 if (pcie_fw & F_PCIE_FW_ERR) 448 break; 449 } 450 451 if (i >= next_tx_check) { 452 check_tx_state(adap, &tx_state[0]); 453 next_tx_check = i + 1000; 454 } 455 456 if (sleep_ok) { 457 ms = delay[delay_idx]; /* last element may repeat */ 458 if (delay_idx < ARRAY_SIZE(delay) - 1) 459 delay_idx++; 460 msleep(ms); 461 } else { 462 mdelay(ms); 463 } 464 465 v = t4_read_reg(adap, ctl_reg); 466 if (v == X_CIM_PF_NOACCESS) 467 continue; 468 if (G_MBOWNER(v) == X_MBOWNER_PL) { 469 if (!(v & F_MBMSGVALID)) { 470 t4_write_reg(adap, ctl_reg, 471 V_MBOWNER(X_MBOWNER_NONE)); 472 continue; 473 } 474 475 /* 476 * Retrieve the command reply and release the mailbox. 477 */ 478 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 479 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 480 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 481 482 res = be64_to_cpu(cmd_rpl[0]); 483 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 484 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 485 res = V_FW_CMD_RETVAL(EIO); 486 } else if (rpl) 487 memcpy(rpl, cmd_rpl, size); 488 return -G_FW_CMD_RETVAL((int)res); 489 } 490 } 491 492 /* 493 * We timed out waiting for a reply to our mailbox command. Report 494 * the error and also check to see if the firmware reported any 495 * errors ... 496 */ 497 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 498 *(const u8 *)cmd, mbox, pcie_fw); 499 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 500 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 501 failed: 502 adap->flags &= ~FW_OK; 503 ret = pcie_fw & F_PCIE_FW_ERR ? -ENXIO : -ETIMEDOUT; 504 t4_fatal_err(adap, true); 505 return ret; 506 } 507 508 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 509 void *rpl, bool sleep_ok) 510 { 511 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 512 sleep_ok, FW_CMD_MAX_TIMEOUT); 513 514 } 515 516 static int t4_edc_err_read(struct adapter *adap, int idx) 517 { 518 u32 edc_ecc_err_addr_reg; 519 u32 edc_bist_status_rdata_reg; 520 521 if (is_t4(adap)) { 522 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 523 return 0; 524 } 525 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 526 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 527 return 0; 528 } 529 530 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 531 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 532 533 CH_WARN(adap, 534 "edc%d err addr 0x%x: 0x%x.\n", 535 idx, edc_ecc_err_addr_reg, 536 t4_read_reg(adap, edc_ecc_err_addr_reg)); 537 CH_WARN(adap, 538 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 539 edc_bist_status_rdata_reg, 540 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 541 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 549 550 return 0; 551 } 552 553 /** 554 * t4_mc_read - read from MC through backdoor accesses 555 * @adap: the adapter 556 * @idx: which MC to access 557 * @addr: address of first byte requested 558 * @data: 64 bytes of data containing the requested address 559 * @ecc: where to store the corresponding 64-bit ECC word 560 * 561 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 562 * that covers the requested address @addr. If @parity is not %NULL it 563 * is assigned the 64-bit ECC word for the read data. 564 */ 565 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 566 { 567 int i; 568 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 569 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 570 571 if (is_t4(adap)) { 572 mc_bist_cmd_reg = A_MC_BIST_CMD; 573 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 574 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 575 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 576 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 577 } else { 578 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 579 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 580 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 581 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 582 idx); 583 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 584 idx); 585 } 586 587 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 588 return -EBUSY; 589 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 590 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 591 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 592 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 593 F_START_BIST | V_BIST_CMD_GAP(1)); 594 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 595 if (i) 596 return i; 597 598 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 599 600 for (i = 15; i >= 0; i--) 601 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 602 if (ecc) 603 *ecc = t4_read_reg64(adap, MC_DATA(16)); 604 #undef MC_DATA 605 return 0; 606 } 607 608 /** 609 * t4_edc_read - read from EDC through backdoor accesses 610 * @adap: the adapter 611 * @idx: which EDC to access 612 * @addr: address of first byte requested 613 * @data: 64 bytes of data containing the requested address 614 * @ecc: where to store the corresponding 64-bit ECC word 615 * 616 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 617 * that covers the requested address @addr. If @parity is not %NULL it 618 * is assigned the 64-bit ECC word for the read data. 619 */ 620 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 621 { 622 int i; 623 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 624 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 625 626 if (is_t4(adap)) { 627 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 628 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 629 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 630 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 631 idx); 632 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 633 idx); 634 } else { 635 /* 636 * These macro are missing in t4_regs.h file. 637 * Added temporarily for testing. 638 */ 639 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 640 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 641 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 642 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 643 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 644 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 645 idx); 646 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 647 idx); 648 #undef EDC_REG_T5 649 #undef EDC_STRIDE_T5 650 } 651 652 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 653 return -EBUSY; 654 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 655 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 656 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 657 t4_write_reg(adap, edc_bist_cmd_reg, 658 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 659 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 660 if (i) 661 return i; 662 663 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 664 665 for (i = 15; i >= 0; i--) 666 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 667 if (ecc) 668 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 669 #undef EDC_DATA 670 return 0; 671 } 672 673 /** 674 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 675 * @adap: the adapter 676 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 677 * @addr: address within indicated memory type 678 * @len: amount of memory to read 679 * @buf: host memory buffer 680 * 681 * Reads an [almost] arbitrary memory region in the firmware: the 682 * firmware memory address, length and host buffer must be aligned on 683 * 32-bit boudaries. The memory is returned as a raw byte sequence from 684 * the firmware's memory. If this memory contains data structures which 685 * contain multi-byte integers, it's the callers responsibility to 686 * perform appropriate byte order conversions. 687 */ 688 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 689 __be32 *buf) 690 { 691 u32 pos, start, end, offset; 692 int ret; 693 694 /* 695 * Argument sanity checks ... 696 */ 697 if ((addr & 0x3) || (len & 0x3)) 698 return -EINVAL; 699 700 /* 701 * The underlaying EDC/MC read routines read 64 bytes at a time so we 702 * need to round down the start and round up the end. We'll start 703 * copying out of the first line at (addr - start) a word at a time. 704 */ 705 start = rounddown2(addr, 64); 706 end = roundup2(addr + len, 64); 707 offset = (addr - start)/sizeof(__be32); 708 709 for (pos = start; pos < end; pos += 64, offset = 0) { 710 __be32 data[16]; 711 712 /* 713 * Read the chip's memory block and bail if there's an error. 714 */ 715 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 716 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 717 else 718 ret = t4_edc_read(adap, mtype, pos, data, NULL); 719 if (ret) 720 return ret; 721 722 /* 723 * Copy the data into the caller's memory buffer. 724 */ 725 while (offset < 16 && len > 0) { 726 *buf++ = data[offset++]; 727 len -= sizeof(__be32); 728 } 729 } 730 731 return 0; 732 } 733 734 /* 735 * Return the specified PCI-E Configuration Space register from our Physical 736 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 737 * since we prefer to let the firmware own all of these registers, but if that 738 * fails we go for it directly ourselves. 739 */ 740 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 741 { 742 743 /* 744 * If fw_attach != 0, construct and send the Firmware LDST Command to 745 * retrieve the specified PCI-E Configuration Space register. 746 */ 747 if (drv_fw_attach != 0) { 748 struct fw_ldst_cmd ldst_cmd; 749 int ret; 750 751 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 752 ldst_cmd.op_to_addrspace = 753 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 754 F_FW_CMD_REQUEST | 755 F_FW_CMD_READ | 756 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 757 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 758 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 759 ldst_cmd.u.pcie.ctrl_to_fn = 760 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 761 ldst_cmd.u.pcie.r = reg; 762 763 /* 764 * If the LDST Command succeeds, return the result, otherwise 765 * fall through to reading it directly ourselves ... 766 */ 767 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 768 &ldst_cmd); 769 if (ret == 0) 770 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 771 772 CH_WARN(adap, "Firmware failed to return " 773 "Configuration Space register %d, err = %d\n", 774 reg, -ret); 775 } 776 777 /* 778 * Read the desired Configuration Space register via the PCI-E 779 * Backdoor mechanism. 780 */ 781 return t4_hw_pci_read_cfg4(adap, reg); 782 } 783 784 /** 785 * t4_get_regs_len - return the size of the chips register set 786 * @adapter: the adapter 787 * 788 * Returns the size of the chip's BAR0 register space. 789 */ 790 unsigned int t4_get_regs_len(struct adapter *adapter) 791 { 792 unsigned int chip_version = chip_id(adapter); 793 794 switch (chip_version) { 795 case CHELSIO_T4: 796 if (adapter->flags & IS_VF) 797 return FW_T4VF_REGMAP_SIZE; 798 return T4_REGMAP_SIZE; 799 800 case CHELSIO_T5: 801 case CHELSIO_T6: 802 if (adapter->flags & IS_VF) 803 return FW_T4VF_REGMAP_SIZE; 804 return T5_REGMAP_SIZE; 805 } 806 807 CH_ERR(adapter, 808 "Unsupported chip version %d\n", chip_version); 809 return 0; 810 } 811 812 /** 813 * t4_get_regs - read chip registers into provided buffer 814 * @adap: the adapter 815 * @buf: register buffer 816 * @buf_size: size (in bytes) of register buffer 817 * 818 * If the provided register buffer isn't large enough for the chip's 819 * full register range, the register dump will be truncated to the 820 * register buffer's size. 821 */ 822 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 823 { 824 static const unsigned int t4_reg_ranges[] = { 825 0x1008, 0x1108, 826 0x1180, 0x1184, 827 0x1190, 0x1194, 828 0x11a0, 0x11a4, 829 0x11b0, 0x11b4, 830 0x11fc, 0x123c, 831 0x1300, 0x173c, 832 0x1800, 0x18fc, 833 0x3000, 0x30d8, 834 0x30e0, 0x30e4, 835 0x30ec, 0x5910, 836 0x5920, 0x5924, 837 0x5960, 0x5960, 838 0x5968, 0x5968, 839 0x5970, 0x5970, 840 0x5978, 0x5978, 841 0x5980, 0x5980, 842 0x5988, 0x5988, 843 0x5990, 0x5990, 844 0x5998, 0x5998, 845 0x59a0, 0x59d4, 846 0x5a00, 0x5ae0, 847 0x5ae8, 0x5ae8, 848 0x5af0, 0x5af0, 849 0x5af8, 0x5af8, 850 0x6000, 0x6098, 851 0x6100, 0x6150, 852 0x6200, 0x6208, 853 0x6240, 0x6248, 854 0x6280, 0x62b0, 855 0x62c0, 0x6338, 856 0x6370, 0x638c, 857 0x6400, 0x643c, 858 0x6500, 0x6524, 859 0x6a00, 0x6a04, 860 0x6a14, 0x6a38, 861 0x6a60, 0x6a70, 862 0x6a78, 0x6a78, 863 0x6b00, 0x6b0c, 864 0x6b1c, 0x6b84, 865 0x6bf0, 0x6bf8, 866 0x6c00, 0x6c0c, 867 0x6c1c, 0x6c84, 868 0x6cf0, 0x6cf8, 869 0x6d00, 0x6d0c, 870 0x6d1c, 0x6d84, 871 0x6df0, 0x6df8, 872 0x6e00, 0x6e0c, 873 0x6e1c, 0x6e84, 874 0x6ef0, 0x6ef8, 875 0x6f00, 0x6f0c, 876 0x6f1c, 0x6f84, 877 0x6ff0, 0x6ff8, 878 0x7000, 0x700c, 879 0x701c, 0x7084, 880 0x70f0, 0x70f8, 881 0x7100, 0x710c, 882 0x711c, 0x7184, 883 0x71f0, 0x71f8, 884 0x7200, 0x720c, 885 0x721c, 0x7284, 886 0x72f0, 0x72f8, 887 0x7300, 0x730c, 888 0x731c, 0x7384, 889 0x73f0, 0x73f8, 890 0x7400, 0x7450, 891 0x7500, 0x7530, 892 0x7600, 0x760c, 893 0x7614, 0x761c, 894 0x7680, 0x76cc, 895 0x7700, 0x7798, 896 0x77c0, 0x77fc, 897 0x7900, 0x79fc, 898 0x7b00, 0x7b58, 899 0x7b60, 0x7b84, 900 0x7b8c, 0x7c38, 901 0x7d00, 0x7d38, 902 0x7d40, 0x7d80, 903 0x7d8c, 0x7ddc, 904 0x7de4, 0x7e04, 905 0x7e10, 0x7e1c, 906 0x7e24, 0x7e38, 907 0x7e40, 0x7e44, 908 0x7e4c, 0x7e78, 909 0x7e80, 0x7ea4, 910 0x7eac, 0x7edc, 911 0x7ee8, 0x7efc, 912 0x8dc0, 0x8e04, 913 0x8e10, 0x8e1c, 914 0x8e30, 0x8e78, 915 0x8ea0, 0x8eb8, 916 0x8ec0, 0x8f6c, 917 0x8fc0, 0x9008, 918 0x9010, 0x9058, 919 0x9060, 0x9060, 920 0x9068, 0x9074, 921 0x90fc, 0x90fc, 922 0x9400, 0x9408, 923 0x9410, 0x9458, 924 0x9600, 0x9600, 925 0x9608, 0x9638, 926 0x9640, 0x96bc, 927 0x9800, 0x9808, 928 0x9820, 0x983c, 929 0x9850, 0x9864, 930 0x9c00, 0x9c6c, 931 0x9c80, 0x9cec, 932 0x9d00, 0x9d6c, 933 0x9d80, 0x9dec, 934 0x9e00, 0x9e6c, 935 0x9e80, 0x9eec, 936 0x9f00, 0x9f6c, 937 0x9f80, 0x9fec, 938 0xd004, 0xd004, 939 0xd010, 0xd03c, 940 0xdfc0, 0xdfe0, 941 0xe000, 0xea7c, 942 0xf000, 0x11110, 943 0x11118, 0x11190, 944 0x19040, 0x1906c, 945 0x19078, 0x19080, 946 0x1908c, 0x190e4, 947 0x190f0, 0x190f8, 948 0x19100, 0x19110, 949 0x19120, 0x19124, 950 0x19150, 0x19194, 951 0x1919c, 0x191b0, 952 0x191d0, 0x191e8, 953 0x19238, 0x1924c, 954 0x193f8, 0x1943c, 955 0x1944c, 0x19474, 956 0x19490, 0x194e0, 957 0x194f0, 0x194f8, 958 0x19800, 0x19c08, 959 0x19c10, 0x19c90, 960 0x19ca0, 0x19ce4, 961 0x19cf0, 0x19d40, 962 0x19d50, 0x19d94, 963 0x19da0, 0x19de8, 964 0x19df0, 0x19e40, 965 0x19e50, 0x19e90, 966 0x19ea0, 0x19f4c, 967 0x1a000, 0x1a004, 968 0x1a010, 0x1a06c, 969 0x1a0b0, 0x1a0e4, 970 0x1a0ec, 0x1a0f4, 971 0x1a100, 0x1a108, 972 0x1a114, 0x1a120, 973 0x1a128, 0x1a130, 974 0x1a138, 0x1a138, 975 0x1a190, 0x1a1c4, 976 0x1a1fc, 0x1a1fc, 977 0x1e040, 0x1e04c, 978 0x1e284, 0x1e28c, 979 0x1e2c0, 0x1e2c0, 980 0x1e2e0, 0x1e2e0, 981 0x1e300, 0x1e384, 982 0x1e3c0, 0x1e3c8, 983 0x1e440, 0x1e44c, 984 0x1e684, 0x1e68c, 985 0x1e6c0, 0x1e6c0, 986 0x1e6e0, 0x1e6e0, 987 0x1e700, 0x1e784, 988 0x1e7c0, 0x1e7c8, 989 0x1e840, 0x1e84c, 990 0x1ea84, 0x1ea8c, 991 0x1eac0, 0x1eac0, 992 0x1eae0, 0x1eae0, 993 0x1eb00, 0x1eb84, 994 0x1ebc0, 0x1ebc8, 995 0x1ec40, 0x1ec4c, 996 0x1ee84, 0x1ee8c, 997 0x1eec0, 0x1eec0, 998 0x1eee0, 0x1eee0, 999 0x1ef00, 0x1ef84, 1000 0x1efc0, 0x1efc8, 1001 0x1f040, 0x1f04c, 1002 0x1f284, 0x1f28c, 1003 0x1f2c0, 0x1f2c0, 1004 0x1f2e0, 0x1f2e0, 1005 0x1f300, 0x1f384, 1006 0x1f3c0, 0x1f3c8, 1007 0x1f440, 0x1f44c, 1008 0x1f684, 0x1f68c, 1009 0x1f6c0, 0x1f6c0, 1010 0x1f6e0, 0x1f6e0, 1011 0x1f700, 0x1f784, 1012 0x1f7c0, 0x1f7c8, 1013 0x1f840, 0x1f84c, 1014 0x1fa84, 0x1fa8c, 1015 0x1fac0, 0x1fac0, 1016 0x1fae0, 0x1fae0, 1017 0x1fb00, 0x1fb84, 1018 0x1fbc0, 0x1fbc8, 1019 0x1fc40, 0x1fc4c, 1020 0x1fe84, 0x1fe8c, 1021 0x1fec0, 0x1fec0, 1022 0x1fee0, 0x1fee0, 1023 0x1ff00, 0x1ff84, 1024 0x1ffc0, 0x1ffc8, 1025 0x20000, 0x2002c, 1026 0x20100, 0x2013c, 1027 0x20190, 0x201a0, 1028 0x201a8, 0x201b8, 1029 0x201c4, 0x201c8, 1030 0x20200, 0x20318, 1031 0x20400, 0x204b4, 1032 0x204c0, 0x20528, 1033 0x20540, 0x20614, 1034 0x21000, 0x21040, 1035 0x2104c, 0x21060, 1036 0x210c0, 0x210ec, 1037 0x21200, 0x21268, 1038 0x21270, 0x21284, 1039 0x212fc, 0x21388, 1040 0x21400, 0x21404, 1041 0x21500, 0x21500, 1042 0x21510, 0x21518, 1043 0x2152c, 0x21530, 1044 0x2153c, 0x2153c, 1045 0x21550, 0x21554, 1046 0x21600, 0x21600, 1047 0x21608, 0x2161c, 1048 0x21624, 0x21628, 1049 0x21630, 0x21634, 1050 0x2163c, 0x2163c, 1051 0x21700, 0x2171c, 1052 0x21780, 0x2178c, 1053 0x21800, 0x21818, 1054 0x21820, 0x21828, 1055 0x21830, 0x21848, 1056 0x21850, 0x21854, 1057 0x21860, 0x21868, 1058 0x21870, 0x21870, 1059 0x21878, 0x21898, 1060 0x218a0, 0x218a8, 1061 0x218b0, 0x218c8, 1062 0x218d0, 0x218d4, 1063 0x218e0, 0x218e8, 1064 0x218f0, 0x218f0, 1065 0x218f8, 0x21a18, 1066 0x21a20, 0x21a28, 1067 0x21a30, 0x21a48, 1068 0x21a50, 0x21a54, 1069 0x21a60, 0x21a68, 1070 0x21a70, 0x21a70, 1071 0x21a78, 0x21a98, 1072 0x21aa0, 0x21aa8, 1073 0x21ab0, 0x21ac8, 1074 0x21ad0, 0x21ad4, 1075 0x21ae0, 0x21ae8, 1076 0x21af0, 0x21af0, 1077 0x21af8, 0x21c18, 1078 0x21c20, 0x21c20, 1079 0x21c28, 0x21c30, 1080 0x21c38, 0x21c38, 1081 0x21c80, 0x21c98, 1082 0x21ca0, 0x21ca8, 1083 0x21cb0, 0x21cc8, 1084 0x21cd0, 0x21cd4, 1085 0x21ce0, 0x21ce8, 1086 0x21cf0, 0x21cf0, 1087 0x21cf8, 0x21d7c, 1088 0x21e00, 0x21e04, 1089 0x22000, 0x2202c, 1090 0x22100, 0x2213c, 1091 0x22190, 0x221a0, 1092 0x221a8, 0x221b8, 1093 0x221c4, 0x221c8, 1094 0x22200, 0x22318, 1095 0x22400, 0x224b4, 1096 0x224c0, 0x22528, 1097 0x22540, 0x22614, 1098 0x23000, 0x23040, 1099 0x2304c, 0x23060, 1100 0x230c0, 0x230ec, 1101 0x23200, 0x23268, 1102 0x23270, 0x23284, 1103 0x232fc, 0x23388, 1104 0x23400, 0x23404, 1105 0x23500, 0x23500, 1106 0x23510, 0x23518, 1107 0x2352c, 0x23530, 1108 0x2353c, 0x2353c, 1109 0x23550, 0x23554, 1110 0x23600, 0x23600, 1111 0x23608, 0x2361c, 1112 0x23624, 0x23628, 1113 0x23630, 0x23634, 1114 0x2363c, 0x2363c, 1115 0x23700, 0x2371c, 1116 0x23780, 0x2378c, 1117 0x23800, 0x23818, 1118 0x23820, 0x23828, 1119 0x23830, 0x23848, 1120 0x23850, 0x23854, 1121 0x23860, 0x23868, 1122 0x23870, 0x23870, 1123 0x23878, 0x23898, 1124 0x238a0, 0x238a8, 1125 0x238b0, 0x238c8, 1126 0x238d0, 0x238d4, 1127 0x238e0, 0x238e8, 1128 0x238f0, 0x238f0, 1129 0x238f8, 0x23a18, 1130 0x23a20, 0x23a28, 1131 0x23a30, 0x23a48, 1132 0x23a50, 0x23a54, 1133 0x23a60, 0x23a68, 1134 0x23a70, 0x23a70, 1135 0x23a78, 0x23a98, 1136 0x23aa0, 0x23aa8, 1137 0x23ab0, 0x23ac8, 1138 0x23ad0, 0x23ad4, 1139 0x23ae0, 0x23ae8, 1140 0x23af0, 0x23af0, 1141 0x23af8, 0x23c18, 1142 0x23c20, 0x23c20, 1143 0x23c28, 0x23c30, 1144 0x23c38, 0x23c38, 1145 0x23c80, 0x23c98, 1146 0x23ca0, 0x23ca8, 1147 0x23cb0, 0x23cc8, 1148 0x23cd0, 0x23cd4, 1149 0x23ce0, 0x23ce8, 1150 0x23cf0, 0x23cf0, 1151 0x23cf8, 0x23d7c, 1152 0x23e00, 0x23e04, 1153 0x24000, 0x2402c, 1154 0x24100, 0x2413c, 1155 0x24190, 0x241a0, 1156 0x241a8, 0x241b8, 1157 0x241c4, 0x241c8, 1158 0x24200, 0x24318, 1159 0x24400, 0x244b4, 1160 0x244c0, 0x24528, 1161 0x24540, 0x24614, 1162 0x25000, 0x25040, 1163 0x2504c, 0x25060, 1164 0x250c0, 0x250ec, 1165 0x25200, 0x25268, 1166 0x25270, 0x25284, 1167 0x252fc, 0x25388, 1168 0x25400, 0x25404, 1169 0x25500, 0x25500, 1170 0x25510, 0x25518, 1171 0x2552c, 0x25530, 1172 0x2553c, 0x2553c, 1173 0x25550, 0x25554, 1174 0x25600, 0x25600, 1175 0x25608, 0x2561c, 1176 0x25624, 0x25628, 1177 0x25630, 0x25634, 1178 0x2563c, 0x2563c, 1179 0x25700, 0x2571c, 1180 0x25780, 0x2578c, 1181 0x25800, 0x25818, 1182 0x25820, 0x25828, 1183 0x25830, 0x25848, 1184 0x25850, 0x25854, 1185 0x25860, 0x25868, 1186 0x25870, 0x25870, 1187 0x25878, 0x25898, 1188 0x258a0, 0x258a8, 1189 0x258b0, 0x258c8, 1190 0x258d0, 0x258d4, 1191 0x258e0, 0x258e8, 1192 0x258f0, 0x258f0, 1193 0x258f8, 0x25a18, 1194 0x25a20, 0x25a28, 1195 0x25a30, 0x25a48, 1196 0x25a50, 0x25a54, 1197 0x25a60, 0x25a68, 1198 0x25a70, 0x25a70, 1199 0x25a78, 0x25a98, 1200 0x25aa0, 0x25aa8, 1201 0x25ab0, 0x25ac8, 1202 0x25ad0, 0x25ad4, 1203 0x25ae0, 0x25ae8, 1204 0x25af0, 0x25af0, 1205 0x25af8, 0x25c18, 1206 0x25c20, 0x25c20, 1207 0x25c28, 0x25c30, 1208 0x25c38, 0x25c38, 1209 0x25c80, 0x25c98, 1210 0x25ca0, 0x25ca8, 1211 0x25cb0, 0x25cc8, 1212 0x25cd0, 0x25cd4, 1213 0x25ce0, 0x25ce8, 1214 0x25cf0, 0x25cf0, 1215 0x25cf8, 0x25d7c, 1216 0x25e00, 0x25e04, 1217 0x26000, 0x2602c, 1218 0x26100, 0x2613c, 1219 0x26190, 0x261a0, 1220 0x261a8, 0x261b8, 1221 0x261c4, 0x261c8, 1222 0x26200, 0x26318, 1223 0x26400, 0x264b4, 1224 0x264c0, 0x26528, 1225 0x26540, 0x26614, 1226 0x27000, 0x27040, 1227 0x2704c, 0x27060, 1228 0x270c0, 0x270ec, 1229 0x27200, 0x27268, 1230 0x27270, 0x27284, 1231 0x272fc, 0x27388, 1232 0x27400, 0x27404, 1233 0x27500, 0x27500, 1234 0x27510, 0x27518, 1235 0x2752c, 0x27530, 1236 0x2753c, 0x2753c, 1237 0x27550, 0x27554, 1238 0x27600, 0x27600, 1239 0x27608, 0x2761c, 1240 0x27624, 0x27628, 1241 0x27630, 0x27634, 1242 0x2763c, 0x2763c, 1243 0x27700, 0x2771c, 1244 0x27780, 0x2778c, 1245 0x27800, 0x27818, 1246 0x27820, 0x27828, 1247 0x27830, 0x27848, 1248 0x27850, 0x27854, 1249 0x27860, 0x27868, 1250 0x27870, 0x27870, 1251 0x27878, 0x27898, 1252 0x278a0, 0x278a8, 1253 0x278b0, 0x278c8, 1254 0x278d0, 0x278d4, 1255 0x278e0, 0x278e8, 1256 0x278f0, 0x278f0, 1257 0x278f8, 0x27a18, 1258 0x27a20, 0x27a28, 1259 0x27a30, 0x27a48, 1260 0x27a50, 0x27a54, 1261 0x27a60, 0x27a68, 1262 0x27a70, 0x27a70, 1263 0x27a78, 0x27a98, 1264 0x27aa0, 0x27aa8, 1265 0x27ab0, 0x27ac8, 1266 0x27ad0, 0x27ad4, 1267 0x27ae0, 0x27ae8, 1268 0x27af0, 0x27af0, 1269 0x27af8, 0x27c18, 1270 0x27c20, 0x27c20, 1271 0x27c28, 0x27c30, 1272 0x27c38, 0x27c38, 1273 0x27c80, 0x27c98, 1274 0x27ca0, 0x27ca8, 1275 0x27cb0, 0x27cc8, 1276 0x27cd0, 0x27cd4, 1277 0x27ce0, 0x27ce8, 1278 0x27cf0, 0x27cf0, 1279 0x27cf8, 0x27d7c, 1280 0x27e00, 0x27e04, 1281 }; 1282 1283 static const unsigned int t4vf_reg_ranges[] = { 1284 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1285 VF_MPS_REG(A_MPS_VF_CTL), 1286 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1287 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1288 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1289 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1290 FW_T4VF_MBDATA_BASE_ADDR, 1291 FW_T4VF_MBDATA_BASE_ADDR + 1292 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1293 }; 1294 1295 static const unsigned int t5_reg_ranges[] = { 1296 0x1008, 0x10c0, 1297 0x10cc, 0x10f8, 1298 0x1100, 0x1100, 1299 0x110c, 0x1148, 1300 0x1180, 0x1184, 1301 0x1190, 0x1194, 1302 0x11a0, 0x11a4, 1303 0x11b0, 0x11b4, 1304 0x11fc, 0x123c, 1305 0x1280, 0x173c, 1306 0x1800, 0x18fc, 1307 0x3000, 0x3028, 1308 0x3060, 0x30b0, 1309 0x30b8, 0x30d8, 1310 0x30e0, 0x30fc, 1311 0x3140, 0x357c, 1312 0x35a8, 0x35cc, 1313 0x35ec, 0x35ec, 1314 0x3600, 0x5624, 1315 0x56cc, 0x56ec, 1316 0x56f4, 0x5720, 1317 0x5728, 0x575c, 1318 0x580c, 0x5814, 1319 0x5890, 0x589c, 1320 0x58a4, 0x58ac, 1321 0x58b8, 0x58bc, 1322 0x5940, 0x59c8, 1323 0x59d0, 0x59dc, 1324 0x59fc, 0x5a18, 1325 0x5a60, 0x5a70, 1326 0x5a80, 0x5a9c, 1327 0x5b94, 0x5bfc, 1328 0x6000, 0x6020, 1329 0x6028, 0x6040, 1330 0x6058, 0x609c, 1331 0x60a8, 0x614c, 1332 0x7700, 0x7798, 1333 0x77c0, 0x78fc, 1334 0x7b00, 0x7b58, 1335 0x7b60, 0x7b84, 1336 0x7b8c, 0x7c54, 1337 0x7d00, 0x7d38, 1338 0x7d40, 0x7d80, 1339 0x7d8c, 0x7ddc, 1340 0x7de4, 0x7e04, 1341 0x7e10, 0x7e1c, 1342 0x7e24, 0x7e38, 1343 0x7e40, 0x7e44, 1344 0x7e4c, 0x7e78, 1345 0x7e80, 0x7edc, 1346 0x7ee8, 0x7efc, 1347 0x8dc0, 0x8de0, 1348 0x8df8, 0x8e04, 1349 0x8e10, 0x8e84, 1350 0x8ea0, 0x8f84, 1351 0x8fc0, 0x9058, 1352 0x9060, 0x9060, 1353 0x9068, 0x90f8, 1354 0x9400, 0x9408, 1355 0x9410, 0x9470, 1356 0x9600, 0x9600, 1357 0x9608, 0x9638, 1358 0x9640, 0x96f4, 1359 0x9800, 0x9808, 1360 0x9810, 0x9864, 1361 0x9c00, 0x9c6c, 1362 0x9c80, 0x9cec, 1363 0x9d00, 0x9d6c, 1364 0x9d80, 0x9dec, 1365 0x9e00, 0x9e6c, 1366 0x9e80, 0x9eec, 1367 0x9f00, 0x9f6c, 1368 0x9f80, 0xa020, 1369 0xd000, 0xd004, 1370 0xd010, 0xd03c, 1371 0xdfc0, 0xdfe0, 1372 0xe000, 0x1106c, 1373 0x11074, 0x11088, 1374 0x1109c, 0x11110, 1375 0x11118, 0x1117c, 1376 0x11190, 0x11204, 1377 0x19040, 0x1906c, 1378 0x19078, 0x19080, 1379 0x1908c, 0x190e8, 1380 0x190f0, 0x190f8, 1381 0x19100, 0x19110, 1382 0x19120, 0x19124, 1383 0x19150, 0x19194, 1384 0x1919c, 0x191b0, 1385 0x191d0, 0x191e8, 1386 0x19238, 0x19290, 1387 0x193f8, 0x19428, 1388 0x19430, 0x19444, 1389 0x1944c, 0x1946c, 1390 0x19474, 0x19474, 1391 0x19490, 0x194cc, 1392 0x194f0, 0x194f8, 1393 0x19c00, 0x19c08, 1394 0x19c10, 0x19c60, 1395 0x19c94, 0x19ce4, 1396 0x19cf0, 0x19d40, 1397 0x19d50, 0x19d94, 1398 0x19da0, 0x19de8, 1399 0x19df0, 0x19e10, 1400 0x19e50, 0x19e90, 1401 0x19ea0, 0x19f24, 1402 0x19f34, 0x19f34, 1403 0x19f40, 0x19f50, 1404 0x19f90, 0x19fb4, 1405 0x19fc4, 0x19fe4, 1406 0x1a000, 0x1a004, 1407 0x1a010, 0x1a06c, 1408 0x1a0b0, 0x1a0e4, 1409 0x1a0ec, 0x1a0f8, 1410 0x1a100, 0x1a108, 1411 0x1a114, 0x1a130, 1412 0x1a138, 0x1a1c4, 1413 0x1a1fc, 0x1a1fc, 1414 0x1e008, 0x1e00c, 1415 0x1e040, 0x1e044, 1416 0x1e04c, 0x1e04c, 1417 0x1e284, 0x1e290, 1418 0x1e2c0, 0x1e2c0, 1419 0x1e2e0, 0x1e2e0, 1420 0x1e300, 0x1e384, 1421 0x1e3c0, 0x1e3c8, 1422 0x1e408, 0x1e40c, 1423 0x1e440, 0x1e444, 1424 0x1e44c, 0x1e44c, 1425 0x1e684, 0x1e690, 1426 0x1e6c0, 0x1e6c0, 1427 0x1e6e0, 0x1e6e0, 1428 0x1e700, 0x1e784, 1429 0x1e7c0, 0x1e7c8, 1430 0x1e808, 0x1e80c, 1431 0x1e840, 0x1e844, 1432 0x1e84c, 0x1e84c, 1433 0x1ea84, 0x1ea90, 1434 0x1eac0, 0x1eac0, 1435 0x1eae0, 0x1eae0, 1436 0x1eb00, 0x1eb84, 1437 0x1ebc0, 0x1ebc8, 1438 0x1ec08, 0x1ec0c, 1439 0x1ec40, 0x1ec44, 1440 0x1ec4c, 0x1ec4c, 1441 0x1ee84, 0x1ee90, 1442 0x1eec0, 0x1eec0, 1443 0x1eee0, 0x1eee0, 1444 0x1ef00, 0x1ef84, 1445 0x1efc0, 0x1efc8, 1446 0x1f008, 0x1f00c, 1447 0x1f040, 0x1f044, 1448 0x1f04c, 0x1f04c, 1449 0x1f284, 0x1f290, 1450 0x1f2c0, 0x1f2c0, 1451 0x1f2e0, 0x1f2e0, 1452 0x1f300, 0x1f384, 1453 0x1f3c0, 0x1f3c8, 1454 0x1f408, 0x1f40c, 1455 0x1f440, 0x1f444, 1456 0x1f44c, 0x1f44c, 1457 0x1f684, 0x1f690, 1458 0x1f6c0, 0x1f6c0, 1459 0x1f6e0, 0x1f6e0, 1460 0x1f700, 0x1f784, 1461 0x1f7c0, 0x1f7c8, 1462 0x1f808, 0x1f80c, 1463 0x1f840, 0x1f844, 1464 0x1f84c, 0x1f84c, 1465 0x1fa84, 0x1fa90, 1466 0x1fac0, 0x1fac0, 1467 0x1fae0, 0x1fae0, 1468 0x1fb00, 0x1fb84, 1469 0x1fbc0, 0x1fbc8, 1470 0x1fc08, 0x1fc0c, 1471 0x1fc40, 0x1fc44, 1472 0x1fc4c, 0x1fc4c, 1473 0x1fe84, 0x1fe90, 1474 0x1fec0, 0x1fec0, 1475 0x1fee0, 0x1fee0, 1476 0x1ff00, 0x1ff84, 1477 0x1ffc0, 0x1ffc8, 1478 0x30000, 0x30030, 1479 0x30100, 0x30144, 1480 0x30190, 0x301a0, 1481 0x301a8, 0x301b8, 1482 0x301c4, 0x301c8, 1483 0x301d0, 0x301d0, 1484 0x30200, 0x30318, 1485 0x30400, 0x304b4, 1486 0x304c0, 0x3052c, 1487 0x30540, 0x3061c, 1488 0x30800, 0x30828, 1489 0x30834, 0x30834, 1490 0x308c0, 0x30908, 1491 0x30910, 0x309ac, 1492 0x30a00, 0x30a14, 1493 0x30a1c, 0x30a2c, 1494 0x30a44, 0x30a50, 1495 0x30a74, 0x30a74, 1496 0x30a7c, 0x30afc, 1497 0x30b08, 0x30c24, 1498 0x30d00, 0x30d00, 1499 0x30d08, 0x30d14, 1500 0x30d1c, 0x30d20, 1501 0x30d3c, 0x30d3c, 1502 0x30d48, 0x30d50, 1503 0x31200, 0x3120c, 1504 0x31220, 0x31220, 1505 0x31240, 0x31240, 1506 0x31600, 0x3160c, 1507 0x31a00, 0x31a1c, 1508 0x31e00, 0x31e20, 1509 0x31e38, 0x31e3c, 1510 0x31e80, 0x31e80, 1511 0x31e88, 0x31ea8, 1512 0x31eb0, 0x31eb4, 1513 0x31ec8, 0x31ed4, 1514 0x31fb8, 0x32004, 1515 0x32200, 0x32200, 1516 0x32208, 0x32240, 1517 0x32248, 0x32280, 1518 0x32288, 0x322c0, 1519 0x322c8, 0x322fc, 1520 0x32600, 0x32630, 1521 0x32a00, 0x32abc, 1522 0x32b00, 0x32b10, 1523 0x32b20, 0x32b30, 1524 0x32b40, 0x32b50, 1525 0x32b60, 0x32b70, 1526 0x33000, 0x33028, 1527 0x33030, 0x33048, 1528 0x33060, 0x33068, 1529 0x33070, 0x3309c, 1530 0x330f0, 0x33128, 1531 0x33130, 0x33148, 1532 0x33160, 0x33168, 1533 0x33170, 0x3319c, 1534 0x331f0, 0x33238, 1535 0x33240, 0x33240, 1536 0x33248, 0x33250, 1537 0x3325c, 0x33264, 1538 0x33270, 0x332b8, 1539 0x332c0, 0x332e4, 1540 0x332f8, 0x33338, 1541 0x33340, 0x33340, 1542 0x33348, 0x33350, 1543 0x3335c, 0x33364, 1544 0x33370, 0x333b8, 1545 0x333c0, 0x333e4, 1546 0x333f8, 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1590 0x34190, 0x341a0, 1591 0x341a8, 0x341b8, 1592 0x341c4, 0x341c8, 1593 0x341d0, 0x341d0, 1594 0x34200, 0x34318, 1595 0x34400, 0x344b4, 1596 0x344c0, 0x3452c, 1597 0x34540, 0x3461c, 1598 0x34800, 0x34828, 1599 0x34834, 0x34834, 1600 0x348c0, 0x34908, 1601 0x34910, 0x349ac, 1602 0x34a00, 0x34a14, 1603 0x34a1c, 0x34a2c, 1604 0x34a44, 0x34a50, 1605 0x34a74, 0x34a74, 1606 0x34a7c, 0x34afc, 1607 0x34b08, 0x34c24, 1608 0x34d00, 0x34d00, 1609 0x34d08, 0x34d14, 1610 0x34d1c, 0x34d20, 1611 0x34d3c, 0x34d3c, 1612 0x34d48, 0x34d50, 1613 0x35200, 0x3520c, 1614 0x35220, 0x35220, 1615 0x35240, 0x35240, 1616 0x35600, 0x3560c, 1617 0x35a00, 0x35a1c, 1618 0x35e00, 0x35e20, 1619 0x35e38, 0x35e3c, 1620 0x35e80, 0x35e80, 1621 0x35e88, 0x35ea8, 1622 0x35eb0, 0x35eb4, 1623 0x35ec8, 0x35ed4, 1624 0x35fb8, 0x36004, 1625 0x36200, 0x36200, 1626 0x36208, 0x36240, 1627 0x36248, 0x36280, 1628 0x36288, 0x362c0, 1629 0x362c8, 0x362fc, 1630 0x36600, 0x36630, 1631 0x36a00, 0x36abc, 1632 0x36b00, 0x36b10, 1633 0x36b20, 0x36b30, 1634 0x36b40, 0x36b50, 1635 0x36b60, 0x36b70, 1636 0x37000, 0x37028, 1637 0x37030, 0x37048, 1638 0x37060, 0x37068, 1639 0x37070, 0x3709c, 1640 0x370f0, 0x37128, 1641 0x37130, 0x37148, 1642 0x37160, 0x37168, 1643 0x37170, 0x3719c, 1644 0x371f0, 0x37238, 1645 0x37240, 0x37240, 1646 0x37248, 0x37250, 1647 0x3725c, 0x37264, 1648 0x37270, 0x372b8, 1649 0x372c0, 0x372e4, 1650 0x372f8, 0x37338, 1651 0x37340, 0x37340, 1652 0x37348, 0x37350, 1653 0x3735c, 0x37364, 1654 0x37370, 0x373b8, 1655 0x373c0, 0x373e4, 1656 0x373f8, 0x37428, 1657 0x37430, 0x37448, 1658 0x37460, 0x37468, 1659 0x37470, 0x3749c, 1660 0x374f0, 0x37528, 1661 0x37530, 0x37548, 1662 0x37560, 0x37568, 1663 0x37570, 0x3759c, 1664 0x375f0, 0x37638, 1665 0x37640, 0x37640, 1666 0x37648, 0x37650, 1667 0x3765c, 0x37664, 1668 0x37670, 0x376b8, 1669 0x376c0, 0x376e4, 1670 0x376f8, 0x37738, 1671 0x37740, 0x37740, 1672 0x37748, 0x37750, 1673 0x3775c, 0x37764, 1674 0x37770, 0x377b8, 1675 0x377c0, 0x377e4, 1676 0x377f8, 0x377fc, 1677 0x37814, 0x37814, 1678 0x3782c, 0x3782c, 1679 0x37880, 0x3788c, 1680 0x378e8, 0x378ec, 1681 0x37900, 0x37928, 1682 0x37930, 0x37948, 1683 0x37960, 0x37968, 1684 0x37970, 0x3799c, 1685 0x379f0, 0x37a38, 1686 0x37a40, 0x37a40, 1687 0x37a48, 0x37a50, 1688 0x37a5c, 0x37a64, 1689 0x37a70, 0x37ab8, 1690 0x37ac0, 0x37ae4, 1691 0x37af8, 0x37b10, 1692 0x37b28, 0x37b28, 1693 0x37b3c, 0x37b50, 1694 0x37bf0, 0x37c10, 1695 0x37c28, 0x37c28, 1696 0x37c3c, 0x37c50, 1697 0x37cf0, 0x37cfc, 1698 0x38000, 0x38030, 1699 0x38100, 0x38144, 1700 0x38190, 0x381a0, 1701 0x381a8, 0x381b8, 1702 0x381c4, 0x381c8, 1703 0x381d0, 0x381d0, 1704 0x38200, 0x38318, 1705 0x38400, 0x384b4, 1706 0x384c0, 0x3852c, 1707 0x38540, 0x3861c, 1708 0x38800, 0x38828, 1709 0x38834, 0x38834, 1710 0x388c0, 0x38908, 1711 0x38910, 0x389ac, 1712 0x38a00, 0x38a14, 1713 0x38a1c, 0x38a2c, 1714 0x38a44, 0x38a50, 1715 0x38a74, 0x38a74, 1716 0x38a7c, 0x38afc, 1717 0x38b08, 0x38c24, 1718 0x38d00, 0x38d00, 1719 0x38d08, 0x38d14, 1720 0x38d1c, 0x38d20, 1721 0x38d3c, 0x38d3c, 1722 0x38d48, 0x38d50, 1723 0x39200, 0x3920c, 1724 0x39220, 0x39220, 1725 0x39240, 0x39240, 1726 0x39600, 0x3960c, 1727 0x39a00, 0x39a1c, 1728 0x39e00, 0x39e20, 1729 0x39e38, 0x39e3c, 1730 0x39e80, 0x39e80, 1731 0x39e88, 0x39ea8, 1732 0x39eb0, 0x39eb4, 1733 0x39ec8, 0x39ed4, 1734 0x39fb8, 0x3a004, 1735 0x3a200, 0x3a200, 1736 0x3a208, 0x3a240, 1737 0x3a248, 0x3a280, 1738 0x3a288, 0x3a2c0, 1739 0x3a2c8, 0x3a2fc, 1740 0x3a600, 0x3a630, 1741 0x3aa00, 0x3aabc, 1742 0x3ab00, 0x3ab10, 1743 0x3ab20, 0x3ab30, 1744 0x3ab40, 0x3ab50, 1745 0x3ab60, 0x3ab70, 1746 0x3b000, 0x3b028, 1747 0x3b030, 0x3b048, 1748 0x3b060, 0x3b068, 1749 0x3b070, 0x3b09c, 1750 0x3b0f0, 0x3b128, 1751 0x3b130, 0x3b148, 1752 0x3b160, 0x3b168, 1753 0x3b170, 0x3b19c, 1754 0x3b1f0, 0x3b238, 1755 0x3b240, 0x3b240, 1756 0x3b248, 0x3b250, 1757 0x3b25c, 0x3b264, 1758 0x3b270, 0x3b2b8, 1759 0x3b2c0, 0x3b2e4, 1760 0x3b2f8, 0x3b338, 1761 0x3b340, 0x3b340, 1762 0x3b348, 0x3b350, 1763 0x3b35c, 0x3b364, 1764 0x3b370, 0x3b3b8, 1765 0x3b3c0, 0x3b3e4, 1766 0x3b3f8, 0x3b428, 1767 0x3b430, 0x3b448, 1768 0x3b460, 0x3b468, 1769 0x3b470, 0x3b49c, 1770 0x3b4f0, 0x3b528, 1771 0x3b530, 0x3b548, 1772 0x3b560, 0x3b568, 1773 0x3b570, 0x3b59c, 1774 0x3b5f0, 0x3b638, 1775 0x3b640, 0x3b640, 1776 0x3b648, 0x3b650, 1777 0x3b65c, 0x3b664, 1778 0x3b670, 0x3b6b8, 1779 0x3b6c0, 0x3b6e4, 1780 0x3b6f8, 0x3b738, 1781 0x3b740, 0x3b740, 1782 0x3b748, 0x3b750, 1783 0x3b75c, 0x3b764, 1784 0x3b770, 0x3b7b8, 1785 0x3b7c0, 0x3b7e4, 1786 0x3b7f8, 0x3b7fc, 1787 0x3b814, 0x3b814, 1788 0x3b82c, 0x3b82c, 1789 0x3b880, 0x3b88c, 1790 0x3b8e8, 0x3b8ec, 1791 0x3b900, 0x3b928, 1792 0x3b930, 0x3b948, 1793 0x3b960, 0x3b968, 1794 0x3b970, 0x3b99c, 1795 0x3b9f0, 0x3ba38, 1796 0x3ba40, 0x3ba40, 1797 0x3ba48, 0x3ba50, 1798 0x3ba5c, 0x3ba64, 1799 0x3ba70, 0x3bab8, 1800 0x3bac0, 0x3bae4, 1801 0x3baf8, 0x3bb10, 1802 0x3bb28, 0x3bb28, 1803 0x3bb3c, 0x3bb50, 1804 0x3bbf0, 0x3bc10, 1805 0x3bc28, 0x3bc28, 1806 0x3bc3c, 0x3bc50, 1807 0x3bcf0, 0x3bcfc, 1808 0x3c000, 0x3c030, 1809 0x3c100, 0x3c144, 1810 0x3c190, 0x3c1a0, 1811 0x3c1a8, 0x3c1b8, 1812 0x3c1c4, 0x3c1c8, 1813 0x3c1d0, 0x3c1d0, 1814 0x3c200, 0x3c318, 1815 0x3c400, 0x3c4b4, 1816 0x3c4c0, 0x3c52c, 1817 0x3c540, 0x3c61c, 1818 0x3c800, 0x3c828, 1819 0x3c834, 0x3c834, 1820 0x3c8c0, 0x3c908, 1821 0x3c910, 0x3c9ac, 1822 0x3ca00, 0x3ca14, 1823 0x3ca1c, 0x3ca2c, 1824 0x3ca44, 0x3ca50, 1825 0x3ca74, 0x3ca74, 1826 0x3ca7c, 0x3cafc, 1827 0x3cb08, 0x3cc24, 1828 0x3cd00, 0x3cd00, 1829 0x3cd08, 0x3cd14, 1830 0x3cd1c, 0x3cd20, 1831 0x3cd3c, 0x3cd3c, 1832 0x3cd48, 0x3cd50, 1833 0x3d200, 0x3d20c, 1834 0x3d220, 0x3d220, 1835 0x3d240, 0x3d240, 1836 0x3d600, 0x3d60c, 1837 0x3da00, 0x3da1c, 1838 0x3de00, 0x3de20, 1839 0x3de38, 0x3de3c, 1840 0x3de80, 0x3de80, 1841 0x3de88, 0x3dea8, 1842 0x3deb0, 0x3deb4, 1843 0x3dec8, 0x3ded4, 1844 0x3dfb8, 0x3e004, 1845 0x3e200, 0x3e200, 1846 0x3e208, 0x3e240, 1847 0x3e248, 0x3e280, 1848 0x3e288, 0x3e2c0, 1849 0x3e2c8, 0x3e2fc, 1850 0x3e600, 0x3e630, 1851 0x3ea00, 0x3eabc, 1852 0x3eb00, 0x3eb10, 1853 0x3eb20, 0x3eb30, 1854 0x3eb40, 0x3eb50, 1855 0x3eb60, 0x3eb70, 1856 0x3f000, 0x3f028, 1857 0x3f030, 0x3f048, 1858 0x3f060, 0x3f068, 1859 0x3f070, 0x3f09c, 1860 0x3f0f0, 0x3f128, 1861 0x3f130, 0x3f148, 1862 0x3f160, 0x3f168, 1863 0x3f170, 0x3f19c, 1864 0x3f1f0, 0x3f238, 1865 0x3f240, 0x3f240, 1866 0x3f248, 0x3f250, 1867 0x3f25c, 0x3f264, 1868 0x3f270, 0x3f2b8, 1869 0x3f2c0, 0x3f2e4, 1870 0x3f2f8, 0x3f338, 1871 0x3f340, 0x3f340, 1872 0x3f348, 0x3f350, 1873 0x3f35c, 0x3f364, 1874 0x3f370, 0x3f3b8, 1875 0x3f3c0, 0x3f3e4, 1876 0x3f3f8, 0x3f428, 1877 0x3f430, 0x3f448, 1878 0x3f460, 0x3f468, 1879 0x3f470, 0x3f49c, 1880 0x3f4f0, 0x3f528, 1881 0x3f530, 0x3f548, 1882 0x3f560, 0x3f568, 1883 0x3f570, 0x3f59c, 1884 0x3f5f0, 0x3f638, 1885 0x3f640, 0x3f640, 1886 0x3f648, 0x3f650, 1887 0x3f65c, 0x3f664, 1888 0x3f670, 0x3f6b8, 1889 0x3f6c0, 0x3f6e4, 1890 0x3f6f8, 0x3f738, 1891 0x3f740, 0x3f740, 1892 0x3f748, 0x3f750, 1893 0x3f75c, 0x3f764, 1894 0x3f770, 0x3f7b8, 1895 0x3f7c0, 0x3f7e4, 1896 0x3f7f8, 0x3f7fc, 1897 0x3f814, 0x3f814, 1898 0x3f82c, 0x3f82c, 1899 0x3f880, 0x3f88c, 1900 0x3f8e8, 0x3f8ec, 1901 0x3f900, 0x3f928, 1902 0x3f930, 0x3f948, 1903 0x3f960, 0x3f968, 1904 0x3f970, 0x3f99c, 1905 0x3f9f0, 0x3fa38, 1906 0x3fa40, 0x3fa40, 1907 0x3fa48, 0x3fa50, 1908 0x3fa5c, 0x3fa64, 1909 0x3fa70, 0x3fab8, 1910 0x3fac0, 0x3fae4, 1911 0x3faf8, 0x3fb10, 1912 0x3fb28, 0x3fb28, 1913 0x3fb3c, 0x3fb50, 1914 0x3fbf0, 0x3fc10, 1915 0x3fc28, 0x3fc28, 1916 0x3fc3c, 0x3fc50, 1917 0x3fcf0, 0x3fcfc, 1918 0x40000, 0x4000c, 1919 0x40040, 0x40050, 1920 0x40060, 0x40068, 1921 0x4007c, 0x4008c, 1922 0x40094, 0x400b0, 1923 0x400c0, 0x40144, 1924 0x40180, 0x4018c, 1925 0x40200, 0x40254, 1926 0x40260, 0x40264, 1927 0x40270, 0x40288, 1928 0x40290, 0x40298, 1929 0x402ac, 0x402c8, 1930 0x402d0, 0x402e0, 1931 0x402f0, 0x402f0, 1932 0x40300, 0x4033c, 1933 0x403f8, 0x403fc, 1934 0x41304, 0x413c4, 1935 0x41400, 0x4140c, 1936 0x41414, 0x4141c, 1937 0x41480, 0x414d0, 1938 0x44000, 0x44054, 1939 0x4405c, 0x44078, 1940 0x440c0, 0x44174, 1941 0x44180, 0x441ac, 1942 0x441b4, 0x441b8, 1943 0x441c0, 0x44254, 1944 0x4425c, 0x44278, 1945 0x442c0, 0x44374, 1946 0x44380, 0x443ac, 1947 0x443b4, 0x443b8, 1948 0x443c0, 0x44454, 1949 0x4445c, 0x44478, 1950 0x444c0, 0x44574, 1951 0x44580, 0x445ac, 1952 0x445b4, 0x445b8, 1953 0x445c0, 0x44654, 1954 0x4465c, 0x44678, 1955 0x446c0, 0x44774, 1956 0x44780, 0x447ac, 1957 0x447b4, 0x447b8, 1958 0x447c0, 0x44854, 1959 0x4485c, 0x44878, 1960 0x448c0, 0x44974, 1961 0x44980, 0x449ac, 1962 0x449b4, 0x449b8, 1963 0x449c0, 0x449fc, 1964 0x45000, 0x45004, 1965 0x45010, 0x45030, 1966 0x45040, 0x45060, 1967 0x45068, 0x45068, 1968 0x45080, 0x45084, 1969 0x450a0, 0x450b0, 1970 0x45200, 0x45204, 1971 0x45210, 0x45230, 1972 0x45240, 0x45260, 1973 0x45268, 0x45268, 1974 0x45280, 0x45284, 1975 0x452a0, 0x452b0, 1976 0x460c0, 0x460e4, 1977 0x47000, 0x4703c, 1978 0x47044, 0x4708c, 1979 0x47200, 0x47250, 1980 0x47400, 0x47408, 1981 0x47414, 0x47420, 1982 0x47600, 0x47618, 1983 0x47800, 0x47814, 1984 0x48000, 0x4800c, 1985 0x48040, 0x48050, 1986 0x48060, 0x48068, 1987 0x4807c, 0x4808c, 1988 0x48094, 0x480b0, 1989 0x480c0, 0x48144, 1990 0x48180, 0x4818c, 1991 0x48200, 0x48254, 1992 0x48260, 0x48264, 1993 0x48270, 0x48288, 1994 0x48290, 0x48298, 1995 0x482ac, 0x482c8, 1996 0x482d0, 0x482e0, 1997 0x482f0, 0x482f0, 1998 0x48300, 0x4833c, 1999 0x483f8, 0x483fc, 2000 0x49304, 0x493c4, 2001 0x49400, 0x4940c, 2002 0x49414, 0x4941c, 2003 0x49480, 0x494d0, 2004 0x4c000, 0x4c054, 2005 0x4c05c, 0x4c078, 2006 0x4c0c0, 0x4c174, 2007 0x4c180, 0x4c1ac, 2008 0x4c1b4, 0x4c1b8, 2009 0x4c1c0, 0x4c254, 2010 0x4c25c, 0x4c278, 2011 0x4c2c0, 0x4c374, 2012 0x4c380, 0x4c3ac, 2013 0x4c3b4, 0x4c3b8, 2014 0x4c3c0, 0x4c454, 2015 0x4c45c, 0x4c478, 2016 0x4c4c0, 0x4c574, 2017 0x4c580, 0x4c5ac, 2018 0x4c5b4, 0x4c5b8, 2019 0x4c5c0, 0x4c654, 2020 0x4c65c, 0x4c678, 2021 0x4c6c0, 0x4c774, 2022 0x4c780, 0x4c7ac, 2023 0x4c7b4, 0x4c7b8, 2024 0x4c7c0, 0x4c854, 2025 0x4c85c, 0x4c878, 2026 0x4c8c0, 0x4c974, 2027 0x4c980, 0x4c9ac, 2028 0x4c9b4, 0x4c9b8, 2029 0x4c9c0, 0x4c9fc, 2030 0x4d000, 0x4d004, 2031 0x4d010, 0x4d030, 2032 0x4d040, 0x4d060, 2033 0x4d068, 0x4d068, 2034 0x4d080, 0x4d084, 2035 0x4d0a0, 0x4d0b0, 2036 0x4d200, 0x4d204, 2037 0x4d210, 0x4d230, 2038 0x4d240, 0x4d260, 2039 0x4d268, 0x4d268, 2040 0x4d280, 0x4d284, 2041 0x4d2a0, 0x4d2b0, 2042 0x4e0c0, 0x4e0e4, 2043 0x4f000, 0x4f03c, 2044 0x4f044, 0x4f08c, 2045 0x4f200, 0x4f250, 2046 0x4f400, 0x4f408, 2047 0x4f414, 0x4f420, 2048 0x4f600, 0x4f618, 2049 0x4f800, 0x4f814, 2050 0x50000, 0x50084, 2051 0x50090, 0x500cc, 2052 0x50400, 0x50400, 2053 0x50800, 0x50884, 2054 0x50890, 0x508cc, 2055 0x50c00, 0x50c00, 2056 0x51000, 0x5101c, 2057 0x51300, 0x51308, 2058 }; 2059 2060 static const unsigned int t5vf_reg_ranges[] = { 2061 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2062 VF_MPS_REG(A_MPS_VF_CTL), 2063 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2064 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2065 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2066 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2067 FW_T4VF_MBDATA_BASE_ADDR, 2068 FW_T4VF_MBDATA_BASE_ADDR + 2069 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2070 }; 2071 2072 static const unsigned int t6_reg_ranges[] = { 2073 0x1008, 0x101c, 2074 0x1024, 0x10a8, 2075 0x10b4, 0x10f8, 2076 0x1100, 0x1114, 2077 0x111c, 0x112c, 2078 0x1138, 0x113c, 2079 0x1144, 0x114c, 2080 0x1180, 0x1184, 2081 0x1190, 0x1194, 2082 0x11a0, 0x11a4, 2083 0x11b0, 0x11c4, 2084 0x11fc, 0x123c, 2085 0x1254, 0x1274, 2086 0x1280, 0x133c, 2087 0x1800, 0x18fc, 2088 0x3000, 0x302c, 2089 0x3060, 0x30b0, 2090 0x30b8, 0x30d8, 2091 0x30e0, 0x30fc, 2092 0x3140, 0x357c, 2093 0x35a8, 0x35cc, 2094 0x35ec, 0x35ec, 2095 0x3600, 0x5624, 2096 0x56cc, 0x56ec, 2097 0x56f4, 0x5720, 2098 0x5728, 0x575c, 2099 0x580c, 0x5814, 2100 0x5890, 0x589c, 2101 0x58a4, 0x58ac, 2102 0x58b8, 0x58bc, 2103 0x5940, 0x595c, 2104 0x5980, 0x598c, 2105 0x59b0, 0x59c8, 2106 0x59d0, 0x59dc, 2107 0x59fc, 0x5a18, 2108 0x5a60, 0x5a6c, 2109 0x5a80, 0x5a8c, 2110 0x5a94, 0x5a9c, 2111 0x5b94, 0x5bfc, 2112 0x5c10, 0x5e48, 2113 0x5e50, 0x5e94, 2114 0x5ea0, 0x5eb0, 2115 0x5ec0, 0x5ec0, 2116 0x5ec8, 0x5ed0, 2117 0x5ee0, 0x5ee0, 2118 0x5ef0, 0x5ef0, 2119 0x5f00, 0x5f00, 2120 0x6000, 0x6020, 2121 0x6028, 0x6040, 2122 0x6058, 0x609c, 2123 0x60a8, 0x619c, 2124 0x7700, 0x7798, 2125 0x77c0, 0x7880, 2126 0x78cc, 0x78fc, 2127 0x7b00, 0x7b58, 2128 0x7b60, 0x7b84, 2129 0x7b8c, 0x7c54, 2130 0x7d00, 0x7d38, 2131 0x7d40, 0x7d84, 2132 0x7d8c, 0x7ddc, 2133 0x7de4, 0x7e04, 2134 0x7e10, 0x7e1c, 2135 0x7e24, 0x7e38, 2136 0x7e40, 0x7e44, 2137 0x7e4c, 0x7e78, 2138 0x7e80, 0x7edc, 2139 0x7ee8, 0x7efc, 2140 0x8dc0, 0x8de0, 2141 0x8df8, 0x8e04, 2142 0x8e10, 0x8e84, 2143 0x8ea0, 0x8f88, 2144 0x8fb8, 0x9058, 2145 0x9060, 0x9060, 2146 0x9068, 0x90f8, 2147 0x9100, 0x9124, 2148 0x9400, 0x9470, 2149 0x9600, 0x9600, 2150 0x9608, 0x9638, 2151 0x9640, 0x9704, 2152 0x9710, 0x971c, 2153 0x9800, 0x9808, 2154 0x9810, 0x9864, 2155 0x9c00, 0x9c6c, 2156 0x9c80, 0x9cec, 2157 0x9d00, 0x9d6c, 2158 0x9d80, 0x9dec, 2159 0x9e00, 0x9e6c, 2160 0x9e80, 0x9eec, 2161 0x9f00, 0x9f6c, 2162 0x9f80, 0xa020, 2163 0xd000, 0xd03c, 2164 0xd100, 0xd118, 2165 0xd200, 0xd214, 2166 0xd220, 0xd234, 2167 0xd240, 0xd254, 2168 0xd260, 0xd274, 2169 0xd280, 0xd294, 2170 0xd2a0, 0xd2b4, 2171 0xd2c0, 0xd2d4, 2172 0xd2e0, 0xd2f4, 2173 0xd300, 0xd31c, 2174 0xdfc0, 0xdfe0, 2175 0xe000, 0xf008, 2176 0xf010, 0xf018, 2177 0xf020, 0xf028, 2178 0x11000, 0x11014, 2179 0x11048, 0x1106c, 2180 0x11074, 0x11088, 2181 0x11098, 0x11120, 2182 0x1112c, 0x1117c, 2183 0x11190, 0x112e0, 2184 0x11300, 0x1130c, 2185 0x12000, 0x1206c, 2186 0x19040, 0x1906c, 2187 0x19078, 0x19080, 2188 0x1908c, 0x190e8, 2189 0x190f0, 0x190f8, 2190 0x19100, 0x19110, 2191 0x19120, 0x19124, 2192 0x19150, 0x19194, 2193 0x1919c, 0x191b0, 2194 0x191d0, 0x191e8, 2195 0x19238, 0x19290, 2196 0x192a4, 0x192b0, 2197 0x19348, 0x1934c, 2198 0x193f8, 0x19418, 2199 0x19420, 0x19428, 2200 0x19430, 0x19444, 2201 0x1944c, 0x1946c, 2202 0x19474, 0x19474, 2203 0x19490, 0x194cc, 2204 0x194f0, 0x194f8, 2205 0x19c00, 0x19c48, 2206 0x19c50, 0x19c80, 2207 0x19c94, 0x19c98, 2208 0x19ca0, 0x19cbc, 2209 0x19ce4, 0x19ce4, 2210 0x19cf0, 0x19cf8, 2211 0x19d00, 0x19d28, 2212 0x19d50, 0x19d78, 2213 0x19d94, 0x19d98, 2214 0x19da0, 0x19de0, 2215 0x19df0, 0x19e10, 2216 0x19e50, 0x19e6c, 2217 0x19ea0, 0x19ebc, 2218 0x19ec4, 0x19ef4, 2219 0x19f04, 0x19f2c, 2220 0x19f34, 0x19f34, 2221 0x19f40, 0x19f50, 2222 0x19f90, 0x19fac, 2223 0x19fc4, 0x19fc8, 2224 0x19fd0, 0x19fe4, 2225 0x1a000, 0x1a004, 2226 0x1a010, 0x1a06c, 2227 0x1a0b0, 0x1a0e4, 2228 0x1a0ec, 0x1a0f8, 2229 0x1a100, 0x1a108, 2230 0x1a114, 0x1a130, 2231 0x1a138, 0x1a1c4, 2232 0x1a1fc, 0x1a1fc, 2233 0x1e008, 0x1e00c, 2234 0x1e040, 0x1e044, 2235 0x1e04c, 0x1e04c, 2236 0x1e284, 0x1e290, 2237 0x1e2c0, 0x1e2c0, 2238 0x1e2e0, 0x1e2e0, 2239 0x1e300, 0x1e384, 2240 0x1e3c0, 0x1e3c8, 2241 0x1e408, 0x1e40c, 2242 0x1e440, 0x1e444, 2243 0x1e44c, 0x1e44c, 2244 0x1e684, 0x1e690, 2245 0x1e6c0, 0x1e6c0, 2246 0x1e6e0, 0x1e6e0, 2247 0x1e700, 0x1e784, 2248 0x1e7c0, 0x1e7c8, 2249 0x1e808, 0x1e80c, 2250 0x1e840, 0x1e844, 2251 0x1e84c, 0x1e84c, 2252 0x1ea84, 0x1ea90, 2253 0x1eac0, 0x1eac0, 2254 0x1eae0, 0x1eae0, 2255 0x1eb00, 0x1eb84, 2256 0x1ebc0, 0x1ebc8, 2257 0x1ec08, 0x1ec0c, 2258 0x1ec40, 0x1ec44, 2259 0x1ec4c, 0x1ec4c, 2260 0x1ee84, 0x1ee90, 2261 0x1eec0, 0x1eec0, 2262 0x1eee0, 0x1eee0, 2263 0x1ef00, 0x1ef84, 2264 0x1efc0, 0x1efc8, 2265 0x1f008, 0x1f00c, 2266 0x1f040, 0x1f044, 2267 0x1f04c, 0x1f04c, 2268 0x1f284, 0x1f290, 2269 0x1f2c0, 0x1f2c0, 2270 0x1f2e0, 0x1f2e0, 2271 0x1f300, 0x1f384, 2272 0x1f3c0, 0x1f3c8, 2273 0x1f408, 0x1f40c, 2274 0x1f440, 0x1f444, 2275 0x1f44c, 0x1f44c, 2276 0x1f684, 0x1f690, 2277 0x1f6c0, 0x1f6c0, 2278 0x1f6e0, 0x1f6e0, 2279 0x1f700, 0x1f784, 2280 0x1f7c0, 0x1f7c8, 2281 0x1f808, 0x1f80c, 2282 0x1f840, 0x1f844, 2283 0x1f84c, 0x1f84c, 2284 0x1fa84, 0x1fa90, 2285 0x1fac0, 0x1fac0, 2286 0x1fae0, 0x1fae0, 2287 0x1fb00, 0x1fb84, 2288 0x1fbc0, 0x1fbc8, 2289 0x1fc08, 0x1fc0c, 2290 0x1fc40, 0x1fc44, 2291 0x1fc4c, 0x1fc4c, 2292 0x1fe84, 0x1fe90, 2293 0x1fec0, 0x1fec0, 2294 0x1fee0, 0x1fee0, 2295 0x1ff00, 0x1ff84, 2296 0x1ffc0, 0x1ffc8, 2297 0x30000, 0x30030, 2298 0x30100, 0x30168, 2299 0x30190, 0x301a0, 2300 0x301a8, 0x301b8, 2301 0x301c4, 0x301c8, 2302 0x301d0, 0x301d0, 2303 0x30200, 0x30320, 2304 0x30400, 0x304b4, 2305 0x304c0, 0x3052c, 2306 0x30540, 0x3061c, 2307 0x30800, 0x308a0, 2308 0x308c0, 0x30908, 2309 0x30910, 0x309b8, 2310 0x30a00, 0x30a04, 2311 0x30a0c, 0x30a14, 2312 0x30a1c, 0x30a2c, 2313 0x30a44, 0x30a50, 2314 0x30a74, 0x30a74, 2315 0x30a7c, 0x30afc, 2316 0x30b08, 0x30c24, 2317 0x30d00, 0x30d14, 2318 0x30d1c, 0x30d3c, 2319 0x30d44, 0x30d4c, 2320 0x30d54, 0x30d74, 2321 0x30d7c, 0x30d7c, 2322 0x30de0, 0x30de0, 2323 0x30e00, 0x30ed4, 2324 0x30f00, 0x30fa4, 2325 0x30fc0, 0x30fc4, 2326 0x31000, 0x31004, 2327 0x31080, 0x310fc, 2328 0x31208, 0x31220, 2329 0x3123c, 0x31254, 2330 0x31300, 0x31300, 2331 0x31308, 0x3131c, 2332 0x31338, 0x3133c, 2333 0x31380, 0x31380, 2334 0x31388, 0x313a8, 2335 0x313b4, 0x313b4, 2336 0x31400, 0x31420, 2337 0x31438, 0x3143c, 2338 0x31480, 0x31480, 2339 0x314a8, 0x314a8, 2340 0x314b0, 0x314b4, 2341 0x314c8, 0x314d4, 2342 0x31a40, 0x31a4c, 2343 0x31af0, 0x31b20, 2344 0x31b38, 0x31b3c, 2345 0x31b80, 0x31b80, 2346 0x31ba8, 0x31ba8, 2347 0x31bb0, 0x31bb4, 2348 0x31bc8, 0x31bd4, 2349 0x32140, 0x3218c, 2350 0x321f0, 0x321f4, 2351 0x32200, 0x32200, 2352 0x32218, 0x32218, 2353 0x32400, 0x32400, 2354 0x32408, 0x3241c, 2355 0x32618, 0x32620, 2356 0x32664, 0x32664, 2357 0x326a8, 0x326a8, 2358 0x326ec, 0x326ec, 2359 0x32a00, 0x32abc, 2360 0x32b00, 0x32b18, 2361 0x32b20, 0x32b38, 2362 0x32b40, 0x32b58, 2363 0x32b60, 0x32b78, 2364 0x32c00, 0x32c00, 2365 0x32c08, 0x32c3c, 2366 0x33000, 0x3302c, 2367 0x33034, 0x33050, 2368 0x33058, 0x33058, 2369 0x33060, 0x3308c, 2370 0x3309c, 0x330ac, 2371 0x330c0, 0x330c0, 2372 0x330c8, 0x330d0, 2373 0x330d8, 0x330e0, 2374 0x330ec, 0x3312c, 2375 0x33134, 0x33150, 2376 0x33158, 0x33158, 2377 0x33160, 0x3318c, 2378 0x3319c, 0x331ac, 2379 0x331c0, 0x331c0, 2380 0x331c8, 0x331d0, 2381 0x331d8, 0x331e0, 2382 0x331ec, 0x33290, 2383 0x33298, 0x332c4, 2384 0x332e4, 0x33390, 2385 0x33398, 0x333c4, 2386 0x333e4, 0x3342c, 2387 0x33434, 0x33450, 2388 0x33458, 0x33458, 2389 0x33460, 0x3348c, 2390 0x3349c, 0x334ac, 2391 0x334c0, 0x334c0, 2392 0x334c8, 0x334d0, 2393 0x334d8, 0x334e0, 2394 0x334ec, 0x3352c, 2395 0x33534, 0x33550, 2396 0x33558, 0x33558, 2397 0x33560, 0x3358c, 2398 0x3359c, 0x335ac, 2399 0x335c0, 0x335c0, 2400 0x335c8, 0x335d0, 2401 0x335d8, 0x335e0, 2402 0x335ec, 0x33690, 2403 0x33698, 0x336c4, 2404 0x336e4, 0x33790, 2405 0x33798, 0x337c4, 2406 0x337e4, 0x337fc, 2407 0x33814, 0x33814, 2408 0x33854, 0x33868, 2409 0x33880, 0x3388c, 2410 0x338c0, 0x338d0, 2411 0x338e8, 0x338ec, 2412 0x33900, 0x3392c, 2413 0x33934, 0x33950, 2414 0x33958, 0x33958, 2415 0x33960, 0x3398c, 2416 0x3399c, 0x339ac, 2417 0x339c0, 0x339c0, 2418 0x339c8, 0x339d0, 2419 0x339d8, 0x339e0, 2420 0x339ec, 0x33a90, 2421 0x33a98, 0x33ac4, 2422 0x33ae4, 0x33b10, 2423 0x33b24, 0x33b28, 2424 0x33b38, 0x33b50, 2425 0x33bf0, 0x33c10, 2426 0x33c24, 0x33c28, 2427 0x33c38, 0x33c50, 2428 0x33cf0, 0x33cfc, 2429 0x34000, 0x34030, 2430 0x34100, 0x34168, 2431 0x34190, 0x341a0, 2432 0x341a8, 0x341b8, 2433 0x341c4, 0x341c8, 2434 0x341d0, 0x341d0, 2435 0x34200, 0x34320, 2436 0x34400, 0x344b4, 2437 0x344c0, 0x3452c, 2438 0x34540, 0x3461c, 2439 0x34800, 0x348a0, 2440 0x348c0, 0x34908, 2441 0x34910, 0x349b8, 2442 0x34a00, 0x34a04, 2443 0x34a0c, 0x34a14, 2444 0x34a1c, 0x34a2c, 2445 0x34a44, 0x34a50, 2446 0x34a74, 0x34a74, 2447 0x34a7c, 0x34afc, 2448 0x34b08, 0x34c24, 2449 0x34d00, 0x34d14, 2450 0x34d1c, 0x34d3c, 2451 0x34d44, 0x34d4c, 2452 0x34d54, 0x34d74, 2453 0x34d7c, 0x34d7c, 2454 0x34de0, 0x34de0, 2455 0x34e00, 0x34ed4, 2456 0x34f00, 0x34fa4, 2457 0x34fc0, 0x34fc4, 2458 0x35000, 0x35004, 2459 0x35080, 0x350fc, 2460 0x35208, 0x35220, 2461 0x3523c, 0x35254, 2462 0x35300, 0x35300, 2463 0x35308, 0x3531c, 2464 0x35338, 0x3533c, 2465 0x35380, 0x35380, 2466 0x35388, 0x353a8, 2467 0x353b4, 0x353b4, 2468 0x35400, 0x35420, 2469 0x35438, 0x3543c, 2470 0x35480, 0x35480, 2471 0x354a8, 0x354a8, 2472 0x354b0, 0x354b4, 2473 0x354c8, 0x354d4, 2474 0x35a40, 0x35a4c, 2475 0x35af0, 0x35b20, 2476 0x35b38, 0x35b3c, 2477 0x35b80, 0x35b80, 2478 0x35ba8, 0x35ba8, 2479 0x35bb0, 0x35bb4, 2480 0x35bc8, 0x35bd4, 2481 0x36140, 0x3618c, 2482 0x361f0, 0x361f4, 2483 0x36200, 0x36200, 2484 0x36218, 0x36218, 2485 0x36400, 0x36400, 2486 0x36408, 0x3641c, 2487 0x36618, 0x36620, 2488 0x36664, 0x36664, 2489 0x366a8, 0x366a8, 2490 0x366ec, 0x366ec, 2491 0x36a00, 0x36abc, 2492 0x36b00, 0x36b18, 2493 0x36b20, 0x36b38, 2494 0x36b40, 0x36b58, 2495 0x36b60, 0x36b78, 2496 0x36c00, 0x36c00, 2497 0x36c08, 0x36c3c, 2498 0x37000, 0x3702c, 2499 0x37034, 0x37050, 2500 0x37058, 0x37058, 2501 0x37060, 0x3708c, 2502 0x3709c, 0x370ac, 2503 0x370c0, 0x370c0, 2504 0x370c8, 0x370d0, 2505 0x370d8, 0x370e0, 2506 0x370ec, 0x3712c, 2507 0x37134, 0x37150, 2508 0x37158, 0x37158, 2509 0x37160, 0x3718c, 2510 0x3719c, 0x371ac, 2511 0x371c0, 0x371c0, 2512 0x371c8, 0x371d0, 2513 0x371d8, 0x371e0, 2514 0x371ec, 0x37290, 2515 0x37298, 0x372c4, 2516 0x372e4, 0x37390, 2517 0x37398, 0x373c4, 2518 0x373e4, 0x3742c, 2519 0x37434, 0x37450, 2520 0x37458, 0x37458, 2521 0x37460, 0x3748c, 2522 0x3749c, 0x374ac, 2523 0x374c0, 0x374c0, 2524 0x374c8, 0x374d0, 2525 0x374d8, 0x374e0, 2526 0x374ec, 0x3752c, 2527 0x37534, 0x37550, 2528 0x37558, 0x37558, 2529 0x37560, 0x3758c, 2530 0x3759c, 0x375ac, 2531 0x375c0, 0x375c0, 2532 0x375c8, 0x375d0, 2533 0x375d8, 0x375e0, 2534 0x375ec, 0x37690, 2535 0x37698, 0x376c4, 2536 0x376e4, 0x37790, 2537 0x37798, 0x377c4, 2538 0x377e4, 0x377fc, 2539 0x37814, 0x37814, 2540 0x37854, 0x37868, 2541 0x37880, 0x3788c, 2542 0x378c0, 0x378d0, 2543 0x378e8, 0x378ec, 2544 0x37900, 0x3792c, 2545 0x37934, 0x37950, 2546 0x37958, 0x37958, 2547 0x37960, 0x3798c, 2548 0x3799c, 0x379ac, 2549 0x379c0, 0x379c0, 2550 0x379c8, 0x379d0, 2551 0x379d8, 0x379e0, 2552 0x379ec, 0x37a90, 2553 0x37a98, 0x37ac4, 2554 0x37ae4, 0x37b10, 2555 0x37b24, 0x37b28, 2556 0x37b38, 0x37b50, 2557 0x37bf0, 0x37c10, 2558 0x37c24, 0x37c28, 2559 0x37c38, 0x37c50, 2560 0x37cf0, 0x37cfc, 2561 0x40040, 0x40040, 2562 0x40080, 0x40084, 2563 0x40100, 0x40100, 2564 0x40140, 0x401bc, 2565 0x40200, 0x40214, 2566 0x40228, 0x40228, 2567 0x40240, 0x40258, 2568 0x40280, 0x40280, 2569 0x40304, 0x40304, 2570 0x40330, 0x4033c, 2571 0x41304, 0x413c8, 2572 0x413d0, 0x413dc, 2573 0x413f0, 0x413f0, 2574 0x41400, 0x4140c, 2575 0x41414, 0x4141c, 2576 0x41480, 0x414d0, 2577 0x44000, 0x4407c, 2578 0x440c0, 0x441ac, 2579 0x441b4, 0x4427c, 2580 0x442c0, 0x443ac, 2581 0x443b4, 0x4447c, 2582 0x444c0, 0x445ac, 2583 0x445b4, 0x4467c, 2584 0x446c0, 0x447ac, 2585 0x447b4, 0x4487c, 2586 0x448c0, 0x449ac, 2587 0x449b4, 0x44a7c, 2588 0x44ac0, 0x44bac, 2589 0x44bb4, 0x44c7c, 2590 0x44cc0, 0x44dac, 2591 0x44db4, 0x44e7c, 2592 0x44ec0, 0x44fac, 2593 0x44fb4, 0x4507c, 2594 0x450c0, 0x451ac, 2595 0x451b4, 0x451fc, 2596 0x45800, 0x45804, 2597 0x45810, 0x45830, 2598 0x45840, 0x45860, 2599 0x45868, 0x45868, 2600 0x45880, 0x45884, 2601 0x458a0, 0x458b0, 2602 0x45a00, 0x45a04, 2603 0x45a10, 0x45a30, 2604 0x45a40, 0x45a60, 2605 0x45a68, 0x45a68, 2606 0x45a80, 0x45a84, 2607 0x45aa0, 0x45ab0, 2608 0x460c0, 0x460e4, 2609 0x47000, 0x4703c, 2610 0x47044, 0x4708c, 2611 0x47200, 0x47250, 2612 0x47400, 0x47408, 2613 0x47414, 0x47420, 2614 0x47600, 0x47618, 2615 0x47800, 0x47814, 2616 0x47820, 0x4782c, 2617 0x50000, 0x50084, 2618 0x50090, 0x500cc, 2619 0x50300, 0x50384, 2620 0x50400, 0x50400, 2621 0x50800, 0x50884, 2622 0x50890, 0x508cc, 2623 0x50b00, 0x50b84, 2624 0x50c00, 0x50c00, 2625 0x51000, 0x51020, 2626 0x51028, 0x510b0, 2627 0x51300, 0x51324, 2628 }; 2629 2630 static const unsigned int t6vf_reg_ranges[] = { 2631 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2632 VF_MPS_REG(A_MPS_VF_CTL), 2633 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2634 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2635 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2636 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2637 FW_T6VF_MBDATA_BASE_ADDR, 2638 FW_T6VF_MBDATA_BASE_ADDR + 2639 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2640 }; 2641 2642 u32 *buf_end = (u32 *)(buf + buf_size); 2643 const unsigned int *reg_ranges; 2644 int reg_ranges_size, range; 2645 unsigned int chip_version = chip_id(adap); 2646 2647 /* 2648 * Select the right set of register ranges to dump depending on the 2649 * adapter chip type. 2650 */ 2651 switch (chip_version) { 2652 case CHELSIO_T4: 2653 if (adap->flags & IS_VF) { 2654 reg_ranges = t4vf_reg_ranges; 2655 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2656 } else { 2657 reg_ranges = t4_reg_ranges; 2658 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2659 } 2660 break; 2661 2662 case CHELSIO_T5: 2663 if (adap->flags & IS_VF) { 2664 reg_ranges = t5vf_reg_ranges; 2665 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2666 } else { 2667 reg_ranges = t5_reg_ranges; 2668 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2669 } 2670 break; 2671 2672 case CHELSIO_T6: 2673 if (adap->flags & IS_VF) { 2674 reg_ranges = t6vf_reg_ranges; 2675 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2676 } else { 2677 reg_ranges = t6_reg_ranges; 2678 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2679 } 2680 break; 2681 2682 default: 2683 CH_ERR(adap, 2684 "Unsupported chip version %d\n", chip_version); 2685 return; 2686 } 2687 2688 /* 2689 * Clear the register buffer and insert the appropriate register 2690 * values selected by the above register ranges. 2691 */ 2692 memset(buf, 0, buf_size); 2693 for (range = 0; range < reg_ranges_size; range += 2) { 2694 unsigned int reg = reg_ranges[range]; 2695 unsigned int last_reg = reg_ranges[range + 1]; 2696 u32 *bufp = (u32 *)(buf + reg); 2697 2698 /* 2699 * Iterate across the register range filling in the register 2700 * buffer but don't write past the end of the register buffer. 2701 */ 2702 while (reg <= last_reg && bufp < buf_end) { 2703 *bufp++ = t4_read_reg(adap, reg); 2704 reg += sizeof(u32); 2705 } 2706 } 2707 } 2708 2709 /* 2710 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2711 * header followed by one or more VPD-R sections, each with its own header. 2712 */ 2713 struct t4_vpd_hdr { 2714 u8 id_tag; 2715 u8 id_len[2]; 2716 u8 id_data[ID_LEN]; 2717 }; 2718 2719 struct t4_vpdr_hdr { 2720 u8 vpdr_tag; 2721 u8 vpdr_len[2]; 2722 }; 2723 2724 /* 2725 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2726 */ 2727 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2728 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2729 2730 #define EEPROM_STAT_ADDR 0x7bfc 2731 #define VPD_SIZE 0x800 2732 #define VPD_BASE 0x400 2733 #define VPD_BASE_OLD 0 2734 #define VPD_LEN 1024 2735 #define VPD_INFO_FLD_HDR_SIZE 3 2736 #define CHELSIO_VPD_UNIQUE_ID 0x82 2737 2738 /* 2739 * Small utility function to wait till any outstanding VPD Access is complete. 2740 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2741 * VPD Access in flight. This allows us to handle the problem of having a 2742 * previous VPD Access time out and prevent an attempt to inject a new VPD 2743 * Request before any in-flight VPD reguest has completed. 2744 */ 2745 static int t4_seeprom_wait(struct adapter *adapter) 2746 { 2747 unsigned int base = adapter->params.pci.vpd_cap_addr; 2748 int max_poll; 2749 2750 /* 2751 * If no VPD Access is in flight, we can just return success right 2752 * away. 2753 */ 2754 if (!adapter->vpd_busy) 2755 return 0; 2756 2757 /* 2758 * Poll the VPD Capability Address/Flag register waiting for it 2759 * to indicate that the operation is complete. 2760 */ 2761 max_poll = EEPROM_MAX_POLL; 2762 do { 2763 u16 val; 2764 2765 udelay(EEPROM_DELAY); 2766 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2767 2768 /* 2769 * If the operation is complete, mark the VPD as no longer 2770 * busy and return success. 2771 */ 2772 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2773 adapter->vpd_busy = 0; 2774 return 0; 2775 } 2776 } while (--max_poll); 2777 2778 /* 2779 * Failure! Note that we leave the VPD Busy status set in order to 2780 * avoid pushing a new VPD Access request into the VPD Capability till 2781 * the current operation eventually succeeds. It's a bug to issue a 2782 * new request when an existing request is in flight and will result 2783 * in corrupt hardware state. 2784 */ 2785 return -ETIMEDOUT; 2786 } 2787 2788 /** 2789 * t4_seeprom_read - read a serial EEPROM location 2790 * @adapter: adapter to read 2791 * @addr: EEPROM virtual address 2792 * @data: where to store the read data 2793 * 2794 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2795 * VPD capability. Note that this function must be called with a virtual 2796 * address. 2797 */ 2798 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2799 { 2800 unsigned int base = adapter->params.pci.vpd_cap_addr; 2801 int ret; 2802 2803 /* 2804 * VPD Accesses must alway be 4-byte aligned! 2805 */ 2806 if (addr >= EEPROMVSIZE || (addr & 3)) 2807 return -EINVAL; 2808 2809 /* 2810 * Wait for any previous operation which may still be in flight to 2811 * complete. 2812 */ 2813 ret = t4_seeprom_wait(adapter); 2814 if (ret) { 2815 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2816 return ret; 2817 } 2818 2819 /* 2820 * Issue our new VPD Read request, mark the VPD as being busy and wait 2821 * for our request to complete. If it doesn't complete, note the 2822 * error and return it to our caller. Note that we do not reset the 2823 * VPD Busy status! 2824 */ 2825 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2826 adapter->vpd_busy = 1; 2827 adapter->vpd_flag = PCI_VPD_ADDR_F; 2828 ret = t4_seeprom_wait(adapter); 2829 if (ret) { 2830 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2831 return ret; 2832 } 2833 2834 /* 2835 * Grab the returned data, swizzle it into our endianness and 2836 * return success. 2837 */ 2838 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2839 *data = le32_to_cpu(*data); 2840 return 0; 2841 } 2842 2843 /** 2844 * t4_seeprom_write - write a serial EEPROM location 2845 * @adapter: adapter to write 2846 * @addr: virtual EEPROM address 2847 * @data: value to write 2848 * 2849 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2850 * VPD capability. Note that this function must be called with a virtual 2851 * address. 2852 */ 2853 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2854 { 2855 unsigned int base = adapter->params.pci.vpd_cap_addr; 2856 int ret; 2857 u32 stats_reg; 2858 int max_poll; 2859 2860 /* 2861 * VPD Accesses must alway be 4-byte aligned! 2862 */ 2863 if (addr >= EEPROMVSIZE || (addr & 3)) 2864 return -EINVAL; 2865 2866 /* 2867 * Wait for any previous operation which may still be in flight to 2868 * complete. 2869 */ 2870 ret = t4_seeprom_wait(adapter); 2871 if (ret) { 2872 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2873 return ret; 2874 } 2875 2876 /* 2877 * Issue our new VPD Read request, mark the VPD as being busy and wait 2878 * for our request to complete. If it doesn't complete, note the 2879 * error and return it to our caller. Note that we do not reset the 2880 * VPD Busy status! 2881 */ 2882 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2883 cpu_to_le32(data)); 2884 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2885 (u16)addr | PCI_VPD_ADDR_F); 2886 adapter->vpd_busy = 1; 2887 adapter->vpd_flag = 0; 2888 ret = t4_seeprom_wait(adapter); 2889 if (ret) { 2890 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2891 return ret; 2892 } 2893 2894 /* 2895 * Reset PCI_VPD_DATA register after a transaction and wait for our 2896 * request to complete. If it doesn't complete, return error. 2897 */ 2898 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2899 max_poll = EEPROM_MAX_POLL; 2900 do { 2901 udelay(EEPROM_DELAY); 2902 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2903 } while ((stats_reg & 0x1) && --max_poll); 2904 if (!max_poll) 2905 return -ETIMEDOUT; 2906 2907 /* Return success! */ 2908 return 0; 2909 } 2910 2911 /** 2912 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2913 * @phys_addr: the physical EEPROM address 2914 * @fn: the PCI function number 2915 * @sz: size of function-specific area 2916 * 2917 * Translate a physical EEPROM address to virtual. The first 1K is 2918 * accessed through virtual addresses starting at 31K, the rest is 2919 * accessed through virtual addresses starting at 0. 2920 * 2921 * The mapping is as follows: 2922 * [0..1K) -> [31K..32K) 2923 * [1K..1K+A) -> [ES-A..ES) 2924 * [1K+A..ES) -> [0..ES-A-1K) 2925 * 2926 * where A = @fn * @sz, and ES = EEPROM size. 2927 */ 2928 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2929 { 2930 fn *= sz; 2931 if (phys_addr < 1024) 2932 return phys_addr + (31 << 10); 2933 if (phys_addr < 1024 + fn) 2934 return EEPROMSIZE - fn + phys_addr - 1024; 2935 if (phys_addr < EEPROMSIZE) 2936 return phys_addr - 1024 - fn; 2937 return -EINVAL; 2938 } 2939 2940 /** 2941 * t4_seeprom_wp - enable/disable EEPROM write protection 2942 * @adapter: the adapter 2943 * @enable: whether to enable or disable write protection 2944 * 2945 * Enables or disables write protection on the serial EEPROM. 2946 */ 2947 int t4_seeprom_wp(struct adapter *adapter, int enable) 2948 { 2949 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2950 } 2951 2952 /** 2953 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2954 * @vpd: Pointer to buffered vpd data structure 2955 * @kw: The keyword to search for 2956 * @region: VPD region to search (starting from 0) 2957 * 2958 * Returns the value of the information field keyword or 2959 * -ENOENT otherwise. 2960 */ 2961 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2962 { 2963 int i, tag; 2964 unsigned int offset, len; 2965 const struct t4_vpdr_hdr *vpdr; 2966 2967 offset = sizeof(struct t4_vpd_hdr); 2968 vpdr = (const void *)(vpd + offset); 2969 tag = vpdr->vpdr_tag; 2970 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2971 while (region--) { 2972 offset += sizeof(struct t4_vpdr_hdr) + len; 2973 vpdr = (const void *)(vpd + offset); 2974 if (++tag != vpdr->vpdr_tag) 2975 return -ENOENT; 2976 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2977 } 2978 offset += sizeof(struct t4_vpdr_hdr); 2979 2980 if (offset + len > VPD_LEN) { 2981 return -ENOENT; 2982 } 2983 2984 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2985 if (memcmp(vpd + i , kw , 2) == 0){ 2986 i += VPD_INFO_FLD_HDR_SIZE; 2987 return i; 2988 } 2989 2990 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2991 } 2992 2993 return -ENOENT; 2994 } 2995 2996 2997 /** 2998 * get_vpd_params - read VPD parameters from VPD EEPROM 2999 * @adapter: adapter to read 3000 * @p: where to store the parameters 3001 * @vpd: caller provided temporary space to read the VPD into 3002 * 3003 * Reads card parameters stored in VPD EEPROM. 3004 */ 3005 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3006 uint16_t device_id, u32 *buf) 3007 { 3008 int i, ret, addr; 3009 int ec, sn, pn, na, md; 3010 u8 csum; 3011 const u8 *vpd = (const u8 *)buf; 3012 3013 /* 3014 * Card information normally starts at VPD_BASE but early cards had 3015 * it at 0. 3016 */ 3017 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3018 if (ret) 3019 return (ret); 3020 3021 /* 3022 * The VPD shall have a unique identifier specified by the PCI SIG. 3023 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3024 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3025 * is expected to automatically put this entry at the 3026 * beginning of the VPD. 3027 */ 3028 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3029 3030 for (i = 0; i < VPD_LEN; i += 4) { 3031 ret = t4_seeprom_read(adapter, addr + i, buf++); 3032 if (ret) 3033 return ret; 3034 } 3035 3036 #define FIND_VPD_KW(var,name) do { \ 3037 var = get_vpd_keyword_val(vpd, name, 0); \ 3038 if (var < 0) { \ 3039 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3040 return -EINVAL; \ 3041 } \ 3042 } while (0) 3043 3044 FIND_VPD_KW(i, "RV"); 3045 for (csum = 0; i >= 0; i--) 3046 csum += vpd[i]; 3047 3048 if (csum) { 3049 CH_ERR(adapter, 3050 "corrupted VPD EEPROM, actual csum %u\n", csum); 3051 return -EINVAL; 3052 } 3053 3054 FIND_VPD_KW(ec, "EC"); 3055 FIND_VPD_KW(sn, "SN"); 3056 FIND_VPD_KW(pn, "PN"); 3057 FIND_VPD_KW(na, "NA"); 3058 #undef FIND_VPD_KW 3059 3060 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3061 strstrip(p->id); 3062 memcpy(p->ec, vpd + ec, EC_LEN); 3063 strstrip(p->ec); 3064 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3065 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3066 strstrip(p->sn); 3067 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3068 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3069 strstrip((char *)p->pn); 3070 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3071 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3072 strstrip((char *)p->na); 3073 3074 if (device_id & 0x80) 3075 return 0; /* Custom card */ 3076 3077 md = get_vpd_keyword_val(vpd, "VF", 1); 3078 if (md < 0) { 3079 snprintf(p->md, sizeof(p->md), "unknown"); 3080 } else { 3081 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3082 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3083 strstrip((char *)p->md); 3084 } 3085 3086 return 0; 3087 } 3088 3089 /* serial flash and firmware constants and flash config file constants */ 3090 enum { 3091 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3092 3093 /* flash command opcodes */ 3094 SF_PROG_PAGE = 2, /* program 256B page */ 3095 SF_WR_DISABLE = 4, /* disable writes */ 3096 SF_RD_STATUS = 5, /* read status register */ 3097 SF_WR_ENABLE = 6, /* enable writes */ 3098 SF_RD_DATA_FAST = 0xb, /* read flash */ 3099 SF_RD_ID = 0x9f, /* read ID */ 3100 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3101 }; 3102 3103 /** 3104 * sf1_read - read data from the serial flash 3105 * @adapter: the adapter 3106 * @byte_cnt: number of bytes to read 3107 * @cont: whether another operation will be chained 3108 * @lock: whether to lock SF for PL access only 3109 * @valp: where to store the read data 3110 * 3111 * Reads up to 4 bytes of data from the serial flash. The location of 3112 * the read needs to be specified prior to calling this by issuing the 3113 * appropriate commands to the serial flash. 3114 */ 3115 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3116 int lock, u32 *valp) 3117 { 3118 int ret; 3119 3120 if (!byte_cnt || byte_cnt > 4) 3121 return -EINVAL; 3122 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3123 return -EBUSY; 3124 t4_write_reg(adapter, A_SF_OP, 3125 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3126 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3127 if (!ret) 3128 *valp = t4_read_reg(adapter, A_SF_DATA); 3129 return ret; 3130 } 3131 3132 /** 3133 * sf1_write - write data to the serial flash 3134 * @adapter: the adapter 3135 * @byte_cnt: number of bytes to write 3136 * @cont: whether another operation will be chained 3137 * @lock: whether to lock SF for PL access only 3138 * @val: value to write 3139 * 3140 * Writes up to 4 bytes of data to the serial flash. The location of 3141 * the write needs to be specified prior to calling this by issuing the 3142 * appropriate commands to the serial flash. 3143 */ 3144 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3145 int lock, u32 val) 3146 { 3147 if (!byte_cnt || byte_cnt > 4) 3148 return -EINVAL; 3149 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3150 return -EBUSY; 3151 t4_write_reg(adapter, A_SF_DATA, val); 3152 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3153 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3154 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3155 } 3156 3157 /** 3158 * flash_wait_op - wait for a flash operation to complete 3159 * @adapter: the adapter 3160 * @attempts: max number of polls of the status register 3161 * @delay: delay between polls in ms 3162 * 3163 * Wait for a flash operation to complete by polling the status register. 3164 */ 3165 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3166 { 3167 int ret; 3168 u32 status; 3169 3170 while (1) { 3171 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3172 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3173 return ret; 3174 if (!(status & 1)) 3175 return 0; 3176 if (--attempts == 0) 3177 return -EAGAIN; 3178 if (delay) 3179 msleep(delay); 3180 } 3181 } 3182 3183 /** 3184 * t4_read_flash - read words from serial flash 3185 * @adapter: the adapter 3186 * @addr: the start address for the read 3187 * @nwords: how many 32-bit words to read 3188 * @data: where to store the read data 3189 * @byte_oriented: whether to store data as bytes or as words 3190 * 3191 * Read the specified number of 32-bit words from the serial flash. 3192 * If @byte_oriented is set the read data is stored as a byte array 3193 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3194 * natural endianness. 3195 */ 3196 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3197 unsigned int nwords, u32 *data, int byte_oriented) 3198 { 3199 int ret; 3200 3201 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3202 return -EINVAL; 3203 3204 addr = swab32(addr) | SF_RD_DATA_FAST; 3205 3206 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3207 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3208 return ret; 3209 3210 for ( ; nwords; nwords--, data++) { 3211 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3212 if (nwords == 1) 3213 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3214 if (ret) 3215 return ret; 3216 if (byte_oriented) 3217 *data = (__force __u32)(cpu_to_be32(*data)); 3218 } 3219 return 0; 3220 } 3221 3222 /** 3223 * t4_write_flash - write up to a page of data to the serial flash 3224 * @adapter: the adapter 3225 * @addr: the start address to write 3226 * @n: length of data to write in bytes 3227 * @data: the data to write 3228 * @byte_oriented: whether to store data as bytes or as words 3229 * 3230 * Writes up to a page of data (256 bytes) to the serial flash starting 3231 * at the given address. All the data must be written to the same page. 3232 * If @byte_oriented is set the write data is stored as byte stream 3233 * (i.e. matches what on disk), otherwise in big-endian. 3234 */ 3235 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3236 unsigned int n, const u8 *data, int byte_oriented) 3237 { 3238 int ret; 3239 u32 buf[SF_PAGE_SIZE / 4]; 3240 unsigned int i, c, left, val, offset = addr & 0xff; 3241 3242 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3243 return -EINVAL; 3244 3245 val = swab32(addr) | SF_PROG_PAGE; 3246 3247 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3248 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3249 goto unlock; 3250 3251 for (left = n; left; left -= c) { 3252 c = min(left, 4U); 3253 for (val = 0, i = 0; i < c; ++i) 3254 val = (val << 8) + *data++; 3255 3256 if (!byte_oriented) 3257 val = cpu_to_be32(val); 3258 3259 ret = sf1_write(adapter, c, c != left, 1, val); 3260 if (ret) 3261 goto unlock; 3262 } 3263 ret = flash_wait_op(adapter, 8, 1); 3264 if (ret) 3265 goto unlock; 3266 3267 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3268 3269 /* Read the page to verify the write succeeded */ 3270 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3271 byte_oriented); 3272 if (ret) 3273 return ret; 3274 3275 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3276 CH_ERR(adapter, 3277 "failed to correctly write the flash page at %#x\n", 3278 addr); 3279 return -EIO; 3280 } 3281 return 0; 3282 3283 unlock: 3284 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3285 return ret; 3286 } 3287 3288 /** 3289 * t4_get_fw_version - read the firmware version 3290 * @adapter: the adapter 3291 * @vers: where to place the version 3292 * 3293 * Reads the FW version from flash. 3294 */ 3295 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3296 { 3297 return t4_read_flash(adapter, FLASH_FW_START + 3298 offsetof(struct fw_hdr, fw_ver), 1, 3299 vers, 0); 3300 } 3301 3302 /** 3303 * t4_get_fw_hdr - read the firmware header 3304 * @adapter: the adapter 3305 * @hdr: where to place the version 3306 * 3307 * Reads the FW header from flash into caller provided buffer. 3308 */ 3309 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3310 { 3311 return t4_read_flash(adapter, FLASH_FW_START, 3312 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3313 } 3314 3315 /** 3316 * t4_get_bs_version - read the firmware bootstrap version 3317 * @adapter: the adapter 3318 * @vers: where to place the version 3319 * 3320 * Reads the FW Bootstrap version from flash. 3321 */ 3322 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3323 { 3324 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3325 offsetof(struct fw_hdr, fw_ver), 1, 3326 vers, 0); 3327 } 3328 3329 /** 3330 * t4_get_tp_version - read the TP microcode version 3331 * @adapter: the adapter 3332 * @vers: where to place the version 3333 * 3334 * Reads the TP microcode version from flash. 3335 */ 3336 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3337 { 3338 return t4_read_flash(adapter, FLASH_FW_START + 3339 offsetof(struct fw_hdr, tp_microcode_ver), 3340 1, vers, 0); 3341 } 3342 3343 /** 3344 * t4_get_exprom_version - return the Expansion ROM version (if any) 3345 * @adapter: the adapter 3346 * @vers: where to place the version 3347 * 3348 * Reads the Expansion ROM header from FLASH and returns the version 3349 * number (if present) through the @vers return value pointer. We return 3350 * this in the Firmware Version Format since it's convenient. Return 3351 * 0 on success, -ENOENT if no Expansion ROM is present. 3352 */ 3353 int t4_get_exprom_version(struct adapter *adapter, u32 *vers) 3354 { 3355 struct exprom_header { 3356 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3357 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3358 } *hdr; 3359 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3360 sizeof(u32))]; 3361 int ret; 3362 3363 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START, 3364 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3365 0); 3366 if (ret) 3367 return ret; 3368 3369 hdr = (struct exprom_header *)exprom_header_buf; 3370 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3371 return -ENOENT; 3372 3373 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3374 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3375 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3376 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3377 return 0; 3378 } 3379 3380 /** 3381 * t4_get_scfg_version - return the Serial Configuration version 3382 * @adapter: the adapter 3383 * @vers: where to place the version 3384 * 3385 * Reads the Serial Configuration Version via the Firmware interface 3386 * (thus this can only be called once we're ready to issue Firmware 3387 * commands). The format of the Serial Configuration version is 3388 * adapter specific. Returns 0 on success, an error on failure. 3389 * 3390 * Note that early versions of the Firmware didn't include the ability 3391 * to retrieve the Serial Configuration version, so we zero-out the 3392 * return-value parameter in that case to avoid leaving it with 3393 * garbage in it. 3394 * 3395 * Also note that the Firmware will return its cached copy of the Serial 3396 * Initialization Revision ID, not the actual Revision ID as written in 3397 * the Serial EEPROM. This is only an issue if a new VPD has been written 3398 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3399 * it's best to defer calling this routine till after a FW_RESET_CMD has 3400 * been issued if the Host Driver will be performing a full adapter 3401 * initialization. 3402 */ 3403 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3404 { 3405 u32 scfgrev_param; 3406 int ret; 3407 3408 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3409 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3410 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3411 1, &scfgrev_param, vers); 3412 if (ret) 3413 *vers = 0; 3414 return ret; 3415 } 3416 3417 /** 3418 * t4_get_vpd_version - return the VPD version 3419 * @adapter: the adapter 3420 * @vers: where to place the version 3421 * 3422 * Reads the VPD via the Firmware interface (thus this can only be called 3423 * once we're ready to issue Firmware commands). The format of the 3424 * VPD version is adapter specific. Returns 0 on success, an error on 3425 * failure. 3426 * 3427 * Note that early versions of the Firmware didn't include the ability 3428 * to retrieve the VPD version, so we zero-out the return-value parameter 3429 * in that case to avoid leaving it with garbage in it. 3430 * 3431 * Also note that the Firmware will return its cached copy of the VPD 3432 * Revision ID, not the actual Revision ID as written in the Serial 3433 * EEPROM. This is only an issue if a new VPD has been written and the 3434 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3435 * to defer calling this routine till after a FW_RESET_CMD has been issued 3436 * if the Host Driver will be performing a full adapter initialization. 3437 */ 3438 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3439 { 3440 u32 vpdrev_param; 3441 int ret; 3442 3443 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3444 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3445 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3446 1, &vpdrev_param, vers); 3447 if (ret) 3448 *vers = 0; 3449 return ret; 3450 } 3451 3452 /** 3453 * t4_get_version_info - extract various chip/firmware version information 3454 * @adapter: the adapter 3455 * 3456 * Reads various chip/firmware version numbers and stores them into the 3457 * adapter Adapter Parameters structure. If any of the efforts fails 3458 * the first failure will be returned, but all of the version numbers 3459 * will be read. 3460 */ 3461 int t4_get_version_info(struct adapter *adapter) 3462 { 3463 int ret = 0; 3464 3465 #define FIRST_RET(__getvinfo) \ 3466 do { \ 3467 int __ret = __getvinfo; \ 3468 if (__ret && !ret) \ 3469 ret = __ret; \ 3470 } while (0) 3471 3472 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3473 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3474 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3475 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3476 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3477 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3478 3479 #undef FIRST_RET 3480 3481 return ret; 3482 } 3483 3484 /** 3485 * t4_flash_erase_sectors - erase a range of flash sectors 3486 * @adapter: the adapter 3487 * @start: the first sector to erase 3488 * @end: the last sector to erase 3489 * 3490 * Erases the sectors in the given inclusive range. 3491 */ 3492 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3493 { 3494 int ret = 0; 3495 3496 if (end >= adapter->params.sf_nsec) 3497 return -EINVAL; 3498 3499 while (start <= end) { 3500 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3501 (ret = sf1_write(adapter, 4, 0, 1, 3502 SF_ERASE_SECTOR | (start << 8))) != 0 || 3503 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3504 CH_ERR(adapter, 3505 "erase of flash sector %d failed, error %d\n", 3506 start, ret); 3507 break; 3508 } 3509 start++; 3510 } 3511 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3512 return ret; 3513 } 3514 3515 /** 3516 * t4_flash_cfg_addr - return the address of the flash configuration file 3517 * @adapter: the adapter 3518 * 3519 * Return the address within the flash where the Firmware Configuration 3520 * File is stored, or an error if the device FLASH is too small to contain 3521 * a Firmware Configuration File. 3522 */ 3523 int t4_flash_cfg_addr(struct adapter *adapter) 3524 { 3525 /* 3526 * If the device FLASH isn't large enough to hold a Firmware 3527 * Configuration File, return an error. 3528 */ 3529 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3530 return -ENOSPC; 3531 3532 return FLASH_CFG_START; 3533 } 3534 3535 /* 3536 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3537 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3538 * and emit an error message for mismatched firmware to save our caller the 3539 * effort ... 3540 */ 3541 static int t4_fw_matches_chip(struct adapter *adap, 3542 const struct fw_hdr *hdr) 3543 { 3544 /* 3545 * The expression below will return FALSE for any unsupported adapter 3546 * which will keep us "honest" in the future ... 3547 */ 3548 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3549 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3550 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3551 return 1; 3552 3553 CH_ERR(adap, 3554 "FW image (%d) is not suitable for this adapter (%d)\n", 3555 hdr->chip, chip_id(adap)); 3556 return 0; 3557 } 3558 3559 /** 3560 * t4_load_fw - download firmware 3561 * @adap: the adapter 3562 * @fw_data: the firmware image to write 3563 * @size: image size 3564 * 3565 * Write the supplied firmware image to the card's serial flash. 3566 */ 3567 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3568 { 3569 u32 csum; 3570 int ret, addr; 3571 unsigned int i; 3572 u8 first_page[SF_PAGE_SIZE]; 3573 const u32 *p = (const u32 *)fw_data; 3574 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3575 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3576 unsigned int fw_start_sec; 3577 unsigned int fw_start; 3578 unsigned int fw_size; 3579 3580 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3581 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3582 fw_start = FLASH_FWBOOTSTRAP_START; 3583 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3584 } else { 3585 fw_start_sec = FLASH_FW_START_SEC; 3586 fw_start = FLASH_FW_START; 3587 fw_size = FLASH_FW_MAX_SIZE; 3588 } 3589 3590 if (!size) { 3591 CH_ERR(adap, "FW image has no data\n"); 3592 return -EINVAL; 3593 } 3594 if (size & 511) { 3595 CH_ERR(adap, 3596 "FW image size not multiple of 512 bytes\n"); 3597 return -EINVAL; 3598 } 3599 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3600 CH_ERR(adap, 3601 "FW image size differs from size in FW header\n"); 3602 return -EINVAL; 3603 } 3604 if (size > fw_size) { 3605 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3606 fw_size); 3607 return -EFBIG; 3608 } 3609 if (!t4_fw_matches_chip(adap, hdr)) 3610 return -EINVAL; 3611 3612 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3613 csum += be32_to_cpu(p[i]); 3614 3615 if (csum != 0xffffffff) { 3616 CH_ERR(adap, 3617 "corrupted firmware image, checksum %#x\n", csum); 3618 return -EINVAL; 3619 } 3620 3621 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3622 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3623 if (ret) 3624 goto out; 3625 3626 /* 3627 * We write the correct version at the end so the driver can see a bad 3628 * version if the FW write fails. Start by writing a copy of the 3629 * first page with a bad version. 3630 */ 3631 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3632 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3633 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3634 if (ret) 3635 goto out; 3636 3637 addr = fw_start; 3638 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3639 addr += SF_PAGE_SIZE; 3640 fw_data += SF_PAGE_SIZE; 3641 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3642 if (ret) 3643 goto out; 3644 } 3645 3646 ret = t4_write_flash(adap, 3647 fw_start + offsetof(struct fw_hdr, fw_ver), 3648 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3649 out: 3650 if (ret) 3651 CH_ERR(adap, "firmware download failed, error %d\n", 3652 ret); 3653 return ret; 3654 } 3655 3656 /** 3657 * t4_fwcache - firmware cache operation 3658 * @adap: the adapter 3659 * @op : the operation (flush or flush and invalidate) 3660 */ 3661 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3662 { 3663 struct fw_params_cmd c; 3664 3665 memset(&c, 0, sizeof(c)); 3666 c.op_to_vfn = 3667 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3668 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3669 V_FW_PARAMS_CMD_PFN(adap->pf) | 3670 V_FW_PARAMS_CMD_VFN(0)); 3671 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3672 c.param[0].mnem = 3673 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3674 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3675 c.param[0].val = (__force __be32)op; 3676 3677 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3678 } 3679 3680 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3681 unsigned int *pif_req_wrptr, 3682 unsigned int *pif_rsp_wrptr) 3683 { 3684 int i, j; 3685 u32 cfg, val, req, rsp; 3686 3687 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3688 if (cfg & F_LADBGEN) 3689 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3690 3691 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3692 req = G_POLADBGWRPTR(val); 3693 rsp = G_PILADBGWRPTR(val); 3694 if (pif_req_wrptr) 3695 *pif_req_wrptr = req; 3696 if (pif_rsp_wrptr) 3697 *pif_rsp_wrptr = rsp; 3698 3699 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3700 for (j = 0; j < 6; j++) { 3701 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3702 V_PILADBGRDPTR(rsp)); 3703 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3704 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3705 req++; 3706 rsp++; 3707 } 3708 req = (req + 2) & M_POLADBGRDPTR; 3709 rsp = (rsp + 2) & M_PILADBGRDPTR; 3710 } 3711 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3712 } 3713 3714 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3715 { 3716 u32 cfg; 3717 int i, j, idx; 3718 3719 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3720 if (cfg & F_LADBGEN) 3721 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3722 3723 for (i = 0; i < CIM_MALA_SIZE; i++) { 3724 for (j = 0; j < 5; j++) { 3725 idx = 8 * i + j; 3726 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3727 V_PILADBGRDPTR(idx)); 3728 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3729 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3730 } 3731 } 3732 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3733 } 3734 3735 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3736 { 3737 unsigned int i, j; 3738 3739 for (i = 0; i < 8; i++) { 3740 u32 *p = la_buf + i; 3741 3742 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3743 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3744 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3745 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3746 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3747 } 3748 } 3749 3750 /** 3751 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3752 * @caps16: a 16-bit Port Capabilities value 3753 * 3754 * Returns the equivalent 32-bit Port Capabilities value. 3755 */ 3756 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3757 { 3758 uint32_t caps32 = 0; 3759 3760 #define CAP16_TO_CAP32(__cap) \ 3761 do { \ 3762 if (caps16 & FW_PORT_CAP_##__cap) \ 3763 caps32 |= FW_PORT_CAP32_##__cap; \ 3764 } while (0) 3765 3766 CAP16_TO_CAP32(SPEED_100M); 3767 CAP16_TO_CAP32(SPEED_1G); 3768 CAP16_TO_CAP32(SPEED_25G); 3769 CAP16_TO_CAP32(SPEED_10G); 3770 CAP16_TO_CAP32(SPEED_40G); 3771 CAP16_TO_CAP32(SPEED_100G); 3772 CAP16_TO_CAP32(FC_RX); 3773 CAP16_TO_CAP32(FC_TX); 3774 CAP16_TO_CAP32(ANEG); 3775 CAP16_TO_CAP32(FORCE_PAUSE); 3776 CAP16_TO_CAP32(MDIAUTO); 3777 CAP16_TO_CAP32(MDISTRAIGHT); 3778 CAP16_TO_CAP32(FEC_RS); 3779 CAP16_TO_CAP32(FEC_BASER_RS); 3780 CAP16_TO_CAP32(802_3_PAUSE); 3781 CAP16_TO_CAP32(802_3_ASM_DIR); 3782 3783 #undef CAP16_TO_CAP32 3784 3785 return caps32; 3786 } 3787 3788 /** 3789 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3790 * @caps32: a 32-bit Port Capabilities value 3791 * 3792 * Returns the equivalent 16-bit Port Capabilities value. Note that 3793 * not all 32-bit Port Capabilities can be represented in the 16-bit 3794 * Port Capabilities and some fields/values may not make it. 3795 */ 3796 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3797 { 3798 uint16_t caps16 = 0; 3799 3800 #define CAP32_TO_CAP16(__cap) \ 3801 do { \ 3802 if (caps32 & FW_PORT_CAP32_##__cap) \ 3803 caps16 |= FW_PORT_CAP_##__cap; \ 3804 } while (0) 3805 3806 CAP32_TO_CAP16(SPEED_100M); 3807 CAP32_TO_CAP16(SPEED_1G); 3808 CAP32_TO_CAP16(SPEED_10G); 3809 CAP32_TO_CAP16(SPEED_25G); 3810 CAP32_TO_CAP16(SPEED_40G); 3811 CAP32_TO_CAP16(SPEED_100G); 3812 CAP32_TO_CAP16(FC_RX); 3813 CAP32_TO_CAP16(FC_TX); 3814 CAP32_TO_CAP16(802_3_PAUSE); 3815 CAP32_TO_CAP16(802_3_ASM_DIR); 3816 CAP32_TO_CAP16(ANEG); 3817 CAP32_TO_CAP16(FORCE_PAUSE); 3818 CAP32_TO_CAP16(MDIAUTO); 3819 CAP32_TO_CAP16(MDISTRAIGHT); 3820 CAP32_TO_CAP16(FEC_RS); 3821 CAP32_TO_CAP16(FEC_BASER_RS); 3822 3823 #undef CAP32_TO_CAP16 3824 3825 return caps16; 3826 } 3827 3828 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none) 3829 { 3830 int8_t fec = 0; 3831 3832 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) 3833 return (unset_means_none ? FEC_NONE : 0); 3834 3835 if (caps & FW_PORT_CAP32_FEC_RS) 3836 fec |= FEC_RS; 3837 if (caps & FW_PORT_CAP32_FEC_BASER_RS) 3838 fec |= FEC_BASER_RS; 3839 if (caps & FW_PORT_CAP32_FEC_NO_FEC) 3840 fec |= FEC_NONE; 3841 3842 return (fec); 3843 } 3844 3845 /* 3846 * Note that 0 is not translated to NO_FEC. 3847 */ 3848 static uint32_t fec_to_fwcap(int8_t fec) 3849 { 3850 uint32_t caps = 0; 3851 3852 /* Only real FECs allowed. */ 3853 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); 3854 3855 if (fec & FEC_RS) 3856 caps |= FW_PORT_CAP32_FEC_RS; 3857 if (fec & FEC_BASER_RS) 3858 caps |= FW_PORT_CAP32_FEC_BASER_RS; 3859 if (fec & FEC_NONE) 3860 caps |= FW_PORT_CAP32_FEC_NO_FEC; 3861 3862 return (caps); 3863 } 3864 3865 /** 3866 * t4_link_l1cfg - apply link configuration to MAC/PHY 3867 * @phy: the PHY to setup 3868 * @mac: the MAC to setup 3869 * @lc: the requested link configuration 3870 * 3871 * Set up a port's MAC and PHY according to a desired link configuration. 3872 * - If the PHY can auto-negotiate first decide what to advertise, then 3873 * enable/disable auto-negotiation as desired, and reset. 3874 * - If the PHY does not auto-negotiate just reset it. 3875 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3876 * otherwise do it later based on the outcome of auto-negotiation. 3877 */ 3878 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3879 struct link_config *lc) 3880 { 3881 struct fw_port_cmd c; 3882 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3883 unsigned int aneg, fc, fec, speed, rcap; 3884 3885 fc = 0; 3886 if (lc->requested_fc & PAUSE_RX) 3887 fc |= FW_PORT_CAP32_FC_RX; 3888 if (lc->requested_fc & PAUSE_TX) 3889 fc |= FW_PORT_CAP32_FC_TX; 3890 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3891 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3892 3893 if (lc->requested_aneg == AUTONEG_DISABLE) 3894 aneg = 0; 3895 else if (lc->requested_aneg == AUTONEG_ENABLE) 3896 aneg = FW_PORT_CAP32_ANEG; 3897 else 3898 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3899 3900 if (aneg) { 3901 speed = lc->pcaps & 3902 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3903 } else if (lc->requested_speed != 0) 3904 speed = speed_to_fwcap(lc->requested_speed); 3905 else 3906 speed = fwcap_top_speed(lc->pcaps); 3907 3908 fec = 0; 3909 if (fec_supported(speed)) { 3910 int force_fec; 3911 3912 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 3913 force_fec = lc->force_fec; 3914 else 3915 force_fec = 0; 3916 3917 if (lc->requested_fec == FEC_AUTO) { 3918 if (force_fec > 0) { 3919 /* 3920 * Must use FORCE_FEC even though requested FEC 3921 * is AUTO. Set all the FEC bits valid for the 3922 * speed and let the firmware pick one. 3923 */ 3924 fec |= FW_PORT_CAP32_FORCE_FEC; 3925 if (speed & FW_PORT_CAP32_SPEED_100G) { 3926 fec |= FW_PORT_CAP32_FEC_RS; 3927 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3928 } else if (speed & FW_PORT_CAP32_SPEED_50G) { 3929 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3930 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3931 } else { 3932 fec |= FW_PORT_CAP32_FEC_RS; 3933 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3934 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3935 } 3936 } else { 3937 /* 3938 * Set only 1b. Old firmwares can't deal with 3939 * multiple bits and new firmwares are free to 3940 * ignore this and try whatever FECs they want 3941 * because we aren't setting FORCE_FEC here. 3942 */ 3943 fec |= fec_to_fwcap(lc->fec_hint); 3944 MPASS(powerof2(fec)); 3945 3946 /* 3947 * Override the hint if the FEC is not valid for 3948 * the potential top speed. Request the best 3949 * FEC at that speed instead. 3950 */ 3951 if (speed & FW_PORT_CAP32_SPEED_100G) { 3952 if (fec == FW_PORT_CAP32_FEC_BASER_RS) 3953 fec = FW_PORT_CAP32_FEC_RS; 3954 } else if (speed & FW_PORT_CAP32_SPEED_50G) { 3955 if (fec == FW_PORT_CAP32_FEC_RS) 3956 fec = FW_PORT_CAP32_FEC_BASER_RS; 3957 } 3958 } 3959 } else { 3960 /* 3961 * User has explicitly requested some FEC(s). Set 3962 * FORCE_FEC unless prohibited from using it. 3963 */ 3964 if (force_fec != 0) 3965 fec |= FW_PORT_CAP32_FORCE_FEC; 3966 fec |= fec_to_fwcap(lc->requested_fec & 3967 M_FW_PORT_CAP32_FEC); 3968 if (lc->requested_fec & FEC_MODULE) 3969 fec |= fec_to_fwcap(lc->fec_hint); 3970 } 3971 3972 /* 3973 * This is for compatibility with old firmwares. The original 3974 * way to request NO_FEC was to not set any of the FEC bits. New 3975 * firmwares understand this too. 3976 */ 3977 if (fec == FW_PORT_CAP32_FEC_NO_FEC) 3978 fec = 0; 3979 } 3980 3981 /* Force AN on for BT cards. */ 3982 if (isset(&adap->bt_map, port)) 3983 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3984 3985 rcap = aneg | speed | fc | fec; 3986 if ((rcap | lc->pcaps) != lc->pcaps) { 3987 #ifdef INVARIANTS 3988 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, 3989 lc->pcaps, rcap & (rcap ^ lc->pcaps)); 3990 #endif 3991 rcap &= lc->pcaps; 3992 } 3993 rcap |= mdi; 3994 3995 memset(&c, 0, sizeof(c)); 3996 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3997 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3998 V_FW_PORT_CMD_PORTID(port)); 3999 if (adap->params.port_caps32) { 4000 c.action_to_len16 = 4001 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 4002 FW_LEN16(c)); 4003 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 4004 } else { 4005 c.action_to_len16 = 4006 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4007 FW_LEN16(c)); 4008 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 4009 } 4010 4011 lc->requested_caps = rcap; 4012 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 4013 } 4014 4015 /** 4016 * t4_restart_aneg - restart autonegotiation 4017 * @adap: the adapter 4018 * @mbox: mbox to use for the FW command 4019 * @port: the port id 4020 * 4021 * Restarts autonegotiation for the selected port. 4022 */ 4023 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 4024 { 4025 struct fw_port_cmd c; 4026 4027 memset(&c, 0, sizeof(c)); 4028 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 4029 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 4030 V_FW_PORT_CMD_PORTID(port)); 4031 c.action_to_len16 = 4032 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4033 FW_LEN16(c)); 4034 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 4035 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4036 } 4037 4038 struct intr_details { 4039 u32 mask; 4040 const char *msg; 4041 }; 4042 4043 struct intr_action { 4044 u32 mask; 4045 int arg; 4046 bool (*action)(struct adapter *, int, bool); 4047 }; 4048 4049 #define NONFATAL_IF_DISABLED 1 4050 struct intr_info { 4051 const char *name; /* name of the INT_CAUSE register */ 4052 int cause_reg; /* INT_CAUSE register */ 4053 int enable_reg; /* INT_ENABLE register */ 4054 u32 fatal; /* bits that are fatal */ 4055 int flags; /* hints */ 4056 const struct intr_details *details; 4057 const struct intr_action *actions; 4058 }; 4059 4060 static inline char 4061 intr_alert_char(u32 cause, u32 enable, u32 fatal) 4062 { 4063 4064 if (cause & fatal) 4065 return ('!'); 4066 if (cause & enable) 4067 return ('*'); 4068 return ('-'); 4069 } 4070 4071 static void 4072 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 4073 { 4074 u32 enable, fatal, leftover; 4075 const struct intr_details *details; 4076 char alert; 4077 4078 enable = t4_read_reg(adap, ii->enable_reg); 4079 if (ii->flags & NONFATAL_IF_DISABLED) 4080 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 4081 else 4082 fatal = ii->fatal; 4083 alert = intr_alert_char(cause, enable, fatal); 4084 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 4085 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4086 4087 leftover = cause; 4088 for (details = ii->details; details && details->mask != 0; details++) { 4089 u32 msgbits = details->mask & cause; 4090 if (msgbits == 0) 4091 continue; 4092 alert = intr_alert_char(msgbits, enable, ii->fatal); 4093 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4094 details->msg); 4095 leftover &= ~msgbits; 4096 } 4097 if (leftover != 0 && leftover != cause) 4098 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4099 } 4100 4101 /* 4102 * Returns true for fatal error. 4103 */ 4104 static bool 4105 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4106 u32 additional_cause, bool verbose) 4107 { 4108 u32 cause, fatal; 4109 bool rc; 4110 const struct intr_action *action; 4111 4112 /* 4113 * Read and display cause. Note that the top level PL_INT_CAUSE is a 4114 * bit special and we need to completely ignore the bits that are not in 4115 * PL_INT_ENABLE. 4116 */ 4117 cause = t4_read_reg(adap, ii->cause_reg); 4118 if (ii->cause_reg == A_PL_INT_CAUSE) 4119 cause &= t4_read_reg(adap, ii->enable_reg); 4120 if (verbose || cause != 0) 4121 t4_show_intr_info(adap, ii, cause); 4122 fatal = cause & ii->fatal; 4123 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4124 fatal &= t4_read_reg(adap, ii->enable_reg); 4125 cause |= additional_cause; 4126 if (cause == 0) 4127 return (false); 4128 4129 rc = fatal != 0; 4130 for (action = ii->actions; action && action->mask != 0; action++) { 4131 if (!(action->mask & cause)) 4132 continue; 4133 rc |= (action->action)(adap, action->arg, verbose); 4134 } 4135 4136 /* clear */ 4137 t4_write_reg(adap, ii->cause_reg, cause); 4138 (void)t4_read_reg(adap, ii->cause_reg); 4139 4140 return (rc); 4141 } 4142 4143 /* 4144 * Interrupt handler for the PCIE module. 4145 */ 4146 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4147 { 4148 static const struct intr_details sysbus_intr_details[] = { 4149 { F_RNPP, "RXNP array parity error" }, 4150 { F_RPCP, "RXPC array parity error" }, 4151 { F_RCIP, "RXCIF array parity error" }, 4152 { F_RCCP, "Rx completions control array parity error" }, 4153 { F_RFTP, "RXFT array parity error" }, 4154 { 0 } 4155 }; 4156 static const struct intr_info sysbus_intr_info = { 4157 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4158 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4159 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4160 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4161 .flags = 0, 4162 .details = sysbus_intr_details, 4163 .actions = NULL, 4164 }; 4165 static const struct intr_details pcie_port_intr_details[] = { 4166 { F_TPCP, "TXPC array parity error" }, 4167 { F_TNPP, "TXNP array parity error" }, 4168 { F_TFTP, "TXFT array parity error" }, 4169 { F_TCAP, "TXCA array parity error" }, 4170 { F_TCIP, "TXCIF array parity error" }, 4171 { F_RCAP, "RXCA array parity error" }, 4172 { F_OTDD, "outbound request TLP discarded" }, 4173 { F_RDPE, "Rx data parity error" }, 4174 { F_TDUE, "Tx uncorrectable data error" }, 4175 { 0 } 4176 }; 4177 static const struct intr_info pcie_port_intr_info = { 4178 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4179 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4180 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4181 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4182 F_OTDD | F_RDPE | F_TDUE, 4183 .flags = 0, 4184 .details = pcie_port_intr_details, 4185 .actions = NULL, 4186 }; 4187 static const struct intr_details pcie_intr_details[] = { 4188 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4189 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4190 { F_MSIDATAPERR, "MSI data parity error" }, 4191 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4192 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4193 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4194 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4195 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4196 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4197 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4198 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4199 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4200 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4201 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4202 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4203 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4204 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4205 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4206 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4207 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4208 { F_FIDPERR, "PCIe FID parity error" }, 4209 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4210 { F_MATAGPERR, "PCIe MA tag parity error" }, 4211 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4212 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4213 { F_RXWRPERR, "PCIe Rx write parity error" }, 4214 { F_RPLPERR, "PCIe replay buffer parity error" }, 4215 { F_PCIESINT, "PCIe core secondary fault" }, 4216 { F_PCIEPINT, "PCIe core primary fault" }, 4217 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4218 { 0 } 4219 }; 4220 static const struct intr_details t5_pcie_intr_details[] = { 4221 { F_IPGRPPERR, "Parity errors observed by IP" }, 4222 { F_NONFATALERR, "PCIe non-fatal error" }, 4223 { F_READRSPERR, "Outbound read error" }, 4224 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4225 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4226 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4227 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4228 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4229 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4230 { F_MAGRPPERR, "MA group FIFO parity error" }, 4231 { F_VFIDPERR, "VFID SRAM parity error" }, 4232 { F_FIDPERR, "FID SRAM parity error" }, 4233 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4234 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4235 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4236 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4237 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4238 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4239 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4240 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4241 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4242 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4243 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4244 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4245 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4246 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4247 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4248 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4249 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4250 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4251 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4252 { 0 } 4253 }; 4254 struct intr_info pcie_intr_info = { 4255 .name = "PCIE_INT_CAUSE", 4256 .cause_reg = A_PCIE_INT_CAUSE, 4257 .enable_reg = A_PCIE_INT_ENABLE, 4258 .fatal = 0xffffffff, 4259 .flags = NONFATAL_IF_DISABLED, 4260 .details = NULL, 4261 .actions = NULL, 4262 }; 4263 bool fatal = false; 4264 4265 if (is_t4(adap)) { 4266 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4267 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4268 4269 pcie_intr_info.details = pcie_intr_details; 4270 } else { 4271 pcie_intr_info.details = t5_pcie_intr_details; 4272 } 4273 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4274 4275 return (fatal); 4276 } 4277 4278 /* 4279 * TP interrupt handler. 4280 */ 4281 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4282 { 4283 static const struct intr_details tp_intr_details[] = { 4284 { 0x3fffffff, "TP parity error" }, 4285 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4286 { 0 } 4287 }; 4288 static const struct intr_info tp_intr_info = { 4289 .name = "TP_INT_CAUSE", 4290 .cause_reg = A_TP_INT_CAUSE, 4291 .enable_reg = A_TP_INT_ENABLE, 4292 .fatal = 0x7fffffff, 4293 .flags = NONFATAL_IF_DISABLED, 4294 .details = tp_intr_details, 4295 .actions = NULL, 4296 }; 4297 4298 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4299 } 4300 4301 /* 4302 * SGE interrupt handler. 4303 */ 4304 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4305 { 4306 static const struct intr_info sge_int1_info = { 4307 .name = "SGE_INT_CAUSE1", 4308 .cause_reg = A_SGE_INT_CAUSE1, 4309 .enable_reg = A_SGE_INT_ENABLE1, 4310 .fatal = 0xffffffff, 4311 .flags = NONFATAL_IF_DISABLED, 4312 .details = NULL, 4313 .actions = NULL, 4314 }; 4315 static const struct intr_info sge_int2_info = { 4316 .name = "SGE_INT_CAUSE2", 4317 .cause_reg = A_SGE_INT_CAUSE2, 4318 .enable_reg = A_SGE_INT_ENABLE2, 4319 .fatal = 0xffffffff, 4320 .flags = NONFATAL_IF_DISABLED, 4321 .details = NULL, 4322 .actions = NULL, 4323 }; 4324 static const struct intr_details sge_int3_details[] = { 4325 { F_ERR_FLM_DBP, 4326 "DBP pointer delivery for invalid context or QID" }, 4327 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4328 "Invalid QID or header request by IDMA" }, 4329 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4330 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4331 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4332 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4333 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4334 { F_ERR_TIMER_ABOVE_MAX_QID, 4335 "SGE GTS with timer 0-5 for IQID > 1023" }, 4336 { F_ERR_CPL_EXCEED_IQE_SIZE, 4337 "SGE received CPL exceeding IQE size" }, 4338 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4339 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4340 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4341 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4342 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4343 "SGE IQID > 1023 received CPL for FL" }, 4344 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4345 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4346 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4347 { F_ERR_ING_CTXT_PRIO, 4348 "Ingress context manager priority user error" }, 4349 { F_ERR_EGR_CTXT_PRIO, 4350 "Egress context manager priority user error" }, 4351 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4352 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4353 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4354 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4355 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4356 { 0x0000000f, "SGE context access for invalid queue" }, 4357 { 0 } 4358 }; 4359 static const struct intr_details t6_sge_int3_details[] = { 4360 { F_ERR_FLM_DBP, 4361 "DBP pointer delivery for invalid context or QID" }, 4362 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4363 "Invalid QID or header request by IDMA" }, 4364 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4365 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4366 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4367 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4368 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4369 { F_ERR_TIMER_ABOVE_MAX_QID, 4370 "SGE GTS with timer 0-5 for IQID > 1023" }, 4371 { F_ERR_CPL_EXCEED_IQE_SIZE, 4372 "SGE received CPL exceeding IQE size" }, 4373 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4374 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4375 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4376 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4377 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4378 "SGE IQID > 1023 received CPL for FL" }, 4379 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4380 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4381 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4382 { F_ERR_ING_CTXT_PRIO, 4383 "Ingress context manager priority user error" }, 4384 { F_ERR_EGR_CTXT_PRIO, 4385 "Egress context manager priority user error" }, 4386 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4387 { F_FATAL_WRE_LEN, 4388 "SGE WRE packet less than advertized length" }, 4389 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4390 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4391 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4392 { 0x0000000f, "SGE context access for invalid queue" }, 4393 { 0 } 4394 }; 4395 struct intr_info sge_int3_info = { 4396 .name = "SGE_INT_CAUSE3", 4397 .cause_reg = A_SGE_INT_CAUSE3, 4398 .enable_reg = A_SGE_INT_ENABLE3, 4399 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4400 .flags = 0, 4401 .details = NULL, 4402 .actions = NULL, 4403 }; 4404 static const struct intr_info sge_int4_info = { 4405 .name = "SGE_INT_CAUSE4", 4406 .cause_reg = A_SGE_INT_CAUSE4, 4407 .enable_reg = A_SGE_INT_ENABLE4, 4408 .fatal = 0, 4409 .flags = 0, 4410 .details = NULL, 4411 .actions = NULL, 4412 }; 4413 static const struct intr_info sge_int5_info = { 4414 .name = "SGE_INT_CAUSE5", 4415 .cause_reg = A_SGE_INT_CAUSE5, 4416 .enable_reg = A_SGE_INT_ENABLE5, 4417 .fatal = 0xffffffff, 4418 .flags = NONFATAL_IF_DISABLED, 4419 .details = NULL, 4420 .actions = NULL, 4421 }; 4422 static const struct intr_info sge_int6_info = { 4423 .name = "SGE_INT_CAUSE6", 4424 .cause_reg = A_SGE_INT_CAUSE6, 4425 .enable_reg = A_SGE_INT_ENABLE6, 4426 .fatal = 0, 4427 .flags = 0, 4428 .details = NULL, 4429 .actions = NULL, 4430 }; 4431 4432 bool fatal; 4433 u32 v; 4434 4435 if (chip_id(adap) <= CHELSIO_T5) { 4436 sge_int3_info.details = sge_int3_details; 4437 } else { 4438 sge_int3_info.details = t6_sge_int3_details; 4439 } 4440 4441 fatal = false; 4442 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4443 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4444 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4445 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4446 if (chip_id(adap) >= CHELSIO_T5) 4447 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4448 if (chip_id(adap) >= CHELSIO_T6) 4449 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4450 4451 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4452 if (v & F_ERROR_QID_VALID) { 4453 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4454 if (v & F_UNCAPTURED_ERROR) 4455 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4456 t4_write_reg(adap, A_SGE_ERROR_STATS, 4457 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4458 } 4459 4460 return (fatal); 4461 } 4462 4463 /* 4464 * CIM interrupt handler. 4465 */ 4466 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4467 { 4468 static const struct intr_details cim_host_intr_details[] = { 4469 /* T6+ */ 4470 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4471 4472 /* T5+ */ 4473 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4474 { F_PLCIM_MSTRSPDATAPARERR, 4475 "PL2CIM master response data parity error" }, 4476 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4477 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4478 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4479 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4480 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4481 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4482 4483 /* T4+ */ 4484 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4485 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4486 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4487 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4488 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4489 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4490 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4491 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4492 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4493 "CIM IBQ PCIe/SGE_HI parity error" }, 4494 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4495 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4496 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4497 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4498 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4499 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4500 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4501 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4502 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4503 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4504 { 0} 4505 }; 4506 static const struct intr_info cim_host_intr_info = { 4507 .name = "CIM_HOST_INT_CAUSE", 4508 .cause_reg = A_CIM_HOST_INT_CAUSE, 4509 .enable_reg = A_CIM_HOST_INT_ENABLE, 4510 .fatal = 0x007fffe6, 4511 .flags = NONFATAL_IF_DISABLED, 4512 .details = cim_host_intr_details, 4513 .actions = NULL, 4514 }; 4515 static const struct intr_details cim_host_upacc_intr_details[] = { 4516 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4517 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4518 { F_TIMEOUTINT, "CIM PIF timeout" }, 4519 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4520 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4521 { F_BLKWRPLINT, "CIM block write to PL space" }, 4522 { F_BLKRDPLINT, "CIM block read from PL space" }, 4523 { F_SGLWRPLINT, 4524 "CIM single write to PL space with illegal BEs" }, 4525 { F_SGLRDPLINT, 4526 "CIM single read from PL space with illegal BEs" }, 4527 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4528 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4529 { F_SGLWRCTLINT, 4530 "CIM single write to CTL space with illegal BEs" }, 4531 { F_SGLRDCTLINT, 4532 "CIM single read from CTL space with illegal BEs" }, 4533 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4534 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4535 { F_SGLWREEPROMINT, 4536 "CIM single write to EEPROM space with illegal BEs" }, 4537 { F_SGLRDEEPROMINT, 4538 "CIM single read from EEPROM space with illegal BEs" }, 4539 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4540 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4541 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4542 { F_SGLRDFLASHINT, 4543 "CIM single read from flash space with illegal BEs" }, 4544 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4545 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4546 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4547 { F_SGLRDBOOTINT, 4548 "CIM single read from boot space with illegal BEs" }, 4549 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4550 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4551 { F_ILLRDINT, "CIM illegal read" }, 4552 { F_ILLWRINT, "CIM illegal write" }, 4553 { F_ILLTRANSINT, "CIM illegal transaction" }, 4554 { F_RSVDSPACEINT, "CIM reserved space access" }, 4555 {0} 4556 }; 4557 static const struct intr_info cim_host_upacc_intr_info = { 4558 .name = "CIM_HOST_UPACC_INT_CAUSE", 4559 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4560 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4561 .fatal = 0x3fffeeff, 4562 .flags = NONFATAL_IF_DISABLED, 4563 .details = cim_host_upacc_intr_details, 4564 .actions = NULL, 4565 }; 4566 static const struct intr_info cim_pf_host_intr_info = { 4567 .name = "CIM_PF_HOST_INT_CAUSE", 4568 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4569 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4570 .fatal = 0, 4571 .flags = 0, 4572 .details = NULL, 4573 .actions = NULL, 4574 }; 4575 u32 val, fw_err; 4576 bool fatal; 4577 4578 /* 4579 * When the Firmware detects an internal error which normally wouldn't 4580 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4581 * to make sure the Host sees the Firmware Crash. So if we have a 4582 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4583 * interrupt. 4584 */ 4585 fw_err = t4_read_reg(adap, A_PCIE_FW); 4586 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4587 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4588 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4589 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4590 } 4591 4592 fatal = (fw_err & F_PCIE_FW_ERR) != 0; 4593 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4594 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4595 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4596 if (fatal) 4597 t4_os_cim_err(adap); 4598 4599 return (fatal); 4600 } 4601 4602 /* 4603 * ULP RX interrupt handler. 4604 */ 4605 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4606 { 4607 static const struct intr_details ulprx_intr_details[] = { 4608 /* T5+ */ 4609 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4610 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4611 4612 /* T4+ */ 4613 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4614 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4615 { 0x007fffff, "ULPRX parity error" }, 4616 { 0 } 4617 }; 4618 static const struct intr_info ulprx_intr_info = { 4619 .name = "ULP_RX_INT_CAUSE", 4620 .cause_reg = A_ULP_RX_INT_CAUSE, 4621 .enable_reg = A_ULP_RX_INT_ENABLE, 4622 .fatal = 0x07ffffff, 4623 .flags = NONFATAL_IF_DISABLED, 4624 .details = ulprx_intr_details, 4625 .actions = NULL, 4626 }; 4627 static const struct intr_info ulprx_intr2_info = { 4628 .name = "ULP_RX_INT_CAUSE_2", 4629 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4630 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4631 .fatal = 0, 4632 .flags = 0, 4633 .details = NULL, 4634 .actions = NULL, 4635 }; 4636 bool fatal = false; 4637 4638 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4639 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4640 4641 return (fatal); 4642 } 4643 4644 /* 4645 * ULP TX interrupt handler. 4646 */ 4647 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4648 { 4649 static const struct intr_details ulptx_intr_details[] = { 4650 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4651 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4652 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4653 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4654 { 0x0fffffff, "ULPTX parity error" }, 4655 { 0 } 4656 }; 4657 static const struct intr_info ulptx_intr_info = { 4658 .name = "ULP_TX_INT_CAUSE", 4659 .cause_reg = A_ULP_TX_INT_CAUSE, 4660 .enable_reg = A_ULP_TX_INT_ENABLE, 4661 .fatal = 0x0fffffff, 4662 .flags = NONFATAL_IF_DISABLED, 4663 .details = ulptx_intr_details, 4664 .actions = NULL, 4665 }; 4666 static const struct intr_info ulptx_intr2_info = { 4667 .name = "ULP_TX_INT_CAUSE_2", 4668 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4669 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4670 .fatal = 0xf0, 4671 .flags = NONFATAL_IF_DISABLED, 4672 .details = NULL, 4673 .actions = NULL, 4674 }; 4675 bool fatal = false; 4676 4677 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4678 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4679 4680 return (fatal); 4681 } 4682 4683 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4684 { 4685 int i; 4686 u32 data[17]; 4687 4688 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4689 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4690 for (i = 0; i < ARRAY_SIZE(data); i++) { 4691 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4692 A_PM_TX_DBG_STAT0 + i, data[i]); 4693 } 4694 4695 return (false); 4696 } 4697 4698 /* 4699 * PM TX interrupt handler. 4700 */ 4701 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4702 { 4703 static const struct intr_action pmtx_intr_actions[] = { 4704 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4705 { 0 }, 4706 }; 4707 static const struct intr_details pmtx_intr_details[] = { 4708 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4709 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4710 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4711 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4712 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4713 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4714 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4715 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4716 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4717 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4718 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4719 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4720 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4721 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4722 { 0 } 4723 }; 4724 static const struct intr_info pmtx_intr_info = { 4725 .name = "PM_TX_INT_CAUSE", 4726 .cause_reg = A_PM_TX_INT_CAUSE, 4727 .enable_reg = A_PM_TX_INT_ENABLE, 4728 .fatal = 0xffffffff, 4729 .flags = 0, 4730 .details = pmtx_intr_details, 4731 .actions = pmtx_intr_actions, 4732 }; 4733 4734 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4735 } 4736 4737 /* 4738 * PM RX interrupt handler. 4739 */ 4740 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4741 { 4742 static const struct intr_details pmrx_intr_details[] = { 4743 /* T6+ */ 4744 { 0x18000000, "PMRX ospi overflow" }, 4745 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4746 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4747 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4748 { F_SDC_ERR, "PMRX SDC error" }, 4749 4750 /* T4+ */ 4751 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4752 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4753 { 0x0003c000, "PMRX iespi Rx framing error" }, 4754 { 0x00003c00, "PMRX iespi Tx framing error" }, 4755 { 0x00000300, "PMRX ocspi Rx framing error" }, 4756 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4757 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4758 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4759 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4760 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4761 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4762 { 0 } 4763 }; 4764 static const struct intr_info pmrx_intr_info = { 4765 .name = "PM_RX_INT_CAUSE", 4766 .cause_reg = A_PM_RX_INT_CAUSE, 4767 .enable_reg = A_PM_RX_INT_ENABLE, 4768 .fatal = 0x1fffffff, 4769 .flags = NONFATAL_IF_DISABLED, 4770 .details = pmrx_intr_details, 4771 .actions = NULL, 4772 }; 4773 4774 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4775 } 4776 4777 /* 4778 * CPL switch interrupt handler. 4779 */ 4780 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4781 { 4782 static const struct intr_details cplsw_intr_details[] = { 4783 /* T5+ */ 4784 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4785 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4786 4787 /* T4+ */ 4788 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4789 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4790 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4791 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4792 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4793 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4794 { 0 } 4795 }; 4796 static const struct intr_info cplsw_intr_info = { 4797 .name = "CPL_INTR_CAUSE", 4798 .cause_reg = A_CPL_INTR_CAUSE, 4799 .enable_reg = A_CPL_INTR_ENABLE, 4800 .fatal = 0xff, 4801 .flags = NONFATAL_IF_DISABLED, 4802 .details = cplsw_intr_details, 4803 .actions = NULL, 4804 }; 4805 4806 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4807 } 4808 4809 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4810 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4811 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4812 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4813 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4814 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4815 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4816 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4817 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4818 4819 /* 4820 * LE interrupt handler. 4821 */ 4822 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4823 { 4824 static const struct intr_details le_intr_details[] = { 4825 { F_REQQPARERR, "LE request queue parity error" }, 4826 { F_UNKNOWNCMD, "LE unknown command" }, 4827 { F_ACTRGNFULL, "LE active region full" }, 4828 { F_PARITYERR, "LE parity error" }, 4829 { F_LIPMISS, "LE LIP miss" }, 4830 { F_LIP0, "LE 0 LIP error" }, 4831 { 0 } 4832 }; 4833 static const struct intr_details t6_le_intr_details[] = { 4834 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4835 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4836 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4837 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4838 { F_TOTCNTERR, "LE total active < TCAM count" }, 4839 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4840 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4841 { F_T6_ACTRGNFULL, "LE active region full" }, 4842 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4843 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4844 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4845 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4846 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4847 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4848 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4849 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4850 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4851 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4852 { 0 } 4853 }; 4854 struct intr_info le_intr_info = { 4855 .name = "LE_DB_INT_CAUSE", 4856 .cause_reg = A_LE_DB_INT_CAUSE, 4857 .enable_reg = A_LE_DB_INT_ENABLE, 4858 .fatal = 0, 4859 .flags = NONFATAL_IF_DISABLED, 4860 .details = NULL, 4861 .actions = NULL, 4862 }; 4863 4864 if (chip_id(adap) <= CHELSIO_T5) { 4865 le_intr_info.details = le_intr_details; 4866 le_intr_info.fatal = T5_LE_FATAL_MASK; 4867 } else { 4868 le_intr_info.details = t6_le_intr_details; 4869 le_intr_info.fatal = T6_LE_FATAL_MASK; 4870 } 4871 4872 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4873 } 4874 4875 /* 4876 * MPS interrupt handler. 4877 */ 4878 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4879 { 4880 static const struct intr_details mps_rx_perr_intr_details[] = { 4881 { 0xffffffff, "MPS Rx parity error" }, 4882 { 0 } 4883 }; 4884 static const struct intr_info mps_rx_perr_intr_info = { 4885 .name = "MPS_RX_PERR_INT_CAUSE", 4886 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4887 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4888 .fatal = 0xffffffff, 4889 .flags = NONFATAL_IF_DISABLED, 4890 .details = mps_rx_perr_intr_details, 4891 .actions = NULL, 4892 }; 4893 static const struct intr_details mps_tx_intr_details[] = { 4894 { F_PORTERR, "MPS Tx destination port is disabled" }, 4895 { F_FRMERR, "MPS Tx framing error" }, 4896 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4897 { F_BUBBLE, "MPS Tx underflow" }, 4898 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4899 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4900 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4901 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4902 { 0 } 4903 }; 4904 static const struct intr_info mps_tx_intr_info = { 4905 .name = "MPS_TX_INT_CAUSE", 4906 .cause_reg = A_MPS_TX_INT_CAUSE, 4907 .enable_reg = A_MPS_TX_INT_ENABLE, 4908 .fatal = 0x1ffff, 4909 .flags = NONFATAL_IF_DISABLED, 4910 .details = mps_tx_intr_details, 4911 .actions = NULL, 4912 }; 4913 static const struct intr_details mps_trc_intr_details[] = { 4914 { F_MISCPERR, "MPS TRC misc parity error" }, 4915 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4916 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4917 { 0 } 4918 }; 4919 static const struct intr_info mps_trc_intr_info = { 4920 .name = "MPS_TRC_INT_CAUSE", 4921 .cause_reg = A_MPS_TRC_INT_CAUSE, 4922 .enable_reg = A_MPS_TRC_INT_ENABLE, 4923 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4924 .flags = 0, 4925 .details = mps_trc_intr_details, 4926 .actions = NULL, 4927 }; 4928 static const struct intr_details mps_stat_sram_intr_details[] = { 4929 { 0xffffffff, "MPS statistics SRAM parity error" }, 4930 { 0 } 4931 }; 4932 static const struct intr_info mps_stat_sram_intr_info = { 4933 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4934 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4935 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4936 .fatal = 0x1fffffff, 4937 .flags = NONFATAL_IF_DISABLED, 4938 .details = mps_stat_sram_intr_details, 4939 .actions = NULL, 4940 }; 4941 static const struct intr_details mps_stat_tx_intr_details[] = { 4942 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4943 { 0 } 4944 }; 4945 static const struct intr_info mps_stat_tx_intr_info = { 4946 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4947 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4948 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4949 .fatal = 0xffffff, 4950 .flags = NONFATAL_IF_DISABLED, 4951 .details = mps_stat_tx_intr_details, 4952 .actions = NULL, 4953 }; 4954 static const struct intr_details mps_stat_rx_intr_details[] = { 4955 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4956 { 0 } 4957 }; 4958 static const struct intr_info mps_stat_rx_intr_info = { 4959 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4960 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4961 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4962 .fatal = 0xffffff, 4963 .flags = 0, 4964 .details = mps_stat_rx_intr_details, 4965 .actions = NULL, 4966 }; 4967 static const struct intr_details mps_cls_intr_details[] = { 4968 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4969 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4970 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4971 { 0 } 4972 }; 4973 static const struct intr_info mps_cls_intr_info = { 4974 .name = "MPS_CLS_INT_CAUSE", 4975 .cause_reg = A_MPS_CLS_INT_CAUSE, 4976 .enable_reg = A_MPS_CLS_INT_ENABLE, 4977 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4978 .flags = 0, 4979 .details = mps_cls_intr_details, 4980 .actions = NULL, 4981 }; 4982 static const struct intr_details mps_stat_sram1_intr_details[] = { 4983 { 0xff, "MPS statistics SRAM1 parity error" }, 4984 { 0 } 4985 }; 4986 static const struct intr_info mps_stat_sram1_intr_info = { 4987 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4988 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4989 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4990 .fatal = 0xff, 4991 .flags = 0, 4992 .details = mps_stat_sram1_intr_details, 4993 .actions = NULL, 4994 }; 4995 4996 bool fatal; 4997 4998 fatal = false; 4999 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 5000 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 5001 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 5002 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 5003 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 5004 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 5005 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 5006 if (chip_id(adap) > CHELSIO_T4) { 5007 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 5008 verbose); 5009 } 5010 5011 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5012 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 5013 5014 return (fatal); 5015 5016 } 5017 5018 /* 5019 * EDC/MC interrupt handler. 5020 */ 5021 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 5022 { 5023 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 5024 unsigned int count_reg, v; 5025 static const struct intr_details mem_intr_details[] = { 5026 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 5027 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 5028 { F_PERR_INT_CAUSE, "FIFO parity error" }, 5029 { 0 } 5030 }; 5031 struct intr_info ii = { 5032 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 5033 .details = mem_intr_details, 5034 .flags = 0, 5035 .actions = NULL, 5036 }; 5037 bool fatal; 5038 5039 switch (idx) { 5040 case MEM_EDC0: 5041 ii.name = "EDC0_INT_CAUSE"; 5042 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 5043 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 5044 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 5045 break; 5046 case MEM_EDC1: 5047 ii.name = "EDC1_INT_CAUSE"; 5048 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 5049 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 5050 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 5051 break; 5052 case MEM_MC0: 5053 ii.name = "MC0_INT_CAUSE"; 5054 if (is_t4(adap)) { 5055 ii.cause_reg = A_MC_INT_CAUSE; 5056 ii.enable_reg = A_MC_INT_ENABLE; 5057 count_reg = A_MC_ECC_STATUS; 5058 } else { 5059 ii.cause_reg = A_MC_P_INT_CAUSE; 5060 ii.enable_reg = A_MC_P_INT_ENABLE; 5061 count_reg = A_MC_P_ECC_STATUS; 5062 } 5063 break; 5064 case MEM_MC1: 5065 ii.name = "MC1_INT_CAUSE"; 5066 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 5067 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 5068 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 5069 break; 5070 } 5071 5072 fatal = t4_handle_intr(adap, &ii, 0, verbose); 5073 5074 v = t4_read_reg(adap, count_reg); 5075 if (v != 0) { 5076 if (G_ECC_UECNT(v) != 0) { 5077 CH_ALERT(adap, 5078 "%s: %u uncorrectable ECC data error(s)\n", 5079 name[idx], G_ECC_UECNT(v)); 5080 } 5081 if (G_ECC_CECNT(v) != 0) { 5082 if (idx <= MEM_EDC1) 5083 t4_edc_err_read(adap, idx); 5084 CH_WARN_RATELIMIT(adap, 5085 "%s: %u correctable ECC data error(s)\n", 5086 name[idx], G_ECC_CECNT(v)); 5087 } 5088 t4_write_reg(adap, count_reg, 0xffffffff); 5089 } 5090 5091 return (fatal); 5092 } 5093 5094 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5095 { 5096 u32 v; 5097 5098 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5099 CH_ALERT(adap, 5100 "MA address wrap-around error by client %u to address %#x\n", 5101 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5102 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5103 5104 return (false); 5105 } 5106 5107 5108 /* 5109 * MA interrupt handler. 5110 */ 5111 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5112 { 5113 static const struct intr_action ma_intr_actions[] = { 5114 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5115 { 0 }, 5116 }; 5117 static const struct intr_info ma_intr_info = { 5118 .name = "MA_INT_CAUSE", 5119 .cause_reg = A_MA_INT_CAUSE, 5120 .enable_reg = A_MA_INT_ENABLE, 5121 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5122 .flags = NONFATAL_IF_DISABLED, 5123 .details = NULL, 5124 .actions = ma_intr_actions, 5125 }; 5126 static const struct intr_info ma_perr_status1 = { 5127 .name = "MA_PARITY_ERROR_STATUS1", 5128 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5129 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5130 .fatal = 0xffffffff, 5131 .flags = 0, 5132 .details = NULL, 5133 .actions = NULL, 5134 }; 5135 static const struct intr_info ma_perr_status2 = { 5136 .name = "MA_PARITY_ERROR_STATUS2", 5137 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5138 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5139 .fatal = 0xffffffff, 5140 .flags = 0, 5141 .details = NULL, 5142 .actions = NULL, 5143 }; 5144 bool fatal; 5145 5146 fatal = false; 5147 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5148 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5149 if (chip_id(adap) > CHELSIO_T4) 5150 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5151 5152 return (fatal); 5153 } 5154 5155 /* 5156 * SMB interrupt handler. 5157 */ 5158 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5159 { 5160 static const struct intr_details smb_intr_details[] = { 5161 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5162 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5163 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5164 { 0 } 5165 }; 5166 static const struct intr_info smb_intr_info = { 5167 .name = "SMB_INT_CAUSE", 5168 .cause_reg = A_SMB_INT_CAUSE, 5169 .enable_reg = A_SMB_INT_ENABLE, 5170 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5171 .flags = 0, 5172 .details = smb_intr_details, 5173 .actions = NULL, 5174 }; 5175 5176 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5177 } 5178 5179 /* 5180 * NC-SI interrupt handler. 5181 */ 5182 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5183 { 5184 static const struct intr_details ncsi_intr_details[] = { 5185 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5186 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5187 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5188 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5189 { 0 } 5190 }; 5191 static const struct intr_info ncsi_intr_info = { 5192 .name = "NCSI_INT_CAUSE", 5193 .cause_reg = A_NCSI_INT_CAUSE, 5194 .enable_reg = A_NCSI_INT_ENABLE, 5195 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5196 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5197 .flags = 0, 5198 .details = ncsi_intr_details, 5199 .actions = NULL, 5200 }; 5201 5202 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5203 } 5204 5205 /* 5206 * MAC interrupt handler. 5207 */ 5208 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5209 { 5210 static const struct intr_details mac_intr_details[] = { 5211 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5212 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5213 { 0 } 5214 }; 5215 char name[32]; 5216 struct intr_info ii; 5217 bool fatal = false; 5218 5219 if (is_t4(adap)) { 5220 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5221 ii.name = &name[0]; 5222 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5223 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5224 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5225 ii.flags = 0; 5226 ii.details = mac_intr_details; 5227 ii.actions = NULL; 5228 } else { 5229 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5230 ii.name = &name[0]; 5231 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5232 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5233 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5234 ii.flags = 0; 5235 ii.details = mac_intr_details; 5236 ii.actions = NULL; 5237 } 5238 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5239 5240 if (chip_id(adap) >= CHELSIO_T5) { 5241 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5242 ii.name = &name[0]; 5243 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5244 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5245 ii.fatal = 0; 5246 ii.flags = 0; 5247 ii.details = NULL; 5248 ii.actions = NULL; 5249 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5250 } 5251 5252 if (chip_id(adap) >= CHELSIO_T6) { 5253 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5254 ii.name = &name[0]; 5255 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5256 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5257 ii.fatal = 0; 5258 ii.flags = 0; 5259 ii.details = NULL; 5260 ii.actions = NULL; 5261 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5262 } 5263 5264 return (fatal); 5265 } 5266 5267 static bool pl_timeout_status(struct adapter *adap, int arg, bool verbose) 5268 { 5269 5270 CH_ALERT(adap, " PL_TIMEOUT_STATUS 0x%08x 0x%08x\n", 5271 t4_read_reg(adap, A_PL_TIMEOUT_STATUS0), 5272 t4_read_reg(adap, A_PL_TIMEOUT_STATUS1)); 5273 5274 return (false); 5275 } 5276 5277 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5278 { 5279 static const struct intr_action plpl_intr_actions[] = { 5280 { F_TIMEOUT, 0, pl_timeout_status }, 5281 { 0 }, 5282 }; 5283 static const struct intr_details plpl_intr_details[] = { 5284 { F_PL_BUSPERR, "Bus parity error" }, 5285 { F_FATALPERR, "Fatal parity error" }, 5286 { F_INVALIDACCESS, "Global reserved memory access" }, 5287 { F_TIMEOUT, "Bus timeout" }, 5288 { F_PLERR, "Module reserved access" }, 5289 { F_PERRVFID, "VFID_MAP parity error" }, 5290 { 0 } 5291 }; 5292 static const struct intr_info plpl_intr_info = { 5293 .name = "PL_PL_INT_CAUSE", 5294 .cause_reg = A_PL_PL_INT_CAUSE, 5295 .enable_reg = A_PL_PL_INT_ENABLE, 5296 .fatal = F_FATALPERR | F_PERRVFID, 5297 .flags = NONFATAL_IF_DISABLED, 5298 .details = plpl_intr_details, 5299 .actions = plpl_intr_actions, 5300 }; 5301 5302 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5303 } 5304 5305 /** 5306 * t4_slow_intr_handler - control path interrupt handler 5307 * @adap: the adapter 5308 * @verbose: increased verbosity, for debug 5309 * 5310 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5311 * The designation 'slow' is because it involves register reads, while 5312 * data interrupts typically don't involve any MMIOs. 5313 */ 5314 bool t4_slow_intr_handler(struct adapter *adap, bool verbose) 5315 { 5316 static const struct intr_details pl_intr_details[] = { 5317 { F_MC1, "MC1" }, 5318 { F_UART, "UART" }, 5319 { F_ULP_TX, "ULP TX" }, 5320 { F_SGE, "SGE" }, 5321 { F_HMA, "HMA" }, 5322 { F_CPL_SWITCH, "CPL Switch" }, 5323 { F_ULP_RX, "ULP RX" }, 5324 { F_PM_RX, "PM RX" }, 5325 { F_PM_TX, "PM TX" }, 5326 { F_MA, "MA" }, 5327 { F_TP, "TP" }, 5328 { F_LE, "LE" }, 5329 { F_EDC1, "EDC1" }, 5330 { F_EDC0, "EDC0" }, 5331 { F_MC, "MC0" }, 5332 { F_PCIE, "PCIE" }, 5333 { F_PMU, "PMU" }, 5334 { F_MAC3, "MAC3" }, 5335 { F_MAC2, "MAC2" }, 5336 { F_MAC1, "MAC1" }, 5337 { F_MAC0, "MAC0" }, 5338 { F_SMB, "SMB" }, 5339 { F_SF, "SF" }, 5340 { F_PL, "PL" }, 5341 { F_NCSI, "NC-SI" }, 5342 { F_MPS, "MPS" }, 5343 { F_MI, "MI" }, 5344 { F_DBG, "DBG" }, 5345 { F_I2CM, "I2CM" }, 5346 { F_CIM, "CIM" }, 5347 { 0 } 5348 }; 5349 static const struct intr_info pl_perr_cause = { 5350 .name = "PL_PERR_CAUSE", 5351 .cause_reg = A_PL_PERR_CAUSE, 5352 .enable_reg = A_PL_PERR_ENABLE, 5353 .fatal = 0xffffffff, 5354 .flags = 0, 5355 .details = pl_intr_details, 5356 .actions = NULL, 5357 }; 5358 static const struct intr_action pl_intr_action[] = { 5359 { F_MC1, MEM_MC1, mem_intr_handler }, 5360 { F_ULP_TX, -1, ulptx_intr_handler }, 5361 { F_SGE, -1, sge_intr_handler }, 5362 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5363 { F_ULP_RX, -1, ulprx_intr_handler }, 5364 { F_PM_RX, -1, pmrx_intr_handler}, 5365 { F_PM_TX, -1, pmtx_intr_handler}, 5366 { F_MA, -1, ma_intr_handler }, 5367 { F_TP, -1, tp_intr_handler }, 5368 { F_LE, -1, le_intr_handler }, 5369 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5370 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5371 { F_MC0, MEM_MC0, mem_intr_handler }, 5372 { F_PCIE, -1, pcie_intr_handler }, 5373 { F_MAC3, 3, mac_intr_handler}, 5374 { F_MAC2, 2, mac_intr_handler}, 5375 { F_MAC1, 1, mac_intr_handler}, 5376 { F_MAC0, 0, mac_intr_handler}, 5377 { F_SMB, -1, smb_intr_handler}, 5378 { F_PL, -1, plpl_intr_handler }, 5379 { F_NCSI, -1, ncsi_intr_handler}, 5380 { F_MPS, -1, mps_intr_handler }, 5381 { F_CIM, -1, cim_intr_handler }, 5382 { 0 } 5383 }; 5384 static const struct intr_info pl_intr_info = { 5385 .name = "PL_INT_CAUSE", 5386 .cause_reg = A_PL_INT_CAUSE, 5387 .enable_reg = A_PL_INT_ENABLE, 5388 .fatal = 0, 5389 .flags = 0, 5390 .details = pl_intr_details, 5391 .actions = pl_intr_action, 5392 }; 5393 u32 perr; 5394 5395 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5396 if (verbose || perr != 0) { 5397 t4_show_intr_info(adap, &pl_perr_cause, perr); 5398 if (perr != 0) 5399 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5400 if (verbose) 5401 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5402 } 5403 5404 return (t4_handle_intr(adap, &pl_intr_info, perr, verbose)); 5405 } 5406 5407 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5408 5409 /** 5410 * t4_intr_enable - enable interrupts 5411 * @adapter: the adapter whose interrupts should be enabled 5412 * 5413 * Enable PF-specific interrupts for the calling function and the top-level 5414 * interrupt concentrator for global interrupts. Interrupts are already 5415 * enabled at each module, here we just enable the roots of the interrupt 5416 * hierarchies. 5417 * 5418 * Note: this function should be called only when the driver manages 5419 * non PF-specific interrupts from the various HW modules. Only one PCI 5420 * function at a time should be doing this. 5421 */ 5422 void t4_intr_enable(struct adapter *adap) 5423 { 5424 u32 val = 0; 5425 5426 if (chip_id(adap) <= CHELSIO_T5) 5427 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5428 else 5429 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5430 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5431 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5432 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5433 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5434 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5435 F_EGRESS_SIZE_ERR; 5436 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5437 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5438 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5439 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5440 } 5441 5442 /** 5443 * t4_intr_disable - disable interrupts 5444 * @adap: the adapter whose interrupts should be disabled 5445 * 5446 * Disable interrupts. We only disable the top-level interrupt 5447 * concentrators. The caller must be a PCI function managing global 5448 * interrupts. 5449 */ 5450 void t4_intr_disable(struct adapter *adap) 5451 { 5452 5453 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5454 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5455 } 5456 5457 /** 5458 * t4_intr_clear - clear all interrupts 5459 * @adap: the adapter whose interrupts should be cleared 5460 * 5461 * Clears all interrupts. The caller must be a PCI function managing 5462 * global interrupts. 5463 */ 5464 void t4_intr_clear(struct adapter *adap) 5465 { 5466 static const u32 cause_reg[] = { 5467 A_CIM_HOST_INT_CAUSE, 5468 A_CIM_HOST_UPACC_INT_CAUSE, 5469 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5470 A_CPL_INTR_CAUSE, 5471 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5472 A_LE_DB_INT_CAUSE, 5473 A_MA_INT_WRAP_STATUS, 5474 A_MA_PARITY_ERROR_STATUS1, 5475 A_MA_INT_CAUSE, 5476 A_MPS_CLS_INT_CAUSE, 5477 A_MPS_RX_PERR_INT_CAUSE, 5478 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5479 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5480 A_MPS_TRC_INT_CAUSE, 5481 A_MPS_TX_INT_CAUSE, 5482 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5483 A_NCSI_INT_CAUSE, 5484 A_PCIE_INT_CAUSE, 5485 A_PCIE_NONFAT_ERR, 5486 A_PL_PL_INT_CAUSE, 5487 A_PM_RX_INT_CAUSE, 5488 A_PM_TX_INT_CAUSE, 5489 A_SGE_INT_CAUSE1, 5490 A_SGE_INT_CAUSE2, 5491 A_SGE_INT_CAUSE3, 5492 A_SGE_INT_CAUSE4, 5493 A_SMB_INT_CAUSE, 5494 A_TP_INT_CAUSE, 5495 A_ULP_RX_INT_CAUSE, 5496 A_ULP_RX_INT_CAUSE_2, 5497 A_ULP_TX_INT_CAUSE, 5498 A_ULP_TX_INT_CAUSE_2, 5499 5500 MYPF_REG(A_PL_PF_INT_CAUSE), 5501 }; 5502 int i; 5503 const int nchan = adap->chip_params->nchan; 5504 5505 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5506 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5507 5508 if (is_t4(adap)) { 5509 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5510 0xffffffff); 5511 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5512 0xffffffff); 5513 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5514 for (i = 0; i < nchan; i++) { 5515 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5516 0xffffffff); 5517 } 5518 } 5519 if (chip_id(adap) >= CHELSIO_T5) { 5520 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5521 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5522 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5523 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5524 if (is_t5(adap)) { 5525 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5526 0xffffffff); 5527 } 5528 for (i = 0; i < nchan; i++) { 5529 t4_write_reg(adap, T5_PORT_REG(i, 5530 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5531 if (chip_id(adap) > CHELSIO_T5) { 5532 t4_write_reg(adap, T5_PORT_REG(i, 5533 A_MAC_PORT_PERR_INT_CAUSE_100G), 5534 0xffffffff); 5535 } 5536 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5537 0xffffffff); 5538 } 5539 } 5540 if (chip_id(adap) >= CHELSIO_T6) { 5541 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5542 } 5543 5544 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5545 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5546 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5547 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5548 } 5549 5550 /** 5551 * hash_mac_addr - return the hash value of a MAC address 5552 * @addr: the 48-bit Ethernet MAC address 5553 * 5554 * Hashes a MAC address according to the hash function used by HW inexact 5555 * (hash) address matching. 5556 */ 5557 static int hash_mac_addr(const u8 *addr) 5558 { 5559 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5560 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5561 a ^= b; 5562 a ^= (a >> 12); 5563 a ^= (a >> 6); 5564 return a & 0x3f; 5565 } 5566 5567 /** 5568 * t4_config_rss_range - configure a portion of the RSS mapping table 5569 * @adapter: the adapter 5570 * @mbox: mbox to use for the FW command 5571 * @viid: virtual interface whose RSS subtable is to be written 5572 * @start: start entry in the table to write 5573 * @n: how many table entries to write 5574 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5575 * @nrspq: number of values in @rspq 5576 * 5577 * Programs the selected part of the VI's RSS mapping table with the 5578 * provided values. If @nrspq < @n the supplied values are used repeatedly 5579 * until the full table range is populated. 5580 * 5581 * The caller must ensure the values in @rspq are in the range allowed for 5582 * @viid. 5583 */ 5584 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5585 int start, int n, const u16 *rspq, unsigned int nrspq) 5586 { 5587 int ret; 5588 const u16 *rsp = rspq; 5589 const u16 *rsp_end = rspq + nrspq; 5590 struct fw_rss_ind_tbl_cmd cmd; 5591 5592 memset(&cmd, 0, sizeof(cmd)); 5593 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5594 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5595 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5596 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5597 5598 /* 5599 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5600 * Queue Identifiers. These Ingress Queue IDs are packed three to 5601 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5602 * reserved. 5603 */ 5604 while (n > 0) { 5605 int nq = min(n, 32); 5606 int nq_packed = 0; 5607 __be32 *qp = &cmd.iq0_to_iq2; 5608 5609 /* 5610 * Set up the firmware RSS command header to send the next 5611 * "nq" Ingress Queue IDs to the firmware. 5612 */ 5613 cmd.niqid = cpu_to_be16(nq); 5614 cmd.startidx = cpu_to_be16(start); 5615 5616 /* 5617 * "nq" more done for the start of the next loop. 5618 */ 5619 start += nq; 5620 n -= nq; 5621 5622 /* 5623 * While there are still Ingress Queue IDs to stuff into the 5624 * current firmware RSS command, retrieve them from the 5625 * Ingress Queue ID array and insert them into the command. 5626 */ 5627 while (nq > 0) { 5628 /* 5629 * Grab up to the next 3 Ingress Queue IDs (wrapping 5630 * around the Ingress Queue ID array if necessary) and 5631 * insert them into the firmware RSS command at the 5632 * current 3-tuple position within the commad. 5633 */ 5634 u16 qbuf[3]; 5635 u16 *qbp = qbuf; 5636 int nqbuf = min(3, nq); 5637 5638 nq -= nqbuf; 5639 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5640 while (nqbuf && nq_packed < 32) { 5641 nqbuf--; 5642 nq_packed++; 5643 *qbp++ = *rsp++; 5644 if (rsp >= rsp_end) 5645 rsp = rspq; 5646 } 5647 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5648 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5649 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5650 } 5651 5652 /* 5653 * Send this portion of the RRS table update to the firmware; 5654 * bail out on any errors. 5655 */ 5656 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5657 if (ret) 5658 return ret; 5659 } 5660 return 0; 5661 } 5662 5663 /** 5664 * t4_config_glbl_rss - configure the global RSS mode 5665 * @adapter: the adapter 5666 * @mbox: mbox to use for the FW command 5667 * @mode: global RSS mode 5668 * @flags: mode-specific flags 5669 * 5670 * Sets the global RSS mode. 5671 */ 5672 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5673 unsigned int flags) 5674 { 5675 struct fw_rss_glb_config_cmd c; 5676 5677 memset(&c, 0, sizeof(c)); 5678 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5679 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5680 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5681 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5682 c.u.manual.mode_pkd = 5683 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5684 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5685 c.u.basicvirtual.mode_keymode = 5686 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5687 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5688 } else 5689 return -EINVAL; 5690 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5691 } 5692 5693 /** 5694 * t4_config_vi_rss - configure per VI RSS settings 5695 * @adapter: the adapter 5696 * @mbox: mbox to use for the FW command 5697 * @viid: the VI id 5698 * @flags: RSS flags 5699 * @defq: id of the default RSS queue for the VI. 5700 * @skeyidx: RSS secret key table index for non-global mode 5701 * @skey: RSS vf_scramble key for VI. 5702 * 5703 * Configures VI-specific RSS properties. 5704 */ 5705 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5706 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5707 unsigned int skey) 5708 { 5709 struct fw_rss_vi_config_cmd c; 5710 5711 memset(&c, 0, sizeof(c)); 5712 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5713 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5714 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5715 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5716 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5717 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5718 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5719 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5720 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5721 5722 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5723 } 5724 5725 /* Read an RSS table row */ 5726 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5727 { 5728 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5729 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5730 5, 0, val); 5731 } 5732 5733 /** 5734 * t4_read_rss - read the contents of the RSS mapping table 5735 * @adapter: the adapter 5736 * @map: holds the contents of the RSS mapping table 5737 * 5738 * Reads the contents of the RSS hash->queue mapping table. 5739 */ 5740 int t4_read_rss(struct adapter *adapter, u16 *map) 5741 { 5742 u32 val; 5743 int i, ret; 5744 int rss_nentries = adapter->chip_params->rss_nentries; 5745 5746 for (i = 0; i < rss_nentries / 2; ++i) { 5747 ret = rd_rss_row(adapter, i, &val); 5748 if (ret) 5749 return ret; 5750 *map++ = G_LKPTBLQUEUE0(val); 5751 *map++ = G_LKPTBLQUEUE1(val); 5752 } 5753 return 0; 5754 } 5755 5756 /** 5757 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5758 * @adap: the adapter 5759 * @cmd: TP fw ldst address space type 5760 * @vals: where the indirect register values are stored/written 5761 * @nregs: how many indirect registers to read/write 5762 * @start_idx: index of first indirect register to read/write 5763 * @rw: Read (1) or Write (0) 5764 * @sleep_ok: if true we may sleep while awaiting command completion 5765 * 5766 * Access TP indirect registers through LDST 5767 **/ 5768 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5769 unsigned int nregs, unsigned int start_index, 5770 unsigned int rw, bool sleep_ok) 5771 { 5772 int ret = 0; 5773 unsigned int i; 5774 struct fw_ldst_cmd c; 5775 5776 for (i = 0; i < nregs; i++) { 5777 memset(&c, 0, sizeof(c)); 5778 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5779 F_FW_CMD_REQUEST | 5780 (rw ? F_FW_CMD_READ : 5781 F_FW_CMD_WRITE) | 5782 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5783 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5784 5785 c.u.addrval.addr = cpu_to_be32(start_index + i); 5786 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5787 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5788 sleep_ok); 5789 if (ret) 5790 return ret; 5791 5792 if (rw) 5793 vals[i] = be32_to_cpu(c.u.addrval.val); 5794 } 5795 return 0; 5796 } 5797 5798 /** 5799 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5800 * @adap: the adapter 5801 * @reg_addr: Address Register 5802 * @reg_data: Data register 5803 * @buff: where the indirect register values are stored/written 5804 * @nregs: how many indirect registers to read/write 5805 * @start_index: index of first indirect register to read/write 5806 * @rw: READ(1) or WRITE(0) 5807 * @sleep_ok: if true we may sleep while awaiting command completion 5808 * 5809 * Read/Write TP indirect registers through LDST if possible. 5810 * Else, use backdoor access 5811 **/ 5812 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5813 u32 *buff, u32 nregs, u32 start_index, int rw, 5814 bool sleep_ok) 5815 { 5816 int rc = -EINVAL; 5817 int cmd; 5818 5819 switch (reg_addr) { 5820 case A_TP_PIO_ADDR: 5821 cmd = FW_LDST_ADDRSPC_TP_PIO; 5822 break; 5823 case A_TP_TM_PIO_ADDR: 5824 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5825 break; 5826 case A_TP_MIB_INDEX: 5827 cmd = FW_LDST_ADDRSPC_TP_MIB; 5828 break; 5829 default: 5830 goto indirect_access; 5831 } 5832 5833 if (t4_use_ldst(adap)) 5834 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5835 sleep_ok); 5836 5837 indirect_access: 5838 5839 if (rc) { 5840 if (rw) 5841 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5842 start_index); 5843 else 5844 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5845 start_index); 5846 } 5847 } 5848 5849 /** 5850 * t4_tp_pio_read - Read TP PIO registers 5851 * @adap: the adapter 5852 * @buff: where the indirect register values are written 5853 * @nregs: how many indirect registers to read 5854 * @start_index: index of first indirect register to read 5855 * @sleep_ok: if true we may sleep while awaiting command completion 5856 * 5857 * Read TP PIO Registers 5858 **/ 5859 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5860 u32 start_index, bool sleep_ok) 5861 { 5862 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5863 start_index, 1, sleep_ok); 5864 } 5865 5866 /** 5867 * t4_tp_pio_write - Write TP PIO registers 5868 * @adap: the adapter 5869 * @buff: where the indirect register values are stored 5870 * @nregs: how many indirect registers to write 5871 * @start_index: index of first indirect register to write 5872 * @sleep_ok: if true we may sleep while awaiting command completion 5873 * 5874 * Write TP PIO Registers 5875 **/ 5876 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5877 u32 start_index, bool sleep_ok) 5878 { 5879 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5880 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5881 } 5882 5883 /** 5884 * t4_tp_tm_pio_read - Read TP TM PIO registers 5885 * @adap: the adapter 5886 * @buff: where the indirect register values are written 5887 * @nregs: how many indirect registers to read 5888 * @start_index: index of first indirect register to read 5889 * @sleep_ok: if true we may sleep while awaiting command completion 5890 * 5891 * Read TP TM PIO Registers 5892 **/ 5893 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5894 u32 start_index, bool sleep_ok) 5895 { 5896 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5897 nregs, start_index, 1, sleep_ok); 5898 } 5899 5900 /** 5901 * t4_tp_mib_read - Read TP MIB registers 5902 * @adap: the adapter 5903 * @buff: where the indirect register values are written 5904 * @nregs: how many indirect registers to read 5905 * @start_index: index of first indirect register to read 5906 * @sleep_ok: if true we may sleep while awaiting command completion 5907 * 5908 * Read TP MIB Registers 5909 **/ 5910 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5911 bool sleep_ok) 5912 { 5913 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5914 start_index, 1, sleep_ok); 5915 } 5916 5917 /** 5918 * t4_read_rss_key - read the global RSS key 5919 * @adap: the adapter 5920 * @key: 10-entry array holding the 320-bit RSS key 5921 * @sleep_ok: if true we may sleep while awaiting command completion 5922 * 5923 * Reads the global 320-bit RSS key. 5924 */ 5925 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5926 { 5927 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5928 } 5929 5930 /** 5931 * t4_write_rss_key - program one of the RSS keys 5932 * @adap: the adapter 5933 * @key: 10-entry array holding the 320-bit RSS key 5934 * @idx: which RSS key to write 5935 * @sleep_ok: if true we may sleep while awaiting command completion 5936 * 5937 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5938 * 0..15 the corresponding entry in the RSS key table is written, 5939 * otherwise the global RSS key is written. 5940 */ 5941 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5942 bool sleep_ok) 5943 { 5944 u8 rss_key_addr_cnt = 16; 5945 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5946 5947 /* 5948 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5949 * allows access to key addresses 16-63 by using KeyWrAddrX 5950 * as index[5:4](upper 2) into key table 5951 */ 5952 if ((chip_id(adap) > CHELSIO_T5) && 5953 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5954 rss_key_addr_cnt = 32; 5955 5956 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5957 5958 if (idx >= 0 && idx < rss_key_addr_cnt) { 5959 if (rss_key_addr_cnt > 16) 5960 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5961 vrt | V_KEYWRADDRX(idx >> 4) | 5962 V_T6_VFWRADDR(idx) | F_KEYWREN); 5963 else 5964 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5965 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5966 } 5967 } 5968 5969 /** 5970 * t4_read_rss_pf_config - read PF RSS Configuration Table 5971 * @adapter: the adapter 5972 * @index: the entry in the PF RSS table to read 5973 * @valp: where to store the returned value 5974 * @sleep_ok: if true we may sleep while awaiting command completion 5975 * 5976 * Reads the PF RSS Configuration Table at the specified index and returns 5977 * the value found there. 5978 */ 5979 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5980 u32 *valp, bool sleep_ok) 5981 { 5982 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5983 } 5984 5985 /** 5986 * t4_write_rss_pf_config - write PF RSS Configuration Table 5987 * @adapter: the adapter 5988 * @index: the entry in the VF RSS table to read 5989 * @val: the value to store 5990 * @sleep_ok: if true we may sleep while awaiting command completion 5991 * 5992 * Writes the PF RSS Configuration Table at the specified index with the 5993 * specified value. 5994 */ 5995 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5996 u32 val, bool sleep_ok) 5997 { 5998 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5999 sleep_ok); 6000 } 6001 6002 /** 6003 * t4_read_rss_vf_config - read VF RSS Configuration Table 6004 * @adapter: the adapter 6005 * @index: the entry in the VF RSS table to read 6006 * @vfl: where to store the returned VFL 6007 * @vfh: where to store the returned VFH 6008 * @sleep_ok: if true we may sleep while awaiting command completion 6009 * 6010 * Reads the VF RSS Configuration Table at the specified index and returns 6011 * the (VFL, VFH) values found there. 6012 */ 6013 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 6014 u32 *vfl, u32 *vfh, bool sleep_ok) 6015 { 6016 u32 vrt, mask, data; 6017 6018 if (chip_id(adapter) <= CHELSIO_T5) { 6019 mask = V_VFWRADDR(M_VFWRADDR); 6020 data = V_VFWRADDR(index); 6021 } else { 6022 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6023 data = V_T6_VFWRADDR(index); 6024 } 6025 /* 6026 * Request that the index'th VF Table values be read into VFL/VFH. 6027 */ 6028 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6029 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6030 vrt |= data | F_VFRDEN; 6031 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6032 6033 /* 6034 * Grab the VFL/VFH values ... 6035 */ 6036 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6037 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6038 } 6039 6040 /** 6041 * t4_write_rss_vf_config - write VF RSS Configuration Table 6042 * 6043 * @adapter: the adapter 6044 * @index: the entry in the VF RSS table to write 6045 * @vfl: the VFL to store 6046 * @vfh: the VFH to store 6047 * 6048 * Writes the VF RSS Configuration Table at the specified index with the 6049 * specified (VFL, VFH) values. 6050 */ 6051 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 6052 u32 vfl, u32 vfh, bool sleep_ok) 6053 { 6054 u32 vrt, mask, data; 6055 6056 if (chip_id(adapter) <= CHELSIO_T5) { 6057 mask = V_VFWRADDR(M_VFWRADDR); 6058 data = V_VFWRADDR(index); 6059 } else { 6060 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6061 data = V_T6_VFWRADDR(index); 6062 } 6063 6064 /* 6065 * Load up VFL/VFH with the values to be written ... 6066 */ 6067 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6068 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6069 6070 /* 6071 * Write the VFL/VFH into the VF Table at index'th location. 6072 */ 6073 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6074 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6075 vrt |= data | F_VFRDEN; 6076 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6077 } 6078 6079 /** 6080 * t4_read_rss_pf_map - read PF RSS Map 6081 * @adapter: the adapter 6082 * @sleep_ok: if true we may sleep while awaiting command completion 6083 * 6084 * Reads the PF RSS Map register and returns its value. 6085 */ 6086 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 6087 { 6088 u32 pfmap; 6089 6090 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6091 6092 return pfmap; 6093 } 6094 6095 /** 6096 * t4_write_rss_pf_map - write PF RSS Map 6097 * @adapter: the adapter 6098 * @pfmap: PF RSS Map value 6099 * 6100 * Writes the specified value to the PF RSS Map register. 6101 */ 6102 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6103 { 6104 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6105 } 6106 6107 /** 6108 * t4_read_rss_pf_mask - read PF RSS Mask 6109 * @adapter: the adapter 6110 * @sleep_ok: if true we may sleep while awaiting command completion 6111 * 6112 * Reads the PF RSS Mask register and returns its value. 6113 */ 6114 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6115 { 6116 u32 pfmask; 6117 6118 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6119 6120 return pfmask; 6121 } 6122 6123 /** 6124 * t4_write_rss_pf_mask - write PF RSS Mask 6125 * @adapter: the adapter 6126 * @pfmask: PF RSS Mask value 6127 * 6128 * Writes the specified value to the PF RSS Mask register. 6129 */ 6130 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6131 { 6132 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6133 } 6134 6135 /** 6136 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6137 * @adap: the adapter 6138 * @v4: holds the TCP/IP counter values 6139 * @v6: holds the TCP/IPv6 counter values 6140 * @sleep_ok: if true we may sleep while awaiting command completion 6141 * 6142 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6143 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6144 */ 6145 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6146 struct tp_tcp_stats *v6, bool sleep_ok) 6147 { 6148 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6149 6150 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6151 #define STAT(x) val[STAT_IDX(x)] 6152 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6153 6154 if (v4) { 6155 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6156 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6157 v4->tcp_out_rsts = STAT(OUT_RST); 6158 v4->tcp_in_segs = STAT64(IN_SEG); 6159 v4->tcp_out_segs = STAT64(OUT_SEG); 6160 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6161 } 6162 if (v6) { 6163 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6164 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6165 v6->tcp_out_rsts = STAT(OUT_RST); 6166 v6->tcp_in_segs = STAT64(IN_SEG); 6167 v6->tcp_out_segs = STAT64(OUT_SEG); 6168 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6169 } 6170 #undef STAT64 6171 #undef STAT 6172 #undef STAT_IDX 6173 } 6174 6175 /** 6176 * t4_tp_get_err_stats - read TP's error MIB counters 6177 * @adap: the adapter 6178 * @st: holds the counter values 6179 * @sleep_ok: if true we may sleep while awaiting command completion 6180 * 6181 * Returns the values of TP's error counters. 6182 */ 6183 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6184 bool sleep_ok) 6185 { 6186 int nchan = adap->chip_params->nchan; 6187 6188 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6189 sleep_ok); 6190 6191 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6192 sleep_ok); 6193 6194 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6195 sleep_ok); 6196 6197 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6198 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6199 6200 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6201 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6202 6203 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6204 sleep_ok); 6205 6206 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6207 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6208 6209 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6210 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6211 6212 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6213 sleep_ok); 6214 } 6215 6216 /** 6217 * t4_tp_get_err_stats - read TP's error MIB counters 6218 * @adap: the adapter 6219 * @st: holds the counter values 6220 * @sleep_ok: if true we may sleep while awaiting command completion 6221 * 6222 * Returns the values of TP's error counters. 6223 */ 6224 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, 6225 bool sleep_ok) 6226 { 6227 int nchan = adap->chip_params->nchan; 6228 6229 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, 6230 sleep_ok); 6231 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, 6232 sleep_ok); 6233 } 6234 6235 /** 6236 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6237 * @adap: the adapter 6238 * @st: holds the counter values 6239 * 6240 * Returns the values of TP's proxy counters. 6241 */ 6242 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6243 bool sleep_ok) 6244 { 6245 int nchan = adap->chip_params->nchan; 6246 6247 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6248 } 6249 6250 /** 6251 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6252 * @adap: the adapter 6253 * @st: holds the counter values 6254 * @sleep_ok: if true we may sleep while awaiting command completion 6255 * 6256 * Returns the values of TP's CPL counters. 6257 */ 6258 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6259 bool sleep_ok) 6260 { 6261 int nchan = adap->chip_params->nchan; 6262 6263 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6264 6265 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6266 } 6267 6268 /** 6269 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6270 * @adap: the adapter 6271 * @st: holds the counter values 6272 * 6273 * Returns the values of TP's RDMA counters. 6274 */ 6275 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6276 bool sleep_ok) 6277 { 6278 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6279 sleep_ok); 6280 } 6281 6282 /** 6283 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6284 * @adap: the adapter 6285 * @idx: the port index 6286 * @st: holds the counter values 6287 * @sleep_ok: if true we may sleep while awaiting command completion 6288 * 6289 * Returns the values of TP's FCoE counters for the selected port. 6290 */ 6291 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6292 struct tp_fcoe_stats *st, bool sleep_ok) 6293 { 6294 u32 val[2]; 6295 6296 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6297 sleep_ok); 6298 6299 t4_tp_mib_read(adap, &st->frames_drop, 1, 6300 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6301 6302 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6303 sleep_ok); 6304 6305 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6306 } 6307 6308 /** 6309 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6310 * @adap: the adapter 6311 * @st: holds the counter values 6312 * @sleep_ok: if true we may sleep while awaiting command completion 6313 * 6314 * Returns the values of TP's counters for non-TCP directly-placed packets. 6315 */ 6316 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6317 bool sleep_ok) 6318 { 6319 u32 val[4]; 6320 6321 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6322 6323 st->frames = val[0]; 6324 st->drops = val[1]; 6325 st->octets = ((u64)val[2] << 32) | val[3]; 6326 } 6327 6328 /** 6329 * t4_tp_get_tid_stats - read TP's tid MIB counters. 6330 * @adap: the adapter 6331 * @st: holds the counter values 6332 * @sleep_ok: if true we may sleep while awaiting command completion 6333 * 6334 * Returns the values of TP's counters for tids. 6335 */ 6336 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, 6337 bool sleep_ok) 6338 { 6339 6340 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); 6341 } 6342 6343 /** 6344 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6345 * @adap: the adapter 6346 * @mtus: where to store the MTU values 6347 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6348 * 6349 * Reads the HW path MTU table. 6350 */ 6351 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6352 { 6353 u32 v; 6354 int i; 6355 6356 for (i = 0; i < NMTUS; ++i) { 6357 t4_write_reg(adap, A_TP_MTU_TABLE, 6358 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6359 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6360 mtus[i] = G_MTUVALUE(v); 6361 if (mtu_log) 6362 mtu_log[i] = G_MTUWIDTH(v); 6363 } 6364 } 6365 6366 /** 6367 * t4_read_cong_tbl - reads the congestion control table 6368 * @adap: the adapter 6369 * @incr: where to store the alpha values 6370 * 6371 * Reads the additive increments programmed into the HW congestion 6372 * control table. 6373 */ 6374 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6375 { 6376 unsigned int mtu, w; 6377 6378 for (mtu = 0; mtu < NMTUS; ++mtu) 6379 for (w = 0; w < NCCTRL_WIN; ++w) { 6380 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6381 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6382 incr[mtu][w] = (u16)t4_read_reg(adap, 6383 A_TP_CCTRL_TABLE) & 0x1fff; 6384 } 6385 } 6386 6387 /** 6388 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6389 * @adap: the adapter 6390 * @addr: the indirect TP register address 6391 * @mask: specifies the field within the register to modify 6392 * @val: new value for the field 6393 * 6394 * Sets a field of an indirect TP register to the given value. 6395 */ 6396 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6397 unsigned int mask, unsigned int val) 6398 { 6399 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6400 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6401 t4_write_reg(adap, A_TP_PIO_DATA, val); 6402 } 6403 6404 /** 6405 * init_cong_ctrl - initialize congestion control parameters 6406 * @a: the alpha values for congestion control 6407 * @b: the beta values for congestion control 6408 * 6409 * Initialize the congestion control parameters. 6410 */ 6411 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6412 { 6413 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6414 a[9] = 2; 6415 a[10] = 3; 6416 a[11] = 4; 6417 a[12] = 5; 6418 a[13] = 6; 6419 a[14] = 7; 6420 a[15] = 8; 6421 a[16] = 9; 6422 a[17] = 10; 6423 a[18] = 14; 6424 a[19] = 17; 6425 a[20] = 21; 6426 a[21] = 25; 6427 a[22] = 30; 6428 a[23] = 35; 6429 a[24] = 45; 6430 a[25] = 60; 6431 a[26] = 80; 6432 a[27] = 100; 6433 a[28] = 200; 6434 a[29] = 300; 6435 a[30] = 400; 6436 a[31] = 500; 6437 6438 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6439 b[9] = b[10] = 1; 6440 b[11] = b[12] = 2; 6441 b[13] = b[14] = b[15] = b[16] = 3; 6442 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6443 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6444 b[28] = b[29] = 6; 6445 b[30] = b[31] = 7; 6446 } 6447 6448 /* The minimum additive increment value for the congestion control table */ 6449 #define CC_MIN_INCR 2U 6450 6451 /** 6452 * t4_load_mtus - write the MTU and congestion control HW tables 6453 * @adap: the adapter 6454 * @mtus: the values for the MTU table 6455 * @alpha: the values for the congestion control alpha parameter 6456 * @beta: the values for the congestion control beta parameter 6457 * 6458 * Write the HW MTU table with the supplied MTUs and the high-speed 6459 * congestion control table with the supplied alpha, beta, and MTUs. 6460 * We write the two tables together because the additive increments 6461 * depend on the MTUs. 6462 */ 6463 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6464 const unsigned short *alpha, const unsigned short *beta) 6465 { 6466 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6467 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6468 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6469 28672, 40960, 57344, 81920, 114688, 163840, 229376 6470 }; 6471 6472 unsigned int i, w; 6473 6474 for (i = 0; i < NMTUS; ++i) { 6475 unsigned int mtu = mtus[i]; 6476 unsigned int log2 = fls(mtu); 6477 6478 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6479 log2--; 6480 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6481 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6482 6483 for (w = 0; w < NCCTRL_WIN; ++w) { 6484 unsigned int inc; 6485 6486 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6487 CC_MIN_INCR); 6488 6489 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6490 (w << 16) | (beta[w] << 13) | inc); 6491 } 6492 } 6493 } 6494 6495 /** 6496 * t4_set_pace_tbl - set the pace table 6497 * @adap: the adapter 6498 * @pace_vals: the pace values in microseconds 6499 * @start: index of the first entry in the HW pace table to set 6500 * @n: how many entries to set 6501 * 6502 * Sets (a subset of the) HW pace table. 6503 */ 6504 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6505 unsigned int start, unsigned int n) 6506 { 6507 unsigned int vals[NTX_SCHED], i; 6508 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6509 6510 if (n > NTX_SCHED) 6511 return -ERANGE; 6512 6513 /* convert values from us to dack ticks, rounding to closest value */ 6514 for (i = 0; i < n; i++, pace_vals++) { 6515 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6516 if (vals[i] > 0x7ff) 6517 return -ERANGE; 6518 if (*pace_vals && vals[i] == 0) 6519 return -ERANGE; 6520 } 6521 for (i = 0; i < n; i++, start++) 6522 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6523 return 0; 6524 } 6525 6526 /** 6527 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6528 * @adap: the adapter 6529 * @kbps: target rate in Kbps 6530 * @sched: the scheduler index 6531 * 6532 * Configure a Tx HW scheduler for the target rate. 6533 */ 6534 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6535 { 6536 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6537 unsigned int clk = adap->params.vpd.cclk * 1000; 6538 unsigned int selected_cpt = 0, selected_bpt = 0; 6539 6540 if (kbps > 0) { 6541 kbps *= 125; /* -> bytes */ 6542 for (cpt = 1; cpt <= 255; cpt++) { 6543 tps = clk / cpt; 6544 bpt = (kbps + tps / 2) / tps; 6545 if (bpt > 0 && bpt <= 255) { 6546 v = bpt * tps; 6547 delta = v >= kbps ? v - kbps : kbps - v; 6548 if (delta < mindelta) { 6549 mindelta = delta; 6550 selected_cpt = cpt; 6551 selected_bpt = bpt; 6552 } 6553 } else if (selected_cpt) 6554 break; 6555 } 6556 if (!selected_cpt) 6557 return -EINVAL; 6558 } 6559 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6560 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6561 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6562 if (sched & 1) 6563 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6564 else 6565 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6566 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6567 return 0; 6568 } 6569 6570 /** 6571 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6572 * @adap: the adapter 6573 * @sched: the scheduler index 6574 * @ipg: the interpacket delay in tenths of nanoseconds 6575 * 6576 * Set the interpacket delay for a HW packet rate scheduler. 6577 */ 6578 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6579 { 6580 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6581 6582 /* convert ipg to nearest number of core clocks */ 6583 ipg *= core_ticks_per_usec(adap); 6584 ipg = (ipg + 5000) / 10000; 6585 if (ipg > M_TXTIMERSEPQ0) 6586 return -EINVAL; 6587 6588 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6589 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6590 if (sched & 1) 6591 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6592 else 6593 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6594 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6595 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6596 return 0; 6597 } 6598 6599 /* 6600 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6601 * clocks. The formula is 6602 * 6603 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6604 * 6605 * which is equivalent to 6606 * 6607 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6608 */ 6609 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6610 { 6611 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6612 6613 return v * 62 + v / 2; 6614 } 6615 6616 /** 6617 * t4_get_chan_txrate - get the current per channel Tx rates 6618 * @adap: the adapter 6619 * @nic_rate: rates for NIC traffic 6620 * @ofld_rate: rates for offloaded traffic 6621 * 6622 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6623 * for each channel. 6624 */ 6625 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6626 { 6627 u32 v; 6628 6629 v = t4_read_reg(adap, A_TP_TX_TRATE); 6630 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6631 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6632 if (adap->chip_params->nchan > 2) { 6633 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6634 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6635 } 6636 6637 v = t4_read_reg(adap, A_TP_TX_ORATE); 6638 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6639 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6640 if (adap->chip_params->nchan > 2) { 6641 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6642 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6643 } 6644 } 6645 6646 /** 6647 * t4_set_trace_filter - configure one of the tracing filters 6648 * @adap: the adapter 6649 * @tp: the desired trace filter parameters 6650 * @idx: which filter to configure 6651 * @enable: whether to enable or disable the filter 6652 * 6653 * Configures one of the tracing filters available in HW. If @tp is %NULL 6654 * it indicates that the filter is already written in the register and it 6655 * just needs to be enabled or disabled. 6656 */ 6657 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6658 int idx, int enable) 6659 { 6660 int i, ofst = idx * 4; 6661 u32 data_reg, mask_reg, cfg; 6662 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6663 6664 if (idx < 0 || idx >= NTRACE) 6665 return -EINVAL; 6666 6667 if (tp == NULL || !enable) { 6668 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6669 enable ? en : 0); 6670 return 0; 6671 } 6672 6673 /* 6674 * TODO - After T4 data book is updated, specify the exact 6675 * section below. 6676 * 6677 * See T4 data book - MPS section for a complete description 6678 * of the below if..else handling of A_MPS_TRC_CFG register 6679 * value. 6680 */ 6681 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6682 if (cfg & F_TRCMULTIFILTER) { 6683 /* 6684 * If multiple tracers are enabled, then maximum 6685 * capture size is 2.5KB (FIFO size of a single channel) 6686 * minus 2 flits for CPL_TRACE_PKT header. 6687 */ 6688 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6689 return -EINVAL; 6690 } else { 6691 /* 6692 * If multiple tracers are disabled, to avoid deadlocks 6693 * maximum packet capture size of 9600 bytes is recommended. 6694 * Also in this mode, only trace0 can be enabled and running. 6695 */ 6696 if (tp->snap_len > 9600 || idx) 6697 return -EINVAL; 6698 } 6699 6700 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6701 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6702 tp->min_len > M_TFMINPKTSIZE) 6703 return -EINVAL; 6704 6705 /* stop the tracer we'll be changing */ 6706 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6707 6708 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6709 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6710 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6711 6712 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6713 t4_write_reg(adap, data_reg, tp->data[i]); 6714 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6715 } 6716 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6717 V_TFCAPTUREMAX(tp->snap_len) | 6718 V_TFMINPKTSIZE(tp->min_len)); 6719 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6720 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6721 (is_t4(adap) ? 6722 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6723 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6724 6725 return 0; 6726 } 6727 6728 /** 6729 * t4_get_trace_filter - query one of the tracing filters 6730 * @adap: the adapter 6731 * @tp: the current trace filter parameters 6732 * @idx: which trace filter to query 6733 * @enabled: non-zero if the filter is enabled 6734 * 6735 * Returns the current settings of one of the HW tracing filters. 6736 */ 6737 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6738 int *enabled) 6739 { 6740 u32 ctla, ctlb; 6741 int i, ofst = idx * 4; 6742 u32 data_reg, mask_reg; 6743 6744 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6745 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6746 6747 if (is_t4(adap)) { 6748 *enabled = !!(ctla & F_TFEN); 6749 tp->port = G_TFPORT(ctla); 6750 tp->invert = !!(ctla & F_TFINVERTMATCH); 6751 } else { 6752 *enabled = !!(ctla & F_T5_TFEN); 6753 tp->port = G_T5_TFPORT(ctla); 6754 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6755 } 6756 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6757 tp->min_len = G_TFMINPKTSIZE(ctlb); 6758 tp->skip_ofst = G_TFOFFSET(ctla); 6759 tp->skip_len = G_TFLENGTH(ctla); 6760 6761 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6762 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6763 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6764 6765 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6766 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6767 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6768 } 6769 } 6770 6771 /** 6772 * t4_pmtx_get_stats - returns the HW stats from PMTX 6773 * @adap: the adapter 6774 * @cnt: where to store the count statistics 6775 * @cycles: where to store the cycle statistics 6776 * 6777 * Returns performance statistics from PMTX. 6778 */ 6779 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6780 { 6781 int i; 6782 u32 data[2]; 6783 6784 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6785 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6786 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6787 if (is_t4(adap)) 6788 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6789 else { 6790 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6791 A_PM_TX_DBG_DATA, data, 2, 6792 A_PM_TX_DBG_STAT_MSB); 6793 cycles[i] = (((u64)data[0] << 32) | data[1]); 6794 } 6795 } 6796 } 6797 6798 /** 6799 * t4_pmrx_get_stats - returns the HW stats from PMRX 6800 * @adap: the adapter 6801 * @cnt: where to store the count statistics 6802 * @cycles: where to store the cycle statistics 6803 * 6804 * Returns performance statistics from PMRX. 6805 */ 6806 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6807 { 6808 int i; 6809 u32 data[2]; 6810 6811 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6812 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6813 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6814 if (is_t4(adap)) { 6815 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6816 } else { 6817 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6818 A_PM_RX_DBG_DATA, data, 2, 6819 A_PM_RX_DBG_STAT_MSB); 6820 cycles[i] = (((u64)data[0] << 32) | data[1]); 6821 } 6822 } 6823 } 6824 6825 /** 6826 * t4_get_mps_bg_map - return the buffer groups associated with a port 6827 * @adap: the adapter 6828 * @idx: the port index 6829 * 6830 * Returns a bitmap indicating which MPS buffer groups are associated 6831 * with the given port. Bit i is set if buffer group i is used by the 6832 * port. 6833 */ 6834 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6835 { 6836 u32 n; 6837 6838 if (adap->params.mps_bg_map) 6839 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6840 6841 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6842 if (n == 0) 6843 return idx == 0 ? 0xf : 0; 6844 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6845 return idx < 2 ? (3 << (2 * idx)) : 0; 6846 return 1 << idx; 6847 } 6848 6849 /* 6850 * TP RX e-channels associated with the port. 6851 */ 6852 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6853 { 6854 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6855 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; 6856 6857 if (n == 0) 6858 return idx == 0 ? all_chan : 0; 6859 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6860 return idx < 2 ? (3 << (2 * idx)) : 0; 6861 return 1 << idx; 6862 } 6863 6864 /* 6865 * TP RX c-channel associated with the port. 6866 */ 6867 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx) 6868 { 6869 u32 param, val; 6870 int ret; 6871 6872 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6873 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP)); 6874 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 6875 if (!ret) 6876 return (val >> (8 * idx)) & 0xff; 6877 6878 return 0; 6879 } 6880 6881 /** 6882 * t4_get_port_type_description - return Port Type string description 6883 * @port_type: firmware Port Type enumeration 6884 */ 6885 const char *t4_get_port_type_description(enum fw_port_type port_type) 6886 { 6887 static const char *const port_type_description[] = { 6888 "Fiber_XFI", 6889 "Fiber_XAUI", 6890 "BT_SGMII", 6891 "BT_XFI", 6892 "BT_XAUI", 6893 "KX4", 6894 "CX4", 6895 "KX", 6896 "KR", 6897 "SFP", 6898 "BP_AP", 6899 "BP4_AP", 6900 "QSFP_10G", 6901 "QSA", 6902 "QSFP", 6903 "BP40_BA", 6904 "KR4_100G", 6905 "CR4_QSFP", 6906 "CR_QSFP", 6907 "CR2_QSFP", 6908 "SFP28", 6909 "KR_SFP28", 6910 }; 6911 6912 if (port_type < ARRAY_SIZE(port_type_description)) 6913 return port_type_description[port_type]; 6914 return "UNKNOWN"; 6915 } 6916 6917 /** 6918 * t4_get_port_stats_offset - collect port stats relative to a previous 6919 * snapshot 6920 * @adap: The adapter 6921 * @idx: The port 6922 * @stats: Current stats to fill 6923 * @offset: Previous stats snapshot 6924 */ 6925 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6926 struct port_stats *stats, 6927 struct port_stats *offset) 6928 { 6929 u64 *s, *o; 6930 int i; 6931 6932 t4_get_port_stats(adap, idx, stats); 6933 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6934 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6935 i++, s++, o++) 6936 *s -= *o; 6937 } 6938 6939 /** 6940 * t4_get_port_stats - collect port statistics 6941 * @adap: the adapter 6942 * @idx: the port index 6943 * @p: the stats structure to fill 6944 * 6945 * Collect statistics related to the given port from HW. 6946 */ 6947 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6948 { 6949 struct port_info *pi = adap->port[idx]; 6950 u32 bgmap = pi->mps_bg_map; 6951 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6952 6953 #define GET_STAT(name) \ 6954 t4_read_reg64(adap, \ 6955 (is_t4(adap) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L) : \ 6956 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L))) 6957 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6958 6959 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6960 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6961 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6962 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6963 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6964 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6965 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6966 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6967 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6968 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6969 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6970 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6971 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6972 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6973 p->tx_drop = GET_STAT(TX_PORT_DROP); 6974 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6975 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6976 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6977 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6978 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6979 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6980 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6981 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6982 6983 if (chip_id(adap) >= CHELSIO_T5) { 6984 if (stat_ctl & F_COUNTPAUSESTATTX) { 6985 p->tx_frames -= p->tx_pause; 6986 p->tx_octets -= p->tx_pause * 64; 6987 } 6988 if (stat_ctl & F_COUNTPAUSEMCTX) 6989 p->tx_mcast_frames -= p->tx_pause; 6990 } 6991 6992 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6993 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6994 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6995 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6996 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6997 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6998 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6999 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 7000 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 7001 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 7002 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 7003 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 7004 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 7005 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 7006 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 7007 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 7008 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 7009 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 7010 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 7011 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 7012 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 7013 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 7014 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 7015 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 7016 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 7017 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 7018 7019 if (pi->fcs_reg != -1) 7020 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; 7021 7022 if (chip_id(adap) >= CHELSIO_T5) { 7023 if (stat_ctl & F_COUNTPAUSESTATRX) { 7024 p->rx_frames -= p->rx_pause; 7025 p->rx_octets -= p->rx_pause * 64; 7026 } 7027 if (stat_ctl & F_COUNTPAUSEMCRX) 7028 p->rx_mcast_frames -= p->rx_pause; 7029 } 7030 7031 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 7032 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 7033 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 7034 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 7035 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 7036 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 7037 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 7038 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 7039 7040 #undef GET_STAT 7041 #undef GET_STAT_COM 7042 } 7043 7044 /** 7045 * t4_get_lb_stats - collect loopback port statistics 7046 * @adap: the adapter 7047 * @idx: the loopback port index 7048 * @p: the stats structure to fill 7049 * 7050 * Return HW statistics for the given loopback port. 7051 */ 7052 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 7053 { 7054 7055 #define GET_STAT(name) \ 7056 t4_read_reg64(adap, \ 7057 (is_t4(adap) ? \ 7058 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 7059 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 7060 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 7061 7062 p->octets = GET_STAT(BYTES); 7063 p->frames = GET_STAT(FRAMES); 7064 p->bcast_frames = GET_STAT(BCAST); 7065 p->mcast_frames = GET_STAT(MCAST); 7066 p->ucast_frames = GET_STAT(UCAST); 7067 p->error_frames = GET_STAT(ERROR); 7068 7069 p->frames_64 = GET_STAT(64B); 7070 p->frames_65_127 = GET_STAT(65B_127B); 7071 p->frames_128_255 = GET_STAT(128B_255B); 7072 p->frames_256_511 = GET_STAT(256B_511B); 7073 p->frames_512_1023 = GET_STAT(512B_1023B); 7074 p->frames_1024_1518 = GET_STAT(1024B_1518B); 7075 p->frames_1519_max = GET_STAT(1519B_MAX); 7076 p->drop = GET_STAT(DROP_FRAMES); 7077 7078 if (idx < adap->params.nports) { 7079 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; 7080 7081 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 7082 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 7083 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 7084 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 7085 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 7086 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 7087 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 7088 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 7089 } 7090 7091 #undef GET_STAT 7092 #undef GET_STAT_COM 7093 } 7094 7095 /** 7096 * t4_wol_magic_enable - enable/disable magic packet WoL 7097 * @adap: the adapter 7098 * @port: the physical port index 7099 * @addr: MAC address expected in magic packets, %NULL to disable 7100 * 7101 * Enables/disables magic packet wake-on-LAN for the selected port. 7102 */ 7103 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 7104 const u8 *addr) 7105 { 7106 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 7107 7108 if (is_t4(adap)) { 7109 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 7110 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 7111 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7112 } else { 7113 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 7114 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 7115 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7116 } 7117 7118 if (addr) { 7119 t4_write_reg(adap, mag_id_reg_l, 7120 (addr[2] << 24) | (addr[3] << 16) | 7121 (addr[4] << 8) | addr[5]); 7122 t4_write_reg(adap, mag_id_reg_h, 7123 (addr[0] << 8) | addr[1]); 7124 } 7125 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 7126 V_MAGICEN(addr != NULL)); 7127 } 7128 7129 /** 7130 * t4_wol_pat_enable - enable/disable pattern-based WoL 7131 * @adap: the adapter 7132 * @port: the physical port index 7133 * @map: bitmap of which HW pattern filters to set 7134 * @mask0: byte mask for bytes 0-63 of a packet 7135 * @mask1: byte mask for bytes 64-127 of a packet 7136 * @crc: Ethernet CRC for selected bytes 7137 * @enable: enable/disable switch 7138 * 7139 * Sets the pattern filters indicated in @map to mask out the bytes 7140 * specified in @mask0/@mask1 in received packets and compare the CRC of 7141 * the resulting packet against @crc. If @enable is %true pattern-based 7142 * WoL is enabled, otherwise disabled. 7143 */ 7144 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 7145 u64 mask0, u64 mask1, unsigned int crc, bool enable) 7146 { 7147 int i; 7148 u32 port_cfg_reg; 7149 7150 if (is_t4(adap)) 7151 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7152 else 7153 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7154 7155 if (!enable) { 7156 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7157 return 0; 7158 } 7159 if (map > 0xff) 7160 return -EINVAL; 7161 7162 #define EPIO_REG(name) \ 7163 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7164 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7165 7166 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7167 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7168 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7169 7170 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7171 if (!(map & 1)) 7172 continue; 7173 7174 /* write byte masks */ 7175 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7176 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7177 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7178 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7179 return -ETIMEDOUT; 7180 7181 /* write CRC */ 7182 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7183 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7184 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7185 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7186 return -ETIMEDOUT; 7187 } 7188 #undef EPIO_REG 7189 7190 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7191 return 0; 7192 } 7193 7194 /* t4_mk_filtdelwr - create a delete filter WR 7195 * @ftid: the filter ID 7196 * @wr: the filter work request to populate 7197 * @qid: ingress queue to receive the delete notification 7198 * 7199 * Creates a filter work request to delete the supplied filter. If @qid is 7200 * negative the delete notification is suppressed. 7201 */ 7202 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7203 { 7204 memset(wr, 0, sizeof(*wr)); 7205 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7206 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7207 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7208 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7209 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7210 if (qid >= 0) 7211 wr->rx_chan_rx_rpl_iq = 7212 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7213 } 7214 7215 #define INIT_CMD(var, cmd, rd_wr) do { \ 7216 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7217 F_FW_CMD_REQUEST | \ 7218 F_FW_CMD_##rd_wr); \ 7219 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7220 } while (0) 7221 7222 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7223 u32 addr, u32 val) 7224 { 7225 u32 ldst_addrspace; 7226 struct fw_ldst_cmd c; 7227 7228 memset(&c, 0, sizeof(c)); 7229 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7230 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7231 F_FW_CMD_REQUEST | 7232 F_FW_CMD_WRITE | 7233 ldst_addrspace); 7234 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7235 c.u.addrval.addr = cpu_to_be32(addr); 7236 c.u.addrval.val = cpu_to_be32(val); 7237 7238 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7239 } 7240 7241 /** 7242 * t4_mdio_rd - read a PHY register through MDIO 7243 * @adap: the adapter 7244 * @mbox: mailbox to use for the FW command 7245 * @phy_addr: the PHY address 7246 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7247 * @reg: the register to read 7248 * @valp: where to store the value 7249 * 7250 * Issues a FW command through the given mailbox to read a PHY register. 7251 */ 7252 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7253 unsigned int mmd, unsigned int reg, unsigned int *valp) 7254 { 7255 int ret; 7256 u32 ldst_addrspace; 7257 struct fw_ldst_cmd c; 7258 7259 memset(&c, 0, sizeof(c)); 7260 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7261 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7262 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7263 ldst_addrspace); 7264 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7265 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7266 V_FW_LDST_CMD_MMD(mmd)); 7267 c.u.mdio.raddr = cpu_to_be16(reg); 7268 7269 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7270 if (ret == 0) 7271 *valp = be16_to_cpu(c.u.mdio.rval); 7272 return ret; 7273 } 7274 7275 /** 7276 * t4_mdio_wr - write a PHY register through MDIO 7277 * @adap: the adapter 7278 * @mbox: mailbox to use for the FW command 7279 * @phy_addr: the PHY address 7280 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7281 * @reg: the register to write 7282 * @valp: value to write 7283 * 7284 * Issues a FW command through the given mailbox to write a PHY register. 7285 */ 7286 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7287 unsigned int mmd, unsigned int reg, unsigned int val) 7288 { 7289 u32 ldst_addrspace; 7290 struct fw_ldst_cmd c; 7291 7292 memset(&c, 0, sizeof(c)); 7293 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7294 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7295 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7296 ldst_addrspace); 7297 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7298 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7299 V_FW_LDST_CMD_MMD(mmd)); 7300 c.u.mdio.raddr = cpu_to_be16(reg); 7301 c.u.mdio.rval = cpu_to_be16(val); 7302 7303 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7304 } 7305 7306 /** 7307 * 7308 * t4_sge_decode_idma_state - decode the idma state 7309 * @adap: the adapter 7310 * @state: the state idma is stuck in 7311 */ 7312 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7313 { 7314 static const char * const t4_decode[] = { 7315 "IDMA_IDLE", 7316 "IDMA_PUSH_MORE_CPL_FIFO", 7317 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7318 "Not used", 7319 "IDMA_PHYSADDR_SEND_PCIEHDR", 7320 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7321 "IDMA_PHYSADDR_SEND_PAYLOAD", 7322 "IDMA_SEND_FIFO_TO_IMSG", 7323 "IDMA_FL_REQ_DATA_FL_PREP", 7324 "IDMA_FL_REQ_DATA_FL", 7325 "IDMA_FL_DROP", 7326 "IDMA_FL_H_REQ_HEADER_FL", 7327 "IDMA_FL_H_SEND_PCIEHDR", 7328 "IDMA_FL_H_PUSH_CPL_FIFO", 7329 "IDMA_FL_H_SEND_CPL", 7330 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7331 "IDMA_FL_H_SEND_IP_HDR", 7332 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7333 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7334 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7335 "IDMA_FL_D_SEND_PCIEHDR", 7336 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7337 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7338 "IDMA_FL_SEND_PCIEHDR", 7339 "IDMA_FL_PUSH_CPL_FIFO", 7340 "IDMA_FL_SEND_CPL", 7341 "IDMA_FL_SEND_PAYLOAD_FIRST", 7342 "IDMA_FL_SEND_PAYLOAD", 7343 "IDMA_FL_REQ_NEXT_DATA_FL", 7344 "IDMA_FL_SEND_NEXT_PCIEHDR", 7345 "IDMA_FL_SEND_PADDING", 7346 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7347 "IDMA_FL_SEND_FIFO_TO_IMSG", 7348 "IDMA_FL_REQ_DATAFL_DONE", 7349 "IDMA_FL_REQ_HEADERFL_DONE", 7350 }; 7351 static const char * const t5_decode[] = { 7352 "IDMA_IDLE", 7353 "IDMA_ALMOST_IDLE", 7354 "IDMA_PUSH_MORE_CPL_FIFO", 7355 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7356 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7357 "IDMA_PHYSADDR_SEND_PCIEHDR", 7358 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7359 "IDMA_PHYSADDR_SEND_PAYLOAD", 7360 "IDMA_SEND_FIFO_TO_IMSG", 7361 "IDMA_FL_REQ_DATA_FL", 7362 "IDMA_FL_DROP", 7363 "IDMA_FL_DROP_SEND_INC", 7364 "IDMA_FL_H_REQ_HEADER_FL", 7365 "IDMA_FL_H_SEND_PCIEHDR", 7366 "IDMA_FL_H_PUSH_CPL_FIFO", 7367 "IDMA_FL_H_SEND_CPL", 7368 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7369 "IDMA_FL_H_SEND_IP_HDR", 7370 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7371 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7372 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7373 "IDMA_FL_D_SEND_PCIEHDR", 7374 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7375 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7376 "IDMA_FL_SEND_PCIEHDR", 7377 "IDMA_FL_PUSH_CPL_FIFO", 7378 "IDMA_FL_SEND_CPL", 7379 "IDMA_FL_SEND_PAYLOAD_FIRST", 7380 "IDMA_FL_SEND_PAYLOAD", 7381 "IDMA_FL_REQ_NEXT_DATA_FL", 7382 "IDMA_FL_SEND_NEXT_PCIEHDR", 7383 "IDMA_FL_SEND_PADDING", 7384 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7385 }; 7386 static const char * const t6_decode[] = { 7387 "IDMA_IDLE", 7388 "IDMA_PUSH_MORE_CPL_FIFO", 7389 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7390 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7391 "IDMA_PHYSADDR_SEND_PCIEHDR", 7392 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7393 "IDMA_PHYSADDR_SEND_PAYLOAD", 7394 "IDMA_FL_REQ_DATA_FL", 7395 "IDMA_FL_DROP", 7396 "IDMA_FL_DROP_SEND_INC", 7397 "IDMA_FL_H_REQ_HEADER_FL", 7398 "IDMA_FL_H_SEND_PCIEHDR", 7399 "IDMA_FL_H_PUSH_CPL_FIFO", 7400 "IDMA_FL_H_SEND_CPL", 7401 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7402 "IDMA_FL_H_SEND_IP_HDR", 7403 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7404 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7405 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7406 "IDMA_FL_D_SEND_PCIEHDR", 7407 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7408 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7409 "IDMA_FL_SEND_PCIEHDR", 7410 "IDMA_FL_PUSH_CPL_FIFO", 7411 "IDMA_FL_SEND_CPL", 7412 "IDMA_FL_SEND_PAYLOAD_FIRST", 7413 "IDMA_FL_SEND_PAYLOAD", 7414 "IDMA_FL_REQ_NEXT_DATA_FL", 7415 "IDMA_FL_SEND_NEXT_PCIEHDR", 7416 "IDMA_FL_SEND_PADDING", 7417 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7418 }; 7419 static const u32 sge_regs[] = { 7420 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7421 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7422 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7423 }; 7424 const char * const *sge_idma_decode; 7425 int sge_idma_decode_nstates; 7426 int i; 7427 unsigned int chip_version = chip_id(adapter); 7428 7429 /* Select the right set of decode strings to dump depending on the 7430 * adapter chip type. 7431 */ 7432 switch (chip_version) { 7433 case CHELSIO_T4: 7434 sge_idma_decode = (const char * const *)t4_decode; 7435 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7436 break; 7437 7438 case CHELSIO_T5: 7439 sge_idma_decode = (const char * const *)t5_decode; 7440 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7441 break; 7442 7443 case CHELSIO_T6: 7444 sge_idma_decode = (const char * const *)t6_decode; 7445 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7446 break; 7447 7448 default: 7449 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7450 return; 7451 } 7452 7453 if (state < sge_idma_decode_nstates) 7454 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7455 else 7456 CH_WARN(adapter, "idma state %d unknown\n", state); 7457 7458 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7459 CH_WARN(adapter, "SGE register %#x value %#x\n", 7460 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7461 } 7462 7463 /** 7464 * t4_sge_ctxt_flush - flush the SGE context cache 7465 * @adap: the adapter 7466 * @mbox: mailbox to use for the FW command 7467 * 7468 * Issues a FW command through the given mailbox to flush the 7469 * SGE context cache. 7470 */ 7471 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type) 7472 { 7473 int ret; 7474 u32 ldst_addrspace; 7475 struct fw_ldst_cmd c; 7476 7477 memset(&c, 0, sizeof(c)); 7478 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ? 7479 FW_LDST_ADDRSPC_SGE_EGRC : 7480 FW_LDST_ADDRSPC_SGE_INGC); 7481 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7482 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7483 ldst_addrspace); 7484 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7485 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7486 7487 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7488 return ret; 7489 } 7490 7491 /** 7492 * t4_fw_hello - establish communication with FW 7493 * @adap: the adapter 7494 * @mbox: mailbox to use for the FW command 7495 * @evt_mbox: mailbox to receive async FW events 7496 * @master: specifies the caller's willingness to be the device master 7497 * @state: returns the current device state (if non-NULL) 7498 * 7499 * Issues a command to establish communication with FW. Returns either 7500 * an error (negative integer) or the mailbox of the Master PF. 7501 */ 7502 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7503 enum dev_master master, enum dev_state *state) 7504 { 7505 int ret; 7506 struct fw_hello_cmd c; 7507 u32 v; 7508 unsigned int master_mbox; 7509 int retries = FW_CMD_HELLO_RETRIES; 7510 7511 retry: 7512 memset(&c, 0, sizeof(c)); 7513 INIT_CMD(c, HELLO, WRITE); 7514 c.err_to_clearinit = cpu_to_be32( 7515 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7516 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7517 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7518 mbox : M_FW_HELLO_CMD_MBMASTER) | 7519 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7520 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7521 F_FW_HELLO_CMD_CLEARINIT); 7522 7523 /* 7524 * Issue the HELLO command to the firmware. If it's not successful 7525 * but indicates that we got a "busy" or "timeout" condition, retry 7526 * the HELLO until we exhaust our retry limit. If we do exceed our 7527 * retry limit, check to see if the firmware left us any error 7528 * information and report that if so ... 7529 */ 7530 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7531 if (ret != FW_SUCCESS) { 7532 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7533 goto retry; 7534 return ret; 7535 } 7536 7537 v = be32_to_cpu(c.err_to_clearinit); 7538 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7539 if (state) { 7540 if (v & F_FW_HELLO_CMD_ERR) 7541 *state = DEV_STATE_ERR; 7542 else if (v & F_FW_HELLO_CMD_INIT) 7543 *state = DEV_STATE_INIT; 7544 else 7545 *state = DEV_STATE_UNINIT; 7546 } 7547 7548 /* 7549 * If we're not the Master PF then we need to wait around for the 7550 * Master PF Driver to finish setting up the adapter. 7551 * 7552 * Note that we also do this wait if we're a non-Master-capable PF and 7553 * there is no current Master PF; a Master PF may show up momentarily 7554 * and we wouldn't want to fail pointlessly. (This can happen when an 7555 * OS loads lots of different drivers rapidly at the same time). In 7556 * this case, the Master PF returned by the firmware will be 7557 * M_PCIE_FW_MASTER so the test below will work ... 7558 */ 7559 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7560 master_mbox != mbox) { 7561 int waiting = FW_CMD_HELLO_TIMEOUT; 7562 7563 /* 7564 * Wait for the firmware to either indicate an error or 7565 * initialized state. If we see either of these we bail out 7566 * and report the issue to the caller. If we exhaust the 7567 * "hello timeout" and we haven't exhausted our retries, try 7568 * again. Otherwise bail with a timeout error. 7569 */ 7570 for (;;) { 7571 u32 pcie_fw; 7572 7573 msleep(50); 7574 waiting -= 50; 7575 7576 /* 7577 * If neither Error nor Initialialized are indicated 7578 * by the firmware keep waiting till we exhaust our 7579 * timeout ... and then retry if we haven't exhausted 7580 * our retries ... 7581 */ 7582 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7583 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7584 if (waiting <= 0) { 7585 if (retries-- > 0) 7586 goto retry; 7587 7588 return -ETIMEDOUT; 7589 } 7590 continue; 7591 } 7592 7593 /* 7594 * We either have an Error or Initialized condition 7595 * report errors preferentially. 7596 */ 7597 if (state) { 7598 if (pcie_fw & F_PCIE_FW_ERR) 7599 *state = DEV_STATE_ERR; 7600 else if (pcie_fw & F_PCIE_FW_INIT) 7601 *state = DEV_STATE_INIT; 7602 } 7603 7604 /* 7605 * If we arrived before a Master PF was selected and 7606 * there's not a valid Master PF, grab its identity 7607 * for our caller. 7608 */ 7609 if (master_mbox == M_PCIE_FW_MASTER && 7610 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7611 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7612 break; 7613 } 7614 } 7615 7616 return master_mbox; 7617 } 7618 7619 /** 7620 * t4_fw_bye - end communication with FW 7621 * @adap: the adapter 7622 * @mbox: mailbox to use for the FW command 7623 * 7624 * Issues a command to terminate communication with FW. 7625 */ 7626 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7627 { 7628 struct fw_bye_cmd c; 7629 7630 memset(&c, 0, sizeof(c)); 7631 INIT_CMD(c, BYE, WRITE); 7632 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7633 } 7634 7635 /** 7636 * t4_fw_reset - issue a reset to FW 7637 * @adap: the adapter 7638 * @mbox: mailbox to use for the FW command 7639 * @reset: specifies the type of reset to perform 7640 * 7641 * Issues a reset command of the specified type to FW. 7642 */ 7643 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7644 { 7645 struct fw_reset_cmd c; 7646 7647 memset(&c, 0, sizeof(c)); 7648 INIT_CMD(c, RESET, WRITE); 7649 c.val = cpu_to_be32(reset); 7650 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7651 } 7652 7653 /** 7654 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7655 * @adap: the adapter 7656 * @mbox: mailbox to use for the FW RESET command (if desired) 7657 * @force: force uP into RESET even if FW RESET command fails 7658 * 7659 * Issues a RESET command to firmware (if desired) with a HALT indication 7660 * and then puts the microprocessor into RESET state. The RESET command 7661 * will only be issued if a legitimate mailbox is provided (mbox <= 7662 * M_PCIE_FW_MASTER). 7663 * 7664 * This is generally used in order for the host to safely manipulate the 7665 * adapter without fear of conflicting with whatever the firmware might 7666 * be doing. The only way out of this state is to RESTART the firmware 7667 * ... 7668 */ 7669 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7670 { 7671 int ret = 0; 7672 7673 /* 7674 * If a legitimate mailbox is provided, issue a RESET command 7675 * with a HALT indication. 7676 */ 7677 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7678 struct fw_reset_cmd c; 7679 7680 memset(&c, 0, sizeof(c)); 7681 INIT_CMD(c, RESET, WRITE); 7682 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7683 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7684 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7685 } 7686 7687 /* 7688 * Normally we won't complete the operation if the firmware RESET 7689 * command fails but if our caller insists we'll go ahead and put the 7690 * uP into RESET. This can be useful if the firmware is hung or even 7691 * missing ... We'll have to take the risk of putting the uP into 7692 * RESET without the cooperation of firmware in that case. 7693 * 7694 * We also force the firmware's HALT flag to be on in case we bypassed 7695 * the firmware RESET command above or we're dealing with old firmware 7696 * which doesn't have the HALT capability. This will serve as a flag 7697 * for the incoming firmware to know that it's coming out of a HALT 7698 * rather than a RESET ... if it's new enough to understand that ... 7699 */ 7700 if (ret == 0 || force) { 7701 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7702 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7703 F_PCIE_FW_HALT); 7704 } 7705 7706 /* 7707 * And we always return the result of the firmware RESET command 7708 * even when we force the uP into RESET ... 7709 */ 7710 return ret; 7711 } 7712 7713 /** 7714 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7715 * @adap: the adapter 7716 * 7717 * Restart firmware previously halted by t4_fw_halt(). On successful 7718 * return the previous PF Master remains as the new PF Master and there 7719 * is no need to issue a new HELLO command, etc. 7720 */ 7721 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7722 { 7723 int ms; 7724 7725 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7726 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7727 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7728 return FW_SUCCESS; 7729 msleep(100); 7730 ms += 100; 7731 } 7732 7733 return -ETIMEDOUT; 7734 } 7735 7736 /** 7737 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7738 * @adap: the adapter 7739 * @mbox: mailbox to use for the FW RESET command (if desired) 7740 * @fw_data: the firmware image to write 7741 * @size: image size 7742 * @force: force upgrade even if firmware doesn't cooperate 7743 * 7744 * Perform all of the steps necessary for upgrading an adapter's 7745 * firmware image. Normally this requires the cooperation of the 7746 * existing firmware in order to halt all existing activities 7747 * but if an invalid mailbox token is passed in we skip that step 7748 * (though we'll still put the adapter microprocessor into RESET in 7749 * that case). 7750 * 7751 * On successful return the new firmware will have been loaded and 7752 * the adapter will have been fully RESET losing all previous setup 7753 * state. On unsuccessful return the adapter may be completely hosed ... 7754 * positive errno indicates that the adapter is ~probably~ intact, a 7755 * negative errno indicates that things are looking bad ... 7756 */ 7757 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7758 const u8 *fw_data, unsigned int size, int force) 7759 { 7760 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7761 unsigned int bootstrap = 7762 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7763 int ret; 7764 7765 if (!t4_fw_matches_chip(adap, fw_hdr)) 7766 return -EINVAL; 7767 7768 if (!bootstrap) { 7769 ret = t4_fw_halt(adap, mbox, force); 7770 if (ret < 0 && !force) 7771 return ret; 7772 } 7773 7774 ret = t4_load_fw(adap, fw_data, size); 7775 if (ret < 0 || bootstrap) 7776 return ret; 7777 7778 return t4_fw_restart(adap, mbox); 7779 } 7780 7781 /** 7782 * t4_fw_initialize - ask FW to initialize the device 7783 * @adap: the adapter 7784 * @mbox: mailbox to use for the FW command 7785 * 7786 * Issues a command to FW to partially initialize the device. This 7787 * performs initialization that generally doesn't depend on user input. 7788 */ 7789 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7790 { 7791 struct fw_initialize_cmd c; 7792 7793 memset(&c, 0, sizeof(c)); 7794 INIT_CMD(c, INITIALIZE, WRITE); 7795 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7796 } 7797 7798 /** 7799 * t4_query_params_rw - query FW or device parameters 7800 * @adap: the adapter 7801 * @mbox: mailbox to use for the FW command 7802 * @pf: the PF 7803 * @vf: the VF 7804 * @nparams: the number of parameters 7805 * @params: the parameter names 7806 * @val: the parameter values 7807 * @rw: Write and read flag 7808 * 7809 * Reads the value of FW or device parameters. Up to 7 parameters can be 7810 * queried at once. 7811 */ 7812 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7813 unsigned int vf, unsigned int nparams, const u32 *params, 7814 u32 *val, int rw) 7815 { 7816 int i, ret; 7817 struct fw_params_cmd c; 7818 __be32 *p = &c.param[0].mnem; 7819 7820 if (nparams > 7) 7821 return -EINVAL; 7822 7823 memset(&c, 0, sizeof(c)); 7824 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7825 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7826 V_FW_PARAMS_CMD_PFN(pf) | 7827 V_FW_PARAMS_CMD_VFN(vf)); 7828 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7829 7830 for (i = 0; i < nparams; i++) { 7831 *p++ = cpu_to_be32(*params++); 7832 if (rw) 7833 *p = cpu_to_be32(*(val + i)); 7834 p++; 7835 } 7836 7837 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7838 if (ret == 0) 7839 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7840 *val++ = be32_to_cpu(*p); 7841 return ret; 7842 } 7843 7844 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7845 unsigned int vf, unsigned int nparams, const u32 *params, 7846 u32 *val) 7847 { 7848 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7849 } 7850 7851 /** 7852 * t4_set_params_timeout - sets FW or device parameters 7853 * @adap: the adapter 7854 * @mbox: mailbox to use for the FW command 7855 * @pf: the PF 7856 * @vf: the VF 7857 * @nparams: the number of parameters 7858 * @params: the parameter names 7859 * @val: the parameter values 7860 * @timeout: the timeout time 7861 * 7862 * Sets the value of FW or device parameters. Up to 7 parameters can be 7863 * specified at once. 7864 */ 7865 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7866 unsigned int pf, unsigned int vf, 7867 unsigned int nparams, const u32 *params, 7868 const u32 *val, int timeout) 7869 { 7870 struct fw_params_cmd c; 7871 __be32 *p = &c.param[0].mnem; 7872 7873 if (nparams > 7) 7874 return -EINVAL; 7875 7876 memset(&c, 0, sizeof(c)); 7877 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7878 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7879 V_FW_PARAMS_CMD_PFN(pf) | 7880 V_FW_PARAMS_CMD_VFN(vf)); 7881 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7882 7883 while (nparams--) { 7884 *p++ = cpu_to_be32(*params++); 7885 *p++ = cpu_to_be32(*val++); 7886 } 7887 7888 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7889 } 7890 7891 /** 7892 * t4_set_params - sets FW or device parameters 7893 * @adap: the adapter 7894 * @mbox: mailbox to use for the FW command 7895 * @pf: the PF 7896 * @vf: the VF 7897 * @nparams: the number of parameters 7898 * @params: the parameter names 7899 * @val: the parameter values 7900 * 7901 * Sets the value of FW or device parameters. Up to 7 parameters can be 7902 * specified at once. 7903 */ 7904 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7905 unsigned int vf, unsigned int nparams, const u32 *params, 7906 const u32 *val) 7907 { 7908 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7909 FW_CMD_MAX_TIMEOUT); 7910 } 7911 7912 /** 7913 * t4_cfg_pfvf - configure PF/VF resource limits 7914 * @adap: the adapter 7915 * @mbox: mailbox to use for the FW command 7916 * @pf: the PF being configured 7917 * @vf: the VF being configured 7918 * @txq: the max number of egress queues 7919 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7920 * @rxqi: the max number of interrupt-capable ingress queues 7921 * @rxq: the max number of interruptless ingress queues 7922 * @tc: the PCI traffic class 7923 * @vi: the max number of virtual interfaces 7924 * @cmask: the channel access rights mask for the PF/VF 7925 * @pmask: the port access rights mask for the PF/VF 7926 * @nexact: the maximum number of exact MPS filters 7927 * @rcaps: read capabilities 7928 * @wxcaps: write/execute capabilities 7929 * 7930 * Configures resource limits and capabilities for a physical or virtual 7931 * function. 7932 */ 7933 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7934 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7935 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7936 unsigned int vi, unsigned int cmask, unsigned int pmask, 7937 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7938 { 7939 struct fw_pfvf_cmd c; 7940 7941 memset(&c, 0, sizeof(c)); 7942 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7943 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7944 V_FW_PFVF_CMD_VFN(vf)); 7945 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7946 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7947 V_FW_PFVF_CMD_NIQ(rxq)); 7948 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7949 V_FW_PFVF_CMD_PMASK(pmask) | 7950 V_FW_PFVF_CMD_NEQ(txq)); 7951 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7952 V_FW_PFVF_CMD_NVI(vi) | 7953 V_FW_PFVF_CMD_NEXACTF(nexact)); 7954 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7955 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7956 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7957 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7958 } 7959 7960 /** 7961 * t4_alloc_vi_func - allocate a virtual interface 7962 * @adap: the adapter 7963 * @mbox: mailbox to use for the FW command 7964 * @port: physical port associated with the VI 7965 * @pf: the PF owning the VI 7966 * @vf: the VF owning the VI 7967 * @nmac: number of MAC addresses needed (1 to 5) 7968 * @mac: the MAC addresses of the VI 7969 * @rss_size: size of RSS table slice associated with this VI 7970 * @portfunc: which Port Application Function MAC Address is desired 7971 * @idstype: Intrusion Detection Type 7972 * 7973 * Allocates a virtual interface for the given physical port. If @mac is 7974 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7975 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7976 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7977 * stored consecutively so the space needed is @nmac * 6 bytes. 7978 * Returns a negative error number or the non-negative VI id. 7979 */ 7980 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7981 unsigned int port, unsigned int pf, unsigned int vf, 7982 unsigned int nmac, u8 *mac, u16 *rss_size, 7983 uint8_t *vfvld, uint16_t *vin, 7984 unsigned int portfunc, unsigned int idstype) 7985 { 7986 int ret; 7987 struct fw_vi_cmd c; 7988 7989 memset(&c, 0, sizeof(c)); 7990 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7991 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7992 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7993 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7994 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7995 V_FW_VI_CMD_FUNC(portfunc)); 7996 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7997 c.nmac = nmac - 1; 7998 if(!rss_size) 7999 c.norss_rsssize = F_FW_VI_CMD_NORSS; 8000 8001 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8002 if (ret) 8003 return ret; 8004 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 8005 8006 if (mac) { 8007 memcpy(mac, c.mac, sizeof(c.mac)); 8008 switch (nmac) { 8009 case 5: 8010 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 8011 case 4: 8012 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 8013 case 3: 8014 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 8015 case 2: 8016 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 8017 } 8018 } 8019 if (rss_size) 8020 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 8021 if (vfvld) { 8022 *vfvld = adap->params.viid_smt_extn_support ? 8023 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 8024 G_FW_VIID_VIVLD(ret); 8025 } 8026 if (vin) { 8027 *vin = adap->params.viid_smt_extn_support ? 8028 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 8029 G_FW_VIID_VIN(ret); 8030 } 8031 8032 return ret; 8033 } 8034 8035 /** 8036 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 8037 * @adap: the adapter 8038 * @mbox: mailbox to use for the FW command 8039 * @port: physical port associated with the VI 8040 * @pf: the PF owning the VI 8041 * @vf: the VF owning the VI 8042 * @nmac: number of MAC addresses needed (1 to 5) 8043 * @mac: the MAC addresses of the VI 8044 * @rss_size: size of RSS table slice associated with this VI 8045 * 8046 * backwards compatible and convieniance routine to allocate a Virtual 8047 * Interface with a Ethernet Port Application Function and Intrustion 8048 * Detection System disabled. 8049 */ 8050 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 8051 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 8052 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 8053 { 8054 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 8055 vfvld, vin, FW_VI_FUNC_ETH, 0); 8056 } 8057 8058 /** 8059 * t4_free_vi - free a virtual interface 8060 * @adap: the adapter 8061 * @mbox: mailbox to use for the FW command 8062 * @pf: the PF owning the VI 8063 * @vf: the VF owning the VI 8064 * @viid: virtual interface identifiler 8065 * 8066 * Free a previously allocated virtual interface. 8067 */ 8068 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 8069 unsigned int vf, unsigned int viid) 8070 { 8071 struct fw_vi_cmd c; 8072 8073 memset(&c, 0, sizeof(c)); 8074 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 8075 F_FW_CMD_REQUEST | 8076 F_FW_CMD_EXEC | 8077 V_FW_VI_CMD_PFN(pf) | 8078 V_FW_VI_CMD_VFN(vf)); 8079 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 8080 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 8081 8082 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8083 } 8084 8085 /** 8086 * t4_set_rxmode - set Rx properties of a virtual interface 8087 * @adap: the adapter 8088 * @mbox: mailbox to use for the FW command 8089 * @viid: the VI id 8090 * @mtu: the new MTU or -1 8091 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 8092 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 8093 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 8094 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 8095 * @sleep_ok: if true we may sleep while awaiting command completion 8096 * 8097 * Sets Rx properties of a virtual interface. 8098 */ 8099 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 8100 int mtu, int promisc, int all_multi, int bcast, int vlanex, 8101 bool sleep_ok) 8102 { 8103 struct fw_vi_rxmode_cmd c; 8104 8105 /* convert to FW values */ 8106 if (mtu < 0) 8107 mtu = M_FW_VI_RXMODE_CMD_MTU; 8108 if (promisc < 0) 8109 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 8110 if (all_multi < 0) 8111 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 8112 if (bcast < 0) 8113 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 8114 if (vlanex < 0) 8115 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 8116 8117 memset(&c, 0, sizeof(c)); 8118 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 8119 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8120 V_FW_VI_RXMODE_CMD_VIID(viid)); 8121 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 8122 c.mtu_to_vlanexen = 8123 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 8124 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 8125 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 8126 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 8127 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 8128 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8129 } 8130 8131 /** 8132 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support 8133 * @adap: the adapter 8134 * @viid: the VI id 8135 * @mac: the MAC address 8136 * @mask: the mask 8137 * @vni: the VNI id for the tunnel protocol 8138 * @vni_mask: mask for the VNI id 8139 * @dip_hit: to enable DIP match for the MPS entry 8140 * @lookup_type: MAC address for inner (1) or outer (0) header 8141 * @sleep_ok: call is allowed to sleep 8142 * 8143 * Allocates an MPS entry with specified MAC address and VNI value. 8144 * 8145 * Returns a negative error number or the allocated index for this mac. 8146 */ 8147 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 8148 const u8 *addr, const u8 *mask, unsigned int vni, 8149 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 8150 bool sleep_ok) 8151 { 8152 struct fw_vi_mac_cmd c; 8153 struct fw_vi_mac_vni *p = c.u.exact_vni; 8154 int ret = 0; 8155 u32 val; 8156 8157 memset(&c, 0, sizeof(c)); 8158 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8159 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8160 V_FW_VI_MAC_CMD_VIID(viid)); 8161 val = V_FW_CMD_LEN16(1) | 8162 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI); 8163 c.freemacs_to_len16 = cpu_to_be32(val); 8164 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8165 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8166 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8167 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); 8168 8169 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | 8170 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) | 8171 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type)); 8172 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); 8173 8174 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8175 if (ret == 0) 8176 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8177 return ret; 8178 } 8179 8180 /** 8181 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam 8182 * @adap: the adapter 8183 * @viid: the VI id 8184 * @mac: the MAC address 8185 * @mask: the mask 8186 * @idx: index at which to add this entry 8187 * @port_id: the port index 8188 * @lookup_type: MAC address for inner (1) or outer (0) header 8189 * @sleep_ok: call is allowed to sleep 8190 * 8191 * Adds the mac entry at the specified index using raw mac interface. 8192 * 8193 * Returns a negative error number or the allocated index for this mac. 8194 */ 8195 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 8196 const u8 *addr, const u8 *mask, unsigned int idx, 8197 u8 lookup_type, u8 port_id, bool sleep_ok) 8198 { 8199 int ret = 0; 8200 struct fw_vi_mac_cmd c; 8201 struct fw_vi_mac_raw *p = &c.u.raw; 8202 u32 val; 8203 8204 memset(&c, 0, sizeof(c)); 8205 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8206 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8207 V_FW_VI_MAC_CMD_VIID(viid)); 8208 val = V_FW_CMD_LEN16(1) | 8209 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8210 c.freemacs_to_len16 = cpu_to_be32(val); 8211 8212 /* Specify that this is an inner mac address */ 8213 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); 8214 8215 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8216 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8217 V_DATAPORTNUM(port_id)); 8218 /* Lookup mask and port mask */ 8219 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8220 V_DATAPORTNUM(M_DATAPORTNUM)); 8221 8222 /* Copy the address and the mask */ 8223 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8224 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8225 8226 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8227 if (ret == 0) { 8228 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); 8229 if (ret != idx) 8230 ret = -ENOMEM; 8231 } 8232 8233 return ret; 8234 } 8235 8236 /** 8237 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 8238 * @adap: the adapter 8239 * @mbox: mailbox to use for the FW command 8240 * @viid: the VI id 8241 * @free: if true any existing filters for this VI id are first removed 8242 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8243 * @addr: the MAC address(es) 8244 * @idx: where to store the index of each allocated filter 8245 * @hash: pointer to hash address filter bitmap 8246 * @sleep_ok: call is allowed to sleep 8247 * 8248 * Allocates an exact-match filter for each of the supplied addresses and 8249 * sets it to the corresponding address. If @idx is not %NULL it should 8250 * have at least @naddr entries, each of which will be set to the index of 8251 * the filter allocated for the corresponding MAC address. If a filter 8252 * could not be allocated for an address its index is set to 0xffff. 8253 * If @hash is not %NULL addresses that fail to allocate an exact filter 8254 * are hashed and update the hash filter bitmap pointed at by @hash. 8255 * 8256 * Returns a negative error number or the number of filters allocated. 8257 */ 8258 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8259 unsigned int viid, bool free, unsigned int naddr, 8260 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8261 { 8262 int offset, ret = 0; 8263 struct fw_vi_mac_cmd c; 8264 unsigned int nfilters = 0; 8265 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8266 unsigned int rem = naddr; 8267 8268 if (naddr > max_naddr) 8269 return -EINVAL; 8270 8271 for (offset = 0; offset < naddr ; /**/) { 8272 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8273 ? rem 8274 : ARRAY_SIZE(c.u.exact)); 8275 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8276 u.exact[fw_naddr]), 16); 8277 struct fw_vi_mac_exact *p; 8278 int i; 8279 8280 memset(&c, 0, sizeof(c)); 8281 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8282 F_FW_CMD_REQUEST | 8283 F_FW_CMD_WRITE | 8284 V_FW_CMD_EXEC(free) | 8285 V_FW_VI_MAC_CMD_VIID(viid)); 8286 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8287 V_FW_CMD_LEN16(len16)); 8288 8289 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8290 p->valid_to_idx = 8291 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8292 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8293 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8294 } 8295 8296 /* 8297 * It's okay if we run out of space in our MAC address arena. 8298 * Some of the addresses we submit may get stored so we need 8299 * to run through the reply to see what the results were ... 8300 */ 8301 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8302 if (ret && ret != -FW_ENOMEM) 8303 break; 8304 8305 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8306 u16 index = G_FW_VI_MAC_CMD_IDX( 8307 be16_to_cpu(p->valid_to_idx)); 8308 8309 if (idx) 8310 idx[offset+i] = (index >= max_naddr 8311 ? 0xffff 8312 : index); 8313 if (index < max_naddr) 8314 nfilters++; 8315 else if (hash) 8316 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8317 } 8318 8319 free = false; 8320 offset += fw_naddr; 8321 rem -= fw_naddr; 8322 } 8323 8324 if (ret == 0 || ret == -FW_ENOMEM) 8325 ret = nfilters; 8326 return ret; 8327 } 8328 8329 /** 8330 * t4_free_encap_mac_filt - frees MPS entry at given index 8331 * @adap: the adapter 8332 * @viid: the VI id 8333 * @idx: index of MPS entry to be freed 8334 * @sleep_ok: call is allowed to sleep 8335 * 8336 * Frees the MPS entry at supplied index 8337 * 8338 * Returns a negative error number or zero on success 8339 */ 8340 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 8341 int idx, bool sleep_ok) 8342 { 8343 struct fw_vi_mac_exact *p; 8344 struct fw_vi_mac_cmd c; 8345 u8 addr[] = {0,0,0,0,0,0}; 8346 int ret = 0; 8347 u32 exact; 8348 8349 memset(&c, 0, sizeof(c)); 8350 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8351 F_FW_CMD_REQUEST | 8352 F_FW_CMD_WRITE | 8353 V_FW_CMD_EXEC(0) | 8354 V_FW_VI_MAC_CMD_VIID(viid)); 8355 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC); 8356 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8357 exact | 8358 V_FW_CMD_LEN16(1)); 8359 p = c.u.exact; 8360 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8361 V_FW_VI_MAC_CMD_IDX(idx)); 8362 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8363 8364 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8365 return ret; 8366 } 8367 8368 /** 8369 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam 8370 * @adap: the adapter 8371 * @viid: the VI id 8372 * @addr: the MAC address 8373 * @mask: the mask 8374 * @idx: index of the entry in mps tcam 8375 * @lookup_type: MAC address for inner (1) or outer (0) header 8376 * @port_id: the port index 8377 * @sleep_ok: call is allowed to sleep 8378 * 8379 * Removes the mac entry at the specified index using raw mac interface. 8380 * 8381 * Returns a negative error number on failure. 8382 */ 8383 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 8384 const u8 *addr, const u8 *mask, unsigned int idx, 8385 u8 lookup_type, u8 port_id, bool sleep_ok) 8386 { 8387 struct fw_vi_mac_cmd c; 8388 struct fw_vi_mac_raw *p = &c.u.raw; 8389 u32 raw; 8390 8391 memset(&c, 0, sizeof(c)); 8392 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8393 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8394 V_FW_CMD_EXEC(0) | 8395 V_FW_VI_MAC_CMD_VIID(viid)); 8396 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8397 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8398 raw | 8399 V_FW_CMD_LEN16(1)); 8400 8401 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | 8402 FW_VI_MAC_ID_BASED_FREE); 8403 8404 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8405 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8406 V_DATAPORTNUM(port_id)); 8407 /* Lookup mask and port mask */ 8408 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8409 V_DATAPORTNUM(M_DATAPORTNUM)); 8410 8411 /* Copy the address and the mask */ 8412 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8413 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8414 8415 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8416 } 8417 8418 /** 8419 * t4_free_mac_filt - frees exact-match filters of given MAC addresses 8420 * @adap: the adapter 8421 * @mbox: mailbox to use for the FW command 8422 * @viid: the VI id 8423 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8424 * @addr: the MAC address(es) 8425 * @sleep_ok: call is allowed to sleep 8426 * 8427 * Frees the exact-match filter for each of the supplied addresses 8428 * 8429 * Returns a negative error number or the number of filters freed. 8430 */ 8431 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 8432 unsigned int viid, unsigned int naddr, 8433 const u8 **addr, bool sleep_ok) 8434 { 8435 int offset, ret = 0; 8436 struct fw_vi_mac_cmd c; 8437 unsigned int nfilters = 0; 8438 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8439 unsigned int rem = naddr; 8440 8441 if (naddr > max_naddr) 8442 return -EINVAL; 8443 8444 for (offset = 0; offset < (int)naddr ; /**/) { 8445 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8446 ? rem 8447 : ARRAY_SIZE(c.u.exact)); 8448 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8449 u.exact[fw_naddr]), 16); 8450 struct fw_vi_mac_exact *p; 8451 int i; 8452 8453 memset(&c, 0, sizeof(c)); 8454 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8455 F_FW_CMD_REQUEST | 8456 F_FW_CMD_WRITE | 8457 V_FW_CMD_EXEC(0) | 8458 V_FW_VI_MAC_CMD_VIID(viid)); 8459 c.freemacs_to_len16 = 8460 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8461 V_FW_CMD_LEN16(len16)); 8462 8463 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { 8464 p->valid_to_idx = cpu_to_be16( 8465 F_FW_VI_MAC_CMD_VALID | 8466 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 8467 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8468 } 8469 8470 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8471 if (ret) 8472 break; 8473 8474 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8475 u16 index = G_FW_VI_MAC_CMD_IDX( 8476 be16_to_cpu(p->valid_to_idx)); 8477 8478 if (index < max_naddr) 8479 nfilters++; 8480 } 8481 8482 offset += fw_naddr; 8483 rem -= fw_naddr; 8484 } 8485 8486 if (ret == 0) 8487 ret = nfilters; 8488 return ret; 8489 } 8490 8491 /** 8492 * t4_change_mac - modifies the exact-match filter for a MAC address 8493 * @adap: the adapter 8494 * @mbox: mailbox to use for the FW command 8495 * @viid: the VI id 8496 * @idx: index of existing filter for old value of MAC address, or -1 8497 * @addr: the new MAC address value 8498 * @persist: whether a new MAC allocation should be persistent 8499 * @smt_idx: add MAC to SMT and return its index, or NULL 8500 * 8501 * Modifies an exact-match filter and sets it to the new MAC address if 8502 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8503 * latter case the address is added persistently if @persist is %true. 8504 * 8505 * Note that in general it is not possible to modify the value of a given 8506 * filter so the generic way to modify an address filter is to free the one 8507 * being used by the old address value and allocate a new filter for the 8508 * new address value. 8509 * 8510 * Returns a negative error number or the index of the filter with the new 8511 * MAC value. Note that this index may differ from @idx. 8512 */ 8513 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8514 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8515 { 8516 int ret, mode; 8517 struct fw_vi_mac_cmd c; 8518 struct fw_vi_mac_exact *p = c.u.exact; 8519 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8520 8521 if (idx < 0) /* new allocation */ 8522 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8523 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8524 8525 memset(&c, 0, sizeof(c)); 8526 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8527 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8528 V_FW_VI_MAC_CMD_VIID(viid)); 8529 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8530 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8531 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8532 V_FW_VI_MAC_CMD_IDX(idx)); 8533 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8534 8535 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8536 if (ret == 0) { 8537 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8538 if (ret >= max_mac_addr) 8539 ret = -ENOMEM; 8540 if (smt_idx) { 8541 if (adap->params.viid_smt_extn_support) 8542 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8543 else { 8544 if (chip_id(adap) <= CHELSIO_T5) 8545 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8546 else 8547 *smt_idx = viid & M_FW_VIID_VIN; 8548 } 8549 } 8550 } 8551 return ret; 8552 } 8553 8554 /** 8555 * t4_set_addr_hash - program the MAC inexact-match hash filter 8556 * @adap: the adapter 8557 * @mbox: mailbox to use for the FW command 8558 * @viid: the VI id 8559 * @ucast: whether the hash filter should also match unicast addresses 8560 * @vec: the value to be written to the hash filter 8561 * @sleep_ok: call is allowed to sleep 8562 * 8563 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8564 */ 8565 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8566 bool ucast, u64 vec, bool sleep_ok) 8567 { 8568 struct fw_vi_mac_cmd c; 8569 u32 val; 8570 8571 memset(&c, 0, sizeof(c)); 8572 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8573 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8574 V_FW_VI_ENABLE_CMD_VIID(viid)); 8575 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8576 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8577 c.freemacs_to_len16 = cpu_to_be32(val); 8578 c.u.hash.hashvec = cpu_to_be64(vec); 8579 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8580 } 8581 8582 /** 8583 * t4_enable_vi_params - enable/disable a virtual interface 8584 * @adap: the adapter 8585 * @mbox: mailbox to use for the FW command 8586 * @viid: the VI id 8587 * @rx_en: 1=enable Rx, 0=disable Rx 8588 * @tx_en: 1=enable Tx, 0=disable Tx 8589 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8590 * 8591 * Enables/disables a virtual interface. Note that setting DCB Enable 8592 * only makes sense when enabling a Virtual Interface ... 8593 */ 8594 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8595 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8596 { 8597 struct fw_vi_enable_cmd c; 8598 8599 memset(&c, 0, sizeof(c)); 8600 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8601 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8602 V_FW_VI_ENABLE_CMD_VIID(viid)); 8603 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8604 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8605 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8606 FW_LEN16(c)); 8607 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8608 } 8609 8610 /** 8611 * t4_enable_vi - enable/disable a virtual interface 8612 * @adap: the adapter 8613 * @mbox: mailbox to use for the FW command 8614 * @viid: the VI id 8615 * @rx_en: 1=enable Rx, 0=disable Rx 8616 * @tx_en: 1=enable Tx, 0=disable Tx 8617 * 8618 * Enables/disables a virtual interface. Note that setting DCB Enable 8619 * only makes sense when enabling a Virtual Interface ... 8620 */ 8621 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8622 bool rx_en, bool tx_en) 8623 { 8624 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8625 } 8626 8627 /** 8628 * t4_identify_port - identify a VI's port by blinking its LED 8629 * @adap: the adapter 8630 * @mbox: mailbox to use for the FW command 8631 * @viid: the VI id 8632 * @nblinks: how many times to blink LED at 2.5 Hz 8633 * 8634 * Identifies a VI's port by blinking its LED. 8635 */ 8636 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8637 unsigned int nblinks) 8638 { 8639 struct fw_vi_enable_cmd c; 8640 8641 memset(&c, 0, sizeof(c)); 8642 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8643 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8644 V_FW_VI_ENABLE_CMD_VIID(viid)); 8645 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8646 c.blinkdur = cpu_to_be16(nblinks); 8647 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8648 } 8649 8650 /** 8651 * t4_iq_stop - stop an ingress queue and its FLs 8652 * @adap: the adapter 8653 * @mbox: mailbox to use for the FW command 8654 * @pf: the PF owning the queues 8655 * @vf: the VF owning the queues 8656 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8657 * @iqid: ingress queue id 8658 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8659 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8660 * 8661 * Stops an ingress queue and its associated FLs, if any. This causes 8662 * any current or future data/messages destined for these queues to be 8663 * tossed. 8664 */ 8665 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8666 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8667 unsigned int fl0id, unsigned int fl1id) 8668 { 8669 struct fw_iq_cmd c; 8670 8671 memset(&c, 0, sizeof(c)); 8672 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8673 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8674 V_FW_IQ_CMD_VFN(vf)); 8675 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8676 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8677 c.iqid = cpu_to_be16(iqid); 8678 c.fl0id = cpu_to_be16(fl0id); 8679 c.fl1id = cpu_to_be16(fl1id); 8680 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8681 } 8682 8683 /** 8684 * t4_iq_free - free an ingress queue and its FLs 8685 * @adap: the adapter 8686 * @mbox: mailbox to use for the FW command 8687 * @pf: the PF owning the queues 8688 * @vf: the VF owning the queues 8689 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8690 * @iqid: ingress queue id 8691 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8692 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8693 * 8694 * Frees an ingress queue and its associated FLs, if any. 8695 */ 8696 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8697 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8698 unsigned int fl0id, unsigned int fl1id) 8699 { 8700 struct fw_iq_cmd c; 8701 8702 memset(&c, 0, sizeof(c)); 8703 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8704 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8705 V_FW_IQ_CMD_VFN(vf)); 8706 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8707 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8708 c.iqid = cpu_to_be16(iqid); 8709 c.fl0id = cpu_to_be16(fl0id); 8710 c.fl1id = cpu_to_be16(fl1id); 8711 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8712 } 8713 8714 /** 8715 * t4_eth_eq_stop - stop an Ethernet egress queue 8716 * @adap: the adapter 8717 * @mbox: mailbox to use for the FW command 8718 * @pf: the PF owning the queues 8719 * @vf: the VF owning the queues 8720 * @eqid: egress queue id 8721 * 8722 * Stops an Ethernet egress queue. The queue can be reinitialized or 8723 * freed but is not otherwise functional after this call. 8724 */ 8725 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8726 unsigned int vf, unsigned int eqid) 8727 { 8728 struct fw_eq_eth_cmd c; 8729 8730 memset(&c, 0, sizeof(c)); 8731 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8732 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8733 V_FW_EQ_ETH_CMD_PFN(pf) | 8734 V_FW_EQ_ETH_CMD_VFN(vf)); 8735 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c)); 8736 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8737 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8738 } 8739 8740 /** 8741 * t4_eth_eq_free - free an Ethernet egress queue 8742 * @adap: the adapter 8743 * @mbox: mailbox to use for the FW command 8744 * @pf: the PF owning the queue 8745 * @vf: the VF owning the queue 8746 * @eqid: egress queue id 8747 * 8748 * Frees an Ethernet egress queue. 8749 */ 8750 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8751 unsigned int vf, unsigned int eqid) 8752 { 8753 struct fw_eq_eth_cmd c; 8754 8755 memset(&c, 0, sizeof(c)); 8756 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8757 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8758 V_FW_EQ_ETH_CMD_PFN(pf) | 8759 V_FW_EQ_ETH_CMD_VFN(vf)); 8760 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8761 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8762 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8763 } 8764 8765 /** 8766 * t4_ctrl_eq_free - free a control egress queue 8767 * @adap: the adapter 8768 * @mbox: mailbox to use for the FW command 8769 * @pf: the PF owning the queue 8770 * @vf: the VF owning the queue 8771 * @eqid: egress queue id 8772 * 8773 * Frees a control egress queue. 8774 */ 8775 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8776 unsigned int vf, unsigned int eqid) 8777 { 8778 struct fw_eq_ctrl_cmd c; 8779 8780 memset(&c, 0, sizeof(c)); 8781 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8782 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8783 V_FW_EQ_CTRL_CMD_PFN(pf) | 8784 V_FW_EQ_CTRL_CMD_VFN(vf)); 8785 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8786 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8787 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8788 } 8789 8790 /** 8791 * t4_ofld_eq_free - free an offload egress queue 8792 * @adap: the adapter 8793 * @mbox: mailbox to use for the FW command 8794 * @pf: the PF owning the queue 8795 * @vf: the VF owning the queue 8796 * @eqid: egress queue id 8797 * 8798 * Frees a control egress queue. 8799 */ 8800 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8801 unsigned int vf, unsigned int eqid) 8802 { 8803 struct fw_eq_ofld_cmd c; 8804 8805 memset(&c, 0, sizeof(c)); 8806 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8807 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8808 V_FW_EQ_OFLD_CMD_PFN(pf) | 8809 V_FW_EQ_OFLD_CMD_VFN(vf)); 8810 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8811 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8812 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8813 } 8814 8815 /** 8816 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8817 * @link_down_rc: Link Down Reason Code 8818 * 8819 * Returns a string representation of the Link Down Reason Code. 8820 */ 8821 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8822 { 8823 static const char *reason[] = { 8824 "Link Down", 8825 "Remote Fault", 8826 "Auto-negotiation Failure", 8827 "Reserved3", 8828 "Insufficient Airflow", 8829 "Unable To Determine Reason", 8830 "No RX Signal Detected", 8831 "Reserved7", 8832 }; 8833 8834 if (link_down_rc >= ARRAY_SIZE(reason)) 8835 return "Bad Reason Code"; 8836 8837 return reason[link_down_rc]; 8838 } 8839 8840 /* 8841 * Return the highest speed set in the port capabilities, in Mb/s. 8842 */ 8843 unsigned int fwcap_to_speed(uint32_t caps) 8844 { 8845 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8846 do { \ 8847 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8848 return __speed; \ 8849 } while (0) 8850 8851 TEST_SPEED_RETURN(400G, 400000); 8852 TEST_SPEED_RETURN(200G, 200000); 8853 TEST_SPEED_RETURN(100G, 100000); 8854 TEST_SPEED_RETURN(50G, 50000); 8855 TEST_SPEED_RETURN(40G, 40000); 8856 TEST_SPEED_RETURN(25G, 25000); 8857 TEST_SPEED_RETURN(10G, 10000); 8858 TEST_SPEED_RETURN(1G, 1000); 8859 TEST_SPEED_RETURN(100M, 100); 8860 8861 #undef TEST_SPEED_RETURN 8862 8863 return 0; 8864 } 8865 8866 /* 8867 * Return the port capabilities bit for the given speed, which is in Mb/s. 8868 */ 8869 uint32_t speed_to_fwcap(unsigned int speed) 8870 { 8871 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8872 do { \ 8873 if (speed == __speed) \ 8874 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8875 } while (0) 8876 8877 TEST_SPEED_RETURN(400G, 400000); 8878 TEST_SPEED_RETURN(200G, 200000); 8879 TEST_SPEED_RETURN(100G, 100000); 8880 TEST_SPEED_RETURN(50G, 50000); 8881 TEST_SPEED_RETURN(40G, 40000); 8882 TEST_SPEED_RETURN(25G, 25000); 8883 TEST_SPEED_RETURN(10G, 10000); 8884 TEST_SPEED_RETURN(1G, 1000); 8885 TEST_SPEED_RETURN(100M, 100); 8886 8887 #undef TEST_SPEED_RETURN 8888 8889 return 0; 8890 } 8891 8892 /* 8893 * Return the port capabilities bit for the highest speed in the capabilities. 8894 */ 8895 uint32_t fwcap_top_speed(uint32_t caps) 8896 { 8897 #define TEST_SPEED_RETURN(__caps_speed) \ 8898 do { \ 8899 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8900 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8901 } while (0) 8902 8903 TEST_SPEED_RETURN(400G); 8904 TEST_SPEED_RETURN(200G); 8905 TEST_SPEED_RETURN(100G); 8906 TEST_SPEED_RETURN(50G); 8907 TEST_SPEED_RETURN(40G); 8908 TEST_SPEED_RETURN(25G); 8909 TEST_SPEED_RETURN(10G); 8910 TEST_SPEED_RETURN(1G); 8911 TEST_SPEED_RETURN(100M); 8912 8913 #undef TEST_SPEED_RETURN 8914 8915 return 0; 8916 } 8917 8918 /** 8919 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8920 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8921 * 8922 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8923 * 32-bit Port Capabilities value. 8924 */ 8925 static uint32_t lstatus_to_fwcap(u32 lstatus) 8926 { 8927 uint32_t linkattr = 0; 8928 8929 /* 8930 * Unfortunately the format of the Link Status in the old 8931 * 16-bit Port Information message isn't the same as the 8932 * 16-bit Port Capabilities bitfield used everywhere else ... 8933 */ 8934 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8935 linkattr |= FW_PORT_CAP32_FC_RX; 8936 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8937 linkattr |= FW_PORT_CAP32_FC_TX; 8938 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8939 linkattr |= FW_PORT_CAP32_SPEED_100M; 8940 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8941 linkattr |= FW_PORT_CAP32_SPEED_1G; 8942 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8943 linkattr |= FW_PORT_CAP32_SPEED_10G; 8944 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8945 linkattr |= FW_PORT_CAP32_SPEED_25G; 8946 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8947 linkattr |= FW_PORT_CAP32_SPEED_40G; 8948 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8949 linkattr |= FW_PORT_CAP32_SPEED_100G; 8950 8951 return linkattr; 8952 } 8953 8954 /* 8955 * Updates all fields owned by the common code in port_info and link_config 8956 * based on information provided by the firmware. Does not touch any 8957 * requested_* field. 8958 */ 8959 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8960 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8961 { 8962 struct link_config old_lc, *lc = &pi->link_cfg; 8963 unsigned char fc; 8964 u32 stat, linkattr; 8965 int old_ptype, old_mtype; 8966 8967 old_ptype = pi->port_type; 8968 old_mtype = pi->mod_type; 8969 old_lc = *lc; 8970 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8971 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8972 8973 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8974 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8975 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8976 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8977 8978 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8979 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8980 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8981 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8982 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8983 8984 linkattr = lstatus_to_fwcap(stat); 8985 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8986 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8987 8988 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8989 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8990 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8991 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8992 8993 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); 8994 lc->acaps = be32_to_cpu(p->u.info32.acaps32); 8995 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); 8996 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8997 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8998 8999 linkattr = be32_to_cpu(p->u.info32.linkattr32); 9000 } else { 9001 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 9002 return; 9003 } 9004 9005 lc->speed = fwcap_to_speed(linkattr); 9006 lc->fec = fwcap_to_fec(linkattr, true); 9007 9008 fc = 0; 9009 if (linkattr & FW_PORT_CAP32_FC_RX) 9010 fc |= PAUSE_RX; 9011 if (linkattr & FW_PORT_CAP32_FC_TX) 9012 fc |= PAUSE_TX; 9013 lc->fc = fc; 9014 9015 if (mod_changed != NULL) 9016 *mod_changed = false; 9017 if (link_changed != NULL) 9018 *link_changed = false; 9019 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 9020 old_lc.pcaps != lc->pcaps) { 9021 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) 9022 lc->fec_hint = fwcap_to_fec(lc->acaps, true); 9023 if (mod_changed != NULL) 9024 *mod_changed = true; 9025 } 9026 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 9027 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 9028 if (link_changed != NULL) 9029 *link_changed = true; 9030 } 9031 } 9032 9033 /** 9034 * t4_update_port_info - retrieve and update port information if changed 9035 * @pi: the port_info 9036 * 9037 * We issue a Get Port Information Command to the Firmware and, if 9038 * successful, we check to see if anything is different from what we 9039 * last recorded and update things accordingly. 9040 */ 9041 int t4_update_port_info(struct port_info *pi) 9042 { 9043 struct adapter *sc = pi->adapter; 9044 struct fw_port_cmd cmd; 9045 enum fw_port_action action; 9046 int ret; 9047 9048 memset(&cmd, 0, sizeof(cmd)); 9049 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 9050 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9051 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 9052 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 9053 FW_PORT_ACTION_GET_PORT_INFO; 9054 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 9055 FW_LEN16(cmd)); 9056 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 9057 if (ret) 9058 return ret; 9059 9060 handle_port_info(pi, &cmd, action, NULL, NULL); 9061 return 0; 9062 } 9063 9064 /** 9065 * t4_handle_fw_rpl - process a FW reply message 9066 * @adap: the adapter 9067 * @rpl: start of the FW message 9068 * 9069 * Processes a FW message, such as link state change messages. 9070 */ 9071 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 9072 { 9073 u8 opcode = *(const u8 *)rpl; 9074 const struct fw_port_cmd *p = (const void *)rpl; 9075 enum fw_port_action action = 9076 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 9077 bool mod_changed, link_changed; 9078 9079 if (opcode == FW_PORT_CMD && 9080 (action == FW_PORT_ACTION_GET_PORT_INFO || 9081 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 9082 /* link/module state change message */ 9083 int i; 9084 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 9085 struct port_info *pi = NULL; 9086 9087 for_each_port(adap, i) { 9088 pi = adap2pinfo(adap, i); 9089 if (pi->tx_chan == chan) 9090 break; 9091 } 9092 9093 PORT_LOCK(pi); 9094 handle_port_info(pi, p, action, &mod_changed, &link_changed); 9095 PORT_UNLOCK(pi); 9096 if (mod_changed) 9097 t4_os_portmod_changed(pi); 9098 if (link_changed) { 9099 PORT_LOCK(pi); 9100 t4_os_link_changed(pi); 9101 PORT_UNLOCK(pi); 9102 } 9103 } else { 9104 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 9105 return -EINVAL; 9106 } 9107 return 0; 9108 } 9109 9110 /** 9111 * get_pci_mode - determine a card's PCI mode 9112 * @adapter: the adapter 9113 * @p: where to store the PCI settings 9114 * 9115 * Determines a card's PCI mode and associated parameters, such as speed 9116 * and width. 9117 */ 9118 static void get_pci_mode(struct adapter *adapter, 9119 struct pci_params *p) 9120 { 9121 u16 val; 9122 u32 pcie_cap; 9123 9124 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9125 if (pcie_cap) { 9126 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 9127 p->speed = val & PCI_EXP_LNKSTA_CLS; 9128 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 9129 } 9130 } 9131 9132 struct flash_desc { 9133 u32 vendor_and_model_id; 9134 u32 size_mb; 9135 }; 9136 9137 int t4_get_flash_params(struct adapter *adapter) 9138 { 9139 /* 9140 * Table for non-standard supported Flash parts. Note, all Flash 9141 * parts must have 64KB sectors. 9142 */ 9143 static struct flash_desc supported_flash[] = { 9144 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 9145 }; 9146 9147 int ret; 9148 u32 flashid = 0; 9149 unsigned int part, manufacturer; 9150 unsigned int density, size = 0; 9151 9152 9153 /* 9154 * Issue a Read ID Command to the Flash part. We decode supported 9155 * Flash parts and their sizes from this. There's a newer Query 9156 * Command which can retrieve detailed geometry information but many 9157 * Flash parts don't support it. 9158 */ 9159 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 9160 if (!ret) 9161 ret = sf1_read(adapter, 3, 0, 1, &flashid); 9162 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 9163 if (ret < 0) 9164 return ret; 9165 9166 /* 9167 * Check to see if it's one of our non-standard supported Flash parts. 9168 */ 9169 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 9170 if (supported_flash[part].vendor_and_model_id == flashid) { 9171 adapter->params.sf_size = 9172 supported_flash[part].size_mb; 9173 adapter->params.sf_nsec = 9174 adapter->params.sf_size / SF_SEC_SIZE; 9175 goto found; 9176 } 9177 9178 /* 9179 * Decode Flash part size. The code below looks repetative with 9180 * common encodings, but that's not guaranteed in the JEDEC 9181 * specification for the Read JADEC ID command. The only thing that 9182 * we're guaranteed by the JADEC specification is where the 9183 * Manufacturer ID is in the returned result. After that each 9184 * Manufacturer ~could~ encode things completely differently. 9185 * Note, all Flash parts must have 64KB sectors. 9186 */ 9187 manufacturer = flashid & 0xff; 9188 switch (manufacturer) { 9189 case 0x20: /* Micron/Numonix */ 9190 /* 9191 * This Density -> Size decoding table is taken from Micron 9192 * Data Sheets. 9193 */ 9194 density = (flashid >> 16) & 0xff; 9195 switch (density) { 9196 case 0x14: size = 1 << 20; break; /* 1MB */ 9197 case 0x15: size = 1 << 21; break; /* 2MB */ 9198 case 0x16: size = 1 << 22; break; /* 4MB */ 9199 case 0x17: size = 1 << 23; break; /* 8MB */ 9200 case 0x18: size = 1 << 24; break; /* 16MB */ 9201 case 0x19: size = 1 << 25; break; /* 32MB */ 9202 case 0x20: size = 1 << 26; break; /* 64MB */ 9203 case 0x21: size = 1 << 27; break; /* 128MB */ 9204 case 0x22: size = 1 << 28; break; /* 256MB */ 9205 } 9206 break; 9207 9208 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 9209 /* 9210 * This Density -> Size decoding table is taken from ISSI 9211 * Data Sheets. 9212 */ 9213 density = (flashid >> 16) & 0xff; 9214 switch (density) { 9215 case 0x16: size = 1 << 25; break; /* 32MB */ 9216 case 0x17: size = 1 << 26; break; /* 64MB */ 9217 } 9218 break; 9219 9220 case 0xc2: /* Macronix */ 9221 /* 9222 * This Density -> Size decoding table is taken from Macronix 9223 * Data Sheets. 9224 */ 9225 density = (flashid >> 16) & 0xff; 9226 switch (density) { 9227 case 0x17: size = 1 << 23; break; /* 8MB */ 9228 case 0x18: size = 1 << 24; break; /* 16MB */ 9229 } 9230 break; 9231 9232 case 0xef: /* Winbond */ 9233 /* 9234 * This Density -> Size decoding table is taken from Winbond 9235 * Data Sheets. 9236 */ 9237 density = (flashid >> 16) & 0xff; 9238 switch (density) { 9239 case 0x17: size = 1 << 23; break; /* 8MB */ 9240 case 0x18: size = 1 << 24; break; /* 16MB */ 9241 } 9242 break; 9243 } 9244 9245 /* If we didn't recognize the FLASH part, that's no real issue: the 9246 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 9247 * use a FLASH part which is at least 4MB in size and has 64KB 9248 * sectors. The unrecognized FLASH part is likely to be much larger 9249 * than 4MB, but that's all we really need. 9250 */ 9251 if (size == 0) { 9252 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 9253 size = 1 << 22; 9254 } 9255 9256 /* 9257 * Store decoded Flash size and fall through into vetting code. 9258 */ 9259 adapter->params.sf_size = size; 9260 adapter->params.sf_nsec = size / SF_SEC_SIZE; 9261 9262 found: 9263 /* 9264 * We should ~probably~ reject adapters with FLASHes which are too 9265 * small but we have some legacy FPGAs with small FLASHes that we'd 9266 * still like to use. So instead we emit a scary message ... 9267 */ 9268 if (adapter->params.sf_size < FLASH_MIN_SIZE) 9269 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 9270 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 9271 9272 return 0; 9273 } 9274 9275 static void set_pcie_completion_timeout(struct adapter *adapter, 9276 u8 range) 9277 { 9278 u16 val; 9279 u32 pcie_cap; 9280 9281 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9282 if (pcie_cap) { 9283 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 9284 val &= 0xfff0; 9285 val |= range ; 9286 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 9287 } 9288 } 9289 9290 const struct chip_params *t4_get_chip_params(int chipid) 9291 { 9292 static const struct chip_params chip_params[] = { 9293 { 9294 /* T4 */ 9295 .nchan = NCHAN, 9296 .pm_stats_cnt = PM_NSTATS, 9297 .cng_ch_bits_log = 2, 9298 .nsched_cls = 15, 9299 .cim_num_obq = CIM_NUM_OBQ, 9300 .filter_opt_len = FILTER_OPT_LEN, 9301 .mps_rplc_size = 128, 9302 .vfcount = 128, 9303 .sge_fl_db = F_DBPRIO, 9304 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 9305 .rss_nentries = RSS_NENTRIES, 9306 .cim_la_size = CIMLA_SIZE, 9307 }, 9308 { 9309 /* T5 */ 9310 .nchan = NCHAN, 9311 .pm_stats_cnt = PM_NSTATS, 9312 .cng_ch_bits_log = 2, 9313 .nsched_cls = 16, 9314 .cim_num_obq = CIM_NUM_OBQ_T5, 9315 .filter_opt_len = T5_FILTER_OPT_LEN, 9316 .mps_rplc_size = 128, 9317 .vfcount = 128, 9318 .sge_fl_db = F_DBPRIO | F_DBTYPE, 9319 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9320 .rss_nentries = RSS_NENTRIES, 9321 .cim_la_size = CIMLA_SIZE, 9322 }, 9323 { 9324 /* T6 */ 9325 .nchan = T6_NCHAN, 9326 .pm_stats_cnt = T6_PM_NSTATS, 9327 .cng_ch_bits_log = 3, 9328 .nsched_cls = 16, 9329 .cim_num_obq = CIM_NUM_OBQ_T5, 9330 .filter_opt_len = T5_FILTER_OPT_LEN, 9331 .mps_rplc_size = 256, 9332 .vfcount = 256, 9333 .sge_fl_db = 0, 9334 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9335 .rss_nentries = T6_RSS_NENTRIES, 9336 .cim_la_size = CIMLA_SIZE_T6, 9337 }, 9338 }; 9339 9340 chipid -= CHELSIO_T4; 9341 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 9342 return NULL; 9343 9344 return &chip_params[chipid]; 9345 } 9346 9347 /** 9348 * t4_prep_adapter - prepare SW and HW for operation 9349 * @adapter: the adapter 9350 * @buf: temporary space of at least VPD_LEN size provided by the caller. 9351 * 9352 * Initialize adapter SW state for the various HW modules, set initial 9353 * values for some adapter tunables, take PHYs out of reset, and 9354 * initialize the MDIO interface. 9355 */ 9356 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 9357 { 9358 int ret; 9359 uint16_t device_id; 9360 uint32_t pl_rev; 9361 9362 get_pci_mode(adapter, &adapter->params.pci); 9363 9364 pl_rev = t4_read_reg(adapter, A_PL_REV); 9365 adapter->params.chipid = G_CHIPID(pl_rev); 9366 adapter->params.rev = G_REV(pl_rev); 9367 if (adapter->params.chipid == 0) { 9368 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 9369 adapter->params.chipid = CHELSIO_T4; 9370 9371 /* T4A1 chip is not supported */ 9372 if (adapter->params.rev == 1) { 9373 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 9374 return -EINVAL; 9375 } 9376 } 9377 9378 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 9379 if (adapter->chip_params == NULL) 9380 return -EINVAL; 9381 9382 adapter->params.pci.vpd_cap_addr = 9383 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 9384 9385 ret = t4_get_flash_params(adapter); 9386 if (ret < 0) 9387 return ret; 9388 9389 /* Cards with real ASICs have the chipid in the PCIe device id */ 9390 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 9391 if (device_id >> 12 == chip_id(adapter)) 9392 adapter->params.cim_la_size = adapter->chip_params->cim_la_size; 9393 else { 9394 /* FPGA */ 9395 adapter->params.fpga = 1; 9396 adapter->params.cim_la_size = 2 * adapter->chip_params->cim_la_size; 9397 } 9398 9399 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 9400 if (ret < 0) 9401 return ret; 9402 9403 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 9404 9405 /* 9406 * Default port and clock for debugging in case we can't reach FW. 9407 */ 9408 adapter->params.nports = 1; 9409 adapter->params.portvec = 1; 9410 adapter->params.vpd.cclk = 50000; 9411 9412 /* Set pci completion timeout value to 4 seconds. */ 9413 set_pcie_completion_timeout(adapter, 0xd); 9414 return 0; 9415 } 9416 9417 /** 9418 * t4_shutdown_adapter - shut down adapter, host & wire 9419 * @adapter: the adapter 9420 * 9421 * Perform an emergency shutdown of the adapter and stop it from 9422 * continuing any further communication on the ports or DMA to the 9423 * host. This is typically used when the adapter and/or firmware 9424 * have crashed and we want to prevent any further accidental 9425 * communication with the rest of the world. This will also force 9426 * the port Link Status to go down -- if register writes work -- 9427 * which should help our peers figure out that we're down. 9428 */ 9429 int t4_shutdown_adapter(struct adapter *adapter) 9430 { 9431 int port; 9432 const bool bt = adapter->bt_map != 0; 9433 9434 t4_intr_disable(adapter); 9435 if (bt) 9436 t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000); 9437 for_each_port(adapter, port) { 9438 u32 a_port_cfg = is_t4(adapter) ? 9439 PORT_REG(port, A_XGMAC_PORT_CFG) : 9440 T5_PORT_REG(port, A_MAC_PORT_CFG); 9441 9442 t4_write_reg(adapter, a_port_cfg, 9443 t4_read_reg(adapter, a_port_cfg) 9444 & ~V_SIGNAL_DET(1)); 9445 if (!bt) { 9446 u32 hss_cfg0 = is_t4(adapter) ? 9447 PORT_REG(port, A_XGMAC_PORT_HSS_CFG0) : 9448 T5_PORT_REG(port, A_MAC_PORT_HSS_CFG0); 9449 t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB | 9450 F_HSSPDWNPLLA | F_HSSPLLBYPB | F_HSSPLLBYPA, 9451 F_HSSPDWNPLLB | F_HSSPDWNPLLA | F_HSSPLLBYPB | 9452 F_HSSPLLBYPA); 9453 } 9454 } 9455 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9456 9457 return 0; 9458 } 9459 9460 /** 9461 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9462 * @adapter: the adapter 9463 * @qid: the Queue ID 9464 * @qtype: the Ingress or Egress type for @qid 9465 * @user: true if this request is for a user mode queue 9466 * @pbar2_qoffset: BAR2 Queue Offset 9467 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9468 * 9469 * Returns the BAR2 SGE Queue Registers information associated with the 9470 * indicated Absolute Queue ID. These are passed back in return value 9471 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9472 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9473 * 9474 * This may return an error which indicates that BAR2 SGE Queue 9475 * registers aren't available. If an error is not returned, then the 9476 * following values are returned: 9477 * 9478 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9479 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9480 * 9481 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9482 * require the "Inferred Queue ID" ability may be used. E.g. the 9483 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9484 * then these "Inferred Queue ID" register may not be used. 9485 */ 9486 int t4_bar2_sge_qregs(struct adapter *adapter, 9487 unsigned int qid, 9488 enum t4_bar2_qtype qtype, 9489 int user, 9490 u64 *pbar2_qoffset, 9491 unsigned int *pbar2_qid) 9492 { 9493 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9494 u64 bar2_page_offset, bar2_qoffset; 9495 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9496 9497 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9498 * mode queues. 9499 */ 9500 if (!user && is_t4(adapter)) 9501 return -EINVAL; 9502 9503 /* Get our SGE Page Size parameters. 9504 */ 9505 page_shift = adapter->params.sge.page_shift; 9506 page_size = 1 << page_shift; 9507 9508 /* Get the right Queues per Page parameters for our Queue. 9509 */ 9510 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9511 ? adapter->params.sge.eq_s_qpp 9512 : adapter->params.sge.iq_s_qpp); 9513 qpp_mask = (1 << qpp_shift) - 1; 9514 9515 /* Calculate the basics of the BAR2 SGE Queue register area: 9516 * o The BAR2 page the Queue registers will be in. 9517 * o The BAR2 Queue ID. 9518 * o The BAR2 Queue ID Offset into the BAR2 page. 9519 */ 9520 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9521 bar2_qid = qid & qpp_mask; 9522 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9523 9524 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9525 * hardware will infer the Absolute Queue ID simply from the writes to 9526 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9527 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9528 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9529 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9530 * from the BAR2 Page and BAR2 Queue ID. 9531 * 9532 * One important censequence of this is that some BAR2 SGE registers 9533 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9534 * there. But other registers synthesize the SGE Queue ID purely 9535 * from the writes to the registers -- the Write Combined Doorbell 9536 * Buffer is a good example. These BAR2 SGE Registers are only 9537 * available for those BAR2 SGE Register areas where the SGE Absolute 9538 * Queue ID can be inferred from simple writes. 9539 */ 9540 bar2_qoffset = bar2_page_offset; 9541 bar2_qinferred = (bar2_qid_offset < page_size); 9542 if (bar2_qinferred) { 9543 bar2_qoffset += bar2_qid_offset; 9544 bar2_qid = 0; 9545 } 9546 9547 *pbar2_qoffset = bar2_qoffset; 9548 *pbar2_qid = bar2_qid; 9549 return 0; 9550 } 9551 9552 /** 9553 * t4_init_devlog_params - initialize adapter->params.devlog 9554 * @adap: the adapter 9555 * @fw_attach: whether we can talk to the firmware 9556 * 9557 * Initialize various fields of the adapter's Firmware Device Log 9558 * Parameters structure. 9559 */ 9560 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9561 { 9562 struct devlog_params *dparams = &adap->params.devlog; 9563 u32 pf_dparams; 9564 unsigned int devlog_meminfo; 9565 struct fw_devlog_cmd devlog_cmd; 9566 int ret; 9567 9568 /* If we're dealing with newer firmware, the Device Log Paramerters 9569 * are stored in a designated register which allows us to access the 9570 * Device Log even if we can't talk to the firmware. 9571 */ 9572 pf_dparams = 9573 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9574 if (pf_dparams) { 9575 unsigned int nentries, nentries128; 9576 9577 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9578 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9579 9580 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9581 nentries = (nentries128 + 1) * 128; 9582 dparams->size = nentries * sizeof(struct fw_devlog_e); 9583 9584 return 0; 9585 } 9586 9587 /* 9588 * For any failing returns ... 9589 */ 9590 memset(dparams, 0, sizeof *dparams); 9591 9592 /* 9593 * If we can't talk to the firmware, there's really nothing we can do 9594 * at this point. 9595 */ 9596 if (!fw_attach) 9597 return -ENXIO; 9598 9599 /* Otherwise, ask the firmware for it's Device Log Parameters. 9600 */ 9601 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9602 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9603 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9604 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9605 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9606 &devlog_cmd); 9607 if (ret) 9608 return ret; 9609 9610 devlog_meminfo = 9611 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9612 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9613 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9614 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9615 9616 return 0; 9617 } 9618 9619 /** 9620 * t4_init_sge_params - initialize adap->params.sge 9621 * @adapter: the adapter 9622 * 9623 * Initialize various fields of the adapter's SGE Parameters structure. 9624 */ 9625 int t4_init_sge_params(struct adapter *adapter) 9626 { 9627 u32 r; 9628 struct sge_params *sp = &adapter->params.sge; 9629 unsigned i, tscale = 1; 9630 9631 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9632 sp->counter_val[0] = G_THRESHOLD_0(r); 9633 sp->counter_val[1] = G_THRESHOLD_1(r); 9634 sp->counter_val[2] = G_THRESHOLD_2(r); 9635 sp->counter_val[3] = G_THRESHOLD_3(r); 9636 9637 if (chip_id(adapter) >= CHELSIO_T6) { 9638 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9639 tscale = G_TSCALE(r); 9640 if (tscale == 0) 9641 tscale = 1; 9642 else 9643 tscale += 2; 9644 } 9645 9646 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9647 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9648 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9649 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9650 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9651 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9652 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9653 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9654 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9655 9656 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9657 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9658 if (is_t4(adapter)) 9659 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9660 else if (is_t5(adapter)) 9661 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9662 else 9663 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9664 9665 /* egress queues: log2 of # of doorbells per BAR2 page */ 9666 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9667 r >>= S_QUEUESPERPAGEPF0 + 9668 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9669 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9670 9671 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9672 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9673 r >>= S_QUEUESPERPAGEPF0 + 9674 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9675 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9676 9677 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9678 r >>= S_HOSTPAGESIZEPF0 + 9679 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9680 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9681 9682 r = t4_read_reg(adapter, A_SGE_CONTROL); 9683 sp->sge_control = r; 9684 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9685 sp->fl_pktshift = G_PKTSHIFT(r); 9686 if (chip_id(adapter) <= CHELSIO_T5) { 9687 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9688 X_INGPADBOUNDARY_SHIFT); 9689 } else { 9690 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9691 X_T6_INGPADBOUNDARY_SHIFT); 9692 } 9693 if (is_t4(adapter)) 9694 sp->pack_boundary = sp->pad_boundary; 9695 else { 9696 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9697 if (G_INGPACKBOUNDARY(r) == 0) 9698 sp->pack_boundary = 16; 9699 else 9700 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9701 } 9702 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9703 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9704 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9705 9706 return 0; 9707 } 9708 9709 /* Convert the LE's hardware hash mask to a shorter filter mask. */ 9710 static inline uint16_t 9711 hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode) 9712 { 9713 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 9714 int i; 9715 uint16_t filter_mask; 9716 uint64_t mask; /* field mask */ 9717 9718 filter_mask = 0; 9719 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 9720 if ((filter_mode & (1 << i)) == 0) 9721 continue; 9722 mask = (1 << width[i]) - 1; 9723 if ((hashmask & mask) == mask) 9724 filter_mask |= 1 << i; 9725 hashmask >>= width[i]; 9726 } 9727 9728 return (filter_mask); 9729 } 9730 9731 /* 9732 * Read and cache the adapter's compressed filter mode and ingress config. 9733 */ 9734 static void 9735 read_filter_mode_and_ingress_config(struct adapter *adap) 9736 { 9737 int rc; 9738 uint32_t v, param[2], val[2]; 9739 struct tp_params *tpp = &adap->params.tp; 9740 uint64_t hash_mask; 9741 9742 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9743 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9744 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 9745 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9746 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9747 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 9748 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); 9749 if (rc == 0) { 9750 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); 9751 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); 9752 tpp->vnic_mode = val[1]; 9753 } else { 9754 /* 9755 * Old firmware. Read filter mode/mask and ingress config 9756 * straight from the hardware. 9757 */ 9758 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true); 9759 tpp->filter_mode = v & 0xffff; 9760 9761 hash_mask = 0; 9762 if (chip_id(adap) > CHELSIO_T4) { 9763 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9764 hash_mask = v; 9765 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9766 hash_mask |= (u64)v << 32; 9767 } 9768 tpp->filter_mask = hashmask_to_filtermask(hash_mask, 9769 tpp->filter_mode); 9770 9771 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true); 9772 if (v & F_VNIC) 9773 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; 9774 else 9775 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; 9776 } 9777 9778 /* 9779 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9780 * shift positions of several elements of the Compressed Filter Tuple 9781 * for this adapter which we need frequently ... 9782 */ 9783 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9784 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9785 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9786 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9787 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9788 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9789 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9790 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9791 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9792 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9793 } 9794 9795 /** 9796 * t4_init_tp_params - initialize adap->params.tp 9797 * @adap: the adapter 9798 * 9799 * Initialize various fields of the adapter's TP Parameters structure. 9800 */ 9801 int t4_init_tp_params(struct adapter *adap) 9802 { 9803 int chan; 9804 u32 tx_len, rx_len, r, v; 9805 struct tp_params *tpp = &adap->params.tp; 9806 9807 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9808 tpp->tre = G_TIMERRESOLUTION(v); 9809 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9810 9811 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9812 for (chan = 0; chan < MAX_NCHAN; chan++) 9813 tpp->tx_modq[chan] = chan; 9814 9815 read_filter_mode_and_ingress_config(adap); 9816 9817 if (chip_id(adap) > CHELSIO_T5) { 9818 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9819 tpp->rx_pkt_encap = v & F_CRXPKTENC; 9820 } else 9821 tpp->rx_pkt_encap = false; 9822 9823 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE); 9824 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE); 9825 9826 r = t4_read_reg(adap, A_TP_PARA_REG2); 9827 rx_len = min(rx_len, G_MAXRXDATA(r)); 9828 tx_len = min(tx_len, G_MAXRXDATA(r)); 9829 9830 r = t4_read_reg(adap, A_TP_PARA_REG7); 9831 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 9832 rx_len = min(rx_len, v); 9833 tx_len = min(tx_len, v); 9834 9835 tpp->max_tx_pdu = tx_len; 9836 tpp->max_rx_pdu = rx_len; 9837 9838 return 0; 9839 } 9840 9841 /** 9842 * t4_filter_field_shift - calculate filter field shift 9843 * @adap: the adapter 9844 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9845 * 9846 * Return the shift position of a filter field within the Compressed 9847 * Filter Tuple. The filter field is specified via its selection bit 9848 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9849 */ 9850 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9851 { 9852 const unsigned int filter_mode = adap->params.tp.filter_mode; 9853 unsigned int sel; 9854 int field_shift; 9855 9856 if ((filter_mode & filter_sel) == 0) 9857 return -1; 9858 9859 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9860 switch (filter_mode & sel) { 9861 case F_FCOE: 9862 field_shift += W_FT_FCOE; 9863 break; 9864 case F_PORT: 9865 field_shift += W_FT_PORT; 9866 break; 9867 case F_VNIC_ID: 9868 field_shift += W_FT_VNIC_ID; 9869 break; 9870 case F_VLAN: 9871 field_shift += W_FT_VLAN; 9872 break; 9873 case F_TOS: 9874 field_shift += W_FT_TOS; 9875 break; 9876 case F_PROTOCOL: 9877 field_shift += W_FT_PROTOCOL; 9878 break; 9879 case F_ETHERTYPE: 9880 field_shift += W_FT_ETHERTYPE; 9881 break; 9882 case F_MACMATCH: 9883 field_shift += W_FT_MACMATCH; 9884 break; 9885 case F_MPSHITTYPE: 9886 field_shift += W_FT_MPSHITTYPE; 9887 break; 9888 case F_FRAGMENTATION: 9889 field_shift += W_FT_FRAGMENTATION; 9890 break; 9891 } 9892 } 9893 return field_shift; 9894 } 9895 9896 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9897 { 9898 u8 addr[6]; 9899 int ret, i, j; 9900 struct port_info *p = adap2pinfo(adap, port_id); 9901 u32 param, val; 9902 struct vi_info *vi = &p->vi[0]; 9903 9904 for (i = 0, j = -1; i <= p->port_id; i++) { 9905 do { 9906 j++; 9907 } while ((adap->params.portvec & (1 << j)) == 0); 9908 } 9909 9910 p->tx_chan = j; 9911 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9912 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9913 p->rx_c_chan = t4_get_rx_c_chan(adap, j); 9914 p->lport = j; 9915 9916 if (!(adap->flags & IS_VF) || 9917 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9918 t4_update_port_info(p); 9919 } 9920 9921 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9922 &vi->vfvld, &vi->vin); 9923 if (ret < 0) 9924 return ret; 9925 9926 vi->viid = ret; 9927 t4_os_set_hw_addr(p, addr); 9928 9929 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9930 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9931 V_FW_PARAMS_PARAM_YZ(vi->viid); 9932 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9933 if (ret) 9934 vi->rss_base = 0xffff; 9935 else { 9936 /* MPASS((val >> 16) == rss_size); */ 9937 vi->rss_base = val & 0xffff; 9938 } 9939 9940 return 0; 9941 } 9942 9943 /** 9944 * t4_read_cimq_cfg - read CIM queue configuration 9945 * @adap: the adapter 9946 * @base: holds the queue base addresses in bytes 9947 * @size: holds the queue sizes in bytes 9948 * @thres: holds the queue full thresholds in bytes 9949 * 9950 * Returns the current configuration of the CIM queues, starting with 9951 * the IBQs, then the OBQs. 9952 */ 9953 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9954 { 9955 unsigned int i, v; 9956 int cim_num_obq = adap->chip_params->cim_num_obq; 9957 9958 for (i = 0; i < CIM_NUM_IBQ; i++) { 9959 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9960 V_QUENUMSELECT(i)); 9961 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9962 /* value is in 256-byte units */ 9963 *base++ = G_CIMQBASE(v) * 256; 9964 *size++ = G_CIMQSIZE(v) * 256; 9965 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9966 } 9967 for (i = 0; i < cim_num_obq; i++) { 9968 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9969 V_QUENUMSELECT(i)); 9970 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9971 /* value is in 256-byte units */ 9972 *base++ = G_CIMQBASE(v) * 256; 9973 *size++ = G_CIMQSIZE(v) * 256; 9974 } 9975 } 9976 9977 /** 9978 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9979 * @adap: the adapter 9980 * @qid: the queue index 9981 * @data: where to store the queue contents 9982 * @n: capacity of @data in 32-bit words 9983 * 9984 * Reads the contents of the selected CIM queue starting at address 0 up 9985 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9986 * error and the number of 32-bit words actually read on success. 9987 */ 9988 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9989 { 9990 int i, err, attempts; 9991 unsigned int addr; 9992 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9993 9994 if (qid > 5 || (n & 3)) 9995 return -EINVAL; 9996 9997 addr = qid * nwords; 9998 if (n > nwords) 9999 n = nwords; 10000 10001 /* It might take 3-10ms before the IBQ debug read access is allowed. 10002 * Wait for 1 Sec with a delay of 1 usec. 10003 */ 10004 attempts = 1000000; 10005 10006 for (i = 0; i < n; i++, addr++) { 10007 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 10008 F_IBQDBGEN); 10009 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 10010 attempts, 1); 10011 if (err) 10012 return err; 10013 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 10014 } 10015 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 10016 return i; 10017 } 10018 10019 /** 10020 * t4_read_cim_obq - read the contents of a CIM outbound queue 10021 * @adap: the adapter 10022 * @qid: the queue index 10023 * @data: where to store the queue contents 10024 * @n: capacity of @data in 32-bit words 10025 * 10026 * Reads the contents of the selected CIM queue starting at address 0 up 10027 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 10028 * error and the number of 32-bit words actually read on success. 10029 */ 10030 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 10031 { 10032 int i, err; 10033 unsigned int addr, v, nwords; 10034 int cim_num_obq = adap->chip_params->cim_num_obq; 10035 10036 if ((qid > (cim_num_obq - 1)) || (n & 3)) 10037 return -EINVAL; 10038 10039 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 10040 V_QUENUMSELECT(qid)); 10041 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 10042 10043 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 10044 nwords = G_CIMQSIZE(v) * 64; /* same */ 10045 if (n > nwords) 10046 n = nwords; 10047 10048 for (i = 0; i < n; i++, addr++) { 10049 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 10050 F_OBQDBGEN); 10051 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 10052 2, 1); 10053 if (err) 10054 return err; 10055 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 10056 } 10057 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 10058 return i; 10059 } 10060 10061 enum { 10062 CIM_QCTL_BASE = 0, 10063 CIM_CTL_BASE = 0x2000, 10064 CIM_PBT_ADDR_BASE = 0x2800, 10065 CIM_PBT_LRF_BASE = 0x3000, 10066 CIM_PBT_DATA_BASE = 0x3800 10067 }; 10068 10069 /** 10070 * t4_cim_read - read a block from CIM internal address space 10071 * @adap: the adapter 10072 * @addr: the start address within the CIM address space 10073 * @n: number of words to read 10074 * @valp: where to store the result 10075 * 10076 * Reads a block of 4-byte words from the CIM intenal address space. 10077 */ 10078 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 10079 unsigned int *valp) 10080 { 10081 int ret = 0; 10082 10083 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10084 return -EBUSY; 10085 10086 for ( ; !ret && n--; addr += 4) { 10087 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 10088 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10089 0, 5, 2); 10090 if (!ret) 10091 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 10092 } 10093 return ret; 10094 } 10095 10096 /** 10097 * t4_cim_write - write a block into CIM internal address space 10098 * @adap: the adapter 10099 * @addr: the start address within the CIM address space 10100 * @n: number of words to write 10101 * @valp: set of values to write 10102 * 10103 * Writes a block of 4-byte words into the CIM intenal address space. 10104 */ 10105 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 10106 const unsigned int *valp) 10107 { 10108 int ret = 0; 10109 10110 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10111 return -EBUSY; 10112 10113 for ( ; !ret && n--; addr += 4) { 10114 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 10115 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 10116 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10117 0, 5, 2); 10118 } 10119 return ret; 10120 } 10121 10122 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 10123 unsigned int val) 10124 { 10125 return t4_cim_write(adap, addr, 1, &val); 10126 } 10127 10128 /** 10129 * t4_cim_ctl_read - read a block from CIM control region 10130 * @adap: the adapter 10131 * @addr: the start address within the CIM control region 10132 * @n: number of words to read 10133 * @valp: where to store the result 10134 * 10135 * Reads a block of 4-byte words from the CIM control region. 10136 */ 10137 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 10138 unsigned int *valp) 10139 { 10140 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 10141 } 10142 10143 /** 10144 * t4_cim_read_la - read CIM LA capture buffer 10145 * @adap: the adapter 10146 * @la_buf: where to store the LA data 10147 * @wrptr: the HW write pointer within the capture buffer 10148 * 10149 * Reads the contents of the CIM LA buffer with the most recent entry at 10150 * the end of the returned data and with the entry at @wrptr first. 10151 * We try to leave the LA in the running state we find it in. 10152 */ 10153 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 10154 { 10155 int i, ret; 10156 unsigned int cfg, val, idx; 10157 10158 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 10159 if (ret) 10160 return ret; 10161 10162 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 10163 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 10164 if (ret) 10165 return ret; 10166 } 10167 10168 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10169 if (ret) 10170 goto restart; 10171 10172 idx = G_UPDBGLAWRPTR(val); 10173 if (wrptr) 10174 *wrptr = idx; 10175 10176 for (i = 0; i < adap->params.cim_la_size; i++) { 10177 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10178 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 10179 if (ret) 10180 break; 10181 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10182 if (ret) 10183 break; 10184 if (val & F_UPDBGLARDEN) { 10185 ret = -ETIMEDOUT; 10186 break; 10187 } 10188 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 10189 if (ret) 10190 break; 10191 10192 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 10193 * identify the 32-bit portion of the full 312-bit data 10194 */ 10195 if (is_t6(adap) && (idx & 0xf) >= 9) 10196 idx = (idx & 0xff0) + 0x10; 10197 else 10198 idx++; 10199 /* address can't exceed 0xfff */ 10200 idx &= M_UPDBGLARDPTR; 10201 } 10202 restart: 10203 if (cfg & F_UPDBGLAEN) { 10204 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10205 cfg & ~F_UPDBGLARDEN); 10206 if (!ret) 10207 ret = r; 10208 } 10209 return ret; 10210 } 10211 10212 /** 10213 * t4_tp_read_la - read TP LA capture buffer 10214 * @adap: the adapter 10215 * @la_buf: where to store the LA data 10216 * @wrptr: the HW write pointer within the capture buffer 10217 * 10218 * Reads the contents of the TP LA buffer with the most recent entry at 10219 * the end of the returned data and with the entry at @wrptr first. 10220 * We leave the LA in the running state we find it in. 10221 */ 10222 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 10223 { 10224 bool last_incomplete; 10225 unsigned int i, cfg, val, idx; 10226 10227 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 10228 if (cfg & F_DBGLAENABLE) /* freeze LA */ 10229 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10230 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 10231 10232 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 10233 idx = G_DBGLAWPTR(val); 10234 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 10235 if (last_incomplete) 10236 idx = (idx + 1) & M_DBGLARPTR; 10237 if (wrptr) 10238 *wrptr = idx; 10239 10240 val &= 0xffff; 10241 val &= ~V_DBGLARPTR(M_DBGLARPTR); 10242 val |= adap->params.tp.la_mask; 10243 10244 for (i = 0; i < TPLA_SIZE; i++) { 10245 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 10246 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 10247 idx = (idx + 1) & M_DBGLARPTR; 10248 } 10249 10250 /* Wipe out last entry if it isn't valid */ 10251 if (last_incomplete) 10252 la_buf[TPLA_SIZE - 1] = ~0ULL; 10253 10254 if (cfg & F_DBGLAENABLE) /* restore running state */ 10255 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10256 cfg | adap->params.tp.la_mask); 10257 } 10258 10259 /* 10260 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 10261 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 10262 * state for more than the Warning Threshold then we'll issue a warning about 10263 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 10264 * appears to be hung every Warning Repeat second till the situation clears. 10265 * If the situation clears, we'll note that as well. 10266 */ 10267 #define SGE_IDMA_WARN_THRESH 1 10268 #define SGE_IDMA_WARN_REPEAT 300 10269 10270 /** 10271 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 10272 * @adapter: the adapter 10273 * @idma: the adapter IDMA Monitor state 10274 * 10275 * Initialize the state of an SGE Ingress DMA Monitor. 10276 */ 10277 void t4_idma_monitor_init(struct adapter *adapter, 10278 struct sge_idma_monitor_state *idma) 10279 { 10280 /* Initialize the state variables for detecting an SGE Ingress DMA 10281 * hang. The SGE has internal counters which count up on each clock 10282 * tick whenever the SGE finds its Ingress DMA State Engines in the 10283 * same state they were on the previous clock tick. The clock used is 10284 * the Core Clock so we have a limit on the maximum "time" they can 10285 * record; typically a very small number of seconds. For instance, 10286 * with a 600MHz Core Clock, we can only count up to a bit more than 10287 * 7s. So we'll synthesize a larger counter in order to not run the 10288 * risk of having the "timers" overflow and give us the flexibility to 10289 * maintain a Hung SGE State Machine of our own which operates across 10290 * a longer time frame. 10291 */ 10292 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 10293 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 10294 } 10295 10296 /** 10297 * t4_idma_monitor - monitor SGE Ingress DMA state 10298 * @adapter: the adapter 10299 * @idma: the adapter IDMA Monitor state 10300 * @hz: number of ticks/second 10301 * @ticks: number of ticks since the last IDMA Monitor call 10302 */ 10303 void t4_idma_monitor(struct adapter *adapter, 10304 struct sge_idma_monitor_state *idma, 10305 int hz, int ticks) 10306 { 10307 int i, idma_same_state_cnt[2]; 10308 10309 /* Read the SGE Debug Ingress DMA Same State Count registers. These 10310 * are counters inside the SGE which count up on each clock when the 10311 * SGE finds its Ingress DMA State Engines in the same states they 10312 * were in the previous clock. The counters will peg out at 10313 * 0xffffffff without wrapping around so once they pass the 1s 10314 * threshold they'll stay above that till the IDMA state changes. 10315 */ 10316 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 10317 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 10318 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10319 10320 for (i = 0; i < 2; i++) { 10321 u32 debug0, debug11; 10322 10323 /* If the Ingress DMA Same State Counter ("timer") is less 10324 * than 1s, then we can reset our synthesized Stall Timer and 10325 * continue. If we have previously emitted warnings about a 10326 * potential stalled Ingress Queue, issue a note indicating 10327 * that the Ingress Queue has resumed forward progress. 10328 */ 10329 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 10330 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 10331 CH_WARN(adapter, "SGE idma%d, queue %u, " 10332 "resumed after %d seconds\n", 10333 i, idma->idma_qid[i], 10334 idma->idma_stalled[i]/hz); 10335 idma->idma_stalled[i] = 0; 10336 continue; 10337 } 10338 10339 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 10340 * domain. The first time we get here it'll be because we 10341 * passed the 1s Threshold; each additional time it'll be 10342 * because the RX Timer Callback is being fired on its regular 10343 * schedule. 10344 * 10345 * If the stall is below our Potential Hung Ingress Queue 10346 * Warning Threshold, continue. 10347 */ 10348 if (idma->idma_stalled[i] == 0) { 10349 idma->idma_stalled[i] = hz; 10350 idma->idma_warn[i] = 0; 10351 } else { 10352 idma->idma_stalled[i] += ticks; 10353 idma->idma_warn[i] -= ticks; 10354 } 10355 10356 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 10357 continue; 10358 10359 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 10360 */ 10361 if (idma->idma_warn[i] > 0) 10362 continue; 10363 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 10364 10365 /* Read and save the SGE IDMA State and Queue ID information. 10366 * We do this every time in case it changes across time ... 10367 * can't be too careful ... 10368 */ 10369 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 10370 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10371 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 10372 10373 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 10374 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10375 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 10376 10377 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 10378 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 10379 i, idma->idma_qid[i], idma->idma_state[i], 10380 idma->idma_stalled[i]/hz, 10381 debug0, debug11); 10382 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 10383 } 10384 } 10385 10386 /** 10387 * t4_set_vf_mac - Set MAC address for the specified VF 10388 * @adapter: The adapter 10389 * @pf: the PF used to instantiate the VFs 10390 * @vf: one of the VFs instantiated by the specified PF 10391 * @naddr: the number of MAC addresses 10392 * @addr: the MAC address(es) to be set to the specified VF 10393 */ 10394 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, 10395 unsigned int naddr, u8 *addr) 10396 { 10397 struct fw_acl_mac_cmd cmd; 10398 10399 memset(&cmd, 0, sizeof(cmd)); 10400 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | 10401 F_FW_CMD_REQUEST | 10402 F_FW_CMD_WRITE | 10403 V_FW_ACL_MAC_CMD_PFN(pf) | 10404 V_FW_ACL_MAC_CMD_VFN(vf)); 10405 10406 /* Note: Do not enable the ACL */ 10407 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); 10408 cmd.nmac = naddr; 10409 10410 switch (pf) { 10411 case 3: 10412 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); 10413 break; 10414 case 2: 10415 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); 10416 break; 10417 case 1: 10418 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); 10419 break; 10420 case 0: 10421 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); 10422 break; 10423 } 10424 10425 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); 10426 } 10427 10428 /** 10429 * t4_read_pace_tbl - read the pace table 10430 * @adap: the adapter 10431 * @pace_vals: holds the returned values 10432 * 10433 * Returns the values of TP's pace table in microseconds. 10434 */ 10435 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 10436 { 10437 unsigned int i, v; 10438 10439 for (i = 0; i < NTX_SCHED; i++) { 10440 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 10441 v = t4_read_reg(adap, A_TP_PACE_TABLE); 10442 pace_vals[i] = dack_ticks_to_usec(adap, v); 10443 } 10444 } 10445 10446 /** 10447 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 10448 * @adap: the adapter 10449 * @sched: the scheduler index 10450 * @kbps: the byte rate in Kbps 10451 * @ipg: the interpacket delay in tenths of nanoseconds 10452 * 10453 * Return the current configuration of a HW Tx scheduler. 10454 */ 10455 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 10456 unsigned int *ipg, bool sleep_ok) 10457 { 10458 unsigned int v, addr, bpt, cpt; 10459 10460 if (kbps) { 10461 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 10462 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10463 if (sched & 1) 10464 v >>= 16; 10465 bpt = (v >> 8) & 0xff; 10466 cpt = v & 0xff; 10467 if (!cpt) 10468 *kbps = 0; /* scheduler disabled */ 10469 else { 10470 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 10471 *kbps = (v * bpt) / 125; 10472 } 10473 } 10474 if (ipg) { 10475 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 10476 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10477 if (sched & 1) 10478 v >>= 16; 10479 v &= 0xffff; 10480 *ipg = (10000 * v) / core_ticks_per_usec(adap); 10481 } 10482 } 10483 10484 /** 10485 * t4_load_cfg - download config file 10486 * @adap: the adapter 10487 * @cfg_data: the cfg text file to write 10488 * @size: text file size 10489 * 10490 * Write the supplied config text file to the card's serial flash. 10491 */ 10492 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 10493 { 10494 int ret, i, n, cfg_addr; 10495 unsigned int addr; 10496 unsigned int flash_cfg_start_sec; 10497 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10498 10499 cfg_addr = t4_flash_cfg_addr(adap); 10500 if (cfg_addr < 0) 10501 return cfg_addr; 10502 10503 addr = cfg_addr; 10504 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10505 10506 if (size > FLASH_CFG_MAX_SIZE) { 10507 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 10508 FLASH_CFG_MAX_SIZE); 10509 return -EFBIG; 10510 } 10511 10512 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 10513 sf_sec_size); 10514 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10515 flash_cfg_start_sec + i - 1); 10516 /* 10517 * If size == 0 then we're simply erasing the FLASH sectors associated 10518 * with the on-adapter Firmware Configuration File. 10519 */ 10520 if (ret || size == 0) 10521 goto out; 10522 10523 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10524 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10525 if ( (size - i) < SF_PAGE_SIZE) 10526 n = size - i; 10527 else 10528 n = SF_PAGE_SIZE; 10529 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 10530 if (ret) 10531 goto out; 10532 10533 addr += SF_PAGE_SIZE; 10534 cfg_data += SF_PAGE_SIZE; 10535 } 10536 10537 out: 10538 if (ret) 10539 CH_ERR(adap, "config file %s failed %d\n", 10540 (size == 0 ? "clear" : "download"), ret); 10541 return ret; 10542 } 10543 10544 /** 10545 * t5_fw_init_extern_mem - initialize the external memory 10546 * @adap: the adapter 10547 * 10548 * Initializes the external memory on T5. 10549 */ 10550 int t5_fw_init_extern_mem(struct adapter *adap) 10551 { 10552 u32 params[1], val[1]; 10553 int ret; 10554 10555 if (!is_t5(adap)) 10556 return 0; 10557 10558 val[0] = 0xff; /* Initialize all MCs */ 10559 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10560 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10561 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10562 FW_CMD_MAX_TIMEOUT); 10563 10564 return ret; 10565 } 10566 10567 /* BIOS boot headers */ 10568 typedef struct pci_expansion_rom_header { 10569 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10570 u8 reserved[22]; /* Reserved per processor Architecture data */ 10571 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10572 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10573 10574 /* Legacy PCI Expansion ROM Header */ 10575 typedef struct legacy_pci_expansion_rom_header { 10576 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10577 u8 size512; /* Current Image Size in units of 512 bytes */ 10578 u8 initentry_point[4]; 10579 u8 cksum; /* Checksum computed on the entire Image */ 10580 u8 reserved[16]; /* Reserved */ 10581 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10582 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10583 10584 /* EFI PCI Expansion ROM Header */ 10585 typedef struct efi_pci_expansion_rom_header { 10586 u8 signature[2]; // ROM signature. The value 0xaa55 10587 u8 initialization_size[2]; /* Units 512. Includes this header */ 10588 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10589 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10590 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10591 u8 compression_type[2]; /* Compression type. */ 10592 /* 10593 * Compression type definition 10594 * 0x0: uncompressed 10595 * 0x1: Compressed 10596 * 0x2-0xFFFF: Reserved 10597 */ 10598 u8 reserved[8]; /* Reserved */ 10599 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10600 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10601 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10602 10603 /* PCI Data Structure Format */ 10604 typedef struct pcir_data_structure { /* PCI Data Structure */ 10605 u8 signature[4]; /* Signature. The string "PCIR" */ 10606 u8 vendor_id[2]; /* Vendor Identification */ 10607 u8 device_id[2]; /* Device Identification */ 10608 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10609 u8 length[2]; /* PCIR Data Structure Length */ 10610 u8 revision; /* PCIR Data Structure Revision */ 10611 u8 class_code[3]; /* Class Code */ 10612 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10613 u8 code_revision[2]; /* Revision Level of Code/Data */ 10614 u8 code_type; /* Code Type. */ 10615 /* 10616 * PCI Expansion ROM Code Types 10617 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10618 * 0x01: Open Firmware standard for PCI. FCODE 10619 * 0x02: Hewlett-Packard PA RISC. HP reserved 10620 * 0x03: EFI Image. EFI 10621 * 0x04-0xFF: Reserved. 10622 */ 10623 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10624 u8 reserved[2]; /* Reserved */ 10625 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10626 10627 /* BOOT constants */ 10628 enum { 10629 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10630 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10631 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10632 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10633 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10634 VENDOR_ID = 0x1425, /* Vendor ID */ 10635 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10636 }; 10637 10638 /* 10639 * modify_device_id - Modifies the device ID of the Boot BIOS image 10640 * @adatper: the device ID to write. 10641 * @boot_data: the boot image to modify. 10642 * 10643 * Write the supplied device ID to the boot BIOS image. 10644 */ 10645 static void modify_device_id(int device_id, u8 *boot_data) 10646 { 10647 legacy_pci_exp_rom_header_t *header; 10648 pcir_data_t *pcir_header; 10649 u32 cur_header = 0; 10650 10651 /* 10652 * Loop through all chained images and change the device ID's 10653 */ 10654 while (1) { 10655 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10656 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10657 le16_to_cpu(*(u16*)header->pcir_offset)]; 10658 10659 /* 10660 * Only modify the Device ID if code type is Legacy or HP. 10661 * 0x00: Okay to modify 10662 * 0x01: FCODE. Do not be modify 10663 * 0x03: Okay to modify 10664 * 0x04-0xFF: Do not modify 10665 */ 10666 if (pcir_header->code_type == 0x00) { 10667 u8 csum = 0; 10668 int i; 10669 10670 /* 10671 * Modify Device ID to match current adatper 10672 */ 10673 *(u16*) pcir_header->device_id = device_id; 10674 10675 /* 10676 * Set checksum temporarily to 0. 10677 * We will recalculate it later. 10678 */ 10679 header->cksum = 0x0; 10680 10681 /* 10682 * Calculate and update checksum 10683 */ 10684 for (i = 0; i < (header->size512 * 512); i++) 10685 csum += (u8)boot_data[cur_header + i]; 10686 10687 /* 10688 * Invert summed value to create the checksum 10689 * Writing new checksum value directly to the boot data 10690 */ 10691 boot_data[cur_header + 7] = -csum; 10692 10693 } else if (pcir_header->code_type == 0x03) { 10694 10695 /* 10696 * Modify Device ID to match current adatper 10697 */ 10698 *(u16*) pcir_header->device_id = device_id; 10699 10700 } 10701 10702 10703 /* 10704 * Check indicator element to identify if this is the last 10705 * image in the ROM. 10706 */ 10707 if (pcir_header->indicator & 0x80) 10708 break; 10709 10710 /* 10711 * Move header pointer up to the next image in the ROM. 10712 */ 10713 cur_header += header->size512 * 512; 10714 } 10715 } 10716 10717 /* 10718 * t4_load_boot - download boot flash 10719 * @adapter: the adapter 10720 * @boot_data: the boot image to write 10721 * @boot_addr: offset in flash to write boot_data 10722 * @size: image size 10723 * 10724 * Write the supplied boot image to the card's serial flash. 10725 * The boot image has the following sections: a 28-byte header and the 10726 * boot image. 10727 */ 10728 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10729 unsigned int boot_addr, unsigned int size) 10730 { 10731 pci_exp_rom_header_t *header; 10732 int pcir_offset ; 10733 pcir_data_t *pcir_header; 10734 int ret, addr; 10735 uint16_t device_id; 10736 unsigned int i; 10737 unsigned int boot_sector = (boot_addr * 1024 ); 10738 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10739 10740 /* 10741 * Make sure the boot image does not encroach on the firmware region 10742 */ 10743 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10744 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10745 return -EFBIG; 10746 } 10747 10748 /* 10749 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10750 * and Boot configuration data sections. These 3 boot sections span 10751 * sectors 0 to 7 in flash and live right before the FW image location. 10752 */ 10753 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10754 sf_sec_size); 10755 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10756 (boot_sector >> 16) + i - 1); 10757 10758 /* 10759 * If size == 0 then we're simply erasing the FLASH sectors associated 10760 * with the on-adapter option ROM file 10761 */ 10762 if (ret || (size == 0)) 10763 goto out; 10764 10765 /* Get boot header */ 10766 header = (pci_exp_rom_header_t *)boot_data; 10767 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10768 /* PCIR Data Structure */ 10769 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10770 10771 /* 10772 * Perform some primitive sanity testing to avoid accidentally 10773 * writing garbage over the boot sectors. We ought to check for 10774 * more but it's not worth it for now ... 10775 */ 10776 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10777 CH_ERR(adap, "boot image too small/large\n"); 10778 return -EFBIG; 10779 } 10780 10781 #ifndef CHELSIO_T4_DIAGS 10782 /* 10783 * Check BOOT ROM header signature 10784 */ 10785 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10786 CH_ERR(adap, "Boot image missing signature\n"); 10787 return -EINVAL; 10788 } 10789 10790 /* 10791 * Check PCI header signature 10792 */ 10793 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10794 CH_ERR(adap, "PCI header missing signature\n"); 10795 return -EINVAL; 10796 } 10797 10798 /* 10799 * Check Vendor ID matches Chelsio ID 10800 */ 10801 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10802 CH_ERR(adap, "Vendor ID missing signature\n"); 10803 return -EINVAL; 10804 } 10805 #endif 10806 10807 /* 10808 * Retrieve adapter's device ID 10809 */ 10810 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10811 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10812 device_id = device_id & 0xf0ff; 10813 10814 /* 10815 * Check PCIE Device ID 10816 */ 10817 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10818 /* 10819 * Change the device ID in the Boot BIOS image to match 10820 * the Device ID of the current adapter. 10821 */ 10822 modify_device_id(device_id, boot_data); 10823 } 10824 10825 /* 10826 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10827 * we finish copying the rest of the boot image. This will ensure 10828 * that the BIOS boot header will only be written if the boot image 10829 * was written in full. 10830 */ 10831 addr = boot_sector; 10832 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10833 addr += SF_PAGE_SIZE; 10834 boot_data += SF_PAGE_SIZE; 10835 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10836 if (ret) 10837 goto out; 10838 } 10839 10840 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10841 (const u8 *)header, 0); 10842 10843 out: 10844 if (ret) 10845 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10846 return ret; 10847 } 10848 10849 /* 10850 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10851 * @adapter: the adapter 10852 * 10853 * Return the address within the flash where the OptionROM Configuration 10854 * is stored, or an error if the device FLASH is too small to contain 10855 * a OptionROM Configuration. 10856 */ 10857 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10858 { 10859 /* 10860 * If the device FLASH isn't large enough to hold a Firmware 10861 * Configuration File, return an error. 10862 */ 10863 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10864 return -ENOSPC; 10865 10866 return FLASH_BOOTCFG_START; 10867 } 10868 10869 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10870 { 10871 int ret, i, n, cfg_addr; 10872 unsigned int addr; 10873 unsigned int flash_cfg_start_sec; 10874 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10875 10876 cfg_addr = t4_flash_bootcfg_addr(adap); 10877 if (cfg_addr < 0) 10878 return cfg_addr; 10879 10880 addr = cfg_addr; 10881 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10882 10883 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10884 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10885 FLASH_BOOTCFG_MAX_SIZE); 10886 return -EFBIG; 10887 } 10888 10889 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10890 sf_sec_size); 10891 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10892 flash_cfg_start_sec + i - 1); 10893 10894 /* 10895 * If size == 0 then we're simply erasing the FLASH sectors associated 10896 * with the on-adapter OptionROM Configuration File. 10897 */ 10898 if (ret || size == 0) 10899 goto out; 10900 10901 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10902 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10903 if ( (size - i) < SF_PAGE_SIZE) 10904 n = size - i; 10905 else 10906 n = SF_PAGE_SIZE; 10907 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10908 if (ret) 10909 goto out; 10910 10911 addr += SF_PAGE_SIZE; 10912 cfg_data += SF_PAGE_SIZE; 10913 } 10914 10915 out: 10916 if (ret) 10917 CH_ERR(adap, "boot config data %s failed %d\n", 10918 (size == 0 ? "clear" : "download"), ret); 10919 return ret; 10920 } 10921 10922 /** 10923 * t4_set_filter_cfg - set up filter mode/mask and ingress config. 10924 * @adap: the adapter 10925 * @mode: a bitmap selecting which optional filter components to enable 10926 * @mask: a bitmap selecting which components to enable in filter mask 10927 * @vnic_mode: the ingress config/vnic mode setting 10928 * 10929 * Sets the filter mode and mask by selecting the optional components to 10930 * enable in filter tuples. Returns 0 on success and a negative error if 10931 * the requested mode needs more bits than are available for optional 10932 * components. The filter mask must be a subset of the filter mode. 10933 */ 10934 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) 10935 { 10936 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 10937 int i, nbits, rc; 10938 uint32_t param, val; 10939 uint16_t fmode, fmask; 10940 const int maxbits = adap->chip_params->filter_opt_len; 10941 10942 if (mode != -1 || mask != -1) { 10943 if (mode != -1) { 10944 fmode = mode; 10945 nbits = 0; 10946 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10947 if (fmode & (1 << i)) 10948 nbits += width[i]; 10949 } 10950 if (nbits > maxbits) { 10951 CH_ERR(adap, "optional fields in the filter " 10952 "mode (0x%x) add up to %d bits " 10953 "(must be <= %db). Remove some fields and " 10954 "try again.\n", fmode, nbits, maxbits); 10955 return -E2BIG; 10956 } 10957 10958 /* 10959 * Hardware wants the bits to be maxed out. Keep 10960 * setting them until there's no room for more. 10961 */ 10962 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10963 if (fmode & (1 << i)) 10964 continue; 10965 if (nbits + width[i] <= maxbits) { 10966 fmode |= 1 << i; 10967 nbits += width[i]; 10968 if (nbits == maxbits) 10969 break; 10970 } 10971 } 10972 10973 fmask = fmode & adap->params.tp.filter_mask; 10974 if (fmask != adap->params.tp.filter_mask) { 10975 CH_WARN(adap, 10976 "filter mask will be changed from 0x%x to " 10977 "0x%x to comply with the filter mode (0x%x).\n", 10978 adap->params.tp.filter_mask, fmask, fmode); 10979 } 10980 } else { 10981 fmode = adap->params.tp.filter_mode; 10982 fmask = mask; 10983 if ((fmode | fmask) != fmode) { 10984 CH_ERR(adap, 10985 "filter mask (0x%x) must be a subset of " 10986 "the filter mode (0x%x).\n", fmask, fmode); 10987 return -EINVAL; 10988 } 10989 } 10990 10991 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10992 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10993 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 10994 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) | 10995 V_FW_PARAMS_PARAM_FILTER_MASK(fmask); 10996 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10997 &val); 10998 if (rc < 0) 10999 return rc; 11000 } 11001 11002 if (vnic_mode != -1) { 11003 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11004 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 11005 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 11006 val = vnic_mode; 11007 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 11008 &val); 11009 if (rc < 0) 11010 return rc; 11011 } 11012 11013 /* Refresh. */ 11014 read_filter_mode_and_ingress_config(adap); 11015 11016 return 0; 11017 } 11018 11019 /** 11020 * t4_clr_port_stats - clear port statistics 11021 * @adap: the adapter 11022 * @idx: the port index 11023 * 11024 * Clear HW statistics for the given port. 11025 */ 11026 void t4_clr_port_stats(struct adapter *adap, int idx) 11027 { 11028 unsigned int i; 11029 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 11030 u32 port_base_addr; 11031 11032 if (is_t4(adap)) 11033 port_base_addr = PORT_BASE(idx); 11034 else 11035 port_base_addr = T5_PORT_BASE(idx); 11036 11037 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 11038 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 11039 t4_write_reg(adap, port_base_addr + i, 0); 11040 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 11041 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 11042 t4_write_reg(adap, port_base_addr + i, 0); 11043 for (i = 0; i < 4; i++) 11044 if (bgmap & (1 << i)) { 11045 t4_write_reg(adap, 11046 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 11047 t4_write_reg(adap, 11048 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 11049 } 11050 } 11051 11052 /** 11053 * t4_i2c_io - read/write I2C data from adapter 11054 * @adap: the adapter 11055 * @port: Port number if per-port device; <0 if not 11056 * @devid: per-port device ID or absolute device ID 11057 * @offset: byte offset into device I2C space 11058 * @len: byte length of I2C space data 11059 * @buf: buffer in which to return I2C data for read 11060 * buffer which holds the I2C data for write 11061 * @write: if true, do a write; else do a read 11062 * Reads/Writes the I2C data from/to the indicated device and location. 11063 */ 11064 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 11065 int port, unsigned int devid, 11066 unsigned int offset, unsigned int len, 11067 u8 *buf, bool write) 11068 { 11069 struct fw_ldst_cmd ldst_cmd, ldst_rpl; 11070 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data); 11071 int ret = 0; 11072 11073 if (len > I2C_PAGE_SIZE) 11074 return -EINVAL; 11075 11076 /* Dont allow reads that spans multiple pages */ 11077 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) 11078 return -EINVAL; 11079 11080 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 11081 ldst_cmd.op_to_addrspace = 11082 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11083 F_FW_CMD_REQUEST | 11084 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) | 11085 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 11086 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 11087 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); 11088 ldst_cmd.u.i2c.did = devid; 11089 11090 while (len > 0) { 11091 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max; 11092 11093 ldst_cmd.u.i2c.boffset = offset; 11094 ldst_cmd.u.i2c.blen = i2c_len; 11095 11096 if (write) 11097 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len); 11098 11099 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd), 11100 write ? NULL : &ldst_rpl); 11101 if (ret) 11102 break; 11103 11104 if (!write) 11105 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len); 11106 offset += i2c_len; 11107 buf += i2c_len; 11108 len -= i2c_len; 11109 } 11110 11111 return ret; 11112 } 11113 11114 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 11115 int port, unsigned int devid, 11116 unsigned int offset, unsigned int len, 11117 u8 *buf) 11118 { 11119 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false); 11120 } 11121 11122 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 11123 int port, unsigned int devid, 11124 unsigned int offset, unsigned int len, 11125 u8 *buf) 11126 { 11127 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true); 11128 } 11129 11130 /** 11131 * t4_sge_ctxt_rd - read an SGE context through FW 11132 * @adap: the adapter 11133 * @mbox: mailbox to use for the FW command 11134 * @cid: the context id 11135 * @ctype: the context type 11136 * @data: where to store the context data 11137 * 11138 * Issues a FW command through the given mailbox to read an SGE context. 11139 */ 11140 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 11141 enum ctxt_type ctype, u32 *data) 11142 { 11143 int ret; 11144 struct fw_ldst_cmd c; 11145 11146 if (ctype == CTXT_EGRESS) 11147 ret = FW_LDST_ADDRSPC_SGE_EGRC; 11148 else if (ctype == CTXT_INGRESS) 11149 ret = FW_LDST_ADDRSPC_SGE_INGC; 11150 else if (ctype == CTXT_FLM) 11151 ret = FW_LDST_ADDRSPC_SGE_FLMC; 11152 else 11153 ret = FW_LDST_ADDRSPC_SGE_CONMC; 11154 11155 memset(&c, 0, sizeof(c)); 11156 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11157 F_FW_CMD_REQUEST | F_FW_CMD_READ | 11158 V_FW_LDST_CMD_ADDRSPACE(ret)); 11159 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 11160 c.u.idctxt.physid = cpu_to_be32(cid); 11161 11162 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11163 if (ret == 0) { 11164 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 11165 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 11166 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 11167 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 11168 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 11169 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 11170 } 11171 return ret; 11172 } 11173 11174 /** 11175 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 11176 * @adap: the adapter 11177 * @cid: the context id 11178 * @ctype: the context type 11179 * @data: where to store the context data 11180 * 11181 * Reads an SGE context directly, bypassing FW. This is only for 11182 * debugging when FW is unavailable. 11183 */ 11184 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 11185 u32 *data) 11186 { 11187 int i, ret; 11188 11189 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 11190 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 11191 if (!ret) 11192 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 11193 *data++ = t4_read_reg(adap, i); 11194 return ret; 11195 } 11196 11197 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 11198 int sleep_ok) 11199 { 11200 struct fw_sched_cmd cmd; 11201 11202 memset(&cmd, 0, sizeof(cmd)); 11203 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11204 F_FW_CMD_REQUEST | 11205 F_FW_CMD_WRITE); 11206 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11207 11208 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 11209 cmd.u.config.type = type; 11210 cmd.u.config.minmaxen = minmaxen; 11211 11212 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11213 NULL, sleep_ok); 11214 } 11215 11216 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 11217 int rateunit, int ratemode, int channel, int cl, 11218 int minrate, int maxrate, int weight, int pktsize, 11219 int burstsize, int sleep_ok) 11220 { 11221 struct fw_sched_cmd cmd; 11222 11223 memset(&cmd, 0, sizeof(cmd)); 11224 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11225 F_FW_CMD_REQUEST | 11226 F_FW_CMD_WRITE); 11227 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11228 11229 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11230 cmd.u.params.type = type; 11231 cmd.u.params.level = level; 11232 cmd.u.params.mode = mode; 11233 cmd.u.params.ch = channel; 11234 cmd.u.params.cl = cl; 11235 cmd.u.params.unit = rateunit; 11236 cmd.u.params.rate = ratemode; 11237 cmd.u.params.min = cpu_to_be32(minrate); 11238 cmd.u.params.max = cpu_to_be32(maxrate); 11239 cmd.u.params.weight = cpu_to_be16(weight); 11240 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11241 cmd.u.params.burstsize = cpu_to_be16(burstsize); 11242 11243 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11244 NULL, sleep_ok); 11245 } 11246 11247 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 11248 unsigned int maxrate, int sleep_ok) 11249 { 11250 struct fw_sched_cmd cmd; 11251 11252 memset(&cmd, 0, sizeof(cmd)); 11253 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11254 F_FW_CMD_REQUEST | 11255 F_FW_CMD_WRITE); 11256 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11257 11258 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11259 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11260 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 11261 cmd.u.params.ch = channel; 11262 cmd.u.params.rate = ratemode; /* REL or ABS */ 11263 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 11264 11265 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11266 NULL, sleep_ok); 11267 } 11268 11269 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 11270 int weight, int sleep_ok) 11271 { 11272 struct fw_sched_cmd cmd; 11273 11274 if (weight < 0 || weight > 100) 11275 return -EINVAL; 11276 11277 memset(&cmd, 0, sizeof(cmd)); 11278 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11279 F_FW_CMD_REQUEST | 11280 F_FW_CMD_WRITE); 11281 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11282 11283 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11284 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11285 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 11286 cmd.u.params.ch = channel; 11287 cmd.u.params.cl = cl; 11288 cmd.u.params.weight = cpu_to_be16(weight); 11289 11290 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11291 NULL, sleep_ok); 11292 } 11293 11294 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 11295 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 11296 { 11297 struct fw_sched_cmd cmd; 11298 11299 memset(&cmd, 0, sizeof(cmd)); 11300 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11301 F_FW_CMD_REQUEST | 11302 F_FW_CMD_WRITE); 11303 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11304 11305 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11306 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11307 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 11308 cmd.u.params.mode = mode; 11309 cmd.u.params.ch = channel; 11310 cmd.u.params.cl = cl; 11311 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 11312 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 11313 cmd.u.params.max = cpu_to_be32(maxrate); 11314 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11315 11316 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11317 NULL, sleep_ok); 11318 } 11319 11320 /* 11321 * t4_config_watchdog - configure (enable/disable) a watchdog timer 11322 * @adapter: the adapter 11323 * @mbox: mailbox to use for the FW command 11324 * @pf: the PF owning the queue 11325 * @vf: the VF owning the queue 11326 * @timeout: watchdog timeout in ms 11327 * @action: watchdog timer / action 11328 * 11329 * There are separate watchdog timers for each possible watchdog 11330 * action. Configure one of the watchdog timers by setting a non-zero 11331 * timeout. Disable a watchdog timer by using a timeout of zero. 11332 */ 11333 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 11334 unsigned int pf, unsigned int vf, 11335 unsigned int timeout, unsigned int action) 11336 { 11337 struct fw_watchdog_cmd wdog; 11338 unsigned int ticks; 11339 11340 /* 11341 * The watchdog command expects a timeout in units of 10ms so we need 11342 * to convert it here (via rounding) and force a minimum of one 10ms 11343 * "tick" if the timeout is non-zero but the conversion results in 0 11344 * ticks. 11345 */ 11346 ticks = (timeout + 5)/10; 11347 if (timeout && !ticks) 11348 ticks = 1; 11349 11350 memset(&wdog, 0, sizeof wdog); 11351 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 11352 F_FW_CMD_REQUEST | 11353 F_FW_CMD_WRITE | 11354 V_FW_PARAMS_CMD_PFN(pf) | 11355 V_FW_PARAMS_CMD_VFN(vf)); 11356 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 11357 wdog.timeout = cpu_to_be32(ticks); 11358 wdog.action = cpu_to_be32(action); 11359 11360 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 11361 } 11362 11363 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 11364 { 11365 struct fw_devlog_cmd devlog_cmd; 11366 int ret; 11367 11368 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11369 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11370 F_FW_CMD_REQUEST | F_FW_CMD_READ); 11371 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11372 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11373 sizeof(devlog_cmd), &devlog_cmd); 11374 if (ret) 11375 return ret; 11376 11377 *level = devlog_cmd.level; 11378 return 0; 11379 } 11380 11381 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 11382 { 11383 struct fw_devlog_cmd devlog_cmd; 11384 11385 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11386 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11387 F_FW_CMD_REQUEST | 11388 F_FW_CMD_WRITE); 11389 devlog_cmd.level = level; 11390 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11391 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11392 sizeof(devlog_cmd), &devlog_cmd); 11393 } 11394 11395 int t4_configure_add_smac(struct adapter *adap) 11396 { 11397 unsigned int param, val; 11398 int ret = 0; 11399 11400 adap->params.smac_add_support = 0; 11401 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11402 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC)); 11403 /* Query FW to check if FW supports adding source mac address 11404 * to TCAM feature or not. 11405 * If FW returns 1, driver can use this feature and driver need to send 11406 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to 11407 * enable adding smac to TCAM. 11408 */ 11409 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11410 if (ret) 11411 return ret; 11412 11413 if (val == 1) { 11414 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 11415 ¶m, &val); 11416 if (!ret) 11417 /* Firmware allows adding explicit TCAM entries. 11418 * Save this internally. 11419 */ 11420 adap->params.smac_add_support = 1; 11421 } 11422 11423 return ret; 11424 } 11425 11426 int t4_configure_ringbb(struct adapter *adap) 11427 { 11428 unsigned int param, val; 11429 int ret = 0; 11430 11431 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11432 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE)); 11433 /* Query FW to check if FW supports ring switch feature or not. 11434 * If FW returns 1, driver can use this feature and driver need to send 11435 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to 11436 * enable the ring backbone configuration. 11437 */ 11438 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11439 if (ret < 0) { 11440 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n", 11441 ret); 11442 goto out; 11443 } 11444 11445 if (val != 1) { 11446 CH_ERR(adap, "FW doesnot support ringbackbone features\n"); 11447 goto out; 11448 } 11449 11450 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11451 if (ret < 0) { 11452 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n", 11453 ret); 11454 goto out; 11455 } 11456 11457 out: 11458 return ret; 11459 } 11460 11461 /* 11462 * t4_set_vlan_acl - Set a VLAN id for the specified VF 11463 * @adapter: the adapter 11464 * @mbox: mailbox to use for the FW command 11465 * @vf: one of the VFs instantiated by the specified PF 11466 * @vlan: The vlanid to be set 11467 * 11468 */ 11469 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 11470 u16 vlan) 11471 { 11472 struct fw_acl_vlan_cmd vlan_cmd; 11473 unsigned int enable; 11474 11475 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); 11476 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); 11477 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) | 11478 F_FW_CMD_REQUEST | 11479 F_FW_CMD_WRITE | 11480 F_FW_CMD_EXEC | 11481 V_FW_ACL_VLAN_CMD_PFN(adap->pf) | 11482 V_FW_ACL_VLAN_CMD_VFN(vf)); 11483 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd)); 11484 /* Drop all packets that donot match vlan id */ 11485 vlan_cmd.dropnovlan_fm = (enable 11486 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN | 11487 F_FW_ACL_VLAN_CMD_FM) 11488 : 0); 11489 if (enable != 0) { 11490 vlan_cmd.nvlan = 1; 11491 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); 11492 } 11493 11494 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); 11495 } 11496 11497 /** 11498 * t4_del_mac - Removes the exact-match filter for a MAC address 11499 * @adap: the adapter 11500 * @mbox: mailbox to use for the FW command 11501 * @viid: the VI id 11502 * @addr: the MAC address value 11503 * @smac: if true, delete from only the smac region of MPS 11504 * 11505 * Modifies an exact-match filter and sets it to the new MAC address if 11506 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11507 * latter case the address is added persistently if @persist is %true. 11508 * 11509 * Returns a negative error number or the index of the filter with the new 11510 * MAC value. Note that this index may differ from @idx. 11511 */ 11512 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11513 const u8 *addr, bool smac) 11514 { 11515 int ret; 11516 struct fw_vi_mac_cmd c; 11517 struct fw_vi_mac_exact *p = c.u.exact; 11518 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11519 11520 memset(&c, 0, sizeof(c)); 11521 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11522 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11523 V_FW_VI_MAC_CMD_VIID(viid)); 11524 c.freemacs_to_len16 = cpu_to_be32( 11525 V_FW_CMD_LEN16(1) | 11526 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11527 11528 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11529 p->valid_to_idx = cpu_to_be16( 11530 F_FW_VI_MAC_CMD_VALID | 11531 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 11532 11533 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11534 if (ret == 0) { 11535 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11536 if (ret < max_mac_addr) 11537 return -ENOMEM; 11538 } 11539 11540 return ret; 11541 } 11542 11543 /** 11544 * t4_add_mac - Adds an exact-match filter for a MAC address 11545 * @adap: the adapter 11546 * @mbox: mailbox to use for the FW command 11547 * @viid: the VI id 11548 * @idx: index of existing filter for old value of MAC address, or -1 11549 * @addr: the new MAC address value 11550 * @persist: whether a new MAC allocation should be persistent 11551 * @add_smt: if true also add the address to the HW SMT 11552 * @smac: if true, update only the smac region of MPS 11553 * 11554 * Modifies an exact-match filter and sets it to the new MAC address if 11555 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11556 * latter case the address is added persistently if @persist is %true. 11557 * 11558 * Returns a negative error number or the index of the filter with the new 11559 * MAC value. Note that this index may differ from @idx. 11560 */ 11561 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11562 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac) 11563 { 11564 int ret, mode; 11565 struct fw_vi_mac_cmd c; 11566 struct fw_vi_mac_exact *p = c.u.exact; 11567 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11568 11569 if (idx < 0) /* new allocation */ 11570 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 11571 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 11572 11573 memset(&c, 0, sizeof(c)); 11574 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11575 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11576 V_FW_VI_MAC_CMD_VIID(viid)); 11577 c.freemacs_to_len16 = cpu_to_be32( 11578 V_FW_CMD_LEN16(1) | 11579 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11580 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 11581 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 11582 V_FW_VI_MAC_CMD_IDX(idx)); 11583 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11584 11585 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11586 if (ret == 0) { 11587 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11588 if (ret >= max_mac_addr) 11589 return -ENOMEM; 11590 if (smt_idx) { 11591 /* Does fw supports returning smt_idx? */ 11592 if (adap->params.viid_smt_extn_support) 11593 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 11594 else { 11595 /* In T4/T5, SMT contains 256 SMAC entries 11596 * organized in 128 rows of 2 entries each. 11597 * In T6, SMT contains 256 SMAC entries in 11598 * 256 rows. 11599 */ 11600 if (chip_id(adap) <= CHELSIO_T5) 11601 *smt_idx = ((viid & M_FW_VIID_VIN) << 1); 11602 else 11603 *smt_idx = (viid & M_FW_VIID_VIN); 11604 } 11605 } 11606 } 11607 11608 return ret; 11609 } 11610