1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 adap->flags &= ~FW_OK; 216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 218 if (pcie_fw != 0xffffffff) 219 t4_os_dump_devlog(adap); 220 } 221 } 222 223 /* 224 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 225 */ 226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 227 u32 mbox_addr) 228 { 229 for ( ; nflit; nflit--, mbox_addr += 8) 230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 231 } 232 233 /* 234 * Handle a FW assertion reported in a mailbox. 235 */ 236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 237 { 238 CH_ALERT(adap, 239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 240 asrt->u.assert.filename_0_7, 241 be32_to_cpu(asrt->u.assert.line), 242 be32_to_cpu(asrt->u.assert.x), 243 be32_to_cpu(asrt->u.assert.y)); 244 } 245 246 struct port_tx_state { 247 uint64_t rx_pause; 248 uint64_t tx_frames; 249 }; 250 251 static void 252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 253 { 254 uint32_t rx_pause_reg, tx_frames_reg; 255 256 if (is_t4(sc)) { 257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 259 } else { 260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 262 } 263 264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 266 } 267 268 static void 269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 270 { 271 int i; 272 273 for_each_port(sc, i) 274 read_tx_state_one(sc, i, &tx_state[i]); 275 } 276 277 static void 278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 279 { 280 uint32_t port_ctl_reg; 281 uint64_t tx_frames, rx_pause; 282 int i; 283 284 for_each_port(sc, i) { 285 rx_pause = tx_state[i].rx_pause; 286 tx_frames = tx_state[i].tx_frames; 287 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 288 289 if (is_t4(sc)) 290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 291 else 292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 294 rx_pause != tx_state[i].rx_pause && 295 tx_frames == tx_state[i].tx_frames) { 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 297 mdelay(1); 298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 299 } 300 } 301 } 302 303 #define X_CIM_PF_NOACCESS 0xeeeeeeee 304 /** 305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 306 * @adap: the adapter 307 * @mbox: index of the mailbox to use 308 * @cmd: the command to write 309 * @size: command length in bytes 310 * @rpl: where to optionally store the reply 311 * @sleep_ok: if true we may sleep while awaiting command completion 312 * @timeout: time to wait for command to finish before timing out 313 * (negative implies @sleep_ok=false) 314 * 315 * Sends the given command to FW through the selected mailbox and waits 316 * for the FW to execute the command. If @rpl is not %NULL it is used to 317 * store the FW's reply to the command. The command and its optional 318 * reply are of the same length. Some FW commands like RESET and 319 * INITIALIZE can take a considerable amount of time to execute. 320 * @sleep_ok determines whether we may sleep while awaiting the response. 321 * If sleeping is allowed we use progressive backoff otherwise we spin. 322 * Note that passing in a negative @timeout is an alternate mechanism 323 * for specifying @sleep_ok=false. This is useful when a higher level 324 * interface allows for specification of @timeout but not @sleep_ok ... 325 * 326 * The return value is 0 on success or a negative errno on failure. A 327 * failure can happen either because we are not able to execute the 328 * command or FW executes it but signals an error. In the latter case 329 * the return value is the error code indicated by FW (negated). 330 */ 331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 332 int size, void *rpl, bool sleep_ok, int timeout) 333 { 334 /* 335 * We delay in small increments at first in an effort to maintain 336 * responsiveness for simple, fast executing commands but then back 337 * off to larger delays to a maximum retry delay. 338 */ 339 static const int delay[] = { 340 1, 1, 3, 5, 10, 10, 20, 50, 100 341 }; 342 u32 v; 343 u64 res; 344 int i, ms, delay_idx, ret, next_tx_check; 345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 347 u32 ctl; 348 __be64 cmd_rpl[MBOX_LEN/8]; 349 u32 pcie_fw; 350 struct port_tx_state tx_state[MAX_NPORTS]; 351 352 if (adap->flags & CHK_MBOX_ACCESS) 353 ASSERT_SYNCHRONIZED_OP(adap); 354 355 if (size <= 0 || (size & 15) || size > MBOX_LEN) 356 return -EINVAL; 357 358 if (adap->flags & IS_VF) { 359 if (is_t6(adap)) 360 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 361 else 362 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 364 } 365 366 /* 367 * If we have a negative timeout, that implies that we can't sleep. 368 */ 369 if (timeout < 0) { 370 sleep_ok = false; 371 timeout = -timeout; 372 } 373 374 /* 375 * Attempt to gain access to the mailbox. 376 */ 377 for (i = 0; i < 4; i++) { 378 ctl = t4_read_reg(adap, ctl_reg); 379 v = G_MBOWNER(ctl); 380 if (v != X_MBOWNER_NONE) 381 break; 382 } 383 384 /* 385 * If we were unable to gain access, report the error to our caller. 386 */ 387 if (v != X_MBOWNER_PL) { 388 t4_report_fw_error(adap); 389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 390 return ret; 391 } 392 393 /* 394 * If we gain ownership of the mailbox and there's a "valid" message 395 * in it, this is likely an asynchronous error message from the 396 * firmware. So we'll report that and then proceed on with attempting 397 * to issue our own command ... which may well fail if the error 398 * presaged the firmware crashing ... 399 */ 400 if (ctl & F_MBMSGVALID) { 401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 402 } 403 404 /* 405 * Copy in the new mailbox command and send it on its way ... 406 */ 407 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 408 memcpy(cmd_rpl, cmd, size); 409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 412 413 if (adap->flags & IS_VF) { 414 /* 415 * For the VFs, the Mailbox Data "registers" are 416 * actually backed by T4's "MA" interface rather than 417 * PL Registers (as is the case for the PFs). Because 418 * these are in different coherency domains, the write 419 * to the VF's PL-register-backed Mailbox Control can 420 * race in front of the writes to the MA-backed VF 421 * Mailbox Data "registers". So we need to do a 422 * read-back on at least one byte of the VF Mailbox 423 * Data registers before doing the write to the VF 424 * Mailbox Control register. 425 */ 426 t4_read_reg(adap, data_reg); 427 } 428 429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 431 next_tx_check = 1000; 432 delay_idx = 0; 433 ms = delay[0]; 434 435 /* 436 * Loop waiting for the reply; bail out if we time out or the firmware 437 * reports an error. 438 */ 439 pcie_fw = 0; 440 for (i = 0; i < timeout; i += ms) { 441 if (!(adap->flags & IS_VF)) { 442 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 443 if (pcie_fw & F_PCIE_FW_ERR) 444 break; 445 } 446 447 if (i >= next_tx_check) { 448 check_tx_state(adap, &tx_state[0]); 449 next_tx_check = i + 1000; 450 } 451 452 if (sleep_ok) { 453 ms = delay[delay_idx]; /* last element may repeat */ 454 if (delay_idx < ARRAY_SIZE(delay) - 1) 455 delay_idx++; 456 msleep(ms); 457 } else { 458 mdelay(ms); 459 } 460 461 v = t4_read_reg(adap, ctl_reg); 462 if (v == X_CIM_PF_NOACCESS) 463 continue; 464 if (G_MBOWNER(v) == X_MBOWNER_PL) { 465 if (!(v & F_MBMSGVALID)) { 466 t4_write_reg(adap, ctl_reg, 467 V_MBOWNER(X_MBOWNER_NONE)); 468 continue; 469 } 470 471 /* 472 * Retrieve the command reply and release the mailbox. 473 */ 474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 477 478 res = be64_to_cpu(cmd_rpl[0]); 479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 481 res = V_FW_CMD_RETVAL(EIO); 482 } else if (rpl) 483 memcpy(rpl, cmd_rpl, size); 484 return -G_FW_CMD_RETVAL((int)res); 485 } 486 } 487 488 /* 489 * We timed out waiting for a reply to our mailbox command. Report 490 * the error and also check to see if the firmware reported any 491 * errors ... 492 */ 493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 494 *(const u8 *)cmd, mbox, pcie_fw); 495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 497 498 if (pcie_fw & F_PCIE_FW_ERR) { 499 ret = -ENXIO; 500 t4_report_fw_error(adap); 501 } else { 502 ret = -ETIMEDOUT; 503 t4_os_dump_devlog(adap); 504 } 505 506 t4_fatal_err(adap, true); 507 return ret; 508 } 509 510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 511 void *rpl, bool sleep_ok) 512 { 513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 514 sleep_ok, FW_CMD_MAX_TIMEOUT); 515 516 } 517 518 static int t4_edc_err_read(struct adapter *adap, int idx) 519 { 520 u32 edc_ecc_err_addr_reg; 521 u32 edc_bist_status_rdata_reg; 522 523 if (is_t4(adap)) { 524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 525 return 0; 526 } 527 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 529 return 0; 530 } 531 532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 534 535 CH_WARN(adap, 536 "edc%d err addr 0x%x: 0x%x.\n", 537 idx, edc_ecc_err_addr_reg, 538 t4_read_reg(adap, edc_ecc_err_addr_reg)); 539 CH_WARN(adap, 540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 541 edc_bist_status_rdata_reg, 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 551 552 return 0; 553 } 554 555 /** 556 * t4_mc_read - read from MC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which MC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568 { 569 int i; 570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 572 573 if (is_t4(adap)) { 574 mc_bist_cmd_reg = A_MC_BIST_CMD; 575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 579 } else { 580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 584 idx); 585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 586 idx); 587 } 588 589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 590 return -EBUSY; 591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 595 F_START_BIST | V_BIST_CMD_GAP(1)); 596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 597 if (i) 598 return i; 599 600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 601 602 for (i = 15; i >= 0; i--) 603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 604 if (ecc) 605 *ecc = t4_read_reg64(adap, MC_DATA(16)); 606 #undef MC_DATA 607 return 0; 608 } 609 610 /** 611 * t4_edc_read - read from EDC through backdoor accesses 612 * @adap: the adapter 613 * @idx: which EDC to access 614 * @addr: address of first byte requested 615 * @data: 64 bytes of data containing the requested address 616 * @ecc: where to store the corresponding 64-bit ECC word 617 * 618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 619 * that covers the requested address @addr. If @parity is not %NULL it 620 * is assigned the 64-bit ECC word for the read data. 621 */ 622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 623 { 624 int i; 625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 627 628 if (is_t4(adap)) { 629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 633 idx); 634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 635 idx); 636 } else { 637 /* 638 * These macro are missing in t4_regs.h file. 639 * Added temporarily for testing. 640 */ 641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 649 idx); 650 #undef EDC_REG_T5 651 #undef EDC_STRIDE_T5 652 } 653 654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 655 return -EBUSY; 656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 659 t4_write_reg(adap, edc_bist_cmd_reg, 660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 662 if (i) 663 return i; 664 665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 666 667 for (i = 15; i >= 0; i--) 668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 669 if (ecc) 670 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 671 #undef EDC_DATA 672 return 0; 673 } 674 675 /** 676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 677 * @adap: the adapter 678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 679 * @addr: address within indicated memory type 680 * @len: amount of memory to read 681 * @buf: host memory buffer 682 * 683 * Reads an [almost] arbitrary memory region in the firmware: the 684 * firmware memory address, length and host buffer must be aligned on 685 * 32-bit boudaries. The memory is returned as a raw byte sequence from 686 * the firmware's memory. If this memory contains data structures which 687 * contain multi-byte integers, it's the callers responsibility to 688 * perform appropriate byte order conversions. 689 */ 690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 691 __be32 *buf) 692 { 693 u32 pos, start, end, offset; 694 int ret; 695 696 /* 697 * Argument sanity checks ... 698 */ 699 if ((addr & 0x3) || (len & 0x3)) 700 return -EINVAL; 701 702 /* 703 * The underlaying EDC/MC read routines read 64 bytes at a time so we 704 * need to round down the start and round up the end. We'll start 705 * copying out of the first line at (addr - start) a word at a time. 706 */ 707 start = rounddown2(addr, 64); 708 end = roundup2(addr + len, 64); 709 offset = (addr - start)/sizeof(__be32); 710 711 for (pos = start; pos < end; pos += 64, offset = 0) { 712 __be32 data[16]; 713 714 /* 715 * Read the chip's memory block and bail if there's an error. 716 */ 717 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 719 else 720 ret = t4_edc_read(adap, mtype, pos, data, NULL); 721 if (ret) 722 return ret; 723 724 /* 725 * Copy the data into the caller's memory buffer. 726 */ 727 while (offset < 16 && len > 0) { 728 *buf++ = data[offset++]; 729 len -= sizeof(__be32); 730 } 731 } 732 733 return 0; 734 } 735 736 /* 737 * Return the specified PCI-E Configuration Space register from our Physical 738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 739 * since we prefer to let the firmware own all of these registers, but if that 740 * fails we go for it directly ourselves. 741 */ 742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 743 { 744 745 /* 746 * If fw_attach != 0, construct and send the Firmware LDST Command to 747 * retrieve the specified PCI-E Configuration Space register. 748 */ 749 if (drv_fw_attach != 0) { 750 struct fw_ldst_cmd ldst_cmd; 751 int ret; 752 753 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 754 ldst_cmd.op_to_addrspace = 755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 756 F_FW_CMD_REQUEST | 757 F_FW_CMD_READ | 758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 761 ldst_cmd.u.pcie.ctrl_to_fn = 762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 763 ldst_cmd.u.pcie.r = reg; 764 765 /* 766 * If the LDST Command succeeds, return the result, otherwise 767 * fall through to reading it directly ourselves ... 768 */ 769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 770 &ldst_cmd); 771 if (ret == 0) 772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 773 774 CH_WARN(adap, "Firmware failed to return " 775 "Configuration Space register %d, err = %d\n", 776 reg, -ret); 777 } 778 779 /* 780 * Read the desired Configuration Space register via the PCI-E 781 * Backdoor mechanism. 782 */ 783 return t4_hw_pci_read_cfg4(adap, reg); 784 } 785 786 /** 787 * t4_get_regs_len - return the size of the chips register set 788 * @adapter: the adapter 789 * 790 * Returns the size of the chip's BAR0 register space. 791 */ 792 unsigned int t4_get_regs_len(struct adapter *adapter) 793 { 794 unsigned int chip_version = chip_id(adapter); 795 796 switch (chip_version) { 797 case CHELSIO_T4: 798 if (adapter->flags & IS_VF) 799 return FW_T4VF_REGMAP_SIZE; 800 return T4_REGMAP_SIZE; 801 802 case CHELSIO_T5: 803 case CHELSIO_T6: 804 if (adapter->flags & IS_VF) 805 return FW_T4VF_REGMAP_SIZE; 806 return T5_REGMAP_SIZE; 807 } 808 809 CH_ERR(adapter, 810 "Unsupported chip version %d\n", chip_version); 811 return 0; 812 } 813 814 /** 815 * t4_get_regs - read chip registers into provided buffer 816 * @adap: the adapter 817 * @buf: register buffer 818 * @buf_size: size (in bytes) of register buffer 819 * 820 * If the provided register buffer isn't large enough for the chip's 821 * full register range, the register dump will be truncated to the 822 * register buffer's size. 823 */ 824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 825 { 826 static const unsigned int t4_reg_ranges[] = { 827 0x1008, 0x1108, 828 0x1180, 0x1184, 829 0x1190, 0x1194, 830 0x11a0, 0x11a4, 831 0x11b0, 0x11b4, 832 0x11fc, 0x123c, 833 0x1300, 0x173c, 834 0x1800, 0x18fc, 835 0x3000, 0x30d8, 836 0x30e0, 0x30e4, 837 0x30ec, 0x5910, 838 0x5920, 0x5924, 839 0x5960, 0x5960, 840 0x5968, 0x5968, 841 0x5970, 0x5970, 842 0x5978, 0x5978, 843 0x5980, 0x5980, 844 0x5988, 0x5988, 845 0x5990, 0x5990, 846 0x5998, 0x5998, 847 0x59a0, 0x59d4, 848 0x5a00, 0x5ae0, 849 0x5ae8, 0x5ae8, 850 0x5af0, 0x5af0, 851 0x5af8, 0x5af8, 852 0x6000, 0x6098, 853 0x6100, 0x6150, 854 0x6200, 0x6208, 855 0x6240, 0x6248, 856 0x6280, 0x62b0, 857 0x62c0, 0x6338, 858 0x6370, 0x638c, 859 0x6400, 0x643c, 860 0x6500, 0x6524, 861 0x6a00, 0x6a04, 862 0x6a14, 0x6a38, 863 0x6a60, 0x6a70, 864 0x6a78, 0x6a78, 865 0x6b00, 0x6b0c, 866 0x6b1c, 0x6b84, 867 0x6bf0, 0x6bf8, 868 0x6c00, 0x6c0c, 869 0x6c1c, 0x6c84, 870 0x6cf0, 0x6cf8, 871 0x6d00, 0x6d0c, 872 0x6d1c, 0x6d84, 873 0x6df0, 0x6df8, 874 0x6e00, 0x6e0c, 875 0x6e1c, 0x6e84, 876 0x6ef0, 0x6ef8, 877 0x6f00, 0x6f0c, 878 0x6f1c, 0x6f84, 879 0x6ff0, 0x6ff8, 880 0x7000, 0x700c, 881 0x701c, 0x7084, 882 0x70f0, 0x70f8, 883 0x7100, 0x710c, 884 0x711c, 0x7184, 885 0x71f0, 0x71f8, 886 0x7200, 0x720c, 887 0x721c, 0x7284, 888 0x72f0, 0x72f8, 889 0x7300, 0x730c, 890 0x731c, 0x7384, 891 0x73f0, 0x73f8, 892 0x7400, 0x7450, 893 0x7500, 0x7530, 894 0x7600, 0x760c, 895 0x7614, 0x761c, 896 0x7680, 0x76cc, 897 0x7700, 0x7798, 898 0x77c0, 0x77fc, 899 0x7900, 0x79fc, 900 0x7b00, 0x7b58, 901 0x7b60, 0x7b84, 902 0x7b8c, 0x7c38, 903 0x7d00, 0x7d38, 904 0x7d40, 0x7d80, 905 0x7d8c, 0x7ddc, 906 0x7de4, 0x7e04, 907 0x7e10, 0x7e1c, 908 0x7e24, 0x7e38, 909 0x7e40, 0x7e44, 910 0x7e4c, 0x7e78, 911 0x7e80, 0x7ea4, 912 0x7eac, 0x7edc, 913 0x7ee8, 0x7efc, 914 0x8dc0, 0x8e04, 915 0x8e10, 0x8e1c, 916 0x8e30, 0x8e78, 917 0x8ea0, 0x8eb8, 918 0x8ec0, 0x8f6c, 919 0x8fc0, 0x9008, 920 0x9010, 0x9058, 921 0x9060, 0x9060, 922 0x9068, 0x9074, 923 0x90fc, 0x90fc, 924 0x9400, 0x9408, 925 0x9410, 0x9458, 926 0x9600, 0x9600, 927 0x9608, 0x9638, 928 0x9640, 0x96bc, 929 0x9800, 0x9808, 930 0x9820, 0x983c, 931 0x9850, 0x9864, 932 0x9c00, 0x9c6c, 933 0x9c80, 0x9cec, 934 0x9d00, 0x9d6c, 935 0x9d80, 0x9dec, 936 0x9e00, 0x9e6c, 937 0x9e80, 0x9eec, 938 0x9f00, 0x9f6c, 939 0x9f80, 0x9fec, 940 0xd004, 0xd004, 941 0xd010, 0xd03c, 942 0xdfc0, 0xdfe0, 943 0xe000, 0xea7c, 944 0xf000, 0x11110, 945 0x11118, 0x11190, 946 0x19040, 0x1906c, 947 0x19078, 0x19080, 948 0x1908c, 0x190e4, 949 0x190f0, 0x190f8, 950 0x19100, 0x19110, 951 0x19120, 0x19124, 952 0x19150, 0x19194, 953 0x1919c, 0x191b0, 954 0x191d0, 0x191e8, 955 0x19238, 0x1924c, 956 0x193f8, 0x1943c, 957 0x1944c, 0x19474, 958 0x19490, 0x194e0, 959 0x194f0, 0x194f8, 960 0x19800, 0x19c08, 961 0x19c10, 0x19c90, 962 0x19ca0, 0x19ce4, 963 0x19cf0, 0x19d40, 964 0x19d50, 0x19d94, 965 0x19da0, 0x19de8, 966 0x19df0, 0x19e40, 967 0x19e50, 0x19e90, 968 0x19ea0, 0x19f4c, 969 0x1a000, 0x1a004, 970 0x1a010, 0x1a06c, 971 0x1a0b0, 0x1a0e4, 972 0x1a0ec, 0x1a0f4, 973 0x1a100, 0x1a108, 974 0x1a114, 0x1a120, 975 0x1a128, 0x1a130, 976 0x1a138, 0x1a138, 977 0x1a190, 0x1a1c4, 978 0x1a1fc, 0x1a1fc, 979 0x1e040, 0x1e04c, 980 0x1e284, 0x1e28c, 981 0x1e2c0, 0x1e2c0, 982 0x1e2e0, 0x1e2e0, 983 0x1e300, 0x1e384, 984 0x1e3c0, 0x1e3c8, 985 0x1e440, 0x1e44c, 986 0x1e684, 0x1e68c, 987 0x1e6c0, 0x1e6c0, 988 0x1e6e0, 0x1e6e0, 989 0x1e700, 0x1e784, 990 0x1e7c0, 0x1e7c8, 991 0x1e840, 0x1e84c, 992 0x1ea84, 0x1ea8c, 993 0x1eac0, 0x1eac0, 994 0x1eae0, 0x1eae0, 995 0x1eb00, 0x1eb84, 996 0x1ebc0, 0x1ebc8, 997 0x1ec40, 0x1ec4c, 998 0x1ee84, 0x1ee8c, 999 0x1eec0, 0x1eec0, 1000 0x1eee0, 0x1eee0, 1001 0x1ef00, 0x1ef84, 1002 0x1efc0, 0x1efc8, 1003 0x1f040, 0x1f04c, 1004 0x1f284, 0x1f28c, 1005 0x1f2c0, 0x1f2c0, 1006 0x1f2e0, 0x1f2e0, 1007 0x1f300, 0x1f384, 1008 0x1f3c0, 0x1f3c8, 1009 0x1f440, 0x1f44c, 1010 0x1f684, 0x1f68c, 1011 0x1f6c0, 0x1f6c0, 1012 0x1f6e0, 0x1f6e0, 1013 0x1f700, 0x1f784, 1014 0x1f7c0, 0x1f7c8, 1015 0x1f840, 0x1f84c, 1016 0x1fa84, 0x1fa8c, 1017 0x1fac0, 0x1fac0, 1018 0x1fae0, 0x1fae0, 1019 0x1fb00, 0x1fb84, 1020 0x1fbc0, 0x1fbc8, 1021 0x1fc40, 0x1fc4c, 1022 0x1fe84, 0x1fe8c, 1023 0x1fec0, 0x1fec0, 1024 0x1fee0, 0x1fee0, 1025 0x1ff00, 0x1ff84, 1026 0x1ffc0, 0x1ffc8, 1027 0x20000, 0x2002c, 1028 0x20100, 0x2013c, 1029 0x20190, 0x201a0, 1030 0x201a8, 0x201b8, 1031 0x201c4, 0x201c8, 1032 0x20200, 0x20318, 1033 0x20400, 0x204b4, 1034 0x204c0, 0x20528, 1035 0x20540, 0x20614, 1036 0x21000, 0x21040, 1037 0x2104c, 0x21060, 1038 0x210c0, 0x210ec, 1039 0x21200, 0x21268, 1040 0x21270, 0x21284, 1041 0x212fc, 0x21388, 1042 0x21400, 0x21404, 1043 0x21500, 0x21500, 1044 0x21510, 0x21518, 1045 0x2152c, 0x21530, 1046 0x2153c, 0x2153c, 1047 0x21550, 0x21554, 1048 0x21600, 0x21600, 1049 0x21608, 0x2161c, 1050 0x21624, 0x21628, 1051 0x21630, 0x21634, 1052 0x2163c, 0x2163c, 1053 0x21700, 0x2171c, 1054 0x21780, 0x2178c, 1055 0x21800, 0x21818, 1056 0x21820, 0x21828, 1057 0x21830, 0x21848, 1058 0x21850, 0x21854, 1059 0x21860, 0x21868, 1060 0x21870, 0x21870, 1061 0x21878, 0x21898, 1062 0x218a0, 0x218a8, 1063 0x218b0, 0x218c8, 1064 0x218d0, 0x218d4, 1065 0x218e0, 0x218e8, 1066 0x218f0, 0x218f0, 1067 0x218f8, 0x21a18, 1068 0x21a20, 0x21a28, 1069 0x21a30, 0x21a48, 1070 0x21a50, 0x21a54, 1071 0x21a60, 0x21a68, 1072 0x21a70, 0x21a70, 1073 0x21a78, 0x21a98, 1074 0x21aa0, 0x21aa8, 1075 0x21ab0, 0x21ac8, 1076 0x21ad0, 0x21ad4, 1077 0x21ae0, 0x21ae8, 1078 0x21af0, 0x21af0, 1079 0x21af8, 0x21c18, 1080 0x21c20, 0x21c20, 1081 0x21c28, 0x21c30, 1082 0x21c38, 0x21c38, 1083 0x21c80, 0x21c98, 1084 0x21ca0, 0x21ca8, 1085 0x21cb0, 0x21cc8, 1086 0x21cd0, 0x21cd4, 1087 0x21ce0, 0x21ce8, 1088 0x21cf0, 0x21cf0, 1089 0x21cf8, 0x21d7c, 1090 0x21e00, 0x21e04, 1091 0x22000, 0x2202c, 1092 0x22100, 0x2213c, 1093 0x22190, 0x221a0, 1094 0x221a8, 0x221b8, 1095 0x221c4, 0x221c8, 1096 0x22200, 0x22318, 1097 0x22400, 0x224b4, 1098 0x224c0, 0x22528, 1099 0x22540, 0x22614, 1100 0x23000, 0x23040, 1101 0x2304c, 0x23060, 1102 0x230c0, 0x230ec, 1103 0x23200, 0x23268, 1104 0x23270, 0x23284, 1105 0x232fc, 0x23388, 1106 0x23400, 0x23404, 1107 0x23500, 0x23500, 1108 0x23510, 0x23518, 1109 0x2352c, 0x23530, 1110 0x2353c, 0x2353c, 1111 0x23550, 0x23554, 1112 0x23600, 0x23600, 1113 0x23608, 0x2361c, 1114 0x23624, 0x23628, 1115 0x23630, 0x23634, 1116 0x2363c, 0x2363c, 1117 0x23700, 0x2371c, 1118 0x23780, 0x2378c, 1119 0x23800, 0x23818, 1120 0x23820, 0x23828, 1121 0x23830, 0x23848, 1122 0x23850, 0x23854, 1123 0x23860, 0x23868, 1124 0x23870, 0x23870, 1125 0x23878, 0x23898, 1126 0x238a0, 0x238a8, 1127 0x238b0, 0x238c8, 1128 0x238d0, 0x238d4, 1129 0x238e0, 0x238e8, 1130 0x238f0, 0x238f0, 1131 0x238f8, 0x23a18, 1132 0x23a20, 0x23a28, 1133 0x23a30, 0x23a48, 1134 0x23a50, 0x23a54, 1135 0x23a60, 0x23a68, 1136 0x23a70, 0x23a70, 1137 0x23a78, 0x23a98, 1138 0x23aa0, 0x23aa8, 1139 0x23ab0, 0x23ac8, 1140 0x23ad0, 0x23ad4, 1141 0x23ae0, 0x23ae8, 1142 0x23af0, 0x23af0, 1143 0x23af8, 0x23c18, 1144 0x23c20, 0x23c20, 1145 0x23c28, 0x23c30, 1146 0x23c38, 0x23c38, 1147 0x23c80, 0x23c98, 1148 0x23ca0, 0x23ca8, 1149 0x23cb0, 0x23cc8, 1150 0x23cd0, 0x23cd4, 1151 0x23ce0, 0x23ce8, 1152 0x23cf0, 0x23cf0, 1153 0x23cf8, 0x23d7c, 1154 0x23e00, 0x23e04, 1155 0x24000, 0x2402c, 1156 0x24100, 0x2413c, 1157 0x24190, 0x241a0, 1158 0x241a8, 0x241b8, 1159 0x241c4, 0x241c8, 1160 0x24200, 0x24318, 1161 0x24400, 0x244b4, 1162 0x244c0, 0x24528, 1163 0x24540, 0x24614, 1164 0x25000, 0x25040, 1165 0x2504c, 0x25060, 1166 0x250c0, 0x250ec, 1167 0x25200, 0x25268, 1168 0x25270, 0x25284, 1169 0x252fc, 0x25388, 1170 0x25400, 0x25404, 1171 0x25500, 0x25500, 1172 0x25510, 0x25518, 1173 0x2552c, 0x25530, 1174 0x2553c, 0x2553c, 1175 0x25550, 0x25554, 1176 0x25600, 0x25600, 1177 0x25608, 0x2561c, 1178 0x25624, 0x25628, 1179 0x25630, 0x25634, 1180 0x2563c, 0x2563c, 1181 0x25700, 0x2571c, 1182 0x25780, 0x2578c, 1183 0x25800, 0x25818, 1184 0x25820, 0x25828, 1185 0x25830, 0x25848, 1186 0x25850, 0x25854, 1187 0x25860, 0x25868, 1188 0x25870, 0x25870, 1189 0x25878, 0x25898, 1190 0x258a0, 0x258a8, 1191 0x258b0, 0x258c8, 1192 0x258d0, 0x258d4, 1193 0x258e0, 0x258e8, 1194 0x258f0, 0x258f0, 1195 0x258f8, 0x25a18, 1196 0x25a20, 0x25a28, 1197 0x25a30, 0x25a48, 1198 0x25a50, 0x25a54, 1199 0x25a60, 0x25a68, 1200 0x25a70, 0x25a70, 1201 0x25a78, 0x25a98, 1202 0x25aa0, 0x25aa8, 1203 0x25ab0, 0x25ac8, 1204 0x25ad0, 0x25ad4, 1205 0x25ae0, 0x25ae8, 1206 0x25af0, 0x25af0, 1207 0x25af8, 0x25c18, 1208 0x25c20, 0x25c20, 1209 0x25c28, 0x25c30, 1210 0x25c38, 0x25c38, 1211 0x25c80, 0x25c98, 1212 0x25ca0, 0x25ca8, 1213 0x25cb0, 0x25cc8, 1214 0x25cd0, 0x25cd4, 1215 0x25ce0, 0x25ce8, 1216 0x25cf0, 0x25cf0, 1217 0x25cf8, 0x25d7c, 1218 0x25e00, 0x25e04, 1219 0x26000, 0x2602c, 1220 0x26100, 0x2613c, 1221 0x26190, 0x261a0, 1222 0x261a8, 0x261b8, 1223 0x261c4, 0x261c8, 1224 0x26200, 0x26318, 1225 0x26400, 0x264b4, 1226 0x264c0, 0x26528, 1227 0x26540, 0x26614, 1228 0x27000, 0x27040, 1229 0x2704c, 0x27060, 1230 0x270c0, 0x270ec, 1231 0x27200, 0x27268, 1232 0x27270, 0x27284, 1233 0x272fc, 0x27388, 1234 0x27400, 0x27404, 1235 0x27500, 0x27500, 1236 0x27510, 0x27518, 1237 0x2752c, 0x27530, 1238 0x2753c, 0x2753c, 1239 0x27550, 0x27554, 1240 0x27600, 0x27600, 1241 0x27608, 0x2761c, 1242 0x27624, 0x27628, 1243 0x27630, 0x27634, 1244 0x2763c, 0x2763c, 1245 0x27700, 0x2771c, 1246 0x27780, 0x2778c, 1247 0x27800, 0x27818, 1248 0x27820, 0x27828, 1249 0x27830, 0x27848, 1250 0x27850, 0x27854, 1251 0x27860, 0x27868, 1252 0x27870, 0x27870, 1253 0x27878, 0x27898, 1254 0x278a0, 0x278a8, 1255 0x278b0, 0x278c8, 1256 0x278d0, 0x278d4, 1257 0x278e0, 0x278e8, 1258 0x278f0, 0x278f0, 1259 0x278f8, 0x27a18, 1260 0x27a20, 0x27a28, 1261 0x27a30, 0x27a48, 1262 0x27a50, 0x27a54, 1263 0x27a60, 0x27a68, 1264 0x27a70, 0x27a70, 1265 0x27a78, 0x27a98, 1266 0x27aa0, 0x27aa8, 1267 0x27ab0, 0x27ac8, 1268 0x27ad0, 0x27ad4, 1269 0x27ae0, 0x27ae8, 1270 0x27af0, 0x27af0, 1271 0x27af8, 0x27c18, 1272 0x27c20, 0x27c20, 1273 0x27c28, 0x27c30, 1274 0x27c38, 0x27c38, 1275 0x27c80, 0x27c98, 1276 0x27ca0, 0x27ca8, 1277 0x27cb0, 0x27cc8, 1278 0x27cd0, 0x27cd4, 1279 0x27ce0, 0x27ce8, 1280 0x27cf0, 0x27cf0, 1281 0x27cf8, 0x27d7c, 1282 0x27e00, 0x27e04, 1283 }; 1284 1285 static const unsigned int t4vf_reg_ranges[] = { 1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1287 VF_MPS_REG(A_MPS_VF_CTL), 1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1292 FW_T4VF_MBDATA_BASE_ADDR, 1293 FW_T4VF_MBDATA_BASE_ADDR + 1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1295 }; 1296 1297 static const unsigned int t5_reg_ranges[] = { 1298 0x1008, 0x10c0, 1299 0x10cc, 0x10f8, 1300 0x1100, 0x1100, 1301 0x110c, 0x1148, 1302 0x1180, 0x1184, 1303 0x1190, 0x1194, 1304 0x11a0, 0x11a4, 1305 0x11b0, 0x11b4, 1306 0x11fc, 0x123c, 1307 0x1280, 0x173c, 1308 0x1800, 0x18fc, 1309 0x3000, 0x3028, 1310 0x3060, 0x30b0, 1311 0x30b8, 0x30d8, 1312 0x30e0, 0x30fc, 1313 0x3140, 0x357c, 1314 0x35a8, 0x35cc, 1315 0x35ec, 0x35ec, 1316 0x3600, 0x5624, 1317 0x56cc, 0x56ec, 1318 0x56f4, 0x5720, 1319 0x5728, 0x575c, 1320 0x580c, 0x5814, 1321 0x5890, 0x589c, 1322 0x58a4, 0x58ac, 1323 0x58b8, 0x58bc, 1324 0x5940, 0x59c8, 1325 0x59d0, 0x59dc, 1326 0x59fc, 0x5a18, 1327 0x5a60, 0x5a70, 1328 0x5a80, 0x5a9c, 1329 0x5b94, 0x5bfc, 1330 0x6000, 0x6020, 1331 0x6028, 0x6040, 1332 0x6058, 0x609c, 1333 0x60a8, 0x614c, 1334 0x7700, 0x7798, 1335 0x77c0, 0x78fc, 1336 0x7b00, 0x7b58, 1337 0x7b60, 0x7b84, 1338 0x7b8c, 0x7c54, 1339 0x7d00, 0x7d38, 1340 0x7d40, 0x7d80, 1341 0x7d8c, 0x7ddc, 1342 0x7de4, 0x7e04, 1343 0x7e10, 0x7e1c, 1344 0x7e24, 0x7e38, 1345 0x7e40, 0x7e44, 1346 0x7e4c, 0x7e78, 1347 0x7e80, 0x7edc, 1348 0x7ee8, 0x7efc, 1349 0x8dc0, 0x8de0, 1350 0x8df8, 0x8e04, 1351 0x8e10, 0x8e84, 1352 0x8ea0, 0x8f84, 1353 0x8fc0, 0x9058, 1354 0x9060, 0x9060, 1355 0x9068, 0x90f8, 1356 0x9400, 0x9408, 1357 0x9410, 0x9470, 1358 0x9600, 0x9600, 1359 0x9608, 0x9638, 1360 0x9640, 0x96f4, 1361 0x9800, 0x9808, 1362 0x9810, 0x9864, 1363 0x9c00, 0x9c6c, 1364 0x9c80, 0x9cec, 1365 0x9d00, 0x9d6c, 1366 0x9d80, 0x9dec, 1367 0x9e00, 0x9e6c, 1368 0x9e80, 0x9eec, 1369 0x9f00, 0x9f6c, 1370 0x9f80, 0xa020, 1371 0xd000, 0xd004, 1372 0xd010, 0xd03c, 1373 0xdfc0, 0xdfe0, 1374 0xe000, 0x1106c, 1375 0x11074, 0x11088, 1376 0x1109c, 0x11110, 1377 0x11118, 0x1117c, 1378 0x11190, 0x11204, 1379 0x19040, 0x1906c, 1380 0x19078, 0x19080, 1381 0x1908c, 0x190e8, 1382 0x190f0, 0x190f8, 1383 0x19100, 0x19110, 1384 0x19120, 0x19124, 1385 0x19150, 0x19194, 1386 0x1919c, 0x191b0, 1387 0x191d0, 0x191e8, 1388 0x19238, 0x19290, 1389 0x193f8, 0x19428, 1390 0x19430, 0x19444, 1391 0x1944c, 0x1946c, 1392 0x19474, 0x19474, 1393 0x19490, 0x194cc, 1394 0x194f0, 0x194f8, 1395 0x19c00, 0x19c08, 1396 0x19c10, 0x19c60, 1397 0x19c94, 0x19ce4, 1398 0x19cf0, 0x19d40, 1399 0x19d50, 0x19d94, 1400 0x19da0, 0x19de8, 1401 0x19df0, 0x19e10, 1402 0x19e50, 0x19e90, 1403 0x19ea0, 0x19f24, 1404 0x19f34, 0x19f34, 1405 0x19f40, 0x19f50, 1406 0x19f90, 0x19fb4, 1407 0x19fc4, 0x19fe4, 1408 0x1a000, 0x1a004, 1409 0x1a010, 0x1a06c, 1410 0x1a0b0, 0x1a0e4, 1411 0x1a0ec, 0x1a0f8, 1412 0x1a100, 0x1a108, 1413 0x1a114, 0x1a130, 1414 0x1a138, 0x1a1c4, 1415 0x1a1fc, 0x1a1fc, 1416 0x1e008, 0x1e00c, 1417 0x1e040, 0x1e044, 1418 0x1e04c, 0x1e04c, 1419 0x1e284, 0x1e290, 1420 0x1e2c0, 0x1e2c0, 1421 0x1e2e0, 0x1e2e0, 1422 0x1e300, 0x1e384, 1423 0x1e3c0, 0x1e3c8, 1424 0x1e408, 0x1e40c, 1425 0x1e440, 0x1e444, 1426 0x1e44c, 0x1e44c, 1427 0x1e684, 0x1e690, 1428 0x1e6c0, 0x1e6c0, 1429 0x1e6e0, 0x1e6e0, 1430 0x1e700, 0x1e784, 1431 0x1e7c0, 0x1e7c8, 1432 0x1e808, 0x1e80c, 1433 0x1e840, 0x1e844, 1434 0x1e84c, 0x1e84c, 1435 0x1ea84, 0x1ea90, 1436 0x1eac0, 0x1eac0, 1437 0x1eae0, 0x1eae0, 1438 0x1eb00, 0x1eb84, 1439 0x1ebc0, 0x1ebc8, 1440 0x1ec08, 0x1ec0c, 1441 0x1ec40, 0x1ec44, 1442 0x1ec4c, 0x1ec4c, 1443 0x1ee84, 0x1ee90, 1444 0x1eec0, 0x1eec0, 1445 0x1eee0, 0x1eee0, 1446 0x1ef00, 0x1ef84, 1447 0x1efc0, 0x1efc8, 1448 0x1f008, 0x1f00c, 1449 0x1f040, 0x1f044, 1450 0x1f04c, 0x1f04c, 1451 0x1f284, 0x1f290, 1452 0x1f2c0, 0x1f2c0, 1453 0x1f2e0, 0x1f2e0, 1454 0x1f300, 0x1f384, 1455 0x1f3c0, 0x1f3c8, 1456 0x1f408, 0x1f40c, 1457 0x1f440, 0x1f444, 1458 0x1f44c, 0x1f44c, 1459 0x1f684, 0x1f690, 1460 0x1f6c0, 0x1f6c0, 1461 0x1f6e0, 0x1f6e0, 1462 0x1f700, 0x1f784, 1463 0x1f7c0, 0x1f7c8, 1464 0x1f808, 0x1f80c, 1465 0x1f840, 0x1f844, 1466 0x1f84c, 0x1f84c, 1467 0x1fa84, 0x1fa90, 1468 0x1fac0, 0x1fac0, 1469 0x1fae0, 0x1fae0, 1470 0x1fb00, 0x1fb84, 1471 0x1fbc0, 0x1fbc8, 1472 0x1fc08, 0x1fc0c, 1473 0x1fc40, 0x1fc44, 1474 0x1fc4c, 0x1fc4c, 1475 0x1fe84, 0x1fe90, 1476 0x1fec0, 0x1fec0, 1477 0x1fee0, 0x1fee0, 1478 0x1ff00, 0x1ff84, 1479 0x1ffc0, 0x1ffc8, 1480 0x30000, 0x30030, 1481 0x30100, 0x30144, 1482 0x30190, 0x301a0, 1483 0x301a8, 0x301b8, 1484 0x301c4, 0x301c8, 1485 0x301d0, 0x301d0, 1486 0x30200, 0x30318, 1487 0x30400, 0x304b4, 1488 0x304c0, 0x3052c, 1489 0x30540, 0x3061c, 1490 0x30800, 0x30828, 1491 0x30834, 0x30834, 1492 0x308c0, 0x30908, 1493 0x30910, 0x309ac, 1494 0x30a00, 0x30a14, 1495 0x30a1c, 0x30a2c, 1496 0x30a44, 0x30a50, 1497 0x30a74, 0x30a74, 1498 0x30a7c, 0x30afc, 1499 0x30b08, 0x30c24, 1500 0x30d00, 0x30d00, 1501 0x30d08, 0x30d14, 1502 0x30d1c, 0x30d20, 1503 0x30d3c, 0x30d3c, 1504 0x30d48, 0x30d50, 1505 0x31200, 0x3120c, 1506 0x31220, 0x31220, 1507 0x31240, 0x31240, 1508 0x31600, 0x3160c, 1509 0x31a00, 0x31a1c, 1510 0x31e00, 0x31e20, 1511 0x31e38, 0x31e3c, 1512 0x31e80, 0x31e80, 1513 0x31e88, 0x31ea8, 1514 0x31eb0, 0x31eb4, 1515 0x31ec8, 0x31ed4, 1516 0x31fb8, 0x32004, 1517 0x32200, 0x32200, 1518 0x32208, 0x32240, 1519 0x32248, 0x32280, 1520 0x32288, 0x322c0, 1521 0x322c8, 0x322fc, 1522 0x32600, 0x32630, 1523 0x32a00, 0x32abc, 1524 0x32b00, 0x32b10, 1525 0x32b20, 0x32b30, 1526 0x32b40, 0x32b50, 1527 0x32b60, 0x32b70, 1528 0x33000, 0x33028, 1529 0x33030, 0x33048, 1530 0x33060, 0x33068, 1531 0x33070, 0x3309c, 1532 0x330f0, 0x33128, 1533 0x33130, 0x33148, 1534 0x33160, 0x33168, 1535 0x33170, 0x3319c, 1536 0x331f0, 0x33238, 1537 0x33240, 0x33240, 1538 0x33248, 0x33250, 1539 0x3325c, 0x33264, 1540 0x33270, 0x332b8, 1541 0x332c0, 0x332e4, 1542 0x332f8, 0x33338, 1543 0x33340, 0x33340, 1544 0x33348, 0x33350, 1545 0x3335c, 0x33364, 1546 0x33370, 0x333b8, 1547 0x333c0, 0x333e4, 1548 0x333f8, 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1722 0x38d1c, 0x38d20, 1723 0x38d3c, 0x38d3c, 1724 0x38d48, 0x38d50, 1725 0x39200, 0x3920c, 1726 0x39220, 0x39220, 1727 0x39240, 0x39240, 1728 0x39600, 0x3960c, 1729 0x39a00, 0x39a1c, 1730 0x39e00, 0x39e20, 1731 0x39e38, 0x39e3c, 1732 0x39e80, 0x39e80, 1733 0x39e88, 0x39ea8, 1734 0x39eb0, 0x39eb4, 1735 0x39ec8, 0x39ed4, 1736 0x39fb8, 0x3a004, 1737 0x3a200, 0x3a200, 1738 0x3a208, 0x3a240, 1739 0x3a248, 0x3a280, 1740 0x3a288, 0x3a2c0, 1741 0x3a2c8, 0x3a2fc, 1742 0x3a600, 0x3a630, 1743 0x3aa00, 0x3aabc, 1744 0x3ab00, 0x3ab10, 1745 0x3ab20, 0x3ab30, 1746 0x3ab40, 0x3ab50, 1747 0x3ab60, 0x3ab70, 1748 0x3b000, 0x3b028, 1749 0x3b030, 0x3b048, 1750 0x3b060, 0x3b068, 1751 0x3b070, 0x3b09c, 1752 0x3b0f0, 0x3b128, 1753 0x3b130, 0x3b148, 1754 0x3b160, 0x3b168, 1755 0x3b170, 0x3b19c, 1756 0x3b1f0, 0x3b238, 1757 0x3b240, 0x3b240, 1758 0x3b248, 0x3b250, 1759 0x3b25c, 0x3b264, 1760 0x3b270, 0x3b2b8, 1761 0x3b2c0, 0x3b2e4, 1762 0x3b2f8, 0x3b338, 1763 0x3b340, 0x3b340, 1764 0x3b348, 0x3b350, 1765 0x3b35c, 0x3b364, 1766 0x3b370, 0x3b3b8, 1767 0x3b3c0, 0x3b3e4, 1768 0x3b3f8, 0x3b428, 1769 0x3b430, 0x3b448, 1770 0x3b460, 0x3b468, 1771 0x3b470, 0x3b49c, 1772 0x3b4f0, 0x3b528, 1773 0x3b530, 0x3b548, 1774 0x3b560, 0x3b568, 1775 0x3b570, 0x3b59c, 1776 0x3b5f0, 0x3b638, 1777 0x3b640, 0x3b640, 1778 0x3b648, 0x3b650, 1779 0x3b65c, 0x3b664, 1780 0x3b670, 0x3b6b8, 1781 0x3b6c0, 0x3b6e4, 1782 0x3b6f8, 0x3b738, 1783 0x3b740, 0x3b740, 1784 0x3b748, 0x3b750, 1785 0x3b75c, 0x3b764, 1786 0x3b770, 0x3b7b8, 1787 0x3b7c0, 0x3b7e4, 1788 0x3b7f8, 0x3b7fc, 1789 0x3b814, 0x3b814, 1790 0x3b82c, 0x3b82c, 1791 0x3b880, 0x3b88c, 1792 0x3b8e8, 0x3b8ec, 1793 0x3b900, 0x3b928, 1794 0x3b930, 0x3b948, 1795 0x3b960, 0x3b968, 1796 0x3b970, 0x3b99c, 1797 0x3b9f0, 0x3ba38, 1798 0x3ba40, 0x3ba40, 1799 0x3ba48, 0x3ba50, 1800 0x3ba5c, 0x3ba64, 1801 0x3ba70, 0x3bab8, 1802 0x3bac0, 0x3bae4, 1803 0x3baf8, 0x3bb10, 1804 0x3bb28, 0x3bb28, 1805 0x3bb3c, 0x3bb50, 1806 0x3bbf0, 0x3bc10, 1807 0x3bc28, 0x3bc28, 1808 0x3bc3c, 0x3bc50, 1809 0x3bcf0, 0x3bcfc, 1810 0x3c000, 0x3c030, 1811 0x3c100, 0x3c144, 1812 0x3c190, 0x3c1a0, 1813 0x3c1a8, 0x3c1b8, 1814 0x3c1c4, 0x3c1c8, 1815 0x3c1d0, 0x3c1d0, 1816 0x3c200, 0x3c318, 1817 0x3c400, 0x3c4b4, 1818 0x3c4c0, 0x3c52c, 1819 0x3c540, 0x3c61c, 1820 0x3c800, 0x3c828, 1821 0x3c834, 0x3c834, 1822 0x3c8c0, 0x3c908, 1823 0x3c910, 0x3c9ac, 1824 0x3ca00, 0x3ca14, 1825 0x3ca1c, 0x3ca2c, 1826 0x3ca44, 0x3ca50, 1827 0x3ca74, 0x3ca74, 1828 0x3ca7c, 0x3cafc, 1829 0x3cb08, 0x3cc24, 1830 0x3cd00, 0x3cd00, 1831 0x3cd08, 0x3cd14, 1832 0x3cd1c, 0x3cd20, 1833 0x3cd3c, 0x3cd3c, 1834 0x3cd48, 0x3cd50, 1835 0x3d200, 0x3d20c, 1836 0x3d220, 0x3d220, 1837 0x3d240, 0x3d240, 1838 0x3d600, 0x3d60c, 1839 0x3da00, 0x3da1c, 1840 0x3de00, 0x3de20, 1841 0x3de38, 0x3de3c, 1842 0x3de80, 0x3de80, 1843 0x3de88, 0x3dea8, 1844 0x3deb0, 0x3deb4, 1845 0x3dec8, 0x3ded4, 1846 0x3dfb8, 0x3e004, 1847 0x3e200, 0x3e200, 1848 0x3e208, 0x3e240, 1849 0x3e248, 0x3e280, 1850 0x3e288, 0x3e2c0, 1851 0x3e2c8, 0x3e2fc, 1852 0x3e600, 0x3e630, 1853 0x3ea00, 0x3eabc, 1854 0x3eb00, 0x3eb10, 1855 0x3eb20, 0x3eb30, 1856 0x3eb40, 0x3eb50, 1857 0x3eb60, 0x3eb70, 1858 0x3f000, 0x3f028, 1859 0x3f030, 0x3f048, 1860 0x3f060, 0x3f068, 1861 0x3f070, 0x3f09c, 1862 0x3f0f0, 0x3f128, 1863 0x3f130, 0x3f148, 1864 0x3f160, 0x3f168, 1865 0x3f170, 0x3f19c, 1866 0x3f1f0, 0x3f238, 1867 0x3f240, 0x3f240, 1868 0x3f248, 0x3f250, 1869 0x3f25c, 0x3f264, 1870 0x3f270, 0x3f2b8, 1871 0x3f2c0, 0x3f2e4, 1872 0x3f2f8, 0x3f338, 1873 0x3f340, 0x3f340, 1874 0x3f348, 0x3f350, 1875 0x3f35c, 0x3f364, 1876 0x3f370, 0x3f3b8, 1877 0x3f3c0, 0x3f3e4, 1878 0x3f3f8, 0x3f428, 1879 0x3f430, 0x3f448, 1880 0x3f460, 0x3f468, 1881 0x3f470, 0x3f49c, 1882 0x3f4f0, 0x3f528, 1883 0x3f530, 0x3f548, 1884 0x3f560, 0x3f568, 1885 0x3f570, 0x3f59c, 1886 0x3f5f0, 0x3f638, 1887 0x3f640, 0x3f640, 1888 0x3f648, 0x3f650, 1889 0x3f65c, 0x3f664, 1890 0x3f670, 0x3f6b8, 1891 0x3f6c0, 0x3f6e4, 1892 0x3f6f8, 0x3f738, 1893 0x3f740, 0x3f740, 1894 0x3f748, 0x3f750, 1895 0x3f75c, 0x3f764, 1896 0x3f770, 0x3f7b8, 1897 0x3f7c0, 0x3f7e4, 1898 0x3f7f8, 0x3f7fc, 1899 0x3f814, 0x3f814, 1900 0x3f82c, 0x3f82c, 1901 0x3f880, 0x3f88c, 1902 0x3f8e8, 0x3f8ec, 1903 0x3f900, 0x3f928, 1904 0x3f930, 0x3f948, 1905 0x3f960, 0x3f968, 1906 0x3f970, 0x3f99c, 1907 0x3f9f0, 0x3fa38, 1908 0x3fa40, 0x3fa40, 1909 0x3fa48, 0x3fa50, 1910 0x3fa5c, 0x3fa64, 1911 0x3fa70, 0x3fab8, 1912 0x3fac0, 0x3fae4, 1913 0x3faf8, 0x3fb10, 1914 0x3fb28, 0x3fb28, 1915 0x3fb3c, 0x3fb50, 1916 0x3fbf0, 0x3fc10, 1917 0x3fc28, 0x3fc28, 1918 0x3fc3c, 0x3fc50, 1919 0x3fcf0, 0x3fcfc, 1920 0x40000, 0x4000c, 1921 0x40040, 0x40050, 1922 0x40060, 0x40068, 1923 0x4007c, 0x4008c, 1924 0x40094, 0x400b0, 1925 0x400c0, 0x40144, 1926 0x40180, 0x4018c, 1927 0x40200, 0x40254, 1928 0x40260, 0x40264, 1929 0x40270, 0x40288, 1930 0x40290, 0x40298, 1931 0x402ac, 0x402c8, 1932 0x402d0, 0x402e0, 1933 0x402f0, 0x402f0, 1934 0x40300, 0x4033c, 1935 0x403f8, 0x403fc, 1936 0x41304, 0x413c4, 1937 0x41400, 0x4140c, 1938 0x41414, 0x4141c, 1939 0x41480, 0x414d0, 1940 0x44000, 0x44054, 1941 0x4405c, 0x44078, 1942 0x440c0, 0x44174, 1943 0x44180, 0x441ac, 1944 0x441b4, 0x441b8, 1945 0x441c0, 0x44254, 1946 0x4425c, 0x44278, 1947 0x442c0, 0x44374, 1948 0x44380, 0x443ac, 1949 0x443b4, 0x443b8, 1950 0x443c0, 0x44454, 1951 0x4445c, 0x44478, 1952 0x444c0, 0x44574, 1953 0x44580, 0x445ac, 1954 0x445b4, 0x445b8, 1955 0x445c0, 0x44654, 1956 0x4465c, 0x44678, 1957 0x446c0, 0x44774, 1958 0x44780, 0x447ac, 1959 0x447b4, 0x447b8, 1960 0x447c0, 0x44854, 1961 0x4485c, 0x44878, 1962 0x448c0, 0x44974, 1963 0x44980, 0x449ac, 1964 0x449b4, 0x449b8, 1965 0x449c0, 0x449fc, 1966 0x45000, 0x45004, 1967 0x45010, 0x45030, 1968 0x45040, 0x45060, 1969 0x45068, 0x45068, 1970 0x45080, 0x45084, 1971 0x450a0, 0x450b0, 1972 0x45200, 0x45204, 1973 0x45210, 0x45230, 1974 0x45240, 0x45260, 1975 0x45268, 0x45268, 1976 0x45280, 0x45284, 1977 0x452a0, 0x452b0, 1978 0x460c0, 0x460e4, 1979 0x47000, 0x4703c, 1980 0x47044, 0x4708c, 1981 0x47200, 0x47250, 1982 0x47400, 0x47408, 1983 0x47414, 0x47420, 1984 0x47600, 0x47618, 1985 0x47800, 0x47814, 1986 0x48000, 0x4800c, 1987 0x48040, 0x48050, 1988 0x48060, 0x48068, 1989 0x4807c, 0x4808c, 1990 0x48094, 0x480b0, 1991 0x480c0, 0x48144, 1992 0x48180, 0x4818c, 1993 0x48200, 0x48254, 1994 0x48260, 0x48264, 1995 0x48270, 0x48288, 1996 0x48290, 0x48298, 1997 0x482ac, 0x482c8, 1998 0x482d0, 0x482e0, 1999 0x482f0, 0x482f0, 2000 0x48300, 0x4833c, 2001 0x483f8, 0x483fc, 2002 0x49304, 0x493c4, 2003 0x49400, 0x4940c, 2004 0x49414, 0x4941c, 2005 0x49480, 0x494d0, 2006 0x4c000, 0x4c054, 2007 0x4c05c, 0x4c078, 2008 0x4c0c0, 0x4c174, 2009 0x4c180, 0x4c1ac, 2010 0x4c1b4, 0x4c1b8, 2011 0x4c1c0, 0x4c254, 2012 0x4c25c, 0x4c278, 2013 0x4c2c0, 0x4c374, 2014 0x4c380, 0x4c3ac, 2015 0x4c3b4, 0x4c3b8, 2016 0x4c3c0, 0x4c454, 2017 0x4c45c, 0x4c478, 2018 0x4c4c0, 0x4c574, 2019 0x4c580, 0x4c5ac, 2020 0x4c5b4, 0x4c5b8, 2021 0x4c5c0, 0x4c654, 2022 0x4c65c, 0x4c678, 2023 0x4c6c0, 0x4c774, 2024 0x4c780, 0x4c7ac, 2025 0x4c7b4, 0x4c7b8, 2026 0x4c7c0, 0x4c854, 2027 0x4c85c, 0x4c878, 2028 0x4c8c0, 0x4c974, 2029 0x4c980, 0x4c9ac, 2030 0x4c9b4, 0x4c9b8, 2031 0x4c9c0, 0x4c9fc, 2032 0x4d000, 0x4d004, 2033 0x4d010, 0x4d030, 2034 0x4d040, 0x4d060, 2035 0x4d068, 0x4d068, 2036 0x4d080, 0x4d084, 2037 0x4d0a0, 0x4d0b0, 2038 0x4d200, 0x4d204, 2039 0x4d210, 0x4d230, 2040 0x4d240, 0x4d260, 2041 0x4d268, 0x4d268, 2042 0x4d280, 0x4d284, 2043 0x4d2a0, 0x4d2b0, 2044 0x4e0c0, 0x4e0e4, 2045 0x4f000, 0x4f03c, 2046 0x4f044, 0x4f08c, 2047 0x4f200, 0x4f250, 2048 0x4f400, 0x4f408, 2049 0x4f414, 0x4f420, 2050 0x4f600, 0x4f618, 2051 0x4f800, 0x4f814, 2052 0x50000, 0x50084, 2053 0x50090, 0x500cc, 2054 0x50400, 0x50400, 2055 0x50800, 0x50884, 2056 0x50890, 0x508cc, 2057 0x50c00, 0x50c00, 2058 0x51000, 0x5101c, 2059 0x51300, 0x51308, 2060 }; 2061 2062 static const unsigned int t5vf_reg_ranges[] = { 2063 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2064 VF_MPS_REG(A_MPS_VF_CTL), 2065 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2066 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2068 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2069 FW_T4VF_MBDATA_BASE_ADDR, 2070 FW_T4VF_MBDATA_BASE_ADDR + 2071 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2072 }; 2073 2074 static const unsigned int t6_reg_ranges[] = { 2075 0x1008, 0x101c, 2076 0x1024, 0x10a8, 2077 0x10b4, 0x10f8, 2078 0x1100, 0x1114, 2079 0x111c, 0x112c, 2080 0x1138, 0x113c, 2081 0x1144, 0x114c, 2082 0x1180, 0x1184, 2083 0x1190, 0x1194, 2084 0x11a0, 0x11a4, 2085 0x11b0, 0x11c4, 2086 0x11fc, 0x123c, 2087 0x1254, 0x1274, 2088 0x1280, 0x133c, 2089 0x1800, 0x18fc, 2090 0x3000, 0x302c, 2091 0x3060, 0x30b0, 2092 0x30b8, 0x30d8, 2093 0x30e0, 0x30fc, 2094 0x3140, 0x357c, 2095 0x35a8, 0x35cc, 2096 0x35ec, 0x35ec, 2097 0x3600, 0x5624, 2098 0x56cc, 0x56ec, 2099 0x56f4, 0x5720, 2100 0x5728, 0x575c, 2101 0x580c, 0x5814, 2102 0x5890, 0x589c, 2103 0x58a4, 0x58ac, 2104 0x58b8, 0x58bc, 2105 0x5940, 0x595c, 2106 0x5980, 0x598c, 2107 0x59b0, 0x59c8, 2108 0x59d0, 0x59dc, 2109 0x59fc, 0x5a18, 2110 0x5a60, 0x5a6c, 2111 0x5a80, 0x5a8c, 2112 0x5a94, 0x5a9c, 2113 0x5b94, 0x5bfc, 2114 0x5c10, 0x5e48, 2115 0x5e50, 0x5e94, 2116 0x5ea0, 0x5eb0, 2117 0x5ec0, 0x5ec0, 2118 0x5ec8, 0x5ed0, 2119 0x5ee0, 0x5ee0, 2120 0x5ef0, 0x5ef0, 2121 0x5f00, 0x5f00, 2122 0x6000, 0x6020, 2123 0x6028, 0x6040, 2124 0x6058, 0x609c, 2125 0x60a8, 0x619c, 2126 0x7700, 0x7798, 2127 0x77c0, 0x7880, 2128 0x78cc, 0x78fc, 2129 0x7b00, 0x7b58, 2130 0x7b60, 0x7b84, 2131 0x7b8c, 0x7c54, 2132 0x7d00, 0x7d38, 2133 0x7d40, 0x7d84, 2134 0x7d8c, 0x7ddc, 2135 0x7de4, 0x7e04, 2136 0x7e10, 0x7e1c, 2137 0x7e24, 0x7e38, 2138 0x7e40, 0x7e44, 2139 0x7e4c, 0x7e78, 2140 0x7e80, 0x7edc, 2141 0x7ee8, 0x7efc, 2142 0x8dc0, 0x8de0, 2143 0x8df8, 0x8e04, 2144 0x8e10, 0x8e84, 2145 0x8ea0, 0x8f88, 2146 0x8fb8, 0x9058, 2147 0x9060, 0x9060, 2148 0x9068, 0x90f8, 2149 0x9100, 0x9124, 2150 0x9400, 0x9470, 2151 0x9600, 0x9600, 2152 0x9608, 0x9638, 2153 0x9640, 0x9704, 2154 0x9710, 0x971c, 2155 0x9800, 0x9808, 2156 0x9810, 0x9864, 2157 0x9c00, 0x9c6c, 2158 0x9c80, 0x9cec, 2159 0x9d00, 0x9d6c, 2160 0x9d80, 0x9dec, 2161 0x9e00, 0x9e6c, 2162 0x9e80, 0x9eec, 2163 0x9f00, 0x9f6c, 2164 0x9f80, 0xa020, 2165 0xd000, 0xd03c, 2166 0xd100, 0xd118, 2167 0xd200, 0xd214, 2168 0xd220, 0xd234, 2169 0xd240, 0xd254, 2170 0xd260, 0xd274, 2171 0xd280, 0xd294, 2172 0xd2a0, 0xd2b4, 2173 0xd2c0, 0xd2d4, 2174 0xd2e0, 0xd2f4, 2175 0xd300, 0xd31c, 2176 0xdfc0, 0xdfe0, 2177 0xe000, 0xf008, 2178 0xf010, 0xf018, 2179 0xf020, 0xf028, 2180 0x11000, 0x11014, 2181 0x11048, 0x1106c, 2182 0x11074, 0x11088, 2183 0x11098, 0x11120, 2184 0x1112c, 0x1117c, 2185 0x11190, 0x112e0, 2186 0x11300, 0x1130c, 2187 0x12000, 0x1206c, 2188 0x19040, 0x1906c, 2189 0x19078, 0x19080, 2190 0x1908c, 0x190e8, 2191 0x190f0, 0x190f8, 2192 0x19100, 0x19110, 2193 0x19120, 0x19124, 2194 0x19150, 0x19194, 2195 0x1919c, 0x191b0, 2196 0x191d0, 0x191e8, 2197 0x19238, 0x19290, 2198 0x192a4, 0x192b0, 2199 0x19348, 0x1934c, 2200 0x193f8, 0x19418, 2201 0x19420, 0x19428, 2202 0x19430, 0x19444, 2203 0x1944c, 0x1946c, 2204 0x19474, 0x19474, 2205 0x19490, 0x194cc, 2206 0x194f0, 0x194f8, 2207 0x19c00, 0x19c48, 2208 0x19c50, 0x19c80, 2209 0x19c94, 0x19c98, 2210 0x19ca0, 0x19cbc, 2211 0x19ce4, 0x19ce4, 2212 0x19cf0, 0x19cf8, 2213 0x19d00, 0x19d28, 2214 0x19d50, 0x19d78, 2215 0x19d94, 0x19d98, 2216 0x19da0, 0x19de0, 2217 0x19df0, 0x19e10, 2218 0x19e50, 0x19e6c, 2219 0x19ea0, 0x19ebc, 2220 0x19ec4, 0x19ef4, 2221 0x19f04, 0x19f2c, 2222 0x19f34, 0x19f34, 2223 0x19f40, 0x19f50, 2224 0x19f90, 0x19fac, 2225 0x19fc4, 0x19fc8, 2226 0x19fd0, 0x19fe4, 2227 0x1a000, 0x1a004, 2228 0x1a010, 0x1a06c, 2229 0x1a0b0, 0x1a0e4, 2230 0x1a0ec, 0x1a0f8, 2231 0x1a100, 0x1a108, 2232 0x1a114, 0x1a130, 2233 0x1a138, 0x1a1c4, 2234 0x1a1fc, 0x1a1fc, 2235 0x1e008, 0x1e00c, 2236 0x1e040, 0x1e044, 2237 0x1e04c, 0x1e04c, 2238 0x1e284, 0x1e290, 2239 0x1e2c0, 0x1e2c0, 2240 0x1e2e0, 0x1e2e0, 2241 0x1e300, 0x1e384, 2242 0x1e3c0, 0x1e3c8, 2243 0x1e408, 0x1e40c, 2244 0x1e440, 0x1e444, 2245 0x1e44c, 0x1e44c, 2246 0x1e684, 0x1e690, 2247 0x1e6c0, 0x1e6c0, 2248 0x1e6e0, 0x1e6e0, 2249 0x1e700, 0x1e784, 2250 0x1e7c0, 0x1e7c8, 2251 0x1e808, 0x1e80c, 2252 0x1e840, 0x1e844, 2253 0x1e84c, 0x1e84c, 2254 0x1ea84, 0x1ea90, 2255 0x1eac0, 0x1eac0, 2256 0x1eae0, 0x1eae0, 2257 0x1eb00, 0x1eb84, 2258 0x1ebc0, 0x1ebc8, 2259 0x1ec08, 0x1ec0c, 2260 0x1ec40, 0x1ec44, 2261 0x1ec4c, 0x1ec4c, 2262 0x1ee84, 0x1ee90, 2263 0x1eec0, 0x1eec0, 2264 0x1eee0, 0x1eee0, 2265 0x1ef00, 0x1ef84, 2266 0x1efc0, 0x1efc8, 2267 0x1f008, 0x1f00c, 2268 0x1f040, 0x1f044, 2269 0x1f04c, 0x1f04c, 2270 0x1f284, 0x1f290, 2271 0x1f2c0, 0x1f2c0, 2272 0x1f2e0, 0x1f2e0, 2273 0x1f300, 0x1f384, 2274 0x1f3c0, 0x1f3c8, 2275 0x1f408, 0x1f40c, 2276 0x1f440, 0x1f444, 2277 0x1f44c, 0x1f44c, 2278 0x1f684, 0x1f690, 2279 0x1f6c0, 0x1f6c0, 2280 0x1f6e0, 0x1f6e0, 2281 0x1f700, 0x1f784, 2282 0x1f7c0, 0x1f7c8, 2283 0x1f808, 0x1f80c, 2284 0x1f840, 0x1f844, 2285 0x1f84c, 0x1f84c, 2286 0x1fa84, 0x1fa90, 2287 0x1fac0, 0x1fac0, 2288 0x1fae0, 0x1fae0, 2289 0x1fb00, 0x1fb84, 2290 0x1fbc0, 0x1fbc8, 2291 0x1fc08, 0x1fc0c, 2292 0x1fc40, 0x1fc44, 2293 0x1fc4c, 0x1fc4c, 2294 0x1fe84, 0x1fe90, 2295 0x1fec0, 0x1fec0, 2296 0x1fee0, 0x1fee0, 2297 0x1ff00, 0x1ff84, 2298 0x1ffc0, 0x1ffc8, 2299 0x30000, 0x30030, 2300 0x30100, 0x30168, 2301 0x30190, 0x301a0, 2302 0x301a8, 0x301b8, 2303 0x301c4, 0x301c8, 2304 0x301d0, 0x301d0, 2305 0x30200, 0x30320, 2306 0x30400, 0x304b4, 2307 0x304c0, 0x3052c, 2308 0x30540, 0x3061c, 2309 0x30800, 0x308a0, 2310 0x308c0, 0x30908, 2311 0x30910, 0x309b8, 2312 0x30a00, 0x30a04, 2313 0x30a0c, 0x30a14, 2314 0x30a1c, 0x30a2c, 2315 0x30a44, 0x30a50, 2316 0x30a74, 0x30a74, 2317 0x30a7c, 0x30afc, 2318 0x30b08, 0x30c24, 2319 0x30d00, 0x30d14, 2320 0x30d1c, 0x30d3c, 2321 0x30d44, 0x30d4c, 2322 0x30d54, 0x30d74, 2323 0x30d7c, 0x30d7c, 2324 0x30de0, 0x30de0, 2325 0x30e00, 0x30ed4, 2326 0x30f00, 0x30fa4, 2327 0x30fc0, 0x30fc4, 2328 0x31000, 0x31004, 2329 0x31080, 0x310fc, 2330 0x31208, 0x31220, 2331 0x3123c, 0x31254, 2332 0x31300, 0x31300, 2333 0x31308, 0x3131c, 2334 0x31338, 0x3133c, 2335 0x31380, 0x31380, 2336 0x31388, 0x313a8, 2337 0x313b4, 0x313b4, 2338 0x31400, 0x31420, 2339 0x31438, 0x3143c, 2340 0x31480, 0x31480, 2341 0x314a8, 0x314a8, 2342 0x314b0, 0x314b4, 2343 0x314c8, 0x314d4, 2344 0x31a40, 0x31a4c, 2345 0x31af0, 0x31b20, 2346 0x31b38, 0x31b3c, 2347 0x31b80, 0x31b80, 2348 0x31ba8, 0x31ba8, 2349 0x31bb0, 0x31bb4, 2350 0x31bc8, 0x31bd4, 2351 0x32140, 0x3218c, 2352 0x321f0, 0x321f4, 2353 0x32200, 0x32200, 2354 0x32218, 0x32218, 2355 0x32400, 0x32400, 2356 0x32408, 0x3241c, 2357 0x32618, 0x32620, 2358 0x32664, 0x32664, 2359 0x326a8, 0x326a8, 2360 0x326ec, 0x326ec, 2361 0x32a00, 0x32abc, 2362 0x32b00, 0x32b18, 2363 0x32b20, 0x32b38, 2364 0x32b40, 0x32b58, 2365 0x32b60, 0x32b78, 2366 0x32c00, 0x32c00, 2367 0x32c08, 0x32c3c, 2368 0x33000, 0x3302c, 2369 0x33034, 0x33050, 2370 0x33058, 0x33058, 2371 0x33060, 0x3308c, 2372 0x3309c, 0x330ac, 2373 0x330c0, 0x330c0, 2374 0x330c8, 0x330d0, 2375 0x330d8, 0x330e0, 2376 0x330ec, 0x3312c, 2377 0x33134, 0x33150, 2378 0x33158, 0x33158, 2379 0x33160, 0x3318c, 2380 0x3319c, 0x331ac, 2381 0x331c0, 0x331c0, 2382 0x331c8, 0x331d0, 2383 0x331d8, 0x331e0, 2384 0x331ec, 0x33290, 2385 0x33298, 0x332c4, 2386 0x332e4, 0x33390, 2387 0x33398, 0x333c4, 2388 0x333e4, 0x3342c, 2389 0x33434, 0x33450, 2390 0x33458, 0x33458, 2391 0x33460, 0x3348c, 2392 0x3349c, 0x334ac, 2393 0x334c0, 0x334c0, 2394 0x334c8, 0x334d0, 2395 0x334d8, 0x334e0, 2396 0x334ec, 0x3352c, 2397 0x33534, 0x33550, 2398 0x33558, 0x33558, 2399 0x33560, 0x3358c, 2400 0x3359c, 0x335ac, 2401 0x335c0, 0x335c0, 2402 0x335c8, 0x335d0, 2403 0x335d8, 0x335e0, 2404 0x335ec, 0x33690, 2405 0x33698, 0x336c4, 2406 0x336e4, 0x33790, 2407 0x33798, 0x337c4, 2408 0x337e4, 0x337fc, 2409 0x33814, 0x33814, 2410 0x33854, 0x33868, 2411 0x33880, 0x3388c, 2412 0x338c0, 0x338d0, 2413 0x338e8, 0x338ec, 2414 0x33900, 0x3392c, 2415 0x33934, 0x33950, 2416 0x33958, 0x33958, 2417 0x33960, 0x3398c, 2418 0x3399c, 0x339ac, 2419 0x339c0, 0x339c0, 2420 0x339c8, 0x339d0, 2421 0x339d8, 0x339e0, 2422 0x339ec, 0x33a90, 2423 0x33a98, 0x33ac4, 2424 0x33ae4, 0x33b10, 2425 0x33b24, 0x33b28, 2426 0x33b38, 0x33b50, 2427 0x33bf0, 0x33c10, 2428 0x33c24, 0x33c28, 2429 0x33c38, 0x33c50, 2430 0x33cf0, 0x33cfc, 2431 0x34000, 0x34030, 2432 0x34100, 0x34168, 2433 0x34190, 0x341a0, 2434 0x341a8, 0x341b8, 2435 0x341c4, 0x341c8, 2436 0x341d0, 0x341d0, 2437 0x34200, 0x34320, 2438 0x34400, 0x344b4, 2439 0x344c0, 0x3452c, 2440 0x34540, 0x3461c, 2441 0x34800, 0x348a0, 2442 0x348c0, 0x34908, 2443 0x34910, 0x349b8, 2444 0x34a00, 0x34a04, 2445 0x34a0c, 0x34a14, 2446 0x34a1c, 0x34a2c, 2447 0x34a44, 0x34a50, 2448 0x34a74, 0x34a74, 2449 0x34a7c, 0x34afc, 2450 0x34b08, 0x34c24, 2451 0x34d00, 0x34d14, 2452 0x34d1c, 0x34d3c, 2453 0x34d44, 0x34d4c, 2454 0x34d54, 0x34d74, 2455 0x34d7c, 0x34d7c, 2456 0x34de0, 0x34de0, 2457 0x34e00, 0x34ed4, 2458 0x34f00, 0x34fa4, 2459 0x34fc0, 0x34fc4, 2460 0x35000, 0x35004, 2461 0x35080, 0x350fc, 2462 0x35208, 0x35220, 2463 0x3523c, 0x35254, 2464 0x35300, 0x35300, 2465 0x35308, 0x3531c, 2466 0x35338, 0x3533c, 2467 0x35380, 0x35380, 2468 0x35388, 0x353a8, 2469 0x353b4, 0x353b4, 2470 0x35400, 0x35420, 2471 0x35438, 0x3543c, 2472 0x35480, 0x35480, 2473 0x354a8, 0x354a8, 2474 0x354b0, 0x354b4, 2475 0x354c8, 0x354d4, 2476 0x35a40, 0x35a4c, 2477 0x35af0, 0x35b20, 2478 0x35b38, 0x35b3c, 2479 0x35b80, 0x35b80, 2480 0x35ba8, 0x35ba8, 2481 0x35bb0, 0x35bb4, 2482 0x35bc8, 0x35bd4, 2483 0x36140, 0x3618c, 2484 0x361f0, 0x361f4, 2485 0x36200, 0x36200, 2486 0x36218, 0x36218, 2487 0x36400, 0x36400, 2488 0x36408, 0x3641c, 2489 0x36618, 0x36620, 2490 0x36664, 0x36664, 2491 0x366a8, 0x366a8, 2492 0x366ec, 0x366ec, 2493 0x36a00, 0x36abc, 2494 0x36b00, 0x36b18, 2495 0x36b20, 0x36b38, 2496 0x36b40, 0x36b58, 2497 0x36b60, 0x36b78, 2498 0x36c00, 0x36c00, 2499 0x36c08, 0x36c3c, 2500 0x37000, 0x3702c, 2501 0x37034, 0x37050, 2502 0x37058, 0x37058, 2503 0x37060, 0x3708c, 2504 0x3709c, 0x370ac, 2505 0x370c0, 0x370c0, 2506 0x370c8, 0x370d0, 2507 0x370d8, 0x370e0, 2508 0x370ec, 0x3712c, 2509 0x37134, 0x37150, 2510 0x37158, 0x37158, 2511 0x37160, 0x3718c, 2512 0x3719c, 0x371ac, 2513 0x371c0, 0x371c0, 2514 0x371c8, 0x371d0, 2515 0x371d8, 0x371e0, 2516 0x371ec, 0x37290, 2517 0x37298, 0x372c4, 2518 0x372e4, 0x37390, 2519 0x37398, 0x373c4, 2520 0x373e4, 0x3742c, 2521 0x37434, 0x37450, 2522 0x37458, 0x37458, 2523 0x37460, 0x3748c, 2524 0x3749c, 0x374ac, 2525 0x374c0, 0x374c0, 2526 0x374c8, 0x374d0, 2527 0x374d8, 0x374e0, 2528 0x374ec, 0x3752c, 2529 0x37534, 0x37550, 2530 0x37558, 0x37558, 2531 0x37560, 0x3758c, 2532 0x3759c, 0x375ac, 2533 0x375c0, 0x375c0, 2534 0x375c8, 0x375d0, 2535 0x375d8, 0x375e0, 2536 0x375ec, 0x37690, 2537 0x37698, 0x376c4, 2538 0x376e4, 0x37790, 2539 0x37798, 0x377c4, 2540 0x377e4, 0x377fc, 2541 0x37814, 0x37814, 2542 0x37854, 0x37868, 2543 0x37880, 0x3788c, 2544 0x378c0, 0x378d0, 2545 0x378e8, 0x378ec, 2546 0x37900, 0x3792c, 2547 0x37934, 0x37950, 2548 0x37958, 0x37958, 2549 0x37960, 0x3798c, 2550 0x3799c, 0x379ac, 2551 0x379c0, 0x379c0, 2552 0x379c8, 0x379d0, 2553 0x379d8, 0x379e0, 2554 0x379ec, 0x37a90, 2555 0x37a98, 0x37ac4, 2556 0x37ae4, 0x37b10, 2557 0x37b24, 0x37b28, 2558 0x37b38, 0x37b50, 2559 0x37bf0, 0x37c10, 2560 0x37c24, 0x37c28, 2561 0x37c38, 0x37c50, 2562 0x37cf0, 0x37cfc, 2563 0x40040, 0x40040, 2564 0x40080, 0x40084, 2565 0x40100, 0x40100, 2566 0x40140, 0x401bc, 2567 0x40200, 0x40214, 2568 0x40228, 0x40228, 2569 0x40240, 0x40258, 2570 0x40280, 0x40280, 2571 0x40304, 0x40304, 2572 0x40330, 0x4033c, 2573 0x41304, 0x413c8, 2574 0x413d0, 0x413dc, 2575 0x413f0, 0x413f0, 2576 0x41400, 0x4140c, 2577 0x41414, 0x4141c, 2578 0x41480, 0x414d0, 2579 0x44000, 0x4407c, 2580 0x440c0, 0x441ac, 2581 0x441b4, 0x4427c, 2582 0x442c0, 0x443ac, 2583 0x443b4, 0x4447c, 2584 0x444c0, 0x445ac, 2585 0x445b4, 0x4467c, 2586 0x446c0, 0x447ac, 2587 0x447b4, 0x4487c, 2588 0x448c0, 0x449ac, 2589 0x449b4, 0x44a7c, 2590 0x44ac0, 0x44bac, 2591 0x44bb4, 0x44c7c, 2592 0x44cc0, 0x44dac, 2593 0x44db4, 0x44e7c, 2594 0x44ec0, 0x44fac, 2595 0x44fb4, 0x4507c, 2596 0x450c0, 0x451ac, 2597 0x451b4, 0x451fc, 2598 0x45800, 0x45804, 2599 0x45810, 0x45830, 2600 0x45840, 0x45860, 2601 0x45868, 0x45868, 2602 0x45880, 0x45884, 2603 0x458a0, 0x458b0, 2604 0x45a00, 0x45a04, 2605 0x45a10, 0x45a30, 2606 0x45a40, 0x45a60, 2607 0x45a68, 0x45a68, 2608 0x45a80, 0x45a84, 2609 0x45aa0, 0x45ab0, 2610 0x460c0, 0x460e4, 2611 0x47000, 0x4703c, 2612 0x47044, 0x4708c, 2613 0x47200, 0x47250, 2614 0x47400, 0x47408, 2615 0x47414, 0x47420, 2616 0x47600, 0x47618, 2617 0x47800, 0x47814, 2618 0x47820, 0x4782c, 2619 0x50000, 0x50084, 2620 0x50090, 0x500cc, 2621 0x50300, 0x50384, 2622 0x50400, 0x50400, 2623 0x50800, 0x50884, 2624 0x50890, 0x508cc, 2625 0x50b00, 0x50b84, 2626 0x50c00, 0x50c00, 2627 0x51000, 0x51020, 2628 0x51028, 0x510b0, 2629 0x51300, 0x51324, 2630 }; 2631 2632 static const unsigned int t6vf_reg_ranges[] = { 2633 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2634 VF_MPS_REG(A_MPS_VF_CTL), 2635 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2636 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2637 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2638 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2639 FW_T6VF_MBDATA_BASE_ADDR, 2640 FW_T6VF_MBDATA_BASE_ADDR + 2641 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2642 }; 2643 2644 u32 *buf_end = (u32 *)(buf + buf_size); 2645 const unsigned int *reg_ranges; 2646 int reg_ranges_size, range; 2647 unsigned int chip_version = chip_id(adap); 2648 2649 /* 2650 * Select the right set of register ranges to dump depending on the 2651 * adapter chip type. 2652 */ 2653 switch (chip_version) { 2654 case CHELSIO_T4: 2655 if (adap->flags & IS_VF) { 2656 reg_ranges = t4vf_reg_ranges; 2657 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2658 } else { 2659 reg_ranges = t4_reg_ranges; 2660 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2661 } 2662 break; 2663 2664 case CHELSIO_T5: 2665 if (adap->flags & IS_VF) { 2666 reg_ranges = t5vf_reg_ranges; 2667 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2668 } else { 2669 reg_ranges = t5_reg_ranges; 2670 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2671 } 2672 break; 2673 2674 case CHELSIO_T6: 2675 if (adap->flags & IS_VF) { 2676 reg_ranges = t6vf_reg_ranges; 2677 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2678 } else { 2679 reg_ranges = t6_reg_ranges; 2680 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2681 } 2682 break; 2683 2684 default: 2685 CH_ERR(adap, 2686 "Unsupported chip version %d\n", chip_version); 2687 return; 2688 } 2689 2690 /* 2691 * Clear the register buffer and insert the appropriate register 2692 * values selected by the above register ranges. 2693 */ 2694 memset(buf, 0, buf_size); 2695 for (range = 0; range < reg_ranges_size; range += 2) { 2696 unsigned int reg = reg_ranges[range]; 2697 unsigned int last_reg = reg_ranges[range + 1]; 2698 u32 *bufp = (u32 *)(buf + reg); 2699 2700 /* 2701 * Iterate across the register range filling in the register 2702 * buffer but don't write past the end of the register buffer. 2703 */ 2704 while (reg <= last_reg && bufp < buf_end) { 2705 *bufp++ = t4_read_reg(adap, reg); 2706 reg += sizeof(u32); 2707 } 2708 } 2709 } 2710 2711 /* 2712 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2713 * header followed by one or more VPD-R sections, each with its own header. 2714 */ 2715 struct t4_vpd_hdr { 2716 u8 id_tag; 2717 u8 id_len[2]; 2718 u8 id_data[ID_LEN]; 2719 }; 2720 2721 struct t4_vpdr_hdr { 2722 u8 vpdr_tag; 2723 u8 vpdr_len[2]; 2724 }; 2725 2726 /* 2727 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2728 */ 2729 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2730 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2731 2732 #define EEPROM_STAT_ADDR 0x7bfc 2733 #define VPD_SIZE 0x800 2734 #define VPD_BASE 0x400 2735 #define VPD_BASE_OLD 0 2736 #define VPD_LEN 1024 2737 #define VPD_INFO_FLD_HDR_SIZE 3 2738 #define CHELSIO_VPD_UNIQUE_ID 0x82 2739 2740 /* 2741 * Small utility function to wait till any outstanding VPD Access is complete. 2742 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2743 * VPD Access in flight. This allows us to handle the problem of having a 2744 * previous VPD Access time out and prevent an attempt to inject a new VPD 2745 * Request before any in-flight VPD reguest has completed. 2746 */ 2747 static int t4_seeprom_wait(struct adapter *adapter) 2748 { 2749 unsigned int base = adapter->params.pci.vpd_cap_addr; 2750 int max_poll; 2751 2752 /* 2753 * If no VPD Access is in flight, we can just return success right 2754 * away. 2755 */ 2756 if (!adapter->vpd_busy) 2757 return 0; 2758 2759 /* 2760 * Poll the VPD Capability Address/Flag register waiting for it 2761 * to indicate that the operation is complete. 2762 */ 2763 max_poll = EEPROM_MAX_POLL; 2764 do { 2765 u16 val; 2766 2767 udelay(EEPROM_DELAY); 2768 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2769 2770 /* 2771 * If the operation is complete, mark the VPD as no longer 2772 * busy and return success. 2773 */ 2774 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2775 adapter->vpd_busy = 0; 2776 return 0; 2777 } 2778 } while (--max_poll); 2779 2780 /* 2781 * Failure! Note that we leave the VPD Busy status set in order to 2782 * avoid pushing a new VPD Access request into the VPD Capability till 2783 * the current operation eventually succeeds. It's a bug to issue a 2784 * new request when an existing request is in flight and will result 2785 * in corrupt hardware state. 2786 */ 2787 return -ETIMEDOUT; 2788 } 2789 2790 /** 2791 * t4_seeprom_read - read a serial EEPROM location 2792 * @adapter: adapter to read 2793 * @addr: EEPROM virtual address 2794 * @data: where to store the read data 2795 * 2796 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2797 * VPD capability. Note that this function must be called with a virtual 2798 * address. 2799 */ 2800 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2801 { 2802 unsigned int base = adapter->params.pci.vpd_cap_addr; 2803 int ret; 2804 2805 /* 2806 * VPD Accesses must alway be 4-byte aligned! 2807 */ 2808 if (addr >= EEPROMVSIZE || (addr & 3)) 2809 return -EINVAL; 2810 2811 /* 2812 * Wait for any previous operation which may still be in flight to 2813 * complete. 2814 */ 2815 ret = t4_seeprom_wait(adapter); 2816 if (ret) { 2817 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2818 return ret; 2819 } 2820 2821 /* 2822 * Issue our new VPD Read request, mark the VPD as being busy and wait 2823 * for our request to complete. If it doesn't complete, note the 2824 * error and return it to our caller. Note that we do not reset the 2825 * VPD Busy status! 2826 */ 2827 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2828 adapter->vpd_busy = 1; 2829 adapter->vpd_flag = PCI_VPD_ADDR_F; 2830 ret = t4_seeprom_wait(adapter); 2831 if (ret) { 2832 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2833 return ret; 2834 } 2835 2836 /* 2837 * Grab the returned data, swizzle it into our endianness and 2838 * return success. 2839 */ 2840 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2841 *data = le32_to_cpu(*data); 2842 return 0; 2843 } 2844 2845 /** 2846 * t4_seeprom_write - write a serial EEPROM location 2847 * @adapter: adapter to write 2848 * @addr: virtual EEPROM address 2849 * @data: value to write 2850 * 2851 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2852 * VPD capability. Note that this function must be called with a virtual 2853 * address. 2854 */ 2855 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2856 { 2857 unsigned int base = adapter->params.pci.vpd_cap_addr; 2858 int ret; 2859 u32 stats_reg; 2860 int max_poll; 2861 2862 /* 2863 * VPD Accesses must alway be 4-byte aligned! 2864 */ 2865 if (addr >= EEPROMVSIZE || (addr & 3)) 2866 return -EINVAL; 2867 2868 /* 2869 * Wait for any previous operation which may still be in flight to 2870 * complete. 2871 */ 2872 ret = t4_seeprom_wait(adapter); 2873 if (ret) { 2874 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2875 return ret; 2876 } 2877 2878 /* 2879 * Issue our new VPD Read request, mark the VPD as being busy and wait 2880 * for our request to complete. If it doesn't complete, note the 2881 * error and return it to our caller. Note that we do not reset the 2882 * VPD Busy status! 2883 */ 2884 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2885 cpu_to_le32(data)); 2886 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2887 (u16)addr | PCI_VPD_ADDR_F); 2888 adapter->vpd_busy = 1; 2889 adapter->vpd_flag = 0; 2890 ret = t4_seeprom_wait(adapter); 2891 if (ret) { 2892 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2893 return ret; 2894 } 2895 2896 /* 2897 * Reset PCI_VPD_DATA register after a transaction and wait for our 2898 * request to complete. If it doesn't complete, return error. 2899 */ 2900 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2901 max_poll = EEPROM_MAX_POLL; 2902 do { 2903 udelay(EEPROM_DELAY); 2904 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2905 } while ((stats_reg & 0x1) && --max_poll); 2906 if (!max_poll) 2907 return -ETIMEDOUT; 2908 2909 /* Return success! */ 2910 return 0; 2911 } 2912 2913 /** 2914 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2915 * @phys_addr: the physical EEPROM address 2916 * @fn: the PCI function number 2917 * @sz: size of function-specific area 2918 * 2919 * Translate a physical EEPROM address to virtual. The first 1K is 2920 * accessed through virtual addresses starting at 31K, the rest is 2921 * accessed through virtual addresses starting at 0. 2922 * 2923 * The mapping is as follows: 2924 * [0..1K) -> [31K..32K) 2925 * [1K..1K+A) -> [ES-A..ES) 2926 * [1K+A..ES) -> [0..ES-A-1K) 2927 * 2928 * where A = @fn * @sz, and ES = EEPROM size. 2929 */ 2930 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2931 { 2932 fn *= sz; 2933 if (phys_addr < 1024) 2934 return phys_addr + (31 << 10); 2935 if (phys_addr < 1024 + fn) 2936 return EEPROMSIZE - fn + phys_addr - 1024; 2937 if (phys_addr < EEPROMSIZE) 2938 return phys_addr - 1024 - fn; 2939 return -EINVAL; 2940 } 2941 2942 /** 2943 * t4_seeprom_wp - enable/disable EEPROM write protection 2944 * @adapter: the adapter 2945 * @enable: whether to enable or disable write protection 2946 * 2947 * Enables or disables write protection on the serial EEPROM. 2948 */ 2949 int t4_seeprom_wp(struct adapter *adapter, int enable) 2950 { 2951 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2952 } 2953 2954 /** 2955 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2956 * @vpd: Pointer to buffered vpd data structure 2957 * @kw: The keyword to search for 2958 * @region: VPD region to search (starting from 0) 2959 * 2960 * Returns the value of the information field keyword or 2961 * -ENOENT otherwise. 2962 */ 2963 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2964 { 2965 int i, tag; 2966 unsigned int offset, len; 2967 const struct t4_vpdr_hdr *vpdr; 2968 2969 offset = sizeof(struct t4_vpd_hdr); 2970 vpdr = (const void *)(vpd + offset); 2971 tag = vpdr->vpdr_tag; 2972 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2973 while (region--) { 2974 offset += sizeof(struct t4_vpdr_hdr) + len; 2975 vpdr = (const void *)(vpd + offset); 2976 if (++tag != vpdr->vpdr_tag) 2977 return -ENOENT; 2978 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2979 } 2980 offset += sizeof(struct t4_vpdr_hdr); 2981 2982 if (offset + len > VPD_LEN) { 2983 return -ENOENT; 2984 } 2985 2986 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2987 if (memcmp(vpd + i , kw , 2) == 0){ 2988 i += VPD_INFO_FLD_HDR_SIZE; 2989 return i; 2990 } 2991 2992 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2993 } 2994 2995 return -ENOENT; 2996 } 2997 2998 2999 /** 3000 * get_vpd_params - read VPD parameters from VPD EEPROM 3001 * @adapter: adapter to read 3002 * @p: where to store the parameters 3003 * @vpd: caller provided temporary space to read the VPD into 3004 * 3005 * Reads card parameters stored in VPD EEPROM. 3006 */ 3007 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3008 uint16_t device_id, u32 *buf) 3009 { 3010 int i, ret, addr; 3011 int ec, sn, pn, na, md; 3012 u8 csum; 3013 const u8 *vpd = (const u8 *)buf; 3014 3015 /* 3016 * Card information normally starts at VPD_BASE but early cards had 3017 * it at 0. 3018 */ 3019 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3020 if (ret) 3021 return (ret); 3022 3023 /* 3024 * The VPD shall have a unique identifier specified by the PCI SIG. 3025 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3026 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3027 * is expected to automatically put this entry at the 3028 * beginning of the VPD. 3029 */ 3030 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3031 3032 for (i = 0; i < VPD_LEN; i += 4) { 3033 ret = t4_seeprom_read(adapter, addr + i, buf++); 3034 if (ret) 3035 return ret; 3036 } 3037 3038 #define FIND_VPD_KW(var,name) do { \ 3039 var = get_vpd_keyword_val(vpd, name, 0); \ 3040 if (var < 0) { \ 3041 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3042 return -EINVAL; \ 3043 } \ 3044 } while (0) 3045 3046 FIND_VPD_KW(i, "RV"); 3047 for (csum = 0; i >= 0; i--) 3048 csum += vpd[i]; 3049 3050 if (csum) { 3051 CH_ERR(adapter, 3052 "corrupted VPD EEPROM, actual csum %u\n", csum); 3053 return -EINVAL; 3054 } 3055 3056 FIND_VPD_KW(ec, "EC"); 3057 FIND_VPD_KW(sn, "SN"); 3058 FIND_VPD_KW(pn, "PN"); 3059 FIND_VPD_KW(na, "NA"); 3060 #undef FIND_VPD_KW 3061 3062 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3063 strstrip(p->id); 3064 memcpy(p->ec, vpd + ec, EC_LEN); 3065 strstrip(p->ec); 3066 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3067 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3068 strstrip(p->sn); 3069 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3070 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3071 strstrip((char *)p->pn); 3072 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3073 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3074 strstrip((char *)p->na); 3075 3076 if (device_id & 0x80) 3077 return 0; /* Custom card */ 3078 3079 md = get_vpd_keyword_val(vpd, "VF", 1); 3080 if (md < 0) { 3081 snprintf(p->md, sizeof(p->md), "unknown"); 3082 } else { 3083 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3084 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3085 strstrip((char *)p->md); 3086 } 3087 3088 return 0; 3089 } 3090 3091 /* serial flash and firmware constants and flash config file constants */ 3092 enum { 3093 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3094 3095 /* flash command opcodes */ 3096 SF_PROG_PAGE = 2, /* program 256B page */ 3097 SF_WR_DISABLE = 4, /* disable writes */ 3098 SF_RD_STATUS = 5, /* read status register */ 3099 SF_WR_ENABLE = 6, /* enable writes */ 3100 SF_RD_DATA_FAST = 0xb, /* read flash */ 3101 SF_RD_ID = 0x9f, /* read ID */ 3102 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3103 }; 3104 3105 /** 3106 * sf1_read - read data from the serial flash 3107 * @adapter: the adapter 3108 * @byte_cnt: number of bytes to read 3109 * @cont: whether another operation will be chained 3110 * @lock: whether to lock SF for PL access only 3111 * @valp: where to store the read data 3112 * 3113 * Reads up to 4 bytes of data from the serial flash. The location of 3114 * the read needs to be specified prior to calling this by issuing the 3115 * appropriate commands to the serial flash. 3116 */ 3117 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3118 int lock, u32 *valp) 3119 { 3120 int ret; 3121 3122 if (!byte_cnt || byte_cnt > 4) 3123 return -EINVAL; 3124 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3125 return -EBUSY; 3126 t4_write_reg(adapter, A_SF_OP, 3127 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3128 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3129 if (!ret) 3130 *valp = t4_read_reg(adapter, A_SF_DATA); 3131 return ret; 3132 } 3133 3134 /** 3135 * sf1_write - write data to the serial flash 3136 * @adapter: the adapter 3137 * @byte_cnt: number of bytes to write 3138 * @cont: whether another operation will be chained 3139 * @lock: whether to lock SF for PL access only 3140 * @val: value to write 3141 * 3142 * Writes up to 4 bytes of data to the serial flash. The location of 3143 * the write needs to be specified prior to calling this by issuing the 3144 * appropriate commands to the serial flash. 3145 */ 3146 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3147 int lock, u32 val) 3148 { 3149 if (!byte_cnt || byte_cnt > 4) 3150 return -EINVAL; 3151 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3152 return -EBUSY; 3153 t4_write_reg(adapter, A_SF_DATA, val); 3154 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3155 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3156 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3157 } 3158 3159 /** 3160 * flash_wait_op - wait for a flash operation to complete 3161 * @adapter: the adapter 3162 * @attempts: max number of polls of the status register 3163 * @delay: delay between polls in ms 3164 * 3165 * Wait for a flash operation to complete by polling the status register. 3166 */ 3167 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3168 { 3169 int ret; 3170 u32 status; 3171 3172 while (1) { 3173 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3174 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3175 return ret; 3176 if (!(status & 1)) 3177 return 0; 3178 if (--attempts == 0) 3179 return -EAGAIN; 3180 if (delay) 3181 msleep(delay); 3182 } 3183 } 3184 3185 /** 3186 * t4_read_flash - read words from serial flash 3187 * @adapter: the adapter 3188 * @addr: the start address for the read 3189 * @nwords: how many 32-bit words to read 3190 * @data: where to store the read data 3191 * @byte_oriented: whether to store data as bytes or as words 3192 * 3193 * Read the specified number of 32-bit words from the serial flash. 3194 * If @byte_oriented is set the read data is stored as a byte array 3195 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3196 * natural endianness. 3197 */ 3198 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3199 unsigned int nwords, u32 *data, int byte_oriented) 3200 { 3201 int ret; 3202 3203 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3204 return -EINVAL; 3205 3206 addr = swab32(addr) | SF_RD_DATA_FAST; 3207 3208 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3209 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3210 return ret; 3211 3212 for ( ; nwords; nwords--, data++) { 3213 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3214 if (nwords == 1) 3215 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3216 if (ret) 3217 return ret; 3218 if (byte_oriented) 3219 *data = (__force __u32)(cpu_to_be32(*data)); 3220 } 3221 return 0; 3222 } 3223 3224 /** 3225 * t4_write_flash - write up to a page of data to the serial flash 3226 * @adapter: the adapter 3227 * @addr: the start address to write 3228 * @n: length of data to write in bytes 3229 * @data: the data to write 3230 * @byte_oriented: whether to store data as bytes or as words 3231 * 3232 * Writes up to a page of data (256 bytes) to the serial flash starting 3233 * at the given address. All the data must be written to the same page. 3234 * If @byte_oriented is set the write data is stored as byte stream 3235 * (i.e. matches what on disk), otherwise in big-endian. 3236 */ 3237 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3238 unsigned int n, const u8 *data, int byte_oriented) 3239 { 3240 int ret; 3241 u32 buf[SF_PAGE_SIZE / 4]; 3242 unsigned int i, c, left, val, offset = addr & 0xff; 3243 3244 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3245 return -EINVAL; 3246 3247 val = swab32(addr) | SF_PROG_PAGE; 3248 3249 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3250 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3251 goto unlock; 3252 3253 for (left = n; left; left -= c) { 3254 c = min(left, 4U); 3255 for (val = 0, i = 0; i < c; ++i) 3256 val = (val << 8) + *data++; 3257 3258 if (!byte_oriented) 3259 val = cpu_to_be32(val); 3260 3261 ret = sf1_write(adapter, c, c != left, 1, val); 3262 if (ret) 3263 goto unlock; 3264 } 3265 ret = flash_wait_op(adapter, 8, 1); 3266 if (ret) 3267 goto unlock; 3268 3269 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3270 3271 /* Read the page to verify the write succeeded */ 3272 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3273 byte_oriented); 3274 if (ret) 3275 return ret; 3276 3277 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3278 CH_ERR(adapter, 3279 "failed to correctly write the flash page at %#x\n", 3280 addr); 3281 return -EIO; 3282 } 3283 return 0; 3284 3285 unlock: 3286 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3287 return ret; 3288 } 3289 3290 /** 3291 * t4_get_fw_version - read the firmware version 3292 * @adapter: the adapter 3293 * @vers: where to place the version 3294 * 3295 * Reads the FW version from flash. 3296 */ 3297 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3298 { 3299 return t4_read_flash(adapter, FLASH_FW_START + 3300 offsetof(struct fw_hdr, fw_ver), 1, 3301 vers, 0); 3302 } 3303 3304 /** 3305 * t4_get_fw_hdr - read the firmware header 3306 * @adapter: the adapter 3307 * @hdr: where to place the version 3308 * 3309 * Reads the FW header from flash into caller provided buffer. 3310 */ 3311 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3312 { 3313 return t4_read_flash(adapter, FLASH_FW_START, 3314 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3315 } 3316 3317 /** 3318 * t4_get_bs_version - read the firmware bootstrap version 3319 * @adapter: the adapter 3320 * @vers: where to place the version 3321 * 3322 * Reads the FW Bootstrap version from flash. 3323 */ 3324 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3325 { 3326 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3327 offsetof(struct fw_hdr, fw_ver), 1, 3328 vers, 0); 3329 } 3330 3331 /** 3332 * t4_get_tp_version - read the TP microcode version 3333 * @adapter: the adapter 3334 * @vers: where to place the version 3335 * 3336 * Reads the TP microcode version from flash. 3337 */ 3338 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3339 { 3340 return t4_read_flash(adapter, FLASH_FW_START + 3341 offsetof(struct fw_hdr, tp_microcode_ver), 3342 1, vers, 0); 3343 } 3344 3345 /** 3346 * t4_get_exprom_version - return the Expansion ROM version (if any) 3347 * @adapter: the adapter 3348 * @vers: where to place the version 3349 * 3350 * Reads the Expansion ROM header from FLASH and returns the version 3351 * number (if present) through the @vers return value pointer. We return 3352 * this in the Firmware Version Format since it's convenient. Return 3353 * 0 on success, -ENOENT if no Expansion ROM is present. 3354 */ 3355 int t4_get_exprom_version(struct adapter *adapter, u32 *vers) 3356 { 3357 struct exprom_header { 3358 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3359 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3360 } *hdr; 3361 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3362 sizeof(u32))]; 3363 int ret; 3364 3365 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START, 3366 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3367 0); 3368 if (ret) 3369 return ret; 3370 3371 hdr = (struct exprom_header *)exprom_header_buf; 3372 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3373 return -ENOENT; 3374 3375 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3376 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3377 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3378 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3379 return 0; 3380 } 3381 3382 /** 3383 * t4_get_scfg_version - return the Serial Configuration version 3384 * @adapter: the adapter 3385 * @vers: where to place the version 3386 * 3387 * Reads the Serial Configuration Version via the Firmware interface 3388 * (thus this can only be called once we're ready to issue Firmware 3389 * commands). The format of the Serial Configuration version is 3390 * adapter specific. Returns 0 on success, an error on failure. 3391 * 3392 * Note that early versions of the Firmware didn't include the ability 3393 * to retrieve the Serial Configuration version, so we zero-out the 3394 * return-value parameter in that case to avoid leaving it with 3395 * garbage in it. 3396 * 3397 * Also note that the Firmware will return its cached copy of the Serial 3398 * Initialization Revision ID, not the actual Revision ID as written in 3399 * the Serial EEPROM. This is only an issue if a new VPD has been written 3400 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3401 * it's best to defer calling this routine till after a FW_RESET_CMD has 3402 * been issued if the Host Driver will be performing a full adapter 3403 * initialization. 3404 */ 3405 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3406 { 3407 u32 scfgrev_param; 3408 int ret; 3409 3410 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3411 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3412 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3413 1, &scfgrev_param, vers); 3414 if (ret) 3415 *vers = 0; 3416 return ret; 3417 } 3418 3419 /** 3420 * t4_get_vpd_version - return the VPD version 3421 * @adapter: the adapter 3422 * @vers: where to place the version 3423 * 3424 * Reads the VPD via the Firmware interface (thus this can only be called 3425 * once we're ready to issue Firmware commands). The format of the 3426 * VPD version is adapter specific. Returns 0 on success, an error on 3427 * failure. 3428 * 3429 * Note that early versions of the Firmware didn't include the ability 3430 * to retrieve the VPD version, so we zero-out the return-value parameter 3431 * in that case to avoid leaving it with garbage in it. 3432 * 3433 * Also note that the Firmware will return its cached copy of the VPD 3434 * Revision ID, not the actual Revision ID as written in the Serial 3435 * EEPROM. This is only an issue if a new VPD has been written and the 3436 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3437 * to defer calling this routine till after a FW_RESET_CMD has been issued 3438 * if the Host Driver will be performing a full adapter initialization. 3439 */ 3440 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3441 { 3442 u32 vpdrev_param; 3443 int ret; 3444 3445 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3446 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3447 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3448 1, &vpdrev_param, vers); 3449 if (ret) 3450 *vers = 0; 3451 return ret; 3452 } 3453 3454 /** 3455 * t4_get_version_info - extract various chip/firmware version information 3456 * @adapter: the adapter 3457 * 3458 * Reads various chip/firmware version numbers and stores them into the 3459 * adapter Adapter Parameters structure. If any of the efforts fails 3460 * the first failure will be returned, but all of the version numbers 3461 * will be read. 3462 */ 3463 int t4_get_version_info(struct adapter *adapter) 3464 { 3465 int ret = 0; 3466 3467 #define FIRST_RET(__getvinfo) \ 3468 do { \ 3469 int __ret = __getvinfo; \ 3470 if (__ret && !ret) \ 3471 ret = __ret; \ 3472 } while (0) 3473 3474 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3475 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3476 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3477 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3478 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3479 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3480 3481 #undef FIRST_RET 3482 3483 return ret; 3484 } 3485 3486 /** 3487 * t4_flash_erase_sectors - erase a range of flash sectors 3488 * @adapter: the adapter 3489 * @start: the first sector to erase 3490 * @end: the last sector to erase 3491 * 3492 * Erases the sectors in the given inclusive range. 3493 */ 3494 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3495 { 3496 int ret = 0; 3497 3498 if (end >= adapter->params.sf_nsec) 3499 return -EINVAL; 3500 3501 while (start <= end) { 3502 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3503 (ret = sf1_write(adapter, 4, 0, 1, 3504 SF_ERASE_SECTOR | (start << 8))) != 0 || 3505 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3506 CH_ERR(adapter, 3507 "erase of flash sector %d failed, error %d\n", 3508 start, ret); 3509 break; 3510 } 3511 start++; 3512 } 3513 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3514 return ret; 3515 } 3516 3517 /** 3518 * t4_flash_cfg_addr - return the address of the flash configuration file 3519 * @adapter: the adapter 3520 * 3521 * Return the address within the flash where the Firmware Configuration 3522 * File is stored, or an error if the device FLASH is too small to contain 3523 * a Firmware Configuration File. 3524 */ 3525 int t4_flash_cfg_addr(struct adapter *adapter) 3526 { 3527 /* 3528 * If the device FLASH isn't large enough to hold a Firmware 3529 * Configuration File, return an error. 3530 */ 3531 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3532 return -ENOSPC; 3533 3534 return FLASH_CFG_START; 3535 } 3536 3537 /* 3538 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3539 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3540 * and emit an error message for mismatched firmware to save our caller the 3541 * effort ... 3542 */ 3543 static int t4_fw_matches_chip(struct adapter *adap, 3544 const struct fw_hdr *hdr) 3545 { 3546 /* 3547 * The expression below will return FALSE for any unsupported adapter 3548 * which will keep us "honest" in the future ... 3549 */ 3550 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3551 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3552 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3553 return 1; 3554 3555 CH_ERR(adap, 3556 "FW image (%d) is not suitable for this adapter (%d)\n", 3557 hdr->chip, chip_id(adap)); 3558 return 0; 3559 } 3560 3561 /** 3562 * t4_load_fw - download firmware 3563 * @adap: the adapter 3564 * @fw_data: the firmware image to write 3565 * @size: image size 3566 * 3567 * Write the supplied firmware image to the card's serial flash. 3568 */ 3569 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3570 { 3571 u32 csum; 3572 int ret, addr; 3573 unsigned int i; 3574 u8 first_page[SF_PAGE_SIZE]; 3575 const u32 *p = (const u32 *)fw_data; 3576 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3577 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3578 unsigned int fw_start_sec; 3579 unsigned int fw_start; 3580 unsigned int fw_size; 3581 3582 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3583 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3584 fw_start = FLASH_FWBOOTSTRAP_START; 3585 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3586 } else { 3587 fw_start_sec = FLASH_FW_START_SEC; 3588 fw_start = FLASH_FW_START; 3589 fw_size = FLASH_FW_MAX_SIZE; 3590 } 3591 3592 if (!size) { 3593 CH_ERR(adap, "FW image has no data\n"); 3594 return -EINVAL; 3595 } 3596 if (size & 511) { 3597 CH_ERR(adap, 3598 "FW image size not multiple of 512 bytes\n"); 3599 return -EINVAL; 3600 } 3601 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3602 CH_ERR(adap, 3603 "FW image size differs from size in FW header\n"); 3604 return -EINVAL; 3605 } 3606 if (size > fw_size) { 3607 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3608 fw_size); 3609 return -EFBIG; 3610 } 3611 if (!t4_fw_matches_chip(adap, hdr)) 3612 return -EINVAL; 3613 3614 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3615 csum += be32_to_cpu(p[i]); 3616 3617 if (csum != 0xffffffff) { 3618 CH_ERR(adap, 3619 "corrupted firmware image, checksum %#x\n", csum); 3620 return -EINVAL; 3621 } 3622 3623 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3624 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3625 if (ret) 3626 goto out; 3627 3628 /* 3629 * We write the correct version at the end so the driver can see a bad 3630 * version if the FW write fails. Start by writing a copy of the 3631 * first page with a bad version. 3632 */ 3633 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3634 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3635 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3636 if (ret) 3637 goto out; 3638 3639 addr = fw_start; 3640 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3641 addr += SF_PAGE_SIZE; 3642 fw_data += SF_PAGE_SIZE; 3643 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3644 if (ret) 3645 goto out; 3646 } 3647 3648 ret = t4_write_flash(adap, 3649 fw_start + offsetof(struct fw_hdr, fw_ver), 3650 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3651 out: 3652 if (ret) 3653 CH_ERR(adap, "firmware download failed, error %d\n", 3654 ret); 3655 return ret; 3656 } 3657 3658 /** 3659 * t4_fwcache - firmware cache operation 3660 * @adap: the adapter 3661 * @op : the operation (flush or flush and invalidate) 3662 */ 3663 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3664 { 3665 struct fw_params_cmd c; 3666 3667 memset(&c, 0, sizeof(c)); 3668 c.op_to_vfn = 3669 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3670 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3671 V_FW_PARAMS_CMD_PFN(adap->pf) | 3672 V_FW_PARAMS_CMD_VFN(0)); 3673 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3674 c.param[0].mnem = 3675 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3676 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3677 c.param[0].val = (__force __be32)op; 3678 3679 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3680 } 3681 3682 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3683 unsigned int *pif_req_wrptr, 3684 unsigned int *pif_rsp_wrptr) 3685 { 3686 int i, j; 3687 u32 cfg, val, req, rsp; 3688 3689 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3690 if (cfg & F_LADBGEN) 3691 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3692 3693 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3694 req = G_POLADBGWRPTR(val); 3695 rsp = G_PILADBGWRPTR(val); 3696 if (pif_req_wrptr) 3697 *pif_req_wrptr = req; 3698 if (pif_rsp_wrptr) 3699 *pif_rsp_wrptr = rsp; 3700 3701 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3702 for (j = 0; j < 6; j++) { 3703 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3704 V_PILADBGRDPTR(rsp)); 3705 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3706 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3707 req++; 3708 rsp++; 3709 } 3710 req = (req + 2) & M_POLADBGRDPTR; 3711 rsp = (rsp + 2) & M_PILADBGRDPTR; 3712 } 3713 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3714 } 3715 3716 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3717 { 3718 u32 cfg; 3719 int i, j, idx; 3720 3721 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3722 if (cfg & F_LADBGEN) 3723 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3724 3725 for (i = 0; i < CIM_MALA_SIZE; i++) { 3726 for (j = 0; j < 5; j++) { 3727 idx = 8 * i + j; 3728 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3729 V_PILADBGRDPTR(idx)); 3730 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3731 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3732 } 3733 } 3734 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3735 } 3736 3737 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3738 { 3739 unsigned int i, j; 3740 3741 for (i = 0; i < 8; i++) { 3742 u32 *p = la_buf + i; 3743 3744 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3745 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3746 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3747 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3748 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3749 } 3750 } 3751 3752 /** 3753 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3754 * @caps16: a 16-bit Port Capabilities value 3755 * 3756 * Returns the equivalent 32-bit Port Capabilities value. 3757 */ 3758 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3759 { 3760 uint32_t caps32 = 0; 3761 3762 #define CAP16_TO_CAP32(__cap) \ 3763 do { \ 3764 if (caps16 & FW_PORT_CAP_##__cap) \ 3765 caps32 |= FW_PORT_CAP32_##__cap; \ 3766 } while (0) 3767 3768 CAP16_TO_CAP32(SPEED_100M); 3769 CAP16_TO_CAP32(SPEED_1G); 3770 CAP16_TO_CAP32(SPEED_25G); 3771 CAP16_TO_CAP32(SPEED_10G); 3772 CAP16_TO_CAP32(SPEED_40G); 3773 CAP16_TO_CAP32(SPEED_100G); 3774 CAP16_TO_CAP32(FC_RX); 3775 CAP16_TO_CAP32(FC_TX); 3776 CAP16_TO_CAP32(ANEG); 3777 CAP16_TO_CAP32(FORCE_PAUSE); 3778 CAP16_TO_CAP32(MDIAUTO); 3779 CAP16_TO_CAP32(MDISTRAIGHT); 3780 CAP16_TO_CAP32(FEC_RS); 3781 CAP16_TO_CAP32(FEC_BASER_RS); 3782 CAP16_TO_CAP32(802_3_PAUSE); 3783 CAP16_TO_CAP32(802_3_ASM_DIR); 3784 3785 #undef CAP16_TO_CAP32 3786 3787 return caps32; 3788 } 3789 3790 /** 3791 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3792 * @caps32: a 32-bit Port Capabilities value 3793 * 3794 * Returns the equivalent 16-bit Port Capabilities value. Note that 3795 * not all 32-bit Port Capabilities can be represented in the 16-bit 3796 * Port Capabilities and some fields/values may not make it. 3797 */ 3798 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3799 { 3800 uint16_t caps16 = 0; 3801 3802 #define CAP32_TO_CAP16(__cap) \ 3803 do { \ 3804 if (caps32 & FW_PORT_CAP32_##__cap) \ 3805 caps16 |= FW_PORT_CAP_##__cap; \ 3806 } while (0) 3807 3808 CAP32_TO_CAP16(SPEED_100M); 3809 CAP32_TO_CAP16(SPEED_1G); 3810 CAP32_TO_CAP16(SPEED_10G); 3811 CAP32_TO_CAP16(SPEED_25G); 3812 CAP32_TO_CAP16(SPEED_40G); 3813 CAP32_TO_CAP16(SPEED_100G); 3814 CAP32_TO_CAP16(FC_RX); 3815 CAP32_TO_CAP16(FC_TX); 3816 CAP32_TO_CAP16(802_3_PAUSE); 3817 CAP32_TO_CAP16(802_3_ASM_DIR); 3818 CAP32_TO_CAP16(ANEG); 3819 CAP32_TO_CAP16(FORCE_PAUSE); 3820 CAP32_TO_CAP16(MDIAUTO); 3821 CAP32_TO_CAP16(MDISTRAIGHT); 3822 CAP32_TO_CAP16(FEC_RS); 3823 CAP32_TO_CAP16(FEC_BASER_RS); 3824 3825 #undef CAP32_TO_CAP16 3826 3827 return caps16; 3828 } 3829 3830 static bool 3831 is_bt(struct port_info *pi) 3832 { 3833 3834 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 3835 pi->port_type == FW_PORT_TYPE_BT_XFI || 3836 pi->port_type == FW_PORT_TYPE_BT_XAUI); 3837 } 3838 3839 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none) 3840 { 3841 int8_t fec = 0; 3842 3843 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) 3844 return (unset_means_none ? FEC_NONE : 0); 3845 3846 if (caps & FW_PORT_CAP32_FEC_RS) 3847 fec |= FEC_RS; 3848 if (caps & FW_PORT_CAP32_FEC_BASER_RS) 3849 fec |= FEC_BASER_RS; 3850 if (caps & FW_PORT_CAP32_FEC_NO_FEC) 3851 fec |= FEC_NONE; 3852 3853 return (fec); 3854 } 3855 3856 /* 3857 * Note that 0 is not translated to NO_FEC. 3858 */ 3859 static uint32_t fec_to_fwcap(int8_t fec) 3860 { 3861 uint32_t caps = 0; 3862 3863 /* Only real FECs allowed. */ 3864 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); 3865 3866 if (fec & FEC_RS) 3867 caps |= FW_PORT_CAP32_FEC_RS; 3868 if (fec & FEC_BASER_RS) 3869 caps |= FW_PORT_CAP32_FEC_BASER_RS; 3870 if (fec & FEC_NONE) 3871 caps |= FW_PORT_CAP32_FEC_NO_FEC; 3872 3873 return (caps); 3874 } 3875 3876 /** 3877 * t4_link_l1cfg - apply link configuration to MAC/PHY 3878 * @phy: the PHY to setup 3879 * @mac: the MAC to setup 3880 * @lc: the requested link configuration 3881 * 3882 * Set up a port's MAC and PHY according to a desired link configuration. 3883 * - If the PHY can auto-negotiate first decide what to advertise, then 3884 * enable/disable auto-negotiation as desired, and reset. 3885 * - If the PHY does not auto-negotiate just reset it. 3886 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3887 * otherwise do it later based on the outcome of auto-negotiation. 3888 */ 3889 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3890 struct link_config *lc) 3891 { 3892 struct fw_port_cmd c; 3893 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3894 unsigned int aneg, fc, fec, speed, rcap; 3895 3896 fc = 0; 3897 if (lc->requested_fc & PAUSE_RX) 3898 fc |= FW_PORT_CAP32_FC_RX; 3899 if (lc->requested_fc & PAUSE_TX) 3900 fc |= FW_PORT_CAP32_FC_TX; 3901 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3902 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3903 3904 if (lc->requested_aneg == AUTONEG_DISABLE) 3905 aneg = 0; 3906 else if (lc->requested_aneg == AUTONEG_ENABLE) 3907 aneg = FW_PORT_CAP32_ANEG; 3908 else 3909 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3910 3911 if (aneg) { 3912 speed = lc->pcaps & 3913 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3914 } else if (lc->requested_speed != 0) 3915 speed = speed_to_fwcap(lc->requested_speed); 3916 else 3917 speed = fwcap_top_speed(lc->pcaps); 3918 3919 fec = 0; 3920 #ifdef INVARIANTS 3921 if (lc->force_fec != 0) 3922 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_FEC); 3923 #endif 3924 if (fec_supported(speed)) { 3925 if (lc->requested_fec == FEC_AUTO) { 3926 if (lc->force_fec > 0) { 3927 /* 3928 * Must use FORCE_FEC even though requested FEC 3929 * is AUTO. Set all the FEC bits valid for the 3930 * speed and let the firmware pick one. 3931 */ 3932 fec |= FW_PORT_CAP32_FORCE_FEC; 3933 if (speed & FW_PORT_CAP32_SPEED_100G) { 3934 fec |= FW_PORT_CAP32_FEC_RS; 3935 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3936 } else { 3937 fec |= FW_PORT_CAP32_FEC_RS; 3938 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3939 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3940 } 3941 } else { 3942 /* 3943 * Set only 1b. Old firmwares can't deal with 3944 * multiple bits and new firmwares are free to 3945 * ignore this and try whatever FECs they want 3946 * because we aren't setting FORCE_FEC here. 3947 */ 3948 fec |= fec_to_fwcap(lc->fec_hint); 3949 } 3950 } else { 3951 /* 3952 * User has explicitly requested some FEC(s). Set 3953 * FORCE_FEC unless prohibited from using it. 3954 */ 3955 if (lc->force_fec != 0) 3956 fec |= FW_PORT_CAP32_FORCE_FEC; 3957 fec |= fec_to_fwcap(lc->requested_fec & 3958 M_FW_PORT_CAP32_FEC); 3959 if (lc->requested_fec & FEC_MODULE) 3960 fec |= fec_to_fwcap(lc->fec_hint); 3961 } 3962 } 3963 3964 /* Force AN on for BT cards. */ 3965 if (is_bt(adap->port[adap->chan_map[port]])) 3966 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3967 3968 rcap = aneg | speed | fc | fec; 3969 if ((rcap | lc->pcaps) != lc->pcaps) { 3970 #ifdef INVARIANTS 3971 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, 3972 lc->pcaps, rcap & (rcap ^ lc->pcaps)); 3973 #endif 3974 rcap &= lc->pcaps; 3975 } 3976 rcap |= mdi; 3977 3978 memset(&c, 0, sizeof(c)); 3979 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3980 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3981 V_FW_PORT_CMD_PORTID(port)); 3982 if (adap->params.port_caps32) { 3983 c.action_to_len16 = 3984 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3985 FW_LEN16(c)); 3986 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3987 } else { 3988 c.action_to_len16 = 3989 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3990 FW_LEN16(c)); 3991 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3992 } 3993 3994 lc->requested_caps = rcap; 3995 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3996 } 3997 3998 /** 3999 * t4_restart_aneg - restart autonegotiation 4000 * @adap: the adapter 4001 * @mbox: mbox to use for the FW command 4002 * @port: the port id 4003 * 4004 * Restarts autonegotiation for the selected port. 4005 */ 4006 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 4007 { 4008 struct fw_port_cmd c; 4009 4010 memset(&c, 0, sizeof(c)); 4011 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 4012 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 4013 V_FW_PORT_CMD_PORTID(port)); 4014 c.action_to_len16 = 4015 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4016 FW_LEN16(c)); 4017 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 4018 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4019 } 4020 4021 struct intr_details { 4022 u32 mask; 4023 const char *msg; 4024 }; 4025 4026 struct intr_action { 4027 u32 mask; 4028 int arg; 4029 bool (*action)(struct adapter *, int, bool); 4030 }; 4031 4032 #define NONFATAL_IF_DISABLED 1 4033 struct intr_info { 4034 const char *name; /* name of the INT_CAUSE register */ 4035 int cause_reg; /* INT_CAUSE register */ 4036 int enable_reg; /* INT_ENABLE register */ 4037 u32 fatal; /* bits that are fatal */ 4038 int flags; /* hints */ 4039 const struct intr_details *details; 4040 const struct intr_action *actions; 4041 }; 4042 4043 static inline char 4044 intr_alert_char(u32 cause, u32 enable, u32 fatal) 4045 { 4046 4047 if (cause & fatal) 4048 return ('!'); 4049 if (cause & enable) 4050 return ('*'); 4051 return ('-'); 4052 } 4053 4054 static void 4055 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 4056 { 4057 u32 enable, fatal, leftover; 4058 const struct intr_details *details; 4059 char alert; 4060 4061 enable = t4_read_reg(adap, ii->enable_reg); 4062 if (ii->flags & NONFATAL_IF_DISABLED) 4063 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 4064 else 4065 fatal = ii->fatal; 4066 alert = intr_alert_char(cause, enable, fatal); 4067 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 4068 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4069 4070 leftover = cause; 4071 for (details = ii->details; details && details->mask != 0; details++) { 4072 u32 msgbits = details->mask & cause; 4073 if (msgbits == 0) 4074 continue; 4075 alert = intr_alert_char(msgbits, enable, ii->fatal); 4076 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4077 details->msg); 4078 leftover &= ~msgbits; 4079 } 4080 if (leftover != 0 && leftover != cause) 4081 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4082 } 4083 4084 /* 4085 * Returns true for fatal error. 4086 */ 4087 static bool 4088 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4089 u32 additional_cause, bool verbose) 4090 { 4091 u32 cause, fatal; 4092 bool rc; 4093 const struct intr_action *action; 4094 4095 /* 4096 * Read and display cause. Note that the top level PL_INT_CAUSE is a 4097 * bit special and we need to completely ignore the bits that are not in 4098 * PL_INT_ENABLE. 4099 */ 4100 cause = t4_read_reg(adap, ii->cause_reg); 4101 if (ii->cause_reg == A_PL_INT_CAUSE) 4102 cause &= t4_read_reg(adap, ii->enable_reg); 4103 if (verbose || cause != 0) 4104 t4_show_intr_info(adap, ii, cause); 4105 fatal = cause & ii->fatal; 4106 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4107 fatal &= t4_read_reg(adap, ii->enable_reg); 4108 cause |= additional_cause; 4109 if (cause == 0) 4110 return (false); 4111 4112 rc = fatal != 0; 4113 for (action = ii->actions; action && action->mask != 0; action++) { 4114 if (!(action->mask & cause)) 4115 continue; 4116 rc |= (action->action)(adap, action->arg, verbose); 4117 } 4118 4119 /* clear */ 4120 t4_write_reg(adap, ii->cause_reg, cause); 4121 (void)t4_read_reg(adap, ii->cause_reg); 4122 4123 return (rc); 4124 } 4125 4126 /* 4127 * Interrupt handler for the PCIE module. 4128 */ 4129 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4130 { 4131 static const struct intr_details sysbus_intr_details[] = { 4132 { F_RNPP, "RXNP array parity error" }, 4133 { F_RPCP, "RXPC array parity error" }, 4134 { F_RCIP, "RXCIF array parity error" }, 4135 { F_RCCP, "Rx completions control array parity error" }, 4136 { F_RFTP, "RXFT array parity error" }, 4137 { 0 } 4138 }; 4139 static const struct intr_info sysbus_intr_info = { 4140 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4141 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4142 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4143 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4144 .flags = 0, 4145 .details = sysbus_intr_details, 4146 .actions = NULL, 4147 }; 4148 static const struct intr_details pcie_port_intr_details[] = { 4149 { F_TPCP, "TXPC array parity error" }, 4150 { F_TNPP, "TXNP array parity error" }, 4151 { F_TFTP, "TXFT array parity error" }, 4152 { F_TCAP, "TXCA array parity error" }, 4153 { F_TCIP, "TXCIF array parity error" }, 4154 { F_RCAP, "RXCA array parity error" }, 4155 { F_OTDD, "outbound request TLP discarded" }, 4156 { F_RDPE, "Rx data parity error" }, 4157 { F_TDUE, "Tx uncorrectable data error" }, 4158 { 0 } 4159 }; 4160 static const struct intr_info pcie_port_intr_info = { 4161 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4162 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4163 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4164 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4165 F_OTDD | F_RDPE | F_TDUE, 4166 .flags = 0, 4167 .details = pcie_port_intr_details, 4168 .actions = NULL, 4169 }; 4170 static const struct intr_details pcie_intr_details[] = { 4171 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4172 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4173 { F_MSIDATAPERR, "MSI data parity error" }, 4174 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4175 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4176 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4177 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4178 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4179 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4180 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4181 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4182 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4183 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4184 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4185 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4186 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4187 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4188 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4189 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4190 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4191 { F_FIDPERR, "PCIe FID parity error" }, 4192 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4193 { F_MATAGPERR, "PCIe MA tag parity error" }, 4194 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4195 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4196 { F_RXWRPERR, "PCIe Rx write parity error" }, 4197 { F_RPLPERR, "PCIe replay buffer parity error" }, 4198 { F_PCIESINT, "PCIe core secondary fault" }, 4199 { F_PCIEPINT, "PCIe core primary fault" }, 4200 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4201 { 0 } 4202 }; 4203 static const struct intr_details t5_pcie_intr_details[] = { 4204 { F_IPGRPPERR, "Parity errors observed by IP" }, 4205 { F_NONFATALERR, "PCIe non-fatal error" }, 4206 { F_READRSPERR, "Outbound read error" }, 4207 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4208 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4209 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4210 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4211 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4212 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4213 { F_MAGRPPERR, "MA group FIFO parity error" }, 4214 { F_VFIDPERR, "VFID SRAM parity error" }, 4215 { F_FIDPERR, "FID SRAM parity error" }, 4216 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4217 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4218 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4219 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4220 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4221 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4222 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4223 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4224 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4225 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4226 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4227 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4228 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4229 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4230 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4231 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4232 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4233 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4234 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4235 { 0 } 4236 }; 4237 struct intr_info pcie_intr_info = { 4238 .name = "PCIE_INT_CAUSE", 4239 .cause_reg = A_PCIE_INT_CAUSE, 4240 .enable_reg = A_PCIE_INT_ENABLE, 4241 .fatal = 0xffffffff, 4242 .flags = NONFATAL_IF_DISABLED, 4243 .details = NULL, 4244 .actions = NULL, 4245 }; 4246 bool fatal = false; 4247 4248 if (is_t4(adap)) { 4249 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4250 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4251 4252 pcie_intr_info.details = pcie_intr_details; 4253 } else { 4254 pcie_intr_info.details = t5_pcie_intr_details; 4255 } 4256 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4257 4258 return (fatal); 4259 } 4260 4261 /* 4262 * TP interrupt handler. 4263 */ 4264 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4265 { 4266 static const struct intr_details tp_intr_details[] = { 4267 { 0x3fffffff, "TP parity error" }, 4268 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4269 { 0 } 4270 }; 4271 static const struct intr_info tp_intr_info = { 4272 .name = "TP_INT_CAUSE", 4273 .cause_reg = A_TP_INT_CAUSE, 4274 .enable_reg = A_TP_INT_ENABLE, 4275 .fatal = 0x7fffffff, 4276 .flags = NONFATAL_IF_DISABLED, 4277 .details = tp_intr_details, 4278 .actions = NULL, 4279 }; 4280 4281 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4282 } 4283 4284 /* 4285 * SGE interrupt handler. 4286 */ 4287 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4288 { 4289 static const struct intr_info sge_int1_info = { 4290 .name = "SGE_INT_CAUSE1", 4291 .cause_reg = A_SGE_INT_CAUSE1, 4292 .enable_reg = A_SGE_INT_ENABLE1, 4293 .fatal = 0xffffffff, 4294 .flags = NONFATAL_IF_DISABLED, 4295 .details = NULL, 4296 .actions = NULL, 4297 }; 4298 static const struct intr_info sge_int2_info = { 4299 .name = "SGE_INT_CAUSE2", 4300 .cause_reg = A_SGE_INT_CAUSE2, 4301 .enable_reg = A_SGE_INT_ENABLE2, 4302 .fatal = 0xffffffff, 4303 .flags = NONFATAL_IF_DISABLED, 4304 .details = NULL, 4305 .actions = NULL, 4306 }; 4307 static const struct intr_details sge_int3_details[] = { 4308 { F_ERR_FLM_DBP, 4309 "DBP pointer delivery for invalid context or QID" }, 4310 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4311 "Invalid QID or header request by IDMA" }, 4312 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4313 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4314 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4315 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4316 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4317 { F_ERR_TIMER_ABOVE_MAX_QID, 4318 "SGE GTS with timer 0-5 for IQID > 1023" }, 4319 { F_ERR_CPL_EXCEED_IQE_SIZE, 4320 "SGE received CPL exceeding IQE size" }, 4321 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4322 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4323 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4324 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4325 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4326 "SGE IQID > 1023 received CPL for FL" }, 4327 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4328 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4329 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4330 { F_ERR_ING_CTXT_PRIO, 4331 "Ingress context manager priority user error" }, 4332 { F_ERR_EGR_CTXT_PRIO, 4333 "Egress context manager priority user error" }, 4334 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4335 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4336 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4337 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4338 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4339 { 0x0000000f, "SGE context access for invalid queue" }, 4340 { 0 } 4341 }; 4342 static const struct intr_details t6_sge_int3_details[] = { 4343 { F_ERR_FLM_DBP, 4344 "DBP pointer delivery for invalid context or QID" }, 4345 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4346 "Invalid QID or header request by IDMA" }, 4347 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4348 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4349 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4350 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4351 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4352 { F_ERR_TIMER_ABOVE_MAX_QID, 4353 "SGE GTS with timer 0-5 for IQID > 1023" }, 4354 { F_ERR_CPL_EXCEED_IQE_SIZE, 4355 "SGE received CPL exceeding IQE size" }, 4356 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4357 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4358 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4359 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4360 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4361 "SGE IQID > 1023 received CPL for FL" }, 4362 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4363 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4364 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4365 { F_ERR_ING_CTXT_PRIO, 4366 "Ingress context manager priority user error" }, 4367 { F_ERR_EGR_CTXT_PRIO, 4368 "Egress context manager priority user error" }, 4369 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4370 { F_FATAL_WRE_LEN, 4371 "SGE WRE packet less than advertized length" }, 4372 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4373 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4374 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4375 { 0x0000000f, "SGE context access for invalid queue" }, 4376 { 0 } 4377 }; 4378 struct intr_info sge_int3_info = { 4379 .name = "SGE_INT_CAUSE3", 4380 .cause_reg = A_SGE_INT_CAUSE3, 4381 .enable_reg = A_SGE_INT_ENABLE3, 4382 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4383 .flags = 0, 4384 .details = NULL, 4385 .actions = NULL, 4386 }; 4387 static const struct intr_info sge_int4_info = { 4388 .name = "SGE_INT_CAUSE4", 4389 .cause_reg = A_SGE_INT_CAUSE4, 4390 .enable_reg = A_SGE_INT_ENABLE4, 4391 .fatal = 0, 4392 .flags = 0, 4393 .details = NULL, 4394 .actions = NULL, 4395 }; 4396 static const struct intr_info sge_int5_info = { 4397 .name = "SGE_INT_CAUSE5", 4398 .cause_reg = A_SGE_INT_CAUSE5, 4399 .enable_reg = A_SGE_INT_ENABLE5, 4400 .fatal = 0xffffffff, 4401 .flags = NONFATAL_IF_DISABLED, 4402 .details = NULL, 4403 .actions = NULL, 4404 }; 4405 static const struct intr_info sge_int6_info = { 4406 .name = "SGE_INT_CAUSE6", 4407 .cause_reg = A_SGE_INT_CAUSE6, 4408 .enable_reg = A_SGE_INT_ENABLE6, 4409 .fatal = 0, 4410 .flags = 0, 4411 .details = NULL, 4412 .actions = NULL, 4413 }; 4414 4415 bool fatal; 4416 u32 v; 4417 4418 if (chip_id(adap) <= CHELSIO_T5) { 4419 sge_int3_info.details = sge_int3_details; 4420 } else { 4421 sge_int3_info.details = t6_sge_int3_details; 4422 } 4423 4424 fatal = false; 4425 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4426 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4427 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4428 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4429 if (chip_id(adap) >= CHELSIO_T5) 4430 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4431 if (chip_id(adap) >= CHELSIO_T6) 4432 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4433 4434 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4435 if (v & F_ERROR_QID_VALID) { 4436 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4437 if (v & F_UNCAPTURED_ERROR) 4438 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4439 t4_write_reg(adap, A_SGE_ERROR_STATS, 4440 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4441 } 4442 4443 return (fatal); 4444 } 4445 4446 /* 4447 * CIM interrupt handler. 4448 */ 4449 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4450 { 4451 static const struct intr_action cim_host_intr_actions[] = { 4452 { F_TIMER0INT, 0, t4_os_dump_cimla }, 4453 { 0 }, 4454 }; 4455 static const struct intr_details cim_host_intr_details[] = { 4456 /* T6+ */ 4457 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4458 4459 /* T5+ */ 4460 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4461 { F_PLCIM_MSTRSPDATAPARERR, 4462 "PL2CIM master response data parity error" }, 4463 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4464 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4465 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4466 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4467 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4468 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4469 4470 /* T4+ */ 4471 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4472 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4473 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4474 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4475 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4476 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4477 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4478 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4479 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4480 "CIM IBQ PCIe/SGE_HI parity error" }, 4481 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4482 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4483 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4484 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4485 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4486 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4487 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4488 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4489 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4490 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4491 { 0} 4492 }; 4493 static const struct intr_info cim_host_intr_info = { 4494 .name = "CIM_HOST_INT_CAUSE", 4495 .cause_reg = A_CIM_HOST_INT_CAUSE, 4496 .enable_reg = A_CIM_HOST_INT_ENABLE, 4497 .fatal = 0x007fffe6, 4498 .flags = NONFATAL_IF_DISABLED, 4499 .details = cim_host_intr_details, 4500 .actions = cim_host_intr_actions, 4501 }; 4502 static const struct intr_details cim_host_upacc_intr_details[] = { 4503 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4504 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4505 { F_TIMEOUTINT, "CIM PIF timeout" }, 4506 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4507 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4508 { F_BLKWRPLINT, "CIM block write to PL space" }, 4509 { F_BLKRDPLINT, "CIM block read from PL space" }, 4510 { F_SGLWRPLINT, 4511 "CIM single write to PL space with illegal BEs" }, 4512 { F_SGLRDPLINT, 4513 "CIM single read from PL space with illegal BEs" }, 4514 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4515 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4516 { F_SGLWRCTLINT, 4517 "CIM single write to CTL space with illegal BEs" }, 4518 { F_SGLRDCTLINT, 4519 "CIM single read from CTL space with illegal BEs" }, 4520 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4521 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4522 { F_SGLWREEPROMINT, 4523 "CIM single write to EEPROM space with illegal BEs" }, 4524 { F_SGLRDEEPROMINT, 4525 "CIM single read from EEPROM space with illegal BEs" }, 4526 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4527 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4528 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4529 { F_SGLRDFLASHINT, 4530 "CIM single read from flash space with illegal BEs" }, 4531 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4532 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4533 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4534 { F_SGLRDBOOTINT, 4535 "CIM single read from boot space with illegal BEs" }, 4536 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4537 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4538 { F_ILLRDINT, "CIM illegal read" }, 4539 { F_ILLWRINT, "CIM illegal write" }, 4540 { F_ILLTRANSINT, "CIM illegal transaction" }, 4541 { F_RSVDSPACEINT, "CIM reserved space access" }, 4542 {0} 4543 }; 4544 static const struct intr_info cim_host_upacc_intr_info = { 4545 .name = "CIM_HOST_UPACC_INT_CAUSE", 4546 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4547 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4548 .fatal = 0x3fffeeff, 4549 .flags = NONFATAL_IF_DISABLED, 4550 .details = cim_host_upacc_intr_details, 4551 .actions = NULL, 4552 }; 4553 static const struct intr_info cim_pf_host_intr_info = { 4554 .name = "CIM_PF_HOST_INT_CAUSE", 4555 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4556 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4557 .fatal = 0, 4558 .flags = 0, 4559 .details = NULL, 4560 .actions = NULL, 4561 }; 4562 u32 val, fw_err; 4563 bool fatal; 4564 4565 fw_err = t4_read_reg(adap, A_PCIE_FW); 4566 if (fw_err & F_PCIE_FW_ERR) 4567 t4_report_fw_error(adap); 4568 4569 /* 4570 * When the Firmware detects an internal error which normally wouldn't 4571 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4572 * to make sure the Host sees the Firmware Crash. So if we have a 4573 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4574 * interrupt. 4575 */ 4576 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4577 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4578 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4579 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4580 } 4581 4582 fatal = false; 4583 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4584 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4585 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4586 4587 return (fatal); 4588 } 4589 4590 /* 4591 * ULP RX interrupt handler. 4592 */ 4593 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4594 { 4595 static const struct intr_details ulprx_intr_details[] = { 4596 /* T5+ */ 4597 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4598 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4599 4600 /* T4+ */ 4601 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4602 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4603 { 0x007fffff, "ULPRX parity error" }, 4604 { 0 } 4605 }; 4606 static const struct intr_info ulprx_intr_info = { 4607 .name = "ULP_RX_INT_CAUSE", 4608 .cause_reg = A_ULP_RX_INT_CAUSE, 4609 .enable_reg = A_ULP_RX_INT_ENABLE, 4610 .fatal = 0x07ffffff, 4611 .flags = NONFATAL_IF_DISABLED, 4612 .details = ulprx_intr_details, 4613 .actions = NULL, 4614 }; 4615 static const struct intr_info ulprx_intr2_info = { 4616 .name = "ULP_RX_INT_CAUSE_2", 4617 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4618 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4619 .fatal = 0, 4620 .flags = 0, 4621 .details = NULL, 4622 .actions = NULL, 4623 }; 4624 bool fatal = false; 4625 4626 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4627 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4628 4629 return (fatal); 4630 } 4631 4632 /* 4633 * ULP TX interrupt handler. 4634 */ 4635 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4636 { 4637 static const struct intr_details ulptx_intr_details[] = { 4638 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4639 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4640 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4641 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4642 { 0x0fffffff, "ULPTX parity error" }, 4643 { 0 } 4644 }; 4645 static const struct intr_info ulptx_intr_info = { 4646 .name = "ULP_TX_INT_CAUSE", 4647 .cause_reg = A_ULP_TX_INT_CAUSE, 4648 .enable_reg = A_ULP_TX_INT_ENABLE, 4649 .fatal = 0x0fffffff, 4650 .flags = NONFATAL_IF_DISABLED, 4651 .details = ulptx_intr_details, 4652 .actions = NULL, 4653 }; 4654 static const struct intr_info ulptx_intr2_info = { 4655 .name = "ULP_TX_INT_CAUSE_2", 4656 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4657 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4658 .fatal = 0xf0, 4659 .flags = NONFATAL_IF_DISABLED, 4660 .details = NULL, 4661 .actions = NULL, 4662 }; 4663 bool fatal = false; 4664 4665 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4666 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4667 4668 return (fatal); 4669 } 4670 4671 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4672 { 4673 int i; 4674 u32 data[17]; 4675 4676 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4677 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4678 for (i = 0; i < ARRAY_SIZE(data); i++) { 4679 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4680 A_PM_TX_DBG_STAT0 + i, data[i]); 4681 } 4682 4683 return (false); 4684 } 4685 4686 /* 4687 * PM TX interrupt handler. 4688 */ 4689 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4690 { 4691 static const struct intr_action pmtx_intr_actions[] = { 4692 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4693 { 0 }, 4694 }; 4695 static const struct intr_details pmtx_intr_details[] = { 4696 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4697 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4698 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4699 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4700 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4701 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4702 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4703 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4704 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4705 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4706 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4707 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4708 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4709 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4710 { 0 } 4711 }; 4712 static const struct intr_info pmtx_intr_info = { 4713 .name = "PM_TX_INT_CAUSE", 4714 .cause_reg = A_PM_TX_INT_CAUSE, 4715 .enable_reg = A_PM_TX_INT_ENABLE, 4716 .fatal = 0xffffffff, 4717 .flags = 0, 4718 .details = pmtx_intr_details, 4719 .actions = pmtx_intr_actions, 4720 }; 4721 4722 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4723 } 4724 4725 /* 4726 * PM RX interrupt handler. 4727 */ 4728 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4729 { 4730 static const struct intr_details pmrx_intr_details[] = { 4731 /* T6+ */ 4732 { 0x18000000, "PMRX ospi overflow" }, 4733 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4734 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4735 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4736 { F_SDC_ERR, "PMRX SDC error" }, 4737 4738 /* T4+ */ 4739 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4740 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4741 { 0x0003c000, "PMRX iespi Rx framing error" }, 4742 { 0x00003c00, "PMRX iespi Tx framing error" }, 4743 { 0x00000300, "PMRX ocspi Rx framing error" }, 4744 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4745 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4746 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4747 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4748 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4749 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4750 { 0 } 4751 }; 4752 static const struct intr_info pmrx_intr_info = { 4753 .name = "PM_RX_INT_CAUSE", 4754 .cause_reg = A_PM_RX_INT_CAUSE, 4755 .enable_reg = A_PM_RX_INT_ENABLE, 4756 .fatal = 0x1fffffff, 4757 .flags = NONFATAL_IF_DISABLED, 4758 .details = pmrx_intr_details, 4759 .actions = NULL, 4760 }; 4761 4762 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4763 } 4764 4765 /* 4766 * CPL switch interrupt handler. 4767 */ 4768 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4769 { 4770 static const struct intr_details cplsw_intr_details[] = { 4771 /* T5+ */ 4772 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4773 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4774 4775 /* T4+ */ 4776 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4777 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4778 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4779 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4780 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4781 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4782 { 0 } 4783 }; 4784 static const struct intr_info cplsw_intr_info = { 4785 .name = "CPL_INTR_CAUSE", 4786 .cause_reg = A_CPL_INTR_CAUSE, 4787 .enable_reg = A_CPL_INTR_ENABLE, 4788 .fatal = 0xff, 4789 .flags = NONFATAL_IF_DISABLED, 4790 .details = cplsw_intr_details, 4791 .actions = NULL, 4792 }; 4793 4794 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4795 } 4796 4797 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4798 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4799 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4800 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4801 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4802 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4803 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4804 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4805 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4806 4807 /* 4808 * LE interrupt handler. 4809 */ 4810 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4811 { 4812 static const struct intr_details le_intr_details[] = { 4813 { F_REQQPARERR, "LE request queue parity error" }, 4814 { F_UNKNOWNCMD, "LE unknown command" }, 4815 { F_ACTRGNFULL, "LE active region full" }, 4816 { F_PARITYERR, "LE parity error" }, 4817 { F_LIPMISS, "LE LIP miss" }, 4818 { F_LIP0, "LE 0 LIP error" }, 4819 { 0 } 4820 }; 4821 static const struct intr_details t6_le_intr_details[] = { 4822 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4823 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4824 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4825 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4826 { F_TOTCNTERR, "LE total active < TCAM count" }, 4827 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4828 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4829 { F_T6_ACTRGNFULL, "LE active region full" }, 4830 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4831 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4832 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4833 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4834 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4835 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4836 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4837 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4838 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4839 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4840 { 0 } 4841 }; 4842 struct intr_info le_intr_info = { 4843 .name = "LE_DB_INT_CAUSE", 4844 .cause_reg = A_LE_DB_INT_CAUSE, 4845 .enable_reg = A_LE_DB_INT_ENABLE, 4846 .fatal = 0, 4847 .flags = NONFATAL_IF_DISABLED, 4848 .details = NULL, 4849 .actions = NULL, 4850 }; 4851 4852 if (chip_id(adap) <= CHELSIO_T5) { 4853 le_intr_info.details = le_intr_details; 4854 le_intr_info.fatal = T5_LE_FATAL_MASK; 4855 } else { 4856 le_intr_info.details = t6_le_intr_details; 4857 le_intr_info.fatal = T6_LE_FATAL_MASK; 4858 } 4859 4860 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4861 } 4862 4863 /* 4864 * MPS interrupt handler. 4865 */ 4866 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4867 { 4868 static const struct intr_details mps_rx_perr_intr_details[] = { 4869 { 0xffffffff, "MPS Rx parity error" }, 4870 { 0 } 4871 }; 4872 static const struct intr_info mps_rx_perr_intr_info = { 4873 .name = "MPS_RX_PERR_INT_CAUSE", 4874 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4875 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4876 .fatal = 0xffffffff, 4877 .flags = NONFATAL_IF_DISABLED, 4878 .details = mps_rx_perr_intr_details, 4879 .actions = NULL, 4880 }; 4881 static const struct intr_details mps_tx_intr_details[] = { 4882 { F_PORTERR, "MPS Tx destination port is disabled" }, 4883 { F_FRMERR, "MPS Tx framing error" }, 4884 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4885 { F_BUBBLE, "MPS Tx underflow" }, 4886 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4887 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4888 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4889 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4890 { 0 } 4891 }; 4892 static const struct intr_info mps_tx_intr_info = { 4893 .name = "MPS_TX_INT_CAUSE", 4894 .cause_reg = A_MPS_TX_INT_CAUSE, 4895 .enable_reg = A_MPS_TX_INT_ENABLE, 4896 .fatal = 0x1ffff, 4897 .flags = NONFATAL_IF_DISABLED, 4898 .details = mps_tx_intr_details, 4899 .actions = NULL, 4900 }; 4901 static const struct intr_details mps_trc_intr_details[] = { 4902 { F_MISCPERR, "MPS TRC misc parity error" }, 4903 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4904 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4905 { 0 } 4906 }; 4907 static const struct intr_info mps_trc_intr_info = { 4908 .name = "MPS_TRC_INT_CAUSE", 4909 .cause_reg = A_MPS_TRC_INT_CAUSE, 4910 .enable_reg = A_MPS_TRC_INT_ENABLE, 4911 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4912 .flags = 0, 4913 .details = mps_trc_intr_details, 4914 .actions = NULL, 4915 }; 4916 static const struct intr_details mps_stat_sram_intr_details[] = { 4917 { 0xffffffff, "MPS statistics SRAM parity error" }, 4918 { 0 } 4919 }; 4920 static const struct intr_info mps_stat_sram_intr_info = { 4921 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4922 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4923 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4924 .fatal = 0x1fffffff, 4925 .flags = NONFATAL_IF_DISABLED, 4926 .details = mps_stat_sram_intr_details, 4927 .actions = NULL, 4928 }; 4929 static const struct intr_details mps_stat_tx_intr_details[] = { 4930 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4931 { 0 } 4932 }; 4933 static const struct intr_info mps_stat_tx_intr_info = { 4934 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4935 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4936 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4937 .fatal = 0xffffff, 4938 .flags = NONFATAL_IF_DISABLED, 4939 .details = mps_stat_tx_intr_details, 4940 .actions = NULL, 4941 }; 4942 static const struct intr_details mps_stat_rx_intr_details[] = { 4943 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4944 { 0 } 4945 }; 4946 static const struct intr_info mps_stat_rx_intr_info = { 4947 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4948 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4949 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4950 .fatal = 0xffffff, 4951 .flags = 0, 4952 .details = mps_stat_rx_intr_details, 4953 .actions = NULL, 4954 }; 4955 static const struct intr_details mps_cls_intr_details[] = { 4956 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4957 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4958 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4959 { 0 } 4960 }; 4961 static const struct intr_info mps_cls_intr_info = { 4962 .name = "MPS_CLS_INT_CAUSE", 4963 .cause_reg = A_MPS_CLS_INT_CAUSE, 4964 .enable_reg = A_MPS_CLS_INT_ENABLE, 4965 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4966 .flags = 0, 4967 .details = mps_cls_intr_details, 4968 .actions = NULL, 4969 }; 4970 static const struct intr_details mps_stat_sram1_intr_details[] = { 4971 { 0xff, "MPS statistics SRAM1 parity error" }, 4972 { 0 } 4973 }; 4974 static const struct intr_info mps_stat_sram1_intr_info = { 4975 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4976 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4977 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4978 .fatal = 0xff, 4979 .flags = 0, 4980 .details = mps_stat_sram1_intr_details, 4981 .actions = NULL, 4982 }; 4983 4984 bool fatal; 4985 4986 fatal = false; 4987 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 4988 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 4989 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 4990 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 4991 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 4992 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 4993 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 4994 if (chip_id(adap) > CHELSIO_T4) { 4995 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 4996 verbose); 4997 } 4998 4999 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5000 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 5001 5002 return (fatal); 5003 5004 } 5005 5006 /* 5007 * EDC/MC interrupt handler. 5008 */ 5009 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 5010 { 5011 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 5012 unsigned int count_reg, v; 5013 static const struct intr_details mem_intr_details[] = { 5014 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 5015 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 5016 { F_PERR_INT_CAUSE, "FIFO parity error" }, 5017 { 0 } 5018 }; 5019 struct intr_info ii = { 5020 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 5021 .details = mem_intr_details, 5022 .flags = 0, 5023 .actions = NULL, 5024 }; 5025 bool fatal; 5026 5027 switch (idx) { 5028 case MEM_EDC0: 5029 ii.name = "EDC0_INT_CAUSE"; 5030 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 5031 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 5032 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 5033 break; 5034 case MEM_EDC1: 5035 ii.name = "EDC1_INT_CAUSE"; 5036 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 5037 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 5038 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 5039 break; 5040 case MEM_MC0: 5041 ii.name = "MC0_INT_CAUSE"; 5042 if (is_t4(adap)) { 5043 ii.cause_reg = A_MC_INT_CAUSE; 5044 ii.enable_reg = A_MC_INT_ENABLE; 5045 count_reg = A_MC_ECC_STATUS; 5046 } else { 5047 ii.cause_reg = A_MC_P_INT_CAUSE; 5048 ii.enable_reg = A_MC_P_INT_ENABLE; 5049 count_reg = A_MC_P_ECC_STATUS; 5050 } 5051 break; 5052 case MEM_MC1: 5053 ii.name = "MC1_INT_CAUSE"; 5054 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 5055 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 5056 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 5057 break; 5058 } 5059 5060 fatal = t4_handle_intr(adap, &ii, 0, verbose); 5061 5062 v = t4_read_reg(adap, count_reg); 5063 if (v != 0) { 5064 if (G_ECC_UECNT(v) != 0) { 5065 CH_ALERT(adap, 5066 "%s: %u uncorrectable ECC data error(s)\n", 5067 name[idx], G_ECC_UECNT(v)); 5068 } 5069 if (G_ECC_CECNT(v) != 0) { 5070 if (idx <= MEM_EDC1) 5071 t4_edc_err_read(adap, idx); 5072 CH_WARN_RATELIMIT(adap, 5073 "%s: %u correctable ECC data error(s)\n", 5074 name[idx], G_ECC_CECNT(v)); 5075 } 5076 t4_write_reg(adap, count_reg, 0xffffffff); 5077 } 5078 5079 return (fatal); 5080 } 5081 5082 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5083 { 5084 u32 v; 5085 5086 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5087 CH_ALERT(adap, 5088 "MA address wrap-around error by client %u to address %#x\n", 5089 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5090 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5091 5092 return (false); 5093 } 5094 5095 5096 /* 5097 * MA interrupt handler. 5098 */ 5099 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5100 { 5101 static const struct intr_action ma_intr_actions[] = { 5102 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5103 { 0 }, 5104 }; 5105 static const struct intr_info ma_intr_info = { 5106 .name = "MA_INT_CAUSE", 5107 .cause_reg = A_MA_INT_CAUSE, 5108 .enable_reg = A_MA_INT_ENABLE, 5109 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5110 .flags = NONFATAL_IF_DISABLED, 5111 .details = NULL, 5112 .actions = ma_intr_actions, 5113 }; 5114 static const struct intr_info ma_perr_status1 = { 5115 .name = "MA_PARITY_ERROR_STATUS1", 5116 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5117 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5118 .fatal = 0xffffffff, 5119 .flags = 0, 5120 .details = NULL, 5121 .actions = NULL, 5122 }; 5123 static const struct intr_info ma_perr_status2 = { 5124 .name = "MA_PARITY_ERROR_STATUS2", 5125 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5126 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5127 .fatal = 0xffffffff, 5128 .flags = 0, 5129 .details = NULL, 5130 .actions = NULL, 5131 }; 5132 bool fatal; 5133 5134 fatal = false; 5135 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5136 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5137 if (chip_id(adap) > CHELSIO_T4) 5138 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5139 5140 return (fatal); 5141 } 5142 5143 /* 5144 * SMB interrupt handler. 5145 */ 5146 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5147 { 5148 static const struct intr_details smb_intr_details[] = { 5149 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5150 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5151 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5152 { 0 } 5153 }; 5154 static const struct intr_info smb_intr_info = { 5155 .name = "SMB_INT_CAUSE", 5156 .cause_reg = A_SMB_INT_CAUSE, 5157 .enable_reg = A_SMB_INT_ENABLE, 5158 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5159 .flags = 0, 5160 .details = smb_intr_details, 5161 .actions = NULL, 5162 }; 5163 5164 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5165 } 5166 5167 /* 5168 * NC-SI interrupt handler. 5169 */ 5170 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5171 { 5172 static const struct intr_details ncsi_intr_details[] = { 5173 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5174 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5175 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5176 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5177 { 0 } 5178 }; 5179 static const struct intr_info ncsi_intr_info = { 5180 .name = "NCSI_INT_CAUSE", 5181 .cause_reg = A_NCSI_INT_CAUSE, 5182 .enable_reg = A_NCSI_INT_ENABLE, 5183 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5184 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5185 .flags = 0, 5186 .details = ncsi_intr_details, 5187 .actions = NULL, 5188 }; 5189 5190 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5191 } 5192 5193 /* 5194 * MAC interrupt handler. 5195 */ 5196 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5197 { 5198 static const struct intr_details mac_intr_details[] = { 5199 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5200 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5201 { 0 } 5202 }; 5203 char name[32]; 5204 struct intr_info ii; 5205 bool fatal = false; 5206 5207 if (is_t4(adap)) { 5208 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5209 ii.name = &name[0]; 5210 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5211 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5212 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5213 ii.flags = 0; 5214 ii.details = mac_intr_details; 5215 ii.actions = NULL; 5216 } else { 5217 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5218 ii.name = &name[0]; 5219 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5220 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5221 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5222 ii.flags = 0; 5223 ii.details = mac_intr_details; 5224 ii.actions = NULL; 5225 } 5226 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5227 5228 if (chip_id(adap) >= CHELSIO_T5) { 5229 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5230 ii.name = &name[0]; 5231 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5232 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5233 ii.fatal = 0; 5234 ii.flags = 0; 5235 ii.details = NULL; 5236 ii.actions = NULL; 5237 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5238 } 5239 5240 if (chip_id(adap) >= CHELSIO_T6) { 5241 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5242 ii.name = &name[0]; 5243 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5244 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5245 ii.fatal = 0; 5246 ii.flags = 0; 5247 ii.details = NULL; 5248 ii.actions = NULL; 5249 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5250 } 5251 5252 return (fatal); 5253 } 5254 5255 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5256 { 5257 static const struct intr_details plpl_intr_details[] = { 5258 { F_FATALPERR, "Fatal parity error" }, 5259 { F_PERRVFID, "VFID_MAP parity error" }, 5260 { 0 } 5261 }; 5262 static const struct intr_info plpl_intr_info = { 5263 .name = "PL_PL_INT_CAUSE", 5264 .cause_reg = A_PL_PL_INT_CAUSE, 5265 .enable_reg = A_PL_PL_INT_ENABLE, 5266 .fatal = F_FATALPERR | F_PERRVFID, 5267 .flags = NONFATAL_IF_DISABLED, 5268 .details = plpl_intr_details, 5269 .actions = NULL, 5270 }; 5271 5272 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5273 } 5274 5275 /** 5276 * t4_slow_intr_handler - control path interrupt handler 5277 * @adap: the adapter 5278 * @verbose: increased verbosity, for debug 5279 * 5280 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5281 * The designation 'slow' is because it involves register reads, while 5282 * data interrupts typically don't involve any MMIOs. 5283 */ 5284 int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5285 { 5286 static const struct intr_details pl_intr_details[] = { 5287 { F_MC1, "MC1" }, 5288 { F_UART, "UART" }, 5289 { F_ULP_TX, "ULP TX" }, 5290 { F_SGE, "SGE" }, 5291 { F_HMA, "HMA" }, 5292 { F_CPL_SWITCH, "CPL Switch" }, 5293 { F_ULP_RX, "ULP RX" }, 5294 { F_PM_RX, "PM RX" }, 5295 { F_PM_TX, "PM TX" }, 5296 { F_MA, "MA" }, 5297 { F_TP, "TP" }, 5298 { F_LE, "LE" }, 5299 { F_EDC1, "EDC1" }, 5300 { F_EDC0, "EDC0" }, 5301 { F_MC, "MC0" }, 5302 { F_PCIE, "PCIE" }, 5303 { F_PMU, "PMU" }, 5304 { F_MAC3, "MAC3" }, 5305 { F_MAC2, "MAC2" }, 5306 { F_MAC1, "MAC1" }, 5307 { F_MAC0, "MAC0" }, 5308 { F_SMB, "SMB" }, 5309 { F_SF, "SF" }, 5310 { F_PL, "PL" }, 5311 { F_NCSI, "NC-SI" }, 5312 { F_MPS, "MPS" }, 5313 { F_MI, "MI" }, 5314 { F_DBG, "DBG" }, 5315 { F_I2CM, "I2CM" }, 5316 { F_CIM, "CIM" }, 5317 { 0 } 5318 }; 5319 static const struct intr_info pl_perr_cause = { 5320 .name = "PL_PERR_CAUSE", 5321 .cause_reg = A_PL_PERR_CAUSE, 5322 .enable_reg = A_PL_PERR_ENABLE, 5323 .fatal = 0xffffffff, 5324 .flags = 0, 5325 .details = pl_intr_details, 5326 .actions = NULL, 5327 }; 5328 static const struct intr_action pl_intr_action[] = { 5329 { F_MC1, MEM_MC1, mem_intr_handler }, 5330 { F_ULP_TX, -1, ulptx_intr_handler }, 5331 { F_SGE, -1, sge_intr_handler }, 5332 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5333 { F_ULP_RX, -1, ulprx_intr_handler }, 5334 { F_PM_RX, -1, pmrx_intr_handler}, 5335 { F_PM_TX, -1, pmtx_intr_handler}, 5336 { F_MA, -1, ma_intr_handler }, 5337 { F_TP, -1, tp_intr_handler }, 5338 { F_LE, -1, le_intr_handler }, 5339 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5340 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5341 { F_MC0, MEM_MC0, mem_intr_handler }, 5342 { F_PCIE, -1, pcie_intr_handler }, 5343 { F_MAC3, 3, mac_intr_handler}, 5344 { F_MAC2, 2, mac_intr_handler}, 5345 { F_MAC1, 1, mac_intr_handler}, 5346 { F_MAC0, 0, mac_intr_handler}, 5347 { F_SMB, -1, smb_intr_handler}, 5348 { F_PL, -1, plpl_intr_handler }, 5349 { F_NCSI, -1, ncsi_intr_handler}, 5350 { F_MPS, -1, mps_intr_handler }, 5351 { F_CIM, -1, cim_intr_handler }, 5352 { 0 } 5353 }; 5354 static const struct intr_info pl_intr_info = { 5355 .name = "PL_INT_CAUSE", 5356 .cause_reg = A_PL_INT_CAUSE, 5357 .enable_reg = A_PL_INT_ENABLE, 5358 .fatal = 0, 5359 .flags = 0, 5360 .details = pl_intr_details, 5361 .actions = pl_intr_action, 5362 }; 5363 bool fatal; 5364 u32 perr; 5365 5366 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5367 if (verbose || perr != 0) { 5368 t4_show_intr_info(adap, &pl_perr_cause, perr); 5369 if (perr != 0) 5370 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5371 if (verbose) 5372 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5373 } 5374 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5375 if (fatal) 5376 t4_fatal_err(adap, false); 5377 5378 return (0); 5379 } 5380 5381 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5382 5383 /** 5384 * t4_intr_enable - enable interrupts 5385 * @adapter: the adapter whose interrupts should be enabled 5386 * 5387 * Enable PF-specific interrupts for the calling function and the top-level 5388 * interrupt concentrator for global interrupts. Interrupts are already 5389 * enabled at each module, here we just enable the roots of the interrupt 5390 * hierarchies. 5391 * 5392 * Note: this function should be called only when the driver manages 5393 * non PF-specific interrupts from the various HW modules. Only one PCI 5394 * function at a time should be doing this. 5395 */ 5396 void t4_intr_enable(struct adapter *adap) 5397 { 5398 u32 val = 0; 5399 5400 if (chip_id(adap) <= CHELSIO_T5) 5401 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5402 else 5403 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5404 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5405 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5406 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5407 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5408 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5409 F_EGRESS_SIZE_ERR; 5410 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5411 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5412 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5413 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5414 } 5415 5416 /** 5417 * t4_intr_disable - disable interrupts 5418 * @adap: the adapter whose interrupts should be disabled 5419 * 5420 * Disable interrupts. We only disable the top-level interrupt 5421 * concentrators. The caller must be a PCI function managing global 5422 * interrupts. 5423 */ 5424 void t4_intr_disable(struct adapter *adap) 5425 { 5426 5427 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5428 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5429 } 5430 5431 /** 5432 * t4_intr_clear - clear all interrupts 5433 * @adap: the adapter whose interrupts should be cleared 5434 * 5435 * Clears all interrupts. The caller must be a PCI function managing 5436 * global interrupts. 5437 */ 5438 void t4_intr_clear(struct adapter *adap) 5439 { 5440 static const u32 cause_reg[] = { 5441 A_CIM_HOST_INT_CAUSE, 5442 A_CIM_HOST_UPACC_INT_CAUSE, 5443 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5444 A_CPL_INTR_CAUSE, 5445 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5446 A_LE_DB_INT_CAUSE, 5447 A_MA_INT_WRAP_STATUS, 5448 A_MA_PARITY_ERROR_STATUS1, 5449 A_MA_INT_CAUSE, 5450 A_MPS_CLS_INT_CAUSE, 5451 A_MPS_RX_PERR_INT_CAUSE, 5452 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5453 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5454 A_MPS_TRC_INT_CAUSE, 5455 A_MPS_TX_INT_CAUSE, 5456 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5457 A_NCSI_INT_CAUSE, 5458 A_PCIE_INT_CAUSE, 5459 A_PCIE_NONFAT_ERR, 5460 A_PL_PL_INT_CAUSE, 5461 A_PM_RX_INT_CAUSE, 5462 A_PM_TX_INT_CAUSE, 5463 A_SGE_INT_CAUSE1, 5464 A_SGE_INT_CAUSE2, 5465 A_SGE_INT_CAUSE3, 5466 A_SGE_INT_CAUSE4, 5467 A_SMB_INT_CAUSE, 5468 A_TP_INT_CAUSE, 5469 A_ULP_RX_INT_CAUSE, 5470 A_ULP_RX_INT_CAUSE_2, 5471 A_ULP_TX_INT_CAUSE, 5472 A_ULP_TX_INT_CAUSE_2, 5473 5474 MYPF_REG(A_PL_PF_INT_CAUSE), 5475 }; 5476 int i; 5477 const int nchan = adap->chip_params->nchan; 5478 5479 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5480 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5481 5482 if (is_t4(adap)) { 5483 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5484 0xffffffff); 5485 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5486 0xffffffff); 5487 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5488 for (i = 0; i < nchan; i++) { 5489 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5490 0xffffffff); 5491 } 5492 } 5493 if (chip_id(adap) >= CHELSIO_T5) { 5494 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5495 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5496 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5497 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5498 if (is_t5(adap)) { 5499 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5500 0xffffffff); 5501 } 5502 for (i = 0; i < nchan; i++) { 5503 t4_write_reg(adap, T5_PORT_REG(i, 5504 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5505 if (chip_id(adap) > CHELSIO_T5) { 5506 t4_write_reg(adap, T5_PORT_REG(i, 5507 A_MAC_PORT_PERR_INT_CAUSE_100G), 5508 0xffffffff); 5509 } 5510 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5511 0xffffffff); 5512 } 5513 } 5514 if (chip_id(adap) >= CHELSIO_T6) { 5515 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5516 } 5517 5518 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5519 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5520 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5521 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5522 } 5523 5524 /** 5525 * hash_mac_addr - return the hash value of a MAC address 5526 * @addr: the 48-bit Ethernet MAC address 5527 * 5528 * Hashes a MAC address according to the hash function used by HW inexact 5529 * (hash) address matching. 5530 */ 5531 static int hash_mac_addr(const u8 *addr) 5532 { 5533 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5534 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5535 a ^= b; 5536 a ^= (a >> 12); 5537 a ^= (a >> 6); 5538 return a & 0x3f; 5539 } 5540 5541 /** 5542 * t4_config_rss_range - configure a portion of the RSS mapping table 5543 * @adapter: the adapter 5544 * @mbox: mbox to use for the FW command 5545 * @viid: virtual interface whose RSS subtable is to be written 5546 * @start: start entry in the table to write 5547 * @n: how many table entries to write 5548 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5549 * @nrspq: number of values in @rspq 5550 * 5551 * Programs the selected part of the VI's RSS mapping table with the 5552 * provided values. If @nrspq < @n the supplied values are used repeatedly 5553 * until the full table range is populated. 5554 * 5555 * The caller must ensure the values in @rspq are in the range allowed for 5556 * @viid. 5557 */ 5558 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5559 int start, int n, const u16 *rspq, unsigned int nrspq) 5560 { 5561 int ret; 5562 const u16 *rsp = rspq; 5563 const u16 *rsp_end = rspq + nrspq; 5564 struct fw_rss_ind_tbl_cmd cmd; 5565 5566 memset(&cmd, 0, sizeof(cmd)); 5567 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5568 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5569 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5570 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5571 5572 /* 5573 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5574 * Queue Identifiers. These Ingress Queue IDs are packed three to 5575 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5576 * reserved. 5577 */ 5578 while (n > 0) { 5579 int nq = min(n, 32); 5580 int nq_packed = 0; 5581 __be32 *qp = &cmd.iq0_to_iq2; 5582 5583 /* 5584 * Set up the firmware RSS command header to send the next 5585 * "nq" Ingress Queue IDs to the firmware. 5586 */ 5587 cmd.niqid = cpu_to_be16(nq); 5588 cmd.startidx = cpu_to_be16(start); 5589 5590 /* 5591 * "nq" more done for the start of the next loop. 5592 */ 5593 start += nq; 5594 n -= nq; 5595 5596 /* 5597 * While there are still Ingress Queue IDs to stuff into the 5598 * current firmware RSS command, retrieve them from the 5599 * Ingress Queue ID array and insert them into the command. 5600 */ 5601 while (nq > 0) { 5602 /* 5603 * Grab up to the next 3 Ingress Queue IDs (wrapping 5604 * around the Ingress Queue ID array if necessary) and 5605 * insert them into the firmware RSS command at the 5606 * current 3-tuple position within the commad. 5607 */ 5608 u16 qbuf[3]; 5609 u16 *qbp = qbuf; 5610 int nqbuf = min(3, nq); 5611 5612 nq -= nqbuf; 5613 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5614 while (nqbuf && nq_packed < 32) { 5615 nqbuf--; 5616 nq_packed++; 5617 *qbp++ = *rsp++; 5618 if (rsp >= rsp_end) 5619 rsp = rspq; 5620 } 5621 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5622 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5623 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5624 } 5625 5626 /* 5627 * Send this portion of the RRS table update to the firmware; 5628 * bail out on any errors. 5629 */ 5630 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5631 if (ret) 5632 return ret; 5633 } 5634 return 0; 5635 } 5636 5637 /** 5638 * t4_config_glbl_rss - configure the global RSS mode 5639 * @adapter: the adapter 5640 * @mbox: mbox to use for the FW command 5641 * @mode: global RSS mode 5642 * @flags: mode-specific flags 5643 * 5644 * Sets the global RSS mode. 5645 */ 5646 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5647 unsigned int flags) 5648 { 5649 struct fw_rss_glb_config_cmd c; 5650 5651 memset(&c, 0, sizeof(c)); 5652 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5653 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5654 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5655 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5656 c.u.manual.mode_pkd = 5657 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5658 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5659 c.u.basicvirtual.mode_keymode = 5660 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5661 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5662 } else 5663 return -EINVAL; 5664 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5665 } 5666 5667 /** 5668 * t4_config_vi_rss - configure per VI RSS settings 5669 * @adapter: the adapter 5670 * @mbox: mbox to use for the FW command 5671 * @viid: the VI id 5672 * @flags: RSS flags 5673 * @defq: id of the default RSS queue for the VI. 5674 * @skeyidx: RSS secret key table index for non-global mode 5675 * @skey: RSS vf_scramble key for VI. 5676 * 5677 * Configures VI-specific RSS properties. 5678 */ 5679 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5680 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5681 unsigned int skey) 5682 { 5683 struct fw_rss_vi_config_cmd c; 5684 5685 memset(&c, 0, sizeof(c)); 5686 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5687 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5688 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5689 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5690 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5691 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5692 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5693 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5694 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5695 5696 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5697 } 5698 5699 /* Read an RSS table row */ 5700 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5701 { 5702 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5703 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5704 5, 0, val); 5705 } 5706 5707 /** 5708 * t4_read_rss - read the contents of the RSS mapping table 5709 * @adapter: the adapter 5710 * @map: holds the contents of the RSS mapping table 5711 * 5712 * Reads the contents of the RSS hash->queue mapping table. 5713 */ 5714 int t4_read_rss(struct adapter *adapter, u16 *map) 5715 { 5716 u32 val; 5717 int i, ret; 5718 int rss_nentries = adapter->chip_params->rss_nentries; 5719 5720 for (i = 0; i < rss_nentries / 2; ++i) { 5721 ret = rd_rss_row(adapter, i, &val); 5722 if (ret) 5723 return ret; 5724 *map++ = G_LKPTBLQUEUE0(val); 5725 *map++ = G_LKPTBLQUEUE1(val); 5726 } 5727 return 0; 5728 } 5729 5730 /** 5731 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5732 * @adap: the adapter 5733 * @cmd: TP fw ldst address space type 5734 * @vals: where the indirect register values are stored/written 5735 * @nregs: how many indirect registers to read/write 5736 * @start_idx: index of first indirect register to read/write 5737 * @rw: Read (1) or Write (0) 5738 * @sleep_ok: if true we may sleep while awaiting command completion 5739 * 5740 * Access TP indirect registers through LDST 5741 **/ 5742 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5743 unsigned int nregs, unsigned int start_index, 5744 unsigned int rw, bool sleep_ok) 5745 { 5746 int ret = 0; 5747 unsigned int i; 5748 struct fw_ldst_cmd c; 5749 5750 for (i = 0; i < nregs; i++) { 5751 memset(&c, 0, sizeof(c)); 5752 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5753 F_FW_CMD_REQUEST | 5754 (rw ? F_FW_CMD_READ : 5755 F_FW_CMD_WRITE) | 5756 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5757 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5758 5759 c.u.addrval.addr = cpu_to_be32(start_index + i); 5760 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5761 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5762 sleep_ok); 5763 if (ret) 5764 return ret; 5765 5766 if (rw) 5767 vals[i] = be32_to_cpu(c.u.addrval.val); 5768 } 5769 return 0; 5770 } 5771 5772 /** 5773 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5774 * @adap: the adapter 5775 * @reg_addr: Address Register 5776 * @reg_data: Data register 5777 * @buff: where the indirect register values are stored/written 5778 * @nregs: how many indirect registers to read/write 5779 * @start_index: index of first indirect register to read/write 5780 * @rw: READ(1) or WRITE(0) 5781 * @sleep_ok: if true we may sleep while awaiting command completion 5782 * 5783 * Read/Write TP indirect registers through LDST if possible. 5784 * Else, use backdoor access 5785 **/ 5786 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5787 u32 *buff, u32 nregs, u32 start_index, int rw, 5788 bool sleep_ok) 5789 { 5790 int rc = -EINVAL; 5791 int cmd; 5792 5793 switch (reg_addr) { 5794 case A_TP_PIO_ADDR: 5795 cmd = FW_LDST_ADDRSPC_TP_PIO; 5796 break; 5797 case A_TP_TM_PIO_ADDR: 5798 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5799 break; 5800 case A_TP_MIB_INDEX: 5801 cmd = FW_LDST_ADDRSPC_TP_MIB; 5802 break; 5803 default: 5804 goto indirect_access; 5805 } 5806 5807 if (t4_use_ldst(adap)) 5808 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5809 sleep_ok); 5810 5811 indirect_access: 5812 5813 if (rc) { 5814 if (rw) 5815 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5816 start_index); 5817 else 5818 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5819 start_index); 5820 } 5821 } 5822 5823 /** 5824 * t4_tp_pio_read - Read TP PIO registers 5825 * @adap: the adapter 5826 * @buff: where the indirect register values are written 5827 * @nregs: how many indirect registers to read 5828 * @start_index: index of first indirect register to read 5829 * @sleep_ok: if true we may sleep while awaiting command completion 5830 * 5831 * Read TP PIO Registers 5832 **/ 5833 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5834 u32 start_index, bool sleep_ok) 5835 { 5836 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5837 start_index, 1, sleep_ok); 5838 } 5839 5840 /** 5841 * t4_tp_pio_write - Write TP PIO registers 5842 * @adap: the adapter 5843 * @buff: where the indirect register values are stored 5844 * @nregs: how many indirect registers to write 5845 * @start_index: index of first indirect register to write 5846 * @sleep_ok: if true we may sleep while awaiting command completion 5847 * 5848 * Write TP PIO Registers 5849 **/ 5850 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5851 u32 start_index, bool sleep_ok) 5852 { 5853 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5854 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5855 } 5856 5857 /** 5858 * t4_tp_tm_pio_read - Read TP TM PIO registers 5859 * @adap: the adapter 5860 * @buff: where the indirect register values are written 5861 * @nregs: how many indirect registers to read 5862 * @start_index: index of first indirect register to read 5863 * @sleep_ok: if true we may sleep while awaiting command completion 5864 * 5865 * Read TP TM PIO Registers 5866 **/ 5867 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5868 u32 start_index, bool sleep_ok) 5869 { 5870 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5871 nregs, start_index, 1, sleep_ok); 5872 } 5873 5874 /** 5875 * t4_tp_mib_read - Read TP MIB registers 5876 * @adap: the adapter 5877 * @buff: where the indirect register values are written 5878 * @nregs: how many indirect registers to read 5879 * @start_index: index of first indirect register to read 5880 * @sleep_ok: if true we may sleep while awaiting command completion 5881 * 5882 * Read TP MIB Registers 5883 **/ 5884 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5885 bool sleep_ok) 5886 { 5887 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5888 start_index, 1, sleep_ok); 5889 } 5890 5891 /** 5892 * t4_read_rss_key - read the global RSS key 5893 * @adap: the adapter 5894 * @key: 10-entry array holding the 320-bit RSS key 5895 * @sleep_ok: if true we may sleep while awaiting command completion 5896 * 5897 * Reads the global 320-bit RSS key. 5898 */ 5899 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5900 { 5901 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5902 } 5903 5904 /** 5905 * t4_write_rss_key - program one of the RSS keys 5906 * @adap: the adapter 5907 * @key: 10-entry array holding the 320-bit RSS key 5908 * @idx: which RSS key to write 5909 * @sleep_ok: if true we may sleep while awaiting command completion 5910 * 5911 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5912 * 0..15 the corresponding entry in the RSS key table is written, 5913 * otherwise the global RSS key is written. 5914 */ 5915 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5916 bool sleep_ok) 5917 { 5918 u8 rss_key_addr_cnt = 16; 5919 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5920 5921 /* 5922 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5923 * allows access to key addresses 16-63 by using KeyWrAddrX 5924 * as index[5:4](upper 2) into key table 5925 */ 5926 if ((chip_id(adap) > CHELSIO_T5) && 5927 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5928 rss_key_addr_cnt = 32; 5929 5930 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5931 5932 if (idx >= 0 && idx < rss_key_addr_cnt) { 5933 if (rss_key_addr_cnt > 16) 5934 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5935 vrt | V_KEYWRADDRX(idx >> 4) | 5936 V_T6_VFWRADDR(idx) | F_KEYWREN); 5937 else 5938 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5939 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5940 } 5941 } 5942 5943 /** 5944 * t4_read_rss_pf_config - read PF RSS Configuration Table 5945 * @adapter: the adapter 5946 * @index: the entry in the PF RSS table to read 5947 * @valp: where to store the returned value 5948 * @sleep_ok: if true we may sleep while awaiting command completion 5949 * 5950 * Reads the PF RSS Configuration Table at the specified index and returns 5951 * the value found there. 5952 */ 5953 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5954 u32 *valp, bool sleep_ok) 5955 { 5956 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5957 } 5958 5959 /** 5960 * t4_write_rss_pf_config - write PF RSS Configuration Table 5961 * @adapter: the adapter 5962 * @index: the entry in the VF RSS table to read 5963 * @val: the value to store 5964 * @sleep_ok: if true we may sleep while awaiting command completion 5965 * 5966 * Writes the PF RSS Configuration Table at the specified index with the 5967 * specified value. 5968 */ 5969 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5970 u32 val, bool sleep_ok) 5971 { 5972 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5973 sleep_ok); 5974 } 5975 5976 /** 5977 * t4_read_rss_vf_config - read VF RSS Configuration Table 5978 * @adapter: the adapter 5979 * @index: the entry in the VF RSS table to read 5980 * @vfl: where to store the returned VFL 5981 * @vfh: where to store the returned VFH 5982 * @sleep_ok: if true we may sleep while awaiting command completion 5983 * 5984 * Reads the VF RSS Configuration Table at the specified index and returns 5985 * the (VFL, VFH) values found there. 5986 */ 5987 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5988 u32 *vfl, u32 *vfh, bool sleep_ok) 5989 { 5990 u32 vrt, mask, data; 5991 5992 if (chip_id(adapter) <= CHELSIO_T5) { 5993 mask = V_VFWRADDR(M_VFWRADDR); 5994 data = V_VFWRADDR(index); 5995 } else { 5996 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5997 data = V_T6_VFWRADDR(index); 5998 } 5999 /* 6000 * Request that the index'th VF Table values be read into VFL/VFH. 6001 */ 6002 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6003 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6004 vrt |= data | F_VFRDEN; 6005 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6006 6007 /* 6008 * Grab the VFL/VFH values ... 6009 */ 6010 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6011 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6012 } 6013 6014 /** 6015 * t4_write_rss_vf_config - write VF RSS Configuration Table 6016 * 6017 * @adapter: the adapter 6018 * @index: the entry in the VF RSS table to write 6019 * @vfl: the VFL to store 6020 * @vfh: the VFH to store 6021 * 6022 * Writes the VF RSS Configuration Table at the specified index with the 6023 * specified (VFL, VFH) values. 6024 */ 6025 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 6026 u32 vfl, u32 vfh, bool sleep_ok) 6027 { 6028 u32 vrt, mask, data; 6029 6030 if (chip_id(adapter) <= CHELSIO_T5) { 6031 mask = V_VFWRADDR(M_VFWRADDR); 6032 data = V_VFWRADDR(index); 6033 } else { 6034 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6035 data = V_T6_VFWRADDR(index); 6036 } 6037 6038 /* 6039 * Load up VFL/VFH with the values to be written ... 6040 */ 6041 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6042 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6043 6044 /* 6045 * Write the VFL/VFH into the VF Table at index'th location. 6046 */ 6047 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6048 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6049 vrt |= data | F_VFRDEN; 6050 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6051 } 6052 6053 /** 6054 * t4_read_rss_pf_map - read PF RSS Map 6055 * @adapter: the adapter 6056 * @sleep_ok: if true we may sleep while awaiting command completion 6057 * 6058 * Reads the PF RSS Map register and returns its value. 6059 */ 6060 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 6061 { 6062 u32 pfmap; 6063 6064 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6065 6066 return pfmap; 6067 } 6068 6069 /** 6070 * t4_write_rss_pf_map - write PF RSS Map 6071 * @adapter: the adapter 6072 * @pfmap: PF RSS Map value 6073 * 6074 * Writes the specified value to the PF RSS Map register. 6075 */ 6076 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6077 { 6078 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6079 } 6080 6081 /** 6082 * t4_read_rss_pf_mask - read PF RSS Mask 6083 * @adapter: the adapter 6084 * @sleep_ok: if true we may sleep while awaiting command completion 6085 * 6086 * Reads the PF RSS Mask register and returns its value. 6087 */ 6088 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6089 { 6090 u32 pfmask; 6091 6092 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6093 6094 return pfmask; 6095 } 6096 6097 /** 6098 * t4_write_rss_pf_mask - write PF RSS Mask 6099 * @adapter: the adapter 6100 * @pfmask: PF RSS Mask value 6101 * 6102 * Writes the specified value to the PF RSS Mask register. 6103 */ 6104 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6105 { 6106 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6107 } 6108 6109 /** 6110 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6111 * @adap: the adapter 6112 * @v4: holds the TCP/IP counter values 6113 * @v6: holds the TCP/IPv6 counter values 6114 * @sleep_ok: if true we may sleep while awaiting command completion 6115 * 6116 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6117 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6118 */ 6119 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6120 struct tp_tcp_stats *v6, bool sleep_ok) 6121 { 6122 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6123 6124 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6125 #define STAT(x) val[STAT_IDX(x)] 6126 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6127 6128 if (v4) { 6129 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6130 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6131 v4->tcp_out_rsts = STAT(OUT_RST); 6132 v4->tcp_in_segs = STAT64(IN_SEG); 6133 v4->tcp_out_segs = STAT64(OUT_SEG); 6134 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6135 } 6136 if (v6) { 6137 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6138 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6139 v6->tcp_out_rsts = STAT(OUT_RST); 6140 v6->tcp_in_segs = STAT64(IN_SEG); 6141 v6->tcp_out_segs = STAT64(OUT_SEG); 6142 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6143 } 6144 #undef STAT64 6145 #undef STAT 6146 #undef STAT_IDX 6147 } 6148 6149 /** 6150 * t4_tp_get_err_stats - read TP's error MIB counters 6151 * @adap: the adapter 6152 * @st: holds the counter values 6153 * @sleep_ok: if true we may sleep while awaiting command completion 6154 * 6155 * Returns the values of TP's error counters. 6156 */ 6157 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6158 bool sleep_ok) 6159 { 6160 int nchan = adap->chip_params->nchan; 6161 6162 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6163 sleep_ok); 6164 6165 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6166 sleep_ok); 6167 6168 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6169 sleep_ok); 6170 6171 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6172 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6173 6174 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6175 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6176 6177 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6178 sleep_ok); 6179 6180 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6181 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6182 6183 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6184 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6185 6186 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6187 sleep_ok); 6188 } 6189 6190 /** 6191 * t4_tp_get_err_stats - read TP's error MIB counters 6192 * @adap: the adapter 6193 * @st: holds the counter values 6194 * @sleep_ok: if true we may sleep while awaiting command completion 6195 * 6196 * Returns the values of TP's error counters. 6197 */ 6198 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, 6199 bool sleep_ok) 6200 { 6201 int nchan = adap->chip_params->nchan; 6202 6203 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, 6204 sleep_ok); 6205 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, 6206 sleep_ok); 6207 } 6208 6209 /** 6210 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6211 * @adap: the adapter 6212 * @st: holds the counter values 6213 * 6214 * Returns the values of TP's proxy counters. 6215 */ 6216 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6217 bool sleep_ok) 6218 { 6219 int nchan = adap->chip_params->nchan; 6220 6221 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6222 } 6223 6224 /** 6225 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6226 * @adap: the adapter 6227 * @st: holds the counter values 6228 * @sleep_ok: if true we may sleep while awaiting command completion 6229 * 6230 * Returns the values of TP's CPL counters. 6231 */ 6232 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6233 bool sleep_ok) 6234 { 6235 int nchan = adap->chip_params->nchan; 6236 6237 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6238 6239 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6240 } 6241 6242 /** 6243 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6244 * @adap: the adapter 6245 * @st: holds the counter values 6246 * 6247 * Returns the values of TP's RDMA counters. 6248 */ 6249 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6250 bool sleep_ok) 6251 { 6252 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6253 sleep_ok); 6254 } 6255 6256 /** 6257 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6258 * @adap: the adapter 6259 * @idx: the port index 6260 * @st: holds the counter values 6261 * @sleep_ok: if true we may sleep while awaiting command completion 6262 * 6263 * Returns the values of TP's FCoE counters for the selected port. 6264 */ 6265 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6266 struct tp_fcoe_stats *st, bool sleep_ok) 6267 { 6268 u32 val[2]; 6269 6270 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6271 sleep_ok); 6272 6273 t4_tp_mib_read(adap, &st->frames_drop, 1, 6274 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6275 6276 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6277 sleep_ok); 6278 6279 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6280 } 6281 6282 /** 6283 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6284 * @adap: the adapter 6285 * @st: holds the counter values 6286 * @sleep_ok: if true we may sleep while awaiting command completion 6287 * 6288 * Returns the values of TP's counters for non-TCP directly-placed packets. 6289 */ 6290 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6291 bool sleep_ok) 6292 { 6293 u32 val[4]; 6294 6295 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6296 6297 st->frames = val[0]; 6298 st->drops = val[1]; 6299 st->octets = ((u64)val[2] << 32) | val[3]; 6300 } 6301 6302 /** 6303 * t4_tp_get_tid_stats - read TP's tid MIB counters. 6304 * @adap: the adapter 6305 * @st: holds the counter values 6306 * @sleep_ok: if true we may sleep while awaiting command completion 6307 * 6308 * Returns the values of TP's counters for tids. 6309 */ 6310 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, 6311 bool sleep_ok) 6312 { 6313 6314 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); 6315 } 6316 6317 /** 6318 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6319 * @adap: the adapter 6320 * @mtus: where to store the MTU values 6321 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6322 * 6323 * Reads the HW path MTU table. 6324 */ 6325 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6326 { 6327 u32 v; 6328 int i; 6329 6330 for (i = 0; i < NMTUS; ++i) { 6331 t4_write_reg(adap, A_TP_MTU_TABLE, 6332 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6333 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6334 mtus[i] = G_MTUVALUE(v); 6335 if (mtu_log) 6336 mtu_log[i] = G_MTUWIDTH(v); 6337 } 6338 } 6339 6340 /** 6341 * t4_read_cong_tbl - reads the congestion control table 6342 * @adap: the adapter 6343 * @incr: where to store the alpha values 6344 * 6345 * Reads the additive increments programmed into the HW congestion 6346 * control table. 6347 */ 6348 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6349 { 6350 unsigned int mtu, w; 6351 6352 for (mtu = 0; mtu < NMTUS; ++mtu) 6353 for (w = 0; w < NCCTRL_WIN; ++w) { 6354 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6355 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6356 incr[mtu][w] = (u16)t4_read_reg(adap, 6357 A_TP_CCTRL_TABLE) & 0x1fff; 6358 } 6359 } 6360 6361 /** 6362 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6363 * @adap: the adapter 6364 * @addr: the indirect TP register address 6365 * @mask: specifies the field within the register to modify 6366 * @val: new value for the field 6367 * 6368 * Sets a field of an indirect TP register to the given value. 6369 */ 6370 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6371 unsigned int mask, unsigned int val) 6372 { 6373 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6374 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6375 t4_write_reg(adap, A_TP_PIO_DATA, val); 6376 } 6377 6378 /** 6379 * init_cong_ctrl - initialize congestion control parameters 6380 * @a: the alpha values for congestion control 6381 * @b: the beta values for congestion control 6382 * 6383 * Initialize the congestion control parameters. 6384 */ 6385 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6386 { 6387 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6388 a[9] = 2; 6389 a[10] = 3; 6390 a[11] = 4; 6391 a[12] = 5; 6392 a[13] = 6; 6393 a[14] = 7; 6394 a[15] = 8; 6395 a[16] = 9; 6396 a[17] = 10; 6397 a[18] = 14; 6398 a[19] = 17; 6399 a[20] = 21; 6400 a[21] = 25; 6401 a[22] = 30; 6402 a[23] = 35; 6403 a[24] = 45; 6404 a[25] = 60; 6405 a[26] = 80; 6406 a[27] = 100; 6407 a[28] = 200; 6408 a[29] = 300; 6409 a[30] = 400; 6410 a[31] = 500; 6411 6412 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6413 b[9] = b[10] = 1; 6414 b[11] = b[12] = 2; 6415 b[13] = b[14] = b[15] = b[16] = 3; 6416 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6417 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6418 b[28] = b[29] = 6; 6419 b[30] = b[31] = 7; 6420 } 6421 6422 /* The minimum additive increment value for the congestion control table */ 6423 #define CC_MIN_INCR 2U 6424 6425 /** 6426 * t4_load_mtus - write the MTU and congestion control HW tables 6427 * @adap: the adapter 6428 * @mtus: the values for the MTU table 6429 * @alpha: the values for the congestion control alpha parameter 6430 * @beta: the values for the congestion control beta parameter 6431 * 6432 * Write the HW MTU table with the supplied MTUs and the high-speed 6433 * congestion control table with the supplied alpha, beta, and MTUs. 6434 * We write the two tables together because the additive increments 6435 * depend on the MTUs. 6436 */ 6437 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6438 const unsigned short *alpha, const unsigned short *beta) 6439 { 6440 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6441 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6442 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6443 28672, 40960, 57344, 81920, 114688, 163840, 229376 6444 }; 6445 6446 unsigned int i, w; 6447 6448 for (i = 0; i < NMTUS; ++i) { 6449 unsigned int mtu = mtus[i]; 6450 unsigned int log2 = fls(mtu); 6451 6452 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6453 log2--; 6454 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6455 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6456 6457 for (w = 0; w < NCCTRL_WIN; ++w) { 6458 unsigned int inc; 6459 6460 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6461 CC_MIN_INCR); 6462 6463 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6464 (w << 16) | (beta[w] << 13) | inc); 6465 } 6466 } 6467 } 6468 6469 /** 6470 * t4_set_pace_tbl - set the pace table 6471 * @adap: the adapter 6472 * @pace_vals: the pace values in microseconds 6473 * @start: index of the first entry in the HW pace table to set 6474 * @n: how many entries to set 6475 * 6476 * Sets (a subset of the) HW pace table. 6477 */ 6478 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6479 unsigned int start, unsigned int n) 6480 { 6481 unsigned int vals[NTX_SCHED], i; 6482 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6483 6484 if (n > NTX_SCHED) 6485 return -ERANGE; 6486 6487 /* convert values from us to dack ticks, rounding to closest value */ 6488 for (i = 0; i < n; i++, pace_vals++) { 6489 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6490 if (vals[i] > 0x7ff) 6491 return -ERANGE; 6492 if (*pace_vals && vals[i] == 0) 6493 return -ERANGE; 6494 } 6495 for (i = 0; i < n; i++, start++) 6496 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6497 return 0; 6498 } 6499 6500 /** 6501 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6502 * @adap: the adapter 6503 * @kbps: target rate in Kbps 6504 * @sched: the scheduler index 6505 * 6506 * Configure a Tx HW scheduler for the target rate. 6507 */ 6508 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6509 { 6510 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6511 unsigned int clk = adap->params.vpd.cclk * 1000; 6512 unsigned int selected_cpt = 0, selected_bpt = 0; 6513 6514 if (kbps > 0) { 6515 kbps *= 125; /* -> bytes */ 6516 for (cpt = 1; cpt <= 255; cpt++) { 6517 tps = clk / cpt; 6518 bpt = (kbps + tps / 2) / tps; 6519 if (bpt > 0 && bpt <= 255) { 6520 v = bpt * tps; 6521 delta = v >= kbps ? v - kbps : kbps - v; 6522 if (delta < mindelta) { 6523 mindelta = delta; 6524 selected_cpt = cpt; 6525 selected_bpt = bpt; 6526 } 6527 } else if (selected_cpt) 6528 break; 6529 } 6530 if (!selected_cpt) 6531 return -EINVAL; 6532 } 6533 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6534 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6535 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6536 if (sched & 1) 6537 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6538 else 6539 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6540 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6541 return 0; 6542 } 6543 6544 /** 6545 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6546 * @adap: the adapter 6547 * @sched: the scheduler index 6548 * @ipg: the interpacket delay in tenths of nanoseconds 6549 * 6550 * Set the interpacket delay for a HW packet rate scheduler. 6551 */ 6552 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6553 { 6554 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6555 6556 /* convert ipg to nearest number of core clocks */ 6557 ipg *= core_ticks_per_usec(adap); 6558 ipg = (ipg + 5000) / 10000; 6559 if (ipg > M_TXTIMERSEPQ0) 6560 return -EINVAL; 6561 6562 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6563 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6564 if (sched & 1) 6565 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6566 else 6567 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6568 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6569 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6570 return 0; 6571 } 6572 6573 /* 6574 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6575 * clocks. The formula is 6576 * 6577 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6578 * 6579 * which is equivalent to 6580 * 6581 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6582 */ 6583 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6584 { 6585 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6586 6587 return v * 62 + v / 2; 6588 } 6589 6590 /** 6591 * t4_get_chan_txrate - get the current per channel Tx rates 6592 * @adap: the adapter 6593 * @nic_rate: rates for NIC traffic 6594 * @ofld_rate: rates for offloaded traffic 6595 * 6596 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6597 * for each channel. 6598 */ 6599 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6600 { 6601 u32 v; 6602 6603 v = t4_read_reg(adap, A_TP_TX_TRATE); 6604 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6605 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6606 if (adap->chip_params->nchan > 2) { 6607 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6608 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6609 } 6610 6611 v = t4_read_reg(adap, A_TP_TX_ORATE); 6612 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6613 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6614 if (adap->chip_params->nchan > 2) { 6615 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6616 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6617 } 6618 } 6619 6620 /** 6621 * t4_set_trace_filter - configure one of the tracing filters 6622 * @adap: the adapter 6623 * @tp: the desired trace filter parameters 6624 * @idx: which filter to configure 6625 * @enable: whether to enable or disable the filter 6626 * 6627 * Configures one of the tracing filters available in HW. If @tp is %NULL 6628 * it indicates that the filter is already written in the register and it 6629 * just needs to be enabled or disabled. 6630 */ 6631 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6632 int idx, int enable) 6633 { 6634 int i, ofst = idx * 4; 6635 u32 data_reg, mask_reg, cfg; 6636 u32 multitrc = F_TRCMULTIFILTER; 6637 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6638 6639 if (idx < 0 || idx >= NTRACE) 6640 return -EINVAL; 6641 6642 if (tp == NULL || !enable) { 6643 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6644 enable ? en : 0); 6645 return 0; 6646 } 6647 6648 /* 6649 * TODO - After T4 data book is updated, specify the exact 6650 * section below. 6651 * 6652 * See T4 data book - MPS section for a complete description 6653 * of the below if..else handling of A_MPS_TRC_CFG register 6654 * value. 6655 */ 6656 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6657 if (cfg & F_TRCMULTIFILTER) { 6658 /* 6659 * If multiple tracers are enabled, then maximum 6660 * capture size is 2.5KB (FIFO size of a single channel) 6661 * minus 2 flits for CPL_TRACE_PKT header. 6662 */ 6663 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6664 return -EINVAL; 6665 } else { 6666 /* 6667 * If multiple tracers are disabled, to avoid deadlocks 6668 * maximum packet capture size of 9600 bytes is recommended. 6669 * Also in this mode, only trace0 can be enabled and running. 6670 */ 6671 multitrc = 0; 6672 if (tp->snap_len > 9600 || idx) 6673 return -EINVAL; 6674 } 6675 6676 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6677 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6678 tp->min_len > M_TFMINPKTSIZE) 6679 return -EINVAL; 6680 6681 /* stop the tracer we'll be changing */ 6682 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6683 6684 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6685 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6686 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6687 6688 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6689 t4_write_reg(adap, data_reg, tp->data[i]); 6690 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6691 } 6692 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6693 V_TFCAPTUREMAX(tp->snap_len) | 6694 V_TFMINPKTSIZE(tp->min_len)); 6695 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6696 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6697 (is_t4(adap) ? 6698 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6699 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6700 6701 return 0; 6702 } 6703 6704 /** 6705 * t4_get_trace_filter - query one of the tracing filters 6706 * @adap: the adapter 6707 * @tp: the current trace filter parameters 6708 * @idx: which trace filter to query 6709 * @enabled: non-zero if the filter is enabled 6710 * 6711 * Returns the current settings of one of the HW tracing filters. 6712 */ 6713 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6714 int *enabled) 6715 { 6716 u32 ctla, ctlb; 6717 int i, ofst = idx * 4; 6718 u32 data_reg, mask_reg; 6719 6720 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6721 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6722 6723 if (is_t4(adap)) { 6724 *enabled = !!(ctla & F_TFEN); 6725 tp->port = G_TFPORT(ctla); 6726 tp->invert = !!(ctla & F_TFINVERTMATCH); 6727 } else { 6728 *enabled = !!(ctla & F_T5_TFEN); 6729 tp->port = G_T5_TFPORT(ctla); 6730 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6731 } 6732 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6733 tp->min_len = G_TFMINPKTSIZE(ctlb); 6734 tp->skip_ofst = G_TFOFFSET(ctla); 6735 tp->skip_len = G_TFLENGTH(ctla); 6736 6737 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6738 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6739 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6740 6741 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6742 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6743 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6744 } 6745 } 6746 6747 /** 6748 * t4_pmtx_get_stats - returns the HW stats from PMTX 6749 * @adap: the adapter 6750 * @cnt: where to store the count statistics 6751 * @cycles: where to store the cycle statistics 6752 * 6753 * Returns performance statistics from PMTX. 6754 */ 6755 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6756 { 6757 int i; 6758 u32 data[2]; 6759 6760 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6761 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6762 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6763 if (is_t4(adap)) 6764 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6765 else { 6766 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6767 A_PM_TX_DBG_DATA, data, 2, 6768 A_PM_TX_DBG_STAT_MSB); 6769 cycles[i] = (((u64)data[0] << 32) | data[1]); 6770 } 6771 } 6772 } 6773 6774 /** 6775 * t4_pmrx_get_stats - returns the HW stats from PMRX 6776 * @adap: the adapter 6777 * @cnt: where to store the count statistics 6778 * @cycles: where to store the cycle statistics 6779 * 6780 * Returns performance statistics from PMRX. 6781 */ 6782 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6783 { 6784 int i; 6785 u32 data[2]; 6786 6787 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6788 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6789 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6790 if (is_t4(adap)) { 6791 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6792 } else { 6793 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6794 A_PM_RX_DBG_DATA, data, 2, 6795 A_PM_RX_DBG_STAT_MSB); 6796 cycles[i] = (((u64)data[0] << 32) | data[1]); 6797 } 6798 } 6799 } 6800 6801 /** 6802 * t4_get_mps_bg_map - return the buffer groups associated with a port 6803 * @adap: the adapter 6804 * @idx: the port index 6805 * 6806 * Returns a bitmap indicating which MPS buffer groups are associated 6807 * with the given port. Bit i is set if buffer group i is used by the 6808 * port. 6809 */ 6810 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6811 { 6812 u32 n; 6813 6814 if (adap->params.mps_bg_map) 6815 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6816 6817 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6818 if (n == 0) 6819 return idx == 0 ? 0xf : 0; 6820 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6821 return idx < 2 ? (3 << (2 * idx)) : 0; 6822 return 1 << idx; 6823 } 6824 6825 /* 6826 * TP RX e-channels associated with the port. 6827 */ 6828 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6829 { 6830 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6831 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; 6832 6833 if (n == 0) 6834 return idx == 0 ? all_chan : 0; 6835 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6836 return idx < 2 ? (3 << (2 * idx)) : 0; 6837 return 1 << idx; 6838 } 6839 6840 /* 6841 * TP RX c-channel associated with the port. 6842 */ 6843 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx) 6844 { 6845 u32 param, val; 6846 int ret; 6847 6848 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6849 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP)); 6850 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 6851 if (!ret) 6852 return (val >> (8 * idx)) & 0xff; 6853 6854 return 0; 6855 } 6856 6857 /** 6858 * t4_get_port_type_description - return Port Type string description 6859 * @port_type: firmware Port Type enumeration 6860 */ 6861 const char *t4_get_port_type_description(enum fw_port_type port_type) 6862 { 6863 static const char *const port_type_description[] = { 6864 "Fiber_XFI", 6865 "Fiber_XAUI", 6866 "BT_SGMII", 6867 "BT_XFI", 6868 "BT_XAUI", 6869 "KX4", 6870 "CX4", 6871 "KX", 6872 "KR", 6873 "SFP", 6874 "BP_AP", 6875 "BP4_AP", 6876 "QSFP_10G", 6877 "QSA", 6878 "QSFP", 6879 "BP40_BA", 6880 "KR4_100G", 6881 "CR4_QSFP", 6882 "CR_QSFP", 6883 "CR2_QSFP", 6884 "SFP28", 6885 "KR_SFP28", 6886 }; 6887 6888 if (port_type < ARRAY_SIZE(port_type_description)) 6889 return port_type_description[port_type]; 6890 return "UNKNOWN"; 6891 } 6892 6893 /** 6894 * t4_get_port_stats_offset - collect port stats relative to a previous 6895 * snapshot 6896 * @adap: The adapter 6897 * @idx: The port 6898 * @stats: Current stats to fill 6899 * @offset: Previous stats snapshot 6900 */ 6901 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6902 struct port_stats *stats, 6903 struct port_stats *offset) 6904 { 6905 u64 *s, *o; 6906 int i; 6907 6908 t4_get_port_stats(adap, idx, stats); 6909 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6910 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6911 i++, s++, o++) 6912 *s -= *o; 6913 } 6914 6915 /** 6916 * t4_get_port_stats - collect port statistics 6917 * @adap: the adapter 6918 * @idx: the port index 6919 * @p: the stats structure to fill 6920 * 6921 * Collect statistics related to the given port from HW. 6922 */ 6923 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6924 { 6925 struct port_info *pi = adap->port[idx]; 6926 u32 bgmap = pi->mps_bg_map; 6927 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6928 6929 #define GET_STAT(name) \ 6930 t4_read_reg64(adap, \ 6931 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6932 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6933 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6934 6935 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6936 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6937 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6938 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6939 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6940 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6941 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6942 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6943 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6944 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6945 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6946 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6947 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6948 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6949 p->tx_drop = GET_STAT(TX_PORT_DROP); 6950 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6951 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6952 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6953 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6954 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6955 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6956 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6957 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6958 6959 if (chip_id(adap) >= CHELSIO_T5) { 6960 if (stat_ctl & F_COUNTPAUSESTATTX) { 6961 p->tx_frames -= p->tx_pause; 6962 p->tx_octets -= p->tx_pause * 64; 6963 } 6964 if (stat_ctl & F_COUNTPAUSEMCTX) 6965 p->tx_mcast_frames -= p->tx_pause; 6966 } 6967 6968 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6969 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6970 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6971 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6972 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6973 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6974 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6975 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6976 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6977 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6978 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6979 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6980 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6981 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6982 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6983 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6984 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6985 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6986 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6987 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6988 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6989 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6990 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6991 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6992 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6993 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6994 6995 if (pi->fcs_reg != -1) 6996 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; 6997 6998 if (chip_id(adap) >= CHELSIO_T5) { 6999 if (stat_ctl & F_COUNTPAUSESTATRX) { 7000 p->rx_frames -= p->rx_pause; 7001 p->rx_octets -= p->rx_pause * 64; 7002 } 7003 if (stat_ctl & F_COUNTPAUSEMCRX) 7004 p->rx_mcast_frames -= p->rx_pause; 7005 } 7006 7007 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 7008 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 7009 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 7010 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 7011 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 7012 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 7013 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 7014 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 7015 7016 #undef GET_STAT 7017 #undef GET_STAT_COM 7018 } 7019 7020 /** 7021 * t4_get_lb_stats - collect loopback port statistics 7022 * @adap: the adapter 7023 * @idx: the loopback port index 7024 * @p: the stats structure to fill 7025 * 7026 * Return HW statistics for the given loopback port. 7027 */ 7028 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 7029 { 7030 7031 #define GET_STAT(name) \ 7032 t4_read_reg64(adap, \ 7033 (is_t4(adap) ? \ 7034 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 7035 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 7036 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 7037 7038 p->octets = GET_STAT(BYTES); 7039 p->frames = GET_STAT(FRAMES); 7040 p->bcast_frames = GET_STAT(BCAST); 7041 p->mcast_frames = GET_STAT(MCAST); 7042 p->ucast_frames = GET_STAT(UCAST); 7043 p->error_frames = GET_STAT(ERROR); 7044 7045 p->frames_64 = GET_STAT(64B); 7046 p->frames_65_127 = GET_STAT(65B_127B); 7047 p->frames_128_255 = GET_STAT(128B_255B); 7048 p->frames_256_511 = GET_STAT(256B_511B); 7049 p->frames_512_1023 = GET_STAT(512B_1023B); 7050 p->frames_1024_1518 = GET_STAT(1024B_1518B); 7051 p->frames_1519_max = GET_STAT(1519B_MAX); 7052 p->drop = GET_STAT(DROP_FRAMES); 7053 7054 if (idx < adap->params.nports) { 7055 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; 7056 7057 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 7058 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 7059 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 7060 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 7061 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 7062 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 7063 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 7064 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 7065 } 7066 7067 #undef GET_STAT 7068 #undef GET_STAT_COM 7069 } 7070 7071 /** 7072 * t4_wol_magic_enable - enable/disable magic packet WoL 7073 * @adap: the adapter 7074 * @port: the physical port index 7075 * @addr: MAC address expected in magic packets, %NULL to disable 7076 * 7077 * Enables/disables magic packet wake-on-LAN for the selected port. 7078 */ 7079 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 7080 const u8 *addr) 7081 { 7082 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 7083 7084 if (is_t4(adap)) { 7085 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 7086 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 7087 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7088 } else { 7089 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 7090 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 7091 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7092 } 7093 7094 if (addr) { 7095 t4_write_reg(adap, mag_id_reg_l, 7096 (addr[2] << 24) | (addr[3] << 16) | 7097 (addr[4] << 8) | addr[5]); 7098 t4_write_reg(adap, mag_id_reg_h, 7099 (addr[0] << 8) | addr[1]); 7100 } 7101 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 7102 V_MAGICEN(addr != NULL)); 7103 } 7104 7105 /** 7106 * t4_wol_pat_enable - enable/disable pattern-based WoL 7107 * @adap: the adapter 7108 * @port: the physical port index 7109 * @map: bitmap of which HW pattern filters to set 7110 * @mask0: byte mask for bytes 0-63 of a packet 7111 * @mask1: byte mask for bytes 64-127 of a packet 7112 * @crc: Ethernet CRC for selected bytes 7113 * @enable: enable/disable switch 7114 * 7115 * Sets the pattern filters indicated in @map to mask out the bytes 7116 * specified in @mask0/@mask1 in received packets and compare the CRC of 7117 * the resulting packet against @crc. If @enable is %true pattern-based 7118 * WoL is enabled, otherwise disabled. 7119 */ 7120 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 7121 u64 mask0, u64 mask1, unsigned int crc, bool enable) 7122 { 7123 int i; 7124 u32 port_cfg_reg; 7125 7126 if (is_t4(adap)) 7127 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7128 else 7129 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7130 7131 if (!enable) { 7132 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7133 return 0; 7134 } 7135 if (map > 0xff) 7136 return -EINVAL; 7137 7138 #define EPIO_REG(name) \ 7139 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7140 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7141 7142 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7143 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7144 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7145 7146 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7147 if (!(map & 1)) 7148 continue; 7149 7150 /* write byte masks */ 7151 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7152 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7153 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7154 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7155 return -ETIMEDOUT; 7156 7157 /* write CRC */ 7158 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7159 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7160 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7161 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7162 return -ETIMEDOUT; 7163 } 7164 #undef EPIO_REG 7165 7166 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7167 return 0; 7168 } 7169 7170 /* t4_mk_filtdelwr - create a delete filter WR 7171 * @ftid: the filter ID 7172 * @wr: the filter work request to populate 7173 * @qid: ingress queue to receive the delete notification 7174 * 7175 * Creates a filter work request to delete the supplied filter. If @qid is 7176 * negative the delete notification is suppressed. 7177 */ 7178 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7179 { 7180 memset(wr, 0, sizeof(*wr)); 7181 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7182 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7183 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7184 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7185 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7186 if (qid >= 0) 7187 wr->rx_chan_rx_rpl_iq = 7188 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7189 } 7190 7191 #define INIT_CMD(var, cmd, rd_wr) do { \ 7192 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7193 F_FW_CMD_REQUEST | \ 7194 F_FW_CMD_##rd_wr); \ 7195 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7196 } while (0) 7197 7198 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7199 u32 addr, u32 val) 7200 { 7201 u32 ldst_addrspace; 7202 struct fw_ldst_cmd c; 7203 7204 memset(&c, 0, sizeof(c)); 7205 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7206 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7207 F_FW_CMD_REQUEST | 7208 F_FW_CMD_WRITE | 7209 ldst_addrspace); 7210 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7211 c.u.addrval.addr = cpu_to_be32(addr); 7212 c.u.addrval.val = cpu_to_be32(val); 7213 7214 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7215 } 7216 7217 /** 7218 * t4_mdio_rd - read a PHY register through MDIO 7219 * @adap: the adapter 7220 * @mbox: mailbox to use for the FW command 7221 * @phy_addr: the PHY address 7222 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7223 * @reg: the register to read 7224 * @valp: where to store the value 7225 * 7226 * Issues a FW command through the given mailbox to read a PHY register. 7227 */ 7228 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7229 unsigned int mmd, unsigned int reg, unsigned int *valp) 7230 { 7231 int ret; 7232 u32 ldst_addrspace; 7233 struct fw_ldst_cmd c; 7234 7235 memset(&c, 0, sizeof(c)); 7236 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7237 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7238 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7239 ldst_addrspace); 7240 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7241 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7242 V_FW_LDST_CMD_MMD(mmd)); 7243 c.u.mdio.raddr = cpu_to_be16(reg); 7244 7245 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7246 if (ret == 0) 7247 *valp = be16_to_cpu(c.u.mdio.rval); 7248 return ret; 7249 } 7250 7251 /** 7252 * t4_mdio_wr - write a PHY register through MDIO 7253 * @adap: the adapter 7254 * @mbox: mailbox to use for the FW command 7255 * @phy_addr: the PHY address 7256 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7257 * @reg: the register to write 7258 * @valp: value to write 7259 * 7260 * Issues a FW command through the given mailbox to write a PHY register. 7261 */ 7262 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7263 unsigned int mmd, unsigned int reg, unsigned int val) 7264 { 7265 u32 ldst_addrspace; 7266 struct fw_ldst_cmd c; 7267 7268 memset(&c, 0, sizeof(c)); 7269 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7270 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7271 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7272 ldst_addrspace); 7273 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7274 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7275 V_FW_LDST_CMD_MMD(mmd)); 7276 c.u.mdio.raddr = cpu_to_be16(reg); 7277 c.u.mdio.rval = cpu_to_be16(val); 7278 7279 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7280 } 7281 7282 /** 7283 * 7284 * t4_sge_decode_idma_state - decode the idma state 7285 * @adap: the adapter 7286 * @state: the state idma is stuck in 7287 */ 7288 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7289 { 7290 static const char * const t4_decode[] = { 7291 "IDMA_IDLE", 7292 "IDMA_PUSH_MORE_CPL_FIFO", 7293 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7294 "Not used", 7295 "IDMA_PHYSADDR_SEND_PCIEHDR", 7296 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7297 "IDMA_PHYSADDR_SEND_PAYLOAD", 7298 "IDMA_SEND_FIFO_TO_IMSG", 7299 "IDMA_FL_REQ_DATA_FL_PREP", 7300 "IDMA_FL_REQ_DATA_FL", 7301 "IDMA_FL_DROP", 7302 "IDMA_FL_H_REQ_HEADER_FL", 7303 "IDMA_FL_H_SEND_PCIEHDR", 7304 "IDMA_FL_H_PUSH_CPL_FIFO", 7305 "IDMA_FL_H_SEND_CPL", 7306 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7307 "IDMA_FL_H_SEND_IP_HDR", 7308 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7309 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7310 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7311 "IDMA_FL_D_SEND_PCIEHDR", 7312 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7313 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7314 "IDMA_FL_SEND_PCIEHDR", 7315 "IDMA_FL_PUSH_CPL_FIFO", 7316 "IDMA_FL_SEND_CPL", 7317 "IDMA_FL_SEND_PAYLOAD_FIRST", 7318 "IDMA_FL_SEND_PAYLOAD", 7319 "IDMA_FL_REQ_NEXT_DATA_FL", 7320 "IDMA_FL_SEND_NEXT_PCIEHDR", 7321 "IDMA_FL_SEND_PADDING", 7322 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7323 "IDMA_FL_SEND_FIFO_TO_IMSG", 7324 "IDMA_FL_REQ_DATAFL_DONE", 7325 "IDMA_FL_REQ_HEADERFL_DONE", 7326 }; 7327 static const char * const t5_decode[] = { 7328 "IDMA_IDLE", 7329 "IDMA_ALMOST_IDLE", 7330 "IDMA_PUSH_MORE_CPL_FIFO", 7331 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7332 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7333 "IDMA_PHYSADDR_SEND_PCIEHDR", 7334 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7335 "IDMA_PHYSADDR_SEND_PAYLOAD", 7336 "IDMA_SEND_FIFO_TO_IMSG", 7337 "IDMA_FL_REQ_DATA_FL", 7338 "IDMA_FL_DROP", 7339 "IDMA_FL_DROP_SEND_INC", 7340 "IDMA_FL_H_REQ_HEADER_FL", 7341 "IDMA_FL_H_SEND_PCIEHDR", 7342 "IDMA_FL_H_PUSH_CPL_FIFO", 7343 "IDMA_FL_H_SEND_CPL", 7344 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7345 "IDMA_FL_H_SEND_IP_HDR", 7346 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7347 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7348 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7349 "IDMA_FL_D_SEND_PCIEHDR", 7350 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7351 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7352 "IDMA_FL_SEND_PCIEHDR", 7353 "IDMA_FL_PUSH_CPL_FIFO", 7354 "IDMA_FL_SEND_CPL", 7355 "IDMA_FL_SEND_PAYLOAD_FIRST", 7356 "IDMA_FL_SEND_PAYLOAD", 7357 "IDMA_FL_REQ_NEXT_DATA_FL", 7358 "IDMA_FL_SEND_NEXT_PCIEHDR", 7359 "IDMA_FL_SEND_PADDING", 7360 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7361 }; 7362 static const char * const t6_decode[] = { 7363 "IDMA_IDLE", 7364 "IDMA_PUSH_MORE_CPL_FIFO", 7365 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7366 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7367 "IDMA_PHYSADDR_SEND_PCIEHDR", 7368 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7369 "IDMA_PHYSADDR_SEND_PAYLOAD", 7370 "IDMA_FL_REQ_DATA_FL", 7371 "IDMA_FL_DROP", 7372 "IDMA_FL_DROP_SEND_INC", 7373 "IDMA_FL_H_REQ_HEADER_FL", 7374 "IDMA_FL_H_SEND_PCIEHDR", 7375 "IDMA_FL_H_PUSH_CPL_FIFO", 7376 "IDMA_FL_H_SEND_CPL", 7377 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7378 "IDMA_FL_H_SEND_IP_HDR", 7379 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7380 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7381 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7382 "IDMA_FL_D_SEND_PCIEHDR", 7383 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7384 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7385 "IDMA_FL_SEND_PCIEHDR", 7386 "IDMA_FL_PUSH_CPL_FIFO", 7387 "IDMA_FL_SEND_CPL", 7388 "IDMA_FL_SEND_PAYLOAD_FIRST", 7389 "IDMA_FL_SEND_PAYLOAD", 7390 "IDMA_FL_REQ_NEXT_DATA_FL", 7391 "IDMA_FL_SEND_NEXT_PCIEHDR", 7392 "IDMA_FL_SEND_PADDING", 7393 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7394 }; 7395 static const u32 sge_regs[] = { 7396 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7397 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7398 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7399 }; 7400 const char * const *sge_idma_decode; 7401 int sge_idma_decode_nstates; 7402 int i; 7403 unsigned int chip_version = chip_id(adapter); 7404 7405 /* Select the right set of decode strings to dump depending on the 7406 * adapter chip type. 7407 */ 7408 switch (chip_version) { 7409 case CHELSIO_T4: 7410 sge_idma_decode = (const char * const *)t4_decode; 7411 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7412 break; 7413 7414 case CHELSIO_T5: 7415 sge_idma_decode = (const char * const *)t5_decode; 7416 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7417 break; 7418 7419 case CHELSIO_T6: 7420 sge_idma_decode = (const char * const *)t6_decode; 7421 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7422 break; 7423 7424 default: 7425 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7426 return; 7427 } 7428 7429 if (state < sge_idma_decode_nstates) 7430 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7431 else 7432 CH_WARN(adapter, "idma state %d unknown\n", state); 7433 7434 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7435 CH_WARN(adapter, "SGE register %#x value %#x\n", 7436 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7437 } 7438 7439 /** 7440 * t4_sge_ctxt_flush - flush the SGE context cache 7441 * @adap: the adapter 7442 * @mbox: mailbox to use for the FW command 7443 * 7444 * Issues a FW command through the given mailbox to flush the 7445 * SGE context cache. 7446 */ 7447 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type) 7448 { 7449 int ret; 7450 u32 ldst_addrspace; 7451 struct fw_ldst_cmd c; 7452 7453 memset(&c, 0, sizeof(c)); 7454 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ? 7455 FW_LDST_ADDRSPC_SGE_EGRC : 7456 FW_LDST_ADDRSPC_SGE_INGC); 7457 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7458 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7459 ldst_addrspace); 7460 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7461 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7462 7463 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7464 return ret; 7465 } 7466 7467 /** 7468 * t4_fw_hello - establish communication with FW 7469 * @adap: the adapter 7470 * @mbox: mailbox to use for the FW command 7471 * @evt_mbox: mailbox to receive async FW events 7472 * @master: specifies the caller's willingness to be the device master 7473 * @state: returns the current device state (if non-NULL) 7474 * 7475 * Issues a command to establish communication with FW. Returns either 7476 * an error (negative integer) or the mailbox of the Master PF. 7477 */ 7478 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7479 enum dev_master master, enum dev_state *state) 7480 { 7481 int ret; 7482 struct fw_hello_cmd c; 7483 u32 v; 7484 unsigned int master_mbox; 7485 int retries = FW_CMD_HELLO_RETRIES; 7486 7487 retry: 7488 memset(&c, 0, sizeof(c)); 7489 INIT_CMD(c, HELLO, WRITE); 7490 c.err_to_clearinit = cpu_to_be32( 7491 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7492 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7493 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7494 mbox : M_FW_HELLO_CMD_MBMASTER) | 7495 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7496 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7497 F_FW_HELLO_CMD_CLEARINIT); 7498 7499 /* 7500 * Issue the HELLO command to the firmware. If it's not successful 7501 * but indicates that we got a "busy" or "timeout" condition, retry 7502 * the HELLO until we exhaust our retry limit. If we do exceed our 7503 * retry limit, check to see if the firmware left us any error 7504 * information and report that if so ... 7505 */ 7506 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7507 if (ret != FW_SUCCESS) { 7508 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7509 goto retry; 7510 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7511 t4_report_fw_error(adap); 7512 return ret; 7513 } 7514 7515 v = be32_to_cpu(c.err_to_clearinit); 7516 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7517 if (state) { 7518 if (v & F_FW_HELLO_CMD_ERR) 7519 *state = DEV_STATE_ERR; 7520 else if (v & F_FW_HELLO_CMD_INIT) 7521 *state = DEV_STATE_INIT; 7522 else 7523 *state = DEV_STATE_UNINIT; 7524 } 7525 7526 /* 7527 * If we're not the Master PF then we need to wait around for the 7528 * Master PF Driver to finish setting up the adapter. 7529 * 7530 * Note that we also do this wait if we're a non-Master-capable PF and 7531 * there is no current Master PF; a Master PF may show up momentarily 7532 * and we wouldn't want to fail pointlessly. (This can happen when an 7533 * OS loads lots of different drivers rapidly at the same time). In 7534 * this case, the Master PF returned by the firmware will be 7535 * M_PCIE_FW_MASTER so the test below will work ... 7536 */ 7537 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7538 master_mbox != mbox) { 7539 int waiting = FW_CMD_HELLO_TIMEOUT; 7540 7541 /* 7542 * Wait for the firmware to either indicate an error or 7543 * initialized state. If we see either of these we bail out 7544 * and report the issue to the caller. If we exhaust the 7545 * "hello timeout" and we haven't exhausted our retries, try 7546 * again. Otherwise bail with a timeout error. 7547 */ 7548 for (;;) { 7549 u32 pcie_fw; 7550 7551 msleep(50); 7552 waiting -= 50; 7553 7554 /* 7555 * If neither Error nor Initialialized are indicated 7556 * by the firmware keep waiting till we exhaust our 7557 * timeout ... and then retry if we haven't exhausted 7558 * our retries ... 7559 */ 7560 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7561 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7562 if (waiting <= 0) { 7563 if (retries-- > 0) 7564 goto retry; 7565 7566 return -ETIMEDOUT; 7567 } 7568 continue; 7569 } 7570 7571 /* 7572 * We either have an Error or Initialized condition 7573 * report errors preferentially. 7574 */ 7575 if (state) { 7576 if (pcie_fw & F_PCIE_FW_ERR) 7577 *state = DEV_STATE_ERR; 7578 else if (pcie_fw & F_PCIE_FW_INIT) 7579 *state = DEV_STATE_INIT; 7580 } 7581 7582 /* 7583 * If we arrived before a Master PF was selected and 7584 * there's not a valid Master PF, grab its identity 7585 * for our caller. 7586 */ 7587 if (master_mbox == M_PCIE_FW_MASTER && 7588 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7589 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7590 break; 7591 } 7592 } 7593 7594 return master_mbox; 7595 } 7596 7597 /** 7598 * t4_fw_bye - end communication with FW 7599 * @adap: the adapter 7600 * @mbox: mailbox to use for the FW command 7601 * 7602 * Issues a command to terminate communication with FW. 7603 */ 7604 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7605 { 7606 struct fw_bye_cmd c; 7607 7608 memset(&c, 0, sizeof(c)); 7609 INIT_CMD(c, BYE, WRITE); 7610 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7611 } 7612 7613 /** 7614 * t4_fw_reset - issue a reset to FW 7615 * @adap: the adapter 7616 * @mbox: mailbox to use for the FW command 7617 * @reset: specifies the type of reset to perform 7618 * 7619 * Issues a reset command of the specified type to FW. 7620 */ 7621 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7622 { 7623 struct fw_reset_cmd c; 7624 7625 memset(&c, 0, sizeof(c)); 7626 INIT_CMD(c, RESET, WRITE); 7627 c.val = cpu_to_be32(reset); 7628 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7629 } 7630 7631 /** 7632 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7633 * @adap: the adapter 7634 * @mbox: mailbox to use for the FW RESET command (if desired) 7635 * @force: force uP into RESET even if FW RESET command fails 7636 * 7637 * Issues a RESET command to firmware (if desired) with a HALT indication 7638 * and then puts the microprocessor into RESET state. The RESET command 7639 * will only be issued if a legitimate mailbox is provided (mbox <= 7640 * M_PCIE_FW_MASTER). 7641 * 7642 * This is generally used in order for the host to safely manipulate the 7643 * adapter without fear of conflicting with whatever the firmware might 7644 * be doing. The only way out of this state is to RESTART the firmware 7645 * ... 7646 */ 7647 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7648 { 7649 int ret = 0; 7650 7651 /* 7652 * If a legitimate mailbox is provided, issue a RESET command 7653 * with a HALT indication. 7654 */ 7655 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7656 struct fw_reset_cmd c; 7657 7658 memset(&c, 0, sizeof(c)); 7659 INIT_CMD(c, RESET, WRITE); 7660 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7661 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7662 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7663 } 7664 7665 /* 7666 * Normally we won't complete the operation if the firmware RESET 7667 * command fails but if our caller insists we'll go ahead and put the 7668 * uP into RESET. This can be useful if the firmware is hung or even 7669 * missing ... We'll have to take the risk of putting the uP into 7670 * RESET without the cooperation of firmware in that case. 7671 * 7672 * We also force the firmware's HALT flag to be on in case we bypassed 7673 * the firmware RESET command above or we're dealing with old firmware 7674 * which doesn't have the HALT capability. This will serve as a flag 7675 * for the incoming firmware to know that it's coming out of a HALT 7676 * rather than a RESET ... if it's new enough to understand that ... 7677 */ 7678 if (ret == 0 || force) { 7679 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7680 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7681 F_PCIE_FW_HALT); 7682 } 7683 7684 /* 7685 * And we always return the result of the firmware RESET command 7686 * even when we force the uP into RESET ... 7687 */ 7688 return ret; 7689 } 7690 7691 /** 7692 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7693 * @adap: the adapter 7694 * 7695 * Restart firmware previously halted by t4_fw_halt(). On successful 7696 * return the previous PF Master remains as the new PF Master and there 7697 * is no need to issue a new HELLO command, etc. 7698 */ 7699 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7700 { 7701 int ms; 7702 7703 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7704 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7705 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7706 return FW_SUCCESS; 7707 msleep(100); 7708 ms += 100; 7709 } 7710 7711 return -ETIMEDOUT; 7712 } 7713 7714 /** 7715 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7716 * @adap: the adapter 7717 * @mbox: mailbox to use for the FW RESET command (if desired) 7718 * @fw_data: the firmware image to write 7719 * @size: image size 7720 * @force: force upgrade even if firmware doesn't cooperate 7721 * 7722 * Perform all of the steps necessary for upgrading an adapter's 7723 * firmware image. Normally this requires the cooperation of the 7724 * existing firmware in order to halt all existing activities 7725 * but if an invalid mailbox token is passed in we skip that step 7726 * (though we'll still put the adapter microprocessor into RESET in 7727 * that case). 7728 * 7729 * On successful return the new firmware will have been loaded and 7730 * the adapter will have been fully RESET losing all previous setup 7731 * state. On unsuccessful return the adapter may be completely hosed ... 7732 * positive errno indicates that the adapter is ~probably~ intact, a 7733 * negative errno indicates that things are looking bad ... 7734 */ 7735 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7736 const u8 *fw_data, unsigned int size, int force) 7737 { 7738 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7739 unsigned int bootstrap = 7740 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7741 int ret; 7742 7743 if (!t4_fw_matches_chip(adap, fw_hdr)) 7744 return -EINVAL; 7745 7746 if (!bootstrap) { 7747 ret = t4_fw_halt(adap, mbox, force); 7748 if (ret < 0 && !force) 7749 return ret; 7750 } 7751 7752 ret = t4_load_fw(adap, fw_data, size); 7753 if (ret < 0 || bootstrap) 7754 return ret; 7755 7756 return t4_fw_restart(adap, mbox); 7757 } 7758 7759 /** 7760 * t4_fw_initialize - ask FW to initialize the device 7761 * @adap: the adapter 7762 * @mbox: mailbox to use for the FW command 7763 * 7764 * Issues a command to FW to partially initialize the device. This 7765 * performs initialization that generally doesn't depend on user input. 7766 */ 7767 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7768 { 7769 struct fw_initialize_cmd c; 7770 7771 memset(&c, 0, sizeof(c)); 7772 INIT_CMD(c, INITIALIZE, WRITE); 7773 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7774 } 7775 7776 /** 7777 * t4_query_params_rw - query FW or device parameters 7778 * @adap: the adapter 7779 * @mbox: mailbox to use for the FW command 7780 * @pf: the PF 7781 * @vf: the VF 7782 * @nparams: the number of parameters 7783 * @params: the parameter names 7784 * @val: the parameter values 7785 * @rw: Write and read flag 7786 * 7787 * Reads the value of FW or device parameters. Up to 7 parameters can be 7788 * queried at once. 7789 */ 7790 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7791 unsigned int vf, unsigned int nparams, const u32 *params, 7792 u32 *val, int rw) 7793 { 7794 int i, ret; 7795 struct fw_params_cmd c; 7796 __be32 *p = &c.param[0].mnem; 7797 7798 if (nparams > 7) 7799 return -EINVAL; 7800 7801 memset(&c, 0, sizeof(c)); 7802 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7803 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7804 V_FW_PARAMS_CMD_PFN(pf) | 7805 V_FW_PARAMS_CMD_VFN(vf)); 7806 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7807 7808 for (i = 0; i < nparams; i++) { 7809 *p++ = cpu_to_be32(*params++); 7810 if (rw) 7811 *p = cpu_to_be32(*(val + i)); 7812 p++; 7813 } 7814 7815 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7816 if (ret == 0) 7817 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7818 *val++ = be32_to_cpu(*p); 7819 return ret; 7820 } 7821 7822 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7823 unsigned int vf, unsigned int nparams, const u32 *params, 7824 u32 *val) 7825 { 7826 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7827 } 7828 7829 /** 7830 * t4_set_params_timeout - sets FW or device parameters 7831 * @adap: the adapter 7832 * @mbox: mailbox to use for the FW command 7833 * @pf: the PF 7834 * @vf: the VF 7835 * @nparams: the number of parameters 7836 * @params: the parameter names 7837 * @val: the parameter values 7838 * @timeout: the timeout time 7839 * 7840 * Sets the value of FW or device parameters. Up to 7 parameters can be 7841 * specified at once. 7842 */ 7843 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7844 unsigned int pf, unsigned int vf, 7845 unsigned int nparams, const u32 *params, 7846 const u32 *val, int timeout) 7847 { 7848 struct fw_params_cmd c; 7849 __be32 *p = &c.param[0].mnem; 7850 7851 if (nparams > 7) 7852 return -EINVAL; 7853 7854 memset(&c, 0, sizeof(c)); 7855 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7856 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7857 V_FW_PARAMS_CMD_PFN(pf) | 7858 V_FW_PARAMS_CMD_VFN(vf)); 7859 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7860 7861 while (nparams--) { 7862 *p++ = cpu_to_be32(*params++); 7863 *p++ = cpu_to_be32(*val++); 7864 } 7865 7866 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7867 } 7868 7869 /** 7870 * t4_set_params - sets FW or device parameters 7871 * @adap: the adapter 7872 * @mbox: mailbox to use for the FW command 7873 * @pf: the PF 7874 * @vf: the VF 7875 * @nparams: the number of parameters 7876 * @params: the parameter names 7877 * @val: the parameter values 7878 * 7879 * Sets the value of FW or device parameters. Up to 7 parameters can be 7880 * specified at once. 7881 */ 7882 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7883 unsigned int vf, unsigned int nparams, const u32 *params, 7884 const u32 *val) 7885 { 7886 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7887 FW_CMD_MAX_TIMEOUT); 7888 } 7889 7890 /** 7891 * t4_cfg_pfvf - configure PF/VF resource limits 7892 * @adap: the adapter 7893 * @mbox: mailbox to use for the FW command 7894 * @pf: the PF being configured 7895 * @vf: the VF being configured 7896 * @txq: the max number of egress queues 7897 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7898 * @rxqi: the max number of interrupt-capable ingress queues 7899 * @rxq: the max number of interruptless ingress queues 7900 * @tc: the PCI traffic class 7901 * @vi: the max number of virtual interfaces 7902 * @cmask: the channel access rights mask for the PF/VF 7903 * @pmask: the port access rights mask for the PF/VF 7904 * @nexact: the maximum number of exact MPS filters 7905 * @rcaps: read capabilities 7906 * @wxcaps: write/execute capabilities 7907 * 7908 * Configures resource limits and capabilities for a physical or virtual 7909 * function. 7910 */ 7911 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7912 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7913 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7914 unsigned int vi, unsigned int cmask, unsigned int pmask, 7915 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7916 { 7917 struct fw_pfvf_cmd c; 7918 7919 memset(&c, 0, sizeof(c)); 7920 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7921 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7922 V_FW_PFVF_CMD_VFN(vf)); 7923 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7924 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7925 V_FW_PFVF_CMD_NIQ(rxq)); 7926 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7927 V_FW_PFVF_CMD_PMASK(pmask) | 7928 V_FW_PFVF_CMD_NEQ(txq)); 7929 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7930 V_FW_PFVF_CMD_NVI(vi) | 7931 V_FW_PFVF_CMD_NEXACTF(nexact)); 7932 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7933 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7934 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7935 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7936 } 7937 7938 /** 7939 * t4_alloc_vi_func - allocate a virtual interface 7940 * @adap: the adapter 7941 * @mbox: mailbox to use for the FW command 7942 * @port: physical port associated with the VI 7943 * @pf: the PF owning the VI 7944 * @vf: the VF owning the VI 7945 * @nmac: number of MAC addresses needed (1 to 5) 7946 * @mac: the MAC addresses of the VI 7947 * @rss_size: size of RSS table slice associated with this VI 7948 * @portfunc: which Port Application Function MAC Address is desired 7949 * @idstype: Intrusion Detection Type 7950 * 7951 * Allocates a virtual interface for the given physical port. If @mac is 7952 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7953 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7954 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7955 * stored consecutively so the space needed is @nmac * 6 bytes. 7956 * Returns a negative error number or the non-negative VI id. 7957 */ 7958 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7959 unsigned int port, unsigned int pf, unsigned int vf, 7960 unsigned int nmac, u8 *mac, u16 *rss_size, 7961 uint8_t *vfvld, uint16_t *vin, 7962 unsigned int portfunc, unsigned int idstype) 7963 { 7964 int ret; 7965 struct fw_vi_cmd c; 7966 7967 memset(&c, 0, sizeof(c)); 7968 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7969 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7970 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7971 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7972 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7973 V_FW_VI_CMD_FUNC(portfunc)); 7974 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7975 c.nmac = nmac - 1; 7976 if(!rss_size) 7977 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7978 7979 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7980 if (ret) 7981 return ret; 7982 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7983 7984 if (mac) { 7985 memcpy(mac, c.mac, sizeof(c.mac)); 7986 switch (nmac) { 7987 case 5: 7988 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7989 case 4: 7990 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7991 case 3: 7992 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7993 case 2: 7994 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7995 } 7996 } 7997 if (rss_size) 7998 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7999 if (vfvld) { 8000 *vfvld = adap->params.viid_smt_extn_support ? 8001 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 8002 G_FW_VIID_VIVLD(ret); 8003 } 8004 if (vin) { 8005 *vin = adap->params.viid_smt_extn_support ? 8006 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 8007 G_FW_VIID_VIN(ret); 8008 } 8009 8010 return ret; 8011 } 8012 8013 /** 8014 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 8015 * @adap: the adapter 8016 * @mbox: mailbox to use for the FW command 8017 * @port: physical port associated with the VI 8018 * @pf: the PF owning the VI 8019 * @vf: the VF owning the VI 8020 * @nmac: number of MAC addresses needed (1 to 5) 8021 * @mac: the MAC addresses of the VI 8022 * @rss_size: size of RSS table slice associated with this VI 8023 * 8024 * backwards compatible and convieniance routine to allocate a Virtual 8025 * Interface with a Ethernet Port Application Function and Intrustion 8026 * Detection System disabled. 8027 */ 8028 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 8029 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 8030 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 8031 { 8032 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 8033 vfvld, vin, FW_VI_FUNC_ETH, 0); 8034 } 8035 8036 /** 8037 * t4_free_vi - free a virtual interface 8038 * @adap: the adapter 8039 * @mbox: mailbox to use for the FW command 8040 * @pf: the PF owning the VI 8041 * @vf: the VF owning the VI 8042 * @viid: virtual interface identifiler 8043 * 8044 * Free a previously allocated virtual interface. 8045 */ 8046 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 8047 unsigned int vf, unsigned int viid) 8048 { 8049 struct fw_vi_cmd c; 8050 8051 memset(&c, 0, sizeof(c)); 8052 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 8053 F_FW_CMD_REQUEST | 8054 F_FW_CMD_EXEC | 8055 V_FW_VI_CMD_PFN(pf) | 8056 V_FW_VI_CMD_VFN(vf)); 8057 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 8058 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 8059 8060 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8061 } 8062 8063 /** 8064 * t4_set_rxmode - set Rx properties of a virtual interface 8065 * @adap: the adapter 8066 * @mbox: mailbox to use for the FW command 8067 * @viid: the VI id 8068 * @mtu: the new MTU or -1 8069 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 8070 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 8071 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 8072 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 8073 * @sleep_ok: if true we may sleep while awaiting command completion 8074 * 8075 * Sets Rx properties of a virtual interface. 8076 */ 8077 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 8078 int mtu, int promisc, int all_multi, int bcast, int vlanex, 8079 bool sleep_ok) 8080 { 8081 struct fw_vi_rxmode_cmd c; 8082 8083 /* convert to FW values */ 8084 if (mtu < 0) 8085 mtu = M_FW_VI_RXMODE_CMD_MTU; 8086 if (promisc < 0) 8087 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 8088 if (all_multi < 0) 8089 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 8090 if (bcast < 0) 8091 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 8092 if (vlanex < 0) 8093 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 8094 8095 memset(&c, 0, sizeof(c)); 8096 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 8097 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8098 V_FW_VI_RXMODE_CMD_VIID(viid)); 8099 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 8100 c.mtu_to_vlanexen = 8101 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 8102 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 8103 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 8104 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 8105 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 8106 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8107 } 8108 8109 /** 8110 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support 8111 * @adap: the adapter 8112 * @viid: the VI id 8113 * @mac: the MAC address 8114 * @mask: the mask 8115 * @vni: the VNI id for the tunnel protocol 8116 * @vni_mask: mask for the VNI id 8117 * @dip_hit: to enable DIP match for the MPS entry 8118 * @lookup_type: MAC address for inner (1) or outer (0) header 8119 * @sleep_ok: call is allowed to sleep 8120 * 8121 * Allocates an MPS entry with specified MAC address and VNI value. 8122 * 8123 * Returns a negative error number or the allocated index for this mac. 8124 */ 8125 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 8126 const u8 *addr, const u8 *mask, unsigned int vni, 8127 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 8128 bool sleep_ok) 8129 { 8130 struct fw_vi_mac_cmd c; 8131 struct fw_vi_mac_vni *p = c.u.exact_vni; 8132 int ret = 0; 8133 u32 val; 8134 8135 memset(&c, 0, sizeof(c)); 8136 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8137 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8138 V_FW_VI_MAC_CMD_VIID(viid)); 8139 val = V_FW_CMD_LEN16(1) | 8140 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI); 8141 c.freemacs_to_len16 = cpu_to_be32(val); 8142 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8143 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8144 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8145 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); 8146 8147 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | 8148 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) | 8149 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type)); 8150 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); 8151 8152 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8153 if (ret == 0) 8154 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8155 return ret; 8156 } 8157 8158 /** 8159 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam 8160 * @adap: the adapter 8161 * @viid: the VI id 8162 * @mac: the MAC address 8163 * @mask: the mask 8164 * @idx: index at which to add this entry 8165 * @port_id: the port index 8166 * @lookup_type: MAC address for inner (1) or outer (0) header 8167 * @sleep_ok: call is allowed to sleep 8168 * 8169 * Adds the mac entry at the specified index using raw mac interface. 8170 * 8171 * Returns a negative error number or the allocated index for this mac. 8172 */ 8173 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 8174 const u8 *addr, const u8 *mask, unsigned int idx, 8175 u8 lookup_type, u8 port_id, bool sleep_ok) 8176 { 8177 int ret = 0; 8178 struct fw_vi_mac_cmd c; 8179 struct fw_vi_mac_raw *p = &c.u.raw; 8180 u32 val; 8181 8182 memset(&c, 0, sizeof(c)); 8183 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8184 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8185 V_FW_VI_MAC_CMD_VIID(viid)); 8186 val = V_FW_CMD_LEN16(1) | 8187 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8188 c.freemacs_to_len16 = cpu_to_be32(val); 8189 8190 /* Specify that this is an inner mac address */ 8191 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); 8192 8193 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8194 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8195 V_DATAPORTNUM(port_id)); 8196 /* Lookup mask and port mask */ 8197 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8198 V_DATAPORTNUM(M_DATAPORTNUM)); 8199 8200 /* Copy the address and the mask */ 8201 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8202 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8203 8204 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8205 if (ret == 0) { 8206 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); 8207 if (ret != idx) 8208 ret = -ENOMEM; 8209 } 8210 8211 return ret; 8212 } 8213 8214 /** 8215 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 8216 * @adap: the adapter 8217 * @mbox: mailbox to use for the FW command 8218 * @viid: the VI id 8219 * @free: if true any existing filters for this VI id are first removed 8220 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8221 * @addr: the MAC address(es) 8222 * @idx: where to store the index of each allocated filter 8223 * @hash: pointer to hash address filter bitmap 8224 * @sleep_ok: call is allowed to sleep 8225 * 8226 * Allocates an exact-match filter for each of the supplied addresses and 8227 * sets it to the corresponding address. If @idx is not %NULL it should 8228 * have at least @naddr entries, each of which will be set to the index of 8229 * the filter allocated for the corresponding MAC address. If a filter 8230 * could not be allocated for an address its index is set to 0xffff. 8231 * If @hash is not %NULL addresses that fail to allocate an exact filter 8232 * are hashed and update the hash filter bitmap pointed at by @hash. 8233 * 8234 * Returns a negative error number or the number of filters allocated. 8235 */ 8236 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8237 unsigned int viid, bool free, unsigned int naddr, 8238 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8239 { 8240 int offset, ret = 0; 8241 struct fw_vi_mac_cmd c; 8242 unsigned int nfilters = 0; 8243 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8244 unsigned int rem = naddr; 8245 8246 if (naddr > max_naddr) 8247 return -EINVAL; 8248 8249 for (offset = 0; offset < naddr ; /**/) { 8250 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8251 ? rem 8252 : ARRAY_SIZE(c.u.exact)); 8253 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8254 u.exact[fw_naddr]), 16); 8255 struct fw_vi_mac_exact *p; 8256 int i; 8257 8258 memset(&c, 0, sizeof(c)); 8259 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8260 F_FW_CMD_REQUEST | 8261 F_FW_CMD_WRITE | 8262 V_FW_CMD_EXEC(free) | 8263 V_FW_VI_MAC_CMD_VIID(viid)); 8264 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8265 V_FW_CMD_LEN16(len16)); 8266 8267 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8268 p->valid_to_idx = 8269 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8270 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8271 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8272 } 8273 8274 /* 8275 * It's okay if we run out of space in our MAC address arena. 8276 * Some of the addresses we submit may get stored so we need 8277 * to run through the reply to see what the results were ... 8278 */ 8279 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8280 if (ret && ret != -FW_ENOMEM) 8281 break; 8282 8283 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8284 u16 index = G_FW_VI_MAC_CMD_IDX( 8285 be16_to_cpu(p->valid_to_idx)); 8286 8287 if (idx) 8288 idx[offset+i] = (index >= max_naddr 8289 ? 0xffff 8290 : index); 8291 if (index < max_naddr) 8292 nfilters++; 8293 else if (hash) 8294 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8295 } 8296 8297 free = false; 8298 offset += fw_naddr; 8299 rem -= fw_naddr; 8300 } 8301 8302 if (ret == 0 || ret == -FW_ENOMEM) 8303 ret = nfilters; 8304 return ret; 8305 } 8306 8307 /** 8308 * t4_free_encap_mac_filt - frees MPS entry at given index 8309 * @adap: the adapter 8310 * @viid: the VI id 8311 * @idx: index of MPS entry to be freed 8312 * @sleep_ok: call is allowed to sleep 8313 * 8314 * Frees the MPS entry at supplied index 8315 * 8316 * Returns a negative error number or zero on success 8317 */ 8318 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 8319 int idx, bool sleep_ok) 8320 { 8321 struct fw_vi_mac_exact *p; 8322 struct fw_vi_mac_cmd c; 8323 u8 addr[] = {0,0,0,0,0,0}; 8324 int ret = 0; 8325 u32 exact; 8326 8327 memset(&c, 0, sizeof(c)); 8328 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8329 F_FW_CMD_REQUEST | 8330 F_FW_CMD_WRITE | 8331 V_FW_CMD_EXEC(0) | 8332 V_FW_VI_MAC_CMD_VIID(viid)); 8333 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC); 8334 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8335 exact | 8336 V_FW_CMD_LEN16(1)); 8337 p = c.u.exact; 8338 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8339 V_FW_VI_MAC_CMD_IDX(idx)); 8340 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8341 8342 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8343 return ret; 8344 } 8345 8346 /** 8347 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam 8348 * @adap: the adapter 8349 * @viid: the VI id 8350 * @addr: the MAC address 8351 * @mask: the mask 8352 * @idx: index of the entry in mps tcam 8353 * @lookup_type: MAC address for inner (1) or outer (0) header 8354 * @port_id: the port index 8355 * @sleep_ok: call is allowed to sleep 8356 * 8357 * Removes the mac entry at the specified index using raw mac interface. 8358 * 8359 * Returns a negative error number on failure. 8360 */ 8361 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 8362 const u8 *addr, const u8 *mask, unsigned int idx, 8363 u8 lookup_type, u8 port_id, bool sleep_ok) 8364 { 8365 struct fw_vi_mac_cmd c; 8366 struct fw_vi_mac_raw *p = &c.u.raw; 8367 u32 raw; 8368 8369 memset(&c, 0, sizeof(c)); 8370 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8371 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8372 V_FW_CMD_EXEC(0) | 8373 V_FW_VI_MAC_CMD_VIID(viid)); 8374 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8375 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8376 raw | 8377 V_FW_CMD_LEN16(1)); 8378 8379 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | 8380 FW_VI_MAC_ID_BASED_FREE); 8381 8382 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8383 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8384 V_DATAPORTNUM(port_id)); 8385 /* Lookup mask and port mask */ 8386 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8387 V_DATAPORTNUM(M_DATAPORTNUM)); 8388 8389 /* Copy the address and the mask */ 8390 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8391 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8392 8393 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8394 } 8395 8396 /** 8397 * t4_free_mac_filt - frees exact-match filters of given MAC addresses 8398 * @adap: the adapter 8399 * @mbox: mailbox to use for the FW command 8400 * @viid: the VI id 8401 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8402 * @addr: the MAC address(es) 8403 * @sleep_ok: call is allowed to sleep 8404 * 8405 * Frees the exact-match filter for each of the supplied addresses 8406 * 8407 * Returns a negative error number or the number of filters freed. 8408 */ 8409 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 8410 unsigned int viid, unsigned int naddr, 8411 const u8 **addr, bool sleep_ok) 8412 { 8413 int offset, ret = 0; 8414 struct fw_vi_mac_cmd c; 8415 unsigned int nfilters = 0; 8416 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8417 unsigned int rem = naddr; 8418 8419 if (naddr > max_naddr) 8420 return -EINVAL; 8421 8422 for (offset = 0; offset < (int)naddr ; /**/) { 8423 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8424 ? rem 8425 : ARRAY_SIZE(c.u.exact)); 8426 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8427 u.exact[fw_naddr]), 16); 8428 struct fw_vi_mac_exact *p; 8429 int i; 8430 8431 memset(&c, 0, sizeof(c)); 8432 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8433 F_FW_CMD_REQUEST | 8434 F_FW_CMD_WRITE | 8435 V_FW_CMD_EXEC(0) | 8436 V_FW_VI_MAC_CMD_VIID(viid)); 8437 c.freemacs_to_len16 = 8438 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8439 V_FW_CMD_LEN16(len16)); 8440 8441 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { 8442 p->valid_to_idx = cpu_to_be16( 8443 F_FW_VI_MAC_CMD_VALID | 8444 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 8445 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8446 } 8447 8448 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8449 if (ret) 8450 break; 8451 8452 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8453 u16 index = G_FW_VI_MAC_CMD_IDX( 8454 be16_to_cpu(p->valid_to_idx)); 8455 8456 if (index < max_naddr) 8457 nfilters++; 8458 } 8459 8460 offset += fw_naddr; 8461 rem -= fw_naddr; 8462 } 8463 8464 if (ret == 0) 8465 ret = nfilters; 8466 return ret; 8467 } 8468 8469 /** 8470 * t4_change_mac - modifies the exact-match filter for a MAC address 8471 * @adap: the adapter 8472 * @mbox: mailbox to use for the FW command 8473 * @viid: the VI id 8474 * @idx: index of existing filter for old value of MAC address, or -1 8475 * @addr: the new MAC address value 8476 * @persist: whether a new MAC allocation should be persistent 8477 * @smt_idx: add MAC to SMT and return its index, or NULL 8478 * 8479 * Modifies an exact-match filter and sets it to the new MAC address if 8480 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8481 * latter case the address is added persistently if @persist is %true. 8482 * 8483 * Note that in general it is not possible to modify the value of a given 8484 * filter so the generic way to modify an address filter is to free the one 8485 * being used by the old address value and allocate a new filter for the 8486 * new address value. 8487 * 8488 * Returns a negative error number or the index of the filter with the new 8489 * MAC value. Note that this index may differ from @idx. 8490 */ 8491 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8492 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8493 { 8494 int ret, mode; 8495 struct fw_vi_mac_cmd c; 8496 struct fw_vi_mac_exact *p = c.u.exact; 8497 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8498 8499 if (idx < 0) /* new allocation */ 8500 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8501 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8502 8503 memset(&c, 0, sizeof(c)); 8504 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8505 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8506 V_FW_VI_MAC_CMD_VIID(viid)); 8507 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8508 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8509 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8510 V_FW_VI_MAC_CMD_IDX(idx)); 8511 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8512 8513 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8514 if (ret == 0) { 8515 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8516 if (ret >= max_mac_addr) 8517 ret = -ENOMEM; 8518 if (smt_idx) { 8519 if (adap->params.viid_smt_extn_support) 8520 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8521 else { 8522 if (chip_id(adap) <= CHELSIO_T5) 8523 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8524 else 8525 *smt_idx = viid & M_FW_VIID_VIN; 8526 } 8527 } 8528 } 8529 return ret; 8530 } 8531 8532 /** 8533 * t4_set_addr_hash - program the MAC inexact-match hash filter 8534 * @adap: the adapter 8535 * @mbox: mailbox to use for the FW command 8536 * @viid: the VI id 8537 * @ucast: whether the hash filter should also match unicast addresses 8538 * @vec: the value to be written to the hash filter 8539 * @sleep_ok: call is allowed to sleep 8540 * 8541 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8542 */ 8543 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8544 bool ucast, u64 vec, bool sleep_ok) 8545 { 8546 struct fw_vi_mac_cmd c; 8547 u32 val; 8548 8549 memset(&c, 0, sizeof(c)); 8550 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8551 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8552 V_FW_VI_ENABLE_CMD_VIID(viid)); 8553 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8554 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8555 c.freemacs_to_len16 = cpu_to_be32(val); 8556 c.u.hash.hashvec = cpu_to_be64(vec); 8557 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8558 } 8559 8560 /** 8561 * t4_enable_vi_params - enable/disable a virtual interface 8562 * @adap: the adapter 8563 * @mbox: mailbox to use for the FW command 8564 * @viid: the VI id 8565 * @rx_en: 1=enable Rx, 0=disable Rx 8566 * @tx_en: 1=enable Tx, 0=disable Tx 8567 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8568 * 8569 * Enables/disables a virtual interface. Note that setting DCB Enable 8570 * only makes sense when enabling a Virtual Interface ... 8571 */ 8572 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8573 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8574 { 8575 struct fw_vi_enable_cmd c; 8576 8577 memset(&c, 0, sizeof(c)); 8578 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8579 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8580 V_FW_VI_ENABLE_CMD_VIID(viid)); 8581 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8582 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8583 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8584 FW_LEN16(c)); 8585 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8586 } 8587 8588 /** 8589 * t4_enable_vi - enable/disable a virtual interface 8590 * @adap: the adapter 8591 * @mbox: mailbox to use for the FW command 8592 * @viid: the VI id 8593 * @rx_en: 1=enable Rx, 0=disable Rx 8594 * @tx_en: 1=enable Tx, 0=disable Tx 8595 * 8596 * Enables/disables a virtual interface. Note that setting DCB Enable 8597 * only makes sense when enabling a Virtual Interface ... 8598 */ 8599 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8600 bool rx_en, bool tx_en) 8601 { 8602 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8603 } 8604 8605 /** 8606 * t4_identify_port - identify a VI's port by blinking its LED 8607 * @adap: the adapter 8608 * @mbox: mailbox to use for the FW command 8609 * @viid: the VI id 8610 * @nblinks: how many times to blink LED at 2.5 Hz 8611 * 8612 * Identifies a VI's port by blinking its LED. 8613 */ 8614 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8615 unsigned int nblinks) 8616 { 8617 struct fw_vi_enable_cmd c; 8618 8619 memset(&c, 0, sizeof(c)); 8620 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8621 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8622 V_FW_VI_ENABLE_CMD_VIID(viid)); 8623 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8624 c.blinkdur = cpu_to_be16(nblinks); 8625 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8626 } 8627 8628 /** 8629 * t4_iq_stop - stop an ingress queue and its FLs 8630 * @adap: the adapter 8631 * @mbox: mailbox to use for the FW command 8632 * @pf: the PF owning the queues 8633 * @vf: the VF owning the queues 8634 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8635 * @iqid: ingress queue id 8636 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8637 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8638 * 8639 * Stops an ingress queue and its associated FLs, if any. This causes 8640 * any current or future data/messages destined for these queues to be 8641 * tossed. 8642 */ 8643 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8644 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8645 unsigned int fl0id, unsigned int fl1id) 8646 { 8647 struct fw_iq_cmd c; 8648 8649 memset(&c, 0, sizeof(c)); 8650 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8651 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8652 V_FW_IQ_CMD_VFN(vf)); 8653 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8654 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8655 c.iqid = cpu_to_be16(iqid); 8656 c.fl0id = cpu_to_be16(fl0id); 8657 c.fl1id = cpu_to_be16(fl1id); 8658 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8659 } 8660 8661 /** 8662 * t4_iq_free - free an ingress queue and its FLs 8663 * @adap: the adapter 8664 * @mbox: mailbox to use for the FW command 8665 * @pf: the PF owning the queues 8666 * @vf: the VF owning the queues 8667 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8668 * @iqid: ingress queue id 8669 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8670 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8671 * 8672 * Frees an ingress queue and its associated FLs, if any. 8673 */ 8674 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8675 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8676 unsigned int fl0id, unsigned int fl1id) 8677 { 8678 struct fw_iq_cmd c; 8679 8680 memset(&c, 0, sizeof(c)); 8681 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8682 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8683 V_FW_IQ_CMD_VFN(vf)); 8684 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8685 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8686 c.iqid = cpu_to_be16(iqid); 8687 c.fl0id = cpu_to_be16(fl0id); 8688 c.fl1id = cpu_to_be16(fl1id); 8689 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8690 } 8691 8692 /** 8693 * t4_eth_eq_stop - stop an Ethernet egress queue 8694 * @adap: the adapter 8695 * @mbox: mailbox to use for the FW command 8696 * @pf: the PF owning the queues 8697 * @vf: the VF owning the queues 8698 * @eqid: egress queue id 8699 * 8700 * Stops an Ethernet egress queue. The queue can be reinitialized or 8701 * freed but is not otherwise functional after this call. 8702 */ 8703 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8704 unsigned int vf, unsigned int eqid) 8705 { 8706 struct fw_eq_eth_cmd c; 8707 8708 memset(&c, 0, sizeof(c)); 8709 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8710 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8711 V_FW_EQ_ETH_CMD_PFN(pf) | 8712 V_FW_EQ_ETH_CMD_VFN(vf)); 8713 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c)); 8714 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8715 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8716 } 8717 8718 /** 8719 * t4_eth_eq_free - free an Ethernet egress queue 8720 * @adap: the adapter 8721 * @mbox: mailbox to use for the FW command 8722 * @pf: the PF owning the queue 8723 * @vf: the VF owning the queue 8724 * @eqid: egress queue id 8725 * 8726 * Frees an Ethernet egress queue. 8727 */ 8728 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8729 unsigned int vf, unsigned int eqid) 8730 { 8731 struct fw_eq_eth_cmd c; 8732 8733 memset(&c, 0, sizeof(c)); 8734 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8735 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8736 V_FW_EQ_ETH_CMD_PFN(pf) | 8737 V_FW_EQ_ETH_CMD_VFN(vf)); 8738 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8739 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8740 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8741 } 8742 8743 /** 8744 * t4_ctrl_eq_free - free a control egress queue 8745 * @adap: the adapter 8746 * @mbox: mailbox to use for the FW command 8747 * @pf: the PF owning the queue 8748 * @vf: the VF owning the queue 8749 * @eqid: egress queue id 8750 * 8751 * Frees a control egress queue. 8752 */ 8753 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8754 unsigned int vf, unsigned int eqid) 8755 { 8756 struct fw_eq_ctrl_cmd c; 8757 8758 memset(&c, 0, sizeof(c)); 8759 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8760 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8761 V_FW_EQ_CTRL_CMD_PFN(pf) | 8762 V_FW_EQ_CTRL_CMD_VFN(vf)); 8763 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8764 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8765 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8766 } 8767 8768 /** 8769 * t4_ofld_eq_free - free an offload egress queue 8770 * @adap: the adapter 8771 * @mbox: mailbox to use for the FW command 8772 * @pf: the PF owning the queue 8773 * @vf: the VF owning the queue 8774 * @eqid: egress queue id 8775 * 8776 * Frees a control egress queue. 8777 */ 8778 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8779 unsigned int vf, unsigned int eqid) 8780 { 8781 struct fw_eq_ofld_cmd c; 8782 8783 memset(&c, 0, sizeof(c)); 8784 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8785 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8786 V_FW_EQ_OFLD_CMD_PFN(pf) | 8787 V_FW_EQ_OFLD_CMD_VFN(vf)); 8788 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8789 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8790 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8791 } 8792 8793 /** 8794 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8795 * @link_down_rc: Link Down Reason Code 8796 * 8797 * Returns a string representation of the Link Down Reason Code. 8798 */ 8799 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8800 { 8801 static const char *reason[] = { 8802 "Link Down", 8803 "Remote Fault", 8804 "Auto-negotiation Failure", 8805 "Reserved3", 8806 "Insufficient Airflow", 8807 "Unable To Determine Reason", 8808 "No RX Signal Detected", 8809 "Reserved7", 8810 }; 8811 8812 if (link_down_rc >= ARRAY_SIZE(reason)) 8813 return "Bad Reason Code"; 8814 8815 return reason[link_down_rc]; 8816 } 8817 8818 /* 8819 * Return the highest speed set in the port capabilities, in Mb/s. 8820 */ 8821 unsigned int fwcap_to_speed(uint32_t caps) 8822 { 8823 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8824 do { \ 8825 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8826 return __speed; \ 8827 } while (0) 8828 8829 TEST_SPEED_RETURN(400G, 400000); 8830 TEST_SPEED_RETURN(200G, 200000); 8831 TEST_SPEED_RETURN(100G, 100000); 8832 TEST_SPEED_RETURN(50G, 50000); 8833 TEST_SPEED_RETURN(40G, 40000); 8834 TEST_SPEED_RETURN(25G, 25000); 8835 TEST_SPEED_RETURN(10G, 10000); 8836 TEST_SPEED_RETURN(1G, 1000); 8837 TEST_SPEED_RETURN(100M, 100); 8838 8839 #undef TEST_SPEED_RETURN 8840 8841 return 0; 8842 } 8843 8844 /* 8845 * Return the port capabilities bit for the given speed, which is in Mb/s. 8846 */ 8847 uint32_t speed_to_fwcap(unsigned int speed) 8848 { 8849 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8850 do { \ 8851 if (speed == __speed) \ 8852 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8853 } while (0) 8854 8855 TEST_SPEED_RETURN(400G, 400000); 8856 TEST_SPEED_RETURN(200G, 200000); 8857 TEST_SPEED_RETURN(100G, 100000); 8858 TEST_SPEED_RETURN(50G, 50000); 8859 TEST_SPEED_RETURN(40G, 40000); 8860 TEST_SPEED_RETURN(25G, 25000); 8861 TEST_SPEED_RETURN(10G, 10000); 8862 TEST_SPEED_RETURN(1G, 1000); 8863 TEST_SPEED_RETURN(100M, 100); 8864 8865 #undef TEST_SPEED_RETURN 8866 8867 return 0; 8868 } 8869 8870 /* 8871 * Return the port capabilities bit for the highest speed in the capabilities. 8872 */ 8873 uint32_t fwcap_top_speed(uint32_t caps) 8874 { 8875 #define TEST_SPEED_RETURN(__caps_speed) \ 8876 do { \ 8877 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8878 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8879 } while (0) 8880 8881 TEST_SPEED_RETURN(400G); 8882 TEST_SPEED_RETURN(200G); 8883 TEST_SPEED_RETURN(100G); 8884 TEST_SPEED_RETURN(50G); 8885 TEST_SPEED_RETURN(40G); 8886 TEST_SPEED_RETURN(25G); 8887 TEST_SPEED_RETURN(10G); 8888 TEST_SPEED_RETURN(1G); 8889 TEST_SPEED_RETURN(100M); 8890 8891 #undef TEST_SPEED_RETURN 8892 8893 return 0; 8894 } 8895 8896 /** 8897 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8898 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8899 * 8900 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8901 * 32-bit Port Capabilities value. 8902 */ 8903 static uint32_t lstatus_to_fwcap(u32 lstatus) 8904 { 8905 uint32_t linkattr = 0; 8906 8907 /* 8908 * Unfortunately the format of the Link Status in the old 8909 * 16-bit Port Information message isn't the same as the 8910 * 16-bit Port Capabilities bitfield used everywhere else ... 8911 */ 8912 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8913 linkattr |= FW_PORT_CAP32_FC_RX; 8914 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8915 linkattr |= FW_PORT_CAP32_FC_TX; 8916 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8917 linkattr |= FW_PORT_CAP32_SPEED_100M; 8918 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8919 linkattr |= FW_PORT_CAP32_SPEED_1G; 8920 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8921 linkattr |= FW_PORT_CAP32_SPEED_10G; 8922 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8923 linkattr |= FW_PORT_CAP32_SPEED_25G; 8924 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8925 linkattr |= FW_PORT_CAP32_SPEED_40G; 8926 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8927 linkattr |= FW_PORT_CAP32_SPEED_100G; 8928 8929 return linkattr; 8930 } 8931 8932 /* 8933 * Updates all fields owned by the common code in port_info and link_config 8934 * based on information provided by the firmware. Does not touch any 8935 * requested_* field. 8936 */ 8937 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8938 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8939 { 8940 struct link_config old_lc, *lc = &pi->link_cfg; 8941 unsigned char fc; 8942 u32 stat, linkattr; 8943 int old_ptype, old_mtype; 8944 8945 old_ptype = pi->port_type; 8946 old_mtype = pi->mod_type; 8947 old_lc = *lc; 8948 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8949 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8950 8951 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8952 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8953 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8954 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8955 8956 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8957 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8958 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8959 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8960 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8961 8962 linkattr = lstatus_to_fwcap(stat); 8963 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8964 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8965 8966 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8967 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8968 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8969 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8970 8971 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); 8972 lc->acaps = be32_to_cpu(p->u.info32.acaps32); 8973 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); 8974 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8975 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8976 8977 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8978 } else { 8979 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8980 return; 8981 } 8982 8983 lc->speed = fwcap_to_speed(linkattr); 8984 lc->fec = fwcap_to_fec(linkattr, true); 8985 8986 fc = 0; 8987 if (linkattr & FW_PORT_CAP32_FC_RX) 8988 fc |= PAUSE_RX; 8989 if (linkattr & FW_PORT_CAP32_FC_TX) 8990 fc |= PAUSE_TX; 8991 lc->fc = fc; 8992 8993 if (mod_changed != NULL) 8994 *mod_changed = false; 8995 if (link_changed != NULL) 8996 *link_changed = false; 8997 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 8998 old_lc.pcaps != lc->pcaps) { 8999 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) 9000 lc->fec_hint = fwcap_to_fec(lc->acaps, true); 9001 if (mod_changed != NULL) 9002 *mod_changed = true; 9003 } 9004 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 9005 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 9006 if (link_changed != NULL) 9007 *link_changed = true; 9008 } 9009 } 9010 9011 /** 9012 * t4_update_port_info - retrieve and update port information if changed 9013 * @pi: the port_info 9014 * 9015 * We issue a Get Port Information Command to the Firmware and, if 9016 * successful, we check to see if anything is different from what we 9017 * last recorded and update things accordingly. 9018 */ 9019 int t4_update_port_info(struct port_info *pi) 9020 { 9021 struct adapter *sc = pi->adapter; 9022 struct fw_port_cmd cmd; 9023 enum fw_port_action action; 9024 int ret; 9025 9026 memset(&cmd, 0, sizeof(cmd)); 9027 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 9028 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9029 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 9030 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 9031 FW_PORT_ACTION_GET_PORT_INFO; 9032 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 9033 FW_LEN16(cmd)); 9034 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 9035 if (ret) 9036 return ret; 9037 9038 handle_port_info(pi, &cmd, action, NULL, NULL); 9039 return 0; 9040 } 9041 9042 /** 9043 * t4_handle_fw_rpl - process a FW reply message 9044 * @adap: the adapter 9045 * @rpl: start of the FW message 9046 * 9047 * Processes a FW message, such as link state change messages. 9048 */ 9049 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 9050 { 9051 u8 opcode = *(const u8 *)rpl; 9052 const struct fw_port_cmd *p = (const void *)rpl; 9053 enum fw_port_action action = 9054 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 9055 bool mod_changed, link_changed; 9056 9057 if (opcode == FW_PORT_CMD && 9058 (action == FW_PORT_ACTION_GET_PORT_INFO || 9059 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 9060 /* link/module state change message */ 9061 int i; 9062 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 9063 struct port_info *pi = NULL; 9064 struct link_config *lc; 9065 9066 for_each_port(adap, i) { 9067 pi = adap2pinfo(adap, i); 9068 if (pi->tx_chan == chan) 9069 break; 9070 } 9071 9072 lc = &pi->link_cfg; 9073 PORT_LOCK(pi); 9074 handle_port_info(pi, p, action, &mod_changed, &link_changed); 9075 PORT_UNLOCK(pi); 9076 if (mod_changed) 9077 t4_os_portmod_changed(pi); 9078 if (link_changed) { 9079 PORT_LOCK(pi); 9080 t4_os_link_changed(pi); 9081 PORT_UNLOCK(pi); 9082 } 9083 } else { 9084 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 9085 return -EINVAL; 9086 } 9087 return 0; 9088 } 9089 9090 /** 9091 * get_pci_mode - determine a card's PCI mode 9092 * @adapter: the adapter 9093 * @p: where to store the PCI settings 9094 * 9095 * Determines a card's PCI mode and associated parameters, such as speed 9096 * and width. 9097 */ 9098 static void get_pci_mode(struct adapter *adapter, 9099 struct pci_params *p) 9100 { 9101 u16 val; 9102 u32 pcie_cap; 9103 9104 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9105 if (pcie_cap) { 9106 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 9107 p->speed = val & PCI_EXP_LNKSTA_CLS; 9108 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 9109 } 9110 } 9111 9112 struct flash_desc { 9113 u32 vendor_and_model_id; 9114 u32 size_mb; 9115 }; 9116 9117 int t4_get_flash_params(struct adapter *adapter) 9118 { 9119 /* 9120 * Table for non-standard supported Flash parts. Note, all Flash 9121 * parts must have 64KB sectors. 9122 */ 9123 static struct flash_desc supported_flash[] = { 9124 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 9125 }; 9126 9127 int ret; 9128 u32 flashid = 0; 9129 unsigned int part, manufacturer; 9130 unsigned int density, size = 0; 9131 9132 9133 /* 9134 * Issue a Read ID Command to the Flash part. We decode supported 9135 * Flash parts and their sizes from this. There's a newer Query 9136 * Command which can retrieve detailed geometry information but many 9137 * Flash parts don't support it. 9138 */ 9139 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 9140 if (!ret) 9141 ret = sf1_read(adapter, 3, 0, 1, &flashid); 9142 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 9143 if (ret < 0) 9144 return ret; 9145 9146 /* 9147 * Check to see if it's one of our non-standard supported Flash parts. 9148 */ 9149 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 9150 if (supported_flash[part].vendor_and_model_id == flashid) { 9151 adapter->params.sf_size = 9152 supported_flash[part].size_mb; 9153 adapter->params.sf_nsec = 9154 adapter->params.sf_size / SF_SEC_SIZE; 9155 goto found; 9156 } 9157 9158 /* 9159 * Decode Flash part size. The code below looks repetative with 9160 * common encodings, but that's not guaranteed in the JEDEC 9161 * specification for the Read JADEC ID command. The only thing that 9162 * we're guaranteed by the JADEC specification is where the 9163 * Manufacturer ID is in the returned result. After that each 9164 * Manufacturer ~could~ encode things completely differently. 9165 * Note, all Flash parts must have 64KB sectors. 9166 */ 9167 manufacturer = flashid & 0xff; 9168 switch (manufacturer) { 9169 case 0x20: /* Micron/Numonix */ 9170 /* 9171 * This Density -> Size decoding table is taken from Micron 9172 * Data Sheets. 9173 */ 9174 density = (flashid >> 16) & 0xff; 9175 switch (density) { 9176 case 0x14: size = 1 << 20; break; /* 1MB */ 9177 case 0x15: size = 1 << 21; break; /* 2MB */ 9178 case 0x16: size = 1 << 22; break; /* 4MB */ 9179 case 0x17: size = 1 << 23; break; /* 8MB */ 9180 case 0x18: size = 1 << 24; break; /* 16MB */ 9181 case 0x19: size = 1 << 25; break; /* 32MB */ 9182 case 0x20: size = 1 << 26; break; /* 64MB */ 9183 case 0x21: size = 1 << 27; break; /* 128MB */ 9184 case 0x22: size = 1 << 28; break; /* 256MB */ 9185 } 9186 break; 9187 9188 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 9189 /* 9190 * This Density -> Size decoding table is taken from ISSI 9191 * Data Sheets. 9192 */ 9193 density = (flashid >> 16) & 0xff; 9194 switch (density) { 9195 case 0x16: size = 1 << 25; break; /* 32MB */ 9196 case 0x17: size = 1 << 26; break; /* 64MB */ 9197 } 9198 break; 9199 9200 case 0xc2: /* Macronix */ 9201 /* 9202 * This Density -> Size decoding table is taken from Macronix 9203 * Data Sheets. 9204 */ 9205 density = (flashid >> 16) & 0xff; 9206 switch (density) { 9207 case 0x17: size = 1 << 23; break; /* 8MB */ 9208 case 0x18: size = 1 << 24; break; /* 16MB */ 9209 } 9210 break; 9211 9212 case 0xef: /* Winbond */ 9213 /* 9214 * This Density -> Size decoding table is taken from Winbond 9215 * Data Sheets. 9216 */ 9217 density = (flashid >> 16) & 0xff; 9218 switch (density) { 9219 case 0x17: size = 1 << 23; break; /* 8MB */ 9220 case 0x18: size = 1 << 24; break; /* 16MB */ 9221 } 9222 break; 9223 } 9224 9225 /* If we didn't recognize the FLASH part, that's no real issue: the 9226 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 9227 * use a FLASH part which is at least 4MB in size and has 64KB 9228 * sectors. The unrecognized FLASH part is likely to be much larger 9229 * than 4MB, but that's all we really need. 9230 */ 9231 if (size == 0) { 9232 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 9233 size = 1 << 22; 9234 } 9235 9236 /* 9237 * Store decoded Flash size and fall through into vetting code. 9238 */ 9239 adapter->params.sf_size = size; 9240 adapter->params.sf_nsec = size / SF_SEC_SIZE; 9241 9242 found: 9243 /* 9244 * We should ~probably~ reject adapters with FLASHes which are too 9245 * small but we have some legacy FPGAs with small FLASHes that we'd 9246 * still like to use. So instead we emit a scary message ... 9247 */ 9248 if (adapter->params.sf_size < FLASH_MIN_SIZE) 9249 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 9250 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 9251 9252 return 0; 9253 } 9254 9255 static void set_pcie_completion_timeout(struct adapter *adapter, 9256 u8 range) 9257 { 9258 u16 val; 9259 u32 pcie_cap; 9260 9261 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9262 if (pcie_cap) { 9263 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 9264 val &= 0xfff0; 9265 val |= range ; 9266 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 9267 } 9268 } 9269 9270 const struct chip_params *t4_get_chip_params(int chipid) 9271 { 9272 static const struct chip_params chip_params[] = { 9273 { 9274 /* T4 */ 9275 .nchan = NCHAN, 9276 .pm_stats_cnt = PM_NSTATS, 9277 .cng_ch_bits_log = 2, 9278 .nsched_cls = 15, 9279 .cim_num_obq = CIM_NUM_OBQ, 9280 .filter_opt_len = FILTER_OPT_LEN, 9281 .mps_rplc_size = 128, 9282 .vfcount = 128, 9283 .sge_fl_db = F_DBPRIO, 9284 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 9285 .rss_nentries = RSS_NENTRIES, 9286 }, 9287 { 9288 /* T5 */ 9289 .nchan = NCHAN, 9290 .pm_stats_cnt = PM_NSTATS, 9291 .cng_ch_bits_log = 2, 9292 .nsched_cls = 16, 9293 .cim_num_obq = CIM_NUM_OBQ_T5, 9294 .filter_opt_len = T5_FILTER_OPT_LEN, 9295 .mps_rplc_size = 128, 9296 .vfcount = 128, 9297 .sge_fl_db = F_DBPRIO | F_DBTYPE, 9298 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9299 .rss_nentries = RSS_NENTRIES, 9300 }, 9301 { 9302 /* T6 */ 9303 .nchan = T6_NCHAN, 9304 .pm_stats_cnt = T6_PM_NSTATS, 9305 .cng_ch_bits_log = 3, 9306 .nsched_cls = 16, 9307 .cim_num_obq = CIM_NUM_OBQ_T5, 9308 .filter_opt_len = T5_FILTER_OPT_LEN, 9309 .mps_rplc_size = 256, 9310 .vfcount = 256, 9311 .sge_fl_db = 0, 9312 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9313 .rss_nentries = T6_RSS_NENTRIES, 9314 }, 9315 }; 9316 9317 chipid -= CHELSIO_T4; 9318 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 9319 return NULL; 9320 9321 return &chip_params[chipid]; 9322 } 9323 9324 /** 9325 * t4_prep_adapter - prepare SW and HW for operation 9326 * @adapter: the adapter 9327 * @buf: temporary space of at least VPD_LEN size provided by the caller. 9328 * 9329 * Initialize adapter SW state for the various HW modules, set initial 9330 * values for some adapter tunables, take PHYs out of reset, and 9331 * initialize the MDIO interface. 9332 */ 9333 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 9334 { 9335 int ret; 9336 uint16_t device_id; 9337 uint32_t pl_rev; 9338 9339 get_pci_mode(adapter, &adapter->params.pci); 9340 9341 pl_rev = t4_read_reg(adapter, A_PL_REV); 9342 adapter->params.chipid = G_CHIPID(pl_rev); 9343 adapter->params.rev = G_REV(pl_rev); 9344 if (adapter->params.chipid == 0) { 9345 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 9346 adapter->params.chipid = CHELSIO_T4; 9347 9348 /* T4A1 chip is not supported */ 9349 if (adapter->params.rev == 1) { 9350 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 9351 return -EINVAL; 9352 } 9353 } 9354 9355 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 9356 if (adapter->chip_params == NULL) 9357 return -EINVAL; 9358 9359 adapter->params.pci.vpd_cap_addr = 9360 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 9361 9362 ret = t4_get_flash_params(adapter); 9363 if (ret < 0) 9364 return ret; 9365 9366 /* Cards with real ASICs have the chipid in the PCIe device id */ 9367 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 9368 if (device_id >> 12 == chip_id(adapter)) 9369 adapter->params.cim_la_size = CIMLA_SIZE; 9370 else { 9371 /* FPGA */ 9372 adapter->params.fpga = 1; 9373 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 9374 } 9375 9376 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 9377 if (ret < 0) 9378 return ret; 9379 9380 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 9381 9382 /* 9383 * Default port and clock for debugging in case we can't reach FW. 9384 */ 9385 adapter->params.nports = 1; 9386 adapter->params.portvec = 1; 9387 adapter->params.vpd.cclk = 50000; 9388 9389 /* Set pci completion timeout value to 4 seconds. */ 9390 set_pcie_completion_timeout(adapter, 0xd); 9391 return 0; 9392 } 9393 9394 /** 9395 * t4_shutdown_adapter - shut down adapter, host & wire 9396 * @adapter: the adapter 9397 * 9398 * Perform an emergency shutdown of the adapter and stop it from 9399 * continuing any further communication on the ports or DMA to the 9400 * host. This is typically used when the adapter and/or firmware 9401 * have crashed and we want to prevent any further accidental 9402 * communication with the rest of the world. This will also force 9403 * the port Link Status to go down -- if register writes work -- 9404 * which should help our peers figure out that we're down. 9405 */ 9406 int t4_shutdown_adapter(struct adapter *adapter) 9407 { 9408 int port; 9409 9410 t4_intr_disable(adapter); 9411 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 9412 for_each_port(adapter, port) { 9413 u32 a_port_cfg = is_t4(adapter) ? 9414 PORT_REG(port, A_XGMAC_PORT_CFG) : 9415 T5_PORT_REG(port, A_MAC_PORT_CFG); 9416 9417 t4_write_reg(adapter, a_port_cfg, 9418 t4_read_reg(adapter, a_port_cfg) 9419 & ~V_SIGNAL_DET(1)); 9420 } 9421 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9422 9423 return 0; 9424 } 9425 9426 /** 9427 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9428 * @adapter: the adapter 9429 * @qid: the Queue ID 9430 * @qtype: the Ingress or Egress type for @qid 9431 * @user: true if this request is for a user mode queue 9432 * @pbar2_qoffset: BAR2 Queue Offset 9433 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9434 * 9435 * Returns the BAR2 SGE Queue Registers information associated with the 9436 * indicated Absolute Queue ID. These are passed back in return value 9437 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9438 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9439 * 9440 * This may return an error which indicates that BAR2 SGE Queue 9441 * registers aren't available. If an error is not returned, then the 9442 * following values are returned: 9443 * 9444 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9445 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9446 * 9447 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9448 * require the "Inferred Queue ID" ability may be used. E.g. the 9449 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9450 * then these "Inferred Queue ID" register may not be used. 9451 */ 9452 int t4_bar2_sge_qregs(struct adapter *adapter, 9453 unsigned int qid, 9454 enum t4_bar2_qtype qtype, 9455 int user, 9456 u64 *pbar2_qoffset, 9457 unsigned int *pbar2_qid) 9458 { 9459 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9460 u64 bar2_page_offset, bar2_qoffset; 9461 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9462 9463 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9464 * mode queues. 9465 */ 9466 if (!user && is_t4(adapter)) 9467 return -EINVAL; 9468 9469 /* Get our SGE Page Size parameters. 9470 */ 9471 page_shift = adapter->params.sge.page_shift; 9472 page_size = 1 << page_shift; 9473 9474 /* Get the right Queues per Page parameters for our Queue. 9475 */ 9476 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9477 ? adapter->params.sge.eq_s_qpp 9478 : adapter->params.sge.iq_s_qpp); 9479 qpp_mask = (1 << qpp_shift) - 1; 9480 9481 /* Calculate the basics of the BAR2 SGE Queue register area: 9482 * o The BAR2 page the Queue registers will be in. 9483 * o The BAR2 Queue ID. 9484 * o The BAR2 Queue ID Offset into the BAR2 page. 9485 */ 9486 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9487 bar2_qid = qid & qpp_mask; 9488 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9489 9490 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9491 * hardware will infer the Absolute Queue ID simply from the writes to 9492 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9493 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9494 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9495 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9496 * from the BAR2 Page and BAR2 Queue ID. 9497 * 9498 * One important censequence of this is that some BAR2 SGE registers 9499 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9500 * there. But other registers synthesize the SGE Queue ID purely 9501 * from the writes to the registers -- the Write Combined Doorbell 9502 * Buffer is a good example. These BAR2 SGE Registers are only 9503 * available for those BAR2 SGE Register areas where the SGE Absolute 9504 * Queue ID can be inferred from simple writes. 9505 */ 9506 bar2_qoffset = bar2_page_offset; 9507 bar2_qinferred = (bar2_qid_offset < page_size); 9508 if (bar2_qinferred) { 9509 bar2_qoffset += bar2_qid_offset; 9510 bar2_qid = 0; 9511 } 9512 9513 *pbar2_qoffset = bar2_qoffset; 9514 *pbar2_qid = bar2_qid; 9515 return 0; 9516 } 9517 9518 /** 9519 * t4_init_devlog_params - initialize adapter->params.devlog 9520 * @adap: the adapter 9521 * @fw_attach: whether we can talk to the firmware 9522 * 9523 * Initialize various fields of the adapter's Firmware Device Log 9524 * Parameters structure. 9525 */ 9526 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9527 { 9528 struct devlog_params *dparams = &adap->params.devlog; 9529 u32 pf_dparams; 9530 unsigned int devlog_meminfo; 9531 struct fw_devlog_cmd devlog_cmd; 9532 int ret; 9533 9534 /* If we're dealing with newer firmware, the Device Log Paramerters 9535 * are stored in a designated register which allows us to access the 9536 * Device Log even if we can't talk to the firmware. 9537 */ 9538 pf_dparams = 9539 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9540 if (pf_dparams) { 9541 unsigned int nentries, nentries128; 9542 9543 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9544 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9545 9546 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9547 nentries = (nentries128 + 1) * 128; 9548 dparams->size = nentries * sizeof(struct fw_devlog_e); 9549 9550 return 0; 9551 } 9552 9553 /* 9554 * For any failing returns ... 9555 */ 9556 memset(dparams, 0, sizeof *dparams); 9557 9558 /* 9559 * If we can't talk to the firmware, there's really nothing we can do 9560 * at this point. 9561 */ 9562 if (!fw_attach) 9563 return -ENXIO; 9564 9565 /* Otherwise, ask the firmware for it's Device Log Parameters. 9566 */ 9567 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9568 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9569 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9570 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9571 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9572 &devlog_cmd); 9573 if (ret) 9574 return ret; 9575 9576 devlog_meminfo = 9577 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9578 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9579 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9580 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9581 9582 return 0; 9583 } 9584 9585 /** 9586 * t4_init_sge_params - initialize adap->params.sge 9587 * @adapter: the adapter 9588 * 9589 * Initialize various fields of the adapter's SGE Parameters structure. 9590 */ 9591 int t4_init_sge_params(struct adapter *adapter) 9592 { 9593 u32 r; 9594 struct sge_params *sp = &adapter->params.sge; 9595 unsigned i, tscale = 1; 9596 9597 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9598 sp->counter_val[0] = G_THRESHOLD_0(r); 9599 sp->counter_val[1] = G_THRESHOLD_1(r); 9600 sp->counter_val[2] = G_THRESHOLD_2(r); 9601 sp->counter_val[3] = G_THRESHOLD_3(r); 9602 9603 if (chip_id(adapter) >= CHELSIO_T6) { 9604 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9605 tscale = G_TSCALE(r); 9606 if (tscale == 0) 9607 tscale = 1; 9608 else 9609 tscale += 2; 9610 } 9611 9612 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9613 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9614 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9615 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9616 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9617 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9618 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9619 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9620 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9621 9622 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9623 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9624 if (is_t4(adapter)) 9625 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9626 else if (is_t5(adapter)) 9627 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9628 else 9629 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9630 9631 /* egress queues: log2 of # of doorbells per BAR2 page */ 9632 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9633 r >>= S_QUEUESPERPAGEPF0 + 9634 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9635 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9636 9637 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9638 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9639 r >>= S_QUEUESPERPAGEPF0 + 9640 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9641 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9642 9643 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9644 r >>= S_HOSTPAGESIZEPF0 + 9645 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9646 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9647 9648 r = t4_read_reg(adapter, A_SGE_CONTROL); 9649 sp->sge_control = r; 9650 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9651 sp->fl_pktshift = G_PKTSHIFT(r); 9652 if (chip_id(adapter) <= CHELSIO_T5) { 9653 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9654 X_INGPADBOUNDARY_SHIFT); 9655 } else { 9656 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9657 X_T6_INGPADBOUNDARY_SHIFT); 9658 } 9659 if (is_t4(adapter)) 9660 sp->pack_boundary = sp->pad_boundary; 9661 else { 9662 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9663 if (G_INGPACKBOUNDARY(r) == 0) 9664 sp->pack_boundary = 16; 9665 else 9666 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9667 } 9668 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9669 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9670 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9671 9672 return 0; 9673 } 9674 9675 /* Convert the LE's hardware hash mask to a shorter filter mask. */ 9676 static inline uint16_t 9677 hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode) 9678 { 9679 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 9680 int i; 9681 uint16_t filter_mask; 9682 uint64_t mask; /* field mask */ 9683 9684 filter_mask = 0; 9685 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 9686 if ((filter_mode & (1 << i)) == 0) 9687 continue; 9688 mask = (1 << width[i]) - 1; 9689 if ((hashmask & mask) == mask) 9690 filter_mask |= 1 << i; 9691 hashmask >>= width[i]; 9692 } 9693 9694 return (filter_mask); 9695 } 9696 9697 /* 9698 * Read and cache the adapter's compressed filter mode and ingress config. 9699 */ 9700 static void 9701 read_filter_mode_and_ingress_config(struct adapter *adap) 9702 { 9703 int rc; 9704 uint32_t v, param[2], val[2]; 9705 struct tp_params *tpp = &adap->params.tp; 9706 uint64_t hash_mask; 9707 9708 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9709 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9710 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 9711 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9712 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9713 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 9714 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); 9715 if (rc == 0) { 9716 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); 9717 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); 9718 tpp->vnic_mode = val[1]; 9719 } else { 9720 /* 9721 * Old firmware. Read filter mode/mask and ingress config 9722 * straight from the hardware. 9723 */ 9724 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true); 9725 tpp->filter_mode = v & 0xffff; 9726 9727 hash_mask = 0; 9728 if (chip_id(adap) > CHELSIO_T4) { 9729 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9730 hash_mask = v; 9731 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9732 hash_mask |= (u64)v << 32; 9733 } 9734 tpp->filter_mask = hashmask_to_filtermask(hash_mask, 9735 tpp->filter_mode); 9736 9737 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true); 9738 if (v & F_VNIC) 9739 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; 9740 else 9741 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; 9742 } 9743 9744 /* 9745 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9746 * shift positions of several elements of the Compressed Filter Tuple 9747 * for this adapter which we need frequently ... 9748 */ 9749 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9750 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9751 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9752 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9753 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9754 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9755 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9756 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9757 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9758 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9759 } 9760 9761 /** 9762 * t4_init_tp_params - initialize adap->params.tp 9763 * @adap: the adapter 9764 * 9765 * Initialize various fields of the adapter's TP Parameters structure. 9766 */ 9767 int t4_init_tp_params(struct adapter *adap) 9768 { 9769 int chan; 9770 u32 tx_len, rx_len, r, v; 9771 struct tp_params *tpp = &adap->params.tp; 9772 9773 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9774 tpp->tre = G_TIMERRESOLUTION(v); 9775 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9776 9777 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9778 for (chan = 0; chan < MAX_NCHAN; chan++) 9779 tpp->tx_modq[chan] = chan; 9780 9781 read_filter_mode_and_ingress_config(adap); 9782 9783 if (chip_id(adap) > CHELSIO_T5) { 9784 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9785 tpp->rx_pkt_encap = v & F_CRXPKTENC; 9786 } else 9787 tpp->rx_pkt_encap = false; 9788 9789 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE); 9790 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE); 9791 9792 r = t4_read_reg(adap, A_TP_PARA_REG2); 9793 rx_len = min(rx_len, G_MAXRXDATA(r)); 9794 tx_len = min(tx_len, G_MAXRXDATA(r)); 9795 9796 r = t4_read_reg(adap, A_TP_PARA_REG7); 9797 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 9798 rx_len = min(rx_len, v); 9799 tx_len = min(tx_len, v); 9800 9801 tpp->max_tx_pdu = tx_len; 9802 tpp->max_rx_pdu = rx_len; 9803 9804 return 0; 9805 } 9806 9807 /** 9808 * t4_filter_field_shift - calculate filter field shift 9809 * @adap: the adapter 9810 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9811 * 9812 * Return the shift position of a filter field within the Compressed 9813 * Filter Tuple. The filter field is specified via its selection bit 9814 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9815 */ 9816 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9817 { 9818 const unsigned int filter_mode = adap->params.tp.filter_mode; 9819 unsigned int sel; 9820 int field_shift; 9821 9822 if ((filter_mode & filter_sel) == 0) 9823 return -1; 9824 9825 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9826 switch (filter_mode & sel) { 9827 case F_FCOE: 9828 field_shift += W_FT_FCOE; 9829 break; 9830 case F_PORT: 9831 field_shift += W_FT_PORT; 9832 break; 9833 case F_VNIC_ID: 9834 field_shift += W_FT_VNIC_ID; 9835 break; 9836 case F_VLAN: 9837 field_shift += W_FT_VLAN; 9838 break; 9839 case F_TOS: 9840 field_shift += W_FT_TOS; 9841 break; 9842 case F_PROTOCOL: 9843 field_shift += W_FT_PROTOCOL; 9844 break; 9845 case F_ETHERTYPE: 9846 field_shift += W_FT_ETHERTYPE; 9847 break; 9848 case F_MACMATCH: 9849 field_shift += W_FT_MACMATCH; 9850 break; 9851 case F_MPSHITTYPE: 9852 field_shift += W_FT_MPSHITTYPE; 9853 break; 9854 case F_FRAGMENTATION: 9855 field_shift += W_FT_FRAGMENTATION; 9856 break; 9857 } 9858 } 9859 return field_shift; 9860 } 9861 9862 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9863 { 9864 u8 addr[6]; 9865 int ret, i, j; 9866 struct port_info *p = adap2pinfo(adap, port_id); 9867 u32 param, val; 9868 struct vi_info *vi = &p->vi[0]; 9869 9870 for (i = 0, j = -1; i <= p->port_id; i++) { 9871 do { 9872 j++; 9873 } while ((adap->params.portvec & (1 << j)) == 0); 9874 } 9875 9876 p->tx_chan = j; 9877 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9878 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9879 p->rx_c_chan = t4_get_rx_c_chan(adap, j); 9880 p->lport = j; 9881 9882 if (!(adap->flags & IS_VF) || 9883 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9884 t4_update_port_info(p); 9885 } 9886 9887 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9888 &vi->vfvld, &vi->vin); 9889 if (ret < 0) 9890 return ret; 9891 9892 vi->viid = ret; 9893 t4_os_set_hw_addr(p, addr); 9894 9895 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9896 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9897 V_FW_PARAMS_PARAM_YZ(vi->viid); 9898 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9899 if (ret) 9900 vi->rss_base = 0xffff; 9901 else { 9902 /* MPASS((val >> 16) == rss_size); */ 9903 vi->rss_base = val & 0xffff; 9904 } 9905 9906 return 0; 9907 } 9908 9909 /** 9910 * t4_read_cimq_cfg - read CIM queue configuration 9911 * @adap: the adapter 9912 * @base: holds the queue base addresses in bytes 9913 * @size: holds the queue sizes in bytes 9914 * @thres: holds the queue full thresholds in bytes 9915 * 9916 * Returns the current configuration of the CIM queues, starting with 9917 * the IBQs, then the OBQs. 9918 */ 9919 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9920 { 9921 unsigned int i, v; 9922 int cim_num_obq = adap->chip_params->cim_num_obq; 9923 9924 for (i = 0; i < CIM_NUM_IBQ; i++) { 9925 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9926 V_QUENUMSELECT(i)); 9927 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9928 /* value is in 256-byte units */ 9929 *base++ = G_CIMQBASE(v) * 256; 9930 *size++ = G_CIMQSIZE(v) * 256; 9931 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9932 } 9933 for (i = 0; i < cim_num_obq; i++) { 9934 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9935 V_QUENUMSELECT(i)); 9936 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9937 /* value is in 256-byte units */ 9938 *base++ = G_CIMQBASE(v) * 256; 9939 *size++ = G_CIMQSIZE(v) * 256; 9940 } 9941 } 9942 9943 /** 9944 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9945 * @adap: the adapter 9946 * @qid: the queue index 9947 * @data: where to store the queue contents 9948 * @n: capacity of @data in 32-bit words 9949 * 9950 * Reads the contents of the selected CIM queue starting at address 0 up 9951 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9952 * error and the number of 32-bit words actually read on success. 9953 */ 9954 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9955 { 9956 int i, err, attempts; 9957 unsigned int addr; 9958 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9959 9960 if (qid > 5 || (n & 3)) 9961 return -EINVAL; 9962 9963 addr = qid * nwords; 9964 if (n > nwords) 9965 n = nwords; 9966 9967 /* It might take 3-10ms before the IBQ debug read access is allowed. 9968 * Wait for 1 Sec with a delay of 1 usec. 9969 */ 9970 attempts = 1000000; 9971 9972 for (i = 0; i < n; i++, addr++) { 9973 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 9974 F_IBQDBGEN); 9975 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 9976 attempts, 1); 9977 if (err) 9978 return err; 9979 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 9980 } 9981 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 9982 return i; 9983 } 9984 9985 /** 9986 * t4_read_cim_obq - read the contents of a CIM outbound queue 9987 * @adap: the adapter 9988 * @qid: the queue index 9989 * @data: where to store the queue contents 9990 * @n: capacity of @data in 32-bit words 9991 * 9992 * Reads the contents of the selected CIM queue starting at address 0 up 9993 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9994 * error and the number of 32-bit words actually read on success. 9995 */ 9996 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9997 { 9998 int i, err; 9999 unsigned int addr, v, nwords; 10000 int cim_num_obq = adap->chip_params->cim_num_obq; 10001 10002 if ((qid > (cim_num_obq - 1)) || (n & 3)) 10003 return -EINVAL; 10004 10005 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 10006 V_QUENUMSELECT(qid)); 10007 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 10008 10009 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 10010 nwords = G_CIMQSIZE(v) * 64; /* same */ 10011 if (n > nwords) 10012 n = nwords; 10013 10014 for (i = 0; i < n; i++, addr++) { 10015 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 10016 F_OBQDBGEN); 10017 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 10018 2, 1); 10019 if (err) 10020 return err; 10021 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 10022 } 10023 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 10024 return i; 10025 } 10026 10027 enum { 10028 CIM_QCTL_BASE = 0, 10029 CIM_CTL_BASE = 0x2000, 10030 CIM_PBT_ADDR_BASE = 0x2800, 10031 CIM_PBT_LRF_BASE = 0x3000, 10032 CIM_PBT_DATA_BASE = 0x3800 10033 }; 10034 10035 /** 10036 * t4_cim_read - read a block from CIM internal address space 10037 * @adap: the adapter 10038 * @addr: the start address within the CIM address space 10039 * @n: number of words to read 10040 * @valp: where to store the result 10041 * 10042 * Reads a block of 4-byte words from the CIM intenal address space. 10043 */ 10044 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 10045 unsigned int *valp) 10046 { 10047 int ret = 0; 10048 10049 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10050 return -EBUSY; 10051 10052 for ( ; !ret && n--; addr += 4) { 10053 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 10054 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10055 0, 5, 2); 10056 if (!ret) 10057 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 10058 } 10059 return ret; 10060 } 10061 10062 /** 10063 * t4_cim_write - write a block into CIM internal address space 10064 * @adap: the adapter 10065 * @addr: the start address within the CIM address space 10066 * @n: number of words to write 10067 * @valp: set of values to write 10068 * 10069 * Writes a block of 4-byte words into the CIM intenal address space. 10070 */ 10071 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 10072 const unsigned int *valp) 10073 { 10074 int ret = 0; 10075 10076 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10077 return -EBUSY; 10078 10079 for ( ; !ret && n--; addr += 4) { 10080 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 10081 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 10082 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10083 0, 5, 2); 10084 } 10085 return ret; 10086 } 10087 10088 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 10089 unsigned int val) 10090 { 10091 return t4_cim_write(adap, addr, 1, &val); 10092 } 10093 10094 /** 10095 * t4_cim_ctl_read - read a block from CIM control region 10096 * @adap: the adapter 10097 * @addr: the start address within the CIM control region 10098 * @n: number of words to read 10099 * @valp: where to store the result 10100 * 10101 * Reads a block of 4-byte words from the CIM control region. 10102 */ 10103 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 10104 unsigned int *valp) 10105 { 10106 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 10107 } 10108 10109 /** 10110 * t4_cim_read_la - read CIM LA capture buffer 10111 * @adap: the adapter 10112 * @la_buf: where to store the LA data 10113 * @wrptr: the HW write pointer within the capture buffer 10114 * 10115 * Reads the contents of the CIM LA buffer with the most recent entry at 10116 * the end of the returned data and with the entry at @wrptr first. 10117 * We try to leave the LA in the running state we find it in. 10118 */ 10119 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 10120 { 10121 int i, ret; 10122 unsigned int cfg, val, idx; 10123 10124 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 10125 if (ret) 10126 return ret; 10127 10128 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 10129 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 10130 if (ret) 10131 return ret; 10132 } 10133 10134 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10135 if (ret) 10136 goto restart; 10137 10138 idx = G_UPDBGLAWRPTR(val); 10139 if (wrptr) 10140 *wrptr = idx; 10141 10142 for (i = 0; i < adap->params.cim_la_size; i++) { 10143 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10144 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 10145 if (ret) 10146 break; 10147 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10148 if (ret) 10149 break; 10150 if (val & F_UPDBGLARDEN) { 10151 ret = -ETIMEDOUT; 10152 break; 10153 } 10154 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 10155 if (ret) 10156 break; 10157 10158 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 10159 * identify the 32-bit portion of the full 312-bit data 10160 */ 10161 if (is_t6(adap) && (idx & 0xf) >= 9) 10162 idx = (idx & 0xff0) + 0x10; 10163 else 10164 idx++; 10165 /* address can't exceed 0xfff */ 10166 idx &= M_UPDBGLARDPTR; 10167 } 10168 restart: 10169 if (cfg & F_UPDBGLAEN) { 10170 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10171 cfg & ~F_UPDBGLARDEN); 10172 if (!ret) 10173 ret = r; 10174 } 10175 return ret; 10176 } 10177 10178 /** 10179 * t4_tp_read_la - read TP LA capture buffer 10180 * @adap: the adapter 10181 * @la_buf: where to store the LA data 10182 * @wrptr: the HW write pointer within the capture buffer 10183 * 10184 * Reads the contents of the TP LA buffer with the most recent entry at 10185 * the end of the returned data and with the entry at @wrptr first. 10186 * We leave the LA in the running state we find it in. 10187 */ 10188 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 10189 { 10190 bool last_incomplete; 10191 unsigned int i, cfg, val, idx; 10192 10193 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 10194 if (cfg & F_DBGLAENABLE) /* freeze LA */ 10195 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10196 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 10197 10198 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 10199 idx = G_DBGLAWPTR(val); 10200 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 10201 if (last_incomplete) 10202 idx = (idx + 1) & M_DBGLARPTR; 10203 if (wrptr) 10204 *wrptr = idx; 10205 10206 val &= 0xffff; 10207 val &= ~V_DBGLARPTR(M_DBGLARPTR); 10208 val |= adap->params.tp.la_mask; 10209 10210 for (i = 0; i < TPLA_SIZE; i++) { 10211 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 10212 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 10213 idx = (idx + 1) & M_DBGLARPTR; 10214 } 10215 10216 /* Wipe out last entry if it isn't valid */ 10217 if (last_incomplete) 10218 la_buf[TPLA_SIZE - 1] = ~0ULL; 10219 10220 if (cfg & F_DBGLAENABLE) /* restore running state */ 10221 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10222 cfg | adap->params.tp.la_mask); 10223 } 10224 10225 /* 10226 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 10227 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 10228 * state for more than the Warning Threshold then we'll issue a warning about 10229 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 10230 * appears to be hung every Warning Repeat second till the situation clears. 10231 * If the situation clears, we'll note that as well. 10232 */ 10233 #define SGE_IDMA_WARN_THRESH 1 10234 #define SGE_IDMA_WARN_REPEAT 300 10235 10236 /** 10237 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 10238 * @adapter: the adapter 10239 * @idma: the adapter IDMA Monitor state 10240 * 10241 * Initialize the state of an SGE Ingress DMA Monitor. 10242 */ 10243 void t4_idma_monitor_init(struct adapter *adapter, 10244 struct sge_idma_monitor_state *idma) 10245 { 10246 /* Initialize the state variables for detecting an SGE Ingress DMA 10247 * hang. The SGE has internal counters which count up on each clock 10248 * tick whenever the SGE finds its Ingress DMA State Engines in the 10249 * same state they were on the previous clock tick. The clock used is 10250 * the Core Clock so we have a limit on the maximum "time" they can 10251 * record; typically a very small number of seconds. For instance, 10252 * with a 600MHz Core Clock, we can only count up to a bit more than 10253 * 7s. So we'll synthesize a larger counter in order to not run the 10254 * risk of having the "timers" overflow and give us the flexibility to 10255 * maintain a Hung SGE State Machine of our own which operates across 10256 * a longer time frame. 10257 */ 10258 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 10259 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 10260 } 10261 10262 /** 10263 * t4_idma_monitor - monitor SGE Ingress DMA state 10264 * @adapter: the adapter 10265 * @idma: the adapter IDMA Monitor state 10266 * @hz: number of ticks/second 10267 * @ticks: number of ticks since the last IDMA Monitor call 10268 */ 10269 void t4_idma_monitor(struct adapter *adapter, 10270 struct sge_idma_monitor_state *idma, 10271 int hz, int ticks) 10272 { 10273 int i, idma_same_state_cnt[2]; 10274 10275 /* Read the SGE Debug Ingress DMA Same State Count registers. These 10276 * are counters inside the SGE which count up on each clock when the 10277 * SGE finds its Ingress DMA State Engines in the same states they 10278 * were in the previous clock. The counters will peg out at 10279 * 0xffffffff without wrapping around so once they pass the 1s 10280 * threshold they'll stay above that till the IDMA state changes. 10281 */ 10282 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 10283 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 10284 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10285 10286 for (i = 0; i < 2; i++) { 10287 u32 debug0, debug11; 10288 10289 /* If the Ingress DMA Same State Counter ("timer") is less 10290 * than 1s, then we can reset our synthesized Stall Timer and 10291 * continue. If we have previously emitted warnings about a 10292 * potential stalled Ingress Queue, issue a note indicating 10293 * that the Ingress Queue has resumed forward progress. 10294 */ 10295 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 10296 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 10297 CH_WARN(adapter, "SGE idma%d, queue %u, " 10298 "resumed after %d seconds\n", 10299 i, idma->idma_qid[i], 10300 idma->idma_stalled[i]/hz); 10301 idma->idma_stalled[i] = 0; 10302 continue; 10303 } 10304 10305 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 10306 * domain. The first time we get here it'll be because we 10307 * passed the 1s Threshold; each additional time it'll be 10308 * because the RX Timer Callback is being fired on its regular 10309 * schedule. 10310 * 10311 * If the stall is below our Potential Hung Ingress Queue 10312 * Warning Threshold, continue. 10313 */ 10314 if (idma->idma_stalled[i] == 0) { 10315 idma->idma_stalled[i] = hz; 10316 idma->idma_warn[i] = 0; 10317 } else { 10318 idma->idma_stalled[i] += ticks; 10319 idma->idma_warn[i] -= ticks; 10320 } 10321 10322 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 10323 continue; 10324 10325 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 10326 */ 10327 if (idma->idma_warn[i] > 0) 10328 continue; 10329 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 10330 10331 /* Read and save the SGE IDMA State and Queue ID information. 10332 * We do this every time in case it changes across time ... 10333 * can't be too careful ... 10334 */ 10335 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 10336 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10337 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 10338 10339 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 10340 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10341 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 10342 10343 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 10344 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 10345 i, idma->idma_qid[i], idma->idma_state[i], 10346 idma->idma_stalled[i]/hz, 10347 debug0, debug11); 10348 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 10349 } 10350 } 10351 10352 /** 10353 * t4_set_vf_mac - Set MAC address for the specified VF 10354 * @adapter: The adapter 10355 * @pf: the PF used to instantiate the VFs 10356 * @vf: one of the VFs instantiated by the specified PF 10357 * @naddr: the number of MAC addresses 10358 * @addr: the MAC address(es) to be set to the specified VF 10359 */ 10360 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, 10361 unsigned int naddr, u8 *addr) 10362 { 10363 struct fw_acl_mac_cmd cmd; 10364 10365 memset(&cmd, 0, sizeof(cmd)); 10366 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | 10367 F_FW_CMD_REQUEST | 10368 F_FW_CMD_WRITE | 10369 V_FW_ACL_MAC_CMD_PFN(pf) | 10370 V_FW_ACL_MAC_CMD_VFN(vf)); 10371 10372 /* Note: Do not enable the ACL */ 10373 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); 10374 cmd.nmac = naddr; 10375 10376 switch (pf) { 10377 case 3: 10378 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); 10379 break; 10380 case 2: 10381 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); 10382 break; 10383 case 1: 10384 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); 10385 break; 10386 case 0: 10387 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); 10388 break; 10389 } 10390 10391 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); 10392 } 10393 10394 /** 10395 * t4_read_pace_tbl - read the pace table 10396 * @adap: the adapter 10397 * @pace_vals: holds the returned values 10398 * 10399 * Returns the values of TP's pace table in microseconds. 10400 */ 10401 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 10402 { 10403 unsigned int i, v; 10404 10405 for (i = 0; i < NTX_SCHED; i++) { 10406 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 10407 v = t4_read_reg(adap, A_TP_PACE_TABLE); 10408 pace_vals[i] = dack_ticks_to_usec(adap, v); 10409 } 10410 } 10411 10412 /** 10413 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 10414 * @adap: the adapter 10415 * @sched: the scheduler index 10416 * @kbps: the byte rate in Kbps 10417 * @ipg: the interpacket delay in tenths of nanoseconds 10418 * 10419 * Return the current configuration of a HW Tx scheduler. 10420 */ 10421 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 10422 unsigned int *ipg, bool sleep_ok) 10423 { 10424 unsigned int v, addr, bpt, cpt; 10425 10426 if (kbps) { 10427 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 10428 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10429 if (sched & 1) 10430 v >>= 16; 10431 bpt = (v >> 8) & 0xff; 10432 cpt = v & 0xff; 10433 if (!cpt) 10434 *kbps = 0; /* scheduler disabled */ 10435 else { 10436 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 10437 *kbps = (v * bpt) / 125; 10438 } 10439 } 10440 if (ipg) { 10441 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 10442 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10443 if (sched & 1) 10444 v >>= 16; 10445 v &= 0xffff; 10446 *ipg = (10000 * v) / core_ticks_per_usec(adap); 10447 } 10448 } 10449 10450 /** 10451 * t4_load_cfg - download config file 10452 * @adap: the adapter 10453 * @cfg_data: the cfg text file to write 10454 * @size: text file size 10455 * 10456 * Write the supplied config text file to the card's serial flash. 10457 */ 10458 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 10459 { 10460 int ret, i, n, cfg_addr; 10461 unsigned int addr; 10462 unsigned int flash_cfg_start_sec; 10463 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10464 10465 cfg_addr = t4_flash_cfg_addr(adap); 10466 if (cfg_addr < 0) 10467 return cfg_addr; 10468 10469 addr = cfg_addr; 10470 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10471 10472 if (size > FLASH_CFG_MAX_SIZE) { 10473 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 10474 FLASH_CFG_MAX_SIZE); 10475 return -EFBIG; 10476 } 10477 10478 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 10479 sf_sec_size); 10480 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10481 flash_cfg_start_sec + i - 1); 10482 /* 10483 * If size == 0 then we're simply erasing the FLASH sectors associated 10484 * with the on-adapter Firmware Configuration File. 10485 */ 10486 if (ret || size == 0) 10487 goto out; 10488 10489 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10490 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10491 if ( (size - i) < SF_PAGE_SIZE) 10492 n = size - i; 10493 else 10494 n = SF_PAGE_SIZE; 10495 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 10496 if (ret) 10497 goto out; 10498 10499 addr += SF_PAGE_SIZE; 10500 cfg_data += SF_PAGE_SIZE; 10501 } 10502 10503 out: 10504 if (ret) 10505 CH_ERR(adap, "config file %s failed %d\n", 10506 (size == 0 ? "clear" : "download"), ret); 10507 return ret; 10508 } 10509 10510 /** 10511 * t5_fw_init_extern_mem - initialize the external memory 10512 * @adap: the adapter 10513 * 10514 * Initializes the external memory on T5. 10515 */ 10516 int t5_fw_init_extern_mem(struct adapter *adap) 10517 { 10518 u32 params[1], val[1]; 10519 int ret; 10520 10521 if (!is_t5(adap)) 10522 return 0; 10523 10524 val[0] = 0xff; /* Initialize all MCs */ 10525 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10526 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10527 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10528 FW_CMD_MAX_TIMEOUT); 10529 10530 return ret; 10531 } 10532 10533 /* BIOS boot headers */ 10534 typedef struct pci_expansion_rom_header { 10535 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10536 u8 reserved[22]; /* Reserved per processor Architecture data */ 10537 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10538 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10539 10540 /* Legacy PCI Expansion ROM Header */ 10541 typedef struct legacy_pci_expansion_rom_header { 10542 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10543 u8 size512; /* Current Image Size in units of 512 bytes */ 10544 u8 initentry_point[4]; 10545 u8 cksum; /* Checksum computed on the entire Image */ 10546 u8 reserved[16]; /* Reserved */ 10547 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10548 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10549 10550 /* EFI PCI Expansion ROM Header */ 10551 typedef struct efi_pci_expansion_rom_header { 10552 u8 signature[2]; // ROM signature. The value 0xaa55 10553 u8 initialization_size[2]; /* Units 512. Includes this header */ 10554 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10555 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10556 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10557 u8 compression_type[2]; /* Compression type. */ 10558 /* 10559 * Compression type definition 10560 * 0x0: uncompressed 10561 * 0x1: Compressed 10562 * 0x2-0xFFFF: Reserved 10563 */ 10564 u8 reserved[8]; /* Reserved */ 10565 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10566 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10567 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10568 10569 /* PCI Data Structure Format */ 10570 typedef struct pcir_data_structure { /* PCI Data Structure */ 10571 u8 signature[4]; /* Signature. The string "PCIR" */ 10572 u8 vendor_id[2]; /* Vendor Identification */ 10573 u8 device_id[2]; /* Device Identification */ 10574 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10575 u8 length[2]; /* PCIR Data Structure Length */ 10576 u8 revision; /* PCIR Data Structure Revision */ 10577 u8 class_code[3]; /* Class Code */ 10578 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10579 u8 code_revision[2]; /* Revision Level of Code/Data */ 10580 u8 code_type; /* Code Type. */ 10581 /* 10582 * PCI Expansion ROM Code Types 10583 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10584 * 0x01: Open Firmware standard for PCI. FCODE 10585 * 0x02: Hewlett-Packard PA RISC. HP reserved 10586 * 0x03: EFI Image. EFI 10587 * 0x04-0xFF: Reserved. 10588 */ 10589 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10590 u8 reserved[2]; /* Reserved */ 10591 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10592 10593 /* BOOT constants */ 10594 enum { 10595 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10596 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10597 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10598 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10599 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10600 VENDOR_ID = 0x1425, /* Vendor ID */ 10601 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10602 }; 10603 10604 /* 10605 * modify_device_id - Modifies the device ID of the Boot BIOS image 10606 * @adatper: the device ID to write. 10607 * @boot_data: the boot image to modify. 10608 * 10609 * Write the supplied device ID to the boot BIOS image. 10610 */ 10611 static void modify_device_id(int device_id, u8 *boot_data) 10612 { 10613 legacy_pci_exp_rom_header_t *header; 10614 pcir_data_t *pcir_header; 10615 u32 cur_header = 0; 10616 10617 /* 10618 * Loop through all chained images and change the device ID's 10619 */ 10620 while (1) { 10621 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10622 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10623 le16_to_cpu(*(u16*)header->pcir_offset)]; 10624 10625 /* 10626 * Only modify the Device ID if code type is Legacy or HP. 10627 * 0x00: Okay to modify 10628 * 0x01: FCODE. Do not be modify 10629 * 0x03: Okay to modify 10630 * 0x04-0xFF: Do not modify 10631 */ 10632 if (pcir_header->code_type == 0x00) { 10633 u8 csum = 0; 10634 int i; 10635 10636 /* 10637 * Modify Device ID to match current adatper 10638 */ 10639 *(u16*) pcir_header->device_id = device_id; 10640 10641 /* 10642 * Set checksum temporarily to 0. 10643 * We will recalculate it later. 10644 */ 10645 header->cksum = 0x0; 10646 10647 /* 10648 * Calculate and update checksum 10649 */ 10650 for (i = 0; i < (header->size512 * 512); i++) 10651 csum += (u8)boot_data[cur_header + i]; 10652 10653 /* 10654 * Invert summed value to create the checksum 10655 * Writing new checksum value directly to the boot data 10656 */ 10657 boot_data[cur_header + 7] = -csum; 10658 10659 } else if (pcir_header->code_type == 0x03) { 10660 10661 /* 10662 * Modify Device ID to match current adatper 10663 */ 10664 *(u16*) pcir_header->device_id = device_id; 10665 10666 } 10667 10668 10669 /* 10670 * Check indicator element to identify if this is the last 10671 * image in the ROM. 10672 */ 10673 if (pcir_header->indicator & 0x80) 10674 break; 10675 10676 /* 10677 * Move header pointer up to the next image in the ROM. 10678 */ 10679 cur_header += header->size512 * 512; 10680 } 10681 } 10682 10683 /* 10684 * t4_load_boot - download boot flash 10685 * @adapter: the adapter 10686 * @boot_data: the boot image to write 10687 * @boot_addr: offset in flash to write boot_data 10688 * @size: image size 10689 * 10690 * Write the supplied boot image to the card's serial flash. 10691 * The boot image has the following sections: a 28-byte header and the 10692 * boot image. 10693 */ 10694 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10695 unsigned int boot_addr, unsigned int size) 10696 { 10697 pci_exp_rom_header_t *header; 10698 int pcir_offset ; 10699 pcir_data_t *pcir_header; 10700 int ret, addr; 10701 uint16_t device_id; 10702 unsigned int i; 10703 unsigned int boot_sector = (boot_addr * 1024 ); 10704 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10705 10706 /* 10707 * Make sure the boot image does not encroach on the firmware region 10708 */ 10709 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10710 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10711 return -EFBIG; 10712 } 10713 10714 /* 10715 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10716 * and Boot configuration data sections. These 3 boot sections span 10717 * sectors 0 to 7 in flash and live right before the FW image location. 10718 */ 10719 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10720 sf_sec_size); 10721 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10722 (boot_sector >> 16) + i - 1); 10723 10724 /* 10725 * If size == 0 then we're simply erasing the FLASH sectors associated 10726 * with the on-adapter option ROM file 10727 */ 10728 if (ret || (size == 0)) 10729 goto out; 10730 10731 /* Get boot header */ 10732 header = (pci_exp_rom_header_t *)boot_data; 10733 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10734 /* PCIR Data Structure */ 10735 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10736 10737 /* 10738 * Perform some primitive sanity testing to avoid accidentally 10739 * writing garbage over the boot sectors. We ought to check for 10740 * more but it's not worth it for now ... 10741 */ 10742 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10743 CH_ERR(adap, "boot image too small/large\n"); 10744 return -EFBIG; 10745 } 10746 10747 #ifndef CHELSIO_T4_DIAGS 10748 /* 10749 * Check BOOT ROM header signature 10750 */ 10751 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10752 CH_ERR(adap, "Boot image missing signature\n"); 10753 return -EINVAL; 10754 } 10755 10756 /* 10757 * Check PCI header signature 10758 */ 10759 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10760 CH_ERR(adap, "PCI header missing signature\n"); 10761 return -EINVAL; 10762 } 10763 10764 /* 10765 * Check Vendor ID matches Chelsio ID 10766 */ 10767 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10768 CH_ERR(adap, "Vendor ID missing signature\n"); 10769 return -EINVAL; 10770 } 10771 #endif 10772 10773 /* 10774 * Retrieve adapter's device ID 10775 */ 10776 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10777 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10778 device_id = device_id & 0xf0ff; 10779 10780 /* 10781 * Check PCIE Device ID 10782 */ 10783 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10784 /* 10785 * Change the device ID in the Boot BIOS image to match 10786 * the Device ID of the current adapter. 10787 */ 10788 modify_device_id(device_id, boot_data); 10789 } 10790 10791 /* 10792 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10793 * we finish copying the rest of the boot image. This will ensure 10794 * that the BIOS boot header will only be written if the boot image 10795 * was written in full. 10796 */ 10797 addr = boot_sector; 10798 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10799 addr += SF_PAGE_SIZE; 10800 boot_data += SF_PAGE_SIZE; 10801 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10802 if (ret) 10803 goto out; 10804 } 10805 10806 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10807 (const u8 *)header, 0); 10808 10809 out: 10810 if (ret) 10811 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10812 return ret; 10813 } 10814 10815 /* 10816 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10817 * @adapter: the adapter 10818 * 10819 * Return the address within the flash where the OptionROM Configuration 10820 * is stored, or an error if the device FLASH is too small to contain 10821 * a OptionROM Configuration. 10822 */ 10823 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10824 { 10825 /* 10826 * If the device FLASH isn't large enough to hold a Firmware 10827 * Configuration File, return an error. 10828 */ 10829 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10830 return -ENOSPC; 10831 10832 return FLASH_BOOTCFG_START; 10833 } 10834 10835 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10836 { 10837 int ret, i, n, cfg_addr; 10838 unsigned int addr; 10839 unsigned int flash_cfg_start_sec; 10840 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10841 10842 cfg_addr = t4_flash_bootcfg_addr(adap); 10843 if (cfg_addr < 0) 10844 return cfg_addr; 10845 10846 addr = cfg_addr; 10847 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10848 10849 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10850 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10851 FLASH_BOOTCFG_MAX_SIZE); 10852 return -EFBIG; 10853 } 10854 10855 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10856 sf_sec_size); 10857 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10858 flash_cfg_start_sec + i - 1); 10859 10860 /* 10861 * If size == 0 then we're simply erasing the FLASH sectors associated 10862 * with the on-adapter OptionROM Configuration File. 10863 */ 10864 if (ret || size == 0) 10865 goto out; 10866 10867 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10868 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10869 if ( (size - i) < SF_PAGE_SIZE) 10870 n = size - i; 10871 else 10872 n = SF_PAGE_SIZE; 10873 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10874 if (ret) 10875 goto out; 10876 10877 addr += SF_PAGE_SIZE; 10878 cfg_data += SF_PAGE_SIZE; 10879 } 10880 10881 out: 10882 if (ret) 10883 CH_ERR(adap, "boot config data %s failed %d\n", 10884 (size == 0 ? "clear" : "download"), ret); 10885 return ret; 10886 } 10887 10888 /** 10889 * t4_set_filter_cfg - set up filter mode/mask and ingress config. 10890 * @adap: the adapter 10891 * @mode: a bitmap selecting which optional filter components to enable 10892 * @mask: a bitmap selecting which components to enable in filter mask 10893 * @vnic_mode: the ingress config/vnic mode setting 10894 * 10895 * Sets the filter mode and mask by selecting the optional components to 10896 * enable in filter tuples. Returns 0 on success and a negative error if 10897 * the requested mode needs more bits than are available for optional 10898 * components. The filter mask must be a subset of the filter mode. 10899 */ 10900 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) 10901 { 10902 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 10903 int i, nbits, rc; 10904 uint32_t param, val; 10905 uint16_t fmode, fmask; 10906 const int maxbits = adap->chip_params->filter_opt_len; 10907 10908 if (mode != -1 || mask != -1) { 10909 if (mode != -1) { 10910 fmode = mode; 10911 nbits = 0; 10912 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10913 if (fmode & (1 << i)) 10914 nbits += width[i]; 10915 } 10916 if (nbits > maxbits) { 10917 CH_ERR(adap, "optional fields in the filter " 10918 "mode (0x%x) add up to %d bits " 10919 "(must be <= %db). Remove some fields and " 10920 "try again.\n", fmode, nbits, maxbits); 10921 return -E2BIG; 10922 } 10923 10924 /* 10925 * Hardware wants the bits to be maxed out. Keep 10926 * setting them until there's no room for more. 10927 */ 10928 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10929 if (fmode & (1 << i)) 10930 continue; 10931 if (nbits + width[i] <= maxbits) { 10932 fmode |= 1 << i; 10933 nbits += width[i]; 10934 if (nbits == maxbits) 10935 break; 10936 } 10937 } 10938 10939 fmask = fmode & adap->params.tp.filter_mask; 10940 if (fmask != adap->params.tp.filter_mask) { 10941 CH_WARN(adap, 10942 "filter mask will be changed from 0x%x to " 10943 "0x%x to comply with the filter mode (0x%x).\n", 10944 adap->params.tp.filter_mask, fmask, fmode); 10945 } 10946 } else { 10947 fmode = adap->params.tp.filter_mode; 10948 fmask = mask; 10949 if ((fmode | fmask) != fmode) { 10950 CH_ERR(adap, 10951 "filter mask (0x%x) must be a subset of " 10952 "the filter mode (0x%x).\n", fmask, fmode); 10953 return -EINVAL; 10954 } 10955 } 10956 10957 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10958 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10959 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 10960 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) | 10961 V_FW_PARAMS_PARAM_FILTER_MASK(fmask); 10962 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10963 &val); 10964 if (rc < 0) 10965 return rc; 10966 } 10967 10968 if (vnic_mode != -1) { 10969 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10970 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10971 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 10972 val = vnic_mode; 10973 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10974 &val); 10975 if (rc < 0) 10976 return rc; 10977 } 10978 10979 /* Refresh. */ 10980 read_filter_mode_and_ingress_config(adap); 10981 10982 return 0; 10983 } 10984 10985 /** 10986 * t4_clr_port_stats - clear port statistics 10987 * @adap: the adapter 10988 * @idx: the port index 10989 * 10990 * Clear HW statistics for the given port. 10991 */ 10992 void t4_clr_port_stats(struct adapter *adap, int idx) 10993 { 10994 unsigned int i; 10995 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 10996 u32 port_base_addr; 10997 10998 if (is_t4(adap)) 10999 port_base_addr = PORT_BASE(idx); 11000 else 11001 port_base_addr = T5_PORT_BASE(idx); 11002 11003 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 11004 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 11005 t4_write_reg(adap, port_base_addr + i, 0); 11006 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 11007 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 11008 t4_write_reg(adap, port_base_addr + i, 0); 11009 for (i = 0; i < 4; i++) 11010 if (bgmap & (1 << i)) { 11011 t4_write_reg(adap, 11012 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 11013 t4_write_reg(adap, 11014 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 11015 } 11016 } 11017 11018 /** 11019 * t4_i2c_io - read/write I2C data from adapter 11020 * @adap: the adapter 11021 * @port: Port number if per-port device; <0 if not 11022 * @devid: per-port device ID or absolute device ID 11023 * @offset: byte offset into device I2C space 11024 * @len: byte length of I2C space data 11025 * @buf: buffer in which to return I2C data for read 11026 * buffer which holds the I2C data for write 11027 * @write: if true, do a write; else do a read 11028 * Reads/Writes the I2C data from/to the indicated device and location. 11029 */ 11030 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 11031 int port, unsigned int devid, 11032 unsigned int offset, unsigned int len, 11033 u8 *buf, bool write) 11034 { 11035 struct fw_ldst_cmd ldst_cmd, ldst_rpl; 11036 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data); 11037 int ret = 0; 11038 11039 if (len > I2C_PAGE_SIZE) 11040 return -EINVAL; 11041 11042 /* Dont allow reads that spans multiple pages */ 11043 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) 11044 return -EINVAL; 11045 11046 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 11047 ldst_cmd.op_to_addrspace = 11048 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11049 F_FW_CMD_REQUEST | 11050 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) | 11051 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 11052 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 11053 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); 11054 ldst_cmd.u.i2c.did = devid; 11055 11056 while (len > 0) { 11057 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max; 11058 11059 ldst_cmd.u.i2c.boffset = offset; 11060 ldst_cmd.u.i2c.blen = i2c_len; 11061 11062 if (write) 11063 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len); 11064 11065 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd), 11066 write ? NULL : &ldst_rpl); 11067 if (ret) 11068 break; 11069 11070 if (!write) 11071 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len); 11072 offset += i2c_len; 11073 buf += i2c_len; 11074 len -= i2c_len; 11075 } 11076 11077 return ret; 11078 } 11079 11080 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 11081 int port, unsigned int devid, 11082 unsigned int offset, unsigned int len, 11083 u8 *buf) 11084 { 11085 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false); 11086 } 11087 11088 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 11089 int port, unsigned int devid, 11090 unsigned int offset, unsigned int len, 11091 u8 *buf) 11092 { 11093 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true); 11094 } 11095 11096 /** 11097 * t4_sge_ctxt_rd - read an SGE context through FW 11098 * @adap: the adapter 11099 * @mbox: mailbox to use for the FW command 11100 * @cid: the context id 11101 * @ctype: the context type 11102 * @data: where to store the context data 11103 * 11104 * Issues a FW command through the given mailbox to read an SGE context. 11105 */ 11106 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 11107 enum ctxt_type ctype, u32 *data) 11108 { 11109 int ret; 11110 struct fw_ldst_cmd c; 11111 11112 if (ctype == CTXT_EGRESS) 11113 ret = FW_LDST_ADDRSPC_SGE_EGRC; 11114 else if (ctype == CTXT_INGRESS) 11115 ret = FW_LDST_ADDRSPC_SGE_INGC; 11116 else if (ctype == CTXT_FLM) 11117 ret = FW_LDST_ADDRSPC_SGE_FLMC; 11118 else 11119 ret = FW_LDST_ADDRSPC_SGE_CONMC; 11120 11121 memset(&c, 0, sizeof(c)); 11122 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11123 F_FW_CMD_REQUEST | F_FW_CMD_READ | 11124 V_FW_LDST_CMD_ADDRSPACE(ret)); 11125 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 11126 c.u.idctxt.physid = cpu_to_be32(cid); 11127 11128 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11129 if (ret == 0) { 11130 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 11131 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 11132 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 11133 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 11134 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 11135 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 11136 } 11137 return ret; 11138 } 11139 11140 /** 11141 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 11142 * @adap: the adapter 11143 * @cid: the context id 11144 * @ctype: the context type 11145 * @data: where to store the context data 11146 * 11147 * Reads an SGE context directly, bypassing FW. This is only for 11148 * debugging when FW is unavailable. 11149 */ 11150 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 11151 u32 *data) 11152 { 11153 int i, ret; 11154 11155 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 11156 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 11157 if (!ret) 11158 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 11159 *data++ = t4_read_reg(adap, i); 11160 return ret; 11161 } 11162 11163 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 11164 int sleep_ok) 11165 { 11166 struct fw_sched_cmd cmd; 11167 11168 memset(&cmd, 0, sizeof(cmd)); 11169 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11170 F_FW_CMD_REQUEST | 11171 F_FW_CMD_WRITE); 11172 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11173 11174 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 11175 cmd.u.config.type = type; 11176 cmd.u.config.minmaxen = minmaxen; 11177 11178 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11179 NULL, sleep_ok); 11180 } 11181 11182 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 11183 int rateunit, int ratemode, int channel, int cl, 11184 int minrate, int maxrate, int weight, int pktsize, 11185 int burstsize, int sleep_ok) 11186 { 11187 struct fw_sched_cmd cmd; 11188 11189 memset(&cmd, 0, sizeof(cmd)); 11190 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11191 F_FW_CMD_REQUEST | 11192 F_FW_CMD_WRITE); 11193 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11194 11195 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11196 cmd.u.params.type = type; 11197 cmd.u.params.level = level; 11198 cmd.u.params.mode = mode; 11199 cmd.u.params.ch = channel; 11200 cmd.u.params.cl = cl; 11201 cmd.u.params.unit = rateunit; 11202 cmd.u.params.rate = ratemode; 11203 cmd.u.params.min = cpu_to_be32(minrate); 11204 cmd.u.params.max = cpu_to_be32(maxrate); 11205 cmd.u.params.weight = cpu_to_be16(weight); 11206 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11207 cmd.u.params.burstsize = cpu_to_be16(burstsize); 11208 11209 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11210 NULL, sleep_ok); 11211 } 11212 11213 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 11214 unsigned int maxrate, int sleep_ok) 11215 { 11216 struct fw_sched_cmd cmd; 11217 11218 memset(&cmd, 0, sizeof(cmd)); 11219 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11220 F_FW_CMD_REQUEST | 11221 F_FW_CMD_WRITE); 11222 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11223 11224 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11225 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11226 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 11227 cmd.u.params.ch = channel; 11228 cmd.u.params.rate = ratemode; /* REL or ABS */ 11229 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 11230 11231 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11232 NULL, sleep_ok); 11233 } 11234 11235 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 11236 int weight, int sleep_ok) 11237 { 11238 struct fw_sched_cmd cmd; 11239 11240 if (weight < 0 || weight > 100) 11241 return -EINVAL; 11242 11243 memset(&cmd, 0, sizeof(cmd)); 11244 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11245 F_FW_CMD_REQUEST | 11246 F_FW_CMD_WRITE); 11247 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11248 11249 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11250 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11251 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 11252 cmd.u.params.ch = channel; 11253 cmd.u.params.cl = cl; 11254 cmd.u.params.weight = cpu_to_be16(weight); 11255 11256 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11257 NULL, sleep_ok); 11258 } 11259 11260 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 11261 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 11262 { 11263 struct fw_sched_cmd cmd; 11264 11265 memset(&cmd, 0, sizeof(cmd)); 11266 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11267 F_FW_CMD_REQUEST | 11268 F_FW_CMD_WRITE); 11269 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11270 11271 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11272 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11273 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 11274 cmd.u.params.mode = mode; 11275 cmd.u.params.ch = channel; 11276 cmd.u.params.cl = cl; 11277 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 11278 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 11279 cmd.u.params.max = cpu_to_be32(maxrate); 11280 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11281 11282 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11283 NULL, sleep_ok); 11284 } 11285 11286 /* 11287 * t4_config_watchdog - configure (enable/disable) a watchdog timer 11288 * @adapter: the adapter 11289 * @mbox: mailbox to use for the FW command 11290 * @pf: the PF owning the queue 11291 * @vf: the VF owning the queue 11292 * @timeout: watchdog timeout in ms 11293 * @action: watchdog timer / action 11294 * 11295 * There are separate watchdog timers for each possible watchdog 11296 * action. Configure one of the watchdog timers by setting a non-zero 11297 * timeout. Disable a watchdog timer by using a timeout of zero. 11298 */ 11299 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 11300 unsigned int pf, unsigned int vf, 11301 unsigned int timeout, unsigned int action) 11302 { 11303 struct fw_watchdog_cmd wdog; 11304 unsigned int ticks; 11305 11306 /* 11307 * The watchdog command expects a timeout in units of 10ms so we need 11308 * to convert it here (via rounding) and force a minimum of one 10ms 11309 * "tick" if the timeout is non-zero but the conversion results in 0 11310 * ticks. 11311 */ 11312 ticks = (timeout + 5)/10; 11313 if (timeout && !ticks) 11314 ticks = 1; 11315 11316 memset(&wdog, 0, sizeof wdog); 11317 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 11318 F_FW_CMD_REQUEST | 11319 F_FW_CMD_WRITE | 11320 V_FW_PARAMS_CMD_PFN(pf) | 11321 V_FW_PARAMS_CMD_VFN(vf)); 11322 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 11323 wdog.timeout = cpu_to_be32(ticks); 11324 wdog.action = cpu_to_be32(action); 11325 11326 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 11327 } 11328 11329 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 11330 { 11331 struct fw_devlog_cmd devlog_cmd; 11332 int ret; 11333 11334 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11335 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11336 F_FW_CMD_REQUEST | F_FW_CMD_READ); 11337 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11338 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11339 sizeof(devlog_cmd), &devlog_cmd); 11340 if (ret) 11341 return ret; 11342 11343 *level = devlog_cmd.level; 11344 return 0; 11345 } 11346 11347 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 11348 { 11349 struct fw_devlog_cmd devlog_cmd; 11350 11351 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11352 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11353 F_FW_CMD_REQUEST | 11354 F_FW_CMD_WRITE); 11355 devlog_cmd.level = level; 11356 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11357 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11358 sizeof(devlog_cmd), &devlog_cmd); 11359 } 11360 11361 int t4_configure_add_smac(struct adapter *adap) 11362 { 11363 unsigned int param, val; 11364 int ret = 0; 11365 11366 adap->params.smac_add_support = 0; 11367 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11368 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC)); 11369 /* Query FW to check if FW supports adding source mac address 11370 * to TCAM feature or not. 11371 * If FW returns 1, driver can use this feature and driver need to send 11372 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to 11373 * enable adding smac to TCAM. 11374 */ 11375 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11376 if (ret) 11377 return ret; 11378 11379 if (val == 1) { 11380 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 11381 ¶m, &val); 11382 if (!ret) 11383 /* Firmware allows adding explicit TCAM entries. 11384 * Save this internally. 11385 */ 11386 adap->params.smac_add_support = 1; 11387 } 11388 11389 return ret; 11390 } 11391 11392 int t4_configure_ringbb(struct adapter *adap) 11393 { 11394 unsigned int param, val; 11395 int ret = 0; 11396 11397 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11398 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE)); 11399 /* Query FW to check if FW supports ring switch feature or not. 11400 * If FW returns 1, driver can use this feature and driver need to send 11401 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to 11402 * enable the ring backbone configuration. 11403 */ 11404 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11405 if (ret < 0) { 11406 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n", 11407 ret); 11408 goto out; 11409 } 11410 11411 if (val != 1) { 11412 CH_ERR(adap, "FW doesnot support ringbackbone features\n"); 11413 goto out; 11414 } 11415 11416 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11417 if (ret < 0) { 11418 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n", 11419 ret); 11420 goto out; 11421 } 11422 11423 out: 11424 return ret; 11425 } 11426 11427 /* 11428 * t4_set_vlan_acl - Set a VLAN id for the specified VF 11429 * @adapter: the adapter 11430 * @mbox: mailbox to use for the FW command 11431 * @vf: one of the VFs instantiated by the specified PF 11432 * @vlan: The vlanid to be set 11433 * 11434 */ 11435 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 11436 u16 vlan) 11437 { 11438 struct fw_acl_vlan_cmd vlan_cmd; 11439 unsigned int enable; 11440 11441 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); 11442 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); 11443 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) | 11444 F_FW_CMD_REQUEST | 11445 F_FW_CMD_WRITE | 11446 F_FW_CMD_EXEC | 11447 V_FW_ACL_VLAN_CMD_PFN(adap->pf) | 11448 V_FW_ACL_VLAN_CMD_VFN(vf)); 11449 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd)); 11450 /* Drop all packets that donot match vlan id */ 11451 vlan_cmd.dropnovlan_fm = (enable 11452 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN | 11453 F_FW_ACL_VLAN_CMD_FM) 11454 : 0); 11455 if (enable != 0) { 11456 vlan_cmd.nvlan = 1; 11457 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); 11458 } 11459 11460 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); 11461 } 11462 11463 /** 11464 * t4_del_mac - Removes the exact-match filter for a MAC address 11465 * @adap: the adapter 11466 * @mbox: mailbox to use for the FW command 11467 * @viid: the VI id 11468 * @addr: the MAC address value 11469 * @smac: if true, delete from only the smac region of MPS 11470 * 11471 * Modifies an exact-match filter and sets it to the new MAC address if 11472 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11473 * latter case the address is added persistently if @persist is %true. 11474 * 11475 * Returns a negative error number or the index of the filter with the new 11476 * MAC value. Note that this index may differ from @idx. 11477 */ 11478 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11479 const u8 *addr, bool smac) 11480 { 11481 int ret; 11482 struct fw_vi_mac_cmd c; 11483 struct fw_vi_mac_exact *p = c.u.exact; 11484 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11485 11486 memset(&c, 0, sizeof(c)); 11487 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11488 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11489 V_FW_VI_MAC_CMD_VIID(viid)); 11490 c.freemacs_to_len16 = cpu_to_be32( 11491 V_FW_CMD_LEN16(1) | 11492 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11493 11494 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11495 p->valid_to_idx = cpu_to_be16( 11496 F_FW_VI_MAC_CMD_VALID | 11497 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 11498 11499 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11500 if (ret == 0) { 11501 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11502 if (ret < max_mac_addr) 11503 return -ENOMEM; 11504 } 11505 11506 return ret; 11507 } 11508 11509 /** 11510 * t4_add_mac - Adds an exact-match filter for a MAC address 11511 * @adap: the adapter 11512 * @mbox: mailbox to use for the FW command 11513 * @viid: the VI id 11514 * @idx: index of existing filter for old value of MAC address, or -1 11515 * @addr: the new MAC address value 11516 * @persist: whether a new MAC allocation should be persistent 11517 * @add_smt: if true also add the address to the HW SMT 11518 * @smac: if true, update only the smac region of MPS 11519 * 11520 * Modifies an exact-match filter and sets it to the new MAC address if 11521 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11522 * latter case the address is added persistently if @persist is %true. 11523 * 11524 * Returns a negative error number or the index of the filter with the new 11525 * MAC value. Note that this index may differ from @idx. 11526 */ 11527 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11528 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac) 11529 { 11530 int ret, mode; 11531 struct fw_vi_mac_cmd c; 11532 struct fw_vi_mac_exact *p = c.u.exact; 11533 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11534 11535 if (idx < 0) /* new allocation */ 11536 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 11537 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 11538 11539 memset(&c, 0, sizeof(c)); 11540 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11541 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11542 V_FW_VI_MAC_CMD_VIID(viid)); 11543 c.freemacs_to_len16 = cpu_to_be32( 11544 V_FW_CMD_LEN16(1) | 11545 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11546 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 11547 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 11548 V_FW_VI_MAC_CMD_IDX(idx)); 11549 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11550 11551 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11552 if (ret == 0) { 11553 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11554 if (ret >= max_mac_addr) 11555 return -ENOMEM; 11556 if (smt_idx) { 11557 /* Does fw supports returning smt_idx? */ 11558 if (adap->params.viid_smt_extn_support) 11559 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 11560 else { 11561 /* In T4/T5, SMT contains 256 SMAC entries 11562 * organized in 128 rows of 2 entries each. 11563 * In T6, SMT contains 256 SMAC entries in 11564 * 256 rows. 11565 */ 11566 if (chip_id(adap) <= CHELSIO_T5) 11567 *smt_idx = ((viid & M_FW_VIID_VIN) << 1); 11568 else 11569 *smt_idx = (viid & M_FW_VIID_VIN); 11570 } 11571 } 11572 } 11573 11574 return ret; 11575 } 11576