xref: /freebsd/sys/dev/cxgbe/common/t4_hw.c (revision f5ef5f675d9d9eb6e35ed9142d70ecf774456ad4)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
31 
32 #include "opt_inet.h"
33 
34 #include <sys/param.h>
35 #include <sys/eventhandler.h>
36 
37 #include "common.h"
38 #include "t4_regs.h"
39 #include "t4_regs_values.h"
40 #include "firmware/t4fw_interface.h"
41 
42 #undef msleep
43 #define msleep(x) do { \
44 	if (cold) \
45 		DELAY((x) * 1000); \
46 	else \
47 		pause("t4hw", (x) * hz / 1000); \
48 } while (0)
49 
50 /**
51  *	t4_wait_op_done_val - wait until an operation is completed
52  *	@adapter: the adapter performing the operation
53  *	@reg: the register to check for completion
54  *	@mask: a single-bit field within @reg that indicates completion
55  *	@polarity: the value of the field when the operation is completed
56  *	@attempts: number of check iterations
57  *	@delay: delay in usecs between iterations
58  *	@valp: where to store the value of the register at completion time
59  *
60  *	Wait until an operation is completed by checking a bit in a register
61  *	up to @attempts times.  If @valp is not NULL the value of the register
62  *	at the time it indicated completion is stored there.  Returns 0 if the
63  *	operation completes and	-EAGAIN	otherwise.
64  */
65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
66 			       int polarity, int attempts, int delay, u32 *valp)
67 {
68 	while (1) {
69 		u32 val = t4_read_reg(adapter, reg);
70 
71 		if (!!(val & mask) == polarity) {
72 			if (valp)
73 				*valp = val;
74 			return 0;
75 		}
76 		if (--attempts == 0)
77 			return -EAGAIN;
78 		if (delay)
79 			udelay(delay);
80 	}
81 }
82 
83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
84 				  int polarity, int attempts, int delay)
85 {
86 	return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
87 				   delay, NULL);
88 }
89 
90 /**
91  *	t4_set_reg_field - set a register field to a value
92  *	@adapter: the adapter to program
93  *	@addr: the register address
94  *	@mask: specifies the portion of the register to modify
95  *	@val: the new value for the register field
96  *
97  *	Sets a register field specified by the supplied mask to the
98  *	given value.
99  */
100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
101 		      u32 val)
102 {
103 	u32 v = t4_read_reg(adapter, addr) & ~mask;
104 
105 	t4_write_reg(adapter, addr, v | val);
106 	(void) t4_read_reg(adapter, addr);      /* flush */
107 }
108 
109 /**
110  *	t4_read_indirect - read indirectly addressed registers
111  *	@adap: the adapter
112  *	@addr_reg: register holding the indirect address
113  *	@data_reg: register holding the value of the indirect register
114  *	@vals: where the read register values are stored
115  *	@nregs: how many indirect registers to read
116  *	@start_idx: index of first indirect register to read
117  *
118  *	Reads registers that are accessed indirectly through an address/data
119  *	register pair.
120  */
121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
122 			     unsigned int data_reg, u32 *vals,
123 			     unsigned int nregs, unsigned int start_idx)
124 {
125 	while (nregs--) {
126 		t4_write_reg(adap, addr_reg, start_idx);
127 		*vals++ = t4_read_reg(adap, data_reg);
128 		start_idx++;
129 	}
130 }
131 
132 /**
133  *	t4_write_indirect - write indirectly addressed registers
134  *	@adap: the adapter
135  *	@addr_reg: register holding the indirect addresses
136  *	@data_reg: register holding the value for the indirect registers
137  *	@vals: values to write
138  *	@nregs: how many indirect registers to write
139  *	@start_idx: address of first indirect register to write
140  *
141  *	Writes a sequential block of registers that are accessed indirectly
142  *	through an address/data register pair.
143  */
144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
145 		       unsigned int data_reg, const u32 *vals,
146 		       unsigned int nregs, unsigned int start_idx)
147 {
148 	while (nregs--) {
149 		t4_write_reg(adap, addr_reg, start_idx++);
150 		t4_write_reg(adap, data_reg, *vals++);
151 	}
152 }
153 
154 /*
155  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
156  * mechanism.  This guarantees that we get the real value even if we're
157  * operating within a Virtual Machine and the Hypervisor is trapping our
158  * Configuration Space accesses.
159  *
160  * N.B. This routine should only be used as a last resort: the firmware uses
161  *      the backdoor registers on a regular basis and we can end up
162  *      conflicting with it's uses!
163  */
164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
165 {
166 	u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
167 	u32 val;
168 
169 	if (chip_id(adap) <= CHELSIO_T5)
170 		req |= F_ENABLE;
171 	else
172 		req |= F_T6_ENABLE;
173 
174 	if (is_t4(adap))
175 		req |= F_LOCALCFG;
176 
177 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
178 	val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
179 
180 	/*
181 	 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
182 	 * Configuration Space read.  (None of the other fields matter when
183 	 * F_ENABLE is 0 so a simple register write is easier than a
184 	 * read-modify-write via t4_set_reg_field().)
185 	 */
186 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
187 
188 	return val;
189 }
190 
191 /*
192  * t4_report_fw_error - report firmware error
193  * @adap: the adapter
194  *
195  * The adapter firmware can indicate error conditions to the host.
196  * If the firmware has indicated an error, print out the reason for
197  * the firmware error.
198  */
199 static void t4_report_fw_error(struct adapter *adap)
200 {
201 	static const char *const reason[] = {
202 		"Crash",			/* PCIE_FW_EVAL_CRASH */
203 		"During Device Preparation",	/* PCIE_FW_EVAL_PREP */
204 		"During Device Configuration",	/* PCIE_FW_EVAL_CONF */
205 		"During Device Initialization",	/* PCIE_FW_EVAL_INIT */
206 		"Unexpected Event",		/* PCIE_FW_EVAL_UNEXPECTEDEVENT */
207 		"Insufficient Airflow",		/* PCIE_FW_EVAL_OVERHEAT */
208 		"Device Shutdown",		/* PCIE_FW_EVAL_DEVICESHUTDOWN */
209 		"Reserved",			/* reserved */
210 	};
211 	u32 pcie_fw;
212 
213 	pcie_fw = t4_read_reg(adap, A_PCIE_FW);
214 	if (pcie_fw & F_PCIE_FW_ERR) {
215 		adap->flags &= ~FW_OK;
216 		CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n",
217 		    reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw);
218 		if (pcie_fw != 0xffffffff)
219 			t4_os_dump_devlog(adap);
220 	}
221 }
222 
223 /*
224  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
225  */
226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
227 			 u32 mbox_addr)
228 {
229 	for ( ; nflit; nflit--, mbox_addr += 8)
230 		*rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
231 }
232 
233 /*
234  * Handle a FW assertion reported in a mailbox.
235  */
236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
237 {
238 	CH_ALERT(adap,
239 		  "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
240 		  asrt->u.assert.filename_0_7,
241 		  be32_to_cpu(asrt->u.assert.line),
242 		  be32_to_cpu(asrt->u.assert.x),
243 		  be32_to_cpu(asrt->u.assert.y));
244 }
245 
246 struct port_tx_state {
247 	uint64_t rx_pause;
248 	uint64_t tx_frames;
249 };
250 
251 static void
252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
253 {
254 	uint32_t rx_pause_reg, tx_frames_reg;
255 
256 	if (is_t4(sc)) {
257 		tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
258 		rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
259 	} else {
260 		tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
261 		rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
262 	}
263 
264 	tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
265 	tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
266 }
267 
268 static void
269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
270 {
271 	int i;
272 
273 	for_each_port(sc, i)
274 		read_tx_state_one(sc, i, &tx_state[i]);
275 }
276 
277 static void
278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
279 {
280 	uint32_t port_ctl_reg;
281 	uint64_t tx_frames, rx_pause;
282 	int i;
283 
284 	for_each_port(sc, i) {
285 		rx_pause = tx_state[i].rx_pause;
286 		tx_frames = tx_state[i].tx_frames;
287 		read_tx_state_one(sc, i, &tx_state[i]);	/* update */
288 
289 		if (is_t4(sc))
290 			port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL);
291 		else
292 			port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL);
293 		if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN &&
294 		    rx_pause != tx_state[i].rx_pause &&
295 		    tx_frames == tx_state[i].tx_frames) {
296 			t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
297 			mdelay(1);
298 			t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
299 		}
300 	}
301 }
302 
303 #define X_CIM_PF_NOACCESS 0xeeeeeeee
304 /**
305  *	t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
306  *	@adap: the adapter
307  *	@mbox: index of the mailbox to use
308  *	@cmd: the command to write
309  *	@size: command length in bytes
310  *	@rpl: where to optionally store the reply
311  *	@sleep_ok: if true we may sleep while awaiting command completion
312  *	@timeout: time to wait for command to finish before timing out
313  *		(negative implies @sleep_ok=false)
314  *
315  *	Sends the given command to FW through the selected mailbox and waits
316  *	for the FW to execute the command.  If @rpl is not %NULL it is used to
317  *	store the FW's reply to the command.  The command and its optional
318  *	reply are of the same length.  Some FW commands like RESET and
319  *	INITIALIZE can take a considerable amount of time to execute.
320  *	@sleep_ok determines whether we may sleep while awaiting the response.
321  *	If sleeping is allowed we use progressive backoff otherwise we spin.
322  *	Note that passing in a negative @timeout is an alternate mechanism
323  *	for specifying @sleep_ok=false.  This is useful when a higher level
324  *	interface allows for specification of @timeout but not @sleep_ok ...
325  *
326  *	The return value is 0 on success or a negative errno on failure.  A
327  *	failure can happen either because we are not able to execute the
328  *	command or FW executes it but signals an error.  In the latter case
329  *	the return value is the error code indicated by FW (negated).
330  */
331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
332 			    int size, void *rpl, bool sleep_ok, int timeout)
333 {
334 	/*
335 	 * We delay in small increments at first in an effort to maintain
336 	 * responsiveness for simple, fast executing commands but then back
337 	 * off to larger delays to a maximum retry delay.
338 	 */
339 	static const int delay[] = {
340 		1, 1, 3, 5, 10, 10, 20, 50, 100
341 	};
342 	u32 v;
343 	u64 res;
344 	int i, ms, delay_idx, ret, next_tx_check;
345 	u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
346 	u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
347 	u32 ctl;
348 	__be64 cmd_rpl[MBOX_LEN/8];
349 	u32 pcie_fw;
350 	struct port_tx_state tx_state[MAX_NPORTS];
351 
352 	if (adap->flags & CHK_MBOX_ACCESS)
353 		ASSERT_SYNCHRONIZED_OP(adap);
354 
355 	if (size <= 0 || (size & 15) || size > MBOX_LEN)
356 		return -EINVAL;
357 
358 	if (adap->flags & IS_VF) {
359 		if (is_t6(adap))
360 			data_reg = FW_T6VF_MBDATA_BASE_ADDR;
361 		else
362 			data_reg = FW_T4VF_MBDATA_BASE_ADDR;
363 		ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
364 	}
365 
366 	/*
367 	 * If we have a negative timeout, that implies that we can't sleep.
368 	 */
369 	if (timeout < 0) {
370 		sleep_ok = false;
371 		timeout = -timeout;
372 	}
373 
374 	/*
375 	 * Attempt to gain access to the mailbox.
376 	 */
377 	for (i = 0; i < 4; i++) {
378 		ctl = t4_read_reg(adap, ctl_reg);
379 		v = G_MBOWNER(ctl);
380 		if (v != X_MBOWNER_NONE)
381 			break;
382 	}
383 
384 	/*
385 	 * If we were unable to gain access, report the error to our caller.
386 	 */
387 	if (v != X_MBOWNER_PL) {
388 		t4_report_fw_error(adap);
389 		ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
390 		return ret;
391 	}
392 
393 	/*
394 	 * If we gain ownership of the mailbox and there's a "valid" message
395 	 * in it, this is likely an asynchronous error message from the
396 	 * firmware.  So we'll report that and then proceed on with attempting
397 	 * to issue our own command ... which may well fail if the error
398 	 * presaged the firmware crashing ...
399 	 */
400 	if (ctl & F_MBMSGVALID) {
401 		CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true);
402 	}
403 
404 	/*
405 	 * Copy in the new mailbox command and send it on its way ...
406 	 */
407 	memset(cmd_rpl, 0, sizeof(cmd_rpl));
408 	memcpy(cmd_rpl, cmd, size);
409 	CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false);
410 	for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++)
411 		t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i]));
412 
413 	if (adap->flags & IS_VF) {
414 		/*
415 		 * For the VFs, the Mailbox Data "registers" are
416 		 * actually backed by T4's "MA" interface rather than
417 		 * PL Registers (as is the case for the PFs).  Because
418 		 * these are in different coherency domains, the write
419 		 * to the VF's PL-register-backed Mailbox Control can
420 		 * race in front of the writes to the MA-backed VF
421 		 * Mailbox Data "registers".  So we need to do a
422 		 * read-back on at least one byte of the VF Mailbox
423 		 * Data registers before doing the write to the VF
424 		 * Mailbox Control register.
425 		 */
426 		t4_read_reg(adap, data_reg);
427 	}
428 
429 	t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
430 	read_tx_state(adap, &tx_state[0]);	/* also flushes the write_reg */
431 	next_tx_check = 1000;
432 	delay_idx = 0;
433 	ms = delay[0];
434 
435 	/*
436 	 * Loop waiting for the reply; bail out if we time out or the firmware
437 	 * reports an error.
438 	 */
439 	pcie_fw = 0;
440 	for (i = 0; i < timeout; i += ms) {
441 		if (!(adap->flags & IS_VF)) {
442 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
443 			if (pcie_fw & F_PCIE_FW_ERR)
444 				break;
445 		}
446 
447 		if (i >= next_tx_check) {
448 			check_tx_state(adap, &tx_state[0]);
449 			next_tx_check = i + 1000;
450 		}
451 
452 		if (sleep_ok) {
453 			ms = delay[delay_idx];  /* last element may repeat */
454 			if (delay_idx < ARRAY_SIZE(delay) - 1)
455 				delay_idx++;
456 			msleep(ms);
457 		} else {
458 			mdelay(ms);
459 		}
460 
461 		v = t4_read_reg(adap, ctl_reg);
462 		if (v == X_CIM_PF_NOACCESS)
463 			continue;
464 		if (G_MBOWNER(v) == X_MBOWNER_PL) {
465 			if (!(v & F_MBMSGVALID)) {
466 				t4_write_reg(adap, ctl_reg,
467 					     V_MBOWNER(X_MBOWNER_NONE));
468 				continue;
469 			}
470 
471 			/*
472 			 * Retrieve the command reply and release the mailbox.
473 			 */
474 			get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
475 			CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false);
476 			t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
477 
478 			res = be64_to_cpu(cmd_rpl[0]);
479 			if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
480 				fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
481 				res = V_FW_CMD_RETVAL(EIO);
482 			} else if (rpl)
483 				memcpy(rpl, cmd_rpl, size);
484 			return -G_FW_CMD_RETVAL((int)res);
485 		}
486 	}
487 
488 	/*
489 	 * We timed out waiting for a reply to our mailbox command.  Report
490 	 * the error and also check to see if the firmware reported any
491 	 * errors ...
492 	 */
493 	CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n",
494 	    *(const u8 *)cmd, mbox, pcie_fw);
495 	CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true);
496 	CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true);
497 
498 	if (pcie_fw & F_PCIE_FW_ERR) {
499 		ret = -ENXIO;
500 		t4_report_fw_error(adap);
501 	} else {
502 		ret = -ETIMEDOUT;
503 		t4_os_dump_devlog(adap);
504 	}
505 
506 	t4_fatal_err(adap, true);
507 	return ret;
508 }
509 
510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
511 		    void *rpl, bool sleep_ok)
512 {
513 		return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
514 					       sleep_ok, FW_CMD_MAX_TIMEOUT);
515 
516 }
517 
518 static int t4_edc_err_read(struct adapter *adap, int idx)
519 {
520 	u32 edc_ecc_err_addr_reg;
521 	u32 edc_bist_status_rdata_reg;
522 
523 	if (is_t4(adap)) {
524 		CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
525 		return 0;
526 	}
527 	if (idx != MEM_EDC0 && idx != MEM_EDC1) {
528 		CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
529 		return 0;
530 	}
531 
532 	edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
533 	edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
534 
535 	CH_WARN(adap,
536 		"edc%d err addr 0x%x: 0x%x.\n",
537 		idx, edc_ecc_err_addr_reg,
538 		t4_read_reg(adap, edc_ecc_err_addr_reg));
539 	CH_WARN(adap,
540 	 	"bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
541 		edc_bist_status_rdata_reg,
542 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
543 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
544 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
545 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
546 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
547 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
548 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
549 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
550 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
551 
552 	return 0;
553 }
554 
555 /**
556  *	t4_mc_read - read from MC through backdoor accesses
557  *	@adap: the adapter
558  *	@idx: which MC to access
559  *	@addr: address of first byte requested
560  *	@data: 64 bytes of data containing the requested address
561  *	@ecc: where to store the corresponding 64-bit ECC word
562  *
563  *	Read 64 bytes of data from MC starting at a 64-byte-aligned address
564  *	that covers the requested address @addr.  If @parity is not %NULL it
565  *	is assigned the 64-bit ECC word for the read data.
566  */
567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
568 {
569 	int i;
570 	u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
571 	u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
572 
573 	if (is_t4(adap)) {
574 		mc_bist_cmd_reg = A_MC_BIST_CMD;
575 		mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
576 		mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
577 		mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
578 		mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
579 	} else {
580 		mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
581 		mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
582 		mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
583 		mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
584 						  idx);
585 		mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
586 						  idx);
587 	}
588 
589 	if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
590 		return -EBUSY;
591 	t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
592 	t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
593 	t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
594 	t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
595 		     F_START_BIST | V_BIST_CMD_GAP(1));
596 	i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
597 	if (i)
598 		return i;
599 
600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
601 
602 	for (i = 15; i >= 0; i--)
603 		*data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
604 	if (ecc)
605 		*ecc = t4_read_reg64(adap, MC_DATA(16));
606 #undef MC_DATA
607 	return 0;
608 }
609 
610 /**
611  *	t4_edc_read - read from EDC through backdoor accesses
612  *	@adap: the adapter
613  *	@idx: which EDC to access
614  *	@addr: address of first byte requested
615  *	@data: 64 bytes of data containing the requested address
616  *	@ecc: where to store the corresponding 64-bit ECC word
617  *
618  *	Read 64 bytes of data from EDC starting at a 64-byte-aligned address
619  *	that covers the requested address @addr.  If @parity is not %NULL it
620  *	is assigned the 64-bit ECC word for the read data.
621  */
622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
623 {
624 	int i;
625 	u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
626 	u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
627 
628 	if (is_t4(adap)) {
629 		edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
630 		edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
631 		edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
632 		edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
633 						    idx);
634 		edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
635 						    idx);
636 	} else {
637 /*
638  * These macro are missing in t4_regs.h file.
639  * Added temporarily for testing.
640  */
641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
643 		edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
644 		edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
645 		edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
646 		edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
647 						    idx);
648 		edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
649 						    idx);
650 #undef EDC_REG_T5
651 #undef EDC_STRIDE_T5
652 	}
653 
654 	if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
655 		return -EBUSY;
656 	t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
657 	t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
658 	t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
659 	t4_write_reg(adap, edc_bist_cmd_reg,
660 		     V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
661 	i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
662 	if (i)
663 		return i;
664 
665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
666 
667 	for (i = 15; i >= 0; i--)
668 		*data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
669 	if (ecc)
670 		*ecc = t4_read_reg64(adap, EDC_DATA(16));
671 #undef EDC_DATA
672 	return 0;
673 }
674 
675 /**
676  *	t4_mem_read - read EDC 0, EDC 1 or MC into buffer
677  *	@adap: the adapter
678  *	@mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
679  *	@addr: address within indicated memory type
680  *	@len: amount of memory to read
681  *	@buf: host memory buffer
682  *
683  *	Reads an [almost] arbitrary memory region in the firmware: the
684  *	firmware memory address, length and host buffer must be aligned on
685  *	32-bit boudaries.  The memory is returned as a raw byte sequence from
686  *	the firmware's memory.  If this memory contains data structures which
687  *	contain multi-byte integers, it's the callers responsibility to
688  *	perform appropriate byte order conversions.
689  */
690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
691 		__be32 *buf)
692 {
693 	u32 pos, start, end, offset;
694 	int ret;
695 
696 	/*
697 	 * Argument sanity checks ...
698 	 */
699 	if ((addr & 0x3) || (len & 0x3))
700 		return -EINVAL;
701 
702 	/*
703 	 * The underlaying EDC/MC read routines read 64 bytes at a time so we
704 	 * need to round down the start and round up the end.  We'll start
705 	 * copying out of the first line at (addr - start) a word at a time.
706 	 */
707 	start = rounddown2(addr, 64);
708 	end = roundup2(addr + len, 64);
709 	offset = (addr - start)/sizeof(__be32);
710 
711 	for (pos = start; pos < end; pos += 64, offset = 0) {
712 		__be32 data[16];
713 
714 		/*
715 		 * Read the chip's memory block and bail if there's an error.
716 		 */
717 		if ((mtype == MEM_MC) || (mtype == MEM_MC1))
718 			ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
719 		else
720 			ret = t4_edc_read(adap, mtype, pos, data, NULL);
721 		if (ret)
722 			return ret;
723 
724 		/*
725 		 * Copy the data into the caller's memory buffer.
726 		 */
727 		while (offset < 16 && len > 0) {
728 			*buf++ = data[offset++];
729 			len -= sizeof(__be32);
730 		}
731 	}
732 
733 	return 0;
734 }
735 
736 /*
737  * Return the specified PCI-E Configuration Space register from our Physical
738  * Function.  We try first via a Firmware LDST Command (if fw_attach != 0)
739  * since we prefer to let the firmware own all of these registers, but if that
740  * fails we go for it directly ourselves.
741  */
742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
743 {
744 
745 	/*
746 	 * If fw_attach != 0, construct and send the Firmware LDST Command to
747 	 * retrieve the specified PCI-E Configuration Space register.
748 	 */
749 	if (drv_fw_attach != 0) {
750 		struct fw_ldst_cmd ldst_cmd;
751 		int ret;
752 
753 		memset(&ldst_cmd, 0, sizeof(ldst_cmd));
754 		ldst_cmd.op_to_addrspace =
755 			cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
756 				    F_FW_CMD_REQUEST |
757 				    F_FW_CMD_READ |
758 				    V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
759 		ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
760 		ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
761 		ldst_cmd.u.pcie.ctrl_to_fn =
762 			(F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
763 		ldst_cmd.u.pcie.r = reg;
764 
765 		/*
766 		 * If the LDST Command succeeds, return the result, otherwise
767 		 * fall through to reading it directly ourselves ...
768 		 */
769 		ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
770 				 &ldst_cmd);
771 		if (ret == 0)
772 			return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
773 
774 		CH_WARN(adap, "Firmware failed to return "
775 			"Configuration Space register %d, err = %d\n",
776 			reg, -ret);
777 	}
778 
779 	/*
780 	 * Read the desired Configuration Space register via the PCI-E
781 	 * Backdoor mechanism.
782 	 */
783 	return t4_hw_pci_read_cfg4(adap, reg);
784 }
785 
786 /**
787  *	t4_get_regs_len - return the size of the chips register set
788  *	@adapter: the adapter
789  *
790  *	Returns the size of the chip's BAR0 register space.
791  */
792 unsigned int t4_get_regs_len(struct adapter *adapter)
793 {
794 	unsigned int chip_version = chip_id(adapter);
795 
796 	switch (chip_version) {
797 	case CHELSIO_T4:
798 		if (adapter->flags & IS_VF)
799 			return FW_T4VF_REGMAP_SIZE;
800 		return T4_REGMAP_SIZE;
801 
802 	case CHELSIO_T5:
803 	case CHELSIO_T6:
804 		if (adapter->flags & IS_VF)
805 			return FW_T4VF_REGMAP_SIZE;
806 		return T5_REGMAP_SIZE;
807 	}
808 
809 	CH_ERR(adapter,
810 		"Unsupported chip version %d\n", chip_version);
811 	return 0;
812 }
813 
814 /**
815  *	t4_get_regs - read chip registers into provided buffer
816  *	@adap: the adapter
817  *	@buf: register buffer
818  *	@buf_size: size (in bytes) of register buffer
819  *
820  *	If the provided register buffer isn't large enough for the chip's
821  *	full register range, the register dump will be truncated to the
822  *	register buffer's size.
823  */
824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
825 {
826 	static const unsigned int t4_reg_ranges[] = {
827 		0x1008, 0x1108,
828 		0x1180, 0x1184,
829 		0x1190, 0x1194,
830 		0x11a0, 0x11a4,
831 		0x11b0, 0x11b4,
832 		0x11fc, 0x123c,
833 		0x1300, 0x173c,
834 		0x1800, 0x18fc,
835 		0x3000, 0x30d8,
836 		0x30e0, 0x30e4,
837 		0x30ec, 0x5910,
838 		0x5920, 0x5924,
839 		0x5960, 0x5960,
840 		0x5968, 0x5968,
841 		0x5970, 0x5970,
842 		0x5978, 0x5978,
843 		0x5980, 0x5980,
844 		0x5988, 0x5988,
845 		0x5990, 0x5990,
846 		0x5998, 0x5998,
847 		0x59a0, 0x59d4,
848 		0x5a00, 0x5ae0,
849 		0x5ae8, 0x5ae8,
850 		0x5af0, 0x5af0,
851 		0x5af8, 0x5af8,
852 		0x6000, 0x6098,
853 		0x6100, 0x6150,
854 		0x6200, 0x6208,
855 		0x6240, 0x6248,
856 		0x6280, 0x62b0,
857 		0x62c0, 0x6338,
858 		0x6370, 0x638c,
859 		0x6400, 0x643c,
860 		0x6500, 0x6524,
861 		0x6a00, 0x6a04,
862 		0x6a14, 0x6a38,
863 		0x6a60, 0x6a70,
864 		0x6a78, 0x6a78,
865 		0x6b00, 0x6b0c,
866 		0x6b1c, 0x6b84,
867 		0x6bf0, 0x6bf8,
868 		0x6c00, 0x6c0c,
869 		0x6c1c, 0x6c84,
870 		0x6cf0, 0x6cf8,
871 		0x6d00, 0x6d0c,
872 		0x6d1c, 0x6d84,
873 		0x6df0, 0x6df8,
874 		0x6e00, 0x6e0c,
875 		0x6e1c, 0x6e84,
876 		0x6ef0, 0x6ef8,
877 		0x6f00, 0x6f0c,
878 		0x6f1c, 0x6f84,
879 		0x6ff0, 0x6ff8,
880 		0x7000, 0x700c,
881 		0x701c, 0x7084,
882 		0x70f0, 0x70f8,
883 		0x7100, 0x710c,
884 		0x711c, 0x7184,
885 		0x71f0, 0x71f8,
886 		0x7200, 0x720c,
887 		0x721c, 0x7284,
888 		0x72f0, 0x72f8,
889 		0x7300, 0x730c,
890 		0x731c, 0x7384,
891 		0x73f0, 0x73f8,
892 		0x7400, 0x7450,
893 		0x7500, 0x7530,
894 		0x7600, 0x760c,
895 		0x7614, 0x761c,
896 		0x7680, 0x76cc,
897 		0x7700, 0x7798,
898 		0x77c0, 0x77fc,
899 		0x7900, 0x79fc,
900 		0x7b00, 0x7b58,
901 		0x7b60, 0x7b84,
902 		0x7b8c, 0x7c38,
903 		0x7d00, 0x7d38,
904 		0x7d40, 0x7d80,
905 		0x7d8c, 0x7ddc,
906 		0x7de4, 0x7e04,
907 		0x7e10, 0x7e1c,
908 		0x7e24, 0x7e38,
909 		0x7e40, 0x7e44,
910 		0x7e4c, 0x7e78,
911 		0x7e80, 0x7ea4,
912 		0x7eac, 0x7edc,
913 		0x7ee8, 0x7efc,
914 		0x8dc0, 0x8e04,
915 		0x8e10, 0x8e1c,
916 		0x8e30, 0x8e78,
917 		0x8ea0, 0x8eb8,
918 		0x8ec0, 0x8f6c,
919 		0x8fc0, 0x9008,
920 		0x9010, 0x9058,
921 		0x9060, 0x9060,
922 		0x9068, 0x9074,
923 		0x90fc, 0x90fc,
924 		0x9400, 0x9408,
925 		0x9410, 0x9458,
926 		0x9600, 0x9600,
927 		0x9608, 0x9638,
928 		0x9640, 0x96bc,
929 		0x9800, 0x9808,
930 		0x9820, 0x983c,
931 		0x9850, 0x9864,
932 		0x9c00, 0x9c6c,
933 		0x9c80, 0x9cec,
934 		0x9d00, 0x9d6c,
935 		0x9d80, 0x9dec,
936 		0x9e00, 0x9e6c,
937 		0x9e80, 0x9eec,
938 		0x9f00, 0x9f6c,
939 		0x9f80, 0x9fec,
940 		0xd004, 0xd004,
941 		0xd010, 0xd03c,
942 		0xdfc0, 0xdfe0,
943 		0xe000, 0xea7c,
944 		0xf000, 0x11110,
945 		0x11118, 0x11190,
946 		0x19040, 0x1906c,
947 		0x19078, 0x19080,
948 		0x1908c, 0x190e4,
949 		0x190f0, 0x190f8,
950 		0x19100, 0x19110,
951 		0x19120, 0x19124,
952 		0x19150, 0x19194,
953 		0x1919c, 0x191b0,
954 		0x191d0, 0x191e8,
955 		0x19238, 0x1924c,
956 		0x193f8, 0x1943c,
957 		0x1944c, 0x19474,
958 		0x19490, 0x194e0,
959 		0x194f0, 0x194f8,
960 		0x19800, 0x19c08,
961 		0x19c10, 0x19c90,
962 		0x19ca0, 0x19ce4,
963 		0x19cf0, 0x19d40,
964 		0x19d50, 0x19d94,
965 		0x19da0, 0x19de8,
966 		0x19df0, 0x19e40,
967 		0x19e50, 0x19e90,
968 		0x19ea0, 0x19f4c,
969 		0x1a000, 0x1a004,
970 		0x1a010, 0x1a06c,
971 		0x1a0b0, 0x1a0e4,
972 		0x1a0ec, 0x1a0f4,
973 		0x1a100, 0x1a108,
974 		0x1a114, 0x1a120,
975 		0x1a128, 0x1a130,
976 		0x1a138, 0x1a138,
977 		0x1a190, 0x1a1c4,
978 		0x1a1fc, 0x1a1fc,
979 		0x1e040, 0x1e04c,
980 		0x1e284, 0x1e28c,
981 		0x1e2c0, 0x1e2c0,
982 		0x1e2e0, 0x1e2e0,
983 		0x1e300, 0x1e384,
984 		0x1e3c0, 0x1e3c8,
985 		0x1e440, 0x1e44c,
986 		0x1e684, 0x1e68c,
987 		0x1e6c0, 0x1e6c0,
988 		0x1e6e0, 0x1e6e0,
989 		0x1e700, 0x1e784,
990 		0x1e7c0, 0x1e7c8,
991 		0x1e840, 0x1e84c,
992 		0x1ea84, 0x1ea8c,
993 		0x1eac0, 0x1eac0,
994 		0x1eae0, 0x1eae0,
995 		0x1eb00, 0x1eb84,
996 		0x1ebc0, 0x1ebc8,
997 		0x1ec40, 0x1ec4c,
998 		0x1ee84, 0x1ee8c,
999 		0x1eec0, 0x1eec0,
1000 		0x1eee0, 0x1eee0,
1001 		0x1ef00, 0x1ef84,
1002 		0x1efc0, 0x1efc8,
1003 		0x1f040, 0x1f04c,
1004 		0x1f284, 0x1f28c,
1005 		0x1f2c0, 0x1f2c0,
1006 		0x1f2e0, 0x1f2e0,
1007 		0x1f300, 0x1f384,
1008 		0x1f3c0, 0x1f3c8,
1009 		0x1f440, 0x1f44c,
1010 		0x1f684, 0x1f68c,
1011 		0x1f6c0, 0x1f6c0,
1012 		0x1f6e0, 0x1f6e0,
1013 		0x1f700, 0x1f784,
1014 		0x1f7c0, 0x1f7c8,
1015 		0x1f840, 0x1f84c,
1016 		0x1fa84, 0x1fa8c,
1017 		0x1fac0, 0x1fac0,
1018 		0x1fae0, 0x1fae0,
1019 		0x1fb00, 0x1fb84,
1020 		0x1fbc0, 0x1fbc8,
1021 		0x1fc40, 0x1fc4c,
1022 		0x1fe84, 0x1fe8c,
1023 		0x1fec0, 0x1fec0,
1024 		0x1fee0, 0x1fee0,
1025 		0x1ff00, 0x1ff84,
1026 		0x1ffc0, 0x1ffc8,
1027 		0x20000, 0x2002c,
1028 		0x20100, 0x2013c,
1029 		0x20190, 0x201a0,
1030 		0x201a8, 0x201b8,
1031 		0x201c4, 0x201c8,
1032 		0x20200, 0x20318,
1033 		0x20400, 0x204b4,
1034 		0x204c0, 0x20528,
1035 		0x20540, 0x20614,
1036 		0x21000, 0x21040,
1037 		0x2104c, 0x21060,
1038 		0x210c0, 0x210ec,
1039 		0x21200, 0x21268,
1040 		0x21270, 0x21284,
1041 		0x212fc, 0x21388,
1042 		0x21400, 0x21404,
1043 		0x21500, 0x21500,
1044 		0x21510, 0x21518,
1045 		0x2152c, 0x21530,
1046 		0x2153c, 0x2153c,
1047 		0x21550, 0x21554,
1048 		0x21600, 0x21600,
1049 		0x21608, 0x2161c,
1050 		0x21624, 0x21628,
1051 		0x21630, 0x21634,
1052 		0x2163c, 0x2163c,
1053 		0x21700, 0x2171c,
1054 		0x21780, 0x2178c,
1055 		0x21800, 0x21818,
1056 		0x21820, 0x21828,
1057 		0x21830, 0x21848,
1058 		0x21850, 0x21854,
1059 		0x21860, 0x21868,
1060 		0x21870, 0x21870,
1061 		0x21878, 0x21898,
1062 		0x218a0, 0x218a8,
1063 		0x218b0, 0x218c8,
1064 		0x218d0, 0x218d4,
1065 		0x218e0, 0x218e8,
1066 		0x218f0, 0x218f0,
1067 		0x218f8, 0x21a18,
1068 		0x21a20, 0x21a28,
1069 		0x21a30, 0x21a48,
1070 		0x21a50, 0x21a54,
1071 		0x21a60, 0x21a68,
1072 		0x21a70, 0x21a70,
1073 		0x21a78, 0x21a98,
1074 		0x21aa0, 0x21aa8,
1075 		0x21ab0, 0x21ac8,
1076 		0x21ad0, 0x21ad4,
1077 		0x21ae0, 0x21ae8,
1078 		0x21af0, 0x21af0,
1079 		0x21af8, 0x21c18,
1080 		0x21c20, 0x21c20,
1081 		0x21c28, 0x21c30,
1082 		0x21c38, 0x21c38,
1083 		0x21c80, 0x21c98,
1084 		0x21ca0, 0x21ca8,
1085 		0x21cb0, 0x21cc8,
1086 		0x21cd0, 0x21cd4,
1087 		0x21ce0, 0x21ce8,
1088 		0x21cf0, 0x21cf0,
1089 		0x21cf8, 0x21d7c,
1090 		0x21e00, 0x21e04,
1091 		0x22000, 0x2202c,
1092 		0x22100, 0x2213c,
1093 		0x22190, 0x221a0,
1094 		0x221a8, 0x221b8,
1095 		0x221c4, 0x221c8,
1096 		0x22200, 0x22318,
1097 		0x22400, 0x224b4,
1098 		0x224c0, 0x22528,
1099 		0x22540, 0x22614,
1100 		0x23000, 0x23040,
1101 		0x2304c, 0x23060,
1102 		0x230c0, 0x230ec,
1103 		0x23200, 0x23268,
1104 		0x23270, 0x23284,
1105 		0x232fc, 0x23388,
1106 		0x23400, 0x23404,
1107 		0x23500, 0x23500,
1108 		0x23510, 0x23518,
1109 		0x2352c, 0x23530,
1110 		0x2353c, 0x2353c,
1111 		0x23550, 0x23554,
1112 		0x23600, 0x23600,
1113 		0x23608, 0x2361c,
1114 		0x23624, 0x23628,
1115 		0x23630, 0x23634,
1116 		0x2363c, 0x2363c,
1117 		0x23700, 0x2371c,
1118 		0x23780, 0x2378c,
1119 		0x23800, 0x23818,
1120 		0x23820, 0x23828,
1121 		0x23830, 0x23848,
1122 		0x23850, 0x23854,
1123 		0x23860, 0x23868,
1124 		0x23870, 0x23870,
1125 		0x23878, 0x23898,
1126 		0x238a0, 0x238a8,
1127 		0x238b0, 0x238c8,
1128 		0x238d0, 0x238d4,
1129 		0x238e0, 0x238e8,
1130 		0x238f0, 0x238f0,
1131 		0x238f8, 0x23a18,
1132 		0x23a20, 0x23a28,
1133 		0x23a30, 0x23a48,
1134 		0x23a50, 0x23a54,
1135 		0x23a60, 0x23a68,
1136 		0x23a70, 0x23a70,
1137 		0x23a78, 0x23a98,
1138 		0x23aa0, 0x23aa8,
1139 		0x23ab0, 0x23ac8,
1140 		0x23ad0, 0x23ad4,
1141 		0x23ae0, 0x23ae8,
1142 		0x23af0, 0x23af0,
1143 		0x23af8, 0x23c18,
1144 		0x23c20, 0x23c20,
1145 		0x23c28, 0x23c30,
1146 		0x23c38, 0x23c38,
1147 		0x23c80, 0x23c98,
1148 		0x23ca0, 0x23ca8,
1149 		0x23cb0, 0x23cc8,
1150 		0x23cd0, 0x23cd4,
1151 		0x23ce0, 0x23ce8,
1152 		0x23cf0, 0x23cf0,
1153 		0x23cf8, 0x23d7c,
1154 		0x23e00, 0x23e04,
1155 		0x24000, 0x2402c,
1156 		0x24100, 0x2413c,
1157 		0x24190, 0x241a0,
1158 		0x241a8, 0x241b8,
1159 		0x241c4, 0x241c8,
1160 		0x24200, 0x24318,
1161 		0x24400, 0x244b4,
1162 		0x244c0, 0x24528,
1163 		0x24540, 0x24614,
1164 		0x25000, 0x25040,
1165 		0x2504c, 0x25060,
1166 		0x250c0, 0x250ec,
1167 		0x25200, 0x25268,
1168 		0x25270, 0x25284,
1169 		0x252fc, 0x25388,
1170 		0x25400, 0x25404,
1171 		0x25500, 0x25500,
1172 		0x25510, 0x25518,
1173 		0x2552c, 0x25530,
1174 		0x2553c, 0x2553c,
1175 		0x25550, 0x25554,
1176 		0x25600, 0x25600,
1177 		0x25608, 0x2561c,
1178 		0x25624, 0x25628,
1179 		0x25630, 0x25634,
1180 		0x2563c, 0x2563c,
1181 		0x25700, 0x2571c,
1182 		0x25780, 0x2578c,
1183 		0x25800, 0x25818,
1184 		0x25820, 0x25828,
1185 		0x25830, 0x25848,
1186 		0x25850, 0x25854,
1187 		0x25860, 0x25868,
1188 		0x25870, 0x25870,
1189 		0x25878, 0x25898,
1190 		0x258a0, 0x258a8,
1191 		0x258b0, 0x258c8,
1192 		0x258d0, 0x258d4,
1193 		0x258e0, 0x258e8,
1194 		0x258f0, 0x258f0,
1195 		0x258f8, 0x25a18,
1196 		0x25a20, 0x25a28,
1197 		0x25a30, 0x25a48,
1198 		0x25a50, 0x25a54,
1199 		0x25a60, 0x25a68,
1200 		0x25a70, 0x25a70,
1201 		0x25a78, 0x25a98,
1202 		0x25aa0, 0x25aa8,
1203 		0x25ab0, 0x25ac8,
1204 		0x25ad0, 0x25ad4,
1205 		0x25ae0, 0x25ae8,
1206 		0x25af0, 0x25af0,
1207 		0x25af8, 0x25c18,
1208 		0x25c20, 0x25c20,
1209 		0x25c28, 0x25c30,
1210 		0x25c38, 0x25c38,
1211 		0x25c80, 0x25c98,
1212 		0x25ca0, 0x25ca8,
1213 		0x25cb0, 0x25cc8,
1214 		0x25cd0, 0x25cd4,
1215 		0x25ce0, 0x25ce8,
1216 		0x25cf0, 0x25cf0,
1217 		0x25cf8, 0x25d7c,
1218 		0x25e00, 0x25e04,
1219 		0x26000, 0x2602c,
1220 		0x26100, 0x2613c,
1221 		0x26190, 0x261a0,
1222 		0x261a8, 0x261b8,
1223 		0x261c4, 0x261c8,
1224 		0x26200, 0x26318,
1225 		0x26400, 0x264b4,
1226 		0x264c0, 0x26528,
1227 		0x26540, 0x26614,
1228 		0x27000, 0x27040,
1229 		0x2704c, 0x27060,
1230 		0x270c0, 0x270ec,
1231 		0x27200, 0x27268,
1232 		0x27270, 0x27284,
1233 		0x272fc, 0x27388,
1234 		0x27400, 0x27404,
1235 		0x27500, 0x27500,
1236 		0x27510, 0x27518,
1237 		0x2752c, 0x27530,
1238 		0x2753c, 0x2753c,
1239 		0x27550, 0x27554,
1240 		0x27600, 0x27600,
1241 		0x27608, 0x2761c,
1242 		0x27624, 0x27628,
1243 		0x27630, 0x27634,
1244 		0x2763c, 0x2763c,
1245 		0x27700, 0x2771c,
1246 		0x27780, 0x2778c,
1247 		0x27800, 0x27818,
1248 		0x27820, 0x27828,
1249 		0x27830, 0x27848,
1250 		0x27850, 0x27854,
1251 		0x27860, 0x27868,
1252 		0x27870, 0x27870,
1253 		0x27878, 0x27898,
1254 		0x278a0, 0x278a8,
1255 		0x278b0, 0x278c8,
1256 		0x278d0, 0x278d4,
1257 		0x278e0, 0x278e8,
1258 		0x278f0, 0x278f0,
1259 		0x278f8, 0x27a18,
1260 		0x27a20, 0x27a28,
1261 		0x27a30, 0x27a48,
1262 		0x27a50, 0x27a54,
1263 		0x27a60, 0x27a68,
1264 		0x27a70, 0x27a70,
1265 		0x27a78, 0x27a98,
1266 		0x27aa0, 0x27aa8,
1267 		0x27ab0, 0x27ac8,
1268 		0x27ad0, 0x27ad4,
1269 		0x27ae0, 0x27ae8,
1270 		0x27af0, 0x27af0,
1271 		0x27af8, 0x27c18,
1272 		0x27c20, 0x27c20,
1273 		0x27c28, 0x27c30,
1274 		0x27c38, 0x27c38,
1275 		0x27c80, 0x27c98,
1276 		0x27ca0, 0x27ca8,
1277 		0x27cb0, 0x27cc8,
1278 		0x27cd0, 0x27cd4,
1279 		0x27ce0, 0x27ce8,
1280 		0x27cf0, 0x27cf0,
1281 		0x27cf8, 0x27d7c,
1282 		0x27e00, 0x27e04,
1283 	};
1284 
1285 	static const unsigned int t4vf_reg_ranges[] = {
1286 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1287 		VF_MPS_REG(A_MPS_VF_CTL),
1288 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1289 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1290 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1291 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1292 		FW_T4VF_MBDATA_BASE_ADDR,
1293 		FW_T4VF_MBDATA_BASE_ADDR +
1294 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1295 	};
1296 
1297 	static const unsigned int t5_reg_ranges[] = {
1298 		0x1008, 0x10c0,
1299 		0x10cc, 0x10f8,
1300 		0x1100, 0x1100,
1301 		0x110c, 0x1148,
1302 		0x1180, 0x1184,
1303 		0x1190, 0x1194,
1304 		0x11a0, 0x11a4,
1305 		0x11b0, 0x11b4,
1306 		0x11fc, 0x123c,
1307 		0x1280, 0x173c,
1308 		0x1800, 0x18fc,
1309 		0x3000, 0x3028,
1310 		0x3060, 0x30b0,
1311 		0x30b8, 0x30d8,
1312 		0x30e0, 0x30fc,
1313 		0x3140, 0x357c,
1314 		0x35a8, 0x35cc,
1315 		0x35ec, 0x35ec,
1316 		0x3600, 0x5624,
1317 		0x56cc, 0x56ec,
1318 		0x56f4, 0x5720,
1319 		0x5728, 0x575c,
1320 		0x580c, 0x5814,
1321 		0x5890, 0x589c,
1322 		0x58a4, 0x58ac,
1323 		0x58b8, 0x58bc,
1324 		0x5940, 0x59c8,
1325 		0x59d0, 0x59dc,
1326 		0x59fc, 0x5a18,
1327 		0x5a60, 0x5a70,
1328 		0x5a80, 0x5a9c,
1329 		0x5b94, 0x5bfc,
1330 		0x6000, 0x6020,
1331 		0x6028, 0x6040,
1332 		0x6058, 0x609c,
1333 		0x60a8, 0x614c,
1334 		0x7700, 0x7798,
1335 		0x77c0, 0x78fc,
1336 		0x7b00, 0x7b58,
1337 		0x7b60, 0x7b84,
1338 		0x7b8c, 0x7c54,
1339 		0x7d00, 0x7d38,
1340 		0x7d40, 0x7d80,
1341 		0x7d8c, 0x7ddc,
1342 		0x7de4, 0x7e04,
1343 		0x7e10, 0x7e1c,
1344 		0x7e24, 0x7e38,
1345 		0x7e40, 0x7e44,
1346 		0x7e4c, 0x7e78,
1347 		0x7e80, 0x7edc,
1348 		0x7ee8, 0x7efc,
1349 		0x8dc0, 0x8de0,
1350 		0x8df8, 0x8e04,
1351 		0x8e10, 0x8e84,
1352 		0x8ea0, 0x8f84,
1353 		0x8fc0, 0x9058,
1354 		0x9060, 0x9060,
1355 		0x9068, 0x90f8,
1356 		0x9400, 0x9408,
1357 		0x9410, 0x9470,
1358 		0x9600, 0x9600,
1359 		0x9608, 0x9638,
1360 		0x9640, 0x96f4,
1361 		0x9800, 0x9808,
1362 		0x9820, 0x983c,
1363 		0x9850, 0x9864,
1364 		0x9c00, 0x9c6c,
1365 		0x9c80, 0x9cec,
1366 		0x9d00, 0x9d6c,
1367 		0x9d80, 0x9dec,
1368 		0x9e00, 0x9e6c,
1369 		0x9e80, 0x9eec,
1370 		0x9f00, 0x9f6c,
1371 		0x9f80, 0xa020,
1372 		0xd004, 0xd004,
1373 		0xd010, 0xd03c,
1374 		0xdfc0, 0xdfe0,
1375 		0xe000, 0x1106c,
1376 		0x11074, 0x11088,
1377 		0x1109c, 0x1117c,
1378 		0x11190, 0x11204,
1379 		0x19040, 0x1906c,
1380 		0x19078, 0x19080,
1381 		0x1908c, 0x190e8,
1382 		0x190f0, 0x190f8,
1383 		0x19100, 0x19110,
1384 		0x19120, 0x19124,
1385 		0x19150, 0x19194,
1386 		0x1919c, 0x191b0,
1387 		0x191d0, 0x191e8,
1388 		0x19238, 0x19290,
1389 		0x193f8, 0x19428,
1390 		0x19430, 0x19444,
1391 		0x1944c, 0x1946c,
1392 		0x19474, 0x19474,
1393 		0x19490, 0x194cc,
1394 		0x194f0, 0x194f8,
1395 		0x19c00, 0x19c08,
1396 		0x19c10, 0x19c60,
1397 		0x19c94, 0x19ce4,
1398 		0x19cf0, 0x19d40,
1399 		0x19d50, 0x19d94,
1400 		0x19da0, 0x19de8,
1401 		0x19df0, 0x19e10,
1402 		0x19e50, 0x19e90,
1403 		0x19ea0, 0x19f24,
1404 		0x19f34, 0x19f34,
1405 		0x19f40, 0x19f50,
1406 		0x19f90, 0x19fb4,
1407 		0x19fc4, 0x19fe4,
1408 		0x1a000, 0x1a004,
1409 		0x1a010, 0x1a06c,
1410 		0x1a0b0, 0x1a0e4,
1411 		0x1a0ec, 0x1a0f8,
1412 		0x1a100, 0x1a108,
1413 		0x1a114, 0x1a120,
1414 		0x1a128, 0x1a130,
1415 		0x1a138, 0x1a138,
1416 		0x1a190, 0x1a1c4,
1417 		0x1a1fc, 0x1a1fc,
1418 		0x1e008, 0x1e00c,
1419 		0x1e040, 0x1e044,
1420 		0x1e04c, 0x1e04c,
1421 		0x1e284, 0x1e290,
1422 		0x1e2c0, 0x1e2c0,
1423 		0x1e2e0, 0x1e2e0,
1424 		0x1e300, 0x1e384,
1425 		0x1e3c0, 0x1e3c8,
1426 		0x1e408, 0x1e40c,
1427 		0x1e440, 0x1e444,
1428 		0x1e44c, 0x1e44c,
1429 		0x1e684, 0x1e690,
1430 		0x1e6c0, 0x1e6c0,
1431 		0x1e6e0, 0x1e6e0,
1432 		0x1e700, 0x1e784,
1433 		0x1e7c0, 0x1e7c8,
1434 		0x1e808, 0x1e80c,
1435 		0x1e840, 0x1e844,
1436 		0x1e84c, 0x1e84c,
1437 		0x1ea84, 0x1ea90,
1438 		0x1eac0, 0x1eac0,
1439 		0x1eae0, 0x1eae0,
1440 		0x1eb00, 0x1eb84,
1441 		0x1ebc0, 0x1ebc8,
1442 		0x1ec08, 0x1ec0c,
1443 		0x1ec40, 0x1ec44,
1444 		0x1ec4c, 0x1ec4c,
1445 		0x1ee84, 0x1ee90,
1446 		0x1eec0, 0x1eec0,
1447 		0x1eee0, 0x1eee0,
1448 		0x1ef00, 0x1ef84,
1449 		0x1efc0, 0x1efc8,
1450 		0x1f008, 0x1f00c,
1451 		0x1f040, 0x1f044,
1452 		0x1f04c, 0x1f04c,
1453 		0x1f284, 0x1f290,
1454 		0x1f2c0, 0x1f2c0,
1455 		0x1f2e0, 0x1f2e0,
1456 		0x1f300, 0x1f384,
1457 		0x1f3c0, 0x1f3c8,
1458 		0x1f408, 0x1f40c,
1459 		0x1f440, 0x1f444,
1460 		0x1f44c, 0x1f44c,
1461 		0x1f684, 0x1f690,
1462 		0x1f6c0, 0x1f6c0,
1463 		0x1f6e0, 0x1f6e0,
1464 		0x1f700, 0x1f784,
1465 		0x1f7c0, 0x1f7c8,
1466 		0x1f808, 0x1f80c,
1467 		0x1f840, 0x1f844,
1468 		0x1f84c, 0x1f84c,
1469 		0x1fa84, 0x1fa90,
1470 		0x1fac0, 0x1fac0,
1471 		0x1fae0, 0x1fae0,
1472 		0x1fb00, 0x1fb84,
1473 		0x1fbc0, 0x1fbc8,
1474 		0x1fc08, 0x1fc0c,
1475 		0x1fc40, 0x1fc44,
1476 		0x1fc4c, 0x1fc4c,
1477 		0x1fe84, 0x1fe90,
1478 		0x1fec0, 0x1fec0,
1479 		0x1fee0, 0x1fee0,
1480 		0x1ff00, 0x1ff84,
1481 		0x1ffc0, 0x1ffc8,
1482 		0x30000, 0x30030,
1483 		0x30100, 0x30144,
1484 		0x30190, 0x301a0,
1485 		0x301a8, 0x301b8,
1486 		0x301c4, 0x301c8,
1487 		0x301d0, 0x301d0,
1488 		0x30200, 0x30318,
1489 		0x30400, 0x304b4,
1490 		0x304c0, 0x3052c,
1491 		0x30540, 0x3061c,
1492 		0x30800, 0x30828,
1493 		0x30834, 0x30834,
1494 		0x308c0, 0x30908,
1495 		0x30910, 0x309ac,
1496 		0x30a00, 0x30a14,
1497 		0x30a1c, 0x30a2c,
1498 		0x30a44, 0x30a50,
1499 		0x30a74, 0x30a74,
1500 		0x30a7c, 0x30afc,
1501 		0x30b08, 0x30c24,
1502 		0x30d00, 0x30d00,
1503 		0x30d08, 0x30d14,
1504 		0x30d1c, 0x30d20,
1505 		0x30d3c, 0x30d3c,
1506 		0x30d48, 0x30d50,
1507 		0x31200, 0x3120c,
1508 		0x31220, 0x31220,
1509 		0x31240, 0x31240,
1510 		0x31600, 0x3160c,
1511 		0x31a00, 0x31a1c,
1512 		0x31e00, 0x31e20,
1513 		0x31e38, 0x31e3c,
1514 		0x31e80, 0x31e80,
1515 		0x31e88, 0x31ea8,
1516 		0x31eb0, 0x31eb4,
1517 		0x31ec8, 0x31ed4,
1518 		0x31fb8, 0x32004,
1519 		0x32200, 0x32200,
1520 		0x32208, 0x32240,
1521 		0x32248, 0x32280,
1522 		0x32288, 0x322c0,
1523 		0x322c8, 0x322fc,
1524 		0x32600, 0x32630,
1525 		0x32a00, 0x32abc,
1526 		0x32b00, 0x32b10,
1527 		0x32b20, 0x32b30,
1528 		0x32b40, 0x32b50,
1529 		0x32b60, 0x32b70,
1530 		0x33000, 0x33028,
1531 		0x33030, 0x33048,
1532 		0x33060, 0x33068,
1533 		0x33070, 0x3309c,
1534 		0x330f0, 0x33128,
1535 		0x33130, 0x33148,
1536 		0x33160, 0x33168,
1537 		0x33170, 0x3319c,
1538 		0x331f0, 0x33238,
1539 		0x33240, 0x33240,
1540 		0x33248, 0x33250,
1541 		0x3325c, 0x33264,
1542 		0x33270, 0x332b8,
1543 		0x332c0, 0x332e4,
1544 		0x332f8, 0x33338,
1545 		0x33340, 0x33340,
1546 		0x33348, 0x33350,
1547 		0x3335c, 0x33364,
1548 		0x33370, 0x333b8,
1549 		0x333c0, 0x333e4,
1550 		0x333f8, 0x33428,
1551 		0x33430, 0x33448,
1552 		0x33460, 0x33468,
1553 		0x33470, 0x3349c,
1554 		0x334f0, 0x33528,
1555 		0x33530, 0x33548,
1556 		0x33560, 0x33568,
1557 		0x33570, 0x3359c,
1558 		0x335f0, 0x33638,
1559 		0x33640, 0x33640,
1560 		0x33648, 0x33650,
1561 		0x3365c, 0x33664,
1562 		0x33670, 0x336b8,
1563 		0x336c0, 0x336e4,
1564 		0x336f8, 0x33738,
1565 		0x33740, 0x33740,
1566 		0x33748, 0x33750,
1567 		0x3375c, 0x33764,
1568 		0x33770, 0x337b8,
1569 		0x337c0, 0x337e4,
1570 		0x337f8, 0x337fc,
1571 		0x33814, 0x33814,
1572 		0x3382c, 0x3382c,
1573 		0x33880, 0x3388c,
1574 		0x338e8, 0x338ec,
1575 		0x33900, 0x33928,
1576 		0x33930, 0x33948,
1577 		0x33960, 0x33968,
1578 		0x33970, 0x3399c,
1579 		0x339f0, 0x33a38,
1580 		0x33a40, 0x33a40,
1581 		0x33a48, 0x33a50,
1582 		0x33a5c, 0x33a64,
1583 		0x33a70, 0x33ab8,
1584 		0x33ac0, 0x33ae4,
1585 		0x33af8, 0x33b10,
1586 		0x33b28, 0x33b28,
1587 		0x33b3c, 0x33b50,
1588 		0x33bf0, 0x33c10,
1589 		0x33c28, 0x33c28,
1590 		0x33c3c, 0x33c50,
1591 		0x33cf0, 0x33cfc,
1592 		0x34000, 0x34030,
1593 		0x34100, 0x34144,
1594 		0x34190, 0x341a0,
1595 		0x341a8, 0x341b8,
1596 		0x341c4, 0x341c8,
1597 		0x341d0, 0x341d0,
1598 		0x34200, 0x34318,
1599 		0x34400, 0x344b4,
1600 		0x344c0, 0x3452c,
1601 		0x34540, 0x3461c,
1602 		0x34800, 0x34828,
1603 		0x34834, 0x34834,
1604 		0x348c0, 0x34908,
1605 		0x34910, 0x349ac,
1606 		0x34a00, 0x34a14,
1607 		0x34a1c, 0x34a2c,
1608 		0x34a44, 0x34a50,
1609 		0x34a74, 0x34a74,
1610 		0x34a7c, 0x34afc,
1611 		0x34b08, 0x34c24,
1612 		0x34d00, 0x34d00,
1613 		0x34d08, 0x34d14,
1614 		0x34d1c, 0x34d20,
1615 		0x34d3c, 0x34d3c,
1616 		0x34d48, 0x34d50,
1617 		0x35200, 0x3520c,
1618 		0x35220, 0x35220,
1619 		0x35240, 0x35240,
1620 		0x35600, 0x3560c,
1621 		0x35a00, 0x35a1c,
1622 		0x35e00, 0x35e20,
1623 		0x35e38, 0x35e3c,
1624 		0x35e80, 0x35e80,
1625 		0x35e88, 0x35ea8,
1626 		0x35eb0, 0x35eb4,
1627 		0x35ec8, 0x35ed4,
1628 		0x35fb8, 0x36004,
1629 		0x36200, 0x36200,
1630 		0x36208, 0x36240,
1631 		0x36248, 0x36280,
1632 		0x36288, 0x362c0,
1633 		0x362c8, 0x362fc,
1634 		0x36600, 0x36630,
1635 		0x36a00, 0x36abc,
1636 		0x36b00, 0x36b10,
1637 		0x36b20, 0x36b30,
1638 		0x36b40, 0x36b50,
1639 		0x36b60, 0x36b70,
1640 		0x37000, 0x37028,
1641 		0x37030, 0x37048,
1642 		0x37060, 0x37068,
1643 		0x37070, 0x3709c,
1644 		0x370f0, 0x37128,
1645 		0x37130, 0x37148,
1646 		0x37160, 0x37168,
1647 		0x37170, 0x3719c,
1648 		0x371f0, 0x37238,
1649 		0x37240, 0x37240,
1650 		0x37248, 0x37250,
1651 		0x3725c, 0x37264,
1652 		0x37270, 0x372b8,
1653 		0x372c0, 0x372e4,
1654 		0x372f8, 0x37338,
1655 		0x37340, 0x37340,
1656 		0x37348, 0x37350,
1657 		0x3735c, 0x37364,
1658 		0x37370, 0x373b8,
1659 		0x373c0, 0x373e4,
1660 		0x373f8, 0x37428,
1661 		0x37430, 0x37448,
1662 		0x37460, 0x37468,
1663 		0x37470, 0x3749c,
1664 		0x374f0, 0x37528,
1665 		0x37530, 0x37548,
1666 		0x37560, 0x37568,
1667 		0x37570, 0x3759c,
1668 		0x375f0, 0x37638,
1669 		0x37640, 0x37640,
1670 		0x37648, 0x37650,
1671 		0x3765c, 0x37664,
1672 		0x37670, 0x376b8,
1673 		0x376c0, 0x376e4,
1674 		0x376f8, 0x37738,
1675 		0x37740, 0x37740,
1676 		0x37748, 0x37750,
1677 		0x3775c, 0x37764,
1678 		0x37770, 0x377b8,
1679 		0x377c0, 0x377e4,
1680 		0x377f8, 0x377fc,
1681 		0x37814, 0x37814,
1682 		0x3782c, 0x3782c,
1683 		0x37880, 0x3788c,
1684 		0x378e8, 0x378ec,
1685 		0x37900, 0x37928,
1686 		0x37930, 0x37948,
1687 		0x37960, 0x37968,
1688 		0x37970, 0x3799c,
1689 		0x379f0, 0x37a38,
1690 		0x37a40, 0x37a40,
1691 		0x37a48, 0x37a50,
1692 		0x37a5c, 0x37a64,
1693 		0x37a70, 0x37ab8,
1694 		0x37ac0, 0x37ae4,
1695 		0x37af8, 0x37b10,
1696 		0x37b28, 0x37b28,
1697 		0x37b3c, 0x37b50,
1698 		0x37bf0, 0x37c10,
1699 		0x37c28, 0x37c28,
1700 		0x37c3c, 0x37c50,
1701 		0x37cf0, 0x37cfc,
1702 		0x38000, 0x38030,
1703 		0x38100, 0x38144,
1704 		0x38190, 0x381a0,
1705 		0x381a8, 0x381b8,
1706 		0x381c4, 0x381c8,
1707 		0x381d0, 0x381d0,
1708 		0x38200, 0x38318,
1709 		0x38400, 0x384b4,
1710 		0x384c0, 0x3852c,
1711 		0x38540, 0x3861c,
1712 		0x38800, 0x38828,
1713 		0x38834, 0x38834,
1714 		0x388c0, 0x38908,
1715 		0x38910, 0x389ac,
1716 		0x38a00, 0x38a14,
1717 		0x38a1c, 0x38a2c,
1718 		0x38a44, 0x38a50,
1719 		0x38a74, 0x38a74,
1720 		0x38a7c, 0x38afc,
1721 		0x38b08, 0x38c24,
1722 		0x38d00, 0x38d00,
1723 		0x38d08, 0x38d14,
1724 		0x38d1c, 0x38d20,
1725 		0x38d3c, 0x38d3c,
1726 		0x38d48, 0x38d50,
1727 		0x39200, 0x3920c,
1728 		0x39220, 0x39220,
1729 		0x39240, 0x39240,
1730 		0x39600, 0x3960c,
1731 		0x39a00, 0x39a1c,
1732 		0x39e00, 0x39e20,
1733 		0x39e38, 0x39e3c,
1734 		0x39e80, 0x39e80,
1735 		0x39e88, 0x39ea8,
1736 		0x39eb0, 0x39eb4,
1737 		0x39ec8, 0x39ed4,
1738 		0x39fb8, 0x3a004,
1739 		0x3a200, 0x3a200,
1740 		0x3a208, 0x3a240,
1741 		0x3a248, 0x3a280,
1742 		0x3a288, 0x3a2c0,
1743 		0x3a2c8, 0x3a2fc,
1744 		0x3a600, 0x3a630,
1745 		0x3aa00, 0x3aabc,
1746 		0x3ab00, 0x3ab10,
1747 		0x3ab20, 0x3ab30,
1748 		0x3ab40, 0x3ab50,
1749 		0x3ab60, 0x3ab70,
1750 		0x3b000, 0x3b028,
1751 		0x3b030, 0x3b048,
1752 		0x3b060, 0x3b068,
1753 		0x3b070, 0x3b09c,
1754 		0x3b0f0, 0x3b128,
1755 		0x3b130, 0x3b148,
1756 		0x3b160, 0x3b168,
1757 		0x3b170, 0x3b19c,
1758 		0x3b1f0, 0x3b238,
1759 		0x3b240, 0x3b240,
1760 		0x3b248, 0x3b250,
1761 		0x3b25c, 0x3b264,
1762 		0x3b270, 0x3b2b8,
1763 		0x3b2c0, 0x3b2e4,
1764 		0x3b2f8, 0x3b338,
1765 		0x3b340, 0x3b340,
1766 		0x3b348, 0x3b350,
1767 		0x3b35c, 0x3b364,
1768 		0x3b370, 0x3b3b8,
1769 		0x3b3c0, 0x3b3e4,
1770 		0x3b3f8, 0x3b428,
1771 		0x3b430, 0x3b448,
1772 		0x3b460, 0x3b468,
1773 		0x3b470, 0x3b49c,
1774 		0x3b4f0, 0x3b528,
1775 		0x3b530, 0x3b548,
1776 		0x3b560, 0x3b568,
1777 		0x3b570, 0x3b59c,
1778 		0x3b5f0, 0x3b638,
1779 		0x3b640, 0x3b640,
1780 		0x3b648, 0x3b650,
1781 		0x3b65c, 0x3b664,
1782 		0x3b670, 0x3b6b8,
1783 		0x3b6c0, 0x3b6e4,
1784 		0x3b6f8, 0x3b738,
1785 		0x3b740, 0x3b740,
1786 		0x3b748, 0x3b750,
1787 		0x3b75c, 0x3b764,
1788 		0x3b770, 0x3b7b8,
1789 		0x3b7c0, 0x3b7e4,
1790 		0x3b7f8, 0x3b7fc,
1791 		0x3b814, 0x3b814,
1792 		0x3b82c, 0x3b82c,
1793 		0x3b880, 0x3b88c,
1794 		0x3b8e8, 0x3b8ec,
1795 		0x3b900, 0x3b928,
1796 		0x3b930, 0x3b948,
1797 		0x3b960, 0x3b968,
1798 		0x3b970, 0x3b99c,
1799 		0x3b9f0, 0x3ba38,
1800 		0x3ba40, 0x3ba40,
1801 		0x3ba48, 0x3ba50,
1802 		0x3ba5c, 0x3ba64,
1803 		0x3ba70, 0x3bab8,
1804 		0x3bac0, 0x3bae4,
1805 		0x3baf8, 0x3bb10,
1806 		0x3bb28, 0x3bb28,
1807 		0x3bb3c, 0x3bb50,
1808 		0x3bbf0, 0x3bc10,
1809 		0x3bc28, 0x3bc28,
1810 		0x3bc3c, 0x3bc50,
1811 		0x3bcf0, 0x3bcfc,
1812 		0x3c000, 0x3c030,
1813 		0x3c100, 0x3c144,
1814 		0x3c190, 0x3c1a0,
1815 		0x3c1a8, 0x3c1b8,
1816 		0x3c1c4, 0x3c1c8,
1817 		0x3c1d0, 0x3c1d0,
1818 		0x3c200, 0x3c318,
1819 		0x3c400, 0x3c4b4,
1820 		0x3c4c0, 0x3c52c,
1821 		0x3c540, 0x3c61c,
1822 		0x3c800, 0x3c828,
1823 		0x3c834, 0x3c834,
1824 		0x3c8c0, 0x3c908,
1825 		0x3c910, 0x3c9ac,
1826 		0x3ca00, 0x3ca14,
1827 		0x3ca1c, 0x3ca2c,
1828 		0x3ca44, 0x3ca50,
1829 		0x3ca74, 0x3ca74,
1830 		0x3ca7c, 0x3cafc,
1831 		0x3cb08, 0x3cc24,
1832 		0x3cd00, 0x3cd00,
1833 		0x3cd08, 0x3cd14,
1834 		0x3cd1c, 0x3cd20,
1835 		0x3cd3c, 0x3cd3c,
1836 		0x3cd48, 0x3cd50,
1837 		0x3d200, 0x3d20c,
1838 		0x3d220, 0x3d220,
1839 		0x3d240, 0x3d240,
1840 		0x3d600, 0x3d60c,
1841 		0x3da00, 0x3da1c,
1842 		0x3de00, 0x3de20,
1843 		0x3de38, 0x3de3c,
1844 		0x3de80, 0x3de80,
1845 		0x3de88, 0x3dea8,
1846 		0x3deb0, 0x3deb4,
1847 		0x3dec8, 0x3ded4,
1848 		0x3dfb8, 0x3e004,
1849 		0x3e200, 0x3e200,
1850 		0x3e208, 0x3e240,
1851 		0x3e248, 0x3e280,
1852 		0x3e288, 0x3e2c0,
1853 		0x3e2c8, 0x3e2fc,
1854 		0x3e600, 0x3e630,
1855 		0x3ea00, 0x3eabc,
1856 		0x3eb00, 0x3eb10,
1857 		0x3eb20, 0x3eb30,
1858 		0x3eb40, 0x3eb50,
1859 		0x3eb60, 0x3eb70,
1860 		0x3f000, 0x3f028,
1861 		0x3f030, 0x3f048,
1862 		0x3f060, 0x3f068,
1863 		0x3f070, 0x3f09c,
1864 		0x3f0f0, 0x3f128,
1865 		0x3f130, 0x3f148,
1866 		0x3f160, 0x3f168,
1867 		0x3f170, 0x3f19c,
1868 		0x3f1f0, 0x3f238,
1869 		0x3f240, 0x3f240,
1870 		0x3f248, 0x3f250,
1871 		0x3f25c, 0x3f264,
1872 		0x3f270, 0x3f2b8,
1873 		0x3f2c0, 0x3f2e4,
1874 		0x3f2f8, 0x3f338,
1875 		0x3f340, 0x3f340,
1876 		0x3f348, 0x3f350,
1877 		0x3f35c, 0x3f364,
1878 		0x3f370, 0x3f3b8,
1879 		0x3f3c0, 0x3f3e4,
1880 		0x3f3f8, 0x3f428,
1881 		0x3f430, 0x3f448,
1882 		0x3f460, 0x3f468,
1883 		0x3f470, 0x3f49c,
1884 		0x3f4f0, 0x3f528,
1885 		0x3f530, 0x3f548,
1886 		0x3f560, 0x3f568,
1887 		0x3f570, 0x3f59c,
1888 		0x3f5f0, 0x3f638,
1889 		0x3f640, 0x3f640,
1890 		0x3f648, 0x3f650,
1891 		0x3f65c, 0x3f664,
1892 		0x3f670, 0x3f6b8,
1893 		0x3f6c0, 0x3f6e4,
1894 		0x3f6f8, 0x3f738,
1895 		0x3f740, 0x3f740,
1896 		0x3f748, 0x3f750,
1897 		0x3f75c, 0x3f764,
1898 		0x3f770, 0x3f7b8,
1899 		0x3f7c0, 0x3f7e4,
1900 		0x3f7f8, 0x3f7fc,
1901 		0x3f814, 0x3f814,
1902 		0x3f82c, 0x3f82c,
1903 		0x3f880, 0x3f88c,
1904 		0x3f8e8, 0x3f8ec,
1905 		0x3f900, 0x3f928,
1906 		0x3f930, 0x3f948,
1907 		0x3f960, 0x3f968,
1908 		0x3f970, 0x3f99c,
1909 		0x3f9f0, 0x3fa38,
1910 		0x3fa40, 0x3fa40,
1911 		0x3fa48, 0x3fa50,
1912 		0x3fa5c, 0x3fa64,
1913 		0x3fa70, 0x3fab8,
1914 		0x3fac0, 0x3fae4,
1915 		0x3faf8, 0x3fb10,
1916 		0x3fb28, 0x3fb28,
1917 		0x3fb3c, 0x3fb50,
1918 		0x3fbf0, 0x3fc10,
1919 		0x3fc28, 0x3fc28,
1920 		0x3fc3c, 0x3fc50,
1921 		0x3fcf0, 0x3fcfc,
1922 		0x40000, 0x4000c,
1923 		0x40040, 0x40050,
1924 		0x40060, 0x40068,
1925 		0x4007c, 0x4008c,
1926 		0x40094, 0x400b0,
1927 		0x400c0, 0x40144,
1928 		0x40180, 0x4018c,
1929 		0x40200, 0x40254,
1930 		0x40260, 0x40264,
1931 		0x40270, 0x40288,
1932 		0x40290, 0x40298,
1933 		0x402ac, 0x402c8,
1934 		0x402d0, 0x402e0,
1935 		0x402f0, 0x402f0,
1936 		0x40300, 0x4033c,
1937 		0x403f8, 0x403fc,
1938 		0x41304, 0x413c4,
1939 		0x41400, 0x4140c,
1940 		0x41414, 0x4141c,
1941 		0x41480, 0x414d0,
1942 		0x44000, 0x44054,
1943 		0x4405c, 0x44078,
1944 		0x440c0, 0x44174,
1945 		0x44180, 0x441ac,
1946 		0x441b4, 0x441b8,
1947 		0x441c0, 0x44254,
1948 		0x4425c, 0x44278,
1949 		0x442c0, 0x44374,
1950 		0x44380, 0x443ac,
1951 		0x443b4, 0x443b8,
1952 		0x443c0, 0x44454,
1953 		0x4445c, 0x44478,
1954 		0x444c0, 0x44574,
1955 		0x44580, 0x445ac,
1956 		0x445b4, 0x445b8,
1957 		0x445c0, 0x44654,
1958 		0x4465c, 0x44678,
1959 		0x446c0, 0x44774,
1960 		0x44780, 0x447ac,
1961 		0x447b4, 0x447b8,
1962 		0x447c0, 0x44854,
1963 		0x4485c, 0x44878,
1964 		0x448c0, 0x44974,
1965 		0x44980, 0x449ac,
1966 		0x449b4, 0x449b8,
1967 		0x449c0, 0x449fc,
1968 		0x45000, 0x45004,
1969 		0x45010, 0x45030,
1970 		0x45040, 0x45060,
1971 		0x45068, 0x45068,
1972 		0x45080, 0x45084,
1973 		0x450a0, 0x450b0,
1974 		0x45200, 0x45204,
1975 		0x45210, 0x45230,
1976 		0x45240, 0x45260,
1977 		0x45268, 0x45268,
1978 		0x45280, 0x45284,
1979 		0x452a0, 0x452b0,
1980 		0x460c0, 0x460e4,
1981 		0x47000, 0x4703c,
1982 		0x47044, 0x4708c,
1983 		0x47200, 0x47250,
1984 		0x47400, 0x47408,
1985 		0x47414, 0x47420,
1986 		0x47600, 0x47618,
1987 		0x47800, 0x47814,
1988 		0x48000, 0x4800c,
1989 		0x48040, 0x48050,
1990 		0x48060, 0x48068,
1991 		0x4807c, 0x4808c,
1992 		0x48094, 0x480b0,
1993 		0x480c0, 0x48144,
1994 		0x48180, 0x4818c,
1995 		0x48200, 0x48254,
1996 		0x48260, 0x48264,
1997 		0x48270, 0x48288,
1998 		0x48290, 0x48298,
1999 		0x482ac, 0x482c8,
2000 		0x482d0, 0x482e0,
2001 		0x482f0, 0x482f0,
2002 		0x48300, 0x4833c,
2003 		0x483f8, 0x483fc,
2004 		0x49304, 0x493c4,
2005 		0x49400, 0x4940c,
2006 		0x49414, 0x4941c,
2007 		0x49480, 0x494d0,
2008 		0x4c000, 0x4c054,
2009 		0x4c05c, 0x4c078,
2010 		0x4c0c0, 0x4c174,
2011 		0x4c180, 0x4c1ac,
2012 		0x4c1b4, 0x4c1b8,
2013 		0x4c1c0, 0x4c254,
2014 		0x4c25c, 0x4c278,
2015 		0x4c2c0, 0x4c374,
2016 		0x4c380, 0x4c3ac,
2017 		0x4c3b4, 0x4c3b8,
2018 		0x4c3c0, 0x4c454,
2019 		0x4c45c, 0x4c478,
2020 		0x4c4c0, 0x4c574,
2021 		0x4c580, 0x4c5ac,
2022 		0x4c5b4, 0x4c5b8,
2023 		0x4c5c0, 0x4c654,
2024 		0x4c65c, 0x4c678,
2025 		0x4c6c0, 0x4c774,
2026 		0x4c780, 0x4c7ac,
2027 		0x4c7b4, 0x4c7b8,
2028 		0x4c7c0, 0x4c854,
2029 		0x4c85c, 0x4c878,
2030 		0x4c8c0, 0x4c974,
2031 		0x4c980, 0x4c9ac,
2032 		0x4c9b4, 0x4c9b8,
2033 		0x4c9c0, 0x4c9fc,
2034 		0x4d000, 0x4d004,
2035 		0x4d010, 0x4d030,
2036 		0x4d040, 0x4d060,
2037 		0x4d068, 0x4d068,
2038 		0x4d080, 0x4d084,
2039 		0x4d0a0, 0x4d0b0,
2040 		0x4d200, 0x4d204,
2041 		0x4d210, 0x4d230,
2042 		0x4d240, 0x4d260,
2043 		0x4d268, 0x4d268,
2044 		0x4d280, 0x4d284,
2045 		0x4d2a0, 0x4d2b0,
2046 		0x4e0c0, 0x4e0e4,
2047 		0x4f000, 0x4f03c,
2048 		0x4f044, 0x4f08c,
2049 		0x4f200, 0x4f250,
2050 		0x4f400, 0x4f408,
2051 		0x4f414, 0x4f420,
2052 		0x4f600, 0x4f618,
2053 		0x4f800, 0x4f814,
2054 		0x50000, 0x50084,
2055 		0x50090, 0x500cc,
2056 		0x50400, 0x50400,
2057 		0x50800, 0x50884,
2058 		0x50890, 0x508cc,
2059 		0x50c00, 0x50c00,
2060 		0x51000, 0x5101c,
2061 		0x51300, 0x51308,
2062 	};
2063 
2064 	static const unsigned int t5vf_reg_ranges[] = {
2065 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2066 		VF_MPS_REG(A_MPS_VF_CTL),
2067 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2068 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2069 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2070 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2071 		FW_T4VF_MBDATA_BASE_ADDR,
2072 		FW_T4VF_MBDATA_BASE_ADDR +
2073 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2074 	};
2075 
2076 	static const unsigned int t6_reg_ranges[] = {
2077 		0x1008, 0x101c,
2078 		0x1024, 0x10a8,
2079 		0x10b4, 0x10f8,
2080 		0x1100, 0x1114,
2081 		0x111c, 0x112c,
2082 		0x1138, 0x113c,
2083 		0x1144, 0x114c,
2084 		0x1180, 0x1184,
2085 		0x1190, 0x1194,
2086 		0x11a0, 0x11a4,
2087 		0x11b0, 0x11b4,
2088 		0x11fc, 0x1274,
2089 		0x1280, 0x133c,
2090 		0x1800, 0x18fc,
2091 		0x3000, 0x302c,
2092 		0x3060, 0x30b0,
2093 		0x30b8, 0x30d8,
2094 		0x30e0, 0x30fc,
2095 		0x3140, 0x357c,
2096 		0x35a8, 0x35cc,
2097 		0x35ec, 0x35ec,
2098 		0x3600, 0x5624,
2099 		0x56cc, 0x56ec,
2100 		0x56f4, 0x5720,
2101 		0x5728, 0x575c,
2102 		0x580c, 0x5814,
2103 		0x5890, 0x589c,
2104 		0x58a4, 0x58ac,
2105 		0x58b8, 0x58bc,
2106 		0x5940, 0x595c,
2107 		0x5980, 0x598c,
2108 		0x59b0, 0x59c8,
2109 		0x59d0, 0x59dc,
2110 		0x59fc, 0x5a18,
2111 		0x5a60, 0x5a6c,
2112 		0x5a80, 0x5a8c,
2113 		0x5a94, 0x5a9c,
2114 		0x5b94, 0x5bfc,
2115 		0x5c10, 0x5e48,
2116 		0x5e50, 0x5e94,
2117 		0x5ea0, 0x5eb0,
2118 		0x5ec0, 0x5ec0,
2119 		0x5ec8, 0x5ed0,
2120 		0x5ee0, 0x5ee0,
2121 		0x5ef0, 0x5ef0,
2122 		0x5f00, 0x5f00,
2123 		0x6000, 0x6020,
2124 		0x6028, 0x6040,
2125 		0x6058, 0x609c,
2126 		0x60a8, 0x619c,
2127 		0x7700, 0x7798,
2128 		0x77c0, 0x7880,
2129 		0x78cc, 0x78fc,
2130 		0x7b00, 0x7b58,
2131 		0x7b60, 0x7b84,
2132 		0x7b8c, 0x7c54,
2133 		0x7d00, 0x7d38,
2134 		0x7d40, 0x7d84,
2135 		0x7d8c, 0x7ddc,
2136 		0x7de4, 0x7e04,
2137 		0x7e10, 0x7e1c,
2138 		0x7e24, 0x7e38,
2139 		0x7e40, 0x7e44,
2140 		0x7e4c, 0x7e78,
2141 		0x7e80, 0x7edc,
2142 		0x7ee8, 0x7efc,
2143 		0x8dc0, 0x8de4,
2144 		0x8df8, 0x8e04,
2145 		0x8e10, 0x8e84,
2146 		0x8ea0, 0x8f88,
2147 		0x8fb8, 0x9058,
2148 		0x9060, 0x9060,
2149 		0x9068, 0x90f8,
2150 		0x9100, 0x9124,
2151 		0x9400, 0x9470,
2152 		0x9600, 0x9600,
2153 		0x9608, 0x9638,
2154 		0x9640, 0x9704,
2155 		0x9710, 0x971c,
2156 		0x9800, 0x9808,
2157 		0x9820, 0x983c,
2158 		0x9850, 0x9864,
2159 		0x9c00, 0x9c6c,
2160 		0x9c80, 0x9cec,
2161 		0x9d00, 0x9d6c,
2162 		0x9d80, 0x9dec,
2163 		0x9e00, 0x9e6c,
2164 		0x9e80, 0x9eec,
2165 		0x9f00, 0x9f6c,
2166 		0x9f80, 0xa020,
2167 		0xd004, 0xd03c,
2168 		0xd100, 0xd118,
2169 		0xd200, 0xd214,
2170 		0xd220, 0xd234,
2171 		0xd240, 0xd254,
2172 		0xd260, 0xd274,
2173 		0xd280, 0xd294,
2174 		0xd2a0, 0xd2b4,
2175 		0xd2c0, 0xd2d4,
2176 		0xd2e0, 0xd2f4,
2177 		0xd300, 0xd31c,
2178 		0xdfc0, 0xdfe0,
2179 		0xe000, 0xf008,
2180 		0xf010, 0xf018,
2181 		0xf020, 0xf028,
2182 		0x11000, 0x11014,
2183 		0x11048, 0x1106c,
2184 		0x11074, 0x11088,
2185 		0x11098, 0x11120,
2186 		0x1112c, 0x1117c,
2187 		0x11190, 0x112e0,
2188 		0x11300, 0x1130c,
2189 		0x12000, 0x1206c,
2190 		0x19040, 0x1906c,
2191 		0x19078, 0x19080,
2192 		0x1908c, 0x190e8,
2193 		0x190f0, 0x190f8,
2194 		0x19100, 0x19110,
2195 		0x19120, 0x19124,
2196 		0x19150, 0x19194,
2197 		0x1919c, 0x191b0,
2198 		0x191d0, 0x191e8,
2199 		0x19238, 0x19290,
2200 		0x192a4, 0x192b0,
2201 		0x192bc, 0x192bc,
2202 		0x19348, 0x1934c,
2203 		0x193f8, 0x19418,
2204 		0x19420, 0x19428,
2205 		0x19430, 0x19444,
2206 		0x1944c, 0x1946c,
2207 		0x19474, 0x19474,
2208 		0x19490, 0x194cc,
2209 		0x194f0, 0x194f8,
2210 		0x19c00, 0x19c48,
2211 		0x19c50, 0x19c80,
2212 		0x19c94, 0x19c98,
2213 		0x19ca0, 0x19cbc,
2214 		0x19ce4, 0x19ce4,
2215 		0x19cf0, 0x19cf8,
2216 		0x19d00, 0x19d28,
2217 		0x19d50, 0x19d78,
2218 		0x19d94, 0x19d98,
2219 		0x19da0, 0x19dc8,
2220 		0x19df0, 0x19e10,
2221 		0x19e50, 0x19e6c,
2222 		0x19ea0, 0x19ebc,
2223 		0x19ec4, 0x19ef4,
2224 		0x19f04, 0x19f2c,
2225 		0x19f34, 0x19f34,
2226 		0x19f40, 0x19f50,
2227 		0x19f90, 0x19fac,
2228 		0x19fc4, 0x19fc8,
2229 		0x19fd0, 0x19fe4,
2230 		0x1a000, 0x1a004,
2231 		0x1a010, 0x1a06c,
2232 		0x1a0b0, 0x1a0e4,
2233 		0x1a0ec, 0x1a0f8,
2234 		0x1a100, 0x1a108,
2235 		0x1a114, 0x1a120,
2236 		0x1a128, 0x1a130,
2237 		0x1a138, 0x1a138,
2238 		0x1a190, 0x1a1c4,
2239 		0x1a1fc, 0x1a1fc,
2240 		0x1e008, 0x1e00c,
2241 		0x1e040, 0x1e044,
2242 		0x1e04c, 0x1e04c,
2243 		0x1e284, 0x1e290,
2244 		0x1e2c0, 0x1e2c0,
2245 		0x1e2e0, 0x1e2e0,
2246 		0x1e300, 0x1e384,
2247 		0x1e3c0, 0x1e3c8,
2248 		0x1e408, 0x1e40c,
2249 		0x1e440, 0x1e444,
2250 		0x1e44c, 0x1e44c,
2251 		0x1e684, 0x1e690,
2252 		0x1e6c0, 0x1e6c0,
2253 		0x1e6e0, 0x1e6e0,
2254 		0x1e700, 0x1e784,
2255 		0x1e7c0, 0x1e7c8,
2256 		0x1e808, 0x1e80c,
2257 		0x1e840, 0x1e844,
2258 		0x1e84c, 0x1e84c,
2259 		0x1ea84, 0x1ea90,
2260 		0x1eac0, 0x1eac0,
2261 		0x1eae0, 0x1eae0,
2262 		0x1eb00, 0x1eb84,
2263 		0x1ebc0, 0x1ebc8,
2264 		0x1ec08, 0x1ec0c,
2265 		0x1ec40, 0x1ec44,
2266 		0x1ec4c, 0x1ec4c,
2267 		0x1ee84, 0x1ee90,
2268 		0x1eec0, 0x1eec0,
2269 		0x1eee0, 0x1eee0,
2270 		0x1ef00, 0x1ef84,
2271 		0x1efc0, 0x1efc8,
2272 		0x1f008, 0x1f00c,
2273 		0x1f040, 0x1f044,
2274 		0x1f04c, 0x1f04c,
2275 		0x1f284, 0x1f290,
2276 		0x1f2c0, 0x1f2c0,
2277 		0x1f2e0, 0x1f2e0,
2278 		0x1f300, 0x1f384,
2279 		0x1f3c0, 0x1f3c8,
2280 		0x1f408, 0x1f40c,
2281 		0x1f440, 0x1f444,
2282 		0x1f44c, 0x1f44c,
2283 		0x1f684, 0x1f690,
2284 		0x1f6c0, 0x1f6c0,
2285 		0x1f6e0, 0x1f6e0,
2286 		0x1f700, 0x1f784,
2287 		0x1f7c0, 0x1f7c8,
2288 		0x1f808, 0x1f80c,
2289 		0x1f840, 0x1f844,
2290 		0x1f84c, 0x1f84c,
2291 		0x1fa84, 0x1fa90,
2292 		0x1fac0, 0x1fac0,
2293 		0x1fae0, 0x1fae0,
2294 		0x1fb00, 0x1fb84,
2295 		0x1fbc0, 0x1fbc8,
2296 		0x1fc08, 0x1fc0c,
2297 		0x1fc40, 0x1fc44,
2298 		0x1fc4c, 0x1fc4c,
2299 		0x1fe84, 0x1fe90,
2300 		0x1fec0, 0x1fec0,
2301 		0x1fee0, 0x1fee0,
2302 		0x1ff00, 0x1ff84,
2303 		0x1ffc0, 0x1ffc8,
2304 		0x30000, 0x30030,
2305 		0x30100, 0x30168,
2306 		0x30190, 0x301a0,
2307 		0x301a8, 0x301b8,
2308 		0x301c4, 0x301c8,
2309 		0x301d0, 0x301d0,
2310 		0x30200, 0x30320,
2311 		0x30400, 0x304b4,
2312 		0x304c0, 0x3052c,
2313 		0x30540, 0x3061c,
2314 		0x30800, 0x308a0,
2315 		0x308c0, 0x30908,
2316 		0x30910, 0x309b8,
2317 		0x30a00, 0x30a04,
2318 		0x30a0c, 0x30a14,
2319 		0x30a1c, 0x30a2c,
2320 		0x30a44, 0x30a50,
2321 		0x30a74, 0x30a74,
2322 		0x30a7c, 0x30afc,
2323 		0x30b08, 0x30c24,
2324 		0x30d00, 0x30d14,
2325 		0x30d1c, 0x30d3c,
2326 		0x30d44, 0x30d4c,
2327 		0x30d54, 0x30d74,
2328 		0x30d7c, 0x30d7c,
2329 		0x30de0, 0x30de0,
2330 		0x30e00, 0x30ed4,
2331 		0x30f00, 0x30fa4,
2332 		0x30fc0, 0x30fc4,
2333 		0x31000, 0x31004,
2334 		0x31080, 0x310fc,
2335 		0x31208, 0x31220,
2336 		0x3123c, 0x31254,
2337 		0x31300, 0x31300,
2338 		0x31308, 0x3131c,
2339 		0x31338, 0x3133c,
2340 		0x31380, 0x31380,
2341 		0x31388, 0x313a8,
2342 		0x313b4, 0x313b4,
2343 		0x31400, 0x31420,
2344 		0x31438, 0x3143c,
2345 		0x31480, 0x31480,
2346 		0x314a8, 0x314a8,
2347 		0x314b0, 0x314b4,
2348 		0x314c8, 0x314d4,
2349 		0x31a40, 0x31a4c,
2350 		0x31af0, 0x31b20,
2351 		0x31b38, 0x31b3c,
2352 		0x31b80, 0x31b80,
2353 		0x31ba8, 0x31ba8,
2354 		0x31bb0, 0x31bb4,
2355 		0x31bc8, 0x31bd4,
2356 		0x32140, 0x3218c,
2357 		0x321f0, 0x321f4,
2358 		0x32200, 0x32200,
2359 		0x32218, 0x32218,
2360 		0x32400, 0x32400,
2361 		0x32408, 0x3241c,
2362 		0x32618, 0x32620,
2363 		0x32664, 0x32664,
2364 		0x326a8, 0x326a8,
2365 		0x326ec, 0x326ec,
2366 		0x32a00, 0x32abc,
2367 		0x32b00, 0x32b18,
2368 		0x32b20, 0x32b38,
2369 		0x32b40, 0x32b58,
2370 		0x32b60, 0x32b78,
2371 		0x32c00, 0x32c00,
2372 		0x32c08, 0x32c3c,
2373 		0x33000, 0x3302c,
2374 		0x33034, 0x33050,
2375 		0x33058, 0x33058,
2376 		0x33060, 0x3308c,
2377 		0x3309c, 0x330ac,
2378 		0x330c0, 0x330c0,
2379 		0x330c8, 0x330d0,
2380 		0x330d8, 0x330e0,
2381 		0x330ec, 0x3312c,
2382 		0x33134, 0x33150,
2383 		0x33158, 0x33158,
2384 		0x33160, 0x3318c,
2385 		0x3319c, 0x331ac,
2386 		0x331c0, 0x331c0,
2387 		0x331c8, 0x331d0,
2388 		0x331d8, 0x331e0,
2389 		0x331ec, 0x33290,
2390 		0x33298, 0x332c4,
2391 		0x332e4, 0x33390,
2392 		0x33398, 0x333c4,
2393 		0x333e4, 0x3342c,
2394 		0x33434, 0x33450,
2395 		0x33458, 0x33458,
2396 		0x33460, 0x3348c,
2397 		0x3349c, 0x334ac,
2398 		0x334c0, 0x334c0,
2399 		0x334c8, 0x334d0,
2400 		0x334d8, 0x334e0,
2401 		0x334ec, 0x3352c,
2402 		0x33534, 0x33550,
2403 		0x33558, 0x33558,
2404 		0x33560, 0x3358c,
2405 		0x3359c, 0x335ac,
2406 		0x335c0, 0x335c0,
2407 		0x335c8, 0x335d0,
2408 		0x335d8, 0x335e0,
2409 		0x335ec, 0x33690,
2410 		0x33698, 0x336c4,
2411 		0x336e4, 0x33790,
2412 		0x33798, 0x337c4,
2413 		0x337e4, 0x337fc,
2414 		0x33814, 0x33814,
2415 		0x33854, 0x33868,
2416 		0x33880, 0x3388c,
2417 		0x338c0, 0x338d0,
2418 		0x338e8, 0x338ec,
2419 		0x33900, 0x3392c,
2420 		0x33934, 0x33950,
2421 		0x33958, 0x33958,
2422 		0x33960, 0x3398c,
2423 		0x3399c, 0x339ac,
2424 		0x339c0, 0x339c0,
2425 		0x339c8, 0x339d0,
2426 		0x339d8, 0x339e0,
2427 		0x339ec, 0x33a90,
2428 		0x33a98, 0x33ac4,
2429 		0x33ae4, 0x33b10,
2430 		0x33b24, 0x33b28,
2431 		0x33b38, 0x33b50,
2432 		0x33bf0, 0x33c10,
2433 		0x33c24, 0x33c28,
2434 		0x33c38, 0x33c50,
2435 		0x33cf0, 0x33cfc,
2436 		0x34000, 0x34030,
2437 		0x34100, 0x34168,
2438 		0x34190, 0x341a0,
2439 		0x341a8, 0x341b8,
2440 		0x341c4, 0x341c8,
2441 		0x341d0, 0x341d0,
2442 		0x34200, 0x34320,
2443 		0x34400, 0x344b4,
2444 		0x344c0, 0x3452c,
2445 		0x34540, 0x3461c,
2446 		0x34800, 0x348a0,
2447 		0x348c0, 0x34908,
2448 		0x34910, 0x349b8,
2449 		0x34a00, 0x34a04,
2450 		0x34a0c, 0x34a14,
2451 		0x34a1c, 0x34a2c,
2452 		0x34a44, 0x34a50,
2453 		0x34a74, 0x34a74,
2454 		0x34a7c, 0x34afc,
2455 		0x34b08, 0x34c24,
2456 		0x34d00, 0x34d14,
2457 		0x34d1c, 0x34d3c,
2458 		0x34d44, 0x34d4c,
2459 		0x34d54, 0x34d74,
2460 		0x34d7c, 0x34d7c,
2461 		0x34de0, 0x34de0,
2462 		0x34e00, 0x34ed4,
2463 		0x34f00, 0x34fa4,
2464 		0x34fc0, 0x34fc4,
2465 		0x35000, 0x35004,
2466 		0x35080, 0x350fc,
2467 		0x35208, 0x35220,
2468 		0x3523c, 0x35254,
2469 		0x35300, 0x35300,
2470 		0x35308, 0x3531c,
2471 		0x35338, 0x3533c,
2472 		0x35380, 0x35380,
2473 		0x35388, 0x353a8,
2474 		0x353b4, 0x353b4,
2475 		0x35400, 0x35420,
2476 		0x35438, 0x3543c,
2477 		0x35480, 0x35480,
2478 		0x354a8, 0x354a8,
2479 		0x354b0, 0x354b4,
2480 		0x354c8, 0x354d4,
2481 		0x35a40, 0x35a4c,
2482 		0x35af0, 0x35b20,
2483 		0x35b38, 0x35b3c,
2484 		0x35b80, 0x35b80,
2485 		0x35ba8, 0x35ba8,
2486 		0x35bb0, 0x35bb4,
2487 		0x35bc8, 0x35bd4,
2488 		0x36140, 0x3618c,
2489 		0x361f0, 0x361f4,
2490 		0x36200, 0x36200,
2491 		0x36218, 0x36218,
2492 		0x36400, 0x36400,
2493 		0x36408, 0x3641c,
2494 		0x36618, 0x36620,
2495 		0x36664, 0x36664,
2496 		0x366a8, 0x366a8,
2497 		0x366ec, 0x366ec,
2498 		0x36a00, 0x36abc,
2499 		0x36b00, 0x36b18,
2500 		0x36b20, 0x36b38,
2501 		0x36b40, 0x36b58,
2502 		0x36b60, 0x36b78,
2503 		0x36c00, 0x36c00,
2504 		0x36c08, 0x36c3c,
2505 		0x37000, 0x3702c,
2506 		0x37034, 0x37050,
2507 		0x37058, 0x37058,
2508 		0x37060, 0x3708c,
2509 		0x3709c, 0x370ac,
2510 		0x370c0, 0x370c0,
2511 		0x370c8, 0x370d0,
2512 		0x370d8, 0x370e0,
2513 		0x370ec, 0x3712c,
2514 		0x37134, 0x37150,
2515 		0x37158, 0x37158,
2516 		0x37160, 0x3718c,
2517 		0x3719c, 0x371ac,
2518 		0x371c0, 0x371c0,
2519 		0x371c8, 0x371d0,
2520 		0x371d8, 0x371e0,
2521 		0x371ec, 0x37290,
2522 		0x37298, 0x372c4,
2523 		0x372e4, 0x37390,
2524 		0x37398, 0x373c4,
2525 		0x373e4, 0x3742c,
2526 		0x37434, 0x37450,
2527 		0x37458, 0x37458,
2528 		0x37460, 0x3748c,
2529 		0x3749c, 0x374ac,
2530 		0x374c0, 0x374c0,
2531 		0x374c8, 0x374d0,
2532 		0x374d8, 0x374e0,
2533 		0x374ec, 0x3752c,
2534 		0x37534, 0x37550,
2535 		0x37558, 0x37558,
2536 		0x37560, 0x3758c,
2537 		0x3759c, 0x375ac,
2538 		0x375c0, 0x375c0,
2539 		0x375c8, 0x375d0,
2540 		0x375d8, 0x375e0,
2541 		0x375ec, 0x37690,
2542 		0x37698, 0x376c4,
2543 		0x376e4, 0x37790,
2544 		0x37798, 0x377c4,
2545 		0x377e4, 0x377fc,
2546 		0x37814, 0x37814,
2547 		0x37854, 0x37868,
2548 		0x37880, 0x3788c,
2549 		0x378c0, 0x378d0,
2550 		0x378e8, 0x378ec,
2551 		0x37900, 0x3792c,
2552 		0x37934, 0x37950,
2553 		0x37958, 0x37958,
2554 		0x37960, 0x3798c,
2555 		0x3799c, 0x379ac,
2556 		0x379c0, 0x379c0,
2557 		0x379c8, 0x379d0,
2558 		0x379d8, 0x379e0,
2559 		0x379ec, 0x37a90,
2560 		0x37a98, 0x37ac4,
2561 		0x37ae4, 0x37b10,
2562 		0x37b24, 0x37b28,
2563 		0x37b38, 0x37b50,
2564 		0x37bf0, 0x37c10,
2565 		0x37c24, 0x37c28,
2566 		0x37c38, 0x37c50,
2567 		0x37cf0, 0x37cfc,
2568 		0x40040, 0x40040,
2569 		0x40080, 0x40084,
2570 		0x40100, 0x40100,
2571 		0x40140, 0x401bc,
2572 		0x40200, 0x40214,
2573 		0x40228, 0x40228,
2574 		0x40240, 0x40258,
2575 		0x40280, 0x40280,
2576 		0x40304, 0x40304,
2577 		0x40330, 0x4033c,
2578 		0x41304, 0x413c8,
2579 		0x413d0, 0x413dc,
2580 		0x413f0, 0x413f0,
2581 		0x41400, 0x4140c,
2582 		0x41414, 0x4141c,
2583 		0x41480, 0x414d0,
2584 		0x44000, 0x4407c,
2585 		0x440c0, 0x441ac,
2586 		0x441b4, 0x4427c,
2587 		0x442c0, 0x443ac,
2588 		0x443b4, 0x4447c,
2589 		0x444c0, 0x445ac,
2590 		0x445b4, 0x4467c,
2591 		0x446c0, 0x447ac,
2592 		0x447b4, 0x4487c,
2593 		0x448c0, 0x449ac,
2594 		0x449b4, 0x44a7c,
2595 		0x44ac0, 0x44bac,
2596 		0x44bb4, 0x44c7c,
2597 		0x44cc0, 0x44dac,
2598 		0x44db4, 0x44e7c,
2599 		0x44ec0, 0x44fac,
2600 		0x44fb4, 0x4507c,
2601 		0x450c0, 0x451ac,
2602 		0x451b4, 0x451fc,
2603 		0x45800, 0x45804,
2604 		0x45810, 0x45830,
2605 		0x45840, 0x45860,
2606 		0x45868, 0x45868,
2607 		0x45880, 0x45884,
2608 		0x458a0, 0x458b0,
2609 		0x45a00, 0x45a04,
2610 		0x45a10, 0x45a30,
2611 		0x45a40, 0x45a60,
2612 		0x45a68, 0x45a68,
2613 		0x45a80, 0x45a84,
2614 		0x45aa0, 0x45ab0,
2615 		0x460c0, 0x460e4,
2616 		0x47000, 0x4703c,
2617 		0x47044, 0x4708c,
2618 		0x47200, 0x47250,
2619 		0x47400, 0x47408,
2620 		0x47414, 0x47420,
2621 		0x47600, 0x47618,
2622 		0x47800, 0x47814,
2623 		0x47820, 0x4782c,
2624 		0x50000, 0x50084,
2625 		0x50090, 0x500cc,
2626 		0x50300, 0x50384,
2627 		0x50400, 0x50400,
2628 		0x50800, 0x50884,
2629 		0x50890, 0x508cc,
2630 		0x50b00, 0x50b84,
2631 		0x50c00, 0x50c00,
2632 		0x51000, 0x51020,
2633 		0x51028, 0x510b0,
2634 		0x51300, 0x51324,
2635 	};
2636 
2637 	static const unsigned int t6vf_reg_ranges[] = {
2638 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2639 		VF_MPS_REG(A_MPS_VF_CTL),
2640 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2641 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2642 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2643 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2644 		FW_T6VF_MBDATA_BASE_ADDR,
2645 		FW_T6VF_MBDATA_BASE_ADDR +
2646 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2647 	};
2648 
2649 	u32 *buf_end = (u32 *)(buf + buf_size);
2650 	const unsigned int *reg_ranges;
2651 	int reg_ranges_size, range;
2652 	unsigned int chip_version = chip_id(adap);
2653 
2654 	/*
2655 	 * Select the right set of register ranges to dump depending on the
2656 	 * adapter chip type.
2657 	 */
2658 	switch (chip_version) {
2659 	case CHELSIO_T4:
2660 		if (adap->flags & IS_VF) {
2661 			reg_ranges = t4vf_reg_ranges;
2662 			reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2663 		} else {
2664 			reg_ranges = t4_reg_ranges;
2665 			reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2666 		}
2667 		break;
2668 
2669 	case CHELSIO_T5:
2670 		if (adap->flags & IS_VF) {
2671 			reg_ranges = t5vf_reg_ranges;
2672 			reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2673 		} else {
2674 			reg_ranges = t5_reg_ranges;
2675 			reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2676 		}
2677 		break;
2678 
2679 	case CHELSIO_T6:
2680 		if (adap->flags & IS_VF) {
2681 			reg_ranges = t6vf_reg_ranges;
2682 			reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2683 		} else {
2684 			reg_ranges = t6_reg_ranges;
2685 			reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2686 		}
2687 		break;
2688 
2689 	default:
2690 		CH_ERR(adap,
2691 			"Unsupported chip version %d\n", chip_version);
2692 		return;
2693 	}
2694 
2695 	/*
2696 	 * Clear the register buffer and insert the appropriate register
2697 	 * values selected by the above register ranges.
2698 	 */
2699 	memset(buf, 0, buf_size);
2700 	for (range = 0; range < reg_ranges_size; range += 2) {
2701 		unsigned int reg = reg_ranges[range];
2702 		unsigned int last_reg = reg_ranges[range + 1];
2703 		u32 *bufp = (u32 *)(buf + reg);
2704 
2705 		/*
2706 		 * Iterate across the register range filling in the register
2707 		 * buffer but don't write past the end of the register buffer.
2708 		 */
2709 		while (reg <= last_reg && bufp < buf_end) {
2710 			*bufp++ = t4_read_reg(adap, reg);
2711 			reg += sizeof(u32);
2712 		}
2713 	}
2714 }
2715 
2716 /*
2717  * Partial EEPROM Vital Product Data structure.  The VPD starts with one ID
2718  * header followed by one or more VPD-R sections, each with its own header.
2719  */
2720 struct t4_vpd_hdr {
2721 	u8  id_tag;
2722 	u8  id_len[2];
2723 	u8  id_data[ID_LEN];
2724 };
2725 
2726 struct t4_vpdr_hdr {
2727 	u8  vpdr_tag;
2728 	u8  vpdr_len[2];
2729 };
2730 
2731 /*
2732  * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2733  */
2734 #define EEPROM_DELAY		10		/* 10us per poll spin */
2735 #define EEPROM_MAX_POLL		5000		/* x 5000 == 50ms */
2736 
2737 #define EEPROM_STAT_ADDR	0x7bfc
2738 #define VPD_SIZE		0x800
2739 #define VPD_BASE		0x400
2740 #define VPD_BASE_OLD		0
2741 #define VPD_LEN			1024
2742 #define VPD_INFO_FLD_HDR_SIZE	3
2743 #define CHELSIO_VPD_UNIQUE_ID	0x82
2744 
2745 /*
2746  * Small utility function to wait till any outstanding VPD Access is complete.
2747  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2748  * VPD Access in flight.  This allows us to handle the problem of having a
2749  * previous VPD Access time out and prevent an attempt to inject a new VPD
2750  * Request before any in-flight VPD reguest has completed.
2751  */
2752 static int t4_seeprom_wait(struct adapter *adapter)
2753 {
2754 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2755 	int max_poll;
2756 
2757 	/*
2758 	 * If no VPD Access is in flight, we can just return success right
2759 	 * away.
2760 	 */
2761 	if (!adapter->vpd_busy)
2762 		return 0;
2763 
2764 	/*
2765 	 * Poll the VPD Capability Address/Flag register waiting for it
2766 	 * to indicate that the operation is complete.
2767 	 */
2768 	max_poll = EEPROM_MAX_POLL;
2769 	do {
2770 		u16 val;
2771 
2772 		udelay(EEPROM_DELAY);
2773 		t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2774 
2775 		/*
2776 		 * If the operation is complete, mark the VPD as no longer
2777 		 * busy and return success.
2778 		 */
2779 		if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2780 			adapter->vpd_busy = 0;
2781 			return 0;
2782 		}
2783 	} while (--max_poll);
2784 
2785 	/*
2786 	 * Failure!  Note that we leave the VPD Busy status set in order to
2787 	 * avoid pushing a new VPD Access request into the VPD Capability till
2788 	 * the current operation eventually succeeds.  It's a bug to issue a
2789 	 * new request when an existing request is in flight and will result
2790 	 * in corrupt hardware state.
2791 	 */
2792 	return -ETIMEDOUT;
2793 }
2794 
2795 /**
2796  *	t4_seeprom_read - read a serial EEPROM location
2797  *	@adapter: adapter to read
2798  *	@addr: EEPROM virtual address
2799  *	@data: where to store the read data
2800  *
2801  *	Read a 32-bit word from a location in serial EEPROM using the card's PCI
2802  *	VPD capability.  Note that this function must be called with a virtual
2803  *	address.
2804  */
2805 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2806 {
2807 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2808 	int ret;
2809 
2810 	/*
2811 	 * VPD Accesses must alway be 4-byte aligned!
2812 	 */
2813 	if (addr >= EEPROMVSIZE || (addr & 3))
2814 		return -EINVAL;
2815 
2816 	/*
2817 	 * Wait for any previous operation which may still be in flight to
2818 	 * complete.
2819 	 */
2820 	ret = t4_seeprom_wait(adapter);
2821 	if (ret) {
2822 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2823 		return ret;
2824 	}
2825 
2826 	/*
2827 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2828 	 * for our request to complete.  If it doesn't complete, note the
2829 	 * error and return it to our caller.  Note that we do not reset the
2830 	 * VPD Busy status!
2831 	 */
2832 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2833 	adapter->vpd_busy = 1;
2834 	adapter->vpd_flag = PCI_VPD_ADDR_F;
2835 	ret = t4_seeprom_wait(adapter);
2836 	if (ret) {
2837 		CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2838 		return ret;
2839 	}
2840 
2841 	/*
2842 	 * Grab the returned data, swizzle it into our endianness and
2843 	 * return success.
2844 	 */
2845 	t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2846 	*data = le32_to_cpu(*data);
2847 	return 0;
2848 }
2849 
2850 /**
2851  *	t4_seeprom_write - write a serial EEPROM location
2852  *	@adapter: adapter to write
2853  *	@addr: virtual EEPROM address
2854  *	@data: value to write
2855  *
2856  *	Write a 32-bit word to a location in serial EEPROM using the card's PCI
2857  *	VPD capability.  Note that this function must be called with a virtual
2858  *	address.
2859  */
2860 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2861 {
2862 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2863 	int ret;
2864 	u32 stats_reg;
2865 	int max_poll;
2866 
2867 	/*
2868 	 * VPD Accesses must alway be 4-byte aligned!
2869 	 */
2870 	if (addr >= EEPROMVSIZE || (addr & 3))
2871 		return -EINVAL;
2872 
2873 	/*
2874 	 * Wait for any previous operation which may still be in flight to
2875 	 * complete.
2876 	 */
2877 	ret = t4_seeprom_wait(adapter);
2878 	if (ret) {
2879 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2880 		return ret;
2881 	}
2882 
2883 	/*
2884 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2885 	 * for our request to complete.  If it doesn't complete, note the
2886 	 * error and return it to our caller.  Note that we do not reset the
2887 	 * VPD Busy status!
2888 	 */
2889 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2890 				 cpu_to_le32(data));
2891 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2892 				 (u16)addr | PCI_VPD_ADDR_F);
2893 	adapter->vpd_busy = 1;
2894 	adapter->vpd_flag = 0;
2895 	ret = t4_seeprom_wait(adapter);
2896 	if (ret) {
2897 		CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2898 		return ret;
2899 	}
2900 
2901 	/*
2902 	 * Reset PCI_VPD_DATA register after a transaction and wait for our
2903 	 * request to complete. If it doesn't complete, return error.
2904 	 */
2905 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2906 	max_poll = EEPROM_MAX_POLL;
2907 	do {
2908 		udelay(EEPROM_DELAY);
2909 		t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2910 	} while ((stats_reg & 0x1) && --max_poll);
2911 	if (!max_poll)
2912 		return -ETIMEDOUT;
2913 
2914 	/* Return success! */
2915 	return 0;
2916 }
2917 
2918 /**
2919  *	t4_eeprom_ptov - translate a physical EEPROM address to virtual
2920  *	@phys_addr: the physical EEPROM address
2921  *	@fn: the PCI function number
2922  *	@sz: size of function-specific area
2923  *
2924  *	Translate a physical EEPROM address to virtual.  The first 1K is
2925  *	accessed through virtual addresses starting at 31K, the rest is
2926  *	accessed through virtual addresses starting at 0.
2927  *
2928  *	The mapping is as follows:
2929  *	[0..1K) -> [31K..32K)
2930  *	[1K..1K+A) -> [ES-A..ES)
2931  *	[1K+A..ES) -> [0..ES-A-1K)
2932  *
2933  *	where A = @fn * @sz, and ES = EEPROM size.
2934  */
2935 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2936 {
2937 	fn *= sz;
2938 	if (phys_addr < 1024)
2939 		return phys_addr + (31 << 10);
2940 	if (phys_addr < 1024 + fn)
2941 		return EEPROMSIZE - fn + phys_addr - 1024;
2942 	if (phys_addr < EEPROMSIZE)
2943 		return phys_addr - 1024 - fn;
2944 	return -EINVAL;
2945 }
2946 
2947 /**
2948  *	t4_seeprom_wp - enable/disable EEPROM write protection
2949  *	@adapter: the adapter
2950  *	@enable: whether to enable or disable write protection
2951  *
2952  *	Enables or disables write protection on the serial EEPROM.
2953  */
2954 int t4_seeprom_wp(struct adapter *adapter, int enable)
2955 {
2956 	return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2957 }
2958 
2959 /**
2960  *	get_vpd_keyword_val - Locates an information field keyword in the VPD
2961  *	@vpd: Pointer to buffered vpd data structure
2962  *	@kw: The keyword to search for
2963  *	@region: VPD region to search (starting from 0)
2964  *
2965  *	Returns the value of the information field keyword or
2966  *	-ENOENT otherwise.
2967  */
2968 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
2969 {
2970 	int i, tag;
2971 	unsigned int offset, len;
2972 	const struct t4_vpdr_hdr *vpdr;
2973 
2974 	offset = sizeof(struct t4_vpd_hdr);
2975 	vpdr = (const void *)(vpd + offset);
2976 	tag = vpdr->vpdr_tag;
2977 	len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2978 	while (region--) {
2979 		offset += sizeof(struct t4_vpdr_hdr) + len;
2980 		vpdr = (const void *)(vpd + offset);
2981 		if (++tag != vpdr->vpdr_tag)
2982 			return -ENOENT;
2983 		len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2984 	}
2985 	offset += sizeof(struct t4_vpdr_hdr);
2986 
2987 	if (offset + len > VPD_LEN) {
2988 		return -ENOENT;
2989 	}
2990 
2991 	for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2992 		if (memcmp(vpd + i , kw , 2) == 0){
2993 			i += VPD_INFO_FLD_HDR_SIZE;
2994 			return i;
2995 		}
2996 
2997 		i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2];
2998 	}
2999 
3000 	return -ENOENT;
3001 }
3002 
3003 
3004 /**
3005  *	get_vpd_params - read VPD parameters from VPD EEPROM
3006  *	@adapter: adapter to read
3007  *	@p: where to store the parameters
3008  *	@vpd: caller provided temporary space to read the VPD into
3009  *
3010  *	Reads card parameters stored in VPD EEPROM.
3011  */
3012 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
3013     uint16_t device_id, u32 *buf)
3014 {
3015 	int i, ret, addr;
3016 	int ec, sn, pn, na, md;
3017 	u8 csum;
3018 	const u8 *vpd = (const u8 *)buf;
3019 
3020 	/*
3021 	 * Card information normally starts at VPD_BASE but early cards had
3022 	 * it at 0.
3023 	 */
3024 	ret = t4_seeprom_read(adapter, VPD_BASE, buf);
3025 	if (ret)
3026 		return (ret);
3027 
3028 	/*
3029 	 * The VPD shall have a unique identifier specified by the PCI SIG.
3030 	 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
3031 	 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
3032 	 * is expected to automatically put this entry at the
3033 	 * beginning of the VPD.
3034 	 */
3035 	addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
3036 
3037 	for (i = 0; i < VPD_LEN; i += 4) {
3038 		ret = t4_seeprom_read(adapter, addr + i, buf++);
3039 		if (ret)
3040 			return ret;
3041 	}
3042 
3043 #define FIND_VPD_KW(var,name) do { \
3044 	var = get_vpd_keyword_val(vpd, name, 0); \
3045 	if (var < 0) { \
3046 		CH_ERR(adapter, "missing VPD keyword " name "\n"); \
3047 		return -EINVAL; \
3048 	} \
3049 } while (0)
3050 
3051 	FIND_VPD_KW(i, "RV");
3052 	for (csum = 0; i >= 0; i--)
3053 		csum += vpd[i];
3054 
3055 	if (csum) {
3056 		CH_ERR(adapter,
3057 			"corrupted VPD EEPROM, actual csum %u\n", csum);
3058 		return -EINVAL;
3059 	}
3060 
3061 	FIND_VPD_KW(ec, "EC");
3062 	FIND_VPD_KW(sn, "SN");
3063 	FIND_VPD_KW(pn, "PN");
3064 	FIND_VPD_KW(na, "NA");
3065 #undef FIND_VPD_KW
3066 
3067 	memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN);
3068 	strstrip(p->id);
3069 	memcpy(p->ec, vpd + ec, EC_LEN);
3070 	strstrip(p->ec);
3071 	i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3072 	memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3073 	strstrip(p->sn);
3074 	i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3075 	memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3076 	strstrip((char *)p->pn);
3077 	i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3078 	memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3079 	strstrip((char *)p->na);
3080 
3081 	if (device_id & 0x80)
3082 		return 0;	/* Custom card */
3083 
3084 	md = get_vpd_keyword_val(vpd, "VF", 1);
3085 	if (md < 0) {
3086 		snprintf(p->md, sizeof(p->md), "unknown");
3087 	} else {
3088 		i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2];
3089 		memcpy(p->md, vpd + md, min(i, MD_LEN));
3090 		strstrip((char *)p->md);
3091 	}
3092 
3093 	return 0;
3094 }
3095 
3096 /* serial flash and firmware constants and flash config file constants */
3097 enum {
3098 	SF_ATTEMPTS = 10,	/* max retries for SF operations */
3099 
3100 	/* flash command opcodes */
3101 	SF_PROG_PAGE    = 2,	/* program 256B page */
3102 	SF_WR_DISABLE   = 4,	/* disable writes */
3103 	SF_RD_STATUS    = 5,	/* read status register */
3104 	SF_WR_ENABLE    = 6,	/* enable writes */
3105 	SF_RD_DATA_FAST = 0xb,	/* read flash */
3106 	SF_RD_ID	= 0x9f,	/* read ID */
3107 	SF_ERASE_SECTOR = 0xd8,	/* erase 64KB sector */
3108 };
3109 
3110 /**
3111  *	sf1_read - read data from the serial flash
3112  *	@adapter: the adapter
3113  *	@byte_cnt: number of bytes to read
3114  *	@cont: whether another operation will be chained
3115  *	@lock: whether to lock SF for PL access only
3116  *	@valp: where to store the read data
3117  *
3118  *	Reads up to 4 bytes of data from the serial flash.  The location of
3119  *	the read needs to be specified prior to calling this by issuing the
3120  *	appropriate commands to the serial flash.
3121  */
3122 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3123 		    int lock, u32 *valp)
3124 {
3125 	int ret;
3126 
3127 	if (!byte_cnt || byte_cnt > 4)
3128 		return -EINVAL;
3129 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3130 		return -EBUSY;
3131 	t4_write_reg(adapter, A_SF_OP,
3132 		     V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3133 	ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3134 	if (!ret)
3135 		*valp = t4_read_reg(adapter, A_SF_DATA);
3136 	return ret;
3137 }
3138 
3139 /**
3140  *	sf1_write - write data to the serial flash
3141  *	@adapter: the adapter
3142  *	@byte_cnt: number of bytes to write
3143  *	@cont: whether another operation will be chained
3144  *	@lock: whether to lock SF for PL access only
3145  *	@val: value to write
3146  *
3147  *	Writes up to 4 bytes of data to the serial flash.  The location of
3148  *	the write needs to be specified prior to calling this by issuing the
3149  *	appropriate commands to the serial flash.
3150  */
3151 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3152 		     int lock, u32 val)
3153 {
3154 	if (!byte_cnt || byte_cnt > 4)
3155 		return -EINVAL;
3156 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3157 		return -EBUSY;
3158 	t4_write_reg(adapter, A_SF_DATA, val);
3159 	t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3160 		     V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3161 	return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3162 }
3163 
3164 /**
3165  *	flash_wait_op - wait for a flash operation to complete
3166  *	@adapter: the adapter
3167  *	@attempts: max number of polls of the status register
3168  *	@delay: delay between polls in ms
3169  *
3170  *	Wait for a flash operation to complete by polling the status register.
3171  */
3172 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3173 {
3174 	int ret;
3175 	u32 status;
3176 
3177 	while (1) {
3178 		if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3179 		    (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3180 			return ret;
3181 		if (!(status & 1))
3182 			return 0;
3183 		if (--attempts == 0)
3184 			return -EAGAIN;
3185 		if (delay)
3186 			msleep(delay);
3187 	}
3188 }
3189 
3190 /**
3191  *	t4_read_flash - read words from serial flash
3192  *	@adapter: the adapter
3193  *	@addr: the start address for the read
3194  *	@nwords: how many 32-bit words to read
3195  *	@data: where to store the read data
3196  *	@byte_oriented: whether to store data as bytes or as words
3197  *
3198  *	Read the specified number of 32-bit words from the serial flash.
3199  *	If @byte_oriented is set the read data is stored as a byte array
3200  *	(i.e., big-endian), otherwise as 32-bit words in the platform's
3201  *	natural endianness.
3202  */
3203 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3204 		  unsigned int nwords, u32 *data, int byte_oriented)
3205 {
3206 	int ret;
3207 
3208 	if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3209 		return -EINVAL;
3210 
3211 	addr = swab32(addr) | SF_RD_DATA_FAST;
3212 
3213 	if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3214 	    (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3215 		return ret;
3216 
3217 	for ( ; nwords; nwords--, data++) {
3218 		ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3219 		if (nwords == 1)
3220 			t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3221 		if (ret)
3222 			return ret;
3223 		if (byte_oriented)
3224 			*data = (__force __u32)(cpu_to_be32(*data));
3225 	}
3226 	return 0;
3227 }
3228 
3229 /**
3230  *	t4_write_flash - write up to a page of data to the serial flash
3231  *	@adapter: the adapter
3232  *	@addr: the start address to write
3233  *	@n: length of data to write in bytes
3234  *	@data: the data to write
3235  *	@byte_oriented: whether to store data as bytes or as words
3236  *
3237  *	Writes up to a page of data (256 bytes) to the serial flash starting
3238  *	at the given address.  All the data must be written to the same page.
3239  *	If @byte_oriented is set the write data is stored as byte stream
3240  *	(i.e. matches what on disk), otherwise in big-endian.
3241  */
3242 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3243 			  unsigned int n, const u8 *data, int byte_oriented)
3244 {
3245 	int ret;
3246 	u32 buf[SF_PAGE_SIZE / 4];
3247 	unsigned int i, c, left, val, offset = addr & 0xff;
3248 
3249 	if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3250 		return -EINVAL;
3251 
3252 	val = swab32(addr) | SF_PROG_PAGE;
3253 
3254 	if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3255 	    (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3256 		goto unlock;
3257 
3258 	for (left = n; left; left -= c) {
3259 		c = min(left, 4U);
3260 		for (val = 0, i = 0; i < c; ++i)
3261 			val = (val << 8) + *data++;
3262 
3263 		if (!byte_oriented)
3264 			val = cpu_to_be32(val);
3265 
3266 		ret = sf1_write(adapter, c, c != left, 1, val);
3267 		if (ret)
3268 			goto unlock;
3269 	}
3270 	ret = flash_wait_op(adapter, 8, 1);
3271 	if (ret)
3272 		goto unlock;
3273 
3274 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3275 
3276 	/* Read the page to verify the write succeeded */
3277 	ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3278 			    byte_oriented);
3279 	if (ret)
3280 		return ret;
3281 
3282 	if (memcmp(data - n, (u8 *)buf + offset, n)) {
3283 		CH_ERR(adapter,
3284 			"failed to correctly write the flash page at %#x\n",
3285 			addr);
3286 		return -EIO;
3287 	}
3288 	return 0;
3289 
3290 unlock:
3291 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3292 	return ret;
3293 }
3294 
3295 /**
3296  *	t4_get_fw_version - read the firmware version
3297  *	@adapter: the adapter
3298  *	@vers: where to place the version
3299  *
3300  *	Reads the FW version from flash.
3301  */
3302 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3303 {
3304 	return t4_read_flash(adapter, FLASH_FW_START +
3305 			     offsetof(struct fw_hdr, fw_ver), 1,
3306 			     vers, 0);
3307 }
3308 
3309 /**
3310  *	t4_get_fw_hdr - read the firmware header
3311  *	@adapter: the adapter
3312  *	@hdr: where to place the version
3313  *
3314  *	Reads the FW header from flash into caller provided buffer.
3315  */
3316 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
3317 {
3318 	return t4_read_flash(adapter, FLASH_FW_START,
3319 	    sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1);
3320 }
3321 
3322 /**
3323  *	t4_get_bs_version - read the firmware bootstrap version
3324  *	@adapter: the adapter
3325  *	@vers: where to place the version
3326  *
3327  *	Reads the FW Bootstrap version from flash.
3328  */
3329 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3330 {
3331 	return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3332 			     offsetof(struct fw_hdr, fw_ver), 1,
3333 			     vers, 0);
3334 }
3335 
3336 /**
3337  *	t4_get_tp_version - read the TP microcode version
3338  *	@adapter: the adapter
3339  *	@vers: where to place the version
3340  *
3341  *	Reads the TP microcode version from flash.
3342  */
3343 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3344 {
3345 	return t4_read_flash(adapter, FLASH_FW_START +
3346 			     offsetof(struct fw_hdr, tp_microcode_ver),
3347 			     1, vers, 0);
3348 }
3349 
3350 /**
3351  *	t4_get_exprom_version - return the Expansion ROM version (if any)
3352  *	@adapter: the adapter
3353  *	@vers: where to place the version
3354  *
3355  *	Reads the Expansion ROM header from FLASH and returns the version
3356  *	number (if present) through the @vers return value pointer.  We return
3357  *	this in the Firmware Version Format since it's convenient.  Return
3358  *	0 on success, -ENOENT if no Expansion ROM is present.
3359  */
3360 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3361 {
3362 	struct exprom_header {
3363 		unsigned char hdr_arr[16];	/* must start with 0x55aa */
3364 		unsigned char hdr_ver[4];	/* Expansion ROM version */
3365 	} *hdr;
3366 	u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3367 					   sizeof(u32))];
3368 	int ret;
3369 
3370 	ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3371 			    ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3372 			    0);
3373 	if (ret)
3374 		return ret;
3375 
3376 	hdr = (struct exprom_header *)exprom_header_buf;
3377 	if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3378 		return -ENOENT;
3379 
3380 	*vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3381 		 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3382 		 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3383 		 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3384 	return 0;
3385 }
3386 
3387 /**
3388  *	t4_get_scfg_version - return the Serial Configuration version
3389  *	@adapter: the adapter
3390  *	@vers: where to place the version
3391  *
3392  *	Reads the Serial Configuration Version via the Firmware interface
3393  *	(thus this can only be called once we're ready to issue Firmware
3394  *	commands).  The format of the Serial Configuration version is
3395  *	adapter specific.  Returns 0 on success, an error on failure.
3396  *
3397  *	Note that early versions of the Firmware didn't include the ability
3398  *	to retrieve the Serial Configuration version, so we zero-out the
3399  *	return-value parameter in that case to avoid leaving it with
3400  *	garbage in it.
3401  *
3402  *	Also note that the Firmware will return its cached copy of the Serial
3403  *	Initialization Revision ID, not the actual Revision ID as written in
3404  *	the Serial EEPROM.  This is only an issue if a new VPD has been written
3405  *	and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3406  *	it's best to defer calling this routine till after a FW_RESET_CMD has
3407  *	been issued if the Host Driver will be performing a full adapter
3408  *	initialization.
3409  */
3410 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3411 {
3412 	u32 scfgrev_param;
3413 	int ret;
3414 
3415 	scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3416 			 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3417 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3418 			      1, &scfgrev_param, vers);
3419 	if (ret)
3420 		*vers = 0;
3421 	return ret;
3422 }
3423 
3424 /**
3425  *	t4_get_vpd_version - return the VPD version
3426  *	@adapter: the adapter
3427  *	@vers: where to place the version
3428  *
3429  *	Reads the VPD via the Firmware interface (thus this can only be called
3430  *	once we're ready to issue Firmware commands).  The format of the
3431  *	VPD version is adapter specific.  Returns 0 on success, an error on
3432  *	failure.
3433  *
3434  *	Note that early versions of the Firmware didn't include the ability
3435  *	to retrieve the VPD version, so we zero-out the return-value parameter
3436  *	in that case to avoid leaving it with garbage in it.
3437  *
3438  *	Also note that the Firmware will return its cached copy of the VPD
3439  *	Revision ID, not the actual Revision ID as written in the Serial
3440  *	EEPROM.  This is only an issue if a new VPD has been written and the
3441  *	Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3442  *	to defer calling this routine till after a FW_RESET_CMD has been issued
3443  *	if the Host Driver will be performing a full adapter initialization.
3444  */
3445 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3446 {
3447 	u32 vpdrev_param;
3448 	int ret;
3449 
3450 	vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3451 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3452 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3453 			      1, &vpdrev_param, vers);
3454 	if (ret)
3455 		*vers = 0;
3456 	return ret;
3457 }
3458 
3459 /**
3460  *	t4_get_version_info - extract various chip/firmware version information
3461  *	@adapter: the adapter
3462  *
3463  *	Reads various chip/firmware version numbers and stores them into the
3464  *	adapter Adapter Parameters structure.  If any of the efforts fails
3465  *	the first failure will be returned, but all of the version numbers
3466  *	will be read.
3467  */
3468 int t4_get_version_info(struct adapter *adapter)
3469 {
3470 	int ret = 0;
3471 
3472 	#define FIRST_RET(__getvinfo) \
3473 	do { \
3474 		int __ret = __getvinfo; \
3475 		if (__ret && !ret) \
3476 			ret = __ret; \
3477 	} while (0)
3478 
3479 	FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3480 	FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3481 	FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3482 	FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3483 	FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3484 	FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3485 
3486 	#undef FIRST_RET
3487 
3488 	return ret;
3489 }
3490 
3491 /**
3492  *	t4_flash_erase_sectors - erase a range of flash sectors
3493  *	@adapter: the adapter
3494  *	@start: the first sector to erase
3495  *	@end: the last sector to erase
3496  *
3497  *	Erases the sectors in the given inclusive range.
3498  */
3499 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3500 {
3501 	int ret = 0;
3502 
3503 	if (end >= adapter->params.sf_nsec)
3504 		return -EINVAL;
3505 
3506 	while (start <= end) {
3507 		if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3508 		    (ret = sf1_write(adapter, 4, 0, 1,
3509 				     SF_ERASE_SECTOR | (start << 8))) != 0 ||
3510 		    (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3511 			CH_ERR(adapter,
3512 				"erase of flash sector %d failed, error %d\n",
3513 				start, ret);
3514 			break;
3515 		}
3516 		start++;
3517 	}
3518 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3519 	return ret;
3520 }
3521 
3522 /**
3523  *	t4_flash_cfg_addr - return the address of the flash configuration file
3524  *	@adapter: the adapter
3525  *
3526  *	Return the address within the flash where the Firmware Configuration
3527  *	File is stored, or an error if the device FLASH is too small to contain
3528  *	a Firmware Configuration File.
3529  */
3530 int t4_flash_cfg_addr(struct adapter *adapter)
3531 {
3532 	/*
3533 	 * If the device FLASH isn't large enough to hold a Firmware
3534 	 * Configuration File, return an error.
3535 	 */
3536 	if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3537 		return -ENOSPC;
3538 
3539 	return FLASH_CFG_START;
3540 }
3541 
3542 /*
3543  * Return TRUE if the specified firmware matches the adapter.  I.e. T4
3544  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3545  * and emit an error message for mismatched firmware to save our caller the
3546  * effort ...
3547  */
3548 static int t4_fw_matches_chip(struct adapter *adap,
3549 			      const struct fw_hdr *hdr)
3550 {
3551 	/*
3552 	 * The expression below will return FALSE for any unsupported adapter
3553 	 * which will keep us "honest" in the future ...
3554 	 */
3555 	if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3556 	    (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3557 	    (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3558 		return 1;
3559 
3560 	CH_ERR(adap,
3561 		"FW image (%d) is not suitable for this adapter (%d)\n",
3562 		hdr->chip, chip_id(adap));
3563 	return 0;
3564 }
3565 
3566 /**
3567  *	t4_load_fw - download firmware
3568  *	@adap: the adapter
3569  *	@fw_data: the firmware image to write
3570  *	@size: image size
3571  *
3572  *	Write the supplied firmware image to the card's serial flash.
3573  */
3574 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3575 {
3576 	u32 csum;
3577 	int ret, addr;
3578 	unsigned int i;
3579 	u8 first_page[SF_PAGE_SIZE];
3580 	const u32 *p = (const u32 *)fw_data;
3581 	const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3582 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3583 	unsigned int fw_start_sec;
3584 	unsigned int fw_start;
3585 	unsigned int fw_size;
3586 
3587 	if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3588 		fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3589 		fw_start = FLASH_FWBOOTSTRAP_START;
3590 		fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3591 	} else {
3592 		fw_start_sec = FLASH_FW_START_SEC;
3593  		fw_start = FLASH_FW_START;
3594 		fw_size = FLASH_FW_MAX_SIZE;
3595 	}
3596 
3597 	if (!size) {
3598 		CH_ERR(adap, "FW image has no data\n");
3599 		return -EINVAL;
3600 	}
3601 	if (size & 511) {
3602 		CH_ERR(adap,
3603 			"FW image size not multiple of 512 bytes\n");
3604 		return -EINVAL;
3605 	}
3606 	if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3607 		CH_ERR(adap,
3608 			"FW image size differs from size in FW header\n");
3609 		return -EINVAL;
3610 	}
3611 	if (size > fw_size) {
3612 		CH_ERR(adap, "FW image too large, max is %u bytes\n",
3613 			fw_size);
3614 		return -EFBIG;
3615 	}
3616 	if (!t4_fw_matches_chip(adap, hdr))
3617 		return -EINVAL;
3618 
3619 	for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3620 		csum += be32_to_cpu(p[i]);
3621 
3622 	if (csum != 0xffffffff) {
3623 		CH_ERR(adap,
3624 			"corrupted firmware image, checksum %#x\n", csum);
3625 		return -EINVAL;
3626 	}
3627 
3628 	i = DIV_ROUND_UP(size, sf_sec_size);	/* # of sectors spanned */
3629 	ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3630 	if (ret)
3631 		goto out;
3632 
3633 	/*
3634 	 * We write the correct version at the end so the driver can see a bad
3635 	 * version if the FW write fails.  Start by writing a copy of the
3636 	 * first page with a bad version.
3637 	 */
3638 	memcpy(first_page, fw_data, SF_PAGE_SIZE);
3639 	((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3640 	ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3641 	if (ret)
3642 		goto out;
3643 
3644 	addr = fw_start;
3645 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3646 		addr += SF_PAGE_SIZE;
3647 		fw_data += SF_PAGE_SIZE;
3648 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3649 		if (ret)
3650 			goto out;
3651 	}
3652 
3653 	ret = t4_write_flash(adap,
3654 			     fw_start + offsetof(struct fw_hdr, fw_ver),
3655 			     sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3656 out:
3657 	if (ret)
3658 		CH_ERR(adap, "firmware download failed, error %d\n",
3659 			ret);
3660 	return ret;
3661 }
3662 
3663 /**
3664  *	t4_fwcache - firmware cache operation
3665  *	@adap: the adapter
3666  *	@op  : the operation (flush or flush and invalidate)
3667  */
3668 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3669 {
3670 	struct fw_params_cmd c;
3671 
3672 	memset(&c, 0, sizeof(c));
3673 	c.op_to_vfn =
3674 	    cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3675 			    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3676 				V_FW_PARAMS_CMD_PFN(adap->pf) |
3677 				V_FW_PARAMS_CMD_VFN(0));
3678 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3679 	c.param[0].mnem =
3680 	    cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3681 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3682 	c.param[0].val = (__force __be32)op;
3683 
3684 	return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3685 }
3686 
3687 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3688 			unsigned int *pif_req_wrptr,
3689 			unsigned int *pif_rsp_wrptr)
3690 {
3691 	int i, j;
3692 	u32 cfg, val, req, rsp;
3693 
3694 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3695 	if (cfg & F_LADBGEN)
3696 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3697 
3698 	val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3699 	req = G_POLADBGWRPTR(val);
3700 	rsp = G_PILADBGWRPTR(val);
3701 	if (pif_req_wrptr)
3702 		*pif_req_wrptr = req;
3703 	if (pif_rsp_wrptr)
3704 		*pif_rsp_wrptr = rsp;
3705 
3706 	for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3707 		for (j = 0; j < 6; j++) {
3708 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3709 				     V_PILADBGRDPTR(rsp));
3710 			*pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3711 			*pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3712 			req++;
3713 			rsp++;
3714 		}
3715 		req = (req + 2) & M_POLADBGRDPTR;
3716 		rsp = (rsp + 2) & M_PILADBGRDPTR;
3717 	}
3718 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3719 }
3720 
3721 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3722 {
3723 	u32 cfg;
3724 	int i, j, idx;
3725 
3726 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3727 	if (cfg & F_LADBGEN)
3728 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3729 
3730 	for (i = 0; i < CIM_MALA_SIZE; i++) {
3731 		for (j = 0; j < 5; j++) {
3732 			idx = 8 * i + j;
3733 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3734 				     V_PILADBGRDPTR(idx));
3735 			*ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3736 			*ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3737 		}
3738 	}
3739 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3740 }
3741 
3742 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3743 {
3744 	unsigned int i, j;
3745 
3746 	for (i = 0; i < 8; i++) {
3747 		u32 *p = la_buf + i;
3748 
3749 		t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3750 		j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3751 		t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3752 		for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3753 			*p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3754 	}
3755 }
3756 
3757 /**
3758  *	fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3759  *	@caps16: a 16-bit Port Capabilities value
3760  *
3761  *	Returns the equivalent 32-bit Port Capabilities value.
3762  */
3763 static uint32_t fwcaps16_to_caps32(uint16_t caps16)
3764 {
3765 	uint32_t caps32 = 0;
3766 
3767 	#define CAP16_TO_CAP32(__cap) \
3768 		do { \
3769 			if (caps16 & FW_PORT_CAP_##__cap) \
3770 				caps32 |= FW_PORT_CAP32_##__cap; \
3771 		} while (0)
3772 
3773 	CAP16_TO_CAP32(SPEED_100M);
3774 	CAP16_TO_CAP32(SPEED_1G);
3775 	CAP16_TO_CAP32(SPEED_25G);
3776 	CAP16_TO_CAP32(SPEED_10G);
3777 	CAP16_TO_CAP32(SPEED_40G);
3778 	CAP16_TO_CAP32(SPEED_100G);
3779 	CAP16_TO_CAP32(FC_RX);
3780 	CAP16_TO_CAP32(FC_TX);
3781 	CAP16_TO_CAP32(ANEG);
3782 	CAP16_TO_CAP32(FORCE_PAUSE);
3783 	CAP16_TO_CAP32(MDIAUTO);
3784 	CAP16_TO_CAP32(MDISTRAIGHT);
3785 	CAP16_TO_CAP32(FEC_RS);
3786 	CAP16_TO_CAP32(FEC_BASER_RS);
3787 	CAP16_TO_CAP32(802_3_PAUSE);
3788 	CAP16_TO_CAP32(802_3_ASM_DIR);
3789 
3790 	#undef CAP16_TO_CAP32
3791 
3792 	return caps32;
3793 }
3794 
3795 /**
3796  *	fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3797  *	@caps32: a 32-bit Port Capabilities value
3798  *
3799  *	Returns the equivalent 16-bit Port Capabilities value.  Note that
3800  *	not all 32-bit Port Capabilities can be represented in the 16-bit
3801  *	Port Capabilities and some fields/values may not make it.
3802  */
3803 static uint16_t fwcaps32_to_caps16(uint32_t caps32)
3804 {
3805 	uint16_t caps16 = 0;
3806 
3807 	#define CAP32_TO_CAP16(__cap) \
3808 		do { \
3809 			if (caps32 & FW_PORT_CAP32_##__cap) \
3810 				caps16 |= FW_PORT_CAP_##__cap; \
3811 		} while (0)
3812 
3813 	CAP32_TO_CAP16(SPEED_100M);
3814 	CAP32_TO_CAP16(SPEED_1G);
3815 	CAP32_TO_CAP16(SPEED_10G);
3816 	CAP32_TO_CAP16(SPEED_25G);
3817 	CAP32_TO_CAP16(SPEED_40G);
3818 	CAP32_TO_CAP16(SPEED_100G);
3819 	CAP32_TO_CAP16(FC_RX);
3820 	CAP32_TO_CAP16(FC_TX);
3821 	CAP32_TO_CAP16(802_3_PAUSE);
3822 	CAP32_TO_CAP16(802_3_ASM_DIR);
3823 	CAP32_TO_CAP16(ANEG);
3824 	CAP32_TO_CAP16(FORCE_PAUSE);
3825 	CAP32_TO_CAP16(MDIAUTO);
3826 	CAP32_TO_CAP16(MDISTRAIGHT);
3827 	CAP32_TO_CAP16(FEC_RS);
3828 	CAP32_TO_CAP16(FEC_BASER_RS);
3829 
3830 	#undef CAP32_TO_CAP16
3831 
3832 	return caps16;
3833 }
3834 
3835 static bool
3836 is_bt(struct port_info *pi)
3837 {
3838 
3839 	return (pi->port_type == FW_PORT_TYPE_BT_SGMII ||
3840 	    pi->port_type == FW_PORT_TYPE_BT_XFI ||
3841 	    pi->port_type == FW_PORT_TYPE_BT_XAUI);
3842 }
3843 
3844 /**
3845  *	t4_link_l1cfg - apply link configuration to MAC/PHY
3846  *	@phy: the PHY to setup
3847  *	@mac: the MAC to setup
3848  *	@lc: the requested link configuration
3849  *
3850  *	Set up a port's MAC and PHY according to a desired link configuration.
3851  *	- If the PHY can auto-negotiate first decide what to advertise, then
3852  *	  enable/disable auto-negotiation as desired, and reset.
3853  *	- If the PHY does not auto-negotiate just reset it.
3854  *	- If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3855  *	  otherwise do it later based on the outcome of auto-negotiation.
3856  */
3857 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3858 		  struct link_config *lc)
3859 {
3860 	struct fw_port_cmd c;
3861 	unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
3862 	unsigned int aneg, fc, fec, speed, rcap;
3863 
3864 	fc = 0;
3865 	if (lc->requested_fc & PAUSE_RX)
3866 		fc |= FW_PORT_CAP32_FC_RX;
3867 	if (lc->requested_fc & PAUSE_TX)
3868 		fc |= FW_PORT_CAP32_FC_TX;
3869 	if (!(lc->requested_fc & PAUSE_AUTONEG))
3870 		fc |= FW_PORT_CAP32_FORCE_PAUSE;
3871 
3872 	fec = 0;
3873 	if (lc->requested_fec == FEC_AUTO)
3874 		fec = lc->fec_hint;
3875 	else {
3876 		if (lc->requested_fec & FEC_RS)
3877 			fec |= FW_PORT_CAP32_FEC_RS;
3878 		if (lc->requested_fec & FEC_BASER_RS)
3879 			fec |= FW_PORT_CAP32_FEC_BASER_RS;
3880 	}
3881 
3882 	if (lc->requested_aneg == AUTONEG_DISABLE)
3883 		aneg = 0;
3884 	else if (lc->requested_aneg == AUTONEG_ENABLE)
3885 		aneg = FW_PORT_CAP32_ANEG;
3886 	else
3887 		aneg = lc->supported & FW_PORT_CAP32_ANEG;
3888 
3889 	if (aneg) {
3890 		speed = lc->supported & V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
3891 	} else if (lc->requested_speed != 0)
3892 		speed = speed_to_fwcap(lc->requested_speed);
3893 	else
3894 		speed = fwcap_top_speed(lc->supported);
3895 
3896 	/* Force AN on for BT cards. */
3897 	if (is_bt(adap->port[adap->chan_map[port]]))
3898 		aneg = lc->supported & FW_PORT_CAP32_ANEG;
3899 
3900 	rcap = aneg | speed | fc | fec;
3901 	if ((rcap | lc->supported) != lc->supported) {
3902 #ifdef INVARIANTS
3903 		CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x\n", rcap,
3904 		    lc->supported);
3905 #endif
3906 		rcap &= lc->supported;
3907 	}
3908 	rcap |= mdi;
3909 
3910 	memset(&c, 0, sizeof(c));
3911 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3912 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3913 				     V_FW_PORT_CMD_PORTID(port));
3914 	if (adap->params.port_caps32) {
3915 		c.action_to_len16 =
3916 		    cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
3917 			FW_LEN16(c));
3918 		c.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
3919 	} else {
3920 		c.action_to_len16 =
3921 		    cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3922 			    FW_LEN16(c));
3923 		c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
3924 	}
3925 
3926 	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3927 }
3928 
3929 /**
3930  *	t4_restart_aneg - restart autonegotiation
3931  *	@adap: the adapter
3932  *	@mbox: mbox to use for the FW command
3933  *	@port: the port id
3934  *
3935  *	Restarts autonegotiation for the selected port.
3936  */
3937 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3938 {
3939 	struct fw_port_cmd c;
3940 
3941 	memset(&c, 0, sizeof(c));
3942 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3943 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3944 				     V_FW_PORT_CMD_PORTID(port));
3945 	c.action_to_len16 =
3946 		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3947 			    FW_LEN16(c));
3948 	c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3949 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3950 }
3951 
3952 struct intr_details {
3953 	u32 mask;
3954 	const char *msg;
3955 };
3956 
3957 struct intr_action {
3958 	u32 mask;
3959 	int arg;
3960 	bool (*action)(struct adapter *, int, bool);
3961 };
3962 
3963 #define NONFATAL_IF_DISABLED 1
3964 struct intr_info {
3965 	const char *name;	/* name of the INT_CAUSE register */
3966 	int cause_reg;		/* INT_CAUSE register */
3967 	int enable_reg;		/* INT_ENABLE register */
3968 	u32 fatal;		/* bits that are fatal */
3969 	int flags;		/* hints */
3970 	const struct intr_details *details;
3971 	const struct intr_action *actions;
3972 };
3973 
3974 static inline char
3975 intr_alert_char(u32 cause, u32 enable, u32 fatal)
3976 {
3977 
3978 	if (cause & fatal)
3979 		return ('!');
3980 	if (cause & enable)
3981 		return ('*');
3982 	return ('-');
3983 }
3984 
3985 static void
3986 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
3987 {
3988 	u32 enable, fatal, leftover;
3989 	const struct intr_details *details;
3990 	char alert;
3991 
3992 	enable = t4_read_reg(adap, ii->enable_reg);
3993 	if (ii->flags & NONFATAL_IF_DISABLED)
3994 		fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);
3995 	else
3996 		fatal = ii->fatal;
3997 	alert = intr_alert_char(cause, enable, fatal);
3998 	CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
3999 	    alert, ii->name, ii->cause_reg, cause, enable, fatal);
4000 
4001 	leftover = cause;
4002 	for (details = ii->details; details && details->mask != 0; details++) {
4003 		u32 msgbits = details->mask & cause;
4004 		if (msgbits == 0)
4005 			continue;
4006 		alert = intr_alert_char(msgbits, enable, ii->fatal);
4007 		CH_ALERT(adap, "  %c [0x%08x] %s\n", alert, msgbits,
4008 		    details->msg);
4009 		leftover &= ~msgbits;
4010 	}
4011 	if (leftover != 0 && leftover != cause)
4012 		CH_ALERT(adap, "  ? [0x%08x]\n", leftover);
4013 }
4014 
4015 /*
4016  * Returns true for fatal error.
4017  */
4018 static bool
4019 t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
4020     u32 additional_cause, bool verbose)
4021 {
4022 	u32 cause, fatal;
4023 	bool rc;
4024 	const struct intr_action *action;
4025 
4026 	/*
4027 	 * Read and display cause.  Note that the top level PL_INT_CAUSE is a
4028 	 * bit special and we need to completely ignore the bits that are not in
4029 	 * PL_INT_ENABLE.
4030 	 */
4031 	cause = t4_read_reg(adap, ii->cause_reg);
4032 	if (ii->cause_reg == A_PL_INT_CAUSE)
4033 		cause &= t4_read_reg(adap, ii->enable_reg);
4034 	if (verbose || cause != 0)
4035 		t4_show_intr_info(adap, ii, cause);
4036 	fatal = cause & ii->fatal;
4037 	if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED)
4038 		fatal &= t4_read_reg(adap, ii->enable_reg);
4039 	cause |= additional_cause;
4040 	if (cause == 0)
4041 		return (false);
4042 
4043 	rc = fatal != 0;
4044 	for (action = ii->actions; action && action->mask != 0; action++) {
4045 		if (!(action->mask & cause))
4046 			continue;
4047 		rc |= (action->action)(adap, action->arg, verbose);
4048 	}
4049 
4050 	/* clear */
4051 	t4_write_reg(adap, ii->cause_reg, cause);
4052 	(void)t4_read_reg(adap, ii->cause_reg);
4053 
4054 	return (rc);
4055 }
4056 
4057 /*
4058  * Interrupt handler for the PCIE module.
4059  */
4060 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
4061 {
4062 	static const struct intr_details sysbus_intr_details[] = {
4063 		{ F_RNPP, "RXNP array parity error" },
4064 		{ F_RPCP, "RXPC array parity error" },
4065 		{ F_RCIP, "RXCIF array parity error" },
4066 		{ F_RCCP, "Rx completions control array parity error" },
4067 		{ F_RFTP, "RXFT array parity error" },
4068 		{ 0 }
4069 	};
4070 	static const struct intr_info sysbus_intr_info = {
4071 		.name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
4072 		.cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4073 		.enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,
4074 		.fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP,
4075 		.flags = 0,
4076 		.details = sysbus_intr_details,
4077 		.actions = NULL,
4078 	};
4079 	static const struct intr_details pcie_port_intr_details[] = {
4080 		{ F_TPCP, "TXPC array parity error" },
4081 		{ F_TNPP, "TXNP array parity error" },
4082 		{ F_TFTP, "TXFT array parity error" },
4083 		{ F_TCAP, "TXCA array parity error" },
4084 		{ F_TCIP, "TXCIF array parity error" },
4085 		{ F_RCAP, "RXCA array parity error" },
4086 		{ F_OTDD, "outbound request TLP discarded" },
4087 		{ F_RDPE, "Rx data parity error" },
4088 		{ F_TDUE, "Tx uncorrectable data error" },
4089 		{ 0 }
4090 	};
4091 	static const struct intr_info pcie_port_intr_info = {
4092 		.name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
4093 		.cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4094 		.enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,
4095 		.fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP |
4096 		    F_OTDD | F_RDPE | F_TDUE,
4097 		.flags = 0,
4098 		.details = pcie_port_intr_details,
4099 		.actions = NULL,
4100 	};
4101 	static const struct intr_details pcie_intr_details[] = {
4102 		{ F_MSIADDRLPERR, "MSI AddrL parity error" },
4103 		{ F_MSIADDRHPERR, "MSI AddrH parity error" },
4104 		{ F_MSIDATAPERR, "MSI data parity error" },
4105 		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error" },
4106 		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error" },
4107 		{ F_MSIXDATAPERR, "MSI-X data parity error" },
4108 		{ F_MSIXDIPERR, "MSI-X DI parity error" },
4109 		{ F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" },
4110 		{ F_PIOREQPERR, "PCIe PIO request FIFO parity error" },
4111 		{ F_TARTAGPERR, "PCIe target tag FIFO parity error" },
4112 		{ F_CCNTPERR, "PCIe CMD channel count parity error" },
4113 		{ F_CREQPERR, "PCIe CMD channel request parity error" },
4114 		{ F_CRSPPERR, "PCIe CMD channel response parity error" },
4115 		{ F_DCNTPERR, "PCIe DMA channel count parity error" },
4116 		{ F_DREQPERR, "PCIe DMA channel request parity error" },
4117 		{ F_DRSPPERR, "PCIe DMA channel response parity error" },
4118 		{ F_HCNTPERR, "PCIe HMA channel count parity error" },
4119 		{ F_HREQPERR, "PCIe HMA channel request parity error" },
4120 		{ F_HRSPPERR, "PCIe HMA channel response parity error" },
4121 		{ F_CFGSNPPERR, "PCIe config snoop FIFO parity error" },
4122 		{ F_FIDPERR, "PCIe FID parity error" },
4123 		{ F_INTXCLRPERR, "PCIe INTx clear parity error" },
4124 		{ F_MATAGPERR, "PCIe MA tag parity error" },
4125 		{ F_PIOTAGPERR, "PCIe PIO tag parity error" },
4126 		{ F_RXCPLPERR, "PCIe Rx completion parity error" },
4127 		{ F_RXWRPERR, "PCIe Rx write parity error" },
4128 		{ F_RPLPERR, "PCIe replay buffer parity error" },
4129 		{ F_PCIESINT, "PCIe core secondary fault" },
4130 		{ F_PCIEPINT, "PCIe core primary fault" },
4131 		{ F_UNXSPLCPLERR, "PCIe unexpected split completion error" },
4132 		{ 0 }
4133 	};
4134 	static const struct intr_details t5_pcie_intr_details[] = {
4135 		{ F_IPGRPPERR, "Parity errors observed by IP" },
4136 		{ F_NONFATALERR, "PCIe non-fatal error" },
4137 		{ F_READRSPERR, "Outbound read error" },
4138 		{ F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" },
4139 		{ F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" },
4140 		{ F_IPRETRYPERR, "PCIe IP replay buffer parity error" },
4141 		{ F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" },
4142 		{ F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" },
4143 		{ F_PIOTAGQPERR, "PIO tag queue FIFO parity error" },
4144 		{ F_MAGRPPERR, "MA group FIFO parity error" },
4145 		{ F_VFIDPERR, "VFID SRAM parity error" },
4146 		{ F_FIDPERR, "FID SRAM parity error" },
4147 		{ F_CFGSNPPERR, "config snoop FIFO parity error" },
4148 		{ F_HRSPPERR, "HMA channel response data SRAM parity error" },
4149 		{ F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4150 		{ F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4151 		{ F_DRSPPERR, "DMA channel response data SRAM parity error" },
4152 		{ F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4153 		{ F_CRSPPERR, "CMD channel response data SRAM parity error" },
4154 		{ F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4155 		{ F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" },
4156 		{ F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" },
4157 		{ F_PIOREQGRPPERR, "PIO request group FIFOs parity error" },
4158 		{ F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" },
4159 		{ F_MSIXDIPERR, "MSI-X DI SRAM parity error" },
4160 		{ F_MSIXDATAPERR, "MSI-X data SRAM parity error" },
4161 		{ F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" },
4162 		{ F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" },
4163 		{ F_MSIXSTIPERR, "MSI-X STI SRAM parity error" },
4164 		{ F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" },
4165 		{ F_MSTGRPPERR, "Master response read queue SRAM parity error" },
4166 		{ 0 }
4167 	};
4168 	struct intr_info pcie_intr_info = {
4169 		.name = "PCIE_INT_CAUSE",
4170 		.cause_reg = A_PCIE_INT_CAUSE,
4171 		.enable_reg = A_PCIE_INT_ENABLE,
4172 		.fatal = 0xffffffff,
4173 		.flags = NONFATAL_IF_DISABLED,
4174 		.details = NULL,
4175 		.actions = NULL,
4176 	};
4177 	bool fatal = false;
4178 
4179 	if (is_t4(adap)) {
4180 		fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
4181 		fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
4182 
4183 		pcie_intr_info.details = pcie_intr_details;
4184 	} else {
4185 		pcie_intr_info.details = t5_pcie_intr_details;
4186 	}
4187 	fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
4188 
4189 	return (fatal);
4190 }
4191 
4192 /*
4193  * TP interrupt handler.
4194  */
4195 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
4196 {
4197 	static const struct intr_details tp_intr_details[] = {
4198 		{ 0x3fffffff, "TP parity error" },
4199 		{ F_FLMTXFLSTEMPTY, "TP out of Tx pages" },
4200 		{ 0 }
4201 	};
4202 	static const struct intr_info tp_intr_info = {
4203 		.name = "TP_INT_CAUSE",
4204 		.cause_reg = A_TP_INT_CAUSE,
4205 		.enable_reg = A_TP_INT_ENABLE,
4206 		.fatal = 0x7fffffff,
4207 		.flags = NONFATAL_IF_DISABLED,
4208 		.details = tp_intr_details,
4209 		.actions = NULL,
4210 	};
4211 
4212 	return (t4_handle_intr(adap, &tp_intr_info, 0, verbose));
4213 }
4214 
4215 /*
4216  * SGE interrupt handler.
4217  */
4218 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
4219 {
4220 	static const struct intr_info sge_int1_info = {
4221 		.name = "SGE_INT_CAUSE1",
4222 		.cause_reg = A_SGE_INT_CAUSE1,
4223 		.enable_reg = A_SGE_INT_ENABLE1,
4224 		.fatal = 0xffffffff,
4225 		.flags = NONFATAL_IF_DISABLED,
4226 		.details = NULL,
4227 		.actions = NULL,
4228 	};
4229 	static const struct intr_info sge_int2_info = {
4230 		.name = "SGE_INT_CAUSE2",
4231 		.cause_reg = A_SGE_INT_CAUSE2,
4232 		.enable_reg = A_SGE_INT_ENABLE2,
4233 		.fatal = 0xffffffff,
4234 		.flags = NONFATAL_IF_DISABLED,
4235 		.details = NULL,
4236 		.actions = NULL,
4237 	};
4238 	static const struct intr_details sge_int3_details[] = {
4239 		{ F_ERR_FLM_DBP,
4240 			"DBP pointer delivery for invalid context or QID" },
4241 		{ F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4242 			"Invalid QID or header request by IDMA" },
4243 		{ F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4244 		{ F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4245 		{ F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4246 		{ F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4247 		{ F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4248 		{ F_ERR_TIMER_ABOVE_MAX_QID,
4249 			"SGE GTS with timer 0-5 for IQID > 1023" },
4250 		{ F_ERR_CPL_EXCEED_IQE_SIZE,
4251 			"SGE received CPL exceeding IQE size" },
4252 		{ F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4253 		{ F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4254 		{ F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4255 		{ F_ERR_DROPPED_DB, "SGE DB dropped" },
4256 		{ F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4257 		  "SGE IQID > 1023 received CPL for FL" },
4258 		{ F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4259 			F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4260 		{ F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4261 		{ F_ERR_ING_CTXT_PRIO,
4262 			"Ingress context manager priority user error" },
4263 		{ F_ERR_EGR_CTXT_PRIO,
4264 			"Egress context manager priority user error" },
4265 		{ F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" },
4266 		{ F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" },
4267 		{ F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4268 		{ F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4269 		{ F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4270 		{ 0x0000000f, "SGE context access for invalid queue" },
4271 		{ 0 }
4272 	};
4273 	static const struct intr_details t6_sge_int3_details[] = {
4274 		{ F_ERR_FLM_DBP,
4275 			"DBP pointer delivery for invalid context or QID" },
4276 		{ F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4277 			"Invalid QID or header request by IDMA" },
4278 		{ F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4279 		{ F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4280 		{ F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4281 		{ F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4282 		{ F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4283 		{ F_ERR_TIMER_ABOVE_MAX_QID,
4284 			"SGE GTS with timer 0-5 for IQID > 1023" },
4285 		{ F_ERR_CPL_EXCEED_IQE_SIZE,
4286 			"SGE received CPL exceeding IQE size" },
4287 		{ F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4288 		{ F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4289 		{ F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4290 		{ F_ERR_DROPPED_DB, "SGE DB dropped" },
4291 		{ F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4292 			"SGE IQID > 1023 received CPL for FL" },
4293 		{ F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4294 			F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4295 		{ F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4296 		{ F_ERR_ING_CTXT_PRIO,
4297 			"Ingress context manager priority user error" },
4298 		{ F_ERR_EGR_CTXT_PRIO,
4299 			"Egress context manager priority user error" },
4300 		{ F_DBP_TBUF_FULL, "SGE DBP tbuf full" },
4301 		{ F_FATAL_WRE_LEN,
4302 			"SGE WRE packet less than advertized length" },
4303 		{ F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4304 		{ F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4305 		{ F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4306 		{ 0x0000000f, "SGE context access for invalid queue" },
4307 		{ 0 }
4308 	};
4309 	struct intr_info sge_int3_info = {
4310 		.name = "SGE_INT_CAUSE3",
4311 		.cause_reg = A_SGE_INT_CAUSE3,
4312 		.enable_reg = A_SGE_INT_ENABLE3,
4313 		.fatal = F_ERR_CPL_EXCEED_IQE_SIZE,
4314 		.flags = 0,
4315 		.details = NULL,
4316 		.actions = NULL,
4317 	};
4318 	static const struct intr_info sge_int4_info = {
4319 		.name = "SGE_INT_CAUSE4",
4320 		.cause_reg = A_SGE_INT_CAUSE4,
4321 		.enable_reg = A_SGE_INT_ENABLE4,
4322 		.fatal = 0,
4323 		.flags = 0,
4324 		.details = NULL,
4325 		.actions = NULL,
4326 	};
4327 	static const struct intr_info sge_int5_info = {
4328 		.name = "SGE_INT_CAUSE5",
4329 		.cause_reg = A_SGE_INT_CAUSE5,
4330 		.enable_reg = A_SGE_INT_ENABLE5,
4331 		.fatal = 0xffffffff,
4332 		.flags = NONFATAL_IF_DISABLED,
4333 		.details = NULL,
4334 		.actions = NULL,
4335 	};
4336 	static const struct intr_info sge_int6_info = {
4337 		.name = "SGE_INT_CAUSE6",
4338 		.cause_reg = A_SGE_INT_CAUSE6,
4339 		.enable_reg = A_SGE_INT_ENABLE6,
4340 		.fatal = 0,
4341 		.flags = 0,
4342 		.details = NULL,
4343 		.actions = NULL,
4344 	};
4345 
4346 	bool fatal;
4347 	u32 v;
4348 
4349 	if (chip_id(adap) <= CHELSIO_T5) {
4350 		sge_int3_info.details = sge_int3_details;
4351 	} else {
4352 		sge_int3_info.details = t6_sge_int3_details;
4353 	}
4354 
4355 	fatal = false;
4356 	fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
4357 	fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
4358 	fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
4359 	fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
4360 	if (chip_id(adap) >= CHELSIO_T5)
4361 		fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
4362 	if (chip_id(adap) >= CHELSIO_T6)
4363 		fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
4364 
4365 	v = t4_read_reg(adap, A_SGE_ERROR_STATS);
4366 	if (v & F_ERROR_QID_VALID) {
4367 		CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v));
4368 		if (v & F_UNCAPTURED_ERROR)
4369 			CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n");
4370 		t4_write_reg(adap, A_SGE_ERROR_STATS,
4371 		    F_ERROR_QID_VALID | F_UNCAPTURED_ERROR);
4372 	}
4373 
4374 	return (fatal);
4375 }
4376 
4377 /*
4378  * CIM interrupt handler.
4379  */
4380 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
4381 {
4382 	static const struct intr_action cim_host_intr_actions[] = {
4383 		{ F_TIMER0INT, 0, t4_os_dump_cimla },
4384 		{ 0 },
4385 	};
4386 	static const struct intr_details cim_host_intr_details[] = {
4387 		/* T6+ */
4388 		{ F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" },
4389 
4390 		/* T5+ */
4391 		{ F_MA_CIM_INTFPERR, "MA2CIM interface parity error" },
4392 		{ F_PLCIM_MSTRSPDATAPARERR,
4393 			"PL2CIM master response data parity error" },
4394 		{ F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" },
4395 		{ F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" },
4396 		{ F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" },
4397 		{ F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" },
4398 		{ F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" },
4399 		{ F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" },
4400 
4401 		/* T4+ */
4402 		{ F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" },
4403 		{ F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" },
4404 		{ F_MBHOSTPARERR, "CIM mailbox host read parity error" },
4405 		{ F_MBUPPARERR, "CIM mailbox uP parity error" },
4406 		{ F_IBQTP0PARERR, "CIM IBQ TP0 parity error" },
4407 		{ F_IBQTP1PARERR, "CIM IBQ TP1 parity error" },
4408 		{ F_IBQULPPARERR, "CIM IBQ ULP parity error" },
4409 		{ F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" },
4410 		{ F_IBQSGEHIPARERR | F_IBQPCIEPARERR,	/* same bit */
4411 			"CIM IBQ PCIe/SGE_HI parity error" },
4412 		{ F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" },
4413 		{ F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" },
4414 		{ F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" },
4415 		{ F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" },
4416 		{ F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" },
4417 		{ F_OBQSGEPARERR, "CIM OBQ SGE parity error" },
4418 		{ F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" },
4419 		{ F_TIMER1INT, "CIM TIMER0 interrupt" },
4420 		{ F_TIMER0INT, "CIM TIMER0 interrupt" },
4421 		{ F_PREFDROPINT, "CIM control register prefetch drop" },
4422 		{ 0}
4423 	};
4424 	static const struct intr_info cim_host_intr_info = {
4425 		.name = "CIM_HOST_INT_CAUSE",
4426 		.cause_reg = A_CIM_HOST_INT_CAUSE,
4427 		.enable_reg = A_CIM_HOST_INT_ENABLE,
4428 		.fatal = 0x007fffe6,
4429 		.flags = NONFATAL_IF_DISABLED,
4430 		.details = cim_host_intr_details,
4431 		.actions = cim_host_intr_actions,
4432 	};
4433 	static const struct intr_details cim_host_upacc_intr_details[] = {
4434 		{ F_EEPROMWRINT, "CIM EEPROM came out of busy state" },
4435 		{ F_TIMEOUTMAINT, "CIM PIF MA timeout" },
4436 		{ F_TIMEOUTINT, "CIM PIF timeout" },
4437 		{ F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" },
4438 		{ F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" },
4439 		{ F_BLKWRPLINT, "CIM block write to PL space" },
4440 		{ F_BLKRDPLINT, "CIM block read from PL space" },
4441 		{ F_SGLWRPLINT,
4442 			"CIM single write to PL space with illegal BEs" },
4443 		{ F_SGLRDPLINT,
4444 			"CIM single read from PL space with illegal BEs" },
4445 		{ F_BLKWRCTLINT, "CIM block write to CTL space" },
4446 		{ F_BLKRDCTLINT, "CIM block read from CTL space" },
4447 		{ F_SGLWRCTLINT,
4448 			"CIM single write to CTL space with illegal BEs" },
4449 		{ F_SGLRDCTLINT,
4450 			"CIM single read from CTL space with illegal BEs" },
4451 		{ F_BLKWREEPROMINT, "CIM block write to EEPROM space" },
4452 		{ F_BLKRDEEPROMINT, "CIM block read from EEPROM space" },
4453 		{ F_SGLWREEPROMINT,
4454 			"CIM single write to EEPROM space with illegal BEs" },
4455 		{ F_SGLRDEEPROMINT,
4456 			"CIM single read from EEPROM space with illegal BEs" },
4457 		{ F_BLKWRFLASHINT, "CIM block write to flash space" },
4458 		{ F_BLKRDFLASHINT, "CIM block read from flash space" },
4459 		{ F_SGLWRFLASHINT, "CIM single write to flash space" },
4460 		{ F_SGLRDFLASHINT,
4461 			"CIM single read from flash space with illegal BEs" },
4462 		{ F_BLKWRBOOTINT, "CIM block write to boot space" },
4463 		{ F_BLKRDBOOTINT, "CIM block read from boot space" },
4464 		{ F_SGLWRBOOTINT, "CIM single write to boot space" },
4465 		{ F_SGLRDBOOTINT,
4466 			"CIM single read from boot space with illegal BEs" },
4467 		{ F_ILLWRBEINT, "CIM illegal write BEs" },
4468 		{ F_ILLRDBEINT, "CIM illegal read BEs" },
4469 		{ F_ILLRDINT, "CIM illegal read" },
4470 		{ F_ILLWRINT, "CIM illegal write" },
4471 		{ F_ILLTRANSINT, "CIM illegal transaction" },
4472 		{ F_RSVDSPACEINT, "CIM reserved space access" },
4473 		{0}
4474 	};
4475 	static const struct intr_info cim_host_upacc_intr_info = {
4476 		.name = "CIM_HOST_UPACC_INT_CAUSE",
4477 		.cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
4478 		.enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
4479 		.fatal = 0x3fffeeff,
4480 		.flags = NONFATAL_IF_DISABLED,
4481 		.details = cim_host_upacc_intr_details,
4482 		.actions = NULL,
4483 	};
4484 	static const struct intr_info cim_pf_host_intr_info = {
4485 		.name = "CIM_PF_HOST_INT_CAUSE",
4486 		.cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4487 		.enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),
4488 		.fatal = 0,
4489 		.flags = 0,
4490 		.details = NULL,
4491 		.actions = NULL,
4492 	};
4493 	u32 val, fw_err;
4494 	bool fatal;
4495 
4496 	fw_err = t4_read_reg(adap, A_PCIE_FW);
4497 	if (fw_err & F_PCIE_FW_ERR)
4498 		t4_report_fw_error(adap);
4499 
4500 	/*
4501 	 * When the Firmware detects an internal error which normally wouldn't
4502 	 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
4503 	 * to make sure the Host sees the Firmware Crash.  So if we have a
4504 	 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
4505 	 * interrupt.
4506 	 */
4507 	val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE);
4508 	if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) ||
4509 	    G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) {
4510 		t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT);
4511 	}
4512 
4513 	fatal = false;
4514 	fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
4515 	fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
4516 	fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
4517 
4518 	return (fatal);
4519 }
4520 
4521 /*
4522  * ULP RX interrupt handler.
4523  */
4524 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
4525 {
4526 	static const struct intr_details ulprx_intr_details[] = {
4527 		/* T5+ */
4528 		{ F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
4529 		{ F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
4530 
4531 		/* T4+ */
4532 		{ F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
4533 		{ F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
4534 		{ 0x007fffff, "ULPRX parity error" },
4535 		{ 0 }
4536 	};
4537 	static const struct intr_info ulprx_intr_info = {
4538 		.name = "ULP_RX_INT_CAUSE",
4539 		.cause_reg = A_ULP_RX_INT_CAUSE,
4540 		.enable_reg = A_ULP_RX_INT_ENABLE,
4541 		.fatal = 0x07ffffff,
4542 		.flags = NONFATAL_IF_DISABLED,
4543 		.details = ulprx_intr_details,
4544 		.actions = NULL,
4545 	};
4546 	static const struct intr_info ulprx_intr2_info = {
4547 		.name = "ULP_RX_INT_CAUSE_2",
4548 		.cause_reg = A_ULP_RX_INT_CAUSE_2,
4549 		.enable_reg = A_ULP_RX_INT_ENABLE_2,
4550 		.fatal = 0,
4551 		.flags = 0,
4552 		.details = NULL,
4553 		.actions = NULL,
4554 	};
4555 	bool fatal = false;
4556 
4557 	fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
4558 	fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
4559 
4560 	return (fatal);
4561 }
4562 
4563 /*
4564  * ULP TX interrupt handler.
4565  */
4566 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
4567 {
4568 	static const struct intr_details ulptx_intr_details[] = {
4569 		{ F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
4570 		{ F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
4571 		{ F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
4572 		{ F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
4573 		{ 0x0fffffff, "ULPTX parity error" },
4574 		{ 0 }
4575 	};
4576 	static const struct intr_info ulptx_intr_info = {
4577 		.name = "ULP_TX_INT_CAUSE",
4578 		.cause_reg = A_ULP_TX_INT_CAUSE,
4579 		.enable_reg = A_ULP_TX_INT_ENABLE,
4580 		.fatal = 0x0fffffff,
4581 		.flags = NONFATAL_IF_DISABLED,
4582 		.details = ulptx_intr_details,
4583 		.actions = NULL,
4584 	};
4585 	static const struct intr_info ulptx_intr2_info = {
4586 		.name = "ULP_TX_INT_CAUSE_2",
4587 		.cause_reg = A_ULP_TX_INT_CAUSE_2,
4588 		.enable_reg = A_ULP_TX_INT_ENABLE_2,
4589 		.fatal = 0xf0,
4590 		.flags = NONFATAL_IF_DISABLED,
4591 		.details = NULL,
4592 		.actions = NULL,
4593 	};
4594 	bool fatal = false;
4595 
4596 	fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
4597 	fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose);
4598 
4599 	return (fatal);
4600 }
4601 
4602 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
4603 {
4604 	int i;
4605 	u32 data[17];
4606 
4607 	t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
4608 	    ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
4609 	for (i = 0; i < ARRAY_SIZE(data); i++) {
4610 		CH_ALERT(adap, "  - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
4611 		    A_PM_TX_DBG_STAT0 + i, data[i]);
4612 	}
4613 
4614 	return (false);
4615 }
4616 
4617 /*
4618  * PM TX interrupt handler.
4619  */
4620 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
4621 {
4622 	static const struct intr_action pmtx_intr_actions[] = {
4623 		{ 0xffffffff, 0, pmtx_dump_dbg_stats },
4624 		{ 0 },
4625 	};
4626 	static const struct intr_details pmtx_intr_details[] = {
4627 		{ F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
4628 		{ F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
4629 		{ F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
4630 		{ F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" },
4631 		{ 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
4632 		{ 0x00f00000, "PMTX icspi FIFO Rx framing error" },
4633 		{ 0x000f0000, "PMTX icspi FIFO Tx framing error" },
4634 		{ 0x0000f000, "PMTX oespi FIFO Rx framing error" },
4635 		{ 0x00000f00, "PMTX oespi FIFO Tx framing error" },
4636 		{ 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
4637 		{ F_OESPI_PAR_ERROR, "PMTX oespi parity error" },
4638 		{ F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" },
4639 		{ F_ICSPI_PAR_ERROR, "PMTX icspi parity error" },
4640 		{ F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
4641 		{ 0 }
4642 	};
4643 	static const struct intr_info pmtx_intr_info = {
4644 		.name = "PM_TX_INT_CAUSE",
4645 		.cause_reg = A_PM_TX_INT_CAUSE,
4646 		.enable_reg = A_PM_TX_INT_ENABLE,
4647 		.fatal = 0xffffffff,
4648 		.flags = 0,
4649 		.details = pmtx_intr_details,
4650 		.actions = pmtx_intr_actions,
4651 	};
4652 
4653 	return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose));
4654 }
4655 
4656 /*
4657  * PM RX interrupt handler.
4658  */
4659 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
4660 {
4661 	static const struct intr_details pmrx_intr_details[] = {
4662 		/* T6+ */
4663 		{ 0x18000000, "PMRX ospi overflow" },
4664 		{ F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
4665 		{ F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" },
4666 		{ F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" },
4667 		{ F_SDC_ERR, "PMRX SDC error" },
4668 
4669 		/* T4+ */
4670 		{ F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" },
4671 		{ 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
4672 		{ 0x0003c000, "PMRX iespi Rx framing error" },
4673 		{ 0x00003c00, "PMRX iespi Tx framing error" },
4674 		{ 0x00000300, "PMRX ocspi Rx framing error" },
4675 		{ 0x000000c0, "PMRX ocspi Tx framing error" },
4676 		{ 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
4677 		{ F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" },
4678 		{ F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" },
4679 		{ F_IESPI_PAR_ERROR, "PMRX iespi parity error" },
4680 		{ F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
4681 		{ 0 }
4682 	};
4683 	static const struct intr_info pmrx_intr_info = {
4684 		.name = "PM_RX_INT_CAUSE",
4685 		.cause_reg = A_PM_RX_INT_CAUSE,
4686 		.enable_reg = A_PM_RX_INT_ENABLE,
4687 		.fatal = 0x1fffffff,
4688 		.flags = NONFATAL_IF_DISABLED,
4689 		.details = pmrx_intr_details,
4690 		.actions = NULL,
4691 	};
4692 
4693 	return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose));
4694 }
4695 
4696 /*
4697  * CPL switch interrupt handler.
4698  */
4699 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
4700 {
4701 	static const struct intr_details cplsw_intr_details[] = {
4702 		/* T5+ */
4703 		{ F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
4704 		{ F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
4705 
4706 		/* T4+ */
4707 		{ F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" },
4708 		{ F_CIM_OVFL_ERROR, "CPLSW CIM overflow" },
4709 		{ F_TP_FRAMING_ERROR, "CPLSW TP framing error" },
4710 		{ F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" },
4711 		{ F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" },
4712 		{ F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
4713 		{ 0 }
4714 	};
4715 	static const struct intr_info cplsw_intr_info = {
4716 		.name = "CPL_INTR_CAUSE",
4717 		.cause_reg = A_CPL_INTR_CAUSE,
4718 		.enable_reg = A_CPL_INTR_ENABLE,
4719 		.fatal = 0xff,
4720 		.flags = NONFATAL_IF_DISABLED,
4721 		.details = cplsw_intr_details,
4722 		.actions = NULL,
4723 	};
4724 
4725 	return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose));
4726 }
4727 
4728 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
4729 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR)
4730 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \
4731     F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \
4732     F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \
4733     F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR)
4734 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
4735     F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
4736     F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
4737 
4738 /*
4739  * LE interrupt handler.
4740  */
4741 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
4742 {
4743 	static const struct intr_details le_intr_details[] = {
4744 		{ F_REQQPARERR, "LE request queue parity error" },
4745 		{ F_UNKNOWNCMD, "LE unknown command" },
4746 		{ F_ACTRGNFULL, "LE active region full" },
4747 		{ F_PARITYERR, "LE parity error" },
4748 		{ F_LIPMISS, "LE LIP miss" },
4749 		{ F_LIP0, "LE 0 LIP error" },
4750 		{ 0 }
4751 	};
4752 	static const struct intr_details t6_le_intr_details[] = {
4753 		{ F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" },
4754 		{ F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" },
4755 		{ F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" },
4756 		{ F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" },
4757 		{ F_TOTCNTERR, "LE total active < TCAM count" },
4758 		{ F_CMDPRSRINTERR, "LE internal error in parser" },
4759 		{ F_CMDTIDERR, "Incorrect tid in LE command" },
4760 		{ F_T6_ACTRGNFULL, "LE active region full" },
4761 		{ F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" },
4762 		{ F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" },
4763 		{ F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" },
4764 		{ F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" },
4765 		{ F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" },
4766 		{ F_TCAMACCFAIL, "LE TCAM access failure" },
4767 		{ F_T6_UNKNOWNCMD, "LE unknown command" },
4768 		{ F_T6_LIP0, "LE found 0 LIP during CLIP substitution" },
4769 		{ F_T6_LIPMISS, "LE CLIP lookup miss" },
4770 		{ T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
4771 		{ 0 }
4772 	};
4773 	struct intr_info le_intr_info = {
4774 		.name = "LE_DB_INT_CAUSE",
4775 		.cause_reg = A_LE_DB_INT_CAUSE,
4776 		.enable_reg = A_LE_DB_INT_ENABLE,
4777 		.fatal = 0,
4778 		.flags = NONFATAL_IF_DISABLED,
4779 		.details = NULL,
4780 		.actions = NULL,
4781 	};
4782 
4783 	if (chip_id(adap) <= CHELSIO_T5) {
4784 		le_intr_info.details = le_intr_details;
4785 		le_intr_info.fatal = T5_LE_FATAL_MASK;
4786 	} else {
4787 		le_intr_info.details = t6_le_intr_details;
4788 		le_intr_info.fatal = T6_LE_FATAL_MASK;
4789 	}
4790 
4791 	return (t4_handle_intr(adap, &le_intr_info, 0, verbose));
4792 }
4793 
4794 /*
4795  * MPS interrupt handler.
4796  */
4797 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
4798 {
4799 	static const struct intr_details mps_rx_perr_intr_details[] = {
4800 		{ 0xffffffff, "MPS Rx parity error" },
4801 		{ 0 }
4802 	};
4803 	static const struct intr_info mps_rx_perr_intr_info = {
4804 		.name = "MPS_RX_PERR_INT_CAUSE",
4805 		.cause_reg = A_MPS_RX_PERR_INT_CAUSE,
4806 		.enable_reg = A_MPS_RX_PERR_INT_ENABLE,
4807 		.fatal = 0xffffffff,
4808 		.flags = NONFATAL_IF_DISABLED,
4809 		.details = mps_rx_perr_intr_details,
4810 		.actions = NULL,
4811 	};
4812 	static const struct intr_details mps_tx_intr_details[] = {
4813 		{ F_PORTERR, "MPS Tx destination port is disabled" },
4814 		{ F_FRMERR, "MPS Tx framing error" },
4815 		{ F_SECNTERR, "MPS Tx SOP/EOP error" },
4816 		{ F_BUBBLE, "MPS Tx underflow" },
4817 		{ V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" },
4818 		{ V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" },
4819 		{ F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" },
4820 		{ V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" },
4821 		{ 0 }
4822 	};
4823 	static const struct intr_info mps_tx_intr_info = {
4824 		.name = "MPS_TX_INT_CAUSE",
4825 		.cause_reg = A_MPS_TX_INT_CAUSE,
4826 		.enable_reg = A_MPS_TX_INT_ENABLE,
4827 		.fatal = 0x1ffff,
4828 		.flags = NONFATAL_IF_DISABLED,
4829 		.details = mps_tx_intr_details,
4830 		.actions = NULL,
4831 	};
4832 	static const struct intr_details mps_trc_intr_details[] = {
4833 		{ F_MISCPERR, "MPS TRC misc parity error" },
4834 		{ V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
4835 		{ V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" },
4836 		{ 0 }
4837 	};
4838 	static const struct intr_info mps_trc_intr_info = {
4839 		.name = "MPS_TRC_INT_CAUSE",
4840 		.cause_reg = A_MPS_TRC_INT_CAUSE,
4841 		.enable_reg = A_MPS_TRC_INT_ENABLE,
4842 		.fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
4843 		.flags = 0,
4844 		.details = mps_trc_intr_details,
4845 		.actions = NULL,
4846 	};
4847 	static const struct intr_details mps_stat_sram_intr_details[] = {
4848 		{ 0xffffffff, "MPS statistics SRAM parity error" },
4849 		{ 0 }
4850 	};
4851 	static const struct intr_info mps_stat_sram_intr_info = {
4852 		.name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
4853 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4854 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
4855 		.fatal = 0x1fffffff,
4856 		.flags = NONFATAL_IF_DISABLED,
4857 		.details = mps_stat_sram_intr_details,
4858 		.actions = NULL,
4859 	};
4860 	static const struct intr_details mps_stat_tx_intr_details[] = {
4861 		{ 0xffffff, "MPS statistics Tx FIFO parity error" },
4862 		{ 0 }
4863 	};
4864 	static const struct intr_info mps_stat_tx_intr_info = {
4865 		.name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
4866 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4867 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,
4868 		.fatal =  0xffffff,
4869 		.flags = NONFATAL_IF_DISABLED,
4870 		.details = mps_stat_tx_intr_details,
4871 		.actions = NULL,
4872 	};
4873 	static const struct intr_details mps_stat_rx_intr_details[] = {
4874 		{ 0xffffff, "MPS statistics Rx FIFO parity error" },
4875 		{ 0 }
4876 	};
4877 	static const struct intr_info mps_stat_rx_intr_info = {
4878 		.name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
4879 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4880 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,
4881 		.fatal =  0xffffff,
4882 		.flags = 0,
4883 		.details = mps_stat_rx_intr_details,
4884 		.actions = NULL,
4885 	};
4886 	static const struct intr_details mps_cls_intr_details[] = {
4887 		{ F_HASHSRAM, "MPS hash SRAM parity error" },
4888 		{ F_MATCHTCAM, "MPS match TCAM parity error" },
4889 		{ F_MATCHSRAM, "MPS match SRAM parity error" },
4890 		{ 0 }
4891 	};
4892 	static const struct intr_info mps_cls_intr_info = {
4893 		.name = "MPS_CLS_INT_CAUSE",
4894 		.cause_reg = A_MPS_CLS_INT_CAUSE,
4895 		.enable_reg = A_MPS_CLS_INT_ENABLE,
4896 		.fatal =  F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM,
4897 		.flags = 0,
4898 		.details = mps_cls_intr_details,
4899 		.actions = NULL,
4900 	};
4901 	static const struct intr_details mps_stat_sram1_intr_details[] = {
4902 		{ 0xff, "MPS statistics SRAM1 parity error" },
4903 		{ 0 }
4904 	};
4905 	static const struct intr_info mps_stat_sram1_intr_info = {
4906 		.name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
4907 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
4908 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,
4909 		.fatal = 0xff,
4910 		.flags = 0,
4911 		.details = mps_stat_sram1_intr_details,
4912 		.actions = NULL,
4913 	};
4914 
4915 	bool fatal;
4916 
4917 	fatal = false;
4918 	fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
4919 	fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
4920 	fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
4921 	fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
4922 	fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
4923 	fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
4924 	fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose);
4925 	if (chip_id(adap) > CHELSIO_T4) {
4926 		fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0,
4927 		    verbose);
4928 	}
4929 
4930 	t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
4931 	t4_read_reg(adap, A_MPS_INT_CAUSE);	/* flush */
4932 
4933 	return (fatal);
4934 
4935 }
4936 
4937 /*
4938  * EDC/MC interrupt handler.
4939  */
4940 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
4941 {
4942 	static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
4943 	unsigned int count_reg, v;
4944 	static const struct intr_details mem_intr_details[] = {
4945 		{ F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" },
4946 		{ F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" },
4947 		{ F_PERR_INT_CAUSE, "FIFO parity error" },
4948 		{ 0 }
4949 	};
4950 	struct intr_info ii = {
4951 		.fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE,
4952 		.details = mem_intr_details,
4953 		.flags = 0,
4954 		.actions = NULL,
4955 	};
4956 	bool fatal;
4957 
4958 	switch (idx) {
4959 	case MEM_EDC0:
4960 		ii.name = "EDC0_INT_CAUSE";
4961 		ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0);
4962 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);
4963 		count_reg = EDC_REG(A_EDC_ECC_STATUS, 0);
4964 		break;
4965 	case MEM_EDC1:
4966 		ii.name = "EDC1_INT_CAUSE";
4967 		ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1);
4968 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);
4969 		count_reg = EDC_REG(A_EDC_ECC_STATUS, 1);
4970 		break;
4971 	case MEM_MC0:
4972 		ii.name = "MC0_INT_CAUSE";
4973 		if (is_t4(adap)) {
4974 			ii.cause_reg = A_MC_INT_CAUSE;
4975 			ii.enable_reg = A_MC_INT_ENABLE;
4976 			count_reg = A_MC_ECC_STATUS;
4977 		} else {
4978 			ii.cause_reg = A_MC_P_INT_CAUSE;
4979 			ii.enable_reg = A_MC_P_INT_ENABLE;
4980 			count_reg = A_MC_P_ECC_STATUS;
4981 		}
4982 		break;
4983 	case MEM_MC1:
4984 		ii.name = "MC1_INT_CAUSE";
4985 		ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1);
4986 		ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);
4987 		count_reg = MC_REG(A_MC_P_ECC_STATUS, 1);
4988 		break;
4989 	}
4990 
4991 	fatal = t4_handle_intr(adap, &ii, 0, verbose);
4992 
4993 	v = t4_read_reg(adap, count_reg);
4994 	if (v != 0) {
4995 		if (G_ECC_UECNT(v) != 0) {
4996 			CH_ALERT(adap,
4997 			    "%s: %u uncorrectable ECC data error(s)\n",
4998 			    name[idx], G_ECC_UECNT(v));
4999 		}
5000 		if (G_ECC_CECNT(v) != 0) {
5001 			if (idx <= MEM_EDC1)
5002 				t4_edc_err_read(adap, idx);
5003 			CH_WARN_RATELIMIT(adap,
5004 			    "%s: %u correctable ECC data error(s)\n",
5005 			    name[idx], G_ECC_CECNT(v));
5006 		}
5007 		t4_write_reg(adap, count_reg, 0xffffffff);
5008 	}
5009 
5010 	return (fatal);
5011 }
5012 
5013 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
5014 {
5015 	u32 v;
5016 
5017 	v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS);
5018 	CH_ALERT(adap,
5019 	    "MA address wrap-around error by client %u to address %#x\n",
5020 	    G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4);
5021 	t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v);
5022 
5023 	return (false);
5024 }
5025 
5026 
5027 /*
5028  * MA interrupt handler.
5029  */
5030 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
5031 {
5032 	static const struct intr_action ma_intr_actions[] = {
5033 		{ F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status },
5034 		{ 0 },
5035 	};
5036 	static const struct intr_info ma_intr_info = {
5037 		.name = "MA_INT_CAUSE",
5038 		.cause_reg = A_MA_INT_CAUSE,
5039 		.enable_reg = A_MA_INT_ENABLE,
5040 		.fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE,
5041 		.flags = NONFATAL_IF_DISABLED,
5042 		.details = NULL,
5043 		.actions = ma_intr_actions,
5044 	};
5045 	static const struct intr_info ma_perr_status1 = {
5046 		.name = "MA_PARITY_ERROR_STATUS1",
5047 		.cause_reg = A_MA_PARITY_ERROR_STATUS1,
5048 		.enable_reg = A_MA_PARITY_ERROR_ENABLE1,
5049 		.fatal = 0xffffffff,
5050 		.flags = 0,
5051 		.details = NULL,
5052 		.actions = NULL,
5053 	};
5054 	static const struct intr_info ma_perr_status2 = {
5055 		.name = "MA_PARITY_ERROR_STATUS2",
5056 		.cause_reg = A_MA_PARITY_ERROR_STATUS2,
5057 		.enable_reg = A_MA_PARITY_ERROR_ENABLE2,
5058 		.fatal = 0xffffffff,
5059 		.flags = 0,
5060 		.details = NULL,
5061 		.actions = NULL,
5062 	};
5063 	bool fatal;
5064 
5065 	fatal = false;
5066 	fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose);
5067 	fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose);
5068 	if (chip_id(adap) > CHELSIO_T4)
5069 		fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose);
5070 
5071 	return (fatal);
5072 }
5073 
5074 /*
5075  * SMB interrupt handler.
5076  */
5077 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
5078 {
5079 	static const struct intr_details smb_intr_details[] = {
5080 		{ F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" },
5081 		{ F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" },
5082 		{ F_SLVFIFOPARINT, "SMB slave FIFO parity error" },
5083 		{ 0 }
5084 	};
5085 	static const struct intr_info smb_intr_info = {
5086 		.name = "SMB_INT_CAUSE",
5087 		.cause_reg = A_SMB_INT_CAUSE,
5088 		.enable_reg = A_SMB_INT_ENABLE,
5089 		.fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT,
5090 		.flags = 0,
5091 		.details = smb_intr_details,
5092 		.actions = NULL,
5093 	};
5094 
5095 	return (t4_handle_intr(adap, &smb_intr_info, 0, verbose));
5096 }
5097 
5098 /*
5099  * NC-SI interrupt handler.
5100  */
5101 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
5102 {
5103 	static const struct intr_details ncsi_intr_details[] = {
5104 		{ F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" },
5105 		{ F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" },
5106 		{ F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" },
5107 		{ F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" },
5108 		{ 0 }
5109 	};
5110 	static const struct intr_info ncsi_intr_info = {
5111 		.name = "NCSI_INT_CAUSE",
5112 		.cause_reg = A_NCSI_INT_CAUSE,
5113 		.enable_reg = A_NCSI_INT_ENABLE,
5114 		.fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR |
5115 		    F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR,
5116 		.flags = 0,
5117 		.details = ncsi_intr_details,
5118 		.actions = NULL,
5119 	};
5120 
5121 	return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose));
5122 }
5123 
5124 /*
5125  * MAC interrupt handler.
5126  */
5127 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
5128 {
5129 	static const struct intr_details mac_intr_details[] = {
5130 		{ F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" },
5131 		{ F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" },
5132 		{ 0 }
5133 	};
5134 	char name[32];
5135 	struct intr_info ii;
5136 	bool fatal = false;
5137 
5138 	if (is_t4(adap)) {
5139 		snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
5140 		ii.name = &name[0];
5141 		ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
5142 		ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);
5143 		ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5144 		ii.flags = 0;
5145 		ii.details = mac_intr_details;
5146 		ii.actions = NULL;
5147 	} else {
5148 		snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
5149 		ii.name = &name[0];
5150 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
5151 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);
5152 		ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5153 		ii.flags = 0;
5154 		ii.details = mac_intr_details;
5155 		ii.actions = NULL;
5156 	}
5157 	fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5158 
5159 	if (chip_id(adap) >= CHELSIO_T5) {
5160 		snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
5161 		ii.name = &name[0];
5162 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
5163 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);
5164 		ii.fatal = 0;
5165 		ii.flags = 0;
5166 		ii.details = NULL;
5167 		ii.actions = NULL;
5168 		fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5169 	}
5170 
5171 	if (chip_id(adap) >= CHELSIO_T6) {
5172 		snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
5173 		ii.name = &name[0];
5174 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
5175 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);
5176 		ii.fatal = 0;
5177 		ii.flags = 0;
5178 		ii.details = NULL;
5179 		ii.actions = NULL;
5180 		fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5181 	}
5182 
5183 	return (fatal);
5184 }
5185 
5186 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
5187 {
5188 	static const struct intr_details plpl_intr_details[] = {
5189 		{ F_FATALPERR, "Fatal parity error" },
5190 		{ F_PERRVFID, "VFID_MAP parity error" },
5191 		{ 0 }
5192 	};
5193 	static const struct intr_info plpl_intr_info = {
5194 		.name = "PL_PL_INT_CAUSE",
5195 		.cause_reg = A_PL_PL_INT_CAUSE,
5196 		.enable_reg = A_PL_PL_INT_ENABLE,
5197 		.fatal = F_FATALPERR | F_PERRVFID,
5198 		.flags = NONFATAL_IF_DISABLED,
5199 		.details = plpl_intr_details,
5200 		.actions = NULL,
5201 	};
5202 
5203 	return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose));
5204 }
5205 
5206 /**
5207  *	t4_slow_intr_handler - control path interrupt handler
5208  *	@adap: the adapter
5209  *	@verbose: increased verbosity, for debug
5210  *
5211  *	T4 interrupt handler for non-data global interrupt events, e.g., errors.
5212  *	The designation 'slow' is because it involves register reads, while
5213  *	data interrupts typically don't involve any MMIOs.
5214  */
5215 int t4_slow_intr_handler(struct adapter *adap, bool verbose)
5216 {
5217 	static const struct intr_details pl_intr_details[] = {
5218 		{ F_MC1, "MC1" },
5219 		{ F_UART, "UART" },
5220 		{ F_ULP_TX, "ULP TX" },
5221 		{ F_SGE, "SGE" },
5222 		{ F_HMA, "HMA" },
5223 		{ F_CPL_SWITCH, "CPL Switch" },
5224 		{ F_ULP_RX, "ULP RX" },
5225 		{ F_PM_RX, "PM RX" },
5226 		{ F_PM_TX, "PM TX" },
5227 		{ F_MA, "MA" },
5228 		{ F_TP, "TP" },
5229 		{ F_LE, "LE" },
5230 		{ F_EDC1, "EDC1" },
5231 		{ F_EDC0, "EDC0" },
5232 		{ F_MC, "MC0" },
5233 		{ F_PCIE, "PCIE" },
5234 		{ F_PMU, "PMU" },
5235 		{ F_MAC3, "MAC3" },
5236 		{ F_MAC2, "MAC2" },
5237 		{ F_MAC1, "MAC1" },
5238 		{ F_MAC0, "MAC0" },
5239 		{ F_SMB, "SMB" },
5240 		{ F_SF, "SF" },
5241 		{ F_PL, "PL" },
5242 		{ F_NCSI, "NC-SI" },
5243 		{ F_MPS, "MPS" },
5244 		{ F_MI, "MI" },
5245 		{ F_DBG, "DBG" },
5246 		{ F_I2CM, "I2CM" },
5247 		{ F_CIM, "CIM" },
5248 		{ 0 }
5249 	};
5250 	static const struct intr_info pl_perr_cause = {
5251 		.name = "PL_PERR_CAUSE",
5252 		.cause_reg = A_PL_PERR_CAUSE,
5253 		.enable_reg = A_PL_PERR_ENABLE,
5254 		.fatal = 0xffffffff,
5255 		.flags = 0,
5256 		.details = pl_intr_details,
5257 		.actions = NULL,
5258 	};
5259 	static const struct intr_action pl_intr_action[] = {
5260 		{ F_MC1, MEM_MC1, mem_intr_handler },
5261 		{ F_ULP_TX, -1, ulptx_intr_handler },
5262 		{ F_SGE, -1, sge_intr_handler },
5263 		{ F_CPL_SWITCH, -1, cplsw_intr_handler },
5264 		{ F_ULP_RX, -1, ulprx_intr_handler },
5265 		{ F_PM_RX, -1, pmrx_intr_handler},
5266 		{ F_PM_TX, -1, pmtx_intr_handler},
5267 		{ F_MA, -1, ma_intr_handler },
5268 		{ F_TP, -1, tp_intr_handler },
5269 		{ F_LE, -1, le_intr_handler },
5270 		{ F_EDC1, MEM_EDC1, mem_intr_handler },
5271 		{ F_EDC0, MEM_EDC0, mem_intr_handler },
5272 		{ F_MC0, MEM_MC0, mem_intr_handler },
5273 		{ F_PCIE, -1, pcie_intr_handler },
5274 		{ F_MAC3, 3, mac_intr_handler},
5275 		{ F_MAC2, 2, mac_intr_handler},
5276 		{ F_MAC1, 1, mac_intr_handler},
5277 		{ F_MAC0, 0, mac_intr_handler},
5278 		{ F_SMB, -1, smb_intr_handler},
5279 		{ F_PL, -1, plpl_intr_handler },
5280 		{ F_NCSI, -1, ncsi_intr_handler},
5281 		{ F_MPS, -1, mps_intr_handler },
5282 		{ F_CIM, -1, cim_intr_handler },
5283 		{ 0 }
5284 	};
5285 	static const struct intr_info pl_intr_info = {
5286 		.name = "PL_INT_CAUSE",
5287 		.cause_reg = A_PL_INT_CAUSE,
5288 		.enable_reg = A_PL_INT_ENABLE,
5289 		.fatal = 0,
5290 		.flags = 0,
5291 		.details = pl_intr_details,
5292 		.actions = pl_intr_action,
5293 	};
5294 	bool fatal;
5295 	u32 perr;
5296 
5297 	perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
5298 	if (verbose || perr != 0) {
5299 		t4_show_intr_info(adap, &pl_perr_cause, perr);
5300 		if (perr != 0)
5301 			t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
5302 		if (verbose)
5303 			perr |= t4_read_reg(adap, pl_intr_info.enable_reg);
5304 	}
5305 	fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose);
5306 	if (fatal)
5307 		t4_fatal_err(adap, false);
5308 
5309 	return (0);
5310 }
5311 
5312 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
5313 
5314 /**
5315  *	t4_intr_enable - enable interrupts
5316  *	@adapter: the adapter whose interrupts should be enabled
5317  *
5318  *	Enable PF-specific interrupts for the calling function and the top-level
5319  *	interrupt concentrator for global interrupts.  Interrupts are already
5320  *	enabled at each module,	here we just enable the roots of the interrupt
5321  *	hierarchies.
5322  *
5323  *	Note: this function should be called only when the driver manages
5324  *	non PF-specific interrupts from the various HW modules.  Only one PCI
5325  *	function at a time should be doing this.
5326  */
5327 void t4_intr_enable(struct adapter *adap)
5328 {
5329 	u32 val = 0;
5330 
5331 	if (chip_id(adap) <= CHELSIO_T5)
5332 		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
5333 	else
5334 		val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
5335 	val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
5336 	    F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
5337 	    F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
5338 	    F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5339 	    F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT |
5340 	    F_EGRESS_SIZE_ERR;
5341 	t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val);
5342 	t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
5343 	t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
5344 	t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
5345 }
5346 
5347 /**
5348  *	t4_intr_disable - disable interrupts
5349  *	@adap: the adapter whose interrupts should be disabled
5350  *
5351  *	Disable interrupts.  We only disable the top-level interrupt
5352  *	concentrators.  The caller must be a PCI function managing global
5353  *	interrupts.
5354  */
5355 void t4_intr_disable(struct adapter *adap)
5356 {
5357 
5358 	t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
5359 	t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
5360 }
5361 
5362 /**
5363  *	t4_intr_clear - clear all interrupts
5364  *	@adap: the adapter whose interrupts should be cleared
5365  *
5366  *	Clears all interrupts.  The caller must be a PCI function managing
5367  *	global interrupts.
5368  */
5369 void t4_intr_clear(struct adapter *adap)
5370 {
5371 	static const u32 cause_reg[] = {
5372 		A_CIM_HOST_INT_CAUSE,
5373 		A_CIM_HOST_UPACC_INT_CAUSE,
5374 		MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
5375 		A_CPL_INTR_CAUSE,
5376 		EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1),
5377 		A_LE_DB_INT_CAUSE,
5378 		A_MA_INT_WRAP_STATUS,
5379 		A_MA_PARITY_ERROR_STATUS1,
5380 		A_MA_INT_CAUSE,
5381 		A_MPS_CLS_INT_CAUSE,
5382 		A_MPS_RX_PERR_INT_CAUSE,
5383 		A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
5384 		A_MPS_STAT_PERR_INT_CAUSE_SRAM,
5385 		A_MPS_TRC_INT_CAUSE,
5386 		A_MPS_TX_INT_CAUSE,
5387 		A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
5388 		A_NCSI_INT_CAUSE,
5389 		A_PCIE_INT_CAUSE,
5390 		A_PCIE_NONFAT_ERR,
5391 		A_PL_PL_INT_CAUSE,
5392 		A_PM_RX_INT_CAUSE,
5393 		A_PM_TX_INT_CAUSE,
5394 		A_SGE_INT_CAUSE1,
5395 		A_SGE_INT_CAUSE2,
5396 		A_SGE_INT_CAUSE3,
5397 		A_SGE_INT_CAUSE4,
5398 		A_SMB_INT_CAUSE,
5399 		A_TP_INT_CAUSE,
5400 		A_ULP_RX_INT_CAUSE,
5401 		A_ULP_RX_INT_CAUSE_2,
5402 		A_ULP_TX_INT_CAUSE,
5403 		A_ULP_TX_INT_CAUSE_2,
5404 
5405 		MYPF_REG(A_PL_PF_INT_CAUSE),
5406 	};
5407 	int i;
5408 	const int nchan = adap->chip_params->nchan;
5409 
5410 	for (i = 0; i < ARRAY_SIZE(cause_reg); i++)
5411 		t4_write_reg(adap, cause_reg[i], 0xffffffff);
5412 
5413 	if (is_t4(adap)) {
5414 		t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
5415 		    0xffffffff);
5416 		t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
5417 		    0xffffffff);
5418 		t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff);
5419 		for (i = 0; i < nchan; i++) {
5420 			t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE),
5421 			    0xffffffff);
5422 		}
5423 	}
5424 	if (chip_id(adap) >= CHELSIO_T5) {
5425 		t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
5426 		t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff);
5427 		t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff);
5428 		t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff);
5429 		if (is_t5(adap)) {
5430 			t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1),
5431 			    0xffffffff);
5432 		}
5433 		for (i = 0; i < nchan; i++) {
5434 			t4_write_reg(adap, T5_PORT_REG(i,
5435 			    A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff);
5436 			if (chip_id(adap) > CHELSIO_T5) {
5437 				t4_write_reg(adap, T5_PORT_REG(i,
5438 				    A_MAC_PORT_PERR_INT_CAUSE_100G),
5439 				    0xffffffff);
5440 			}
5441 			t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE),
5442 			    0xffffffff);
5443 		}
5444 	}
5445 	if (chip_id(adap) >= CHELSIO_T6) {
5446 		t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff);
5447 	}
5448 
5449 	t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
5450 	t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff);
5451 	t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff);
5452 	(void) t4_read_reg(adap, A_PL_INT_CAUSE);          /* flush */
5453 }
5454 
5455 /**
5456  *	hash_mac_addr - return the hash value of a MAC address
5457  *	@addr: the 48-bit Ethernet MAC address
5458  *
5459  *	Hashes a MAC address according to the hash function used by HW inexact
5460  *	(hash) address matching.
5461  */
5462 static int hash_mac_addr(const u8 *addr)
5463 {
5464 	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
5465 	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
5466 	a ^= b;
5467 	a ^= (a >> 12);
5468 	a ^= (a >> 6);
5469 	return a & 0x3f;
5470 }
5471 
5472 /**
5473  *	t4_config_rss_range - configure a portion of the RSS mapping table
5474  *	@adapter: the adapter
5475  *	@mbox: mbox to use for the FW command
5476  *	@viid: virtual interface whose RSS subtable is to be written
5477  *	@start: start entry in the table to write
5478  *	@n: how many table entries to write
5479  *	@rspq: values for the "response queue" (Ingress Queue) lookup table
5480  *	@nrspq: number of values in @rspq
5481  *
5482  *	Programs the selected part of the VI's RSS mapping table with the
5483  *	provided values.  If @nrspq < @n the supplied values are used repeatedly
5484  *	until the full table range is populated.
5485  *
5486  *	The caller must ensure the values in @rspq are in the range allowed for
5487  *	@viid.
5488  */
5489 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5490 			int start, int n, const u16 *rspq, unsigned int nrspq)
5491 {
5492 	int ret;
5493 	const u16 *rsp = rspq;
5494 	const u16 *rsp_end = rspq + nrspq;
5495 	struct fw_rss_ind_tbl_cmd cmd;
5496 
5497 	memset(&cmd, 0, sizeof(cmd));
5498 	cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
5499 				     F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5500 				     V_FW_RSS_IND_TBL_CMD_VIID(viid));
5501 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5502 
5503 	/*
5504 	 * Each firmware RSS command can accommodate up to 32 RSS Ingress
5505 	 * Queue Identifiers.  These Ingress Queue IDs are packed three to
5506 	 * a 32-bit word as 10-bit values with the upper remaining 2 bits
5507 	 * reserved.
5508 	 */
5509 	while (n > 0) {
5510 		int nq = min(n, 32);
5511 		int nq_packed = 0;
5512 		__be32 *qp = &cmd.iq0_to_iq2;
5513 
5514 		/*
5515 		 * Set up the firmware RSS command header to send the next
5516 		 * "nq" Ingress Queue IDs to the firmware.
5517 		 */
5518 		cmd.niqid = cpu_to_be16(nq);
5519 		cmd.startidx = cpu_to_be16(start);
5520 
5521 		/*
5522 		 * "nq" more done for the start of the next loop.
5523 		 */
5524 		start += nq;
5525 		n -= nq;
5526 
5527 		/*
5528 		 * While there are still Ingress Queue IDs to stuff into the
5529 		 * current firmware RSS command, retrieve them from the
5530 		 * Ingress Queue ID array and insert them into the command.
5531 		 */
5532 		while (nq > 0) {
5533 			/*
5534 			 * Grab up to the next 3 Ingress Queue IDs (wrapping
5535 			 * around the Ingress Queue ID array if necessary) and
5536 			 * insert them into the firmware RSS command at the
5537 			 * current 3-tuple position within the commad.
5538 			 */
5539 			u16 qbuf[3];
5540 			u16 *qbp = qbuf;
5541 			int nqbuf = min(3, nq);
5542 
5543 			nq -= nqbuf;
5544 			qbuf[0] = qbuf[1] = qbuf[2] = 0;
5545 			while (nqbuf && nq_packed < 32) {
5546 				nqbuf--;
5547 				nq_packed++;
5548 				*qbp++ = *rsp++;
5549 				if (rsp >= rsp_end)
5550 					rsp = rspq;
5551 			}
5552 			*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
5553 					    V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
5554 					    V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
5555 		}
5556 
5557 		/*
5558 		 * Send this portion of the RRS table update to the firmware;
5559 		 * bail out on any errors.
5560 		 */
5561 		ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5562 		if (ret)
5563 			return ret;
5564 	}
5565 	return 0;
5566 }
5567 
5568 /**
5569  *	t4_config_glbl_rss - configure the global RSS mode
5570  *	@adapter: the adapter
5571  *	@mbox: mbox to use for the FW command
5572  *	@mode: global RSS mode
5573  *	@flags: mode-specific flags
5574  *
5575  *	Sets the global RSS mode.
5576  */
5577 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5578 		       unsigned int flags)
5579 {
5580 	struct fw_rss_glb_config_cmd c;
5581 
5582 	memset(&c, 0, sizeof(c));
5583 	c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
5584 				    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5585 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5586 	if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5587 		c.u.manual.mode_pkd =
5588 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5589 	} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5590 		c.u.basicvirtual.mode_keymode =
5591 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5592 		c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5593 	} else
5594 		return -EINVAL;
5595 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5596 }
5597 
5598 /**
5599  *	t4_config_vi_rss - configure per VI RSS settings
5600  *	@adapter: the adapter
5601  *	@mbox: mbox to use for the FW command
5602  *	@viid: the VI id
5603  *	@flags: RSS flags
5604  *	@defq: id of the default RSS queue for the VI.
5605  *	@skeyidx: RSS secret key table index for non-global mode
5606  *	@skey: RSS vf_scramble key for VI.
5607  *
5608  *	Configures VI-specific RSS properties.
5609  */
5610 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5611 		     unsigned int flags, unsigned int defq, unsigned int skeyidx,
5612 		     unsigned int skey)
5613 {
5614 	struct fw_rss_vi_config_cmd c;
5615 
5616 	memset(&c, 0, sizeof(c));
5617 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5618 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5619 				   V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
5620 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5621 	c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5622 					V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
5623 	c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
5624 					V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
5625 	c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
5626 
5627 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5628 }
5629 
5630 /* Read an RSS table row */
5631 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5632 {
5633 	t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
5634 	return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
5635 				   5, 0, val);
5636 }
5637 
5638 /**
5639  *	t4_read_rss - read the contents of the RSS mapping table
5640  *	@adapter: the adapter
5641  *	@map: holds the contents of the RSS mapping table
5642  *
5643  *	Reads the contents of the RSS hash->queue mapping table.
5644  */
5645 int t4_read_rss(struct adapter *adapter, u16 *map)
5646 {
5647 	u32 val;
5648 	int i, ret;
5649 
5650 	for (i = 0; i < RSS_NENTRIES / 2; ++i) {
5651 		ret = rd_rss_row(adapter, i, &val);
5652 		if (ret)
5653 			return ret;
5654 		*map++ = G_LKPTBLQUEUE0(val);
5655 		*map++ = G_LKPTBLQUEUE1(val);
5656 	}
5657 	return 0;
5658 }
5659 
5660 /**
5661  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5662  * @adap: the adapter
5663  * @cmd: TP fw ldst address space type
5664  * @vals: where the indirect register values are stored/written
5665  * @nregs: how many indirect registers to read/write
5666  * @start_idx: index of first indirect register to read/write
5667  * @rw: Read (1) or Write (0)
5668  * @sleep_ok: if true we may sleep while awaiting command completion
5669  *
5670  * Access TP indirect registers through LDST
5671  **/
5672 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5673 			    unsigned int nregs, unsigned int start_index,
5674 			    unsigned int rw, bool sleep_ok)
5675 {
5676 	int ret = 0;
5677 	unsigned int i;
5678 	struct fw_ldst_cmd c;
5679 
5680 	for (i = 0; i < nregs; i++) {
5681 		memset(&c, 0, sizeof(c));
5682 		c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5683 						F_FW_CMD_REQUEST |
5684 						(rw ? F_FW_CMD_READ :
5685 						      F_FW_CMD_WRITE) |
5686 						V_FW_LDST_CMD_ADDRSPACE(cmd));
5687 		c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5688 
5689 		c.u.addrval.addr = cpu_to_be32(start_index + i);
5690 		c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5691 		ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5692 				      sleep_ok);
5693 		if (ret)
5694 			return ret;
5695 
5696 		if (rw)
5697 			vals[i] = be32_to_cpu(c.u.addrval.val);
5698 	}
5699 	return 0;
5700 }
5701 
5702 /**
5703  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5704  * @adap: the adapter
5705  * @reg_addr: Address Register
5706  * @reg_data: Data register
5707  * @buff: where the indirect register values are stored/written
5708  * @nregs: how many indirect registers to read/write
5709  * @start_index: index of first indirect register to read/write
5710  * @rw: READ(1) or WRITE(0)
5711  * @sleep_ok: if true we may sleep while awaiting command completion
5712  *
5713  * Read/Write TP indirect registers through LDST if possible.
5714  * Else, use backdoor access
5715  **/
5716 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5717 			      u32 *buff, u32 nregs, u32 start_index, int rw,
5718 			      bool sleep_ok)
5719 {
5720 	int rc = -EINVAL;
5721 	int cmd;
5722 
5723 	switch (reg_addr) {
5724 	case A_TP_PIO_ADDR:
5725 		cmd = FW_LDST_ADDRSPC_TP_PIO;
5726 		break;
5727 	case A_TP_TM_PIO_ADDR:
5728 		cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5729 		break;
5730 	case A_TP_MIB_INDEX:
5731 		cmd = FW_LDST_ADDRSPC_TP_MIB;
5732 		break;
5733 	default:
5734 		goto indirect_access;
5735 	}
5736 
5737 	if (t4_use_ldst(adap))
5738 		rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5739 				      sleep_ok);
5740 
5741 indirect_access:
5742 
5743 	if (rc) {
5744 		if (rw)
5745 			t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5746 					 start_index);
5747 		else
5748 			t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5749 					  start_index);
5750 	}
5751 }
5752 
5753 /**
5754  * t4_tp_pio_read - Read TP PIO registers
5755  * @adap: the adapter
5756  * @buff: where the indirect register values are written
5757  * @nregs: how many indirect registers to read
5758  * @start_index: index of first indirect register to read
5759  * @sleep_ok: if true we may sleep while awaiting command completion
5760  *
5761  * Read TP PIO Registers
5762  **/
5763 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5764 		    u32 start_index, bool sleep_ok)
5765 {
5766 	t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
5767 			  start_index, 1, sleep_ok);
5768 }
5769 
5770 /**
5771  * t4_tp_pio_write - Write TP PIO registers
5772  * @adap: the adapter
5773  * @buff: where the indirect register values are stored
5774  * @nregs: how many indirect registers to write
5775  * @start_index: index of first indirect register to write
5776  * @sleep_ok: if true we may sleep while awaiting command completion
5777  *
5778  * Write TP PIO Registers
5779  **/
5780 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
5781 		     u32 start_index, bool sleep_ok)
5782 {
5783 	t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5784 	    __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
5785 }
5786 
5787 /**
5788  * t4_tp_tm_pio_read - Read TP TM PIO registers
5789  * @adap: the adapter
5790  * @buff: where the indirect register values are written
5791  * @nregs: how many indirect registers to read
5792  * @start_index: index of first indirect register to read
5793  * @sleep_ok: if true we may sleep while awaiting command completion
5794  *
5795  * Read TP TM PIO Registers
5796  **/
5797 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5798 		       u32 start_index, bool sleep_ok)
5799 {
5800 	t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
5801 			  nregs, start_index, 1, sleep_ok);
5802 }
5803 
5804 /**
5805  * t4_tp_mib_read - Read TP MIB registers
5806  * @adap: the adapter
5807  * @buff: where the indirect register values are written
5808  * @nregs: how many indirect registers to read
5809  * @start_index: index of first indirect register to read
5810  * @sleep_ok: if true we may sleep while awaiting command completion
5811  *
5812  * Read TP MIB Registers
5813  **/
5814 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5815 		    bool sleep_ok)
5816 {
5817 	t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
5818 			  start_index, 1, sleep_ok);
5819 }
5820 
5821 /**
5822  *	t4_read_rss_key - read the global RSS key
5823  *	@adap: the adapter
5824  *	@key: 10-entry array holding the 320-bit RSS key
5825  * 	@sleep_ok: if true we may sleep while awaiting command completion
5826  *
5827  *	Reads the global 320-bit RSS key.
5828  */
5829 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5830 {
5831 	t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5832 }
5833 
5834 /**
5835  *	t4_write_rss_key - program one of the RSS keys
5836  *	@adap: the adapter
5837  *	@key: 10-entry array holding the 320-bit RSS key
5838  *	@idx: which RSS key to write
5839  * 	@sleep_ok: if true we may sleep while awaiting command completion
5840  *
5841  *	Writes one of the RSS keys with the given 320-bit value.  If @idx is
5842  *	0..15 the corresponding entry in the RSS key table is written,
5843  *	otherwise the global RSS key is written.
5844  */
5845 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5846 		      bool sleep_ok)
5847 {
5848 	u8 rss_key_addr_cnt = 16;
5849 	u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
5850 
5851 	/*
5852 	 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5853 	 * allows access to key addresses 16-63 by using KeyWrAddrX
5854 	 * as index[5:4](upper 2) into key table
5855 	 */
5856 	if ((chip_id(adap) > CHELSIO_T5) &&
5857 	    (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
5858 		rss_key_addr_cnt = 32;
5859 
5860 	t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5861 
5862 	if (idx >= 0 && idx < rss_key_addr_cnt) {
5863 		if (rss_key_addr_cnt > 16)
5864 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5865 				     vrt | V_KEYWRADDRX(idx >> 4) |
5866 				     V_T6_VFWRADDR(idx) | F_KEYWREN);
5867 		else
5868 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5869 				     vrt| V_KEYWRADDR(idx) | F_KEYWREN);
5870 	}
5871 }
5872 
5873 /**
5874  *	t4_read_rss_pf_config - read PF RSS Configuration Table
5875  *	@adapter: the adapter
5876  *	@index: the entry in the PF RSS table to read
5877  *	@valp: where to store the returned value
5878  * 	@sleep_ok: if true we may sleep while awaiting command completion
5879  *
5880  *	Reads the PF RSS Configuration Table at the specified index and returns
5881  *	the value found there.
5882  */
5883 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5884 			   u32 *valp, bool sleep_ok)
5885 {
5886 	t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
5887 }
5888 
5889 /**
5890  *	t4_write_rss_pf_config - write PF RSS Configuration Table
5891  *	@adapter: the adapter
5892  *	@index: the entry in the VF RSS table to read
5893  *	@val: the value to store
5894  * 	@sleep_ok: if true we may sleep while awaiting command completion
5895  *
5896  *	Writes the PF RSS Configuration Table at the specified index with the
5897  *	specified value.
5898  */
5899 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
5900 			    u32 val, bool sleep_ok)
5901 {
5902 	t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
5903 			sleep_ok);
5904 }
5905 
5906 /**
5907  *	t4_read_rss_vf_config - read VF RSS Configuration Table
5908  *	@adapter: the adapter
5909  *	@index: the entry in the VF RSS table to read
5910  *	@vfl: where to store the returned VFL
5911  *	@vfh: where to store the returned VFH
5912  * 	@sleep_ok: if true we may sleep while awaiting command completion
5913  *
5914  *	Reads the VF RSS Configuration Table at the specified index and returns
5915  *	the (VFL, VFH) values found there.
5916  */
5917 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5918 			   u32 *vfl, u32 *vfh, bool sleep_ok)
5919 {
5920 	u32 vrt, mask, data;
5921 
5922 	if (chip_id(adapter) <= CHELSIO_T5) {
5923 		mask = V_VFWRADDR(M_VFWRADDR);
5924 		data = V_VFWRADDR(index);
5925 	} else {
5926 		 mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5927 		 data = V_T6_VFWRADDR(index);
5928 	}
5929 	/*
5930 	 * Request that the index'th VF Table values be read into VFL/VFH.
5931 	 */
5932 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5933 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5934 	vrt |= data | F_VFRDEN;
5935 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5936 
5937 	/*
5938 	 * Grab the VFL/VFH values ...
5939 	 */
5940 	t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5941 	t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5942 }
5943 
5944 /**
5945  *	t4_write_rss_vf_config - write VF RSS Configuration Table
5946  *
5947  *	@adapter: the adapter
5948  *	@index: the entry in the VF RSS table to write
5949  *	@vfl: the VFL to store
5950  *	@vfh: the VFH to store
5951  *
5952  *	Writes the VF RSS Configuration Table at the specified index with the
5953  *	specified (VFL, VFH) values.
5954  */
5955 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
5956 			    u32 vfl, u32 vfh, bool sleep_ok)
5957 {
5958 	u32 vrt, mask, data;
5959 
5960 	if (chip_id(adapter) <= CHELSIO_T5) {
5961 		mask = V_VFWRADDR(M_VFWRADDR);
5962 		data = V_VFWRADDR(index);
5963 	} else {
5964 		mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5965 		data = V_T6_VFWRADDR(index);
5966 	}
5967 
5968 	/*
5969 	 * Load up VFL/VFH with the values to be written ...
5970 	 */
5971 	t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5972 	t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5973 
5974 	/*
5975 	 * Write the VFL/VFH into the VF Table at index'th location.
5976 	 */
5977 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5978 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5979 	vrt |= data | F_VFRDEN;
5980 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5981 }
5982 
5983 /**
5984  *	t4_read_rss_pf_map - read PF RSS Map
5985  *	@adapter: the adapter
5986  * 	@sleep_ok: if true we may sleep while awaiting command completion
5987  *
5988  *	Reads the PF RSS Map register and returns its value.
5989  */
5990 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5991 {
5992 	u32 pfmap;
5993 
5994 	t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
5995 
5996 	return pfmap;
5997 }
5998 
5999 /**
6000  *	t4_write_rss_pf_map - write PF RSS Map
6001  *	@adapter: the adapter
6002  *	@pfmap: PF RSS Map value
6003  *
6004  *	Writes the specified value to the PF RSS Map register.
6005  */
6006 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
6007 {
6008 	t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6009 }
6010 
6011 /**
6012  *	t4_read_rss_pf_mask - read PF RSS Mask
6013  *	@adapter: the adapter
6014  * 	@sleep_ok: if true we may sleep while awaiting command completion
6015  *
6016  *	Reads the PF RSS Mask register and returns its value.
6017  */
6018 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
6019 {
6020 	u32 pfmask;
6021 
6022 	t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6023 
6024 	return pfmask;
6025 }
6026 
6027 /**
6028  *	t4_write_rss_pf_mask - write PF RSS Mask
6029  *	@adapter: the adapter
6030  *	@pfmask: PF RSS Mask value
6031  *
6032  *	Writes the specified value to the PF RSS Mask register.
6033  */
6034 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
6035 {
6036 	t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6037 }
6038 
6039 /**
6040  *	t4_tp_get_tcp_stats - read TP's TCP MIB counters
6041  *	@adap: the adapter
6042  *	@v4: holds the TCP/IP counter values
6043  *	@v6: holds the TCP/IPv6 counter values
6044  * 	@sleep_ok: if true we may sleep while awaiting command completion
6045  *
6046  *	Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
6047  *	Either @v4 or @v6 may be %NULL to skip the corresponding stats.
6048  */
6049 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
6050 			 struct tp_tcp_stats *v6, bool sleep_ok)
6051 {
6052 	u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
6053 
6054 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
6055 #define STAT(x)     val[STAT_IDX(x)]
6056 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
6057 
6058 	if (v4) {
6059 		t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6060 			       A_TP_MIB_TCP_OUT_RST, sleep_ok);
6061 		v4->tcp_out_rsts = STAT(OUT_RST);
6062 		v4->tcp_in_segs  = STAT64(IN_SEG);
6063 		v4->tcp_out_segs = STAT64(OUT_SEG);
6064 		v4->tcp_retrans_segs = STAT64(RXT_SEG);
6065 	}
6066 	if (v6) {
6067 		t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6068 			       A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
6069 		v6->tcp_out_rsts = STAT(OUT_RST);
6070 		v6->tcp_in_segs  = STAT64(IN_SEG);
6071 		v6->tcp_out_segs = STAT64(OUT_SEG);
6072 		v6->tcp_retrans_segs = STAT64(RXT_SEG);
6073 	}
6074 #undef STAT64
6075 #undef STAT
6076 #undef STAT_IDX
6077 }
6078 
6079 /**
6080  *	t4_tp_get_err_stats - read TP's error MIB counters
6081  *	@adap: the adapter
6082  *	@st: holds the counter values
6083  * 	@sleep_ok: if true we may sleep while awaiting command completion
6084  *
6085  *	Returns the values of TP's error counters.
6086  */
6087 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
6088 			 bool sleep_ok)
6089 {
6090 	int nchan = adap->chip_params->nchan;
6091 
6092 	t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
6093 		       sleep_ok);
6094 
6095 	t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
6096 		       sleep_ok);
6097 
6098 	t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
6099 		       sleep_ok);
6100 
6101 	t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
6102 		       A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
6103 
6104 	t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
6105 		       A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
6106 
6107 	t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
6108 		       sleep_ok);
6109 
6110 	t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
6111 		       A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
6112 
6113 	t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
6114 		       A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
6115 
6116 	t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
6117 		       sleep_ok);
6118 }
6119 
6120 /**
6121  *	t4_tp_get_proxy_stats - read TP's proxy MIB counters
6122  *	@adap: the adapter
6123  *	@st: holds the counter values
6124  *
6125  *	Returns the values of TP's proxy counters.
6126  */
6127 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
6128     bool sleep_ok)
6129 {
6130 	int nchan = adap->chip_params->nchan;
6131 
6132 	t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
6133 }
6134 
6135 /**
6136  *	t4_tp_get_cpl_stats - read TP's CPL MIB counters
6137  *	@adap: the adapter
6138  *	@st: holds the counter values
6139  * 	@sleep_ok: if true we may sleep while awaiting command completion
6140  *
6141  *	Returns the values of TP's CPL counters.
6142  */
6143 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
6144 			 bool sleep_ok)
6145 {
6146 	int nchan = adap->chip_params->nchan;
6147 
6148 	t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
6149 
6150 	t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
6151 }
6152 
6153 /**
6154  *	t4_tp_get_rdma_stats - read TP's RDMA MIB counters
6155  *	@adap: the adapter
6156  *	@st: holds the counter values
6157  *
6158  *	Returns the values of TP's RDMA counters.
6159  */
6160 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
6161 			  bool sleep_ok)
6162 {
6163 	t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
6164 		       sleep_ok);
6165 }
6166 
6167 /**
6168  *	t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
6169  *	@adap: the adapter
6170  *	@idx: the port index
6171  *	@st: holds the counter values
6172  * 	@sleep_ok: if true we may sleep while awaiting command completion
6173  *
6174  *	Returns the values of TP's FCoE counters for the selected port.
6175  */
6176 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
6177 		       struct tp_fcoe_stats *st, bool sleep_ok)
6178 {
6179 	u32 val[2];
6180 
6181 	t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
6182 		       sleep_ok);
6183 
6184 	t4_tp_mib_read(adap, &st->frames_drop, 1,
6185 		       A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
6186 
6187 	t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
6188 		       sleep_ok);
6189 
6190 	st->octets_ddp = ((u64)val[0] << 32) | val[1];
6191 }
6192 
6193 /**
6194  *	t4_get_usm_stats - read TP's non-TCP DDP MIB counters
6195  *	@adap: the adapter
6196  *	@st: holds the counter values
6197  * 	@sleep_ok: if true we may sleep while awaiting command completion
6198  *
6199  *	Returns the values of TP's counters for non-TCP directly-placed packets.
6200  */
6201 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
6202 		      bool sleep_ok)
6203 {
6204 	u32 val[4];
6205 
6206 	t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
6207 
6208 	st->frames = val[0];
6209 	st->drops = val[1];
6210 	st->octets = ((u64)val[2] << 32) | val[3];
6211 }
6212 
6213 /**
6214  *	t4_read_mtu_tbl - returns the values in the HW path MTU table
6215  *	@adap: the adapter
6216  *	@mtus: where to store the MTU values
6217  *	@mtu_log: where to store the MTU base-2 log (may be %NULL)
6218  *
6219  *	Reads the HW path MTU table.
6220  */
6221 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
6222 {
6223 	u32 v;
6224 	int i;
6225 
6226 	for (i = 0; i < NMTUS; ++i) {
6227 		t4_write_reg(adap, A_TP_MTU_TABLE,
6228 			     V_MTUINDEX(0xff) | V_MTUVALUE(i));
6229 		v = t4_read_reg(adap, A_TP_MTU_TABLE);
6230 		mtus[i] = G_MTUVALUE(v);
6231 		if (mtu_log)
6232 			mtu_log[i] = G_MTUWIDTH(v);
6233 	}
6234 }
6235 
6236 /**
6237  *	t4_read_cong_tbl - reads the congestion control table
6238  *	@adap: the adapter
6239  *	@incr: where to store the alpha values
6240  *
6241  *	Reads the additive increments programmed into the HW congestion
6242  *	control table.
6243  */
6244 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
6245 {
6246 	unsigned int mtu, w;
6247 
6248 	for (mtu = 0; mtu < NMTUS; ++mtu)
6249 		for (w = 0; w < NCCTRL_WIN; ++w) {
6250 			t4_write_reg(adap, A_TP_CCTRL_TABLE,
6251 				     V_ROWINDEX(0xffff) | (mtu << 5) | w);
6252 			incr[mtu][w] = (u16)t4_read_reg(adap,
6253 						A_TP_CCTRL_TABLE) & 0x1fff;
6254 		}
6255 }
6256 
6257 /**
6258  *	t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
6259  *	@adap: the adapter
6260  *	@addr: the indirect TP register address
6261  *	@mask: specifies the field within the register to modify
6262  *	@val: new value for the field
6263  *
6264  *	Sets a field of an indirect TP register to the given value.
6265  */
6266 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
6267 			    unsigned int mask, unsigned int val)
6268 {
6269 	t4_write_reg(adap, A_TP_PIO_ADDR, addr);
6270 	val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
6271 	t4_write_reg(adap, A_TP_PIO_DATA, val);
6272 }
6273 
6274 /**
6275  *	init_cong_ctrl - initialize congestion control parameters
6276  *	@a: the alpha values for congestion control
6277  *	@b: the beta values for congestion control
6278  *
6279  *	Initialize the congestion control parameters.
6280  */
6281 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
6282 {
6283 	a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
6284 	a[9] = 2;
6285 	a[10] = 3;
6286 	a[11] = 4;
6287 	a[12] = 5;
6288 	a[13] = 6;
6289 	a[14] = 7;
6290 	a[15] = 8;
6291 	a[16] = 9;
6292 	a[17] = 10;
6293 	a[18] = 14;
6294 	a[19] = 17;
6295 	a[20] = 21;
6296 	a[21] = 25;
6297 	a[22] = 30;
6298 	a[23] = 35;
6299 	a[24] = 45;
6300 	a[25] = 60;
6301 	a[26] = 80;
6302 	a[27] = 100;
6303 	a[28] = 200;
6304 	a[29] = 300;
6305 	a[30] = 400;
6306 	a[31] = 500;
6307 
6308 	b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
6309 	b[9] = b[10] = 1;
6310 	b[11] = b[12] = 2;
6311 	b[13] = b[14] = b[15] = b[16] = 3;
6312 	b[17] = b[18] = b[19] = b[20] = b[21] = 4;
6313 	b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
6314 	b[28] = b[29] = 6;
6315 	b[30] = b[31] = 7;
6316 }
6317 
6318 /* The minimum additive increment value for the congestion control table */
6319 #define CC_MIN_INCR 2U
6320 
6321 /**
6322  *	t4_load_mtus - write the MTU and congestion control HW tables
6323  *	@adap: the adapter
6324  *	@mtus: the values for the MTU table
6325  *	@alpha: the values for the congestion control alpha parameter
6326  *	@beta: the values for the congestion control beta parameter
6327  *
6328  *	Write the HW MTU table with the supplied MTUs and the high-speed
6329  *	congestion control table with the supplied alpha, beta, and MTUs.
6330  *	We write the two tables together because the additive increments
6331  *	depend on the MTUs.
6332  */
6333 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
6334 		  const unsigned short *alpha, const unsigned short *beta)
6335 {
6336 	static const unsigned int avg_pkts[NCCTRL_WIN] = {
6337 		2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
6338 		896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
6339 		28672, 40960, 57344, 81920, 114688, 163840, 229376
6340 	};
6341 
6342 	unsigned int i, w;
6343 
6344 	for (i = 0; i < NMTUS; ++i) {
6345 		unsigned int mtu = mtus[i];
6346 		unsigned int log2 = fls(mtu);
6347 
6348 		if (!(mtu & ((1 << log2) >> 2)))     /* round */
6349 			log2--;
6350 		t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
6351 			     V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
6352 
6353 		for (w = 0; w < NCCTRL_WIN; ++w) {
6354 			unsigned int inc;
6355 
6356 			inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
6357 				  CC_MIN_INCR);
6358 
6359 			t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
6360 				     (w << 16) | (beta[w] << 13) | inc);
6361 		}
6362 	}
6363 }
6364 
6365 /**
6366  *	t4_set_pace_tbl - set the pace table
6367  *	@adap: the adapter
6368  *	@pace_vals: the pace values in microseconds
6369  *	@start: index of the first entry in the HW pace table to set
6370  *	@n: how many entries to set
6371  *
6372  *	Sets (a subset of the) HW pace table.
6373  */
6374 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
6375 		     unsigned int start, unsigned int n)
6376 {
6377 	unsigned int vals[NTX_SCHED], i;
6378 	unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
6379 
6380 	if (n > NTX_SCHED)
6381 	    return -ERANGE;
6382 
6383 	/* convert values from us to dack ticks, rounding to closest value */
6384 	for (i = 0; i < n; i++, pace_vals++) {
6385 		vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
6386 		if (vals[i] > 0x7ff)
6387 			return -ERANGE;
6388 		if (*pace_vals && vals[i] == 0)
6389 			return -ERANGE;
6390 	}
6391 	for (i = 0; i < n; i++, start++)
6392 		t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
6393 	return 0;
6394 }
6395 
6396 /**
6397  *	t4_set_sched_bps - set the bit rate for a HW traffic scheduler
6398  *	@adap: the adapter
6399  *	@kbps: target rate in Kbps
6400  *	@sched: the scheduler index
6401  *
6402  *	Configure a Tx HW scheduler for the target rate.
6403  */
6404 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
6405 {
6406 	unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
6407 	unsigned int clk = adap->params.vpd.cclk * 1000;
6408 	unsigned int selected_cpt = 0, selected_bpt = 0;
6409 
6410 	if (kbps > 0) {
6411 		kbps *= 125;     /* -> bytes */
6412 		for (cpt = 1; cpt <= 255; cpt++) {
6413 			tps = clk / cpt;
6414 			bpt = (kbps + tps / 2) / tps;
6415 			if (bpt > 0 && bpt <= 255) {
6416 				v = bpt * tps;
6417 				delta = v >= kbps ? v - kbps : kbps - v;
6418 				if (delta < mindelta) {
6419 					mindelta = delta;
6420 					selected_cpt = cpt;
6421 					selected_bpt = bpt;
6422 				}
6423 			} else if (selected_cpt)
6424 				break;
6425 		}
6426 		if (!selected_cpt)
6427 			return -EINVAL;
6428 	}
6429 	t4_write_reg(adap, A_TP_TM_PIO_ADDR,
6430 		     A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
6431 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6432 	if (sched & 1)
6433 		v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
6434 	else
6435 		v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
6436 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6437 	return 0;
6438 }
6439 
6440 /**
6441  *	t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
6442  *	@adap: the adapter
6443  *	@sched: the scheduler index
6444  *	@ipg: the interpacket delay in tenths of nanoseconds
6445  *
6446  *	Set the interpacket delay for a HW packet rate scheduler.
6447  */
6448 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
6449 {
6450 	unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
6451 
6452 	/* convert ipg to nearest number of core clocks */
6453 	ipg *= core_ticks_per_usec(adap);
6454 	ipg = (ipg + 5000) / 10000;
6455 	if (ipg > M_TXTIMERSEPQ0)
6456 		return -EINVAL;
6457 
6458 	t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
6459 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6460 	if (sched & 1)
6461 		v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
6462 	else
6463 		v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
6464 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6465 	t4_read_reg(adap, A_TP_TM_PIO_DATA);
6466 	return 0;
6467 }
6468 
6469 /*
6470  * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
6471  * clocks.  The formula is
6472  *
6473  * bytes/s = bytes256 * 256 * ClkFreq / 4096
6474  *
6475  * which is equivalent to
6476  *
6477  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
6478  */
6479 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
6480 {
6481 	u64 v = (u64)bytes256 * adap->params.vpd.cclk;
6482 
6483 	return v * 62 + v / 2;
6484 }
6485 
6486 /**
6487  *	t4_get_chan_txrate - get the current per channel Tx rates
6488  *	@adap: the adapter
6489  *	@nic_rate: rates for NIC traffic
6490  *	@ofld_rate: rates for offloaded traffic
6491  *
6492  *	Return the current Tx rates in bytes/s for NIC and offloaded traffic
6493  *	for each channel.
6494  */
6495 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
6496 {
6497 	u32 v;
6498 
6499 	v = t4_read_reg(adap, A_TP_TX_TRATE);
6500 	nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
6501 	nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
6502 	if (adap->chip_params->nchan > 2) {
6503 		nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
6504 		nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
6505 	}
6506 
6507 	v = t4_read_reg(adap, A_TP_TX_ORATE);
6508 	ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
6509 	ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
6510 	if (adap->chip_params->nchan > 2) {
6511 		ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
6512 		ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
6513 	}
6514 }
6515 
6516 /**
6517  *	t4_set_trace_filter - configure one of the tracing filters
6518  *	@adap: the adapter
6519  *	@tp: the desired trace filter parameters
6520  *	@idx: which filter to configure
6521  *	@enable: whether to enable or disable the filter
6522  *
6523  *	Configures one of the tracing filters available in HW.  If @tp is %NULL
6524  *	it indicates that the filter is already written in the register and it
6525  *	just needs to be enabled or disabled.
6526  */
6527 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
6528     int idx, int enable)
6529 {
6530 	int i, ofst = idx * 4;
6531 	u32 data_reg, mask_reg, cfg;
6532 	u32 multitrc = F_TRCMULTIFILTER;
6533 	u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
6534 
6535 	if (idx < 0 || idx >= NTRACE)
6536 		return -EINVAL;
6537 
6538 	if (tp == NULL || !enable) {
6539 		t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
6540 		    enable ? en : 0);
6541 		return 0;
6542 	}
6543 
6544 	/*
6545 	 * TODO - After T4 data book is updated, specify the exact
6546 	 * section below.
6547 	 *
6548 	 * See T4 data book - MPS section for a complete description
6549 	 * of the below if..else handling of A_MPS_TRC_CFG register
6550 	 * value.
6551 	 */
6552 	cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
6553 	if (cfg & F_TRCMULTIFILTER) {
6554 		/*
6555 		 * If multiple tracers are enabled, then maximum
6556 		 * capture size is 2.5KB (FIFO size of a single channel)
6557 		 * minus 2 flits for CPL_TRACE_PKT header.
6558 		 */
6559 		if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
6560 			return -EINVAL;
6561 	} else {
6562 		/*
6563 		 * If multiple tracers are disabled, to avoid deadlocks
6564 		 * maximum packet capture size of 9600 bytes is recommended.
6565 		 * Also in this mode, only trace0 can be enabled and running.
6566 		 */
6567 		multitrc = 0;
6568 		if (tp->snap_len > 9600 || idx)
6569 			return -EINVAL;
6570 	}
6571 
6572 	if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
6573 	    tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
6574 	    tp->min_len > M_TFMINPKTSIZE)
6575 		return -EINVAL;
6576 
6577 	/* stop the tracer we'll be changing */
6578 	t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
6579 
6580 	idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
6581 	data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
6582 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
6583 
6584 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6585 		t4_write_reg(adap, data_reg, tp->data[i]);
6586 		t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6587 	}
6588 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
6589 		     V_TFCAPTUREMAX(tp->snap_len) |
6590 		     V_TFMINPKTSIZE(tp->min_len));
6591 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
6592 		     V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
6593 		     (is_t4(adap) ?
6594 		     V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
6595 		     V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
6596 
6597 	return 0;
6598 }
6599 
6600 /**
6601  *	t4_get_trace_filter - query one of the tracing filters
6602  *	@adap: the adapter
6603  *	@tp: the current trace filter parameters
6604  *	@idx: which trace filter to query
6605  *	@enabled: non-zero if the filter is enabled
6606  *
6607  *	Returns the current settings of one of the HW tracing filters.
6608  */
6609 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6610 			 int *enabled)
6611 {
6612 	u32 ctla, ctlb;
6613 	int i, ofst = idx * 4;
6614 	u32 data_reg, mask_reg;
6615 
6616 	ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
6617 	ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
6618 
6619 	if (is_t4(adap)) {
6620 		*enabled = !!(ctla & F_TFEN);
6621 		tp->port =  G_TFPORT(ctla);
6622 		tp->invert = !!(ctla & F_TFINVERTMATCH);
6623 	} else {
6624 		*enabled = !!(ctla & F_T5_TFEN);
6625 		tp->port = G_T5_TFPORT(ctla);
6626 		tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
6627 	}
6628 	tp->snap_len = G_TFCAPTUREMAX(ctlb);
6629 	tp->min_len = G_TFMINPKTSIZE(ctlb);
6630 	tp->skip_ofst = G_TFOFFSET(ctla);
6631 	tp->skip_len = G_TFLENGTH(ctla);
6632 
6633 	ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
6634 	data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
6635 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
6636 
6637 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6638 		tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6639 		tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6640 	}
6641 }
6642 
6643 /**
6644  *	t4_pmtx_get_stats - returns the HW stats from PMTX
6645  *	@adap: the adapter
6646  *	@cnt: where to store the count statistics
6647  *	@cycles: where to store the cycle statistics
6648  *
6649  *	Returns performance statistics from PMTX.
6650  */
6651 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6652 {
6653 	int i;
6654 	u32 data[2];
6655 
6656 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6657 		t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
6658 		cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
6659 		if (is_t4(adap))
6660 			cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
6661 		else {
6662 			t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
6663 					 A_PM_TX_DBG_DATA, data, 2,
6664 					 A_PM_TX_DBG_STAT_MSB);
6665 			cycles[i] = (((u64)data[0] << 32) | data[1]);
6666 		}
6667 	}
6668 }
6669 
6670 /**
6671  *	t4_pmrx_get_stats - returns the HW stats from PMRX
6672  *	@adap: the adapter
6673  *	@cnt: where to store the count statistics
6674  *	@cycles: where to store the cycle statistics
6675  *
6676  *	Returns performance statistics from PMRX.
6677  */
6678 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6679 {
6680 	int i;
6681 	u32 data[2];
6682 
6683 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6684 		t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
6685 		cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
6686 		if (is_t4(adap)) {
6687 			cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
6688 		} else {
6689 			t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
6690 					 A_PM_RX_DBG_DATA, data, 2,
6691 					 A_PM_RX_DBG_STAT_MSB);
6692 			cycles[i] = (((u64)data[0] << 32) | data[1]);
6693 		}
6694 	}
6695 }
6696 
6697 /**
6698  *	t4_get_mps_bg_map - return the buffer groups associated with a port
6699  *	@adap: the adapter
6700  *	@idx: the port index
6701  *
6702  *	Returns a bitmap indicating which MPS buffer groups are associated
6703  *	with the given port.  Bit i is set if buffer group i is used by the
6704  *	port.
6705  */
6706 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
6707 {
6708 	u32 n;
6709 
6710 	if (adap->params.mps_bg_map)
6711 		return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
6712 
6713 	n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6714 	if (n == 0)
6715 		return idx == 0 ? 0xf : 0;
6716 	if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6717 		return idx < 2 ? (3 << (2 * idx)) : 0;
6718 	return 1 << idx;
6719 }
6720 
6721 /*
6722  * TP RX e-channels associated with the port.
6723  */
6724 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
6725 {
6726 	u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
6727 
6728 	if (n == 0)
6729 		return idx == 0 ? 0xf : 0;
6730 	if (n == 1 && chip_id(adap) <= CHELSIO_T5)
6731 		return idx < 2 ? (3 << (2 * idx)) : 0;
6732 	return 1 << idx;
6733 }
6734 
6735 /**
6736  *      t4_get_port_type_description - return Port Type string description
6737  *      @port_type: firmware Port Type enumeration
6738  */
6739 const char *t4_get_port_type_description(enum fw_port_type port_type)
6740 {
6741 	static const char *const port_type_description[] = {
6742 		"Fiber_XFI",
6743 		"Fiber_XAUI",
6744 		"BT_SGMII",
6745 		"BT_XFI",
6746 		"BT_XAUI",
6747 		"KX4",
6748 		"CX4",
6749 		"KX",
6750 		"KR",
6751 		"SFP",
6752 		"BP_AP",
6753 		"BP4_AP",
6754 		"QSFP_10G",
6755 		"QSA",
6756 		"QSFP",
6757 		"BP40_BA",
6758 		"KR4_100G",
6759 		"CR4_QSFP",
6760 		"CR_QSFP",
6761 		"CR2_QSFP",
6762 		"SFP28",
6763 		"KR_SFP28",
6764 	};
6765 
6766 	if (port_type < ARRAY_SIZE(port_type_description))
6767 		return port_type_description[port_type];
6768 	return "UNKNOWN";
6769 }
6770 
6771 /**
6772  *      t4_get_port_stats_offset - collect port stats relative to a previous
6773  *				   snapshot
6774  *      @adap: The adapter
6775  *      @idx: The port
6776  *      @stats: Current stats to fill
6777  *      @offset: Previous stats snapshot
6778  */
6779 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6780 		struct port_stats *stats,
6781 		struct port_stats *offset)
6782 {
6783 	u64 *s, *o;
6784 	int i;
6785 
6786 	t4_get_port_stats(adap, idx, stats);
6787 	for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
6788 			i < (sizeof(struct port_stats)/sizeof(u64)) ;
6789 			i++, s++, o++)
6790 		*s -= *o;
6791 }
6792 
6793 /**
6794  *	t4_get_port_stats - collect port statistics
6795  *	@adap: the adapter
6796  *	@idx: the port index
6797  *	@p: the stats structure to fill
6798  *
6799  *	Collect statistics related to the given port from HW.
6800  */
6801 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6802 {
6803 	u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
6804 	u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
6805 
6806 #define GET_STAT(name) \
6807 	t4_read_reg64(adap, \
6808 	(is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
6809 	T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
6810 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6811 
6812 	p->tx_pause		= GET_STAT(TX_PORT_PAUSE);
6813 	p->tx_octets		= GET_STAT(TX_PORT_BYTES);
6814 	p->tx_frames		= GET_STAT(TX_PORT_FRAMES);
6815 	p->tx_bcast_frames	= GET_STAT(TX_PORT_BCAST);
6816 	p->tx_mcast_frames	= GET_STAT(TX_PORT_MCAST);
6817 	p->tx_ucast_frames	= GET_STAT(TX_PORT_UCAST);
6818 	p->tx_error_frames	= GET_STAT(TX_PORT_ERROR);
6819 	p->tx_frames_64		= GET_STAT(TX_PORT_64B);
6820 	p->tx_frames_65_127	= GET_STAT(TX_PORT_65B_127B);
6821 	p->tx_frames_128_255	= GET_STAT(TX_PORT_128B_255B);
6822 	p->tx_frames_256_511	= GET_STAT(TX_PORT_256B_511B);
6823 	p->tx_frames_512_1023	= GET_STAT(TX_PORT_512B_1023B);
6824 	p->tx_frames_1024_1518	= GET_STAT(TX_PORT_1024B_1518B);
6825 	p->tx_frames_1519_max	= GET_STAT(TX_PORT_1519B_MAX);
6826 	p->tx_drop		= GET_STAT(TX_PORT_DROP);
6827 	p->tx_ppp0		= GET_STAT(TX_PORT_PPP0);
6828 	p->tx_ppp1		= GET_STAT(TX_PORT_PPP1);
6829 	p->tx_ppp2		= GET_STAT(TX_PORT_PPP2);
6830 	p->tx_ppp3		= GET_STAT(TX_PORT_PPP3);
6831 	p->tx_ppp4		= GET_STAT(TX_PORT_PPP4);
6832 	p->tx_ppp5		= GET_STAT(TX_PORT_PPP5);
6833 	p->tx_ppp6		= GET_STAT(TX_PORT_PPP6);
6834 	p->tx_ppp7		= GET_STAT(TX_PORT_PPP7);
6835 
6836 	if (chip_id(adap) >= CHELSIO_T5) {
6837 		if (stat_ctl & F_COUNTPAUSESTATTX) {
6838 			p->tx_frames -= p->tx_pause;
6839 			p->tx_octets -= p->tx_pause * 64;
6840 		}
6841 		if (stat_ctl & F_COUNTPAUSEMCTX)
6842 			p->tx_mcast_frames -= p->tx_pause;
6843 	}
6844 
6845 	p->rx_pause		= GET_STAT(RX_PORT_PAUSE);
6846 	p->rx_octets		= GET_STAT(RX_PORT_BYTES);
6847 	p->rx_frames		= GET_STAT(RX_PORT_FRAMES);
6848 	p->rx_bcast_frames	= GET_STAT(RX_PORT_BCAST);
6849 	p->rx_mcast_frames	= GET_STAT(RX_PORT_MCAST);
6850 	p->rx_ucast_frames	= GET_STAT(RX_PORT_UCAST);
6851 	p->rx_too_long		= GET_STAT(RX_PORT_MTU_ERROR);
6852 	p->rx_jabber		= GET_STAT(RX_PORT_MTU_CRC_ERROR);
6853 	p->rx_fcs_err		= GET_STAT(RX_PORT_CRC_ERROR);
6854 	p->rx_len_err		= GET_STAT(RX_PORT_LEN_ERROR);
6855 	p->rx_symbol_err	= GET_STAT(RX_PORT_SYM_ERROR);
6856 	p->rx_runt		= GET_STAT(RX_PORT_LESS_64B);
6857 	p->rx_frames_64		= GET_STAT(RX_PORT_64B);
6858 	p->rx_frames_65_127	= GET_STAT(RX_PORT_65B_127B);
6859 	p->rx_frames_128_255	= GET_STAT(RX_PORT_128B_255B);
6860 	p->rx_frames_256_511	= GET_STAT(RX_PORT_256B_511B);
6861 	p->rx_frames_512_1023	= GET_STAT(RX_PORT_512B_1023B);
6862 	p->rx_frames_1024_1518	= GET_STAT(RX_PORT_1024B_1518B);
6863 	p->rx_frames_1519_max	= GET_STAT(RX_PORT_1519B_MAX);
6864 	p->rx_ppp0		= GET_STAT(RX_PORT_PPP0);
6865 	p->rx_ppp1		= GET_STAT(RX_PORT_PPP1);
6866 	p->rx_ppp2		= GET_STAT(RX_PORT_PPP2);
6867 	p->rx_ppp3		= GET_STAT(RX_PORT_PPP3);
6868 	p->rx_ppp4		= GET_STAT(RX_PORT_PPP4);
6869 	p->rx_ppp5		= GET_STAT(RX_PORT_PPP5);
6870 	p->rx_ppp6		= GET_STAT(RX_PORT_PPP6);
6871 	p->rx_ppp7		= GET_STAT(RX_PORT_PPP7);
6872 
6873 	if (chip_id(adap) >= CHELSIO_T5) {
6874 		if (stat_ctl & F_COUNTPAUSESTATRX) {
6875 			p->rx_frames -= p->rx_pause;
6876 			p->rx_octets -= p->rx_pause * 64;
6877 		}
6878 		if (stat_ctl & F_COUNTPAUSEMCRX)
6879 			p->rx_mcast_frames -= p->rx_pause;
6880 	}
6881 
6882 	p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6883 	p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6884 	p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6885 	p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6886 	p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6887 	p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6888 	p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6889 	p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6890 
6891 #undef GET_STAT
6892 #undef GET_STAT_COM
6893 }
6894 
6895 /**
6896  *	t4_get_lb_stats - collect loopback port statistics
6897  *	@adap: the adapter
6898  *	@idx: the loopback port index
6899  *	@p: the stats structure to fill
6900  *
6901  *	Return HW statistics for the given loopback port.
6902  */
6903 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6904 {
6905 	u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
6906 
6907 #define GET_STAT(name) \
6908 	t4_read_reg64(adap, \
6909 	(is_t4(adap) ? \
6910 	PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
6911 	T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
6912 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6913 
6914 	p->octets	= GET_STAT(BYTES);
6915 	p->frames	= GET_STAT(FRAMES);
6916 	p->bcast_frames	= GET_STAT(BCAST);
6917 	p->mcast_frames	= GET_STAT(MCAST);
6918 	p->ucast_frames	= GET_STAT(UCAST);
6919 	p->error_frames	= GET_STAT(ERROR);
6920 
6921 	p->frames_64		= GET_STAT(64B);
6922 	p->frames_65_127	= GET_STAT(65B_127B);
6923 	p->frames_128_255	= GET_STAT(128B_255B);
6924 	p->frames_256_511	= GET_STAT(256B_511B);
6925 	p->frames_512_1023	= GET_STAT(512B_1023B);
6926 	p->frames_1024_1518	= GET_STAT(1024B_1518B);
6927 	p->frames_1519_max	= GET_STAT(1519B_MAX);
6928 	p->drop			= GET_STAT(DROP_FRAMES);
6929 
6930 	p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6931 	p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6932 	p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6933 	p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6934 	p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6935 	p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6936 	p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6937 	p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6938 
6939 #undef GET_STAT
6940 #undef GET_STAT_COM
6941 }
6942 
6943 /**
6944  *	t4_wol_magic_enable - enable/disable magic packet WoL
6945  *	@adap: the adapter
6946  *	@port: the physical port index
6947  *	@addr: MAC address expected in magic packets, %NULL to disable
6948  *
6949  *	Enables/disables magic packet wake-on-LAN for the selected port.
6950  */
6951 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
6952 			 const u8 *addr)
6953 {
6954 	u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
6955 
6956 	if (is_t4(adap)) {
6957 		mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
6958 		mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
6959 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
6960 	} else {
6961 		mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
6962 		mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
6963 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
6964 	}
6965 
6966 	if (addr) {
6967 		t4_write_reg(adap, mag_id_reg_l,
6968 			     (addr[2] << 24) | (addr[3] << 16) |
6969 			     (addr[4] << 8) | addr[5]);
6970 		t4_write_reg(adap, mag_id_reg_h,
6971 			     (addr[0] << 8) | addr[1]);
6972 	}
6973 	t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
6974 			 V_MAGICEN(addr != NULL));
6975 }
6976 
6977 /**
6978  *	t4_wol_pat_enable - enable/disable pattern-based WoL
6979  *	@adap: the adapter
6980  *	@port: the physical port index
6981  *	@map: bitmap of which HW pattern filters to set
6982  *	@mask0: byte mask for bytes 0-63 of a packet
6983  *	@mask1: byte mask for bytes 64-127 of a packet
6984  *	@crc: Ethernet CRC for selected bytes
6985  *	@enable: enable/disable switch
6986  *
6987  *	Sets the pattern filters indicated in @map to mask out the bytes
6988  *	specified in @mask0/@mask1 in received packets and compare the CRC of
6989  *	the resulting packet against @crc.  If @enable is %true pattern-based
6990  *	WoL is enabled, otherwise disabled.
6991  */
6992 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
6993 		      u64 mask0, u64 mask1, unsigned int crc, bool enable)
6994 {
6995 	int i;
6996 	u32 port_cfg_reg;
6997 
6998 	if (is_t4(adap))
6999 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7000 	else
7001 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7002 
7003 	if (!enable) {
7004 		t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
7005 		return 0;
7006 	}
7007 	if (map > 0xff)
7008 		return -EINVAL;
7009 
7010 #define EPIO_REG(name) \
7011 	(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
7012 	T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
7013 
7014 	t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
7015 	t4_write_reg(adap, EPIO_REG(DATA2), mask1);
7016 	t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
7017 
7018 	for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
7019 		if (!(map & 1))
7020 			continue;
7021 
7022 		/* write byte masks */
7023 		t4_write_reg(adap, EPIO_REG(DATA0), mask0);
7024 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
7025 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
7026 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7027 			return -ETIMEDOUT;
7028 
7029 		/* write CRC */
7030 		t4_write_reg(adap, EPIO_REG(DATA0), crc);
7031 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
7032 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
7033 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7034 			return -ETIMEDOUT;
7035 	}
7036 #undef EPIO_REG
7037 
7038 	t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
7039 	return 0;
7040 }
7041 
7042 /*     t4_mk_filtdelwr - create a delete filter WR
7043  *     @ftid: the filter ID
7044  *     @wr: the filter work request to populate
7045  *     @qid: ingress queue to receive the delete notification
7046  *
7047  *     Creates a filter work request to delete the supplied filter.  If @qid is
7048  *     negative the delete notification is suppressed.
7049  */
7050 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
7051 {
7052 	memset(wr, 0, sizeof(*wr));
7053 	wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
7054 	wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
7055 	wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
7056 				    V_FW_FILTER_WR_NOREPLY(qid < 0));
7057 	wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
7058 	if (qid >= 0)
7059 		wr->rx_chan_rx_rpl_iq =
7060 				cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
7061 }
7062 
7063 #define INIT_CMD(var, cmd, rd_wr) do { \
7064 	(var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
7065 					F_FW_CMD_REQUEST | \
7066 					F_FW_CMD_##rd_wr); \
7067 	(var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
7068 } while (0)
7069 
7070 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
7071 			  u32 addr, u32 val)
7072 {
7073 	u32 ldst_addrspace;
7074 	struct fw_ldst_cmd c;
7075 
7076 	memset(&c, 0, sizeof(c));
7077 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
7078 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7079 					F_FW_CMD_REQUEST |
7080 					F_FW_CMD_WRITE |
7081 					ldst_addrspace);
7082 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7083 	c.u.addrval.addr = cpu_to_be32(addr);
7084 	c.u.addrval.val = cpu_to_be32(val);
7085 
7086 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7087 }
7088 
7089 /**
7090  *	t4_mdio_rd - read a PHY register through MDIO
7091  *	@adap: the adapter
7092  *	@mbox: mailbox to use for the FW command
7093  *	@phy_addr: the PHY address
7094  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
7095  *	@reg: the register to read
7096  *	@valp: where to store the value
7097  *
7098  *	Issues a FW command through the given mailbox to read a PHY register.
7099  */
7100 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7101 	       unsigned int mmd, unsigned int reg, unsigned int *valp)
7102 {
7103 	int ret;
7104 	u32 ldst_addrspace;
7105 	struct fw_ldst_cmd c;
7106 
7107 	memset(&c, 0, sizeof(c));
7108 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7109 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7110 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
7111 					ldst_addrspace);
7112 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7113 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7114 					 V_FW_LDST_CMD_MMD(mmd));
7115 	c.u.mdio.raddr = cpu_to_be16(reg);
7116 
7117 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7118 	if (ret == 0)
7119 		*valp = be16_to_cpu(c.u.mdio.rval);
7120 	return ret;
7121 }
7122 
7123 /**
7124  *	t4_mdio_wr - write a PHY register through MDIO
7125  *	@adap: the adapter
7126  *	@mbox: mailbox to use for the FW command
7127  *	@phy_addr: the PHY address
7128  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
7129  *	@reg: the register to write
7130  *	@valp: value to write
7131  *
7132  *	Issues a FW command through the given mailbox to write a PHY register.
7133  */
7134 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7135 	       unsigned int mmd, unsigned int reg, unsigned int val)
7136 {
7137 	u32 ldst_addrspace;
7138 	struct fw_ldst_cmd c;
7139 
7140 	memset(&c, 0, sizeof(c));
7141 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7142 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7143 					F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7144 					ldst_addrspace);
7145 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7146 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7147 					 V_FW_LDST_CMD_MMD(mmd));
7148 	c.u.mdio.raddr = cpu_to_be16(reg);
7149 	c.u.mdio.rval = cpu_to_be16(val);
7150 
7151 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7152 }
7153 
7154 /**
7155  *
7156  *	t4_sge_decode_idma_state - decode the idma state
7157  *	@adap: the adapter
7158  *	@state: the state idma is stuck in
7159  */
7160 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
7161 {
7162 	static const char * const t4_decode[] = {
7163 		"IDMA_IDLE",
7164 		"IDMA_PUSH_MORE_CPL_FIFO",
7165 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7166 		"Not used",
7167 		"IDMA_PHYSADDR_SEND_PCIEHDR",
7168 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7169 		"IDMA_PHYSADDR_SEND_PAYLOAD",
7170 		"IDMA_SEND_FIFO_TO_IMSG",
7171 		"IDMA_FL_REQ_DATA_FL_PREP",
7172 		"IDMA_FL_REQ_DATA_FL",
7173 		"IDMA_FL_DROP",
7174 		"IDMA_FL_H_REQ_HEADER_FL",
7175 		"IDMA_FL_H_SEND_PCIEHDR",
7176 		"IDMA_FL_H_PUSH_CPL_FIFO",
7177 		"IDMA_FL_H_SEND_CPL",
7178 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
7179 		"IDMA_FL_H_SEND_IP_HDR",
7180 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
7181 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
7182 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
7183 		"IDMA_FL_D_SEND_PCIEHDR",
7184 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7185 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
7186 		"IDMA_FL_SEND_PCIEHDR",
7187 		"IDMA_FL_PUSH_CPL_FIFO",
7188 		"IDMA_FL_SEND_CPL",
7189 		"IDMA_FL_SEND_PAYLOAD_FIRST",
7190 		"IDMA_FL_SEND_PAYLOAD",
7191 		"IDMA_FL_REQ_NEXT_DATA_FL",
7192 		"IDMA_FL_SEND_NEXT_PCIEHDR",
7193 		"IDMA_FL_SEND_PADDING",
7194 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
7195 		"IDMA_FL_SEND_FIFO_TO_IMSG",
7196 		"IDMA_FL_REQ_DATAFL_DONE",
7197 		"IDMA_FL_REQ_HEADERFL_DONE",
7198 	};
7199 	static const char * const t5_decode[] = {
7200 		"IDMA_IDLE",
7201 		"IDMA_ALMOST_IDLE",
7202 		"IDMA_PUSH_MORE_CPL_FIFO",
7203 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7204 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7205 		"IDMA_PHYSADDR_SEND_PCIEHDR",
7206 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7207 		"IDMA_PHYSADDR_SEND_PAYLOAD",
7208 		"IDMA_SEND_FIFO_TO_IMSG",
7209 		"IDMA_FL_REQ_DATA_FL",
7210 		"IDMA_FL_DROP",
7211 		"IDMA_FL_DROP_SEND_INC",
7212 		"IDMA_FL_H_REQ_HEADER_FL",
7213 		"IDMA_FL_H_SEND_PCIEHDR",
7214 		"IDMA_FL_H_PUSH_CPL_FIFO",
7215 		"IDMA_FL_H_SEND_CPL",
7216 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
7217 		"IDMA_FL_H_SEND_IP_HDR",
7218 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
7219 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
7220 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
7221 		"IDMA_FL_D_SEND_PCIEHDR",
7222 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7223 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
7224 		"IDMA_FL_SEND_PCIEHDR",
7225 		"IDMA_FL_PUSH_CPL_FIFO",
7226 		"IDMA_FL_SEND_CPL",
7227 		"IDMA_FL_SEND_PAYLOAD_FIRST",
7228 		"IDMA_FL_SEND_PAYLOAD",
7229 		"IDMA_FL_REQ_NEXT_DATA_FL",
7230 		"IDMA_FL_SEND_NEXT_PCIEHDR",
7231 		"IDMA_FL_SEND_PADDING",
7232 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
7233 	};
7234 	static const char * const t6_decode[] = {
7235 		"IDMA_IDLE",
7236 		"IDMA_PUSH_MORE_CPL_FIFO",
7237 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7238 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7239 		"IDMA_PHYSADDR_SEND_PCIEHDR",
7240 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7241 		"IDMA_PHYSADDR_SEND_PAYLOAD",
7242 		"IDMA_FL_REQ_DATA_FL",
7243 		"IDMA_FL_DROP",
7244 		"IDMA_FL_DROP_SEND_INC",
7245 		"IDMA_FL_H_REQ_HEADER_FL",
7246 		"IDMA_FL_H_SEND_PCIEHDR",
7247 		"IDMA_FL_H_PUSH_CPL_FIFO",
7248 		"IDMA_FL_H_SEND_CPL",
7249 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
7250 		"IDMA_FL_H_SEND_IP_HDR",
7251 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
7252 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
7253 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
7254 		"IDMA_FL_D_SEND_PCIEHDR",
7255 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7256 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
7257 		"IDMA_FL_SEND_PCIEHDR",
7258 		"IDMA_FL_PUSH_CPL_FIFO",
7259 		"IDMA_FL_SEND_CPL",
7260 		"IDMA_FL_SEND_PAYLOAD_FIRST",
7261 		"IDMA_FL_SEND_PAYLOAD",
7262 		"IDMA_FL_REQ_NEXT_DATA_FL",
7263 		"IDMA_FL_SEND_NEXT_PCIEHDR",
7264 		"IDMA_FL_SEND_PADDING",
7265 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
7266 	};
7267 	static const u32 sge_regs[] = {
7268 		A_SGE_DEBUG_DATA_LOW_INDEX_2,
7269 		A_SGE_DEBUG_DATA_LOW_INDEX_3,
7270 		A_SGE_DEBUG_DATA_HIGH_INDEX_10,
7271 	};
7272 	const char * const *sge_idma_decode;
7273 	int sge_idma_decode_nstates;
7274 	int i;
7275 	unsigned int chip_version = chip_id(adapter);
7276 
7277 	/* Select the right set of decode strings to dump depending on the
7278 	 * adapter chip type.
7279 	 */
7280 	switch (chip_version) {
7281 	case CHELSIO_T4:
7282 		sge_idma_decode = (const char * const *)t4_decode;
7283 		sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
7284 		break;
7285 
7286 	case CHELSIO_T5:
7287 		sge_idma_decode = (const char * const *)t5_decode;
7288 		sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
7289 		break;
7290 
7291 	case CHELSIO_T6:
7292 		sge_idma_decode = (const char * const *)t6_decode;
7293 		sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
7294 		break;
7295 
7296 	default:
7297 		CH_ERR(adapter,	"Unsupported chip version %d\n", chip_version);
7298 		return;
7299 	}
7300 
7301 	if (state < sge_idma_decode_nstates)
7302 		CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
7303 	else
7304 		CH_WARN(adapter, "idma state %d unknown\n", state);
7305 
7306 	for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
7307 		CH_WARN(adapter, "SGE register %#x value %#x\n",
7308 			sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
7309 }
7310 
7311 /**
7312  *      t4_sge_ctxt_flush - flush the SGE context cache
7313  *      @adap: the adapter
7314  *      @mbox: mailbox to use for the FW command
7315  *
7316  *      Issues a FW command through the given mailbox to flush the
7317  *      SGE context cache.
7318  */
7319 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
7320 {
7321 	int ret;
7322 	u32 ldst_addrspace;
7323 	struct fw_ldst_cmd c;
7324 
7325 	memset(&c, 0, sizeof(c));
7326 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
7327 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7328 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
7329 					ldst_addrspace);
7330 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7331 	c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
7332 
7333 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7334 	return ret;
7335 }
7336 
7337 /**
7338  *      t4_fw_hello - establish communication with FW
7339  *      @adap: the adapter
7340  *      @mbox: mailbox to use for the FW command
7341  *      @evt_mbox: mailbox to receive async FW events
7342  *      @master: specifies the caller's willingness to be the device master
7343  *	@state: returns the current device state (if non-NULL)
7344  *
7345  *	Issues a command to establish communication with FW.  Returns either
7346  *	an error (negative integer) or the mailbox of the Master PF.
7347  */
7348 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
7349 		enum dev_master master, enum dev_state *state)
7350 {
7351 	int ret;
7352 	struct fw_hello_cmd c;
7353 	u32 v;
7354 	unsigned int master_mbox;
7355 	int retries = FW_CMD_HELLO_RETRIES;
7356 
7357 retry:
7358 	memset(&c, 0, sizeof(c));
7359 	INIT_CMD(c, HELLO, WRITE);
7360 	c.err_to_clearinit = cpu_to_be32(
7361 		V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
7362 		V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
7363 		V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
7364 					mbox : M_FW_HELLO_CMD_MBMASTER) |
7365 		V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
7366 		V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
7367 		F_FW_HELLO_CMD_CLEARINIT);
7368 
7369 	/*
7370 	 * Issue the HELLO command to the firmware.  If it's not successful
7371 	 * but indicates that we got a "busy" or "timeout" condition, retry
7372 	 * the HELLO until we exhaust our retry limit.  If we do exceed our
7373 	 * retry limit, check to see if the firmware left us any error
7374 	 * information and report that if so ...
7375 	 */
7376 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7377 	if (ret != FW_SUCCESS) {
7378 		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
7379 			goto retry;
7380 		if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
7381 			t4_report_fw_error(adap);
7382 		return ret;
7383 	}
7384 
7385 	v = be32_to_cpu(c.err_to_clearinit);
7386 	master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
7387 	if (state) {
7388 		if (v & F_FW_HELLO_CMD_ERR)
7389 			*state = DEV_STATE_ERR;
7390 		else if (v & F_FW_HELLO_CMD_INIT)
7391 			*state = DEV_STATE_INIT;
7392 		else
7393 			*state = DEV_STATE_UNINIT;
7394 	}
7395 
7396 	/*
7397 	 * If we're not the Master PF then we need to wait around for the
7398 	 * Master PF Driver to finish setting up the adapter.
7399 	 *
7400 	 * Note that we also do this wait if we're a non-Master-capable PF and
7401 	 * there is no current Master PF; a Master PF may show up momentarily
7402 	 * and we wouldn't want to fail pointlessly.  (This can happen when an
7403 	 * OS loads lots of different drivers rapidly at the same time).  In
7404 	 * this case, the Master PF returned by the firmware will be
7405 	 * M_PCIE_FW_MASTER so the test below will work ...
7406 	 */
7407 	if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
7408 	    master_mbox != mbox) {
7409 		int waiting = FW_CMD_HELLO_TIMEOUT;
7410 
7411 		/*
7412 		 * Wait for the firmware to either indicate an error or
7413 		 * initialized state.  If we see either of these we bail out
7414 		 * and report the issue to the caller.  If we exhaust the
7415 		 * "hello timeout" and we haven't exhausted our retries, try
7416 		 * again.  Otherwise bail with a timeout error.
7417 		 */
7418 		for (;;) {
7419 			u32 pcie_fw;
7420 
7421 			msleep(50);
7422 			waiting -= 50;
7423 
7424 			/*
7425 			 * If neither Error nor Initialialized are indicated
7426 			 * by the firmware keep waiting till we exhaust our
7427 			 * timeout ... and then retry if we haven't exhausted
7428 			 * our retries ...
7429 			 */
7430 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
7431 			if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
7432 				if (waiting <= 0) {
7433 					if (retries-- > 0)
7434 						goto retry;
7435 
7436 					return -ETIMEDOUT;
7437 				}
7438 				continue;
7439 			}
7440 
7441 			/*
7442 			 * We either have an Error or Initialized condition
7443 			 * report errors preferentially.
7444 			 */
7445 			if (state) {
7446 				if (pcie_fw & F_PCIE_FW_ERR)
7447 					*state = DEV_STATE_ERR;
7448 				else if (pcie_fw & F_PCIE_FW_INIT)
7449 					*state = DEV_STATE_INIT;
7450 			}
7451 
7452 			/*
7453 			 * If we arrived before a Master PF was selected and
7454 			 * there's not a valid Master PF, grab its identity
7455 			 * for our caller.
7456 			 */
7457 			if (master_mbox == M_PCIE_FW_MASTER &&
7458 			    (pcie_fw & F_PCIE_FW_MASTER_VLD))
7459 				master_mbox = G_PCIE_FW_MASTER(pcie_fw);
7460 			break;
7461 		}
7462 	}
7463 
7464 	return master_mbox;
7465 }
7466 
7467 /**
7468  *	t4_fw_bye - end communication with FW
7469  *	@adap: the adapter
7470  *	@mbox: mailbox to use for the FW command
7471  *
7472  *	Issues a command to terminate communication with FW.
7473  */
7474 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
7475 {
7476 	struct fw_bye_cmd c;
7477 
7478 	memset(&c, 0, sizeof(c));
7479 	INIT_CMD(c, BYE, WRITE);
7480 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7481 }
7482 
7483 /**
7484  *	t4_fw_reset - issue a reset to FW
7485  *	@adap: the adapter
7486  *	@mbox: mailbox to use for the FW command
7487  *	@reset: specifies the type of reset to perform
7488  *
7489  *	Issues a reset command of the specified type to FW.
7490  */
7491 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7492 {
7493 	struct fw_reset_cmd c;
7494 
7495 	memset(&c, 0, sizeof(c));
7496 	INIT_CMD(c, RESET, WRITE);
7497 	c.val = cpu_to_be32(reset);
7498 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7499 }
7500 
7501 /**
7502  *	t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7503  *	@adap: the adapter
7504  *	@mbox: mailbox to use for the FW RESET command (if desired)
7505  *	@force: force uP into RESET even if FW RESET command fails
7506  *
7507  *	Issues a RESET command to firmware (if desired) with a HALT indication
7508  *	and then puts the microprocessor into RESET state.  The RESET command
7509  *	will only be issued if a legitimate mailbox is provided (mbox <=
7510  *	M_PCIE_FW_MASTER).
7511  *
7512  *	This is generally used in order for the host to safely manipulate the
7513  *	adapter without fear of conflicting with whatever the firmware might
7514  *	be doing.  The only way out of this state is to RESTART the firmware
7515  *	...
7516  */
7517 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7518 {
7519 	int ret = 0;
7520 
7521 	/*
7522 	 * If a legitimate mailbox is provided, issue a RESET command
7523 	 * with a HALT indication.
7524 	 */
7525 	if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) {
7526 		struct fw_reset_cmd c;
7527 
7528 		memset(&c, 0, sizeof(c));
7529 		INIT_CMD(c, RESET, WRITE);
7530 		c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
7531 		c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
7532 		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7533 	}
7534 
7535 	/*
7536 	 * Normally we won't complete the operation if the firmware RESET
7537 	 * command fails but if our caller insists we'll go ahead and put the
7538 	 * uP into RESET.  This can be useful if the firmware is hung or even
7539 	 * missing ...  We'll have to take the risk of putting the uP into
7540 	 * RESET without the cooperation of firmware in that case.
7541 	 *
7542 	 * We also force the firmware's HALT flag to be on in case we bypassed
7543 	 * the firmware RESET command above or we're dealing with old firmware
7544 	 * which doesn't have the HALT capability.  This will serve as a flag
7545 	 * for the incoming firmware to know that it's coming out of a HALT
7546 	 * rather than a RESET ... if it's new enough to understand that ...
7547 	 */
7548 	if (ret == 0 || force) {
7549 		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
7550 		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
7551 				 F_PCIE_FW_HALT);
7552 	}
7553 
7554 	/*
7555 	 * And we always return the result of the firmware RESET command
7556 	 * even when we force the uP into RESET ...
7557 	 */
7558 	return ret;
7559 }
7560 
7561 /**
7562  *	t4_fw_restart - restart the firmware by taking the uP out of RESET
7563  *	@adap: the adapter
7564  *
7565  *	Restart firmware previously halted by t4_fw_halt().  On successful
7566  *	return the previous PF Master remains as the new PF Master and there
7567  *	is no need to issue a new HELLO command, etc.
7568  */
7569 int t4_fw_restart(struct adapter *adap, unsigned int mbox)
7570 {
7571 	int ms;
7572 
7573 	t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
7574 	for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7575 		if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
7576 			return FW_SUCCESS;
7577 		msleep(100);
7578 		ms += 100;
7579 	}
7580 
7581 	return -ETIMEDOUT;
7582 }
7583 
7584 /**
7585  *	t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7586  *	@adap: the adapter
7587  *	@mbox: mailbox to use for the FW RESET command (if desired)
7588  *	@fw_data: the firmware image to write
7589  *	@size: image size
7590  *	@force: force upgrade even if firmware doesn't cooperate
7591  *
7592  *	Perform all of the steps necessary for upgrading an adapter's
7593  *	firmware image.  Normally this requires the cooperation of the
7594  *	existing firmware in order to halt all existing activities
7595  *	but if an invalid mailbox token is passed in we skip that step
7596  *	(though we'll still put the adapter microprocessor into RESET in
7597  *	that case).
7598  *
7599  *	On successful return the new firmware will have been loaded and
7600  *	the adapter will have been fully RESET losing all previous setup
7601  *	state.  On unsuccessful return the adapter may be completely hosed ...
7602  *	positive errno indicates that the adapter is ~probably~ intact, a
7603  *	negative errno indicates that things are looking bad ...
7604  */
7605 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7606 		  const u8 *fw_data, unsigned int size, int force)
7607 {
7608 	const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7609 	unsigned int bootstrap =
7610 	    be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
7611 	int ret;
7612 
7613 	if (!t4_fw_matches_chip(adap, fw_hdr))
7614 		return -EINVAL;
7615 
7616 	if (!bootstrap) {
7617 		ret = t4_fw_halt(adap, mbox, force);
7618 		if (ret < 0 && !force)
7619 			return ret;
7620 	}
7621 
7622 	ret = t4_load_fw(adap, fw_data, size);
7623 	if (ret < 0 || bootstrap)
7624 		return ret;
7625 
7626 	return t4_fw_restart(adap, mbox);
7627 }
7628 
7629 /**
7630  *	t4_fw_initialize - ask FW to initialize the device
7631  *	@adap: the adapter
7632  *	@mbox: mailbox to use for the FW command
7633  *
7634  *	Issues a command to FW to partially initialize the device.  This
7635  *	performs initialization that generally doesn't depend on user input.
7636  */
7637 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7638 {
7639 	struct fw_initialize_cmd c;
7640 
7641 	memset(&c, 0, sizeof(c));
7642 	INIT_CMD(c, INITIALIZE, WRITE);
7643 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7644 }
7645 
7646 /**
7647  *	t4_query_params_rw - query FW or device parameters
7648  *	@adap: the adapter
7649  *	@mbox: mailbox to use for the FW command
7650  *	@pf: the PF
7651  *	@vf: the VF
7652  *	@nparams: the number of parameters
7653  *	@params: the parameter names
7654  *	@val: the parameter values
7655  *	@rw: Write and read flag
7656  *
7657  *	Reads the value of FW or device parameters.  Up to 7 parameters can be
7658  *	queried at once.
7659  */
7660 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7661 		       unsigned int vf, unsigned int nparams, const u32 *params,
7662 		       u32 *val, int rw)
7663 {
7664 	int i, ret;
7665 	struct fw_params_cmd c;
7666 	__be32 *p = &c.param[0].mnem;
7667 
7668 	if (nparams > 7)
7669 		return -EINVAL;
7670 
7671 	memset(&c, 0, sizeof(c));
7672 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7673 				  F_FW_CMD_REQUEST | F_FW_CMD_READ |
7674 				  V_FW_PARAMS_CMD_PFN(pf) |
7675 				  V_FW_PARAMS_CMD_VFN(vf));
7676 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7677 
7678 	for (i = 0; i < nparams; i++) {
7679 		*p++ = cpu_to_be32(*params++);
7680 		if (rw)
7681 			*p = cpu_to_be32(*(val + i));
7682 		p++;
7683 	}
7684 
7685 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7686 	if (ret == 0)
7687 		for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7688 			*val++ = be32_to_cpu(*p);
7689 	return ret;
7690 }
7691 
7692 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7693 		    unsigned int vf, unsigned int nparams, const u32 *params,
7694 		    u32 *val)
7695 {
7696 	return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
7697 }
7698 
7699 /**
7700  *      t4_set_params_timeout - sets FW or device parameters
7701  *      @adap: the adapter
7702  *      @mbox: mailbox to use for the FW command
7703  *      @pf: the PF
7704  *      @vf: the VF
7705  *      @nparams: the number of parameters
7706  *      @params: the parameter names
7707  *      @val: the parameter values
7708  *      @timeout: the timeout time
7709  *
7710  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7711  *      specified at once.
7712  */
7713 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7714 			  unsigned int pf, unsigned int vf,
7715 			  unsigned int nparams, const u32 *params,
7716 			  const u32 *val, int timeout)
7717 {
7718 	struct fw_params_cmd c;
7719 	__be32 *p = &c.param[0].mnem;
7720 
7721 	if (nparams > 7)
7722 		return -EINVAL;
7723 
7724 	memset(&c, 0, sizeof(c));
7725 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7726 				  F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7727 				  V_FW_PARAMS_CMD_PFN(pf) |
7728 				  V_FW_PARAMS_CMD_VFN(vf));
7729 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7730 
7731 	while (nparams--) {
7732 		*p++ = cpu_to_be32(*params++);
7733 		*p++ = cpu_to_be32(*val++);
7734 	}
7735 
7736 	return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7737 }
7738 
7739 /**
7740  *	t4_set_params - sets FW or device parameters
7741  *	@adap: the adapter
7742  *	@mbox: mailbox to use for the FW command
7743  *	@pf: the PF
7744  *	@vf: the VF
7745  *	@nparams: the number of parameters
7746  *	@params: the parameter names
7747  *	@val: the parameter values
7748  *
7749  *	Sets the value of FW or device parameters.  Up to 7 parameters can be
7750  *	specified at once.
7751  */
7752 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7753 		  unsigned int vf, unsigned int nparams, const u32 *params,
7754 		  const u32 *val)
7755 {
7756 	return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7757 				     FW_CMD_MAX_TIMEOUT);
7758 }
7759 
7760 /**
7761  *	t4_cfg_pfvf - configure PF/VF resource limits
7762  *	@adap: the adapter
7763  *	@mbox: mailbox to use for the FW command
7764  *	@pf: the PF being configured
7765  *	@vf: the VF being configured
7766  *	@txq: the max number of egress queues
7767  *	@txq_eth_ctrl: the max number of egress Ethernet or control queues
7768  *	@rxqi: the max number of interrupt-capable ingress queues
7769  *	@rxq: the max number of interruptless ingress queues
7770  *	@tc: the PCI traffic class
7771  *	@vi: the max number of virtual interfaces
7772  *	@cmask: the channel access rights mask for the PF/VF
7773  *	@pmask: the port access rights mask for the PF/VF
7774  *	@nexact: the maximum number of exact MPS filters
7775  *	@rcaps: read capabilities
7776  *	@wxcaps: write/execute capabilities
7777  *
7778  *	Configures resource limits and capabilities for a physical or virtual
7779  *	function.
7780  */
7781 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7782 		unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7783 		unsigned int rxqi, unsigned int rxq, unsigned int tc,
7784 		unsigned int vi, unsigned int cmask, unsigned int pmask,
7785 		unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7786 {
7787 	struct fw_pfvf_cmd c;
7788 
7789 	memset(&c, 0, sizeof(c));
7790 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
7791 				  F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
7792 				  V_FW_PFVF_CMD_VFN(vf));
7793 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7794 	c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
7795 				     V_FW_PFVF_CMD_NIQ(rxq));
7796 	c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
7797 				    V_FW_PFVF_CMD_PMASK(pmask) |
7798 				    V_FW_PFVF_CMD_NEQ(txq));
7799 	c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
7800 				      V_FW_PFVF_CMD_NVI(vi) |
7801 				      V_FW_PFVF_CMD_NEXACTF(nexact));
7802 	c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
7803 				     V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
7804 				     V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
7805 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7806 }
7807 
7808 /**
7809  *	t4_alloc_vi_func - allocate a virtual interface
7810  *	@adap: the adapter
7811  *	@mbox: mailbox to use for the FW command
7812  *	@port: physical port associated with the VI
7813  *	@pf: the PF owning the VI
7814  *	@vf: the VF owning the VI
7815  *	@nmac: number of MAC addresses needed (1 to 5)
7816  *	@mac: the MAC addresses of the VI
7817  *	@rss_size: size of RSS table slice associated with this VI
7818  *	@portfunc: which Port Application Function MAC Address is desired
7819  *	@idstype: Intrusion Detection Type
7820  *
7821  *	Allocates a virtual interface for the given physical port.  If @mac is
7822  *	not %NULL it contains the MAC addresses of the VI as assigned by FW.
7823  *	If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
7824  *	@mac should be large enough to hold @nmac Ethernet addresses, they are
7825  *	stored consecutively so the space needed is @nmac * 6 bytes.
7826  *	Returns a negative error number or the non-negative VI id.
7827  */
7828 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
7829 		     unsigned int port, unsigned int pf, unsigned int vf,
7830 		     unsigned int nmac, u8 *mac, u16 *rss_size,
7831 		     uint8_t *vfvld, uint16_t *vin,
7832 		     unsigned int portfunc, unsigned int idstype)
7833 {
7834 	int ret;
7835 	struct fw_vi_cmd c;
7836 
7837 	memset(&c, 0, sizeof(c));
7838 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
7839 				  F_FW_CMD_WRITE | F_FW_CMD_EXEC |
7840 				  V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
7841 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
7842 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
7843 				     V_FW_VI_CMD_FUNC(portfunc));
7844 	c.portid_pkd = V_FW_VI_CMD_PORTID(port);
7845 	c.nmac = nmac - 1;
7846 	if(!rss_size)
7847 		c.norss_rsssize = F_FW_VI_CMD_NORSS;
7848 
7849 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7850 	if (ret)
7851 		return ret;
7852 	ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
7853 
7854 	if (mac) {
7855 		memcpy(mac, c.mac, sizeof(c.mac));
7856 		switch (nmac) {
7857 		case 5:
7858 			memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7859 		case 4:
7860 			memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7861 		case 3:
7862 			memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7863 		case 2:
7864 			memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7865 		}
7866 	}
7867 	if (rss_size)
7868 		*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
7869 	if (vfvld) {
7870 		*vfvld = adap->params.viid_smt_extn_support ?
7871 		    G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) :
7872 		    G_FW_VIID_VIVLD(ret);
7873 	}
7874 	if (vin) {
7875 		*vin = adap->params.viid_smt_extn_support ?
7876 		    G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) :
7877 		    G_FW_VIID_VIN(ret);
7878 	}
7879 
7880 	return ret;
7881 }
7882 
7883 /**
7884  *      t4_alloc_vi - allocate an [Ethernet Function] virtual interface
7885  *      @adap: the adapter
7886  *      @mbox: mailbox to use for the FW command
7887  *      @port: physical port associated with the VI
7888  *      @pf: the PF owning the VI
7889  *      @vf: the VF owning the VI
7890  *      @nmac: number of MAC addresses needed (1 to 5)
7891  *      @mac: the MAC addresses of the VI
7892  *      @rss_size: size of RSS table slice associated with this VI
7893  *
7894  *	backwards compatible and convieniance routine to allocate a Virtual
7895  *	Interface with a Ethernet Port Application Function and Intrustion
7896  *	Detection System disabled.
7897  */
7898 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7899 		unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7900 		u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
7901 {
7902 	return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
7903 				vfvld, vin, FW_VI_FUNC_ETH, 0);
7904 }
7905 
7906 /**
7907  * 	t4_free_vi - free a virtual interface
7908  * 	@adap: the adapter
7909  * 	@mbox: mailbox to use for the FW command
7910  * 	@pf: the PF owning the VI
7911  * 	@vf: the VF owning the VI
7912  * 	@viid: virtual interface identifiler
7913  *
7914  * 	Free a previously allocated virtual interface.
7915  */
7916 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7917 	       unsigned int vf, unsigned int viid)
7918 {
7919 	struct fw_vi_cmd c;
7920 
7921 	memset(&c, 0, sizeof(c));
7922 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
7923 				  F_FW_CMD_REQUEST |
7924 				  F_FW_CMD_EXEC |
7925 				  V_FW_VI_CMD_PFN(pf) |
7926 				  V_FW_VI_CMD_VFN(vf));
7927 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
7928 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
7929 
7930 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7931 }
7932 
7933 /**
7934  *	t4_set_rxmode - set Rx properties of a virtual interface
7935  *	@adap: the adapter
7936  *	@mbox: mailbox to use for the FW command
7937  *	@viid: the VI id
7938  *	@mtu: the new MTU or -1
7939  *	@promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7940  *	@all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7941  *	@bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7942  *	@vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7943  *	@sleep_ok: if true we may sleep while awaiting command completion
7944  *
7945  *	Sets Rx properties of a virtual interface.
7946  */
7947 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7948 		  int mtu, int promisc, int all_multi, int bcast, int vlanex,
7949 		  bool sleep_ok)
7950 {
7951 	struct fw_vi_rxmode_cmd c;
7952 
7953 	/* convert to FW values */
7954 	if (mtu < 0)
7955 		mtu = M_FW_VI_RXMODE_CMD_MTU;
7956 	if (promisc < 0)
7957 		promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
7958 	if (all_multi < 0)
7959 		all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
7960 	if (bcast < 0)
7961 		bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
7962 	if (vlanex < 0)
7963 		vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
7964 
7965 	memset(&c, 0, sizeof(c));
7966 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
7967 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7968 				   V_FW_VI_RXMODE_CMD_VIID(viid));
7969 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7970 	c.mtu_to_vlanexen =
7971 		cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
7972 			    V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
7973 			    V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
7974 			    V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
7975 			    V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
7976 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7977 }
7978 
7979 /**
7980  *	t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7981  *	@adap: the adapter
7982  *	@mbox: mailbox to use for the FW command
7983  *	@viid: the VI id
7984  *	@free: if true any existing filters for this VI id are first removed
7985  *	@naddr: the number of MAC addresses to allocate filters for (up to 7)
7986  *	@addr: the MAC address(es)
7987  *	@idx: where to store the index of each allocated filter
7988  *	@hash: pointer to hash address filter bitmap
7989  *	@sleep_ok: call is allowed to sleep
7990  *
7991  *	Allocates an exact-match filter for each of the supplied addresses and
7992  *	sets it to the corresponding address.  If @idx is not %NULL it should
7993  *	have at least @naddr entries, each of which will be set to the index of
7994  *	the filter allocated for the corresponding MAC address.  If a filter
7995  *	could not be allocated for an address its index is set to 0xffff.
7996  *	If @hash is not %NULL addresses that fail to allocate an exact filter
7997  *	are hashed and update the hash filter bitmap pointed at by @hash.
7998  *
7999  *	Returns a negative error number or the number of filters allocated.
8000  */
8001 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
8002 		      unsigned int viid, bool free, unsigned int naddr,
8003 		      const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
8004 {
8005 	int offset, ret = 0;
8006 	struct fw_vi_mac_cmd c;
8007 	unsigned int nfilters = 0;
8008 	unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8009 	unsigned int rem = naddr;
8010 
8011 	if (naddr > max_naddr)
8012 		return -EINVAL;
8013 
8014 	for (offset = 0; offset < naddr ; /**/) {
8015 		unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8016 					 ? rem
8017 					 : ARRAY_SIZE(c.u.exact));
8018 		size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8019 						     u.exact[fw_naddr]), 16);
8020 		struct fw_vi_mac_exact *p;
8021 		int i;
8022 
8023 		memset(&c, 0, sizeof(c));
8024 		c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8025 					   F_FW_CMD_REQUEST |
8026 					   F_FW_CMD_WRITE |
8027 					   V_FW_CMD_EXEC(free) |
8028 					   V_FW_VI_MAC_CMD_VIID(viid));
8029 		c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
8030 						  V_FW_CMD_LEN16(len16));
8031 
8032 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8033 			p->valid_to_idx =
8034 				cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8035 					    V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8036 			memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8037 		}
8038 
8039 		/*
8040 		 * It's okay if we run out of space in our MAC address arena.
8041 		 * Some of the addresses we submit may get stored so we need
8042 		 * to run through the reply to see what the results were ...
8043 		 */
8044 		ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8045 		if (ret && ret != -FW_ENOMEM)
8046 			break;
8047 
8048 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8049 			u16 index = G_FW_VI_MAC_CMD_IDX(
8050 						be16_to_cpu(p->valid_to_idx));
8051 
8052 			if (idx)
8053 				idx[offset+i] = (index >=  max_naddr
8054 						 ? 0xffff
8055 						 : index);
8056 			if (index < max_naddr)
8057 				nfilters++;
8058 			else if (hash)
8059 				*hash |= (1ULL << hash_mac_addr(addr[offset+i]));
8060 		}
8061 
8062 		free = false;
8063 		offset += fw_naddr;
8064 		rem -= fw_naddr;
8065 	}
8066 
8067 	if (ret == 0 || ret == -FW_ENOMEM)
8068 		ret = nfilters;
8069 	return ret;
8070 }
8071 
8072 /**
8073  *	t4_change_mac - modifies the exact-match filter for a MAC address
8074  *	@adap: the adapter
8075  *	@mbox: mailbox to use for the FW command
8076  *	@viid: the VI id
8077  *	@idx: index of existing filter for old value of MAC address, or -1
8078  *	@addr: the new MAC address value
8079  *	@persist: whether a new MAC allocation should be persistent
8080  *	@smt_idx: add MAC to SMT and return its index, or NULL
8081  *
8082  *	Modifies an exact-match filter and sets it to the new MAC address if
8083  *	@idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
8084  *	latter case the address is added persistently if @persist is %true.
8085  *
8086  *	Note that in general it is not possible to modify the value of a given
8087  *	filter so the generic way to modify an address filter is to free the one
8088  *	being used by the old address value and allocate a new filter for the
8089  *	new address value.
8090  *
8091  *	Returns a negative error number or the index of the filter with the new
8092  *	MAC value.  Note that this index may differ from @idx.
8093  */
8094 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8095 		  int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
8096 {
8097 	int ret, mode;
8098 	struct fw_vi_mac_cmd c;
8099 	struct fw_vi_mac_exact *p = c.u.exact;
8100 	unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
8101 
8102 	if (idx < 0)		/* new allocation */
8103 		idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8104 	mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8105 
8106 	memset(&c, 0, sizeof(c));
8107 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8108 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8109 				   V_FW_VI_MAC_CMD_VIID(viid));
8110 	c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
8111 	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8112 				      V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
8113 				      V_FW_VI_MAC_CMD_IDX(idx));
8114 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
8115 
8116 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8117 	if (ret == 0) {
8118 		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8119 		if (ret >= max_mac_addr)
8120 			ret = -ENOMEM;
8121 		if (smt_idx) {
8122 			if (adap->params.viid_smt_extn_support)
8123 				*smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
8124 			else {
8125 				if (chip_id(adap) <= CHELSIO_T5)
8126 					*smt_idx = (viid & M_FW_VIID_VIN) << 1;
8127 				else
8128 					*smt_idx = viid & M_FW_VIID_VIN;
8129 			}
8130 		}
8131 	}
8132 	return ret;
8133 }
8134 
8135 /**
8136  *	t4_set_addr_hash - program the MAC inexact-match hash filter
8137  *	@adap: the adapter
8138  *	@mbox: mailbox to use for the FW command
8139  *	@viid: the VI id
8140  *	@ucast: whether the hash filter should also match unicast addresses
8141  *	@vec: the value to be written to the hash filter
8142  *	@sleep_ok: call is allowed to sleep
8143  *
8144  *	Sets the 64-bit inexact-match hash filter for a virtual interface.
8145  */
8146 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8147 		     bool ucast, u64 vec, bool sleep_ok)
8148 {
8149 	struct fw_vi_mac_cmd c;
8150 	u32 val;
8151 
8152 	memset(&c, 0, sizeof(c));
8153 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8154 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8155 				   V_FW_VI_ENABLE_CMD_VIID(viid));
8156 	val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
8157 	      V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
8158 	c.freemacs_to_len16 = cpu_to_be32(val);
8159 	c.u.hash.hashvec = cpu_to_be64(vec);
8160 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8161 }
8162 
8163 /**
8164  *      t4_enable_vi_params - enable/disable a virtual interface
8165  *      @adap: the adapter
8166  *      @mbox: mailbox to use for the FW command
8167  *      @viid: the VI id
8168  *      @rx_en: 1=enable Rx, 0=disable Rx
8169  *      @tx_en: 1=enable Tx, 0=disable Tx
8170  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8171  *
8172  *      Enables/disables a virtual interface.  Note that setting DCB Enable
8173  *      only makes sense when enabling a Virtual Interface ...
8174  */
8175 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8176 			unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8177 {
8178 	struct fw_vi_enable_cmd c;
8179 
8180 	memset(&c, 0, sizeof(c));
8181 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8182 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8183 				   V_FW_VI_ENABLE_CMD_VIID(viid));
8184 	c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
8185 				     V_FW_VI_ENABLE_CMD_EEN(tx_en) |
8186 				     V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
8187 				     FW_LEN16(c));
8188 	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8189 }
8190 
8191 /**
8192  *	t4_enable_vi - enable/disable a virtual interface
8193  *	@adap: the adapter
8194  *	@mbox: mailbox to use for the FW command
8195  *	@viid: the VI id
8196  *	@rx_en: 1=enable Rx, 0=disable Rx
8197  *	@tx_en: 1=enable Tx, 0=disable Tx
8198  *
8199  *	Enables/disables a virtual interface.  Note that setting DCB Enable
8200  *	only makes sense when enabling a Virtual Interface ...
8201  */
8202 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8203 		 bool rx_en, bool tx_en)
8204 {
8205 	return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8206 }
8207 
8208 /**
8209  *	t4_identify_port - identify a VI's port by blinking its LED
8210  *	@adap: the adapter
8211  *	@mbox: mailbox to use for the FW command
8212  *	@viid: the VI id
8213  *	@nblinks: how many times to blink LED at 2.5 Hz
8214  *
8215  *	Identifies a VI's port by blinking its LED.
8216  */
8217 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8218 		     unsigned int nblinks)
8219 {
8220 	struct fw_vi_enable_cmd c;
8221 
8222 	memset(&c, 0, sizeof(c));
8223 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8224 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8225 				   V_FW_VI_ENABLE_CMD_VIID(viid));
8226 	c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
8227 	c.blinkdur = cpu_to_be16(nblinks);
8228 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8229 }
8230 
8231 /**
8232  *	t4_iq_stop - stop an ingress queue and its FLs
8233  *	@adap: the adapter
8234  *	@mbox: mailbox to use for the FW command
8235  *	@pf: the PF owning the queues
8236  *	@vf: the VF owning the queues
8237  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8238  *	@iqid: ingress queue id
8239  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
8240  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
8241  *
8242  *	Stops an ingress queue and its associated FLs, if any.  This causes
8243  *	any current or future data/messages destined for these queues to be
8244  *	tossed.
8245  */
8246 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8247 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
8248 	       unsigned int fl0id, unsigned int fl1id)
8249 {
8250 	struct fw_iq_cmd c;
8251 
8252 	memset(&c, 0, sizeof(c));
8253 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8254 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8255 				  V_FW_IQ_CMD_VFN(vf));
8256 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
8257 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8258 	c.iqid = cpu_to_be16(iqid);
8259 	c.fl0id = cpu_to_be16(fl0id);
8260 	c.fl1id = cpu_to_be16(fl1id);
8261 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8262 }
8263 
8264 /**
8265  *	t4_iq_free - free an ingress queue and its FLs
8266  *	@adap: the adapter
8267  *	@mbox: mailbox to use for the FW command
8268  *	@pf: the PF owning the queues
8269  *	@vf: the VF owning the queues
8270  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8271  *	@iqid: ingress queue id
8272  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
8273  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
8274  *
8275  *	Frees an ingress queue and its associated FLs, if any.
8276  */
8277 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8278 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
8279 	       unsigned int fl0id, unsigned int fl1id)
8280 {
8281 	struct fw_iq_cmd c;
8282 
8283 	memset(&c, 0, sizeof(c));
8284 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8285 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8286 				  V_FW_IQ_CMD_VFN(vf));
8287 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
8288 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8289 	c.iqid = cpu_to_be16(iqid);
8290 	c.fl0id = cpu_to_be16(fl0id);
8291 	c.fl1id = cpu_to_be16(fl1id);
8292 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8293 }
8294 
8295 /**
8296  *	t4_eth_eq_free - free an Ethernet egress queue
8297  *	@adap: the adapter
8298  *	@mbox: mailbox to use for the FW command
8299  *	@pf: the PF owning the queue
8300  *	@vf: the VF owning the queue
8301  *	@eqid: egress queue id
8302  *
8303  *	Frees an Ethernet egress queue.
8304  */
8305 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8306 		   unsigned int vf, unsigned int eqid)
8307 {
8308 	struct fw_eq_eth_cmd c;
8309 
8310 	memset(&c, 0, sizeof(c));
8311 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8312 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8313 				  V_FW_EQ_ETH_CMD_PFN(pf) |
8314 				  V_FW_EQ_ETH_CMD_VFN(vf));
8315 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
8316 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8317 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8318 }
8319 
8320 /**
8321  *	t4_ctrl_eq_free - free a control egress queue
8322  *	@adap: the adapter
8323  *	@mbox: mailbox to use for the FW command
8324  *	@pf: the PF owning the queue
8325  *	@vf: the VF owning the queue
8326  *	@eqid: egress queue id
8327  *
8328  *	Frees a control egress queue.
8329  */
8330 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8331 		    unsigned int vf, unsigned int eqid)
8332 {
8333 	struct fw_eq_ctrl_cmd c;
8334 
8335 	memset(&c, 0, sizeof(c));
8336 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
8337 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8338 				  V_FW_EQ_CTRL_CMD_PFN(pf) |
8339 				  V_FW_EQ_CTRL_CMD_VFN(vf));
8340 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
8341 	c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
8342 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8343 }
8344 
8345 /**
8346  *	t4_ofld_eq_free - free an offload egress queue
8347  *	@adap: the adapter
8348  *	@mbox: mailbox to use for the FW command
8349  *	@pf: the PF owning the queue
8350  *	@vf: the VF owning the queue
8351  *	@eqid: egress queue id
8352  *
8353  *	Frees a control egress queue.
8354  */
8355 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8356 		    unsigned int vf, unsigned int eqid)
8357 {
8358 	struct fw_eq_ofld_cmd c;
8359 
8360 	memset(&c, 0, sizeof(c));
8361 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
8362 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8363 				  V_FW_EQ_OFLD_CMD_PFN(pf) |
8364 				  V_FW_EQ_OFLD_CMD_VFN(vf));
8365 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
8366 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
8367 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8368 }
8369 
8370 /**
8371  *	t4_link_down_rc_str - return a string for a Link Down Reason Code
8372  *	@link_down_rc: Link Down Reason Code
8373  *
8374  *	Returns a string representation of the Link Down Reason Code.
8375  */
8376 const char *t4_link_down_rc_str(unsigned char link_down_rc)
8377 {
8378 	static const char *reason[] = {
8379 		"Link Down",
8380 		"Remote Fault",
8381 		"Auto-negotiation Failure",
8382 		"Reserved3",
8383 		"Insufficient Airflow",
8384 		"Unable To Determine Reason",
8385 		"No RX Signal Detected",
8386 		"Reserved7",
8387 	};
8388 
8389 	if (link_down_rc >= ARRAY_SIZE(reason))
8390 		return "Bad Reason Code";
8391 
8392 	return reason[link_down_rc];
8393 }
8394 
8395 /*
8396  * Return the highest speed set in the port capabilities, in Mb/s.
8397  */
8398 unsigned int fwcap_to_speed(uint32_t caps)
8399 {
8400 	#define TEST_SPEED_RETURN(__caps_speed, __speed) \
8401 		do { \
8402 			if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8403 				return __speed; \
8404 		} while (0)
8405 
8406 	TEST_SPEED_RETURN(400G, 400000);
8407 	TEST_SPEED_RETURN(200G, 200000);
8408 	TEST_SPEED_RETURN(100G, 100000);
8409 	TEST_SPEED_RETURN(50G,   50000);
8410 	TEST_SPEED_RETURN(40G,   40000);
8411 	TEST_SPEED_RETURN(25G,   25000);
8412 	TEST_SPEED_RETURN(10G,   10000);
8413 	TEST_SPEED_RETURN(1G,     1000);
8414 	TEST_SPEED_RETURN(100M,    100);
8415 
8416 	#undef TEST_SPEED_RETURN
8417 
8418 	return 0;
8419 }
8420 
8421 /*
8422  * Return the port capabilities bit for the given speed, which is in Mb/s.
8423  */
8424 uint32_t speed_to_fwcap(unsigned int speed)
8425 {
8426 	#define TEST_SPEED_RETURN(__caps_speed, __speed) \
8427 		do { \
8428 			if (speed == __speed) \
8429 				return FW_PORT_CAP32_SPEED_##__caps_speed; \
8430 		} while (0)
8431 
8432 	TEST_SPEED_RETURN(400G, 400000);
8433 	TEST_SPEED_RETURN(200G, 200000);
8434 	TEST_SPEED_RETURN(100G, 100000);
8435 	TEST_SPEED_RETURN(50G,   50000);
8436 	TEST_SPEED_RETURN(40G,   40000);
8437 	TEST_SPEED_RETURN(25G,   25000);
8438 	TEST_SPEED_RETURN(10G,   10000);
8439 	TEST_SPEED_RETURN(1G,     1000);
8440 	TEST_SPEED_RETURN(100M,    100);
8441 
8442 	#undef TEST_SPEED_RETURN
8443 
8444 	return 0;
8445 }
8446 
8447 /*
8448  * Return the port capabilities bit for the highest speed in the capabilities.
8449  */
8450 uint32_t fwcap_top_speed(uint32_t caps)
8451 {
8452 	#define TEST_SPEED_RETURN(__caps_speed) \
8453 		do { \
8454 			if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8455 				return FW_PORT_CAP32_SPEED_##__caps_speed; \
8456 		} while (0)
8457 
8458 	TEST_SPEED_RETURN(400G);
8459 	TEST_SPEED_RETURN(200G);
8460 	TEST_SPEED_RETURN(100G);
8461 	TEST_SPEED_RETURN(50G);
8462 	TEST_SPEED_RETURN(40G);
8463 	TEST_SPEED_RETURN(25G);
8464 	TEST_SPEED_RETURN(10G);
8465 	TEST_SPEED_RETURN(1G);
8466 	TEST_SPEED_RETURN(100M);
8467 
8468 	#undef TEST_SPEED_RETURN
8469 
8470 	return 0;
8471 }
8472 
8473 
8474 /**
8475  *	lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8476  *	@lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8477  *
8478  *	Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8479  *	32-bit Port Capabilities value.
8480  */
8481 static uint32_t lstatus_to_fwcap(u32 lstatus)
8482 {
8483 	uint32_t linkattr = 0;
8484 
8485 	/*
8486 	 * Unfortunately the format of the Link Status in the old
8487 	 * 16-bit Port Information message isn't the same as the
8488 	 * 16-bit Port Capabilities bitfield used everywhere else ...
8489 	 */
8490 	if (lstatus & F_FW_PORT_CMD_RXPAUSE)
8491 		linkattr |= FW_PORT_CAP32_FC_RX;
8492 	if (lstatus & F_FW_PORT_CMD_TXPAUSE)
8493 		linkattr |= FW_PORT_CAP32_FC_TX;
8494 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
8495 		linkattr |= FW_PORT_CAP32_SPEED_100M;
8496 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
8497 		linkattr |= FW_PORT_CAP32_SPEED_1G;
8498 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
8499 		linkattr |= FW_PORT_CAP32_SPEED_10G;
8500 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
8501 		linkattr |= FW_PORT_CAP32_SPEED_25G;
8502 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
8503 		linkattr |= FW_PORT_CAP32_SPEED_40G;
8504 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
8505 		linkattr |= FW_PORT_CAP32_SPEED_100G;
8506 
8507 	return linkattr;
8508 }
8509 
8510 /*
8511  * Updates all fields owned by the common code in port_info and link_config
8512  * based on information provided by the firmware.  Does not touch any
8513  * requested_* field.
8514  */
8515 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
8516     enum fw_port_action action, bool *mod_changed, bool *link_changed)
8517 {
8518 	struct link_config old_lc, *lc = &pi->link_cfg;
8519 	unsigned char fc, fec;
8520 	u32 stat, linkattr;
8521 	int old_ptype, old_mtype;
8522 
8523 	old_ptype = pi->port_type;
8524 	old_mtype = pi->mod_type;
8525 	old_lc = *lc;
8526 	if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8527 		stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
8528 
8529 		pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
8530 		pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
8531 		pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
8532 		    G_FW_PORT_CMD_MDIOADDR(stat) : -1;
8533 
8534 		lc->supported = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap));
8535 		lc->advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap));
8536 		lc->lp_advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap));
8537 		lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
8538 		lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
8539 
8540 		linkattr = lstatus_to_fwcap(stat);
8541 	} else if (action == FW_PORT_ACTION_GET_PORT_INFO32) {
8542 		stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32);
8543 
8544 		pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat);
8545 		pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat);
8546 		pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ?
8547 		    G_FW_PORT_CMD_MDIOADDR32(stat) : -1;
8548 
8549 		lc->supported = be32_to_cpu(p->u.info32.pcaps32);
8550 		lc->advertising = be32_to_cpu(p->u.info32.acaps32);
8551 		lc->lp_advertising = be16_to_cpu(p->u.info32.lpacaps32);
8552 		lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0;
8553 		lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat);
8554 
8555 		linkattr = be32_to_cpu(p->u.info32.linkattr32);
8556 	} else {
8557 		CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action);
8558 		return;
8559 	}
8560 
8561 	lc->speed = fwcap_to_speed(linkattr);
8562 
8563 	fc = 0;
8564 	if (linkattr & FW_PORT_CAP32_FC_RX)
8565 		fc |= PAUSE_RX;
8566 	if (linkattr & FW_PORT_CAP32_FC_TX)
8567 		fc |= PAUSE_TX;
8568 	lc->fc = fc;
8569 
8570 	fec = FEC_NONE;
8571 	if (linkattr & FW_PORT_CAP32_FEC_RS)
8572 		fec |= FEC_RS;
8573 	if (linkattr & FW_PORT_CAP32_FEC_BASER_RS)
8574 		fec |= FEC_BASER_RS;
8575 	lc->fec = fec;
8576 
8577 	if (mod_changed != NULL)
8578 		*mod_changed = false;
8579 	if (link_changed != NULL)
8580 		*link_changed = false;
8581 	if (old_ptype != pi->port_type || old_mtype != pi->mod_type ||
8582 	    old_lc.supported != lc->supported) {
8583 		if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) {
8584 			lc->fec_hint = lc->advertising &
8585 			    V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC);
8586 		}
8587 		if (mod_changed != NULL)
8588 			*mod_changed = true;
8589 	}
8590 	if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed ||
8591 	    old_lc.fec != lc->fec || old_lc.fc != lc->fc) {
8592 		if (link_changed != NULL)
8593 			*link_changed = true;
8594 	}
8595 }
8596 
8597 /**
8598  *	t4_update_port_info - retrieve and update port information if changed
8599  *	@pi: the port_info
8600  *
8601  *	We issue a Get Port Information Command to the Firmware and, if
8602  *	successful, we check to see if anything is different from what we
8603  *	last recorded and update things accordingly.
8604  */
8605  int t4_update_port_info(struct port_info *pi)
8606  {
8607 	struct adapter *sc = pi->adapter;
8608 	struct fw_port_cmd cmd;
8609 	enum fw_port_action action;
8610 	int ret;
8611 
8612 	memset(&cmd, 0, sizeof(cmd));
8613 	cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
8614 	    F_FW_CMD_REQUEST | F_FW_CMD_READ |
8615 	    V_FW_PORT_CMD_PORTID(pi->tx_chan));
8616 	action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
8617 	    FW_PORT_ACTION_GET_PORT_INFO;
8618 	cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
8619 	    FW_LEN16(cmd));
8620 	ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
8621 	if (ret)
8622 		return ret;
8623 
8624 	handle_port_info(pi, &cmd, action, NULL, NULL);
8625 	return 0;
8626 }
8627 
8628 /**
8629  *	t4_handle_fw_rpl - process a FW reply message
8630  *	@adap: the adapter
8631  *	@rpl: start of the FW message
8632  *
8633  *	Processes a FW message, such as link state change messages.
8634  */
8635 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8636 {
8637 	u8 opcode = *(const u8 *)rpl;
8638 	const struct fw_port_cmd *p = (const void *)rpl;
8639 	enum fw_port_action action =
8640 	    G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
8641 	bool mod_changed, link_changed;
8642 
8643 	if (opcode == FW_PORT_CMD &&
8644 	    (action == FW_PORT_ACTION_GET_PORT_INFO ||
8645 	    action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8646 		/* link/module state change message */
8647 		int i;
8648 		int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
8649 		struct port_info *pi = NULL;
8650 		struct link_config *lc;
8651 
8652 		for_each_port(adap, i) {
8653 			pi = adap2pinfo(adap, i);
8654 			if (pi->tx_chan == chan)
8655 				break;
8656 		}
8657 
8658 		lc = &pi->link_cfg;
8659 		PORT_LOCK(pi);
8660 		handle_port_info(pi, p, action, &mod_changed, &link_changed);
8661 		PORT_UNLOCK(pi);
8662 		if (mod_changed)
8663 			t4_os_portmod_changed(pi);
8664 		if (link_changed) {
8665 			PORT_LOCK(pi);
8666 			t4_os_link_changed(pi);
8667 			PORT_UNLOCK(pi);
8668 		}
8669 	} else {
8670 		CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
8671 		return -EINVAL;
8672 	}
8673 	return 0;
8674 }
8675 
8676 /**
8677  *	get_pci_mode - determine a card's PCI mode
8678  *	@adapter: the adapter
8679  *	@p: where to store the PCI settings
8680  *
8681  *	Determines a card's PCI mode and associated parameters, such as speed
8682  *	and width.
8683  */
8684 static void get_pci_mode(struct adapter *adapter,
8685 				   struct pci_params *p)
8686 {
8687 	u16 val;
8688 	u32 pcie_cap;
8689 
8690 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
8691 	if (pcie_cap) {
8692 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
8693 		p->speed = val & PCI_EXP_LNKSTA_CLS;
8694 		p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8695 	}
8696 }
8697 
8698 struct flash_desc {
8699 	u32 vendor_and_model_id;
8700 	u32 size_mb;
8701 };
8702 
8703 int t4_get_flash_params(struct adapter *adapter)
8704 {
8705 	/*
8706 	 * Table for non-standard supported Flash parts.  Note, all Flash
8707 	 * parts must have 64KB sectors.
8708 	 */
8709 	static struct flash_desc supported_flash[] = {
8710 		{ 0x00150201, 4 << 20 },	/* Spansion 4MB S25FL032P */
8711 	};
8712 
8713 	int ret;
8714 	u32 flashid = 0;
8715 	unsigned int part, manufacturer;
8716 	unsigned int density, size = 0;
8717 
8718 
8719 	/*
8720 	 * Issue a Read ID Command to the Flash part.  We decode supported
8721 	 * Flash parts and their sizes from this.  There's a newer Query
8722 	 * Command which can retrieve detailed geometry information but many
8723 	 * Flash parts don't support it.
8724 	 */
8725 	ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
8726 	if (!ret)
8727 		ret = sf1_read(adapter, 3, 0, 1, &flashid);
8728 	t4_write_reg(adapter, A_SF_OP, 0);	/* unlock SF */
8729 	if (ret < 0)
8730 		return ret;
8731 
8732 	/*
8733 	 * Check to see if it's one of our non-standard supported Flash parts.
8734 	 */
8735 	for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8736 		if (supported_flash[part].vendor_and_model_id == flashid) {
8737 			adapter->params.sf_size =
8738 				supported_flash[part].size_mb;
8739 			adapter->params.sf_nsec =
8740 				adapter->params.sf_size / SF_SEC_SIZE;
8741 			goto found;
8742 		}
8743 
8744 	/*
8745 	 * Decode Flash part size.  The code below looks repetative with
8746 	 * common encodings, but that's not guaranteed in the JEDEC
8747 	 * specification for the Read JADEC ID command.  The only thing that
8748 	 * we're guaranteed by the JADEC specification is where the
8749 	 * Manufacturer ID is in the returned result.  After that each
8750 	 * Manufacturer ~could~ encode things completely differently.
8751 	 * Note, all Flash parts must have 64KB sectors.
8752 	 */
8753 	manufacturer = flashid & 0xff;
8754 	switch (manufacturer) {
8755 	case 0x20: /* Micron/Numonix */
8756 		/*
8757 		 * This Density -> Size decoding table is taken from Micron
8758 		 * Data Sheets.
8759 		 */
8760 		density = (flashid >> 16) & 0xff;
8761 		switch (density) {
8762 		case 0x14: size = 1 << 20; break; /*   1MB */
8763 		case 0x15: size = 1 << 21; break; /*   2MB */
8764 		case 0x16: size = 1 << 22; break; /*   4MB */
8765 		case 0x17: size = 1 << 23; break; /*   8MB */
8766 		case 0x18: size = 1 << 24; break; /*  16MB */
8767 		case 0x19: size = 1 << 25; break; /*  32MB */
8768 		case 0x20: size = 1 << 26; break; /*  64MB */
8769 		case 0x21: size = 1 << 27; break; /* 128MB */
8770 		case 0x22: size = 1 << 28; break; /* 256MB */
8771 		}
8772 		break;
8773 
8774 	case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */
8775 		/*
8776 		 * This Density -> Size decoding table is taken from ISSI
8777 		 * Data Sheets.
8778 		 */
8779 		density = (flashid >> 16) & 0xff;
8780 		switch (density) {
8781 		case 0x16: size = 1 << 25; break; /*  32MB */
8782 		case 0x17: size = 1 << 26; break; /*  64MB */
8783 		}
8784 		break;
8785 
8786 	case 0xc2: /* Macronix */
8787 		/*
8788 		 * This Density -> Size decoding table is taken from Macronix
8789 		 * Data Sheets.
8790 		 */
8791 		density = (flashid >> 16) & 0xff;
8792 		switch (density) {
8793 		case 0x17: size = 1 << 23; break; /*   8MB */
8794 		case 0x18: size = 1 << 24; break; /*  16MB */
8795 		}
8796 		break;
8797 
8798 	case 0xef: /* Winbond */
8799 		/*
8800 		 * This Density -> Size decoding table is taken from Winbond
8801 		 * Data Sheets.
8802 		 */
8803 		density = (flashid >> 16) & 0xff;
8804 		switch (density) {
8805 		case 0x17: size = 1 << 23; break; /*   8MB */
8806 		case 0x18: size = 1 << 24; break; /*  16MB */
8807 		}
8808 		break;
8809 	}
8810 
8811 	/* If we didn't recognize the FLASH part, that's no real issue: the
8812 	 * Hardware/Software contract says that Hardware will _*ALWAYS*_
8813 	 * use a FLASH part which is at least 4MB in size and has 64KB
8814 	 * sectors.  The unrecognized FLASH part is likely to be much larger
8815 	 * than 4MB, but that's all we really need.
8816 	 */
8817 	if (size == 0) {
8818 		CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid);
8819 		size = 1 << 22;
8820 	}
8821 
8822 	/*
8823 	 * Store decoded Flash size and fall through into vetting code.
8824 	 */
8825 	adapter->params.sf_size = size;
8826 	adapter->params.sf_nsec = size / SF_SEC_SIZE;
8827 
8828  found:
8829 	/*
8830 	 * We should ~probably~ reject adapters with FLASHes which are too
8831 	 * small but we have some legacy FPGAs with small FLASHes that we'd
8832 	 * still like to use.  So instead we emit a scary message ...
8833 	 */
8834 	if (adapter->params.sf_size < FLASH_MIN_SIZE)
8835 		CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
8836 			flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
8837 
8838 	return 0;
8839 }
8840 
8841 static void set_pcie_completion_timeout(struct adapter *adapter,
8842 						  u8 range)
8843 {
8844 	u16 val;
8845 	u32 pcie_cap;
8846 
8847 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
8848 	if (pcie_cap) {
8849 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
8850 		val &= 0xfff0;
8851 		val |= range ;
8852 		t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
8853 	}
8854 }
8855 
8856 const struct chip_params *t4_get_chip_params(int chipid)
8857 {
8858 	static const struct chip_params chip_params[] = {
8859 		{
8860 			/* T4 */
8861 			.nchan = NCHAN,
8862 			.pm_stats_cnt = PM_NSTATS,
8863 			.cng_ch_bits_log = 2,
8864 			.nsched_cls = 15,
8865 			.cim_num_obq = CIM_NUM_OBQ,
8866 			.mps_rplc_size = 128,
8867 			.vfcount = 128,
8868 			.sge_fl_db = F_DBPRIO,
8869 			.mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
8870 		},
8871 		{
8872 			/* T5 */
8873 			.nchan = NCHAN,
8874 			.pm_stats_cnt = PM_NSTATS,
8875 			.cng_ch_bits_log = 2,
8876 			.nsched_cls = 16,
8877 			.cim_num_obq = CIM_NUM_OBQ_T5,
8878 			.mps_rplc_size = 128,
8879 			.vfcount = 128,
8880 			.sge_fl_db = F_DBPRIO | F_DBTYPE,
8881 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
8882 		},
8883 		{
8884 			/* T6 */
8885 			.nchan = T6_NCHAN,
8886 			.pm_stats_cnt = T6_PM_NSTATS,
8887 			.cng_ch_bits_log = 3,
8888 			.nsched_cls = 16,
8889 			.cim_num_obq = CIM_NUM_OBQ_T5,
8890 			.mps_rplc_size = 256,
8891 			.vfcount = 256,
8892 			.sge_fl_db = 0,
8893 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
8894 		},
8895 	};
8896 
8897 	chipid -= CHELSIO_T4;
8898 	if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
8899 		return NULL;
8900 
8901 	return &chip_params[chipid];
8902 }
8903 
8904 /**
8905  *	t4_prep_adapter - prepare SW and HW for operation
8906  *	@adapter: the adapter
8907  *	@buf: temporary space of at least VPD_LEN size provided by the caller.
8908  *
8909  *	Initialize adapter SW state for the various HW modules, set initial
8910  *	values for some adapter tunables, take PHYs out of reset, and
8911  *	initialize the MDIO interface.
8912  */
8913 int t4_prep_adapter(struct adapter *adapter, u32 *buf)
8914 {
8915 	int ret;
8916 	uint16_t device_id;
8917 	uint32_t pl_rev;
8918 
8919 	get_pci_mode(adapter, &adapter->params.pci);
8920 
8921 	pl_rev = t4_read_reg(adapter, A_PL_REV);
8922 	adapter->params.chipid = G_CHIPID(pl_rev);
8923 	adapter->params.rev = G_REV(pl_rev);
8924 	if (adapter->params.chipid == 0) {
8925 		/* T4 did not have chipid in PL_REV (T5 onwards do) */
8926 		adapter->params.chipid = CHELSIO_T4;
8927 
8928 		/* T4A1 chip is not supported */
8929 		if (adapter->params.rev == 1) {
8930 			CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
8931 			return -EINVAL;
8932 		}
8933 	}
8934 
8935 	adapter->chip_params = t4_get_chip_params(chip_id(adapter));
8936 	if (adapter->chip_params == NULL)
8937 		return -EINVAL;
8938 
8939 	adapter->params.pci.vpd_cap_addr =
8940 	    t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
8941 
8942 	ret = t4_get_flash_params(adapter);
8943 	if (ret < 0)
8944 		return ret;
8945 
8946 	/* Cards with real ASICs have the chipid in the PCIe device id */
8947 	t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
8948 	if (device_id >> 12 == chip_id(adapter))
8949 		adapter->params.cim_la_size = CIMLA_SIZE;
8950 	else {
8951 		/* FPGA */
8952 		adapter->params.fpga = 1;
8953 		adapter->params.cim_la_size = 2 * CIMLA_SIZE;
8954 	}
8955 
8956 	ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf);
8957 	if (ret < 0)
8958 		return ret;
8959 
8960 	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8961 
8962 	/*
8963 	 * Default port and clock for debugging in case we can't reach FW.
8964 	 */
8965 	adapter->params.nports = 1;
8966 	adapter->params.portvec = 1;
8967 	adapter->params.vpd.cclk = 50000;
8968 
8969 	/* Set pci completion timeout value to 4 seconds. */
8970 	set_pcie_completion_timeout(adapter, 0xd);
8971 	return 0;
8972 }
8973 
8974 /**
8975  *	t4_shutdown_adapter - shut down adapter, host & wire
8976  *	@adapter: the adapter
8977  *
8978  *	Perform an emergency shutdown of the adapter and stop it from
8979  *	continuing any further communication on the ports or DMA to the
8980  *	host.  This is typically used when the adapter and/or firmware
8981  *	have crashed and we want to prevent any further accidental
8982  *	communication with the rest of the world.  This will also force
8983  *	the port Link Status to go down -- if register writes work --
8984  *	which should help our peers figure out that we're down.
8985  */
8986 int t4_shutdown_adapter(struct adapter *adapter)
8987 {
8988 	int port;
8989 
8990 	t4_intr_disable(adapter);
8991 	t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
8992 	for_each_port(adapter, port) {
8993 		u32 a_port_cfg = is_t4(adapter) ?
8994 				 PORT_REG(port, A_XGMAC_PORT_CFG) :
8995 				 T5_PORT_REG(port, A_MAC_PORT_CFG);
8996 
8997 		t4_write_reg(adapter, a_port_cfg,
8998 			     t4_read_reg(adapter, a_port_cfg)
8999 			     & ~V_SIGNAL_DET(1));
9000 	}
9001 	t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
9002 
9003 	return 0;
9004 }
9005 
9006 /**
9007  *	t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9008  *	@adapter: the adapter
9009  *	@qid: the Queue ID
9010  *	@qtype: the Ingress or Egress type for @qid
9011  *	@user: true if this request is for a user mode queue
9012  *	@pbar2_qoffset: BAR2 Queue Offset
9013  *	@pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9014  *
9015  *	Returns the BAR2 SGE Queue Registers information associated with the
9016  *	indicated Absolute Queue ID.  These are passed back in return value
9017  *	pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9018  *	and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9019  *
9020  *	This may return an error which indicates that BAR2 SGE Queue
9021  *	registers aren't available.  If an error is not returned, then the
9022  *	following values are returned:
9023  *
9024  *	  *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9025  *	  *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9026  *
9027  *	If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9028  *	require the "Inferred Queue ID" ability may be used.  E.g. the
9029  *	Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9030  *	then these "Inferred Queue ID" register may not be used.
9031  */
9032 int t4_bar2_sge_qregs(struct adapter *adapter,
9033 		      unsigned int qid,
9034 		      enum t4_bar2_qtype qtype,
9035 		      int user,
9036 		      u64 *pbar2_qoffset,
9037 		      unsigned int *pbar2_qid)
9038 {
9039 	unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9040 	u64 bar2_page_offset, bar2_qoffset;
9041 	unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9042 
9043 	/* T4 doesn't support BAR2 SGE Queue registers for kernel
9044 	 * mode queues.
9045 	 */
9046 	if (!user && is_t4(adapter))
9047 		return -EINVAL;
9048 
9049 	/* Get our SGE Page Size parameters.
9050 	 */
9051 	page_shift = adapter->params.sge.page_shift;
9052 	page_size = 1 << page_shift;
9053 
9054 	/* Get the right Queues per Page parameters for our Queue.
9055 	 */
9056 	qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9057 		     ? adapter->params.sge.eq_s_qpp
9058 		     : adapter->params.sge.iq_s_qpp);
9059 	qpp_mask = (1 << qpp_shift) - 1;
9060 
9061 	/* Calculate the basics of the BAR2 SGE Queue register area:
9062 	 *  o The BAR2 page the Queue registers will be in.
9063 	 *  o The BAR2 Queue ID.
9064 	 *  o The BAR2 Queue ID Offset into the BAR2 page.
9065 	 */
9066 	bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9067 	bar2_qid = qid & qpp_mask;
9068 	bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9069 
9070 	/* If the BAR2 Queue ID Offset is less than the Page Size, then the
9071 	 * hardware will infer the Absolute Queue ID simply from the writes to
9072 	 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9073 	 * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
9074 	 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9075 	 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9076 	 * from the BAR2 Page and BAR2 Queue ID.
9077 	 *
9078 	 * One important censequence of this is that some BAR2 SGE registers
9079 	 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9080 	 * there.  But other registers synthesize the SGE Queue ID purely
9081 	 * from the writes to the registers -- the Write Combined Doorbell
9082 	 * Buffer is a good example.  These BAR2 SGE Registers are only
9083 	 * available for those BAR2 SGE Register areas where the SGE Absolute
9084 	 * Queue ID can be inferred from simple writes.
9085 	 */
9086 	bar2_qoffset = bar2_page_offset;
9087 	bar2_qinferred = (bar2_qid_offset < page_size);
9088 	if (bar2_qinferred) {
9089 		bar2_qoffset += bar2_qid_offset;
9090 		bar2_qid = 0;
9091 	}
9092 
9093 	*pbar2_qoffset = bar2_qoffset;
9094 	*pbar2_qid = bar2_qid;
9095 	return 0;
9096 }
9097 
9098 /**
9099  *	t4_init_devlog_params - initialize adapter->params.devlog
9100  *	@adap: the adapter
9101  *	@fw_attach: whether we can talk to the firmware
9102  *
9103  *	Initialize various fields of the adapter's Firmware Device Log
9104  *	Parameters structure.
9105  */
9106 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
9107 {
9108 	struct devlog_params *dparams = &adap->params.devlog;
9109 	u32 pf_dparams;
9110 	unsigned int devlog_meminfo;
9111 	struct fw_devlog_cmd devlog_cmd;
9112 	int ret;
9113 
9114 	/* If we're dealing with newer firmware, the Device Log Paramerters
9115 	 * are stored in a designated register which allows us to access the
9116 	 * Device Log even if we can't talk to the firmware.
9117 	 */
9118 	pf_dparams =
9119 		t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
9120 	if (pf_dparams) {
9121 		unsigned int nentries, nentries128;
9122 
9123 		dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
9124 		dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
9125 
9126 		nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
9127 		nentries = (nentries128 + 1) * 128;
9128 		dparams->size = nentries * sizeof(struct fw_devlog_e);
9129 
9130 		return 0;
9131 	}
9132 
9133 	/*
9134 	 * For any failing returns ...
9135 	 */
9136 	memset(dparams, 0, sizeof *dparams);
9137 
9138 	/*
9139 	 * If we can't talk to the firmware, there's really nothing we can do
9140 	 * at this point.
9141 	 */
9142 	if (!fw_attach)
9143 		return -ENXIO;
9144 
9145 	/* Otherwise, ask the firmware for it's Device Log Parameters.
9146 	 */
9147 	memset(&devlog_cmd, 0, sizeof devlog_cmd);
9148 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9149 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
9150 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9151 	ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9152 			 &devlog_cmd);
9153 	if (ret)
9154 		return ret;
9155 
9156 	devlog_meminfo =
9157 		be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9158 	dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
9159 	dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
9160 	dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9161 
9162 	return 0;
9163 }
9164 
9165 /**
9166  *	t4_init_sge_params - initialize adap->params.sge
9167  *	@adapter: the adapter
9168  *
9169  *	Initialize various fields of the adapter's SGE Parameters structure.
9170  */
9171 int t4_init_sge_params(struct adapter *adapter)
9172 {
9173 	u32 r;
9174 	struct sge_params *sp = &adapter->params.sge;
9175 	unsigned i, tscale = 1;
9176 
9177 	r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
9178 	sp->counter_val[0] = G_THRESHOLD_0(r);
9179 	sp->counter_val[1] = G_THRESHOLD_1(r);
9180 	sp->counter_val[2] = G_THRESHOLD_2(r);
9181 	sp->counter_val[3] = G_THRESHOLD_3(r);
9182 
9183 	if (chip_id(adapter) >= CHELSIO_T6) {
9184 		r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
9185 		tscale = G_TSCALE(r);
9186 		if (tscale == 0)
9187 			tscale = 1;
9188 		else
9189 			tscale += 2;
9190 	}
9191 
9192 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
9193 	sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
9194 	sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
9195 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
9196 	sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
9197 	sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
9198 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
9199 	sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
9200 	sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
9201 
9202 	r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
9203 	sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
9204 	if (is_t4(adapter))
9205 		sp->fl_starve_threshold2 = sp->fl_starve_threshold;
9206 	else if (is_t5(adapter))
9207 		sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
9208 	else
9209 		sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
9210 
9211 	/* egress queues: log2 of # of doorbells per BAR2 page */
9212 	r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
9213 	r >>= S_QUEUESPERPAGEPF0 +
9214 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9215 	sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
9216 
9217 	/* ingress queues: log2 of # of doorbells per BAR2 page */
9218 	r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
9219 	r >>= S_QUEUESPERPAGEPF0 +
9220 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9221 	sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
9222 
9223 	r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
9224 	r >>= S_HOSTPAGESIZEPF0 +
9225 	    (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
9226 	sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
9227 
9228 	r = t4_read_reg(adapter, A_SGE_CONTROL);
9229 	sp->sge_control = r;
9230 	sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
9231 	sp->fl_pktshift = G_PKTSHIFT(r);
9232 	if (chip_id(adapter) <= CHELSIO_T5) {
9233 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9234 		    X_INGPADBOUNDARY_SHIFT);
9235 	} else {
9236 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9237 		    X_T6_INGPADBOUNDARY_SHIFT);
9238 	}
9239 	if (is_t4(adapter))
9240 		sp->pack_boundary = sp->pad_boundary;
9241 	else {
9242 		r = t4_read_reg(adapter, A_SGE_CONTROL2);
9243 		if (G_INGPACKBOUNDARY(r) == 0)
9244 			sp->pack_boundary = 16;
9245 		else
9246 			sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
9247 	}
9248 	for (i = 0; i < SGE_FLBUF_SIZES; i++)
9249 		sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
9250 		    A_SGE_FL_BUFFER_SIZE0 + (4 * i));
9251 
9252 	return 0;
9253 }
9254 
9255 /*
9256  * Read and cache the adapter's compressed filter mode and ingress config.
9257  */
9258 static void read_filter_mode_and_ingress_config(struct adapter *adap,
9259     bool sleep_ok)
9260 {
9261 	uint32_t v;
9262 	struct tp_params *tpp = &adap->params.tp;
9263 
9264 	t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP,
9265 	    sleep_ok);
9266 	t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG,
9267 	    sleep_ok);
9268 
9269 	/*
9270 	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9271 	 * shift positions of several elements of the Compressed Filter Tuple
9272 	 * for this adapter which we need frequently ...
9273 	 */
9274 	tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
9275 	tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
9276 	tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
9277 	tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
9278 	tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
9279 	tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
9280 	tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
9281 	tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
9282 	tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
9283 	tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
9284 
9285 	if (chip_id(adap) > CHELSIO_T4) {
9286 		v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3));
9287 		adap->params.tp.hash_filter_mask = v;
9288 		v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
9289 		adap->params.tp.hash_filter_mask |= (u64)v << 32;
9290 	}
9291 }
9292 
9293 /**
9294  *      t4_init_tp_params - initialize adap->params.tp
9295  *      @adap: the adapter
9296  *
9297  *      Initialize various fields of the adapter's TP Parameters structure.
9298  */
9299 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9300 {
9301 	int chan;
9302 	u32 v;
9303 	struct tp_params *tpp = &adap->params.tp;
9304 
9305 	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
9306 	tpp->tre = G_TIMERRESOLUTION(v);
9307 	tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
9308 
9309 	/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9310 	for (chan = 0; chan < MAX_NCHAN; chan++)
9311 		tpp->tx_modq[chan] = chan;
9312 
9313 	read_filter_mode_and_ingress_config(adap, sleep_ok);
9314 
9315 	/*
9316 	 * Cache a mask of the bits that represent the error vector portion of
9317 	 * rx_pkt.err_vec.  T6+ can use a compressed error vector to make room
9318 	 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
9319 	 */
9320 	tpp->err_vec_mask = htobe16(0xffff);
9321 	if (chip_id(adap) > CHELSIO_T5) {
9322 		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
9323 		if (v & F_CRXPKTENC) {
9324 			tpp->err_vec_mask =
9325 			    htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
9326 		}
9327 	}
9328 
9329 	return 0;
9330 }
9331 
9332 /**
9333  *      t4_filter_field_shift - calculate filter field shift
9334  *      @adap: the adapter
9335  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9336  *
9337  *      Return the shift position of a filter field within the Compressed
9338  *      Filter Tuple.  The filter field is specified via its selection bit
9339  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
9340  */
9341 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9342 {
9343 	unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9344 	unsigned int sel;
9345 	int field_shift;
9346 
9347 	if ((filter_mode & filter_sel) == 0)
9348 		return -1;
9349 
9350 	for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9351 		switch (filter_mode & sel) {
9352 		case F_FCOE:
9353 			field_shift += W_FT_FCOE;
9354 			break;
9355 		case F_PORT:
9356 			field_shift += W_FT_PORT;
9357 			break;
9358 		case F_VNIC_ID:
9359 			field_shift += W_FT_VNIC_ID;
9360 			break;
9361 		case F_VLAN:
9362 			field_shift += W_FT_VLAN;
9363 			break;
9364 		case F_TOS:
9365 			field_shift += W_FT_TOS;
9366 			break;
9367 		case F_PROTOCOL:
9368 			field_shift += W_FT_PROTOCOL;
9369 			break;
9370 		case F_ETHERTYPE:
9371 			field_shift += W_FT_ETHERTYPE;
9372 			break;
9373 		case F_MACMATCH:
9374 			field_shift += W_FT_MACMATCH;
9375 			break;
9376 		case F_MPSHITTYPE:
9377 			field_shift += W_FT_MPSHITTYPE;
9378 			break;
9379 		case F_FRAGMENTATION:
9380 			field_shift += W_FT_FRAGMENTATION;
9381 			break;
9382 		}
9383 	}
9384 	return field_shift;
9385 }
9386 
9387 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
9388 {
9389 	u8 addr[6];
9390 	int ret, i, j;
9391 	struct port_info *p = adap2pinfo(adap, port_id);
9392 	u32 param, val;
9393 	struct vi_info *vi = &p->vi[0];
9394 
9395 	for (i = 0, j = -1; i <= p->port_id; i++) {
9396 		do {
9397 			j++;
9398 		} while ((adap->params.portvec & (1 << j)) == 0);
9399 	}
9400 
9401 	p->tx_chan = j;
9402 	p->mps_bg_map = t4_get_mps_bg_map(adap, j);
9403 	p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
9404 	p->lport = j;
9405 
9406 	if (!(adap->flags & IS_VF) ||
9407 	    adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
9408  		t4_update_port_info(p);
9409 	}
9410 
9411 	ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size,
9412 	    &vi->vfvld, &vi->vin);
9413 	if (ret < 0)
9414 		return ret;
9415 
9416 	vi->viid = ret;
9417 	t4_os_set_hw_addr(p, addr);
9418 
9419 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9420 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
9421 	    V_FW_PARAMS_PARAM_YZ(vi->viid);
9422 	ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
9423 	if (ret)
9424 		vi->rss_base = 0xffff;
9425 	else {
9426 		/* MPASS((val >> 16) == rss_size); */
9427 		vi->rss_base = val & 0xffff;
9428 	}
9429 
9430 	return 0;
9431 }
9432 
9433 /**
9434  *	t4_read_cimq_cfg - read CIM queue configuration
9435  *	@adap: the adapter
9436  *	@base: holds the queue base addresses in bytes
9437  *	@size: holds the queue sizes in bytes
9438  *	@thres: holds the queue full thresholds in bytes
9439  *
9440  *	Returns the current configuration of the CIM queues, starting with
9441  *	the IBQs, then the OBQs.
9442  */
9443 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9444 {
9445 	unsigned int i, v;
9446 	int cim_num_obq = adap->chip_params->cim_num_obq;
9447 
9448 	for (i = 0; i < CIM_NUM_IBQ; i++) {
9449 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
9450 			     V_QUENUMSELECT(i));
9451 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9452 		/* value is in 256-byte units */
9453 		*base++ = G_CIMQBASE(v) * 256;
9454 		*size++ = G_CIMQSIZE(v) * 256;
9455 		*thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
9456 	}
9457 	for (i = 0; i < cim_num_obq; i++) {
9458 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9459 			     V_QUENUMSELECT(i));
9460 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9461 		/* value is in 256-byte units */
9462 		*base++ = G_CIMQBASE(v) * 256;
9463 		*size++ = G_CIMQSIZE(v) * 256;
9464 	}
9465 }
9466 
9467 /**
9468  *	t4_read_cim_ibq - read the contents of a CIM inbound queue
9469  *	@adap: the adapter
9470  *	@qid: the queue index
9471  *	@data: where to store the queue contents
9472  *	@n: capacity of @data in 32-bit words
9473  *
9474  *	Reads the contents of the selected CIM queue starting at address 0 up
9475  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9476  *	error and the number of 32-bit words actually read on success.
9477  */
9478 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9479 {
9480 	int i, err, attempts;
9481 	unsigned int addr;
9482 	const unsigned int nwords = CIM_IBQ_SIZE * 4;
9483 
9484 	if (qid > 5 || (n & 3))
9485 		return -EINVAL;
9486 
9487 	addr = qid * nwords;
9488 	if (n > nwords)
9489 		n = nwords;
9490 
9491 	/* It might take 3-10ms before the IBQ debug read access is allowed.
9492 	 * Wait for 1 Sec with a delay of 1 usec.
9493 	 */
9494 	attempts = 1000000;
9495 
9496 	for (i = 0; i < n; i++, addr++) {
9497 		t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
9498 			     F_IBQDBGEN);
9499 		err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
9500 				      attempts, 1);
9501 		if (err)
9502 			return err;
9503 		*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
9504 	}
9505 	t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
9506 	return i;
9507 }
9508 
9509 /**
9510  *	t4_read_cim_obq - read the contents of a CIM outbound queue
9511  *	@adap: the adapter
9512  *	@qid: the queue index
9513  *	@data: where to store the queue contents
9514  *	@n: capacity of @data in 32-bit words
9515  *
9516  *	Reads the contents of the selected CIM queue starting at address 0 up
9517  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9518  *	error and the number of 32-bit words actually read on success.
9519  */
9520 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9521 {
9522 	int i, err;
9523 	unsigned int addr, v, nwords;
9524 	int cim_num_obq = adap->chip_params->cim_num_obq;
9525 
9526 	if ((qid > (cim_num_obq - 1)) || (n & 3))
9527 		return -EINVAL;
9528 
9529 	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9530 		     V_QUENUMSELECT(qid));
9531 	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9532 
9533 	addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
9534 	nwords = G_CIMQSIZE(v) * 64;  /* same */
9535 	if (n > nwords)
9536 		n = nwords;
9537 
9538 	for (i = 0; i < n; i++, addr++) {
9539 		t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
9540 			     F_OBQDBGEN);
9541 		err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
9542 				      2, 1);
9543 		if (err)
9544 			return err;
9545 		*data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
9546 	}
9547 	t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
9548 	return i;
9549 }
9550 
9551 enum {
9552 	CIM_QCTL_BASE     = 0,
9553 	CIM_CTL_BASE      = 0x2000,
9554 	CIM_PBT_ADDR_BASE = 0x2800,
9555 	CIM_PBT_LRF_BASE  = 0x3000,
9556 	CIM_PBT_DATA_BASE = 0x3800
9557 };
9558 
9559 /**
9560  *	t4_cim_read - read a block from CIM internal address space
9561  *	@adap: the adapter
9562  *	@addr: the start address within the CIM address space
9563  *	@n: number of words to read
9564  *	@valp: where to store the result
9565  *
9566  *	Reads a block of 4-byte words from the CIM intenal address space.
9567  */
9568 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9569 		unsigned int *valp)
9570 {
9571 	int ret = 0;
9572 
9573 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9574 		return -EBUSY;
9575 
9576 	for ( ; !ret && n--; addr += 4) {
9577 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
9578 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9579 				      0, 5, 2);
9580 		if (!ret)
9581 			*valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
9582 	}
9583 	return ret;
9584 }
9585 
9586 /**
9587  *	t4_cim_write - write a block into CIM internal address space
9588  *	@adap: the adapter
9589  *	@addr: the start address within the CIM address space
9590  *	@n: number of words to write
9591  *	@valp: set of values to write
9592  *
9593  *	Writes a block of 4-byte words into the CIM intenal address space.
9594  */
9595 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9596 		 const unsigned int *valp)
9597 {
9598 	int ret = 0;
9599 
9600 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9601 		return -EBUSY;
9602 
9603 	for ( ; !ret && n--; addr += 4) {
9604 		t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
9605 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
9606 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
9607 				      0, 5, 2);
9608 	}
9609 	return ret;
9610 }
9611 
9612 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9613 			 unsigned int val)
9614 {
9615 	return t4_cim_write(adap, addr, 1, &val);
9616 }
9617 
9618 /**
9619  *	t4_cim_ctl_read - read a block from CIM control region
9620  *	@adap: the adapter
9621  *	@addr: the start address within the CIM control region
9622  *	@n: number of words to read
9623  *	@valp: where to store the result
9624  *
9625  *	Reads a block of 4-byte words from the CIM control region.
9626  */
9627 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
9628 		    unsigned int *valp)
9629 {
9630 	return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
9631 }
9632 
9633 /**
9634  *	t4_cim_read_la - read CIM LA capture buffer
9635  *	@adap: the adapter
9636  *	@la_buf: where to store the LA data
9637  *	@wrptr: the HW write pointer within the capture buffer
9638  *
9639  *	Reads the contents of the CIM LA buffer with the most recent entry at
9640  *	the end	of the returned data and with the entry at @wrptr first.
9641  *	We try to leave the LA in the running state we find it in.
9642  */
9643 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9644 {
9645 	int i, ret;
9646 	unsigned int cfg, val, idx;
9647 
9648 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
9649 	if (ret)
9650 		return ret;
9651 
9652 	if (cfg & F_UPDBGLAEN) {	/* LA is running, freeze it */
9653 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
9654 		if (ret)
9655 			return ret;
9656 	}
9657 
9658 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
9659 	if (ret)
9660 		goto restart;
9661 
9662 	idx = G_UPDBGLAWRPTR(val);
9663 	if (wrptr)
9664 		*wrptr = idx;
9665 
9666 	for (i = 0; i < adap->params.cim_la_size; i++) {
9667 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
9668 				    V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
9669 		if (ret)
9670 			break;
9671 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
9672 		if (ret)
9673 			break;
9674 		if (val & F_UPDBGLARDEN) {
9675 			ret = -ETIMEDOUT;
9676 			break;
9677 		}
9678 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
9679 		if (ret)
9680 			break;
9681 
9682 		/* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
9683 		idx = (idx + 1) & M_UPDBGLARDPTR;
9684 		/*
9685 		 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9686 		 * identify the 32-bit portion of the full 312-bit data
9687 		 */
9688 		if (is_t6(adap))
9689 			while ((idx & 0xf) > 9)
9690 				idx = (idx + 1) % M_UPDBGLARDPTR;
9691 	}
9692 restart:
9693 	if (cfg & F_UPDBGLAEN) {
9694 		int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
9695 				      cfg & ~F_UPDBGLARDEN);
9696 		if (!ret)
9697 			ret = r;
9698 	}
9699 	return ret;
9700 }
9701 
9702 /**
9703  *	t4_tp_read_la - read TP LA capture buffer
9704  *	@adap: the adapter
9705  *	@la_buf: where to store the LA data
9706  *	@wrptr: the HW write pointer within the capture buffer
9707  *
9708  *	Reads the contents of the TP LA buffer with the most recent entry at
9709  *	the end	of the returned data and with the entry at @wrptr first.
9710  *	We leave the LA in the running state we find it in.
9711  */
9712 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9713 {
9714 	bool last_incomplete;
9715 	unsigned int i, cfg, val, idx;
9716 
9717 	cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
9718 	if (cfg & F_DBGLAENABLE)			/* freeze LA */
9719 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
9720 			     adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
9721 
9722 	val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
9723 	idx = G_DBGLAWPTR(val);
9724 	last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
9725 	if (last_incomplete)
9726 		idx = (idx + 1) & M_DBGLARPTR;
9727 	if (wrptr)
9728 		*wrptr = idx;
9729 
9730 	val &= 0xffff;
9731 	val &= ~V_DBGLARPTR(M_DBGLARPTR);
9732 	val |= adap->params.tp.la_mask;
9733 
9734 	for (i = 0; i < TPLA_SIZE; i++) {
9735 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
9736 		la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
9737 		idx = (idx + 1) & M_DBGLARPTR;
9738 	}
9739 
9740 	/* Wipe out last entry if it isn't valid */
9741 	if (last_incomplete)
9742 		la_buf[TPLA_SIZE - 1] = ~0ULL;
9743 
9744 	if (cfg & F_DBGLAENABLE)		/* restore running state */
9745 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
9746 			     cfg | adap->params.tp.la_mask);
9747 }
9748 
9749 /*
9750  * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
9751  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
9752  * state for more than the Warning Threshold then we'll issue a warning about
9753  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
9754  * appears to be hung every Warning Repeat second till the situation clears.
9755  * If the situation clears, we'll note that as well.
9756  */
9757 #define SGE_IDMA_WARN_THRESH 1
9758 #define SGE_IDMA_WARN_REPEAT 300
9759 
9760 /**
9761  *	t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
9762  *	@adapter: the adapter
9763  *	@idma: the adapter IDMA Monitor state
9764  *
9765  *	Initialize the state of an SGE Ingress DMA Monitor.
9766  */
9767 void t4_idma_monitor_init(struct adapter *adapter,
9768 			  struct sge_idma_monitor_state *idma)
9769 {
9770 	/* Initialize the state variables for detecting an SGE Ingress DMA
9771 	 * hang.  The SGE has internal counters which count up on each clock
9772 	 * tick whenever the SGE finds its Ingress DMA State Engines in the
9773 	 * same state they were on the previous clock tick.  The clock used is
9774 	 * the Core Clock so we have a limit on the maximum "time" they can
9775 	 * record; typically a very small number of seconds.  For instance,
9776 	 * with a 600MHz Core Clock, we can only count up to a bit more than
9777 	 * 7s.  So we'll synthesize a larger counter in order to not run the
9778 	 * risk of having the "timers" overflow and give us the flexibility to
9779 	 * maintain a Hung SGE State Machine of our own which operates across
9780 	 * a longer time frame.
9781 	 */
9782 	idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
9783 	idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
9784 }
9785 
9786 /**
9787  *	t4_idma_monitor - monitor SGE Ingress DMA state
9788  *	@adapter: the adapter
9789  *	@idma: the adapter IDMA Monitor state
9790  *	@hz: number of ticks/second
9791  *	@ticks: number of ticks since the last IDMA Monitor call
9792  */
9793 void t4_idma_monitor(struct adapter *adapter,
9794 		     struct sge_idma_monitor_state *idma,
9795 		     int hz, int ticks)
9796 {
9797 	int i, idma_same_state_cnt[2];
9798 
9799 	 /* Read the SGE Debug Ingress DMA Same State Count registers.  These
9800 	  * are counters inside the SGE which count up on each clock when the
9801 	  * SGE finds its Ingress DMA State Engines in the same states they
9802 	  * were in the previous clock.  The counters will peg out at
9803 	  * 0xffffffff without wrapping around so once they pass the 1s
9804 	  * threshold they'll stay above that till the IDMA state changes.
9805 	  */
9806 	t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
9807 	idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
9808 	idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9809 
9810 	for (i = 0; i < 2; i++) {
9811 		u32 debug0, debug11;
9812 
9813 		/* If the Ingress DMA Same State Counter ("timer") is less
9814 		 * than 1s, then we can reset our synthesized Stall Timer and
9815 		 * continue.  If we have previously emitted warnings about a
9816 		 * potential stalled Ingress Queue, issue a note indicating
9817 		 * that the Ingress Queue has resumed forward progress.
9818 		 */
9819 		if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
9820 			if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
9821 				CH_WARN(adapter, "SGE idma%d, queue %u, "
9822 					"resumed after %d seconds\n",
9823 					i, idma->idma_qid[i],
9824 					idma->idma_stalled[i]/hz);
9825 			idma->idma_stalled[i] = 0;
9826 			continue;
9827 		}
9828 
9829 		/* Synthesize an SGE Ingress DMA Same State Timer in the Hz
9830 		 * domain.  The first time we get here it'll be because we
9831 		 * passed the 1s Threshold; each additional time it'll be
9832 		 * because the RX Timer Callback is being fired on its regular
9833 		 * schedule.
9834 		 *
9835 		 * If the stall is below our Potential Hung Ingress Queue
9836 		 * Warning Threshold, continue.
9837 		 */
9838 		if (idma->idma_stalled[i] == 0) {
9839 			idma->idma_stalled[i] = hz;
9840 			idma->idma_warn[i] = 0;
9841 		} else {
9842 			idma->idma_stalled[i] += ticks;
9843 			idma->idma_warn[i] -= ticks;
9844 		}
9845 
9846 		if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
9847 			continue;
9848 
9849 		/* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
9850 		 */
9851 		if (idma->idma_warn[i] > 0)
9852 			continue;
9853 		idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
9854 
9855 		/* Read and save the SGE IDMA State and Queue ID information.
9856 		 * We do this every time in case it changes across time ...
9857 		 * can't be too careful ...
9858 		 */
9859 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
9860 		debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9861 		idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
9862 
9863 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
9864 		debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
9865 		idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
9866 
9867 		CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
9868 			" state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
9869 			i, idma->idma_qid[i], idma->idma_state[i],
9870 			idma->idma_stalled[i]/hz,
9871 			debug0, debug11);
9872 		t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
9873 	}
9874 }
9875 
9876 /**
9877  *	t4_read_pace_tbl - read the pace table
9878  *	@adap: the adapter
9879  *	@pace_vals: holds the returned values
9880  *
9881  *	Returns the values of TP's pace table in microseconds.
9882  */
9883 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
9884 {
9885 	unsigned int i, v;
9886 
9887 	for (i = 0; i < NTX_SCHED; i++) {
9888 		t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
9889 		v = t4_read_reg(adap, A_TP_PACE_TABLE);
9890 		pace_vals[i] = dack_ticks_to_usec(adap, v);
9891 	}
9892 }
9893 
9894 /**
9895  *	t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
9896  *	@adap: the adapter
9897  *	@sched: the scheduler index
9898  *	@kbps: the byte rate in Kbps
9899  *	@ipg: the interpacket delay in tenths of nanoseconds
9900  *
9901  *	Return the current configuration of a HW Tx scheduler.
9902  */
9903 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
9904 		     unsigned int *ipg, bool sleep_ok)
9905 {
9906 	unsigned int v, addr, bpt, cpt;
9907 
9908 	if (kbps) {
9909 		addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
9910 		t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9911 		if (sched & 1)
9912 			v >>= 16;
9913 		bpt = (v >> 8) & 0xff;
9914 		cpt = v & 0xff;
9915 		if (!cpt)
9916 			*kbps = 0;	/* scheduler disabled */
9917 		else {
9918 			v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
9919 			*kbps = (v * bpt) / 125;
9920 		}
9921 	}
9922 	if (ipg) {
9923 		addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
9924 		t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
9925 		if (sched & 1)
9926 			v >>= 16;
9927 		v &= 0xffff;
9928 		*ipg = (10000 * v) / core_ticks_per_usec(adap);
9929 	}
9930 }
9931 
9932 /**
9933  *	t4_load_cfg - download config file
9934  *	@adap: the adapter
9935  *	@cfg_data: the cfg text file to write
9936  *	@size: text file size
9937  *
9938  *	Write the supplied config text file to the card's serial flash.
9939  */
9940 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
9941 {
9942 	int ret, i, n, cfg_addr;
9943 	unsigned int addr;
9944 	unsigned int flash_cfg_start_sec;
9945 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9946 
9947 	cfg_addr = t4_flash_cfg_addr(adap);
9948 	if (cfg_addr < 0)
9949 		return cfg_addr;
9950 
9951 	addr = cfg_addr;
9952 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
9953 
9954 	if (size > FLASH_CFG_MAX_SIZE) {
9955 		CH_ERR(adap, "cfg file too large, max is %u bytes\n",
9956 		       FLASH_CFG_MAX_SIZE);
9957 		return -EFBIG;
9958 	}
9959 
9960 	i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,	/* # of sectors spanned */
9961 			 sf_sec_size);
9962 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9963 				     flash_cfg_start_sec + i - 1);
9964 	/*
9965 	 * If size == 0 then we're simply erasing the FLASH sectors associated
9966 	 * with the on-adapter Firmware Configuration File.
9967 	 */
9968 	if (ret || size == 0)
9969 		goto out;
9970 
9971 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
9972 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
9973 		if ( (size - i) <  SF_PAGE_SIZE)
9974 			n = size - i;
9975 		else
9976 			n = SF_PAGE_SIZE;
9977 		ret = t4_write_flash(adap, addr, n, cfg_data, 1);
9978 		if (ret)
9979 			goto out;
9980 
9981 		addr += SF_PAGE_SIZE;
9982 		cfg_data += SF_PAGE_SIZE;
9983 	}
9984 
9985 out:
9986 	if (ret)
9987 		CH_ERR(adap, "config file %s failed %d\n",
9988 		       (size == 0 ? "clear" : "download"), ret);
9989 	return ret;
9990 }
9991 
9992 /**
9993  *	t5_fw_init_extern_mem - initialize the external memory
9994  *	@adap: the adapter
9995  *
9996  *	Initializes the external memory on T5.
9997  */
9998 int t5_fw_init_extern_mem(struct adapter *adap)
9999 {
10000 	u32 params[1], val[1];
10001 	int ret;
10002 
10003 	if (!is_t5(adap))
10004 		return 0;
10005 
10006 	val[0] = 0xff; /* Initialize all MCs */
10007 	params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10008 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
10009 	ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
10010 			FW_CMD_MAX_TIMEOUT);
10011 
10012 	return ret;
10013 }
10014 
10015 /* BIOS boot headers */
10016 typedef struct pci_expansion_rom_header {
10017 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
10018 	u8	reserved[22]; /* Reserved per processor Architecture data */
10019 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
10020 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
10021 
10022 /* Legacy PCI Expansion ROM Header */
10023 typedef struct legacy_pci_expansion_rom_header {
10024 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
10025 	u8	size512; /* Current Image Size in units of 512 bytes */
10026 	u8	initentry_point[4];
10027 	u8	cksum; /* Checksum computed on the entire Image */
10028 	u8	reserved[16]; /* Reserved */
10029 	u8	pcir_offset[2]; /* Offset to PCI Data Struture */
10030 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
10031 
10032 /* EFI PCI Expansion ROM Header */
10033 typedef struct efi_pci_expansion_rom_header {
10034 	u8	signature[2]; // ROM signature. The value 0xaa55
10035 	u8	initialization_size[2]; /* Units 512. Includes this header */
10036 	u8	efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
10037 	u8	efi_subsystem[2]; /* Subsystem value for EFI image header */
10038 	u8	efi_machine_type[2]; /* Machine type from EFI image header */
10039 	u8	compression_type[2]; /* Compression type. */
10040 		/*
10041 		 * Compression type definition
10042 		 * 0x0: uncompressed
10043 		 * 0x1: Compressed
10044 		 * 0x2-0xFFFF: Reserved
10045 		 */
10046 	u8	reserved[8]; /* Reserved */
10047 	u8	efi_image_header_offset[2]; /* Offset to EFI Image */
10048 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
10049 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
10050 
10051 /* PCI Data Structure Format */
10052 typedef struct pcir_data_structure { /* PCI Data Structure */
10053 	u8	signature[4]; /* Signature. The string "PCIR" */
10054 	u8	vendor_id[2]; /* Vendor Identification */
10055 	u8	device_id[2]; /* Device Identification */
10056 	u8	vital_product[2]; /* Pointer to Vital Product Data */
10057 	u8	length[2]; /* PCIR Data Structure Length */
10058 	u8	revision; /* PCIR Data Structure Revision */
10059 	u8	class_code[3]; /* Class Code */
10060 	u8	image_length[2]; /* Image Length. Multiple of 512B */
10061 	u8	code_revision[2]; /* Revision Level of Code/Data */
10062 	u8	code_type; /* Code Type. */
10063 		/*
10064 		 * PCI Expansion ROM Code Types
10065 		 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10066 		 * 0x01: Open Firmware standard for PCI. FCODE
10067 		 * 0x02: Hewlett-Packard PA RISC. HP reserved
10068 		 * 0x03: EFI Image. EFI
10069 		 * 0x04-0xFF: Reserved.
10070 		 */
10071 	u8	indicator; /* Indicator. Identifies the last image in the ROM */
10072 	u8	reserved[2]; /* Reserved */
10073 } pcir_data_t; /* PCI__DATA_STRUCTURE */
10074 
10075 /* BOOT constants */
10076 enum {
10077 	BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
10078 	BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
10079 	BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
10080 	BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
10081 	BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment  */
10082 	VENDOR_ID = 0x1425, /* Vendor ID */
10083 	PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
10084 };
10085 
10086 /*
10087  *	modify_device_id - Modifies the device ID of the Boot BIOS image
10088  *	@adatper: the device ID to write.
10089  *	@boot_data: the boot image to modify.
10090  *
10091  *	Write the supplied device ID to the boot BIOS image.
10092  */
10093 static void modify_device_id(int device_id, u8 *boot_data)
10094 {
10095 	legacy_pci_exp_rom_header_t *header;
10096 	pcir_data_t *pcir_header;
10097 	u32 cur_header = 0;
10098 
10099 	/*
10100 	 * Loop through all chained images and change the device ID's
10101 	 */
10102 	while (1) {
10103 		header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
10104 		pcir_header = (pcir_data_t *) &boot_data[cur_header +
10105 			      le16_to_cpu(*(u16*)header->pcir_offset)];
10106 
10107 		/*
10108 		 * Only modify the Device ID if code type is Legacy or HP.
10109 		 * 0x00: Okay to modify
10110 		 * 0x01: FCODE. Do not be modify
10111 		 * 0x03: Okay to modify
10112 		 * 0x04-0xFF: Do not modify
10113 		 */
10114 		if (pcir_header->code_type == 0x00) {
10115 			u8 csum = 0;
10116 			int i;
10117 
10118 			/*
10119 			 * Modify Device ID to match current adatper
10120 			 */
10121 			*(u16*) pcir_header->device_id = device_id;
10122 
10123 			/*
10124 			 * Set checksum temporarily to 0.
10125 			 * We will recalculate it later.
10126 			 */
10127 			header->cksum = 0x0;
10128 
10129 			/*
10130 			 * Calculate and update checksum
10131 			 */
10132 			for (i = 0; i < (header->size512 * 512); i++)
10133 				csum += (u8)boot_data[cur_header + i];
10134 
10135 			/*
10136 			 * Invert summed value to create the checksum
10137 			 * Writing new checksum value directly to the boot data
10138 			 */
10139 			boot_data[cur_header + 7] = -csum;
10140 
10141 		} else if (pcir_header->code_type == 0x03) {
10142 
10143 			/*
10144 			 * Modify Device ID to match current adatper
10145 			 */
10146 			*(u16*) pcir_header->device_id = device_id;
10147 
10148 		}
10149 
10150 
10151 		/*
10152 		 * Check indicator element to identify if this is the last
10153 		 * image in the ROM.
10154 		 */
10155 		if (pcir_header->indicator & 0x80)
10156 			break;
10157 
10158 		/*
10159 		 * Move header pointer up to the next image in the ROM.
10160 		 */
10161 		cur_header += header->size512 * 512;
10162 	}
10163 }
10164 
10165 /*
10166  *	t4_load_boot - download boot flash
10167  *	@adapter: the adapter
10168  *	@boot_data: the boot image to write
10169  *	@boot_addr: offset in flash to write boot_data
10170  *	@size: image size
10171  *
10172  *	Write the supplied boot image to the card's serial flash.
10173  *	The boot image has the following sections: a 28-byte header and the
10174  *	boot image.
10175  */
10176 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10177 		 unsigned int boot_addr, unsigned int size)
10178 {
10179 	pci_exp_rom_header_t *header;
10180 	int pcir_offset ;
10181 	pcir_data_t *pcir_header;
10182 	int ret, addr;
10183 	uint16_t device_id;
10184 	unsigned int i;
10185 	unsigned int boot_sector = (boot_addr * 1024 );
10186 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10187 
10188 	/*
10189 	 * Make sure the boot image does not encroach on the firmware region
10190 	 */
10191 	if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10192 		CH_ERR(adap, "boot image encroaching on firmware region\n");
10193 		return -EFBIG;
10194 	}
10195 
10196 	/*
10197 	 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10198 	 * and Boot configuration data sections. These 3 boot sections span
10199 	 * sectors 0 to 7 in flash and live right before the FW image location.
10200 	 */
10201 	i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
10202 			sf_sec_size);
10203 	ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10204 				     (boot_sector >> 16) + i - 1);
10205 
10206 	/*
10207 	 * If size == 0 then we're simply erasing the FLASH sectors associated
10208 	 * with the on-adapter option ROM file
10209 	 */
10210 	if (ret || (size == 0))
10211 		goto out;
10212 
10213 	/* Get boot header */
10214 	header = (pci_exp_rom_header_t *)boot_data;
10215 	pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
10216 	/* PCIR Data Structure */
10217 	pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
10218 
10219 	/*
10220 	 * Perform some primitive sanity testing to avoid accidentally
10221 	 * writing garbage over the boot sectors.  We ought to check for
10222 	 * more but it's not worth it for now ...
10223 	 */
10224 	if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10225 		CH_ERR(adap, "boot image too small/large\n");
10226 		return -EFBIG;
10227 	}
10228 
10229 #ifndef CHELSIO_T4_DIAGS
10230 	/*
10231 	 * Check BOOT ROM header signature
10232 	 */
10233 	if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
10234 		CH_ERR(adap, "Boot image missing signature\n");
10235 		return -EINVAL;
10236 	}
10237 
10238 	/*
10239 	 * Check PCI header signature
10240 	 */
10241 	if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
10242 		CH_ERR(adap, "PCI header missing signature\n");
10243 		return -EINVAL;
10244 	}
10245 
10246 	/*
10247 	 * Check Vendor ID matches Chelsio ID
10248 	 */
10249 	if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
10250 		CH_ERR(adap, "Vendor ID missing signature\n");
10251 		return -EINVAL;
10252 	}
10253 #endif
10254 
10255 	/*
10256 	 * Retrieve adapter's device ID
10257 	 */
10258 	t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
10259 	/* Want to deal with PF 0 so I strip off PF 4 indicator */
10260 	device_id = device_id & 0xf0ff;
10261 
10262 	/*
10263 	 * Check PCIE Device ID
10264 	 */
10265 	if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
10266 		/*
10267 		 * Change the device ID in the Boot BIOS image to match
10268 		 * the Device ID of the current adapter.
10269 		 */
10270 		modify_device_id(device_id, boot_data);
10271 	}
10272 
10273 	/*
10274 	 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10275 	 * we finish copying the rest of the boot image. This will ensure
10276 	 * that the BIOS boot header will only be written if the boot image
10277 	 * was written in full.
10278 	 */
10279 	addr = boot_sector;
10280 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10281 		addr += SF_PAGE_SIZE;
10282 		boot_data += SF_PAGE_SIZE;
10283 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
10284 		if (ret)
10285 			goto out;
10286 	}
10287 
10288 	ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10289 			     (const u8 *)header, 0);
10290 
10291 out:
10292 	if (ret)
10293 		CH_ERR(adap, "boot image download failed, error %d\n", ret);
10294 	return ret;
10295 }
10296 
10297 /*
10298  *	t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
10299  *	@adapter: the adapter
10300  *
10301  *	Return the address within the flash where the OptionROM Configuration
10302  *	is stored, or an error if the device FLASH is too small to contain
10303  *	a OptionROM Configuration.
10304  */
10305 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10306 {
10307 	/*
10308 	 * If the device FLASH isn't large enough to hold a Firmware
10309 	 * Configuration File, return an error.
10310 	 */
10311 	if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10312 		return -ENOSPC;
10313 
10314 	return FLASH_BOOTCFG_START;
10315 }
10316 
10317 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
10318 {
10319 	int ret, i, n, cfg_addr;
10320 	unsigned int addr;
10321 	unsigned int flash_cfg_start_sec;
10322 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10323 
10324 	cfg_addr = t4_flash_bootcfg_addr(adap);
10325 	if (cfg_addr < 0)
10326 		return cfg_addr;
10327 
10328 	addr = cfg_addr;
10329 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
10330 
10331 	if (size > FLASH_BOOTCFG_MAX_SIZE) {
10332 		CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
10333 			FLASH_BOOTCFG_MAX_SIZE);
10334 		return -EFBIG;
10335 	}
10336 
10337 	i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
10338 			 sf_sec_size);
10339 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10340 					flash_cfg_start_sec + i - 1);
10341 
10342 	/*
10343 	 * If size == 0 then we're simply erasing the FLASH sectors associated
10344 	 * with the on-adapter OptionROM Configuration File.
10345 	 */
10346 	if (ret || size == 0)
10347 		goto out;
10348 
10349 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
10350 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10351 		if ( (size - i) <  SF_PAGE_SIZE)
10352 			n = size - i;
10353 		else
10354 			n = SF_PAGE_SIZE;
10355 		ret = t4_write_flash(adap, addr, n, cfg_data, 0);
10356 		if (ret)
10357 			goto out;
10358 
10359 		addr += SF_PAGE_SIZE;
10360 		cfg_data += SF_PAGE_SIZE;
10361 	}
10362 
10363 out:
10364 	if (ret)
10365 		CH_ERR(adap, "boot config data %s failed %d\n",
10366 				(size == 0 ? "clear" : "download"), ret);
10367 	return ret;
10368 }
10369 
10370 /**
10371  *	t4_set_filter_mode - configure the optional components of filter tuples
10372  *	@adap: the adapter
10373  *	@mode_map: a bitmap selcting which optional filter components to enable
10374  * 	@sleep_ok: if true we may sleep while awaiting command completion
10375  *
10376  *	Sets the filter mode by selecting the optional components to enable
10377  *	in filter tuples.  Returns 0 on success and a negative error if the
10378  *	requested mode needs more bits than are available for optional
10379  *	components.
10380  */
10381 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
10382 		       bool sleep_ok)
10383 {
10384 	static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
10385 
10386 	int i, nbits = 0;
10387 
10388 	for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
10389 		if (mode_map & (1 << i))
10390 			nbits += width[i];
10391 	if (nbits > FILTER_OPT_LEN)
10392 		return -EINVAL;
10393 	t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok);
10394 	read_filter_mode_and_ingress_config(adap, sleep_ok);
10395 
10396 	return 0;
10397 }
10398 
10399 /**
10400  *	t4_clr_port_stats - clear port statistics
10401  *	@adap: the adapter
10402  *	@idx: the port index
10403  *
10404  *	Clear HW statistics for the given port.
10405  */
10406 void t4_clr_port_stats(struct adapter *adap, int idx)
10407 {
10408 	unsigned int i;
10409 	u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
10410 	u32 port_base_addr;
10411 
10412 	if (is_t4(adap))
10413 		port_base_addr = PORT_BASE(idx);
10414 	else
10415 		port_base_addr = T5_PORT_BASE(idx);
10416 
10417 	for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
10418 			i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
10419 		t4_write_reg(adap, port_base_addr + i, 0);
10420 	for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
10421 			i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
10422 		t4_write_reg(adap, port_base_addr + i, 0);
10423 	for (i = 0; i < 4; i++)
10424 		if (bgmap & (1 << i)) {
10425 			t4_write_reg(adap,
10426 			A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
10427 			t4_write_reg(adap,
10428 			A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
10429 		}
10430 }
10431 
10432 /**
10433  *	t4_i2c_rd - read I2C data from adapter
10434  *	@adap: the adapter
10435  *	@port: Port number if per-port device; <0 if not
10436  *	@devid: per-port device ID or absolute device ID
10437  *	@offset: byte offset into device I2C space
10438  *	@len: byte length of I2C space data
10439  *	@buf: buffer in which to return I2C data
10440  *
10441  *	Reads the I2C data from the indicated device and location.
10442  */
10443 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
10444 	      int port, unsigned int devid,
10445 	      unsigned int offset, unsigned int len,
10446 	      u8 *buf)
10447 {
10448 	u32 ldst_addrspace;
10449 	struct fw_ldst_cmd ldst;
10450 	int ret;
10451 
10452 	if (port >= 4 ||
10453 	    devid >= 256 ||
10454 	    offset >= 256 ||
10455 	    len > sizeof ldst.u.i2c.data)
10456 		return -EINVAL;
10457 
10458 	memset(&ldst, 0, sizeof ldst);
10459 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
10460 	ldst.op_to_addrspace =
10461 		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10462 			    F_FW_CMD_REQUEST |
10463 			    F_FW_CMD_READ |
10464 			    ldst_addrspace);
10465 	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
10466 	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
10467 	ldst.u.i2c.did = devid;
10468 	ldst.u.i2c.boffset = offset;
10469 	ldst.u.i2c.blen = len;
10470 	ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
10471 	if (!ret)
10472 		memcpy(buf, ldst.u.i2c.data, len);
10473 	return ret;
10474 }
10475 
10476 /**
10477  *	t4_i2c_wr - write I2C data to adapter
10478  *	@adap: the adapter
10479  *	@port: Port number if per-port device; <0 if not
10480  *	@devid: per-port device ID or absolute device ID
10481  *	@offset: byte offset into device I2C space
10482  *	@len: byte length of I2C space data
10483  *	@buf: buffer containing new I2C data
10484  *
10485  *	Write the I2C data to the indicated device and location.
10486  */
10487 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
10488 	      int port, unsigned int devid,
10489 	      unsigned int offset, unsigned int len,
10490 	      u8 *buf)
10491 {
10492 	u32 ldst_addrspace;
10493 	struct fw_ldst_cmd ldst;
10494 
10495 	if (port >= 4 ||
10496 	    devid >= 256 ||
10497 	    offset >= 256 ||
10498 	    len > sizeof ldst.u.i2c.data)
10499 		return -EINVAL;
10500 
10501 	memset(&ldst, 0, sizeof ldst);
10502 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
10503 	ldst.op_to_addrspace =
10504 		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10505 			    F_FW_CMD_REQUEST |
10506 			    F_FW_CMD_WRITE |
10507 			    ldst_addrspace);
10508 	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
10509 	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
10510 	ldst.u.i2c.did = devid;
10511 	ldst.u.i2c.boffset = offset;
10512 	ldst.u.i2c.blen = len;
10513 	memcpy(ldst.u.i2c.data, buf, len);
10514 	return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
10515 }
10516 
10517 /**
10518  * 	t4_sge_ctxt_rd - read an SGE context through FW
10519  * 	@adap: the adapter
10520  * 	@mbox: mailbox to use for the FW command
10521  * 	@cid: the context id
10522  * 	@ctype: the context type
10523  * 	@data: where to store the context data
10524  *
10525  * 	Issues a FW command through the given mailbox to read an SGE context.
10526  */
10527 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10528 		   enum ctxt_type ctype, u32 *data)
10529 {
10530 	int ret;
10531 	struct fw_ldst_cmd c;
10532 
10533 	if (ctype == CTXT_EGRESS)
10534 		ret = FW_LDST_ADDRSPC_SGE_EGRC;
10535 	else if (ctype == CTXT_INGRESS)
10536 		ret = FW_LDST_ADDRSPC_SGE_INGC;
10537 	else if (ctype == CTXT_FLM)
10538 		ret = FW_LDST_ADDRSPC_SGE_FLMC;
10539 	else
10540 		ret = FW_LDST_ADDRSPC_SGE_CONMC;
10541 
10542 	memset(&c, 0, sizeof(c));
10543 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10544 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
10545 					V_FW_LDST_CMD_ADDRSPACE(ret));
10546 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10547 	c.u.idctxt.physid = cpu_to_be32(cid);
10548 
10549 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10550 	if (ret == 0) {
10551 		data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10552 		data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10553 		data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10554 		data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10555 		data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10556 		data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10557 	}
10558 	return ret;
10559 }
10560 
10561 /**
10562  * 	t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10563  * 	@adap: the adapter
10564  * 	@cid: the context id
10565  * 	@ctype: the context type
10566  * 	@data: where to store the context data
10567  *
10568  * 	Reads an SGE context directly, bypassing FW.  This is only for
10569  * 	debugging when FW is unavailable.
10570  */
10571 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
10572 		      u32 *data)
10573 {
10574 	int i, ret;
10575 
10576 	t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
10577 	ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
10578 	if (!ret)
10579 		for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
10580 			*data++ = t4_read_reg(adap, i);
10581 	return ret;
10582 }
10583 
10584 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
10585     int sleep_ok)
10586 {
10587 	struct fw_sched_cmd cmd;
10588 
10589 	memset(&cmd, 0, sizeof(cmd));
10590 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10591 				      F_FW_CMD_REQUEST |
10592 				      F_FW_CMD_WRITE);
10593 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10594 
10595 	cmd.u.config.sc = FW_SCHED_SC_CONFIG;
10596 	cmd.u.config.type = type;
10597 	cmd.u.config.minmaxen = minmaxen;
10598 
10599 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10600 			       NULL, sleep_ok);
10601 }
10602 
10603 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
10604 		    int rateunit, int ratemode, int channel, int cl,
10605 		    int minrate, int maxrate, int weight, int pktsize,
10606 		    int burstsize, int sleep_ok)
10607 {
10608 	struct fw_sched_cmd cmd;
10609 
10610 	memset(&cmd, 0, sizeof(cmd));
10611 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10612 				      F_FW_CMD_REQUEST |
10613 				      F_FW_CMD_WRITE);
10614 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10615 
10616 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10617 	cmd.u.params.type = type;
10618 	cmd.u.params.level = level;
10619 	cmd.u.params.mode = mode;
10620 	cmd.u.params.ch = channel;
10621 	cmd.u.params.cl = cl;
10622 	cmd.u.params.unit = rateunit;
10623 	cmd.u.params.rate = ratemode;
10624 	cmd.u.params.min = cpu_to_be32(minrate);
10625 	cmd.u.params.max = cpu_to_be32(maxrate);
10626 	cmd.u.params.weight = cpu_to_be16(weight);
10627 	cmd.u.params.pktsize = cpu_to_be16(pktsize);
10628 	cmd.u.params.burstsize = cpu_to_be16(burstsize);
10629 
10630 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10631 			       NULL, sleep_ok);
10632 }
10633 
10634 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
10635     unsigned int maxrate, int sleep_ok)
10636 {
10637 	struct fw_sched_cmd cmd;
10638 
10639 	memset(&cmd, 0, sizeof(cmd));
10640 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10641 				      F_FW_CMD_REQUEST |
10642 				      F_FW_CMD_WRITE);
10643 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10644 
10645 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10646 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10647 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
10648 	cmd.u.params.ch = channel;
10649 	cmd.u.params.rate = ratemode;		/* REL or ABS */
10650 	cmd.u.params.max = cpu_to_be32(maxrate);/*  %  or kbps */
10651 
10652 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10653 			       NULL, sleep_ok);
10654 }
10655 
10656 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
10657     int weight, int sleep_ok)
10658 {
10659 	struct fw_sched_cmd cmd;
10660 
10661 	if (weight < 0 || weight > 100)
10662 		return -EINVAL;
10663 
10664 	memset(&cmd, 0, sizeof(cmd));
10665 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10666 				      F_FW_CMD_REQUEST |
10667 				      F_FW_CMD_WRITE);
10668 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10669 
10670 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10671 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10672 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
10673 	cmd.u.params.ch = channel;
10674 	cmd.u.params.cl = cl;
10675 	cmd.u.params.weight = cpu_to_be16(weight);
10676 
10677 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10678 			       NULL, sleep_ok);
10679 }
10680 
10681 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
10682     int mode, unsigned int maxrate, int pktsize, int sleep_ok)
10683 {
10684 	struct fw_sched_cmd cmd;
10685 
10686 	memset(&cmd, 0, sizeof(cmd));
10687 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
10688 				      F_FW_CMD_REQUEST |
10689 				      F_FW_CMD_WRITE);
10690 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10691 
10692 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10693 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
10694 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
10695 	cmd.u.params.mode = mode;
10696 	cmd.u.params.ch = channel;
10697 	cmd.u.params.cl = cl;
10698 	cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
10699 	cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
10700 	cmd.u.params.max = cpu_to_be32(maxrate);
10701 	cmd.u.params.pktsize = cpu_to_be16(pktsize);
10702 
10703 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
10704 			       NULL, sleep_ok);
10705 }
10706 
10707 /*
10708  *	t4_config_watchdog - configure (enable/disable) a watchdog timer
10709  *	@adapter: the adapter
10710  * 	@mbox: mailbox to use for the FW command
10711  * 	@pf: the PF owning the queue
10712  * 	@vf: the VF owning the queue
10713  *	@timeout: watchdog timeout in ms
10714  *	@action: watchdog timer / action
10715  *
10716  *	There are separate watchdog timers for each possible watchdog
10717  *	action.  Configure one of the watchdog timers by setting a non-zero
10718  *	timeout.  Disable a watchdog timer by using a timeout of zero.
10719  */
10720 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
10721 		       unsigned int pf, unsigned int vf,
10722 		       unsigned int timeout, unsigned int action)
10723 {
10724 	struct fw_watchdog_cmd wdog;
10725 	unsigned int ticks;
10726 
10727 	/*
10728 	 * The watchdog command expects a timeout in units of 10ms so we need
10729 	 * to convert it here (via rounding) and force a minimum of one 10ms
10730 	 * "tick" if the timeout is non-zero but the conversion results in 0
10731 	 * ticks.
10732 	 */
10733 	ticks = (timeout + 5)/10;
10734 	if (timeout && !ticks)
10735 		ticks = 1;
10736 
10737 	memset(&wdog, 0, sizeof wdog);
10738 	wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
10739 				     F_FW_CMD_REQUEST |
10740 				     F_FW_CMD_WRITE |
10741 				     V_FW_PARAMS_CMD_PFN(pf) |
10742 				     V_FW_PARAMS_CMD_VFN(vf));
10743 	wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
10744 	wdog.timeout = cpu_to_be32(ticks);
10745 	wdog.action = cpu_to_be32(action);
10746 
10747 	return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
10748 }
10749 
10750 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
10751 {
10752 	struct fw_devlog_cmd devlog_cmd;
10753 	int ret;
10754 
10755 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
10756 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
10757 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
10758 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
10759 	ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
10760 			 sizeof(devlog_cmd), &devlog_cmd);
10761 	if (ret)
10762 		return ret;
10763 
10764 	*level = devlog_cmd.level;
10765 	return 0;
10766 }
10767 
10768 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
10769 {
10770 	struct fw_devlog_cmd devlog_cmd;
10771 
10772 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
10773 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
10774 					     F_FW_CMD_REQUEST |
10775 					     F_FW_CMD_WRITE);
10776 	devlog_cmd.level = level;
10777 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
10778 	return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
10779 			  sizeof(devlog_cmd), &devlog_cmd);
10780 }
10781