1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 216 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 217 adap->flags &= ~FW_OK; 218 } 219 } 220 221 /* 222 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 223 */ 224 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 225 u32 mbox_addr) 226 { 227 for ( ; nflit; nflit--, mbox_addr += 8) 228 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 229 } 230 231 /* 232 * Handle a FW assertion reported in a mailbox. 233 */ 234 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 235 { 236 CH_ALERT(adap, 237 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 238 asrt->u.assert.filename_0_7, 239 be32_to_cpu(asrt->u.assert.line), 240 be32_to_cpu(asrt->u.assert.x), 241 be32_to_cpu(asrt->u.assert.y)); 242 } 243 244 struct port_tx_state { 245 uint64_t rx_pause; 246 uint64_t tx_frames; 247 }; 248 249 static void 250 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 251 { 252 uint32_t rx_pause_reg, tx_frames_reg; 253 254 if (is_t4(sc)) { 255 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 256 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 257 } else { 258 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 259 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 260 } 261 262 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 263 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 264 } 265 266 static void 267 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 268 { 269 int i; 270 271 for_each_port(sc, i) 272 read_tx_state_one(sc, i, &tx_state[i]); 273 } 274 275 static void 276 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 277 { 278 uint32_t port_ctl_reg; 279 uint64_t tx_frames, rx_pause; 280 int i; 281 282 for_each_port(sc, i) { 283 rx_pause = tx_state[i].rx_pause; 284 tx_frames = tx_state[i].tx_frames; 285 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 286 287 if (is_t4(sc)) 288 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 289 else 290 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 291 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 292 rx_pause != tx_state[i].rx_pause && 293 tx_frames == tx_state[i].tx_frames) { 294 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 295 mdelay(1); 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 297 } 298 } 299 } 300 301 #define X_CIM_PF_NOACCESS 0xeeeeeeee 302 /** 303 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 304 * @adap: the adapter 305 * @mbox: index of the mailbox to use 306 * @cmd: the command to write 307 * @size: command length in bytes 308 * @rpl: where to optionally store the reply 309 * @sleep_ok: if true we may sleep while awaiting command completion 310 * @timeout: time to wait for command to finish before timing out 311 * (negative implies @sleep_ok=false) 312 * 313 * Sends the given command to FW through the selected mailbox and waits 314 * for the FW to execute the command. If @rpl is not %NULL it is used to 315 * store the FW's reply to the command. The command and its optional 316 * reply are of the same length. Some FW commands like RESET and 317 * INITIALIZE can take a considerable amount of time to execute. 318 * @sleep_ok determines whether we may sleep while awaiting the response. 319 * If sleeping is allowed we use progressive backoff otherwise we spin. 320 * Note that passing in a negative @timeout is an alternate mechanism 321 * for specifying @sleep_ok=false. This is useful when a higher level 322 * interface allows for specification of @timeout but not @sleep_ok ... 323 * 324 * The return value is 0 on success or a negative errno on failure. A 325 * failure can happen either because we are not able to execute the 326 * command or FW executes it but signals an error. In the latter case 327 * the return value is the error code indicated by FW (negated). 328 */ 329 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 330 int size, void *rpl, bool sleep_ok, int timeout) 331 { 332 /* 333 * We delay in small increments at first in an effort to maintain 334 * responsiveness for simple, fast executing commands but then back 335 * off to larger delays to a maximum retry delay. 336 */ 337 static const int delay[] = { 338 1, 1, 3, 5, 10, 10, 20, 50, 100 339 }; 340 u32 v; 341 u64 res; 342 int i, ms, delay_idx, ret, next_tx_check; 343 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 344 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 345 u32 ctl; 346 __be64 cmd_rpl[MBOX_LEN/8]; 347 u32 pcie_fw; 348 struct port_tx_state tx_state[MAX_NPORTS]; 349 350 if (adap->flags & CHK_MBOX_ACCESS) 351 ASSERT_SYNCHRONIZED_OP(adap); 352 353 if (size <= 0 || (size & 15) || size > MBOX_LEN) 354 return -EINVAL; 355 356 if (adap->flags & IS_VF) { 357 if (is_t6(adap)) 358 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 359 else 360 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 361 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 362 } 363 364 /* 365 * If we have a negative timeout, that implies that we can't sleep. 366 */ 367 if (timeout < 0) { 368 sleep_ok = false; 369 timeout = -timeout; 370 } 371 372 /* 373 * Attempt to gain access to the mailbox. 374 */ 375 for (i = 0; i < 4; i++) { 376 ctl = t4_read_reg(adap, ctl_reg); 377 v = G_MBOWNER(ctl); 378 if (v != X_MBOWNER_NONE) 379 break; 380 } 381 382 /* 383 * If we were unable to gain access, report the error to our caller. 384 */ 385 if (v != X_MBOWNER_PL) { 386 t4_report_fw_error(adap); 387 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 388 return ret; 389 } 390 391 /* 392 * If we gain ownership of the mailbox and there's a "valid" message 393 * in it, this is likely an asynchronous error message from the 394 * firmware. So we'll report that and then proceed on with attempting 395 * to issue our own command ... which may well fail if the error 396 * presaged the firmware crashing ... 397 */ 398 if (ctl & F_MBMSGVALID) { 399 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 400 } 401 402 /* 403 * Copy in the new mailbox command and send it on its way ... 404 */ 405 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 406 memcpy(cmd_rpl, cmd, size); 407 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 408 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 409 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 410 411 if (adap->flags & IS_VF) { 412 /* 413 * For the VFs, the Mailbox Data "registers" are 414 * actually backed by T4's "MA" interface rather than 415 * PL Registers (as is the case for the PFs). Because 416 * these are in different coherency domains, the write 417 * to the VF's PL-register-backed Mailbox Control can 418 * race in front of the writes to the MA-backed VF 419 * Mailbox Data "registers". So we need to do a 420 * read-back on at least one byte of the VF Mailbox 421 * Data registers before doing the write to the VF 422 * Mailbox Control register. 423 */ 424 t4_read_reg(adap, data_reg); 425 } 426 427 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 428 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 429 next_tx_check = 1000; 430 delay_idx = 0; 431 ms = delay[0]; 432 433 /* 434 * Loop waiting for the reply; bail out if we time out or the firmware 435 * reports an error. 436 */ 437 pcie_fw = 0; 438 for (i = 0; i < timeout; i += ms) { 439 if (!(adap->flags & IS_VF)) { 440 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 441 if (pcie_fw & F_PCIE_FW_ERR) 442 break; 443 } 444 445 if (i >= next_tx_check) { 446 check_tx_state(adap, &tx_state[0]); 447 next_tx_check = i + 1000; 448 } 449 450 if (sleep_ok) { 451 ms = delay[delay_idx]; /* last element may repeat */ 452 if (delay_idx < ARRAY_SIZE(delay) - 1) 453 delay_idx++; 454 msleep(ms); 455 } else { 456 mdelay(ms); 457 } 458 459 v = t4_read_reg(adap, ctl_reg); 460 if (v == X_CIM_PF_NOACCESS) 461 continue; 462 if (G_MBOWNER(v) == X_MBOWNER_PL) { 463 if (!(v & F_MBMSGVALID)) { 464 t4_write_reg(adap, ctl_reg, 465 V_MBOWNER(X_MBOWNER_NONE)); 466 continue; 467 } 468 469 /* 470 * Retrieve the command reply and release the mailbox. 471 */ 472 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 473 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 474 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 475 476 res = be64_to_cpu(cmd_rpl[0]); 477 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 478 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 479 res = V_FW_CMD_RETVAL(EIO); 480 } else if (rpl) 481 memcpy(rpl, cmd_rpl, size); 482 return -G_FW_CMD_RETVAL((int)res); 483 } 484 } 485 486 /* 487 * We timed out waiting for a reply to our mailbox command. Report 488 * the error and also check to see if the firmware reported any 489 * errors ... 490 */ 491 ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; 492 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 493 *(const u8 *)cmd, mbox, pcie_fw); 494 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 495 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 496 497 t4_report_fw_error(adap); 498 t4_fatal_err(adap, true); 499 return ret; 500 } 501 502 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 503 void *rpl, bool sleep_ok) 504 { 505 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 506 sleep_ok, FW_CMD_MAX_TIMEOUT); 507 508 } 509 510 static int t4_edc_err_read(struct adapter *adap, int idx) 511 { 512 u32 edc_ecc_err_addr_reg; 513 u32 edc_bist_status_rdata_reg; 514 515 if (is_t4(adap)) { 516 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 517 return 0; 518 } 519 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 520 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 521 return 0; 522 } 523 524 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 525 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 526 527 CH_WARN(adap, 528 "edc%d err addr 0x%x: 0x%x.\n", 529 idx, edc_ecc_err_addr_reg, 530 t4_read_reg(adap, edc_ecc_err_addr_reg)); 531 CH_WARN(adap, 532 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 533 edc_bist_status_rdata_reg, 534 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 535 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 536 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 537 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 538 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 539 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 540 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 541 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 543 544 return 0; 545 } 546 547 /** 548 * t4_mc_read - read from MC through backdoor accesses 549 * @adap: the adapter 550 * @idx: which MC to access 551 * @addr: address of first byte requested 552 * @data: 64 bytes of data containing the requested address 553 * @ecc: where to store the corresponding 64-bit ECC word 554 * 555 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 556 * that covers the requested address @addr. If @parity is not %NULL it 557 * is assigned the 64-bit ECC word for the read data. 558 */ 559 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 560 { 561 int i; 562 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 563 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 564 565 if (is_t4(adap)) { 566 mc_bist_cmd_reg = A_MC_BIST_CMD; 567 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 568 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 569 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 570 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 571 } else { 572 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 573 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 574 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 575 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 576 idx); 577 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 578 idx); 579 } 580 581 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 582 return -EBUSY; 583 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 584 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 585 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 586 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 587 F_START_BIST | V_BIST_CMD_GAP(1)); 588 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 589 if (i) 590 return i; 591 592 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 593 594 for (i = 15; i >= 0; i--) 595 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 596 if (ecc) 597 *ecc = t4_read_reg64(adap, MC_DATA(16)); 598 #undef MC_DATA 599 return 0; 600 } 601 602 /** 603 * t4_edc_read - read from EDC through backdoor accesses 604 * @adap: the adapter 605 * @idx: which EDC to access 606 * @addr: address of first byte requested 607 * @data: 64 bytes of data containing the requested address 608 * @ecc: where to store the corresponding 64-bit ECC word 609 * 610 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 611 * that covers the requested address @addr. If @parity is not %NULL it 612 * is assigned the 64-bit ECC word for the read data. 613 */ 614 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 615 { 616 int i; 617 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 618 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 619 620 if (is_t4(adap)) { 621 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 622 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 623 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 624 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 625 idx); 626 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 627 idx); 628 } else { 629 /* 630 * These macro are missing in t4_regs.h file. 631 * Added temporarily for testing. 632 */ 633 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 634 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 635 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 636 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 637 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 638 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 639 idx); 640 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 641 idx); 642 #undef EDC_REG_T5 643 #undef EDC_STRIDE_T5 644 } 645 646 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 647 return -EBUSY; 648 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 649 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 650 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 651 t4_write_reg(adap, edc_bist_cmd_reg, 652 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 653 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 654 if (i) 655 return i; 656 657 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 658 659 for (i = 15; i >= 0; i--) 660 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 661 if (ecc) 662 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 663 #undef EDC_DATA 664 return 0; 665 } 666 667 /** 668 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 669 * @adap: the adapter 670 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 671 * @addr: address within indicated memory type 672 * @len: amount of memory to read 673 * @buf: host memory buffer 674 * 675 * Reads an [almost] arbitrary memory region in the firmware: the 676 * firmware memory address, length and host buffer must be aligned on 677 * 32-bit boudaries. The memory is returned as a raw byte sequence from 678 * the firmware's memory. If this memory contains data structures which 679 * contain multi-byte integers, it's the callers responsibility to 680 * perform appropriate byte order conversions. 681 */ 682 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 683 __be32 *buf) 684 { 685 u32 pos, start, end, offset; 686 int ret; 687 688 /* 689 * Argument sanity checks ... 690 */ 691 if ((addr & 0x3) || (len & 0x3)) 692 return -EINVAL; 693 694 /* 695 * The underlaying EDC/MC read routines read 64 bytes at a time so we 696 * need to round down the start and round up the end. We'll start 697 * copying out of the first line at (addr - start) a word at a time. 698 */ 699 start = rounddown2(addr, 64); 700 end = roundup2(addr + len, 64); 701 offset = (addr - start)/sizeof(__be32); 702 703 for (pos = start; pos < end; pos += 64, offset = 0) { 704 __be32 data[16]; 705 706 /* 707 * Read the chip's memory block and bail if there's an error. 708 */ 709 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 710 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 711 else 712 ret = t4_edc_read(adap, mtype, pos, data, NULL); 713 if (ret) 714 return ret; 715 716 /* 717 * Copy the data into the caller's memory buffer. 718 */ 719 while (offset < 16 && len > 0) { 720 *buf++ = data[offset++]; 721 len -= sizeof(__be32); 722 } 723 } 724 725 return 0; 726 } 727 728 /* 729 * Return the specified PCI-E Configuration Space register from our Physical 730 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 731 * since we prefer to let the firmware own all of these registers, but if that 732 * fails we go for it directly ourselves. 733 */ 734 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 735 { 736 737 /* 738 * If fw_attach != 0, construct and send the Firmware LDST Command to 739 * retrieve the specified PCI-E Configuration Space register. 740 */ 741 if (drv_fw_attach != 0) { 742 struct fw_ldst_cmd ldst_cmd; 743 int ret; 744 745 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 746 ldst_cmd.op_to_addrspace = 747 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 748 F_FW_CMD_REQUEST | 749 F_FW_CMD_READ | 750 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 751 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 752 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 753 ldst_cmd.u.pcie.ctrl_to_fn = 754 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 755 ldst_cmd.u.pcie.r = reg; 756 757 /* 758 * If the LDST Command succeeds, return the result, otherwise 759 * fall through to reading it directly ourselves ... 760 */ 761 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 762 &ldst_cmd); 763 if (ret == 0) 764 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 765 766 CH_WARN(adap, "Firmware failed to return " 767 "Configuration Space register %d, err = %d\n", 768 reg, -ret); 769 } 770 771 /* 772 * Read the desired Configuration Space register via the PCI-E 773 * Backdoor mechanism. 774 */ 775 return t4_hw_pci_read_cfg4(adap, reg); 776 } 777 778 /** 779 * t4_get_regs_len - return the size of the chips register set 780 * @adapter: the adapter 781 * 782 * Returns the size of the chip's BAR0 register space. 783 */ 784 unsigned int t4_get_regs_len(struct adapter *adapter) 785 { 786 unsigned int chip_version = chip_id(adapter); 787 788 switch (chip_version) { 789 case CHELSIO_T4: 790 if (adapter->flags & IS_VF) 791 return FW_T4VF_REGMAP_SIZE; 792 return T4_REGMAP_SIZE; 793 794 case CHELSIO_T5: 795 case CHELSIO_T6: 796 if (adapter->flags & IS_VF) 797 return FW_T4VF_REGMAP_SIZE; 798 return T5_REGMAP_SIZE; 799 } 800 801 CH_ERR(adapter, 802 "Unsupported chip version %d\n", chip_version); 803 return 0; 804 } 805 806 /** 807 * t4_get_regs - read chip registers into provided buffer 808 * @adap: the adapter 809 * @buf: register buffer 810 * @buf_size: size (in bytes) of register buffer 811 * 812 * If the provided register buffer isn't large enough for the chip's 813 * full register range, the register dump will be truncated to the 814 * register buffer's size. 815 */ 816 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 817 { 818 static const unsigned int t4_reg_ranges[] = { 819 0x1008, 0x1108, 820 0x1180, 0x1184, 821 0x1190, 0x1194, 822 0x11a0, 0x11a4, 823 0x11b0, 0x11b4, 824 0x11fc, 0x123c, 825 0x1300, 0x173c, 826 0x1800, 0x18fc, 827 0x3000, 0x30d8, 828 0x30e0, 0x30e4, 829 0x30ec, 0x5910, 830 0x5920, 0x5924, 831 0x5960, 0x5960, 832 0x5968, 0x5968, 833 0x5970, 0x5970, 834 0x5978, 0x5978, 835 0x5980, 0x5980, 836 0x5988, 0x5988, 837 0x5990, 0x5990, 838 0x5998, 0x5998, 839 0x59a0, 0x59d4, 840 0x5a00, 0x5ae0, 841 0x5ae8, 0x5ae8, 842 0x5af0, 0x5af0, 843 0x5af8, 0x5af8, 844 0x6000, 0x6098, 845 0x6100, 0x6150, 846 0x6200, 0x6208, 847 0x6240, 0x6248, 848 0x6280, 0x62b0, 849 0x62c0, 0x6338, 850 0x6370, 0x638c, 851 0x6400, 0x643c, 852 0x6500, 0x6524, 853 0x6a00, 0x6a04, 854 0x6a14, 0x6a38, 855 0x6a60, 0x6a70, 856 0x6a78, 0x6a78, 857 0x6b00, 0x6b0c, 858 0x6b1c, 0x6b84, 859 0x6bf0, 0x6bf8, 860 0x6c00, 0x6c0c, 861 0x6c1c, 0x6c84, 862 0x6cf0, 0x6cf8, 863 0x6d00, 0x6d0c, 864 0x6d1c, 0x6d84, 865 0x6df0, 0x6df8, 866 0x6e00, 0x6e0c, 867 0x6e1c, 0x6e84, 868 0x6ef0, 0x6ef8, 869 0x6f00, 0x6f0c, 870 0x6f1c, 0x6f84, 871 0x6ff0, 0x6ff8, 872 0x7000, 0x700c, 873 0x701c, 0x7084, 874 0x70f0, 0x70f8, 875 0x7100, 0x710c, 876 0x711c, 0x7184, 877 0x71f0, 0x71f8, 878 0x7200, 0x720c, 879 0x721c, 0x7284, 880 0x72f0, 0x72f8, 881 0x7300, 0x730c, 882 0x731c, 0x7384, 883 0x73f0, 0x73f8, 884 0x7400, 0x7450, 885 0x7500, 0x7530, 886 0x7600, 0x760c, 887 0x7614, 0x761c, 888 0x7680, 0x76cc, 889 0x7700, 0x7798, 890 0x77c0, 0x77fc, 891 0x7900, 0x79fc, 892 0x7b00, 0x7b58, 893 0x7b60, 0x7b84, 894 0x7b8c, 0x7c38, 895 0x7d00, 0x7d38, 896 0x7d40, 0x7d80, 897 0x7d8c, 0x7ddc, 898 0x7de4, 0x7e04, 899 0x7e10, 0x7e1c, 900 0x7e24, 0x7e38, 901 0x7e40, 0x7e44, 902 0x7e4c, 0x7e78, 903 0x7e80, 0x7ea4, 904 0x7eac, 0x7edc, 905 0x7ee8, 0x7efc, 906 0x8dc0, 0x8e04, 907 0x8e10, 0x8e1c, 908 0x8e30, 0x8e78, 909 0x8ea0, 0x8eb8, 910 0x8ec0, 0x8f6c, 911 0x8fc0, 0x9008, 912 0x9010, 0x9058, 913 0x9060, 0x9060, 914 0x9068, 0x9074, 915 0x90fc, 0x90fc, 916 0x9400, 0x9408, 917 0x9410, 0x9458, 918 0x9600, 0x9600, 919 0x9608, 0x9638, 920 0x9640, 0x96bc, 921 0x9800, 0x9808, 922 0x9820, 0x983c, 923 0x9850, 0x9864, 924 0x9c00, 0x9c6c, 925 0x9c80, 0x9cec, 926 0x9d00, 0x9d6c, 927 0x9d80, 0x9dec, 928 0x9e00, 0x9e6c, 929 0x9e80, 0x9eec, 930 0x9f00, 0x9f6c, 931 0x9f80, 0x9fec, 932 0xd004, 0xd004, 933 0xd010, 0xd03c, 934 0xdfc0, 0xdfe0, 935 0xe000, 0xea7c, 936 0xf000, 0x11110, 937 0x11118, 0x11190, 938 0x19040, 0x1906c, 939 0x19078, 0x19080, 940 0x1908c, 0x190e4, 941 0x190f0, 0x190f8, 942 0x19100, 0x19110, 943 0x19120, 0x19124, 944 0x19150, 0x19194, 945 0x1919c, 0x191b0, 946 0x191d0, 0x191e8, 947 0x19238, 0x1924c, 948 0x193f8, 0x1943c, 949 0x1944c, 0x19474, 950 0x19490, 0x194e0, 951 0x194f0, 0x194f8, 952 0x19800, 0x19c08, 953 0x19c10, 0x19c90, 954 0x19ca0, 0x19ce4, 955 0x19cf0, 0x19d40, 956 0x19d50, 0x19d94, 957 0x19da0, 0x19de8, 958 0x19df0, 0x19e40, 959 0x19e50, 0x19e90, 960 0x19ea0, 0x19f4c, 961 0x1a000, 0x1a004, 962 0x1a010, 0x1a06c, 963 0x1a0b0, 0x1a0e4, 964 0x1a0ec, 0x1a0f4, 965 0x1a100, 0x1a108, 966 0x1a114, 0x1a120, 967 0x1a128, 0x1a130, 968 0x1a138, 0x1a138, 969 0x1a190, 0x1a1c4, 970 0x1a1fc, 0x1a1fc, 971 0x1e040, 0x1e04c, 972 0x1e284, 0x1e28c, 973 0x1e2c0, 0x1e2c0, 974 0x1e2e0, 0x1e2e0, 975 0x1e300, 0x1e384, 976 0x1e3c0, 0x1e3c8, 977 0x1e440, 0x1e44c, 978 0x1e684, 0x1e68c, 979 0x1e6c0, 0x1e6c0, 980 0x1e6e0, 0x1e6e0, 981 0x1e700, 0x1e784, 982 0x1e7c0, 0x1e7c8, 983 0x1e840, 0x1e84c, 984 0x1ea84, 0x1ea8c, 985 0x1eac0, 0x1eac0, 986 0x1eae0, 0x1eae0, 987 0x1eb00, 0x1eb84, 988 0x1ebc0, 0x1ebc8, 989 0x1ec40, 0x1ec4c, 990 0x1ee84, 0x1ee8c, 991 0x1eec0, 0x1eec0, 992 0x1eee0, 0x1eee0, 993 0x1ef00, 0x1ef84, 994 0x1efc0, 0x1efc8, 995 0x1f040, 0x1f04c, 996 0x1f284, 0x1f28c, 997 0x1f2c0, 0x1f2c0, 998 0x1f2e0, 0x1f2e0, 999 0x1f300, 0x1f384, 1000 0x1f3c0, 0x1f3c8, 1001 0x1f440, 0x1f44c, 1002 0x1f684, 0x1f68c, 1003 0x1f6c0, 0x1f6c0, 1004 0x1f6e0, 0x1f6e0, 1005 0x1f700, 0x1f784, 1006 0x1f7c0, 0x1f7c8, 1007 0x1f840, 0x1f84c, 1008 0x1fa84, 0x1fa8c, 1009 0x1fac0, 0x1fac0, 1010 0x1fae0, 0x1fae0, 1011 0x1fb00, 0x1fb84, 1012 0x1fbc0, 0x1fbc8, 1013 0x1fc40, 0x1fc4c, 1014 0x1fe84, 0x1fe8c, 1015 0x1fec0, 0x1fec0, 1016 0x1fee0, 0x1fee0, 1017 0x1ff00, 0x1ff84, 1018 0x1ffc0, 0x1ffc8, 1019 0x20000, 0x2002c, 1020 0x20100, 0x2013c, 1021 0x20190, 0x201a0, 1022 0x201a8, 0x201b8, 1023 0x201c4, 0x201c8, 1024 0x20200, 0x20318, 1025 0x20400, 0x204b4, 1026 0x204c0, 0x20528, 1027 0x20540, 0x20614, 1028 0x21000, 0x21040, 1029 0x2104c, 0x21060, 1030 0x210c0, 0x210ec, 1031 0x21200, 0x21268, 1032 0x21270, 0x21284, 1033 0x212fc, 0x21388, 1034 0x21400, 0x21404, 1035 0x21500, 0x21500, 1036 0x21510, 0x21518, 1037 0x2152c, 0x21530, 1038 0x2153c, 0x2153c, 1039 0x21550, 0x21554, 1040 0x21600, 0x21600, 1041 0x21608, 0x2161c, 1042 0x21624, 0x21628, 1043 0x21630, 0x21634, 1044 0x2163c, 0x2163c, 1045 0x21700, 0x2171c, 1046 0x21780, 0x2178c, 1047 0x21800, 0x21818, 1048 0x21820, 0x21828, 1049 0x21830, 0x21848, 1050 0x21850, 0x21854, 1051 0x21860, 0x21868, 1052 0x21870, 0x21870, 1053 0x21878, 0x21898, 1054 0x218a0, 0x218a8, 1055 0x218b0, 0x218c8, 1056 0x218d0, 0x218d4, 1057 0x218e0, 0x218e8, 1058 0x218f0, 0x218f0, 1059 0x218f8, 0x21a18, 1060 0x21a20, 0x21a28, 1061 0x21a30, 0x21a48, 1062 0x21a50, 0x21a54, 1063 0x21a60, 0x21a68, 1064 0x21a70, 0x21a70, 1065 0x21a78, 0x21a98, 1066 0x21aa0, 0x21aa8, 1067 0x21ab0, 0x21ac8, 1068 0x21ad0, 0x21ad4, 1069 0x21ae0, 0x21ae8, 1070 0x21af0, 0x21af0, 1071 0x21af8, 0x21c18, 1072 0x21c20, 0x21c20, 1073 0x21c28, 0x21c30, 1074 0x21c38, 0x21c38, 1075 0x21c80, 0x21c98, 1076 0x21ca0, 0x21ca8, 1077 0x21cb0, 0x21cc8, 1078 0x21cd0, 0x21cd4, 1079 0x21ce0, 0x21ce8, 1080 0x21cf0, 0x21cf0, 1081 0x21cf8, 0x21d7c, 1082 0x21e00, 0x21e04, 1083 0x22000, 0x2202c, 1084 0x22100, 0x2213c, 1085 0x22190, 0x221a0, 1086 0x221a8, 0x221b8, 1087 0x221c4, 0x221c8, 1088 0x22200, 0x22318, 1089 0x22400, 0x224b4, 1090 0x224c0, 0x22528, 1091 0x22540, 0x22614, 1092 0x23000, 0x23040, 1093 0x2304c, 0x23060, 1094 0x230c0, 0x230ec, 1095 0x23200, 0x23268, 1096 0x23270, 0x23284, 1097 0x232fc, 0x23388, 1098 0x23400, 0x23404, 1099 0x23500, 0x23500, 1100 0x23510, 0x23518, 1101 0x2352c, 0x23530, 1102 0x2353c, 0x2353c, 1103 0x23550, 0x23554, 1104 0x23600, 0x23600, 1105 0x23608, 0x2361c, 1106 0x23624, 0x23628, 1107 0x23630, 0x23634, 1108 0x2363c, 0x2363c, 1109 0x23700, 0x2371c, 1110 0x23780, 0x2378c, 1111 0x23800, 0x23818, 1112 0x23820, 0x23828, 1113 0x23830, 0x23848, 1114 0x23850, 0x23854, 1115 0x23860, 0x23868, 1116 0x23870, 0x23870, 1117 0x23878, 0x23898, 1118 0x238a0, 0x238a8, 1119 0x238b0, 0x238c8, 1120 0x238d0, 0x238d4, 1121 0x238e0, 0x238e8, 1122 0x238f0, 0x238f0, 1123 0x238f8, 0x23a18, 1124 0x23a20, 0x23a28, 1125 0x23a30, 0x23a48, 1126 0x23a50, 0x23a54, 1127 0x23a60, 0x23a68, 1128 0x23a70, 0x23a70, 1129 0x23a78, 0x23a98, 1130 0x23aa0, 0x23aa8, 1131 0x23ab0, 0x23ac8, 1132 0x23ad0, 0x23ad4, 1133 0x23ae0, 0x23ae8, 1134 0x23af0, 0x23af0, 1135 0x23af8, 0x23c18, 1136 0x23c20, 0x23c20, 1137 0x23c28, 0x23c30, 1138 0x23c38, 0x23c38, 1139 0x23c80, 0x23c98, 1140 0x23ca0, 0x23ca8, 1141 0x23cb0, 0x23cc8, 1142 0x23cd0, 0x23cd4, 1143 0x23ce0, 0x23ce8, 1144 0x23cf0, 0x23cf0, 1145 0x23cf8, 0x23d7c, 1146 0x23e00, 0x23e04, 1147 0x24000, 0x2402c, 1148 0x24100, 0x2413c, 1149 0x24190, 0x241a0, 1150 0x241a8, 0x241b8, 1151 0x241c4, 0x241c8, 1152 0x24200, 0x24318, 1153 0x24400, 0x244b4, 1154 0x244c0, 0x24528, 1155 0x24540, 0x24614, 1156 0x25000, 0x25040, 1157 0x2504c, 0x25060, 1158 0x250c0, 0x250ec, 1159 0x25200, 0x25268, 1160 0x25270, 0x25284, 1161 0x252fc, 0x25388, 1162 0x25400, 0x25404, 1163 0x25500, 0x25500, 1164 0x25510, 0x25518, 1165 0x2552c, 0x25530, 1166 0x2553c, 0x2553c, 1167 0x25550, 0x25554, 1168 0x25600, 0x25600, 1169 0x25608, 0x2561c, 1170 0x25624, 0x25628, 1171 0x25630, 0x25634, 1172 0x2563c, 0x2563c, 1173 0x25700, 0x2571c, 1174 0x25780, 0x2578c, 1175 0x25800, 0x25818, 1176 0x25820, 0x25828, 1177 0x25830, 0x25848, 1178 0x25850, 0x25854, 1179 0x25860, 0x25868, 1180 0x25870, 0x25870, 1181 0x25878, 0x25898, 1182 0x258a0, 0x258a8, 1183 0x258b0, 0x258c8, 1184 0x258d0, 0x258d4, 1185 0x258e0, 0x258e8, 1186 0x258f0, 0x258f0, 1187 0x258f8, 0x25a18, 1188 0x25a20, 0x25a28, 1189 0x25a30, 0x25a48, 1190 0x25a50, 0x25a54, 1191 0x25a60, 0x25a68, 1192 0x25a70, 0x25a70, 1193 0x25a78, 0x25a98, 1194 0x25aa0, 0x25aa8, 1195 0x25ab0, 0x25ac8, 1196 0x25ad0, 0x25ad4, 1197 0x25ae0, 0x25ae8, 1198 0x25af0, 0x25af0, 1199 0x25af8, 0x25c18, 1200 0x25c20, 0x25c20, 1201 0x25c28, 0x25c30, 1202 0x25c38, 0x25c38, 1203 0x25c80, 0x25c98, 1204 0x25ca0, 0x25ca8, 1205 0x25cb0, 0x25cc8, 1206 0x25cd0, 0x25cd4, 1207 0x25ce0, 0x25ce8, 1208 0x25cf0, 0x25cf0, 1209 0x25cf8, 0x25d7c, 1210 0x25e00, 0x25e04, 1211 0x26000, 0x2602c, 1212 0x26100, 0x2613c, 1213 0x26190, 0x261a0, 1214 0x261a8, 0x261b8, 1215 0x261c4, 0x261c8, 1216 0x26200, 0x26318, 1217 0x26400, 0x264b4, 1218 0x264c0, 0x26528, 1219 0x26540, 0x26614, 1220 0x27000, 0x27040, 1221 0x2704c, 0x27060, 1222 0x270c0, 0x270ec, 1223 0x27200, 0x27268, 1224 0x27270, 0x27284, 1225 0x272fc, 0x27388, 1226 0x27400, 0x27404, 1227 0x27500, 0x27500, 1228 0x27510, 0x27518, 1229 0x2752c, 0x27530, 1230 0x2753c, 0x2753c, 1231 0x27550, 0x27554, 1232 0x27600, 0x27600, 1233 0x27608, 0x2761c, 1234 0x27624, 0x27628, 1235 0x27630, 0x27634, 1236 0x2763c, 0x2763c, 1237 0x27700, 0x2771c, 1238 0x27780, 0x2778c, 1239 0x27800, 0x27818, 1240 0x27820, 0x27828, 1241 0x27830, 0x27848, 1242 0x27850, 0x27854, 1243 0x27860, 0x27868, 1244 0x27870, 0x27870, 1245 0x27878, 0x27898, 1246 0x278a0, 0x278a8, 1247 0x278b0, 0x278c8, 1248 0x278d0, 0x278d4, 1249 0x278e0, 0x278e8, 1250 0x278f0, 0x278f0, 1251 0x278f8, 0x27a18, 1252 0x27a20, 0x27a28, 1253 0x27a30, 0x27a48, 1254 0x27a50, 0x27a54, 1255 0x27a60, 0x27a68, 1256 0x27a70, 0x27a70, 1257 0x27a78, 0x27a98, 1258 0x27aa0, 0x27aa8, 1259 0x27ab0, 0x27ac8, 1260 0x27ad0, 0x27ad4, 1261 0x27ae0, 0x27ae8, 1262 0x27af0, 0x27af0, 1263 0x27af8, 0x27c18, 1264 0x27c20, 0x27c20, 1265 0x27c28, 0x27c30, 1266 0x27c38, 0x27c38, 1267 0x27c80, 0x27c98, 1268 0x27ca0, 0x27ca8, 1269 0x27cb0, 0x27cc8, 1270 0x27cd0, 0x27cd4, 1271 0x27ce0, 0x27ce8, 1272 0x27cf0, 0x27cf0, 1273 0x27cf8, 0x27d7c, 1274 0x27e00, 0x27e04, 1275 }; 1276 1277 static const unsigned int t4vf_reg_ranges[] = { 1278 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1279 VF_MPS_REG(A_MPS_VF_CTL), 1280 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1281 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1282 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1283 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1284 FW_T4VF_MBDATA_BASE_ADDR, 1285 FW_T4VF_MBDATA_BASE_ADDR + 1286 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1287 }; 1288 1289 static const unsigned int t5_reg_ranges[] = { 1290 0x1008, 0x10c0, 1291 0x10cc, 0x10f8, 1292 0x1100, 0x1100, 1293 0x110c, 0x1148, 1294 0x1180, 0x1184, 1295 0x1190, 0x1194, 1296 0x11a0, 0x11a4, 1297 0x11b0, 0x11b4, 1298 0x11fc, 0x123c, 1299 0x1280, 0x173c, 1300 0x1800, 0x18fc, 1301 0x3000, 0x3028, 1302 0x3060, 0x30b0, 1303 0x30b8, 0x30d8, 1304 0x30e0, 0x30fc, 1305 0x3140, 0x357c, 1306 0x35a8, 0x35cc, 1307 0x35ec, 0x35ec, 1308 0x3600, 0x5624, 1309 0x56cc, 0x56ec, 1310 0x56f4, 0x5720, 1311 0x5728, 0x575c, 1312 0x580c, 0x5814, 1313 0x5890, 0x589c, 1314 0x58a4, 0x58ac, 1315 0x58b8, 0x58bc, 1316 0x5940, 0x59c8, 1317 0x59d0, 0x59dc, 1318 0x59fc, 0x5a18, 1319 0x5a60, 0x5a70, 1320 0x5a80, 0x5a9c, 1321 0x5b94, 0x5bfc, 1322 0x6000, 0x6020, 1323 0x6028, 0x6040, 1324 0x6058, 0x609c, 1325 0x60a8, 0x614c, 1326 0x7700, 0x7798, 1327 0x77c0, 0x78fc, 1328 0x7b00, 0x7b58, 1329 0x7b60, 0x7b84, 1330 0x7b8c, 0x7c54, 1331 0x7d00, 0x7d38, 1332 0x7d40, 0x7d80, 1333 0x7d8c, 0x7ddc, 1334 0x7de4, 0x7e04, 1335 0x7e10, 0x7e1c, 1336 0x7e24, 0x7e38, 1337 0x7e40, 0x7e44, 1338 0x7e4c, 0x7e78, 1339 0x7e80, 0x7edc, 1340 0x7ee8, 0x7efc, 1341 0x8dc0, 0x8de0, 1342 0x8df8, 0x8e04, 1343 0x8e10, 0x8e84, 1344 0x8ea0, 0x8f84, 1345 0x8fc0, 0x9058, 1346 0x9060, 0x9060, 1347 0x9068, 0x90f8, 1348 0x9400, 0x9408, 1349 0x9410, 0x9470, 1350 0x9600, 0x9600, 1351 0x9608, 0x9638, 1352 0x9640, 0x96f4, 1353 0x9800, 0x9808, 1354 0x9820, 0x983c, 1355 0x9850, 0x9864, 1356 0x9c00, 0x9c6c, 1357 0x9c80, 0x9cec, 1358 0x9d00, 0x9d6c, 1359 0x9d80, 0x9dec, 1360 0x9e00, 0x9e6c, 1361 0x9e80, 0x9eec, 1362 0x9f00, 0x9f6c, 1363 0x9f80, 0xa020, 1364 0xd004, 0xd004, 1365 0xd010, 0xd03c, 1366 0xdfc0, 0xdfe0, 1367 0xe000, 0x1106c, 1368 0x11074, 0x11088, 1369 0x1109c, 0x1117c, 1370 0x11190, 0x11204, 1371 0x19040, 0x1906c, 1372 0x19078, 0x19080, 1373 0x1908c, 0x190e8, 1374 0x190f0, 0x190f8, 1375 0x19100, 0x19110, 1376 0x19120, 0x19124, 1377 0x19150, 0x19194, 1378 0x1919c, 0x191b0, 1379 0x191d0, 0x191e8, 1380 0x19238, 0x19290, 1381 0x193f8, 0x19428, 1382 0x19430, 0x19444, 1383 0x1944c, 0x1946c, 1384 0x19474, 0x19474, 1385 0x19490, 0x194cc, 1386 0x194f0, 0x194f8, 1387 0x19c00, 0x19c08, 1388 0x19c10, 0x19c60, 1389 0x19c94, 0x19ce4, 1390 0x19cf0, 0x19d40, 1391 0x19d50, 0x19d94, 1392 0x19da0, 0x19de8, 1393 0x19df0, 0x19e10, 1394 0x19e50, 0x19e90, 1395 0x19ea0, 0x19f24, 1396 0x19f34, 0x19f34, 1397 0x19f40, 0x19f50, 1398 0x19f90, 0x19fb4, 1399 0x19fc4, 0x19fe4, 1400 0x1a000, 0x1a004, 1401 0x1a010, 0x1a06c, 1402 0x1a0b0, 0x1a0e4, 1403 0x1a0ec, 0x1a0f8, 1404 0x1a100, 0x1a108, 1405 0x1a114, 0x1a120, 1406 0x1a128, 0x1a130, 1407 0x1a138, 0x1a138, 1408 0x1a190, 0x1a1c4, 1409 0x1a1fc, 0x1a1fc, 1410 0x1e008, 0x1e00c, 1411 0x1e040, 0x1e044, 1412 0x1e04c, 0x1e04c, 1413 0x1e284, 0x1e290, 1414 0x1e2c0, 0x1e2c0, 1415 0x1e2e0, 0x1e2e0, 1416 0x1e300, 0x1e384, 1417 0x1e3c0, 0x1e3c8, 1418 0x1e408, 0x1e40c, 1419 0x1e440, 0x1e444, 1420 0x1e44c, 0x1e44c, 1421 0x1e684, 0x1e690, 1422 0x1e6c0, 0x1e6c0, 1423 0x1e6e0, 0x1e6e0, 1424 0x1e700, 0x1e784, 1425 0x1e7c0, 0x1e7c8, 1426 0x1e808, 0x1e80c, 1427 0x1e840, 0x1e844, 1428 0x1e84c, 0x1e84c, 1429 0x1ea84, 0x1ea90, 1430 0x1eac0, 0x1eac0, 1431 0x1eae0, 0x1eae0, 1432 0x1eb00, 0x1eb84, 1433 0x1ebc0, 0x1ebc8, 1434 0x1ec08, 0x1ec0c, 1435 0x1ec40, 0x1ec44, 1436 0x1ec4c, 0x1ec4c, 1437 0x1ee84, 0x1ee90, 1438 0x1eec0, 0x1eec0, 1439 0x1eee0, 0x1eee0, 1440 0x1ef00, 0x1ef84, 1441 0x1efc0, 0x1efc8, 1442 0x1f008, 0x1f00c, 1443 0x1f040, 0x1f044, 1444 0x1f04c, 0x1f04c, 1445 0x1f284, 0x1f290, 1446 0x1f2c0, 0x1f2c0, 1447 0x1f2e0, 0x1f2e0, 1448 0x1f300, 0x1f384, 1449 0x1f3c0, 0x1f3c8, 1450 0x1f408, 0x1f40c, 1451 0x1f440, 0x1f444, 1452 0x1f44c, 0x1f44c, 1453 0x1f684, 0x1f690, 1454 0x1f6c0, 0x1f6c0, 1455 0x1f6e0, 0x1f6e0, 1456 0x1f700, 0x1f784, 1457 0x1f7c0, 0x1f7c8, 1458 0x1f808, 0x1f80c, 1459 0x1f840, 0x1f844, 1460 0x1f84c, 0x1f84c, 1461 0x1fa84, 0x1fa90, 1462 0x1fac0, 0x1fac0, 1463 0x1fae0, 0x1fae0, 1464 0x1fb00, 0x1fb84, 1465 0x1fbc0, 0x1fbc8, 1466 0x1fc08, 0x1fc0c, 1467 0x1fc40, 0x1fc44, 1468 0x1fc4c, 0x1fc4c, 1469 0x1fe84, 0x1fe90, 1470 0x1fec0, 0x1fec0, 1471 0x1fee0, 0x1fee0, 1472 0x1ff00, 0x1ff84, 1473 0x1ffc0, 0x1ffc8, 1474 0x30000, 0x30030, 1475 0x30100, 0x30144, 1476 0x30190, 0x301a0, 1477 0x301a8, 0x301b8, 1478 0x301c4, 0x301c8, 1479 0x301d0, 0x301d0, 1480 0x30200, 0x30318, 1481 0x30400, 0x304b4, 1482 0x304c0, 0x3052c, 1483 0x30540, 0x3061c, 1484 0x30800, 0x30828, 1485 0x30834, 0x30834, 1486 0x308c0, 0x30908, 1487 0x30910, 0x309ac, 1488 0x30a00, 0x30a14, 1489 0x30a1c, 0x30a2c, 1490 0x30a44, 0x30a50, 1491 0x30a74, 0x30a74, 1492 0x30a7c, 0x30afc, 1493 0x30b08, 0x30c24, 1494 0x30d00, 0x30d00, 1495 0x30d08, 0x30d14, 1496 0x30d1c, 0x30d20, 1497 0x30d3c, 0x30d3c, 1498 0x30d48, 0x30d50, 1499 0x31200, 0x3120c, 1500 0x31220, 0x31220, 1501 0x31240, 0x31240, 1502 0x31600, 0x3160c, 1503 0x31a00, 0x31a1c, 1504 0x31e00, 0x31e20, 1505 0x31e38, 0x31e3c, 1506 0x31e80, 0x31e80, 1507 0x31e88, 0x31ea8, 1508 0x31eb0, 0x31eb4, 1509 0x31ec8, 0x31ed4, 1510 0x31fb8, 0x32004, 1511 0x32200, 0x32200, 1512 0x32208, 0x32240, 1513 0x32248, 0x32280, 1514 0x32288, 0x322c0, 1515 0x322c8, 0x322fc, 1516 0x32600, 0x32630, 1517 0x32a00, 0x32abc, 1518 0x32b00, 0x32b10, 1519 0x32b20, 0x32b30, 1520 0x32b40, 0x32b50, 1521 0x32b60, 0x32b70, 1522 0x33000, 0x33028, 1523 0x33030, 0x33048, 1524 0x33060, 0x33068, 1525 0x33070, 0x3309c, 1526 0x330f0, 0x33128, 1527 0x33130, 0x33148, 1528 0x33160, 0x33168, 1529 0x33170, 0x3319c, 1530 0x331f0, 0x33238, 1531 0x33240, 0x33240, 1532 0x33248, 0x33250, 1533 0x3325c, 0x33264, 1534 0x33270, 0x332b8, 1535 0x332c0, 0x332e4, 1536 0x332f8, 0x33338, 1537 0x33340, 0x33340, 1538 0x33348, 0x33350, 1539 0x3335c, 0x33364, 1540 0x33370, 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1584 0x34000, 0x34030, 1585 0x34100, 0x34144, 1586 0x34190, 0x341a0, 1587 0x341a8, 0x341b8, 1588 0x341c4, 0x341c8, 1589 0x341d0, 0x341d0, 1590 0x34200, 0x34318, 1591 0x34400, 0x344b4, 1592 0x344c0, 0x3452c, 1593 0x34540, 0x3461c, 1594 0x34800, 0x34828, 1595 0x34834, 0x34834, 1596 0x348c0, 0x34908, 1597 0x34910, 0x349ac, 1598 0x34a00, 0x34a14, 1599 0x34a1c, 0x34a2c, 1600 0x34a44, 0x34a50, 1601 0x34a74, 0x34a74, 1602 0x34a7c, 0x34afc, 1603 0x34b08, 0x34c24, 1604 0x34d00, 0x34d00, 1605 0x34d08, 0x34d14, 1606 0x34d1c, 0x34d20, 1607 0x34d3c, 0x34d3c, 1608 0x34d48, 0x34d50, 1609 0x35200, 0x3520c, 1610 0x35220, 0x35220, 1611 0x35240, 0x35240, 1612 0x35600, 0x3560c, 1613 0x35a00, 0x35a1c, 1614 0x35e00, 0x35e20, 1615 0x35e38, 0x35e3c, 1616 0x35e80, 0x35e80, 1617 0x35e88, 0x35ea8, 1618 0x35eb0, 0x35eb4, 1619 0x35ec8, 0x35ed4, 1620 0x35fb8, 0x36004, 1621 0x36200, 0x36200, 1622 0x36208, 0x36240, 1623 0x36248, 0x36280, 1624 0x36288, 0x362c0, 1625 0x362c8, 0x362fc, 1626 0x36600, 0x36630, 1627 0x36a00, 0x36abc, 1628 0x36b00, 0x36b10, 1629 0x36b20, 0x36b30, 1630 0x36b40, 0x36b50, 1631 0x36b60, 0x36b70, 1632 0x37000, 0x37028, 1633 0x37030, 0x37048, 1634 0x37060, 0x37068, 1635 0x37070, 0x3709c, 1636 0x370f0, 0x37128, 1637 0x37130, 0x37148, 1638 0x37160, 0x37168, 1639 0x37170, 0x3719c, 1640 0x371f0, 0x37238, 1641 0x37240, 0x37240, 1642 0x37248, 0x37250, 1643 0x3725c, 0x37264, 1644 0x37270, 0x372b8, 1645 0x372c0, 0x372e4, 1646 0x372f8, 0x37338, 1647 0x37340, 0x37340, 1648 0x37348, 0x37350, 1649 0x3735c, 0x37364, 1650 0x37370, 0x373b8, 1651 0x373c0, 0x373e4, 1652 0x373f8, 0x37428, 1653 0x37430, 0x37448, 1654 0x37460, 0x37468, 1655 0x37470, 0x3749c, 1656 0x374f0, 0x37528, 1657 0x37530, 0x37548, 1658 0x37560, 0x37568, 1659 0x37570, 0x3759c, 1660 0x375f0, 0x37638, 1661 0x37640, 0x37640, 1662 0x37648, 0x37650, 1663 0x3765c, 0x37664, 1664 0x37670, 0x376b8, 1665 0x376c0, 0x376e4, 1666 0x376f8, 0x37738, 1667 0x37740, 0x37740, 1668 0x37748, 0x37750, 1669 0x3775c, 0x37764, 1670 0x37770, 0x377b8, 1671 0x377c0, 0x377e4, 1672 0x377f8, 0x377fc, 1673 0x37814, 0x37814, 1674 0x3782c, 0x3782c, 1675 0x37880, 0x3788c, 1676 0x378e8, 0x378ec, 1677 0x37900, 0x37928, 1678 0x37930, 0x37948, 1679 0x37960, 0x37968, 1680 0x37970, 0x3799c, 1681 0x379f0, 0x37a38, 1682 0x37a40, 0x37a40, 1683 0x37a48, 0x37a50, 1684 0x37a5c, 0x37a64, 1685 0x37a70, 0x37ab8, 1686 0x37ac0, 0x37ae4, 1687 0x37af8, 0x37b10, 1688 0x37b28, 0x37b28, 1689 0x37b3c, 0x37b50, 1690 0x37bf0, 0x37c10, 1691 0x37c28, 0x37c28, 1692 0x37c3c, 0x37c50, 1693 0x37cf0, 0x37cfc, 1694 0x38000, 0x38030, 1695 0x38100, 0x38144, 1696 0x38190, 0x381a0, 1697 0x381a8, 0x381b8, 1698 0x381c4, 0x381c8, 1699 0x381d0, 0x381d0, 1700 0x38200, 0x38318, 1701 0x38400, 0x384b4, 1702 0x384c0, 0x3852c, 1703 0x38540, 0x3861c, 1704 0x38800, 0x38828, 1705 0x38834, 0x38834, 1706 0x388c0, 0x38908, 1707 0x38910, 0x389ac, 1708 0x38a00, 0x38a14, 1709 0x38a1c, 0x38a2c, 1710 0x38a44, 0x38a50, 1711 0x38a74, 0x38a74, 1712 0x38a7c, 0x38afc, 1713 0x38b08, 0x38c24, 1714 0x38d00, 0x38d00, 1715 0x38d08, 0x38d14, 1716 0x38d1c, 0x38d20, 1717 0x38d3c, 0x38d3c, 1718 0x38d48, 0x38d50, 1719 0x39200, 0x3920c, 1720 0x39220, 0x39220, 1721 0x39240, 0x39240, 1722 0x39600, 0x3960c, 1723 0x39a00, 0x39a1c, 1724 0x39e00, 0x39e20, 1725 0x39e38, 0x39e3c, 1726 0x39e80, 0x39e80, 1727 0x39e88, 0x39ea8, 1728 0x39eb0, 0x39eb4, 1729 0x39ec8, 0x39ed4, 1730 0x39fb8, 0x3a004, 1731 0x3a200, 0x3a200, 1732 0x3a208, 0x3a240, 1733 0x3a248, 0x3a280, 1734 0x3a288, 0x3a2c0, 1735 0x3a2c8, 0x3a2fc, 1736 0x3a600, 0x3a630, 1737 0x3aa00, 0x3aabc, 1738 0x3ab00, 0x3ab10, 1739 0x3ab20, 0x3ab30, 1740 0x3ab40, 0x3ab50, 1741 0x3ab60, 0x3ab70, 1742 0x3b000, 0x3b028, 1743 0x3b030, 0x3b048, 1744 0x3b060, 0x3b068, 1745 0x3b070, 0x3b09c, 1746 0x3b0f0, 0x3b128, 1747 0x3b130, 0x3b148, 1748 0x3b160, 0x3b168, 1749 0x3b170, 0x3b19c, 1750 0x3b1f0, 0x3b238, 1751 0x3b240, 0x3b240, 1752 0x3b248, 0x3b250, 1753 0x3b25c, 0x3b264, 1754 0x3b270, 0x3b2b8, 1755 0x3b2c0, 0x3b2e4, 1756 0x3b2f8, 0x3b338, 1757 0x3b340, 0x3b340, 1758 0x3b348, 0x3b350, 1759 0x3b35c, 0x3b364, 1760 0x3b370, 0x3b3b8, 1761 0x3b3c0, 0x3b3e4, 1762 0x3b3f8, 0x3b428, 1763 0x3b430, 0x3b448, 1764 0x3b460, 0x3b468, 1765 0x3b470, 0x3b49c, 1766 0x3b4f0, 0x3b528, 1767 0x3b530, 0x3b548, 1768 0x3b560, 0x3b568, 1769 0x3b570, 0x3b59c, 1770 0x3b5f0, 0x3b638, 1771 0x3b640, 0x3b640, 1772 0x3b648, 0x3b650, 1773 0x3b65c, 0x3b664, 1774 0x3b670, 0x3b6b8, 1775 0x3b6c0, 0x3b6e4, 1776 0x3b6f8, 0x3b738, 1777 0x3b740, 0x3b740, 1778 0x3b748, 0x3b750, 1779 0x3b75c, 0x3b764, 1780 0x3b770, 0x3b7b8, 1781 0x3b7c0, 0x3b7e4, 1782 0x3b7f8, 0x3b7fc, 1783 0x3b814, 0x3b814, 1784 0x3b82c, 0x3b82c, 1785 0x3b880, 0x3b88c, 1786 0x3b8e8, 0x3b8ec, 1787 0x3b900, 0x3b928, 1788 0x3b930, 0x3b948, 1789 0x3b960, 0x3b968, 1790 0x3b970, 0x3b99c, 1791 0x3b9f0, 0x3ba38, 1792 0x3ba40, 0x3ba40, 1793 0x3ba48, 0x3ba50, 1794 0x3ba5c, 0x3ba64, 1795 0x3ba70, 0x3bab8, 1796 0x3bac0, 0x3bae4, 1797 0x3baf8, 0x3bb10, 1798 0x3bb28, 0x3bb28, 1799 0x3bb3c, 0x3bb50, 1800 0x3bbf0, 0x3bc10, 1801 0x3bc28, 0x3bc28, 1802 0x3bc3c, 0x3bc50, 1803 0x3bcf0, 0x3bcfc, 1804 0x3c000, 0x3c030, 1805 0x3c100, 0x3c144, 1806 0x3c190, 0x3c1a0, 1807 0x3c1a8, 0x3c1b8, 1808 0x3c1c4, 0x3c1c8, 1809 0x3c1d0, 0x3c1d0, 1810 0x3c200, 0x3c318, 1811 0x3c400, 0x3c4b4, 1812 0x3c4c0, 0x3c52c, 1813 0x3c540, 0x3c61c, 1814 0x3c800, 0x3c828, 1815 0x3c834, 0x3c834, 1816 0x3c8c0, 0x3c908, 1817 0x3c910, 0x3c9ac, 1818 0x3ca00, 0x3ca14, 1819 0x3ca1c, 0x3ca2c, 1820 0x3ca44, 0x3ca50, 1821 0x3ca74, 0x3ca74, 1822 0x3ca7c, 0x3cafc, 1823 0x3cb08, 0x3cc24, 1824 0x3cd00, 0x3cd00, 1825 0x3cd08, 0x3cd14, 1826 0x3cd1c, 0x3cd20, 1827 0x3cd3c, 0x3cd3c, 1828 0x3cd48, 0x3cd50, 1829 0x3d200, 0x3d20c, 1830 0x3d220, 0x3d220, 1831 0x3d240, 0x3d240, 1832 0x3d600, 0x3d60c, 1833 0x3da00, 0x3da1c, 1834 0x3de00, 0x3de20, 1835 0x3de38, 0x3de3c, 1836 0x3de80, 0x3de80, 1837 0x3de88, 0x3dea8, 1838 0x3deb0, 0x3deb4, 1839 0x3dec8, 0x3ded4, 1840 0x3dfb8, 0x3e004, 1841 0x3e200, 0x3e200, 1842 0x3e208, 0x3e240, 1843 0x3e248, 0x3e280, 1844 0x3e288, 0x3e2c0, 1845 0x3e2c8, 0x3e2fc, 1846 0x3e600, 0x3e630, 1847 0x3ea00, 0x3eabc, 1848 0x3eb00, 0x3eb10, 1849 0x3eb20, 0x3eb30, 1850 0x3eb40, 0x3eb50, 1851 0x3eb60, 0x3eb70, 1852 0x3f000, 0x3f028, 1853 0x3f030, 0x3f048, 1854 0x3f060, 0x3f068, 1855 0x3f070, 0x3f09c, 1856 0x3f0f0, 0x3f128, 1857 0x3f130, 0x3f148, 1858 0x3f160, 0x3f168, 1859 0x3f170, 0x3f19c, 1860 0x3f1f0, 0x3f238, 1861 0x3f240, 0x3f240, 1862 0x3f248, 0x3f250, 1863 0x3f25c, 0x3f264, 1864 0x3f270, 0x3f2b8, 1865 0x3f2c0, 0x3f2e4, 1866 0x3f2f8, 0x3f338, 1867 0x3f340, 0x3f340, 1868 0x3f348, 0x3f350, 1869 0x3f35c, 0x3f364, 1870 0x3f370, 0x3f3b8, 1871 0x3f3c0, 0x3f3e4, 1872 0x3f3f8, 0x3f428, 1873 0x3f430, 0x3f448, 1874 0x3f460, 0x3f468, 1875 0x3f470, 0x3f49c, 1876 0x3f4f0, 0x3f528, 1877 0x3f530, 0x3f548, 1878 0x3f560, 0x3f568, 1879 0x3f570, 0x3f59c, 1880 0x3f5f0, 0x3f638, 1881 0x3f640, 0x3f640, 1882 0x3f648, 0x3f650, 1883 0x3f65c, 0x3f664, 1884 0x3f670, 0x3f6b8, 1885 0x3f6c0, 0x3f6e4, 1886 0x3f6f8, 0x3f738, 1887 0x3f740, 0x3f740, 1888 0x3f748, 0x3f750, 1889 0x3f75c, 0x3f764, 1890 0x3f770, 0x3f7b8, 1891 0x3f7c0, 0x3f7e4, 1892 0x3f7f8, 0x3f7fc, 1893 0x3f814, 0x3f814, 1894 0x3f82c, 0x3f82c, 1895 0x3f880, 0x3f88c, 1896 0x3f8e8, 0x3f8ec, 1897 0x3f900, 0x3f928, 1898 0x3f930, 0x3f948, 1899 0x3f960, 0x3f968, 1900 0x3f970, 0x3f99c, 1901 0x3f9f0, 0x3fa38, 1902 0x3fa40, 0x3fa40, 1903 0x3fa48, 0x3fa50, 1904 0x3fa5c, 0x3fa64, 1905 0x3fa70, 0x3fab8, 1906 0x3fac0, 0x3fae4, 1907 0x3faf8, 0x3fb10, 1908 0x3fb28, 0x3fb28, 1909 0x3fb3c, 0x3fb50, 1910 0x3fbf0, 0x3fc10, 1911 0x3fc28, 0x3fc28, 1912 0x3fc3c, 0x3fc50, 1913 0x3fcf0, 0x3fcfc, 1914 0x40000, 0x4000c, 1915 0x40040, 0x40050, 1916 0x40060, 0x40068, 1917 0x4007c, 0x4008c, 1918 0x40094, 0x400b0, 1919 0x400c0, 0x40144, 1920 0x40180, 0x4018c, 1921 0x40200, 0x40254, 1922 0x40260, 0x40264, 1923 0x40270, 0x40288, 1924 0x40290, 0x40298, 1925 0x402ac, 0x402c8, 1926 0x402d0, 0x402e0, 1927 0x402f0, 0x402f0, 1928 0x40300, 0x4033c, 1929 0x403f8, 0x403fc, 1930 0x41304, 0x413c4, 1931 0x41400, 0x4140c, 1932 0x41414, 0x4141c, 1933 0x41480, 0x414d0, 1934 0x44000, 0x44054, 1935 0x4405c, 0x44078, 1936 0x440c0, 0x44174, 1937 0x44180, 0x441ac, 1938 0x441b4, 0x441b8, 1939 0x441c0, 0x44254, 1940 0x4425c, 0x44278, 1941 0x442c0, 0x44374, 1942 0x44380, 0x443ac, 1943 0x443b4, 0x443b8, 1944 0x443c0, 0x44454, 1945 0x4445c, 0x44478, 1946 0x444c0, 0x44574, 1947 0x44580, 0x445ac, 1948 0x445b4, 0x445b8, 1949 0x445c0, 0x44654, 1950 0x4465c, 0x44678, 1951 0x446c0, 0x44774, 1952 0x44780, 0x447ac, 1953 0x447b4, 0x447b8, 1954 0x447c0, 0x44854, 1955 0x4485c, 0x44878, 1956 0x448c0, 0x44974, 1957 0x44980, 0x449ac, 1958 0x449b4, 0x449b8, 1959 0x449c0, 0x449fc, 1960 0x45000, 0x45004, 1961 0x45010, 0x45030, 1962 0x45040, 0x45060, 1963 0x45068, 0x45068, 1964 0x45080, 0x45084, 1965 0x450a0, 0x450b0, 1966 0x45200, 0x45204, 1967 0x45210, 0x45230, 1968 0x45240, 0x45260, 1969 0x45268, 0x45268, 1970 0x45280, 0x45284, 1971 0x452a0, 0x452b0, 1972 0x460c0, 0x460e4, 1973 0x47000, 0x4703c, 1974 0x47044, 0x4708c, 1975 0x47200, 0x47250, 1976 0x47400, 0x47408, 1977 0x47414, 0x47420, 1978 0x47600, 0x47618, 1979 0x47800, 0x47814, 1980 0x48000, 0x4800c, 1981 0x48040, 0x48050, 1982 0x48060, 0x48068, 1983 0x4807c, 0x4808c, 1984 0x48094, 0x480b0, 1985 0x480c0, 0x48144, 1986 0x48180, 0x4818c, 1987 0x48200, 0x48254, 1988 0x48260, 0x48264, 1989 0x48270, 0x48288, 1990 0x48290, 0x48298, 1991 0x482ac, 0x482c8, 1992 0x482d0, 0x482e0, 1993 0x482f0, 0x482f0, 1994 0x48300, 0x4833c, 1995 0x483f8, 0x483fc, 1996 0x49304, 0x493c4, 1997 0x49400, 0x4940c, 1998 0x49414, 0x4941c, 1999 0x49480, 0x494d0, 2000 0x4c000, 0x4c054, 2001 0x4c05c, 0x4c078, 2002 0x4c0c0, 0x4c174, 2003 0x4c180, 0x4c1ac, 2004 0x4c1b4, 0x4c1b8, 2005 0x4c1c0, 0x4c254, 2006 0x4c25c, 0x4c278, 2007 0x4c2c0, 0x4c374, 2008 0x4c380, 0x4c3ac, 2009 0x4c3b4, 0x4c3b8, 2010 0x4c3c0, 0x4c454, 2011 0x4c45c, 0x4c478, 2012 0x4c4c0, 0x4c574, 2013 0x4c580, 0x4c5ac, 2014 0x4c5b4, 0x4c5b8, 2015 0x4c5c0, 0x4c654, 2016 0x4c65c, 0x4c678, 2017 0x4c6c0, 0x4c774, 2018 0x4c780, 0x4c7ac, 2019 0x4c7b4, 0x4c7b8, 2020 0x4c7c0, 0x4c854, 2021 0x4c85c, 0x4c878, 2022 0x4c8c0, 0x4c974, 2023 0x4c980, 0x4c9ac, 2024 0x4c9b4, 0x4c9b8, 2025 0x4c9c0, 0x4c9fc, 2026 0x4d000, 0x4d004, 2027 0x4d010, 0x4d030, 2028 0x4d040, 0x4d060, 2029 0x4d068, 0x4d068, 2030 0x4d080, 0x4d084, 2031 0x4d0a0, 0x4d0b0, 2032 0x4d200, 0x4d204, 2033 0x4d210, 0x4d230, 2034 0x4d240, 0x4d260, 2035 0x4d268, 0x4d268, 2036 0x4d280, 0x4d284, 2037 0x4d2a0, 0x4d2b0, 2038 0x4e0c0, 0x4e0e4, 2039 0x4f000, 0x4f03c, 2040 0x4f044, 0x4f08c, 2041 0x4f200, 0x4f250, 2042 0x4f400, 0x4f408, 2043 0x4f414, 0x4f420, 2044 0x4f600, 0x4f618, 2045 0x4f800, 0x4f814, 2046 0x50000, 0x50084, 2047 0x50090, 0x500cc, 2048 0x50400, 0x50400, 2049 0x50800, 0x50884, 2050 0x50890, 0x508cc, 2051 0x50c00, 0x50c00, 2052 0x51000, 0x5101c, 2053 0x51300, 0x51308, 2054 }; 2055 2056 static const unsigned int t5vf_reg_ranges[] = { 2057 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2058 VF_MPS_REG(A_MPS_VF_CTL), 2059 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2060 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2061 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2062 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2063 FW_T4VF_MBDATA_BASE_ADDR, 2064 FW_T4VF_MBDATA_BASE_ADDR + 2065 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2066 }; 2067 2068 static const unsigned int t6_reg_ranges[] = { 2069 0x1008, 0x101c, 2070 0x1024, 0x10a8, 2071 0x10b4, 0x10f8, 2072 0x1100, 0x1114, 2073 0x111c, 0x112c, 2074 0x1138, 0x113c, 2075 0x1144, 0x114c, 2076 0x1180, 0x1184, 2077 0x1190, 0x1194, 2078 0x11a0, 0x11a4, 2079 0x11b0, 0x11b4, 2080 0x11fc, 0x1274, 2081 0x1280, 0x133c, 2082 0x1800, 0x18fc, 2083 0x3000, 0x302c, 2084 0x3060, 0x30b0, 2085 0x30b8, 0x30d8, 2086 0x30e0, 0x30fc, 2087 0x3140, 0x357c, 2088 0x35a8, 0x35cc, 2089 0x35ec, 0x35ec, 2090 0x3600, 0x5624, 2091 0x56cc, 0x56ec, 2092 0x56f4, 0x5720, 2093 0x5728, 0x575c, 2094 0x580c, 0x5814, 2095 0x5890, 0x589c, 2096 0x58a4, 0x58ac, 2097 0x58b8, 0x58bc, 2098 0x5940, 0x595c, 2099 0x5980, 0x598c, 2100 0x59b0, 0x59c8, 2101 0x59d0, 0x59dc, 2102 0x59fc, 0x5a18, 2103 0x5a60, 0x5a6c, 2104 0x5a80, 0x5a8c, 2105 0x5a94, 0x5a9c, 2106 0x5b94, 0x5bfc, 2107 0x5c10, 0x5e48, 2108 0x5e50, 0x5e94, 2109 0x5ea0, 0x5eb0, 2110 0x5ec0, 0x5ec0, 2111 0x5ec8, 0x5ed0, 2112 0x5ee0, 0x5ee0, 2113 0x5ef0, 0x5ef0, 2114 0x5f00, 0x5f00, 2115 0x6000, 0x6020, 2116 0x6028, 0x6040, 2117 0x6058, 0x609c, 2118 0x60a8, 0x619c, 2119 0x7700, 0x7798, 2120 0x77c0, 0x7880, 2121 0x78cc, 0x78fc, 2122 0x7b00, 0x7b58, 2123 0x7b60, 0x7b84, 2124 0x7b8c, 0x7c54, 2125 0x7d00, 0x7d38, 2126 0x7d40, 0x7d84, 2127 0x7d8c, 0x7ddc, 2128 0x7de4, 0x7e04, 2129 0x7e10, 0x7e1c, 2130 0x7e24, 0x7e38, 2131 0x7e40, 0x7e44, 2132 0x7e4c, 0x7e78, 2133 0x7e80, 0x7edc, 2134 0x7ee8, 0x7efc, 2135 0x8dc0, 0x8de4, 2136 0x8df8, 0x8e04, 2137 0x8e10, 0x8e84, 2138 0x8ea0, 0x8f88, 2139 0x8fb8, 0x9058, 2140 0x9060, 0x9060, 2141 0x9068, 0x90f8, 2142 0x9100, 0x9124, 2143 0x9400, 0x9470, 2144 0x9600, 0x9600, 2145 0x9608, 0x9638, 2146 0x9640, 0x9704, 2147 0x9710, 0x971c, 2148 0x9800, 0x9808, 2149 0x9820, 0x983c, 2150 0x9850, 0x9864, 2151 0x9c00, 0x9c6c, 2152 0x9c80, 0x9cec, 2153 0x9d00, 0x9d6c, 2154 0x9d80, 0x9dec, 2155 0x9e00, 0x9e6c, 2156 0x9e80, 0x9eec, 2157 0x9f00, 0x9f6c, 2158 0x9f80, 0xa020, 2159 0xd004, 0xd03c, 2160 0xd100, 0xd118, 2161 0xd200, 0xd214, 2162 0xd220, 0xd234, 2163 0xd240, 0xd254, 2164 0xd260, 0xd274, 2165 0xd280, 0xd294, 2166 0xd2a0, 0xd2b4, 2167 0xd2c0, 0xd2d4, 2168 0xd2e0, 0xd2f4, 2169 0xd300, 0xd31c, 2170 0xdfc0, 0xdfe0, 2171 0xe000, 0xf008, 2172 0xf010, 0xf018, 2173 0xf020, 0xf028, 2174 0x11000, 0x11014, 2175 0x11048, 0x1106c, 2176 0x11074, 0x11088, 2177 0x11098, 0x11120, 2178 0x1112c, 0x1117c, 2179 0x11190, 0x112e0, 2180 0x11300, 0x1130c, 2181 0x12000, 0x1206c, 2182 0x19040, 0x1906c, 2183 0x19078, 0x19080, 2184 0x1908c, 0x190e8, 2185 0x190f0, 0x190f8, 2186 0x19100, 0x19110, 2187 0x19120, 0x19124, 2188 0x19150, 0x19194, 2189 0x1919c, 0x191b0, 2190 0x191d0, 0x191e8, 2191 0x19238, 0x19290, 2192 0x192a4, 0x192b0, 2193 0x192bc, 0x192bc, 2194 0x19348, 0x1934c, 2195 0x193f8, 0x19418, 2196 0x19420, 0x19428, 2197 0x19430, 0x19444, 2198 0x1944c, 0x1946c, 2199 0x19474, 0x19474, 2200 0x19490, 0x194cc, 2201 0x194f0, 0x194f8, 2202 0x19c00, 0x19c48, 2203 0x19c50, 0x19c80, 2204 0x19c94, 0x19c98, 2205 0x19ca0, 0x19cbc, 2206 0x19ce4, 0x19ce4, 2207 0x19cf0, 0x19cf8, 2208 0x19d00, 0x19d28, 2209 0x19d50, 0x19d78, 2210 0x19d94, 0x19d98, 2211 0x19da0, 0x19dc8, 2212 0x19df0, 0x19e10, 2213 0x19e50, 0x19e6c, 2214 0x19ea0, 0x19ebc, 2215 0x19ec4, 0x19ef4, 2216 0x19f04, 0x19f2c, 2217 0x19f34, 0x19f34, 2218 0x19f40, 0x19f50, 2219 0x19f90, 0x19fac, 2220 0x19fc4, 0x19fc8, 2221 0x19fd0, 0x19fe4, 2222 0x1a000, 0x1a004, 2223 0x1a010, 0x1a06c, 2224 0x1a0b0, 0x1a0e4, 2225 0x1a0ec, 0x1a0f8, 2226 0x1a100, 0x1a108, 2227 0x1a114, 0x1a120, 2228 0x1a128, 0x1a130, 2229 0x1a138, 0x1a138, 2230 0x1a190, 0x1a1c4, 2231 0x1a1fc, 0x1a1fc, 2232 0x1e008, 0x1e00c, 2233 0x1e040, 0x1e044, 2234 0x1e04c, 0x1e04c, 2235 0x1e284, 0x1e290, 2236 0x1e2c0, 0x1e2c0, 2237 0x1e2e0, 0x1e2e0, 2238 0x1e300, 0x1e384, 2239 0x1e3c0, 0x1e3c8, 2240 0x1e408, 0x1e40c, 2241 0x1e440, 0x1e444, 2242 0x1e44c, 0x1e44c, 2243 0x1e684, 0x1e690, 2244 0x1e6c0, 0x1e6c0, 2245 0x1e6e0, 0x1e6e0, 2246 0x1e700, 0x1e784, 2247 0x1e7c0, 0x1e7c8, 2248 0x1e808, 0x1e80c, 2249 0x1e840, 0x1e844, 2250 0x1e84c, 0x1e84c, 2251 0x1ea84, 0x1ea90, 2252 0x1eac0, 0x1eac0, 2253 0x1eae0, 0x1eae0, 2254 0x1eb00, 0x1eb84, 2255 0x1ebc0, 0x1ebc8, 2256 0x1ec08, 0x1ec0c, 2257 0x1ec40, 0x1ec44, 2258 0x1ec4c, 0x1ec4c, 2259 0x1ee84, 0x1ee90, 2260 0x1eec0, 0x1eec0, 2261 0x1eee0, 0x1eee0, 2262 0x1ef00, 0x1ef84, 2263 0x1efc0, 0x1efc8, 2264 0x1f008, 0x1f00c, 2265 0x1f040, 0x1f044, 2266 0x1f04c, 0x1f04c, 2267 0x1f284, 0x1f290, 2268 0x1f2c0, 0x1f2c0, 2269 0x1f2e0, 0x1f2e0, 2270 0x1f300, 0x1f384, 2271 0x1f3c0, 0x1f3c8, 2272 0x1f408, 0x1f40c, 2273 0x1f440, 0x1f444, 2274 0x1f44c, 0x1f44c, 2275 0x1f684, 0x1f690, 2276 0x1f6c0, 0x1f6c0, 2277 0x1f6e0, 0x1f6e0, 2278 0x1f700, 0x1f784, 2279 0x1f7c0, 0x1f7c8, 2280 0x1f808, 0x1f80c, 2281 0x1f840, 0x1f844, 2282 0x1f84c, 0x1f84c, 2283 0x1fa84, 0x1fa90, 2284 0x1fac0, 0x1fac0, 2285 0x1fae0, 0x1fae0, 2286 0x1fb00, 0x1fb84, 2287 0x1fbc0, 0x1fbc8, 2288 0x1fc08, 0x1fc0c, 2289 0x1fc40, 0x1fc44, 2290 0x1fc4c, 0x1fc4c, 2291 0x1fe84, 0x1fe90, 2292 0x1fec0, 0x1fec0, 2293 0x1fee0, 0x1fee0, 2294 0x1ff00, 0x1ff84, 2295 0x1ffc0, 0x1ffc8, 2296 0x30000, 0x30030, 2297 0x30100, 0x30168, 2298 0x30190, 0x301a0, 2299 0x301a8, 0x301b8, 2300 0x301c4, 0x301c8, 2301 0x301d0, 0x301d0, 2302 0x30200, 0x30320, 2303 0x30400, 0x304b4, 2304 0x304c0, 0x3052c, 2305 0x30540, 0x3061c, 2306 0x30800, 0x308a0, 2307 0x308c0, 0x30908, 2308 0x30910, 0x309b8, 2309 0x30a00, 0x30a04, 2310 0x30a0c, 0x30a14, 2311 0x30a1c, 0x30a2c, 2312 0x30a44, 0x30a50, 2313 0x30a74, 0x30a74, 2314 0x30a7c, 0x30afc, 2315 0x30b08, 0x30c24, 2316 0x30d00, 0x30d14, 2317 0x30d1c, 0x30d3c, 2318 0x30d44, 0x30d4c, 2319 0x30d54, 0x30d74, 2320 0x30d7c, 0x30d7c, 2321 0x30de0, 0x30de0, 2322 0x30e00, 0x30ed4, 2323 0x30f00, 0x30fa4, 2324 0x30fc0, 0x30fc4, 2325 0x31000, 0x31004, 2326 0x31080, 0x310fc, 2327 0x31208, 0x31220, 2328 0x3123c, 0x31254, 2329 0x31300, 0x31300, 2330 0x31308, 0x3131c, 2331 0x31338, 0x3133c, 2332 0x31380, 0x31380, 2333 0x31388, 0x313a8, 2334 0x313b4, 0x313b4, 2335 0x31400, 0x31420, 2336 0x31438, 0x3143c, 2337 0x31480, 0x31480, 2338 0x314a8, 0x314a8, 2339 0x314b0, 0x314b4, 2340 0x314c8, 0x314d4, 2341 0x31a40, 0x31a4c, 2342 0x31af0, 0x31b20, 2343 0x31b38, 0x31b3c, 2344 0x31b80, 0x31b80, 2345 0x31ba8, 0x31ba8, 2346 0x31bb0, 0x31bb4, 2347 0x31bc8, 0x31bd4, 2348 0x32140, 0x3218c, 2349 0x321f0, 0x321f4, 2350 0x32200, 0x32200, 2351 0x32218, 0x32218, 2352 0x32400, 0x32400, 2353 0x32408, 0x3241c, 2354 0x32618, 0x32620, 2355 0x32664, 0x32664, 2356 0x326a8, 0x326a8, 2357 0x326ec, 0x326ec, 2358 0x32a00, 0x32abc, 2359 0x32b00, 0x32b18, 2360 0x32b20, 0x32b38, 2361 0x32b40, 0x32b58, 2362 0x32b60, 0x32b78, 2363 0x32c00, 0x32c00, 2364 0x32c08, 0x32c3c, 2365 0x33000, 0x3302c, 2366 0x33034, 0x33050, 2367 0x33058, 0x33058, 2368 0x33060, 0x3308c, 2369 0x3309c, 0x330ac, 2370 0x330c0, 0x330c0, 2371 0x330c8, 0x330d0, 2372 0x330d8, 0x330e0, 2373 0x330ec, 0x3312c, 2374 0x33134, 0x33150, 2375 0x33158, 0x33158, 2376 0x33160, 0x3318c, 2377 0x3319c, 0x331ac, 2378 0x331c0, 0x331c0, 2379 0x331c8, 0x331d0, 2380 0x331d8, 0x331e0, 2381 0x331ec, 0x33290, 2382 0x33298, 0x332c4, 2383 0x332e4, 0x33390, 2384 0x33398, 0x333c4, 2385 0x333e4, 0x3342c, 2386 0x33434, 0x33450, 2387 0x33458, 0x33458, 2388 0x33460, 0x3348c, 2389 0x3349c, 0x334ac, 2390 0x334c0, 0x334c0, 2391 0x334c8, 0x334d0, 2392 0x334d8, 0x334e0, 2393 0x334ec, 0x3352c, 2394 0x33534, 0x33550, 2395 0x33558, 0x33558, 2396 0x33560, 0x3358c, 2397 0x3359c, 0x335ac, 2398 0x335c0, 0x335c0, 2399 0x335c8, 0x335d0, 2400 0x335d8, 0x335e0, 2401 0x335ec, 0x33690, 2402 0x33698, 0x336c4, 2403 0x336e4, 0x33790, 2404 0x33798, 0x337c4, 2405 0x337e4, 0x337fc, 2406 0x33814, 0x33814, 2407 0x33854, 0x33868, 2408 0x33880, 0x3388c, 2409 0x338c0, 0x338d0, 2410 0x338e8, 0x338ec, 2411 0x33900, 0x3392c, 2412 0x33934, 0x33950, 2413 0x33958, 0x33958, 2414 0x33960, 0x3398c, 2415 0x3399c, 0x339ac, 2416 0x339c0, 0x339c0, 2417 0x339c8, 0x339d0, 2418 0x339d8, 0x339e0, 2419 0x339ec, 0x33a90, 2420 0x33a98, 0x33ac4, 2421 0x33ae4, 0x33b10, 2422 0x33b24, 0x33b28, 2423 0x33b38, 0x33b50, 2424 0x33bf0, 0x33c10, 2425 0x33c24, 0x33c28, 2426 0x33c38, 0x33c50, 2427 0x33cf0, 0x33cfc, 2428 0x34000, 0x34030, 2429 0x34100, 0x34168, 2430 0x34190, 0x341a0, 2431 0x341a8, 0x341b8, 2432 0x341c4, 0x341c8, 2433 0x341d0, 0x341d0, 2434 0x34200, 0x34320, 2435 0x34400, 0x344b4, 2436 0x344c0, 0x3452c, 2437 0x34540, 0x3461c, 2438 0x34800, 0x348a0, 2439 0x348c0, 0x34908, 2440 0x34910, 0x349b8, 2441 0x34a00, 0x34a04, 2442 0x34a0c, 0x34a14, 2443 0x34a1c, 0x34a2c, 2444 0x34a44, 0x34a50, 2445 0x34a74, 0x34a74, 2446 0x34a7c, 0x34afc, 2447 0x34b08, 0x34c24, 2448 0x34d00, 0x34d14, 2449 0x34d1c, 0x34d3c, 2450 0x34d44, 0x34d4c, 2451 0x34d54, 0x34d74, 2452 0x34d7c, 0x34d7c, 2453 0x34de0, 0x34de0, 2454 0x34e00, 0x34ed4, 2455 0x34f00, 0x34fa4, 2456 0x34fc0, 0x34fc4, 2457 0x35000, 0x35004, 2458 0x35080, 0x350fc, 2459 0x35208, 0x35220, 2460 0x3523c, 0x35254, 2461 0x35300, 0x35300, 2462 0x35308, 0x3531c, 2463 0x35338, 0x3533c, 2464 0x35380, 0x35380, 2465 0x35388, 0x353a8, 2466 0x353b4, 0x353b4, 2467 0x35400, 0x35420, 2468 0x35438, 0x3543c, 2469 0x35480, 0x35480, 2470 0x354a8, 0x354a8, 2471 0x354b0, 0x354b4, 2472 0x354c8, 0x354d4, 2473 0x35a40, 0x35a4c, 2474 0x35af0, 0x35b20, 2475 0x35b38, 0x35b3c, 2476 0x35b80, 0x35b80, 2477 0x35ba8, 0x35ba8, 2478 0x35bb0, 0x35bb4, 2479 0x35bc8, 0x35bd4, 2480 0x36140, 0x3618c, 2481 0x361f0, 0x361f4, 2482 0x36200, 0x36200, 2483 0x36218, 0x36218, 2484 0x36400, 0x36400, 2485 0x36408, 0x3641c, 2486 0x36618, 0x36620, 2487 0x36664, 0x36664, 2488 0x366a8, 0x366a8, 2489 0x366ec, 0x366ec, 2490 0x36a00, 0x36abc, 2491 0x36b00, 0x36b18, 2492 0x36b20, 0x36b38, 2493 0x36b40, 0x36b58, 2494 0x36b60, 0x36b78, 2495 0x36c00, 0x36c00, 2496 0x36c08, 0x36c3c, 2497 0x37000, 0x3702c, 2498 0x37034, 0x37050, 2499 0x37058, 0x37058, 2500 0x37060, 0x3708c, 2501 0x3709c, 0x370ac, 2502 0x370c0, 0x370c0, 2503 0x370c8, 0x370d0, 2504 0x370d8, 0x370e0, 2505 0x370ec, 0x3712c, 2506 0x37134, 0x37150, 2507 0x37158, 0x37158, 2508 0x37160, 0x3718c, 2509 0x3719c, 0x371ac, 2510 0x371c0, 0x371c0, 2511 0x371c8, 0x371d0, 2512 0x371d8, 0x371e0, 2513 0x371ec, 0x37290, 2514 0x37298, 0x372c4, 2515 0x372e4, 0x37390, 2516 0x37398, 0x373c4, 2517 0x373e4, 0x3742c, 2518 0x37434, 0x37450, 2519 0x37458, 0x37458, 2520 0x37460, 0x3748c, 2521 0x3749c, 0x374ac, 2522 0x374c0, 0x374c0, 2523 0x374c8, 0x374d0, 2524 0x374d8, 0x374e0, 2525 0x374ec, 0x3752c, 2526 0x37534, 0x37550, 2527 0x37558, 0x37558, 2528 0x37560, 0x3758c, 2529 0x3759c, 0x375ac, 2530 0x375c0, 0x375c0, 2531 0x375c8, 0x375d0, 2532 0x375d8, 0x375e0, 2533 0x375ec, 0x37690, 2534 0x37698, 0x376c4, 2535 0x376e4, 0x37790, 2536 0x37798, 0x377c4, 2537 0x377e4, 0x377fc, 2538 0x37814, 0x37814, 2539 0x37854, 0x37868, 2540 0x37880, 0x3788c, 2541 0x378c0, 0x378d0, 2542 0x378e8, 0x378ec, 2543 0x37900, 0x3792c, 2544 0x37934, 0x37950, 2545 0x37958, 0x37958, 2546 0x37960, 0x3798c, 2547 0x3799c, 0x379ac, 2548 0x379c0, 0x379c0, 2549 0x379c8, 0x379d0, 2550 0x379d8, 0x379e0, 2551 0x379ec, 0x37a90, 2552 0x37a98, 0x37ac4, 2553 0x37ae4, 0x37b10, 2554 0x37b24, 0x37b28, 2555 0x37b38, 0x37b50, 2556 0x37bf0, 0x37c10, 2557 0x37c24, 0x37c28, 2558 0x37c38, 0x37c50, 2559 0x37cf0, 0x37cfc, 2560 0x40040, 0x40040, 2561 0x40080, 0x40084, 2562 0x40100, 0x40100, 2563 0x40140, 0x401bc, 2564 0x40200, 0x40214, 2565 0x40228, 0x40228, 2566 0x40240, 0x40258, 2567 0x40280, 0x40280, 2568 0x40304, 0x40304, 2569 0x40330, 0x4033c, 2570 0x41304, 0x413c8, 2571 0x413d0, 0x413dc, 2572 0x413f0, 0x413f0, 2573 0x41400, 0x4140c, 2574 0x41414, 0x4141c, 2575 0x41480, 0x414d0, 2576 0x44000, 0x4407c, 2577 0x440c0, 0x441ac, 2578 0x441b4, 0x4427c, 2579 0x442c0, 0x443ac, 2580 0x443b4, 0x4447c, 2581 0x444c0, 0x445ac, 2582 0x445b4, 0x4467c, 2583 0x446c0, 0x447ac, 2584 0x447b4, 0x4487c, 2585 0x448c0, 0x449ac, 2586 0x449b4, 0x44a7c, 2587 0x44ac0, 0x44bac, 2588 0x44bb4, 0x44c7c, 2589 0x44cc0, 0x44dac, 2590 0x44db4, 0x44e7c, 2591 0x44ec0, 0x44fac, 2592 0x44fb4, 0x4507c, 2593 0x450c0, 0x451ac, 2594 0x451b4, 0x451fc, 2595 0x45800, 0x45804, 2596 0x45810, 0x45830, 2597 0x45840, 0x45860, 2598 0x45868, 0x45868, 2599 0x45880, 0x45884, 2600 0x458a0, 0x458b0, 2601 0x45a00, 0x45a04, 2602 0x45a10, 0x45a30, 2603 0x45a40, 0x45a60, 2604 0x45a68, 0x45a68, 2605 0x45a80, 0x45a84, 2606 0x45aa0, 0x45ab0, 2607 0x460c0, 0x460e4, 2608 0x47000, 0x4703c, 2609 0x47044, 0x4708c, 2610 0x47200, 0x47250, 2611 0x47400, 0x47408, 2612 0x47414, 0x47420, 2613 0x47600, 0x47618, 2614 0x47800, 0x47814, 2615 0x47820, 0x4782c, 2616 0x50000, 0x50084, 2617 0x50090, 0x500cc, 2618 0x50300, 0x50384, 2619 0x50400, 0x50400, 2620 0x50800, 0x50884, 2621 0x50890, 0x508cc, 2622 0x50b00, 0x50b84, 2623 0x50c00, 0x50c00, 2624 0x51000, 0x51020, 2625 0x51028, 0x510b0, 2626 0x51300, 0x51324, 2627 }; 2628 2629 static const unsigned int t6vf_reg_ranges[] = { 2630 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2631 VF_MPS_REG(A_MPS_VF_CTL), 2632 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2633 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2634 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2635 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2636 FW_T6VF_MBDATA_BASE_ADDR, 2637 FW_T6VF_MBDATA_BASE_ADDR + 2638 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2639 }; 2640 2641 u32 *buf_end = (u32 *)(buf + buf_size); 2642 const unsigned int *reg_ranges; 2643 int reg_ranges_size, range; 2644 unsigned int chip_version = chip_id(adap); 2645 2646 /* 2647 * Select the right set of register ranges to dump depending on the 2648 * adapter chip type. 2649 */ 2650 switch (chip_version) { 2651 case CHELSIO_T4: 2652 if (adap->flags & IS_VF) { 2653 reg_ranges = t4vf_reg_ranges; 2654 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2655 } else { 2656 reg_ranges = t4_reg_ranges; 2657 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2658 } 2659 break; 2660 2661 case CHELSIO_T5: 2662 if (adap->flags & IS_VF) { 2663 reg_ranges = t5vf_reg_ranges; 2664 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2665 } else { 2666 reg_ranges = t5_reg_ranges; 2667 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2668 } 2669 break; 2670 2671 case CHELSIO_T6: 2672 if (adap->flags & IS_VF) { 2673 reg_ranges = t6vf_reg_ranges; 2674 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2675 } else { 2676 reg_ranges = t6_reg_ranges; 2677 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2678 } 2679 break; 2680 2681 default: 2682 CH_ERR(adap, 2683 "Unsupported chip version %d\n", chip_version); 2684 return; 2685 } 2686 2687 /* 2688 * Clear the register buffer and insert the appropriate register 2689 * values selected by the above register ranges. 2690 */ 2691 memset(buf, 0, buf_size); 2692 for (range = 0; range < reg_ranges_size; range += 2) { 2693 unsigned int reg = reg_ranges[range]; 2694 unsigned int last_reg = reg_ranges[range + 1]; 2695 u32 *bufp = (u32 *)(buf + reg); 2696 2697 /* 2698 * Iterate across the register range filling in the register 2699 * buffer but don't write past the end of the register buffer. 2700 */ 2701 while (reg <= last_reg && bufp < buf_end) { 2702 *bufp++ = t4_read_reg(adap, reg); 2703 reg += sizeof(u32); 2704 } 2705 } 2706 } 2707 2708 /* 2709 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2710 * header followed by one or more VPD-R sections, each with its own header. 2711 */ 2712 struct t4_vpd_hdr { 2713 u8 id_tag; 2714 u8 id_len[2]; 2715 u8 id_data[ID_LEN]; 2716 }; 2717 2718 struct t4_vpdr_hdr { 2719 u8 vpdr_tag; 2720 u8 vpdr_len[2]; 2721 }; 2722 2723 /* 2724 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2725 */ 2726 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2727 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2728 2729 #define EEPROM_STAT_ADDR 0x7bfc 2730 #define VPD_SIZE 0x800 2731 #define VPD_BASE 0x400 2732 #define VPD_BASE_OLD 0 2733 #define VPD_LEN 1024 2734 #define VPD_INFO_FLD_HDR_SIZE 3 2735 #define CHELSIO_VPD_UNIQUE_ID 0x82 2736 2737 /* 2738 * Small utility function to wait till any outstanding VPD Access is complete. 2739 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2740 * VPD Access in flight. This allows us to handle the problem of having a 2741 * previous VPD Access time out and prevent an attempt to inject a new VPD 2742 * Request before any in-flight VPD reguest has completed. 2743 */ 2744 static int t4_seeprom_wait(struct adapter *adapter) 2745 { 2746 unsigned int base = adapter->params.pci.vpd_cap_addr; 2747 int max_poll; 2748 2749 /* 2750 * If no VPD Access is in flight, we can just return success right 2751 * away. 2752 */ 2753 if (!adapter->vpd_busy) 2754 return 0; 2755 2756 /* 2757 * Poll the VPD Capability Address/Flag register waiting for it 2758 * to indicate that the operation is complete. 2759 */ 2760 max_poll = EEPROM_MAX_POLL; 2761 do { 2762 u16 val; 2763 2764 udelay(EEPROM_DELAY); 2765 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2766 2767 /* 2768 * If the operation is complete, mark the VPD as no longer 2769 * busy and return success. 2770 */ 2771 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2772 adapter->vpd_busy = 0; 2773 return 0; 2774 } 2775 } while (--max_poll); 2776 2777 /* 2778 * Failure! Note that we leave the VPD Busy status set in order to 2779 * avoid pushing a new VPD Access request into the VPD Capability till 2780 * the current operation eventually succeeds. It's a bug to issue a 2781 * new request when an existing request is in flight and will result 2782 * in corrupt hardware state. 2783 */ 2784 return -ETIMEDOUT; 2785 } 2786 2787 /** 2788 * t4_seeprom_read - read a serial EEPROM location 2789 * @adapter: adapter to read 2790 * @addr: EEPROM virtual address 2791 * @data: where to store the read data 2792 * 2793 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2794 * VPD capability. Note that this function must be called with a virtual 2795 * address. 2796 */ 2797 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2798 { 2799 unsigned int base = adapter->params.pci.vpd_cap_addr; 2800 int ret; 2801 2802 /* 2803 * VPD Accesses must alway be 4-byte aligned! 2804 */ 2805 if (addr >= EEPROMVSIZE || (addr & 3)) 2806 return -EINVAL; 2807 2808 /* 2809 * Wait for any previous operation which may still be in flight to 2810 * complete. 2811 */ 2812 ret = t4_seeprom_wait(adapter); 2813 if (ret) { 2814 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2815 return ret; 2816 } 2817 2818 /* 2819 * Issue our new VPD Read request, mark the VPD as being busy and wait 2820 * for our request to complete. If it doesn't complete, note the 2821 * error and return it to our caller. Note that we do not reset the 2822 * VPD Busy status! 2823 */ 2824 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2825 adapter->vpd_busy = 1; 2826 adapter->vpd_flag = PCI_VPD_ADDR_F; 2827 ret = t4_seeprom_wait(adapter); 2828 if (ret) { 2829 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2830 return ret; 2831 } 2832 2833 /* 2834 * Grab the returned data, swizzle it into our endianness and 2835 * return success. 2836 */ 2837 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2838 *data = le32_to_cpu(*data); 2839 return 0; 2840 } 2841 2842 /** 2843 * t4_seeprom_write - write a serial EEPROM location 2844 * @adapter: adapter to write 2845 * @addr: virtual EEPROM address 2846 * @data: value to write 2847 * 2848 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2849 * VPD capability. Note that this function must be called with a virtual 2850 * address. 2851 */ 2852 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2853 { 2854 unsigned int base = adapter->params.pci.vpd_cap_addr; 2855 int ret; 2856 u32 stats_reg; 2857 int max_poll; 2858 2859 /* 2860 * VPD Accesses must alway be 4-byte aligned! 2861 */ 2862 if (addr >= EEPROMVSIZE || (addr & 3)) 2863 return -EINVAL; 2864 2865 /* 2866 * Wait for any previous operation which may still be in flight to 2867 * complete. 2868 */ 2869 ret = t4_seeprom_wait(adapter); 2870 if (ret) { 2871 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2872 return ret; 2873 } 2874 2875 /* 2876 * Issue our new VPD Read request, mark the VPD as being busy and wait 2877 * for our request to complete. If it doesn't complete, note the 2878 * error and return it to our caller. Note that we do not reset the 2879 * VPD Busy status! 2880 */ 2881 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2882 cpu_to_le32(data)); 2883 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2884 (u16)addr | PCI_VPD_ADDR_F); 2885 adapter->vpd_busy = 1; 2886 adapter->vpd_flag = 0; 2887 ret = t4_seeprom_wait(adapter); 2888 if (ret) { 2889 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2890 return ret; 2891 } 2892 2893 /* 2894 * Reset PCI_VPD_DATA register after a transaction and wait for our 2895 * request to complete. If it doesn't complete, return error. 2896 */ 2897 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2898 max_poll = EEPROM_MAX_POLL; 2899 do { 2900 udelay(EEPROM_DELAY); 2901 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2902 } while ((stats_reg & 0x1) && --max_poll); 2903 if (!max_poll) 2904 return -ETIMEDOUT; 2905 2906 /* Return success! */ 2907 return 0; 2908 } 2909 2910 /** 2911 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2912 * @phys_addr: the physical EEPROM address 2913 * @fn: the PCI function number 2914 * @sz: size of function-specific area 2915 * 2916 * Translate a physical EEPROM address to virtual. The first 1K is 2917 * accessed through virtual addresses starting at 31K, the rest is 2918 * accessed through virtual addresses starting at 0. 2919 * 2920 * The mapping is as follows: 2921 * [0..1K) -> [31K..32K) 2922 * [1K..1K+A) -> [ES-A..ES) 2923 * [1K+A..ES) -> [0..ES-A-1K) 2924 * 2925 * where A = @fn * @sz, and ES = EEPROM size. 2926 */ 2927 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2928 { 2929 fn *= sz; 2930 if (phys_addr < 1024) 2931 return phys_addr + (31 << 10); 2932 if (phys_addr < 1024 + fn) 2933 return EEPROMSIZE - fn + phys_addr - 1024; 2934 if (phys_addr < EEPROMSIZE) 2935 return phys_addr - 1024 - fn; 2936 return -EINVAL; 2937 } 2938 2939 /** 2940 * t4_seeprom_wp - enable/disable EEPROM write protection 2941 * @adapter: the adapter 2942 * @enable: whether to enable or disable write protection 2943 * 2944 * Enables or disables write protection on the serial EEPROM. 2945 */ 2946 int t4_seeprom_wp(struct adapter *adapter, int enable) 2947 { 2948 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2949 } 2950 2951 /** 2952 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2953 * @vpd: Pointer to buffered vpd data structure 2954 * @kw: The keyword to search for 2955 * @region: VPD region to search (starting from 0) 2956 * 2957 * Returns the value of the information field keyword or 2958 * -ENOENT otherwise. 2959 */ 2960 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2961 { 2962 int i, tag; 2963 unsigned int offset, len; 2964 const struct t4_vpdr_hdr *vpdr; 2965 2966 offset = sizeof(struct t4_vpd_hdr); 2967 vpdr = (const void *)(vpd + offset); 2968 tag = vpdr->vpdr_tag; 2969 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2970 while (region--) { 2971 offset += sizeof(struct t4_vpdr_hdr) + len; 2972 vpdr = (const void *)(vpd + offset); 2973 if (++tag != vpdr->vpdr_tag) 2974 return -ENOENT; 2975 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2976 } 2977 offset += sizeof(struct t4_vpdr_hdr); 2978 2979 if (offset + len > VPD_LEN) { 2980 return -ENOENT; 2981 } 2982 2983 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2984 if (memcmp(vpd + i , kw , 2) == 0){ 2985 i += VPD_INFO_FLD_HDR_SIZE; 2986 return i; 2987 } 2988 2989 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2990 } 2991 2992 return -ENOENT; 2993 } 2994 2995 2996 /** 2997 * get_vpd_params - read VPD parameters from VPD EEPROM 2998 * @adapter: adapter to read 2999 * @p: where to store the parameters 3000 * @vpd: caller provided temporary space to read the VPD into 3001 * 3002 * Reads card parameters stored in VPD EEPROM. 3003 */ 3004 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3005 uint16_t device_id, u32 *buf) 3006 { 3007 int i, ret, addr; 3008 int ec, sn, pn, na, md; 3009 u8 csum; 3010 const u8 *vpd = (const u8 *)buf; 3011 3012 /* 3013 * Card information normally starts at VPD_BASE but early cards had 3014 * it at 0. 3015 */ 3016 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3017 if (ret) 3018 return (ret); 3019 3020 /* 3021 * The VPD shall have a unique identifier specified by the PCI SIG. 3022 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3023 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3024 * is expected to automatically put this entry at the 3025 * beginning of the VPD. 3026 */ 3027 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3028 3029 for (i = 0; i < VPD_LEN; i += 4) { 3030 ret = t4_seeprom_read(adapter, addr + i, buf++); 3031 if (ret) 3032 return ret; 3033 } 3034 3035 #define FIND_VPD_KW(var,name) do { \ 3036 var = get_vpd_keyword_val(vpd, name, 0); \ 3037 if (var < 0) { \ 3038 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3039 return -EINVAL; \ 3040 } \ 3041 } while (0) 3042 3043 FIND_VPD_KW(i, "RV"); 3044 for (csum = 0; i >= 0; i--) 3045 csum += vpd[i]; 3046 3047 if (csum) { 3048 CH_ERR(adapter, 3049 "corrupted VPD EEPROM, actual csum %u\n", csum); 3050 return -EINVAL; 3051 } 3052 3053 FIND_VPD_KW(ec, "EC"); 3054 FIND_VPD_KW(sn, "SN"); 3055 FIND_VPD_KW(pn, "PN"); 3056 FIND_VPD_KW(na, "NA"); 3057 #undef FIND_VPD_KW 3058 3059 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3060 strstrip(p->id); 3061 memcpy(p->ec, vpd + ec, EC_LEN); 3062 strstrip(p->ec); 3063 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3064 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3065 strstrip(p->sn); 3066 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3067 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3068 strstrip((char *)p->pn); 3069 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3070 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3071 strstrip((char *)p->na); 3072 3073 if (device_id & 0x80) 3074 return 0; /* Custom card */ 3075 3076 md = get_vpd_keyword_val(vpd, "VF", 1); 3077 if (md < 0) { 3078 snprintf(p->md, sizeof(p->md), "unknown"); 3079 } else { 3080 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3081 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3082 strstrip((char *)p->md); 3083 } 3084 3085 return 0; 3086 } 3087 3088 /* serial flash and firmware constants and flash config file constants */ 3089 enum { 3090 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3091 3092 /* flash command opcodes */ 3093 SF_PROG_PAGE = 2, /* program 256B page */ 3094 SF_WR_DISABLE = 4, /* disable writes */ 3095 SF_RD_STATUS = 5, /* read status register */ 3096 SF_WR_ENABLE = 6, /* enable writes */ 3097 SF_RD_DATA_FAST = 0xb, /* read flash */ 3098 SF_RD_ID = 0x9f, /* read ID */ 3099 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3100 }; 3101 3102 /** 3103 * sf1_read - read data from the serial flash 3104 * @adapter: the adapter 3105 * @byte_cnt: number of bytes to read 3106 * @cont: whether another operation will be chained 3107 * @lock: whether to lock SF for PL access only 3108 * @valp: where to store the read data 3109 * 3110 * Reads up to 4 bytes of data from the serial flash. The location of 3111 * the read needs to be specified prior to calling this by issuing the 3112 * appropriate commands to the serial flash. 3113 */ 3114 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3115 int lock, u32 *valp) 3116 { 3117 int ret; 3118 3119 if (!byte_cnt || byte_cnt > 4) 3120 return -EINVAL; 3121 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3122 return -EBUSY; 3123 t4_write_reg(adapter, A_SF_OP, 3124 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3125 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3126 if (!ret) 3127 *valp = t4_read_reg(adapter, A_SF_DATA); 3128 return ret; 3129 } 3130 3131 /** 3132 * sf1_write - write data to the serial flash 3133 * @adapter: the adapter 3134 * @byte_cnt: number of bytes to write 3135 * @cont: whether another operation will be chained 3136 * @lock: whether to lock SF for PL access only 3137 * @val: value to write 3138 * 3139 * Writes up to 4 bytes of data to the serial flash. The location of 3140 * the write needs to be specified prior to calling this by issuing the 3141 * appropriate commands to the serial flash. 3142 */ 3143 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3144 int lock, u32 val) 3145 { 3146 if (!byte_cnt || byte_cnt > 4) 3147 return -EINVAL; 3148 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3149 return -EBUSY; 3150 t4_write_reg(adapter, A_SF_DATA, val); 3151 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3152 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3153 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3154 } 3155 3156 /** 3157 * flash_wait_op - wait for a flash operation to complete 3158 * @adapter: the adapter 3159 * @attempts: max number of polls of the status register 3160 * @delay: delay between polls in ms 3161 * 3162 * Wait for a flash operation to complete by polling the status register. 3163 */ 3164 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3165 { 3166 int ret; 3167 u32 status; 3168 3169 while (1) { 3170 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3171 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3172 return ret; 3173 if (!(status & 1)) 3174 return 0; 3175 if (--attempts == 0) 3176 return -EAGAIN; 3177 if (delay) 3178 msleep(delay); 3179 } 3180 } 3181 3182 /** 3183 * t4_read_flash - read words from serial flash 3184 * @adapter: the adapter 3185 * @addr: the start address for the read 3186 * @nwords: how many 32-bit words to read 3187 * @data: where to store the read data 3188 * @byte_oriented: whether to store data as bytes or as words 3189 * 3190 * Read the specified number of 32-bit words from the serial flash. 3191 * If @byte_oriented is set the read data is stored as a byte array 3192 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3193 * natural endianness. 3194 */ 3195 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3196 unsigned int nwords, u32 *data, int byte_oriented) 3197 { 3198 int ret; 3199 3200 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3201 return -EINVAL; 3202 3203 addr = swab32(addr) | SF_RD_DATA_FAST; 3204 3205 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3206 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3207 return ret; 3208 3209 for ( ; nwords; nwords--, data++) { 3210 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3211 if (nwords == 1) 3212 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3213 if (ret) 3214 return ret; 3215 if (byte_oriented) 3216 *data = (__force __u32)(cpu_to_be32(*data)); 3217 } 3218 return 0; 3219 } 3220 3221 /** 3222 * t4_write_flash - write up to a page of data to the serial flash 3223 * @adapter: the adapter 3224 * @addr: the start address to write 3225 * @n: length of data to write in bytes 3226 * @data: the data to write 3227 * @byte_oriented: whether to store data as bytes or as words 3228 * 3229 * Writes up to a page of data (256 bytes) to the serial flash starting 3230 * at the given address. All the data must be written to the same page. 3231 * If @byte_oriented is set the write data is stored as byte stream 3232 * (i.e. matches what on disk), otherwise in big-endian. 3233 */ 3234 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3235 unsigned int n, const u8 *data, int byte_oriented) 3236 { 3237 int ret; 3238 u32 buf[SF_PAGE_SIZE / 4]; 3239 unsigned int i, c, left, val, offset = addr & 0xff; 3240 3241 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3242 return -EINVAL; 3243 3244 val = swab32(addr) | SF_PROG_PAGE; 3245 3246 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3247 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3248 goto unlock; 3249 3250 for (left = n; left; left -= c) { 3251 c = min(left, 4U); 3252 for (val = 0, i = 0; i < c; ++i) 3253 val = (val << 8) + *data++; 3254 3255 if (!byte_oriented) 3256 val = cpu_to_be32(val); 3257 3258 ret = sf1_write(adapter, c, c != left, 1, val); 3259 if (ret) 3260 goto unlock; 3261 } 3262 ret = flash_wait_op(adapter, 8, 1); 3263 if (ret) 3264 goto unlock; 3265 3266 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3267 3268 /* Read the page to verify the write succeeded */ 3269 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3270 byte_oriented); 3271 if (ret) 3272 return ret; 3273 3274 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3275 CH_ERR(adapter, 3276 "failed to correctly write the flash page at %#x\n", 3277 addr); 3278 return -EIO; 3279 } 3280 return 0; 3281 3282 unlock: 3283 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3284 return ret; 3285 } 3286 3287 /** 3288 * t4_get_fw_version - read the firmware version 3289 * @adapter: the adapter 3290 * @vers: where to place the version 3291 * 3292 * Reads the FW version from flash. 3293 */ 3294 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3295 { 3296 return t4_read_flash(adapter, FLASH_FW_START + 3297 offsetof(struct fw_hdr, fw_ver), 1, 3298 vers, 0); 3299 } 3300 3301 /** 3302 * t4_get_fw_hdr - read the firmware header 3303 * @adapter: the adapter 3304 * @hdr: where to place the version 3305 * 3306 * Reads the FW header from flash into caller provided buffer. 3307 */ 3308 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3309 { 3310 return t4_read_flash(adapter, FLASH_FW_START, 3311 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3312 } 3313 3314 /** 3315 * t4_get_bs_version - read the firmware bootstrap version 3316 * @adapter: the adapter 3317 * @vers: where to place the version 3318 * 3319 * Reads the FW Bootstrap version from flash. 3320 */ 3321 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3322 { 3323 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3324 offsetof(struct fw_hdr, fw_ver), 1, 3325 vers, 0); 3326 } 3327 3328 /** 3329 * t4_get_tp_version - read the TP microcode version 3330 * @adapter: the adapter 3331 * @vers: where to place the version 3332 * 3333 * Reads the TP microcode version from flash. 3334 */ 3335 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3336 { 3337 return t4_read_flash(adapter, FLASH_FW_START + 3338 offsetof(struct fw_hdr, tp_microcode_ver), 3339 1, vers, 0); 3340 } 3341 3342 /** 3343 * t4_get_exprom_version - return the Expansion ROM version (if any) 3344 * @adapter: the adapter 3345 * @vers: where to place the version 3346 * 3347 * Reads the Expansion ROM header from FLASH and returns the version 3348 * number (if present) through the @vers return value pointer. We return 3349 * this in the Firmware Version Format since it's convenient. Return 3350 * 0 on success, -ENOENT if no Expansion ROM is present. 3351 */ 3352 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 3353 { 3354 struct exprom_header { 3355 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3356 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3357 } *hdr; 3358 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3359 sizeof(u32))]; 3360 int ret; 3361 3362 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 3363 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3364 0); 3365 if (ret) 3366 return ret; 3367 3368 hdr = (struct exprom_header *)exprom_header_buf; 3369 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3370 return -ENOENT; 3371 3372 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3373 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3374 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3375 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3376 return 0; 3377 } 3378 3379 /** 3380 * t4_get_scfg_version - return the Serial Configuration version 3381 * @adapter: the adapter 3382 * @vers: where to place the version 3383 * 3384 * Reads the Serial Configuration Version via the Firmware interface 3385 * (thus this can only be called once we're ready to issue Firmware 3386 * commands). The format of the Serial Configuration version is 3387 * adapter specific. Returns 0 on success, an error on failure. 3388 * 3389 * Note that early versions of the Firmware didn't include the ability 3390 * to retrieve the Serial Configuration version, so we zero-out the 3391 * return-value parameter in that case to avoid leaving it with 3392 * garbage in it. 3393 * 3394 * Also note that the Firmware will return its cached copy of the Serial 3395 * Initialization Revision ID, not the actual Revision ID as written in 3396 * the Serial EEPROM. This is only an issue if a new VPD has been written 3397 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3398 * it's best to defer calling this routine till after a FW_RESET_CMD has 3399 * been issued if the Host Driver will be performing a full adapter 3400 * initialization. 3401 */ 3402 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3403 { 3404 u32 scfgrev_param; 3405 int ret; 3406 3407 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3408 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3409 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3410 1, &scfgrev_param, vers); 3411 if (ret) 3412 *vers = 0; 3413 return ret; 3414 } 3415 3416 /** 3417 * t4_get_vpd_version - return the VPD version 3418 * @adapter: the adapter 3419 * @vers: where to place the version 3420 * 3421 * Reads the VPD via the Firmware interface (thus this can only be called 3422 * once we're ready to issue Firmware commands). The format of the 3423 * VPD version is adapter specific. Returns 0 on success, an error on 3424 * failure. 3425 * 3426 * Note that early versions of the Firmware didn't include the ability 3427 * to retrieve the VPD version, so we zero-out the return-value parameter 3428 * in that case to avoid leaving it with garbage in it. 3429 * 3430 * Also note that the Firmware will return its cached copy of the VPD 3431 * Revision ID, not the actual Revision ID as written in the Serial 3432 * EEPROM. This is only an issue if a new VPD has been written and the 3433 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3434 * to defer calling this routine till after a FW_RESET_CMD has been issued 3435 * if the Host Driver will be performing a full adapter initialization. 3436 */ 3437 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3438 { 3439 u32 vpdrev_param; 3440 int ret; 3441 3442 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3443 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3444 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3445 1, &vpdrev_param, vers); 3446 if (ret) 3447 *vers = 0; 3448 return ret; 3449 } 3450 3451 /** 3452 * t4_get_version_info - extract various chip/firmware version information 3453 * @adapter: the adapter 3454 * 3455 * Reads various chip/firmware version numbers and stores them into the 3456 * adapter Adapter Parameters structure. If any of the efforts fails 3457 * the first failure will be returned, but all of the version numbers 3458 * will be read. 3459 */ 3460 int t4_get_version_info(struct adapter *adapter) 3461 { 3462 int ret = 0; 3463 3464 #define FIRST_RET(__getvinfo) \ 3465 do { \ 3466 int __ret = __getvinfo; \ 3467 if (__ret && !ret) \ 3468 ret = __ret; \ 3469 } while (0) 3470 3471 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3472 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3473 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3474 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3475 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3476 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3477 3478 #undef FIRST_RET 3479 3480 return ret; 3481 } 3482 3483 /** 3484 * t4_flash_erase_sectors - erase a range of flash sectors 3485 * @adapter: the adapter 3486 * @start: the first sector to erase 3487 * @end: the last sector to erase 3488 * 3489 * Erases the sectors in the given inclusive range. 3490 */ 3491 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3492 { 3493 int ret = 0; 3494 3495 if (end >= adapter->params.sf_nsec) 3496 return -EINVAL; 3497 3498 while (start <= end) { 3499 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3500 (ret = sf1_write(adapter, 4, 0, 1, 3501 SF_ERASE_SECTOR | (start << 8))) != 0 || 3502 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3503 CH_ERR(adapter, 3504 "erase of flash sector %d failed, error %d\n", 3505 start, ret); 3506 break; 3507 } 3508 start++; 3509 } 3510 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3511 return ret; 3512 } 3513 3514 /** 3515 * t4_flash_cfg_addr - return the address of the flash configuration file 3516 * @adapter: the adapter 3517 * 3518 * Return the address within the flash where the Firmware Configuration 3519 * File is stored, or an error if the device FLASH is too small to contain 3520 * a Firmware Configuration File. 3521 */ 3522 int t4_flash_cfg_addr(struct adapter *adapter) 3523 { 3524 /* 3525 * If the device FLASH isn't large enough to hold a Firmware 3526 * Configuration File, return an error. 3527 */ 3528 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3529 return -ENOSPC; 3530 3531 return FLASH_CFG_START; 3532 } 3533 3534 /* 3535 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3536 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3537 * and emit an error message for mismatched firmware to save our caller the 3538 * effort ... 3539 */ 3540 static int t4_fw_matches_chip(struct adapter *adap, 3541 const struct fw_hdr *hdr) 3542 { 3543 /* 3544 * The expression below will return FALSE for any unsupported adapter 3545 * which will keep us "honest" in the future ... 3546 */ 3547 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3548 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3549 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3550 return 1; 3551 3552 CH_ERR(adap, 3553 "FW image (%d) is not suitable for this adapter (%d)\n", 3554 hdr->chip, chip_id(adap)); 3555 return 0; 3556 } 3557 3558 /** 3559 * t4_load_fw - download firmware 3560 * @adap: the adapter 3561 * @fw_data: the firmware image to write 3562 * @size: image size 3563 * 3564 * Write the supplied firmware image to the card's serial flash. 3565 */ 3566 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3567 { 3568 u32 csum; 3569 int ret, addr; 3570 unsigned int i; 3571 u8 first_page[SF_PAGE_SIZE]; 3572 const u32 *p = (const u32 *)fw_data; 3573 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3574 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3575 unsigned int fw_start_sec; 3576 unsigned int fw_start; 3577 unsigned int fw_size; 3578 3579 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3580 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3581 fw_start = FLASH_FWBOOTSTRAP_START; 3582 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3583 } else { 3584 fw_start_sec = FLASH_FW_START_SEC; 3585 fw_start = FLASH_FW_START; 3586 fw_size = FLASH_FW_MAX_SIZE; 3587 } 3588 3589 if (!size) { 3590 CH_ERR(adap, "FW image has no data\n"); 3591 return -EINVAL; 3592 } 3593 if (size & 511) { 3594 CH_ERR(adap, 3595 "FW image size not multiple of 512 bytes\n"); 3596 return -EINVAL; 3597 } 3598 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3599 CH_ERR(adap, 3600 "FW image size differs from size in FW header\n"); 3601 return -EINVAL; 3602 } 3603 if (size > fw_size) { 3604 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3605 fw_size); 3606 return -EFBIG; 3607 } 3608 if (!t4_fw_matches_chip(adap, hdr)) 3609 return -EINVAL; 3610 3611 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3612 csum += be32_to_cpu(p[i]); 3613 3614 if (csum != 0xffffffff) { 3615 CH_ERR(adap, 3616 "corrupted firmware image, checksum %#x\n", csum); 3617 return -EINVAL; 3618 } 3619 3620 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3621 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3622 if (ret) 3623 goto out; 3624 3625 /* 3626 * We write the correct version at the end so the driver can see a bad 3627 * version if the FW write fails. Start by writing a copy of the 3628 * first page with a bad version. 3629 */ 3630 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3631 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3632 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3633 if (ret) 3634 goto out; 3635 3636 addr = fw_start; 3637 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3638 addr += SF_PAGE_SIZE; 3639 fw_data += SF_PAGE_SIZE; 3640 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3641 if (ret) 3642 goto out; 3643 } 3644 3645 ret = t4_write_flash(adap, 3646 fw_start + offsetof(struct fw_hdr, fw_ver), 3647 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3648 out: 3649 if (ret) 3650 CH_ERR(adap, "firmware download failed, error %d\n", 3651 ret); 3652 return ret; 3653 } 3654 3655 /** 3656 * t4_fwcache - firmware cache operation 3657 * @adap: the adapter 3658 * @op : the operation (flush or flush and invalidate) 3659 */ 3660 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3661 { 3662 struct fw_params_cmd c; 3663 3664 memset(&c, 0, sizeof(c)); 3665 c.op_to_vfn = 3666 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3667 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3668 V_FW_PARAMS_CMD_PFN(adap->pf) | 3669 V_FW_PARAMS_CMD_VFN(0)); 3670 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3671 c.param[0].mnem = 3672 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3673 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3674 c.param[0].val = (__force __be32)op; 3675 3676 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3677 } 3678 3679 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3680 unsigned int *pif_req_wrptr, 3681 unsigned int *pif_rsp_wrptr) 3682 { 3683 int i, j; 3684 u32 cfg, val, req, rsp; 3685 3686 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3687 if (cfg & F_LADBGEN) 3688 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3689 3690 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3691 req = G_POLADBGWRPTR(val); 3692 rsp = G_PILADBGWRPTR(val); 3693 if (pif_req_wrptr) 3694 *pif_req_wrptr = req; 3695 if (pif_rsp_wrptr) 3696 *pif_rsp_wrptr = rsp; 3697 3698 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3699 for (j = 0; j < 6; j++) { 3700 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3701 V_PILADBGRDPTR(rsp)); 3702 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3703 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3704 req++; 3705 rsp++; 3706 } 3707 req = (req + 2) & M_POLADBGRDPTR; 3708 rsp = (rsp + 2) & M_PILADBGRDPTR; 3709 } 3710 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3711 } 3712 3713 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3714 { 3715 u32 cfg; 3716 int i, j, idx; 3717 3718 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3719 if (cfg & F_LADBGEN) 3720 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3721 3722 for (i = 0; i < CIM_MALA_SIZE; i++) { 3723 for (j = 0; j < 5; j++) { 3724 idx = 8 * i + j; 3725 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3726 V_PILADBGRDPTR(idx)); 3727 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3728 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3729 } 3730 } 3731 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3732 } 3733 3734 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3735 { 3736 unsigned int i, j; 3737 3738 for (i = 0; i < 8; i++) { 3739 u32 *p = la_buf + i; 3740 3741 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3742 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3743 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3744 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3745 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3746 } 3747 } 3748 3749 /** 3750 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3751 * @caps16: a 16-bit Port Capabilities value 3752 * 3753 * Returns the equivalent 32-bit Port Capabilities value. 3754 */ 3755 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3756 { 3757 uint32_t caps32 = 0; 3758 3759 #define CAP16_TO_CAP32(__cap) \ 3760 do { \ 3761 if (caps16 & FW_PORT_CAP_##__cap) \ 3762 caps32 |= FW_PORT_CAP32_##__cap; \ 3763 } while (0) 3764 3765 CAP16_TO_CAP32(SPEED_100M); 3766 CAP16_TO_CAP32(SPEED_1G); 3767 CAP16_TO_CAP32(SPEED_25G); 3768 CAP16_TO_CAP32(SPEED_10G); 3769 CAP16_TO_CAP32(SPEED_40G); 3770 CAP16_TO_CAP32(SPEED_100G); 3771 CAP16_TO_CAP32(FC_RX); 3772 CAP16_TO_CAP32(FC_TX); 3773 CAP16_TO_CAP32(ANEG); 3774 CAP16_TO_CAP32(FORCE_PAUSE); 3775 CAP16_TO_CAP32(MDIAUTO); 3776 CAP16_TO_CAP32(MDISTRAIGHT); 3777 CAP16_TO_CAP32(FEC_RS); 3778 CAP16_TO_CAP32(FEC_BASER_RS); 3779 CAP16_TO_CAP32(802_3_PAUSE); 3780 CAP16_TO_CAP32(802_3_ASM_DIR); 3781 3782 #undef CAP16_TO_CAP32 3783 3784 return caps32; 3785 } 3786 3787 /** 3788 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3789 * @caps32: a 32-bit Port Capabilities value 3790 * 3791 * Returns the equivalent 16-bit Port Capabilities value. Note that 3792 * not all 32-bit Port Capabilities can be represented in the 16-bit 3793 * Port Capabilities and some fields/values may not make it. 3794 */ 3795 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3796 { 3797 uint16_t caps16 = 0; 3798 3799 #define CAP32_TO_CAP16(__cap) \ 3800 do { \ 3801 if (caps32 & FW_PORT_CAP32_##__cap) \ 3802 caps16 |= FW_PORT_CAP_##__cap; \ 3803 } while (0) 3804 3805 CAP32_TO_CAP16(SPEED_100M); 3806 CAP32_TO_CAP16(SPEED_1G); 3807 CAP32_TO_CAP16(SPEED_10G); 3808 CAP32_TO_CAP16(SPEED_25G); 3809 CAP32_TO_CAP16(SPEED_40G); 3810 CAP32_TO_CAP16(SPEED_100G); 3811 CAP32_TO_CAP16(FC_RX); 3812 CAP32_TO_CAP16(FC_TX); 3813 CAP32_TO_CAP16(802_3_PAUSE); 3814 CAP32_TO_CAP16(802_3_ASM_DIR); 3815 CAP32_TO_CAP16(ANEG); 3816 CAP32_TO_CAP16(FORCE_PAUSE); 3817 CAP32_TO_CAP16(MDIAUTO); 3818 CAP32_TO_CAP16(MDISTRAIGHT); 3819 CAP32_TO_CAP16(FEC_RS); 3820 CAP32_TO_CAP16(FEC_BASER_RS); 3821 3822 #undef CAP32_TO_CAP16 3823 3824 return caps16; 3825 } 3826 3827 static bool 3828 is_bt(struct port_info *pi) 3829 { 3830 3831 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 3832 pi->port_type == FW_PORT_TYPE_BT_XFI || 3833 pi->port_type == FW_PORT_TYPE_BT_XAUI); 3834 } 3835 3836 /** 3837 * t4_link_l1cfg - apply link configuration to MAC/PHY 3838 * @phy: the PHY to setup 3839 * @mac: the MAC to setup 3840 * @lc: the requested link configuration 3841 * 3842 * Set up a port's MAC and PHY according to a desired link configuration. 3843 * - If the PHY can auto-negotiate first decide what to advertise, then 3844 * enable/disable auto-negotiation as desired, and reset. 3845 * - If the PHY does not auto-negotiate just reset it. 3846 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3847 * otherwise do it later based on the outcome of auto-negotiation. 3848 */ 3849 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3850 struct link_config *lc) 3851 { 3852 struct fw_port_cmd c; 3853 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3854 unsigned int aneg, fc, fec, speed, rcap; 3855 3856 fc = 0; 3857 if (lc->requested_fc & PAUSE_RX) 3858 fc |= FW_PORT_CAP32_FC_RX; 3859 if (lc->requested_fc & PAUSE_TX) 3860 fc |= FW_PORT_CAP32_FC_TX; 3861 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3862 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3863 3864 fec = 0; 3865 if (lc->requested_fec == FEC_AUTO) 3866 fec = lc->fec_hint; 3867 else { 3868 if (lc->requested_fec & FEC_RS) 3869 fec |= FW_PORT_CAP32_FEC_RS; 3870 if (lc->requested_fec & FEC_BASER_RS) 3871 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3872 } 3873 3874 if (lc->requested_aneg == AUTONEG_DISABLE) 3875 aneg = 0; 3876 else if (lc->requested_aneg == AUTONEG_ENABLE) 3877 aneg = FW_PORT_CAP32_ANEG; 3878 else 3879 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3880 3881 if (aneg) { 3882 speed = lc->supported & V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3883 } else if (lc->requested_speed != 0) 3884 speed = speed_to_fwcap(lc->requested_speed); 3885 else 3886 speed = fwcap_top_speed(lc->supported); 3887 3888 /* Force AN on for BT cards. */ 3889 if (is_bt(adap->port[port])) 3890 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3891 3892 rcap = aneg | speed | fc | fec; 3893 if ((rcap | lc->supported) != lc->supported) { 3894 #ifdef INVARIANTS 3895 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x\n", rcap, 3896 lc->supported); 3897 #endif 3898 rcap &= lc->supported; 3899 } 3900 rcap |= mdi; 3901 3902 memset(&c, 0, sizeof(c)); 3903 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3904 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3905 V_FW_PORT_CMD_PORTID(port)); 3906 if (adap->params.port_caps32) { 3907 c.action_to_len16 = 3908 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3909 FW_LEN16(c)); 3910 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3911 } else { 3912 c.action_to_len16 = 3913 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3914 FW_LEN16(c)); 3915 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3916 } 3917 3918 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3919 } 3920 3921 /** 3922 * t4_restart_aneg - restart autonegotiation 3923 * @adap: the adapter 3924 * @mbox: mbox to use for the FW command 3925 * @port: the port id 3926 * 3927 * Restarts autonegotiation for the selected port. 3928 */ 3929 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3930 { 3931 struct fw_port_cmd c; 3932 3933 memset(&c, 0, sizeof(c)); 3934 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3935 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3936 V_FW_PORT_CMD_PORTID(port)); 3937 c.action_to_len16 = 3938 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3939 FW_LEN16(c)); 3940 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3941 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3942 } 3943 3944 struct intr_details { 3945 u32 mask; 3946 const char *msg; 3947 }; 3948 3949 struct intr_action { 3950 u32 mask; 3951 int arg; 3952 bool (*action)(struct adapter *, int, bool); 3953 }; 3954 3955 struct intr_info { 3956 const char *name; /* name of the INT_CAUSE register */ 3957 int cause_reg; /* INT_CAUSE register */ 3958 int enable_reg; /* INT_ENABLE register */ 3959 u32 fatal; /* bits that are fatal */ 3960 const struct intr_details *details; 3961 const struct intr_action *actions; 3962 }; 3963 3964 static inline char 3965 intr_alert_char(u32 cause, u32 enable, u32 fatal) 3966 { 3967 3968 if (cause & fatal) 3969 return ('!'); 3970 if (cause & enable) 3971 return ('*'); 3972 return ('-'); 3973 } 3974 3975 static void 3976 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 3977 { 3978 u32 enable, leftover; 3979 const struct intr_details *details; 3980 char alert; 3981 3982 enable = t4_read_reg(adap, ii->enable_reg); 3983 alert = intr_alert_char(cause, enable, ii->fatal); 3984 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 3985 alert, ii->name, ii->cause_reg, cause, enable, ii->fatal); 3986 3987 leftover = cause; 3988 for (details = ii->details; details && details->mask != 0; details++) { 3989 u32 msgbits = details->mask & cause; 3990 if (msgbits == 0) 3991 continue; 3992 alert = intr_alert_char(msgbits, enable, ii->fatal); 3993 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 3994 details->msg); 3995 leftover &= ~msgbits; 3996 } 3997 if (leftover != 0 && leftover != cause) 3998 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 3999 } 4000 4001 /* 4002 * Returns true for fatal error. 4003 */ 4004 static bool 4005 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4006 u32 additional_cause, bool verbose) 4007 { 4008 u32 cause; 4009 bool fatal; 4010 const struct intr_action *action; 4011 4012 /* read and display cause. */ 4013 cause = t4_read_reg(adap, ii->cause_reg); 4014 if (verbose || cause != 0) 4015 t4_show_intr_info(adap, ii, cause); 4016 fatal = (cause & ii->fatal) != 0; 4017 cause |= additional_cause; 4018 if (cause == 0) 4019 return (false); 4020 4021 for (action = ii->actions; action && action->mask != 0; action++) { 4022 if (!(action->mask & cause)) 4023 continue; 4024 fatal |= (action->action)(adap, action->arg, verbose); 4025 } 4026 4027 /* clear */ 4028 t4_write_reg(adap, ii->cause_reg, cause); 4029 (void)t4_read_reg(adap, ii->cause_reg); 4030 4031 return (fatal); 4032 } 4033 4034 /* 4035 * Interrupt handler for the PCIE module. 4036 */ 4037 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4038 { 4039 static const struct intr_details sysbus_intr_details[] = { 4040 { F_RNPP, "RXNP array parity error" }, 4041 { F_RPCP, "RXPC array parity error" }, 4042 { F_RCIP, "RXCIF array parity error" }, 4043 { F_RCCP, "Rx completions control array parity error" }, 4044 { F_RFTP, "RXFT array parity error" }, 4045 { 0 } 4046 }; 4047 static const struct intr_info sysbus_intr_info = { 4048 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4049 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4050 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4051 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4052 .details = sysbus_intr_details, 4053 .actions = NULL, 4054 }; 4055 static const struct intr_details pcie_port_intr_details[] = { 4056 { F_TPCP, "TXPC array parity error" }, 4057 { F_TNPP, "TXNP array parity error" }, 4058 { F_TFTP, "TXFT array parity error" }, 4059 { F_TCAP, "TXCA array parity error" }, 4060 { F_TCIP, "TXCIF array parity error" }, 4061 { F_RCAP, "RXCA array parity error" }, 4062 { F_OTDD, "outbound request TLP discarded" }, 4063 { F_RDPE, "Rx data parity error" }, 4064 { F_TDUE, "Tx uncorrectable data error" }, 4065 { 0 } 4066 }; 4067 static const struct intr_info pcie_port_intr_info = { 4068 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4069 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4070 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4071 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4072 F_OTDD | F_RDPE | F_TDUE, 4073 .details = pcie_port_intr_details, 4074 .actions = NULL, 4075 }; 4076 static const struct intr_details pcie_intr_details[] = { 4077 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4078 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4079 { F_MSIDATAPERR, "MSI data parity error" }, 4080 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4081 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4082 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4083 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4084 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4085 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4086 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4087 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4088 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4089 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4090 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4091 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4092 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4093 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4094 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4095 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4096 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4097 { F_FIDPERR, "PCIe FID parity error" }, 4098 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4099 { F_MATAGPERR, "PCIe MA tag parity error" }, 4100 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4101 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4102 { F_RXWRPERR, "PCIe Rx write parity error" }, 4103 { F_RPLPERR, "PCIe replay buffer parity error" }, 4104 { F_PCIESINT, "PCIe core secondary fault" }, 4105 { F_PCIEPINT, "PCIe core primary fault" }, 4106 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4107 { 0 } 4108 }; 4109 static const struct intr_details t5_pcie_intr_details[] = { 4110 { F_IPGRPPERR, "Parity errors observed by IP" }, 4111 { F_NONFATALERR, "PCIe non-fatal error" }, 4112 { F_READRSPERR, "Outbound read error" }, 4113 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4114 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4115 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4116 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4117 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4118 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4119 { F_MAGRPPERR, "MA group FIFO parity error" }, 4120 { F_VFIDPERR, "VFID SRAM parity error" }, 4121 { F_FIDPERR, "FID SRAM parity error" }, 4122 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4123 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4124 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4125 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4126 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4127 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4128 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4129 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4130 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4131 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4132 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4133 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4134 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4135 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4136 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4137 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4138 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4139 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4140 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4141 { 0 } 4142 }; 4143 struct intr_info pcie_intr_info = { 4144 .name = "PCIE_INT_CAUSE", 4145 .cause_reg = A_PCIE_INT_CAUSE, 4146 .enable_reg = A_PCIE_INT_ENABLE, 4147 .fatal = 0, 4148 .details = NULL, 4149 .actions = NULL, 4150 }; 4151 bool fatal = false; 4152 4153 if (is_t4(adap)) { 4154 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4155 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4156 4157 pcie_intr_info.fatal = 0x3fffffc0; 4158 pcie_intr_info.details = pcie_intr_details; 4159 } else { 4160 pcie_intr_info.fatal = is_t5(adap) ? 0xbfffff40 : 0x9fffff40; 4161 pcie_intr_info.details = t5_pcie_intr_details; 4162 } 4163 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4164 4165 return (fatal); 4166 } 4167 4168 /* 4169 * TP interrupt handler. 4170 */ 4171 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4172 { 4173 static const struct intr_details tp_intr_details[] = { 4174 { 0x3fffffff, "TP parity error" }, 4175 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4176 { 0 } 4177 }; 4178 static const struct intr_info tp_intr_info = { 4179 .name = "TP_INT_CAUSE", 4180 .cause_reg = A_TP_INT_CAUSE, 4181 .enable_reg = A_TP_INT_ENABLE, 4182 .fatal = 0x7fffffff, 4183 .details = tp_intr_details, 4184 .actions = NULL, 4185 }; 4186 4187 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4188 } 4189 4190 /* 4191 * SGE interrupt handler. 4192 */ 4193 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4194 { 4195 static const struct intr_info sge_int1_info = { 4196 .name = "SGE_INT_CAUSE1", 4197 .cause_reg = A_SGE_INT_CAUSE1, 4198 .enable_reg = A_SGE_INT_ENABLE1, 4199 .fatal = 0xffffffff, 4200 .details = NULL, 4201 .actions = NULL, 4202 }; 4203 static const struct intr_info sge_int2_info = { 4204 .name = "SGE_INT_CAUSE2", 4205 .cause_reg = A_SGE_INT_CAUSE2, 4206 .enable_reg = A_SGE_INT_ENABLE2, 4207 .fatal = 0xffffffff, 4208 .details = NULL, 4209 .actions = NULL, 4210 }; 4211 static const struct intr_details sge_int3_details[] = { 4212 { F_ERR_FLM_DBP, 4213 "DBP pointer delivery for invalid context or QID" }, 4214 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4215 "Invalid QID or header request by IDMA" }, 4216 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4217 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4218 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4219 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4220 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4221 { F_ERR_TIMER_ABOVE_MAX_QID, 4222 "SGE GTS with timer 0-5 for IQID > 1023" }, 4223 { F_ERR_CPL_EXCEED_IQE_SIZE, 4224 "SGE received CPL exceeding IQE size" }, 4225 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4226 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4227 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4228 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4229 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4230 "SGE IQID > 1023 received CPL for FL" }, 4231 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4232 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4233 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4234 { F_ERR_ING_CTXT_PRIO, 4235 "Ingress context manager priority user error" }, 4236 { F_ERR_EGR_CTXT_PRIO, 4237 "Egress context manager priority user error" }, 4238 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4239 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4240 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4241 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4242 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4243 { 0x0000000f, "SGE context access for invalid queue" }, 4244 { 0 } 4245 }; 4246 static const struct intr_details t6_sge_int3_details[] = { 4247 { F_ERR_FLM_DBP, 4248 "DBP pointer delivery for invalid context or QID" }, 4249 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4250 "Invalid QID or header request by IDMA" }, 4251 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4252 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4253 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4254 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4255 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4256 { F_ERR_TIMER_ABOVE_MAX_QID, 4257 "SGE GTS with timer 0-5 for IQID > 1023" }, 4258 { F_ERR_CPL_EXCEED_IQE_SIZE, 4259 "SGE received CPL exceeding IQE size" }, 4260 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4261 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4262 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4263 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4264 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4265 "SGE IQID > 1023 received CPL for FL" }, 4266 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4267 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4268 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4269 { F_ERR_ING_CTXT_PRIO, 4270 "Ingress context manager priority user error" }, 4271 { F_ERR_EGR_CTXT_PRIO, 4272 "Egress context manager priority user error" }, 4273 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4274 { F_FATAL_WRE_LEN, 4275 "SGE WRE packet less than advertized length" }, 4276 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4277 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4278 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4279 { 0x0000000f, "SGE context access for invalid queue" }, 4280 { 0 } 4281 }; 4282 struct intr_info sge_int3_info = { 4283 .name = "SGE_INT_CAUSE3", 4284 .cause_reg = A_SGE_INT_CAUSE3, 4285 .enable_reg = A_SGE_INT_ENABLE3, 4286 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4287 .details = NULL, 4288 .actions = NULL, 4289 }; 4290 static const struct intr_info sge_int4_info = { 4291 .name = "SGE_INT_CAUSE4", 4292 .cause_reg = A_SGE_INT_CAUSE4, 4293 .enable_reg = A_SGE_INT_ENABLE4, 4294 .fatal = 0, 4295 .details = NULL, 4296 .actions = NULL, 4297 }; 4298 static const struct intr_info sge_int5_info = { 4299 .name = "SGE_INT_CAUSE5", 4300 .cause_reg = A_SGE_INT_CAUSE5, 4301 .enable_reg = A_SGE_INT_ENABLE5, 4302 .fatal = 0xffffffff, 4303 .details = NULL, 4304 .actions = NULL, 4305 }; 4306 static const struct intr_info sge_int6_info = { 4307 .name = "SGE_INT_CAUSE6", 4308 .cause_reg = A_SGE_INT_CAUSE6, 4309 .enable_reg = A_SGE_INT_ENABLE6, 4310 .fatal = 0, 4311 .details = NULL, 4312 .actions = NULL, 4313 }; 4314 4315 bool fatal; 4316 u32 v; 4317 4318 if (chip_id(adap) <= CHELSIO_T5) { 4319 sge_int3_info.details = sge_int3_details; 4320 } else { 4321 sge_int3_info.details = t6_sge_int3_details; 4322 } 4323 4324 fatal = false; 4325 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4326 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4327 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4328 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4329 if (chip_id(adap) >= CHELSIO_T5) 4330 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4331 if (chip_id(adap) >= CHELSIO_T6) 4332 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4333 4334 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4335 if (v & F_ERROR_QID_VALID) { 4336 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4337 if (v & F_UNCAPTURED_ERROR) 4338 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4339 t4_write_reg(adap, A_SGE_ERROR_STATS, 4340 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4341 } 4342 4343 return (fatal); 4344 } 4345 4346 /* 4347 * CIM interrupt handler. 4348 */ 4349 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4350 { 4351 static const struct intr_details cim_host_intr_details[] = { 4352 /* T6+ */ 4353 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4354 4355 /* T5+ */ 4356 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4357 { F_PLCIM_MSTRSPDATAPARERR, 4358 "PL2CIM master response data parity error" }, 4359 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4360 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4361 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4362 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4363 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4364 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4365 4366 /* T4+ */ 4367 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4368 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4369 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4370 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4371 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4372 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4373 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4374 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4375 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4376 "CIM IBQ PCIe/SGE_HI parity error" }, 4377 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4378 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4379 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4380 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4381 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4382 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4383 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4384 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4385 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4386 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4387 { 0} 4388 }; 4389 struct intr_info cim_host_intr_info = { 4390 .name = "CIM_HOST_INT_CAUSE", 4391 .cause_reg = A_CIM_HOST_INT_CAUSE, 4392 .enable_reg = A_CIM_HOST_INT_ENABLE, 4393 .fatal = 0, 4394 .details = cim_host_intr_details, 4395 .actions = NULL, 4396 }; 4397 static const struct intr_details cim_host_upacc_intr_details[] = { 4398 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4399 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4400 { F_TIMEOUTINT, "CIM PIF timeout" }, 4401 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4402 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4403 { F_BLKWRPLINT, "CIM block write to PL space" }, 4404 { F_BLKRDPLINT, "CIM block read from PL space" }, 4405 { F_SGLWRPLINT, 4406 "CIM single write to PL space with illegal BEs" }, 4407 { F_SGLRDPLINT, 4408 "CIM single read from PL space with illegal BEs" }, 4409 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4410 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4411 { F_SGLWRCTLINT, 4412 "CIM single write to CTL space with illegal BEs" }, 4413 { F_SGLRDCTLINT, 4414 "CIM single read from CTL space with illegal BEs" }, 4415 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4416 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4417 { F_SGLWREEPROMINT, 4418 "CIM single write to EEPROM space with illegal BEs" }, 4419 { F_SGLRDEEPROMINT, 4420 "CIM single read from EEPROM space with illegal BEs" }, 4421 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4422 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4423 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4424 { F_SGLRDFLASHINT, 4425 "CIM single read from flash space with illegal BEs" }, 4426 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4427 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4428 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4429 { F_SGLRDBOOTINT, 4430 "CIM single read from boot space with illegal BEs" }, 4431 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4432 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4433 { F_ILLRDINT, "CIM illegal read" }, 4434 { F_ILLWRINT, "CIM illegal write" }, 4435 { F_ILLTRANSINT, "CIM illegal transaction" }, 4436 { F_RSVDSPACEINT, "CIM reserved space access" }, 4437 {0} 4438 }; 4439 static const struct intr_info cim_host_upacc_intr_info = { 4440 .name = "CIM_HOST_UPACC_INT_CAUSE", 4441 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4442 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4443 .fatal = 0x3fffeeff, 4444 .details = cim_host_upacc_intr_details, 4445 .actions = NULL, 4446 }; 4447 static const struct intr_info cim_pf_host_intr_info = { 4448 .name = "CIM_PF_HOST_INT_CAUSE", 4449 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4450 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4451 .fatal = 0, 4452 .details = NULL, 4453 .actions = NULL, 4454 }; 4455 u32 val, fw_err; 4456 bool fatal; 4457 4458 fw_err = t4_read_reg(adap, A_PCIE_FW); 4459 if (fw_err & F_PCIE_FW_ERR) 4460 t4_report_fw_error(adap); 4461 4462 /* 4463 * When the Firmware detects an internal error which normally wouldn't 4464 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4465 * to make sure the Host sees the Firmware Crash. So if we have a 4466 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4467 * interrupt. 4468 */ 4469 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4470 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4471 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4472 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4473 } 4474 4475 fatal = false; 4476 if (is_t4(adap)) 4477 cim_host_intr_info.fatal = 0x001fffe2; 4478 else if (is_t5(adap)) 4479 cim_host_intr_info.fatal = 0x007dffe2; 4480 else 4481 cim_host_intr_info.fatal = 0x007dffe6; 4482 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4483 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4484 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4485 4486 return (fatal); 4487 } 4488 4489 /* 4490 * ULP RX interrupt handler. 4491 */ 4492 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4493 { 4494 static const struct intr_details ulprx_intr_details[] = { 4495 /* T5+ */ 4496 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4497 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4498 4499 /* T4+ */ 4500 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4501 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4502 { 0x007fffff, "ULPRX parity error" }, 4503 { 0 } 4504 }; 4505 static const struct intr_info ulprx_intr_info = { 4506 .name = "ULP_RX_INT_CAUSE", 4507 .cause_reg = A_ULP_RX_INT_CAUSE, 4508 .enable_reg = A_ULP_RX_INT_ENABLE, 4509 .fatal = 0x07ffffff, 4510 .details = ulprx_intr_details, 4511 .actions = NULL, 4512 }; 4513 static const struct intr_info ulprx_intr2_info = { 4514 .name = "ULP_RX_INT_CAUSE_2", 4515 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4516 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4517 .fatal = 0, 4518 .details = NULL, 4519 .actions = NULL, 4520 }; 4521 bool fatal = false; 4522 4523 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4524 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4525 4526 return (fatal); 4527 } 4528 4529 /* 4530 * ULP TX interrupt handler. 4531 */ 4532 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4533 { 4534 static const struct intr_details ulptx_intr_details[] = { 4535 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4536 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4537 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4538 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4539 { 0x0fffffff, "ULPTX parity error" }, 4540 { 0 } 4541 }; 4542 static const struct intr_info ulptx_intr_info = { 4543 .name = "ULP_TX_INT_CAUSE", 4544 .cause_reg = A_ULP_TX_INT_CAUSE, 4545 .enable_reg = A_ULP_TX_INT_ENABLE, 4546 .fatal = 0x0fffffff, 4547 .details = ulptx_intr_details, 4548 .actions = NULL, 4549 }; 4550 static const struct intr_info ulptx_intr2_info = { 4551 .name = "ULP_TX_INT_CAUSE_2", 4552 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4553 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4554 .fatal = 0, 4555 .details = NULL, 4556 .actions = NULL, 4557 }; 4558 bool fatal = false; 4559 4560 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4561 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4562 4563 return (fatal); 4564 } 4565 4566 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4567 { 4568 int i; 4569 u32 data[17]; 4570 4571 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4572 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4573 for (i = 0; i < ARRAY_SIZE(data); i++) { 4574 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4575 A_PM_TX_DBG_STAT0 + i, data[i]); 4576 } 4577 4578 return (false); 4579 } 4580 4581 /* 4582 * PM TX interrupt handler. 4583 */ 4584 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4585 { 4586 static const struct intr_action pmtx_intr_actions[] = { 4587 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4588 { 0 }, 4589 }; 4590 static const struct intr_details pmtx_intr_details[] = { 4591 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4592 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4593 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4594 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4595 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4596 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4597 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4598 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4599 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4600 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4601 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4602 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4603 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4604 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4605 { 0 } 4606 }; 4607 static const struct intr_info pmtx_intr_info = { 4608 .name = "PM_TX_INT_CAUSE", 4609 .cause_reg = A_PM_TX_INT_CAUSE, 4610 .enable_reg = A_PM_TX_INT_ENABLE, 4611 .fatal = 0xffffffff, 4612 .details = pmtx_intr_details, 4613 .actions = pmtx_intr_actions, 4614 }; 4615 4616 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4617 } 4618 4619 /* 4620 * PM RX interrupt handler. 4621 */ 4622 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4623 { 4624 static const struct intr_details pmrx_intr_details[] = { 4625 /* T6+ */ 4626 { 0x18000000, "PMRX ospi overflow" }, 4627 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4628 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4629 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4630 { F_SDC_ERR, "PMRX SDC error" }, 4631 4632 /* T4+ */ 4633 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4634 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4635 { 0x0003c000, "PMRX iespi Rx framing error" }, 4636 { 0x00003c00, "PMRX iespi Tx framing error" }, 4637 { 0x00000300, "PMRX ocspi Rx framing error" }, 4638 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4639 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4640 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4641 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4642 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4643 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4644 { 0 } 4645 }; 4646 static const struct intr_info pmrx_intr_info = { 4647 .name = "PM_RX_INT_CAUSE", 4648 .cause_reg = A_PM_RX_INT_CAUSE, 4649 .enable_reg = A_PM_RX_INT_ENABLE, 4650 .fatal = 0x1fffffff, 4651 .details = pmrx_intr_details, 4652 .actions = NULL, 4653 }; 4654 4655 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4656 } 4657 4658 /* 4659 * CPL switch interrupt handler. 4660 */ 4661 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4662 { 4663 static const struct intr_details cplsw_intr_details[] = { 4664 /* T5+ */ 4665 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4666 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4667 4668 /* T4+ */ 4669 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4670 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4671 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4672 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4673 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4674 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4675 { 0 } 4676 }; 4677 struct intr_info cplsw_intr_info = { 4678 .name = "CPL_INTR_CAUSE", 4679 .cause_reg = A_CPL_INTR_CAUSE, 4680 .enable_reg = A_CPL_INTR_ENABLE, 4681 .fatal = 0, 4682 .details = cplsw_intr_details, 4683 .actions = NULL, 4684 }; 4685 4686 if (is_t4(adap)) 4687 cplsw_intr_info.fatal = 0x2f; 4688 else if (is_t5(adap)) 4689 cplsw_intr_info.fatal = 0xef; 4690 else 4691 cplsw_intr_info.fatal = 0xff; 4692 4693 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4694 } 4695 4696 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4697 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4698 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4699 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4700 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4701 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4702 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4703 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4704 4705 /* 4706 * LE interrupt handler. 4707 */ 4708 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4709 { 4710 static const struct intr_details le_intr_details[] = { 4711 { F_REQQPARERR, "LE request queue parity error" }, 4712 { F_UNKNOWNCMD, "LE unknown command" }, 4713 { F_ACTRGNFULL, "LE active region full" }, 4714 { F_PARITYERR, "LE parity error" }, 4715 { F_LIPMISS, "LE LIP miss" }, 4716 { F_LIP0, "LE 0 LIP error" }, 4717 { 0 } 4718 }; 4719 static const struct intr_details t6_le_intr_details[] = { 4720 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4721 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4722 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4723 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4724 { F_TOTCNTERR, "LE total active < TCAM count" }, 4725 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4726 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4727 { F_T6_ACTRGNFULL, "LE active region full" }, 4728 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4729 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4730 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4731 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4732 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4733 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4734 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4735 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4736 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4737 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4738 { 0 } 4739 }; 4740 struct intr_info le_intr_info = { 4741 .name = "LE_DB_INT_CAUSE", 4742 .cause_reg = A_LE_DB_INT_CAUSE, 4743 .enable_reg = A_LE_DB_INT_ENABLE, 4744 .fatal = 0, 4745 .details = NULL, 4746 .actions = NULL, 4747 }; 4748 4749 if (chip_id(adap) <= CHELSIO_T5) { 4750 le_intr_info.details = le_intr_details; 4751 le_intr_info.fatal = T4_LE_FATAL_MASK; 4752 if (is_t5(adap)) 4753 le_intr_info.fatal |= F_VFPARERR; 4754 } else { 4755 le_intr_info.details = t6_le_intr_details; 4756 le_intr_info.fatal = T6_LE_FATAL_MASK; 4757 } 4758 4759 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4760 } 4761 4762 /* 4763 * MPS interrupt handler. 4764 */ 4765 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4766 { 4767 static const struct intr_details mps_rx_perr_intr_details[] = { 4768 { 0xffffffff, "MPS Rx parity error" }, 4769 { 0 } 4770 }; 4771 static const struct intr_info mps_rx_perr_intr_info = { 4772 .name = "MPS_RX_PERR_INT_CAUSE", 4773 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4774 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4775 .fatal = 0xffffffff, 4776 .details = mps_rx_perr_intr_details, 4777 .actions = NULL, 4778 }; 4779 static const struct intr_details mps_tx_intr_details[] = { 4780 { F_PORTERR, "MPS Tx destination port is disabled" }, 4781 { F_FRMERR, "MPS Tx framing error" }, 4782 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4783 { F_BUBBLE, "MPS Tx underflow" }, 4784 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4785 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4786 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4787 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4788 { 0 } 4789 }; 4790 struct intr_info mps_tx_intr_info = { 4791 .name = "MPS_TX_INT_CAUSE", 4792 .cause_reg = A_MPS_TX_INT_CAUSE, 4793 .enable_reg = A_MPS_TX_INT_ENABLE, 4794 .fatal = 0x1ffff, 4795 .details = mps_tx_intr_details, 4796 .actions = NULL, 4797 }; 4798 static const struct intr_details mps_trc_intr_details[] = { 4799 { F_MISCPERR, "MPS TRC misc parity error" }, 4800 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4801 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4802 { 0 } 4803 }; 4804 static const struct intr_info mps_trc_intr_info = { 4805 .name = "MPS_TRC_INT_CAUSE", 4806 .cause_reg = A_MPS_TRC_INT_CAUSE, 4807 .enable_reg = A_MPS_TRC_INT_ENABLE, 4808 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4809 .details = mps_trc_intr_details, 4810 .actions = NULL, 4811 }; 4812 static const struct intr_details mps_stat_sram_intr_details[] = { 4813 { 0xffffffff, "MPS statistics SRAM parity error" }, 4814 { 0 } 4815 }; 4816 static const struct intr_info mps_stat_sram_intr_info = { 4817 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4818 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4819 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4820 .fatal = 0x1fffffff, 4821 .details = mps_stat_sram_intr_details, 4822 .actions = NULL, 4823 }; 4824 static const struct intr_details mps_stat_tx_intr_details[] = { 4825 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4826 { 0 } 4827 }; 4828 static const struct intr_info mps_stat_tx_intr_info = { 4829 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4830 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4831 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4832 .fatal = 0xffffff, 4833 .details = mps_stat_tx_intr_details, 4834 .actions = NULL, 4835 }; 4836 static const struct intr_details mps_stat_rx_intr_details[] = { 4837 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4838 { 0 } 4839 }; 4840 static const struct intr_info mps_stat_rx_intr_info = { 4841 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4842 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4843 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4844 .fatal = 0xffffff, 4845 .details = mps_stat_rx_intr_details, 4846 .actions = NULL, 4847 }; 4848 static const struct intr_details mps_cls_intr_details[] = { 4849 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4850 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4851 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4852 { 0 } 4853 }; 4854 static const struct intr_info mps_cls_intr_info = { 4855 .name = "MPS_CLS_INT_CAUSE", 4856 .cause_reg = A_MPS_CLS_INT_CAUSE, 4857 .enable_reg = A_MPS_CLS_INT_ENABLE, 4858 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4859 .details = mps_cls_intr_details, 4860 .actions = NULL, 4861 }; 4862 static const struct intr_details mps_stat_sram1_intr_details[] = { 4863 { 0xff, "MPS statistics SRAM1 parity error" }, 4864 { 0 } 4865 }; 4866 static const struct intr_info mps_stat_sram1_intr_info = { 4867 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4868 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4869 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4870 .fatal = 0xff, 4871 .details = mps_stat_sram1_intr_details, 4872 .actions = NULL, 4873 }; 4874 4875 bool fatal; 4876 4877 if (chip_id(adap) == CHELSIO_T6) 4878 mps_tx_intr_info.fatal &= ~F_BUBBLE; 4879 4880 fatal = false; 4881 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 4882 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 4883 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 4884 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 4885 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 4886 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 4887 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 4888 if (chip_id(adap) > CHELSIO_T4) { 4889 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 4890 verbose); 4891 } 4892 4893 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 4894 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 4895 4896 return (fatal); 4897 4898 } 4899 4900 /* 4901 * EDC/MC interrupt handler. 4902 */ 4903 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 4904 { 4905 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 4906 unsigned int count_reg, v; 4907 static const struct intr_details mem_intr_details[] = { 4908 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 4909 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 4910 { F_PERR_INT_CAUSE, "FIFO parity error" }, 4911 { 0 } 4912 }; 4913 struct intr_info ii = { 4914 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 4915 .details = mem_intr_details, 4916 .actions = NULL, 4917 }; 4918 bool fatal; 4919 4920 switch (idx) { 4921 case MEM_EDC0: 4922 ii.name = "EDC0_INT_CAUSE"; 4923 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 4924 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 4925 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 4926 break; 4927 case MEM_EDC1: 4928 ii.name = "EDC1_INT_CAUSE"; 4929 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 4930 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 4931 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 4932 break; 4933 case MEM_MC0: 4934 ii.name = "MC0_INT_CAUSE"; 4935 if (is_t4(adap)) { 4936 ii.cause_reg = A_MC_INT_CAUSE; 4937 ii.enable_reg = A_MC_INT_ENABLE; 4938 count_reg = A_MC_ECC_STATUS; 4939 } else { 4940 ii.cause_reg = A_MC_P_INT_CAUSE; 4941 ii.enable_reg = A_MC_P_INT_ENABLE; 4942 count_reg = A_MC_P_ECC_STATUS; 4943 } 4944 break; 4945 case MEM_MC1: 4946 ii.name = "MC1_INT_CAUSE"; 4947 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 4948 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 4949 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 4950 break; 4951 } 4952 4953 fatal = t4_handle_intr(adap, &ii, 0, verbose); 4954 4955 v = t4_read_reg(adap, count_reg); 4956 if (v != 0) { 4957 if (G_ECC_UECNT(v) != 0) { 4958 CH_ALERT(adap, 4959 "%s: %u uncorrectable ECC data error(s)\n", 4960 name[idx], G_ECC_UECNT(v)); 4961 } 4962 if (G_ECC_CECNT(v) != 0) { 4963 if (idx <= MEM_EDC1) 4964 t4_edc_err_read(adap, idx); 4965 CH_WARN_RATELIMIT(adap, 4966 "%s: %u correctable ECC data error(s)\n", 4967 name[idx], G_ECC_CECNT(v)); 4968 } 4969 t4_write_reg(adap, count_reg, 0xffffffff); 4970 } 4971 4972 return (fatal); 4973 } 4974 4975 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 4976 { 4977 u32 v; 4978 4979 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 4980 CH_ALERT(adap, 4981 "MA address wrap-around error by client %u to address %#x\n", 4982 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 4983 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 4984 4985 return (false); 4986 } 4987 4988 4989 /* 4990 * MA interrupt handler. 4991 */ 4992 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 4993 { 4994 static const struct intr_action ma_intr_actions[] = { 4995 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 4996 { 0 }, 4997 }; 4998 static const struct intr_info ma_intr_info = { 4999 .name = "MA_INT_CAUSE", 5000 .cause_reg = A_MA_INT_CAUSE, 5001 .enable_reg = A_MA_INT_ENABLE, 5002 .fatal = F_MEM_WRAP_INT_CAUSE | F_MEM_PERR_INT_CAUSE | 5003 F_MEM_TO_INT_CAUSE, 5004 .details = NULL, 5005 .actions = ma_intr_actions, 5006 }; 5007 static const struct intr_info ma_perr_status1 = { 5008 .name = "MA_PARITY_ERROR_STATUS1", 5009 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5010 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5011 .fatal = 0xffffffff, 5012 .details = NULL, 5013 .actions = NULL, 5014 }; 5015 static const struct intr_info ma_perr_status2 = { 5016 .name = "MA_PARITY_ERROR_STATUS2", 5017 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5018 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5019 .fatal = 0xffffffff, 5020 .details = NULL, 5021 .actions = NULL, 5022 }; 5023 bool fatal; 5024 5025 fatal = false; 5026 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5027 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5028 if (chip_id(adap) > CHELSIO_T4) 5029 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5030 5031 return (fatal); 5032 } 5033 5034 /* 5035 * SMB interrupt handler. 5036 */ 5037 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5038 { 5039 static const struct intr_details smb_intr_details[] = { 5040 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5041 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5042 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5043 { 0 } 5044 }; 5045 static const struct intr_info smb_intr_info = { 5046 .name = "SMB_INT_CAUSE", 5047 .cause_reg = A_SMB_INT_CAUSE, 5048 .enable_reg = A_SMB_INT_ENABLE, 5049 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5050 .details = smb_intr_details, 5051 .actions = NULL, 5052 }; 5053 5054 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5055 } 5056 5057 /* 5058 * NC-SI interrupt handler. 5059 */ 5060 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5061 { 5062 static const struct intr_details ncsi_intr_details[] = { 5063 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5064 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5065 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5066 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5067 { 0 } 5068 }; 5069 static const struct intr_info ncsi_intr_info = { 5070 .name = "NCSI_INT_CAUSE", 5071 .cause_reg = A_NCSI_INT_CAUSE, 5072 .enable_reg = A_NCSI_INT_ENABLE, 5073 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5074 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5075 .details = ncsi_intr_details, 5076 .actions = NULL, 5077 }; 5078 5079 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5080 } 5081 5082 /* 5083 * MAC interrupt handler. 5084 */ 5085 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5086 { 5087 static const struct intr_details mac_intr_details[] = { 5088 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5089 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5090 { 0 } 5091 }; 5092 char name[32]; 5093 struct intr_info ii; 5094 bool fatal = false; 5095 5096 if (is_t4(adap)) { 5097 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5098 ii.name = &name[0]; 5099 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5100 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5101 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR, 5102 ii.details = mac_intr_details, 5103 ii.actions = NULL; 5104 } else { 5105 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5106 ii.name = &name[0]; 5107 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5108 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5109 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR, 5110 ii.details = mac_intr_details, 5111 ii.actions = NULL; 5112 } 5113 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5114 5115 if (chip_id(adap) >= CHELSIO_T5) { 5116 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5117 ii.name = &name[0]; 5118 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5119 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5120 ii.fatal = 0; 5121 ii.details = NULL; 5122 ii.actions = NULL; 5123 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5124 } 5125 5126 if (chip_id(adap) >= CHELSIO_T6) { 5127 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5128 ii.name = &name[0]; 5129 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5130 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5131 ii.fatal = 0; 5132 ii.details = NULL; 5133 ii.actions = NULL; 5134 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5135 } 5136 5137 return (fatal); 5138 } 5139 5140 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5141 { 5142 static const struct intr_details plpl_intr_details[] = { 5143 { F_FATALPERR, "Fatal parity error" }, 5144 { F_PERRVFID, "VFID_MAP parity error" }, 5145 { 0 } 5146 }; 5147 struct intr_info plpl_intr_info = { 5148 .name = "PL_PL_INT_CAUSE", 5149 .cause_reg = A_PL_PL_INT_CAUSE, 5150 .enable_reg = A_PL_PL_INT_ENABLE, 5151 .fatal = F_FATALPERR, 5152 .details = plpl_intr_details, 5153 .actions = NULL, 5154 }; 5155 5156 if (is_t4(adap)) 5157 plpl_intr_info.fatal |= F_PERRVFID; 5158 5159 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5160 } 5161 5162 /** 5163 * t4_slow_intr_handler - control path interrupt handler 5164 * @adap: the adapter 5165 * @verbose: increased verbosity, for debug 5166 * 5167 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5168 * The designation 'slow' is because it involves register reads, while 5169 * data interrupts typically don't involve any MMIOs. 5170 */ 5171 int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5172 { 5173 static const struct intr_details pl_intr_details[] = { 5174 { F_MC1, "MC1" }, 5175 { F_UART, "UART" }, 5176 { F_ULP_TX, "ULP TX" }, 5177 { F_SGE, "SGE" }, 5178 { F_HMA, "HMA" }, 5179 { F_CPL_SWITCH, "CPL Switch" }, 5180 { F_ULP_RX, "ULP RX" }, 5181 { F_PM_RX, "PM RX" }, 5182 { F_PM_TX, "PM TX" }, 5183 { F_MA, "MA" }, 5184 { F_TP, "TP" }, 5185 { F_LE, "LE" }, 5186 { F_EDC1, "EDC1" }, 5187 { F_EDC0, "EDC0" }, 5188 { F_MC, "MC0" }, 5189 { F_PCIE, "PCIE" }, 5190 { F_PMU, "PMU" }, 5191 { F_MAC3, "MAC3" }, 5192 { F_MAC2, "MAC2" }, 5193 { F_MAC1, "MAC1" }, 5194 { F_MAC0, "MAC0" }, 5195 { F_SMB, "SMB" }, 5196 { F_SF, "SF" }, 5197 { F_PL, "PL" }, 5198 { F_NCSI, "NC-SI" }, 5199 { F_MPS, "MPS" }, 5200 { F_MI, "MI" }, 5201 { F_DBG, "DBG" }, 5202 { F_I2CM, "I2CM" }, 5203 { F_CIM, "CIM" }, 5204 { 0 } 5205 }; 5206 static const struct intr_info pl_perr_cause = { 5207 .name = "PL_PERR_CAUSE", 5208 .cause_reg = A_PL_PERR_CAUSE, 5209 .enable_reg = A_PL_PERR_ENABLE, 5210 .fatal = 0xffffffff, 5211 .details = pl_intr_details, 5212 .actions = NULL, 5213 }; 5214 static const struct intr_action pl_intr_action[] = { 5215 { F_MC1, MEM_MC1, mem_intr_handler }, 5216 { F_ULP_TX, -1, ulptx_intr_handler }, 5217 { F_SGE, -1, sge_intr_handler }, 5218 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5219 { F_ULP_RX, -1, ulprx_intr_handler }, 5220 { F_PM_RX, -1, pmrx_intr_handler}, 5221 { F_PM_TX, -1, pmtx_intr_handler}, 5222 { F_MA, -1, ma_intr_handler }, 5223 { F_TP, -1, tp_intr_handler }, 5224 { F_LE, -1, le_intr_handler }, 5225 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5226 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5227 { F_MC0, MEM_MC0, mem_intr_handler }, 5228 { F_PCIE, -1, pcie_intr_handler }, 5229 { F_MAC3, 3, mac_intr_handler}, 5230 { F_MAC2, 2, mac_intr_handler}, 5231 { F_MAC1, 1, mac_intr_handler}, 5232 { F_MAC0, 0, mac_intr_handler}, 5233 { F_SMB, -1, smb_intr_handler}, 5234 { F_PL, -1, plpl_intr_handler }, 5235 { F_NCSI, -1, ncsi_intr_handler}, 5236 { F_MPS, -1, mps_intr_handler }, 5237 { F_CIM, -1, cim_intr_handler }, 5238 { 0 } 5239 }; 5240 static const struct intr_info pl_intr_info = { 5241 .name = "PL_INT_CAUSE", 5242 .cause_reg = A_PL_INT_CAUSE, 5243 .enable_reg = A_PL_INT_ENABLE, 5244 .fatal = 0, 5245 .details = pl_intr_details, 5246 .actions = pl_intr_action, 5247 }; 5248 bool fatal; 5249 u32 perr; 5250 5251 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5252 if (verbose || perr != 0) { 5253 t4_show_intr_info(adap, &pl_perr_cause, perr); 5254 if (perr != 0) 5255 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5256 if (verbose) 5257 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5258 } 5259 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5260 if (fatal) 5261 t4_fatal_err(adap, false); 5262 5263 return (0); 5264 } 5265 5266 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5267 5268 /** 5269 * t4_intr_enable - enable interrupts 5270 * @adapter: the adapter whose interrupts should be enabled 5271 * 5272 * Enable PF-specific interrupts for the calling function and the top-level 5273 * interrupt concentrator for global interrupts. Interrupts are already 5274 * enabled at each module, here we just enable the roots of the interrupt 5275 * hierarchies. 5276 * 5277 * Note: this function should be called only when the driver manages 5278 * non PF-specific interrupts from the various HW modules. Only one PCI 5279 * function at a time should be doing this. 5280 */ 5281 void t4_intr_enable(struct adapter *adap) 5282 { 5283 u32 val = 0; 5284 5285 if (chip_id(adap) <= CHELSIO_T5) 5286 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5287 else 5288 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5289 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5290 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5291 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5292 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5293 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5294 F_EGRESS_SIZE_ERR; 5295 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5296 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5297 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5298 } 5299 5300 /** 5301 * t4_intr_disable - disable interrupts 5302 * @adap: the adapter whose interrupts should be disabled 5303 * 5304 * Disable interrupts. We only disable the top-level interrupt 5305 * concentrators. The caller must be a PCI function managing global 5306 * interrupts. 5307 */ 5308 void t4_intr_disable(struct adapter *adap) 5309 { 5310 5311 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5312 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5313 } 5314 5315 /** 5316 * t4_intr_clear - clear all interrupts 5317 * @adap: the adapter whose interrupts should be cleared 5318 * 5319 * Clears all interrupts. The caller must be a PCI function managing 5320 * global interrupts. 5321 */ 5322 void t4_intr_clear(struct adapter *adap) 5323 { 5324 static const u32 cause_reg[] = { 5325 A_CIM_HOST_INT_CAUSE, 5326 A_CIM_HOST_UPACC_INT_CAUSE, 5327 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5328 A_CPL_INTR_CAUSE, 5329 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5330 A_LE_DB_INT_CAUSE, 5331 A_MA_INT_WRAP_STATUS, 5332 A_MA_PARITY_ERROR_STATUS1, 5333 A_MA_INT_CAUSE, 5334 A_MPS_CLS_INT_CAUSE, 5335 A_MPS_RX_PERR_INT_CAUSE, 5336 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5337 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5338 A_MPS_TRC_INT_CAUSE, 5339 A_MPS_TX_INT_CAUSE, 5340 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5341 A_NCSI_INT_CAUSE, 5342 A_PCIE_INT_CAUSE, 5343 A_PCIE_NONFAT_ERR, 5344 A_PL_PL_INT_CAUSE, 5345 A_PM_RX_INT_CAUSE, 5346 A_PM_TX_INT_CAUSE, 5347 A_SGE_INT_CAUSE1, 5348 A_SGE_INT_CAUSE2, 5349 A_SGE_INT_CAUSE3, 5350 A_SGE_INT_CAUSE4, 5351 A_SMB_INT_CAUSE, 5352 A_TP_INT_CAUSE, 5353 A_ULP_RX_INT_CAUSE, 5354 A_ULP_RX_INT_CAUSE_2, 5355 A_ULP_TX_INT_CAUSE, 5356 A_ULP_TX_INT_CAUSE_2, 5357 5358 MYPF_REG(A_PL_PF_INT_CAUSE), 5359 }; 5360 int i; 5361 const int nchan = adap->chip_params->nchan; 5362 5363 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5364 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5365 5366 if (is_t4(adap)) { 5367 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5368 0xffffffff); 5369 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5370 0xffffffff); 5371 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5372 for (i = 0; i < nchan; i++) { 5373 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5374 0xffffffff); 5375 } 5376 } 5377 if (chip_id(adap) >= CHELSIO_T5) { 5378 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5379 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5380 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5381 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5382 if (is_t5(adap)) { 5383 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5384 0xffffffff); 5385 } 5386 for (i = 0; i < nchan; i++) { 5387 t4_write_reg(adap, T5_PORT_REG(i, 5388 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5389 if (chip_id(adap) > CHELSIO_T5) { 5390 t4_write_reg(adap, T5_PORT_REG(i, 5391 A_MAC_PORT_PERR_INT_CAUSE_100G), 5392 0xffffffff); 5393 } 5394 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5395 0xffffffff); 5396 } 5397 } 5398 if (chip_id(adap) >= CHELSIO_T6) { 5399 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5400 } 5401 5402 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5403 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5404 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5405 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5406 } 5407 5408 /** 5409 * hash_mac_addr - return the hash value of a MAC address 5410 * @addr: the 48-bit Ethernet MAC address 5411 * 5412 * Hashes a MAC address according to the hash function used by HW inexact 5413 * (hash) address matching. 5414 */ 5415 static int hash_mac_addr(const u8 *addr) 5416 { 5417 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5418 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5419 a ^= b; 5420 a ^= (a >> 12); 5421 a ^= (a >> 6); 5422 return a & 0x3f; 5423 } 5424 5425 /** 5426 * t4_config_rss_range - configure a portion of the RSS mapping table 5427 * @adapter: the adapter 5428 * @mbox: mbox to use for the FW command 5429 * @viid: virtual interface whose RSS subtable is to be written 5430 * @start: start entry in the table to write 5431 * @n: how many table entries to write 5432 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5433 * @nrspq: number of values in @rspq 5434 * 5435 * Programs the selected part of the VI's RSS mapping table with the 5436 * provided values. If @nrspq < @n the supplied values are used repeatedly 5437 * until the full table range is populated. 5438 * 5439 * The caller must ensure the values in @rspq are in the range allowed for 5440 * @viid. 5441 */ 5442 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5443 int start, int n, const u16 *rspq, unsigned int nrspq) 5444 { 5445 int ret; 5446 const u16 *rsp = rspq; 5447 const u16 *rsp_end = rspq + nrspq; 5448 struct fw_rss_ind_tbl_cmd cmd; 5449 5450 memset(&cmd, 0, sizeof(cmd)); 5451 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5452 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5453 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5454 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5455 5456 /* 5457 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5458 * Queue Identifiers. These Ingress Queue IDs are packed three to 5459 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5460 * reserved. 5461 */ 5462 while (n > 0) { 5463 int nq = min(n, 32); 5464 int nq_packed = 0; 5465 __be32 *qp = &cmd.iq0_to_iq2; 5466 5467 /* 5468 * Set up the firmware RSS command header to send the next 5469 * "nq" Ingress Queue IDs to the firmware. 5470 */ 5471 cmd.niqid = cpu_to_be16(nq); 5472 cmd.startidx = cpu_to_be16(start); 5473 5474 /* 5475 * "nq" more done for the start of the next loop. 5476 */ 5477 start += nq; 5478 n -= nq; 5479 5480 /* 5481 * While there are still Ingress Queue IDs to stuff into the 5482 * current firmware RSS command, retrieve them from the 5483 * Ingress Queue ID array and insert them into the command. 5484 */ 5485 while (nq > 0) { 5486 /* 5487 * Grab up to the next 3 Ingress Queue IDs (wrapping 5488 * around the Ingress Queue ID array if necessary) and 5489 * insert them into the firmware RSS command at the 5490 * current 3-tuple position within the commad. 5491 */ 5492 u16 qbuf[3]; 5493 u16 *qbp = qbuf; 5494 int nqbuf = min(3, nq); 5495 5496 nq -= nqbuf; 5497 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5498 while (nqbuf && nq_packed < 32) { 5499 nqbuf--; 5500 nq_packed++; 5501 *qbp++ = *rsp++; 5502 if (rsp >= rsp_end) 5503 rsp = rspq; 5504 } 5505 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5506 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5507 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5508 } 5509 5510 /* 5511 * Send this portion of the RRS table update to the firmware; 5512 * bail out on any errors. 5513 */ 5514 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5515 if (ret) 5516 return ret; 5517 } 5518 return 0; 5519 } 5520 5521 /** 5522 * t4_config_glbl_rss - configure the global RSS mode 5523 * @adapter: the adapter 5524 * @mbox: mbox to use for the FW command 5525 * @mode: global RSS mode 5526 * @flags: mode-specific flags 5527 * 5528 * Sets the global RSS mode. 5529 */ 5530 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5531 unsigned int flags) 5532 { 5533 struct fw_rss_glb_config_cmd c; 5534 5535 memset(&c, 0, sizeof(c)); 5536 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5537 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5538 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5539 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5540 c.u.manual.mode_pkd = 5541 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5542 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5543 c.u.basicvirtual.mode_keymode = 5544 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5545 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5546 } else 5547 return -EINVAL; 5548 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5549 } 5550 5551 /** 5552 * t4_config_vi_rss - configure per VI RSS settings 5553 * @adapter: the adapter 5554 * @mbox: mbox to use for the FW command 5555 * @viid: the VI id 5556 * @flags: RSS flags 5557 * @defq: id of the default RSS queue for the VI. 5558 * @skeyidx: RSS secret key table index for non-global mode 5559 * @skey: RSS vf_scramble key for VI. 5560 * 5561 * Configures VI-specific RSS properties. 5562 */ 5563 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5564 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5565 unsigned int skey) 5566 { 5567 struct fw_rss_vi_config_cmd c; 5568 5569 memset(&c, 0, sizeof(c)); 5570 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5571 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5572 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5573 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5574 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5575 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5576 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5577 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5578 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5579 5580 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5581 } 5582 5583 /* Read an RSS table row */ 5584 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5585 { 5586 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5587 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5588 5, 0, val); 5589 } 5590 5591 /** 5592 * t4_read_rss - read the contents of the RSS mapping table 5593 * @adapter: the adapter 5594 * @map: holds the contents of the RSS mapping table 5595 * 5596 * Reads the contents of the RSS hash->queue mapping table. 5597 */ 5598 int t4_read_rss(struct adapter *adapter, u16 *map) 5599 { 5600 u32 val; 5601 int i, ret; 5602 5603 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 5604 ret = rd_rss_row(adapter, i, &val); 5605 if (ret) 5606 return ret; 5607 *map++ = G_LKPTBLQUEUE0(val); 5608 *map++ = G_LKPTBLQUEUE1(val); 5609 } 5610 return 0; 5611 } 5612 5613 /** 5614 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5615 * @adap: the adapter 5616 * @cmd: TP fw ldst address space type 5617 * @vals: where the indirect register values are stored/written 5618 * @nregs: how many indirect registers to read/write 5619 * @start_idx: index of first indirect register to read/write 5620 * @rw: Read (1) or Write (0) 5621 * @sleep_ok: if true we may sleep while awaiting command completion 5622 * 5623 * Access TP indirect registers through LDST 5624 **/ 5625 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5626 unsigned int nregs, unsigned int start_index, 5627 unsigned int rw, bool sleep_ok) 5628 { 5629 int ret = 0; 5630 unsigned int i; 5631 struct fw_ldst_cmd c; 5632 5633 for (i = 0; i < nregs; i++) { 5634 memset(&c, 0, sizeof(c)); 5635 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5636 F_FW_CMD_REQUEST | 5637 (rw ? F_FW_CMD_READ : 5638 F_FW_CMD_WRITE) | 5639 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5640 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5641 5642 c.u.addrval.addr = cpu_to_be32(start_index + i); 5643 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5644 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5645 sleep_ok); 5646 if (ret) 5647 return ret; 5648 5649 if (rw) 5650 vals[i] = be32_to_cpu(c.u.addrval.val); 5651 } 5652 return 0; 5653 } 5654 5655 /** 5656 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5657 * @adap: the adapter 5658 * @reg_addr: Address Register 5659 * @reg_data: Data register 5660 * @buff: where the indirect register values are stored/written 5661 * @nregs: how many indirect registers to read/write 5662 * @start_index: index of first indirect register to read/write 5663 * @rw: READ(1) or WRITE(0) 5664 * @sleep_ok: if true we may sleep while awaiting command completion 5665 * 5666 * Read/Write TP indirect registers through LDST if possible. 5667 * Else, use backdoor access 5668 **/ 5669 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5670 u32 *buff, u32 nregs, u32 start_index, int rw, 5671 bool sleep_ok) 5672 { 5673 int rc = -EINVAL; 5674 int cmd; 5675 5676 switch (reg_addr) { 5677 case A_TP_PIO_ADDR: 5678 cmd = FW_LDST_ADDRSPC_TP_PIO; 5679 break; 5680 case A_TP_TM_PIO_ADDR: 5681 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5682 break; 5683 case A_TP_MIB_INDEX: 5684 cmd = FW_LDST_ADDRSPC_TP_MIB; 5685 break; 5686 default: 5687 goto indirect_access; 5688 } 5689 5690 if (t4_use_ldst(adap)) 5691 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5692 sleep_ok); 5693 5694 indirect_access: 5695 5696 if (rc) { 5697 if (rw) 5698 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5699 start_index); 5700 else 5701 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5702 start_index); 5703 } 5704 } 5705 5706 /** 5707 * t4_tp_pio_read - Read TP PIO registers 5708 * @adap: the adapter 5709 * @buff: where the indirect register values are written 5710 * @nregs: how many indirect registers to read 5711 * @start_index: index of first indirect register to read 5712 * @sleep_ok: if true we may sleep while awaiting command completion 5713 * 5714 * Read TP PIO Registers 5715 **/ 5716 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5717 u32 start_index, bool sleep_ok) 5718 { 5719 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5720 start_index, 1, sleep_ok); 5721 } 5722 5723 /** 5724 * t4_tp_pio_write - Write TP PIO registers 5725 * @adap: the adapter 5726 * @buff: where the indirect register values are stored 5727 * @nregs: how many indirect registers to write 5728 * @start_index: index of first indirect register to write 5729 * @sleep_ok: if true we may sleep while awaiting command completion 5730 * 5731 * Write TP PIO Registers 5732 **/ 5733 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5734 u32 start_index, bool sleep_ok) 5735 { 5736 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5737 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5738 } 5739 5740 /** 5741 * t4_tp_tm_pio_read - Read TP TM PIO registers 5742 * @adap: the adapter 5743 * @buff: where the indirect register values are written 5744 * @nregs: how many indirect registers to read 5745 * @start_index: index of first indirect register to read 5746 * @sleep_ok: if true we may sleep while awaiting command completion 5747 * 5748 * Read TP TM PIO Registers 5749 **/ 5750 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5751 u32 start_index, bool sleep_ok) 5752 { 5753 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5754 nregs, start_index, 1, sleep_ok); 5755 } 5756 5757 /** 5758 * t4_tp_mib_read - Read TP MIB registers 5759 * @adap: the adapter 5760 * @buff: where the indirect register values are written 5761 * @nregs: how many indirect registers to read 5762 * @start_index: index of first indirect register to read 5763 * @sleep_ok: if true we may sleep while awaiting command completion 5764 * 5765 * Read TP MIB Registers 5766 **/ 5767 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5768 bool sleep_ok) 5769 { 5770 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5771 start_index, 1, sleep_ok); 5772 } 5773 5774 /** 5775 * t4_read_rss_key - read the global RSS key 5776 * @adap: the adapter 5777 * @key: 10-entry array holding the 320-bit RSS key 5778 * @sleep_ok: if true we may sleep while awaiting command completion 5779 * 5780 * Reads the global 320-bit RSS key. 5781 */ 5782 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5783 { 5784 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5785 } 5786 5787 /** 5788 * t4_write_rss_key - program one of the RSS keys 5789 * @adap: the adapter 5790 * @key: 10-entry array holding the 320-bit RSS key 5791 * @idx: which RSS key to write 5792 * @sleep_ok: if true we may sleep while awaiting command completion 5793 * 5794 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5795 * 0..15 the corresponding entry in the RSS key table is written, 5796 * otherwise the global RSS key is written. 5797 */ 5798 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5799 bool sleep_ok) 5800 { 5801 u8 rss_key_addr_cnt = 16; 5802 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5803 5804 /* 5805 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5806 * allows access to key addresses 16-63 by using KeyWrAddrX 5807 * as index[5:4](upper 2) into key table 5808 */ 5809 if ((chip_id(adap) > CHELSIO_T5) && 5810 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5811 rss_key_addr_cnt = 32; 5812 5813 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5814 5815 if (idx >= 0 && idx < rss_key_addr_cnt) { 5816 if (rss_key_addr_cnt > 16) 5817 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5818 vrt | V_KEYWRADDRX(idx >> 4) | 5819 V_T6_VFWRADDR(idx) | F_KEYWREN); 5820 else 5821 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5822 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5823 } 5824 } 5825 5826 /** 5827 * t4_read_rss_pf_config - read PF RSS Configuration Table 5828 * @adapter: the adapter 5829 * @index: the entry in the PF RSS table to read 5830 * @valp: where to store the returned value 5831 * @sleep_ok: if true we may sleep while awaiting command completion 5832 * 5833 * Reads the PF RSS Configuration Table at the specified index and returns 5834 * the value found there. 5835 */ 5836 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5837 u32 *valp, bool sleep_ok) 5838 { 5839 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5840 } 5841 5842 /** 5843 * t4_write_rss_pf_config - write PF RSS Configuration Table 5844 * @adapter: the adapter 5845 * @index: the entry in the VF RSS table to read 5846 * @val: the value to store 5847 * @sleep_ok: if true we may sleep while awaiting command completion 5848 * 5849 * Writes the PF RSS Configuration Table at the specified index with the 5850 * specified value. 5851 */ 5852 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5853 u32 val, bool sleep_ok) 5854 { 5855 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5856 sleep_ok); 5857 } 5858 5859 /** 5860 * t4_read_rss_vf_config - read VF RSS Configuration Table 5861 * @adapter: the adapter 5862 * @index: the entry in the VF RSS table to read 5863 * @vfl: where to store the returned VFL 5864 * @vfh: where to store the returned VFH 5865 * @sleep_ok: if true we may sleep while awaiting command completion 5866 * 5867 * Reads the VF RSS Configuration Table at the specified index and returns 5868 * the (VFL, VFH) values found there. 5869 */ 5870 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5871 u32 *vfl, u32 *vfh, bool sleep_ok) 5872 { 5873 u32 vrt, mask, data; 5874 5875 if (chip_id(adapter) <= CHELSIO_T5) { 5876 mask = V_VFWRADDR(M_VFWRADDR); 5877 data = V_VFWRADDR(index); 5878 } else { 5879 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5880 data = V_T6_VFWRADDR(index); 5881 } 5882 /* 5883 * Request that the index'th VF Table values be read into VFL/VFH. 5884 */ 5885 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5886 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5887 vrt |= data | F_VFRDEN; 5888 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5889 5890 /* 5891 * Grab the VFL/VFH values ... 5892 */ 5893 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5894 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5895 } 5896 5897 /** 5898 * t4_write_rss_vf_config - write VF RSS Configuration Table 5899 * 5900 * @adapter: the adapter 5901 * @index: the entry in the VF RSS table to write 5902 * @vfl: the VFL to store 5903 * @vfh: the VFH to store 5904 * 5905 * Writes the VF RSS Configuration Table at the specified index with the 5906 * specified (VFL, VFH) values. 5907 */ 5908 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 5909 u32 vfl, u32 vfh, bool sleep_ok) 5910 { 5911 u32 vrt, mask, data; 5912 5913 if (chip_id(adapter) <= CHELSIO_T5) { 5914 mask = V_VFWRADDR(M_VFWRADDR); 5915 data = V_VFWRADDR(index); 5916 } else { 5917 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5918 data = V_T6_VFWRADDR(index); 5919 } 5920 5921 /* 5922 * Load up VFL/VFH with the values to be written ... 5923 */ 5924 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5925 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5926 5927 /* 5928 * Write the VFL/VFH into the VF Table at index'th location. 5929 */ 5930 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5931 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5932 vrt |= data | F_VFRDEN; 5933 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5934 } 5935 5936 /** 5937 * t4_read_rss_pf_map - read PF RSS Map 5938 * @adapter: the adapter 5939 * @sleep_ok: if true we may sleep while awaiting command completion 5940 * 5941 * Reads the PF RSS Map register and returns its value. 5942 */ 5943 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 5944 { 5945 u32 pfmap; 5946 5947 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5948 5949 return pfmap; 5950 } 5951 5952 /** 5953 * t4_write_rss_pf_map - write PF RSS Map 5954 * @adapter: the adapter 5955 * @pfmap: PF RSS Map value 5956 * 5957 * Writes the specified value to the PF RSS Map register. 5958 */ 5959 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 5960 { 5961 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5962 } 5963 5964 /** 5965 * t4_read_rss_pf_mask - read PF RSS Mask 5966 * @adapter: the adapter 5967 * @sleep_ok: if true we may sleep while awaiting command completion 5968 * 5969 * Reads the PF RSS Mask register and returns its value. 5970 */ 5971 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 5972 { 5973 u32 pfmask; 5974 5975 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5976 5977 return pfmask; 5978 } 5979 5980 /** 5981 * t4_write_rss_pf_mask - write PF RSS Mask 5982 * @adapter: the adapter 5983 * @pfmask: PF RSS Mask value 5984 * 5985 * Writes the specified value to the PF RSS Mask register. 5986 */ 5987 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 5988 { 5989 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5990 } 5991 5992 /** 5993 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 5994 * @adap: the adapter 5995 * @v4: holds the TCP/IP counter values 5996 * @v6: holds the TCP/IPv6 counter values 5997 * @sleep_ok: if true we may sleep while awaiting command completion 5998 * 5999 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6000 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6001 */ 6002 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6003 struct tp_tcp_stats *v6, bool sleep_ok) 6004 { 6005 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6006 6007 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6008 #define STAT(x) val[STAT_IDX(x)] 6009 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6010 6011 if (v4) { 6012 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6013 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6014 v4->tcp_out_rsts = STAT(OUT_RST); 6015 v4->tcp_in_segs = STAT64(IN_SEG); 6016 v4->tcp_out_segs = STAT64(OUT_SEG); 6017 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6018 } 6019 if (v6) { 6020 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6021 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6022 v6->tcp_out_rsts = STAT(OUT_RST); 6023 v6->tcp_in_segs = STAT64(IN_SEG); 6024 v6->tcp_out_segs = STAT64(OUT_SEG); 6025 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6026 } 6027 #undef STAT64 6028 #undef STAT 6029 #undef STAT_IDX 6030 } 6031 6032 /** 6033 * t4_tp_get_err_stats - read TP's error MIB counters 6034 * @adap: the adapter 6035 * @st: holds the counter values 6036 * @sleep_ok: if true we may sleep while awaiting command completion 6037 * 6038 * Returns the values of TP's error counters. 6039 */ 6040 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6041 bool sleep_ok) 6042 { 6043 int nchan = adap->chip_params->nchan; 6044 6045 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6046 sleep_ok); 6047 6048 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6049 sleep_ok); 6050 6051 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6052 sleep_ok); 6053 6054 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6055 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6056 6057 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6058 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6059 6060 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6061 sleep_ok); 6062 6063 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6064 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6065 6066 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6067 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6068 6069 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6070 sleep_ok); 6071 } 6072 6073 /** 6074 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6075 * @adap: the adapter 6076 * @st: holds the counter values 6077 * 6078 * Returns the values of TP's proxy counters. 6079 */ 6080 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6081 bool sleep_ok) 6082 { 6083 int nchan = adap->chip_params->nchan; 6084 6085 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6086 } 6087 6088 /** 6089 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6090 * @adap: the adapter 6091 * @st: holds the counter values 6092 * @sleep_ok: if true we may sleep while awaiting command completion 6093 * 6094 * Returns the values of TP's CPL counters. 6095 */ 6096 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6097 bool sleep_ok) 6098 { 6099 int nchan = adap->chip_params->nchan; 6100 6101 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6102 6103 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6104 } 6105 6106 /** 6107 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6108 * @adap: the adapter 6109 * @st: holds the counter values 6110 * 6111 * Returns the values of TP's RDMA counters. 6112 */ 6113 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6114 bool sleep_ok) 6115 { 6116 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6117 sleep_ok); 6118 } 6119 6120 /** 6121 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6122 * @adap: the adapter 6123 * @idx: the port index 6124 * @st: holds the counter values 6125 * @sleep_ok: if true we may sleep while awaiting command completion 6126 * 6127 * Returns the values of TP's FCoE counters for the selected port. 6128 */ 6129 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6130 struct tp_fcoe_stats *st, bool sleep_ok) 6131 { 6132 u32 val[2]; 6133 6134 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6135 sleep_ok); 6136 6137 t4_tp_mib_read(adap, &st->frames_drop, 1, 6138 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6139 6140 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6141 sleep_ok); 6142 6143 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6144 } 6145 6146 /** 6147 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6148 * @adap: the adapter 6149 * @st: holds the counter values 6150 * @sleep_ok: if true we may sleep while awaiting command completion 6151 * 6152 * Returns the values of TP's counters for non-TCP directly-placed packets. 6153 */ 6154 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6155 bool sleep_ok) 6156 { 6157 u32 val[4]; 6158 6159 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6160 6161 st->frames = val[0]; 6162 st->drops = val[1]; 6163 st->octets = ((u64)val[2] << 32) | val[3]; 6164 } 6165 6166 /** 6167 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6168 * @adap: the adapter 6169 * @mtus: where to store the MTU values 6170 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6171 * 6172 * Reads the HW path MTU table. 6173 */ 6174 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6175 { 6176 u32 v; 6177 int i; 6178 6179 for (i = 0; i < NMTUS; ++i) { 6180 t4_write_reg(adap, A_TP_MTU_TABLE, 6181 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6182 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6183 mtus[i] = G_MTUVALUE(v); 6184 if (mtu_log) 6185 mtu_log[i] = G_MTUWIDTH(v); 6186 } 6187 } 6188 6189 /** 6190 * t4_read_cong_tbl - reads the congestion control table 6191 * @adap: the adapter 6192 * @incr: where to store the alpha values 6193 * 6194 * Reads the additive increments programmed into the HW congestion 6195 * control table. 6196 */ 6197 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6198 { 6199 unsigned int mtu, w; 6200 6201 for (mtu = 0; mtu < NMTUS; ++mtu) 6202 for (w = 0; w < NCCTRL_WIN; ++w) { 6203 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6204 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6205 incr[mtu][w] = (u16)t4_read_reg(adap, 6206 A_TP_CCTRL_TABLE) & 0x1fff; 6207 } 6208 } 6209 6210 /** 6211 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6212 * @adap: the adapter 6213 * @addr: the indirect TP register address 6214 * @mask: specifies the field within the register to modify 6215 * @val: new value for the field 6216 * 6217 * Sets a field of an indirect TP register to the given value. 6218 */ 6219 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6220 unsigned int mask, unsigned int val) 6221 { 6222 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6223 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6224 t4_write_reg(adap, A_TP_PIO_DATA, val); 6225 } 6226 6227 /** 6228 * init_cong_ctrl - initialize congestion control parameters 6229 * @a: the alpha values for congestion control 6230 * @b: the beta values for congestion control 6231 * 6232 * Initialize the congestion control parameters. 6233 */ 6234 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6235 { 6236 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6237 a[9] = 2; 6238 a[10] = 3; 6239 a[11] = 4; 6240 a[12] = 5; 6241 a[13] = 6; 6242 a[14] = 7; 6243 a[15] = 8; 6244 a[16] = 9; 6245 a[17] = 10; 6246 a[18] = 14; 6247 a[19] = 17; 6248 a[20] = 21; 6249 a[21] = 25; 6250 a[22] = 30; 6251 a[23] = 35; 6252 a[24] = 45; 6253 a[25] = 60; 6254 a[26] = 80; 6255 a[27] = 100; 6256 a[28] = 200; 6257 a[29] = 300; 6258 a[30] = 400; 6259 a[31] = 500; 6260 6261 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6262 b[9] = b[10] = 1; 6263 b[11] = b[12] = 2; 6264 b[13] = b[14] = b[15] = b[16] = 3; 6265 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6266 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6267 b[28] = b[29] = 6; 6268 b[30] = b[31] = 7; 6269 } 6270 6271 /* The minimum additive increment value for the congestion control table */ 6272 #define CC_MIN_INCR 2U 6273 6274 /** 6275 * t4_load_mtus - write the MTU and congestion control HW tables 6276 * @adap: the adapter 6277 * @mtus: the values for the MTU table 6278 * @alpha: the values for the congestion control alpha parameter 6279 * @beta: the values for the congestion control beta parameter 6280 * 6281 * Write the HW MTU table with the supplied MTUs and the high-speed 6282 * congestion control table with the supplied alpha, beta, and MTUs. 6283 * We write the two tables together because the additive increments 6284 * depend on the MTUs. 6285 */ 6286 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6287 const unsigned short *alpha, const unsigned short *beta) 6288 { 6289 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6290 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6291 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6292 28672, 40960, 57344, 81920, 114688, 163840, 229376 6293 }; 6294 6295 unsigned int i, w; 6296 6297 for (i = 0; i < NMTUS; ++i) { 6298 unsigned int mtu = mtus[i]; 6299 unsigned int log2 = fls(mtu); 6300 6301 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6302 log2--; 6303 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6304 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6305 6306 for (w = 0; w < NCCTRL_WIN; ++w) { 6307 unsigned int inc; 6308 6309 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6310 CC_MIN_INCR); 6311 6312 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6313 (w << 16) | (beta[w] << 13) | inc); 6314 } 6315 } 6316 } 6317 6318 /** 6319 * t4_set_pace_tbl - set the pace table 6320 * @adap: the adapter 6321 * @pace_vals: the pace values in microseconds 6322 * @start: index of the first entry in the HW pace table to set 6323 * @n: how many entries to set 6324 * 6325 * Sets (a subset of the) HW pace table. 6326 */ 6327 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6328 unsigned int start, unsigned int n) 6329 { 6330 unsigned int vals[NTX_SCHED], i; 6331 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6332 6333 if (n > NTX_SCHED) 6334 return -ERANGE; 6335 6336 /* convert values from us to dack ticks, rounding to closest value */ 6337 for (i = 0; i < n; i++, pace_vals++) { 6338 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6339 if (vals[i] > 0x7ff) 6340 return -ERANGE; 6341 if (*pace_vals && vals[i] == 0) 6342 return -ERANGE; 6343 } 6344 for (i = 0; i < n; i++, start++) 6345 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6346 return 0; 6347 } 6348 6349 /** 6350 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6351 * @adap: the adapter 6352 * @kbps: target rate in Kbps 6353 * @sched: the scheduler index 6354 * 6355 * Configure a Tx HW scheduler for the target rate. 6356 */ 6357 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6358 { 6359 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6360 unsigned int clk = adap->params.vpd.cclk * 1000; 6361 unsigned int selected_cpt = 0, selected_bpt = 0; 6362 6363 if (kbps > 0) { 6364 kbps *= 125; /* -> bytes */ 6365 for (cpt = 1; cpt <= 255; cpt++) { 6366 tps = clk / cpt; 6367 bpt = (kbps + tps / 2) / tps; 6368 if (bpt > 0 && bpt <= 255) { 6369 v = bpt * tps; 6370 delta = v >= kbps ? v - kbps : kbps - v; 6371 if (delta < mindelta) { 6372 mindelta = delta; 6373 selected_cpt = cpt; 6374 selected_bpt = bpt; 6375 } 6376 } else if (selected_cpt) 6377 break; 6378 } 6379 if (!selected_cpt) 6380 return -EINVAL; 6381 } 6382 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6383 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6384 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6385 if (sched & 1) 6386 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6387 else 6388 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6389 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6390 return 0; 6391 } 6392 6393 /** 6394 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6395 * @adap: the adapter 6396 * @sched: the scheduler index 6397 * @ipg: the interpacket delay in tenths of nanoseconds 6398 * 6399 * Set the interpacket delay for a HW packet rate scheduler. 6400 */ 6401 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6402 { 6403 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6404 6405 /* convert ipg to nearest number of core clocks */ 6406 ipg *= core_ticks_per_usec(adap); 6407 ipg = (ipg + 5000) / 10000; 6408 if (ipg > M_TXTIMERSEPQ0) 6409 return -EINVAL; 6410 6411 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6412 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6413 if (sched & 1) 6414 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6415 else 6416 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6417 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6418 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6419 return 0; 6420 } 6421 6422 /* 6423 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6424 * clocks. The formula is 6425 * 6426 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6427 * 6428 * which is equivalent to 6429 * 6430 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6431 */ 6432 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6433 { 6434 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6435 6436 return v * 62 + v / 2; 6437 } 6438 6439 /** 6440 * t4_get_chan_txrate - get the current per channel Tx rates 6441 * @adap: the adapter 6442 * @nic_rate: rates for NIC traffic 6443 * @ofld_rate: rates for offloaded traffic 6444 * 6445 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6446 * for each channel. 6447 */ 6448 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6449 { 6450 u32 v; 6451 6452 v = t4_read_reg(adap, A_TP_TX_TRATE); 6453 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6454 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6455 if (adap->chip_params->nchan > 2) { 6456 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6457 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6458 } 6459 6460 v = t4_read_reg(adap, A_TP_TX_ORATE); 6461 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6462 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6463 if (adap->chip_params->nchan > 2) { 6464 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6465 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6466 } 6467 } 6468 6469 /** 6470 * t4_set_trace_filter - configure one of the tracing filters 6471 * @adap: the adapter 6472 * @tp: the desired trace filter parameters 6473 * @idx: which filter to configure 6474 * @enable: whether to enable or disable the filter 6475 * 6476 * Configures one of the tracing filters available in HW. If @tp is %NULL 6477 * it indicates that the filter is already written in the register and it 6478 * just needs to be enabled or disabled. 6479 */ 6480 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6481 int idx, int enable) 6482 { 6483 int i, ofst = idx * 4; 6484 u32 data_reg, mask_reg, cfg; 6485 u32 multitrc = F_TRCMULTIFILTER; 6486 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6487 6488 if (idx < 0 || idx >= NTRACE) 6489 return -EINVAL; 6490 6491 if (tp == NULL || !enable) { 6492 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6493 enable ? en : 0); 6494 return 0; 6495 } 6496 6497 /* 6498 * TODO - After T4 data book is updated, specify the exact 6499 * section below. 6500 * 6501 * See T4 data book - MPS section for a complete description 6502 * of the below if..else handling of A_MPS_TRC_CFG register 6503 * value. 6504 */ 6505 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6506 if (cfg & F_TRCMULTIFILTER) { 6507 /* 6508 * If multiple tracers are enabled, then maximum 6509 * capture size is 2.5KB (FIFO size of a single channel) 6510 * minus 2 flits for CPL_TRACE_PKT header. 6511 */ 6512 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6513 return -EINVAL; 6514 } else { 6515 /* 6516 * If multiple tracers are disabled, to avoid deadlocks 6517 * maximum packet capture size of 9600 bytes is recommended. 6518 * Also in this mode, only trace0 can be enabled and running. 6519 */ 6520 multitrc = 0; 6521 if (tp->snap_len > 9600 || idx) 6522 return -EINVAL; 6523 } 6524 6525 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6526 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6527 tp->min_len > M_TFMINPKTSIZE) 6528 return -EINVAL; 6529 6530 /* stop the tracer we'll be changing */ 6531 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6532 6533 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6534 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6535 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6536 6537 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6538 t4_write_reg(adap, data_reg, tp->data[i]); 6539 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6540 } 6541 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6542 V_TFCAPTUREMAX(tp->snap_len) | 6543 V_TFMINPKTSIZE(tp->min_len)); 6544 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6545 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6546 (is_t4(adap) ? 6547 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6548 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6549 6550 return 0; 6551 } 6552 6553 /** 6554 * t4_get_trace_filter - query one of the tracing filters 6555 * @adap: the adapter 6556 * @tp: the current trace filter parameters 6557 * @idx: which trace filter to query 6558 * @enabled: non-zero if the filter is enabled 6559 * 6560 * Returns the current settings of one of the HW tracing filters. 6561 */ 6562 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6563 int *enabled) 6564 { 6565 u32 ctla, ctlb; 6566 int i, ofst = idx * 4; 6567 u32 data_reg, mask_reg; 6568 6569 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6570 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6571 6572 if (is_t4(adap)) { 6573 *enabled = !!(ctla & F_TFEN); 6574 tp->port = G_TFPORT(ctla); 6575 tp->invert = !!(ctla & F_TFINVERTMATCH); 6576 } else { 6577 *enabled = !!(ctla & F_T5_TFEN); 6578 tp->port = G_T5_TFPORT(ctla); 6579 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6580 } 6581 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6582 tp->min_len = G_TFMINPKTSIZE(ctlb); 6583 tp->skip_ofst = G_TFOFFSET(ctla); 6584 tp->skip_len = G_TFLENGTH(ctla); 6585 6586 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6587 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6588 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6589 6590 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6591 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6592 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6593 } 6594 } 6595 6596 /** 6597 * t4_pmtx_get_stats - returns the HW stats from PMTX 6598 * @adap: the adapter 6599 * @cnt: where to store the count statistics 6600 * @cycles: where to store the cycle statistics 6601 * 6602 * Returns performance statistics from PMTX. 6603 */ 6604 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6605 { 6606 int i; 6607 u32 data[2]; 6608 6609 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6610 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6611 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6612 if (is_t4(adap)) 6613 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6614 else { 6615 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6616 A_PM_TX_DBG_DATA, data, 2, 6617 A_PM_TX_DBG_STAT_MSB); 6618 cycles[i] = (((u64)data[0] << 32) | data[1]); 6619 } 6620 } 6621 } 6622 6623 /** 6624 * t4_pmrx_get_stats - returns the HW stats from PMRX 6625 * @adap: the adapter 6626 * @cnt: where to store the count statistics 6627 * @cycles: where to store the cycle statistics 6628 * 6629 * Returns performance statistics from PMRX. 6630 */ 6631 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6632 { 6633 int i; 6634 u32 data[2]; 6635 6636 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6637 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6638 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6639 if (is_t4(adap)) { 6640 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6641 } else { 6642 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6643 A_PM_RX_DBG_DATA, data, 2, 6644 A_PM_RX_DBG_STAT_MSB); 6645 cycles[i] = (((u64)data[0] << 32) | data[1]); 6646 } 6647 } 6648 } 6649 6650 /** 6651 * t4_get_mps_bg_map - return the buffer groups associated with a port 6652 * @adap: the adapter 6653 * @idx: the port index 6654 * 6655 * Returns a bitmap indicating which MPS buffer groups are associated 6656 * with the given port. Bit i is set if buffer group i is used by the 6657 * port. 6658 */ 6659 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6660 { 6661 u32 n; 6662 6663 if (adap->params.mps_bg_map) 6664 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6665 6666 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6667 if (n == 0) 6668 return idx == 0 ? 0xf : 0; 6669 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6670 return idx < 2 ? (3 << (2 * idx)) : 0; 6671 return 1 << idx; 6672 } 6673 6674 /* 6675 * TP RX e-channels associated with the port. 6676 */ 6677 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6678 { 6679 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6680 6681 if (n == 0) 6682 return idx == 0 ? 0xf : 0; 6683 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6684 return idx < 2 ? (3 << (2 * idx)) : 0; 6685 return 1 << idx; 6686 } 6687 6688 /** 6689 * t4_get_port_type_description - return Port Type string description 6690 * @port_type: firmware Port Type enumeration 6691 */ 6692 const char *t4_get_port_type_description(enum fw_port_type port_type) 6693 { 6694 static const char *const port_type_description[] = { 6695 "Fiber_XFI", 6696 "Fiber_XAUI", 6697 "BT_SGMII", 6698 "BT_XFI", 6699 "BT_XAUI", 6700 "KX4", 6701 "CX4", 6702 "KX", 6703 "KR", 6704 "SFP", 6705 "BP_AP", 6706 "BP4_AP", 6707 "QSFP_10G", 6708 "QSA", 6709 "QSFP", 6710 "BP40_BA", 6711 "KR4_100G", 6712 "CR4_QSFP", 6713 "CR_QSFP", 6714 "CR2_QSFP", 6715 "SFP28", 6716 "KR_SFP28", 6717 }; 6718 6719 if (port_type < ARRAY_SIZE(port_type_description)) 6720 return port_type_description[port_type]; 6721 return "UNKNOWN"; 6722 } 6723 6724 /** 6725 * t4_get_port_stats_offset - collect port stats relative to a previous 6726 * snapshot 6727 * @adap: The adapter 6728 * @idx: The port 6729 * @stats: Current stats to fill 6730 * @offset: Previous stats snapshot 6731 */ 6732 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6733 struct port_stats *stats, 6734 struct port_stats *offset) 6735 { 6736 u64 *s, *o; 6737 int i; 6738 6739 t4_get_port_stats(adap, idx, stats); 6740 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6741 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6742 i++, s++, o++) 6743 *s -= *o; 6744 } 6745 6746 /** 6747 * t4_get_port_stats - collect port statistics 6748 * @adap: the adapter 6749 * @idx: the port index 6750 * @p: the stats structure to fill 6751 * 6752 * Collect statistics related to the given port from HW. 6753 */ 6754 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6755 { 6756 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6757 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6758 6759 #define GET_STAT(name) \ 6760 t4_read_reg64(adap, \ 6761 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6762 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6763 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6764 6765 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6766 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6767 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6768 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6769 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6770 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6771 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6772 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6773 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6774 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6775 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6776 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6777 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6778 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6779 p->tx_drop = GET_STAT(TX_PORT_DROP); 6780 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6781 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6782 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6783 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6784 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6785 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6786 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6787 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6788 6789 if (chip_id(adap) >= CHELSIO_T5) { 6790 if (stat_ctl & F_COUNTPAUSESTATTX) { 6791 p->tx_frames -= p->tx_pause; 6792 p->tx_octets -= p->tx_pause * 64; 6793 } 6794 if (stat_ctl & F_COUNTPAUSEMCTX) 6795 p->tx_mcast_frames -= p->tx_pause; 6796 } 6797 6798 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6799 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6800 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6801 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6802 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6803 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6804 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6805 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6806 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 6807 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6808 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6809 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6810 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6811 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6812 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6813 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6814 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6815 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6816 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6817 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6818 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6819 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6820 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6821 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6822 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6823 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6824 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6825 6826 if (chip_id(adap) >= CHELSIO_T5) { 6827 if (stat_ctl & F_COUNTPAUSESTATRX) { 6828 p->rx_frames -= p->rx_pause; 6829 p->rx_octets -= p->rx_pause * 64; 6830 } 6831 if (stat_ctl & F_COUNTPAUSEMCRX) 6832 p->rx_mcast_frames -= p->rx_pause; 6833 } 6834 6835 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6836 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6837 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6838 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6839 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6840 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6841 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6842 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6843 6844 #undef GET_STAT 6845 #undef GET_STAT_COM 6846 } 6847 6848 /** 6849 * t4_get_lb_stats - collect loopback port statistics 6850 * @adap: the adapter 6851 * @idx: the loopback port index 6852 * @p: the stats structure to fill 6853 * 6854 * Return HW statistics for the given loopback port. 6855 */ 6856 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 6857 { 6858 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6859 6860 #define GET_STAT(name) \ 6861 t4_read_reg64(adap, \ 6862 (is_t4(adap) ? \ 6863 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 6864 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 6865 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6866 6867 p->octets = GET_STAT(BYTES); 6868 p->frames = GET_STAT(FRAMES); 6869 p->bcast_frames = GET_STAT(BCAST); 6870 p->mcast_frames = GET_STAT(MCAST); 6871 p->ucast_frames = GET_STAT(UCAST); 6872 p->error_frames = GET_STAT(ERROR); 6873 6874 p->frames_64 = GET_STAT(64B); 6875 p->frames_65_127 = GET_STAT(65B_127B); 6876 p->frames_128_255 = GET_STAT(128B_255B); 6877 p->frames_256_511 = GET_STAT(256B_511B); 6878 p->frames_512_1023 = GET_STAT(512B_1023B); 6879 p->frames_1024_1518 = GET_STAT(1024B_1518B); 6880 p->frames_1519_max = GET_STAT(1519B_MAX); 6881 p->drop = GET_STAT(DROP_FRAMES); 6882 6883 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 6884 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 6885 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 6886 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 6887 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 6888 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 6889 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 6890 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 6891 6892 #undef GET_STAT 6893 #undef GET_STAT_COM 6894 } 6895 6896 /** 6897 * t4_wol_magic_enable - enable/disable magic packet WoL 6898 * @adap: the adapter 6899 * @port: the physical port index 6900 * @addr: MAC address expected in magic packets, %NULL to disable 6901 * 6902 * Enables/disables magic packet wake-on-LAN for the selected port. 6903 */ 6904 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 6905 const u8 *addr) 6906 { 6907 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 6908 6909 if (is_t4(adap)) { 6910 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 6911 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 6912 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6913 } else { 6914 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 6915 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 6916 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6917 } 6918 6919 if (addr) { 6920 t4_write_reg(adap, mag_id_reg_l, 6921 (addr[2] << 24) | (addr[3] << 16) | 6922 (addr[4] << 8) | addr[5]); 6923 t4_write_reg(adap, mag_id_reg_h, 6924 (addr[0] << 8) | addr[1]); 6925 } 6926 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 6927 V_MAGICEN(addr != NULL)); 6928 } 6929 6930 /** 6931 * t4_wol_pat_enable - enable/disable pattern-based WoL 6932 * @adap: the adapter 6933 * @port: the physical port index 6934 * @map: bitmap of which HW pattern filters to set 6935 * @mask0: byte mask for bytes 0-63 of a packet 6936 * @mask1: byte mask for bytes 64-127 of a packet 6937 * @crc: Ethernet CRC for selected bytes 6938 * @enable: enable/disable switch 6939 * 6940 * Sets the pattern filters indicated in @map to mask out the bytes 6941 * specified in @mask0/@mask1 in received packets and compare the CRC of 6942 * the resulting packet against @crc. If @enable is %true pattern-based 6943 * WoL is enabled, otherwise disabled. 6944 */ 6945 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 6946 u64 mask0, u64 mask1, unsigned int crc, bool enable) 6947 { 6948 int i; 6949 u32 port_cfg_reg; 6950 6951 if (is_t4(adap)) 6952 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6953 else 6954 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6955 6956 if (!enable) { 6957 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 6958 return 0; 6959 } 6960 if (map > 0xff) 6961 return -EINVAL; 6962 6963 #define EPIO_REG(name) \ 6964 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 6965 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 6966 6967 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 6968 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 6969 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 6970 6971 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 6972 if (!(map & 1)) 6973 continue; 6974 6975 /* write byte masks */ 6976 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 6977 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 6978 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6979 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6980 return -ETIMEDOUT; 6981 6982 /* write CRC */ 6983 t4_write_reg(adap, EPIO_REG(DATA0), crc); 6984 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 6985 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6986 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6987 return -ETIMEDOUT; 6988 } 6989 #undef EPIO_REG 6990 6991 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 6992 return 0; 6993 } 6994 6995 /* t4_mk_filtdelwr - create a delete filter WR 6996 * @ftid: the filter ID 6997 * @wr: the filter work request to populate 6998 * @qid: ingress queue to receive the delete notification 6999 * 7000 * Creates a filter work request to delete the supplied filter. If @qid is 7001 * negative the delete notification is suppressed. 7002 */ 7003 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7004 { 7005 memset(wr, 0, sizeof(*wr)); 7006 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7007 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7008 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7009 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7010 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7011 if (qid >= 0) 7012 wr->rx_chan_rx_rpl_iq = 7013 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7014 } 7015 7016 #define INIT_CMD(var, cmd, rd_wr) do { \ 7017 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7018 F_FW_CMD_REQUEST | \ 7019 F_FW_CMD_##rd_wr); \ 7020 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7021 } while (0) 7022 7023 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7024 u32 addr, u32 val) 7025 { 7026 u32 ldst_addrspace; 7027 struct fw_ldst_cmd c; 7028 7029 memset(&c, 0, sizeof(c)); 7030 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7031 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7032 F_FW_CMD_REQUEST | 7033 F_FW_CMD_WRITE | 7034 ldst_addrspace); 7035 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7036 c.u.addrval.addr = cpu_to_be32(addr); 7037 c.u.addrval.val = cpu_to_be32(val); 7038 7039 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7040 } 7041 7042 /** 7043 * t4_mdio_rd - read a PHY register through MDIO 7044 * @adap: the adapter 7045 * @mbox: mailbox to use for the FW command 7046 * @phy_addr: the PHY address 7047 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7048 * @reg: the register to read 7049 * @valp: where to store the value 7050 * 7051 * Issues a FW command through the given mailbox to read a PHY register. 7052 */ 7053 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7054 unsigned int mmd, unsigned int reg, unsigned int *valp) 7055 { 7056 int ret; 7057 u32 ldst_addrspace; 7058 struct fw_ldst_cmd c; 7059 7060 memset(&c, 0, sizeof(c)); 7061 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7062 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7063 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7064 ldst_addrspace); 7065 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7066 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7067 V_FW_LDST_CMD_MMD(mmd)); 7068 c.u.mdio.raddr = cpu_to_be16(reg); 7069 7070 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7071 if (ret == 0) 7072 *valp = be16_to_cpu(c.u.mdio.rval); 7073 return ret; 7074 } 7075 7076 /** 7077 * t4_mdio_wr - write a PHY register through MDIO 7078 * @adap: the adapter 7079 * @mbox: mailbox to use for the FW command 7080 * @phy_addr: the PHY address 7081 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7082 * @reg: the register to write 7083 * @valp: value to write 7084 * 7085 * Issues a FW command through the given mailbox to write a PHY register. 7086 */ 7087 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7088 unsigned int mmd, unsigned int reg, unsigned int val) 7089 { 7090 u32 ldst_addrspace; 7091 struct fw_ldst_cmd c; 7092 7093 memset(&c, 0, sizeof(c)); 7094 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7095 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7096 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7097 ldst_addrspace); 7098 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7099 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7100 V_FW_LDST_CMD_MMD(mmd)); 7101 c.u.mdio.raddr = cpu_to_be16(reg); 7102 c.u.mdio.rval = cpu_to_be16(val); 7103 7104 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7105 } 7106 7107 /** 7108 * 7109 * t4_sge_decode_idma_state - decode the idma state 7110 * @adap: the adapter 7111 * @state: the state idma is stuck in 7112 */ 7113 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7114 { 7115 static const char * const t4_decode[] = { 7116 "IDMA_IDLE", 7117 "IDMA_PUSH_MORE_CPL_FIFO", 7118 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7119 "Not used", 7120 "IDMA_PHYSADDR_SEND_PCIEHDR", 7121 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7122 "IDMA_PHYSADDR_SEND_PAYLOAD", 7123 "IDMA_SEND_FIFO_TO_IMSG", 7124 "IDMA_FL_REQ_DATA_FL_PREP", 7125 "IDMA_FL_REQ_DATA_FL", 7126 "IDMA_FL_DROP", 7127 "IDMA_FL_H_REQ_HEADER_FL", 7128 "IDMA_FL_H_SEND_PCIEHDR", 7129 "IDMA_FL_H_PUSH_CPL_FIFO", 7130 "IDMA_FL_H_SEND_CPL", 7131 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7132 "IDMA_FL_H_SEND_IP_HDR", 7133 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7134 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7135 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7136 "IDMA_FL_D_SEND_PCIEHDR", 7137 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7138 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7139 "IDMA_FL_SEND_PCIEHDR", 7140 "IDMA_FL_PUSH_CPL_FIFO", 7141 "IDMA_FL_SEND_CPL", 7142 "IDMA_FL_SEND_PAYLOAD_FIRST", 7143 "IDMA_FL_SEND_PAYLOAD", 7144 "IDMA_FL_REQ_NEXT_DATA_FL", 7145 "IDMA_FL_SEND_NEXT_PCIEHDR", 7146 "IDMA_FL_SEND_PADDING", 7147 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7148 "IDMA_FL_SEND_FIFO_TO_IMSG", 7149 "IDMA_FL_REQ_DATAFL_DONE", 7150 "IDMA_FL_REQ_HEADERFL_DONE", 7151 }; 7152 static const char * const t5_decode[] = { 7153 "IDMA_IDLE", 7154 "IDMA_ALMOST_IDLE", 7155 "IDMA_PUSH_MORE_CPL_FIFO", 7156 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7157 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7158 "IDMA_PHYSADDR_SEND_PCIEHDR", 7159 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7160 "IDMA_PHYSADDR_SEND_PAYLOAD", 7161 "IDMA_SEND_FIFO_TO_IMSG", 7162 "IDMA_FL_REQ_DATA_FL", 7163 "IDMA_FL_DROP", 7164 "IDMA_FL_DROP_SEND_INC", 7165 "IDMA_FL_H_REQ_HEADER_FL", 7166 "IDMA_FL_H_SEND_PCIEHDR", 7167 "IDMA_FL_H_PUSH_CPL_FIFO", 7168 "IDMA_FL_H_SEND_CPL", 7169 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7170 "IDMA_FL_H_SEND_IP_HDR", 7171 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7172 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7173 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7174 "IDMA_FL_D_SEND_PCIEHDR", 7175 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7176 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7177 "IDMA_FL_SEND_PCIEHDR", 7178 "IDMA_FL_PUSH_CPL_FIFO", 7179 "IDMA_FL_SEND_CPL", 7180 "IDMA_FL_SEND_PAYLOAD_FIRST", 7181 "IDMA_FL_SEND_PAYLOAD", 7182 "IDMA_FL_REQ_NEXT_DATA_FL", 7183 "IDMA_FL_SEND_NEXT_PCIEHDR", 7184 "IDMA_FL_SEND_PADDING", 7185 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7186 }; 7187 static const char * const t6_decode[] = { 7188 "IDMA_IDLE", 7189 "IDMA_PUSH_MORE_CPL_FIFO", 7190 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7191 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7192 "IDMA_PHYSADDR_SEND_PCIEHDR", 7193 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7194 "IDMA_PHYSADDR_SEND_PAYLOAD", 7195 "IDMA_FL_REQ_DATA_FL", 7196 "IDMA_FL_DROP", 7197 "IDMA_FL_DROP_SEND_INC", 7198 "IDMA_FL_H_REQ_HEADER_FL", 7199 "IDMA_FL_H_SEND_PCIEHDR", 7200 "IDMA_FL_H_PUSH_CPL_FIFO", 7201 "IDMA_FL_H_SEND_CPL", 7202 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7203 "IDMA_FL_H_SEND_IP_HDR", 7204 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7205 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7206 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7207 "IDMA_FL_D_SEND_PCIEHDR", 7208 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7209 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7210 "IDMA_FL_SEND_PCIEHDR", 7211 "IDMA_FL_PUSH_CPL_FIFO", 7212 "IDMA_FL_SEND_CPL", 7213 "IDMA_FL_SEND_PAYLOAD_FIRST", 7214 "IDMA_FL_SEND_PAYLOAD", 7215 "IDMA_FL_REQ_NEXT_DATA_FL", 7216 "IDMA_FL_SEND_NEXT_PCIEHDR", 7217 "IDMA_FL_SEND_PADDING", 7218 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7219 }; 7220 static const u32 sge_regs[] = { 7221 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7222 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7223 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7224 }; 7225 const char * const *sge_idma_decode; 7226 int sge_idma_decode_nstates; 7227 int i; 7228 unsigned int chip_version = chip_id(adapter); 7229 7230 /* Select the right set of decode strings to dump depending on the 7231 * adapter chip type. 7232 */ 7233 switch (chip_version) { 7234 case CHELSIO_T4: 7235 sge_idma_decode = (const char * const *)t4_decode; 7236 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7237 break; 7238 7239 case CHELSIO_T5: 7240 sge_idma_decode = (const char * const *)t5_decode; 7241 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7242 break; 7243 7244 case CHELSIO_T6: 7245 sge_idma_decode = (const char * const *)t6_decode; 7246 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7247 break; 7248 7249 default: 7250 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7251 return; 7252 } 7253 7254 if (state < sge_idma_decode_nstates) 7255 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7256 else 7257 CH_WARN(adapter, "idma state %d unknown\n", state); 7258 7259 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7260 CH_WARN(adapter, "SGE register %#x value %#x\n", 7261 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7262 } 7263 7264 /** 7265 * t4_sge_ctxt_flush - flush the SGE context cache 7266 * @adap: the adapter 7267 * @mbox: mailbox to use for the FW command 7268 * 7269 * Issues a FW command through the given mailbox to flush the 7270 * SGE context cache. 7271 */ 7272 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 7273 { 7274 int ret; 7275 u32 ldst_addrspace; 7276 struct fw_ldst_cmd c; 7277 7278 memset(&c, 0, sizeof(c)); 7279 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC); 7280 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7281 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7282 ldst_addrspace); 7283 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7284 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7285 7286 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7287 return ret; 7288 } 7289 7290 /** 7291 * t4_fw_hello - establish communication with FW 7292 * @adap: the adapter 7293 * @mbox: mailbox to use for the FW command 7294 * @evt_mbox: mailbox to receive async FW events 7295 * @master: specifies the caller's willingness to be the device master 7296 * @state: returns the current device state (if non-NULL) 7297 * 7298 * Issues a command to establish communication with FW. Returns either 7299 * an error (negative integer) or the mailbox of the Master PF. 7300 */ 7301 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7302 enum dev_master master, enum dev_state *state) 7303 { 7304 int ret; 7305 struct fw_hello_cmd c; 7306 u32 v; 7307 unsigned int master_mbox; 7308 int retries = FW_CMD_HELLO_RETRIES; 7309 7310 retry: 7311 memset(&c, 0, sizeof(c)); 7312 INIT_CMD(c, HELLO, WRITE); 7313 c.err_to_clearinit = cpu_to_be32( 7314 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7315 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7316 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7317 mbox : M_FW_HELLO_CMD_MBMASTER) | 7318 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7319 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7320 F_FW_HELLO_CMD_CLEARINIT); 7321 7322 /* 7323 * Issue the HELLO command to the firmware. If it's not successful 7324 * but indicates that we got a "busy" or "timeout" condition, retry 7325 * the HELLO until we exhaust our retry limit. If we do exceed our 7326 * retry limit, check to see if the firmware left us any error 7327 * information and report that if so ... 7328 */ 7329 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7330 if (ret != FW_SUCCESS) { 7331 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7332 goto retry; 7333 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7334 t4_report_fw_error(adap); 7335 return ret; 7336 } 7337 7338 v = be32_to_cpu(c.err_to_clearinit); 7339 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7340 if (state) { 7341 if (v & F_FW_HELLO_CMD_ERR) 7342 *state = DEV_STATE_ERR; 7343 else if (v & F_FW_HELLO_CMD_INIT) 7344 *state = DEV_STATE_INIT; 7345 else 7346 *state = DEV_STATE_UNINIT; 7347 } 7348 7349 /* 7350 * If we're not the Master PF then we need to wait around for the 7351 * Master PF Driver to finish setting up the adapter. 7352 * 7353 * Note that we also do this wait if we're a non-Master-capable PF and 7354 * there is no current Master PF; a Master PF may show up momentarily 7355 * and we wouldn't want to fail pointlessly. (This can happen when an 7356 * OS loads lots of different drivers rapidly at the same time). In 7357 * this case, the Master PF returned by the firmware will be 7358 * M_PCIE_FW_MASTER so the test below will work ... 7359 */ 7360 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7361 master_mbox != mbox) { 7362 int waiting = FW_CMD_HELLO_TIMEOUT; 7363 7364 /* 7365 * Wait for the firmware to either indicate an error or 7366 * initialized state. If we see either of these we bail out 7367 * and report the issue to the caller. If we exhaust the 7368 * "hello timeout" and we haven't exhausted our retries, try 7369 * again. Otherwise bail with a timeout error. 7370 */ 7371 for (;;) { 7372 u32 pcie_fw; 7373 7374 msleep(50); 7375 waiting -= 50; 7376 7377 /* 7378 * If neither Error nor Initialialized are indicated 7379 * by the firmware keep waiting till we exhaust our 7380 * timeout ... and then retry if we haven't exhausted 7381 * our retries ... 7382 */ 7383 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7384 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7385 if (waiting <= 0) { 7386 if (retries-- > 0) 7387 goto retry; 7388 7389 return -ETIMEDOUT; 7390 } 7391 continue; 7392 } 7393 7394 /* 7395 * We either have an Error or Initialized condition 7396 * report errors preferentially. 7397 */ 7398 if (state) { 7399 if (pcie_fw & F_PCIE_FW_ERR) 7400 *state = DEV_STATE_ERR; 7401 else if (pcie_fw & F_PCIE_FW_INIT) 7402 *state = DEV_STATE_INIT; 7403 } 7404 7405 /* 7406 * If we arrived before a Master PF was selected and 7407 * there's not a valid Master PF, grab its identity 7408 * for our caller. 7409 */ 7410 if (master_mbox == M_PCIE_FW_MASTER && 7411 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7412 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7413 break; 7414 } 7415 } 7416 7417 return master_mbox; 7418 } 7419 7420 /** 7421 * t4_fw_bye - end communication with FW 7422 * @adap: the adapter 7423 * @mbox: mailbox to use for the FW command 7424 * 7425 * Issues a command to terminate communication with FW. 7426 */ 7427 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7428 { 7429 struct fw_bye_cmd c; 7430 7431 memset(&c, 0, sizeof(c)); 7432 INIT_CMD(c, BYE, WRITE); 7433 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7434 } 7435 7436 /** 7437 * t4_fw_reset - issue a reset to FW 7438 * @adap: the adapter 7439 * @mbox: mailbox to use for the FW command 7440 * @reset: specifies the type of reset to perform 7441 * 7442 * Issues a reset command of the specified type to FW. 7443 */ 7444 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7445 { 7446 struct fw_reset_cmd c; 7447 7448 memset(&c, 0, sizeof(c)); 7449 INIT_CMD(c, RESET, WRITE); 7450 c.val = cpu_to_be32(reset); 7451 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7452 } 7453 7454 /** 7455 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7456 * @adap: the adapter 7457 * @mbox: mailbox to use for the FW RESET command (if desired) 7458 * @force: force uP into RESET even if FW RESET command fails 7459 * 7460 * Issues a RESET command to firmware (if desired) with a HALT indication 7461 * and then puts the microprocessor into RESET state. The RESET command 7462 * will only be issued if a legitimate mailbox is provided (mbox <= 7463 * M_PCIE_FW_MASTER). 7464 * 7465 * This is generally used in order for the host to safely manipulate the 7466 * adapter without fear of conflicting with whatever the firmware might 7467 * be doing. The only way out of this state is to RESTART the firmware 7468 * ... 7469 */ 7470 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7471 { 7472 int ret = 0; 7473 7474 /* 7475 * If a legitimate mailbox is provided, issue a RESET command 7476 * with a HALT indication. 7477 */ 7478 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7479 struct fw_reset_cmd c; 7480 7481 memset(&c, 0, sizeof(c)); 7482 INIT_CMD(c, RESET, WRITE); 7483 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7484 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7485 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7486 } 7487 7488 /* 7489 * Normally we won't complete the operation if the firmware RESET 7490 * command fails but if our caller insists we'll go ahead and put the 7491 * uP into RESET. This can be useful if the firmware is hung or even 7492 * missing ... We'll have to take the risk of putting the uP into 7493 * RESET without the cooperation of firmware in that case. 7494 * 7495 * We also force the firmware's HALT flag to be on in case we bypassed 7496 * the firmware RESET command above or we're dealing with old firmware 7497 * which doesn't have the HALT capability. This will serve as a flag 7498 * for the incoming firmware to know that it's coming out of a HALT 7499 * rather than a RESET ... if it's new enough to understand that ... 7500 */ 7501 if (ret == 0 || force) { 7502 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7503 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7504 F_PCIE_FW_HALT); 7505 } 7506 7507 /* 7508 * And we always return the result of the firmware RESET command 7509 * even when we force the uP into RESET ... 7510 */ 7511 return ret; 7512 } 7513 7514 /** 7515 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7516 * @adap: the adapter 7517 * 7518 * Restart firmware previously halted by t4_fw_halt(). On successful 7519 * return the previous PF Master remains as the new PF Master and there 7520 * is no need to issue a new HELLO command, etc. 7521 */ 7522 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7523 { 7524 int ms; 7525 7526 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7527 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7528 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7529 return FW_SUCCESS; 7530 msleep(100); 7531 ms += 100; 7532 } 7533 7534 return -ETIMEDOUT; 7535 } 7536 7537 /** 7538 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7539 * @adap: the adapter 7540 * @mbox: mailbox to use for the FW RESET command (if desired) 7541 * @fw_data: the firmware image to write 7542 * @size: image size 7543 * @force: force upgrade even if firmware doesn't cooperate 7544 * 7545 * Perform all of the steps necessary for upgrading an adapter's 7546 * firmware image. Normally this requires the cooperation of the 7547 * existing firmware in order to halt all existing activities 7548 * but if an invalid mailbox token is passed in we skip that step 7549 * (though we'll still put the adapter microprocessor into RESET in 7550 * that case). 7551 * 7552 * On successful return the new firmware will have been loaded and 7553 * the adapter will have been fully RESET losing all previous setup 7554 * state. On unsuccessful return the adapter may be completely hosed ... 7555 * positive errno indicates that the adapter is ~probably~ intact, a 7556 * negative errno indicates that things are looking bad ... 7557 */ 7558 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7559 const u8 *fw_data, unsigned int size, int force) 7560 { 7561 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7562 unsigned int bootstrap = 7563 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7564 int ret; 7565 7566 if (!t4_fw_matches_chip(adap, fw_hdr)) 7567 return -EINVAL; 7568 7569 if (!bootstrap) { 7570 ret = t4_fw_halt(adap, mbox, force); 7571 if (ret < 0 && !force) 7572 return ret; 7573 } 7574 7575 ret = t4_load_fw(adap, fw_data, size); 7576 if (ret < 0 || bootstrap) 7577 return ret; 7578 7579 return t4_fw_restart(adap, mbox); 7580 } 7581 7582 /** 7583 * t4_fw_initialize - ask FW to initialize the device 7584 * @adap: the adapter 7585 * @mbox: mailbox to use for the FW command 7586 * 7587 * Issues a command to FW to partially initialize the device. This 7588 * performs initialization that generally doesn't depend on user input. 7589 */ 7590 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7591 { 7592 struct fw_initialize_cmd c; 7593 7594 memset(&c, 0, sizeof(c)); 7595 INIT_CMD(c, INITIALIZE, WRITE); 7596 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7597 } 7598 7599 /** 7600 * t4_query_params_rw - query FW or device parameters 7601 * @adap: the adapter 7602 * @mbox: mailbox to use for the FW command 7603 * @pf: the PF 7604 * @vf: the VF 7605 * @nparams: the number of parameters 7606 * @params: the parameter names 7607 * @val: the parameter values 7608 * @rw: Write and read flag 7609 * 7610 * Reads the value of FW or device parameters. Up to 7 parameters can be 7611 * queried at once. 7612 */ 7613 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7614 unsigned int vf, unsigned int nparams, const u32 *params, 7615 u32 *val, int rw) 7616 { 7617 int i, ret; 7618 struct fw_params_cmd c; 7619 __be32 *p = &c.param[0].mnem; 7620 7621 if (nparams > 7) 7622 return -EINVAL; 7623 7624 memset(&c, 0, sizeof(c)); 7625 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7626 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7627 V_FW_PARAMS_CMD_PFN(pf) | 7628 V_FW_PARAMS_CMD_VFN(vf)); 7629 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7630 7631 for (i = 0; i < nparams; i++) { 7632 *p++ = cpu_to_be32(*params++); 7633 if (rw) 7634 *p = cpu_to_be32(*(val + i)); 7635 p++; 7636 } 7637 7638 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7639 if (ret == 0) 7640 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7641 *val++ = be32_to_cpu(*p); 7642 return ret; 7643 } 7644 7645 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7646 unsigned int vf, unsigned int nparams, const u32 *params, 7647 u32 *val) 7648 { 7649 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7650 } 7651 7652 /** 7653 * t4_set_params_timeout - sets FW or device parameters 7654 * @adap: the adapter 7655 * @mbox: mailbox to use for the FW command 7656 * @pf: the PF 7657 * @vf: the VF 7658 * @nparams: the number of parameters 7659 * @params: the parameter names 7660 * @val: the parameter values 7661 * @timeout: the timeout time 7662 * 7663 * Sets the value of FW or device parameters. Up to 7 parameters can be 7664 * specified at once. 7665 */ 7666 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7667 unsigned int pf, unsigned int vf, 7668 unsigned int nparams, const u32 *params, 7669 const u32 *val, int timeout) 7670 { 7671 struct fw_params_cmd c; 7672 __be32 *p = &c.param[0].mnem; 7673 7674 if (nparams > 7) 7675 return -EINVAL; 7676 7677 memset(&c, 0, sizeof(c)); 7678 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7679 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7680 V_FW_PARAMS_CMD_PFN(pf) | 7681 V_FW_PARAMS_CMD_VFN(vf)); 7682 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7683 7684 while (nparams--) { 7685 *p++ = cpu_to_be32(*params++); 7686 *p++ = cpu_to_be32(*val++); 7687 } 7688 7689 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7690 } 7691 7692 /** 7693 * t4_set_params - sets FW or device parameters 7694 * @adap: the adapter 7695 * @mbox: mailbox to use for the FW command 7696 * @pf: the PF 7697 * @vf: the VF 7698 * @nparams: the number of parameters 7699 * @params: the parameter names 7700 * @val: the parameter values 7701 * 7702 * Sets the value of FW or device parameters. Up to 7 parameters can be 7703 * specified at once. 7704 */ 7705 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7706 unsigned int vf, unsigned int nparams, const u32 *params, 7707 const u32 *val) 7708 { 7709 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7710 FW_CMD_MAX_TIMEOUT); 7711 } 7712 7713 /** 7714 * t4_cfg_pfvf - configure PF/VF resource limits 7715 * @adap: the adapter 7716 * @mbox: mailbox to use for the FW command 7717 * @pf: the PF being configured 7718 * @vf: the VF being configured 7719 * @txq: the max number of egress queues 7720 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7721 * @rxqi: the max number of interrupt-capable ingress queues 7722 * @rxq: the max number of interruptless ingress queues 7723 * @tc: the PCI traffic class 7724 * @vi: the max number of virtual interfaces 7725 * @cmask: the channel access rights mask for the PF/VF 7726 * @pmask: the port access rights mask for the PF/VF 7727 * @nexact: the maximum number of exact MPS filters 7728 * @rcaps: read capabilities 7729 * @wxcaps: write/execute capabilities 7730 * 7731 * Configures resource limits and capabilities for a physical or virtual 7732 * function. 7733 */ 7734 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7735 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7736 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7737 unsigned int vi, unsigned int cmask, unsigned int pmask, 7738 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7739 { 7740 struct fw_pfvf_cmd c; 7741 7742 memset(&c, 0, sizeof(c)); 7743 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7744 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7745 V_FW_PFVF_CMD_VFN(vf)); 7746 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7747 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7748 V_FW_PFVF_CMD_NIQ(rxq)); 7749 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7750 V_FW_PFVF_CMD_PMASK(pmask) | 7751 V_FW_PFVF_CMD_NEQ(txq)); 7752 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7753 V_FW_PFVF_CMD_NVI(vi) | 7754 V_FW_PFVF_CMD_NEXACTF(nexact)); 7755 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7756 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7757 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7758 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7759 } 7760 7761 /** 7762 * t4_alloc_vi_func - allocate a virtual interface 7763 * @adap: the adapter 7764 * @mbox: mailbox to use for the FW command 7765 * @port: physical port associated with the VI 7766 * @pf: the PF owning the VI 7767 * @vf: the VF owning the VI 7768 * @nmac: number of MAC addresses needed (1 to 5) 7769 * @mac: the MAC addresses of the VI 7770 * @rss_size: size of RSS table slice associated with this VI 7771 * @portfunc: which Port Application Function MAC Address is desired 7772 * @idstype: Intrusion Detection Type 7773 * 7774 * Allocates a virtual interface for the given physical port. If @mac is 7775 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7776 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7777 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7778 * stored consecutively so the space needed is @nmac * 6 bytes. 7779 * Returns a negative error number or the non-negative VI id. 7780 */ 7781 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7782 unsigned int port, unsigned int pf, unsigned int vf, 7783 unsigned int nmac, u8 *mac, u16 *rss_size, 7784 unsigned int portfunc, unsigned int idstype) 7785 { 7786 int ret; 7787 struct fw_vi_cmd c; 7788 7789 memset(&c, 0, sizeof(c)); 7790 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7791 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7792 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7793 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7794 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7795 V_FW_VI_CMD_FUNC(portfunc)); 7796 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7797 c.nmac = nmac - 1; 7798 if(!rss_size) 7799 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7800 7801 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7802 if (ret) 7803 return ret; 7804 7805 if (mac) { 7806 memcpy(mac, c.mac, sizeof(c.mac)); 7807 switch (nmac) { 7808 case 5: 7809 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7810 case 4: 7811 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7812 case 3: 7813 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7814 case 2: 7815 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7816 } 7817 } 7818 if (rss_size) 7819 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7820 return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7821 } 7822 7823 /** 7824 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7825 * @adap: the adapter 7826 * @mbox: mailbox to use for the FW command 7827 * @port: physical port associated with the VI 7828 * @pf: the PF owning the VI 7829 * @vf: the VF owning the VI 7830 * @nmac: number of MAC addresses needed (1 to 5) 7831 * @mac: the MAC addresses of the VI 7832 * @rss_size: size of RSS table slice associated with this VI 7833 * 7834 * backwards compatible and convieniance routine to allocate a Virtual 7835 * Interface with a Ethernet Port Application Function and Intrustion 7836 * Detection System disabled. 7837 */ 7838 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 7839 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 7840 u16 *rss_size) 7841 { 7842 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 7843 FW_VI_FUNC_ETH, 0); 7844 } 7845 7846 /** 7847 * t4_free_vi - free a virtual interface 7848 * @adap: the adapter 7849 * @mbox: mailbox to use for the FW command 7850 * @pf: the PF owning the VI 7851 * @vf: the VF owning the VI 7852 * @viid: virtual interface identifiler 7853 * 7854 * Free a previously allocated virtual interface. 7855 */ 7856 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 7857 unsigned int vf, unsigned int viid) 7858 { 7859 struct fw_vi_cmd c; 7860 7861 memset(&c, 0, sizeof(c)); 7862 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 7863 F_FW_CMD_REQUEST | 7864 F_FW_CMD_EXEC | 7865 V_FW_VI_CMD_PFN(pf) | 7866 V_FW_VI_CMD_VFN(vf)); 7867 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 7868 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 7869 7870 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7871 } 7872 7873 /** 7874 * t4_set_rxmode - set Rx properties of a virtual interface 7875 * @adap: the adapter 7876 * @mbox: mailbox to use for the FW command 7877 * @viid: the VI id 7878 * @mtu: the new MTU or -1 7879 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 7880 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 7881 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 7882 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 7883 * @sleep_ok: if true we may sleep while awaiting command completion 7884 * 7885 * Sets Rx properties of a virtual interface. 7886 */ 7887 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 7888 int mtu, int promisc, int all_multi, int bcast, int vlanex, 7889 bool sleep_ok) 7890 { 7891 struct fw_vi_rxmode_cmd c; 7892 7893 /* convert to FW values */ 7894 if (mtu < 0) 7895 mtu = M_FW_VI_RXMODE_CMD_MTU; 7896 if (promisc < 0) 7897 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 7898 if (all_multi < 0) 7899 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 7900 if (bcast < 0) 7901 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 7902 if (vlanex < 0) 7903 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 7904 7905 memset(&c, 0, sizeof(c)); 7906 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 7907 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7908 V_FW_VI_RXMODE_CMD_VIID(viid)); 7909 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7910 c.mtu_to_vlanexen = 7911 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 7912 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 7913 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 7914 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 7915 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 7916 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7917 } 7918 7919 /** 7920 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 7921 * @adap: the adapter 7922 * @mbox: mailbox to use for the FW command 7923 * @viid: the VI id 7924 * @free: if true any existing filters for this VI id are first removed 7925 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 7926 * @addr: the MAC address(es) 7927 * @idx: where to store the index of each allocated filter 7928 * @hash: pointer to hash address filter bitmap 7929 * @sleep_ok: call is allowed to sleep 7930 * 7931 * Allocates an exact-match filter for each of the supplied addresses and 7932 * sets it to the corresponding address. If @idx is not %NULL it should 7933 * have at least @naddr entries, each of which will be set to the index of 7934 * the filter allocated for the corresponding MAC address. If a filter 7935 * could not be allocated for an address its index is set to 0xffff. 7936 * If @hash is not %NULL addresses that fail to allocate an exact filter 7937 * are hashed and update the hash filter bitmap pointed at by @hash. 7938 * 7939 * Returns a negative error number or the number of filters allocated. 7940 */ 7941 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 7942 unsigned int viid, bool free, unsigned int naddr, 7943 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 7944 { 7945 int offset, ret = 0; 7946 struct fw_vi_mac_cmd c; 7947 unsigned int nfilters = 0; 7948 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 7949 unsigned int rem = naddr; 7950 7951 if (naddr > max_naddr) 7952 return -EINVAL; 7953 7954 for (offset = 0; offset < naddr ; /**/) { 7955 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 7956 ? rem 7957 : ARRAY_SIZE(c.u.exact)); 7958 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 7959 u.exact[fw_naddr]), 16); 7960 struct fw_vi_mac_exact *p; 7961 int i; 7962 7963 memset(&c, 0, sizeof(c)); 7964 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7965 F_FW_CMD_REQUEST | 7966 F_FW_CMD_WRITE | 7967 V_FW_CMD_EXEC(free) | 7968 V_FW_VI_MAC_CMD_VIID(viid)); 7969 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 7970 V_FW_CMD_LEN16(len16)); 7971 7972 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7973 p->valid_to_idx = 7974 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7975 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 7976 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 7977 } 7978 7979 /* 7980 * It's okay if we run out of space in our MAC address arena. 7981 * Some of the addresses we submit may get stored so we need 7982 * to run through the reply to see what the results were ... 7983 */ 7984 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 7985 if (ret && ret != -FW_ENOMEM) 7986 break; 7987 7988 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7989 u16 index = G_FW_VI_MAC_CMD_IDX( 7990 be16_to_cpu(p->valid_to_idx)); 7991 7992 if (idx) 7993 idx[offset+i] = (index >= max_naddr 7994 ? 0xffff 7995 : index); 7996 if (index < max_naddr) 7997 nfilters++; 7998 else if (hash) 7999 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8000 } 8001 8002 free = false; 8003 offset += fw_naddr; 8004 rem -= fw_naddr; 8005 } 8006 8007 if (ret == 0 || ret == -FW_ENOMEM) 8008 ret = nfilters; 8009 return ret; 8010 } 8011 8012 /** 8013 * t4_change_mac - modifies the exact-match filter for a MAC address 8014 * @adap: the adapter 8015 * @mbox: mailbox to use for the FW command 8016 * @viid: the VI id 8017 * @idx: index of existing filter for old value of MAC address, or -1 8018 * @addr: the new MAC address value 8019 * @persist: whether a new MAC allocation should be persistent 8020 * @add_smt: if true also add the address to the HW SMT 8021 * 8022 * Modifies an exact-match filter and sets it to the new MAC address if 8023 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8024 * latter case the address is added persistently if @persist is %true. 8025 * 8026 * Note that in general it is not possible to modify the value of a given 8027 * filter so the generic way to modify an address filter is to free the one 8028 * being used by the old address value and allocate a new filter for the 8029 * new address value. 8030 * 8031 * Returns a negative error number or the index of the filter with the new 8032 * MAC value. Note that this index may differ from @idx. 8033 */ 8034 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8035 int idx, const u8 *addr, bool persist, bool add_smt) 8036 { 8037 int ret, mode; 8038 struct fw_vi_mac_cmd c; 8039 struct fw_vi_mac_exact *p = c.u.exact; 8040 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8041 8042 if (idx < 0) /* new allocation */ 8043 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8044 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8045 8046 memset(&c, 0, sizeof(c)); 8047 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8048 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8049 V_FW_VI_MAC_CMD_VIID(viid)); 8050 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8051 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8052 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8053 V_FW_VI_MAC_CMD_IDX(idx)); 8054 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8055 8056 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8057 if (ret == 0) { 8058 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8059 if (ret >= max_mac_addr) 8060 ret = -ENOMEM; 8061 } 8062 return ret; 8063 } 8064 8065 /** 8066 * t4_set_addr_hash - program the MAC inexact-match hash filter 8067 * @adap: the adapter 8068 * @mbox: mailbox to use for the FW command 8069 * @viid: the VI id 8070 * @ucast: whether the hash filter should also match unicast addresses 8071 * @vec: the value to be written to the hash filter 8072 * @sleep_ok: call is allowed to sleep 8073 * 8074 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8075 */ 8076 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8077 bool ucast, u64 vec, bool sleep_ok) 8078 { 8079 struct fw_vi_mac_cmd c; 8080 u32 val; 8081 8082 memset(&c, 0, sizeof(c)); 8083 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8084 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8085 V_FW_VI_ENABLE_CMD_VIID(viid)); 8086 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8087 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8088 c.freemacs_to_len16 = cpu_to_be32(val); 8089 c.u.hash.hashvec = cpu_to_be64(vec); 8090 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8091 } 8092 8093 /** 8094 * t4_enable_vi_params - enable/disable a virtual interface 8095 * @adap: the adapter 8096 * @mbox: mailbox to use for the FW command 8097 * @viid: the VI id 8098 * @rx_en: 1=enable Rx, 0=disable Rx 8099 * @tx_en: 1=enable Tx, 0=disable Tx 8100 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8101 * 8102 * Enables/disables a virtual interface. Note that setting DCB Enable 8103 * only makes sense when enabling a Virtual Interface ... 8104 */ 8105 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8106 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8107 { 8108 struct fw_vi_enable_cmd c; 8109 8110 memset(&c, 0, sizeof(c)); 8111 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8112 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8113 V_FW_VI_ENABLE_CMD_VIID(viid)); 8114 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8115 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8116 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8117 FW_LEN16(c)); 8118 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8119 } 8120 8121 /** 8122 * t4_enable_vi - enable/disable a virtual interface 8123 * @adap: the adapter 8124 * @mbox: mailbox to use for the FW command 8125 * @viid: the VI id 8126 * @rx_en: 1=enable Rx, 0=disable Rx 8127 * @tx_en: 1=enable Tx, 0=disable Tx 8128 * 8129 * Enables/disables a virtual interface. Note that setting DCB Enable 8130 * only makes sense when enabling a Virtual Interface ... 8131 */ 8132 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8133 bool rx_en, bool tx_en) 8134 { 8135 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8136 } 8137 8138 /** 8139 * t4_identify_port - identify a VI's port by blinking its LED 8140 * @adap: the adapter 8141 * @mbox: mailbox to use for the FW command 8142 * @viid: the VI id 8143 * @nblinks: how many times to blink LED at 2.5 Hz 8144 * 8145 * Identifies a VI's port by blinking its LED. 8146 */ 8147 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8148 unsigned int nblinks) 8149 { 8150 struct fw_vi_enable_cmd c; 8151 8152 memset(&c, 0, sizeof(c)); 8153 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8154 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8155 V_FW_VI_ENABLE_CMD_VIID(viid)); 8156 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8157 c.blinkdur = cpu_to_be16(nblinks); 8158 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8159 } 8160 8161 /** 8162 * t4_iq_stop - stop an ingress queue and its FLs 8163 * @adap: the adapter 8164 * @mbox: mailbox to use for the FW command 8165 * @pf: the PF owning the queues 8166 * @vf: the VF owning the queues 8167 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8168 * @iqid: ingress queue id 8169 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8170 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8171 * 8172 * Stops an ingress queue and its associated FLs, if any. This causes 8173 * any current or future data/messages destined for these queues to be 8174 * tossed. 8175 */ 8176 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8177 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8178 unsigned int fl0id, unsigned int fl1id) 8179 { 8180 struct fw_iq_cmd c; 8181 8182 memset(&c, 0, sizeof(c)); 8183 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8184 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8185 V_FW_IQ_CMD_VFN(vf)); 8186 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8187 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8188 c.iqid = cpu_to_be16(iqid); 8189 c.fl0id = cpu_to_be16(fl0id); 8190 c.fl1id = cpu_to_be16(fl1id); 8191 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8192 } 8193 8194 /** 8195 * t4_iq_free - free an ingress queue and its FLs 8196 * @adap: the adapter 8197 * @mbox: mailbox to use for the FW command 8198 * @pf: the PF owning the queues 8199 * @vf: the VF owning the queues 8200 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8201 * @iqid: ingress queue id 8202 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8203 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8204 * 8205 * Frees an ingress queue and its associated FLs, if any. 8206 */ 8207 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8208 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8209 unsigned int fl0id, unsigned int fl1id) 8210 { 8211 struct fw_iq_cmd c; 8212 8213 memset(&c, 0, sizeof(c)); 8214 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8215 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8216 V_FW_IQ_CMD_VFN(vf)); 8217 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8218 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8219 c.iqid = cpu_to_be16(iqid); 8220 c.fl0id = cpu_to_be16(fl0id); 8221 c.fl1id = cpu_to_be16(fl1id); 8222 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8223 } 8224 8225 /** 8226 * t4_eth_eq_free - free an Ethernet egress queue 8227 * @adap: the adapter 8228 * @mbox: mailbox to use for the FW command 8229 * @pf: the PF owning the queue 8230 * @vf: the VF owning the queue 8231 * @eqid: egress queue id 8232 * 8233 * Frees an Ethernet egress queue. 8234 */ 8235 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8236 unsigned int vf, unsigned int eqid) 8237 { 8238 struct fw_eq_eth_cmd c; 8239 8240 memset(&c, 0, sizeof(c)); 8241 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8242 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8243 V_FW_EQ_ETH_CMD_PFN(pf) | 8244 V_FW_EQ_ETH_CMD_VFN(vf)); 8245 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8246 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8247 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8248 } 8249 8250 /** 8251 * t4_ctrl_eq_free - free a control egress queue 8252 * @adap: the adapter 8253 * @mbox: mailbox to use for the FW command 8254 * @pf: the PF owning the queue 8255 * @vf: the VF owning the queue 8256 * @eqid: egress queue id 8257 * 8258 * Frees a control egress queue. 8259 */ 8260 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8261 unsigned int vf, unsigned int eqid) 8262 { 8263 struct fw_eq_ctrl_cmd c; 8264 8265 memset(&c, 0, sizeof(c)); 8266 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8267 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8268 V_FW_EQ_CTRL_CMD_PFN(pf) | 8269 V_FW_EQ_CTRL_CMD_VFN(vf)); 8270 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8271 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8272 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8273 } 8274 8275 /** 8276 * t4_ofld_eq_free - free an offload egress queue 8277 * @adap: the adapter 8278 * @mbox: mailbox to use for the FW command 8279 * @pf: the PF owning the queue 8280 * @vf: the VF owning the queue 8281 * @eqid: egress queue id 8282 * 8283 * Frees a control egress queue. 8284 */ 8285 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8286 unsigned int vf, unsigned int eqid) 8287 { 8288 struct fw_eq_ofld_cmd c; 8289 8290 memset(&c, 0, sizeof(c)); 8291 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8292 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8293 V_FW_EQ_OFLD_CMD_PFN(pf) | 8294 V_FW_EQ_OFLD_CMD_VFN(vf)); 8295 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8296 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8297 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8298 } 8299 8300 /** 8301 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8302 * @link_down_rc: Link Down Reason Code 8303 * 8304 * Returns a string representation of the Link Down Reason Code. 8305 */ 8306 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8307 { 8308 static const char *reason[] = { 8309 "Link Down", 8310 "Remote Fault", 8311 "Auto-negotiation Failure", 8312 "Reserved3", 8313 "Insufficient Airflow", 8314 "Unable To Determine Reason", 8315 "No RX Signal Detected", 8316 "Reserved7", 8317 }; 8318 8319 if (link_down_rc >= ARRAY_SIZE(reason)) 8320 return "Bad Reason Code"; 8321 8322 return reason[link_down_rc]; 8323 } 8324 8325 /* 8326 * Return the highest speed set in the port capabilities, in Mb/s. 8327 */ 8328 unsigned int fwcap_to_speed(uint32_t caps) 8329 { 8330 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8331 do { \ 8332 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8333 return __speed; \ 8334 } while (0) 8335 8336 TEST_SPEED_RETURN(400G, 400000); 8337 TEST_SPEED_RETURN(200G, 200000); 8338 TEST_SPEED_RETURN(100G, 100000); 8339 TEST_SPEED_RETURN(50G, 50000); 8340 TEST_SPEED_RETURN(40G, 40000); 8341 TEST_SPEED_RETURN(25G, 25000); 8342 TEST_SPEED_RETURN(10G, 10000); 8343 TEST_SPEED_RETURN(1G, 1000); 8344 TEST_SPEED_RETURN(100M, 100); 8345 8346 #undef TEST_SPEED_RETURN 8347 8348 return 0; 8349 } 8350 8351 /* 8352 * Return the port capabilities bit for the given speed, which is in Mb/s. 8353 */ 8354 uint32_t speed_to_fwcap(unsigned int speed) 8355 { 8356 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8357 do { \ 8358 if (speed == __speed) \ 8359 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8360 } while (0) 8361 8362 TEST_SPEED_RETURN(400G, 400000); 8363 TEST_SPEED_RETURN(200G, 200000); 8364 TEST_SPEED_RETURN(100G, 100000); 8365 TEST_SPEED_RETURN(50G, 50000); 8366 TEST_SPEED_RETURN(40G, 40000); 8367 TEST_SPEED_RETURN(25G, 25000); 8368 TEST_SPEED_RETURN(10G, 10000); 8369 TEST_SPEED_RETURN(1G, 1000); 8370 TEST_SPEED_RETURN(100M, 100); 8371 8372 #undef TEST_SPEED_RETURN 8373 8374 return 0; 8375 } 8376 8377 /* 8378 * Return the port capabilities bit for the highest speed in the capabilities. 8379 */ 8380 uint32_t fwcap_top_speed(uint32_t caps) 8381 { 8382 #define TEST_SPEED_RETURN(__caps_speed) \ 8383 do { \ 8384 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8385 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8386 } while (0) 8387 8388 TEST_SPEED_RETURN(400G); 8389 TEST_SPEED_RETURN(200G); 8390 TEST_SPEED_RETURN(100G); 8391 TEST_SPEED_RETURN(50G); 8392 TEST_SPEED_RETURN(40G); 8393 TEST_SPEED_RETURN(25G); 8394 TEST_SPEED_RETURN(10G); 8395 TEST_SPEED_RETURN(1G); 8396 TEST_SPEED_RETURN(100M); 8397 8398 #undef TEST_SPEED_RETURN 8399 8400 return 0; 8401 } 8402 8403 8404 /** 8405 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8406 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8407 * 8408 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8409 * 32-bit Port Capabilities value. 8410 */ 8411 static uint32_t lstatus_to_fwcap(u32 lstatus) 8412 { 8413 uint32_t linkattr = 0; 8414 8415 /* 8416 * Unfortunately the format of the Link Status in the old 8417 * 16-bit Port Information message isn't the same as the 8418 * 16-bit Port Capabilities bitfield used everywhere else ... 8419 */ 8420 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8421 linkattr |= FW_PORT_CAP32_FC_RX; 8422 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8423 linkattr |= FW_PORT_CAP32_FC_TX; 8424 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8425 linkattr |= FW_PORT_CAP32_SPEED_100M; 8426 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8427 linkattr |= FW_PORT_CAP32_SPEED_1G; 8428 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8429 linkattr |= FW_PORT_CAP32_SPEED_10G; 8430 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8431 linkattr |= FW_PORT_CAP32_SPEED_25G; 8432 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8433 linkattr |= FW_PORT_CAP32_SPEED_40G; 8434 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8435 linkattr |= FW_PORT_CAP32_SPEED_100G; 8436 8437 return linkattr; 8438 } 8439 8440 /* 8441 * Updates all fields owned by the common code in port_info and link_config 8442 * based on information provided by the firmware. Does not touch any 8443 * requested_* field. 8444 */ 8445 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8446 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8447 { 8448 struct link_config old_lc, *lc = &pi->link_cfg; 8449 unsigned char fc, fec; 8450 u32 stat, linkattr; 8451 int old_ptype, old_mtype; 8452 8453 old_ptype = pi->port_type; 8454 old_mtype = pi->mod_type; 8455 old_lc = *lc; 8456 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8457 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8458 8459 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8460 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8461 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8462 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8463 8464 lc->supported = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8465 lc->advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8466 lc->lp_advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8467 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8468 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8469 8470 linkattr = lstatus_to_fwcap(stat); 8471 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8472 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8473 8474 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8475 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8476 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8477 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8478 8479 lc->supported = be32_to_cpu(p->u.info32.pcaps32); 8480 lc->advertising = be32_to_cpu(p->u.info32.acaps32); 8481 lc->lp_advertising = be16_to_cpu(p->u.info32.lpacaps32); 8482 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8483 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8484 8485 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8486 } else { 8487 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8488 return; 8489 } 8490 8491 lc->speed = fwcap_to_speed(linkattr); 8492 8493 fc = 0; 8494 if (linkattr & FW_PORT_CAP32_FC_RX) 8495 fc |= PAUSE_RX; 8496 if (linkattr & FW_PORT_CAP32_FC_TX) 8497 fc |= PAUSE_TX; 8498 lc->fc = fc; 8499 8500 fec = FEC_NONE; 8501 if (linkattr & FW_PORT_CAP32_FEC_RS) 8502 fec |= FEC_RS; 8503 if (linkattr & FW_PORT_CAP32_FEC_BASER_RS) 8504 fec |= FEC_BASER_RS; 8505 lc->fec = fec; 8506 8507 if (mod_changed != NULL) 8508 *mod_changed = false; 8509 if (link_changed != NULL) 8510 *link_changed = false; 8511 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 8512 old_lc.supported != lc->supported) { 8513 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 8514 lc->fec_hint = lc->advertising & 8515 V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC); 8516 } 8517 if (mod_changed != NULL) 8518 *mod_changed = true; 8519 } 8520 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 8521 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 8522 if (link_changed != NULL) 8523 *link_changed = true; 8524 } 8525 } 8526 8527 /** 8528 * t4_update_port_info - retrieve and update port information if changed 8529 * @pi: the port_info 8530 * 8531 * We issue a Get Port Information Command to the Firmware and, if 8532 * successful, we check to see if anything is different from what we 8533 * last recorded and update things accordingly. 8534 */ 8535 int t4_update_port_info(struct port_info *pi) 8536 { 8537 struct adapter *sc = pi->adapter; 8538 struct fw_port_cmd cmd; 8539 enum fw_port_action action; 8540 int ret; 8541 8542 memset(&cmd, 0, sizeof(cmd)); 8543 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 8544 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8545 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 8546 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 8547 FW_PORT_ACTION_GET_PORT_INFO; 8548 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 8549 FW_LEN16(cmd)); 8550 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 8551 if (ret) 8552 return ret; 8553 8554 handle_port_info(pi, &cmd, action, NULL, NULL); 8555 return 0; 8556 } 8557 8558 /** 8559 * t4_handle_fw_rpl - process a FW reply message 8560 * @adap: the adapter 8561 * @rpl: start of the FW message 8562 * 8563 * Processes a FW message, such as link state change messages. 8564 */ 8565 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 8566 { 8567 u8 opcode = *(const u8 *)rpl; 8568 const struct fw_port_cmd *p = (const void *)rpl; 8569 enum fw_port_action action = 8570 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 8571 bool mod_changed, link_changed; 8572 8573 if (opcode == FW_PORT_CMD && 8574 (action == FW_PORT_ACTION_GET_PORT_INFO || 8575 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 8576 /* link/module state change message */ 8577 int i; 8578 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 8579 struct port_info *pi = NULL; 8580 struct link_config *lc; 8581 8582 for_each_port(adap, i) { 8583 pi = adap2pinfo(adap, i); 8584 if (pi->tx_chan == chan) 8585 break; 8586 } 8587 8588 lc = &pi->link_cfg; 8589 PORT_LOCK(pi); 8590 handle_port_info(pi, p, action, &mod_changed, &link_changed); 8591 PORT_UNLOCK(pi); 8592 if (mod_changed) 8593 t4_os_portmod_changed(pi); 8594 if (link_changed) { 8595 PORT_LOCK(pi); 8596 t4_os_link_changed(pi); 8597 PORT_UNLOCK(pi); 8598 } 8599 } else { 8600 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 8601 return -EINVAL; 8602 } 8603 return 0; 8604 } 8605 8606 /** 8607 * get_pci_mode - determine a card's PCI mode 8608 * @adapter: the adapter 8609 * @p: where to store the PCI settings 8610 * 8611 * Determines a card's PCI mode and associated parameters, such as speed 8612 * and width. 8613 */ 8614 static void get_pci_mode(struct adapter *adapter, 8615 struct pci_params *p) 8616 { 8617 u16 val; 8618 u32 pcie_cap; 8619 8620 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8621 if (pcie_cap) { 8622 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 8623 p->speed = val & PCI_EXP_LNKSTA_CLS; 8624 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 8625 } 8626 } 8627 8628 struct flash_desc { 8629 u32 vendor_and_model_id; 8630 u32 size_mb; 8631 }; 8632 8633 int t4_get_flash_params(struct adapter *adapter) 8634 { 8635 /* 8636 * Table for non-standard supported Flash parts. Note, all Flash 8637 * parts must have 64KB sectors. 8638 */ 8639 static struct flash_desc supported_flash[] = { 8640 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 8641 }; 8642 8643 int ret; 8644 u32 flashid = 0; 8645 unsigned int part, manufacturer; 8646 unsigned int density, size = 0; 8647 8648 8649 /* 8650 * Issue a Read ID Command to the Flash part. We decode supported 8651 * Flash parts and their sizes from this. There's a newer Query 8652 * Command which can retrieve detailed geometry information but many 8653 * Flash parts don't support it. 8654 */ 8655 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 8656 if (!ret) 8657 ret = sf1_read(adapter, 3, 0, 1, &flashid); 8658 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 8659 if (ret < 0) 8660 return ret; 8661 8662 /* 8663 * Check to see if it's one of our non-standard supported Flash parts. 8664 */ 8665 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 8666 if (supported_flash[part].vendor_and_model_id == flashid) { 8667 adapter->params.sf_size = 8668 supported_flash[part].size_mb; 8669 adapter->params.sf_nsec = 8670 adapter->params.sf_size / SF_SEC_SIZE; 8671 goto found; 8672 } 8673 8674 /* 8675 * Decode Flash part size. The code below looks repetative with 8676 * common encodings, but that's not guaranteed in the JEDEC 8677 * specification for the Read JADEC ID command. The only thing that 8678 * we're guaranteed by the JADEC specification is where the 8679 * Manufacturer ID is in the returned result. After that each 8680 * Manufacturer ~could~ encode things completely differently. 8681 * Note, all Flash parts must have 64KB sectors. 8682 */ 8683 manufacturer = flashid & 0xff; 8684 switch (manufacturer) { 8685 case 0x20: /* Micron/Numonix */ 8686 /* 8687 * This Density -> Size decoding table is taken from Micron 8688 * Data Sheets. 8689 */ 8690 density = (flashid >> 16) & 0xff; 8691 switch (density) { 8692 case 0x14: size = 1 << 20; break; /* 1MB */ 8693 case 0x15: size = 1 << 21; break; /* 2MB */ 8694 case 0x16: size = 1 << 22; break; /* 4MB */ 8695 case 0x17: size = 1 << 23; break; /* 8MB */ 8696 case 0x18: size = 1 << 24; break; /* 16MB */ 8697 case 0x19: size = 1 << 25; break; /* 32MB */ 8698 case 0x20: size = 1 << 26; break; /* 64MB */ 8699 case 0x21: size = 1 << 27; break; /* 128MB */ 8700 case 0x22: size = 1 << 28; break; /* 256MB */ 8701 } 8702 break; 8703 8704 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 8705 /* 8706 * This Density -> Size decoding table is taken from ISSI 8707 * Data Sheets. 8708 */ 8709 density = (flashid >> 16) & 0xff; 8710 switch (density) { 8711 case 0x16: size = 1 << 25; break; /* 32MB */ 8712 case 0x17: size = 1 << 26; break; /* 64MB */ 8713 } 8714 break; 8715 8716 case 0xc2: /* Macronix */ 8717 /* 8718 * This Density -> Size decoding table is taken from Macronix 8719 * Data Sheets. 8720 */ 8721 density = (flashid >> 16) & 0xff; 8722 switch (density) { 8723 case 0x17: size = 1 << 23; break; /* 8MB */ 8724 case 0x18: size = 1 << 24; break; /* 16MB */ 8725 } 8726 break; 8727 8728 case 0xef: /* Winbond */ 8729 /* 8730 * This Density -> Size decoding table is taken from Winbond 8731 * Data Sheets. 8732 */ 8733 density = (flashid >> 16) & 0xff; 8734 switch (density) { 8735 case 0x17: size = 1 << 23; break; /* 8MB */ 8736 case 0x18: size = 1 << 24; break; /* 16MB */ 8737 } 8738 break; 8739 } 8740 8741 /* If we didn't recognize the FLASH part, that's no real issue: the 8742 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 8743 * use a FLASH part which is at least 4MB in size and has 64KB 8744 * sectors. The unrecognized FLASH part is likely to be much larger 8745 * than 4MB, but that's all we really need. 8746 */ 8747 if (size == 0) { 8748 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 8749 size = 1 << 22; 8750 } 8751 8752 /* 8753 * Store decoded Flash size and fall through into vetting code. 8754 */ 8755 adapter->params.sf_size = size; 8756 adapter->params.sf_nsec = size / SF_SEC_SIZE; 8757 8758 found: 8759 /* 8760 * We should ~probably~ reject adapters with FLASHes which are too 8761 * small but we have some legacy FPGAs with small FLASHes that we'd 8762 * still like to use. So instead we emit a scary message ... 8763 */ 8764 if (adapter->params.sf_size < FLASH_MIN_SIZE) 8765 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 8766 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 8767 8768 return 0; 8769 } 8770 8771 static void set_pcie_completion_timeout(struct adapter *adapter, 8772 u8 range) 8773 { 8774 u16 val; 8775 u32 pcie_cap; 8776 8777 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8778 if (pcie_cap) { 8779 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 8780 val &= 0xfff0; 8781 val |= range ; 8782 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 8783 } 8784 } 8785 8786 const struct chip_params *t4_get_chip_params(int chipid) 8787 { 8788 static const struct chip_params chip_params[] = { 8789 { 8790 /* T4 */ 8791 .nchan = NCHAN, 8792 .pm_stats_cnt = PM_NSTATS, 8793 .cng_ch_bits_log = 2, 8794 .nsched_cls = 15, 8795 .cim_num_obq = CIM_NUM_OBQ, 8796 .mps_rplc_size = 128, 8797 .vfcount = 128, 8798 .sge_fl_db = F_DBPRIO, 8799 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 8800 }, 8801 { 8802 /* T5 */ 8803 .nchan = NCHAN, 8804 .pm_stats_cnt = PM_NSTATS, 8805 .cng_ch_bits_log = 2, 8806 .nsched_cls = 16, 8807 .cim_num_obq = CIM_NUM_OBQ_T5, 8808 .mps_rplc_size = 128, 8809 .vfcount = 128, 8810 .sge_fl_db = F_DBPRIO | F_DBTYPE, 8811 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8812 }, 8813 { 8814 /* T6 */ 8815 .nchan = T6_NCHAN, 8816 .pm_stats_cnt = T6_PM_NSTATS, 8817 .cng_ch_bits_log = 3, 8818 .nsched_cls = 16, 8819 .cim_num_obq = CIM_NUM_OBQ_T5, 8820 .mps_rplc_size = 256, 8821 .vfcount = 256, 8822 .sge_fl_db = 0, 8823 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8824 }, 8825 }; 8826 8827 chipid -= CHELSIO_T4; 8828 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 8829 return NULL; 8830 8831 return &chip_params[chipid]; 8832 } 8833 8834 /** 8835 * t4_prep_adapter - prepare SW and HW for operation 8836 * @adapter: the adapter 8837 * @buf: temporary space of at least VPD_LEN size provided by the caller. 8838 * 8839 * Initialize adapter SW state for the various HW modules, set initial 8840 * values for some adapter tunables, take PHYs out of reset, and 8841 * initialize the MDIO interface. 8842 */ 8843 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 8844 { 8845 int ret; 8846 uint16_t device_id; 8847 uint32_t pl_rev; 8848 8849 get_pci_mode(adapter, &adapter->params.pci); 8850 8851 pl_rev = t4_read_reg(adapter, A_PL_REV); 8852 adapter->params.chipid = G_CHIPID(pl_rev); 8853 adapter->params.rev = G_REV(pl_rev); 8854 if (adapter->params.chipid == 0) { 8855 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 8856 adapter->params.chipid = CHELSIO_T4; 8857 8858 /* T4A1 chip is not supported */ 8859 if (adapter->params.rev == 1) { 8860 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 8861 return -EINVAL; 8862 } 8863 } 8864 8865 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 8866 if (adapter->chip_params == NULL) 8867 return -EINVAL; 8868 8869 adapter->params.pci.vpd_cap_addr = 8870 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 8871 8872 ret = t4_get_flash_params(adapter); 8873 if (ret < 0) 8874 return ret; 8875 8876 /* Cards with real ASICs have the chipid in the PCIe device id */ 8877 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 8878 if (device_id >> 12 == chip_id(adapter)) 8879 adapter->params.cim_la_size = CIMLA_SIZE; 8880 else { 8881 /* FPGA */ 8882 adapter->params.fpga = 1; 8883 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 8884 } 8885 8886 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 8887 if (ret < 0) 8888 return ret; 8889 8890 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 8891 8892 /* 8893 * Default port and clock for debugging in case we can't reach FW. 8894 */ 8895 adapter->params.nports = 1; 8896 adapter->params.portvec = 1; 8897 adapter->params.vpd.cclk = 50000; 8898 8899 /* Set pci completion timeout value to 4 seconds. */ 8900 set_pcie_completion_timeout(adapter, 0xd); 8901 return 0; 8902 } 8903 8904 /** 8905 * t4_shutdown_adapter - shut down adapter, host & wire 8906 * @adapter: the adapter 8907 * 8908 * Perform an emergency shutdown of the adapter and stop it from 8909 * continuing any further communication on the ports or DMA to the 8910 * host. This is typically used when the adapter and/or firmware 8911 * have crashed and we want to prevent any further accidental 8912 * communication with the rest of the world. This will also force 8913 * the port Link Status to go down -- if register writes work -- 8914 * which should help our peers figure out that we're down. 8915 */ 8916 int t4_shutdown_adapter(struct adapter *adapter) 8917 { 8918 int port; 8919 8920 t4_intr_disable(adapter); 8921 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 8922 for_each_port(adapter, port) { 8923 u32 a_port_cfg = is_t4(adapter) ? 8924 PORT_REG(port, A_XGMAC_PORT_CFG) : 8925 T5_PORT_REG(port, A_MAC_PORT_CFG); 8926 8927 t4_write_reg(adapter, a_port_cfg, 8928 t4_read_reg(adapter, a_port_cfg) 8929 & ~V_SIGNAL_DET(1)); 8930 } 8931 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 8932 8933 return 0; 8934 } 8935 8936 /** 8937 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 8938 * @adapter: the adapter 8939 * @qid: the Queue ID 8940 * @qtype: the Ingress or Egress type for @qid 8941 * @user: true if this request is for a user mode queue 8942 * @pbar2_qoffset: BAR2 Queue Offset 8943 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 8944 * 8945 * Returns the BAR2 SGE Queue Registers information associated with the 8946 * indicated Absolute Queue ID. These are passed back in return value 8947 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 8948 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 8949 * 8950 * This may return an error which indicates that BAR2 SGE Queue 8951 * registers aren't available. If an error is not returned, then the 8952 * following values are returned: 8953 * 8954 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 8955 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 8956 * 8957 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 8958 * require the "Inferred Queue ID" ability may be used. E.g. the 8959 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 8960 * then these "Inferred Queue ID" register may not be used. 8961 */ 8962 int t4_bar2_sge_qregs(struct adapter *adapter, 8963 unsigned int qid, 8964 enum t4_bar2_qtype qtype, 8965 int user, 8966 u64 *pbar2_qoffset, 8967 unsigned int *pbar2_qid) 8968 { 8969 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 8970 u64 bar2_page_offset, bar2_qoffset; 8971 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 8972 8973 /* T4 doesn't support BAR2 SGE Queue registers for kernel 8974 * mode queues. 8975 */ 8976 if (!user && is_t4(adapter)) 8977 return -EINVAL; 8978 8979 /* Get our SGE Page Size parameters. 8980 */ 8981 page_shift = adapter->params.sge.page_shift; 8982 page_size = 1 << page_shift; 8983 8984 /* Get the right Queues per Page parameters for our Queue. 8985 */ 8986 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 8987 ? adapter->params.sge.eq_s_qpp 8988 : adapter->params.sge.iq_s_qpp); 8989 qpp_mask = (1 << qpp_shift) - 1; 8990 8991 /* Calculate the basics of the BAR2 SGE Queue register area: 8992 * o The BAR2 page the Queue registers will be in. 8993 * o The BAR2 Queue ID. 8994 * o The BAR2 Queue ID Offset into the BAR2 page. 8995 */ 8996 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 8997 bar2_qid = qid & qpp_mask; 8998 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 8999 9000 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9001 * hardware will infer the Absolute Queue ID simply from the writes to 9002 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9003 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9004 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9005 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9006 * from the BAR2 Page and BAR2 Queue ID. 9007 * 9008 * One important censequence of this is that some BAR2 SGE registers 9009 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9010 * there. But other registers synthesize the SGE Queue ID purely 9011 * from the writes to the registers -- the Write Combined Doorbell 9012 * Buffer is a good example. These BAR2 SGE Registers are only 9013 * available for those BAR2 SGE Register areas where the SGE Absolute 9014 * Queue ID can be inferred from simple writes. 9015 */ 9016 bar2_qoffset = bar2_page_offset; 9017 bar2_qinferred = (bar2_qid_offset < page_size); 9018 if (bar2_qinferred) { 9019 bar2_qoffset += bar2_qid_offset; 9020 bar2_qid = 0; 9021 } 9022 9023 *pbar2_qoffset = bar2_qoffset; 9024 *pbar2_qid = bar2_qid; 9025 return 0; 9026 } 9027 9028 /** 9029 * t4_init_devlog_params - initialize adapter->params.devlog 9030 * @adap: the adapter 9031 * @fw_attach: whether we can talk to the firmware 9032 * 9033 * Initialize various fields of the adapter's Firmware Device Log 9034 * Parameters structure. 9035 */ 9036 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9037 { 9038 struct devlog_params *dparams = &adap->params.devlog; 9039 u32 pf_dparams; 9040 unsigned int devlog_meminfo; 9041 struct fw_devlog_cmd devlog_cmd; 9042 int ret; 9043 9044 /* If we're dealing with newer firmware, the Device Log Paramerters 9045 * are stored in a designated register which allows us to access the 9046 * Device Log even if we can't talk to the firmware. 9047 */ 9048 pf_dparams = 9049 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9050 if (pf_dparams) { 9051 unsigned int nentries, nentries128; 9052 9053 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9054 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9055 9056 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9057 nentries = (nentries128 + 1) * 128; 9058 dparams->size = nentries * sizeof(struct fw_devlog_e); 9059 9060 return 0; 9061 } 9062 9063 /* 9064 * For any failing returns ... 9065 */ 9066 memset(dparams, 0, sizeof *dparams); 9067 9068 /* 9069 * If we can't talk to the firmware, there's really nothing we can do 9070 * at this point. 9071 */ 9072 if (!fw_attach) 9073 return -ENXIO; 9074 9075 /* Otherwise, ask the firmware for it's Device Log Parameters. 9076 */ 9077 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9078 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9079 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9080 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9081 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9082 &devlog_cmd); 9083 if (ret) 9084 return ret; 9085 9086 devlog_meminfo = 9087 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9088 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9089 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9090 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9091 9092 return 0; 9093 } 9094 9095 /** 9096 * t4_init_sge_params - initialize adap->params.sge 9097 * @adapter: the adapter 9098 * 9099 * Initialize various fields of the adapter's SGE Parameters structure. 9100 */ 9101 int t4_init_sge_params(struct adapter *adapter) 9102 { 9103 u32 r; 9104 struct sge_params *sp = &adapter->params.sge; 9105 unsigned i, tscale = 1; 9106 9107 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9108 sp->counter_val[0] = G_THRESHOLD_0(r); 9109 sp->counter_val[1] = G_THRESHOLD_1(r); 9110 sp->counter_val[2] = G_THRESHOLD_2(r); 9111 sp->counter_val[3] = G_THRESHOLD_3(r); 9112 9113 if (chip_id(adapter) >= CHELSIO_T6) { 9114 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9115 tscale = G_TSCALE(r); 9116 if (tscale == 0) 9117 tscale = 1; 9118 else 9119 tscale += 2; 9120 } 9121 9122 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9123 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9124 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9125 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9126 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9127 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9128 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9129 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9130 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9131 9132 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9133 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9134 if (is_t4(adapter)) 9135 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9136 else if (is_t5(adapter)) 9137 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9138 else 9139 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9140 9141 /* egress queues: log2 of # of doorbells per BAR2 page */ 9142 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9143 r >>= S_QUEUESPERPAGEPF0 + 9144 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9145 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9146 9147 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9148 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9149 r >>= S_QUEUESPERPAGEPF0 + 9150 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9151 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9152 9153 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9154 r >>= S_HOSTPAGESIZEPF0 + 9155 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9156 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9157 9158 r = t4_read_reg(adapter, A_SGE_CONTROL); 9159 sp->sge_control = r; 9160 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9161 sp->fl_pktshift = G_PKTSHIFT(r); 9162 if (chip_id(adapter) <= CHELSIO_T5) { 9163 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9164 X_INGPADBOUNDARY_SHIFT); 9165 } else { 9166 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9167 X_T6_INGPADBOUNDARY_SHIFT); 9168 } 9169 if (is_t4(adapter)) 9170 sp->pack_boundary = sp->pad_boundary; 9171 else { 9172 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9173 if (G_INGPACKBOUNDARY(r) == 0) 9174 sp->pack_boundary = 16; 9175 else 9176 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9177 } 9178 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9179 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9180 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9181 9182 return 0; 9183 } 9184 9185 /* 9186 * Read and cache the adapter's compressed filter mode and ingress config. 9187 */ 9188 static void read_filter_mode_and_ingress_config(struct adapter *adap, 9189 bool sleep_ok) 9190 { 9191 uint32_t v; 9192 struct tp_params *tpp = &adap->params.tp; 9193 9194 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP, 9195 sleep_ok); 9196 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG, 9197 sleep_ok); 9198 9199 /* 9200 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9201 * shift positions of several elements of the Compressed Filter Tuple 9202 * for this adapter which we need frequently ... 9203 */ 9204 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9205 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9206 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9207 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9208 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9209 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9210 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9211 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9212 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9213 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9214 9215 if (chip_id(adap) > CHELSIO_T4) { 9216 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9217 adap->params.tp.hash_filter_mask = v; 9218 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9219 adap->params.tp.hash_filter_mask |= (u64)v << 32; 9220 } 9221 } 9222 9223 /** 9224 * t4_init_tp_params - initialize adap->params.tp 9225 * @adap: the adapter 9226 * 9227 * Initialize various fields of the adapter's TP Parameters structure. 9228 */ 9229 int t4_init_tp_params(struct adapter *adap, bool sleep_ok) 9230 { 9231 int chan; 9232 u32 v; 9233 struct tp_params *tpp = &adap->params.tp; 9234 9235 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9236 tpp->tre = G_TIMERRESOLUTION(v); 9237 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9238 9239 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9240 for (chan = 0; chan < MAX_NCHAN; chan++) 9241 tpp->tx_modq[chan] = chan; 9242 9243 read_filter_mode_and_ingress_config(adap, sleep_ok); 9244 9245 /* 9246 * Cache a mask of the bits that represent the error vector portion of 9247 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room 9248 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE). 9249 */ 9250 tpp->err_vec_mask = htobe16(0xffff); 9251 if (chip_id(adap) > CHELSIO_T5) { 9252 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9253 if (v & F_CRXPKTENC) { 9254 tpp->err_vec_mask = 9255 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC)); 9256 } 9257 } 9258 9259 return 0; 9260 } 9261 9262 /** 9263 * t4_filter_field_shift - calculate filter field shift 9264 * @adap: the adapter 9265 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9266 * 9267 * Return the shift position of a filter field within the Compressed 9268 * Filter Tuple. The filter field is specified via its selection bit 9269 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9270 */ 9271 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9272 { 9273 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 9274 unsigned int sel; 9275 int field_shift; 9276 9277 if ((filter_mode & filter_sel) == 0) 9278 return -1; 9279 9280 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9281 switch (filter_mode & sel) { 9282 case F_FCOE: 9283 field_shift += W_FT_FCOE; 9284 break; 9285 case F_PORT: 9286 field_shift += W_FT_PORT; 9287 break; 9288 case F_VNIC_ID: 9289 field_shift += W_FT_VNIC_ID; 9290 break; 9291 case F_VLAN: 9292 field_shift += W_FT_VLAN; 9293 break; 9294 case F_TOS: 9295 field_shift += W_FT_TOS; 9296 break; 9297 case F_PROTOCOL: 9298 field_shift += W_FT_PROTOCOL; 9299 break; 9300 case F_ETHERTYPE: 9301 field_shift += W_FT_ETHERTYPE; 9302 break; 9303 case F_MACMATCH: 9304 field_shift += W_FT_MACMATCH; 9305 break; 9306 case F_MPSHITTYPE: 9307 field_shift += W_FT_MPSHITTYPE; 9308 break; 9309 case F_FRAGMENTATION: 9310 field_shift += W_FT_FRAGMENTATION; 9311 break; 9312 } 9313 } 9314 return field_shift; 9315 } 9316 9317 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9318 { 9319 u8 addr[6]; 9320 int ret, i, j; 9321 u16 rss_size; 9322 struct port_info *p = adap2pinfo(adap, port_id); 9323 u32 param, val; 9324 9325 for (i = 0, j = -1; i <= p->port_id; i++) { 9326 do { 9327 j++; 9328 } while ((adap->params.portvec & (1 << j)) == 0); 9329 } 9330 9331 p->tx_chan = j; 9332 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9333 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9334 p->lport = j; 9335 9336 if (!(adap->flags & IS_VF) || 9337 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9338 t4_update_port_info(p); 9339 } 9340 9341 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 9342 if (ret < 0) 9343 return ret; 9344 9345 p->vi[0].viid = ret; 9346 if (chip_id(adap) <= CHELSIO_T5) 9347 p->vi[0].smt_idx = (ret & 0x7f) << 1; 9348 else 9349 p->vi[0].smt_idx = (ret & 0x7f); 9350 p->vi[0].rss_size = rss_size; 9351 t4_os_set_hw_addr(p, addr); 9352 9353 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9354 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9355 V_FW_PARAMS_PARAM_YZ(p->vi[0].viid); 9356 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9357 if (ret) 9358 p->vi[0].rss_base = 0xffff; 9359 else { 9360 /* MPASS((val >> 16) == rss_size); */ 9361 p->vi[0].rss_base = val & 0xffff; 9362 } 9363 9364 return 0; 9365 } 9366 9367 /** 9368 * t4_read_cimq_cfg - read CIM queue configuration 9369 * @adap: the adapter 9370 * @base: holds the queue base addresses in bytes 9371 * @size: holds the queue sizes in bytes 9372 * @thres: holds the queue full thresholds in bytes 9373 * 9374 * Returns the current configuration of the CIM queues, starting with 9375 * the IBQs, then the OBQs. 9376 */ 9377 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9378 { 9379 unsigned int i, v; 9380 int cim_num_obq = adap->chip_params->cim_num_obq; 9381 9382 for (i = 0; i < CIM_NUM_IBQ; i++) { 9383 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9384 V_QUENUMSELECT(i)); 9385 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9386 /* value is in 256-byte units */ 9387 *base++ = G_CIMQBASE(v) * 256; 9388 *size++ = G_CIMQSIZE(v) * 256; 9389 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9390 } 9391 for (i = 0; i < cim_num_obq; i++) { 9392 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9393 V_QUENUMSELECT(i)); 9394 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9395 /* value is in 256-byte units */ 9396 *base++ = G_CIMQBASE(v) * 256; 9397 *size++ = G_CIMQSIZE(v) * 256; 9398 } 9399 } 9400 9401 /** 9402 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9403 * @adap: the adapter 9404 * @qid: the queue index 9405 * @data: where to store the queue contents 9406 * @n: capacity of @data in 32-bit words 9407 * 9408 * Reads the contents of the selected CIM queue starting at address 0 up 9409 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9410 * error and the number of 32-bit words actually read on success. 9411 */ 9412 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9413 { 9414 int i, err, attempts; 9415 unsigned int addr; 9416 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9417 9418 if (qid > 5 || (n & 3)) 9419 return -EINVAL; 9420 9421 addr = qid * nwords; 9422 if (n > nwords) 9423 n = nwords; 9424 9425 /* It might take 3-10ms before the IBQ debug read access is allowed. 9426 * Wait for 1 Sec with a delay of 1 usec. 9427 */ 9428 attempts = 1000000; 9429 9430 for (i = 0; i < n; i++, addr++) { 9431 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 9432 F_IBQDBGEN); 9433 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 9434 attempts, 1); 9435 if (err) 9436 return err; 9437 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 9438 } 9439 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 9440 return i; 9441 } 9442 9443 /** 9444 * t4_read_cim_obq - read the contents of a CIM outbound queue 9445 * @adap: the adapter 9446 * @qid: the queue index 9447 * @data: where to store the queue contents 9448 * @n: capacity of @data in 32-bit words 9449 * 9450 * Reads the contents of the selected CIM queue starting at address 0 up 9451 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9452 * error and the number of 32-bit words actually read on success. 9453 */ 9454 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9455 { 9456 int i, err; 9457 unsigned int addr, v, nwords; 9458 int cim_num_obq = adap->chip_params->cim_num_obq; 9459 9460 if ((qid > (cim_num_obq - 1)) || (n & 3)) 9461 return -EINVAL; 9462 9463 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9464 V_QUENUMSELECT(qid)); 9465 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9466 9467 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 9468 nwords = G_CIMQSIZE(v) * 64; /* same */ 9469 if (n > nwords) 9470 n = nwords; 9471 9472 for (i = 0; i < n; i++, addr++) { 9473 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 9474 F_OBQDBGEN); 9475 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 9476 2, 1); 9477 if (err) 9478 return err; 9479 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 9480 } 9481 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 9482 return i; 9483 } 9484 9485 enum { 9486 CIM_QCTL_BASE = 0, 9487 CIM_CTL_BASE = 0x2000, 9488 CIM_PBT_ADDR_BASE = 0x2800, 9489 CIM_PBT_LRF_BASE = 0x3000, 9490 CIM_PBT_DATA_BASE = 0x3800 9491 }; 9492 9493 /** 9494 * t4_cim_read - read a block from CIM internal address space 9495 * @adap: the adapter 9496 * @addr: the start address within the CIM address space 9497 * @n: number of words to read 9498 * @valp: where to store the result 9499 * 9500 * Reads a block of 4-byte words from the CIM intenal address space. 9501 */ 9502 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 9503 unsigned int *valp) 9504 { 9505 int ret = 0; 9506 9507 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 9508 return -EBUSY; 9509 9510 for ( ; !ret && n--; addr += 4) { 9511 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 9512 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 9513 0, 5, 2); 9514 if (!ret) 9515 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 9516 } 9517 return ret; 9518 } 9519 9520 /** 9521 * t4_cim_write - write a block into CIM internal address space 9522 * @adap: the adapter 9523 * @addr: the start address within the CIM address space 9524 * @n: number of words to write 9525 * @valp: set of values to write 9526 * 9527 * Writes a block of 4-byte words into the CIM intenal address space. 9528 */ 9529 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 9530 const unsigned int *valp) 9531 { 9532 int ret = 0; 9533 9534 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 9535 return -EBUSY; 9536 9537 for ( ; !ret && n--; addr += 4) { 9538 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 9539 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 9540 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 9541 0, 5, 2); 9542 } 9543 return ret; 9544 } 9545 9546 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 9547 unsigned int val) 9548 { 9549 return t4_cim_write(adap, addr, 1, &val); 9550 } 9551 9552 /** 9553 * t4_cim_ctl_read - read a block from CIM control region 9554 * @adap: the adapter 9555 * @addr: the start address within the CIM control region 9556 * @n: number of words to read 9557 * @valp: where to store the result 9558 * 9559 * Reads a block of 4-byte words from the CIM control region. 9560 */ 9561 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 9562 unsigned int *valp) 9563 { 9564 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 9565 } 9566 9567 /** 9568 * t4_cim_read_la - read CIM LA capture buffer 9569 * @adap: the adapter 9570 * @la_buf: where to store the LA data 9571 * @wrptr: the HW write pointer within the capture buffer 9572 * 9573 * Reads the contents of the CIM LA buffer with the most recent entry at 9574 * the end of the returned data and with the entry at @wrptr first. 9575 * We try to leave the LA in the running state we find it in. 9576 */ 9577 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 9578 { 9579 int i, ret; 9580 unsigned int cfg, val, idx; 9581 9582 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9583 if (ret) 9584 return ret; 9585 9586 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 9587 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 9588 if (ret) 9589 return ret; 9590 } 9591 9592 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9593 if (ret) 9594 goto restart; 9595 9596 idx = G_UPDBGLAWRPTR(val); 9597 if (wrptr) 9598 *wrptr = idx; 9599 9600 for (i = 0; i < adap->params.cim_la_size; i++) { 9601 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9602 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 9603 if (ret) 9604 break; 9605 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9606 if (ret) 9607 break; 9608 if (val & F_UPDBGLARDEN) { 9609 ret = -ETIMEDOUT; 9610 break; 9611 } 9612 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 9613 if (ret) 9614 break; 9615 9616 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */ 9617 idx = (idx + 1) & M_UPDBGLARDPTR; 9618 /* 9619 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 9620 * identify the 32-bit portion of the full 312-bit data 9621 */ 9622 if (is_t6(adap)) 9623 while ((idx & 0xf) > 9) 9624 idx = (idx + 1) % M_UPDBGLARDPTR; 9625 } 9626 restart: 9627 if (cfg & F_UPDBGLAEN) { 9628 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9629 cfg & ~F_UPDBGLARDEN); 9630 if (!ret) 9631 ret = r; 9632 } 9633 return ret; 9634 } 9635 9636 /** 9637 * t4_tp_read_la - read TP LA capture buffer 9638 * @adap: the adapter 9639 * @la_buf: where to store the LA data 9640 * @wrptr: the HW write pointer within the capture buffer 9641 * 9642 * Reads the contents of the TP LA buffer with the most recent entry at 9643 * the end of the returned data and with the entry at @wrptr first. 9644 * We leave the LA in the running state we find it in. 9645 */ 9646 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 9647 { 9648 bool last_incomplete; 9649 unsigned int i, cfg, val, idx; 9650 9651 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 9652 if (cfg & F_DBGLAENABLE) /* freeze LA */ 9653 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9654 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 9655 9656 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 9657 idx = G_DBGLAWPTR(val); 9658 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 9659 if (last_incomplete) 9660 idx = (idx + 1) & M_DBGLARPTR; 9661 if (wrptr) 9662 *wrptr = idx; 9663 9664 val &= 0xffff; 9665 val &= ~V_DBGLARPTR(M_DBGLARPTR); 9666 val |= adap->params.tp.la_mask; 9667 9668 for (i = 0; i < TPLA_SIZE; i++) { 9669 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 9670 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 9671 idx = (idx + 1) & M_DBGLARPTR; 9672 } 9673 9674 /* Wipe out last entry if it isn't valid */ 9675 if (last_incomplete) 9676 la_buf[TPLA_SIZE - 1] = ~0ULL; 9677 9678 if (cfg & F_DBGLAENABLE) /* restore running state */ 9679 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9680 cfg | adap->params.tp.la_mask); 9681 } 9682 9683 /* 9684 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 9685 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 9686 * state for more than the Warning Threshold then we'll issue a warning about 9687 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 9688 * appears to be hung every Warning Repeat second till the situation clears. 9689 * If the situation clears, we'll note that as well. 9690 */ 9691 #define SGE_IDMA_WARN_THRESH 1 9692 #define SGE_IDMA_WARN_REPEAT 300 9693 9694 /** 9695 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 9696 * @adapter: the adapter 9697 * @idma: the adapter IDMA Monitor state 9698 * 9699 * Initialize the state of an SGE Ingress DMA Monitor. 9700 */ 9701 void t4_idma_monitor_init(struct adapter *adapter, 9702 struct sge_idma_monitor_state *idma) 9703 { 9704 /* Initialize the state variables for detecting an SGE Ingress DMA 9705 * hang. The SGE has internal counters which count up on each clock 9706 * tick whenever the SGE finds its Ingress DMA State Engines in the 9707 * same state they were on the previous clock tick. The clock used is 9708 * the Core Clock so we have a limit on the maximum "time" they can 9709 * record; typically a very small number of seconds. For instance, 9710 * with a 600MHz Core Clock, we can only count up to a bit more than 9711 * 7s. So we'll synthesize a larger counter in order to not run the 9712 * risk of having the "timers" overflow and give us the flexibility to 9713 * maintain a Hung SGE State Machine of our own which operates across 9714 * a longer time frame. 9715 */ 9716 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 9717 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 9718 } 9719 9720 /** 9721 * t4_idma_monitor - monitor SGE Ingress DMA state 9722 * @adapter: the adapter 9723 * @idma: the adapter IDMA Monitor state 9724 * @hz: number of ticks/second 9725 * @ticks: number of ticks since the last IDMA Monitor call 9726 */ 9727 void t4_idma_monitor(struct adapter *adapter, 9728 struct sge_idma_monitor_state *idma, 9729 int hz, int ticks) 9730 { 9731 int i, idma_same_state_cnt[2]; 9732 9733 /* Read the SGE Debug Ingress DMA Same State Count registers. These 9734 * are counters inside the SGE which count up on each clock when the 9735 * SGE finds its Ingress DMA State Engines in the same states they 9736 * were in the previous clock. The counters will peg out at 9737 * 0xffffffff without wrapping around so once they pass the 1s 9738 * threshold they'll stay above that till the IDMA state changes. 9739 */ 9740 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 9741 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 9742 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9743 9744 for (i = 0; i < 2; i++) { 9745 u32 debug0, debug11; 9746 9747 /* If the Ingress DMA Same State Counter ("timer") is less 9748 * than 1s, then we can reset our synthesized Stall Timer and 9749 * continue. If we have previously emitted warnings about a 9750 * potential stalled Ingress Queue, issue a note indicating 9751 * that the Ingress Queue has resumed forward progress. 9752 */ 9753 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 9754 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 9755 CH_WARN(adapter, "SGE idma%d, queue %u, " 9756 "resumed after %d seconds\n", 9757 i, idma->idma_qid[i], 9758 idma->idma_stalled[i]/hz); 9759 idma->idma_stalled[i] = 0; 9760 continue; 9761 } 9762 9763 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 9764 * domain. The first time we get here it'll be because we 9765 * passed the 1s Threshold; each additional time it'll be 9766 * because the RX Timer Callback is being fired on its regular 9767 * schedule. 9768 * 9769 * If the stall is below our Potential Hung Ingress Queue 9770 * Warning Threshold, continue. 9771 */ 9772 if (idma->idma_stalled[i] == 0) { 9773 idma->idma_stalled[i] = hz; 9774 idma->idma_warn[i] = 0; 9775 } else { 9776 idma->idma_stalled[i] += ticks; 9777 idma->idma_warn[i] -= ticks; 9778 } 9779 9780 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 9781 continue; 9782 9783 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 9784 */ 9785 if (idma->idma_warn[i] > 0) 9786 continue; 9787 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 9788 9789 /* Read and save the SGE IDMA State and Queue ID information. 9790 * We do this every time in case it changes across time ... 9791 * can't be too careful ... 9792 */ 9793 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 9794 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9795 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 9796 9797 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 9798 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9799 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 9800 9801 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 9802 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 9803 i, idma->idma_qid[i], idma->idma_state[i], 9804 idma->idma_stalled[i]/hz, 9805 debug0, debug11); 9806 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 9807 } 9808 } 9809 9810 /** 9811 * t4_read_pace_tbl - read the pace table 9812 * @adap: the adapter 9813 * @pace_vals: holds the returned values 9814 * 9815 * Returns the values of TP's pace table in microseconds. 9816 */ 9817 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 9818 { 9819 unsigned int i, v; 9820 9821 for (i = 0; i < NTX_SCHED; i++) { 9822 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 9823 v = t4_read_reg(adap, A_TP_PACE_TABLE); 9824 pace_vals[i] = dack_ticks_to_usec(adap, v); 9825 } 9826 } 9827 9828 /** 9829 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 9830 * @adap: the adapter 9831 * @sched: the scheduler index 9832 * @kbps: the byte rate in Kbps 9833 * @ipg: the interpacket delay in tenths of nanoseconds 9834 * 9835 * Return the current configuration of a HW Tx scheduler. 9836 */ 9837 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 9838 unsigned int *ipg, bool sleep_ok) 9839 { 9840 unsigned int v, addr, bpt, cpt; 9841 9842 if (kbps) { 9843 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 9844 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9845 if (sched & 1) 9846 v >>= 16; 9847 bpt = (v >> 8) & 0xff; 9848 cpt = v & 0xff; 9849 if (!cpt) 9850 *kbps = 0; /* scheduler disabled */ 9851 else { 9852 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 9853 *kbps = (v * bpt) / 125; 9854 } 9855 } 9856 if (ipg) { 9857 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 9858 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9859 if (sched & 1) 9860 v >>= 16; 9861 v &= 0xffff; 9862 *ipg = (10000 * v) / core_ticks_per_usec(adap); 9863 } 9864 } 9865 9866 /** 9867 * t4_load_cfg - download config file 9868 * @adap: the adapter 9869 * @cfg_data: the cfg text file to write 9870 * @size: text file size 9871 * 9872 * Write the supplied config text file to the card's serial flash. 9873 */ 9874 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 9875 { 9876 int ret, i, n, cfg_addr; 9877 unsigned int addr; 9878 unsigned int flash_cfg_start_sec; 9879 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9880 9881 cfg_addr = t4_flash_cfg_addr(adap); 9882 if (cfg_addr < 0) 9883 return cfg_addr; 9884 9885 addr = cfg_addr; 9886 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9887 9888 if (size > FLASH_CFG_MAX_SIZE) { 9889 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 9890 FLASH_CFG_MAX_SIZE); 9891 return -EFBIG; 9892 } 9893 9894 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 9895 sf_sec_size); 9896 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9897 flash_cfg_start_sec + i - 1); 9898 /* 9899 * If size == 0 then we're simply erasing the FLASH sectors associated 9900 * with the on-adapter Firmware Configuration File. 9901 */ 9902 if (ret || size == 0) 9903 goto out; 9904 9905 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9906 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9907 if ( (size - i) < SF_PAGE_SIZE) 9908 n = size - i; 9909 else 9910 n = SF_PAGE_SIZE; 9911 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 9912 if (ret) 9913 goto out; 9914 9915 addr += SF_PAGE_SIZE; 9916 cfg_data += SF_PAGE_SIZE; 9917 } 9918 9919 out: 9920 if (ret) 9921 CH_ERR(adap, "config file %s failed %d\n", 9922 (size == 0 ? "clear" : "download"), ret); 9923 return ret; 9924 } 9925 9926 /** 9927 * t5_fw_init_extern_mem - initialize the external memory 9928 * @adap: the adapter 9929 * 9930 * Initializes the external memory on T5. 9931 */ 9932 int t5_fw_init_extern_mem(struct adapter *adap) 9933 { 9934 u32 params[1], val[1]; 9935 int ret; 9936 9937 if (!is_t5(adap)) 9938 return 0; 9939 9940 val[0] = 0xff; /* Initialize all MCs */ 9941 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9942 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 9943 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 9944 FW_CMD_MAX_TIMEOUT); 9945 9946 return ret; 9947 } 9948 9949 /* BIOS boot headers */ 9950 typedef struct pci_expansion_rom_header { 9951 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9952 u8 reserved[22]; /* Reserved per processor Architecture data */ 9953 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9954 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 9955 9956 /* Legacy PCI Expansion ROM Header */ 9957 typedef struct legacy_pci_expansion_rom_header { 9958 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9959 u8 size512; /* Current Image Size in units of 512 bytes */ 9960 u8 initentry_point[4]; 9961 u8 cksum; /* Checksum computed on the entire Image */ 9962 u8 reserved[16]; /* Reserved */ 9963 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 9964 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 9965 9966 /* EFI PCI Expansion ROM Header */ 9967 typedef struct efi_pci_expansion_rom_header { 9968 u8 signature[2]; // ROM signature. The value 0xaa55 9969 u8 initialization_size[2]; /* Units 512. Includes this header */ 9970 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 9971 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 9972 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 9973 u8 compression_type[2]; /* Compression type. */ 9974 /* 9975 * Compression type definition 9976 * 0x0: uncompressed 9977 * 0x1: Compressed 9978 * 0x2-0xFFFF: Reserved 9979 */ 9980 u8 reserved[8]; /* Reserved */ 9981 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 9982 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9983 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 9984 9985 /* PCI Data Structure Format */ 9986 typedef struct pcir_data_structure { /* PCI Data Structure */ 9987 u8 signature[4]; /* Signature. The string "PCIR" */ 9988 u8 vendor_id[2]; /* Vendor Identification */ 9989 u8 device_id[2]; /* Device Identification */ 9990 u8 vital_product[2]; /* Pointer to Vital Product Data */ 9991 u8 length[2]; /* PCIR Data Structure Length */ 9992 u8 revision; /* PCIR Data Structure Revision */ 9993 u8 class_code[3]; /* Class Code */ 9994 u8 image_length[2]; /* Image Length. Multiple of 512B */ 9995 u8 code_revision[2]; /* Revision Level of Code/Data */ 9996 u8 code_type; /* Code Type. */ 9997 /* 9998 * PCI Expansion ROM Code Types 9999 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10000 * 0x01: Open Firmware standard for PCI. FCODE 10001 * 0x02: Hewlett-Packard PA RISC. HP reserved 10002 * 0x03: EFI Image. EFI 10003 * 0x04-0xFF: Reserved. 10004 */ 10005 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10006 u8 reserved[2]; /* Reserved */ 10007 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10008 10009 /* BOOT constants */ 10010 enum { 10011 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10012 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10013 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10014 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10015 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10016 VENDOR_ID = 0x1425, /* Vendor ID */ 10017 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10018 }; 10019 10020 /* 10021 * modify_device_id - Modifies the device ID of the Boot BIOS image 10022 * @adatper: the device ID to write. 10023 * @boot_data: the boot image to modify. 10024 * 10025 * Write the supplied device ID to the boot BIOS image. 10026 */ 10027 static void modify_device_id(int device_id, u8 *boot_data) 10028 { 10029 legacy_pci_exp_rom_header_t *header; 10030 pcir_data_t *pcir_header; 10031 u32 cur_header = 0; 10032 10033 /* 10034 * Loop through all chained images and change the device ID's 10035 */ 10036 while (1) { 10037 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10038 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10039 le16_to_cpu(*(u16*)header->pcir_offset)]; 10040 10041 /* 10042 * Only modify the Device ID if code type is Legacy or HP. 10043 * 0x00: Okay to modify 10044 * 0x01: FCODE. Do not be modify 10045 * 0x03: Okay to modify 10046 * 0x04-0xFF: Do not modify 10047 */ 10048 if (pcir_header->code_type == 0x00) { 10049 u8 csum = 0; 10050 int i; 10051 10052 /* 10053 * Modify Device ID to match current adatper 10054 */ 10055 *(u16*) pcir_header->device_id = device_id; 10056 10057 /* 10058 * Set checksum temporarily to 0. 10059 * We will recalculate it later. 10060 */ 10061 header->cksum = 0x0; 10062 10063 /* 10064 * Calculate and update checksum 10065 */ 10066 for (i = 0; i < (header->size512 * 512); i++) 10067 csum += (u8)boot_data[cur_header + i]; 10068 10069 /* 10070 * Invert summed value to create the checksum 10071 * Writing new checksum value directly to the boot data 10072 */ 10073 boot_data[cur_header + 7] = -csum; 10074 10075 } else if (pcir_header->code_type == 0x03) { 10076 10077 /* 10078 * Modify Device ID to match current adatper 10079 */ 10080 *(u16*) pcir_header->device_id = device_id; 10081 10082 } 10083 10084 10085 /* 10086 * Check indicator element to identify if this is the last 10087 * image in the ROM. 10088 */ 10089 if (pcir_header->indicator & 0x80) 10090 break; 10091 10092 /* 10093 * Move header pointer up to the next image in the ROM. 10094 */ 10095 cur_header += header->size512 * 512; 10096 } 10097 } 10098 10099 /* 10100 * t4_load_boot - download boot flash 10101 * @adapter: the adapter 10102 * @boot_data: the boot image to write 10103 * @boot_addr: offset in flash to write boot_data 10104 * @size: image size 10105 * 10106 * Write the supplied boot image to the card's serial flash. 10107 * The boot image has the following sections: a 28-byte header and the 10108 * boot image. 10109 */ 10110 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10111 unsigned int boot_addr, unsigned int size) 10112 { 10113 pci_exp_rom_header_t *header; 10114 int pcir_offset ; 10115 pcir_data_t *pcir_header; 10116 int ret, addr; 10117 uint16_t device_id; 10118 unsigned int i; 10119 unsigned int boot_sector = (boot_addr * 1024 ); 10120 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10121 10122 /* 10123 * Make sure the boot image does not encroach on the firmware region 10124 */ 10125 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10126 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10127 return -EFBIG; 10128 } 10129 10130 /* 10131 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10132 * and Boot configuration data sections. These 3 boot sections span 10133 * sectors 0 to 7 in flash and live right before the FW image location. 10134 */ 10135 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10136 sf_sec_size); 10137 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10138 (boot_sector >> 16) + i - 1); 10139 10140 /* 10141 * If size == 0 then we're simply erasing the FLASH sectors associated 10142 * with the on-adapter option ROM file 10143 */ 10144 if (ret || (size == 0)) 10145 goto out; 10146 10147 /* Get boot header */ 10148 header = (pci_exp_rom_header_t *)boot_data; 10149 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10150 /* PCIR Data Structure */ 10151 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10152 10153 /* 10154 * Perform some primitive sanity testing to avoid accidentally 10155 * writing garbage over the boot sectors. We ought to check for 10156 * more but it's not worth it for now ... 10157 */ 10158 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10159 CH_ERR(adap, "boot image too small/large\n"); 10160 return -EFBIG; 10161 } 10162 10163 #ifndef CHELSIO_T4_DIAGS 10164 /* 10165 * Check BOOT ROM header signature 10166 */ 10167 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10168 CH_ERR(adap, "Boot image missing signature\n"); 10169 return -EINVAL; 10170 } 10171 10172 /* 10173 * Check PCI header signature 10174 */ 10175 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10176 CH_ERR(adap, "PCI header missing signature\n"); 10177 return -EINVAL; 10178 } 10179 10180 /* 10181 * Check Vendor ID matches Chelsio ID 10182 */ 10183 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10184 CH_ERR(adap, "Vendor ID missing signature\n"); 10185 return -EINVAL; 10186 } 10187 #endif 10188 10189 /* 10190 * Retrieve adapter's device ID 10191 */ 10192 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10193 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10194 device_id = device_id & 0xf0ff; 10195 10196 /* 10197 * Check PCIE Device ID 10198 */ 10199 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10200 /* 10201 * Change the device ID in the Boot BIOS image to match 10202 * the Device ID of the current adapter. 10203 */ 10204 modify_device_id(device_id, boot_data); 10205 } 10206 10207 /* 10208 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10209 * we finish copying the rest of the boot image. This will ensure 10210 * that the BIOS boot header will only be written if the boot image 10211 * was written in full. 10212 */ 10213 addr = boot_sector; 10214 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10215 addr += SF_PAGE_SIZE; 10216 boot_data += SF_PAGE_SIZE; 10217 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10218 if (ret) 10219 goto out; 10220 } 10221 10222 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10223 (const u8 *)header, 0); 10224 10225 out: 10226 if (ret) 10227 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10228 return ret; 10229 } 10230 10231 /* 10232 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10233 * @adapter: the adapter 10234 * 10235 * Return the address within the flash where the OptionROM Configuration 10236 * is stored, or an error if the device FLASH is too small to contain 10237 * a OptionROM Configuration. 10238 */ 10239 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10240 { 10241 /* 10242 * If the device FLASH isn't large enough to hold a Firmware 10243 * Configuration File, return an error. 10244 */ 10245 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10246 return -ENOSPC; 10247 10248 return FLASH_BOOTCFG_START; 10249 } 10250 10251 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10252 { 10253 int ret, i, n, cfg_addr; 10254 unsigned int addr; 10255 unsigned int flash_cfg_start_sec; 10256 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10257 10258 cfg_addr = t4_flash_bootcfg_addr(adap); 10259 if (cfg_addr < 0) 10260 return cfg_addr; 10261 10262 addr = cfg_addr; 10263 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10264 10265 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10266 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10267 FLASH_BOOTCFG_MAX_SIZE); 10268 return -EFBIG; 10269 } 10270 10271 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10272 sf_sec_size); 10273 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10274 flash_cfg_start_sec + i - 1); 10275 10276 /* 10277 * If size == 0 then we're simply erasing the FLASH sectors associated 10278 * with the on-adapter OptionROM Configuration File. 10279 */ 10280 if (ret || size == 0) 10281 goto out; 10282 10283 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10284 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10285 if ( (size - i) < SF_PAGE_SIZE) 10286 n = size - i; 10287 else 10288 n = SF_PAGE_SIZE; 10289 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10290 if (ret) 10291 goto out; 10292 10293 addr += SF_PAGE_SIZE; 10294 cfg_data += SF_PAGE_SIZE; 10295 } 10296 10297 out: 10298 if (ret) 10299 CH_ERR(adap, "boot config data %s failed %d\n", 10300 (size == 0 ? "clear" : "download"), ret); 10301 return ret; 10302 } 10303 10304 /** 10305 * t4_set_filter_mode - configure the optional components of filter tuples 10306 * @adap: the adapter 10307 * @mode_map: a bitmap selcting which optional filter components to enable 10308 * @sleep_ok: if true we may sleep while awaiting command completion 10309 * 10310 * Sets the filter mode by selecting the optional components to enable 10311 * in filter tuples. Returns 0 on success and a negative error if the 10312 * requested mode needs more bits than are available for optional 10313 * components. 10314 */ 10315 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 10316 bool sleep_ok) 10317 { 10318 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 10319 10320 int i, nbits = 0; 10321 10322 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 10323 if (mode_map & (1 << i)) 10324 nbits += width[i]; 10325 if (nbits > FILTER_OPT_LEN) 10326 return -EINVAL; 10327 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok); 10328 read_filter_mode_and_ingress_config(adap, sleep_ok); 10329 10330 return 0; 10331 } 10332 10333 /** 10334 * t4_clr_port_stats - clear port statistics 10335 * @adap: the adapter 10336 * @idx: the port index 10337 * 10338 * Clear HW statistics for the given port. 10339 */ 10340 void t4_clr_port_stats(struct adapter *adap, int idx) 10341 { 10342 unsigned int i; 10343 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 10344 u32 port_base_addr; 10345 10346 if (is_t4(adap)) 10347 port_base_addr = PORT_BASE(idx); 10348 else 10349 port_base_addr = T5_PORT_BASE(idx); 10350 10351 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 10352 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 10353 t4_write_reg(adap, port_base_addr + i, 0); 10354 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 10355 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 10356 t4_write_reg(adap, port_base_addr + i, 0); 10357 for (i = 0; i < 4; i++) 10358 if (bgmap & (1 << i)) { 10359 t4_write_reg(adap, 10360 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 10361 t4_write_reg(adap, 10362 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 10363 } 10364 } 10365 10366 /** 10367 * t4_i2c_rd - read I2C data from adapter 10368 * @adap: the adapter 10369 * @port: Port number if per-port device; <0 if not 10370 * @devid: per-port device ID or absolute device ID 10371 * @offset: byte offset into device I2C space 10372 * @len: byte length of I2C space data 10373 * @buf: buffer in which to return I2C data 10374 * 10375 * Reads the I2C data from the indicated device and location. 10376 */ 10377 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 10378 int port, unsigned int devid, 10379 unsigned int offset, unsigned int len, 10380 u8 *buf) 10381 { 10382 u32 ldst_addrspace; 10383 struct fw_ldst_cmd ldst; 10384 int ret; 10385 10386 if (port >= 4 || 10387 devid >= 256 || 10388 offset >= 256 || 10389 len > sizeof ldst.u.i2c.data) 10390 return -EINVAL; 10391 10392 memset(&ldst, 0, sizeof ldst); 10393 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 10394 ldst.op_to_addrspace = 10395 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 10396 F_FW_CMD_REQUEST | 10397 F_FW_CMD_READ | 10398 ldst_addrspace); 10399 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 10400 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 10401 ldst.u.i2c.did = devid; 10402 ldst.u.i2c.boffset = offset; 10403 ldst.u.i2c.blen = len; 10404 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 10405 if (!ret) 10406 memcpy(buf, ldst.u.i2c.data, len); 10407 return ret; 10408 } 10409 10410 /** 10411 * t4_i2c_wr - write I2C data to adapter 10412 * @adap: the adapter 10413 * @port: Port number if per-port device; <0 if not 10414 * @devid: per-port device ID or absolute device ID 10415 * @offset: byte offset into device I2C space 10416 * @len: byte length of I2C space data 10417 * @buf: buffer containing new I2C data 10418 * 10419 * Write the I2C data to the indicated device and location. 10420 */ 10421 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 10422 int port, unsigned int devid, 10423 unsigned int offset, unsigned int len, 10424 u8 *buf) 10425 { 10426 u32 ldst_addrspace; 10427 struct fw_ldst_cmd ldst; 10428 10429 if (port >= 4 || 10430 devid >= 256 || 10431 offset >= 256 || 10432 len > sizeof ldst.u.i2c.data) 10433 return -EINVAL; 10434 10435 memset(&ldst, 0, sizeof ldst); 10436 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 10437 ldst.op_to_addrspace = 10438 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 10439 F_FW_CMD_REQUEST | 10440 F_FW_CMD_WRITE | 10441 ldst_addrspace); 10442 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 10443 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 10444 ldst.u.i2c.did = devid; 10445 ldst.u.i2c.boffset = offset; 10446 ldst.u.i2c.blen = len; 10447 memcpy(ldst.u.i2c.data, buf, len); 10448 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 10449 } 10450 10451 /** 10452 * t4_sge_ctxt_rd - read an SGE context through FW 10453 * @adap: the adapter 10454 * @mbox: mailbox to use for the FW command 10455 * @cid: the context id 10456 * @ctype: the context type 10457 * @data: where to store the context data 10458 * 10459 * Issues a FW command through the given mailbox to read an SGE context. 10460 */ 10461 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 10462 enum ctxt_type ctype, u32 *data) 10463 { 10464 int ret; 10465 struct fw_ldst_cmd c; 10466 10467 if (ctype == CTXT_EGRESS) 10468 ret = FW_LDST_ADDRSPC_SGE_EGRC; 10469 else if (ctype == CTXT_INGRESS) 10470 ret = FW_LDST_ADDRSPC_SGE_INGC; 10471 else if (ctype == CTXT_FLM) 10472 ret = FW_LDST_ADDRSPC_SGE_FLMC; 10473 else 10474 ret = FW_LDST_ADDRSPC_SGE_CONMC; 10475 10476 memset(&c, 0, sizeof(c)); 10477 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 10478 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10479 V_FW_LDST_CMD_ADDRSPACE(ret)); 10480 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 10481 c.u.idctxt.physid = cpu_to_be32(cid); 10482 10483 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 10484 if (ret == 0) { 10485 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 10486 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 10487 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 10488 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 10489 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 10490 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 10491 } 10492 return ret; 10493 } 10494 10495 /** 10496 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 10497 * @adap: the adapter 10498 * @cid: the context id 10499 * @ctype: the context type 10500 * @data: where to store the context data 10501 * 10502 * Reads an SGE context directly, bypassing FW. This is only for 10503 * debugging when FW is unavailable. 10504 */ 10505 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 10506 u32 *data) 10507 { 10508 int i, ret; 10509 10510 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 10511 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 10512 if (!ret) 10513 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 10514 *data++ = t4_read_reg(adap, i); 10515 return ret; 10516 } 10517 10518 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 10519 int sleep_ok) 10520 { 10521 struct fw_sched_cmd cmd; 10522 10523 memset(&cmd, 0, sizeof(cmd)); 10524 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10525 F_FW_CMD_REQUEST | 10526 F_FW_CMD_WRITE); 10527 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10528 10529 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 10530 cmd.u.config.type = type; 10531 cmd.u.config.minmaxen = minmaxen; 10532 10533 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10534 NULL, sleep_ok); 10535 } 10536 10537 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 10538 int rateunit, int ratemode, int channel, int cl, 10539 int minrate, int maxrate, int weight, int pktsize, 10540 int burstsize, int sleep_ok) 10541 { 10542 struct fw_sched_cmd cmd; 10543 10544 memset(&cmd, 0, sizeof(cmd)); 10545 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10546 F_FW_CMD_REQUEST | 10547 F_FW_CMD_WRITE); 10548 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10549 10550 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10551 cmd.u.params.type = type; 10552 cmd.u.params.level = level; 10553 cmd.u.params.mode = mode; 10554 cmd.u.params.ch = channel; 10555 cmd.u.params.cl = cl; 10556 cmd.u.params.unit = rateunit; 10557 cmd.u.params.rate = ratemode; 10558 cmd.u.params.min = cpu_to_be32(minrate); 10559 cmd.u.params.max = cpu_to_be32(maxrate); 10560 cmd.u.params.weight = cpu_to_be16(weight); 10561 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10562 cmd.u.params.burstsize = cpu_to_be16(burstsize); 10563 10564 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10565 NULL, sleep_ok); 10566 } 10567 10568 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 10569 unsigned int maxrate, int sleep_ok) 10570 { 10571 struct fw_sched_cmd cmd; 10572 10573 memset(&cmd, 0, sizeof(cmd)); 10574 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10575 F_FW_CMD_REQUEST | 10576 F_FW_CMD_WRITE); 10577 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10578 10579 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10580 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10581 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 10582 cmd.u.params.ch = channel; 10583 cmd.u.params.rate = ratemode; /* REL or ABS */ 10584 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 10585 10586 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10587 NULL, sleep_ok); 10588 } 10589 10590 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 10591 int weight, int sleep_ok) 10592 { 10593 struct fw_sched_cmd cmd; 10594 10595 if (weight < 0 || weight > 100) 10596 return -EINVAL; 10597 10598 memset(&cmd, 0, sizeof(cmd)); 10599 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10600 F_FW_CMD_REQUEST | 10601 F_FW_CMD_WRITE); 10602 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10603 10604 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10605 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10606 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 10607 cmd.u.params.ch = channel; 10608 cmd.u.params.cl = cl; 10609 cmd.u.params.weight = cpu_to_be16(weight); 10610 10611 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10612 NULL, sleep_ok); 10613 } 10614 10615 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 10616 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 10617 { 10618 struct fw_sched_cmd cmd; 10619 10620 memset(&cmd, 0, sizeof(cmd)); 10621 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10622 F_FW_CMD_REQUEST | 10623 F_FW_CMD_WRITE); 10624 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10625 10626 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10627 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10628 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 10629 cmd.u.params.mode = mode; 10630 cmd.u.params.ch = channel; 10631 cmd.u.params.cl = cl; 10632 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 10633 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 10634 cmd.u.params.max = cpu_to_be32(maxrate); 10635 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10636 10637 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10638 NULL, sleep_ok); 10639 } 10640 10641 /* 10642 * t4_config_watchdog - configure (enable/disable) a watchdog timer 10643 * @adapter: the adapter 10644 * @mbox: mailbox to use for the FW command 10645 * @pf: the PF owning the queue 10646 * @vf: the VF owning the queue 10647 * @timeout: watchdog timeout in ms 10648 * @action: watchdog timer / action 10649 * 10650 * There are separate watchdog timers for each possible watchdog 10651 * action. Configure one of the watchdog timers by setting a non-zero 10652 * timeout. Disable a watchdog timer by using a timeout of zero. 10653 */ 10654 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 10655 unsigned int pf, unsigned int vf, 10656 unsigned int timeout, unsigned int action) 10657 { 10658 struct fw_watchdog_cmd wdog; 10659 unsigned int ticks; 10660 10661 /* 10662 * The watchdog command expects a timeout in units of 10ms so we need 10663 * to convert it here (via rounding) and force a minimum of one 10ms 10664 * "tick" if the timeout is non-zero but the conversion results in 0 10665 * ticks. 10666 */ 10667 ticks = (timeout + 5)/10; 10668 if (timeout && !ticks) 10669 ticks = 1; 10670 10671 memset(&wdog, 0, sizeof wdog); 10672 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 10673 F_FW_CMD_REQUEST | 10674 F_FW_CMD_WRITE | 10675 V_FW_PARAMS_CMD_PFN(pf) | 10676 V_FW_PARAMS_CMD_VFN(vf)); 10677 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 10678 wdog.timeout = cpu_to_be32(ticks); 10679 wdog.action = cpu_to_be32(action); 10680 10681 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 10682 } 10683 10684 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 10685 { 10686 struct fw_devlog_cmd devlog_cmd; 10687 int ret; 10688 10689 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10690 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10691 F_FW_CMD_REQUEST | F_FW_CMD_READ); 10692 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10693 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10694 sizeof(devlog_cmd), &devlog_cmd); 10695 if (ret) 10696 return ret; 10697 10698 *level = devlog_cmd.level; 10699 return 0; 10700 } 10701 10702 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 10703 { 10704 struct fw_devlog_cmd devlog_cmd; 10705 10706 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10707 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10708 F_FW_CMD_REQUEST | 10709 F_FW_CMD_WRITE); 10710 devlog_cmd.level = level; 10711 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10712 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10713 sizeof(devlog_cmd), &devlog_cmd); 10714 } 10715