xref: /freebsd/sys/dev/cxgbe/common/t4_hw.c (revision d93a896ef95946b0bf1219866fcb324b78543444)
1 /*-
2  * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include "opt_inet.h"
31 
32 #include <sys/param.h>
33 #include <sys/eventhandler.h>
34 
35 #include "common.h"
36 #include "t4_regs.h"
37 #include "t4_regs_values.h"
38 #include "firmware/t4fw_interface.h"
39 
40 #undef msleep
41 #define msleep(x) do { \
42 	if (cold) \
43 		DELAY((x) * 1000); \
44 	else \
45 		pause("t4hw", (x) * hz / 1000); \
46 } while (0)
47 
48 /**
49  *	t4_wait_op_done_val - wait until an operation is completed
50  *	@adapter: the adapter performing the operation
51  *	@reg: the register to check for completion
52  *	@mask: a single-bit field within @reg that indicates completion
53  *	@polarity: the value of the field when the operation is completed
54  *	@attempts: number of check iterations
55  *	@delay: delay in usecs between iterations
56  *	@valp: where to store the value of the register at completion time
57  *
58  *	Wait until an operation is completed by checking a bit in a register
59  *	up to @attempts times.  If @valp is not NULL the value of the register
60  *	at the time it indicated completion is stored there.  Returns 0 if the
61  *	operation completes and	-EAGAIN	otherwise.
62  */
63 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
64 			       int polarity, int attempts, int delay, u32 *valp)
65 {
66 	while (1) {
67 		u32 val = t4_read_reg(adapter, reg);
68 
69 		if (!!(val & mask) == polarity) {
70 			if (valp)
71 				*valp = val;
72 			return 0;
73 		}
74 		if (--attempts == 0)
75 			return -EAGAIN;
76 		if (delay)
77 			udelay(delay);
78 	}
79 }
80 
81 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
82 				  int polarity, int attempts, int delay)
83 {
84 	return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
85 				   delay, NULL);
86 }
87 
88 /**
89  *	t4_set_reg_field - set a register field to a value
90  *	@adapter: the adapter to program
91  *	@addr: the register address
92  *	@mask: specifies the portion of the register to modify
93  *	@val: the new value for the register field
94  *
95  *	Sets a register field specified by the supplied mask to the
96  *	given value.
97  */
98 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
99 		      u32 val)
100 {
101 	u32 v = t4_read_reg(adapter, addr) & ~mask;
102 
103 	t4_write_reg(adapter, addr, v | val);
104 	(void) t4_read_reg(adapter, addr);      /* flush */
105 }
106 
107 /**
108  *	t4_read_indirect - read indirectly addressed registers
109  *	@adap: the adapter
110  *	@addr_reg: register holding the indirect address
111  *	@data_reg: register holding the value of the indirect register
112  *	@vals: where the read register values are stored
113  *	@nregs: how many indirect registers to read
114  *	@start_idx: index of first indirect register to read
115  *
116  *	Reads registers that are accessed indirectly through an address/data
117  *	register pair.
118  */
119 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
120 			     unsigned int data_reg, u32 *vals,
121 			     unsigned int nregs, unsigned int start_idx)
122 {
123 	while (nregs--) {
124 		t4_write_reg(adap, addr_reg, start_idx);
125 		*vals++ = t4_read_reg(adap, data_reg);
126 		start_idx++;
127 	}
128 }
129 
130 /**
131  *	t4_write_indirect - write indirectly addressed registers
132  *	@adap: the adapter
133  *	@addr_reg: register holding the indirect addresses
134  *	@data_reg: register holding the value for the indirect registers
135  *	@vals: values to write
136  *	@nregs: how many indirect registers to write
137  *	@start_idx: address of first indirect register to write
138  *
139  *	Writes a sequential block of registers that are accessed indirectly
140  *	through an address/data register pair.
141  */
142 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
143 		       unsigned int data_reg, const u32 *vals,
144 		       unsigned int nregs, unsigned int start_idx)
145 {
146 	while (nregs--) {
147 		t4_write_reg(adap, addr_reg, start_idx++);
148 		t4_write_reg(adap, data_reg, *vals++);
149 	}
150 }
151 
152 /*
153  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
154  * mechanism.  This guarantees that we get the real value even if we're
155  * operating within a Virtual Machine and the Hypervisor is trapping our
156  * Configuration Space accesses.
157  *
158  * N.B. This routine should only be used as a last resort: the firmware uses
159  *      the backdoor registers on a regular basis and we can end up
160  *      conflicting with it's uses!
161  */
162 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
163 {
164 	u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
165 	u32 val;
166 
167 	if (chip_id(adap) <= CHELSIO_T5)
168 		req |= F_ENABLE;
169 	else
170 		req |= F_T6_ENABLE;
171 
172 	if (is_t4(adap))
173 		req |= F_LOCALCFG;
174 
175 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
176 	val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
177 
178 	/*
179 	 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
180 	 * Configuration Space read.  (None of the other fields matter when
181 	 * F_ENABLE is 0 so a simple register write is easier than a
182 	 * read-modify-write via t4_set_reg_field().)
183 	 */
184 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
185 
186 	return val;
187 }
188 
189 /*
190  * t4_report_fw_error - report firmware error
191  * @adap: the adapter
192  *
193  * The adapter firmware can indicate error conditions to the host.
194  * If the firmware has indicated an error, print out the reason for
195  * the firmware error.
196  */
197 static void t4_report_fw_error(struct adapter *adap)
198 {
199 	static const char *const reason[] = {
200 		"Crash",			/* PCIE_FW_EVAL_CRASH */
201 		"During Device Preparation",	/* PCIE_FW_EVAL_PREP */
202 		"During Device Configuration",	/* PCIE_FW_EVAL_CONF */
203 		"During Device Initialization",	/* PCIE_FW_EVAL_INIT */
204 		"Unexpected Event",		/* PCIE_FW_EVAL_UNEXPECTEDEVENT */
205 		"Insufficient Airflow",		/* PCIE_FW_EVAL_OVERHEAT */
206 		"Device Shutdown",		/* PCIE_FW_EVAL_DEVICESHUTDOWN */
207 		"Reserved",			/* reserved */
208 	};
209 	u32 pcie_fw;
210 
211 	pcie_fw = t4_read_reg(adap, A_PCIE_FW);
212 	if (pcie_fw & F_PCIE_FW_ERR)
213 		CH_ERR(adap, "Firmware reports adapter error: %s\n",
214 			reason[G_PCIE_FW_EVAL(pcie_fw)]);
215 }
216 
217 /*
218  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
219  */
220 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
221 			 u32 mbox_addr)
222 {
223 	for ( ; nflit; nflit--, mbox_addr += 8)
224 		*rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
225 }
226 
227 /*
228  * Handle a FW assertion reported in a mailbox.
229  */
230 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
231 {
232 	CH_ALERT(adap,
233 		  "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
234 		  asrt->u.assert.filename_0_7,
235 		  be32_to_cpu(asrt->u.assert.line),
236 		  be32_to_cpu(asrt->u.assert.x),
237 		  be32_to_cpu(asrt->u.assert.y));
238 }
239 
240 #define X_CIM_PF_NOACCESS 0xeeeeeeee
241 /**
242  *	t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
243  *	@adap: the adapter
244  *	@mbox: index of the mailbox to use
245  *	@cmd: the command to write
246  *	@size: command length in bytes
247  *	@rpl: where to optionally store the reply
248  *	@sleep_ok: if true we may sleep while awaiting command completion
249  *	@timeout: time to wait for command to finish before timing out
250  *		(negative implies @sleep_ok=false)
251  *
252  *	Sends the given command to FW through the selected mailbox and waits
253  *	for the FW to execute the command.  If @rpl is not %NULL it is used to
254  *	store the FW's reply to the command.  The command and its optional
255  *	reply are of the same length.  Some FW commands like RESET and
256  *	INITIALIZE can take a considerable amount of time to execute.
257  *	@sleep_ok determines whether we may sleep while awaiting the response.
258  *	If sleeping is allowed we use progressive backoff otherwise we spin.
259  *	Note that passing in a negative @timeout is an alternate mechanism
260  *	for specifying @sleep_ok=false.  This is useful when a higher level
261  *	interface allows for specification of @timeout but not @sleep_ok ...
262  *
263  *	The return value is 0 on success or a negative errno on failure.  A
264  *	failure can happen either because we are not able to execute the
265  *	command or FW executes it but signals an error.  In the latter case
266  *	the return value is the error code indicated by FW (negated).
267  */
268 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
269 			    int size, void *rpl, bool sleep_ok, int timeout)
270 {
271 	/*
272 	 * We delay in small increments at first in an effort to maintain
273 	 * responsiveness for simple, fast executing commands but then back
274 	 * off to larger delays to a maximum retry delay.
275 	 */
276 	static const int delay[] = {
277 		1, 1, 3, 5, 10, 10, 20, 50, 100
278 	};
279 	u32 v;
280 	u64 res;
281 	int i, ms, delay_idx, ret;
282 	const __be64 *p = cmd;
283 	u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
284 	u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
285 	u32 ctl;
286 	__be64 cmd_rpl[MBOX_LEN/8];
287 	u32 pcie_fw;
288 
289 	if ((size & 15) || size > MBOX_LEN)
290 		return -EINVAL;
291 
292 	if (adap->flags & IS_VF) {
293 		if (is_t6(adap))
294 			data_reg = FW_T6VF_MBDATA_BASE_ADDR;
295 		else
296 			data_reg = FW_T4VF_MBDATA_BASE_ADDR;
297 		ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
298 	}
299 
300 	/*
301 	 * If we have a negative timeout, that implies that we can't sleep.
302 	 */
303 	if (timeout < 0) {
304 		sleep_ok = false;
305 		timeout = -timeout;
306 	}
307 
308 	/*
309 	 * Attempt to gain access to the mailbox.
310 	 */
311 	for (i = 0; i < 4; i++) {
312 		ctl = t4_read_reg(adap, ctl_reg);
313 		v = G_MBOWNER(ctl);
314 		if (v != X_MBOWNER_NONE)
315 			break;
316 	}
317 
318 	/*
319 	 * If we were unable to gain access, dequeue ourselves from the
320 	 * mailbox atomic access list and report the error to our caller.
321 	 */
322 	if (v != X_MBOWNER_PL) {
323 		t4_report_fw_error(adap);
324 		ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
325 		return ret;
326 	}
327 
328 	/*
329 	 * If we gain ownership of the mailbox and there's a "valid" message
330 	 * in it, this is likely an asynchronous error message from the
331 	 * firmware.  So we'll report that and then proceed on with attempting
332 	 * to issue our own command ... which may well fail if the error
333 	 * presaged the firmware crashing ...
334 	 */
335 	if (ctl & F_MBMSGVALID) {
336 		CH_ERR(adap, "found VALID command in mbox %u: "
337 		       "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
338 		       (unsigned long long)t4_read_reg64(adap, data_reg),
339 		       (unsigned long long)t4_read_reg64(adap, data_reg + 8),
340 		       (unsigned long long)t4_read_reg64(adap, data_reg + 16),
341 		       (unsigned long long)t4_read_reg64(adap, data_reg + 24),
342 		       (unsigned long long)t4_read_reg64(adap, data_reg + 32),
343 		       (unsigned long long)t4_read_reg64(adap, data_reg + 40),
344 		       (unsigned long long)t4_read_reg64(adap, data_reg + 48),
345 		       (unsigned long long)t4_read_reg64(adap, data_reg + 56));
346 	}
347 
348 	/*
349 	 * Copy in the new mailbox command and send it on its way ...
350 	 */
351 	for (i = 0; i < size; i += 8, p++)
352 		t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
353 
354 	if (adap->flags & IS_VF) {
355 		/*
356 		 * For the VFs, the Mailbox Data "registers" are
357 		 * actually backed by T4's "MA" interface rather than
358 		 * PL Registers (as is the case for the PFs).  Because
359 		 * these are in different coherency domains, the write
360 		 * to the VF's PL-register-backed Mailbox Control can
361 		 * race in front of the writes to the MA-backed VF
362 		 * Mailbox Data "registers".  So we need to do a
363 		 * read-back on at least one byte of the VF Mailbox
364 		 * Data registers before doing the write to the VF
365 		 * Mailbox Control register.
366 		 */
367 		t4_read_reg(adap, data_reg);
368 	}
369 
370 	CH_DUMP_MBOX(adap, mbox, data_reg);
371 
372 	t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
373 	t4_read_reg(adap, ctl_reg);	/* flush write */
374 
375 	delay_idx = 0;
376 	ms = delay[0];
377 
378 	/*
379 	 * Loop waiting for the reply; bail out if we time out or the firmware
380 	 * reports an error.
381 	 */
382 	pcie_fw = 0;
383 	for (i = 0; i < timeout; i += ms) {
384 		if (!(adap->flags & IS_VF)) {
385 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
386 			if (pcie_fw & F_PCIE_FW_ERR)
387 				break;
388 		}
389 		if (sleep_ok) {
390 			ms = delay[delay_idx];  /* last element may repeat */
391 			if (delay_idx < ARRAY_SIZE(delay) - 1)
392 				delay_idx++;
393 			msleep(ms);
394 		} else {
395 			mdelay(ms);
396 		}
397 
398 		v = t4_read_reg(adap, ctl_reg);
399 		if (v == X_CIM_PF_NOACCESS)
400 			continue;
401 		if (G_MBOWNER(v) == X_MBOWNER_PL) {
402 			if (!(v & F_MBMSGVALID)) {
403 				t4_write_reg(adap, ctl_reg,
404 					     V_MBOWNER(X_MBOWNER_NONE));
405 				continue;
406 			}
407 
408 			/*
409 			 * Retrieve the command reply and release the mailbox.
410 			 */
411 			get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
412 			t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
413 
414 			CH_DUMP_MBOX(adap, mbox, data_reg);
415 
416 			res = be64_to_cpu(cmd_rpl[0]);
417 			if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
418 				fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
419 				res = V_FW_CMD_RETVAL(EIO);
420 			} else if (rpl)
421 				memcpy(rpl, cmd_rpl, size);
422 			return -G_FW_CMD_RETVAL((int)res);
423 		}
424 	}
425 
426 	/*
427 	 * We timed out waiting for a reply to our mailbox command.  Report
428 	 * the error and also check to see if the firmware reported any
429 	 * errors ...
430 	 */
431 	ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
432 	CH_ERR(adap, "command %#x in mailbox %d timed out\n",
433 	       *(const u8 *)cmd, mbox);
434 
435 	/* If DUMP_MBOX is set the mbox has already been dumped */
436 	if ((adap->debug_flags & DF_DUMP_MBOX) == 0) {
437 		p = cmd;
438 		CH_ERR(adap, "mbox: %016llx %016llx %016llx %016llx "
439 		    "%016llx %016llx %016llx %016llx\n",
440 		    (unsigned long long)be64_to_cpu(p[0]),
441 		    (unsigned long long)be64_to_cpu(p[1]),
442 		    (unsigned long long)be64_to_cpu(p[2]),
443 		    (unsigned long long)be64_to_cpu(p[3]),
444 		    (unsigned long long)be64_to_cpu(p[4]),
445 		    (unsigned long long)be64_to_cpu(p[5]),
446 		    (unsigned long long)be64_to_cpu(p[6]),
447 		    (unsigned long long)be64_to_cpu(p[7]));
448 	}
449 
450 	t4_report_fw_error(adap);
451 	t4_fatal_err(adap);
452 	return ret;
453 }
454 
455 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
456 		    void *rpl, bool sleep_ok)
457 {
458 		return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
459 					       sleep_ok, FW_CMD_MAX_TIMEOUT);
460 
461 }
462 
463 static int t4_edc_err_read(struct adapter *adap, int idx)
464 {
465 	u32 edc_ecc_err_addr_reg;
466 	u32 edc_bist_status_rdata_reg;
467 
468 	if (is_t4(adap)) {
469 		CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
470 		return 0;
471 	}
472 	if (idx != MEM_EDC0 && idx != MEM_EDC1) {
473 		CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
474 		return 0;
475 	}
476 
477 	edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
478 	edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
479 
480 	CH_WARN(adap,
481 		"edc%d err addr 0x%x: 0x%x.\n",
482 		idx, edc_ecc_err_addr_reg,
483 		t4_read_reg(adap, edc_ecc_err_addr_reg));
484 	CH_WARN(adap,
485 	 	"bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
486 		edc_bist_status_rdata_reg,
487 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
488 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
489 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
490 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
491 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
492 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
493 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
494 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
495 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
496 
497 	return 0;
498 }
499 
500 /**
501  *	t4_mc_read - read from MC through backdoor accesses
502  *	@adap: the adapter
503  *	@idx: which MC to access
504  *	@addr: address of first byte requested
505  *	@data: 64 bytes of data containing the requested address
506  *	@ecc: where to store the corresponding 64-bit ECC word
507  *
508  *	Read 64 bytes of data from MC starting at a 64-byte-aligned address
509  *	that covers the requested address @addr.  If @parity is not %NULL it
510  *	is assigned the 64-bit ECC word for the read data.
511  */
512 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
513 {
514 	int i;
515 	u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
516 	u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
517 
518 	if (is_t4(adap)) {
519 		mc_bist_cmd_reg = A_MC_BIST_CMD;
520 		mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
521 		mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
522 		mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
523 		mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
524 	} else {
525 		mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
526 		mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
527 		mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
528 		mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
529 						  idx);
530 		mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
531 						  idx);
532 	}
533 
534 	if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
535 		return -EBUSY;
536 	t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
537 	t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
538 	t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
539 	t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
540 		     F_START_BIST | V_BIST_CMD_GAP(1));
541 	i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
542 	if (i)
543 		return i;
544 
545 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
546 
547 	for (i = 15; i >= 0; i--)
548 		*data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
549 	if (ecc)
550 		*ecc = t4_read_reg64(adap, MC_DATA(16));
551 #undef MC_DATA
552 	return 0;
553 }
554 
555 /**
556  *	t4_edc_read - read from EDC through backdoor accesses
557  *	@adap: the adapter
558  *	@idx: which EDC to access
559  *	@addr: address of first byte requested
560  *	@data: 64 bytes of data containing the requested address
561  *	@ecc: where to store the corresponding 64-bit ECC word
562  *
563  *	Read 64 bytes of data from EDC starting at a 64-byte-aligned address
564  *	that covers the requested address @addr.  If @parity is not %NULL it
565  *	is assigned the 64-bit ECC word for the read data.
566  */
567 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
568 {
569 	int i;
570 	u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
571 	u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
572 
573 	if (is_t4(adap)) {
574 		edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
575 		edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
576 		edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
577 		edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
578 						    idx);
579 		edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
580 						    idx);
581 	} else {
582 /*
583  * These macro are missing in t4_regs.h file.
584  * Added temporarily for testing.
585  */
586 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
587 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
588 		edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
589 		edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
590 		edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
591 		edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
592 						    idx);
593 		edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
594 						    idx);
595 #undef EDC_REG_T5
596 #undef EDC_STRIDE_T5
597 	}
598 
599 	if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
600 		return -EBUSY;
601 	t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
602 	t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
603 	t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
604 	t4_write_reg(adap, edc_bist_cmd_reg,
605 		     V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
606 	i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
607 	if (i)
608 		return i;
609 
610 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
611 
612 	for (i = 15; i >= 0; i--)
613 		*data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
614 	if (ecc)
615 		*ecc = t4_read_reg64(adap, EDC_DATA(16));
616 #undef EDC_DATA
617 	return 0;
618 }
619 
620 /**
621  *	t4_mem_read - read EDC 0, EDC 1 or MC into buffer
622  *	@adap: the adapter
623  *	@mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
624  *	@addr: address within indicated memory type
625  *	@len: amount of memory to read
626  *	@buf: host memory buffer
627  *
628  *	Reads an [almost] arbitrary memory region in the firmware: the
629  *	firmware memory address, length and host buffer must be aligned on
630  *	32-bit boudaries.  The memory is returned as a raw byte sequence from
631  *	the firmware's memory.  If this memory contains data structures which
632  *	contain multi-byte integers, it's the callers responsibility to
633  *	perform appropriate byte order conversions.
634  */
635 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
636 		__be32 *buf)
637 {
638 	u32 pos, start, end, offset;
639 	int ret;
640 
641 	/*
642 	 * Argument sanity checks ...
643 	 */
644 	if ((addr & 0x3) || (len & 0x3))
645 		return -EINVAL;
646 
647 	/*
648 	 * The underlaying EDC/MC read routines read 64 bytes at a time so we
649 	 * need to round down the start and round up the end.  We'll start
650 	 * copying out of the first line at (addr - start) a word at a time.
651 	 */
652 	start = rounddown2(addr, 64);
653 	end = roundup2(addr + len, 64);
654 	offset = (addr - start)/sizeof(__be32);
655 
656 	for (pos = start; pos < end; pos += 64, offset = 0) {
657 		__be32 data[16];
658 
659 		/*
660 		 * Read the chip's memory block and bail if there's an error.
661 		 */
662 		if ((mtype == MEM_MC) || (mtype == MEM_MC1))
663 			ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
664 		else
665 			ret = t4_edc_read(adap, mtype, pos, data, NULL);
666 		if (ret)
667 			return ret;
668 
669 		/*
670 		 * Copy the data into the caller's memory buffer.
671 		 */
672 		while (offset < 16 && len > 0) {
673 			*buf++ = data[offset++];
674 			len -= sizeof(__be32);
675 		}
676 	}
677 
678 	return 0;
679 }
680 
681 /*
682  * Return the specified PCI-E Configuration Space register from our Physical
683  * Function.  We try first via a Firmware LDST Command (if fw_attach != 0)
684  * since we prefer to let the firmware own all of these registers, but if that
685  * fails we go for it directly ourselves.
686  */
687 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
688 {
689 
690 	/*
691 	 * If fw_attach != 0, construct and send the Firmware LDST Command to
692 	 * retrieve the specified PCI-E Configuration Space register.
693 	 */
694 	if (drv_fw_attach != 0) {
695 		struct fw_ldst_cmd ldst_cmd;
696 		int ret;
697 
698 		memset(&ldst_cmd, 0, sizeof(ldst_cmd));
699 		ldst_cmd.op_to_addrspace =
700 			cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
701 				    F_FW_CMD_REQUEST |
702 				    F_FW_CMD_READ |
703 				    V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
704 		ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
705 		ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
706 		ldst_cmd.u.pcie.ctrl_to_fn =
707 			(F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
708 		ldst_cmd.u.pcie.r = reg;
709 
710 		/*
711 		 * If the LDST Command succeeds, return the result, otherwise
712 		 * fall through to reading it directly ourselves ...
713 		 */
714 		ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
715 				 &ldst_cmd);
716 		if (ret == 0)
717 			return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
718 
719 		CH_WARN(adap, "Firmware failed to return "
720 			"Configuration Space register %d, err = %d\n",
721 			reg, -ret);
722 	}
723 
724 	/*
725 	 * Read the desired Configuration Space register via the PCI-E
726 	 * Backdoor mechanism.
727 	 */
728 	return t4_hw_pci_read_cfg4(adap, reg);
729 }
730 
731 /**
732  *	t4_get_regs_len - return the size of the chips register set
733  *	@adapter: the adapter
734  *
735  *	Returns the size of the chip's BAR0 register space.
736  */
737 unsigned int t4_get_regs_len(struct adapter *adapter)
738 {
739 	unsigned int chip_version = chip_id(adapter);
740 
741 	switch (chip_version) {
742 	case CHELSIO_T4:
743 		if (adapter->flags & IS_VF)
744 			return FW_T4VF_REGMAP_SIZE;
745 		return T4_REGMAP_SIZE;
746 
747 	case CHELSIO_T5:
748 	case CHELSIO_T6:
749 		if (adapter->flags & IS_VF)
750 			return FW_T4VF_REGMAP_SIZE;
751 		return T5_REGMAP_SIZE;
752 	}
753 
754 	CH_ERR(adapter,
755 		"Unsupported chip version %d\n", chip_version);
756 	return 0;
757 }
758 
759 /**
760  *	t4_get_regs - read chip registers into provided buffer
761  *	@adap: the adapter
762  *	@buf: register buffer
763  *	@buf_size: size (in bytes) of register buffer
764  *
765  *	If the provided register buffer isn't large enough for the chip's
766  *	full register range, the register dump will be truncated to the
767  *	register buffer's size.
768  */
769 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
770 {
771 	static const unsigned int t4_reg_ranges[] = {
772 		0x1008, 0x1108,
773 		0x1180, 0x1184,
774 		0x1190, 0x1194,
775 		0x11a0, 0x11a4,
776 		0x11b0, 0x11b4,
777 		0x11fc, 0x123c,
778 		0x1300, 0x173c,
779 		0x1800, 0x18fc,
780 		0x3000, 0x30d8,
781 		0x30e0, 0x30e4,
782 		0x30ec, 0x5910,
783 		0x5920, 0x5924,
784 		0x5960, 0x5960,
785 		0x5968, 0x5968,
786 		0x5970, 0x5970,
787 		0x5978, 0x5978,
788 		0x5980, 0x5980,
789 		0x5988, 0x5988,
790 		0x5990, 0x5990,
791 		0x5998, 0x5998,
792 		0x59a0, 0x59d4,
793 		0x5a00, 0x5ae0,
794 		0x5ae8, 0x5ae8,
795 		0x5af0, 0x5af0,
796 		0x5af8, 0x5af8,
797 		0x6000, 0x6098,
798 		0x6100, 0x6150,
799 		0x6200, 0x6208,
800 		0x6240, 0x6248,
801 		0x6280, 0x62b0,
802 		0x62c0, 0x6338,
803 		0x6370, 0x638c,
804 		0x6400, 0x643c,
805 		0x6500, 0x6524,
806 		0x6a00, 0x6a04,
807 		0x6a14, 0x6a38,
808 		0x6a60, 0x6a70,
809 		0x6a78, 0x6a78,
810 		0x6b00, 0x6b0c,
811 		0x6b1c, 0x6b84,
812 		0x6bf0, 0x6bf8,
813 		0x6c00, 0x6c0c,
814 		0x6c1c, 0x6c84,
815 		0x6cf0, 0x6cf8,
816 		0x6d00, 0x6d0c,
817 		0x6d1c, 0x6d84,
818 		0x6df0, 0x6df8,
819 		0x6e00, 0x6e0c,
820 		0x6e1c, 0x6e84,
821 		0x6ef0, 0x6ef8,
822 		0x6f00, 0x6f0c,
823 		0x6f1c, 0x6f84,
824 		0x6ff0, 0x6ff8,
825 		0x7000, 0x700c,
826 		0x701c, 0x7084,
827 		0x70f0, 0x70f8,
828 		0x7100, 0x710c,
829 		0x711c, 0x7184,
830 		0x71f0, 0x71f8,
831 		0x7200, 0x720c,
832 		0x721c, 0x7284,
833 		0x72f0, 0x72f8,
834 		0x7300, 0x730c,
835 		0x731c, 0x7384,
836 		0x73f0, 0x73f8,
837 		0x7400, 0x7450,
838 		0x7500, 0x7530,
839 		0x7600, 0x760c,
840 		0x7614, 0x761c,
841 		0x7680, 0x76cc,
842 		0x7700, 0x7798,
843 		0x77c0, 0x77fc,
844 		0x7900, 0x79fc,
845 		0x7b00, 0x7b58,
846 		0x7b60, 0x7b84,
847 		0x7b8c, 0x7c38,
848 		0x7d00, 0x7d38,
849 		0x7d40, 0x7d80,
850 		0x7d8c, 0x7ddc,
851 		0x7de4, 0x7e04,
852 		0x7e10, 0x7e1c,
853 		0x7e24, 0x7e38,
854 		0x7e40, 0x7e44,
855 		0x7e4c, 0x7e78,
856 		0x7e80, 0x7ea4,
857 		0x7eac, 0x7edc,
858 		0x7ee8, 0x7efc,
859 		0x8dc0, 0x8e04,
860 		0x8e10, 0x8e1c,
861 		0x8e30, 0x8e78,
862 		0x8ea0, 0x8eb8,
863 		0x8ec0, 0x8f6c,
864 		0x8fc0, 0x9008,
865 		0x9010, 0x9058,
866 		0x9060, 0x9060,
867 		0x9068, 0x9074,
868 		0x90fc, 0x90fc,
869 		0x9400, 0x9408,
870 		0x9410, 0x9458,
871 		0x9600, 0x9600,
872 		0x9608, 0x9638,
873 		0x9640, 0x96bc,
874 		0x9800, 0x9808,
875 		0x9820, 0x983c,
876 		0x9850, 0x9864,
877 		0x9c00, 0x9c6c,
878 		0x9c80, 0x9cec,
879 		0x9d00, 0x9d6c,
880 		0x9d80, 0x9dec,
881 		0x9e00, 0x9e6c,
882 		0x9e80, 0x9eec,
883 		0x9f00, 0x9f6c,
884 		0x9f80, 0x9fec,
885 		0xd004, 0xd004,
886 		0xd010, 0xd03c,
887 		0xdfc0, 0xdfe0,
888 		0xe000, 0xea7c,
889 		0xf000, 0x11110,
890 		0x11118, 0x11190,
891 		0x19040, 0x1906c,
892 		0x19078, 0x19080,
893 		0x1908c, 0x190e4,
894 		0x190f0, 0x190f8,
895 		0x19100, 0x19110,
896 		0x19120, 0x19124,
897 		0x19150, 0x19194,
898 		0x1919c, 0x191b0,
899 		0x191d0, 0x191e8,
900 		0x19238, 0x1924c,
901 		0x193f8, 0x1943c,
902 		0x1944c, 0x19474,
903 		0x19490, 0x194e0,
904 		0x194f0, 0x194f8,
905 		0x19800, 0x19c08,
906 		0x19c10, 0x19c90,
907 		0x19ca0, 0x19ce4,
908 		0x19cf0, 0x19d40,
909 		0x19d50, 0x19d94,
910 		0x19da0, 0x19de8,
911 		0x19df0, 0x19e40,
912 		0x19e50, 0x19e90,
913 		0x19ea0, 0x19f4c,
914 		0x1a000, 0x1a004,
915 		0x1a010, 0x1a06c,
916 		0x1a0b0, 0x1a0e4,
917 		0x1a0ec, 0x1a0f4,
918 		0x1a100, 0x1a108,
919 		0x1a114, 0x1a120,
920 		0x1a128, 0x1a130,
921 		0x1a138, 0x1a138,
922 		0x1a190, 0x1a1c4,
923 		0x1a1fc, 0x1a1fc,
924 		0x1e040, 0x1e04c,
925 		0x1e284, 0x1e28c,
926 		0x1e2c0, 0x1e2c0,
927 		0x1e2e0, 0x1e2e0,
928 		0x1e300, 0x1e384,
929 		0x1e3c0, 0x1e3c8,
930 		0x1e440, 0x1e44c,
931 		0x1e684, 0x1e68c,
932 		0x1e6c0, 0x1e6c0,
933 		0x1e6e0, 0x1e6e0,
934 		0x1e700, 0x1e784,
935 		0x1e7c0, 0x1e7c8,
936 		0x1e840, 0x1e84c,
937 		0x1ea84, 0x1ea8c,
938 		0x1eac0, 0x1eac0,
939 		0x1eae0, 0x1eae0,
940 		0x1eb00, 0x1eb84,
941 		0x1ebc0, 0x1ebc8,
942 		0x1ec40, 0x1ec4c,
943 		0x1ee84, 0x1ee8c,
944 		0x1eec0, 0x1eec0,
945 		0x1eee0, 0x1eee0,
946 		0x1ef00, 0x1ef84,
947 		0x1efc0, 0x1efc8,
948 		0x1f040, 0x1f04c,
949 		0x1f284, 0x1f28c,
950 		0x1f2c0, 0x1f2c0,
951 		0x1f2e0, 0x1f2e0,
952 		0x1f300, 0x1f384,
953 		0x1f3c0, 0x1f3c8,
954 		0x1f440, 0x1f44c,
955 		0x1f684, 0x1f68c,
956 		0x1f6c0, 0x1f6c0,
957 		0x1f6e0, 0x1f6e0,
958 		0x1f700, 0x1f784,
959 		0x1f7c0, 0x1f7c8,
960 		0x1f840, 0x1f84c,
961 		0x1fa84, 0x1fa8c,
962 		0x1fac0, 0x1fac0,
963 		0x1fae0, 0x1fae0,
964 		0x1fb00, 0x1fb84,
965 		0x1fbc0, 0x1fbc8,
966 		0x1fc40, 0x1fc4c,
967 		0x1fe84, 0x1fe8c,
968 		0x1fec0, 0x1fec0,
969 		0x1fee0, 0x1fee0,
970 		0x1ff00, 0x1ff84,
971 		0x1ffc0, 0x1ffc8,
972 		0x20000, 0x2002c,
973 		0x20100, 0x2013c,
974 		0x20190, 0x201a0,
975 		0x201a8, 0x201b8,
976 		0x201c4, 0x201c8,
977 		0x20200, 0x20318,
978 		0x20400, 0x204b4,
979 		0x204c0, 0x20528,
980 		0x20540, 0x20614,
981 		0x21000, 0x21040,
982 		0x2104c, 0x21060,
983 		0x210c0, 0x210ec,
984 		0x21200, 0x21268,
985 		0x21270, 0x21284,
986 		0x212fc, 0x21388,
987 		0x21400, 0x21404,
988 		0x21500, 0x21500,
989 		0x21510, 0x21518,
990 		0x2152c, 0x21530,
991 		0x2153c, 0x2153c,
992 		0x21550, 0x21554,
993 		0x21600, 0x21600,
994 		0x21608, 0x2161c,
995 		0x21624, 0x21628,
996 		0x21630, 0x21634,
997 		0x2163c, 0x2163c,
998 		0x21700, 0x2171c,
999 		0x21780, 0x2178c,
1000 		0x21800, 0x21818,
1001 		0x21820, 0x21828,
1002 		0x21830, 0x21848,
1003 		0x21850, 0x21854,
1004 		0x21860, 0x21868,
1005 		0x21870, 0x21870,
1006 		0x21878, 0x21898,
1007 		0x218a0, 0x218a8,
1008 		0x218b0, 0x218c8,
1009 		0x218d0, 0x218d4,
1010 		0x218e0, 0x218e8,
1011 		0x218f0, 0x218f0,
1012 		0x218f8, 0x21a18,
1013 		0x21a20, 0x21a28,
1014 		0x21a30, 0x21a48,
1015 		0x21a50, 0x21a54,
1016 		0x21a60, 0x21a68,
1017 		0x21a70, 0x21a70,
1018 		0x21a78, 0x21a98,
1019 		0x21aa0, 0x21aa8,
1020 		0x21ab0, 0x21ac8,
1021 		0x21ad0, 0x21ad4,
1022 		0x21ae0, 0x21ae8,
1023 		0x21af0, 0x21af0,
1024 		0x21af8, 0x21c18,
1025 		0x21c20, 0x21c20,
1026 		0x21c28, 0x21c30,
1027 		0x21c38, 0x21c38,
1028 		0x21c80, 0x21c98,
1029 		0x21ca0, 0x21ca8,
1030 		0x21cb0, 0x21cc8,
1031 		0x21cd0, 0x21cd4,
1032 		0x21ce0, 0x21ce8,
1033 		0x21cf0, 0x21cf0,
1034 		0x21cf8, 0x21d7c,
1035 		0x21e00, 0x21e04,
1036 		0x22000, 0x2202c,
1037 		0x22100, 0x2213c,
1038 		0x22190, 0x221a0,
1039 		0x221a8, 0x221b8,
1040 		0x221c4, 0x221c8,
1041 		0x22200, 0x22318,
1042 		0x22400, 0x224b4,
1043 		0x224c0, 0x22528,
1044 		0x22540, 0x22614,
1045 		0x23000, 0x23040,
1046 		0x2304c, 0x23060,
1047 		0x230c0, 0x230ec,
1048 		0x23200, 0x23268,
1049 		0x23270, 0x23284,
1050 		0x232fc, 0x23388,
1051 		0x23400, 0x23404,
1052 		0x23500, 0x23500,
1053 		0x23510, 0x23518,
1054 		0x2352c, 0x23530,
1055 		0x2353c, 0x2353c,
1056 		0x23550, 0x23554,
1057 		0x23600, 0x23600,
1058 		0x23608, 0x2361c,
1059 		0x23624, 0x23628,
1060 		0x23630, 0x23634,
1061 		0x2363c, 0x2363c,
1062 		0x23700, 0x2371c,
1063 		0x23780, 0x2378c,
1064 		0x23800, 0x23818,
1065 		0x23820, 0x23828,
1066 		0x23830, 0x23848,
1067 		0x23850, 0x23854,
1068 		0x23860, 0x23868,
1069 		0x23870, 0x23870,
1070 		0x23878, 0x23898,
1071 		0x238a0, 0x238a8,
1072 		0x238b0, 0x238c8,
1073 		0x238d0, 0x238d4,
1074 		0x238e0, 0x238e8,
1075 		0x238f0, 0x238f0,
1076 		0x238f8, 0x23a18,
1077 		0x23a20, 0x23a28,
1078 		0x23a30, 0x23a48,
1079 		0x23a50, 0x23a54,
1080 		0x23a60, 0x23a68,
1081 		0x23a70, 0x23a70,
1082 		0x23a78, 0x23a98,
1083 		0x23aa0, 0x23aa8,
1084 		0x23ab0, 0x23ac8,
1085 		0x23ad0, 0x23ad4,
1086 		0x23ae0, 0x23ae8,
1087 		0x23af0, 0x23af0,
1088 		0x23af8, 0x23c18,
1089 		0x23c20, 0x23c20,
1090 		0x23c28, 0x23c30,
1091 		0x23c38, 0x23c38,
1092 		0x23c80, 0x23c98,
1093 		0x23ca0, 0x23ca8,
1094 		0x23cb0, 0x23cc8,
1095 		0x23cd0, 0x23cd4,
1096 		0x23ce0, 0x23ce8,
1097 		0x23cf0, 0x23cf0,
1098 		0x23cf8, 0x23d7c,
1099 		0x23e00, 0x23e04,
1100 		0x24000, 0x2402c,
1101 		0x24100, 0x2413c,
1102 		0x24190, 0x241a0,
1103 		0x241a8, 0x241b8,
1104 		0x241c4, 0x241c8,
1105 		0x24200, 0x24318,
1106 		0x24400, 0x244b4,
1107 		0x244c0, 0x24528,
1108 		0x24540, 0x24614,
1109 		0x25000, 0x25040,
1110 		0x2504c, 0x25060,
1111 		0x250c0, 0x250ec,
1112 		0x25200, 0x25268,
1113 		0x25270, 0x25284,
1114 		0x252fc, 0x25388,
1115 		0x25400, 0x25404,
1116 		0x25500, 0x25500,
1117 		0x25510, 0x25518,
1118 		0x2552c, 0x25530,
1119 		0x2553c, 0x2553c,
1120 		0x25550, 0x25554,
1121 		0x25600, 0x25600,
1122 		0x25608, 0x2561c,
1123 		0x25624, 0x25628,
1124 		0x25630, 0x25634,
1125 		0x2563c, 0x2563c,
1126 		0x25700, 0x2571c,
1127 		0x25780, 0x2578c,
1128 		0x25800, 0x25818,
1129 		0x25820, 0x25828,
1130 		0x25830, 0x25848,
1131 		0x25850, 0x25854,
1132 		0x25860, 0x25868,
1133 		0x25870, 0x25870,
1134 		0x25878, 0x25898,
1135 		0x258a0, 0x258a8,
1136 		0x258b0, 0x258c8,
1137 		0x258d0, 0x258d4,
1138 		0x258e0, 0x258e8,
1139 		0x258f0, 0x258f0,
1140 		0x258f8, 0x25a18,
1141 		0x25a20, 0x25a28,
1142 		0x25a30, 0x25a48,
1143 		0x25a50, 0x25a54,
1144 		0x25a60, 0x25a68,
1145 		0x25a70, 0x25a70,
1146 		0x25a78, 0x25a98,
1147 		0x25aa0, 0x25aa8,
1148 		0x25ab0, 0x25ac8,
1149 		0x25ad0, 0x25ad4,
1150 		0x25ae0, 0x25ae8,
1151 		0x25af0, 0x25af0,
1152 		0x25af8, 0x25c18,
1153 		0x25c20, 0x25c20,
1154 		0x25c28, 0x25c30,
1155 		0x25c38, 0x25c38,
1156 		0x25c80, 0x25c98,
1157 		0x25ca0, 0x25ca8,
1158 		0x25cb0, 0x25cc8,
1159 		0x25cd0, 0x25cd4,
1160 		0x25ce0, 0x25ce8,
1161 		0x25cf0, 0x25cf0,
1162 		0x25cf8, 0x25d7c,
1163 		0x25e00, 0x25e04,
1164 		0x26000, 0x2602c,
1165 		0x26100, 0x2613c,
1166 		0x26190, 0x261a0,
1167 		0x261a8, 0x261b8,
1168 		0x261c4, 0x261c8,
1169 		0x26200, 0x26318,
1170 		0x26400, 0x264b4,
1171 		0x264c0, 0x26528,
1172 		0x26540, 0x26614,
1173 		0x27000, 0x27040,
1174 		0x2704c, 0x27060,
1175 		0x270c0, 0x270ec,
1176 		0x27200, 0x27268,
1177 		0x27270, 0x27284,
1178 		0x272fc, 0x27388,
1179 		0x27400, 0x27404,
1180 		0x27500, 0x27500,
1181 		0x27510, 0x27518,
1182 		0x2752c, 0x27530,
1183 		0x2753c, 0x2753c,
1184 		0x27550, 0x27554,
1185 		0x27600, 0x27600,
1186 		0x27608, 0x2761c,
1187 		0x27624, 0x27628,
1188 		0x27630, 0x27634,
1189 		0x2763c, 0x2763c,
1190 		0x27700, 0x2771c,
1191 		0x27780, 0x2778c,
1192 		0x27800, 0x27818,
1193 		0x27820, 0x27828,
1194 		0x27830, 0x27848,
1195 		0x27850, 0x27854,
1196 		0x27860, 0x27868,
1197 		0x27870, 0x27870,
1198 		0x27878, 0x27898,
1199 		0x278a0, 0x278a8,
1200 		0x278b0, 0x278c8,
1201 		0x278d0, 0x278d4,
1202 		0x278e0, 0x278e8,
1203 		0x278f0, 0x278f0,
1204 		0x278f8, 0x27a18,
1205 		0x27a20, 0x27a28,
1206 		0x27a30, 0x27a48,
1207 		0x27a50, 0x27a54,
1208 		0x27a60, 0x27a68,
1209 		0x27a70, 0x27a70,
1210 		0x27a78, 0x27a98,
1211 		0x27aa0, 0x27aa8,
1212 		0x27ab0, 0x27ac8,
1213 		0x27ad0, 0x27ad4,
1214 		0x27ae0, 0x27ae8,
1215 		0x27af0, 0x27af0,
1216 		0x27af8, 0x27c18,
1217 		0x27c20, 0x27c20,
1218 		0x27c28, 0x27c30,
1219 		0x27c38, 0x27c38,
1220 		0x27c80, 0x27c98,
1221 		0x27ca0, 0x27ca8,
1222 		0x27cb0, 0x27cc8,
1223 		0x27cd0, 0x27cd4,
1224 		0x27ce0, 0x27ce8,
1225 		0x27cf0, 0x27cf0,
1226 		0x27cf8, 0x27d7c,
1227 		0x27e00, 0x27e04,
1228 	};
1229 
1230 	static const unsigned int t4vf_reg_ranges[] = {
1231 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1232 		VF_MPS_REG(A_MPS_VF_CTL),
1233 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1234 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1235 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1236 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1237 		FW_T4VF_MBDATA_BASE_ADDR,
1238 		FW_T4VF_MBDATA_BASE_ADDR +
1239 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1240 	};
1241 
1242 	static const unsigned int t5_reg_ranges[] = {
1243 		0x1008, 0x10c0,
1244 		0x10cc, 0x10f8,
1245 		0x1100, 0x1100,
1246 		0x110c, 0x1148,
1247 		0x1180, 0x1184,
1248 		0x1190, 0x1194,
1249 		0x11a0, 0x11a4,
1250 		0x11b0, 0x11b4,
1251 		0x11fc, 0x123c,
1252 		0x1280, 0x173c,
1253 		0x1800, 0x18fc,
1254 		0x3000, 0x3028,
1255 		0x3060, 0x30b0,
1256 		0x30b8, 0x30d8,
1257 		0x30e0, 0x30fc,
1258 		0x3140, 0x357c,
1259 		0x35a8, 0x35cc,
1260 		0x35ec, 0x35ec,
1261 		0x3600, 0x5624,
1262 		0x56cc, 0x56ec,
1263 		0x56f4, 0x5720,
1264 		0x5728, 0x575c,
1265 		0x580c, 0x5814,
1266 		0x5890, 0x589c,
1267 		0x58a4, 0x58ac,
1268 		0x58b8, 0x58bc,
1269 		0x5940, 0x59c8,
1270 		0x59d0, 0x59dc,
1271 		0x59fc, 0x5a18,
1272 		0x5a60, 0x5a70,
1273 		0x5a80, 0x5a9c,
1274 		0x5b94, 0x5bfc,
1275 		0x6000, 0x6020,
1276 		0x6028, 0x6040,
1277 		0x6058, 0x609c,
1278 		0x60a8, 0x614c,
1279 		0x7700, 0x7798,
1280 		0x77c0, 0x78fc,
1281 		0x7b00, 0x7b58,
1282 		0x7b60, 0x7b84,
1283 		0x7b8c, 0x7c54,
1284 		0x7d00, 0x7d38,
1285 		0x7d40, 0x7d80,
1286 		0x7d8c, 0x7ddc,
1287 		0x7de4, 0x7e04,
1288 		0x7e10, 0x7e1c,
1289 		0x7e24, 0x7e38,
1290 		0x7e40, 0x7e44,
1291 		0x7e4c, 0x7e78,
1292 		0x7e80, 0x7edc,
1293 		0x7ee8, 0x7efc,
1294 		0x8dc0, 0x8de0,
1295 		0x8df8, 0x8e04,
1296 		0x8e10, 0x8e84,
1297 		0x8ea0, 0x8f84,
1298 		0x8fc0, 0x9058,
1299 		0x9060, 0x9060,
1300 		0x9068, 0x90f8,
1301 		0x9400, 0x9408,
1302 		0x9410, 0x9470,
1303 		0x9600, 0x9600,
1304 		0x9608, 0x9638,
1305 		0x9640, 0x96f4,
1306 		0x9800, 0x9808,
1307 		0x9820, 0x983c,
1308 		0x9850, 0x9864,
1309 		0x9c00, 0x9c6c,
1310 		0x9c80, 0x9cec,
1311 		0x9d00, 0x9d6c,
1312 		0x9d80, 0x9dec,
1313 		0x9e00, 0x9e6c,
1314 		0x9e80, 0x9eec,
1315 		0x9f00, 0x9f6c,
1316 		0x9f80, 0xa020,
1317 		0xd004, 0xd004,
1318 		0xd010, 0xd03c,
1319 		0xdfc0, 0xdfe0,
1320 		0xe000, 0x1106c,
1321 		0x11074, 0x11088,
1322 		0x1109c, 0x1117c,
1323 		0x11190, 0x11204,
1324 		0x19040, 0x1906c,
1325 		0x19078, 0x19080,
1326 		0x1908c, 0x190e8,
1327 		0x190f0, 0x190f8,
1328 		0x19100, 0x19110,
1329 		0x19120, 0x19124,
1330 		0x19150, 0x19194,
1331 		0x1919c, 0x191b0,
1332 		0x191d0, 0x191e8,
1333 		0x19238, 0x19290,
1334 		0x193f8, 0x19428,
1335 		0x19430, 0x19444,
1336 		0x1944c, 0x1946c,
1337 		0x19474, 0x19474,
1338 		0x19490, 0x194cc,
1339 		0x194f0, 0x194f8,
1340 		0x19c00, 0x19c08,
1341 		0x19c10, 0x19c60,
1342 		0x19c94, 0x19ce4,
1343 		0x19cf0, 0x19d40,
1344 		0x19d50, 0x19d94,
1345 		0x19da0, 0x19de8,
1346 		0x19df0, 0x19e10,
1347 		0x19e50, 0x19e90,
1348 		0x19ea0, 0x19f24,
1349 		0x19f34, 0x19f34,
1350 		0x19f40, 0x19f50,
1351 		0x19f90, 0x19fb4,
1352 		0x19fc4, 0x19fe4,
1353 		0x1a000, 0x1a004,
1354 		0x1a010, 0x1a06c,
1355 		0x1a0b0, 0x1a0e4,
1356 		0x1a0ec, 0x1a0f8,
1357 		0x1a100, 0x1a108,
1358 		0x1a114, 0x1a120,
1359 		0x1a128, 0x1a130,
1360 		0x1a138, 0x1a138,
1361 		0x1a190, 0x1a1c4,
1362 		0x1a1fc, 0x1a1fc,
1363 		0x1e008, 0x1e00c,
1364 		0x1e040, 0x1e044,
1365 		0x1e04c, 0x1e04c,
1366 		0x1e284, 0x1e290,
1367 		0x1e2c0, 0x1e2c0,
1368 		0x1e2e0, 0x1e2e0,
1369 		0x1e300, 0x1e384,
1370 		0x1e3c0, 0x1e3c8,
1371 		0x1e408, 0x1e40c,
1372 		0x1e440, 0x1e444,
1373 		0x1e44c, 0x1e44c,
1374 		0x1e684, 0x1e690,
1375 		0x1e6c0, 0x1e6c0,
1376 		0x1e6e0, 0x1e6e0,
1377 		0x1e700, 0x1e784,
1378 		0x1e7c0, 0x1e7c8,
1379 		0x1e808, 0x1e80c,
1380 		0x1e840, 0x1e844,
1381 		0x1e84c, 0x1e84c,
1382 		0x1ea84, 0x1ea90,
1383 		0x1eac0, 0x1eac0,
1384 		0x1eae0, 0x1eae0,
1385 		0x1eb00, 0x1eb84,
1386 		0x1ebc0, 0x1ebc8,
1387 		0x1ec08, 0x1ec0c,
1388 		0x1ec40, 0x1ec44,
1389 		0x1ec4c, 0x1ec4c,
1390 		0x1ee84, 0x1ee90,
1391 		0x1eec0, 0x1eec0,
1392 		0x1eee0, 0x1eee0,
1393 		0x1ef00, 0x1ef84,
1394 		0x1efc0, 0x1efc8,
1395 		0x1f008, 0x1f00c,
1396 		0x1f040, 0x1f044,
1397 		0x1f04c, 0x1f04c,
1398 		0x1f284, 0x1f290,
1399 		0x1f2c0, 0x1f2c0,
1400 		0x1f2e0, 0x1f2e0,
1401 		0x1f300, 0x1f384,
1402 		0x1f3c0, 0x1f3c8,
1403 		0x1f408, 0x1f40c,
1404 		0x1f440, 0x1f444,
1405 		0x1f44c, 0x1f44c,
1406 		0x1f684, 0x1f690,
1407 		0x1f6c0, 0x1f6c0,
1408 		0x1f6e0, 0x1f6e0,
1409 		0x1f700, 0x1f784,
1410 		0x1f7c0, 0x1f7c8,
1411 		0x1f808, 0x1f80c,
1412 		0x1f840, 0x1f844,
1413 		0x1f84c, 0x1f84c,
1414 		0x1fa84, 0x1fa90,
1415 		0x1fac0, 0x1fac0,
1416 		0x1fae0, 0x1fae0,
1417 		0x1fb00, 0x1fb84,
1418 		0x1fbc0, 0x1fbc8,
1419 		0x1fc08, 0x1fc0c,
1420 		0x1fc40, 0x1fc44,
1421 		0x1fc4c, 0x1fc4c,
1422 		0x1fe84, 0x1fe90,
1423 		0x1fec0, 0x1fec0,
1424 		0x1fee0, 0x1fee0,
1425 		0x1ff00, 0x1ff84,
1426 		0x1ffc0, 0x1ffc8,
1427 		0x30000, 0x30030,
1428 		0x30100, 0x30144,
1429 		0x30190, 0x301a0,
1430 		0x301a8, 0x301b8,
1431 		0x301c4, 0x301c8,
1432 		0x301d0, 0x301d0,
1433 		0x30200, 0x30318,
1434 		0x30400, 0x304b4,
1435 		0x304c0, 0x3052c,
1436 		0x30540, 0x3061c,
1437 		0x30800, 0x30828,
1438 		0x30834, 0x30834,
1439 		0x308c0, 0x30908,
1440 		0x30910, 0x309ac,
1441 		0x30a00, 0x30a14,
1442 		0x30a1c, 0x30a2c,
1443 		0x30a44, 0x30a50,
1444 		0x30a74, 0x30a74,
1445 		0x30a7c, 0x30afc,
1446 		0x30b08, 0x30c24,
1447 		0x30d00, 0x30d00,
1448 		0x30d08, 0x30d14,
1449 		0x30d1c, 0x30d20,
1450 		0x30d3c, 0x30d3c,
1451 		0x30d48, 0x30d50,
1452 		0x31200, 0x3120c,
1453 		0x31220, 0x31220,
1454 		0x31240, 0x31240,
1455 		0x31600, 0x3160c,
1456 		0x31a00, 0x31a1c,
1457 		0x31e00, 0x31e20,
1458 		0x31e38, 0x31e3c,
1459 		0x31e80, 0x31e80,
1460 		0x31e88, 0x31ea8,
1461 		0x31eb0, 0x31eb4,
1462 		0x31ec8, 0x31ed4,
1463 		0x31fb8, 0x32004,
1464 		0x32200, 0x32200,
1465 		0x32208, 0x32240,
1466 		0x32248, 0x32280,
1467 		0x32288, 0x322c0,
1468 		0x322c8, 0x322fc,
1469 		0x32600, 0x32630,
1470 		0x32a00, 0x32abc,
1471 		0x32b00, 0x32b10,
1472 		0x32b20, 0x32b30,
1473 		0x32b40, 0x32b50,
1474 		0x32b60, 0x32b70,
1475 		0x33000, 0x33028,
1476 		0x33030, 0x33048,
1477 		0x33060, 0x33068,
1478 		0x33070, 0x3309c,
1479 		0x330f0, 0x33128,
1480 		0x33130, 0x33148,
1481 		0x33160, 0x33168,
1482 		0x33170, 0x3319c,
1483 		0x331f0, 0x33238,
1484 		0x33240, 0x33240,
1485 		0x33248, 0x33250,
1486 		0x3325c, 0x33264,
1487 		0x33270, 0x332b8,
1488 		0x332c0, 0x332e4,
1489 		0x332f8, 0x33338,
1490 		0x33340, 0x33340,
1491 		0x33348, 0x33350,
1492 		0x3335c, 0x33364,
1493 		0x33370, 0x333b8,
1494 		0x333c0, 0x333e4,
1495 		0x333f8, 0x33428,
1496 		0x33430, 0x33448,
1497 		0x33460, 0x33468,
1498 		0x33470, 0x3349c,
1499 		0x334f0, 0x33528,
1500 		0x33530, 0x33548,
1501 		0x33560, 0x33568,
1502 		0x33570, 0x3359c,
1503 		0x335f0, 0x33638,
1504 		0x33640, 0x33640,
1505 		0x33648, 0x33650,
1506 		0x3365c, 0x33664,
1507 		0x33670, 0x336b8,
1508 		0x336c0, 0x336e4,
1509 		0x336f8, 0x33738,
1510 		0x33740, 0x33740,
1511 		0x33748, 0x33750,
1512 		0x3375c, 0x33764,
1513 		0x33770, 0x337b8,
1514 		0x337c0, 0x337e4,
1515 		0x337f8, 0x337fc,
1516 		0x33814, 0x33814,
1517 		0x3382c, 0x3382c,
1518 		0x33880, 0x3388c,
1519 		0x338e8, 0x338ec,
1520 		0x33900, 0x33928,
1521 		0x33930, 0x33948,
1522 		0x33960, 0x33968,
1523 		0x33970, 0x3399c,
1524 		0x339f0, 0x33a38,
1525 		0x33a40, 0x33a40,
1526 		0x33a48, 0x33a50,
1527 		0x33a5c, 0x33a64,
1528 		0x33a70, 0x33ab8,
1529 		0x33ac0, 0x33ae4,
1530 		0x33af8, 0x33b10,
1531 		0x33b28, 0x33b28,
1532 		0x33b3c, 0x33b50,
1533 		0x33bf0, 0x33c10,
1534 		0x33c28, 0x33c28,
1535 		0x33c3c, 0x33c50,
1536 		0x33cf0, 0x33cfc,
1537 		0x34000, 0x34030,
1538 		0x34100, 0x34144,
1539 		0x34190, 0x341a0,
1540 		0x341a8, 0x341b8,
1541 		0x341c4, 0x341c8,
1542 		0x341d0, 0x341d0,
1543 		0x34200, 0x34318,
1544 		0x34400, 0x344b4,
1545 		0x344c0, 0x3452c,
1546 		0x34540, 0x3461c,
1547 		0x34800, 0x34828,
1548 		0x34834, 0x34834,
1549 		0x348c0, 0x34908,
1550 		0x34910, 0x349ac,
1551 		0x34a00, 0x34a14,
1552 		0x34a1c, 0x34a2c,
1553 		0x34a44, 0x34a50,
1554 		0x34a74, 0x34a74,
1555 		0x34a7c, 0x34afc,
1556 		0x34b08, 0x34c24,
1557 		0x34d00, 0x34d00,
1558 		0x34d08, 0x34d14,
1559 		0x34d1c, 0x34d20,
1560 		0x34d3c, 0x34d3c,
1561 		0x34d48, 0x34d50,
1562 		0x35200, 0x3520c,
1563 		0x35220, 0x35220,
1564 		0x35240, 0x35240,
1565 		0x35600, 0x3560c,
1566 		0x35a00, 0x35a1c,
1567 		0x35e00, 0x35e20,
1568 		0x35e38, 0x35e3c,
1569 		0x35e80, 0x35e80,
1570 		0x35e88, 0x35ea8,
1571 		0x35eb0, 0x35eb4,
1572 		0x35ec8, 0x35ed4,
1573 		0x35fb8, 0x36004,
1574 		0x36200, 0x36200,
1575 		0x36208, 0x36240,
1576 		0x36248, 0x36280,
1577 		0x36288, 0x362c0,
1578 		0x362c8, 0x362fc,
1579 		0x36600, 0x36630,
1580 		0x36a00, 0x36abc,
1581 		0x36b00, 0x36b10,
1582 		0x36b20, 0x36b30,
1583 		0x36b40, 0x36b50,
1584 		0x36b60, 0x36b70,
1585 		0x37000, 0x37028,
1586 		0x37030, 0x37048,
1587 		0x37060, 0x37068,
1588 		0x37070, 0x3709c,
1589 		0x370f0, 0x37128,
1590 		0x37130, 0x37148,
1591 		0x37160, 0x37168,
1592 		0x37170, 0x3719c,
1593 		0x371f0, 0x37238,
1594 		0x37240, 0x37240,
1595 		0x37248, 0x37250,
1596 		0x3725c, 0x37264,
1597 		0x37270, 0x372b8,
1598 		0x372c0, 0x372e4,
1599 		0x372f8, 0x37338,
1600 		0x37340, 0x37340,
1601 		0x37348, 0x37350,
1602 		0x3735c, 0x37364,
1603 		0x37370, 0x373b8,
1604 		0x373c0, 0x373e4,
1605 		0x373f8, 0x37428,
1606 		0x37430, 0x37448,
1607 		0x37460, 0x37468,
1608 		0x37470, 0x3749c,
1609 		0x374f0, 0x37528,
1610 		0x37530, 0x37548,
1611 		0x37560, 0x37568,
1612 		0x37570, 0x3759c,
1613 		0x375f0, 0x37638,
1614 		0x37640, 0x37640,
1615 		0x37648, 0x37650,
1616 		0x3765c, 0x37664,
1617 		0x37670, 0x376b8,
1618 		0x376c0, 0x376e4,
1619 		0x376f8, 0x37738,
1620 		0x37740, 0x37740,
1621 		0x37748, 0x37750,
1622 		0x3775c, 0x37764,
1623 		0x37770, 0x377b8,
1624 		0x377c0, 0x377e4,
1625 		0x377f8, 0x377fc,
1626 		0x37814, 0x37814,
1627 		0x3782c, 0x3782c,
1628 		0x37880, 0x3788c,
1629 		0x378e8, 0x378ec,
1630 		0x37900, 0x37928,
1631 		0x37930, 0x37948,
1632 		0x37960, 0x37968,
1633 		0x37970, 0x3799c,
1634 		0x379f0, 0x37a38,
1635 		0x37a40, 0x37a40,
1636 		0x37a48, 0x37a50,
1637 		0x37a5c, 0x37a64,
1638 		0x37a70, 0x37ab8,
1639 		0x37ac0, 0x37ae4,
1640 		0x37af8, 0x37b10,
1641 		0x37b28, 0x37b28,
1642 		0x37b3c, 0x37b50,
1643 		0x37bf0, 0x37c10,
1644 		0x37c28, 0x37c28,
1645 		0x37c3c, 0x37c50,
1646 		0x37cf0, 0x37cfc,
1647 		0x38000, 0x38030,
1648 		0x38100, 0x38144,
1649 		0x38190, 0x381a0,
1650 		0x381a8, 0x381b8,
1651 		0x381c4, 0x381c8,
1652 		0x381d0, 0x381d0,
1653 		0x38200, 0x38318,
1654 		0x38400, 0x384b4,
1655 		0x384c0, 0x3852c,
1656 		0x38540, 0x3861c,
1657 		0x38800, 0x38828,
1658 		0x38834, 0x38834,
1659 		0x388c0, 0x38908,
1660 		0x38910, 0x389ac,
1661 		0x38a00, 0x38a14,
1662 		0x38a1c, 0x38a2c,
1663 		0x38a44, 0x38a50,
1664 		0x38a74, 0x38a74,
1665 		0x38a7c, 0x38afc,
1666 		0x38b08, 0x38c24,
1667 		0x38d00, 0x38d00,
1668 		0x38d08, 0x38d14,
1669 		0x38d1c, 0x38d20,
1670 		0x38d3c, 0x38d3c,
1671 		0x38d48, 0x38d50,
1672 		0x39200, 0x3920c,
1673 		0x39220, 0x39220,
1674 		0x39240, 0x39240,
1675 		0x39600, 0x3960c,
1676 		0x39a00, 0x39a1c,
1677 		0x39e00, 0x39e20,
1678 		0x39e38, 0x39e3c,
1679 		0x39e80, 0x39e80,
1680 		0x39e88, 0x39ea8,
1681 		0x39eb0, 0x39eb4,
1682 		0x39ec8, 0x39ed4,
1683 		0x39fb8, 0x3a004,
1684 		0x3a200, 0x3a200,
1685 		0x3a208, 0x3a240,
1686 		0x3a248, 0x3a280,
1687 		0x3a288, 0x3a2c0,
1688 		0x3a2c8, 0x3a2fc,
1689 		0x3a600, 0x3a630,
1690 		0x3aa00, 0x3aabc,
1691 		0x3ab00, 0x3ab10,
1692 		0x3ab20, 0x3ab30,
1693 		0x3ab40, 0x3ab50,
1694 		0x3ab60, 0x3ab70,
1695 		0x3b000, 0x3b028,
1696 		0x3b030, 0x3b048,
1697 		0x3b060, 0x3b068,
1698 		0x3b070, 0x3b09c,
1699 		0x3b0f0, 0x3b128,
1700 		0x3b130, 0x3b148,
1701 		0x3b160, 0x3b168,
1702 		0x3b170, 0x3b19c,
1703 		0x3b1f0, 0x3b238,
1704 		0x3b240, 0x3b240,
1705 		0x3b248, 0x3b250,
1706 		0x3b25c, 0x3b264,
1707 		0x3b270, 0x3b2b8,
1708 		0x3b2c0, 0x3b2e4,
1709 		0x3b2f8, 0x3b338,
1710 		0x3b340, 0x3b340,
1711 		0x3b348, 0x3b350,
1712 		0x3b35c, 0x3b364,
1713 		0x3b370, 0x3b3b8,
1714 		0x3b3c0, 0x3b3e4,
1715 		0x3b3f8, 0x3b428,
1716 		0x3b430, 0x3b448,
1717 		0x3b460, 0x3b468,
1718 		0x3b470, 0x3b49c,
1719 		0x3b4f0, 0x3b528,
1720 		0x3b530, 0x3b548,
1721 		0x3b560, 0x3b568,
1722 		0x3b570, 0x3b59c,
1723 		0x3b5f0, 0x3b638,
1724 		0x3b640, 0x3b640,
1725 		0x3b648, 0x3b650,
1726 		0x3b65c, 0x3b664,
1727 		0x3b670, 0x3b6b8,
1728 		0x3b6c0, 0x3b6e4,
1729 		0x3b6f8, 0x3b738,
1730 		0x3b740, 0x3b740,
1731 		0x3b748, 0x3b750,
1732 		0x3b75c, 0x3b764,
1733 		0x3b770, 0x3b7b8,
1734 		0x3b7c0, 0x3b7e4,
1735 		0x3b7f8, 0x3b7fc,
1736 		0x3b814, 0x3b814,
1737 		0x3b82c, 0x3b82c,
1738 		0x3b880, 0x3b88c,
1739 		0x3b8e8, 0x3b8ec,
1740 		0x3b900, 0x3b928,
1741 		0x3b930, 0x3b948,
1742 		0x3b960, 0x3b968,
1743 		0x3b970, 0x3b99c,
1744 		0x3b9f0, 0x3ba38,
1745 		0x3ba40, 0x3ba40,
1746 		0x3ba48, 0x3ba50,
1747 		0x3ba5c, 0x3ba64,
1748 		0x3ba70, 0x3bab8,
1749 		0x3bac0, 0x3bae4,
1750 		0x3baf8, 0x3bb10,
1751 		0x3bb28, 0x3bb28,
1752 		0x3bb3c, 0x3bb50,
1753 		0x3bbf0, 0x3bc10,
1754 		0x3bc28, 0x3bc28,
1755 		0x3bc3c, 0x3bc50,
1756 		0x3bcf0, 0x3bcfc,
1757 		0x3c000, 0x3c030,
1758 		0x3c100, 0x3c144,
1759 		0x3c190, 0x3c1a0,
1760 		0x3c1a8, 0x3c1b8,
1761 		0x3c1c4, 0x3c1c8,
1762 		0x3c1d0, 0x3c1d0,
1763 		0x3c200, 0x3c318,
1764 		0x3c400, 0x3c4b4,
1765 		0x3c4c0, 0x3c52c,
1766 		0x3c540, 0x3c61c,
1767 		0x3c800, 0x3c828,
1768 		0x3c834, 0x3c834,
1769 		0x3c8c0, 0x3c908,
1770 		0x3c910, 0x3c9ac,
1771 		0x3ca00, 0x3ca14,
1772 		0x3ca1c, 0x3ca2c,
1773 		0x3ca44, 0x3ca50,
1774 		0x3ca74, 0x3ca74,
1775 		0x3ca7c, 0x3cafc,
1776 		0x3cb08, 0x3cc24,
1777 		0x3cd00, 0x3cd00,
1778 		0x3cd08, 0x3cd14,
1779 		0x3cd1c, 0x3cd20,
1780 		0x3cd3c, 0x3cd3c,
1781 		0x3cd48, 0x3cd50,
1782 		0x3d200, 0x3d20c,
1783 		0x3d220, 0x3d220,
1784 		0x3d240, 0x3d240,
1785 		0x3d600, 0x3d60c,
1786 		0x3da00, 0x3da1c,
1787 		0x3de00, 0x3de20,
1788 		0x3de38, 0x3de3c,
1789 		0x3de80, 0x3de80,
1790 		0x3de88, 0x3dea8,
1791 		0x3deb0, 0x3deb4,
1792 		0x3dec8, 0x3ded4,
1793 		0x3dfb8, 0x3e004,
1794 		0x3e200, 0x3e200,
1795 		0x3e208, 0x3e240,
1796 		0x3e248, 0x3e280,
1797 		0x3e288, 0x3e2c0,
1798 		0x3e2c8, 0x3e2fc,
1799 		0x3e600, 0x3e630,
1800 		0x3ea00, 0x3eabc,
1801 		0x3eb00, 0x3eb10,
1802 		0x3eb20, 0x3eb30,
1803 		0x3eb40, 0x3eb50,
1804 		0x3eb60, 0x3eb70,
1805 		0x3f000, 0x3f028,
1806 		0x3f030, 0x3f048,
1807 		0x3f060, 0x3f068,
1808 		0x3f070, 0x3f09c,
1809 		0x3f0f0, 0x3f128,
1810 		0x3f130, 0x3f148,
1811 		0x3f160, 0x3f168,
1812 		0x3f170, 0x3f19c,
1813 		0x3f1f0, 0x3f238,
1814 		0x3f240, 0x3f240,
1815 		0x3f248, 0x3f250,
1816 		0x3f25c, 0x3f264,
1817 		0x3f270, 0x3f2b8,
1818 		0x3f2c0, 0x3f2e4,
1819 		0x3f2f8, 0x3f338,
1820 		0x3f340, 0x3f340,
1821 		0x3f348, 0x3f350,
1822 		0x3f35c, 0x3f364,
1823 		0x3f370, 0x3f3b8,
1824 		0x3f3c0, 0x3f3e4,
1825 		0x3f3f8, 0x3f428,
1826 		0x3f430, 0x3f448,
1827 		0x3f460, 0x3f468,
1828 		0x3f470, 0x3f49c,
1829 		0x3f4f0, 0x3f528,
1830 		0x3f530, 0x3f548,
1831 		0x3f560, 0x3f568,
1832 		0x3f570, 0x3f59c,
1833 		0x3f5f0, 0x3f638,
1834 		0x3f640, 0x3f640,
1835 		0x3f648, 0x3f650,
1836 		0x3f65c, 0x3f664,
1837 		0x3f670, 0x3f6b8,
1838 		0x3f6c0, 0x3f6e4,
1839 		0x3f6f8, 0x3f738,
1840 		0x3f740, 0x3f740,
1841 		0x3f748, 0x3f750,
1842 		0x3f75c, 0x3f764,
1843 		0x3f770, 0x3f7b8,
1844 		0x3f7c0, 0x3f7e4,
1845 		0x3f7f8, 0x3f7fc,
1846 		0x3f814, 0x3f814,
1847 		0x3f82c, 0x3f82c,
1848 		0x3f880, 0x3f88c,
1849 		0x3f8e8, 0x3f8ec,
1850 		0x3f900, 0x3f928,
1851 		0x3f930, 0x3f948,
1852 		0x3f960, 0x3f968,
1853 		0x3f970, 0x3f99c,
1854 		0x3f9f0, 0x3fa38,
1855 		0x3fa40, 0x3fa40,
1856 		0x3fa48, 0x3fa50,
1857 		0x3fa5c, 0x3fa64,
1858 		0x3fa70, 0x3fab8,
1859 		0x3fac0, 0x3fae4,
1860 		0x3faf8, 0x3fb10,
1861 		0x3fb28, 0x3fb28,
1862 		0x3fb3c, 0x3fb50,
1863 		0x3fbf0, 0x3fc10,
1864 		0x3fc28, 0x3fc28,
1865 		0x3fc3c, 0x3fc50,
1866 		0x3fcf0, 0x3fcfc,
1867 		0x40000, 0x4000c,
1868 		0x40040, 0x40050,
1869 		0x40060, 0x40068,
1870 		0x4007c, 0x4008c,
1871 		0x40094, 0x400b0,
1872 		0x400c0, 0x40144,
1873 		0x40180, 0x4018c,
1874 		0x40200, 0x40254,
1875 		0x40260, 0x40264,
1876 		0x40270, 0x40288,
1877 		0x40290, 0x40298,
1878 		0x402ac, 0x402c8,
1879 		0x402d0, 0x402e0,
1880 		0x402f0, 0x402f0,
1881 		0x40300, 0x4033c,
1882 		0x403f8, 0x403fc,
1883 		0x41304, 0x413c4,
1884 		0x41400, 0x4140c,
1885 		0x41414, 0x4141c,
1886 		0x41480, 0x414d0,
1887 		0x44000, 0x44054,
1888 		0x4405c, 0x44078,
1889 		0x440c0, 0x44174,
1890 		0x44180, 0x441ac,
1891 		0x441b4, 0x441b8,
1892 		0x441c0, 0x44254,
1893 		0x4425c, 0x44278,
1894 		0x442c0, 0x44374,
1895 		0x44380, 0x443ac,
1896 		0x443b4, 0x443b8,
1897 		0x443c0, 0x44454,
1898 		0x4445c, 0x44478,
1899 		0x444c0, 0x44574,
1900 		0x44580, 0x445ac,
1901 		0x445b4, 0x445b8,
1902 		0x445c0, 0x44654,
1903 		0x4465c, 0x44678,
1904 		0x446c0, 0x44774,
1905 		0x44780, 0x447ac,
1906 		0x447b4, 0x447b8,
1907 		0x447c0, 0x44854,
1908 		0x4485c, 0x44878,
1909 		0x448c0, 0x44974,
1910 		0x44980, 0x449ac,
1911 		0x449b4, 0x449b8,
1912 		0x449c0, 0x449fc,
1913 		0x45000, 0x45004,
1914 		0x45010, 0x45030,
1915 		0x45040, 0x45060,
1916 		0x45068, 0x45068,
1917 		0x45080, 0x45084,
1918 		0x450a0, 0x450b0,
1919 		0x45200, 0x45204,
1920 		0x45210, 0x45230,
1921 		0x45240, 0x45260,
1922 		0x45268, 0x45268,
1923 		0x45280, 0x45284,
1924 		0x452a0, 0x452b0,
1925 		0x460c0, 0x460e4,
1926 		0x47000, 0x4703c,
1927 		0x47044, 0x4708c,
1928 		0x47200, 0x47250,
1929 		0x47400, 0x47408,
1930 		0x47414, 0x47420,
1931 		0x47600, 0x47618,
1932 		0x47800, 0x47814,
1933 		0x48000, 0x4800c,
1934 		0x48040, 0x48050,
1935 		0x48060, 0x48068,
1936 		0x4807c, 0x4808c,
1937 		0x48094, 0x480b0,
1938 		0x480c0, 0x48144,
1939 		0x48180, 0x4818c,
1940 		0x48200, 0x48254,
1941 		0x48260, 0x48264,
1942 		0x48270, 0x48288,
1943 		0x48290, 0x48298,
1944 		0x482ac, 0x482c8,
1945 		0x482d0, 0x482e0,
1946 		0x482f0, 0x482f0,
1947 		0x48300, 0x4833c,
1948 		0x483f8, 0x483fc,
1949 		0x49304, 0x493c4,
1950 		0x49400, 0x4940c,
1951 		0x49414, 0x4941c,
1952 		0x49480, 0x494d0,
1953 		0x4c000, 0x4c054,
1954 		0x4c05c, 0x4c078,
1955 		0x4c0c0, 0x4c174,
1956 		0x4c180, 0x4c1ac,
1957 		0x4c1b4, 0x4c1b8,
1958 		0x4c1c0, 0x4c254,
1959 		0x4c25c, 0x4c278,
1960 		0x4c2c0, 0x4c374,
1961 		0x4c380, 0x4c3ac,
1962 		0x4c3b4, 0x4c3b8,
1963 		0x4c3c0, 0x4c454,
1964 		0x4c45c, 0x4c478,
1965 		0x4c4c0, 0x4c574,
1966 		0x4c580, 0x4c5ac,
1967 		0x4c5b4, 0x4c5b8,
1968 		0x4c5c0, 0x4c654,
1969 		0x4c65c, 0x4c678,
1970 		0x4c6c0, 0x4c774,
1971 		0x4c780, 0x4c7ac,
1972 		0x4c7b4, 0x4c7b8,
1973 		0x4c7c0, 0x4c854,
1974 		0x4c85c, 0x4c878,
1975 		0x4c8c0, 0x4c974,
1976 		0x4c980, 0x4c9ac,
1977 		0x4c9b4, 0x4c9b8,
1978 		0x4c9c0, 0x4c9fc,
1979 		0x4d000, 0x4d004,
1980 		0x4d010, 0x4d030,
1981 		0x4d040, 0x4d060,
1982 		0x4d068, 0x4d068,
1983 		0x4d080, 0x4d084,
1984 		0x4d0a0, 0x4d0b0,
1985 		0x4d200, 0x4d204,
1986 		0x4d210, 0x4d230,
1987 		0x4d240, 0x4d260,
1988 		0x4d268, 0x4d268,
1989 		0x4d280, 0x4d284,
1990 		0x4d2a0, 0x4d2b0,
1991 		0x4e0c0, 0x4e0e4,
1992 		0x4f000, 0x4f03c,
1993 		0x4f044, 0x4f08c,
1994 		0x4f200, 0x4f250,
1995 		0x4f400, 0x4f408,
1996 		0x4f414, 0x4f420,
1997 		0x4f600, 0x4f618,
1998 		0x4f800, 0x4f814,
1999 		0x50000, 0x50084,
2000 		0x50090, 0x500cc,
2001 		0x50400, 0x50400,
2002 		0x50800, 0x50884,
2003 		0x50890, 0x508cc,
2004 		0x50c00, 0x50c00,
2005 		0x51000, 0x5101c,
2006 		0x51300, 0x51308,
2007 	};
2008 
2009 	static const unsigned int t5vf_reg_ranges[] = {
2010 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2011 		VF_MPS_REG(A_MPS_VF_CTL),
2012 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2013 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2014 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2015 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2016 		FW_T4VF_MBDATA_BASE_ADDR,
2017 		FW_T4VF_MBDATA_BASE_ADDR +
2018 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2019 	};
2020 
2021 	static const unsigned int t6_reg_ranges[] = {
2022 		0x1008, 0x101c,
2023 		0x1024, 0x10a8,
2024 		0x10b4, 0x10f8,
2025 		0x1100, 0x1114,
2026 		0x111c, 0x112c,
2027 		0x1138, 0x113c,
2028 		0x1144, 0x114c,
2029 		0x1180, 0x1184,
2030 		0x1190, 0x1194,
2031 		0x11a0, 0x11a4,
2032 		0x11b0, 0x11b4,
2033 		0x11fc, 0x1274,
2034 		0x1280, 0x133c,
2035 		0x1800, 0x18fc,
2036 		0x3000, 0x302c,
2037 		0x3060, 0x30b0,
2038 		0x30b8, 0x30d8,
2039 		0x30e0, 0x30fc,
2040 		0x3140, 0x357c,
2041 		0x35a8, 0x35cc,
2042 		0x35ec, 0x35ec,
2043 		0x3600, 0x5624,
2044 		0x56cc, 0x56ec,
2045 		0x56f4, 0x5720,
2046 		0x5728, 0x575c,
2047 		0x580c, 0x5814,
2048 		0x5890, 0x589c,
2049 		0x58a4, 0x58ac,
2050 		0x58b8, 0x58bc,
2051 		0x5940, 0x595c,
2052 		0x5980, 0x598c,
2053 		0x59b0, 0x59c8,
2054 		0x59d0, 0x59dc,
2055 		0x59fc, 0x5a18,
2056 		0x5a60, 0x5a6c,
2057 		0x5a80, 0x5a8c,
2058 		0x5a94, 0x5a9c,
2059 		0x5b94, 0x5bfc,
2060 		0x5c10, 0x5e48,
2061 		0x5e50, 0x5e94,
2062 		0x5ea0, 0x5eb0,
2063 		0x5ec0, 0x5ec0,
2064 		0x5ec8, 0x5ed0,
2065 		0x5ee0, 0x5ee0,
2066 		0x5ef0, 0x5ef0,
2067 		0x5f00, 0x5f00,
2068 		0x6000, 0x6020,
2069 		0x6028, 0x6040,
2070 		0x6058, 0x609c,
2071 		0x60a8, 0x619c,
2072 		0x7700, 0x7798,
2073 		0x77c0, 0x7880,
2074 		0x78cc, 0x78fc,
2075 		0x7b00, 0x7b58,
2076 		0x7b60, 0x7b84,
2077 		0x7b8c, 0x7c54,
2078 		0x7d00, 0x7d38,
2079 		0x7d40, 0x7d84,
2080 		0x7d8c, 0x7ddc,
2081 		0x7de4, 0x7e04,
2082 		0x7e10, 0x7e1c,
2083 		0x7e24, 0x7e38,
2084 		0x7e40, 0x7e44,
2085 		0x7e4c, 0x7e78,
2086 		0x7e80, 0x7edc,
2087 		0x7ee8, 0x7efc,
2088 		0x8dc0, 0x8de4,
2089 		0x8df8, 0x8e04,
2090 		0x8e10, 0x8e84,
2091 		0x8ea0, 0x8f88,
2092 		0x8fb8, 0x9058,
2093 		0x9060, 0x9060,
2094 		0x9068, 0x90f8,
2095 		0x9100, 0x9124,
2096 		0x9400, 0x9470,
2097 		0x9600, 0x9600,
2098 		0x9608, 0x9638,
2099 		0x9640, 0x9704,
2100 		0x9710, 0x971c,
2101 		0x9800, 0x9808,
2102 		0x9820, 0x983c,
2103 		0x9850, 0x9864,
2104 		0x9c00, 0x9c6c,
2105 		0x9c80, 0x9cec,
2106 		0x9d00, 0x9d6c,
2107 		0x9d80, 0x9dec,
2108 		0x9e00, 0x9e6c,
2109 		0x9e80, 0x9eec,
2110 		0x9f00, 0x9f6c,
2111 		0x9f80, 0xa020,
2112 		0xd004, 0xd03c,
2113 		0xd100, 0xd118,
2114 		0xd200, 0xd214,
2115 		0xd220, 0xd234,
2116 		0xd240, 0xd254,
2117 		0xd260, 0xd274,
2118 		0xd280, 0xd294,
2119 		0xd2a0, 0xd2b4,
2120 		0xd2c0, 0xd2d4,
2121 		0xd2e0, 0xd2f4,
2122 		0xd300, 0xd31c,
2123 		0xdfc0, 0xdfe0,
2124 		0xe000, 0xf008,
2125 		0xf010, 0xf018,
2126 		0xf020, 0xf028,
2127 		0x11000, 0x11014,
2128 		0x11048, 0x1106c,
2129 		0x11074, 0x11088,
2130 		0x11098, 0x11120,
2131 		0x1112c, 0x1117c,
2132 		0x11190, 0x112e0,
2133 		0x11300, 0x1130c,
2134 		0x12000, 0x1206c,
2135 		0x19040, 0x1906c,
2136 		0x19078, 0x19080,
2137 		0x1908c, 0x190e8,
2138 		0x190f0, 0x190f8,
2139 		0x19100, 0x19110,
2140 		0x19120, 0x19124,
2141 		0x19150, 0x19194,
2142 		0x1919c, 0x191b0,
2143 		0x191d0, 0x191e8,
2144 		0x19238, 0x19290,
2145 		0x192a4, 0x192b0,
2146 		0x192bc, 0x192bc,
2147 		0x19348, 0x1934c,
2148 		0x193f8, 0x19418,
2149 		0x19420, 0x19428,
2150 		0x19430, 0x19444,
2151 		0x1944c, 0x1946c,
2152 		0x19474, 0x19474,
2153 		0x19490, 0x194cc,
2154 		0x194f0, 0x194f8,
2155 		0x19c00, 0x19c48,
2156 		0x19c50, 0x19c80,
2157 		0x19c94, 0x19c98,
2158 		0x19ca0, 0x19cbc,
2159 		0x19ce4, 0x19ce4,
2160 		0x19cf0, 0x19cf8,
2161 		0x19d00, 0x19d28,
2162 		0x19d50, 0x19d78,
2163 		0x19d94, 0x19d98,
2164 		0x19da0, 0x19dc8,
2165 		0x19df0, 0x19e10,
2166 		0x19e50, 0x19e6c,
2167 		0x19ea0, 0x19ebc,
2168 		0x19ec4, 0x19ef4,
2169 		0x19f04, 0x19f2c,
2170 		0x19f34, 0x19f34,
2171 		0x19f40, 0x19f50,
2172 		0x19f90, 0x19fac,
2173 		0x19fc4, 0x19fc8,
2174 		0x19fd0, 0x19fe4,
2175 		0x1a000, 0x1a004,
2176 		0x1a010, 0x1a06c,
2177 		0x1a0b0, 0x1a0e4,
2178 		0x1a0ec, 0x1a0f8,
2179 		0x1a100, 0x1a108,
2180 		0x1a114, 0x1a120,
2181 		0x1a128, 0x1a130,
2182 		0x1a138, 0x1a138,
2183 		0x1a190, 0x1a1c4,
2184 		0x1a1fc, 0x1a1fc,
2185 		0x1e008, 0x1e00c,
2186 		0x1e040, 0x1e044,
2187 		0x1e04c, 0x1e04c,
2188 		0x1e284, 0x1e290,
2189 		0x1e2c0, 0x1e2c0,
2190 		0x1e2e0, 0x1e2e0,
2191 		0x1e300, 0x1e384,
2192 		0x1e3c0, 0x1e3c8,
2193 		0x1e408, 0x1e40c,
2194 		0x1e440, 0x1e444,
2195 		0x1e44c, 0x1e44c,
2196 		0x1e684, 0x1e690,
2197 		0x1e6c0, 0x1e6c0,
2198 		0x1e6e0, 0x1e6e0,
2199 		0x1e700, 0x1e784,
2200 		0x1e7c0, 0x1e7c8,
2201 		0x1e808, 0x1e80c,
2202 		0x1e840, 0x1e844,
2203 		0x1e84c, 0x1e84c,
2204 		0x1ea84, 0x1ea90,
2205 		0x1eac0, 0x1eac0,
2206 		0x1eae0, 0x1eae0,
2207 		0x1eb00, 0x1eb84,
2208 		0x1ebc0, 0x1ebc8,
2209 		0x1ec08, 0x1ec0c,
2210 		0x1ec40, 0x1ec44,
2211 		0x1ec4c, 0x1ec4c,
2212 		0x1ee84, 0x1ee90,
2213 		0x1eec0, 0x1eec0,
2214 		0x1eee0, 0x1eee0,
2215 		0x1ef00, 0x1ef84,
2216 		0x1efc0, 0x1efc8,
2217 		0x1f008, 0x1f00c,
2218 		0x1f040, 0x1f044,
2219 		0x1f04c, 0x1f04c,
2220 		0x1f284, 0x1f290,
2221 		0x1f2c0, 0x1f2c0,
2222 		0x1f2e0, 0x1f2e0,
2223 		0x1f300, 0x1f384,
2224 		0x1f3c0, 0x1f3c8,
2225 		0x1f408, 0x1f40c,
2226 		0x1f440, 0x1f444,
2227 		0x1f44c, 0x1f44c,
2228 		0x1f684, 0x1f690,
2229 		0x1f6c0, 0x1f6c0,
2230 		0x1f6e0, 0x1f6e0,
2231 		0x1f700, 0x1f784,
2232 		0x1f7c0, 0x1f7c8,
2233 		0x1f808, 0x1f80c,
2234 		0x1f840, 0x1f844,
2235 		0x1f84c, 0x1f84c,
2236 		0x1fa84, 0x1fa90,
2237 		0x1fac0, 0x1fac0,
2238 		0x1fae0, 0x1fae0,
2239 		0x1fb00, 0x1fb84,
2240 		0x1fbc0, 0x1fbc8,
2241 		0x1fc08, 0x1fc0c,
2242 		0x1fc40, 0x1fc44,
2243 		0x1fc4c, 0x1fc4c,
2244 		0x1fe84, 0x1fe90,
2245 		0x1fec0, 0x1fec0,
2246 		0x1fee0, 0x1fee0,
2247 		0x1ff00, 0x1ff84,
2248 		0x1ffc0, 0x1ffc8,
2249 		0x30000, 0x30030,
2250 		0x30100, 0x30168,
2251 		0x30190, 0x301a0,
2252 		0x301a8, 0x301b8,
2253 		0x301c4, 0x301c8,
2254 		0x301d0, 0x301d0,
2255 		0x30200, 0x30320,
2256 		0x30400, 0x304b4,
2257 		0x304c0, 0x3052c,
2258 		0x30540, 0x3061c,
2259 		0x30800, 0x308a0,
2260 		0x308c0, 0x30908,
2261 		0x30910, 0x309b8,
2262 		0x30a00, 0x30a04,
2263 		0x30a0c, 0x30a14,
2264 		0x30a1c, 0x30a2c,
2265 		0x30a44, 0x30a50,
2266 		0x30a74, 0x30a74,
2267 		0x30a7c, 0x30afc,
2268 		0x30b08, 0x30c24,
2269 		0x30d00, 0x30d14,
2270 		0x30d1c, 0x30d3c,
2271 		0x30d44, 0x30d4c,
2272 		0x30d54, 0x30d74,
2273 		0x30d7c, 0x30d7c,
2274 		0x30de0, 0x30de0,
2275 		0x30e00, 0x30ed4,
2276 		0x30f00, 0x30fa4,
2277 		0x30fc0, 0x30fc4,
2278 		0x31000, 0x31004,
2279 		0x31080, 0x310fc,
2280 		0x31208, 0x31220,
2281 		0x3123c, 0x31254,
2282 		0x31300, 0x31300,
2283 		0x31308, 0x3131c,
2284 		0x31338, 0x3133c,
2285 		0x31380, 0x31380,
2286 		0x31388, 0x313a8,
2287 		0x313b4, 0x313b4,
2288 		0x31400, 0x31420,
2289 		0x31438, 0x3143c,
2290 		0x31480, 0x31480,
2291 		0x314a8, 0x314a8,
2292 		0x314b0, 0x314b4,
2293 		0x314c8, 0x314d4,
2294 		0x31a40, 0x31a4c,
2295 		0x31af0, 0x31b20,
2296 		0x31b38, 0x31b3c,
2297 		0x31b80, 0x31b80,
2298 		0x31ba8, 0x31ba8,
2299 		0x31bb0, 0x31bb4,
2300 		0x31bc8, 0x31bd4,
2301 		0x32140, 0x3218c,
2302 		0x321f0, 0x321f4,
2303 		0x32200, 0x32200,
2304 		0x32218, 0x32218,
2305 		0x32400, 0x32400,
2306 		0x32408, 0x3241c,
2307 		0x32618, 0x32620,
2308 		0x32664, 0x32664,
2309 		0x326a8, 0x326a8,
2310 		0x326ec, 0x326ec,
2311 		0x32a00, 0x32abc,
2312 		0x32b00, 0x32b18,
2313 		0x32b20, 0x32b38,
2314 		0x32b40, 0x32b58,
2315 		0x32b60, 0x32b78,
2316 		0x32c00, 0x32c00,
2317 		0x32c08, 0x32c3c,
2318 		0x33000, 0x3302c,
2319 		0x33034, 0x33050,
2320 		0x33058, 0x33058,
2321 		0x33060, 0x3308c,
2322 		0x3309c, 0x330ac,
2323 		0x330c0, 0x330c0,
2324 		0x330c8, 0x330d0,
2325 		0x330d8, 0x330e0,
2326 		0x330ec, 0x3312c,
2327 		0x33134, 0x33150,
2328 		0x33158, 0x33158,
2329 		0x33160, 0x3318c,
2330 		0x3319c, 0x331ac,
2331 		0x331c0, 0x331c0,
2332 		0x331c8, 0x331d0,
2333 		0x331d8, 0x331e0,
2334 		0x331ec, 0x33290,
2335 		0x33298, 0x332c4,
2336 		0x332e4, 0x33390,
2337 		0x33398, 0x333c4,
2338 		0x333e4, 0x3342c,
2339 		0x33434, 0x33450,
2340 		0x33458, 0x33458,
2341 		0x33460, 0x3348c,
2342 		0x3349c, 0x334ac,
2343 		0x334c0, 0x334c0,
2344 		0x334c8, 0x334d0,
2345 		0x334d8, 0x334e0,
2346 		0x334ec, 0x3352c,
2347 		0x33534, 0x33550,
2348 		0x33558, 0x33558,
2349 		0x33560, 0x3358c,
2350 		0x3359c, 0x335ac,
2351 		0x335c0, 0x335c0,
2352 		0x335c8, 0x335d0,
2353 		0x335d8, 0x335e0,
2354 		0x335ec, 0x33690,
2355 		0x33698, 0x336c4,
2356 		0x336e4, 0x33790,
2357 		0x33798, 0x337c4,
2358 		0x337e4, 0x337fc,
2359 		0x33814, 0x33814,
2360 		0x33854, 0x33868,
2361 		0x33880, 0x3388c,
2362 		0x338c0, 0x338d0,
2363 		0x338e8, 0x338ec,
2364 		0x33900, 0x3392c,
2365 		0x33934, 0x33950,
2366 		0x33958, 0x33958,
2367 		0x33960, 0x3398c,
2368 		0x3399c, 0x339ac,
2369 		0x339c0, 0x339c0,
2370 		0x339c8, 0x339d0,
2371 		0x339d8, 0x339e0,
2372 		0x339ec, 0x33a90,
2373 		0x33a98, 0x33ac4,
2374 		0x33ae4, 0x33b10,
2375 		0x33b24, 0x33b28,
2376 		0x33b38, 0x33b50,
2377 		0x33bf0, 0x33c10,
2378 		0x33c24, 0x33c28,
2379 		0x33c38, 0x33c50,
2380 		0x33cf0, 0x33cfc,
2381 		0x34000, 0x34030,
2382 		0x34100, 0x34168,
2383 		0x34190, 0x341a0,
2384 		0x341a8, 0x341b8,
2385 		0x341c4, 0x341c8,
2386 		0x341d0, 0x341d0,
2387 		0x34200, 0x34320,
2388 		0x34400, 0x344b4,
2389 		0x344c0, 0x3452c,
2390 		0x34540, 0x3461c,
2391 		0x34800, 0x348a0,
2392 		0x348c0, 0x34908,
2393 		0x34910, 0x349b8,
2394 		0x34a00, 0x34a04,
2395 		0x34a0c, 0x34a14,
2396 		0x34a1c, 0x34a2c,
2397 		0x34a44, 0x34a50,
2398 		0x34a74, 0x34a74,
2399 		0x34a7c, 0x34afc,
2400 		0x34b08, 0x34c24,
2401 		0x34d00, 0x34d14,
2402 		0x34d1c, 0x34d3c,
2403 		0x34d44, 0x34d4c,
2404 		0x34d54, 0x34d74,
2405 		0x34d7c, 0x34d7c,
2406 		0x34de0, 0x34de0,
2407 		0x34e00, 0x34ed4,
2408 		0x34f00, 0x34fa4,
2409 		0x34fc0, 0x34fc4,
2410 		0x35000, 0x35004,
2411 		0x35080, 0x350fc,
2412 		0x35208, 0x35220,
2413 		0x3523c, 0x35254,
2414 		0x35300, 0x35300,
2415 		0x35308, 0x3531c,
2416 		0x35338, 0x3533c,
2417 		0x35380, 0x35380,
2418 		0x35388, 0x353a8,
2419 		0x353b4, 0x353b4,
2420 		0x35400, 0x35420,
2421 		0x35438, 0x3543c,
2422 		0x35480, 0x35480,
2423 		0x354a8, 0x354a8,
2424 		0x354b0, 0x354b4,
2425 		0x354c8, 0x354d4,
2426 		0x35a40, 0x35a4c,
2427 		0x35af0, 0x35b20,
2428 		0x35b38, 0x35b3c,
2429 		0x35b80, 0x35b80,
2430 		0x35ba8, 0x35ba8,
2431 		0x35bb0, 0x35bb4,
2432 		0x35bc8, 0x35bd4,
2433 		0x36140, 0x3618c,
2434 		0x361f0, 0x361f4,
2435 		0x36200, 0x36200,
2436 		0x36218, 0x36218,
2437 		0x36400, 0x36400,
2438 		0x36408, 0x3641c,
2439 		0x36618, 0x36620,
2440 		0x36664, 0x36664,
2441 		0x366a8, 0x366a8,
2442 		0x366ec, 0x366ec,
2443 		0x36a00, 0x36abc,
2444 		0x36b00, 0x36b18,
2445 		0x36b20, 0x36b38,
2446 		0x36b40, 0x36b58,
2447 		0x36b60, 0x36b78,
2448 		0x36c00, 0x36c00,
2449 		0x36c08, 0x36c3c,
2450 		0x37000, 0x3702c,
2451 		0x37034, 0x37050,
2452 		0x37058, 0x37058,
2453 		0x37060, 0x3708c,
2454 		0x3709c, 0x370ac,
2455 		0x370c0, 0x370c0,
2456 		0x370c8, 0x370d0,
2457 		0x370d8, 0x370e0,
2458 		0x370ec, 0x3712c,
2459 		0x37134, 0x37150,
2460 		0x37158, 0x37158,
2461 		0x37160, 0x3718c,
2462 		0x3719c, 0x371ac,
2463 		0x371c0, 0x371c0,
2464 		0x371c8, 0x371d0,
2465 		0x371d8, 0x371e0,
2466 		0x371ec, 0x37290,
2467 		0x37298, 0x372c4,
2468 		0x372e4, 0x37390,
2469 		0x37398, 0x373c4,
2470 		0x373e4, 0x3742c,
2471 		0x37434, 0x37450,
2472 		0x37458, 0x37458,
2473 		0x37460, 0x3748c,
2474 		0x3749c, 0x374ac,
2475 		0x374c0, 0x374c0,
2476 		0x374c8, 0x374d0,
2477 		0x374d8, 0x374e0,
2478 		0x374ec, 0x3752c,
2479 		0x37534, 0x37550,
2480 		0x37558, 0x37558,
2481 		0x37560, 0x3758c,
2482 		0x3759c, 0x375ac,
2483 		0x375c0, 0x375c0,
2484 		0x375c8, 0x375d0,
2485 		0x375d8, 0x375e0,
2486 		0x375ec, 0x37690,
2487 		0x37698, 0x376c4,
2488 		0x376e4, 0x37790,
2489 		0x37798, 0x377c4,
2490 		0x377e4, 0x377fc,
2491 		0x37814, 0x37814,
2492 		0x37854, 0x37868,
2493 		0x37880, 0x3788c,
2494 		0x378c0, 0x378d0,
2495 		0x378e8, 0x378ec,
2496 		0x37900, 0x3792c,
2497 		0x37934, 0x37950,
2498 		0x37958, 0x37958,
2499 		0x37960, 0x3798c,
2500 		0x3799c, 0x379ac,
2501 		0x379c0, 0x379c0,
2502 		0x379c8, 0x379d0,
2503 		0x379d8, 0x379e0,
2504 		0x379ec, 0x37a90,
2505 		0x37a98, 0x37ac4,
2506 		0x37ae4, 0x37b10,
2507 		0x37b24, 0x37b28,
2508 		0x37b38, 0x37b50,
2509 		0x37bf0, 0x37c10,
2510 		0x37c24, 0x37c28,
2511 		0x37c38, 0x37c50,
2512 		0x37cf0, 0x37cfc,
2513 		0x40040, 0x40040,
2514 		0x40080, 0x40084,
2515 		0x40100, 0x40100,
2516 		0x40140, 0x401bc,
2517 		0x40200, 0x40214,
2518 		0x40228, 0x40228,
2519 		0x40240, 0x40258,
2520 		0x40280, 0x40280,
2521 		0x40304, 0x40304,
2522 		0x40330, 0x4033c,
2523 		0x41304, 0x413c8,
2524 		0x413d0, 0x413dc,
2525 		0x413f0, 0x413f0,
2526 		0x41400, 0x4140c,
2527 		0x41414, 0x4141c,
2528 		0x41480, 0x414d0,
2529 		0x44000, 0x4407c,
2530 		0x440c0, 0x441ac,
2531 		0x441b4, 0x4427c,
2532 		0x442c0, 0x443ac,
2533 		0x443b4, 0x4447c,
2534 		0x444c0, 0x445ac,
2535 		0x445b4, 0x4467c,
2536 		0x446c0, 0x447ac,
2537 		0x447b4, 0x4487c,
2538 		0x448c0, 0x449ac,
2539 		0x449b4, 0x44a7c,
2540 		0x44ac0, 0x44bac,
2541 		0x44bb4, 0x44c7c,
2542 		0x44cc0, 0x44dac,
2543 		0x44db4, 0x44e7c,
2544 		0x44ec0, 0x44fac,
2545 		0x44fb4, 0x4507c,
2546 		0x450c0, 0x451ac,
2547 		0x451b4, 0x451fc,
2548 		0x45800, 0x45804,
2549 		0x45810, 0x45830,
2550 		0x45840, 0x45860,
2551 		0x45868, 0x45868,
2552 		0x45880, 0x45884,
2553 		0x458a0, 0x458b0,
2554 		0x45a00, 0x45a04,
2555 		0x45a10, 0x45a30,
2556 		0x45a40, 0x45a60,
2557 		0x45a68, 0x45a68,
2558 		0x45a80, 0x45a84,
2559 		0x45aa0, 0x45ab0,
2560 		0x460c0, 0x460e4,
2561 		0x47000, 0x4703c,
2562 		0x47044, 0x4708c,
2563 		0x47200, 0x47250,
2564 		0x47400, 0x47408,
2565 		0x47414, 0x47420,
2566 		0x47600, 0x47618,
2567 		0x47800, 0x47814,
2568 		0x47820, 0x4782c,
2569 		0x50000, 0x50084,
2570 		0x50090, 0x500cc,
2571 		0x50300, 0x50384,
2572 		0x50400, 0x50400,
2573 		0x50800, 0x50884,
2574 		0x50890, 0x508cc,
2575 		0x50b00, 0x50b84,
2576 		0x50c00, 0x50c00,
2577 		0x51000, 0x51020,
2578 		0x51028, 0x510b0,
2579 		0x51300, 0x51324,
2580 	};
2581 
2582 	static const unsigned int t6vf_reg_ranges[] = {
2583 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2584 		VF_MPS_REG(A_MPS_VF_CTL),
2585 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2586 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2587 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2588 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2589 		FW_T6VF_MBDATA_BASE_ADDR,
2590 		FW_T6VF_MBDATA_BASE_ADDR +
2591 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2592 	};
2593 
2594 	u32 *buf_end = (u32 *)(buf + buf_size);
2595 	const unsigned int *reg_ranges;
2596 	int reg_ranges_size, range;
2597 	unsigned int chip_version = chip_id(adap);
2598 
2599 	/*
2600 	 * Select the right set of register ranges to dump depending on the
2601 	 * adapter chip type.
2602 	 */
2603 	switch (chip_version) {
2604 	case CHELSIO_T4:
2605 		if (adap->flags & IS_VF) {
2606 			reg_ranges = t4vf_reg_ranges;
2607 			reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2608 		} else {
2609 			reg_ranges = t4_reg_ranges;
2610 			reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2611 		}
2612 		break;
2613 
2614 	case CHELSIO_T5:
2615 		if (adap->flags & IS_VF) {
2616 			reg_ranges = t5vf_reg_ranges;
2617 			reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2618 		} else {
2619 			reg_ranges = t5_reg_ranges;
2620 			reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2621 		}
2622 		break;
2623 
2624 	case CHELSIO_T6:
2625 		if (adap->flags & IS_VF) {
2626 			reg_ranges = t6vf_reg_ranges;
2627 			reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2628 		} else {
2629 			reg_ranges = t6_reg_ranges;
2630 			reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2631 		}
2632 		break;
2633 
2634 	default:
2635 		CH_ERR(adap,
2636 			"Unsupported chip version %d\n", chip_version);
2637 		return;
2638 	}
2639 
2640 	/*
2641 	 * Clear the register buffer and insert the appropriate register
2642 	 * values selected by the above register ranges.
2643 	 */
2644 	memset(buf, 0, buf_size);
2645 	for (range = 0; range < reg_ranges_size; range += 2) {
2646 		unsigned int reg = reg_ranges[range];
2647 		unsigned int last_reg = reg_ranges[range + 1];
2648 		u32 *bufp = (u32 *)(buf + reg);
2649 
2650 		/*
2651 		 * Iterate across the register range filling in the register
2652 		 * buffer but don't write past the end of the register buffer.
2653 		 */
2654 		while (reg <= last_reg && bufp < buf_end) {
2655 			*bufp++ = t4_read_reg(adap, reg);
2656 			reg += sizeof(u32);
2657 		}
2658 	}
2659 }
2660 
2661 /*
2662  * Partial EEPROM Vital Product Data structure.  Includes only the ID and
2663  * VPD-R sections.
2664  */
2665 struct t4_vpd_hdr {
2666 	u8  id_tag;
2667 	u8  id_len[2];
2668 	u8  id_data[ID_LEN];
2669 	u8  vpdr_tag;
2670 	u8  vpdr_len[2];
2671 };
2672 
2673 /*
2674  * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2675  */
2676 #define EEPROM_DELAY		10		/* 10us per poll spin */
2677 #define EEPROM_MAX_POLL		5000		/* x 5000 == 50ms */
2678 
2679 #define EEPROM_STAT_ADDR	0x7bfc
2680 #define VPD_SIZE		0x800
2681 #define VPD_BASE		0x400
2682 #define VPD_BASE_OLD		0
2683 #define VPD_LEN			1024
2684 #define VPD_INFO_FLD_HDR_SIZE	3
2685 #define CHELSIO_VPD_UNIQUE_ID	0x82
2686 
2687 /*
2688  * Small utility function to wait till any outstanding VPD Access is complete.
2689  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2690  * VPD Access in flight.  This allows us to handle the problem of having a
2691  * previous VPD Access time out and prevent an attempt to inject a new VPD
2692  * Request before any in-flight VPD reguest has completed.
2693  */
2694 static int t4_seeprom_wait(struct adapter *adapter)
2695 {
2696 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2697 	int max_poll;
2698 
2699 	/*
2700 	 * If no VPD Access is in flight, we can just return success right
2701 	 * away.
2702 	 */
2703 	if (!adapter->vpd_busy)
2704 		return 0;
2705 
2706 	/*
2707 	 * Poll the VPD Capability Address/Flag register waiting for it
2708 	 * to indicate that the operation is complete.
2709 	 */
2710 	max_poll = EEPROM_MAX_POLL;
2711 	do {
2712 		u16 val;
2713 
2714 		udelay(EEPROM_DELAY);
2715 		t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2716 
2717 		/*
2718 		 * If the operation is complete, mark the VPD as no longer
2719 		 * busy and return success.
2720 		 */
2721 		if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2722 			adapter->vpd_busy = 0;
2723 			return 0;
2724 		}
2725 	} while (--max_poll);
2726 
2727 	/*
2728 	 * Failure!  Note that we leave the VPD Busy status set in order to
2729 	 * avoid pushing a new VPD Access request into the VPD Capability till
2730 	 * the current operation eventually succeeds.  It's a bug to issue a
2731 	 * new request when an existing request is in flight and will result
2732 	 * in corrupt hardware state.
2733 	 */
2734 	return -ETIMEDOUT;
2735 }
2736 
2737 /**
2738  *	t4_seeprom_read - read a serial EEPROM location
2739  *	@adapter: adapter to read
2740  *	@addr: EEPROM virtual address
2741  *	@data: where to store the read data
2742  *
2743  *	Read a 32-bit word from a location in serial EEPROM using the card's PCI
2744  *	VPD capability.  Note that this function must be called with a virtual
2745  *	address.
2746  */
2747 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2748 {
2749 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2750 	int ret;
2751 
2752 	/*
2753 	 * VPD Accesses must alway be 4-byte aligned!
2754 	 */
2755 	if (addr >= EEPROMVSIZE || (addr & 3))
2756 		return -EINVAL;
2757 
2758 	/*
2759 	 * Wait for any previous operation which may still be in flight to
2760 	 * complete.
2761 	 */
2762 	ret = t4_seeprom_wait(adapter);
2763 	if (ret) {
2764 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2765 		return ret;
2766 	}
2767 
2768 	/*
2769 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2770 	 * for our request to complete.  If it doesn't complete, note the
2771 	 * error and return it to our caller.  Note that we do not reset the
2772 	 * VPD Busy status!
2773 	 */
2774 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2775 	adapter->vpd_busy = 1;
2776 	adapter->vpd_flag = PCI_VPD_ADDR_F;
2777 	ret = t4_seeprom_wait(adapter);
2778 	if (ret) {
2779 		CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2780 		return ret;
2781 	}
2782 
2783 	/*
2784 	 * Grab the returned data, swizzle it into our endianness and
2785 	 * return success.
2786 	 */
2787 	t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2788 	*data = le32_to_cpu(*data);
2789 	return 0;
2790 }
2791 
2792 /**
2793  *	t4_seeprom_write - write a serial EEPROM location
2794  *	@adapter: adapter to write
2795  *	@addr: virtual EEPROM address
2796  *	@data: value to write
2797  *
2798  *	Write a 32-bit word to a location in serial EEPROM using the card's PCI
2799  *	VPD capability.  Note that this function must be called with a virtual
2800  *	address.
2801  */
2802 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2803 {
2804 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2805 	int ret;
2806 	u32 stats_reg;
2807 	int max_poll;
2808 
2809 	/*
2810 	 * VPD Accesses must alway be 4-byte aligned!
2811 	 */
2812 	if (addr >= EEPROMVSIZE || (addr & 3))
2813 		return -EINVAL;
2814 
2815 	/*
2816 	 * Wait for any previous operation which may still be in flight to
2817 	 * complete.
2818 	 */
2819 	ret = t4_seeprom_wait(adapter);
2820 	if (ret) {
2821 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2822 		return ret;
2823 	}
2824 
2825 	/*
2826 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2827 	 * for our request to complete.  If it doesn't complete, note the
2828 	 * error and return it to our caller.  Note that we do not reset the
2829 	 * VPD Busy status!
2830 	 */
2831 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2832 				 cpu_to_le32(data));
2833 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2834 				 (u16)addr | PCI_VPD_ADDR_F);
2835 	adapter->vpd_busy = 1;
2836 	adapter->vpd_flag = 0;
2837 	ret = t4_seeprom_wait(adapter);
2838 	if (ret) {
2839 		CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2840 		return ret;
2841 	}
2842 
2843 	/*
2844 	 * Reset PCI_VPD_DATA register after a transaction and wait for our
2845 	 * request to complete. If it doesn't complete, return error.
2846 	 */
2847 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2848 	max_poll = EEPROM_MAX_POLL;
2849 	do {
2850 		udelay(EEPROM_DELAY);
2851 		t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2852 	} while ((stats_reg & 0x1) && --max_poll);
2853 	if (!max_poll)
2854 		return -ETIMEDOUT;
2855 
2856 	/* Return success! */
2857 	return 0;
2858 }
2859 
2860 /**
2861  *	t4_eeprom_ptov - translate a physical EEPROM address to virtual
2862  *	@phys_addr: the physical EEPROM address
2863  *	@fn: the PCI function number
2864  *	@sz: size of function-specific area
2865  *
2866  *	Translate a physical EEPROM address to virtual.  The first 1K is
2867  *	accessed through virtual addresses starting at 31K, the rest is
2868  *	accessed through virtual addresses starting at 0.
2869  *
2870  *	The mapping is as follows:
2871  *	[0..1K) -> [31K..32K)
2872  *	[1K..1K+A) -> [ES-A..ES)
2873  *	[1K+A..ES) -> [0..ES-A-1K)
2874  *
2875  *	where A = @fn * @sz, and ES = EEPROM size.
2876  */
2877 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2878 {
2879 	fn *= sz;
2880 	if (phys_addr < 1024)
2881 		return phys_addr + (31 << 10);
2882 	if (phys_addr < 1024 + fn)
2883 		return EEPROMSIZE - fn + phys_addr - 1024;
2884 	if (phys_addr < EEPROMSIZE)
2885 		return phys_addr - 1024 - fn;
2886 	return -EINVAL;
2887 }
2888 
2889 /**
2890  *	t4_seeprom_wp - enable/disable EEPROM write protection
2891  *	@adapter: the adapter
2892  *	@enable: whether to enable or disable write protection
2893  *
2894  *	Enables or disables write protection on the serial EEPROM.
2895  */
2896 int t4_seeprom_wp(struct adapter *adapter, int enable)
2897 {
2898 	return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2899 }
2900 
2901 /**
2902  *	get_vpd_keyword_val - Locates an information field keyword in the VPD
2903  *	@v: Pointer to buffered vpd data structure
2904  *	@kw: The keyword to search for
2905  *
2906  *	Returns the value of the information field keyword or
2907  *	-ENOENT otherwise.
2908  */
2909 static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
2910 {
2911 	int i;
2912 	unsigned int offset , len;
2913 	const u8 *buf = (const u8 *)v;
2914 	const u8 *vpdr_len = &v->vpdr_len[0];
2915 	offset = sizeof(struct t4_vpd_hdr);
2916 	len =  (u16)vpdr_len[0] + ((u16)vpdr_len[1] << 8);
2917 
2918 	if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) {
2919 		return -ENOENT;
2920 	}
2921 
2922 	for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2923 		if(memcmp(buf + i , kw , 2) == 0){
2924 			i += VPD_INFO_FLD_HDR_SIZE;
2925 			return i;
2926 		}
2927 
2928 		i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
2929 	}
2930 
2931 	return -ENOENT;
2932 }
2933 
2934 
2935 /**
2936  *	get_vpd_params - read VPD parameters from VPD EEPROM
2937  *	@adapter: adapter to read
2938  *	@p: where to store the parameters
2939  *	@vpd: caller provided temporary space to read the VPD into
2940  *
2941  *	Reads card parameters stored in VPD EEPROM.
2942  */
2943 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
2944     u8 *vpd)
2945 {
2946 	int i, ret, addr;
2947 	int ec, sn, pn, na;
2948 	u8 csum;
2949 	const struct t4_vpd_hdr *v;
2950 
2951 	/*
2952 	 * Card information normally starts at VPD_BASE but early cards had
2953 	 * it at 0.
2954 	 */
2955 	ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd));
2956 	if (ret)
2957 		return (ret);
2958 
2959 	/*
2960 	 * The VPD shall have a unique identifier specified by the PCI SIG.
2961 	 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2962 	 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2963 	 * is expected to automatically put this entry at the
2964 	 * beginning of the VPD.
2965 	 */
2966 	addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2967 
2968 	for (i = 0; i < VPD_LEN; i += 4) {
2969 		ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i));
2970 		if (ret)
2971 			return ret;
2972 	}
2973  	v = (const struct t4_vpd_hdr *)vpd;
2974 
2975 #define FIND_VPD_KW(var,name) do { \
2976 	var = get_vpd_keyword_val(v , name); \
2977 	if (var < 0) { \
2978 		CH_ERR(adapter, "missing VPD keyword " name "\n"); \
2979 		return -EINVAL; \
2980 	} \
2981 } while (0)
2982 
2983 	FIND_VPD_KW(i, "RV");
2984 	for (csum = 0; i >= 0; i--)
2985 		csum += vpd[i];
2986 
2987 	if (csum) {
2988 		CH_ERR(adapter,
2989 			"corrupted VPD EEPROM, actual csum %u\n", csum);
2990 		return -EINVAL;
2991 	}
2992 
2993 	FIND_VPD_KW(ec, "EC");
2994 	FIND_VPD_KW(sn, "SN");
2995 	FIND_VPD_KW(pn, "PN");
2996 	FIND_VPD_KW(na, "NA");
2997 #undef FIND_VPD_KW
2998 
2999 	memcpy(p->id, v->id_data, ID_LEN);
3000 	strstrip(p->id);
3001 	memcpy(p->ec, vpd + ec, EC_LEN);
3002 	strstrip(p->ec);
3003 	i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3004 	memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3005 	strstrip(p->sn);
3006 	i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3007 	memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3008 	strstrip((char *)p->pn);
3009 	i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3010 	memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3011 	strstrip((char *)p->na);
3012 
3013 	return 0;
3014 }
3015 
3016 /* serial flash and firmware constants and flash config file constants */
3017 enum {
3018 	SF_ATTEMPTS = 10,	/* max retries for SF operations */
3019 
3020 	/* flash command opcodes */
3021 	SF_PROG_PAGE    = 2,	/* program 256B page */
3022 	SF_WR_DISABLE   = 4,	/* disable writes */
3023 	SF_RD_STATUS    = 5,	/* read status register */
3024 	SF_WR_ENABLE    = 6,	/* enable writes */
3025 	SF_RD_DATA_FAST = 0xb,	/* read flash */
3026 	SF_RD_ID	= 0x9f,	/* read ID */
3027 	SF_ERASE_SECTOR = 0xd8,	/* erase 64KB sector */
3028 };
3029 
3030 /**
3031  *	sf1_read - read data from the serial flash
3032  *	@adapter: the adapter
3033  *	@byte_cnt: number of bytes to read
3034  *	@cont: whether another operation will be chained
3035  *	@lock: whether to lock SF for PL access only
3036  *	@valp: where to store the read data
3037  *
3038  *	Reads up to 4 bytes of data from the serial flash.  The location of
3039  *	the read needs to be specified prior to calling this by issuing the
3040  *	appropriate commands to the serial flash.
3041  */
3042 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3043 		    int lock, u32 *valp)
3044 {
3045 	int ret;
3046 
3047 	if (!byte_cnt || byte_cnt > 4)
3048 		return -EINVAL;
3049 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3050 		return -EBUSY;
3051 	t4_write_reg(adapter, A_SF_OP,
3052 		     V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3053 	ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3054 	if (!ret)
3055 		*valp = t4_read_reg(adapter, A_SF_DATA);
3056 	return ret;
3057 }
3058 
3059 /**
3060  *	sf1_write - write data to the serial flash
3061  *	@adapter: the adapter
3062  *	@byte_cnt: number of bytes to write
3063  *	@cont: whether another operation will be chained
3064  *	@lock: whether to lock SF for PL access only
3065  *	@val: value to write
3066  *
3067  *	Writes up to 4 bytes of data to the serial flash.  The location of
3068  *	the write needs to be specified prior to calling this by issuing the
3069  *	appropriate commands to the serial flash.
3070  */
3071 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3072 		     int lock, u32 val)
3073 {
3074 	if (!byte_cnt || byte_cnt > 4)
3075 		return -EINVAL;
3076 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3077 		return -EBUSY;
3078 	t4_write_reg(adapter, A_SF_DATA, val);
3079 	t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3080 		     V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3081 	return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3082 }
3083 
3084 /**
3085  *	flash_wait_op - wait for a flash operation to complete
3086  *	@adapter: the adapter
3087  *	@attempts: max number of polls of the status register
3088  *	@delay: delay between polls in ms
3089  *
3090  *	Wait for a flash operation to complete by polling the status register.
3091  */
3092 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3093 {
3094 	int ret;
3095 	u32 status;
3096 
3097 	while (1) {
3098 		if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3099 		    (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3100 			return ret;
3101 		if (!(status & 1))
3102 			return 0;
3103 		if (--attempts == 0)
3104 			return -EAGAIN;
3105 		if (delay)
3106 			msleep(delay);
3107 	}
3108 }
3109 
3110 /**
3111  *	t4_read_flash - read words from serial flash
3112  *	@adapter: the adapter
3113  *	@addr: the start address for the read
3114  *	@nwords: how many 32-bit words to read
3115  *	@data: where to store the read data
3116  *	@byte_oriented: whether to store data as bytes or as words
3117  *
3118  *	Read the specified number of 32-bit words from the serial flash.
3119  *	If @byte_oriented is set the read data is stored as a byte array
3120  *	(i.e., big-endian), otherwise as 32-bit words in the platform's
3121  *	natural endianness.
3122  */
3123 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3124 		  unsigned int nwords, u32 *data, int byte_oriented)
3125 {
3126 	int ret;
3127 
3128 	if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3129 		return -EINVAL;
3130 
3131 	addr = swab32(addr) | SF_RD_DATA_FAST;
3132 
3133 	if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3134 	    (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3135 		return ret;
3136 
3137 	for ( ; nwords; nwords--, data++) {
3138 		ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3139 		if (nwords == 1)
3140 			t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3141 		if (ret)
3142 			return ret;
3143 		if (byte_oriented)
3144 			*data = (__force __u32)(cpu_to_be32(*data));
3145 	}
3146 	return 0;
3147 }
3148 
3149 /**
3150  *	t4_write_flash - write up to a page of data to the serial flash
3151  *	@adapter: the adapter
3152  *	@addr: the start address to write
3153  *	@n: length of data to write in bytes
3154  *	@data: the data to write
3155  *	@byte_oriented: whether to store data as bytes or as words
3156  *
3157  *	Writes up to a page of data (256 bytes) to the serial flash starting
3158  *	at the given address.  All the data must be written to the same page.
3159  *	If @byte_oriented is set the write data is stored as byte stream
3160  *	(i.e. matches what on disk), otherwise in big-endian.
3161  */
3162 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3163 			  unsigned int n, const u8 *data, int byte_oriented)
3164 {
3165 	int ret;
3166 	u32 buf[SF_PAGE_SIZE / 4];
3167 	unsigned int i, c, left, val, offset = addr & 0xff;
3168 
3169 	if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3170 		return -EINVAL;
3171 
3172 	val = swab32(addr) | SF_PROG_PAGE;
3173 
3174 	if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3175 	    (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3176 		goto unlock;
3177 
3178 	for (left = n; left; left -= c) {
3179 		c = min(left, 4U);
3180 		for (val = 0, i = 0; i < c; ++i)
3181 			val = (val << 8) + *data++;
3182 
3183 		if (!byte_oriented)
3184 			val = cpu_to_be32(val);
3185 
3186 		ret = sf1_write(adapter, c, c != left, 1, val);
3187 		if (ret)
3188 			goto unlock;
3189 	}
3190 	ret = flash_wait_op(adapter, 8, 1);
3191 	if (ret)
3192 		goto unlock;
3193 
3194 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3195 
3196 	/* Read the page to verify the write succeeded */
3197 	ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3198 			    byte_oriented);
3199 	if (ret)
3200 		return ret;
3201 
3202 	if (memcmp(data - n, (u8 *)buf + offset, n)) {
3203 		CH_ERR(adapter,
3204 			"failed to correctly write the flash page at %#x\n",
3205 			addr);
3206 		return -EIO;
3207 	}
3208 	return 0;
3209 
3210 unlock:
3211 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3212 	return ret;
3213 }
3214 
3215 /**
3216  *	t4_get_fw_version - read the firmware version
3217  *	@adapter: the adapter
3218  *	@vers: where to place the version
3219  *
3220  *	Reads the FW version from flash.
3221  */
3222 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3223 {
3224 	return t4_read_flash(adapter, FLASH_FW_START +
3225 			     offsetof(struct fw_hdr, fw_ver), 1,
3226 			     vers, 0);
3227 }
3228 
3229 /**
3230  *	t4_get_bs_version - read the firmware bootstrap version
3231  *	@adapter: the adapter
3232  *	@vers: where to place the version
3233  *
3234  *	Reads the FW Bootstrap version from flash.
3235  */
3236 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3237 {
3238 	return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3239 			     offsetof(struct fw_hdr, fw_ver), 1,
3240 			     vers, 0);
3241 }
3242 
3243 /**
3244  *	t4_get_tp_version - read the TP microcode version
3245  *	@adapter: the adapter
3246  *	@vers: where to place the version
3247  *
3248  *	Reads the TP microcode version from flash.
3249  */
3250 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3251 {
3252 	return t4_read_flash(adapter, FLASH_FW_START +
3253 			     offsetof(struct fw_hdr, tp_microcode_ver),
3254 			     1, vers, 0);
3255 }
3256 
3257 /**
3258  *	t4_get_exprom_version - return the Expansion ROM version (if any)
3259  *	@adapter: the adapter
3260  *	@vers: where to place the version
3261  *
3262  *	Reads the Expansion ROM header from FLASH and returns the version
3263  *	number (if present) through the @vers return value pointer.  We return
3264  *	this in the Firmware Version Format since it's convenient.  Return
3265  *	0 on success, -ENOENT if no Expansion ROM is present.
3266  */
3267 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3268 {
3269 	struct exprom_header {
3270 		unsigned char hdr_arr[16];	/* must start with 0x55aa */
3271 		unsigned char hdr_ver[4];	/* Expansion ROM version */
3272 	} *hdr;
3273 	u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3274 					   sizeof(u32))];
3275 	int ret;
3276 
3277 	ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3278 			    ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3279 			    0);
3280 	if (ret)
3281 		return ret;
3282 
3283 	hdr = (struct exprom_header *)exprom_header_buf;
3284 	if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3285 		return -ENOENT;
3286 
3287 	*vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3288 		 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3289 		 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3290 		 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3291 	return 0;
3292 }
3293 
3294 /**
3295  *	t4_get_scfg_version - return the Serial Configuration version
3296  *	@adapter: the adapter
3297  *	@vers: where to place the version
3298  *
3299  *	Reads the Serial Configuration Version via the Firmware interface
3300  *	(thus this can only be called once we're ready to issue Firmware
3301  *	commands).  The format of the Serial Configuration version is
3302  *	adapter specific.  Returns 0 on success, an error on failure.
3303  *
3304  *	Note that early versions of the Firmware didn't include the ability
3305  *	to retrieve the Serial Configuration version, so we zero-out the
3306  *	return-value parameter in that case to avoid leaving it with
3307  *	garbage in it.
3308  *
3309  *	Also note that the Firmware will return its cached copy of the Serial
3310  *	Initialization Revision ID, not the actual Revision ID as written in
3311  *	the Serial EEPROM.  This is only an issue if a new VPD has been written
3312  *	and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3313  *	it's best to defer calling this routine till after a FW_RESET_CMD has
3314  *	been issued if the Host Driver will be performing a full adapter
3315  *	initialization.
3316  */
3317 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3318 {
3319 	u32 scfgrev_param;
3320 	int ret;
3321 
3322 	scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3323 			 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3324 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3325 			      1, &scfgrev_param, vers);
3326 	if (ret)
3327 		*vers = 0;
3328 	return ret;
3329 }
3330 
3331 /**
3332  *	t4_get_vpd_version - return the VPD version
3333  *	@adapter: the adapter
3334  *	@vers: where to place the version
3335  *
3336  *	Reads the VPD via the Firmware interface (thus this can only be called
3337  *	once we're ready to issue Firmware commands).  The format of the
3338  *	VPD version is adapter specific.  Returns 0 on success, an error on
3339  *	failure.
3340  *
3341  *	Note that early versions of the Firmware didn't include the ability
3342  *	to retrieve the VPD version, so we zero-out the return-value parameter
3343  *	in that case to avoid leaving it with garbage in it.
3344  *
3345  *	Also note that the Firmware will return its cached copy of the VPD
3346  *	Revision ID, not the actual Revision ID as written in the Serial
3347  *	EEPROM.  This is only an issue if a new VPD has been written and the
3348  *	Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3349  *	to defer calling this routine till after a FW_RESET_CMD has been issued
3350  *	if the Host Driver will be performing a full adapter initialization.
3351  */
3352 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3353 {
3354 	u32 vpdrev_param;
3355 	int ret;
3356 
3357 	vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3358 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3359 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3360 			      1, &vpdrev_param, vers);
3361 	if (ret)
3362 		*vers = 0;
3363 	return ret;
3364 }
3365 
3366 /**
3367  *	t4_get_version_info - extract various chip/firmware version information
3368  *	@adapter: the adapter
3369  *
3370  *	Reads various chip/firmware version numbers and stores them into the
3371  *	adapter Adapter Parameters structure.  If any of the efforts fails
3372  *	the first failure will be returned, but all of the version numbers
3373  *	will be read.
3374  */
3375 int t4_get_version_info(struct adapter *adapter)
3376 {
3377 	int ret = 0;
3378 
3379 	#define FIRST_RET(__getvinfo) \
3380 	do { \
3381 		int __ret = __getvinfo; \
3382 		if (__ret && !ret) \
3383 			ret = __ret; \
3384 	} while (0)
3385 
3386 	FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3387 	FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3388 	FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3389 	FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3390 	FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3391 	FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3392 
3393 	#undef FIRST_RET
3394 
3395 	return ret;
3396 }
3397 
3398 /**
3399  *	t4_flash_erase_sectors - erase a range of flash sectors
3400  *	@adapter: the adapter
3401  *	@start: the first sector to erase
3402  *	@end: the last sector to erase
3403  *
3404  *	Erases the sectors in the given inclusive range.
3405  */
3406 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3407 {
3408 	int ret = 0;
3409 
3410 	if (end >= adapter->params.sf_nsec)
3411 		return -EINVAL;
3412 
3413 	while (start <= end) {
3414 		if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3415 		    (ret = sf1_write(adapter, 4, 0, 1,
3416 				     SF_ERASE_SECTOR | (start << 8))) != 0 ||
3417 		    (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3418 			CH_ERR(adapter,
3419 				"erase of flash sector %d failed, error %d\n",
3420 				start, ret);
3421 			break;
3422 		}
3423 		start++;
3424 	}
3425 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3426 	return ret;
3427 }
3428 
3429 /**
3430  *	t4_flash_cfg_addr - return the address of the flash configuration file
3431  *	@adapter: the adapter
3432  *
3433  *	Return the address within the flash where the Firmware Configuration
3434  *	File is stored, or an error if the device FLASH is too small to contain
3435  *	a Firmware Configuration File.
3436  */
3437 int t4_flash_cfg_addr(struct adapter *adapter)
3438 {
3439 	/*
3440 	 * If the device FLASH isn't large enough to hold a Firmware
3441 	 * Configuration File, return an error.
3442 	 */
3443 	if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3444 		return -ENOSPC;
3445 
3446 	return FLASH_CFG_START;
3447 }
3448 
3449 /*
3450  * Return TRUE if the specified firmware matches the adapter.  I.e. T4
3451  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3452  * and emit an error message for mismatched firmware to save our caller the
3453  * effort ...
3454  */
3455 static int t4_fw_matches_chip(struct adapter *adap,
3456 			      const struct fw_hdr *hdr)
3457 {
3458 	/*
3459 	 * The expression below will return FALSE for any unsupported adapter
3460 	 * which will keep us "honest" in the future ...
3461 	 */
3462 	if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3463 	    (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3464 	    (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3465 		return 1;
3466 
3467 	CH_ERR(adap,
3468 		"FW image (%d) is not suitable for this adapter (%d)\n",
3469 		hdr->chip, chip_id(adap));
3470 	return 0;
3471 }
3472 
3473 /**
3474  *	t4_load_fw - download firmware
3475  *	@adap: the adapter
3476  *	@fw_data: the firmware image to write
3477  *	@size: image size
3478  *
3479  *	Write the supplied firmware image to the card's serial flash.
3480  */
3481 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3482 {
3483 	u32 csum;
3484 	int ret, addr;
3485 	unsigned int i;
3486 	u8 first_page[SF_PAGE_SIZE];
3487 	const u32 *p = (const u32 *)fw_data;
3488 	const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3489 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3490 	unsigned int fw_start_sec;
3491 	unsigned int fw_start;
3492 	unsigned int fw_size;
3493 
3494 	if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3495 		fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3496 		fw_start = FLASH_FWBOOTSTRAP_START;
3497 		fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3498 	} else {
3499 		fw_start_sec = FLASH_FW_START_SEC;
3500  		fw_start = FLASH_FW_START;
3501 		fw_size = FLASH_FW_MAX_SIZE;
3502 	}
3503 
3504 	if (!size) {
3505 		CH_ERR(adap, "FW image has no data\n");
3506 		return -EINVAL;
3507 	}
3508 	if (size & 511) {
3509 		CH_ERR(adap,
3510 			"FW image size not multiple of 512 bytes\n");
3511 		return -EINVAL;
3512 	}
3513 	if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3514 		CH_ERR(adap,
3515 			"FW image size differs from size in FW header\n");
3516 		return -EINVAL;
3517 	}
3518 	if (size > fw_size) {
3519 		CH_ERR(adap, "FW image too large, max is %u bytes\n",
3520 			fw_size);
3521 		return -EFBIG;
3522 	}
3523 	if (!t4_fw_matches_chip(adap, hdr))
3524 		return -EINVAL;
3525 
3526 	for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3527 		csum += be32_to_cpu(p[i]);
3528 
3529 	if (csum != 0xffffffff) {
3530 		CH_ERR(adap,
3531 			"corrupted firmware image, checksum %#x\n", csum);
3532 		return -EINVAL;
3533 	}
3534 
3535 	i = DIV_ROUND_UP(size, sf_sec_size);	/* # of sectors spanned */
3536 	ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3537 	if (ret)
3538 		goto out;
3539 
3540 	/*
3541 	 * We write the correct version at the end so the driver can see a bad
3542 	 * version if the FW write fails.  Start by writing a copy of the
3543 	 * first page with a bad version.
3544 	 */
3545 	memcpy(first_page, fw_data, SF_PAGE_SIZE);
3546 	((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3547 	ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3548 	if (ret)
3549 		goto out;
3550 
3551 	addr = fw_start;
3552 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3553 		addr += SF_PAGE_SIZE;
3554 		fw_data += SF_PAGE_SIZE;
3555 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3556 		if (ret)
3557 			goto out;
3558 	}
3559 
3560 	ret = t4_write_flash(adap,
3561 			     fw_start + offsetof(struct fw_hdr, fw_ver),
3562 			     sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3563 out:
3564 	if (ret)
3565 		CH_ERR(adap, "firmware download failed, error %d\n",
3566 			ret);
3567 	return ret;
3568 }
3569 
3570 /**
3571  *	t4_fwcache - firmware cache operation
3572  *	@adap: the adapter
3573  *	@op  : the operation (flush or flush and invalidate)
3574  */
3575 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3576 {
3577 	struct fw_params_cmd c;
3578 
3579 	memset(&c, 0, sizeof(c));
3580 	c.op_to_vfn =
3581 	    cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3582 			    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3583 				V_FW_PARAMS_CMD_PFN(adap->pf) |
3584 				V_FW_PARAMS_CMD_VFN(0));
3585 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3586 	c.param[0].mnem =
3587 	    cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3588 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3589 	c.param[0].val = (__force __be32)op;
3590 
3591 	return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3592 }
3593 
3594 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3595 			unsigned int *pif_req_wrptr,
3596 			unsigned int *pif_rsp_wrptr)
3597 {
3598 	int i, j;
3599 	u32 cfg, val, req, rsp;
3600 
3601 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3602 	if (cfg & F_LADBGEN)
3603 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3604 
3605 	val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3606 	req = G_POLADBGWRPTR(val);
3607 	rsp = G_PILADBGWRPTR(val);
3608 	if (pif_req_wrptr)
3609 		*pif_req_wrptr = req;
3610 	if (pif_rsp_wrptr)
3611 		*pif_rsp_wrptr = rsp;
3612 
3613 	for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3614 		for (j = 0; j < 6; j++) {
3615 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3616 				     V_PILADBGRDPTR(rsp));
3617 			*pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3618 			*pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3619 			req++;
3620 			rsp++;
3621 		}
3622 		req = (req + 2) & M_POLADBGRDPTR;
3623 		rsp = (rsp + 2) & M_PILADBGRDPTR;
3624 	}
3625 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3626 }
3627 
3628 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3629 {
3630 	u32 cfg;
3631 	int i, j, idx;
3632 
3633 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3634 	if (cfg & F_LADBGEN)
3635 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3636 
3637 	for (i = 0; i < CIM_MALA_SIZE; i++) {
3638 		for (j = 0; j < 5; j++) {
3639 			idx = 8 * i + j;
3640 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3641 				     V_PILADBGRDPTR(idx));
3642 			*ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3643 			*ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3644 		}
3645 	}
3646 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3647 }
3648 
3649 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3650 {
3651 	unsigned int i, j;
3652 
3653 	for (i = 0; i < 8; i++) {
3654 		u32 *p = la_buf + i;
3655 
3656 		t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3657 		j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3658 		t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3659 		for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3660 			*p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3661 	}
3662 }
3663 
3664 /**
3665  *	t4_link_l1cfg - apply link configuration to MAC/PHY
3666  *	@phy: the PHY to setup
3667  *	@mac: the MAC to setup
3668  *	@lc: the requested link configuration
3669  *
3670  *	Set up a port's MAC and PHY according to a desired link configuration.
3671  *	- If the PHY can auto-negotiate first decide what to advertise, then
3672  *	  enable/disable auto-negotiation as desired, and reset.
3673  *	- If the PHY does not auto-negotiate just reset it.
3674  *	- If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3675  *	  otherwise do it later based on the outcome of auto-negotiation.
3676  */
3677 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3678 		  struct link_config *lc)
3679 {
3680 	struct fw_port_cmd c;
3681 	unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
3682 	unsigned int aneg, fc, fec, speed;
3683 
3684 	fc = 0;
3685 	if (lc->requested_fc & PAUSE_RX)
3686 		fc |= FW_PORT_CAP_FC_RX;
3687 	if (lc->requested_fc & PAUSE_TX)
3688 		fc |= FW_PORT_CAP_FC_TX;
3689 
3690 	fec = 0;
3691 	if (lc->requested_fec & FEC_RS)
3692 		fec = FW_PORT_CAP_FEC_RS;
3693 	else if (lc->requested_fec & FEC_BASER_RS)
3694 		fec = FW_PORT_CAP_FEC_BASER_RS;
3695 	else if (lc->requested_fec & FEC_RESERVED)
3696 		fec = FW_PORT_CAP_FEC_RESERVED;
3697 
3698 	if (!(lc->supported & FW_PORT_CAP_ANEG) ||
3699 	    lc->requested_aneg == AUTONEG_DISABLE) {
3700 		aneg = 0;
3701 		switch (lc->requested_speed) {
3702 		case 100:
3703 			speed = FW_PORT_CAP_SPEED_100G;
3704 			break;
3705 		case 40:
3706 			speed = FW_PORT_CAP_SPEED_40G;
3707 			break;
3708 		case 25:
3709 			speed = FW_PORT_CAP_SPEED_25G;
3710 			break;
3711 		case 10:
3712 			speed = FW_PORT_CAP_SPEED_10G;
3713 			break;
3714 		case 1:
3715 			speed = FW_PORT_CAP_SPEED_1G;
3716 			break;
3717 		default:
3718 			return -EINVAL;
3719 			break;
3720 		}
3721 	} else {
3722 		aneg = FW_PORT_CAP_ANEG;
3723 		speed = lc->supported &
3724 		    V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED);
3725 	}
3726 
3727 	memset(&c, 0, sizeof(c));
3728 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3729 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3730 				     V_FW_PORT_CMD_PORTID(port));
3731 	c.action_to_len16 =
3732 		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3733 			    FW_LEN16(c));
3734 	c.u.l1cfg.rcap = cpu_to_be32(aneg | speed | fc | fec | mdi);
3735 
3736 	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
3737 }
3738 
3739 /**
3740  *	t4_restart_aneg - restart autonegotiation
3741  *	@adap: the adapter
3742  *	@mbox: mbox to use for the FW command
3743  *	@port: the port id
3744  *
3745  *	Restarts autonegotiation for the selected port.
3746  */
3747 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3748 {
3749 	struct fw_port_cmd c;
3750 
3751 	memset(&c, 0, sizeof(c));
3752 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3753 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3754 				     V_FW_PORT_CMD_PORTID(port));
3755 	c.action_to_len16 =
3756 		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3757 			    FW_LEN16(c));
3758 	c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3759 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3760 }
3761 
3762 typedef void (*int_handler_t)(struct adapter *adap);
3763 
3764 struct intr_info {
3765 	unsigned int mask;	/* bits to check in interrupt status */
3766 	const char *msg;	/* message to print or NULL */
3767 	short stat_idx;		/* stat counter to increment or -1 */
3768 	unsigned short fatal;	/* whether the condition reported is fatal */
3769 	int_handler_t int_handler;	/* platform-specific int handler */
3770 };
3771 
3772 /**
3773  *	t4_handle_intr_status - table driven interrupt handler
3774  *	@adapter: the adapter that generated the interrupt
3775  *	@reg: the interrupt status register to process
3776  *	@acts: table of interrupt actions
3777  *
3778  *	A table driven interrupt handler that applies a set of masks to an
3779  *	interrupt status word and performs the corresponding actions if the
3780  *	interrupts described by the mask have occurred.  The actions include
3781  *	optionally emitting a warning or alert message.  The table is terminated
3782  *	by an entry specifying mask 0.  Returns the number of fatal interrupt
3783  *	conditions.
3784  */
3785 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3786 				 const struct intr_info *acts)
3787 {
3788 	int fatal = 0;
3789 	unsigned int mask = 0;
3790 	unsigned int status = t4_read_reg(adapter, reg);
3791 
3792 	for ( ; acts->mask; ++acts) {
3793 		if (!(status & acts->mask))
3794 			continue;
3795 		if (acts->fatal) {
3796 			fatal++;
3797 			CH_ALERT(adapter, "%s (0x%x)\n", acts->msg,
3798 				  status & acts->mask);
3799 		} else if (acts->msg)
3800 			CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg,
3801 				 status & acts->mask);
3802 		if (acts->int_handler)
3803 			acts->int_handler(adapter);
3804 		mask |= acts->mask;
3805 	}
3806 	status &= mask;
3807 	if (status)	/* clear processed interrupts */
3808 		t4_write_reg(adapter, reg, status);
3809 	return fatal;
3810 }
3811 
3812 /*
3813  * Interrupt handler for the PCIE module.
3814  */
3815 static void pcie_intr_handler(struct adapter *adapter)
3816 {
3817 	static const struct intr_info sysbus_intr_info[] = {
3818 		{ F_RNPP, "RXNP array parity error", -1, 1 },
3819 		{ F_RPCP, "RXPC array parity error", -1, 1 },
3820 		{ F_RCIP, "RXCIF array parity error", -1, 1 },
3821 		{ F_RCCP, "Rx completions control array parity error", -1, 1 },
3822 		{ F_RFTP, "RXFT array parity error", -1, 1 },
3823 		{ 0 }
3824 	};
3825 	static const struct intr_info pcie_port_intr_info[] = {
3826 		{ F_TPCP, "TXPC array parity error", -1, 1 },
3827 		{ F_TNPP, "TXNP array parity error", -1, 1 },
3828 		{ F_TFTP, "TXFT array parity error", -1, 1 },
3829 		{ F_TCAP, "TXCA array parity error", -1, 1 },
3830 		{ F_TCIP, "TXCIF array parity error", -1, 1 },
3831 		{ F_RCAP, "RXCA array parity error", -1, 1 },
3832 		{ F_OTDD, "outbound request TLP discarded", -1, 1 },
3833 		{ F_RDPE, "Rx data parity error", -1, 1 },
3834 		{ F_TDUE, "Tx uncorrectable data error", -1, 1 },
3835 		{ 0 }
3836 	};
3837 	static const struct intr_info pcie_intr_info[] = {
3838 		{ F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
3839 		{ F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
3840 		{ F_MSIDATAPERR, "MSI data parity error", -1, 1 },
3841 		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3842 		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3843 		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3844 		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3845 		{ F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
3846 		{ F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
3847 		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3848 		{ F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
3849 		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3850 		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3851 		{ F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
3852 		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3853 		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3854 		{ F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
3855 		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3856 		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3857 		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3858 		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
3859 		{ F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
3860 		{ F_MATAGPERR, "PCI MA tag parity error", -1, 1 },
3861 		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3862 		{ F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
3863 		{ F_RXWRPERR, "PCI Rx write parity error", -1, 1 },
3864 		{ F_RPLPERR, "PCI replay buffer parity error", -1, 1 },
3865 		{ F_PCIESINT, "PCI core secondary fault", -1, 1 },
3866 		{ F_PCIEPINT, "PCI core primary fault", -1, 1 },
3867 		{ F_UNXSPLCPLERR, "PCI unexpected split completion error", -1,
3868 		  0 },
3869 		{ 0 }
3870 	};
3871 
3872 	static const struct intr_info t5_pcie_intr_info[] = {
3873 		{ F_MSTGRPPERR, "Master Response Read Queue parity error",
3874 		  -1, 1 },
3875 		{ F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
3876 		{ F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
3877 		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3878 		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3879 		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3880 		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3881 		{ F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
3882 		  -1, 1 },
3883 		{ F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
3884 		  -1, 1 },
3885 		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3886 		{ F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
3887 		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3888 		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3889 		{ F_DREQWRPERR, "PCI DMA channel write request parity error",
3890 		  -1, 1 },
3891 		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3892 		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3893 		{ F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
3894 		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3895 		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3896 		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3897 		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
3898 		{ F_VFIDPERR, "PCI INTx clear parity error", -1, 1 },
3899 		{ F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
3900 		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3901 		{ F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
3902 		  -1, 1 },
3903 		{ F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
3904 		  -1, 1 },
3905 		{ F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
3906 		{ F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
3907 		{ F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3908 		{ F_READRSPERR, "Outbound read error", -1,
3909 		  0 },
3910 		{ 0 }
3911 	};
3912 
3913 	int fat;
3914 
3915 	if (is_t4(adapter))
3916 		fat = t4_handle_intr_status(adapter,
3917 				A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
3918 				sysbus_intr_info) +
3919 			t4_handle_intr_status(adapter,
3920 					A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
3921 					pcie_port_intr_info) +
3922 			t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3923 					      pcie_intr_info);
3924 	else
3925 		fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3926 					    t5_pcie_intr_info);
3927 	if (fat)
3928 		t4_fatal_err(adapter);
3929 }
3930 
3931 /*
3932  * TP interrupt handler.
3933  */
3934 static void tp_intr_handler(struct adapter *adapter)
3935 {
3936 	static const struct intr_info tp_intr_info[] = {
3937 		{ 0x3fffffff, "TP parity error", -1, 1 },
3938 		{ F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
3939 		{ 0 }
3940 	};
3941 
3942 	if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info))
3943 		t4_fatal_err(adapter);
3944 }
3945 
3946 /*
3947  * SGE interrupt handler.
3948  */
3949 static void sge_intr_handler(struct adapter *adapter)
3950 {
3951 	u64 v;
3952 	u32 err;
3953 
3954 	static const struct intr_info sge_intr_info[] = {
3955 		{ F_ERR_CPL_EXCEED_IQE_SIZE,
3956 		  "SGE received CPL exceeding IQE size", -1, 1 },
3957 		{ F_ERR_INVALID_CIDX_INC,
3958 		  "SGE GTS CIDX increment too large", -1, 0 },
3959 		{ F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
3960 		{ F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
3961 		{ F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
3962 		  "SGE IQID > 1023 received CPL for FL", -1, 0 },
3963 		{ F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
3964 		  0 },
3965 		{ F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
3966 		  0 },
3967 		{ F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
3968 		  0 },
3969 		{ F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
3970 		  0 },
3971 		{ F_ERR_ING_CTXT_PRIO,
3972 		  "SGE too many priority ingress contexts", -1, 0 },
3973 		{ F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
3974 		{ F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
3975 		{ F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 |
3976 		  F_ERR_PCIE_ERROR2 | F_ERR_PCIE_ERROR3,
3977 		  "SGE PCIe error for a DBP thread", -1, 0 },
3978 		{ 0 }
3979 	};
3980 
3981 	static const struct intr_info t4t5_sge_intr_info[] = {
3982 		{ F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
3983 		{ F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
3984 		{ F_ERR_EGR_CTXT_PRIO,
3985 		  "SGE too many priority egress contexts", -1, 0 },
3986 		{ 0 }
3987 	};
3988 
3989 	/*
3990  	* For now, treat below interrupts as fatal so that we disable SGE and
3991  	* get better debug */
3992 	static const struct intr_info t6_sge_intr_info[] = {
3993 		{ F_FATAL_WRE_LEN,
3994 		  "SGE Actual WRE packet is less than advertized length",
3995 		  -1, 1 },
3996 		{ 0 }
3997 	};
3998 
3999 	v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) |
4000 		((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32);
4001 	if (v) {
4002 		CH_ALERT(adapter, "SGE parity error (%#llx)\n",
4003 				(unsigned long long)v);
4004 		t4_write_reg(adapter, A_SGE_INT_CAUSE1, v);
4005 		t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32);
4006 	}
4007 
4008 	v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info);
4009 	if (chip_id(adapter) <= CHELSIO_T5)
4010 		v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
4011 					   t4t5_sge_intr_info);
4012 	else
4013 		v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
4014 					   t6_sge_intr_info);
4015 
4016 	err = t4_read_reg(adapter, A_SGE_ERROR_STATS);
4017 	if (err & F_ERROR_QID_VALID) {
4018 		CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err));
4019 		if (err & F_UNCAPTURED_ERROR)
4020 			CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n");
4021 		t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID |
4022 			     F_UNCAPTURED_ERROR);
4023 	}
4024 
4025 	if (v != 0)
4026 		t4_fatal_err(adapter);
4027 }
4028 
4029 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\
4030 		      F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR)
4031 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\
4032 		      F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR)
4033 
4034 /*
4035  * CIM interrupt handler.
4036  */
4037 static void cim_intr_handler(struct adapter *adapter)
4038 {
4039 	static const struct intr_info cim_intr_info[] = {
4040 		{ F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
4041 		{ CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4042 		{ CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4043 		{ F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
4044 		{ F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
4045 		{ F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
4046 		{ F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
4047 		{ F_TIMER0INT, "CIM TIMER0 interrupt", -1, 1 },
4048 		{ 0 }
4049 	};
4050 	static const struct intr_info cim_upintr_info[] = {
4051 		{ F_RSVDSPACEINT, "CIM reserved space access", -1, 1 },
4052 		{ F_ILLTRANSINT, "CIM illegal transaction", -1, 1 },
4053 		{ F_ILLWRINT, "CIM illegal write", -1, 1 },
4054 		{ F_ILLRDINT, "CIM illegal read", -1, 1 },
4055 		{ F_ILLRDBEINT, "CIM illegal read BE", -1, 1 },
4056 		{ F_ILLWRBEINT, "CIM illegal write BE", -1, 1 },
4057 		{ F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
4058 		{ F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
4059 		{ F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
4060 		{ F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
4061 		{ F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
4062 		{ F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
4063 		{ F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
4064 		{ F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
4065 		{ F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
4066 		{ F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
4067 		{ F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
4068 		{ F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
4069 		{ F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
4070 		{ F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
4071 		{ F_SGLRDPLINT , "CIM single read from PL space", -1, 1 },
4072 		{ F_SGLWRPLINT , "CIM single write to PL space", -1, 1 },
4073 		{ F_BLKRDPLINT , "CIM block read from PL space", -1, 1 },
4074 		{ F_BLKWRPLINT , "CIM block write to PL space", -1, 1 },
4075 		{ F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
4076 		{ F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
4077 		{ F_TIMEOUTINT , "CIM PIF timeout", -1, 1 },
4078 		{ F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
4079 		{ 0 }
4080 	};
4081 	u32 val, fw_err;
4082 	int fat;
4083 
4084 	fw_err = t4_read_reg(adapter, A_PCIE_FW);
4085 	if (fw_err & F_PCIE_FW_ERR)
4086 		t4_report_fw_error(adapter);
4087 
4088 	/* When the Firmware detects an internal error which normally wouldn't
4089 	 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
4090 	 * to make sure the Host sees the Firmware Crash.  So if we have a
4091 	 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
4092 	 * interrupt.
4093 	 */
4094 	val = t4_read_reg(adapter, A_CIM_HOST_INT_CAUSE);
4095 	if (val & F_TIMER0INT)
4096 		if (!(fw_err & F_PCIE_FW_ERR) ||
4097 		    (G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH))
4098 			t4_write_reg(adapter, A_CIM_HOST_INT_CAUSE,
4099 				     F_TIMER0INT);
4100 
4101 	fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE,
4102 				    cim_intr_info) +
4103 	      t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE,
4104 				    cim_upintr_info);
4105 	if (fat)
4106 		t4_fatal_err(adapter);
4107 }
4108 
4109 /*
4110  * ULP RX interrupt handler.
4111  */
4112 static void ulprx_intr_handler(struct adapter *adapter)
4113 {
4114 	static const struct intr_info ulprx_intr_info[] = {
4115 		{ F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 },
4116 		{ F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 },
4117 		{ 0x7fffff, "ULPRX parity error", -1, 1 },
4118 		{ 0 }
4119 	};
4120 
4121 	if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info))
4122 		t4_fatal_err(adapter);
4123 }
4124 
4125 /*
4126  * ULP TX interrupt handler.
4127  */
4128 static void ulptx_intr_handler(struct adapter *adapter)
4129 {
4130 	static const struct intr_info ulptx_intr_info[] = {
4131 		{ F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
4132 		  0 },
4133 		{ F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
4134 		  0 },
4135 		{ F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
4136 		  0 },
4137 		{ F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
4138 		  0 },
4139 		{ 0xfffffff, "ULPTX parity error", -1, 1 },
4140 		{ 0 }
4141 	};
4142 
4143 	if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info))
4144 		t4_fatal_err(adapter);
4145 }
4146 
4147 /*
4148  * PM TX interrupt handler.
4149  */
4150 static void pmtx_intr_handler(struct adapter *adapter)
4151 {
4152 	static const struct intr_info pmtx_intr_info[] = {
4153 		{ F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
4154 		{ F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
4155 		{ F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
4156 		{ F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
4157 		{ 0xffffff0, "PMTX framing error", -1, 1 },
4158 		{ F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
4159 		{ F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1,
4160 		  1 },
4161 		{ F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
4162 		{ F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
4163 		{ 0 }
4164 	};
4165 
4166 	if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info))
4167 		t4_fatal_err(adapter);
4168 }
4169 
4170 /*
4171  * PM RX interrupt handler.
4172  */
4173 static void pmrx_intr_handler(struct adapter *adapter)
4174 {
4175 	static const struct intr_info pmrx_intr_info[] = {
4176 		{ F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
4177 		{ 0x3ffff0, "PMRX framing error", -1, 1 },
4178 		{ F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
4179 		{ F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1,
4180 		  1 },
4181 		{ F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
4182 		{ F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
4183 		{ 0 }
4184 	};
4185 
4186 	if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info))
4187 		t4_fatal_err(adapter);
4188 }
4189 
4190 /*
4191  * CPL switch interrupt handler.
4192  */
4193 static void cplsw_intr_handler(struct adapter *adapter)
4194 {
4195 	static const struct intr_info cplsw_intr_info[] = {
4196 		{ F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
4197 		{ F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
4198 		{ F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
4199 		{ F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
4200 		{ F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
4201 		{ F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
4202 		{ 0 }
4203 	};
4204 
4205 	if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info))
4206 		t4_fatal_err(adapter);
4207 }
4208 
4209 /*
4210  * LE interrupt handler.
4211  */
4212 static void le_intr_handler(struct adapter *adap)
4213 {
4214 	unsigned int chip_ver = chip_id(adap);
4215 	static const struct intr_info le_intr_info[] = {
4216 		{ F_LIPMISS, "LE LIP miss", -1, 0 },
4217 		{ F_LIP0, "LE 0 LIP error", -1, 0 },
4218 		{ F_PARITYERR, "LE parity error", -1, 1 },
4219 		{ F_UNKNOWNCMD, "LE unknown command", -1, 1 },
4220 		{ F_REQQPARERR, "LE request queue parity error", -1, 1 },
4221 		{ 0 }
4222 	};
4223 
4224 	static const struct intr_info t6_le_intr_info[] = {
4225 		{ F_T6_LIPMISS, "LE LIP miss", -1, 0 },
4226 		{ F_T6_LIP0, "LE 0 LIP error", -1, 0 },
4227 		{ F_TCAMINTPERR, "LE parity error", -1, 1 },
4228 		{ F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 },
4229 		{ F_SSRAMINTPERR, "LE request queue parity error", -1, 1 },
4230 		{ 0 }
4231 	};
4232 
4233 	if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE,
4234 				  (chip_ver <= CHELSIO_T5) ?
4235 				  le_intr_info : t6_le_intr_info))
4236 		t4_fatal_err(adap);
4237 }
4238 
4239 /*
4240  * MPS interrupt handler.
4241  */
4242 static void mps_intr_handler(struct adapter *adapter)
4243 {
4244 	static const struct intr_info mps_rx_intr_info[] = {
4245 		{ 0xffffff, "MPS Rx parity error", -1, 1 },
4246 		{ 0 }
4247 	};
4248 	static const struct intr_info mps_tx_intr_info[] = {
4249 		{ V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 },
4250 		{ F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4251 		{ V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error",
4252 		  -1, 1 },
4253 		{ V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error",
4254 		  -1, 1 },
4255 		{ F_BUBBLE, "MPS Tx underflow", -1, 1 },
4256 		{ F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
4257 		{ F_FRMERR, "MPS Tx framing error", -1, 1 },
4258 		{ 0 }
4259 	};
4260 	static const struct intr_info mps_trc_intr_info[] = {
4261 		{ V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 },
4262 		{ V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1,
4263 		  1 },
4264 		{ F_MISCPERR, "MPS TRC misc parity error", -1, 1 },
4265 		{ 0 }
4266 	};
4267 	static const struct intr_info mps_stat_sram_intr_info[] = {
4268 		{ 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4269 		{ 0 }
4270 	};
4271 	static const struct intr_info mps_stat_tx_intr_info[] = {
4272 		{ 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4273 		{ 0 }
4274 	};
4275 	static const struct intr_info mps_stat_rx_intr_info[] = {
4276 		{ 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4277 		{ 0 }
4278 	};
4279 	static const struct intr_info mps_cls_intr_info[] = {
4280 		{ F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
4281 		{ F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
4282 		{ F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
4283 		{ 0 }
4284 	};
4285 
4286 	int fat;
4287 
4288 	fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE,
4289 				    mps_rx_intr_info) +
4290 	      t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE,
4291 				    mps_tx_intr_info) +
4292 	      t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE,
4293 				    mps_trc_intr_info) +
4294 	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4295 				    mps_stat_sram_intr_info) +
4296 	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4297 				    mps_stat_tx_intr_info) +
4298 	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4299 				    mps_stat_rx_intr_info) +
4300 	      t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE,
4301 				    mps_cls_intr_info);
4302 
4303 	t4_write_reg(adapter, A_MPS_INT_CAUSE, 0);
4304 	t4_read_reg(adapter, A_MPS_INT_CAUSE);	/* flush */
4305 	if (fat)
4306 		t4_fatal_err(adapter);
4307 }
4308 
4309 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \
4310 		      F_ECC_UE_INT_CAUSE)
4311 
4312 /*
4313  * EDC/MC interrupt handler.
4314  */
4315 static void mem_intr_handler(struct adapter *adapter, int idx)
4316 {
4317 	static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4318 
4319 	unsigned int addr, cnt_addr, v;
4320 
4321 	if (idx <= MEM_EDC1) {
4322 		addr = EDC_REG(A_EDC_INT_CAUSE, idx);
4323 		cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx);
4324 	} else if (idx == MEM_MC) {
4325 		if (is_t4(adapter)) {
4326 			addr = A_MC_INT_CAUSE;
4327 			cnt_addr = A_MC_ECC_STATUS;
4328 		} else {
4329 			addr = A_MC_P_INT_CAUSE;
4330 			cnt_addr = A_MC_P_ECC_STATUS;
4331 		}
4332 	} else {
4333 		addr = MC_REG(A_MC_P_INT_CAUSE, 1);
4334 		cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1);
4335 	}
4336 
4337 	v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4338 	if (v & F_PERR_INT_CAUSE)
4339 		CH_ALERT(adapter, "%s FIFO parity error\n",
4340 			  name[idx]);
4341 	if (v & F_ECC_CE_INT_CAUSE) {
4342 		u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr));
4343 
4344 		if (idx <= MEM_EDC1)
4345 			t4_edc_err_read(adapter, idx);
4346 
4347 		t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT));
4348 		CH_WARN_RATELIMIT(adapter,
4349 				  "%u %s correctable ECC data error%s\n",
4350 				  cnt, name[idx], cnt > 1 ? "s" : "");
4351 	}
4352 	if (v & F_ECC_UE_INT_CAUSE)
4353 		CH_ALERT(adapter,
4354 			 "%s uncorrectable ECC data error\n", name[idx]);
4355 
4356 	t4_write_reg(adapter, addr, v);
4357 	if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE))
4358 		t4_fatal_err(adapter);
4359 }
4360 
4361 /*
4362  * MA interrupt handler.
4363  */
4364 static void ma_intr_handler(struct adapter *adapter)
4365 {
4366 	u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE);
4367 
4368 	if (status & F_MEM_PERR_INT_CAUSE) {
4369 		CH_ALERT(adapter,
4370 			  "MA parity error, parity status %#x\n",
4371 			  t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1));
4372 		if (is_t5(adapter))
4373 			CH_ALERT(adapter,
4374 				  "MA parity error, parity status %#x\n",
4375 				  t4_read_reg(adapter,
4376 					      A_MA_PARITY_ERROR_STATUS2));
4377 	}
4378 	if (status & F_MEM_WRAP_INT_CAUSE) {
4379 		v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS);
4380 		CH_ALERT(adapter, "MA address wrap-around error by "
4381 			  "client %u to address %#x\n",
4382 			  G_MEM_WRAP_CLIENT_NUM(v),
4383 			  G_MEM_WRAP_ADDRESS(v) << 4);
4384 	}
4385 	t4_write_reg(adapter, A_MA_INT_CAUSE, status);
4386 	t4_fatal_err(adapter);
4387 }
4388 
4389 /*
4390  * SMB interrupt handler.
4391  */
4392 static void smb_intr_handler(struct adapter *adap)
4393 {
4394 	static const struct intr_info smb_intr_info[] = {
4395 		{ F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
4396 		{ F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
4397 		{ F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
4398 		{ 0 }
4399 	};
4400 
4401 	if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info))
4402 		t4_fatal_err(adap);
4403 }
4404 
4405 /*
4406  * NC-SI interrupt handler.
4407  */
4408 static void ncsi_intr_handler(struct adapter *adap)
4409 {
4410 	static const struct intr_info ncsi_intr_info[] = {
4411 		{ F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
4412 		{ F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
4413 		{ F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
4414 		{ F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
4415 		{ 0 }
4416 	};
4417 
4418 	if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info))
4419 		t4_fatal_err(adap);
4420 }
4421 
4422 /*
4423  * XGMAC interrupt handler.
4424  */
4425 static void xgmac_intr_handler(struct adapter *adap, int port)
4426 {
4427 	u32 v, int_cause_reg;
4428 
4429 	if (is_t4(adap))
4430 		int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
4431 	else
4432 		int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
4433 
4434 	v = t4_read_reg(adap, int_cause_reg);
4435 
4436 	v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR);
4437 	if (!v)
4438 		return;
4439 
4440 	if (v & F_TXFIFO_PRTY_ERR)
4441 		CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n",
4442 			  port);
4443 	if (v & F_RXFIFO_PRTY_ERR)
4444 		CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n",
4445 			  port);
4446 	t4_write_reg(adap, int_cause_reg, v);
4447 	t4_fatal_err(adap);
4448 }
4449 
4450 /*
4451  * PL interrupt handler.
4452  */
4453 static void pl_intr_handler(struct adapter *adap)
4454 {
4455 	static const struct intr_info pl_intr_info[] = {
4456 		{ F_FATALPERR, "Fatal parity error", -1, 1 },
4457 		{ F_PERRVFID, "PL VFID_MAP parity error", -1, 1 },
4458 		{ 0 }
4459 	};
4460 
4461 	static const struct intr_info t5_pl_intr_info[] = {
4462 		{ F_FATALPERR, "Fatal parity error", -1, 1 },
4463 		{ 0 }
4464 	};
4465 
4466 	if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE,
4467 				  is_t4(adap) ?
4468 				  pl_intr_info : t5_pl_intr_info))
4469 		t4_fatal_err(adap);
4470 }
4471 
4472 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
4473 
4474 /**
4475  *	t4_slow_intr_handler - control path interrupt handler
4476  *	@adapter: the adapter
4477  *
4478  *	T4 interrupt handler for non-data global interrupt events, e.g., errors.
4479  *	The designation 'slow' is because it involves register reads, while
4480  *	data interrupts typically don't involve any MMIOs.
4481  */
4482 int t4_slow_intr_handler(struct adapter *adapter)
4483 {
4484 	u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
4485 
4486 	if (!(cause & GLBL_INTR_MASK))
4487 		return 0;
4488 	if (cause & F_CIM)
4489 		cim_intr_handler(adapter);
4490 	if (cause & F_MPS)
4491 		mps_intr_handler(adapter);
4492 	if (cause & F_NCSI)
4493 		ncsi_intr_handler(adapter);
4494 	if (cause & F_PL)
4495 		pl_intr_handler(adapter);
4496 	if (cause & F_SMB)
4497 		smb_intr_handler(adapter);
4498 	if (cause & F_MAC0)
4499 		xgmac_intr_handler(adapter, 0);
4500 	if (cause & F_MAC1)
4501 		xgmac_intr_handler(adapter, 1);
4502 	if (cause & F_MAC2)
4503 		xgmac_intr_handler(adapter, 2);
4504 	if (cause & F_MAC3)
4505 		xgmac_intr_handler(adapter, 3);
4506 	if (cause & F_PCIE)
4507 		pcie_intr_handler(adapter);
4508 	if (cause & F_MC0)
4509 		mem_intr_handler(adapter, MEM_MC);
4510 	if (is_t5(adapter) && (cause & F_MC1))
4511 		mem_intr_handler(adapter, MEM_MC1);
4512 	if (cause & F_EDC0)
4513 		mem_intr_handler(adapter, MEM_EDC0);
4514 	if (cause & F_EDC1)
4515 		mem_intr_handler(adapter, MEM_EDC1);
4516 	if (cause & F_LE)
4517 		le_intr_handler(adapter);
4518 	if (cause & F_TP)
4519 		tp_intr_handler(adapter);
4520 	if (cause & F_MA)
4521 		ma_intr_handler(adapter);
4522 	if (cause & F_PM_TX)
4523 		pmtx_intr_handler(adapter);
4524 	if (cause & F_PM_RX)
4525 		pmrx_intr_handler(adapter);
4526 	if (cause & F_ULP_RX)
4527 		ulprx_intr_handler(adapter);
4528 	if (cause & F_CPL_SWITCH)
4529 		cplsw_intr_handler(adapter);
4530 	if (cause & F_SGE)
4531 		sge_intr_handler(adapter);
4532 	if (cause & F_ULP_TX)
4533 		ulptx_intr_handler(adapter);
4534 
4535 	/* Clear the interrupts just processed for which we are the master. */
4536 	t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK);
4537 	(void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */
4538 	return 1;
4539 }
4540 
4541 /**
4542  *	t4_intr_enable - enable interrupts
4543  *	@adapter: the adapter whose interrupts should be enabled
4544  *
4545  *	Enable PF-specific interrupts for the calling function and the top-level
4546  *	interrupt concentrator for global interrupts.  Interrupts are already
4547  *	enabled at each module,	here we just enable the roots of the interrupt
4548  *	hierarchies.
4549  *
4550  *	Note: this function should be called only when the driver manages
4551  *	non PF-specific interrupts from the various HW modules.  Only one PCI
4552  *	function at a time should be doing this.
4553  */
4554 void t4_intr_enable(struct adapter *adapter)
4555 {
4556 	u32 val = 0;
4557 	u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4558 	u32 pf = (chip_id(adapter) <= CHELSIO_T5
4559 		  ? G_SOURCEPF(whoami)
4560 		  : G_T6_SOURCEPF(whoami));
4561 
4562 	if (chip_id(adapter) <= CHELSIO_T5)
4563 		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
4564 	else
4565 		val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
4566 	t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
4567 		     F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
4568 		     F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
4569 		     F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
4570 		     F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4571 		     F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
4572 		     F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
4573 	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
4574 	t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
4575 }
4576 
4577 /**
4578  *	t4_intr_disable - disable interrupts
4579  *	@adapter: the adapter whose interrupts should be disabled
4580  *
4581  *	Disable interrupts.  We only disable the top-level interrupt
4582  *	concentrators.  The caller must be a PCI function managing global
4583  *	interrupts.
4584  */
4585 void t4_intr_disable(struct adapter *adapter)
4586 {
4587 	u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4588 	u32 pf = (chip_id(adapter) <= CHELSIO_T5
4589 		  ? G_SOURCEPF(whoami)
4590 		  : G_T6_SOURCEPF(whoami));
4591 
4592 	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
4593 	t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
4594 }
4595 
4596 /**
4597  *	t4_intr_clear - clear all interrupts
4598  *	@adapter: the adapter whose interrupts should be cleared
4599  *
4600  *	Clears all interrupts.  The caller must be a PCI function managing
4601  *	global interrupts.
4602  */
4603 void t4_intr_clear(struct adapter *adapter)
4604 {
4605 	static const unsigned int cause_reg[] = {
4606 		A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3,
4607 		A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE,
4608 		A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE,
4609 		A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1),
4610 		A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE,
4611 		MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4612 		A_TP_INT_CAUSE,
4613 		A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE,
4614 		A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE,
4615 		A_MPS_RX_PERR_INT_CAUSE,
4616 		A_CPL_INTR_CAUSE,
4617 		MYPF_REG(A_PL_PF_INT_CAUSE),
4618 		A_PL_PL_INT_CAUSE,
4619 		A_LE_DB_INT_CAUSE,
4620 	};
4621 
4622 	unsigned int i;
4623 
4624 	for (i = 0; i < ARRAY_SIZE(cause_reg); ++i)
4625 		t4_write_reg(adapter, cause_reg[i], 0xffffffff);
4626 
4627 	t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE :
4628 				A_MC_P_INT_CAUSE, 0xffffffff);
4629 
4630 	if (is_t4(adapter)) {
4631 		t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4632 				0xffffffff);
4633 		t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4634 				0xffffffff);
4635 	} else
4636 		t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
4637 
4638 	t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK);
4639 	(void) t4_read_reg(adapter, A_PL_INT_CAUSE);          /* flush */
4640 }
4641 
4642 /**
4643  *	hash_mac_addr - return the hash value of a MAC address
4644  *	@addr: the 48-bit Ethernet MAC address
4645  *
4646  *	Hashes a MAC address according to the hash function used by HW inexact
4647  *	(hash) address matching.
4648  */
4649 static int hash_mac_addr(const u8 *addr)
4650 {
4651 	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
4652 	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
4653 	a ^= b;
4654 	a ^= (a >> 12);
4655 	a ^= (a >> 6);
4656 	return a & 0x3f;
4657 }
4658 
4659 /**
4660  *	t4_config_rss_range - configure a portion of the RSS mapping table
4661  *	@adapter: the adapter
4662  *	@mbox: mbox to use for the FW command
4663  *	@viid: virtual interface whose RSS subtable is to be written
4664  *	@start: start entry in the table to write
4665  *	@n: how many table entries to write
4666  *	@rspq: values for the "response queue" (Ingress Queue) lookup table
4667  *	@nrspq: number of values in @rspq
4668  *
4669  *	Programs the selected part of the VI's RSS mapping table with the
4670  *	provided values.  If @nrspq < @n the supplied values are used repeatedly
4671  *	until the full table range is populated.
4672  *
4673  *	The caller must ensure the values in @rspq are in the range allowed for
4674  *	@viid.
4675  */
4676 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4677 			int start, int n, const u16 *rspq, unsigned int nrspq)
4678 {
4679 	int ret;
4680 	const u16 *rsp = rspq;
4681 	const u16 *rsp_end = rspq + nrspq;
4682 	struct fw_rss_ind_tbl_cmd cmd;
4683 
4684 	memset(&cmd, 0, sizeof(cmd));
4685 	cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
4686 				     F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4687 				     V_FW_RSS_IND_TBL_CMD_VIID(viid));
4688 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4689 
4690 	/*
4691 	 * Each firmware RSS command can accommodate up to 32 RSS Ingress
4692 	 * Queue Identifiers.  These Ingress Queue IDs are packed three to
4693 	 * a 32-bit word as 10-bit values with the upper remaining 2 bits
4694 	 * reserved.
4695 	 */
4696 	while (n > 0) {
4697 		int nq = min(n, 32);
4698 		int nq_packed = 0;
4699 		__be32 *qp = &cmd.iq0_to_iq2;
4700 
4701 		/*
4702 		 * Set up the firmware RSS command header to send the next
4703 		 * "nq" Ingress Queue IDs to the firmware.
4704 		 */
4705 		cmd.niqid = cpu_to_be16(nq);
4706 		cmd.startidx = cpu_to_be16(start);
4707 
4708 		/*
4709 		 * "nq" more done for the start of the next loop.
4710 		 */
4711 		start += nq;
4712 		n -= nq;
4713 
4714 		/*
4715 		 * While there are still Ingress Queue IDs to stuff into the
4716 		 * current firmware RSS command, retrieve them from the
4717 		 * Ingress Queue ID array and insert them into the command.
4718 		 */
4719 		while (nq > 0) {
4720 			/*
4721 			 * Grab up to the next 3 Ingress Queue IDs (wrapping
4722 			 * around the Ingress Queue ID array if necessary) and
4723 			 * insert them into the firmware RSS command at the
4724 			 * current 3-tuple position within the commad.
4725 			 */
4726 			u16 qbuf[3];
4727 			u16 *qbp = qbuf;
4728 			int nqbuf = min(3, nq);
4729 
4730 			nq -= nqbuf;
4731 			qbuf[0] = qbuf[1] = qbuf[2] = 0;
4732 			while (nqbuf && nq_packed < 32) {
4733 				nqbuf--;
4734 				nq_packed++;
4735 				*qbp++ = *rsp++;
4736 				if (rsp >= rsp_end)
4737 					rsp = rspq;
4738 			}
4739 			*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
4740 					    V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
4741 					    V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
4742 		}
4743 
4744 		/*
4745 		 * Send this portion of the RRS table update to the firmware;
4746 		 * bail out on any errors.
4747 		 */
4748 		ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4749 		if (ret)
4750 			return ret;
4751 	}
4752 	return 0;
4753 }
4754 
4755 /**
4756  *	t4_config_glbl_rss - configure the global RSS mode
4757  *	@adapter: the adapter
4758  *	@mbox: mbox to use for the FW command
4759  *	@mode: global RSS mode
4760  *	@flags: mode-specific flags
4761  *
4762  *	Sets the global RSS mode.
4763  */
4764 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4765 		       unsigned int flags)
4766 {
4767 	struct fw_rss_glb_config_cmd c;
4768 
4769 	memset(&c, 0, sizeof(c));
4770 	c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
4771 				    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4772 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4773 	if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4774 		c.u.manual.mode_pkd =
4775 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4776 	} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4777 		c.u.basicvirtual.mode_keymode =
4778 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4779 		c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4780 	} else
4781 		return -EINVAL;
4782 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4783 }
4784 
4785 /**
4786  *	t4_config_vi_rss - configure per VI RSS settings
4787  *	@adapter: the adapter
4788  *	@mbox: mbox to use for the FW command
4789  *	@viid: the VI id
4790  *	@flags: RSS flags
4791  *	@defq: id of the default RSS queue for the VI.
4792  *	@skeyidx: RSS secret key table index for non-global mode
4793  *	@skey: RSS vf_scramble key for VI.
4794  *
4795  *	Configures VI-specific RSS properties.
4796  */
4797 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4798 		     unsigned int flags, unsigned int defq, unsigned int skeyidx,
4799 		     unsigned int skey)
4800 {
4801 	struct fw_rss_vi_config_cmd c;
4802 
4803 	memset(&c, 0, sizeof(c));
4804 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4805 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4806 				   V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
4807 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4808 	c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4809 					V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
4810 	c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
4811 					V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
4812 	c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
4813 
4814 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4815 }
4816 
4817 /* Read an RSS table row */
4818 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4819 {
4820 	t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
4821 	return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
4822 				   5, 0, val);
4823 }
4824 
4825 /**
4826  *	t4_read_rss - read the contents of the RSS mapping table
4827  *	@adapter: the adapter
4828  *	@map: holds the contents of the RSS mapping table
4829  *
4830  *	Reads the contents of the RSS hash->queue mapping table.
4831  */
4832 int t4_read_rss(struct adapter *adapter, u16 *map)
4833 {
4834 	u32 val;
4835 	int i, ret;
4836 
4837 	for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4838 		ret = rd_rss_row(adapter, i, &val);
4839 		if (ret)
4840 			return ret;
4841 		*map++ = G_LKPTBLQUEUE0(val);
4842 		*map++ = G_LKPTBLQUEUE1(val);
4843 	}
4844 	return 0;
4845 }
4846 
4847 /**
4848  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
4849  * @adap: the adapter
4850  * @cmd: TP fw ldst address space type
4851  * @vals: where the indirect register values are stored/written
4852  * @nregs: how many indirect registers to read/write
4853  * @start_idx: index of first indirect register to read/write
4854  * @rw: Read (1) or Write (0)
4855  * @sleep_ok: if true we may sleep while awaiting command completion
4856  *
4857  * Access TP indirect registers through LDST
4858  **/
4859 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
4860 			    unsigned int nregs, unsigned int start_index,
4861 			    unsigned int rw, bool sleep_ok)
4862 {
4863 	int ret = 0;
4864 	unsigned int i;
4865 	struct fw_ldst_cmd c;
4866 
4867 	for (i = 0; i < nregs; i++) {
4868 		memset(&c, 0, sizeof(c));
4869 		c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
4870 						F_FW_CMD_REQUEST |
4871 						(rw ? F_FW_CMD_READ :
4872 						      F_FW_CMD_WRITE) |
4873 						V_FW_LDST_CMD_ADDRSPACE(cmd));
4874 		c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4875 
4876 		c.u.addrval.addr = cpu_to_be32(start_index + i);
4877 		c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4878 		ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
4879 				      sleep_ok);
4880 		if (ret)
4881 			return ret;
4882 
4883 		if (rw)
4884 			vals[i] = be32_to_cpu(c.u.addrval.val);
4885 	}
4886 	return 0;
4887 }
4888 
4889 /**
4890  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
4891  * @adap: the adapter
4892  * @reg_addr: Address Register
4893  * @reg_data: Data register
4894  * @buff: where the indirect register values are stored/written
4895  * @nregs: how many indirect registers to read/write
4896  * @start_index: index of first indirect register to read/write
4897  * @rw: READ(1) or WRITE(0)
4898  * @sleep_ok: if true we may sleep while awaiting command completion
4899  *
4900  * Read/Write TP indirect registers through LDST if possible.
4901  * Else, use backdoor access
4902  **/
4903 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
4904 			      u32 *buff, u32 nregs, u32 start_index, int rw,
4905 			      bool sleep_ok)
4906 {
4907 	int rc = -EINVAL;
4908 	int cmd;
4909 
4910 	switch (reg_addr) {
4911 	case A_TP_PIO_ADDR:
4912 		cmd = FW_LDST_ADDRSPC_TP_PIO;
4913 		break;
4914 	case A_TP_TM_PIO_ADDR:
4915 		cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
4916 		break;
4917 	case A_TP_MIB_INDEX:
4918 		cmd = FW_LDST_ADDRSPC_TP_MIB;
4919 		break;
4920 	default:
4921 		goto indirect_access;
4922 	}
4923 
4924 	if (t4_use_ldst(adap))
4925 		rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
4926 				      sleep_ok);
4927 
4928 indirect_access:
4929 
4930 	if (rc) {
4931 		if (rw)
4932 			t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
4933 					 start_index);
4934 		else
4935 			t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
4936 					  start_index);
4937 	}
4938 }
4939 
4940 /**
4941  * t4_tp_pio_read - Read TP PIO registers
4942  * @adap: the adapter
4943  * @buff: where the indirect register values are written
4944  * @nregs: how many indirect registers to read
4945  * @start_index: index of first indirect register to read
4946  * @sleep_ok: if true we may sleep while awaiting command completion
4947  *
4948  * Read TP PIO Registers
4949  **/
4950 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
4951 		    u32 start_index, bool sleep_ok)
4952 {
4953 	t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
4954 			  start_index, 1, sleep_ok);
4955 }
4956 
4957 /**
4958  * t4_tp_pio_write - Write TP PIO registers
4959  * @adap: the adapter
4960  * @buff: where the indirect register values are stored
4961  * @nregs: how many indirect registers to write
4962  * @start_index: index of first indirect register to write
4963  * @sleep_ok: if true we may sleep while awaiting command completion
4964  *
4965  * Write TP PIO Registers
4966  **/
4967 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
4968 		     u32 start_index, bool sleep_ok)
4969 {
4970 	t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4971 	    __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
4972 }
4973 
4974 /**
4975  * t4_tp_tm_pio_read - Read TP TM PIO registers
4976  * @adap: the adapter
4977  * @buff: where the indirect register values are written
4978  * @nregs: how many indirect registers to read
4979  * @start_index: index of first indirect register to read
4980  * @sleep_ok: if true we may sleep while awaiting command completion
4981  *
4982  * Read TP TM PIO Registers
4983  **/
4984 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
4985 		       u32 start_index, bool sleep_ok)
4986 {
4987 	t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
4988 			  nregs, start_index, 1, sleep_ok);
4989 }
4990 
4991 /**
4992  * t4_tp_mib_read - Read TP MIB registers
4993  * @adap: the adapter
4994  * @buff: where the indirect register values are written
4995  * @nregs: how many indirect registers to read
4996  * @start_index: index of first indirect register to read
4997  * @sleep_ok: if true we may sleep while awaiting command completion
4998  *
4999  * Read TP MIB Registers
5000  **/
5001 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5002 		    bool sleep_ok)
5003 {
5004 	t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
5005 			  start_index, 1, sleep_ok);
5006 }
5007 
5008 /**
5009  *	t4_read_rss_key - read the global RSS key
5010  *	@adap: the adapter
5011  *	@key: 10-entry array holding the 320-bit RSS key
5012  * 	@sleep_ok: if true we may sleep while awaiting command completion
5013  *
5014  *	Reads the global 320-bit RSS key.
5015  */
5016 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5017 {
5018 	t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5019 }
5020 
5021 /**
5022  *	t4_write_rss_key - program one of the RSS keys
5023  *	@adap: the adapter
5024  *	@key: 10-entry array holding the 320-bit RSS key
5025  *	@idx: which RSS key to write
5026  * 	@sleep_ok: if true we may sleep while awaiting command completion
5027  *
5028  *	Writes one of the RSS keys with the given 320-bit value.  If @idx is
5029  *	0..15 the corresponding entry in the RSS key table is written,
5030  *	otherwise the global RSS key is written.
5031  */
5032 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5033 		      bool sleep_ok)
5034 {
5035 	u8 rss_key_addr_cnt = 16;
5036 	u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
5037 
5038 	/*
5039 	 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5040 	 * allows access to key addresses 16-63 by using KeyWrAddrX
5041 	 * as index[5:4](upper 2) into key table
5042 	 */
5043 	if ((chip_id(adap) > CHELSIO_T5) &&
5044 	    (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
5045 		rss_key_addr_cnt = 32;
5046 
5047 	t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5048 
5049 	if (idx >= 0 && idx < rss_key_addr_cnt) {
5050 		if (rss_key_addr_cnt > 16)
5051 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5052 				     vrt | V_KEYWRADDRX(idx >> 4) |
5053 				     V_T6_VFWRADDR(idx) | F_KEYWREN);
5054 		else
5055 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5056 				     vrt| V_KEYWRADDR(idx) | F_KEYWREN);
5057 	}
5058 }
5059 
5060 /**
5061  *	t4_read_rss_pf_config - read PF RSS Configuration Table
5062  *	@adapter: the adapter
5063  *	@index: the entry in the PF RSS table to read
5064  *	@valp: where to store the returned value
5065  * 	@sleep_ok: if true we may sleep while awaiting command completion
5066  *
5067  *	Reads the PF RSS Configuration Table at the specified index and returns
5068  *	the value found there.
5069  */
5070 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5071 			   u32 *valp, bool sleep_ok)
5072 {
5073 	t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
5074 }
5075 
5076 /**
5077  *	t4_write_rss_pf_config - write PF RSS Configuration Table
5078  *	@adapter: the adapter
5079  *	@index: the entry in the VF RSS table to read
5080  *	@val: the value to store
5081  * 	@sleep_ok: if true we may sleep while awaiting command completion
5082  *
5083  *	Writes the PF RSS Configuration Table at the specified index with the
5084  *	specified value.
5085  */
5086 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
5087 			    u32 val, bool sleep_ok)
5088 {
5089 	t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
5090 			sleep_ok);
5091 }
5092 
5093 /**
5094  *	t4_read_rss_vf_config - read VF RSS Configuration Table
5095  *	@adapter: the adapter
5096  *	@index: the entry in the VF RSS table to read
5097  *	@vfl: where to store the returned VFL
5098  *	@vfh: where to store the returned VFH
5099  * 	@sleep_ok: if true we may sleep while awaiting command completion
5100  *
5101  *	Reads the VF RSS Configuration Table at the specified index and returns
5102  *	the (VFL, VFH) values found there.
5103  */
5104 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5105 			   u32 *vfl, u32 *vfh, bool sleep_ok)
5106 {
5107 	u32 vrt, mask, data;
5108 
5109 	if (chip_id(adapter) <= CHELSIO_T5) {
5110 		mask = V_VFWRADDR(M_VFWRADDR);
5111 		data = V_VFWRADDR(index);
5112 	} else {
5113 		 mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5114 		 data = V_T6_VFWRADDR(index);
5115 	}
5116 	/*
5117 	 * Request that the index'th VF Table values be read into VFL/VFH.
5118 	 */
5119 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5120 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5121 	vrt |= data | F_VFRDEN;
5122 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5123 
5124 	/*
5125 	 * Grab the VFL/VFH values ...
5126 	 */
5127 	t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5128 	t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5129 }
5130 
5131 /**
5132  *	t4_write_rss_vf_config - write VF RSS Configuration Table
5133  *
5134  *	@adapter: the adapter
5135  *	@index: the entry in the VF RSS table to write
5136  *	@vfl: the VFL to store
5137  *	@vfh: the VFH to store
5138  *
5139  *	Writes the VF RSS Configuration Table at the specified index with the
5140  *	specified (VFL, VFH) values.
5141  */
5142 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
5143 			    u32 vfl, u32 vfh, bool sleep_ok)
5144 {
5145 	u32 vrt, mask, data;
5146 
5147 	if (chip_id(adapter) <= CHELSIO_T5) {
5148 		mask = V_VFWRADDR(M_VFWRADDR);
5149 		data = V_VFWRADDR(index);
5150 	} else {
5151 		mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5152 		data = V_T6_VFWRADDR(index);
5153 	}
5154 
5155 	/*
5156 	 * Load up VFL/VFH with the values to be written ...
5157 	 */
5158 	t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5159 	t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5160 
5161 	/*
5162 	 * Write the VFL/VFH into the VF Table at index'th location.
5163 	 */
5164 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5165 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5166 	vrt |= data | F_VFRDEN;
5167 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5168 }
5169 
5170 /**
5171  *	t4_read_rss_pf_map - read PF RSS Map
5172  *	@adapter: the adapter
5173  * 	@sleep_ok: if true we may sleep while awaiting command completion
5174  *
5175  *	Reads the PF RSS Map register and returns its value.
5176  */
5177 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5178 {
5179 	u32 pfmap;
5180 
5181 	t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
5182 
5183 	return pfmap;
5184 }
5185 
5186 /**
5187  *	t4_write_rss_pf_map - write PF RSS Map
5188  *	@adapter: the adapter
5189  *	@pfmap: PF RSS Map value
5190  *
5191  *	Writes the specified value to the PF RSS Map register.
5192  */
5193 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
5194 {
5195 	t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
5196 }
5197 
5198 /**
5199  *	t4_read_rss_pf_mask - read PF RSS Mask
5200  *	@adapter: the adapter
5201  * 	@sleep_ok: if true we may sleep while awaiting command completion
5202  *
5203  *	Reads the PF RSS Mask register and returns its value.
5204  */
5205 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5206 {
5207 	u32 pfmask;
5208 
5209 	t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
5210 
5211 	return pfmask;
5212 }
5213 
5214 /**
5215  *	t4_write_rss_pf_mask - write PF RSS Mask
5216  *	@adapter: the adapter
5217  *	@pfmask: PF RSS Mask value
5218  *
5219  *	Writes the specified value to the PF RSS Mask register.
5220  */
5221 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
5222 {
5223 	t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
5224 }
5225 
5226 /**
5227  *	t4_tp_get_tcp_stats - read TP's TCP MIB counters
5228  *	@adap: the adapter
5229  *	@v4: holds the TCP/IP counter values
5230  *	@v6: holds the TCP/IPv6 counter values
5231  * 	@sleep_ok: if true we may sleep while awaiting command completion
5232  *
5233  *	Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5234  *	Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5235  */
5236 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5237 			 struct tp_tcp_stats *v6, bool sleep_ok)
5238 {
5239 	u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
5240 
5241 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
5242 #define STAT(x)     val[STAT_IDX(x)]
5243 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5244 
5245 	if (v4) {
5246 		t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5247 			       A_TP_MIB_TCP_OUT_RST, sleep_ok);
5248 		v4->tcp_out_rsts = STAT(OUT_RST);
5249 		v4->tcp_in_segs  = STAT64(IN_SEG);
5250 		v4->tcp_out_segs = STAT64(OUT_SEG);
5251 		v4->tcp_retrans_segs = STAT64(RXT_SEG);
5252 	}
5253 	if (v6) {
5254 		t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5255 			       A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
5256 		v6->tcp_out_rsts = STAT(OUT_RST);
5257 		v6->tcp_in_segs  = STAT64(IN_SEG);
5258 		v6->tcp_out_segs = STAT64(OUT_SEG);
5259 		v6->tcp_retrans_segs = STAT64(RXT_SEG);
5260 	}
5261 #undef STAT64
5262 #undef STAT
5263 #undef STAT_IDX
5264 }
5265 
5266 /**
5267  *	t4_tp_get_err_stats - read TP's error MIB counters
5268  *	@adap: the adapter
5269  *	@st: holds the counter values
5270  * 	@sleep_ok: if true we may sleep while awaiting command completion
5271  *
5272  *	Returns the values of TP's error counters.
5273  */
5274 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5275 			 bool sleep_ok)
5276 {
5277 	int nchan = adap->chip_params->nchan;
5278 
5279 	t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
5280 		       sleep_ok);
5281 
5282 	t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
5283 		       sleep_ok);
5284 
5285 	t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
5286 		       sleep_ok);
5287 
5288 	t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5289 		       A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
5290 
5291 	t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5292 		       A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
5293 
5294 	t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
5295 		       sleep_ok);
5296 
5297 	t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5298 		       A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
5299 
5300 	t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5301 		       A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
5302 
5303 	t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
5304 		       sleep_ok);
5305 }
5306 
5307 /**
5308  *	t4_tp_get_proxy_stats - read TP's proxy MIB counters
5309  *	@adap: the adapter
5310  *	@st: holds the counter values
5311  *
5312  *	Returns the values of TP's proxy counters.
5313  */
5314 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
5315     bool sleep_ok)
5316 {
5317 	int nchan = adap->chip_params->nchan;
5318 
5319 	t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
5320 }
5321 
5322 /**
5323  *	t4_tp_get_cpl_stats - read TP's CPL MIB counters
5324  *	@adap: the adapter
5325  *	@st: holds the counter values
5326  * 	@sleep_ok: if true we may sleep while awaiting command completion
5327  *
5328  *	Returns the values of TP's CPL counters.
5329  */
5330 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5331 			 bool sleep_ok)
5332 {
5333 	int nchan = adap->chip_params->nchan;
5334 
5335 	t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
5336 
5337 	t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
5338 }
5339 
5340 /**
5341  *	t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5342  *	@adap: the adapter
5343  *	@st: holds the counter values
5344  *
5345  *	Returns the values of TP's RDMA counters.
5346  */
5347 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5348 			  bool sleep_ok)
5349 {
5350 	t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
5351 		       sleep_ok);
5352 }
5353 
5354 /**
5355  *	t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5356  *	@adap: the adapter
5357  *	@idx: the port index
5358  *	@st: holds the counter values
5359  * 	@sleep_ok: if true we may sleep while awaiting command completion
5360  *
5361  *	Returns the values of TP's FCoE counters for the selected port.
5362  */
5363 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5364 		       struct tp_fcoe_stats *st, bool sleep_ok)
5365 {
5366 	u32 val[2];
5367 
5368 	t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
5369 		       sleep_ok);
5370 
5371 	t4_tp_mib_read(adap, &st->frames_drop, 1,
5372 		       A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
5373 
5374 	t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
5375 		       sleep_ok);
5376 
5377 	st->octets_ddp = ((u64)val[0] << 32) | val[1];
5378 }
5379 
5380 /**
5381  *	t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5382  *	@adap: the adapter
5383  *	@st: holds the counter values
5384  * 	@sleep_ok: if true we may sleep while awaiting command completion
5385  *
5386  *	Returns the values of TP's counters for non-TCP directly-placed packets.
5387  */
5388 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5389 		      bool sleep_ok)
5390 {
5391 	u32 val[4];
5392 
5393 	t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
5394 
5395 	st->frames = val[0];
5396 	st->drops = val[1];
5397 	st->octets = ((u64)val[2] << 32) | val[3];
5398 }
5399 
5400 /**
5401  *	t4_read_mtu_tbl - returns the values in the HW path MTU table
5402  *	@adap: the adapter
5403  *	@mtus: where to store the MTU values
5404  *	@mtu_log: where to store the MTU base-2 log (may be %NULL)
5405  *
5406  *	Reads the HW path MTU table.
5407  */
5408 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5409 {
5410 	u32 v;
5411 	int i;
5412 
5413 	for (i = 0; i < NMTUS; ++i) {
5414 		t4_write_reg(adap, A_TP_MTU_TABLE,
5415 			     V_MTUINDEX(0xff) | V_MTUVALUE(i));
5416 		v = t4_read_reg(adap, A_TP_MTU_TABLE);
5417 		mtus[i] = G_MTUVALUE(v);
5418 		if (mtu_log)
5419 			mtu_log[i] = G_MTUWIDTH(v);
5420 	}
5421 }
5422 
5423 /**
5424  *	t4_read_cong_tbl - reads the congestion control table
5425  *	@adap: the adapter
5426  *	@incr: where to store the alpha values
5427  *
5428  *	Reads the additive increments programmed into the HW congestion
5429  *	control table.
5430  */
5431 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5432 {
5433 	unsigned int mtu, w;
5434 
5435 	for (mtu = 0; mtu < NMTUS; ++mtu)
5436 		for (w = 0; w < NCCTRL_WIN; ++w) {
5437 			t4_write_reg(adap, A_TP_CCTRL_TABLE,
5438 				     V_ROWINDEX(0xffff) | (mtu << 5) | w);
5439 			incr[mtu][w] = (u16)t4_read_reg(adap,
5440 						A_TP_CCTRL_TABLE) & 0x1fff;
5441 		}
5442 }
5443 
5444 /**
5445  *	t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5446  *	@adap: the adapter
5447  *	@addr: the indirect TP register address
5448  *	@mask: specifies the field within the register to modify
5449  *	@val: new value for the field
5450  *
5451  *	Sets a field of an indirect TP register to the given value.
5452  */
5453 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5454 			    unsigned int mask, unsigned int val)
5455 {
5456 	t4_write_reg(adap, A_TP_PIO_ADDR, addr);
5457 	val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
5458 	t4_write_reg(adap, A_TP_PIO_DATA, val);
5459 }
5460 
5461 /**
5462  *	init_cong_ctrl - initialize congestion control parameters
5463  *	@a: the alpha values for congestion control
5464  *	@b: the beta values for congestion control
5465  *
5466  *	Initialize the congestion control parameters.
5467  */
5468 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5469 {
5470 	a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5471 	a[9] = 2;
5472 	a[10] = 3;
5473 	a[11] = 4;
5474 	a[12] = 5;
5475 	a[13] = 6;
5476 	a[14] = 7;
5477 	a[15] = 8;
5478 	a[16] = 9;
5479 	a[17] = 10;
5480 	a[18] = 14;
5481 	a[19] = 17;
5482 	a[20] = 21;
5483 	a[21] = 25;
5484 	a[22] = 30;
5485 	a[23] = 35;
5486 	a[24] = 45;
5487 	a[25] = 60;
5488 	a[26] = 80;
5489 	a[27] = 100;
5490 	a[28] = 200;
5491 	a[29] = 300;
5492 	a[30] = 400;
5493 	a[31] = 500;
5494 
5495 	b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5496 	b[9] = b[10] = 1;
5497 	b[11] = b[12] = 2;
5498 	b[13] = b[14] = b[15] = b[16] = 3;
5499 	b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5500 	b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5501 	b[28] = b[29] = 6;
5502 	b[30] = b[31] = 7;
5503 }
5504 
5505 /* The minimum additive increment value for the congestion control table */
5506 #define CC_MIN_INCR 2U
5507 
5508 /**
5509  *	t4_load_mtus - write the MTU and congestion control HW tables
5510  *	@adap: the adapter
5511  *	@mtus: the values for the MTU table
5512  *	@alpha: the values for the congestion control alpha parameter
5513  *	@beta: the values for the congestion control beta parameter
5514  *
5515  *	Write the HW MTU table with the supplied MTUs and the high-speed
5516  *	congestion control table with the supplied alpha, beta, and MTUs.
5517  *	We write the two tables together because the additive increments
5518  *	depend on the MTUs.
5519  */
5520 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5521 		  const unsigned short *alpha, const unsigned short *beta)
5522 {
5523 	static const unsigned int avg_pkts[NCCTRL_WIN] = {
5524 		2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5525 		896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5526 		28672, 40960, 57344, 81920, 114688, 163840, 229376
5527 	};
5528 
5529 	unsigned int i, w;
5530 
5531 	for (i = 0; i < NMTUS; ++i) {
5532 		unsigned int mtu = mtus[i];
5533 		unsigned int log2 = fls(mtu);
5534 
5535 		if (!(mtu & ((1 << log2) >> 2)))     /* round */
5536 			log2--;
5537 		t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
5538 			     V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
5539 
5540 		for (w = 0; w < NCCTRL_WIN; ++w) {
5541 			unsigned int inc;
5542 
5543 			inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5544 				  CC_MIN_INCR);
5545 
5546 			t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
5547 				     (w << 16) | (beta[w] << 13) | inc);
5548 		}
5549 	}
5550 }
5551 
5552 /**
5553  *	t4_set_pace_tbl - set the pace table
5554  *	@adap: the adapter
5555  *	@pace_vals: the pace values in microseconds
5556  *	@start: index of the first entry in the HW pace table to set
5557  *	@n: how many entries to set
5558  *
5559  *	Sets (a subset of the) HW pace table.
5560  */
5561 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
5562 		     unsigned int start, unsigned int n)
5563 {
5564 	unsigned int vals[NTX_SCHED], i;
5565 	unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
5566 
5567 	if (n > NTX_SCHED)
5568 	    return -ERANGE;
5569 
5570 	/* convert values from us to dack ticks, rounding to closest value */
5571 	for (i = 0; i < n; i++, pace_vals++) {
5572 		vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
5573 		if (vals[i] > 0x7ff)
5574 			return -ERANGE;
5575 		if (*pace_vals && vals[i] == 0)
5576 			return -ERANGE;
5577 	}
5578 	for (i = 0; i < n; i++, start++)
5579 		t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
5580 	return 0;
5581 }
5582 
5583 /**
5584  *	t4_set_sched_bps - set the bit rate for a HW traffic scheduler
5585  *	@adap: the adapter
5586  *	@kbps: target rate in Kbps
5587  *	@sched: the scheduler index
5588  *
5589  *	Configure a Tx HW scheduler for the target rate.
5590  */
5591 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
5592 {
5593 	unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
5594 	unsigned int clk = adap->params.vpd.cclk * 1000;
5595 	unsigned int selected_cpt = 0, selected_bpt = 0;
5596 
5597 	if (kbps > 0) {
5598 		kbps *= 125;     /* -> bytes */
5599 		for (cpt = 1; cpt <= 255; cpt++) {
5600 			tps = clk / cpt;
5601 			bpt = (kbps + tps / 2) / tps;
5602 			if (bpt > 0 && bpt <= 255) {
5603 				v = bpt * tps;
5604 				delta = v >= kbps ? v - kbps : kbps - v;
5605 				if (delta < mindelta) {
5606 					mindelta = delta;
5607 					selected_cpt = cpt;
5608 					selected_bpt = bpt;
5609 				}
5610 			} else if (selected_cpt)
5611 				break;
5612 		}
5613 		if (!selected_cpt)
5614 			return -EINVAL;
5615 	}
5616 	t4_write_reg(adap, A_TP_TM_PIO_ADDR,
5617 		     A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
5618 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5619 	if (sched & 1)
5620 		v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
5621 	else
5622 		v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
5623 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5624 	return 0;
5625 }
5626 
5627 /**
5628  *	t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
5629  *	@adap: the adapter
5630  *	@sched: the scheduler index
5631  *	@ipg: the interpacket delay in tenths of nanoseconds
5632  *
5633  *	Set the interpacket delay for a HW packet rate scheduler.
5634  */
5635 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
5636 {
5637 	unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
5638 
5639 	/* convert ipg to nearest number of core clocks */
5640 	ipg *= core_ticks_per_usec(adap);
5641 	ipg = (ipg + 5000) / 10000;
5642 	if (ipg > M_TXTIMERSEPQ0)
5643 		return -EINVAL;
5644 
5645 	t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
5646 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5647 	if (sched & 1)
5648 		v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
5649 	else
5650 		v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
5651 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5652 	t4_read_reg(adap, A_TP_TM_PIO_DATA);
5653 	return 0;
5654 }
5655 
5656 /*
5657  * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5658  * clocks.  The formula is
5659  *
5660  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5661  *
5662  * which is equivalent to
5663  *
5664  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5665  */
5666 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5667 {
5668 	u64 v = bytes256 * adap->params.vpd.cclk;
5669 
5670 	return v * 62 + v / 2;
5671 }
5672 
5673 /**
5674  *	t4_get_chan_txrate - get the current per channel Tx rates
5675  *	@adap: the adapter
5676  *	@nic_rate: rates for NIC traffic
5677  *	@ofld_rate: rates for offloaded traffic
5678  *
5679  *	Return the current Tx rates in bytes/s for NIC and offloaded traffic
5680  *	for each channel.
5681  */
5682 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5683 {
5684 	u32 v;
5685 
5686 	v = t4_read_reg(adap, A_TP_TX_TRATE);
5687 	nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
5688 	nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
5689 	if (adap->chip_params->nchan > 2) {
5690 		nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
5691 		nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
5692 	}
5693 
5694 	v = t4_read_reg(adap, A_TP_TX_ORATE);
5695 	ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
5696 	ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
5697 	if (adap->chip_params->nchan > 2) {
5698 		ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
5699 		ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
5700 	}
5701 }
5702 
5703 /**
5704  *	t4_set_trace_filter - configure one of the tracing filters
5705  *	@adap: the adapter
5706  *	@tp: the desired trace filter parameters
5707  *	@idx: which filter to configure
5708  *	@enable: whether to enable or disable the filter
5709  *
5710  *	Configures one of the tracing filters available in HW.  If @tp is %NULL
5711  *	it indicates that the filter is already written in the register and it
5712  *	just needs to be enabled or disabled.
5713  */
5714 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5715     int idx, int enable)
5716 {
5717 	int i, ofst = idx * 4;
5718 	u32 data_reg, mask_reg, cfg;
5719 	u32 multitrc = F_TRCMULTIFILTER;
5720 	u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
5721 
5722 	if (idx < 0 || idx >= NTRACE)
5723 		return -EINVAL;
5724 
5725 	if (tp == NULL || !enable) {
5726 		t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
5727 		    enable ? en : 0);
5728 		return 0;
5729 	}
5730 
5731 	/*
5732 	 * TODO - After T4 data book is updated, specify the exact
5733 	 * section below.
5734 	 *
5735 	 * See T4 data book - MPS section for a complete description
5736 	 * of the below if..else handling of A_MPS_TRC_CFG register
5737 	 * value.
5738 	 */
5739 	cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
5740 	if (cfg & F_TRCMULTIFILTER) {
5741 		/*
5742 		 * If multiple tracers are enabled, then maximum
5743 		 * capture size is 2.5KB (FIFO size of a single channel)
5744 		 * minus 2 flits for CPL_TRACE_PKT header.
5745 		 */
5746 		if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5747 			return -EINVAL;
5748 	} else {
5749 		/*
5750 		 * If multiple tracers are disabled, to avoid deadlocks
5751 		 * maximum packet capture size of 9600 bytes is recommended.
5752 		 * Also in this mode, only trace0 can be enabled and running.
5753 		 */
5754 		multitrc = 0;
5755 		if (tp->snap_len > 9600 || idx)
5756 			return -EINVAL;
5757 	}
5758 
5759 	if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
5760 	    tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
5761 	    tp->min_len > M_TFMINPKTSIZE)
5762 		return -EINVAL;
5763 
5764 	/* stop the tracer we'll be changing */
5765 	t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
5766 
5767 	idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
5768 	data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
5769 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
5770 
5771 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5772 		t4_write_reg(adap, data_reg, tp->data[i]);
5773 		t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5774 	}
5775 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
5776 		     V_TFCAPTUREMAX(tp->snap_len) |
5777 		     V_TFMINPKTSIZE(tp->min_len));
5778 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
5779 		     V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
5780 		     (is_t4(adap) ?
5781 		     V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
5782 		     V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
5783 
5784 	return 0;
5785 }
5786 
5787 /**
5788  *	t4_get_trace_filter - query one of the tracing filters
5789  *	@adap: the adapter
5790  *	@tp: the current trace filter parameters
5791  *	@idx: which trace filter to query
5792  *	@enabled: non-zero if the filter is enabled
5793  *
5794  *	Returns the current settings of one of the HW tracing filters.
5795  */
5796 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5797 			 int *enabled)
5798 {
5799 	u32 ctla, ctlb;
5800 	int i, ofst = idx * 4;
5801 	u32 data_reg, mask_reg;
5802 
5803 	ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
5804 	ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
5805 
5806 	if (is_t4(adap)) {
5807 		*enabled = !!(ctla & F_TFEN);
5808 		tp->port =  G_TFPORT(ctla);
5809 		tp->invert = !!(ctla & F_TFINVERTMATCH);
5810 	} else {
5811 		*enabled = !!(ctla & F_T5_TFEN);
5812 		tp->port = G_T5_TFPORT(ctla);
5813 		tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
5814 	}
5815 	tp->snap_len = G_TFCAPTUREMAX(ctlb);
5816 	tp->min_len = G_TFMINPKTSIZE(ctlb);
5817 	tp->skip_ofst = G_TFOFFSET(ctla);
5818 	tp->skip_len = G_TFLENGTH(ctla);
5819 
5820 	ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
5821 	data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
5822 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
5823 
5824 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5825 		tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5826 		tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5827 	}
5828 }
5829 
5830 /**
5831  *	t4_pmtx_get_stats - returns the HW stats from PMTX
5832  *	@adap: the adapter
5833  *	@cnt: where to store the count statistics
5834  *	@cycles: where to store the cycle statistics
5835  *
5836  *	Returns performance statistics from PMTX.
5837  */
5838 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5839 {
5840 	int i;
5841 	u32 data[2];
5842 
5843 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5844 		t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
5845 		cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
5846 		if (is_t4(adap))
5847 			cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
5848 		else {
5849 			t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
5850 					 A_PM_TX_DBG_DATA, data, 2,
5851 					 A_PM_TX_DBG_STAT_MSB);
5852 			cycles[i] = (((u64)data[0] << 32) | data[1]);
5853 		}
5854 	}
5855 }
5856 
5857 /**
5858  *	t4_pmrx_get_stats - returns the HW stats from PMRX
5859  *	@adap: the adapter
5860  *	@cnt: where to store the count statistics
5861  *	@cycles: where to store the cycle statistics
5862  *
5863  *	Returns performance statistics from PMRX.
5864  */
5865 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5866 {
5867 	int i;
5868 	u32 data[2];
5869 
5870 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5871 		t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
5872 		cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
5873 		if (is_t4(adap)) {
5874 			cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
5875 		} else {
5876 			t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
5877 					 A_PM_RX_DBG_DATA, data, 2,
5878 					 A_PM_RX_DBG_STAT_MSB);
5879 			cycles[i] = (((u64)data[0] << 32) | data[1]);
5880 		}
5881 	}
5882 }
5883 
5884 /**
5885  *	t4_get_mps_bg_map - return the buffer groups associated with a port
5886  *	@adap: the adapter
5887  *	@idx: the port index
5888  *
5889  *	Returns a bitmap indicating which MPS buffer groups are associated
5890  *	with the given port.  Bit i is set if buffer group i is used by the
5891  *	port.
5892  */
5893 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5894 {
5895 	u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
5896 
5897 	if (n == 0)
5898 		return idx == 0 ? 0xf : 0;
5899 	if (n == 1 && chip_id(adap) <= CHELSIO_T5)
5900 		return idx < 2 ? (3 << (2 * idx)) : 0;
5901 	return 1 << idx;
5902 }
5903 
5904 /**
5905  *      t4_get_port_type_description - return Port Type string description
5906  *      @port_type: firmware Port Type enumeration
5907  */
5908 const char *t4_get_port_type_description(enum fw_port_type port_type)
5909 {
5910 	static const char *const port_type_description[] = {
5911 		"Fiber_XFI",
5912 		"Fiber_XAUI",
5913 		"BT_SGMII",
5914 		"BT_XFI",
5915 		"BT_XAUI",
5916 		"KX4",
5917 		"CX4",
5918 		"KX",
5919 		"KR",
5920 		"SFP",
5921 		"BP_AP",
5922 		"BP4_AP",
5923 		"QSFP_10G",
5924 		"QSA",
5925 		"QSFP",
5926 		"BP40_BA",
5927 		"KR4_100G",
5928 		"CR4_QSFP",
5929 		"CR_QSFP",
5930 		"CR2_QSFP",
5931 		"SFP28",
5932 		"KR_SFP28",
5933 	};
5934 
5935 	if (port_type < ARRAY_SIZE(port_type_description))
5936 		return port_type_description[port_type];
5937 	return "UNKNOWN";
5938 }
5939 
5940 /**
5941  *      t4_get_port_stats_offset - collect port stats relative to a previous
5942  *				   snapshot
5943  *      @adap: The adapter
5944  *      @idx: The port
5945  *      @stats: Current stats to fill
5946  *      @offset: Previous stats snapshot
5947  */
5948 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5949 		struct port_stats *stats,
5950 		struct port_stats *offset)
5951 {
5952 	u64 *s, *o;
5953 	int i;
5954 
5955 	t4_get_port_stats(adap, idx, stats);
5956 	for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
5957 			i < (sizeof(struct port_stats)/sizeof(u64)) ;
5958 			i++, s++, o++)
5959 		*s -= *o;
5960 }
5961 
5962 /**
5963  *	t4_get_port_stats - collect port statistics
5964  *	@adap: the adapter
5965  *	@idx: the port index
5966  *	@p: the stats structure to fill
5967  *
5968  *	Collect statistics related to the given port from HW.
5969  */
5970 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5971 {
5972 	u32 bgmap = t4_get_mps_bg_map(adap, idx);
5973 	u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
5974 
5975 #define GET_STAT(name) \
5976 	t4_read_reg64(adap, \
5977 	(is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
5978 	T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
5979 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5980 
5981 	p->tx_pause		= GET_STAT(TX_PORT_PAUSE);
5982 	p->tx_octets		= GET_STAT(TX_PORT_BYTES);
5983 	p->tx_frames		= GET_STAT(TX_PORT_FRAMES);
5984 	p->tx_bcast_frames	= GET_STAT(TX_PORT_BCAST);
5985 	p->tx_mcast_frames	= GET_STAT(TX_PORT_MCAST);
5986 	p->tx_ucast_frames	= GET_STAT(TX_PORT_UCAST);
5987 	p->tx_error_frames	= GET_STAT(TX_PORT_ERROR);
5988 	p->tx_frames_64		= GET_STAT(TX_PORT_64B);
5989 	p->tx_frames_65_127	= GET_STAT(TX_PORT_65B_127B);
5990 	p->tx_frames_128_255	= GET_STAT(TX_PORT_128B_255B);
5991 	p->tx_frames_256_511	= GET_STAT(TX_PORT_256B_511B);
5992 	p->tx_frames_512_1023	= GET_STAT(TX_PORT_512B_1023B);
5993 	p->tx_frames_1024_1518	= GET_STAT(TX_PORT_1024B_1518B);
5994 	p->tx_frames_1519_max	= GET_STAT(TX_PORT_1519B_MAX);
5995 	p->tx_drop		= GET_STAT(TX_PORT_DROP);
5996 	p->tx_ppp0		= GET_STAT(TX_PORT_PPP0);
5997 	p->tx_ppp1		= GET_STAT(TX_PORT_PPP1);
5998 	p->tx_ppp2		= GET_STAT(TX_PORT_PPP2);
5999 	p->tx_ppp3		= GET_STAT(TX_PORT_PPP3);
6000 	p->tx_ppp4		= GET_STAT(TX_PORT_PPP4);
6001 	p->tx_ppp5		= GET_STAT(TX_PORT_PPP5);
6002 	p->tx_ppp6		= GET_STAT(TX_PORT_PPP6);
6003 	p->tx_ppp7		= GET_STAT(TX_PORT_PPP7);
6004 
6005 	if (chip_id(adap) >= CHELSIO_T5) {
6006 		if (stat_ctl & F_COUNTPAUSESTATTX) {
6007 			p->tx_frames -= p->tx_pause;
6008 			p->tx_octets -= p->tx_pause * 64;
6009 		}
6010 		if (stat_ctl & F_COUNTPAUSEMCTX)
6011 			p->tx_mcast_frames -= p->tx_pause;
6012 	}
6013 
6014 	p->rx_pause		= GET_STAT(RX_PORT_PAUSE);
6015 	p->rx_octets		= GET_STAT(RX_PORT_BYTES);
6016 	p->rx_frames		= GET_STAT(RX_PORT_FRAMES);
6017 	p->rx_bcast_frames	= GET_STAT(RX_PORT_BCAST);
6018 	p->rx_mcast_frames	= GET_STAT(RX_PORT_MCAST);
6019 	p->rx_ucast_frames	= GET_STAT(RX_PORT_UCAST);
6020 	p->rx_too_long		= GET_STAT(RX_PORT_MTU_ERROR);
6021 	p->rx_jabber		= GET_STAT(RX_PORT_MTU_CRC_ERROR);
6022 	p->rx_fcs_err		= GET_STAT(RX_PORT_CRC_ERROR);
6023 	p->rx_len_err		= GET_STAT(RX_PORT_LEN_ERROR);
6024 	p->rx_symbol_err	= GET_STAT(RX_PORT_SYM_ERROR);
6025 	p->rx_runt		= GET_STAT(RX_PORT_LESS_64B);
6026 	p->rx_frames_64		= GET_STAT(RX_PORT_64B);
6027 	p->rx_frames_65_127	= GET_STAT(RX_PORT_65B_127B);
6028 	p->rx_frames_128_255	= GET_STAT(RX_PORT_128B_255B);
6029 	p->rx_frames_256_511	= GET_STAT(RX_PORT_256B_511B);
6030 	p->rx_frames_512_1023	= GET_STAT(RX_PORT_512B_1023B);
6031 	p->rx_frames_1024_1518	= GET_STAT(RX_PORT_1024B_1518B);
6032 	p->rx_frames_1519_max	= GET_STAT(RX_PORT_1519B_MAX);
6033 	p->rx_ppp0		= GET_STAT(RX_PORT_PPP0);
6034 	p->rx_ppp1		= GET_STAT(RX_PORT_PPP1);
6035 	p->rx_ppp2		= GET_STAT(RX_PORT_PPP2);
6036 	p->rx_ppp3		= GET_STAT(RX_PORT_PPP3);
6037 	p->rx_ppp4		= GET_STAT(RX_PORT_PPP4);
6038 	p->rx_ppp5		= GET_STAT(RX_PORT_PPP5);
6039 	p->rx_ppp6		= GET_STAT(RX_PORT_PPP6);
6040 	p->rx_ppp7		= GET_STAT(RX_PORT_PPP7);
6041 
6042 	if (chip_id(adap) >= CHELSIO_T5) {
6043 		if (stat_ctl & F_COUNTPAUSESTATRX) {
6044 			p->rx_frames -= p->rx_pause;
6045 			p->rx_octets -= p->rx_pause * 64;
6046 		}
6047 		if (stat_ctl & F_COUNTPAUSEMCRX)
6048 			p->rx_mcast_frames -= p->rx_pause;
6049 	}
6050 
6051 	p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6052 	p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6053 	p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6054 	p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6055 	p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6056 	p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6057 	p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6058 	p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6059 
6060 #undef GET_STAT
6061 #undef GET_STAT_COM
6062 }
6063 
6064 /**
6065  *	t4_get_lb_stats - collect loopback port statistics
6066  *	@adap: the adapter
6067  *	@idx: the loopback port index
6068  *	@p: the stats structure to fill
6069  *
6070  *	Return HW statistics for the given loopback port.
6071  */
6072 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6073 {
6074 	u32 bgmap = t4_get_mps_bg_map(adap, idx);
6075 
6076 #define GET_STAT(name) \
6077 	t4_read_reg64(adap, \
6078 	(is_t4(adap) ? \
6079 	PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
6080 	T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
6081 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6082 
6083 	p->octets	= GET_STAT(BYTES);
6084 	p->frames	= GET_STAT(FRAMES);
6085 	p->bcast_frames	= GET_STAT(BCAST);
6086 	p->mcast_frames	= GET_STAT(MCAST);
6087 	p->ucast_frames	= GET_STAT(UCAST);
6088 	p->error_frames	= GET_STAT(ERROR);
6089 
6090 	p->frames_64		= GET_STAT(64B);
6091 	p->frames_65_127	= GET_STAT(65B_127B);
6092 	p->frames_128_255	= GET_STAT(128B_255B);
6093 	p->frames_256_511	= GET_STAT(256B_511B);
6094 	p->frames_512_1023	= GET_STAT(512B_1023B);
6095 	p->frames_1024_1518	= GET_STAT(1024B_1518B);
6096 	p->frames_1519_max	= GET_STAT(1519B_MAX);
6097 	p->drop			= GET_STAT(DROP_FRAMES);
6098 
6099 	p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6100 	p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6101 	p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6102 	p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6103 	p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6104 	p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6105 	p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6106 	p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6107 
6108 #undef GET_STAT
6109 #undef GET_STAT_COM
6110 }
6111 
6112 /**
6113  *	t4_wol_magic_enable - enable/disable magic packet WoL
6114  *	@adap: the adapter
6115  *	@port: the physical port index
6116  *	@addr: MAC address expected in magic packets, %NULL to disable
6117  *
6118  *	Enables/disables magic packet wake-on-LAN for the selected port.
6119  */
6120 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
6121 			 const u8 *addr)
6122 {
6123 	u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
6124 
6125 	if (is_t4(adap)) {
6126 		mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
6127 		mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
6128 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
6129 	} else {
6130 		mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
6131 		mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
6132 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
6133 	}
6134 
6135 	if (addr) {
6136 		t4_write_reg(adap, mag_id_reg_l,
6137 			     (addr[2] << 24) | (addr[3] << 16) |
6138 			     (addr[4] << 8) | addr[5]);
6139 		t4_write_reg(adap, mag_id_reg_h,
6140 			     (addr[0] << 8) | addr[1]);
6141 	}
6142 	t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
6143 			 V_MAGICEN(addr != NULL));
6144 }
6145 
6146 /**
6147  *	t4_wol_pat_enable - enable/disable pattern-based WoL
6148  *	@adap: the adapter
6149  *	@port: the physical port index
6150  *	@map: bitmap of which HW pattern filters to set
6151  *	@mask0: byte mask for bytes 0-63 of a packet
6152  *	@mask1: byte mask for bytes 64-127 of a packet
6153  *	@crc: Ethernet CRC for selected bytes
6154  *	@enable: enable/disable switch
6155  *
6156  *	Sets the pattern filters indicated in @map to mask out the bytes
6157  *	specified in @mask0/@mask1 in received packets and compare the CRC of
6158  *	the resulting packet against @crc.  If @enable is %true pattern-based
6159  *	WoL is enabled, otherwise disabled.
6160  */
6161 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
6162 		      u64 mask0, u64 mask1, unsigned int crc, bool enable)
6163 {
6164 	int i;
6165 	u32 port_cfg_reg;
6166 
6167 	if (is_t4(adap))
6168 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
6169 	else
6170 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
6171 
6172 	if (!enable) {
6173 		t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
6174 		return 0;
6175 	}
6176 	if (map > 0xff)
6177 		return -EINVAL;
6178 
6179 #define EPIO_REG(name) \
6180 	(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
6181 	T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
6182 
6183 	t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
6184 	t4_write_reg(adap, EPIO_REG(DATA2), mask1);
6185 	t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
6186 
6187 	for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
6188 		if (!(map & 1))
6189 			continue;
6190 
6191 		/* write byte masks */
6192 		t4_write_reg(adap, EPIO_REG(DATA0), mask0);
6193 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
6194 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
6195 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
6196 			return -ETIMEDOUT;
6197 
6198 		/* write CRC */
6199 		t4_write_reg(adap, EPIO_REG(DATA0), crc);
6200 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
6201 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
6202 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
6203 			return -ETIMEDOUT;
6204 	}
6205 #undef EPIO_REG
6206 
6207 	t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
6208 	return 0;
6209 }
6210 
6211 /*     t4_mk_filtdelwr - create a delete filter WR
6212  *     @ftid: the filter ID
6213  *     @wr: the filter work request to populate
6214  *     @qid: ingress queue to receive the delete notification
6215  *
6216  *     Creates a filter work request to delete the supplied filter.  If @qid is
6217  *     negative the delete notification is suppressed.
6218  */
6219 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6220 {
6221 	memset(wr, 0, sizeof(*wr));
6222 	wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
6223 	wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
6224 	wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
6225 				    V_FW_FILTER_WR_NOREPLY(qid < 0));
6226 	wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
6227 	if (qid >= 0)
6228 		wr->rx_chan_rx_rpl_iq =
6229 				cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
6230 }
6231 
6232 #define INIT_CMD(var, cmd, rd_wr) do { \
6233 	(var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
6234 					F_FW_CMD_REQUEST | \
6235 					F_FW_CMD_##rd_wr); \
6236 	(var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6237 } while (0)
6238 
6239 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6240 			  u32 addr, u32 val)
6241 {
6242 	u32 ldst_addrspace;
6243 	struct fw_ldst_cmd c;
6244 
6245 	memset(&c, 0, sizeof(c));
6246 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
6247 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6248 					F_FW_CMD_REQUEST |
6249 					F_FW_CMD_WRITE |
6250 					ldst_addrspace);
6251 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6252 	c.u.addrval.addr = cpu_to_be32(addr);
6253 	c.u.addrval.val = cpu_to_be32(val);
6254 
6255 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6256 }
6257 
6258 /**
6259  *	t4_mdio_rd - read a PHY register through MDIO
6260  *	@adap: the adapter
6261  *	@mbox: mailbox to use for the FW command
6262  *	@phy_addr: the PHY address
6263  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
6264  *	@reg: the register to read
6265  *	@valp: where to store the value
6266  *
6267  *	Issues a FW command through the given mailbox to read a PHY register.
6268  */
6269 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6270 	       unsigned int mmd, unsigned int reg, unsigned int *valp)
6271 {
6272 	int ret;
6273 	u32 ldst_addrspace;
6274 	struct fw_ldst_cmd c;
6275 
6276 	memset(&c, 0, sizeof(c));
6277 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6278 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6279 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
6280 					ldst_addrspace);
6281 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6282 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6283 					 V_FW_LDST_CMD_MMD(mmd));
6284 	c.u.mdio.raddr = cpu_to_be16(reg);
6285 
6286 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6287 	if (ret == 0)
6288 		*valp = be16_to_cpu(c.u.mdio.rval);
6289 	return ret;
6290 }
6291 
6292 /**
6293  *	t4_mdio_wr - write a PHY register through MDIO
6294  *	@adap: the adapter
6295  *	@mbox: mailbox to use for the FW command
6296  *	@phy_addr: the PHY address
6297  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
6298  *	@reg: the register to write
6299  *	@valp: value to write
6300  *
6301  *	Issues a FW command through the given mailbox to write a PHY register.
6302  */
6303 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6304 	       unsigned int mmd, unsigned int reg, unsigned int val)
6305 {
6306 	u32 ldst_addrspace;
6307 	struct fw_ldst_cmd c;
6308 
6309 	memset(&c, 0, sizeof(c));
6310 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6311 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6312 					F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6313 					ldst_addrspace);
6314 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6315 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6316 					 V_FW_LDST_CMD_MMD(mmd));
6317 	c.u.mdio.raddr = cpu_to_be16(reg);
6318 	c.u.mdio.rval = cpu_to_be16(val);
6319 
6320 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6321 }
6322 
6323 /**
6324  *
6325  *	t4_sge_decode_idma_state - decode the idma state
6326  *	@adap: the adapter
6327  *	@state: the state idma is stuck in
6328  */
6329 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6330 {
6331 	static const char * const t4_decode[] = {
6332 		"IDMA_IDLE",
6333 		"IDMA_PUSH_MORE_CPL_FIFO",
6334 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6335 		"Not used",
6336 		"IDMA_PHYSADDR_SEND_PCIEHDR",
6337 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6338 		"IDMA_PHYSADDR_SEND_PAYLOAD",
6339 		"IDMA_SEND_FIFO_TO_IMSG",
6340 		"IDMA_FL_REQ_DATA_FL_PREP",
6341 		"IDMA_FL_REQ_DATA_FL",
6342 		"IDMA_FL_DROP",
6343 		"IDMA_FL_H_REQ_HEADER_FL",
6344 		"IDMA_FL_H_SEND_PCIEHDR",
6345 		"IDMA_FL_H_PUSH_CPL_FIFO",
6346 		"IDMA_FL_H_SEND_CPL",
6347 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6348 		"IDMA_FL_H_SEND_IP_HDR",
6349 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6350 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6351 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6352 		"IDMA_FL_D_SEND_PCIEHDR",
6353 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6354 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6355 		"IDMA_FL_SEND_PCIEHDR",
6356 		"IDMA_FL_PUSH_CPL_FIFO",
6357 		"IDMA_FL_SEND_CPL",
6358 		"IDMA_FL_SEND_PAYLOAD_FIRST",
6359 		"IDMA_FL_SEND_PAYLOAD",
6360 		"IDMA_FL_REQ_NEXT_DATA_FL",
6361 		"IDMA_FL_SEND_NEXT_PCIEHDR",
6362 		"IDMA_FL_SEND_PADDING",
6363 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6364 		"IDMA_FL_SEND_FIFO_TO_IMSG",
6365 		"IDMA_FL_REQ_DATAFL_DONE",
6366 		"IDMA_FL_REQ_HEADERFL_DONE",
6367 	};
6368 	static const char * const t5_decode[] = {
6369 		"IDMA_IDLE",
6370 		"IDMA_ALMOST_IDLE",
6371 		"IDMA_PUSH_MORE_CPL_FIFO",
6372 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6373 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6374 		"IDMA_PHYSADDR_SEND_PCIEHDR",
6375 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6376 		"IDMA_PHYSADDR_SEND_PAYLOAD",
6377 		"IDMA_SEND_FIFO_TO_IMSG",
6378 		"IDMA_FL_REQ_DATA_FL",
6379 		"IDMA_FL_DROP",
6380 		"IDMA_FL_DROP_SEND_INC",
6381 		"IDMA_FL_H_REQ_HEADER_FL",
6382 		"IDMA_FL_H_SEND_PCIEHDR",
6383 		"IDMA_FL_H_PUSH_CPL_FIFO",
6384 		"IDMA_FL_H_SEND_CPL",
6385 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6386 		"IDMA_FL_H_SEND_IP_HDR",
6387 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6388 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6389 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6390 		"IDMA_FL_D_SEND_PCIEHDR",
6391 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6392 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6393 		"IDMA_FL_SEND_PCIEHDR",
6394 		"IDMA_FL_PUSH_CPL_FIFO",
6395 		"IDMA_FL_SEND_CPL",
6396 		"IDMA_FL_SEND_PAYLOAD_FIRST",
6397 		"IDMA_FL_SEND_PAYLOAD",
6398 		"IDMA_FL_REQ_NEXT_DATA_FL",
6399 		"IDMA_FL_SEND_NEXT_PCIEHDR",
6400 		"IDMA_FL_SEND_PADDING",
6401 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6402 	};
6403 	static const char * const t6_decode[] = {
6404 		"IDMA_IDLE",
6405 		"IDMA_PUSH_MORE_CPL_FIFO",
6406 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6407 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6408 		"IDMA_PHYSADDR_SEND_PCIEHDR",
6409 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6410 		"IDMA_PHYSADDR_SEND_PAYLOAD",
6411 		"IDMA_FL_REQ_DATA_FL",
6412 		"IDMA_FL_DROP",
6413 		"IDMA_FL_DROP_SEND_INC",
6414 		"IDMA_FL_H_REQ_HEADER_FL",
6415 		"IDMA_FL_H_SEND_PCIEHDR",
6416 		"IDMA_FL_H_PUSH_CPL_FIFO",
6417 		"IDMA_FL_H_SEND_CPL",
6418 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6419 		"IDMA_FL_H_SEND_IP_HDR",
6420 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6421 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6422 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6423 		"IDMA_FL_D_SEND_PCIEHDR",
6424 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6425 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6426 		"IDMA_FL_SEND_PCIEHDR",
6427 		"IDMA_FL_PUSH_CPL_FIFO",
6428 		"IDMA_FL_SEND_CPL",
6429 		"IDMA_FL_SEND_PAYLOAD_FIRST",
6430 		"IDMA_FL_SEND_PAYLOAD",
6431 		"IDMA_FL_REQ_NEXT_DATA_FL",
6432 		"IDMA_FL_SEND_NEXT_PCIEHDR",
6433 		"IDMA_FL_SEND_PADDING",
6434 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6435 	};
6436 	static const u32 sge_regs[] = {
6437 		A_SGE_DEBUG_DATA_LOW_INDEX_2,
6438 		A_SGE_DEBUG_DATA_LOW_INDEX_3,
6439 		A_SGE_DEBUG_DATA_HIGH_INDEX_10,
6440 	};
6441 	const char * const *sge_idma_decode;
6442 	int sge_idma_decode_nstates;
6443 	int i;
6444 	unsigned int chip_version = chip_id(adapter);
6445 
6446 	/* Select the right set of decode strings to dump depending on the
6447 	 * adapter chip type.
6448 	 */
6449 	switch (chip_version) {
6450 	case CHELSIO_T4:
6451 		sge_idma_decode = (const char * const *)t4_decode;
6452 		sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6453 		break;
6454 
6455 	case CHELSIO_T5:
6456 		sge_idma_decode = (const char * const *)t5_decode;
6457 		sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6458 		break;
6459 
6460 	case CHELSIO_T6:
6461 		sge_idma_decode = (const char * const *)t6_decode;
6462 		sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6463 		break;
6464 
6465 	default:
6466 		CH_ERR(adapter,	"Unsupported chip version %d\n", chip_version);
6467 		return;
6468 	}
6469 
6470 	if (state < sge_idma_decode_nstates)
6471 		CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6472 	else
6473 		CH_WARN(adapter, "idma state %d unknown\n", state);
6474 
6475 	for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6476 		CH_WARN(adapter, "SGE register %#x value %#x\n",
6477 			sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6478 }
6479 
6480 /**
6481  *      t4_sge_ctxt_flush - flush the SGE context cache
6482  *      @adap: the adapter
6483  *      @mbox: mailbox to use for the FW command
6484  *
6485  *      Issues a FW command through the given mailbox to flush the
6486  *      SGE context cache.
6487  */
6488 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6489 {
6490 	int ret;
6491 	u32 ldst_addrspace;
6492 	struct fw_ldst_cmd c;
6493 
6494 	memset(&c, 0, sizeof(c));
6495 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
6496 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6497 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
6498 					ldst_addrspace);
6499 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6500 	c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
6501 
6502 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6503 	return ret;
6504 }
6505 
6506 /**
6507  *      t4_fw_hello - establish communication with FW
6508  *      @adap: the adapter
6509  *      @mbox: mailbox to use for the FW command
6510  *      @evt_mbox: mailbox to receive async FW events
6511  *      @master: specifies the caller's willingness to be the device master
6512  *	@state: returns the current device state (if non-NULL)
6513  *
6514  *	Issues a command to establish communication with FW.  Returns either
6515  *	an error (negative integer) or the mailbox of the Master PF.
6516  */
6517 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6518 		enum dev_master master, enum dev_state *state)
6519 {
6520 	int ret;
6521 	struct fw_hello_cmd c;
6522 	u32 v;
6523 	unsigned int master_mbox;
6524 	int retries = FW_CMD_HELLO_RETRIES;
6525 
6526 retry:
6527 	memset(&c, 0, sizeof(c));
6528 	INIT_CMD(c, HELLO, WRITE);
6529 	c.err_to_clearinit = cpu_to_be32(
6530 		V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
6531 		V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
6532 		V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
6533 					mbox : M_FW_HELLO_CMD_MBMASTER) |
6534 		V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
6535 		V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
6536 		F_FW_HELLO_CMD_CLEARINIT);
6537 
6538 	/*
6539 	 * Issue the HELLO command to the firmware.  If it's not successful
6540 	 * but indicates that we got a "busy" or "timeout" condition, retry
6541 	 * the HELLO until we exhaust our retry limit.  If we do exceed our
6542 	 * retry limit, check to see if the firmware left us any error
6543 	 * information and report that if so ...
6544 	 */
6545 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6546 	if (ret != FW_SUCCESS) {
6547 		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6548 			goto retry;
6549 		if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
6550 			t4_report_fw_error(adap);
6551 		return ret;
6552 	}
6553 
6554 	v = be32_to_cpu(c.err_to_clearinit);
6555 	master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
6556 	if (state) {
6557 		if (v & F_FW_HELLO_CMD_ERR)
6558 			*state = DEV_STATE_ERR;
6559 		else if (v & F_FW_HELLO_CMD_INIT)
6560 			*state = DEV_STATE_INIT;
6561 		else
6562 			*state = DEV_STATE_UNINIT;
6563 	}
6564 
6565 	/*
6566 	 * If we're not the Master PF then we need to wait around for the
6567 	 * Master PF Driver to finish setting up the adapter.
6568 	 *
6569 	 * Note that we also do this wait if we're a non-Master-capable PF and
6570 	 * there is no current Master PF; a Master PF may show up momentarily
6571 	 * and we wouldn't want to fail pointlessly.  (This can happen when an
6572 	 * OS loads lots of different drivers rapidly at the same time).  In
6573 	 * this case, the Master PF returned by the firmware will be
6574 	 * M_PCIE_FW_MASTER so the test below will work ...
6575 	 */
6576 	if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
6577 	    master_mbox != mbox) {
6578 		int waiting = FW_CMD_HELLO_TIMEOUT;
6579 
6580 		/*
6581 		 * Wait for the firmware to either indicate an error or
6582 		 * initialized state.  If we see either of these we bail out
6583 		 * and report the issue to the caller.  If we exhaust the
6584 		 * "hello timeout" and we haven't exhausted our retries, try
6585 		 * again.  Otherwise bail with a timeout error.
6586 		 */
6587 		for (;;) {
6588 			u32 pcie_fw;
6589 
6590 			msleep(50);
6591 			waiting -= 50;
6592 
6593 			/*
6594 			 * If neither Error nor Initialialized are indicated
6595 			 * by the firmware keep waiting till we exhaust our
6596 			 * timeout ... and then retry if we haven't exhausted
6597 			 * our retries ...
6598 			 */
6599 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
6600 			if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
6601 				if (waiting <= 0) {
6602 					if (retries-- > 0)
6603 						goto retry;
6604 
6605 					return -ETIMEDOUT;
6606 				}
6607 				continue;
6608 			}
6609 
6610 			/*
6611 			 * We either have an Error or Initialized condition
6612 			 * report errors preferentially.
6613 			 */
6614 			if (state) {
6615 				if (pcie_fw & F_PCIE_FW_ERR)
6616 					*state = DEV_STATE_ERR;
6617 				else if (pcie_fw & F_PCIE_FW_INIT)
6618 					*state = DEV_STATE_INIT;
6619 			}
6620 
6621 			/*
6622 			 * If we arrived before a Master PF was selected and
6623 			 * there's not a valid Master PF, grab its identity
6624 			 * for our caller.
6625 			 */
6626 			if (master_mbox == M_PCIE_FW_MASTER &&
6627 			    (pcie_fw & F_PCIE_FW_MASTER_VLD))
6628 				master_mbox = G_PCIE_FW_MASTER(pcie_fw);
6629 			break;
6630 		}
6631 	}
6632 
6633 	return master_mbox;
6634 }
6635 
6636 /**
6637  *	t4_fw_bye - end communication with FW
6638  *	@adap: the adapter
6639  *	@mbox: mailbox to use for the FW command
6640  *
6641  *	Issues a command to terminate communication with FW.
6642  */
6643 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6644 {
6645 	struct fw_bye_cmd c;
6646 
6647 	memset(&c, 0, sizeof(c));
6648 	INIT_CMD(c, BYE, WRITE);
6649 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6650 }
6651 
6652 /**
6653  *	t4_fw_reset - issue a reset to FW
6654  *	@adap: the adapter
6655  *	@mbox: mailbox to use for the FW command
6656  *	@reset: specifies the type of reset to perform
6657  *
6658  *	Issues a reset command of the specified type to FW.
6659  */
6660 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6661 {
6662 	struct fw_reset_cmd c;
6663 
6664 	memset(&c, 0, sizeof(c));
6665 	INIT_CMD(c, RESET, WRITE);
6666 	c.val = cpu_to_be32(reset);
6667 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6668 }
6669 
6670 /**
6671  *	t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6672  *	@adap: the adapter
6673  *	@mbox: mailbox to use for the FW RESET command (if desired)
6674  *	@force: force uP into RESET even if FW RESET command fails
6675  *
6676  *	Issues a RESET command to firmware (if desired) with a HALT indication
6677  *	and then puts the microprocessor into RESET state.  The RESET command
6678  *	will only be issued if a legitimate mailbox is provided (mbox <=
6679  *	M_PCIE_FW_MASTER).
6680  *
6681  *	This is generally used in order for the host to safely manipulate the
6682  *	adapter without fear of conflicting with whatever the firmware might
6683  *	be doing.  The only way out of this state is to RESTART the firmware
6684  *	...
6685  */
6686 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6687 {
6688 	int ret = 0;
6689 
6690 	/*
6691 	 * If a legitimate mailbox is provided, issue a RESET command
6692 	 * with a HALT indication.
6693 	 */
6694 	if (mbox <= M_PCIE_FW_MASTER) {
6695 		struct fw_reset_cmd c;
6696 
6697 		memset(&c, 0, sizeof(c));
6698 		INIT_CMD(c, RESET, WRITE);
6699 		c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
6700 		c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
6701 		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6702 	}
6703 
6704 	/*
6705 	 * Normally we won't complete the operation if the firmware RESET
6706 	 * command fails but if our caller insists we'll go ahead and put the
6707 	 * uP into RESET.  This can be useful if the firmware is hung or even
6708 	 * missing ...  We'll have to take the risk of putting the uP into
6709 	 * RESET without the cooperation of firmware in that case.
6710 	 *
6711 	 * We also force the firmware's HALT flag to be on in case we bypassed
6712 	 * the firmware RESET command above or we're dealing with old firmware
6713 	 * which doesn't have the HALT capability.  This will serve as a flag
6714 	 * for the incoming firmware to know that it's coming out of a HALT
6715 	 * rather than a RESET ... if it's new enough to understand that ...
6716 	 */
6717 	if (ret == 0 || force) {
6718 		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
6719 		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
6720 				 F_PCIE_FW_HALT);
6721 	}
6722 
6723 	/*
6724 	 * And we always return the result of the firmware RESET command
6725 	 * even when we force the uP into RESET ...
6726 	 */
6727 	return ret;
6728 }
6729 
6730 /**
6731  *	t4_fw_restart - restart the firmware by taking the uP out of RESET
6732  *	@adap: the adapter
6733  *	@reset: if we want to do a RESET to restart things
6734  *
6735  *	Restart firmware previously halted by t4_fw_halt().  On successful
6736  *	return the previous PF Master remains as the new PF Master and there
6737  *	is no need to issue a new HELLO command, etc.
6738  *
6739  *	We do this in two ways:
6740  *
6741  *	 1. If we're dealing with newer firmware we'll simply want to take
6742  *	    the chip's microprocessor out of RESET.  This will cause the
6743  *	    firmware to start up from its start vector.  And then we'll loop
6744  *	    until the firmware indicates it's started again (PCIE_FW.HALT
6745  *	    reset to 0) or we timeout.
6746  *
6747  *	 2. If we're dealing with older firmware then we'll need to RESET
6748  *	    the chip since older firmware won't recognize the PCIE_FW.HALT
6749  *	    flag and automatically RESET itself on startup.
6750  */
6751 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6752 {
6753 	if (reset) {
6754 		/*
6755 		 * Since we're directing the RESET instead of the firmware
6756 		 * doing it automatically, we need to clear the PCIE_FW.HALT
6757 		 * bit.
6758 		 */
6759 		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
6760 
6761 		/*
6762 		 * If we've been given a valid mailbox, first try to get the
6763 		 * firmware to do the RESET.  If that works, great and we can
6764 		 * return success.  Otherwise, if we haven't been given a
6765 		 * valid mailbox or the RESET command failed, fall back to
6766 		 * hitting the chip with a hammer.
6767 		 */
6768 		if (mbox <= M_PCIE_FW_MASTER) {
6769 			t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6770 			msleep(100);
6771 			if (t4_fw_reset(adap, mbox,
6772 					F_PIORST | F_PIORSTMODE) == 0)
6773 				return 0;
6774 		}
6775 
6776 		t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
6777 		msleep(2000);
6778 	} else {
6779 		int ms;
6780 
6781 		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6782 		for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6783 			if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
6784 				return FW_SUCCESS;
6785 			msleep(100);
6786 			ms += 100;
6787 		}
6788 		return -ETIMEDOUT;
6789 	}
6790 	return 0;
6791 }
6792 
6793 /**
6794  *	t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6795  *	@adap: the adapter
6796  *	@mbox: mailbox to use for the FW RESET command (if desired)
6797  *	@fw_data: the firmware image to write
6798  *	@size: image size
6799  *	@force: force upgrade even if firmware doesn't cooperate
6800  *
6801  *	Perform all of the steps necessary for upgrading an adapter's
6802  *	firmware image.  Normally this requires the cooperation of the
6803  *	existing firmware in order to halt all existing activities
6804  *	but if an invalid mailbox token is passed in we skip that step
6805  *	(though we'll still put the adapter microprocessor into RESET in
6806  *	that case).
6807  *
6808  *	On successful return the new firmware will have been loaded and
6809  *	the adapter will have been fully RESET losing all previous setup
6810  *	state.  On unsuccessful return the adapter may be completely hosed ...
6811  *	positive errno indicates that the adapter is ~probably~ intact, a
6812  *	negative errno indicates that things are looking bad ...
6813  */
6814 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6815 		  const u8 *fw_data, unsigned int size, int force)
6816 {
6817 	const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6818 	unsigned int bootstrap =
6819 	    be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
6820 	int reset, ret;
6821 
6822 	if (!t4_fw_matches_chip(adap, fw_hdr))
6823 		return -EINVAL;
6824 
6825 	if (!bootstrap) {
6826 		ret = t4_fw_halt(adap, mbox, force);
6827 		if (ret < 0 && !force)
6828 			return ret;
6829 	}
6830 
6831 	ret = t4_load_fw(adap, fw_data, size);
6832 	if (ret < 0 || bootstrap)
6833 		return ret;
6834 
6835 	/*
6836 	 * Older versions of the firmware don't understand the new
6837 	 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6838 	 * restart.  So for newly loaded older firmware we'll have to do the
6839 	 * RESET for it so it starts up on a clean slate.  We can tell if
6840 	 * the newly loaded firmware will handle this right by checking
6841 	 * its header flags to see if it advertises the capability.
6842 	 */
6843 	reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6844 	return t4_fw_restart(adap, mbox, reset);
6845 }
6846 
6847 /*
6848  * Card doesn't have a firmware, install one.
6849  */
6850 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data,
6851     unsigned int size)
6852 {
6853 	const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6854 	unsigned int bootstrap =
6855 	    be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
6856 	int ret;
6857 
6858 	if (!t4_fw_matches_chip(adap, fw_hdr) || bootstrap)
6859 		return -EINVAL;
6860 
6861 	t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
6862 	t4_write_reg(adap, A_PCIE_FW, 0);	/* Clobber internal state */
6863 	ret = t4_load_fw(adap, fw_data, size);
6864 	if (ret < 0)
6865 		return ret;
6866 	t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
6867 	msleep(1000);
6868 
6869 	return (0);
6870 }
6871 
6872 /**
6873  *	t4_fw_initialize - ask FW to initialize the device
6874  *	@adap: the adapter
6875  *	@mbox: mailbox to use for the FW command
6876  *
6877  *	Issues a command to FW to partially initialize the device.  This
6878  *	performs initialization that generally doesn't depend on user input.
6879  */
6880 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6881 {
6882 	struct fw_initialize_cmd c;
6883 
6884 	memset(&c, 0, sizeof(c));
6885 	INIT_CMD(c, INITIALIZE, WRITE);
6886 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6887 }
6888 
6889 /**
6890  *	t4_query_params_rw - query FW or device parameters
6891  *	@adap: the adapter
6892  *	@mbox: mailbox to use for the FW command
6893  *	@pf: the PF
6894  *	@vf: the VF
6895  *	@nparams: the number of parameters
6896  *	@params: the parameter names
6897  *	@val: the parameter values
6898  *	@rw: Write and read flag
6899  *
6900  *	Reads the value of FW or device parameters.  Up to 7 parameters can be
6901  *	queried at once.
6902  */
6903 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6904 		       unsigned int vf, unsigned int nparams, const u32 *params,
6905 		       u32 *val, int rw)
6906 {
6907 	int i, ret;
6908 	struct fw_params_cmd c;
6909 	__be32 *p = &c.param[0].mnem;
6910 
6911 	if (nparams > 7)
6912 		return -EINVAL;
6913 
6914 	memset(&c, 0, sizeof(c));
6915 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6916 				  F_FW_CMD_REQUEST | F_FW_CMD_READ |
6917 				  V_FW_PARAMS_CMD_PFN(pf) |
6918 				  V_FW_PARAMS_CMD_VFN(vf));
6919 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6920 
6921 	for (i = 0; i < nparams; i++) {
6922 		*p++ = cpu_to_be32(*params++);
6923 		if (rw)
6924 			*p = cpu_to_be32(*(val + i));
6925 		p++;
6926 	}
6927 
6928 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6929 	if (ret == 0)
6930 		for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6931 			*val++ = be32_to_cpu(*p);
6932 	return ret;
6933 }
6934 
6935 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6936 		    unsigned int vf, unsigned int nparams, const u32 *params,
6937 		    u32 *val)
6938 {
6939 	return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6940 }
6941 
6942 /**
6943  *      t4_set_params_timeout - sets FW or device parameters
6944  *      @adap: the adapter
6945  *      @mbox: mailbox to use for the FW command
6946  *      @pf: the PF
6947  *      @vf: the VF
6948  *      @nparams: the number of parameters
6949  *      @params: the parameter names
6950  *      @val: the parameter values
6951  *      @timeout: the timeout time
6952  *
6953  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6954  *      specified at once.
6955  */
6956 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6957 			  unsigned int pf, unsigned int vf,
6958 			  unsigned int nparams, const u32 *params,
6959 			  const u32 *val, int timeout)
6960 {
6961 	struct fw_params_cmd c;
6962 	__be32 *p = &c.param[0].mnem;
6963 
6964 	if (nparams > 7)
6965 		return -EINVAL;
6966 
6967 	memset(&c, 0, sizeof(c));
6968 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6969 				  F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6970 				  V_FW_PARAMS_CMD_PFN(pf) |
6971 				  V_FW_PARAMS_CMD_VFN(vf));
6972 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6973 
6974 	while (nparams--) {
6975 		*p++ = cpu_to_be32(*params++);
6976 		*p++ = cpu_to_be32(*val++);
6977 	}
6978 
6979 	return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6980 }
6981 
6982 /**
6983  *	t4_set_params - sets FW or device parameters
6984  *	@adap: the adapter
6985  *	@mbox: mailbox to use for the FW command
6986  *	@pf: the PF
6987  *	@vf: the VF
6988  *	@nparams: the number of parameters
6989  *	@params: the parameter names
6990  *	@val: the parameter values
6991  *
6992  *	Sets the value of FW or device parameters.  Up to 7 parameters can be
6993  *	specified at once.
6994  */
6995 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6996 		  unsigned int vf, unsigned int nparams, const u32 *params,
6997 		  const u32 *val)
6998 {
6999 	return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7000 				     FW_CMD_MAX_TIMEOUT);
7001 }
7002 
7003 /**
7004  *	t4_cfg_pfvf - configure PF/VF resource limits
7005  *	@adap: the adapter
7006  *	@mbox: mailbox to use for the FW command
7007  *	@pf: the PF being configured
7008  *	@vf: the VF being configured
7009  *	@txq: the max number of egress queues
7010  *	@txq_eth_ctrl: the max number of egress Ethernet or control queues
7011  *	@rxqi: the max number of interrupt-capable ingress queues
7012  *	@rxq: the max number of interruptless ingress queues
7013  *	@tc: the PCI traffic class
7014  *	@vi: the max number of virtual interfaces
7015  *	@cmask: the channel access rights mask for the PF/VF
7016  *	@pmask: the port access rights mask for the PF/VF
7017  *	@nexact: the maximum number of exact MPS filters
7018  *	@rcaps: read capabilities
7019  *	@wxcaps: write/execute capabilities
7020  *
7021  *	Configures resource limits and capabilities for a physical or virtual
7022  *	function.
7023  */
7024 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7025 		unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7026 		unsigned int rxqi, unsigned int rxq, unsigned int tc,
7027 		unsigned int vi, unsigned int cmask, unsigned int pmask,
7028 		unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7029 {
7030 	struct fw_pfvf_cmd c;
7031 
7032 	memset(&c, 0, sizeof(c));
7033 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
7034 				  F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
7035 				  V_FW_PFVF_CMD_VFN(vf));
7036 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7037 	c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
7038 				     V_FW_PFVF_CMD_NIQ(rxq));
7039 	c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
7040 				    V_FW_PFVF_CMD_PMASK(pmask) |
7041 				    V_FW_PFVF_CMD_NEQ(txq));
7042 	c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
7043 				      V_FW_PFVF_CMD_NVI(vi) |
7044 				      V_FW_PFVF_CMD_NEXACTF(nexact));
7045 	c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
7046 				     V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
7047 				     V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
7048 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7049 }
7050 
7051 /**
7052  *	t4_alloc_vi_func - allocate a virtual interface
7053  *	@adap: the adapter
7054  *	@mbox: mailbox to use for the FW command
7055  *	@port: physical port associated with the VI
7056  *	@pf: the PF owning the VI
7057  *	@vf: the VF owning the VI
7058  *	@nmac: number of MAC addresses needed (1 to 5)
7059  *	@mac: the MAC addresses of the VI
7060  *	@rss_size: size of RSS table slice associated with this VI
7061  *	@portfunc: which Port Application Function MAC Address is desired
7062  *	@idstype: Intrusion Detection Type
7063  *
7064  *	Allocates a virtual interface for the given physical port.  If @mac is
7065  *	not %NULL it contains the MAC addresses of the VI as assigned by FW.
7066  *	If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
7067  *	@mac should be large enough to hold @nmac Ethernet addresses, they are
7068  *	stored consecutively so the space needed is @nmac * 6 bytes.
7069  *	Returns a negative error number or the non-negative VI id.
7070  */
7071 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
7072 		     unsigned int port, unsigned int pf, unsigned int vf,
7073 		     unsigned int nmac, u8 *mac, u16 *rss_size,
7074 		     unsigned int portfunc, unsigned int idstype)
7075 {
7076 	int ret;
7077 	struct fw_vi_cmd c;
7078 
7079 	memset(&c, 0, sizeof(c));
7080 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
7081 				  F_FW_CMD_WRITE | F_FW_CMD_EXEC |
7082 				  V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
7083 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
7084 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
7085 				     V_FW_VI_CMD_FUNC(portfunc));
7086 	c.portid_pkd = V_FW_VI_CMD_PORTID(port);
7087 	c.nmac = nmac - 1;
7088 	if(!rss_size)
7089 		c.norss_rsssize = F_FW_VI_CMD_NORSS;
7090 
7091 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7092 	if (ret)
7093 		return ret;
7094 
7095 	if (mac) {
7096 		memcpy(mac, c.mac, sizeof(c.mac));
7097 		switch (nmac) {
7098 		case 5:
7099 			memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7100 		case 4:
7101 			memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7102 		case 3:
7103 			memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7104 		case 2:
7105 			memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7106 		}
7107 	}
7108 	if (rss_size)
7109 		*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
7110 	return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
7111 }
7112 
7113 /**
7114  *      t4_alloc_vi - allocate an [Ethernet Function] virtual interface
7115  *      @adap: the adapter
7116  *      @mbox: mailbox to use for the FW command
7117  *      @port: physical port associated with the VI
7118  *      @pf: the PF owning the VI
7119  *      @vf: the VF owning the VI
7120  *      @nmac: number of MAC addresses needed (1 to 5)
7121  *      @mac: the MAC addresses of the VI
7122  *      @rss_size: size of RSS table slice associated with this VI
7123  *
7124  *	backwards compatible and convieniance routine to allocate a Virtual
7125  *	Interface with a Ethernet Port Application Function and Intrustion
7126  *	Detection System disabled.
7127  */
7128 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7129 		unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7130 		u16 *rss_size)
7131 {
7132 	return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
7133 				FW_VI_FUNC_ETH, 0);
7134 }
7135 
7136 /**
7137  * 	t4_free_vi - free a virtual interface
7138  * 	@adap: the adapter
7139  * 	@mbox: mailbox to use for the FW command
7140  * 	@pf: the PF owning the VI
7141  * 	@vf: the VF owning the VI
7142  * 	@viid: virtual interface identifiler
7143  *
7144  * 	Free a previously allocated virtual interface.
7145  */
7146 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7147 	       unsigned int vf, unsigned int viid)
7148 {
7149 	struct fw_vi_cmd c;
7150 
7151 	memset(&c, 0, sizeof(c));
7152 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
7153 				  F_FW_CMD_REQUEST |
7154 				  F_FW_CMD_EXEC |
7155 				  V_FW_VI_CMD_PFN(pf) |
7156 				  V_FW_VI_CMD_VFN(vf));
7157 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
7158 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
7159 
7160 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7161 }
7162 
7163 /**
7164  *	t4_set_rxmode - set Rx properties of a virtual interface
7165  *	@adap: the adapter
7166  *	@mbox: mailbox to use for the FW command
7167  *	@viid: the VI id
7168  *	@mtu: the new MTU or -1
7169  *	@promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7170  *	@all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7171  *	@bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7172  *	@vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7173  *	@sleep_ok: if true we may sleep while awaiting command completion
7174  *
7175  *	Sets Rx properties of a virtual interface.
7176  */
7177 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7178 		  int mtu, int promisc, int all_multi, int bcast, int vlanex,
7179 		  bool sleep_ok)
7180 {
7181 	struct fw_vi_rxmode_cmd c;
7182 
7183 	/* convert to FW values */
7184 	if (mtu < 0)
7185 		mtu = M_FW_VI_RXMODE_CMD_MTU;
7186 	if (promisc < 0)
7187 		promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
7188 	if (all_multi < 0)
7189 		all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
7190 	if (bcast < 0)
7191 		bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
7192 	if (vlanex < 0)
7193 		vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
7194 
7195 	memset(&c, 0, sizeof(c));
7196 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
7197 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7198 				   V_FW_VI_RXMODE_CMD_VIID(viid));
7199 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7200 	c.mtu_to_vlanexen =
7201 		cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
7202 			    V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
7203 			    V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
7204 			    V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
7205 			    V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
7206 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7207 }
7208 
7209 /**
7210  *	t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7211  *	@adap: the adapter
7212  *	@mbox: mailbox to use for the FW command
7213  *	@viid: the VI id
7214  *	@free: if true any existing filters for this VI id are first removed
7215  *	@naddr: the number of MAC addresses to allocate filters for (up to 7)
7216  *	@addr: the MAC address(es)
7217  *	@idx: where to store the index of each allocated filter
7218  *	@hash: pointer to hash address filter bitmap
7219  *	@sleep_ok: call is allowed to sleep
7220  *
7221  *	Allocates an exact-match filter for each of the supplied addresses and
7222  *	sets it to the corresponding address.  If @idx is not %NULL it should
7223  *	have at least @naddr entries, each of which will be set to the index of
7224  *	the filter allocated for the corresponding MAC address.  If a filter
7225  *	could not be allocated for an address its index is set to 0xffff.
7226  *	If @hash is not %NULL addresses that fail to allocate an exact filter
7227  *	are hashed and update the hash filter bitmap pointed at by @hash.
7228  *
7229  *	Returns a negative error number or the number of filters allocated.
7230  */
7231 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7232 		      unsigned int viid, bool free, unsigned int naddr,
7233 		      const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7234 {
7235 	int offset, ret = 0;
7236 	struct fw_vi_mac_cmd c;
7237 	unsigned int nfilters = 0;
7238 	unsigned int max_naddr = adap->chip_params->mps_tcam_size;
7239 	unsigned int rem = naddr;
7240 
7241 	if (naddr > max_naddr)
7242 		return -EINVAL;
7243 
7244 	for (offset = 0; offset < naddr ; /**/) {
7245 		unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7246 					 ? rem
7247 					 : ARRAY_SIZE(c.u.exact));
7248 		size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7249 						     u.exact[fw_naddr]), 16);
7250 		struct fw_vi_mac_exact *p;
7251 		int i;
7252 
7253 		memset(&c, 0, sizeof(c));
7254 		c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7255 					   F_FW_CMD_REQUEST |
7256 					   F_FW_CMD_WRITE |
7257 					   V_FW_CMD_EXEC(free) |
7258 					   V_FW_VI_MAC_CMD_VIID(viid));
7259 		c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
7260 						  V_FW_CMD_LEN16(len16));
7261 
7262 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7263 			p->valid_to_idx =
7264 				cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
7265 					    V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
7266 			memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7267 		}
7268 
7269 		/*
7270 		 * It's okay if we run out of space in our MAC address arena.
7271 		 * Some of the addresses we submit may get stored so we need
7272 		 * to run through the reply to see what the results were ...
7273 		 */
7274 		ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7275 		if (ret && ret != -FW_ENOMEM)
7276 			break;
7277 
7278 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7279 			u16 index = G_FW_VI_MAC_CMD_IDX(
7280 						be16_to_cpu(p->valid_to_idx));
7281 
7282 			if (idx)
7283 				idx[offset+i] = (index >=  max_naddr
7284 						 ? 0xffff
7285 						 : index);
7286 			if (index < max_naddr)
7287 				nfilters++;
7288 			else if (hash)
7289 				*hash |= (1ULL << hash_mac_addr(addr[offset+i]));
7290 		}
7291 
7292 		free = false;
7293 		offset += fw_naddr;
7294 		rem -= fw_naddr;
7295 	}
7296 
7297 	if (ret == 0 || ret == -FW_ENOMEM)
7298 		ret = nfilters;
7299 	return ret;
7300 }
7301 
7302 /**
7303  *	t4_change_mac - modifies the exact-match filter for a MAC address
7304  *	@adap: the adapter
7305  *	@mbox: mailbox to use for the FW command
7306  *	@viid: the VI id
7307  *	@idx: index of existing filter for old value of MAC address, or -1
7308  *	@addr: the new MAC address value
7309  *	@persist: whether a new MAC allocation should be persistent
7310  *	@add_smt: if true also add the address to the HW SMT
7311  *
7312  *	Modifies an exact-match filter and sets it to the new MAC address if
7313  *	@idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
7314  *	latter case the address is added persistently if @persist is %true.
7315  *
7316  *	Note that in general it is not possible to modify the value of a given
7317  *	filter so the generic way to modify an address filter is to free the one
7318  *	being used by the old address value and allocate a new filter for the
7319  *	new address value.
7320  *
7321  *	Returns a negative error number or the index of the filter with the new
7322  *	MAC value.  Note that this index may differ from @idx.
7323  */
7324 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7325 		  int idx, const u8 *addr, bool persist, bool add_smt)
7326 {
7327 	int ret, mode;
7328 	struct fw_vi_mac_cmd c;
7329 	struct fw_vi_mac_exact *p = c.u.exact;
7330 	unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
7331 
7332 	if (idx < 0)		/* new allocation */
7333 		idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7334 	mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7335 
7336 	memset(&c, 0, sizeof(c));
7337 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7338 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7339 				   V_FW_VI_MAC_CMD_VIID(viid));
7340 	c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
7341 	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
7342 				      V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
7343 				      V_FW_VI_MAC_CMD_IDX(idx));
7344 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
7345 
7346 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7347 	if (ret == 0) {
7348 		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
7349 		if (ret >= max_mac_addr)
7350 			ret = -ENOMEM;
7351 	}
7352 	return ret;
7353 }
7354 
7355 /**
7356  *	t4_set_addr_hash - program the MAC inexact-match hash filter
7357  *	@adap: the adapter
7358  *	@mbox: mailbox to use for the FW command
7359  *	@viid: the VI id
7360  *	@ucast: whether the hash filter should also match unicast addresses
7361  *	@vec: the value to be written to the hash filter
7362  *	@sleep_ok: call is allowed to sleep
7363  *
7364  *	Sets the 64-bit inexact-match hash filter for a virtual interface.
7365  */
7366 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7367 		     bool ucast, u64 vec, bool sleep_ok)
7368 {
7369 	struct fw_vi_mac_cmd c;
7370 	u32 val;
7371 
7372 	memset(&c, 0, sizeof(c));
7373 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7374 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7375 				   V_FW_VI_ENABLE_CMD_VIID(viid));
7376 	val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
7377 	      V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
7378 	c.freemacs_to_len16 = cpu_to_be32(val);
7379 	c.u.hash.hashvec = cpu_to_be64(vec);
7380 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7381 }
7382 
7383 /**
7384  *      t4_enable_vi_params - enable/disable a virtual interface
7385  *      @adap: the adapter
7386  *      @mbox: mailbox to use for the FW command
7387  *      @viid: the VI id
7388  *      @rx_en: 1=enable Rx, 0=disable Rx
7389  *      @tx_en: 1=enable Tx, 0=disable Tx
7390  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7391  *
7392  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7393  *      only makes sense when enabling a Virtual Interface ...
7394  */
7395 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7396 			unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7397 {
7398 	struct fw_vi_enable_cmd c;
7399 
7400 	memset(&c, 0, sizeof(c));
7401 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7402 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7403 				   V_FW_VI_ENABLE_CMD_VIID(viid));
7404 	c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
7405 				     V_FW_VI_ENABLE_CMD_EEN(tx_en) |
7406 				     V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
7407 				     FW_LEN16(c));
7408 	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7409 }
7410 
7411 /**
7412  *	t4_enable_vi - enable/disable a virtual interface
7413  *	@adap: the adapter
7414  *	@mbox: mailbox to use for the FW command
7415  *	@viid: the VI id
7416  *	@rx_en: 1=enable Rx, 0=disable Rx
7417  *	@tx_en: 1=enable Tx, 0=disable Tx
7418  *
7419  *	Enables/disables a virtual interface.  Note that setting DCB Enable
7420  *	only makes sense when enabling a Virtual Interface ...
7421  */
7422 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7423 		 bool rx_en, bool tx_en)
7424 {
7425 	return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7426 }
7427 
7428 /**
7429  *	t4_identify_port - identify a VI's port by blinking its LED
7430  *	@adap: the adapter
7431  *	@mbox: mailbox to use for the FW command
7432  *	@viid: the VI id
7433  *	@nblinks: how many times to blink LED at 2.5 Hz
7434  *
7435  *	Identifies a VI's port by blinking its LED.
7436  */
7437 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7438 		     unsigned int nblinks)
7439 {
7440 	struct fw_vi_enable_cmd c;
7441 
7442 	memset(&c, 0, sizeof(c));
7443 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7444 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7445 				   V_FW_VI_ENABLE_CMD_VIID(viid));
7446 	c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
7447 	c.blinkdur = cpu_to_be16(nblinks);
7448 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7449 }
7450 
7451 /**
7452  *	t4_iq_stop - stop an ingress queue and its FLs
7453  *	@adap: the adapter
7454  *	@mbox: mailbox to use for the FW command
7455  *	@pf: the PF owning the queues
7456  *	@vf: the VF owning the queues
7457  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7458  *	@iqid: ingress queue id
7459  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
7460  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
7461  *
7462  *	Stops an ingress queue and its associated FLs, if any.  This causes
7463  *	any current or future data/messages destined for these queues to be
7464  *	tossed.
7465  */
7466 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7467 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
7468 	       unsigned int fl0id, unsigned int fl1id)
7469 {
7470 	struct fw_iq_cmd c;
7471 
7472 	memset(&c, 0, sizeof(c));
7473 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7474 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7475 				  V_FW_IQ_CMD_VFN(vf));
7476 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
7477 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7478 	c.iqid = cpu_to_be16(iqid);
7479 	c.fl0id = cpu_to_be16(fl0id);
7480 	c.fl1id = cpu_to_be16(fl1id);
7481 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7482 }
7483 
7484 /**
7485  *	t4_iq_free - free an ingress queue and its FLs
7486  *	@adap: the adapter
7487  *	@mbox: mailbox to use for the FW command
7488  *	@pf: the PF owning the queues
7489  *	@vf: the VF owning the queues
7490  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7491  *	@iqid: ingress queue id
7492  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
7493  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
7494  *
7495  *	Frees an ingress queue and its associated FLs, if any.
7496  */
7497 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7498 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
7499 	       unsigned int fl0id, unsigned int fl1id)
7500 {
7501 	struct fw_iq_cmd c;
7502 
7503 	memset(&c, 0, sizeof(c));
7504 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7505 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7506 				  V_FW_IQ_CMD_VFN(vf));
7507 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
7508 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7509 	c.iqid = cpu_to_be16(iqid);
7510 	c.fl0id = cpu_to_be16(fl0id);
7511 	c.fl1id = cpu_to_be16(fl1id);
7512 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7513 }
7514 
7515 /**
7516  *	t4_eth_eq_free - free an Ethernet egress queue
7517  *	@adap: the adapter
7518  *	@mbox: mailbox to use for the FW command
7519  *	@pf: the PF owning the queue
7520  *	@vf: the VF owning the queue
7521  *	@eqid: egress queue id
7522  *
7523  *	Frees an Ethernet egress queue.
7524  */
7525 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7526 		   unsigned int vf, unsigned int eqid)
7527 {
7528 	struct fw_eq_eth_cmd c;
7529 
7530 	memset(&c, 0, sizeof(c));
7531 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
7532 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7533 				  V_FW_EQ_ETH_CMD_PFN(pf) |
7534 				  V_FW_EQ_ETH_CMD_VFN(vf));
7535 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
7536 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
7537 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7538 }
7539 
7540 /**
7541  *	t4_ctrl_eq_free - free a control egress queue
7542  *	@adap: the adapter
7543  *	@mbox: mailbox to use for the FW command
7544  *	@pf: the PF owning the queue
7545  *	@vf: the VF owning the queue
7546  *	@eqid: egress queue id
7547  *
7548  *	Frees a control egress queue.
7549  */
7550 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7551 		    unsigned int vf, unsigned int eqid)
7552 {
7553 	struct fw_eq_ctrl_cmd c;
7554 
7555 	memset(&c, 0, sizeof(c));
7556 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
7557 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7558 				  V_FW_EQ_CTRL_CMD_PFN(pf) |
7559 				  V_FW_EQ_CTRL_CMD_VFN(vf));
7560 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
7561 	c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
7562 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7563 }
7564 
7565 /**
7566  *	t4_ofld_eq_free - free an offload egress queue
7567  *	@adap: the adapter
7568  *	@mbox: mailbox to use for the FW command
7569  *	@pf: the PF owning the queue
7570  *	@vf: the VF owning the queue
7571  *	@eqid: egress queue id
7572  *
7573  *	Frees a control egress queue.
7574  */
7575 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7576 		    unsigned int vf, unsigned int eqid)
7577 {
7578 	struct fw_eq_ofld_cmd c;
7579 
7580 	memset(&c, 0, sizeof(c));
7581 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
7582 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7583 				  V_FW_EQ_OFLD_CMD_PFN(pf) |
7584 				  V_FW_EQ_OFLD_CMD_VFN(vf));
7585 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
7586 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
7587 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7588 }
7589 
7590 /**
7591  *	t4_link_down_rc_str - return a string for a Link Down Reason Code
7592  *	@link_down_rc: Link Down Reason Code
7593  *
7594  *	Returns a string representation of the Link Down Reason Code.
7595  */
7596 const char *t4_link_down_rc_str(unsigned char link_down_rc)
7597 {
7598 	static const char *reason[] = {
7599 		"Link Down",
7600 		"Remote Fault",
7601 		"Auto-negotiation Failure",
7602 		"Reserved3",
7603 		"Insufficient Airflow",
7604 		"Unable To Determine Reason",
7605 		"No RX Signal Detected",
7606 		"Reserved7",
7607 	};
7608 
7609 	if (link_down_rc >= ARRAY_SIZE(reason))
7610 		return "Bad Reason Code";
7611 
7612 	return reason[link_down_rc];
7613 }
7614 
7615 /*
7616  * Updates all fields owned by the common code in port_info and link_config
7617  * based on information provided by the firmware.  Does not touch any
7618  * requested_* field.
7619  */
7620 static void handle_port_info(struct port_info *pi, const struct fw_port_info *p)
7621 {
7622 	struct link_config *lc = &pi->link_cfg;
7623 	int speed;
7624 	unsigned char fc, fec;
7625 	u32 stat = be32_to_cpu(p->lstatus_to_modtype);
7626 
7627 	pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
7628 	pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
7629 	pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
7630 	    G_FW_PORT_CMD_MDIOADDR(stat) : -1;
7631 
7632 	lc->supported = be16_to_cpu(p->pcap);
7633 	lc->advertising = be16_to_cpu(p->acap);
7634 	lc->lp_advertising = be16_to_cpu(p->lpacap);
7635 	lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
7636 	lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
7637 
7638 	speed = 0;
7639 	if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
7640 		speed = 100;
7641 	else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
7642 		speed = 1000;
7643 	else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
7644 		speed = 10000;
7645 	else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
7646 		speed = 25000;
7647 	else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
7648 		speed = 40000;
7649 	else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
7650 		speed = 100000;
7651 	lc->speed = speed;
7652 
7653 	fc = 0;
7654 	if (stat & F_FW_PORT_CMD_RXPAUSE)
7655 		fc |= PAUSE_RX;
7656 	if (stat & F_FW_PORT_CMD_TXPAUSE)
7657 		fc |= PAUSE_TX;
7658 	lc->fc = fc;
7659 
7660 	fec = 0;
7661 	if (lc->advertising & FW_PORT_CAP_FEC_RS)
7662 		fec |= FEC_RS;
7663 	if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS)
7664 		fec |= FEC_BASER_RS;
7665 	if (lc->advertising & FW_PORT_CAP_FEC_RESERVED)
7666 		fec |= FEC_RESERVED;
7667 	lc->fec = fec;
7668 }
7669 
7670 /**
7671  *	t4_update_port_info - retrieve and update port information if changed
7672  *	@pi: the port_info
7673  *
7674  *	We issue a Get Port Information Command to the Firmware and, if
7675  *	successful, we check to see if anything is different from what we
7676  *	last recorded and update things accordingly.
7677  */
7678  int t4_update_port_info(struct port_info *pi)
7679  {
7680 	struct fw_port_cmd port_cmd;
7681 	int ret;
7682 
7683 	memset(&port_cmd, 0, sizeof port_cmd);
7684 	port_cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
7685 					    F_FW_CMD_REQUEST | F_FW_CMD_READ |
7686 					    V_FW_PORT_CMD_PORTID(pi->tx_chan));
7687 	port_cmd.action_to_len16 = cpu_to_be32(
7688 		V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
7689 		FW_LEN16(port_cmd));
7690 	ret = t4_wr_mbox_ns(pi->adapter, pi->adapter->mbox,
7691 			 &port_cmd, sizeof(port_cmd), &port_cmd);
7692 	if (ret)
7693 		return ret;
7694 
7695 	handle_port_info(pi, &port_cmd.u.info);
7696 	return 0;
7697 }
7698 
7699 /**
7700  *	t4_handle_fw_rpl - process a FW reply message
7701  *	@adap: the adapter
7702  *	@rpl: start of the FW message
7703  *
7704  *	Processes a FW message, such as link state change messages.
7705  */
7706 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7707 {
7708 	u8 opcode = *(const u8 *)rpl;
7709 	const struct fw_port_cmd *p = (const void *)rpl;
7710 	unsigned int action =
7711 			G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
7712 
7713 	if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7714 		/* link/module state change message */
7715 		int i, old_ptype, old_mtype;
7716 		int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
7717 		struct port_info *pi = NULL;
7718 		struct link_config *lc, old_lc;
7719 
7720 		for_each_port(adap, i) {
7721 			pi = adap2pinfo(adap, i);
7722 			if (pi->tx_chan == chan)
7723 				break;
7724 		}
7725 
7726 		lc = &pi->link_cfg;
7727 		old_lc = *lc;
7728 		old_ptype = pi->port_type;
7729 		old_mtype = pi->mod_type;
7730 
7731 		handle_port_info(pi, &p->u.info);
7732 		if (old_ptype != pi->port_type || old_mtype != pi->mod_type) {
7733 			t4_os_portmod_changed(pi, old_ptype, old_mtype,
7734 			    &old_lc);
7735 		}
7736 		if (old_lc.link_ok != lc->link_ok ||
7737 		    old_lc.speed != lc->speed ||
7738 		    old_lc.fc != lc->fc) {
7739 			t4_os_link_changed(pi, &old_lc);
7740 		}
7741 	} else {
7742 		CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
7743 		return -EINVAL;
7744 	}
7745 	return 0;
7746 }
7747 
7748 /**
7749  *	get_pci_mode - determine a card's PCI mode
7750  *	@adapter: the adapter
7751  *	@p: where to store the PCI settings
7752  *
7753  *	Determines a card's PCI mode and associated parameters, such as speed
7754  *	and width.
7755  */
7756 static void get_pci_mode(struct adapter *adapter,
7757 				   struct pci_params *p)
7758 {
7759 	u16 val;
7760 	u32 pcie_cap;
7761 
7762 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7763 	if (pcie_cap) {
7764 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
7765 		p->speed = val & PCI_EXP_LNKSTA_CLS;
7766 		p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7767 	}
7768 }
7769 
7770 struct flash_desc {
7771 	u32 vendor_and_model_id;
7772 	u32 size_mb;
7773 };
7774 
7775 int t4_get_flash_params(struct adapter *adapter)
7776 {
7777 	/*
7778 	 * Table for non-standard supported Flash parts.  Note, all Flash
7779 	 * parts must have 64KB sectors.
7780 	 */
7781 	static struct flash_desc supported_flash[] = {
7782 		{ 0x00150201, 4 << 20 },	/* Spansion 4MB S25FL032P */
7783 	};
7784 
7785 	int ret;
7786 	u32 flashid = 0;
7787 	unsigned int part, manufacturer;
7788 	unsigned int density, size;
7789 
7790 
7791 	/*
7792 	 * Issue a Read ID Command to the Flash part.  We decode supported
7793 	 * Flash parts and their sizes from this.  There's a newer Query
7794 	 * Command which can retrieve detailed geometry information but many
7795 	 * Flash parts don't support it.
7796 	 */
7797 	ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
7798 	if (!ret)
7799 		ret = sf1_read(adapter, 3, 0, 1, &flashid);
7800 	t4_write_reg(adapter, A_SF_OP, 0);	/* unlock SF */
7801 	if (ret < 0)
7802 		return ret;
7803 
7804 	/*
7805 	 * Check to see if it's one of our non-standard supported Flash parts.
7806 	 */
7807 	for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
7808 		if (supported_flash[part].vendor_and_model_id == flashid) {
7809 			adapter->params.sf_size =
7810 				supported_flash[part].size_mb;
7811 			adapter->params.sf_nsec =
7812 				adapter->params.sf_size / SF_SEC_SIZE;
7813 			goto found;
7814 		}
7815 
7816 	/*
7817 	 * Decode Flash part size.  The code below looks repetative with
7818 	 * common encodings, but that's not guaranteed in the JEDEC
7819 	 * specification for the Read JADEC ID command.  The only thing that
7820 	 * we're guaranteed by the JADEC specification is where the
7821 	 * Manufacturer ID is in the returned result.  After that each
7822 	 * Manufacturer ~could~ encode things completely differently.
7823 	 * Note, all Flash parts must have 64KB sectors.
7824 	 */
7825 	manufacturer = flashid & 0xff;
7826 	switch (manufacturer) {
7827 	case 0x20: { /* Micron/Numonix */
7828 		/*
7829 		 * This Density -> Size decoding table is taken from Micron
7830 		 * Data Sheets.
7831 		 */
7832 		density = (flashid >> 16) & 0xff;
7833 		switch (density) {
7834 		case 0x14: size = 1 << 20; break; /*   1MB */
7835 		case 0x15: size = 1 << 21; break; /*   2MB */
7836 		case 0x16: size = 1 << 22; break; /*   4MB */
7837 		case 0x17: size = 1 << 23; break; /*   8MB */
7838 		case 0x18: size = 1 << 24; break; /*  16MB */
7839 		case 0x19: size = 1 << 25; break; /*  32MB */
7840 		case 0x20: size = 1 << 26; break; /*  64MB */
7841 		case 0x21: size = 1 << 27; break; /* 128MB */
7842 		case 0x22: size = 1 << 28; break; /* 256MB */
7843 
7844 		default:
7845 			CH_ERR(adapter, "Micron Flash Part has bad size, "
7846 			       "ID = %#x, Density code = %#x\n",
7847 			       flashid, density);
7848 			return -EINVAL;
7849 		}
7850 		break;
7851 	}
7852 
7853 	case 0xef: { /* Winbond */
7854 		/*
7855 		 * This Density -> Size decoding table is taken from Winbond
7856 		 * Data Sheets.
7857 		 */
7858 		density = (flashid >> 16) & 0xff;
7859 		switch (density) {
7860 		case 0x17: size = 1 << 23; break; /*   8MB */
7861 		case 0x18: size = 1 << 24; break; /*  16MB */
7862 
7863 		default:
7864 			CH_ERR(adapter, "Winbond Flash Part has bad size, "
7865 			       "ID = %#x, Density code = %#x\n",
7866 			       flashid, density);
7867 			return -EINVAL;
7868 		}
7869 		break;
7870 	}
7871 
7872 	default:
7873 		CH_ERR(adapter, "Unsupported Flash Part, ID = %#x\n", flashid);
7874 		return -EINVAL;
7875 	}
7876 
7877 	/*
7878 	 * Store decoded Flash size and fall through into vetting code.
7879 	 */
7880 	adapter->params.sf_size = size;
7881 	adapter->params.sf_nsec = size / SF_SEC_SIZE;
7882 
7883  found:
7884 	/*
7885 	 * We should ~probably~ reject adapters with FLASHes which are too
7886 	 * small but we have some legacy FPGAs with small FLASHes that we'd
7887 	 * still like to use.  So instead we emit a scary message ...
7888 	 */
7889 	if (adapter->params.sf_size < FLASH_MIN_SIZE)
7890 		CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
7891 			flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
7892 
7893 	return 0;
7894 }
7895 
7896 static void set_pcie_completion_timeout(struct adapter *adapter,
7897 						  u8 range)
7898 {
7899 	u16 val;
7900 	u32 pcie_cap;
7901 
7902 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7903 	if (pcie_cap) {
7904 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
7905 		val &= 0xfff0;
7906 		val |= range ;
7907 		t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
7908 	}
7909 }
7910 
7911 const struct chip_params *t4_get_chip_params(int chipid)
7912 {
7913 	static const struct chip_params chip_params[] = {
7914 		{
7915 			/* T4 */
7916 			.nchan = NCHAN,
7917 			.pm_stats_cnt = PM_NSTATS,
7918 			.cng_ch_bits_log = 2,
7919 			.nsched_cls = 15,
7920 			.cim_num_obq = CIM_NUM_OBQ,
7921 			.mps_rplc_size = 128,
7922 			.vfcount = 128,
7923 			.sge_fl_db = F_DBPRIO,
7924 			.mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
7925 		},
7926 		{
7927 			/* T5 */
7928 			.nchan = NCHAN,
7929 			.pm_stats_cnt = PM_NSTATS,
7930 			.cng_ch_bits_log = 2,
7931 			.nsched_cls = 16,
7932 			.cim_num_obq = CIM_NUM_OBQ_T5,
7933 			.mps_rplc_size = 128,
7934 			.vfcount = 128,
7935 			.sge_fl_db = F_DBPRIO | F_DBTYPE,
7936 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7937 		},
7938 		{
7939 			/* T6 */
7940 			.nchan = T6_NCHAN,
7941 			.pm_stats_cnt = T6_PM_NSTATS,
7942 			.cng_ch_bits_log = 3,
7943 			.nsched_cls = 16,
7944 			.cim_num_obq = CIM_NUM_OBQ_T5,
7945 			.mps_rplc_size = 256,
7946 			.vfcount = 256,
7947 			.sge_fl_db = 0,
7948 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7949 		},
7950 	};
7951 
7952 	chipid -= CHELSIO_T4;
7953 	if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
7954 		return NULL;
7955 
7956 	return &chip_params[chipid];
7957 }
7958 
7959 /**
7960  *	t4_prep_adapter - prepare SW and HW for operation
7961  *	@adapter: the adapter
7962  *	@buf: temporary space of at least VPD_LEN size provided by the caller.
7963  *
7964  *	Initialize adapter SW state for the various HW modules, set initial
7965  *	values for some adapter tunables, take PHYs out of reset, and
7966  *	initialize the MDIO interface.
7967  */
7968 int t4_prep_adapter(struct adapter *adapter, u8 *buf)
7969 {
7970 	int ret;
7971 	uint16_t device_id;
7972 	uint32_t pl_rev;
7973 
7974 	get_pci_mode(adapter, &adapter->params.pci);
7975 
7976 	pl_rev = t4_read_reg(adapter, A_PL_REV);
7977 	adapter->params.chipid = G_CHIPID(pl_rev);
7978 	adapter->params.rev = G_REV(pl_rev);
7979 	if (adapter->params.chipid == 0) {
7980 		/* T4 did not have chipid in PL_REV (T5 onwards do) */
7981 		adapter->params.chipid = CHELSIO_T4;
7982 
7983 		/* T4A1 chip is not supported */
7984 		if (adapter->params.rev == 1) {
7985 			CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
7986 			return -EINVAL;
7987 		}
7988 	}
7989 
7990 	adapter->chip_params = t4_get_chip_params(chip_id(adapter));
7991 	if (adapter->chip_params == NULL)
7992 		return -EINVAL;
7993 
7994 	adapter->params.pci.vpd_cap_addr =
7995 	    t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
7996 
7997 	ret = t4_get_flash_params(adapter);
7998 	if (ret < 0)
7999 		return ret;
8000 
8001 	ret = get_vpd_params(adapter, &adapter->params.vpd, buf);
8002 	if (ret < 0)
8003 		return ret;
8004 
8005 	/* Cards with real ASICs have the chipid in the PCIe device id */
8006 	t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
8007 	if (device_id >> 12 == chip_id(adapter))
8008 		adapter->params.cim_la_size = CIMLA_SIZE;
8009 	else {
8010 		/* FPGA */
8011 		adapter->params.fpga = 1;
8012 		adapter->params.cim_la_size = 2 * CIMLA_SIZE;
8013 	}
8014 
8015 	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
8016 
8017 	/*
8018 	 * Default port and clock for debugging in case we can't reach FW.
8019 	 */
8020 	adapter->params.nports = 1;
8021 	adapter->params.portvec = 1;
8022 	adapter->params.vpd.cclk = 50000;
8023 
8024 	/* Set pci completion timeout value to 4 seconds. */
8025 	set_pcie_completion_timeout(adapter, 0xd);
8026 	return 0;
8027 }
8028 
8029 /**
8030  *	t4_shutdown_adapter - shut down adapter, host & wire
8031  *	@adapter: the adapter
8032  *
8033  *	Perform an emergency shutdown of the adapter and stop it from
8034  *	continuing any further communication on the ports or DMA to the
8035  *	host.  This is typically used when the adapter and/or firmware
8036  *	have crashed and we want to prevent any further accidental
8037  *	communication with the rest of the world.  This will also force
8038  *	the port Link Status to go down -- if register writes work --
8039  *	which should help our peers figure out that we're down.
8040  */
8041 int t4_shutdown_adapter(struct adapter *adapter)
8042 {
8043 	int port;
8044 
8045 	t4_intr_disable(adapter);
8046 	t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
8047 	for_each_port(adapter, port) {
8048 		u32 a_port_cfg = is_t4(adapter) ?
8049 				 PORT_REG(port, A_XGMAC_PORT_CFG) :
8050 				 T5_PORT_REG(port, A_MAC_PORT_CFG);
8051 
8052 		t4_write_reg(adapter, a_port_cfg,
8053 			     t4_read_reg(adapter, a_port_cfg)
8054 			     & ~V_SIGNAL_DET(1));
8055 	}
8056 	t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
8057 
8058 	return 0;
8059 }
8060 
8061 /**
8062  *	t4_init_devlog_params - initialize adapter->params.devlog
8063  *	@adap: the adapter
8064  *	@fw_attach: whether we can talk to the firmware
8065  *
8066  *	Initialize various fields of the adapter's Firmware Device Log
8067  *	Parameters structure.
8068  */
8069 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
8070 {
8071 	struct devlog_params *dparams = &adap->params.devlog;
8072 	u32 pf_dparams;
8073 	unsigned int devlog_meminfo;
8074 	struct fw_devlog_cmd devlog_cmd;
8075 	int ret;
8076 
8077 	/* If we're dealing with newer firmware, the Device Log Paramerters
8078 	 * are stored in a designated register which allows us to access the
8079 	 * Device Log even if we can't talk to the firmware.
8080 	 */
8081 	pf_dparams =
8082 		t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
8083 	if (pf_dparams) {
8084 		unsigned int nentries, nentries128;
8085 
8086 		dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
8087 		dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
8088 
8089 		nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
8090 		nentries = (nentries128 + 1) * 128;
8091 		dparams->size = nentries * sizeof(struct fw_devlog_e);
8092 
8093 		return 0;
8094 	}
8095 
8096 	/*
8097 	 * For any failing returns ...
8098 	 */
8099 	memset(dparams, 0, sizeof *dparams);
8100 
8101 	/*
8102 	 * If we can't talk to the firmware, there's really nothing we can do
8103 	 * at this point.
8104 	 */
8105 	if (!fw_attach)
8106 		return -ENXIO;
8107 
8108 	/* Otherwise, ask the firmware for it's Device Log Parameters.
8109 	 */
8110 	memset(&devlog_cmd, 0, sizeof devlog_cmd);
8111 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
8112 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
8113 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
8114 	ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
8115 			 &devlog_cmd);
8116 	if (ret)
8117 		return ret;
8118 
8119 	devlog_meminfo =
8120 		be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
8121 	dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
8122 	dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
8123 	dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
8124 
8125 	return 0;
8126 }
8127 
8128 /**
8129  *	t4_init_sge_params - initialize adap->params.sge
8130  *	@adapter: the adapter
8131  *
8132  *	Initialize various fields of the adapter's SGE Parameters structure.
8133  */
8134 int t4_init_sge_params(struct adapter *adapter)
8135 {
8136 	u32 r;
8137 	struct sge_params *sp = &adapter->params.sge;
8138 	unsigned i, tscale = 1;
8139 
8140 	r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
8141 	sp->counter_val[0] = G_THRESHOLD_0(r);
8142 	sp->counter_val[1] = G_THRESHOLD_1(r);
8143 	sp->counter_val[2] = G_THRESHOLD_2(r);
8144 	sp->counter_val[3] = G_THRESHOLD_3(r);
8145 
8146 	if (chip_id(adapter) >= CHELSIO_T6) {
8147 		r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
8148 		tscale = G_TSCALE(r);
8149 		if (tscale == 0)
8150 			tscale = 1;
8151 		else
8152 			tscale += 2;
8153 	}
8154 
8155 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
8156 	sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
8157 	sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
8158 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
8159 	sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
8160 	sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
8161 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
8162 	sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
8163 	sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
8164 
8165 	r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
8166 	sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
8167 	if (is_t4(adapter))
8168 		sp->fl_starve_threshold2 = sp->fl_starve_threshold;
8169 	else if (is_t5(adapter))
8170 		sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
8171 	else
8172 		sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
8173 
8174 	/* egress queues: log2 of # of doorbells per BAR2 page */
8175 	r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
8176 	r >>= S_QUEUESPERPAGEPF0 +
8177 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
8178 	sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
8179 
8180 	/* ingress queues: log2 of # of doorbells per BAR2 page */
8181 	r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
8182 	r >>= S_QUEUESPERPAGEPF0 +
8183 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
8184 	sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
8185 
8186 	r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
8187 	r >>= S_HOSTPAGESIZEPF0 +
8188 	    (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
8189 	sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
8190 
8191 	r = t4_read_reg(adapter, A_SGE_CONTROL);
8192 	sp->sge_control = r;
8193 	sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
8194 	sp->fl_pktshift = G_PKTSHIFT(r);
8195 	if (chip_id(adapter) <= CHELSIO_T5) {
8196 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
8197 		    X_INGPADBOUNDARY_SHIFT);
8198 	} else {
8199 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
8200 		    X_T6_INGPADBOUNDARY_SHIFT);
8201 	}
8202 	if (is_t4(adapter))
8203 		sp->pack_boundary = sp->pad_boundary;
8204 	else {
8205 		r = t4_read_reg(adapter, A_SGE_CONTROL2);
8206 		if (G_INGPACKBOUNDARY(r) == 0)
8207 			sp->pack_boundary = 16;
8208 		else
8209 			sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
8210 	}
8211 	for (i = 0; i < SGE_FLBUF_SIZES; i++)
8212 		sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
8213 		    A_SGE_FL_BUFFER_SIZE0 + (4 * i));
8214 
8215 	return 0;
8216 }
8217 
8218 /*
8219  * Read and cache the adapter's compressed filter mode and ingress config.
8220  */
8221 static void read_filter_mode_and_ingress_config(struct adapter *adap,
8222     bool sleep_ok)
8223 {
8224 	struct tp_params *tpp = &adap->params.tp;
8225 
8226 	t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP,
8227 	    sleep_ok);
8228 	t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG,
8229 	    sleep_ok);
8230 
8231 	/*
8232 	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
8233 	 * shift positions of several elements of the Compressed Filter Tuple
8234 	 * for this adapter which we need frequently ...
8235 	 */
8236 	tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
8237 	tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
8238 	tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
8239 	tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
8240 	tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
8241 	tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
8242 	tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
8243 	tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
8244 	tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
8245 	tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
8246 
8247 	/*
8248 	 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
8249 	 * represents the presence of an Outer VLAN instead of a VNIC ID.
8250 	 */
8251 	if ((tpp->ingress_config & F_VNIC) == 0)
8252 		tpp->vnic_shift = -1;
8253 }
8254 
8255 /**
8256  *      t4_init_tp_params - initialize adap->params.tp
8257  *      @adap: the adapter
8258  *
8259  *      Initialize various fields of the adapter's TP Parameters structure.
8260  */
8261 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
8262 {
8263 	int chan;
8264 	u32 v;
8265 	struct tp_params *tpp = &adap->params.tp;
8266 
8267 	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
8268 	tpp->tre = G_TIMERRESOLUTION(v);
8269 	tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
8270 
8271 	/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
8272 	for (chan = 0; chan < MAX_NCHAN; chan++)
8273 		tpp->tx_modq[chan] = chan;
8274 
8275 	read_filter_mode_and_ingress_config(adap, sleep_ok);
8276 
8277 	/*
8278 	 * Cache a mask of the bits that represent the error vector portion of
8279 	 * rx_pkt.err_vec.  T6+ can use a compressed error vector to make room
8280 	 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
8281 	 */
8282 	tpp->err_vec_mask = htobe16(0xffff);
8283 	if (chip_id(adap) > CHELSIO_T5) {
8284 		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
8285 		if (v & F_CRXPKTENC) {
8286 			tpp->err_vec_mask =
8287 			    htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
8288 		}
8289 	}
8290 
8291 	return 0;
8292 }
8293 
8294 /**
8295  *      t4_filter_field_shift - calculate filter field shift
8296  *      @adap: the adapter
8297  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8298  *
8299  *      Return the shift position of a filter field within the Compressed
8300  *      Filter Tuple.  The filter field is specified via its selection bit
8301  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8302  */
8303 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8304 {
8305 	unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8306 	unsigned int sel;
8307 	int field_shift;
8308 
8309 	if ((filter_mode & filter_sel) == 0)
8310 		return -1;
8311 
8312 	for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8313 		switch (filter_mode & sel) {
8314 		case F_FCOE:
8315 			field_shift += W_FT_FCOE;
8316 			break;
8317 		case F_PORT:
8318 			field_shift += W_FT_PORT;
8319 			break;
8320 		case F_VNIC_ID:
8321 			field_shift += W_FT_VNIC_ID;
8322 			break;
8323 		case F_VLAN:
8324 			field_shift += W_FT_VLAN;
8325 			break;
8326 		case F_TOS:
8327 			field_shift += W_FT_TOS;
8328 			break;
8329 		case F_PROTOCOL:
8330 			field_shift += W_FT_PROTOCOL;
8331 			break;
8332 		case F_ETHERTYPE:
8333 			field_shift += W_FT_ETHERTYPE;
8334 			break;
8335 		case F_MACMATCH:
8336 			field_shift += W_FT_MACMATCH;
8337 			break;
8338 		case F_MPSHITTYPE:
8339 			field_shift += W_FT_MPSHITTYPE;
8340 			break;
8341 		case F_FRAGMENTATION:
8342 			field_shift += W_FT_FRAGMENTATION;
8343 			break;
8344 		}
8345 	}
8346 	return field_shift;
8347 }
8348 
8349 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
8350 {
8351 	u8 addr[6];
8352 	int ret, i, j;
8353 	struct fw_port_cmd c;
8354 	u16 rss_size;
8355 	struct port_info *p = adap2pinfo(adap, port_id);
8356 	u32 param, val;
8357 
8358 	memset(&c, 0, sizeof(c));
8359 
8360 	for (i = 0, j = -1; i <= p->port_id; i++) {
8361 		do {
8362 			j++;
8363 		} while ((adap->params.portvec & (1 << j)) == 0);
8364 	}
8365 
8366 	if (!(adap->flags & IS_VF) ||
8367 	    adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
8368  		t4_update_port_info(p);
8369 	}
8370 
8371 	ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
8372 	if (ret < 0)
8373 		return ret;
8374 
8375 	p->vi[0].viid = ret;
8376 	if (chip_id(adap) <= CHELSIO_T5)
8377 		p->vi[0].smt_idx = (ret & 0x7f) << 1;
8378 	else
8379 		p->vi[0].smt_idx = (ret & 0x7f);
8380 	p->tx_chan = j;
8381 	p->rx_chan_map = t4_get_mps_bg_map(adap, j);
8382 	p->lport = j;
8383 	p->vi[0].rss_size = rss_size;
8384 	t4_os_set_hw_addr(p, addr);
8385 
8386 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8387 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
8388 	    V_FW_PARAMS_PARAM_YZ(p->vi[0].viid);
8389 	ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
8390 	if (ret)
8391 		p->vi[0].rss_base = 0xffff;
8392 	else {
8393 		/* MPASS((val >> 16) == rss_size); */
8394 		p->vi[0].rss_base = val & 0xffff;
8395 	}
8396 
8397 	return 0;
8398 }
8399 
8400 /**
8401  *	t4_read_cimq_cfg - read CIM queue configuration
8402  *	@adap: the adapter
8403  *	@base: holds the queue base addresses in bytes
8404  *	@size: holds the queue sizes in bytes
8405  *	@thres: holds the queue full thresholds in bytes
8406  *
8407  *	Returns the current configuration of the CIM queues, starting with
8408  *	the IBQs, then the OBQs.
8409  */
8410 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8411 {
8412 	unsigned int i, v;
8413 	int cim_num_obq = adap->chip_params->cim_num_obq;
8414 
8415 	for (i = 0; i < CIM_NUM_IBQ; i++) {
8416 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
8417 			     V_QUENUMSELECT(i));
8418 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8419 		/* value is in 256-byte units */
8420 		*base++ = G_CIMQBASE(v) * 256;
8421 		*size++ = G_CIMQSIZE(v) * 256;
8422 		*thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
8423 	}
8424 	for (i = 0; i < cim_num_obq; i++) {
8425 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8426 			     V_QUENUMSELECT(i));
8427 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8428 		/* value is in 256-byte units */
8429 		*base++ = G_CIMQBASE(v) * 256;
8430 		*size++ = G_CIMQSIZE(v) * 256;
8431 	}
8432 }
8433 
8434 /**
8435  *	t4_read_cim_ibq - read the contents of a CIM inbound queue
8436  *	@adap: the adapter
8437  *	@qid: the queue index
8438  *	@data: where to store the queue contents
8439  *	@n: capacity of @data in 32-bit words
8440  *
8441  *	Reads the contents of the selected CIM queue starting at address 0 up
8442  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8443  *	error and the number of 32-bit words actually read on success.
8444  */
8445 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8446 {
8447 	int i, err, attempts;
8448 	unsigned int addr;
8449 	const unsigned int nwords = CIM_IBQ_SIZE * 4;
8450 
8451 	if (qid > 5 || (n & 3))
8452 		return -EINVAL;
8453 
8454 	addr = qid * nwords;
8455 	if (n > nwords)
8456 		n = nwords;
8457 
8458 	/* It might take 3-10ms before the IBQ debug read access is allowed.
8459 	 * Wait for 1 Sec with a delay of 1 usec.
8460 	 */
8461 	attempts = 1000000;
8462 
8463 	for (i = 0; i < n; i++, addr++) {
8464 		t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
8465 			     F_IBQDBGEN);
8466 		err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
8467 				      attempts, 1);
8468 		if (err)
8469 			return err;
8470 		*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
8471 	}
8472 	t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
8473 	return i;
8474 }
8475 
8476 /**
8477  *	t4_read_cim_obq - read the contents of a CIM outbound queue
8478  *	@adap: the adapter
8479  *	@qid: the queue index
8480  *	@data: where to store the queue contents
8481  *	@n: capacity of @data in 32-bit words
8482  *
8483  *	Reads the contents of the selected CIM queue starting at address 0 up
8484  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8485  *	error and the number of 32-bit words actually read on success.
8486  */
8487 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8488 {
8489 	int i, err;
8490 	unsigned int addr, v, nwords;
8491 	int cim_num_obq = adap->chip_params->cim_num_obq;
8492 
8493 	if ((qid > (cim_num_obq - 1)) || (n & 3))
8494 		return -EINVAL;
8495 
8496 	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8497 		     V_QUENUMSELECT(qid));
8498 	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8499 
8500 	addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
8501 	nwords = G_CIMQSIZE(v) * 64;  /* same */
8502 	if (n > nwords)
8503 		n = nwords;
8504 
8505 	for (i = 0; i < n; i++, addr++) {
8506 		t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
8507 			     F_OBQDBGEN);
8508 		err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
8509 				      2, 1);
8510 		if (err)
8511 			return err;
8512 		*data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
8513 	}
8514 	t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
8515 	return i;
8516 }
8517 
8518 enum {
8519 	CIM_QCTL_BASE     = 0,
8520 	CIM_CTL_BASE      = 0x2000,
8521 	CIM_PBT_ADDR_BASE = 0x2800,
8522 	CIM_PBT_LRF_BASE  = 0x3000,
8523 	CIM_PBT_DATA_BASE = 0x3800
8524 };
8525 
8526 /**
8527  *	t4_cim_read - read a block from CIM internal address space
8528  *	@adap: the adapter
8529  *	@addr: the start address within the CIM address space
8530  *	@n: number of words to read
8531  *	@valp: where to store the result
8532  *
8533  *	Reads a block of 4-byte words from the CIM intenal address space.
8534  */
8535 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8536 		unsigned int *valp)
8537 {
8538 	int ret = 0;
8539 
8540 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8541 		return -EBUSY;
8542 
8543 	for ( ; !ret && n--; addr += 4) {
8544 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
8545 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8546 				      0, 5, 2);
8547 		if (!ret)
8548 			*valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
8549 	}
8550 	return ret;
8551 }
8552 
8553 /**
8554  *	t4_cim_write - write a block into CIM internal address space
8555  *	@adap: the adapter
8556  *	@addr: the start address within the CIM address space
8557  *	@n: number of words to write
8558  *	@valp: set of values to write
8559  *
8560  *	Writes a block of 4-byte words into the CIM intenal address space.
8561  */
8562 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8563 		 const unsigned int *valp)
8564 {
8565 	int ret = 0;
8566 
8567 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8568 		return -EBUSY;
8569 
8570 	for ( ; !ret && n--; addr += 4) {
8571 		t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
8572 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
8573 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8574 				      0, 5, 2);
8575 	}
8576 	return ret;
8577 }
8578 
8579 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8580 			 unsigned int val)
8581 {
8582 	return t4_cim_write(adap, addr, 1, &val);
8583 }
8584 
8585 /**
8586  *	t4_cim_ctl_read - read a block from CIM control region
8587  *	@adap: the adapter
8588  *	@addr: the start address within the CIM control region
8589  *	@n: number of words to read
8590  *	@valp: where to store the result
8591  *
8592  *	Reads a block of 4-byte words from the CIM control region.
8593  */
8594 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
8595 		    unsigned int *valp)
8596 {
8597 	return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
8598 }
8599 
8600 /**
8601  *	t4_cim_read_la - read CIM LA capture buffer
8602  *	@adap: the adapter
8603  *	@la_buf: where to store the LA data
8604  *	@wrptr: the HW write pointer within the capture buffer
8605  *
8606  *	Reads the contents of the CIM LA buffer with the most recent entry at
8607  *	the end	of the returned data and with the entry at @wrptr first.
8608  *	We try to leave the LA in the running state we find it in.
8609  */
8610 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8611 {
8612 	int i, ret;
8613 	unsigned int cfg, val, idx;
8614 
8615 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
8616 	if (ret)
8617 		return ret;
8618 
8619 	if (cfg & F_UPDBGLAEN) {	/* LA is running, freeze it */
8620 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
8621 		if (ret)
8622 			return ret;
8623 	}
8624 
8625 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8626 	if (ret)
8627 		goto restart;
8628 
8629 	idx = G_UPDBGLAWRPTR(val);
8630 	if (wrptr)
8631 		*wrptr = idx;
8632 
8633 	for (i = 0; i < adap->params.cim_la_size; i++) {
8634 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8635 				    V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
8636 		if (ret)
8637 			break;
8638 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8639 		if (ret)
8640 			break;
8641 		if (val & F_UPDBGLARDEN) {
8642 			ret = -ETIMEDOUT;
8643 			break;
8644 		}
8645 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
8646 		if (ret)
8647 			break;
8648 
8649 		/* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
8650 		idx = (idx + 1) & M_UPDBGLARDPTR;
8651 		/*
8652 		 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
8653 		 * identify the 32-bit portion of the full 312-bit data
8654 		 */
8655 		if (is_t6(adap))
8656 			while ((idx & 0xf) > 9)
8657 				idx = (idx + 1) % M_UPDBGLARDPTR;
8658 	}
8659 restart:
8660 	if (cfg & F_UPDBGLAEN) {
8661 		int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8662 				      cfg & ~F_UPDBGLARDEN);
8663 		if (!ret)
8664 			ret = r;
8665 	}
8666 	return ret;
8667 }
8668 
8669 /**
8670  *	t4_tp_read_la - read TP LA capture buffer
8671  *	@adap: the adapter
8672  *	@la_buf: where to store the LA data
8673  *	@wrptr: the HW write pointer within the capture buffer
8674  *
8675  *	Reads the contents of the TP LA buffer with the most recent entry at
8676  *	the end	of the returned data and with the entry at @wrptr first.
8677  *	We leave the LA in the running state we find it in.
8678  */
8679 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8680 {
8681 	bool last_incomplete;
8682 	unsigned int i, cfg, val, idx;
8683 
8684 	cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
8685 	if (cfg & F_DBGLAENABLE)			/* freeze LA */
8686 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8687 			     adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
8688 
8689 	val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
8690 	idx = G_DBGLAWPTR(val);
8691 	last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
8692 	if (last_incomplete)
8693 		idx = (idx + 1) & M_DBGLARPTR;
8694 	if (wrptr)
8695 		*wrptr = idx;
8696 
8697 	val &= 0xffff;
8698 	val &= ~V_DBGLARPTR(M_DBGLARPTR);
8699 	val |= adap->params.tp.la_mask;
8700 
8701 	for (i = 0; i < TPLA_SIZE; i++) {
8702 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
8703 		la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
8704 		idx = (idx + 1) & M_DBGLARPTR;
8705 	}
8706 
8707 	/* Wipe out last entry if it isn't valid */
8708 	if (last_incomplete)
8709 		la_buf[TPLA_SIZE - 1] = ~0ULL;
8710 
8711 	if (cfg & F_DBGLAENABLE)		/* restore running state */
8712 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8713 			     cfg | adap->params.tp.la_mask);
8714 }
8715 
8716 /*
8717  * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8718  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8719  * state for more than the Warning Threshold then we'll issue a warning about
8720  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8721  * appears to be hung every Warning Repeat second till the situation clears.
8722  * If the situation clears, we'll note that as well.
8723  */
8724 #define SGE_IDMA_WARN_THRESH 1
8725 #define SGE_IDMA_WARN_REPEAT 300
8726 
8727 /**
8728  *	t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8729  *	@adapter: the adapter
8730  *	@idma: the adapter IDMA Monitor state
8731  *
8732  *	Initialize the state of an SGE Ingress DMA Monitor.
8733  */
8734 void t4_idma_monitor_init(struct adapter *adapter,
8735 			  struct sge_idma_monitor_state *idma)
8736 {
8737 	/* Initialize the state variables for detecting an SGE Ingress DMA
8738 	 * hang.  The SGE has internal counters which count up on each clock
8739 	 * tick whenever the SGE finds its Ingress DMA State Engines in the
8740 	 * same state they were on the previous clock tick.  The clock used is
8741 	 * the Core Clock so we have a limit on the maximum "time" they can
8742 	 * record; typically a very small number of seconds.  For instance,
8743 	 * with a 600MHz Core Clock, we can only count up to a bit more than
8744 	 * 7s.  So we'll synthesize a larger counter in order to not run the
8745 	 * risk of having the "timers" overflow and give us the flexibility to
8746 	 * maintain a Hung SGE State Machine of our own which operates across
8747 	 * a longer time frame.
8748 	 */
8749 	idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8750 	idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
8751 }
8752 
8753 /**
8754  *	t4_idma_monitor - monitor SGE Ingress DMA state
8755  *	@adapter: the adapter
8756  *	@idma: the adapter IDMA Monitor state
8757  *	@hz: number of ticks/second
8758  *	@ticks: number of ticks since the last IDMA Monitor call
8759  */
8760 void t4_idma_monitor(struct adapter *adapter,
8761 		     struct sge_idma_monitor_state *idma,
8762 		     int hz, int ticks)
8763 {
8764 	int i, idma_same_state_cnt[2];
8765 
8766 	 /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8767 	  * are counters inside the SGE which count up on each clock when the
8768 	  * SGE finds its Ingress DMA State Engines in the same states they
8769 	  * were in the previous clock.  The counters will peg out at
8770 	  * 0xffffffff without wrapping around so once they pass the 1s
8771 	  * threshold they'll stay above that till the IDMA state changes.
8772 	  */
8773 	t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
8774 	idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
8775 	idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8776 
8777 	for (i = 0; i < 2; i++) {
8778 		u32 debug0, debug11;
8779 
8780 		/* If the Ingress DMA Same State Counter ("timer") is less
8781 		 * than 1s, then we can reset our synthesized Stall Timer and
8782 		 * continue.  If we have previously emitted warnings about a
8783 		 * potential stalled Ingress Queue, issue a note indicating
8784 		 * that the Ingress Queue has resumed forward progress.
8785 		 */
8786 		if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8787 			if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
8788 				CH_WARN(adapter, "SGE idma%d, queue %u, "
8789 					"resumed after %d seconds\n",
8790 					i, idma->idma_qid[i],
8791 					idma->idma_stalled[i]/hz);
8792 			idma->idma_stalled[i] = 0;
8793 			continue;
8794 		}
8795 
8796 		/* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8797 		 * domain.  The first time we get here it'll be because we
8798 		 * passed the 1s Threshold; each additional time it'll be
8799 		 * because the RX Timer Callback is being fired on its regular
8800 		 * schedule.
8801 		 *
8802 		 * If the stall is below our Potential Hung Ingress Queue
8803 		 * Warning Threshold, continue.
8804 		 */
8805 		if (idma->idma_stalled[i] == 0) {
8806 			idma->idma_stalled[i] = hz;
8807 			idma->idma_warn[i] = 0;
8808 		} else {
8809 			idma->idma_stalled[i] += ticks;
8810 			idma->idma_warn[i] -= ticks;
8811 		}
8812 
8813 		if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
8814 			continue;
8815 
8816 		/* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8817 		 */
8818 		if (idma->idma_warn[i] > 0)
8819 			continue;
8820 		idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
8821 
8822 		/* Read and save the SGE IDMA State and Queue ID information.
8823 		 * We do this every time in case it changes across time ...
8824 		 * can't be too careful ...
8825 		 */
8826 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
8827 		debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8828 		idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8829 
8830 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
8831 		debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8832 		idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8833 
8834 		CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
8835 			" state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8836 			i, idma->idma_qid[i], idma->idma_state[i],
8837 			idma->idma_stalled[i]/hz,
8838 			debug0, debug11);
8839 		t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8840 	}
8841 }
8842 
8843 /**
8844  *	t4_read_pace_tbl - read the pace table
8845  *	@adap: the adapter
8846  *	@pace_vals: holds the returned values
8847  *
8848  *	Returns the values of TP's pace table in microseconds.
8849  */
8850 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
8851 {
8852 	unsigned int i, v;
8853 
8854 	for (i = 0; i < NTX_SCHED; i++) {
8855 		t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
8856 		v = t4_read_reg(adap, A_TP_PACE_TABLE);
8857 		pace_vals[i] = dack_ticks_to_usec(adap, v);
8858 	}
8859 }
8860 
8861 /**
8862  *	t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
8863  *	@adap: the adapter
8864  *	@sched: the scheduler index
8865  *	@kbps: the byte rate in Kbps
8866  *	@ipg: the interpacket delay in tenths of nanoseconds
8867  *
8868  *	Return the current configuration of a HW Tx scheduler.
8869  */
8870 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
8871 		     unsigned int *ipg, bool sleep_ok)
8872 {
8873 	unsigned int v, addr, bpt, cpt;
8874 
8875 	if (kbps) {
8876 		addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
8877 		t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
8878 		if (sched & 1)
8879 			v >>= 16;
8880 		bpt = (v >> 8) & 0xff;
8881 		cpt = v & 0xff;
8882 		if (!cpt)
8883 			*kbps = 0;	/* scheduler disabled */
8884 		else {
8885 			v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
8886 			*kbps = (v * bpt) / 125;
8887 		}
8888 	}
8889 	if (ipg) {
8890 		addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
8891 		t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
8892 		if (sched & 1)
8893 			v >>= 16;
8894 		v &= 0xffff;
8895 		*ipg = (10000 * v) / core_ticks_per_usec(adap);
8896 	}
8897 }
8898 
8899 /**
8900  *	t4_load_cfg - download config file
8901  *	@adap: the adapter
8902  *	@cfg_data: the cfg text file to write
8903  *	@size: text file size
8904  *
8905  *	Write the supplied config text file to the card's serial flash.
8906  */
8907 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
8908 {
8909 	int ret, i, n, cfg_addr;
8910 	unsigned int addr;
8911 	unsigned int flash_cfg_start_sec;
8912 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8913 
8914 	cfg_addr = t4_flash_cfg_addr(adap);
8915 	if (cfg_addr < 0)
8916 		return cfg_addr;
8917 
8918 	addr = cfg_addr;
8919 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
8920 
8921 	if (size > FLASH_CFG_MAX_SIZE) {
8922 		CH_ERR(adap, "cfg file too large, max is %u bytes\n",
8923 		       FLASH_CFG_MAX_SIZE);
8924 		return -EFBIG;
8925 	}
8926 
8927 	i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,	/* # of sectors spanned */
8928 			 sf_sec_size);
8929 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
8930 				     flash_cfg_start_sec + i - 1);
8931 	/*
8932 	 * If size == 0 then we're simply erasing the FLASH sectors associated
8933 	 * with the on-adapter Firmware Configuration File.
8934 	 */
8935 	if (ret || size == 0)
8936 		goto out;
8937 
8938 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
8939 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
8940 		if ( (size - i) <  SF_PAGE_SIZE)
8941 			n = size - i;
8942 		else
8943 			n = SF_PAGE_SIZE;
8944 		ret = t4_write_flash(adap, addr, n, cfg_data, 1);
8945 		if (ret)
8946 			goto out;
8947 
8948 		addr += SF_PAGE_SIZE;
8949 		cfg_data += SF_PAGE_SIZE;
8950 	}
8951 
8952 out:
8953 	if (ret)
8954 		CH_ERR(adap, "config file %s failed %d\n",
8955 		       (size == 0 ? "clear" : "download"), ret);
8956 	return ret;
8957 }
8958 
8959 /**
8960  *	t5_fw_init_extern_mem - initialize the external memory
8961  *	@adap: the adapter
8962  *
8963  *	Initializes the external memory on T5.
8964  */
8965 int t5_fw_init_extern_mem(struct adapter *adap)
8966 {
8967 	u32 params[1], val[1];
8968 	int ret;
8969 
8970 	if (!is_t5(adap))
8971 		return 0;
8972 
8973 	val[0] = 0xff; /* Initialize all MCs */
8974 	params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8975 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
8976 	ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
8977 			FW_CMD_MAX_TIMEOUT);
8978 
8979 	return ret;
8980 }
8981 
8982 /* BIOS boot headers */
8983 typedef struct pci_expansion_rom_header {
8984 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
8985 	u8	reserved[22]; /* Reserved per processor Architecture data */
8986 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
8987 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
8988 
8989 /* Legacy PCI Expansion ROM Header */
8990 typedef struct legacy_pci_expansion_rom_header {
8991 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
8992 	u8	size512; /* Current Image Size in units of 512 bytes */
8993 	u8	initentry_point[4];
8994 	u8	cksum; /* Checksum computed on the entire Image */
8995 	u8	reserved[16]; /* Reserved */
8996 	u8	pcir_offset[2]; /* Offset to PCI Data Struture */
8997 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
8998 
8999 /* EFI PCI Expansion ROM Header */
9000 typedef struct efi_pci_expansion_rom_header {
9001 	u8	signature[2]; // ROM signature. The value 0xaa55
9002 	u8	initialization_size[2]; /* Units 512. Includes this header */
9003 	u8	efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
9004 	u8	efi_subsystem[2]; /* Subsystem value for EFI image header */
9005 	u8	efi_machine_type[2]; /* Machine type from EFI image header */
9006 	u8	compression_type[2]; /* Compression type. */
9007 		/*
9008 		 * Compression type definition
9009 		 * 0x0: uncompressed
9010 		 * 0x1: Compressed
9011 		 * 0x2-0xFFFF: Reserved
9012 		 */
9013 	u8	reserved[8]; /* Reserved */
9014 	u8	efi_image_header_offset[2]; /* Offset to EFI Image */
9015 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
9016 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
9017 
9018 /* PCI Data Structure Format */
9019 typedef struct pcir_data_structure { /* PCI Data Structure */
9020 	u8	signature[4]; /* Signature. The string "PCIR" */
9021 	u8	vendor_id[2]; /* Vendor Identification */
9022 	u8	device_id[2]; /* Device Identification */
9023 	u8	vital_product[2]; /* Pointer to Vital Product Data */
9024 	u8	length[2]; /* PCIR Data Structure Length */
9025 	u8	revision; /* PCIR Data Structure Revision */
9026 	u8	class_code[3]; /* Class Code */
9027 	u8	image_length[2]; /* Image Length. Multiple of 512B */
9028 	u8	code_revision[2]; /* Revision Level of Code/Data */
9029 	u8	code_type; /* Code Type. */
9030 		/*
9031 		 * PCI Expansion ROM Code Types
9032 		 * 0x00: Intel IA-32, PC-AT compatible. Legacy
9033 		 * 0x01: Open Firmware standard for PCI. FCODE
9034 		 * 0x02: Hewlett-Packard PA RISC. HP reserved
9035 		 * 0x03: EFI Image. EFI
9036 		 * 0x04-0xFF: Reserved.
9037 		 */
9038 	u8	indicator; /* Indicator. Identifies the last image in the ROM */
9039 	u8	reserved[2]; /* Reserved */
9040 } pcir_data_t; /* PCI__DATA_STRUCTURE */
9041 
9042 /* BOOT constants */
9043 enum {
9044 	BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
9045 	BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
9046 	BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
9047 	BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
9048 	BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment  */
9049 	VENDOR_ID = 0x1425, /* Vendor ID */
9050 	PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
9051 };
9052 
9053 /*
9054  *	modify_device_id - Modifies the device ID of the Boot BIOS image
9055  *	@adatper: the device ID to write.
9056  *	@boot_data: the boot image to modify.
9057  *
9058  *	Write the supplied device ID to the boot BIOS image.
9059  */
9060 static void modify_device_id(int device_id, u8 *boot_data)
9061 {
9062 	legacy_pci_exp_rom_header_t *header;
9063 	pcir_data_t *pcir_header;
9064 	u32 cur_header = 0;
9065 
9066 	/*
9067 	 * Loop through all chained images and change the device ID's
9068 	 */
9069 	while (1) {
9070 		header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
9071 		pcir_header = (pcir_data_t *) &boot_data[cur_header +
9072 			      le16_to_cpu(*(u16*)header->pcir_offset)];
9073 
9074 		/*
9075 		 * Only modify the Device ID if code type is Legacy or HP.
9076 		 * 0x00: Okay to modify
9077 		 * 0x01: FCODE. Do not be modify
9078 		 * 0x03: Okay to modify
9079 		 * 0x04-0xFF: Do not modify
9080 		 */
9081 		if (pcir_header->code_type == 0x00) {
9082 			u8 csum = 0;
9083 			int i;
9084 
9085 			/*
9086 			 * Modify Device ID to match current adatper
9087 			 */
9088 			*(u16*) pcir_header->device_id = device_id;
9089 
9090 			/*
9091 			 * Set checksum temporarily to 0.
9092 			 * We will recalculate it later.
9093 			 */
9094 			header->cksum = 0x0;
9095 
9096 			/*
9097 			 * Calculate and update checksum
9098 			 */
9099 			for (i = 0; i < (header->size512 * 512); i++)
9100 				csum += (u8)boot_data[cur_header + i];
9101 
9102 			/*
9103 			 * Invert summed value to create the checksum
9104 			 * Writing new checksum value directly to the boot data
9105 			 */
9106 			boot_data[cur_header + 7] = -csum;
9107 
9108 		} else if (pcir_header->code_type == 0x03) {
9109 
9110 			/*
9111 			 * Modify Device ID to match current adatper
9112 			 */
9113 			*(u16*) pcir_header->device_id = device_id;
9114 
9115 		}
9116 
9117 
9118 		/*
9119 		 * Check indicator element to identify if this is the last
9120 		 * image in the ROM.
9121 		 */
9122 		if (pcir_header->indicator & 0x80)
9123 			break;
9124 
9125 		/*
9126 		 * Move header pointer up to the next image in the ROM.
9127 		 */
9128 		cur_header += header->size512 * 512;
9129 	}
9130 }
9131 
9132 /*
9133  *	t4_load_boot - download boot flash
9134  *	@adapter: the adapter
9135  *	@boot_data: the boot image to write
9136  *	@boot_addr: offset in flash to write boot_data
9137  *	@size: image size
9138  *
9139  *	Write the supplied boot image to the card's serial flash.
9140  *	The boot image has the following sections: a 28-byte header and the
9141  *	boot image.
9142  */
9143 int t4_load_boot(struct adapter *adap, u8 *boot_data,
9144 		 unsigned int boot_addr, unsigned int size)
9145 {
9146 	pci_exp_rom_header_t *header;
9147 	int pcir_offset ;
9148 	pcir_data_t *pcir_header;
9149 	int ret, addr;
9150 	uint16_t device_id;
9151 	unsigned int i;
9152 	unsigned int boot_sector = (boot_addr * 1024 );
9153 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9154 
9155 	/*
9156 	 * Make sure the boot image does not encroach on the firmware region
9157 	 */
9158 	if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
9159 		CH_ERR(adap, "boot image encroaching on firmware region\n");
9160 		return -EFBIG;
9161 	}
9162 
9163 	/*
9164 	 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
9165 	 * and Boot configuration data sections. These 3 boot sections span
9166 	 * sectors 0 to 7 in flash and live right before the FW image location.
9167 	 */
9168 	i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
9169 			sf_sec_size);
9170 	ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
9171 				     (boot_sector >> 16) + i - 1);
9172 
9173 	/*
9174 	 * If size == 0 then we're simply erasing the FLASH sectors associated
9175 	 * with the on-adapter option ROM file
9176 	 */
9177 	if (ret || (size == 0))
9178 		goto out;
9179 
9180 	/* Get boot header */
9181 	header = (pci_exp_rom_header_t *)boot_data;
9182 	pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
9183 	/* PCIR Data Structure */
9184 	pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
9185 
9186 	/*
9187 	 * Perform some primitive sanity testing to avoid accidentally
9188 	 * writing garbage over the boot sectors.  We ought to check for
9189 	 * more but it's not worth it for now ...
9190 	 */
9191 	if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
9192 		CH_ERR(adap, "boot image too small/large\n");
9193 		return -EFBIG;
9194 	}
9195 
9196 #ifndef CHELSIO_T4_DIAGS
9197 	/*
9198 	 * Check BOOT ROM header signature
9199 	 */
9200 	if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
9201 		CH_ERR(adap, "Boot image missing signature\n");
9202 		return -EINVAL;
9203 	}
9204 
9205 	/*
9206 	 * Check PCI header signature
9207 	 */
9208 	if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
9209 		CH_ERR(adap, "PCI header missing signature\n");
9210 		return -EINVAL;
9211 	}
9212 
9213 	/*
9214 	 * Check Vendor ID matches Chelsio ID
9215 	 */
9216 	if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
9217 		CH_ERR(adap, "Vendor ID missing signature\n");
9218 		return -EINVAL;
9219 	}
9220 #endif
9221 
9222 	/*
9223 	 * Retrieve adapter's device ID
9224 	 */
9225 	t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
9226 	/* Want to deal with PF 0 so I strip off PF 4 indicator */
9227 	device_id = device_id & 0xf0ff;
9228 
9229 	/*
9230 	 * Check PCIE Device ID
9231 	 */
9232 	if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
9233 		/*
9234 		 * Change the device ID in the Boot BIOS image to match
9235 		 * the Device ID of the current adapter.
9236 		 */
9237 		modify_device_id(device_id, boot_data);
9238 	}
9239 
9240 	/*
9241 	 * Skip over the first SF_PAGE_SIZE worth of data and write it after
9242 	 * we finish copying the rest of the boot image. This will ensure
9243 	 * that the BIOS boot header will only be written if the boot image
9244 	 * was written in full.
9245 	 */
9246 	addr = boot_sector;
9247 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
9248 		addr += SF_PAGE_SIZE;
9249 		boot_data += SF_PAGE_SIZE;
9250 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
9251 		if (ret)
9252 			goto out;
9253 	}
9254 
9255 	ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
9256 			     (const u8 *)header, 0);
9257 
9258 out:
9259 	if (ret)
9260 		CH_ERR(adap, "boot image download failed, error %d\n", ret);
9261 	return ret;
9262 }
9263 
9264 /*
9265  *	t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
9266  *	@adapter: the adapter
9267  *
9268  *	Return the address within the flash where the OptionROM Configuration
9269  *	is stored, or an error if the device FLASH is too small to contain
9270  *	a OptionROM Configuration.
9271  */
9272 static int t4_flash_bootcfg_addr(struct adapter *adapter)
9273 {
9274 	/*
9275 	 * If the device FLASH isn't large enough to hold a Firmware
9276 	 * Configuration File, return an error.
9277 	 */
9278 	if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
9279 		return -ENOSPC;
9280 
9281 	return FLASH_BOOTCFG_START;
9282 }
9283 
9284 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
9285 {
9286 	int ret, i, n, cfg_addr;
9287 	unsigned int addr;
9288 	unsigned int flash_cfg_start_sec;
9289 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9290 
9291 	cfg_addr = t4_flash_bootcfg_addr(adap);
9292 	if (cfg_addr < 0)
9293 		return cfg_addr;
9294 
9295 	addr = cfg_addr;
9296 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
9297 
9298 	if (size > FLASH_BOOTCFG_MAX_SIZE) {
9299 		CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
9300 			FLASH_BOOTCFG_MAX_SIZE);
9301 		return -EFBIG;
9302 	}
9303 
9304 	i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
9305 			 sf_sec_size);
9306 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9307 					flash_cfg_start_sec + i - 1);
9308 
9309 	/*
9310 	 * If size == 0 then we're simply erasing the FLASH sectors associated
9311 	 * with the on-adapter OptionROM Configuration File.
9312 	 */
9313 	if (ret || size == 0)
9314 		goto out;
9315 
9316 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
9317 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
9318 		if ( (size - i) <  SF_PAGE_SIZE)
9319 			n = size - i;
9320 		else
9321 			n = SF_PAGE_SIZE;
9322 		ret = t4_write_flash(adap, addr, n, cfg_data, 0);
9323 		if (ret)
9324 			goto out;
9325 
9326 		addr += SF_PAGE_SIZE;
9327 		cfg_data += SF_PAGE_SIZE;
9328 	}
9329 
9330 out:
9331 	if (ret)
9332 		CH_ERR(adap, "boot config data %s failed %d\n",
9333 				(size == 0 ? "clear" : "download"), ret);
9334 	return ret;
9335 }
9336 
9337 /**
9338  *	t4_set_filter_mode - configure the optional components of filter tuples
9339  *	@adap: the adapter
9340  *	@mode_map: a bitmap selcting which optional filter components to enable
9341  * 	@sleep_ok: if true we may sleep while awaiting command completion
9342  *
9343  *	Sets the filter mode by selecting the optional components to enable
9344  *	in filter tuples.  Returns 0 on success and a negative error if the
9345  *	requested mode needs more bits than are available for optional
9346  *	components.
9347  */
9348 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
9349 		       bool sleep_ok)
9350 {
9351 	static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
9352 
9353 	int i, nbits = 0;
9354 
9355 	for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
9356 		if (mode_map & (1 << i))
9357 			nbits += width[i];
9358 	if (nbits > FILTER_OPT_LEN)
9359 		return -EINVAL;
9360 	t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok);
9361 	read_filter_mode_and_ingress_config(adap, sleep_ok);
9362 
9363 	return 0;
9364 }
9365 
9366 /**
9367  *	t4_clr_port_stats - clear port statistics
9368  *	@adap: the adapter
9369  *	@idx: the port index
9370  *
9371  *	Clear HW statistics for the given port.
9372  */
9373 void t4_clr_port_stats(struct adapter *adap, int idx)
9374 {
9375 	unsigned int i;
9376 	u32 bgmap = t4_get_mps_bg_map(adap, idx);
9377 	u32 port_base_addr;
9378 
9379 	if (is_t4(adap))
9380 		port_base_addr = PORT_BASE(idx);
9381 	else
9382 		port_base_addr = T5_PORT_BASE(idx);
9383 
9384 	for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
9385 			i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
9386 		t4_write_reg(adap, port_base_addr + i, 0);
9387 	for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
9388 			i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
9389 		t4_write_reg(adap, port_base_addr + i, 0);
9390 	for (i = 0; i < 4; i++)
9391 		if (bgmap & (1 << i)) {
9392 			t4_write_reg(adap,
9393 			A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
9394 			t4_write_reg(adap,
9395 			A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
9396 		}
9397 }
9398 
9399 /**
9400  *	t4_i2c_rd - read I2C data from adapter
9401  *	@adap: the adapter
9402  *	@port: Port number if per-port device; <0 if not
9403  *	@devid: per-port device ID or absolute device ID
9404  *	@offset: byte offset into device I2C space
9405  *	@len: byte length of I2C space data
9406  *	@buf: buffer in which to return I2C data
9407  *
9408  *	Reads the I2C data from the indicated device and location.
9409  */
9410 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
9411 	      int port, unsigned int devid,
9412 	      unsigned int offset, unsigned int len,
9413 	      u8 *buf)
9414 {
9415 	u32 ldst_addrspace;
9416 	struct fw_ldst_cmd ldst;
9417 	int ret;
9418 
9419 	if (port >= 4 ||
9420 	    devid >= 256 ||
9421 	    offset >= 256 ||
9422 	    len > sizeof ldst.u.i2c.data)
9423 		return -EINVAL;
9424 
9425 	memset(&ldst, 0, sizeof ldst);
9426 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9427 	ldst.op_to_addrspace =
9428 		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9429 			    F_FW_CMD_REQUEST |
9430 			    F_FW_CMD_READ |
9431 			    ldst_addrspace);
9432 	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9433 	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9434 	ldst.u.i2c.did = devid;
9435 	ldst.u.i2c.boffset = offset;
9436 	ldst.u.i2c.blen = len;
9437 	ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9438 	if (!ret)
9439 		memcpy(buf, ldst.u.i2c.data, len);
9440 	return ret;
9441 }
9442 
9443 /**
9444  *	t4_i2c_wr - write I2C data to adapter
9445  *	@adap: the adapter
9446  *	@port: Port number if per-port device; <0 if not
9447  *	@devid: per-port device ID or absolute device ID
9448  *	@offset: byte offset into device I2C space
9449  *	@len: byte length of I2C space data
9450  *	@buf: buffer containing new I2C data
9451  *
9452  *	Write the I2C data to the indicated device and location.
9453  */
9454 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
9455 	      int port, unsigned int devid,
9456 	      unsigned int offset, unsigned int len,
9457 	      u8 *buf)
9458 {
9459 	u32 ldst_addrspace;
9460 	struct fw_ldst_cmd ldst;
9461 
9462 	if (port >= 4 ||
9463 	    devid >= 256 ||
9464 	    offset >= 256 ||
9465 	    len > sizeof ldst.u.i2c.data)
9466 		return -EINVAL;
9467 
9468 	memset(&ldst, 0, sizeof ldst);
9469 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9470 	ldst.op_to_addrspace =
9471 		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9472 			    F_FW_CMD_REQUEST |
9473 			    F_FW_CMD_WRITE |
9474 			    ldst_addrspace);
9475 	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9476 	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9477 	ldst.u.i2c.did = devid;
9478 	ldst.u.i2c.boffset = offset;
9479 	ldst.u.i2c.blen = len;
9480 	memcpy(ldst.u.i2c.data, buf, len);
9481 	return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9482 }
9483 
9484 /**
9485  * 	t4_sge_ctxt_rd - read an SGE context through FW
9486  * 	@adap: the adapter
9487  * 	@mbox: mailbox to use for the FW command
9488  * 	@cid: the context id
9489  * 	@ctype: the context type
9490  * 	@data: where to store the context data
9491  *
9492  * 	Issues a FW command through the given mailbox to read an SGE context.
9493  */
9494 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9495 		   enum ctxt_type ctype, u32 *data)
9496 {
9497 	int ret;
9498 	struct fw_ldst_cmd c;
9499 
9500 	if (ctype == CTXT_EGRESS)
9501 		ret = FW_LDST_ADDRSPC_SGE_EGRC;
9502 	else if (ctype == CTXT_INGRESS)
9503 		ret = FW_LDST_ADDRSPC_SGE_INGC;
9504 	else if (ctype == CTXT_FLM)
9505 		ret = FW_LDST_ADDRSPC_SGE_FLMC;
9506 	else
9507 		ret = FW_LDST_ADDRSPC_SGE_CONMC;
9508 
9509 	memset(&c, 0, sizeof(c));
9510 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9511 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
9512 					V_FW_LDST_CMD_ADDRSPACE(ret));
9513 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9514 	c.u.idctxt.physid = cpu_to_be32(cid);
9515 
9516 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9517 	if (ret == 0) {
9518 		data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9519 		data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9520 		data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9521 		data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9522 		data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9523 		data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9524 	}
9525 	return ret;
9526 }
9527 
9528 /**
9529  * 	t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9530  * 	@adap: the adapter
9531  * 	@cid: the context id
9532  * 	@ctype: the context type
9533  * 	@data: where to store the context data
9534  *
9535  * 	Reads an SGE context directly, bypassing FW.  This is only for
9536  * 	debugging when FW is unavailable.
9537  */
9538 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
9539 		      u32 *data)
9540 {
9541 	int i, ret;
9542 
9543 	t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
9544 	ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
9545 	if (!ret)
9546 		for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
9547 			*data++ = t4_read_reg(adap, i);
9548 	return ret;
9549 }
9550 
9551 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
9552     int sleep_ok)
9553 {
9554 	struct fw_sched_cmd cmd;
9555 
9556 	memset(&cmd, 0, sizeof(cmd));
9557 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9558 				      F_FW_CMD_REQUEST |
9559 				      F_FW_CMD_WRITE);
9560 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9561 
9562 	cmd.u.config.sc = FW_SCHED_SC_CONFIG;
9563 	cmd.u.config.type = type;
9564 	cmd.u.config.minmaxen = minmaxen;
9565 
9566 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9567 			       NULL, sleep_ok);
9568 }
9569 
9570 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9571 		    int rateunit, int ratemode, int channel, int cl,
9572 		    int minrate, int maxrate, int weight, int pktsize,
9573 		    int sleep_ok)
9574 {
9575 	struct fw_sched_cmd cmd;
9576 
9577 	memset(&cmd, 0, sizeof(cmd));
9578 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9579 				      F_FW_CMD_REQUEST |
9580 				      F_FW_CMD_WRITE);
9581 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9582 
9583 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9584 	cmd.u.params.type = type;
9585 	cmd.u.params.level = level;
9586 	cmd.u.params.mode = mode;
9587 	cmd.u.params.ch = channel;
9588 	cmd.u.params.cl = cl;
9589 	cmd.u.params.unit = rateunit;
9590 	cmd.u.params.rate = ratemode;
9591 	cmd.u.params.min = cpu_to_be32(minrate);
9592 	cmd.u.params.max = cpu_to_be32(maxrate);
9593 	cmd.u.params.weight = cpu_to_be16(weight);
9594 	cmd.u.params.pktsize = cpu_to_be16(pktsize);
9595 
9596 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9597 			       NULL, sleep_ok);
9598 }
9599 
9600 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
9601     unsigned int maxrate, int sleep_ok)
9602 {
9603 	struct fw_sched_cmd cmd;
9604 
9605 	memset(&cmd, 0, sizeof(cmd));
9606 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9607 				      F_FW_CMD_REQUEST |
9608 				      F_FW_CMD_WRITE);
9609 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9610 
9611 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9612 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
9613 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
9614 	cmd.u.params.ch = channel;
9615 	cmd.u.params.rate = ratemode;		/* REL or ABS */
9616 	cmd.u.params.max = cpu_to_be32(maxrate);/*  %  or kbps */
9617 
9618 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9619 			       NULL, sleep_ok);
9620 }
9621 
9622 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
9623     int weight, int sleep_ok)
9624 {
9625 	struct fw_sched_cmd cmd;
9626 
9627 	if (weight < 0 || weight > 100)
9628 		return -EINVAL;
9629 
9630 	memset(&cmd, 0, sizeof(cmd));
9631 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9632 				      F_FW_CMD_REQUEST |
9633 				      F_FW_CMD_WRITE);
9634 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9635 
9636 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9637 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
9638 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
9639 	cmd.u.params.ch = channel;
9640 	cmd.u.params.cl = cl;
9641 	cmd.u.params.weight = cpu_to_be16(weight);
9642 
9643 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9644 			       NULL, sleep_ok);
9645 }
9646 
9647 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
9648     int mode, unsigned int maxrate, int pktsize, int sleep_ok)
9649 {
9650 	struct fw_sched_cmd cmd;
9651 
9652 	memset(&cmd, 0, sizeof(cmd));
9653 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9654 				      F_FW_CMD_REQUEST |
9655 				      F_FW_CMD_WRITE);
9656 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9657 
9658 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9659 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
9660 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
9661 	cmd.u.params.mode = mode;
9662 	cmd.u.params.ch = channel;
9663 	cmd.u.params.cl = cl;
9664 	cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
9665 	cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
9666 	cmd.u.params.max = cpu_to_be32(maxrate);
9667 	cmd.u.params.pktsize = cpu_to_be16(pktsize);
9668 
9669 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9670 			       NULL, sleep_ok);
9671 }
9672 
9673 /*
9674  *	t4_config_watchdog - configure (enable/disable) a watchdog timer
9675  *	@adapter: the adapter
9676  * 	@mbox: mailbox to use for the FW command
9677  * 	@pf: the PF owning the queue
9678  * 	@vf: the VF owning the queue
9679  *	@timeout: watchdog timeout in ms
9680  *	@action: watchdog timer / action
9681  *
9682  *	There are separate watchdog timers for each possible watchdog
9683  *	action.  Configure one of the watchdog timers by setting a non-zero
9684  *	timeout.  Disable a watchdog timer by using a timeout of zero.
9685  */
9686 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
9687 		       unsigned int pf, unsigned int vf,
9688 		       unsigned int timeout, unsigned int action)
9689 {
9690 	struct fw_watchdog_cmd wdog;
9691 	unsigned int ticks;
9692 
9693 	/*
9694 	 * The watchdog command expects a timeout in units of 10ms so we need
9695 	 * to convert it here (via rounding) and force a minimum of one 10ms
9696 	 * "tick" if the timeout is non-zero but the conversion results in 0
9697 	 * ticks.
9698 	 */
9699 	ticks = (timeout + 5)/10;
9700 	if (timeout && !ticks)
9701 		ticks = 1;
9702 
9703 	memset(&wdog, 0, sizeof wdog);
9704 	wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
9705 				     F_FW_CMD_REQUEST |
9706 				     F_FW_CMD_WRITE |
9707 				     V_FW_PARAMS_CMD_PFN(pf) |
9708 				     V_FW_PARAMS_CMD_VFN(vf));
9709 	wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
9710 	wdog.timeout = cpu_to_be32(ticks);
9711 	wdog.action = cpu_to_be32(action);
9712 
9713 	return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
9714 }
9715 
9716 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
9717 {
9718 	struct fw_devlog_cmd devlog_cmd;
9719 	int ret;
9720 
9721 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9722 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9723 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
9724 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9725 	ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9726 			 sizeof(devlog_cmd), &devlog_cmd);
9727 	if (ret)
9728 		return ret;
9729 
9730 	*level = devlog_cmd.level;
9731 	return 0;
9732 }
9733 
9734 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
9735 {
9736 	struct fw_devlog_cmd devlog_cmd;
9737 
9738 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9739 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9740 					     F_FW_CMD_REQUEST |
9741 					     F_FW_CMD_WRITE);
9742 	devlog_cmd.level = level;
9743 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9744 	return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9745 			  sizeof(devlog_cmd), &devlog_cmd);
9746 }
9747