1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 adap->flags &= ~FW_OK; 216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 218 if (pcie_fw != 0xffffffff) 219 t4_os_dump_devlog(adap); 220 } 221 } 222 223 /* 224 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 225 */ 226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 227 u32 mbox_addr) 228 { 229 for ( ; nflit; nflit--, mbox_addr += 8) 230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 231 } 232 233 /* 234 * Handle a FW assertion reported in a mailbox. 235 */ 236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 237 { 238 CH_ALERT(adap, 239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 240 asrt->u.assert.filename_0_7, 241 be32_to_cpu(asrt->u.assert.line), 242 be32_to_cpu(asrt->u.assert.x), 243 be32_to_cpu(asrt->u.assert.y)); 244 } 245 246 struct port_tx_state { 247 uint64_t rx_pause; 248 uint64_t tx_frames; 249 }; 250 251 static void 252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 253 { 254 uint32_t rx_pause_reg, tx_frames_reg; 255 256 if (is_t4(sc)) { 257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 259 } else { 260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 262 } 263 264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 266 } 267 268 static void 269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 270 { 271 int i; 272 273 for_each_port(sc, i) 274 read_tx_state_one(sc, i, &tx_state[i]); 275 } 276 277 static void 278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 279 { 280 uint32_t port_ctl_reg; 281 uint64_t tx_frames, rx_pause; 282 int i; 283 284 for_each_port(sc, i) { 285 rx_pause = tx_state[i].rx_pause; 286 tx_frames = tx_state[i].tx_frames; 287 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 288 289 if (is_t4(sc)) 290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 291 else 292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 294 rx_pause != tx_state[i].rx_pause && 295 tx_frames == tx_state[i].tx_frames) { 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 297 mdelay(1); 298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 299 } 300 } 301 } 302 303 #define X_CIM_PF_NOACCESS 0xeeeeeeee 304 /** 305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 306 * @adap: the adapter 307 * @mbox: index of the mailbox to use 308 * @cmd: the command to write 309 * @size: command length in bytes 310 * @rpl: where to optionally store the reply 311 * @sleep_ok: if true we may sleep while awaiting command completion 312 * @timeout: time to wait for command to finish before timing out 313 * (negative implies @sleep_ok=false) 314 * 315 * Sends the given command to FW through the selected mailbox and waits 316 * for the FW to execute the command. If @rpl is not %NULL it is used to 317 * store the FW's reply to the command. The command and its optional 318 * reply are of the same length. Some FW commands like RESET and 319 * INITIALIZE can take a considerable amount of time to execute. 320 * @sleep_ok determines whether we may sleep while awaiting the response. 321 * If sleeping is allowed we use progressive backoff otherwise we spin. 322 * Note that passing in a negative @timeout is an alternate mechanism 323 * for specifying @sleep_ok=false. This is useful when a higher level 324 * interface allows for specification of @timeout but not @sleep_ok ... 325 * 326 * The return value is 0 on success or a negative errno on failure. A 327 * failure can happen either because we are not able to execute the 328 * command or FW executes it but signals an error. In the latter case 329 * the return value is the error code indicated by FW (negated). 330 */ 331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 332 int size, void *rpl, bool sleep_ok, int timeout) 333 { 334 /* 335 * We delay in small increments at first in an effort to maintain 336 * responsiveness for simple, fast executing commands but then back 337 * off to larger delays to a maximum retry delay. 338 */ 339 static const int delay[] = { 340 1, 1, 3, 5, 10, 10, 20, 50, 100 341 }; 342 u32 v; 343 u64 res; 344 int i, ms, delay_idx, ret, next_tx_check; 345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 347 u32 ctl; 348 __be64 cmd_rpl[MBOX_LEN/8]; 349 u32 pcie_fw; 350 struct port_tx_state tx_state[MAX_NPORTS]; 351 352 if (adap->flags & CHK_MBOX_ACCESS) 353 ASSERT_SYNCHRONIZED_OP(adap); 354 355 if (size <= 0 || (size & 15) || size > MBOX_LEN) 356 return -EINVAL; 357 358 if (adap->flags & IS_VF) { 359 if (is_t6(adap)) 360 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 361 else 362 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 364 } 365 366 /* 367 * If we have a negative timeout, that implies that we can't sleep. 368 */ 369 if (timeout < 0) { 370 sleep_ok = false; 371 timeout = -timeout; 372 } 373 374 /* 375 * Attempt to gain access to the mailbox. 376 */ 377 for (i = 0; i < 4; i++) { 378 ctl = t4_read_reg(adap, ctl_reg); 379 v = G_MBOWNER(ctl); 380 if (v != X_MBOWNER_NONE) 381 break; 382 } 383 384 /* 385 * If we were unable to gain access, report the error to our caller. 386 */ 387 if (v != X_MBOWNER_PL) { 388 t4_report_fw_error(adap); 389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 390 return ret; 391 } 392 393 /* 394 * If we gain ownership of the mailbox and there's a "valid" message 395 * in it, this is likely an asynchronous error message from the 396 * firmware. So we'll report that and then proceed on with attempting 397 * to issue our own command ... which may well fail if the error 398 * presaged the firmware crashing ... 399 */ 400 if (ctl & F_MBMSGVALID) { 401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 402 } 403 404 /* 405 * Copy in the new mailbox command and send it on its way ... 406 */ 407 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 408 memcpy(cmd_rpl, cmd, size); 409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 412 413 if (adap->flags & IS_VF) { 414 /* 415 * For the VFs, the Mailbox Data "registers" are 416 * actually backed by T4's "MA" interface rather than 417 * PL Registers (as is the case for the PFs). Because 418 * these are in different coherency domains, the write 419 * to the VF's PL-register-backed Mailbox Control can 420 * race in front of the writes to the MA-backed VF 421 * Mailbox Data "registers". So we need to do a 422 * read-back on at least one byte of the VF Mailbox 423 * Data registers before doing the write to the VF 424 * Mailbox Control register. 425 */ 426 t4_read_reg(adap, data_reg); 427 } 428 429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 431 next_tx_check = 1000; 432 delay_idx = 0; 433 ms = delay[0]; 434 435 /* 436 * Loop waiting for the reply; bail out if we time out or the firmware 437 * reports an error. 438 */ 439 pcie_fw = 0; 440 for (i = 0; i < timeout; i += ms) { 441 if (!(adap->flags & IS_VF)) { 442 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 443 if (pcie_fw & F_PCIE_FW_ERR) 444 break; 445 } 446 447 if (i >= next_tx_check) { 448 check_tx_state(adap, &tx_state[0]); 449 next_tx_check = i + 1000; 450 } 451 452 if (sleep_ok) { 453 ms = delay[delay_idx]; /* last element may repeat */ 454 if (delay_idx < ARRAY_SIZE(delay) - 1) 455 delay_idx++; 456 msleep(ms); 457 } else { 458 mdelay(ms); 459 } 460 461 v = t4_read_reg(adap, ctl_reg); 462 if (v == X_CIM_PF_NOACCESS) 463 continue; 464 if (G_MBOWNER(v) == X_MBOWNER_PL) { 465 if (!(v & F_MBMSGVALID)) { 466 t4_write_reg(adap, ctl_reg, 467 V_MBOWNER(X_MBOWNER_NONE)); 468 continue; 469 } 470 471 /* 472 * Retrieve the command reply and release the mailbox. 473 */ 474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 477 478 res = be64_to_cpu(cmd_rpl[0]); 479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 481 res = V_FW_CMD_RETVAL(EIO); 482 } else if (rpl) 483 memcpy(rpl, cmd_rpl, size); 484 return -G_FW_CMD_RETVAL((int)res); 485 } 486 } 487 488 /* 489 * We timed out waiting for a reply to our mailbox command. Report 490 * the error and also check to see if the firmware reported any 491 * errors ... 492 */ 493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 494 *(const u8 *)cmd, mbox, pcie_fw); 495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 497 498 if (pcie_fw & F_PCIE_FW_ERR) { 499 ret = -ENXIO; 500 t4_report_fw_error(adap); 501 } else { 502 ret = -ETIMEDOUT; 503 t4_os_dump_devlog(adap); 504 } 505 506 t4_fatal_err(adap, true); 507 return ret; 508 } 509 510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 511 void *rpl, bool sleep_ok) 512 { 513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 514 sleep_ok, FW_CMD_MAX_TIMEOUT); 515 516 } 517 518 static int t4_edc_err_read(struct adapter *adap, int idx) 519 { 520 u32 edc_ecc_err_addr_reg; 521 u32 edc_bist_status_rdata_reg; 522 523 if (is_t4(adap)) { 524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 525 return 0; 526 } 527 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 529 return 0; 530 } 531 532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 534 535 CH_WARN(adap, 536 "edc%d err addr 0x%x: 0x%x.\n", 537 idx, edc_ecc_err_addr_reg, 538 t4_read_reg(adap, edc_ecc_err_addr_reg)); 539 CH_WARN(adap, 540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 541 edc_bist_status_rdata_reg, 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 551 552 return 0; 553 } 554 555 /** 556 * t4_mc_read - read from MC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which MC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568 { 569 int i; 570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 572 573 if (is_t4(adap)) { 574 mc_bist_cmd_reg = A_MC_BIST_CMD; 575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 579 } else { 580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 584 idx); 585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 586 idx); 587 } 588 589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 590 return -EBUSY; 591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 595 F_START_BIST | V_BIST_CMD_GAP(1)); 596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 597 if (i) 598 return i; 599 600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 601 602 for (i = 15; i >= 0; i--) 603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 604 if (ecc) 605 *ecc = t4_read_reg64(adap, MC_DATA(16)); 606 #undef MC_DATA 607 return 0; 608 } 609 610 /** 611 * t4_edc_read - read from EDC through backdoor accesses 612 * @adap: the adapter 613 * @idx: which EDC to access 614 * @addr: address of first byte requested 615 * @data: 64 bytes of data containing the requested address 616 * @ecc: where to store the corresponding 64-bit ECC word 617 * 618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 619 * that covers the requested address @addr. If @parity is not %NULL it 620 * is assigned the 64-bit ECC word for the read data. 621 */ 622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 623 { 624 int i; 625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 627 628 if (is_t4(adap)) { 629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 633 idx); 634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 635 idx); 636 } else { 637 /* 638 * These macro are missing in t4_regs.h file. 639 * Added temporarily for testing. 640 */ 641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 649 idx); 650 #undef EDC_REG_T5 651 #undef EDC_STRIDE_T5 652 } 653 654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 655 return -EBUSY; 656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 659 t4_write_reg(adap, edc_bist_cmd_reg, 660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 662 if (i) 663 return i; 664 665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 666 667 for (i = 15; i >= 0; i--) 668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 669 if (ecc) 670 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 671 #undef EDC_DATA 672 return 0; 673 } 674 675 /** 676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 677 * @adap: the adapter 678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 679 * @addr: address within indicated memory type 680 * @len: amount of memory to read 681 * @buf: host memory buffer 682 * 683 * Reads an [almost] arbitrary memory region in the firmware: the 684 * firmware memory address, length and host buffer must be aligned on 685 * 32-bit boudaries. The memory is returned as a raw byte sequence from 686 * the firmware's memory. If this memory contains data structures which 687 * contain multi-byte integers, it's the callers responsibility to 688 * perform appropriate byte order conversions. 689 */ 690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 691 __be32 *buf) 692 { 693 u32 pos, start, end, offset; 694 int ret; 695 696 /* 697 * Argument sanity checks ... 698 */ 699 if ((addr & 0x3) || (len & 0x3)) 700 return -EINVAL; 701 702 /* 703 * The underlaying EDC/MC read routines read 64 bytes at a time so we 704 * need to round down the start and round up the end. We'll start 705 * copying out of the first line at (addr - start) a word at a time. 706 */ 707 start = rounddown2(addr, 64); 708 end = roundup2(addr + len, 64); 709 offset = (addr - start)/sizeof(__be32); 710 711 for (pos = start; pos < end; pos += 64, offset = 0) { 712 __be32 data[16]; 713 714 /* 715 * Read the chip's memory block and bail if there's an error. 716 */ 717 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 719 else 720 ret = t4_edc_read(adap, mtype, pos, data, NULL); 721 if (ret) 722 return ret; 723 724 /* 725 * Copy the data into the caller's memory buffer. 726 */ 727 while (offset < 16 && len > 0) { 728 *buf++ = data[offset++]; 729 len -= sizeof(__be32); 730 } 731 } 732 733 return 0; 734 } 735 736 /* 737 * Return the specified PCI-E Configuration Space register from our Physical 738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 739 * since we prefer to let the firmware own all of these registers, but if that 740 * fails we go for it directly ourselves. 741 */ 742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 743 { 744 745 /* 746 * If fw_attach != 0, construct and send the Firmware LDST Command to 747 * retrieve the specified PCI-E Configuration Space register. 748 */ 749 if (drv_fw_attach != 0) { 750 struct fw_ldst_cmd ldst_cmd; 751 int ret; 752 753 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 754 ldst_cmd.op_to_addrspace = 755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 756 F_FW_CMD_REQUEST | 757 F_FW_CMD_READ | 758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 761 ldst_cmd.u.pcie.ctrl_to_fn = 762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 763 ldst_cmd.u.pcie.r = reg; 764 765 /* 766 * If the LDST Command succeeds, return the result, otherwise 767 * fall through to reading it directly ourselves ... 768 */ 769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 770 &ldst_cmd); 771 if (ret == 0) 772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 773 774 CH_WARN(adap, "Firmware failed to return " 775 "Configuration Space register %d, err = %d\n", 776 reg, -ret); 777 } 778 779 /* 780 * Read the desired Configuration Space register via the PCI-E 781 * Backdoor mechanism. 782 */ 783 return t4_hw_pci_read_cfg4(adap, reg); 784 } 785 786 /** 787 * t4_get_regs_len - return the size of the chips register set 788 * @adapter: the adapter 789 * 790 * Returns the size of the chip's BAR0 register space. 791 */ 792 unsigned int t4_get_regs_len(struct adapter *adapter) 793 { 794 unsigned int chip_version = chip_id(adapter); 795 796 switch (chip_version) { 797 case CHELSIO_T4: 798 if (adapter->flags & IS_VF) 799 return FW_T4VF_REGMAP_SIZE; 800 return T4_REGMAP_SIZE; 801 802 case CHELSIO_T5: 803 case CHELSIO_T6: 804 if (adapter->flags & IS_VF) 805 return FW_T4VF_REGMAP_SIZE; 806 return T5_REGMAP_SIZE; 807 } 808 809 CH_ERR(adapter, 810 "Unsupported chip version %d\n", chip_version); 811 return 0; 812 } 813 814 /** 815 * t4_get_regs - read chip registers into provided buffer 816 * @adap: the adapter 817 * @buf: register buffer 818 * @buf_size: size (in bytes) of register buffer 819 * 820 * If the provided register buffer isn't large enough for the chip's 821 * full register range, the register dump will be truncated to the 822 * register buffer's size. 823 */ 824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 825 { 826 static const unsigned int t4_reg_ranges[] = { 827 0x1008, 0x1108, 828 0x1180, 0x1184, 829 0x1190, 0x1194, 830 0x11a0, 0x11a4, 831 0x11b0, 0x11b4, 832 0x11fc, 0x123c, 833 0x1300, 0x173c, 834 0x1800, 0x18fc, 835 0x3000, 0x30d8, 836 0x30e0, 0x30e4, 837 0x30ec, 0x5910, 838 0x5920, 0x5924, 839 0x5960, 0x5960, 840 0x5968, 0x5968, 841 0x5970, 0x5970, 842 0x5978, 0x5978, 843 0x5980, 0x5980, 844 0x5988, 0x5988, 845 0x5990, 0x5990, 846 0x5998, 0x5998, 847 0x59a0, 0x59d4, 848 0x5a00, 0x5ae0, 849 0x5ae8, 0x5ae8, 850 0x5af0, 0x5af0, 851 0x5af8, 0x5af8, 852 0x6000, 0x6098, 853 0x6100, 0x6150, 854 0x6200, 0x6208, 855 0x6240, 0x6248, 856 0x6280, 0x62b0, 857 0x62c0, 0x6338, 858 0x6370, 0x638c, 859 0x6400, 0x643c, 860 0x6500, 0x6524, 861 0x6a00, 0x6a04, 862 0x6a14, 0x6a38, 863 0x6a60, 0x6a70, 864 0x6a78, 0x6a78, 865 0x6b00, 0x6b0c, 866 0x6b1c, 0x6b84, 867 0x6bf0, 0x6bf8, 868 0x6c00, 0x6c0c, 869 0x6c1c, 0x6c84, 870 0x6cf0, 0x6cf8, 871 0x6d00, 0x6d0c, 872 0x6d1c, 0x6d84, 873 0x6df0, 0x6df8, 874 0x6e00, 0x6e0c, 875 0x6e1c, 0x6e84, 876 0x6ef0, 0x6ef8, 877 0x6f00, 0x6f0c, 878 0x6f1c, 0x6f84, 879 0x6ff0, 0x6ff8, 880 0x7000, 0x700c, 881 0x701c, 0x7084, 882 0x70f0, 0x70f8, 883 0x7100, 0x710c, 884 0x711c, 0x7184, 885 0x71f0, 0x71f8, 886 0x7200, 0x720c, 887 0x721c, 0x7284, 888 0x72f0, 0x72f8, 889 0x7300, 0x730c, 890 0x731c, 0x7384, 891 0x73f0, 0x73f8, 892 0x7400, 0x7450, 893 0x7500, 0x7530, 894 0x7600, 0x760c, 895 0x7614, 0x761c, 896 0x7680, 0x76cc, 897 0x7700, 0x7798, 898 0x77c0, 0x77fc, 899 0x7900, 0x79fc, 900 0x7b00, 0x7b58, 901 0x7b60, 0x7b84, 902 0x7b8c, 0x7c38, 903 0x7d00, 0x7d38, 904 0x7d40, 0x7d80, 905 0x7d8c, 0x7ddc, 906 0x7de4, 0x7e04, 907 0x7e10, 0x7e1c, 908 0x7e24, 0x7e38, 909 0x7e40, 0x7e44, 910 0x7e4c, 0x7e78, 911 0x7e80, 0x7ea4, 912 0x7eac, 0x7edc, 913 0x7ee8, 0x7efc, 914 0x8dc0, 0x8e04, 915 0x8e10, 0x8e1c, 916 0x8e30, 0x8e78, 917 0x8ea0, 0x8eb8, 918 0x8ec0, 0x8f6c, 919 0x8fc0, 0x9008, 920 0x9010, 0x9058, 921 0x9060, 0x9060, 922 0x9068, 0x9074, 923 0x90fc, 0x90fc, 924 0x9400, 0x9408, 925 0x9410, 0x9458, 926 0x9600, 0x9600, 927 0x9608, 0x9638, 928 0x9640, 0x96bc, 929 0x9800, 0x9808, 930 0x9820, 0x983c, 931 0x9850, 0x9864, 932 0x9c00, 0x9c6c, 933 0x9c80, 0x9cec, 934 0x9d00, 0x9d6c, 935 0x9d80, 0x9dec, 936 0x9e00, 0x9e6c, 937 0x9e80, 0x9eec, 938 0x9f00, 0x9f6c, 939 0x9f80, 0x9fec, 940 0xd004, 0xd004, 941 0xd010, 0xd03c, 942 0xdfc0, 0xdfe0, 943 0xe000, 0xea7c, 944 0xf000, 0x11110, 945 0x11118, 0x11190, 946 0x19040, 0x1906c, 947 0x19078, 0x19080, 948 0x1908c, 0x190e4, 949 0x190f0, 0x190f8, 950 0x19100, 0x19110, 951 0x19120, 0x19124, 952 0x19150, 0x19194, 953 0x1919c, 0x191b0, 954 0x191d0, 0x191e8, 955 0x19238, 0x1924c, 956 0x193f8, 0x1943c, 957 0x1944c, 0x19474, 958 0x19490, 0x194e0, 959 0x194f0, 0x194f8, 960 0x19800, 0x19c08, 961 0x19c10, 0x19c90, 962 0x19ca0, 0x19ce4, 963 0x19cf0, 0x19d40, 964 0x19d50, 0x19d94, 965 0x19da0, 0x19de8, 966 0x19df0, 0x19e40, 967 0x19e50, 0x19e90, 968 0x19ea0, 0x19f4c, 969 0x1a000, 0x1a004, 970 0x1a010, 0x1a06c, 971 0x1a0b0, 0x1a0e4, 972 0x1a0ec, 0x1a0f4, 973 0x1a100, 0x1a108, 974 0x1a114, 0x1a120, 975 0x1a128, 0x1a130, 976 0x1a138, 0x1a138, 977 0x1a190, 0x1a1c4, 978 0x1a1fc, 0x1a1fc, 979 0x1e040, 0x1e04c, 980 0x1e284, 0x1e28c, 981 0x1e2c0, 0x1e2c0, 982 0x1e2e0, 0x1e2e0, 983 0x1e300, 0x1e384, 984 0x1e3c0, 0x1e3c8, 985 0x1e440, 0x1e44c, 986 0x1e684, 0x1e68c, 987 0x1e6c0, 0x1e6c0, 988 0x1e6e0, 0x1e6e0, 989 0x1e700, 0x1e784, 990 0x1e7c0, 0x1e7c8, 991 0x1e840, 0x1e84c, 992 0x1ea84, 0x1ea8c, 993 0x1eac0, 0x1eac0, 994 0x1eae0, 0x1eae0, 995 0x1eb00, 0x1eb84, 996 0x1ebc0, 0x1ebc8, 997 0x1ec40, 0x1ec4c, 998 0x1ee84, 0x1ee8c, 999 0x1eec0, 0x1eec0, 1000 0x1eee0, 0x1eee0, 1001 0x1ef00, 0x1ef84, 1002 0x1efc0, 0x1efc8, 1003 0x1f040, 0x1f04c, 1004 0x1f284, 0x1f28c, 1005 0x1f2c0, 0x1f2c0, 1006 0x1f2e0, 0x1f2e0, 1007 0x1f300, 0x1f384, 1008 0x1f3c0, 0x1f3c8, 1009 0x1f440, 0x1f44c, 1010 0x1f684, 0x1f68c, 1011 0x1f6c0, 0x1f6c0, 1012 0x1f6e0, 0x1f6e0, 1013 0x1f700, 0x1f784, 1014 0x1f7c0, 0x1f7c8, 1015 0x1f840, 0x1f84c, 1016 0x1fa84, 0x1fa8c, 1017 0x1fac0, 0x1fac0, 1018 0x1fae0, 0x1fae0, 1019 0x1fb00, 0x1fb84, 1020 0x1fbc0, 0x1fbc8, 1021 0x1fc40, 0x1fc4c, 1022 0x1fe84, 0x1fe8c, 1023 0x1fec0, 0x1fec0, 1024 0x1fee0, 0x1fee0, 1025 0x1ff00, 0x1ff84, 1026 0x1ffc0, 0x1ffc8, 1027 0x20000, 0x2002c, 1028 0x20100, 0x2013c, 1029 0x20190, 0x201a0, 1030 0x201a8, 0x201b8, 1031 0x201c4, 0x201c8, 1032 0x20200, 0x20318, 1033 0x20400, 0x204b4, 1034 0x204c0, 0x20528, 1035 0x20540, 0x20614, 1036 0x21000, 0x21040, 1037 0x2104c, 0x21060, 1038 0x210c0, 0x210ec, 1039 0x21200, 0x21268, 1040 0x21270, 0x21284, 1041 0x212fc, 0x21388, 1042 0x21400, 0x21404, 1043 0x21500, 0x21500, 1044 0x21510, 0x21518, 1045 0x2152c, 0x21530, 1046 0x2153c, 0x2153c, 1047 0x21550, 0x21554, 1048 0x21600, 0x21600, 1049 0x21608, 0x2161c, 1050 0x21624, 0x21628, 1051 0x21630, 0x21634, 1052 0x2163c, 0x2163c, 1053 0x21700, 0x2171c, 1054 0x21780, 0x2178c, 1055 0x21800, 0x21818, 1056 0x21820, 0x21828, 1057 0x21830, 0x21848, 1058 0x21850, 0x21854, 1059 0x21860, 0x21868, 1060 0x21870, 0x21870, 1061 0x21878, 0x21898, 1062 0x218a0, 0x218a8, 1063 0x218b0, 0x218c8, 1064 0x218d0, 0x218d4, 1065 0x218e0, 0x218e8, 1066 0x218f0, 0x218f0, 1067 0x218f8, 0x21a18, 1068 0x21a20, 0x21a28, 1069 0x21a30, 0x21a48, 1070 0x21a50, 0x21a54, 1071 0x21a60, 0x21a68, 1072 0x21a70, 0x21a70, 1073 0x21a78, 0x21a98, 1074 0x21aa0, 0x21aa8, 1075 0x21ab0, 0x21ac8, 1076 0x21ad0, 0x21ad4, 1077 0x21ae0, 0x21ae8, 1078 0x21af0, 0x21af0, 1079 0x21af8, 0x21c18, 1080 0x21c20, 0x21c20, 1081 0x21c28, 0x21c30, 1082 0x21c38, 0x21c38, 1083 0x21c80, 0x21c98, 1084 0x21ca0, 0x21ca8, 1085 0x21cb0, 0x21cc8, 1086 0x21cd0, 0x21cd4, 1087 0x21ce0, 0x21ce8, 1088 0x21cf0, 0x21cf0, 1089 0x21cf8, 0x21d7c, 1090 0x21e00, 0x21e04, 1091 0x22000, 0x2202c, 1092 0x22100, 0x2213c, 1093 0x22190, 0x221a0, 1094 0x221a8, 0x221b8, 1095 0x221c4, 0x221c8, 1096 0x22200, 0x22318, 1097 0x22400, 0x224b4, 1098 0x224c0, 0x22528, 1099 0x22540, 0x22614, 1100 0x23000, 0x23040, 1101 0x2304c, 0x23060, 1102 0x230c0, 0x230ec, 1103 0x23200, 0x23268, 1104 0x23270, 0x23284, 1105 0x232fc, 0x23388, 1106 0x23400, 0x23404, 1107 0x23500, 0x23500, 1108 0x23510, 0x23518, 1109 0x2352c, 0x23530, 1110 0x2353c, 0x2353c, 1111 0x23550, 0x23554, 1112 0x23600, 0x23600, 1113 0x23608, 0x2361c, 1114 0x23624, 0x23628, 1115 0x23630, 0x23634, 1116 0x2363c, 0x2363c, 1117 0x23700, 0x2371c, 1118 0x23780, 0x2378c, 1119 0x23800, 0x23818, 1120 0x23820, 0x23828, 1121 0x23830, 0x23848, 1122 0x23850, 0x23854, 1123 0x23860, 0x23868, 1124 0x23870, 0x23870, 1125 0x23878, 0x23898, 1126 0x238a0, 0x238a8, 1127 0x238b0, 0x238c8, 1128 0x238d0, 0x238d4, 1129 0x238e0, 0x238e8, 1130 0x238f0, 0x238f0, 1131 0x238f8, 0x23a18, 1132 0x23a20, 0x23a28, 1133 0x23a30, 0x23a48, 1134 0x23a50, 0x23a54, 1135 0x23a60, 0x23a68, 1136 0x23a70, 0x23a70, 1137 0x23a78, 0x23a98, 1138 0x23aa0, 0x23aa8, 1139 0x23ab0, 0x23ac8, 1140 0x23ad0, 0x23ad4, 1141 0x23ae0, 0x23ae8, 1142 0x23af0, 0x23af0, 1143 0x23af8, 0x23c18, 1144 0x23c20, 0x23c20, 1145 0x23c28, 0x23c30, 1146 0x23c38, 0x23c38, 1147 0x23c80, 0x23c98, 1148 0x23ca0, 0x23ca8, 1149 0x23cb0, 0x23cc8, 1150 0x23cd0, 0x23cd4, 1151 0x23ce0, 0x23ce8, 1152 0x23cf0, 0x23cf0, 1153 0x23cf8, 0x23d7c, 1154 0x23e00, 0x23e04, 1155 0x24000, 0x2402c, 1156 0x24100, 0x2413c, 1157 0x24190, 0x241a0, 1158 0x241a8, 0x241b8, 1159 0x241c4, 0x241c8, 1160 0x24200, 0x24318, 1161 0x24400, 0x244b4, 1162 0x244c0, 0x24528, 1163 0x24540, 0x24614, 1164 0x25000, 0x25040, 1165 0x2504c, 0x25060, 1166 0x250c0, 0x250ec, 1167 0x25200, 0x25268, 1168 0x25270, 0x25284, 1169 0x252fc, 0x25388, 1170 0x25400, 0x25404, 1171 0x25500, 0x25500, 1172 0x25510, 0x25518, 1173 0x2552c, 0x25530, 1174 0x2553c, 0x2553c, 1175 0x25550, 0x25554, 1176 0x25600, 0x25600, 1177 0x25608, 0x2561c, 1178 0x25624, 0x25628, 1179 0x25630, 0x25634, 1180 0x2563c, 0x2563c, 1181 0x25700, 0x2571c, 1182 0x25780, 0x2578c, 1183 0x25800, 0x25818, 1184 0x25820, 0x25828, 1185 0x25830, 0x25848, 1186 0x25850, 0x25854, 1187 0x25860, 0x25868, 1188 0x25870, 0x25870, 1189 0x25878, 0x25898, 1190 0x258a0, 0x258a8, 1191 0x258b0, 0x258c8, 1192 0x258d0, 0x258d4, 1193 0x258e0, 0x258e8, 1194 0x258f0, 0x258f0, 1195 0x258f8, 0x25a18, 1196 0x25a20, 0x25a28, 1197 0x25a30, 0x25a48, 1198 0x25a50, 0x25a54, 1199 0x25a60, 0x25a68, 1200 0x25a70, 0x25a70, 1201 0x25a78, 0x25a98, 1202 0x25aa0, 0x25aa8, 1203 0x25ab0, 0x25ac8, 1204 0x25ad0, 0x25ad4, 1205 0x25ae0, 0x25ae8, 1206 0x25af0, 0x25af0, 1207 0x25af8, 0x25c18, 1208 0x25c20, 0x25c20, 1209 0x25c28, 0x25c30, 1210 0x25c38, 0x25c38, 1211 0x25c80, 0x25c98, 1212 0x25ca0, 0x25ca8, 1213 0x25cb0, 0x25cc8, 1214 0x25cd0, 0x25cd4, 1215 0x25ce0, 0x25ce8, 1216 0x25cf0, 0x25cf0, 1217 0x25cf8, 0x25d7c, 1218 0x25e00, 0x25e04, 1219 0x26000, 0x2602c, 1220 0x26100, 0x2613c, 1221 0x26190, 0x261a0, 1222 0x261a8, 0x261b8, 1223 0x261c4, 0x261c8, 1224 0x26200, 0x26318, 1225 0x26400, 0x264b4, 1226 0x264c0, 0x26528, 1227 0x26540, 0x26614, 1228 0x27000, 0x27040, 1229 0x2704c, 0x27060, 1230 0x270c0, 0x270ec, 1231 0x27200, 0x27268, 1232 0x27270, 0x27284, 1233 0x272fc, 0x27388, 1234 0x27400, 0x27404, 1235 0x27500, 0x27500, 1236 0x27510, 0x27518, 1237 0x2752c, 0x27530, 1238 0x2753c, 0x2753c, 1239 0x27550, 0x27554, 1240 0x27600, 0x27600, 1241 0x27608, 0x2761c, 1242 0x27624, 0x27628, 1243 0x27630, 0x27634, 1244 0x2763c, 0x2763c, 1245 0x27700, 0x2771c, 1246 0x27780, 0x2778c, 1247 0x27800, 0x27818, 1248 0x27820, 0x27828, 1249 0x27830, 0x27848, 1250 0x27850, 0x27854, 1251 0x27860, 0x27868, 1252 0x27870, 0x27870, 1253 0x27878, 0x27898, 1254 0x278a0, 0x278a8, 1255 0x278b0, 0x278c8, 1256 0x278d0, 0x278d4, 1257 0x278e0, 0x278e8, 1258 0x278f0, 0x278f0, 1259 0x278f8, 0x27a18, 1260 0x27a20, 0x27a28, 1261 0x27a30, 0x27a48, 1262 0x27a50, 0x27a54, 1263 0x27a60, 0x27a68, 1264 0x27a70, 0x27a70, 1265 0x27a78, 0x27a98, 1266 0x27aa0, 0x27aa8, 1267 0x27ab0, 0x27ac8, 1268 0x27ad0, 0x27ad4, 1269 0x27ae0, 0x27ae8, 1270 0x27af0, 0x27af0, 1271 0x27af8, 0x27c18, 1272 0x27c20, 0x27c20, 1273 0x27c28, 0x27c30, 1274 0x27c38, 0x27c38, 1275 0x27c80, 0x27c98, 1276 0x27ca0, 0x27ca8, 1277 0x27cb0, 0x27cc8, 1278 0x27cd0, 0x27cd4, 1279 0x27ce0, 0x27ce8, 1280 0x27cf0, 0x27cf0, 1281 0x27cf8, 0x27d7c, 1282 0x27e00, 0x27e04, 1283 }; 1284 1285 static const unsigned int t4vf_reg_ranges[] = { 1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1287 VF_MPS_REG(A_MPS_VF_CTL), 1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1292 FW_T4VF_MBDATA_BASE_ADDR, 1293 FW_T4VF_MBDATA_BASE_ADDR + 1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1295 }; 1296 1297 static const unsigned int t5_reg_ranges[] = { 1298 0x1008, 0x10c0, 1299 0x10cc, 0x10f8, 1300 0x1100, 0x1100, 1301 0x110c, 0x1148, 1302 0x1180, 0x1184, 1303 0x1190, 0x1194, 1304 0x11a0, 0x11a4, 1305 0x11b0, 0x11b4, 1306 0x11fc, 0x123c, 1307 0x1280, 0x173c, 1308 0x1800, 0x18fc, 1309 0x3000, 0x3028, 1310 0x3060, 0x30b0, 1311 0x30b8, 0x30d8, 1312 0x30e0, 0x30fc, 1313 0x3140, 0x357c, 1314 0x35a8, 0x35cc, 1315 0x35ec, 0x35ec, 1316 0x3600, 0x5624, 1317 0x56cc, 0x56ec, 1318 0x56f4, 0x5720, 1319 0x5728, 0x575c, 1320 0x580c, 0x5814, 1321 0x5890, 0x589c, 1322 0x58a4, 0x58ac, 1323 0x58b8, 0x58bc, 1324 0x5940, 0x59c8, 1325 0x59d0, 0x59dc, 1326 0x59fc, 0x5a18, 1327 0x5a60, 0x5a70, 1328 0x5a80, 0x5a9c, 1329 0x5b94, 0x5bfc, 1330 0x6000, 0x6020, 1331 0x6028, 0x6040, 1332 0x6058, 0x609c, 1333 0x60a8, 0x614c, 1334 0x7700, 0x7798, 1335 0x77c0, 0x78fc, 1336 0x7b00, 0x7b58, 1337 0x7b60, 0x7b84, 1338 0x7b8c, 0x7c54, 1339 0x7d00, 0x7d38, 1340 0x7d40, 0x7d80, 1341 0x7d8c, 0x7ddc, 1342 0x7de4, 0x7e04, 1343 0x7e10, 0x7e1c, 1344 0x7e24, 0x7e38, 1345 0x7e40, 0x7e44, 1346 0x7e4c, 0x7e78, 1347 0x7e80, 0x7edc, 1348 0x7ee8, 0x7efc, 1349 0x8dc0, 0x8de0, 1350 0x8df8, 0x8e04, 1351 0x8e10, 0x8e84, 1352 0x8ea0, 0x8f84, 1353 0x8fc0, 0x9058, 1354 0x9060, 0x9060, 1355 0x9068, 0x90f8, 1356 0x9400, 0x9408, 1357 0x9410, 0x9470, 1358 0x9600, 0x9600, 1359 0x9608, 0x9638, 1360 0x9640, 0x96f4, 1361 0x9800, 0x9808, 1362 0x9820, 0x983c, 1363 0x9850, 0x9864, 1364 0x9c00, 0x9c6c, 1365 0x9c80, 0x9cec, 1366 0x9d00, 0x9d6c, 1367 0x9d80, 0x9dec, 1368 0x9e00, 0x9e6c, 1369 0x9e80, 0x9eec, 1370 0x9f00, 0x9f6c, 1371 0x9f80, 0xa020, 1372 0xd004, 0xd004, 1373 0xd010, 0xd03c, 1374 0xdfc0, 0xdfe0, 1375 0xe000, 0x1106c, 1376 0x11074, 0x11088, 1377 0x1109c, 0x1117c, 1378 0x11190, 0x11204, 1379 0x19040, 0x1906c, 1380 0x19078, 0x19080, 1381 0x1908c, 0x190e8, 1382 0x190f0, 0x190f8, 1383 0x19100, 0x19110, 1384 0x19120, 0x19124, 1385 0x19150, 0x19194, 1386 0x1919c, 0x191b0, 1387 0x191d0, 0x191e8, 1388 0x19238, 0x19290, 1389 0x193f8, 0x19428, 1390 0x19430, 0x19444, 1391 0x1944c, 0x1946c, 1392 0x19474, 0x19474, 1393 0x19490, 0x194cc, 1394 0x194f0, 0x194f8, 1395 0x19c00, 0x19c08, 1396 0x19c10, 0x19c60, 1397 0x19c94, 0x19ce4, 1398 0x19cf0, 0x19d40, 1399 0x19d50, 0x19d94, 1400 0x19da0, 0x19de8, 1401 0x19df0, 0x19e10, 1402 0x19e50, 0x19e90, 1403 0x19ea0, 0x19f24, 1404 0x19f34, 0x19f34, 1405 0x19f40, 0x19f50, 1406 0x19f90, 0x19fb4, 1407 0x19fc4, 0x19fe4, 1408 0x1a000, 0x1a004, 1409 0x1a010, 0x1a06c, 1410 0x1a0b0, 0x1a0e4, 1411 0x1a0ec, 0x1a0f8, 1412 0x1a100, 0x1a108, 1413 0x1a114, 0x1a120, 1414 0x1a128, 0x1a130, 1415 0x1a138, 0x1a138, 1416 0x1a190, 0x1a1c4, 1417 0x1a1fc, 0x1a1fc, 1418 0x1e008, 0x1e00c, 1419 0x1e040, 0x1e044, 1420 0x1e04c, 0x1e04c, 1421 0x1e284, 0x1e290, 1422 0x1e2c0, 0x1e2c0, 1423 0x1e2e0, 0x1e2e0, 1424 0x1e300, 0x1e384, 1425 0x1e3c0, 0x1e3c8, 1426 0x1e408, 0x1e40c, 1427 0x1e440, 0x1e444, 1428 0x1e44c, 0x1e44c, 1429 0x1e684, 0x1e690, 1430 0x1e6c0, 0x1e6c0, 1431 0x1e6e0, 0x1e6e0, 1432 0x1e700, 0x1e784, 1433 0x1e7c0, 0x1e7c8, 1434 0x1e808, 0x1e80c, 1435 0x1e840, 0x1e844, 1436 0x1e84c, 0x1e84c, 1437 0x1ea84, 0x1ea90, 1438 0x1eac0, 0x1eac0, 1439 0x1eae0, 0x1eae0, 1440 0x1eb00, 0x1eb84, 1441 0x1ebc0, 0x1ebc8, 1442 0x1ec08, 0x1ec0c, 1443 0x1ec40, 0x1ec44, 1444 0x1ec4c, 0x1ec4c, 1445 0x1ee84, 0x1ee90, 1446 0x1eec0, 0x1eec0, 1447 0x1eee0, 0x1eee0, 1448 0x1ef00, 0x1ef84, 1449 0x1efc0, 0x1efc8, 1450 0x1f008, 0x1f00c, 1451 0x1f040, 0x1f044, 1452 0x1f04c, 0x1f04c, 1453 0x1f284, 0x1f290, 1454 0x1f2c0, 0x1f2c0, 1455 0x1f2e0, 0x1f2e0, 1456 0x1f300, 0x1f384, 1457 0x1f3c0, 0x1f3c8, 1458 0x1f408, 0x1f40c, 1459 0x1f440, 0x1f444, 1460 0x1f44c, 0x1f44c, 1461 0x1f684, 0x1f690, 1462 0x1f6c0, 0x1f6c0, 1463 0x1f6e0, 0x1f6e0, 1464 0x1f700, 0x1f784, 1465 0x1f7c0, 0x1f7c8, 1466 0x1f808, 0x1f80c, 1467 0x1f840, 0x1f844, 1468 0x1f84c, 0x1f84c, 1469 0x1fa84, 0x1fa90, 1470 0x1fac0, 0x1fac0, 1471 0x1fae0, 0x1fae0, 1472 0x1fb00, 0x1fb84, 1473 0x1fbc0, 0x1fbc8, 1474 0x1fc08, 0x1fc0c, 1475 0x1fc40, 0x1fc44, 1476 0x1fc4c, 0x1fc4c, 1477 0x1fe84, 0x1fe90, 1478 0x1fec0, 0x1fec0, 1479 0x1fee0, 0x1fee0, 1480 0x1ff00, 0x1ff84, 1481 0x1ffc0, 0x1ffc8, 1482 0x30000, 0x30030, 1483 0x30100, 0x30144, 1484 0x30190, 0x301a0, 1485 0x301a8, 0x301b8, 1486 0x301c4, 0x301c8, 1487 0x301d0, 0x301d0, 1488 0x30200, 0x30318, 1489 0x30400, 0x304b4, 1490 0x304c0, 0x3052c, 1491 0x30540, 0x3061c, 1492 0x30800, 0x30828, 1493 0x30834, 0x30834, 1494 0x308c0, 0x30908, 1495 0x30910, 0x309ac, 1496 0x30a00, 0x30a14, 1497 0x30a1c, 0x30a2c, 1498 0x30a44, 0x30a50, 1499 0x30a74, 0x30a74, 1500 0x30a7c, 0x30afc, 1501 0x30b08, 0x30c24, 1502 0x30d00, 0x30d00, 1503 0x30d08, 0x30d14, 1504 0x30d1c, 0x30d20, 1505 0x30d3c, 0x30d3c, 1506 0x30d48, 0x30d50, 1507 0x31200, 0x3120c, 1508 0x31220, 0x31220, 1509 0x31240, 0x31240, 1510 0x31600, 0x3160c, 1511 0x31a00, 0x31a1c, 1512 0x31e00, 0x31e20, 1513 0x31e38, 0x31e3c, 1514 0x31e80, 0x31e80, 1515 0x31e88, 0x31ea8, 1516 0x31eb0, 0x31eb4, 1517 0x31ec8, 0x31ed4, 1518 0x31fb8, 0x32004, 1519 0x32200, 0x32200, 1520 0x32208, 0x32240, 1521 0x32248, 0x32280, 1522 0x32288, 0x322c0, 1523 0x322c8, 0x322fc, 1524 0x32600, 0x32630, 1525 0x32a00, 0x32abc, 1526 0x32b00, 0x32b10, 1527 0x32b20, 0x32b30, 1528 0x32b40, 0x32b50, 1529 0x32b60, 0x32b70, 1530 0x33000, 0x33028, 1531 0x33030, 0x33048, 1532 0x33060, 0x33068, 1533 0x33070, 0x3309c, 1534 0x330f0, 0x33128, 1535 0x33130, 0x33148, 1536 0x33160, 0x33168, 1537 0x33170, 0x3319c, 1538 0x331f0, 0x33238, 1539 0x33240, 0x33240, 1540 0x33248, 0x33250, 1541 0x3325c, 0x33264, 1542 0x33270, 0x332b8, 1543 0x332c0, 0x332e4, 1544 0x332f8, 0x33338, 1545 0x33340, 0x33340, 1546 0x33348, 0x33350, 1547 0x3335c, 0x33364, 1548 0x33370, 0x333b8, 1549 0x333c0, 0x333e4, 1550 0x333f8, 0x33428, 1551 0x33430, 0x33448, 1552 0x33460, 0x33468, 1553 0x33470, 0x3349c, 1554 0x334f0, 0x33528, 1555 0x33530, 0x33548, 1556 0x33560, 0x33568, 1557 0x33570, 0x3359c, 1558 0x335f0, 0x33638, 1559 0x33640, 0x33640, 1560 0x33648, 0x33650, 1561 0x3365c, 0x33664, 1562 0x33670, 0x336b8, 1563 0x336c0, 0x336e4, 1564 0x336f8, 0x33738, 1565 0x33740, 0x33740, 1566 0x33748, 0x33750, 1567 0x3375c, 0x33764, 1568 0x33770, 0x337b8, 1569 0x337c0, 0x337e4, 1570 0x337f8, 0x337fc, 1571 0x33814, 0x33814, 1572 0x3382c, 0x3382c, 1573 0x33880, 0x3388c, 1574 0x338e8, 0x338ec, 1575 0x33900, 0x33928, 1576 0x33930, 0x33948, 1577 0x33960, 0x33968, 1578 0x33970, 0x3399c, 1579 0x339f0, 0x33a38, 1580 0x33a40, 0x33a40, 1581 0x33a48, 0x33a50, 1582 0x33a5c, 0x33a64, 1583 0x33a70, 0x33ab8, 1584 0x33ac0, 0x33ae4, 1585 0x33af8, 0x33b10, 1586 0x33b28, 0x33b28, 1587 0x33b3c, 0x33b50, 1588 0x33bf0, 0x33c10, 1589 0x33c28, 0x33c28, 1590 0x33c3c, 0x33c50, 1591 0x33cf0, 0x33cfc, 1592 0x34000, 0x34030, 1593 0x34100, 0x34144, 1594 0x34190, 0x341a0, 1595 0x341a8, 0x341b8, 1596 0x341c4, 0x341c8, 1597 0x341d0, 0x341d0, 1598 0x34200, 0x34318, 1599 0x34400, 0x344b4, 1600 0x344c0, 0x3452c, 1601 0x34540, 0x3461c, 1602 0x34800, 0x34828, 1603 0x34834, 0x34834, 1604 0x348c0, 0x34908, 1605 0x34910, 0x349ac, 1606 0x34a00, 0x34a14, 1607 0x34a1c, 0x34a2c, 1608 0x34a44, 0x34a50, 1609 0x34a74, 0x34a74, 1610 0x34a7c, 0x34afc, 1611 0x34b08, 0x34c24, 1612 0x34d00, 0x34d00, 1613 0x34d08, 0x34d14, 1614 0x34d1c, 0x34d20, 1615 0x34d3c, 0x34d3c, 1616 0x34d48, 0x34d50, 1617 0x35200, 0x3520c, 1618 0x35220, 0x35220, 1619 0x35240, 0x35240, 1620 0x35600, 0x3560c, 1621 0x35a00, 0x35a1c, 1622 0x35e00, 0x35e20, 1623 0x35e38, 0x35e3c, 1624 0x35e80, 0x35e80, 1625 0x35e88, 0x35ea8, 1626 0x35eb0, 0x35eb4, 1627 0x35ec8, 0x35ed4, 1628 0x35fb8, 0x36004, 1629 0x36200, 0x36200, 1630 0x36208, 0x36240, 1631 0x36248, 0x36280, 1632 0x36288, 0x362c0, 1633 0x362c8, 0x362fc, 1634 0x36600, 0x36630, 1635 0x36a00, 0x36abc, 1636 0x36b00, 0x36b10, 1637 0x36b20, 0x36b30, 1638 0x36b40, 0x36b50, 1639 0x36b60, 0x36b70, 1640 0x37000, 0x37028, 1641 0x37030, 0x37048, 1642 0x37060, 0x37068, 1643 0x37070, 0x3709c, 1644 0x370f0, 0x37128, 1645 0x37130, 0x37148, 1646 0x37160, 0x37168, 1647 0x37170, 0x3719c, 1648 0x371f0, 0x37238, 1649 0x37240, 0x37240, 1650 0x37248, 0x37250, 1651 0x3725c, 0x37264, 1652 0x37270, 0x372b8, 1653 0x372c0, 0x372e4, 1654 0x372f8, 0x37338, 1655 0x37340, 0x37340, 1656 0x37348, 0x37350, 1657 0x3735c, 0x37364, 1658 0x37370, 0x373b8, 1659 0x373c0, 0x373e4, 1660 0x373f8, 0x37428, 1661 0x37430, 0x37448, 1662 0x37460, 0x37468, 1663 0x37470, 0x3749c, 1664 0x374f0, 0x37528, 1665 0x37530, 0x37548, 1666 0x37560, 0x37568, 1667 0x37570, 0x3759c, 1668 0x375f0, 0x37638, 1669 0x37640, 0x37640, 1670 0x37648, 0x37650, 1671 0x3765c, 0x37664, 1672 0x37670, 0x376b8, 1673 0x376c0, 0x376e4, 1674 0x376f8, 0x37738, 1675 0x37740, 0x37740, 1676 0x37748, 0x37750, 1677 0x3775c, 0x37764, 1678 0x37770, 0x377b8, 1679 0x377c0, 0x377e4, 1680 0x377f8, 0x377fc, 1681 0x37814, 0x37814, 1682 0x3782c, 0x3782c, 1683 0x37880, 0x3788c, 1684 0x378e8, 0x378ec, 1685 0x37900, 0x37928, 1686 0x37930, 0x37948, 1687 0x37960, 0x37968, 1688 0x37970, 0x3799c, 1689 0x379f0, 0x37a38, 1690 0x37a40, 0x37a40, 1691 0x37a48, 0x37a50, 1692 0x37a5c, 0x37a64, 1693 0x37a70, 0x37ab8, 1694 0x37ac0, 0x37ae4, 1695 0x37af8, 0x37b10, 1696 0x37b28, 0x37b28, 1697 0x37b3c, 0x37b50, 1698 0x37bf0, 0x37c10, 1699 0x37c28, 0x37c28, 1700 0x37c3c, 0x37c50, 1701 0x37cf0, 0x37cfc, 1702 0x38000, 0x38030, 1703 0x38100, 0x38144, 1704 0x38190, 0x381a0, 1705 0x381a8, 0x381b8, 1706 0x381c4, 0x381c8, 1707 0x381d0, 0x381d0, 1708 0x38200, 0x38318, 1709 0x38400, 0x384b4, 1710 0x384c0, 0x3852c, 1711 0x38540, 0x3861c, 1712 0x38800, 0x38828, 1713 0x38834, 0x38834, 1714 0x388c0, 0x38908, 1715 0x38910, 0x389ac, 1716 0x38a00, 0x38a14, 1717 0x38a1c, 0x38a2c, 1718 0x38a44, 0x38a50, 1719 0x38a74, 0x38a74, 1720 0x38a7c, 0x38afc, 1721 0x38b08, 0x38c24, 1722 0x38d00, 0x38d00, 1723 0x38d08, 0x38d14, 1724 0x38d1c, 0x38d20, 1725 0x38d3c, 0x38d3c, 1726 0x38d48, 0x38d50, 1727 0x39200, 0x3920c, 1728 0x39220, 0x39220, 1729 0x39240, 0x39240, 1730 0x39600, 0x3960c, 1731 0x39a00, 0x39a1c, 1732 0x39e00, 0x39e20, 1733 0x39e38, 0x39e3c, 1734 0x39e80, 0x39e80, 1735 0x39e88, 0x39ea8, 1736 0x39eb0, 0x39eb4, 1737 0x39ec8, 0x39ed4, 1738 0x39fb8, 0x3a004, 1739 0x3a200, 0x3a200, 1740 0x3a208, 0x3a240, 1741 0x3a248, 0x3a280, 1742 0x3a288, 0x3a2c0, 1743 0x3a2c8, 0x3a2fc, 1744 0x3a600, 0x3a630, 1745 0x3aa00, 0x3aabc, 1746 0x3ab00, 0x3ab10, 1747 0x3ab20, 0x3ab30, 1748 0x3ab40, 0x3ab50, 1749 0x3ab60, 0x3ab70, 1750 0x3b000, 0x3b028, 1751 0x3b030, 0x3b048, 1752 0x3b060, 0x3b068, 1753 0x3b070, 0x3b09c, 1754 0x3b0f0, 0x3b128, 1755 0x3b130, 0x3b148, 1756 0x3b160, 0x3b168, 1757 0x3b170, 0x3b19c, 1758 0x3b1f0, 0x3b238, 1759 0x3b240, 0x3b240, 1760 0x3b248, 0x3b250, 1761 0x3b25c, 0x3b264, 1762 0x3b270, 0x3b2b8, 1763 0x3b2c0, 0x3b2e4, 1764 0x3b2f8, 0x3b338, 1765 0x3b340, 0x3b340, 1766 0x3b348, 0x3b350, 1767 0x3b35c, 0x3b364, 1768 0x3b370, 0x3b3b8, 1769 0x3b3c0, 0x3b3e4, 1770 0x3b3f8, 0x3b428, 1771 0x3b430, 0x3b448, 1772 0x3b460, 0x3b468, 1773 0x3b470, 0x3b49c, 1774 0x3b4f0, 0x3b528, 1775 0x3b530, 0x3b548, 1776 0x3b560, 0x3b568, 1777 0x3b570, 0x3b59c, 1778 0x3b5f0, 0x3b638, 1779 0x3b640, 0x3b640, 1780 0x3b648, 0x3b650, 1781 0x3b65c, 0x3b664, 1782 0x3b670, 0x3b6b8, 1783 0x3b6c0, 0x3b6e4, 1784 0x3b6f8, 0x3b738, 1785 0x3b740, 0x3b740, 1786 0x3b748, 0x3b750, 1787 0x3b75c, 0x3b764, 1788 0x3b770, 0x3b7b8, 1789 0x3b7c0, 0x3b7e4, 1790 0x3b7f8, 0x3b7fc, 1791 0x3b814, 0x3b814, 1792 0x3b82c, 0x3b82c, 1793 0x3b880, 0x3b88c, 1794 0x3b8e8, 0x3b8ec, 1795 0x3b900, 0x3b928, 1796 0x3b930, 0x3b948, 1797 0x3b960, 0x3b968, 1798 0x3b970, 0x3b99c, 1799 0x3b9f0, 0x3ba38, 1800 0x3ba40, 0x3ba40, 1801 0x3ba48, 0x3ba50, 1802 0x3ba5c, 0x3ba64, 1803 0x3ba70, 0x3bab8, 1804 0x3bac0, 0x3bae4, 1805 0x3baf8, 0x3bb10, 1806 0x3bb28, 0x3bb28, 1807 0x3bb3c, 0x3bb50, 1808 0x3bbf0, 0x3bc10, 1809 0x3bc28, 0x3bc28, 1810 0x3bc3c, 0x3bc50, 1811 0x3bcf0, 0x3bcfc, 1812 0x3c000, 0x3c030, 1813 0x3c100, 0x3c144, 1814 0x3c190, 0x3c1a0, 1815 0x3c1a8, 0x3c1b8, 1816 0x3c1c4, 0x3c1c8, 1817 0x3c1d0, 0x3c1d0, 1818 0x3c200, 0x3c318, 1819 0x3c400, 0x3c4b4, 1820 0x3c4c0, 0x3c52c, 1821 0x3c540, 0x3c61c, 1822 0x3c800, 0x3c828, 1823 0x3c834, 0x3c834, 1824 0x3c8c0, 0x3c908, 1825 0x3c910, 0x3c9ac, 1826 0x3ca00, 0x3ca14, 1827 0x3ca1c, 0x3ca2c, 1828 0x3ca44, 0x3ca50, 1829 0x3ca74, 0x3ca74, 1830 0x3ca7c, 0x3cafc, 1831 0x3cb08, 0x3cc24, 1832 0x3cd00, 0x3cd00, 1833 0x3cd08, 0x3cd14, 1834 0x3cd1c, 0x3cd20, 1835 0x3cd3c, 0x3cd3c, 1836 0x3cd48, 0x3cd50, 1837 0x3d200, 0x3d20c, 1838 0x3d220, 0x3d220, 1839 0x3d240, 0x3d240, 1840 0x3d600, 0x3d60c, 1841 0x3da00, 0x3da1c, 1842 0x3de00, 0x3de20, 1843 0x3de38, 0x3de3c, 1844 0x3de80, 0x3de80, 1845 0x3de88, 0x3dea8, 1846 0x3deb0, 0x3deb4, 1847 0x3dec8, 0x3ded4, 1848 0x3dfb8, 0x3e004, 1849 0x3e200, 0x3e200, 1850 0x3e208, 0x3e240, 1851 0x3e248, 0x3e280, 1852 0x3e288, 0x3e2c0, 1853 0x3e2c8, 0x3e2fc, 1854 0x3e600, 0x3e630, 1855 0x3ea00, 0x3eabc, 1856 0x3eb00, 0x3eb10, 1857 0x3eb20, 0x3eb30, 1858 0x3eb40, 0x3eb50, 1859 0x3eb60, 0x3eb70, 1860 0x3f000, 0x3f028, 1861 0x3f030, 0x3f048, 1862 0x3f060, 0x3f068, 1863 0x3f070, 0x3f09c, 1864 0x3f0f0, 0x3f128, 1865 0x3f130, 0x3f148, 1866 0x3f160, 0x3f168, 1867 0x3f170, 0x3f19c, 1868 0x3f1f0, 0x3f238, 1869 0x3f240, 0x3f240, 1870 0x3f248, 0x3f250, 1871 0x3f25c, 0x3f264, 1872 0x3f270, 0x3f2b8, 1873 0x3f2c0, 0x3f2e4, 1874 0x3f2f8, 0x3f338, 1875 0x3f340, 0x3f340, 1876 0x3f348, 0x3f350, 1877 0x3f35c, 0x3f364, 1878 0x3f370, 0x3f3b8, 1879 0x3f3c0, 0x3f3e4, 1880 0x3f3f8, 0x3f428, 1881 0x3f430, 0x3f448, 1882 0x3f460, 0x3f468, 1883 0x3f470, 0x3f49c, 1884 0x3f4f0, 0x3f528, 1885 0x3f530, 0x3f548, 1886 0x3f560, 0x3f568, 1887 0x3f570, 0x3f59c, 1888 0x3f5f0, 0x3f638, 1889 0x3f640, 0x3f640, 1890 0x3f648, 0x3f650, 1891 0x3f65c, 0x3f664, 1892 0x3f670, 0x3f6b8, 1893 0x3f6c0, 0x3f6e4, 1894 0x3f6f8, 0x3f738, 1895 0x3f740, 0x3f740, 1896 0x3f748, 0x3f750, 1897 0x3f75c, 0x3f764, 1898 0x3f770, 0x3f7b8, 1899 0x3f7c0, 0x3f7e4, 1900 0x3f7f8, 0x3f7fc, 1901 0x3f814, 0x3f814, 1902 0x3f82c, 0x3f82c, 1903 0x3f880, 0x3f88c, 1904 0x3f8e8, 0x3f8ec, 1905 0x3f900, 0x3f928, 1906 0x3f930, 0x3f948, 1907 0x3f960, 0x3f968, 1908 0x3f970, 0x3f99c, 1909 0x3f9f0, 0x3fa38, 1910 0x3fa40, 0x3fa40, 1911 0x3fa48, 0x3fa50, 1912 0x3fa5c, 0x3fa64, 1913 0x3fa70, 0x3fab8, 1914 0x3fac0, 0x3fae4, 1915 0x3faf8, 0x3fb10, 1916 0x3fb28, 0x3fb28, 1917 0x3fb3c, 0x3fb50, 1918 0x3fbf0, 0x3fc10, 1919 0x3fc28, 0x3fc28, 1920 0x3fc3c, 0x3fc50, 1921 0x3fcf0, 0x3fcfc, 1922 0x40000, 0x4000c, 1923 0x40040, 0x40050, 1924 0x40060, 0x40068, 1925 0x4007c, 0x4008c, 1926 0x40094, 0x400b0, 1927 0x400c0, 0x40144, 1928 0x40180, 0x4018c, 1929 0x40200, 0x40254, 1930 0x40260, 0x40264, 1931 0x40270, 0x40288, 1932 0x40290, 0x40298, 1933 0x402ac, 0x402c8, 1934 0x402d0, 0x402e0, 1935 0x402f0, 0x402f0, 1936 0x40300, 0x4033c, 1937 0x403f8, 0x403fc, 1938 0x41304, 0x413c4, 1939 0x41400, 0x4140c, 1940 0x41414, 0x4141c, 1941 0x41480, 0x414d0, 1942 0x44000, 0x44054, 1943 0x4405c, 0x44078, 1944 0x440c0, 0x44174, 1945 0x44180, 0x441ac, 1946 0x441b4, 0x441b8, 1947 0x441c0, 0x44254, 1948 0x4425c, 0x44278, 1949 0x442c0, 0x44374, 1950 0x44380, 0x443ac, 1951 0x443b4, 0x443b8, 1952 0x443c0, 0x44454, 1953 0x4445c, 0x44478, 1954 0x444c0, 0x44574, 1955 0x44580, 0x445ac, 1956 0x445b4, 0x445b8, 1957 0x445c0, 0x44654, 1958 0x4465c, 0x44678, 1959 0x446c0, 0x44774, 1960 0x44780, 0x447ac, 1961 0x447b4, 0x447b8, 1962 0x447c0, 0x44854, 1963 0x4485c, 0x44878, 1964 0x448c0, 0x44974, 1965 0x44980, 0x449ac, 1966 0x449b4, 0x449b8, 1967 0x449c0, 0x449fc, 1968 0x45000, 0x45004, 1969 0x45010, 0x45030, 1970 0x45040, 0x45060, 1971 0x45068, 0x45068, 1972 0x45080, 0x45084, 1973 0x450a0, 0x450b0, 1974 0x45200, 0x45204, 1975 0x45210, 0x45230, 1976 0x45240, 0x45260, 1977 0x45268, 0x45268, 1978 0x45280, 0x45284, 1979 0x452a0, 0x452b0, 1980 0x460c0, 0x460e4, 1981 0x47000, 0x4703c, 1982 0x47044, 0x4708c, 1983 0x47200, 0x47250, 1984 0x47400, 0x47408, 1985 0x47414, 0x47420, 1986 0x47600, 0x47618, 1987 0x47800, 0x47814, 1988 0x48000, 0x4800c, 1989 0x48040, 0x48050, 1990 0x48060, 0x48068, 1991 0x4807c, 0x4808c, 1992 0x48094, 0x480b0, 1993 0x480c0, 0x48144, 1994 0x48180, 0x4818c, 1995 0x48200, 0x48254, 1996 0x48260, 0x48264, 1997 0x48270, 0x48288, 1998 0x48290, 0x48298, 1999 0x482ac, 0x482c8, 2000 0x482d0, 0x482e0, 2001 0x482f0, 0x482f0, 2002 0x48300, 0x4833c, 2003 0x483f8, 0x483fc, 2004 0x49304, 0x493c4, 2005 0x49400, 0x4940c, 2006 0x49414, 0x4941c, 2007 0x49480, 0x494d0, 2008 0x4c000, 0x4c054, 2009 0x4c05c, 0x4c078, 2010 0x4c0c0, 0x4c174, 2011 0x4c180, 0x4c1ac, 2012 0x4c1b4, 0x4c1b8, 2013 0x4c1c0, 0x4c254, 2014 0x4c25c, 0x4c278, 2015 0x4c2c0, 0x4c374, 2016 0x4c380, 0x4c3ac, 2017 0x4c3b4, 0x4c3b8, 2018 0x4c3c0, 0x4c454, 2019 0x4c45c, 0x4c478, 2020 0x4c4c0, 0x4c574, 2021 0x4c580, 0x4c5ac, 2022 0x4c5b4, 0x4c5b8, 2023 0x4c5c0, 0x4c654, 2024 0x4c65c, 0x4c678, 2025 0x4c6c0, 0x4c774, 2026 0x4c780, 0x4c7ac, 2027 0x4c7b4, 0x4c7b8, 2028 0x4c7c0, 0x4c854, 2029 0x4c85c, 0x4c878, 2030 0x4c8c0, 0x4c974, 2031 0x4c980, 0x4c9ac, 2032 0x4c9b4, 0x4c9b8, 2033 0x4c9c0, 0x4c9fc, 2034 0x4d000, 0x4d004, 2035 0x4d010, 0x4d030, 2036 0x4d040, 0x4d060, 2037 0x4d068, 0x4d068, 2038 0x4d080, 0x4d084, 2039 0x4d0a0, 0x4d0b0, 2040 0x4d200, 0x4d204, 2041 0x4d210, 0x4d230, 2042 0x4d240, 0x4d260, 2043 0x4d268, 0x4d268, 2044 0x4d280, 0x4d284, 2045 0x4d2a0, 0x4d2b0, 2046 0x4e0c0, 0x4e0e4, 2047 0x4f000, 0x4f03c, 2048 0x4f044, 0x4f08c, 2049 0x4f200, 0x4f250, 2050 0x4f400, 0x4f408, 2051 0x4f414, 0x4f420, 2052 0x4f600, 0x4f618, 2053 0x4f800, 0x4f814, 2054 0x50000, 0x50084, 2055 0x50090, 0x500cc, 2056 0x50400, 0x50400, 2057 0x50800, 0x50884, 2058 0x50890, 0x508cc, 2059 0x50c00, 0x50c00, 2060 0x51000, 0x5101c, 2061 0x51300, 0x51308, 2062 }; 2063 2064 static const unsigned int t5vf_reg_ranges[] = { 2065 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2066 VF_MPS_REG(A_MPS_VF_CTL), 2067 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2068 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2069 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2070 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2071 FW_T4VF_MBDATA_BASE_ADDR, 2072 FW_T4VF_MBDATA_BASE_ADDR + 2073 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2074 }; 2075 2076 static const unsigned int t6_reg_ranges[] = { 2077 0x1008, 0x101c, 2078 0x1024, 0x10a8, 2079 0x10b4, 0x10f8, 2080 0x1100, 0x1114, 2081 0x111c, 0x112c, 2082 0x1138, 0x113c, 2083 0x1144, 0x114c, 2084 0x1180, 0x1184, 2085 0x1190, 0x1194, 2086 0x11a0, 0x11a4, 2087 0x11b0, 0x11b4, 2088 0x11fc, 0x1274, 2089 0x1280, 0x133c, 2090 0x1800, 0x18fc, 2091 0x3000, 0x302c, 2092 0x3060, 0x30b0, 2093 0x30b8, 0x30d8, 2094 0x30e0, 0x30fc, 2095 0x3140, 0x357c, 2096 0x35a8, 0x35cc, 2097 0x35ec, 0x35ec, 2098 0x3600, 0x5624, 2099 0x56cc, 0x56ec, 2100 0x56f4, 0x5720, 2101 0x5728, 0x575c, 2102 0x580c, 0x5814, 2103 0x5890, 0x589c, 2104 0x58a4, 0x58ac, 2105 0x58b8, 0x58bc, 2106 0x5940, 0x595c, 2107 0x5980, 0x598c, 2108 0x59b0, 0x59c8, 2109 0x59d0, 0x59dc, 2110 0x59fc, 0x5a18, 2111 0x5a60, 0x5a6c, 2112 0x5a80, 0x5a8c, 2113 0x5a94, 0x5a9c, 2114 0x5b94, 0x5bfc, 2115 0x5c10, 0x5e48, 2116 0x5e50, 0x5e94, 2117 0x5ea0, 0x5eb0, 2118 0x5ec0, 0x5ec0, 2119 0x5ec8, 0x5ed0, 2120 0x5ee0, 0x5ee0, 2121 0x5ef0, 0x5ef0, 2122 0x5f00, 0x5f00, 2123 0x6000, 0x6020, 2124 0x6028, 0x6040, 2125 0x6058, 0x609c, 2126 0x60a8, 0x619c, 2127 0x7700, 0x7798, 2128 0x77c0, 0x7880, 2129 0x78cc, 0x78fc, 2130 0x7b00, 0x7b58, 2131 0x7b60, 0x7b84, 2132 0x7b8c, 0x7c54, 2133 0x7d00, 0x7d38, 2134 0x7d40, 0x7d84, 2135 0x7d8c, 0x7ddc, 2136 0x7de4, 0x7e04, 2137 0x7e10, 0x7e1c, 2138 0x7e24, 0x7e38, 2139 0x7e40, 0x7e44, 2140 0x7e4c, 0x7e78, 2141 0x7e80, 0x7edc, 2142 0x7ee8, 0x7efc, 2143 0x8dc0, 0x8de4, 2144 0x8df8, 0x8e04, 2145 0x8e10, 0x8e84, 2146 0x8ea0, 0x8f88, 2147 0x8fb8, 0x9058, 2148 0x9060, 0x9060, 2149 0x9068, 0x90f8, 2150 0x9100, 0x9124, 2151 0x9400, 0x9470, 2152 0x9600, 0x9600, 2153 0x9608, 0x9638, 2154 0x9640, 0x9704, 2155 0x9710, 0x971c, 2156 0x9800, 0x9808, 2157 0x9820, 0x983c, 2158 0x9850, 0x9864, 2159 0x9c00, 0x9c6c, 2160 0x9c80, 0x9cec, 2161 0x9d00, 0x9d6c, 2162 0x9d80, 0x9dec, 2163 0x9e00, 0x9e6c, 2164 0x9e80, 0x9eec, 2165 0x9f00, 0x9f6c, 2166 0x9f80, 0xa020, 2167 0xd004, 0xd03c, 2168 0xd100, 0xd118, 2169 0xd200, 0xd214, 2170 0xd220, 0xd234, 2171 0xd240, 0xd254, 2172 0xd260, 0xd274, 2173 0xd280, 0xd294, 2174 0xd2a0, 0xd2b4, 2175 0xd2c0, 0xd2d4, 2176 0xd2e0, 0xd2f4, 2177 0xd300, 0xd31c, 2178 0xdfc0, 0xdfe0, 2179 0xe000, 0xf008, 2180 0xf010, 0xf018, 2181 0xf020, 0xf028, 2182 0x11000, 0x11014, 2183 0x11048, 0x1106c, 2184 0x11074, 0x11088, 2185 0x11098, 0x11120, 2186 0x1112c, 0x1117c, 2187 0x11190, 0x112e0, 2188 0x11300, 0x1130c, 2189 0x12000, 0x1206c, 2190 0x19040, 0x1906c, 2191 0x19078, 0x19080, 2192 0x1908c, 0x190e8, 2193 0x190f0, 0x190f8, 2194 0x19100, 0x19110, 2195 0x19120, 0x19124, 2196 0x19150, 0x19194, 2197 0x1919c, 0x191b0, 2198 0x191d0, 0x191e8, 2199 0x19238, 0x19290, 2200 0x192a4, 0x192b0, 2201 0x192bc, 0x192bc, 2202 0x19348, 0x1934c, 2203 0x193f8, 0x19418, 2204 0x19420, 0x19428, 2205 0x19430, 0x19444, 2206 0x1944c, 0x1946c, 2207 0x19474, 0x19474, 2208 0x19490, 0x194cc, 2209 0x194f0, 0x194f8, 2210 0x19c00, 0x19c48, 2211 0x19c50, 0x19c80, 2212 0x19c94, 0x19c98, 2213 0x19ca0, 0x19cbc, 2214 0x19ce4, 0x19ce4, 2215 0x19cf0, 0x19cf8, 2216 0x19d00, 0x19d28, 2217 0x19d50, 0x19d78, 2218 0x19d94, 0x19d98, 2219 0x19da0, 0x19dc8, 2220 0x19df0, 0x19e10, 2221 0x19e50, 0x19e6c, 2222 0x19ea0, 0x19ebc, 2223 0x19ec4, 0x19ef4, 2224 0x19f04, 0x19f2c, 2225 0x19f34, 0x19f34, 2226 0x19f40, 0x19f50, 2227 0x19f90, 0x19fac, 2228 0x19fc4, 0x19fc8, 2229 0x19fd0, 0x19fe4, 2230 0x1a000, 0x1a004, 2231 0x1a010, 0x1a06c, 2232 0x1a0b0, 0x1a0e4, 2233 0x1a0ec, 0x1a0f8, 2234 0x1a100, 0x1a108, 2235 0x1a114, 0x1a120, 2236 0x1a128, 0x1a130, 2237 0x1a138, 0x1a138, 2238 0x1a190, 0x1a1c4, 2239 0x1a1fc, 0x1a1fc, 2240 0x1e008, 0x1e00c, 2241 0x1e040, 0x1e044, 2242 0x1e04c, 0x1e04c, 2243 0x1e284, 0x1e290, 2244 0x1e2c0, 0x1e2c0, 2245 0x1e2e0, 0x1e2e0, 2246 0x1e300, 0x1e384, 2247 0x1e3c0, 0x1e3c8, 2248 0x1e408, 0x1e40c, 2249 0x1e440, 0x1e444, 2250 0x1e44c, 0x1e44c, 2251 0x1e684, 0x1e690, 2252 0x1e6c0, 0x1e6c0, 2253 0x1e6e0, 0x1e6e0, 2254 0x1e700, 0x1e784, 2255 0x1e7c0, 0x1e7c8, 2256 0x1e808, 0x1e80c, 2257 0x1e840, 0x1e844, 2258 0x1e84c, 0x1e84c, 2259 0x1ea84, 0x1ea90, 2260 0x1eac0, 0x1eac0, 2261 0x1eae0, 0x1eae0, 2262 0x1eb00, 0x1eb84, 2263 0x1ebc0, 0x1ebc8, 2264 0x1ec08, 0x1ec0c, 2265 0x1ec40, 0x1ec44, 2266 0x1ec4c, 0x1ec4c, 2267 0x1ee84, 0x1ee90, 2268 0x1eec0, 0x1eec0, 2269 0x1eee0, 0x1eee0, 2270 0x1ef00, 0x1ef84, 2271 0x1efc0, 0x1efc8, 2272 0x1f008, 0x1f00c, 2273 0x1f040, 0x1f044, 2274 0x1f04c, 0x1f04c, 2275 0x1f284, 0x1f290, 2276 0x1f2c0, 0x1f2c0, 2277 0x1f2e0, 0x1f2e0, 2278 0x1f300, 0x1f384, 2279 0x1f3c0, 0x1f3c8, 2280 0x1f408, 0x1f40c, 2281 0x1f440, 0x1f444, 2282 0x1f44c, 0x1f44c, 2283 0x1f684, 0x1f690, 2284 0x1f6c0, 0x1f6c0, 2285 0x1f6e0, 0x1f6e0, 2286 0x1f700, 0x1f784, 2287 0x1f7c0, 0x1f7c8, 2288 0x1f808, 0x1f80c, 2289 0x1f840, 0x1f844, 2290 0x1f84c, 0x1f84c, 2291 0x1fa84, 0x1fa90, 2292 0x1fac0, 0x1fac0, 2293 0x1fae0, 0x1fae0, 2294 0x1fb00, 0x1fb84, 2295 0x1fbc0, 0x1fbc8, 2296 0x1fc08, 0x1fc0c, 2297 0x1fc40, 0x1fc44, 2298 0x1fc4c, 0x1fc4c, 2299 0x1fe84, 0x1fe90, 2300 0x1fec0, 0x1fec0, 2301 0x1fee0, 0x1fee0, 2302 0x1ff00, 0x1ff84, 2303 0x1ffc0, 0x1ffc8, 2304 0x30000, 0x30030, 2305 0x30100, 0x30168, 2306 0x30190, 0x301a0, 2307 0x301a8, 0x301b8, 2308 0x301c4, 0x301c8, 2309 0x301d0, 0x301d0, 2310 0x30200, 0x30320, 2311 0x30400, 0x304b4, 2312 0x304c0, 0x3052c, 2313 0x30540, 0x3061c, 2314 0x30800, 0x308a0, 2315 0x308c0, 0x30908, 2316 0x30910, 0x309b8, 2317 0x30a00, 0x30a04, 2318 0x30a0c, 0x30a14, 2319 0x30a1c, 0x30a2c, 2320 0x30a44, 0x30a50, 2321 0x30a74, 0x30a74, 2322 0x30a7c, 0x30afc, 2323 0x30b08, 0x30c24, 2324 0x30d00, 0x30d14, 2325 0x30d1c, 0x30d3c, 2326 0x30d44, 0x30d4c, 2327 0x30d54, 0x30d74, 2328 0x30d7c, 0x30d7c, 2329 0x30de0, 0x30de0, 2330 0x30e00, 0x30ed4, 2331 0x30f00, 0x30fa4, 2332 0x30fc0, 0x30fc4, 2333 0x31000, 0x31004, 2334 0x31080, 0x310fc, 2335 0x31208, 0x31220, 2336 0x3123c, 0x31254, 2337 0x31300, 0x31300, 2338 0x31308, 0x3131c, 2339 0x31338, 0x3133c, 2340 0x31380, 0x31380, 2341 0x31388, 0x313a8, 2342 0x313b4, 0x313b4, 2343 0x31400, 0x31420, 2344 0x31438, 0x3143c, 2345 0x31480, 0x31480, 2346 0x314a8, 0x314a8, 2347 0x314b0, 0x314b4, 2348 0x314c8, 0x314d4, 2349 0x31a40, 0x31a4c, 2350 0x31af0, 0x31b20, 2351 0x31b38, 0x31b3c, 2352 0x31b80, 0x31b80, 2353 0x31ba8, 0x31ba8, 2354 0x31bb0, 0x31bb4, 2355 0x31bc8, 0x31bd4, 2356 0x32140, 0x3218c, 2357 0x321f0, 0x321f4, 2358 0x32200, 0x32200, 2359 0x32218, 0x32218, 2360 0x32400, 0x32400, 2361 0x32408, 0x3241c, 2362 0x32618, 0x32620, 2363 0x32664, 0x32664, 2364 0x326a8, 0x326a8, 2365 0x326ec, 0x326ec, 2366 0x32a00, 0x32abc, 2367 0x32b00, 0x32b18, 2368 0x32b20, 0x32b38, 2369 0x32b40, 0x32b58, 2370 0x32b60, 0x32b78, 2371 0x32c00, 0x32c00, 2372 0x32c08, 0x32c3c, 2373 0x33000, 0x3302c, 2374 0x33034, 0x33050, 2375 0x33058, 0x33058, 2376 0x33060, 0x3308c, 2377 0x3309c, 0x330ac, 2378 0x330c0, 0x330c0, 2379 0x330c8, 0x330d0, 2380 0x330d8, 0x330e0, 2381 0x330ec, 0x3312c, 2382 0x33134, 0x33150, 2383 0x33158, 0x33158, 2384 0x33160, 0x3318c, 2385 0x3319c, 0x331ac, 2386 0x331c0, 0x331c0, 2387 0x331c8, 0x331d0, 2388 0x331d8, 0x331e0, 2389 0x331ec, 0x33290, 2390 0x33298, 0x332c4, 2391 0x332e4, 0x33390, 2392 0x33398, 0x333c4, 2393 0x333e4, 0x3342c, 2394 0x33434, 0x33450, 2395 0x33458, 0x33458, 2396 0x33460, 0x3348c, 2397 0x3349c, 0x334ac, 2398 0x334c0, 0x334c0, 2399 0x334c8, 0x334d0, 2400 0x334d8, 0x334e0, 2401 0x334ec, 0x3352c, 2402 0x33534, 0x33550, 2403 0x33558, 0x33558, 2404 0x33560, 0x3358c, 2405 0x3359c, 0x335ac, 2406 0x335c0, 0x335c0, 2407 0x335c8, 0x335d0, 2408 0x335d8, 0x335e0, 2409 0x335ec, 0x33690, 2410 0x33698, 0x336c4, 2411 0x336e4, 0x33790, 2412 0x33798, 0x337c4, 2413 0x337e4, 0x337fc, 2414 0x33814, 0x33814, 2415 0x33854, 0x33868, 2416 0x33880, 0x3388c, 2417 0x338c0, 0x338d0, 2418 0x338e8, 0x338ec, 2419 0x33900, 0x3392c, 2420 0x33934, 0x33950, 2421 0x33958, 0x33958, 2422 0x33960, 0x3398c, 2423 0x3399c, 0x339ac, 2424 0x339c0, 0x339c0, 2425 0x339c8, 0x339d0, 2426 0x339d8, 0x339e0, 2427 0x339ec, 0x33a90, 2428 0x33a98, 0x33ac4, 2429 0x33ae4, 0x33b10, 2430 0x33b24, 0x33b28, 2431 0x33b38, 0x33b50, 2432 0x33bf0, 0x33c10, 2433 0x33c24, 0x33c28, 2434 0x33c38, 0x33c50, 2435 0x33cf0, 0x33cfc, 2436 0x34000, 0x34030, 2437 0x34100, 0x34168, 2438 0x34190, 0x341a0, 2439 0x341a8, 0x341b8, 2440 0x341c4, 0x341c8, 2441 0x341d0, 0x341d0, 2442 0x34200, 0x34320, 2443 0x34400, 0x344b4, 2444 0x344c0, 0x3452c, 2445 0x34540, 0x3461c, 2446 0x34800, 0x348a0, 2447 0x348c0, 0x34908, 2448 0x34910, 0x349b8, 2449 0x34a00, 0x34a04, 2450 0x34a0c, 0x34a14, 2451 0x34a1c, 0x34a2c, 2452 0x34a44, 0x34a50, 2453 0x34a74, 0x34a74, 2454 0x34a7c, 0x34afc, 2455 0x34b08, 0x34c24, 2456 0x34d00, 0x34d14, 2457 0x34d1c, 0x34d3c, 2458 0x34d44, 0x34d4c, 2459 0x34d54, 0x34d74, 2460 0x34d7c, 0x34d7c, 2461 0x34de0, 0x34de0, 2462 0x34e00, 0x34ed4, 2463 0x34f00, 0x34fa4, 2464 0x34fc0, 0x34fc4, 2465 0x35000, 0x35004, 2466 0x35080, 0x350fc, 2467 0x35208, 0x35220, 2468 0x3523c, 0x35254, 2469 0x35300, 0x35300, 2470 0x35308, 0x3531c, 2471 0x35338, 0x3533c, 2472 0x35380, 0x35380, 2473 0x35388, 0x353a8, 2474 0x353b4, 0x353b4, 2475 0x35400, 0x35420, 2476 0x35438, 0x3543c, 2477 0x35480, 0x35480, 2478 0x354a8, 0x354a8, 2479 0x354b0, 0x354b4, 2480 0x354c8, 0x354d4, 2481 0x35a40, 0x35a4c, 2482 0x35af0, 0x35b20, 2483 0x35b38, 0x35b3c, 2484 0x35b80, 0x35b80, 2485 0x35ba8, 0x35ba8, 2486 0x35bb0, 0x35bb4, 2487 0x35bc8, 0x35bd4, 2488 0x36140, 0x3618c, 2489 0x361f0, 0x361f4, 2490 0x36200, 0x36200, 2491 0x36218, 0x36218, 2492 0x36400, 0x36400, 2493 0x36408, 0x3641c, 2494 0x36618, 0x36620, 2495 0x36664, 0x36664, 2496 0x366a8, 0x366a8, 2497 0x366ec, 0x366ec, 2498 0x36a00, 0x36abc, 2499 0x36b00, 0x36b18, 2500 0x36b20, 0x36b38, 2501 0x36b40, 0x36b58, 2502 0x36b60, 0x36b78, 2503 0x36c00, 0x36c00, 2504 0x36c08, 0x36c3c, 2505 0x37000, 0x3702c, 2506 0x37034, 0x37050, 2507 0x37058, 0x37058, 2508 0x37060, 0x3708c, 2509 0x3709c, 0x370ac, 2510 0x370c0, 0x370c0, 2511 0x370c8, 0x370d0, 2512 0x370d8, 0x370e0, 2513 0x370ec, 0x3712c, 2514 0x37134, 0x37150, 2515 0x37158, 0x37158, 2516 0x37160, 0x3718c, 2517 0x3719c, 0x371ac, 2518 0x371c0, 0x371c0, 2519 0x371c8, 0x371d0, 2520 0x371d8, 0x371e0, 2521 0x371ec, 0x37290, 2522 0x37298, 0x372c4, 2523 0x372e4, 0x37390, 2524 0x37398, 0x373c4, 2525 0x373e4, 0x3742c, 2526 0x37434, 0x37450, 2527 0x37458, 0x37458, 2528 0x37460, 0x3748c, 2529 0x3749c, 0x374ac, 2530 0x374c0, 0x374c0, 2531 0x374c8, 0x374d0, 2532 0x374d8, 0x374e0, 2533 0x374ec, 0x3752c, 2534 0x37534, 0x37550, 2535 0x37558, 0x37558, 2536 0x37560, 0x3758c, 2537 0x3759c, 0x375ac, 2538 0x375c0, 0x375c0, 2539 0x375c8, 0x375d0, 2540 0x375d8, 0x375e0, 2541 0x375ec, 0x37690, 2542 0x37698, 0x376c4, 2543 0x376e4, 0x37790, 2544 0x37798, 0x377c4, 2545 0x377e4, 0x377fc, 2546 0x37814, 0x37814, 2547 0x37854, 0x37868, 2548 0x37880, 0x3788c, 2549 0x378c0, 0x378d0, 2550 0x378e8, 0x378ec, 2551 0x37900, 0x3792c, 2552 0x37934, 0x37950, 2553 0x37958, 0x37958, 2554 0x37960, 0x3798c, 2555 0x3799c, 0x379ac, 2556 0x379c0, 0x379c0, 2557 0x379c8, 0x379d0, 2558 0x379d8, 0x379e0, 2559 0x379ec, 0x37a90, 2560 0x37a98, 0x37ac4, 2561 0x37ae4, 0x37b10, 2562 0x37b24, 0x37b28, 2563 0x37b38, 0x37b50, 2564 0x37bf0, 0x37c10, 2565 0x37c24, 0x37c28, 2566 0x37c38, 0x37c50, 2567 0x37cf0, 0x37cfc, 2568 0x40040, 0x40040, 2569 0x40080, 0x40084, 2570 0x40100, 0x40100, 2571 0x40140, 0x401bc, 2572 0x40200, 0x40214, 2573 0x40228, 0x40228, 2574 0x40240, 0x40258, 2575 0x40280, 0x40280, 2576 0x40304, 0x40304, 2577 0x40330, 0x4033c, 2578 0x41304, 0x413c8, 2579 0x413d0, 0x413dc, 2580 0x413f0, 0x413f0, 2581 0x41400, 0x4140c, 2582 0x41414, 0x4141c, 2583 0x41480, 0x414d0, 2584 0x44000, 0x4407c, 2585 0x440c0, 0x441ac, 2586 0x441b4, 0x4427c, 2587 0x442c0, 0x443ac, 2588 0x443b4, 0x4447c, 2589 0x444c0, 0x445ac, 2590 0x445b4, 0x4467c, 2591 0x446c0, 0x447ac, 2592 0x447b4, 0x4487c, 2593 0x448c0, 0x449ac, 2594 0x449b4, 0x44a7c, 2595 0x44ac0, 0x44bac, 2596 0x44bb4, 0x44c7c, 2597 0x44cc0, 0x44dac, 2598 0x44db4, 0x44e7c, 2599 0x44ec0, 0x44fac, 2600 0x44fb4, 0x4507c, 2601 0x450c0, 0x451ac, 2602 0x451b4, 0x451fc, 2603 0x45800, 0x45804, 2604 0x45810, 0x45830, 2605 0x45840, 0x45860, 2606 0x45868, 0x45868, 2607 0x45880, 0x45884, 2608 0x458a0, 0x458b0, 2609 0x45a00, 0x45a04, 2610 0x45a10, 0x45a30, 2611 0x45a40, 0x45a60, 2612 0x45a68, 0x45a68, 2613 0x45a80, 0x45a84, 2614 0x45aa0, 0x45ab0, 2615 0x460c0, 0x460e4, 2616 0x47000, 0x4703c, 2617 0x47044, 0x4708c, 2618 0x47200, 0x47250, 2619 0x47400, 0x47408, 2620 0x47414, 0x47420, 2621 0x47600, 0x47618, 2622 0x47800, 0x47814, 2623 0x47820, 0x4782c, 2624 0x50000, 0x50084, 2625 0x50090, 0x500cc, 2626 0x50300, 0x50384, 2627 0x50400, 0x50400, 2628 0x50800, 0x50884, 2629 0x50890, 0x508cc, 2630 0x50b00, 0x50b84, 2631 0x50c00, 0x50c00, 2632 0x51000, 0x51020, 2633 0x51028, 0x510b0, 2634 0x51300, 0x51324, 2635 }; 2636 2637 static const unsigned int t6vf_reg_ranges[] = { 2638 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2639 VF_MPS_REG(A_MPS_VF_CTL), 2640 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2641 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2642 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2643 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2644 FW_T6VF_MBDATA_BASE_ADDR, 2645 FW_T6VF_MBDATA_BASE_ADDR + 2646 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2647 }; 2648 2649 u32 *buf_end = (u32 *)(buf + buf_size); 2650 const unsigned int *reg_ranges; 2651 int reg_ranges_size, range; 2652 unsigned int chip_version = chip_id(adap); 2653 2654 /* 2655 * Select the right set of register ranges to dump depending on the 2656 * adapter chip type. 2657 */ 2658 switch (chip_version) { 2659 case CHELSIO_T4: 2660 if (adap->flags & IS_VF) { 2661 reg_ranges = t4vf_reg_ranges; 2662 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2663 } else { 2664 reg_ranges = t4_reg_ranges; 2665 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2666 } 2667 break; 2668 2669 case CHELSIO_T5: 2670 if (adap->flags & IS_VF) { 2671 reg_ranges = t5vf_reg_ranges; 2672 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2673 } else { 2674 reg_ranges = t5_reg_ranges; 2675 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2676 } 2677 break; 2678 2679 case CHELSIO_T6: 2680 if (adap->flags & IS_VF) { 2681 reg_ranges = t6vf_reg_ranges; 2682 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2683 } else { 2684 reg_ranges = t6_reg_ranges; 2685 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2686 } 2687 break; 2688 2689 default: 2690 CH_ERR(adap, 2691 "Unsupported chip version %d\n", chip_version); 2692 return; 2693 } 2694 2695 /* 2696 * Clear the register buffer and insert the appropriate register 2697 * values selected by the above register ranges. 2698 */ 2699 memset(buf, 0, buf_size); 2700 for (range = 0; range < reg_ranges_size; range += 2) { 2701 unsigned int reg = reg_ranges[range]; 2702 unsigned int last_reg = reg_ranges[range + 1]; 2703 u32 *bufp = (u32 *)(buf + reg); 2704 2705 /* 2706 * Iterate across the register range filling in the register 2707 * buffer but don't write past the end of the register buffer. 2708 */ 2709 while (reg <= last_reg && bufp < buf_end) { 2710 *bufp++ = t4_read_reg(adap, reg); 2711 reg += sizeof(u32); 2712 } 2713 } 2714 } 2715 2716 /* 2717 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2718 * header followed by one or more VPD-R sections, each with its own header. 2719 */ 2720 struct t4_vpd_hdr { 2721 u8 id_tag; 2722 u8 id_len[2]; 2723 u8 id_data[ID_LEN]; 2724 }; 2725 2726 struct t4_vpdr_hdr { 2727 u8 vpdr_tag; 2728 u8 vpdr_len[2]; 2729 }; 2730 2731 /* 2732 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2733 */ 2734 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2735 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2736 2737 #define EEPROM_STAT_ADDR 0x7bfc 2738 #define VPD_SIZE 0x800 2739 #define VPD_BASE 0x400 2740 #define VPD_BASE_OLD 0 2741 #define VPD_LEN 1024 2742 #define VPD_INFO_FLD_HDR_SIZE 3 2743 #define CHELSIO_VPD_UNIQUE_ID 0x82 2744 2745 /* 2746 * Small utility function to wait till any outstanding VPD Access is complete. 2747 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2748 * VPD Access in flight. This allows us to handle the problem of having a 2749 * previous VPD Access time out and prevent an attempt to inject a new VPD 2750 * Request before any in-flight VPD reguest has completed. 2751 */ 2752 static int t4_seeprom_wait(struct adapter *adapter) 2753 { 2754 unsigned int base = adapter->params.pci.vpd_cap_addr; 2755 int max_poll; 2756 2757 /* 2758 * If no VPD Access is in flight, we can just return success right 2759 * away. 2760 */ 2761 if (!adapter->vpd_busy) 2762 return 0; 2763 2764 /* 2765 * Poll the VPD Capability Address/Flag register waiting for it 2766 * to indicate that the operation is complete. 2767 */ 2768 max_poll = EEPROM_MAX_POLL; 2769 do { 2770 u16 val; 2771 2772 udelay(EEPROM_DELAY); 2773 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2774 2775 /* 2776 * If the operation is complete, mark the VPD as no longer 2777 * busy and return success. 2778 */ 2779 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2780 adapter->vpd_busy = 0; 2781 return 0; 2782 } 2783 } while (--max_poll); 2784 2785 /* 2786 * Failure! Note that we leave the VPD Busy status set in order to 2787 * avoid pushing a new VPD Access request into the VPD Capability till 2788 * the current operation eventually succeeds. It's a bug to issue a 2789 * new request when an existing request is in flight and will result 2790 * in corrupt hardware state. 2791 */ 2792 return -ETIMEDOUT; 2793 } 2794 2795 /** 2796 * t4_seeprom_read - read a serial EEPROM location 2797 * @adapter: adapter to read 2798 * @addr: EEPROM virtual address 2799 * @data: where to store the read data 2800 * 2801 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2802 * VPD capability. Note that this function must be called with a virtual 2803 * address. 2804 */ 2805 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2806 { 2807 unsigned int base = adapter->params.pci.vpd_cap_addr; 2808 int ret; 2809 2810 /* 2811 * VPD Accesses must alway be 4-byte aligned! 2812 */ 2813 if (addr >= EEPROMVSIZE || (addr & 3)) 2814 return -EINVAL; 2815 2816 /* 2817 * Wait for any previous operation which may still be in flight to 2818 * complete. 2819 */ 2820 ret = t4_seeprom_wait(adapter); 2821 if (ret) { 2822 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2823 return ret; 2824 } 2825 2826 /* 2827 * Issue our new VPD Read request, mark the VPD as being busy and wait 2828 * for our request to complete. If it doesn't complete, note the 2829 * error and return it to our caller. Note that we do not reset the 2830 * VPD Busy status! 2831 */ 2832 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2833 adapter->vpd_busy = 1; 2834 adapter->vpd_flag = PCI_VPD_ADDR_F; 2835 ret = t4_seeprom_wait(adapter); 2836 if (ret) { 2837 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2838 return ret; 2839 } 2840 2841 /* 2842 * Grab the returned data, swizzle it into our endianness and 2843 * return success. 2844 */ 2845 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2846 *data = le32_to_cpu(*data); 2847 return 0; 2848 } 2849 2850 /** 2851 * t4_seeprom_write - write a serial EEPROM location 2852 * @adapter: adapter to write 2853 * @addr: virtual EEPROM address 2854 * @data: value to write 2855 * 2856 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2857 * VPD capability. Note that this function must be called with a virtual 2858 * address. 2859 */ 2860 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2861 { 2862 unsigned int base = adapter->params.pci.vpd_cap_addr; 2863 int ret; 2864 u32 stats_reg; 2865 int max_poll; 2866 2867 /* 2868 * VPD Accesses must alway be 4-byte aligned! 2869 */ 2870 if (addr >= EEPROMVSIZE || (addr & 3)) 2871 return -EINVAL; 2872 2873 /* 2874 * Wait for any previous operation which may still be in flight to 2875 * complete. 2876 */ 2877 ret = t4_seeprom_wait(adapter); 2878 if (ret) { 2879 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2880 return ret; 2881 } 2882 2883 /* 2884 * Issue our new VPD Read request, mark the VPD as being busy and wait 2885 * for our request to complete. If it doesn't complete, note the 2886 * error and return it to our caller. Note that we do not reset the 2887 * VPD Busy status! 2888 */ 2889 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2890 cpu_to_le32(data)); 2891 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2892 (u16)addr | PCI_VPD_ADDR_F); 2893 adapter->vpd_busy = 1; 2894 adapter->vpd_flag = 0; 2895 ret = t4_seeprom_wait(adapter); 2896 if (ret) { 2897 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2898 return ret; 2899 } 2900 2901 /* 2902 * Reset PCI_VPD_DATA register after a transaction and wait for our 2903 * request to complete. If it doesn't complete, return error. 2904 */ 2905 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2906 max_poll = EEPROM_MAX_POLL; 2907 do { 2908 udelay(EEPROM_DELAY); 2909 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2910 } while ((stats_reg & 0x1) && --max_poll); 2911 if (!max_poll) 2912 return -ETIMEDOUT; 2913 2914 /* Return success! */ 2915 return 0; 2916 } 2917 2918 /** 2919 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2920 * @phys_addr: the physical EEPROM address 2921 * @fn: the PCI function number 2922 * @sz: size of function-specific area 2923 * 2924 * Translate a physical EEPROM address to virtual. The first 1K is 2925 * accessed through virtual addresses starting at 31K, the rest is 2926 * accessed through virtual addresses starting at 0. 2927 * 2928 * The mapping is as follows: 2929 * [0..1K) -> [31K..32K) 2930 * [1K..1K+A) -> [ES-A..ES) 2931 * [1K+A..ES) -> [0..ES-A-1K) 2932 * 2933 * where A = @fn * @sz, and ES = EEPROM size. 2934 */ 2935 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2936 { 2937 fn *= sz; 2938 if (phys_addr < 1024) 2939 return phys_addr + (31 << 10); 2940 if (phys_addr < 1024 + fn) 2941 return EEPROMSIZE - fn + phys_addr - 1024; 2942 if (phys_addr < EEPROMSIZE) 2943 return phys_addr - 1024 - fn; 2944 return -EINVAL; 2945 } 2946 2947 /** 2948 * t4_seeprom_wp - enable/disable EEPROM write protection 2949 * @adapter: the adapter 2950 * @enable: whether to enable or disable write protection 2951 * 2952 * Enables or disables write protection on the serial EEPROM. 2953 */ 2954 int t4_seeprom_wp(struct adapter *adapter, int enable) 2955 { 2956 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2957 } 2958 2959 /** 2960 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2961 * @vpd: Pointer to buffered vpd data structure 2962 * @kw: The keyword to search for 2963 * @region: VPD region to search (starting from 0) 2964 * 2965 * Returns the value of the information field keyword or 2966 * -ENOENT otherwise. 2967 */ 2968 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2969 { 2970 int i, tag; 2971 unsigned int offset, len; 2972 const struct t4_vpdr_hdr *vpdr; 2973 2974 offset = sizeof(struct t4_vpd_hdr); 2975 vpdr = (const void *)(vpd + offset); 2976 tag = vpdr->vpdr_tag; 2977 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2978 while (region--) { 2979 offset += sizeof(struct t4_vpdr_hdr) + len; 2980 vpdr = (const void *)(vpd + offset); 2981 if (++tag != vpdr->vpdr_tag) 2982 return -ENOENT; 2983 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2984 } 2985 offset += sizeof(struct t4_vpdr_hdr); 2986 2987 if (offset + len > VPD_LEN) { 2988 return -ENOENT; 2989 } 2990 2991 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2992 if (memcmp(vpd + i , kw , 2) == 0){ 2993 i += VPD_INFO_FLD_HDR_SIZE; 2994 return i; 2995 } 2996 2997 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2998 } 2999 3000 return -ENOENT; 3001 } 3002 3003 3004 /** 3005 * get_vpd_params - read VPD parameters from VPD EEPROM 3006 * @adapter: adapter to read 3007 * @p: where to store the parameters 3008 * @vpd: caller provided temporary space to read the VPD into 3009 * 3010 * Reads card parameters stored in VPD EEPROM. 3011 */ 3012 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3013 uint16_t device_id, u32 *buf) 3014 { 3015 int i, ret, addr; 3016 int ec, sn, pn, na, md; 3017 u8 csum; 3018 const u8 *vpd = (const u8 *)buf; 3019 3020 /* 3021 * Card information normally starts at VPD_BASE but early cards had 3022 * it at 0. 3023 */ 3024 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3025 if (ret) 3026 return (ret); 3027 3028 /* 3029 * The VPD shall have a unique identifier specified by the PCI SIG. 3030 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3031 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3032 * is expected to automatically put this entry at the 3033 * beginning of the VPD. 3034 */ 3035 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3036 3037 for (i = 0; i < VPD_LEN; i += 4) { 3038 ret = t4_seeprom_read(adapter, addr + i, buf++); 3039 if (ret) 3040 return ret; 3041 } 3042 3043 #define FIND_VPD_KW(var,name) do { \ 3044 var = get_vpd_keyword_val(vpd, name, 0); \ 3045 if (var < 0) { \ 3046 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3047 return -EINVAL; \ 3048 } \ 3049 } while (0) 3050 3051 FIND_VPD_KW(i, "RV"); 3052 for (csum = 0; i >= 0; i--) 3053 csum += vpd[i]; 3054 3055 if (csum) { 3056 CH_ERR(adapter, 3057 "corrupted VPD EEPROM, actual csum %u\n", csum); 3058 return -EINVAL; 3059 } 3060 3061 FIND_VPD_KW(ec, "EC"); 3062 FIND_VPD_KW(sn, "SN"); 3063 FIND_VPD_KW(pn, "PN"); 3064 FIND_VPD_KW(na, "NA"); 3065 #undef FIND_VPD_KW 3066 3067 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3068 strstrip(p->id); 3069 memcpy(p->ec, vpd + ec, EC_LEN); 3070 strstrip(p->ec); 3071 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3072 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3073 strstrip(p->sn); 3074 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3075 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3076 strstrip((char *)p->pn); 3077 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3078 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3079 strstrip((char *)p->na); 3080 3081 if (device_id & 0x80) 3082 return 0; /* Custom card */ 3083 3084 md = get_vpd_keyword_val(vpd, "VF", 1); 3085 if (md < 0) { 3086 snprintf(p->md, sizeof(p->md), "unknown"); 3087 } else { 3088 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3089 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3090 strstrip((char *)p->md); 3091 } 3092 3093 return 0; 3094 } 3095 3096 /* serial flash and firmware constants and flash config file constants */ 3097 enum { 3098 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3099 3100 /* flash command opcodes */ 3101 SF_PROG_PAGE = 2, /* program 256B page */ 3102 SF_WR_DISABLE = 4, /* disable writes */ 3103 SF_RD_STATUS = 5, /* read status register */ 3104 SF_WR_ENABLE = 6, /* enable writes */ 3105 SF_RD_DATA_FAST = 0xb, /* read flash */ 3106 SF_RD_ID = 0x9f, /* read ID */ 3107 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3108 }; 3109 3110 /** 3111 * sf1_read - read data from the serial flash 3112 * @adapter: the adapter 3113 * @byte_cnt: number of bytes to read 3114 * @cont: whether another operation will be chained 3115 * @lock: whether to lock SF for PL access only 3116 * @valp: where to store the read data 3117 * 3118 * Reads up to 4 bytes of data from the serial flash. The location of 3119 * the read needs to be specified prior to calling this by issuing the 3120 * appropriate commands to the serial flash. 3121 */ 3122 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3123 int lock, u32 *valp) 3124 { 3125 int ret; 3126 3127 if (!byte_cnt || byte_cnt > 4) 3128 return -EINVAL; 3129 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3130 return -EBUSY; 3131 t4_write_reg(adapter, A_SF_OP, 3132 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3133 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3134 if (!ret) 3135 *valp = t4_read_reg(adapter, A_SF_DATA); 3136 return ret; 3137 } 3138 3139 /** 3140 * sf1_write - write data to the serial flash 3141 * @adapter: the adapter 3142 * @byte_cnt: number of bytes to write 3143 * @cont: whether another operation will be chained 3144 * @lock: whether to lock SF for PL access only 3145 * @val: value to write 3146 * 3147 * Writes up to 4 bytes of data to the serial flash. The location of 3148 * the write needs to be specified prior to calling this by issuing the 3149 * appropriate commands to the serial flash. 3150 */ 3151 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3152 int lock, u32 val) 3153 { 3154 if (!byte_cnt || byte_cnt > 4) 3155 return -EINVAL; 3156 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3157 return -EBUSY; 3158 t4_write_reg(adapter, A_SF_DATA, val); 3159 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3160 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3161 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3162 } 3163 3164 /** 3165 * flash_wait_op - wait for a flash operation to complete 3166 * @adapter: the adapter 3167 * @attempts: max number of polls of the status register 3168 * @delay: delay between polls in ms 3169 * 3170 * Wait for a flash operation to complete by polling the status register. 3171 */ 3172 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3173 { 3174 int ret; 3175 u32 status; 3176 3177 while (1) { 3178 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3179 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3180 return ret; 3181 if (!(status & 1)) 3182 return 0; 3183 if (--attempts == 0) 3184 return -EAGAIN; 3185 if (delay) 3186 msleep(delay); 3187 } 3188 } 3189 3190 /** 3191 * t4_read_flash - read words from serial flash 3192 * @adapter: the adapter 3193 * @addr: the start address for the read 3194 * @nwords: how many 32-bit words to read 3195 * @data: where to store the read data 3196 * @byte_oriented: whether to store data as bytes or as words 3197 * 3198 * Read the specified number of 32-bit words from the serial flash. 3199 * If @byte_oriented is set the read data is stored as a byte array 3200 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3201 * natural endianness. 3202 */ 3203 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3204 unsigned int nwords, u32 *data, int byte_oriented) 3205 { 3206 int ret; 3207 3208 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3209 return -EINVAL; 3210 3211 addr = swab32(addr) | SF_RD_DATA_FAST; 3212 3213 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3214 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3215 return ret; 3216 3217 for ( ; nwords; nwords--, data++) { 3218 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3219 if (nwords == 1) 3220 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3221 if (ret) 3222 return ret; 3223 if (byte_oriented) 3224 *data = (__force __u32)(cpu_to_be32(*data)); 3225 } 3226 return 0; 3227 } 3228 3229 /** 3230 * t4_write_flash - write up to a page of data to the serial flash 3231 * @adapter: the adapter 3232 * @addr: the start address to write 3233 * @n: length of data to write in bytes 3234 * @data: the data to write 3235 * @byte_oriented: whether to store data as bytes or as words 3236 * 3237 * Writes up to a page of data (256 bytes) to the serial flash starting 3238 * at the given address. All the data must be written to the same page. 3239 * If @byte_oriented is set the write data is stored as byte stream 3240 * (i.e. matches what on disk), otherwise in big-endian. 3241 */ 3242 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3243 unsigned int n, const u8 *data, int byte_oriented) 3244 { 3245 int ret; 3246 u32 buf[SF_PAGE_SIZE / 4]; 3247 unsigned int i, c, left, val, offset = addr & 0xff; 3248 3249 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3250 return -EINVAL; 3251 3252 val = swab32(addr) | SF_PROG_PAGE; 3253 3254 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3255 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3256 goto unlock; 3257 3258 for (left = n; left; left -= c) { 3259 c = min(left, 4U); 3260 for (val = 0, i = 0; i < c; ++i) 3261 val = (val << 8) + *data++; 3262 3263 if (!byte_oriented) 3264 val = cpu_to_be32(val); 3265 3266 ret = sf1_write(adapter, c, c != left, 1, val); 3267 if (ret) 3268 goto unlock; 3269 } 3270 ret = flash_wait_op(adapter, 8, 1); 3271 if (ret) 3272 goto unlock; 3273 3274 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3275 3276 /* Read the page to verify the write succeeded */ 3277 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3278 byte_oriented); 3279 if (ret) 3280 return ret; 3281 3282 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3283 CH_ERR(adapter, 3284 "failed to correctly write the flash page at %#x\n", 3285 addr); 3286 return -EIO; 3287 } 3288 return 0; 3289 3290 unlock: 3291 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3292 return ret; 3293 } 3294 3295 /** 3296 * t4_get_fw_version - read the firmware version 3297 * @adapter: the adapter 3298 * @vers: where to place the version 3299 * 3300 * Reads the FW version from flash. 3301 */ 3302 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3303 { 3304 return t4_read_flash(adapter, FLASH_FW_START + 3305 offsetof(struct fw_hdr, fw_ver), 1, 3306 vers, 0); 3307 } 3308 3309 /** 3310 * t4_get_fw_hdr - read the firmware header 3311 * @adapter: the adapter 3312 * @hdr: where to place the version 3313 * 3314 * Reads the FW header from flash into caller provided buffer. 3315 */ 3316 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3317 { 3318 return t4_read_flash(adapter, FLASH_FW_START, 3319 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3320 } 3321 3322 /** 3323 * t4_get_bs_version - read the firmware bootstrap version 3324 * @adapter: the adapter 3325 * @vers: where to place the version 3326 * 3327 * Reads the FW Bootstrap version from flash. 3328 */ 3329 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3330 { 3331 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3332 offsetof(struct fw_hdr, fw_ver), 1, 3333 vers, 0); 3334 } 3335 3336 /** 3337 * t4_get_tp_version - read the TP microcode version 3338 * @adapter: the adapter 3339 * @vers: where to place the version 3340 * 3341 * Reads the TP microcode version from flash. 3342 */ 3343 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3344 { 3345 return t4_read_flash(adapter, FLASH_FW_START + 3346 offsetof(struct fw_hdr, tp_microcode_ver), 3347 1, vers, 0); 3348 } 3349 3350 /** 3351 * t4_get_exprom_version - return the Expansion ROM version (if any) 3352 * @adapter: the adapter 3353 * @vers: where to place the version 3354 * 3355 * Reads the Expansion ROM header from FLASH and returns the version 3356 * number (if present) through the @vers return value pointer. We return 3357 * this in the Firmware Version Format since it's convenient. Return 3358 * 0 on success, -ENOENT if no Expansion ROM is present. 3359 */ 3360 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 3361 { 3362 struct exprom_header { 3363 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3364 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3365 } *hdr; 3366 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3367 sizeof(u32))]; 3368 int ret; 3369 3370 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 3371 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3372 0); 3373 if (ret) 3374 return ret; 3375 3376 hdr = (struct exprom_header *)exprom_header_buf; 3377 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3378 return -ENOENT; 3379 3380 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3381 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3382 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3383 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3384 return 0; 3385 } 3386 3387 /** 3388 * t4_get_scfg_version - return the Serial Configuration version 3389 * @adapter: the adapter 3390 * @vers: where to place the version 3391 * 3392 * Reads the Serial Configuration Version via the Firmware interface 3393 * (thus this can only be called once we're ready to issue Firmware 3394 * commands). The format of the Serial Configuration version is 3395 * adapter specific. Returns 0 on success, an error on failure. 3396 * 3397 * Note that early versions of the Firmware didn't include the ability 3398 * to retrieve the Serial Configuration version, so we zero-out the 3399 * return-value parameter in that case to avoid leaving it with 3400 * garbage in it. 3401 * 3402 * Also note that the Firmware will return its cached copy of the Serial 3403 * Initialization Revision ID, not the actual Revision ID as written in 3404 * the Serial EEPROM. This is only an issue if a new VPD has been written 3405 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3406 * it's best to defer calling this routine till after a FW_RESET_CMD has 3407 * been issued if the Host Driver will be performing a full adapter 3408 * initialization. 3409 */ 3410 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3411 { 3412 u32 scfgrev_param; 3413 int ret; 3414 3415 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3416 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3417 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3418 1, &scfgrev_param, vers); 3419 if (ret) 3420 *vers = 0; 3421 return ret; 3422 } 3423 3424 /** 3425 * t4_get_vpd_version - return the VPD version 3426 * @adapter: the adapter 3427 * @vers: where to place the version 3428 * 3429 * Reads the VPD via the Firmware interface (thus this can only be called 3430 * once we're ready to issue Firmware commands). The format of the 3431 * VPD version is adapter specific. Returns 0 on success, an error on 3432 * failure. 3433 * 3434 * Note that early versions of the Firmware didn't include the ability 3435 * to retrieve the VPD version, so we zero-out the return-value parameter 3436 * in that case to avoid leaving it with garbage in it. 3437 * 3438 * Also note that the Firmware will return its cached copy of the VPD 3439 * Revision ID, not the actual Revision ID as written in the Serial 3440 * EEPROM. This is only an issue if a new VPD has been written and the 3441 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3442 * to defer calling this routine till after a FW_RESET_CMD has been issued 3443 * if the Host Driver will be performing a full adapter initialization. 3444 */ 3445 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3446 { 3447 u32 vpdrev_param; 3448 int ret; 3449 3450 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3451 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3452 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3453 1, &vpdrev_param, vers); 3454 if (ret) 3455 *vers = 0; 3456 return ret; 3457 } 3458 3459 /** 3460 * t4_get_version_info - extract various chip/firmware version information 3461 * @adapter: the adapter 3462 * 3463 * Reads various chip/firmware version numbers and stores them into the 3464 * adapter Adapter Parameters structure. If any of the efforts fails 3465 * the first failure will be returned, but all of the version numbers 3466 * will be read. 3467 */ 3468 int t4_get_version_info(struct adapter *adapter) 3469 { 3470 int ret = 0; 3471 3472 #define FIRST_RET(__getvinfo) \ 3473 do { \ 3474 int __ret = __getvinfo; \ 3475 if (__ret && !ret) \ 3476 ret = __ret; \ 3477 } while (0) 3478 3479 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3480 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3481 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3482 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3483 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3484 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3485 3486 #undef FIRST_RET 3487 3488 return ret; 3489 } 3490 3491 /** 3492 * t4_flash_erase_sectors - erase a range of flash sectors 3493 * @adapter: the adapter 3494 * @start: the first sector to erase 3495 * @end: the last sector to erase 3496 * 3497 * Erases the sectors in the given inclusive range. 3498 */ 3499 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3500 { 3501 int ret = 0; 3502 3503 if (end >= adapter->params.sf_nsec) 3504 return -EINVAL; 3505 3506 while (start <= end) { 3507 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3508 (ret = sf1_write(adapter, 4, 0, 1, 3509 SF_ERASE_SECTOR | (start << 8))) != 0 || 3510 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3511 CH_ERR(adapter, 3512 "erase of flash sector %d failed, error %d\n", 3513 start, ret); 3514 break; 3515 } 3516 start++; 3517 } 3518 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3519 return ret; 3520 } 3521 3522 /** 3523 * t4_flash_cfg_addr - return the address of the flash configuration file 3524 * @adapter: the adapter 3525 * 3526 * Return the address within the flash where the Firmware Configuration 3527 * File is stored, or an error if the device FLASH is too small to contain 3528 * a Firmware Configuration File. 3529 */ 3530 int t4_flash_cfg_addr(struct adapter *adapter) 3531 { 3532 /* 3533 * If the device FLASH isn't large enough to hold a Firmware 3534 * Configuration File, return an error. 3535 */ 3536 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3537 return -ENOSPC; 3538 3539 return FLASH_CFG_START; 3540 } 3541 3542 /* 3543 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3544 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3545 * and emit an error message for mismatched firmware to save our caller the 3546 * effort ... 3547 */ 3548 static int t4_fw_matches_chip(struct adapter *adap, 3549 const struct fw_hdr *hdr) 3550 { 3551 /* 3552 * The expression below will return FALSE for any unsupported adapter 3553 * which will keep us "honest" in the future ... 3554 */ 3555 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3556 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3557 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3558 return 1; 3559 3560 CH_ERR(adap, 3561 "FW image (%d) is not suitable for this adapter (%d)\n", 3562 hdr->chip, chip_id(adap)); 3563 return 0; 3564 } 3565 3566 /** 3567 * t4_load_fw - download firmware 3568 * @adap: the adapter 3569 * @fw_data: the firmware image to write 3570 * @size: image size 3571 * 3572 * Write the supplied firmware image to the card's serial flash. 3573 */ 3574 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3575 { 3576 u32 csum; 3577 int ret, addr; 3578 unsigned int i; 3579 u8 first_page[SF_PAGE_SIZE]; 3580 const u32 *p = (const u32 *)fw_data; 3581 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3582 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3583 unsigned int fw_start_sec; 3584 unsigned int fw_start; 3585 unsigned int fw_size; 3586 3587 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3588 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3589 fw_start = FLASH_FWBOOTSTRAP_START; 3590 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3591 } else { 3592 fw_start_sec = FLASH_FW_START_SEC; 3593 fw_start = FLASH_FW_START; 3594 fw_size = FLASH_FW_MAX_SIZE; 3595 } 3596 3597 if (!size) { 3598 CH_ERR(adap, "FW image has no data\n"); 3599 return -EINVAL; 3600 } 3601 if (size & 511) { 3602 CH_ERR(adap, 3603 "FW image size not multiple of 512 bytes\n"); 3604 return -EINVAL; 3605 } 3606 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3607 CH_ERR(adap, 3608 "FW image size differs from size in FW header\n"); 3609 return -EINVAL; 3610 } 3611 if (size > fw_size) { 3612 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3613 fw_size); 3614 return -EFBIG; 3615 } 3616 if (!t4_fw_matches_chip(adap, hdr)) 3617 return -EINVAL; 3618 3619 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3620 csum += be32_to_cpu(p[i]); 3621 3622 if (csum != 0xffffffff) { 3623 CH_ERR(adap, 3624 "corrupted firmware image, checksum %#x\n", csum); 3625 return -EINVAL; 3626 } 3627 3628 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3629 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3630 if (ret) 3631 goto out; 3632 3633 /* 3634 * We write the correct version at the end so the driver can see a bad 3635 * version if the FW write fails. Start by writing a copy of the 3636 * first page with a bad version. 3637 */ 3638 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3639 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3640 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3641 if (ret) 3642 goto out; 3643 3644 addr = fw_start; 3645 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3646 addr += SF_PAGE_SIZE; 3647 fw_data += SF_PAGE_SIZE; 3648 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3649 if (ret) 3650 goto out; 3651 } 3652 3653 ret = t4_write_flash(adap, 3654 fw_start + offsetof(struct fw_hdr, fw_ver), 3655 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3656 out: 3657 if (ret) 3658 CH_ERR(adap, "firmware download failed, error %d\n", 3659 ret); 3660 return ret; 3661 } 3662 3663 /** 3664 * t4_fwcache - firmware cache operation 3665 * @adap: the adapter 3666 * @op : the operation (flush or flush and invalidate) 3667 */ 3668 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3669 { 3670 struct fw_params_cmd c; 3671 3672 memset(&c, 0, sizeof(c)); 3673 c.op_to_vfn = 3674 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3675 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3676 V_FW_PARAMS_CMD_PFN(adap->pf) | 3677 V_FW_PARAMS_CMD_VFN(0)); 3678 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3679 c.param[0].mnem = 3680 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3681 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3682 c.param[0].val = (__force __be32)op; 3683 3684 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3685 } 3686 3687 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3688 unsigned int *pif_req_wrptr, 3689 unsigned int *pif_rsp_wrptr) 3690 { 3691 int i, j; 3692 u32 cfg, val, req, rsp; 3693 3694 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3695 if (cfg & F_LADBGEN) 3696 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3697 3698 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3699 req = G_POLADBGWRPTR(val); 3700 rsp = G_PILADBGWRPTR(val); 3701 if (pif_req_wrptr) 3702 *pif_req_wrptr = req; 3703 if (pif_rsp_wrptr) 3704 *pif_rsp_wrptr = rsp; 3705 3706 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3707 for (j = 0; j < 6; j++) { 3708 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3709 V_PILADBGRDPTR(rsp)); 3710 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3711 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3712 req++; 3713 rsp++; 3714 } 3715 req = (req + 2) & M_POLADBGRDPTR; 3716 rsp = (rsp + 2) & M_PILADBGRDPTR; 3717 } 3718 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3719 } 3720 3721 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3722 { 3723 u32 cfg; 3724 int i, j, idx; 3725 3726 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3727 if (cfg & F_LADBGEN) 3728 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3729 3730 for (i = 0; i < CIM_MALA_SIZE; i++) { 3731 for (j = 0; j < 5; j++) { 3732 idx = 8 * i + j; 3733 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3734 V_PILADBGRDPTR(idx)); 3735 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3736 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3737 } 3738 } 3739 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3740 } 3741 3742 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3743 { 3744 unsigned int i, j; 3745 3746 for (i = 0; i < 8; i++) { 3747 u32 *p = la_buf + i; 3748 3749 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3750 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3751 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3752 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3753 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3754 } 3755 } 3756 3757 /** 3758 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3759 * @caps16: a 16-bit Port Capabilities value 3760 * 3761 * Returns the equivalent 32-bit Port Capabilities value. 3762 */ 3763 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3764 { 3765 uint32_t caps32 = 0; 3766 3767 #define CAP16_TO_CAP32(__cap) \ 3768 do { \ 3769 if (caps16 & FW_PORT_CAP_##__cap) \ 3770 caps32 |= FW_PORT_CAP32_##__cap; \ 3771 } while (0) 3772 3773 CAP16_TO_CAP32(SPEED_100M); 3774 CAP16_TO_CAP32(SPEED_1G); 3775 CAP16_TO_CAP32(SPEED_25G); 3776 CAP16_TO_CAP32(SPEED_10G); 3777 CAP16_TO_CAP32(SPEED_40G); 3778 CAP16_TO_CAP32(SPEED_100G); 3779 CAP16_TO_CAP32(FC_RX); 3780 CAP16_TO_CAP32(FC_TX); 3781 CAP16_TO_CAP32(ANEG); 3782 CAP16_TO_CAP32(FORCE_PAUSE); 3783 CAP16_TO_CAP32(MDIAUTO); 3784 CAP16_TO_CAP32(MDISTRAIGHT); 3785 CAP16_TO_CAP32(FEC_RS); 3786 CAP16_TO_CAP32(FEC_BASER_RS); 3787 CAP16_TO_CAP32(802_3_PAUSE); 3788 CAP16_TO_CAP32(802_3_ASM_DIR); 3789 3790 #undef CAP16_TO_CAP32 3791 3792 return caps32; 3793 } 3794 3795 /** 3796 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3797 * @caps32: a 32-bit Port Capabilities value 3798 * 3799 * Returns the equivalent 16-bit Port Capabilities value. Note that 3800 * not all 32-bit Port Capabilities can be represented in the 16-bit 3801 * Port Capabilities and some fields/values may not make it. 3802 */ 3803 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3804 { 3805 uint16_t caps16 = 0; 3806 3807 #define CAP32_TO_CAP16(__cap) \ 3808 do { \ 3809 if (caps32 & FW_PORT_CAP32_##__cap) \ 3810 caps16 |= FW_PORT_CAP_##__cap; \ 3811 } while (0) 3812 3813 CAP32_TO_CAP16(SPEED_100M); 3814 CAP32_TO_CAP16(SPEED_1G); 3815 CAP32_TO_CAP16(SPEED_10G); 3816 CAP32_TO_CAP16(SPEED_25G); 3817 CAP32_TO_CAP16(SPEED_40G); 3818 CAP32_TO_CAP16(SPEED_100G); 3819 CAP32_TO_CAP16(FC_RX); 3820 CAP32_TO_CAP16(FC_TX); 3821 CAP32_TO_CAP16(802_3_PAUSE); 3822 CAP32_TO_CAP16(802_3_ASM_DIR); 3823 CAP32_TO_CAP16(ANEG); 3824 CAP32_TO_CAP16(FORCE_PAUSE); 3825 CAP32_TO_CAP16(MDIAUTO); 3826 CAP32_TO_CAP16(MDISTRAIGHT); 3827 CAP32_TO_CAP16(FEC_RS); 3828 CAP32_TO_CAP16(FEC_BASER_RS); 3829 3830 #undef CAP32_TO_CAP16 3831 3832 return caps16; 3833 } 3834 3835 static bool 3836 is_bt(struct port_info *pi) 3837 { 3838 3839 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 3840 pi->port_type == FW_PORT_TYPE_BT_XFI || 3841 pi->port_type == FW_PORT_TYPE_BT_XAUI); 3842 } 3843 3844 /** 3845 * t4_link_l1cfg - apply link configuration to MAC/PHY 3846 * @phy: the PHY to setup 3847 * @mac: the MAC to setup 3848 * @lc: the requested link configuration 3849 * 3850 * Set up a port's MAC and PHY according to a desired link configuration. 3851 * - If the PHY can auto-negotiate first decide what to advertise, then 3852 * enable/disable auto-negotiation as desired, and reset. 3853 * - If the PHY does not auto-negotiate just reset it. 3854 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3855 * otherwise do it later based on the outcome of auto-negotiation. 3856 */ 3857 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3858 struct link_config *lc) 3859 { 3860 struct fw_port_cmd c; 3861 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3862 unsigned int aneg, fc, fec, speed, rcap; 3863 3864 fc = 0; 3865 if (lc->requested_fc & PAUSE_RX) 3866 fc |= FW_PORT_CAP32_FC_RX; 3867 if (lc->requested_fc & PAUSE_TX) 3868 fc |= FW_PORT_CAP32_FC_TX; 3869 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3870 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3871 3872 fec = 0; 3873 if (lc->requested_fec == FEC_AUTO) 3874 fec = lc->fec_hint; 3875 else { 3876 if (lc->requested_fec & FEC_RS) 3877 fec |= FW_PORT_CAP32_FEC_RS; 3878 if (lc->requested_fec & FEC_BASER_RS) 3879 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3880 } 3881 3882 if (lc->requested_aneg == AUTONEG_DISABLE) 3883 aneg = 0; 3884 else if (lc->requested_aneg == AUTONEG_ENABLE) 3885 aneg = FW_PORT_CAP32_ANEG; 3886 else 3887 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3888 3889 if (aneg) { 3890 speed = lc->supported & V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3891 } else if (lc->requested_speed != 0) 3892 speed = speed_to_fwcap(lc->requested_speed); 3893 else 3894 speed = fwcap_top_speed(lc->supported); 3895 3896 /* Force AN on for BT cards. */ 3897 if (is_bt(adap->port[adap->chan_map[port]])) 3898 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3899 3900 rcap = aneg | speed | fc | fec; 3901 if ((rcap | lc->supported) != lc->supported) { 3902 #ifdef INVARIANTS 3903 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x\n", rcap, 3904 lc->supported); 3905 #endif 3906 rcap &= lc->supported; 3907 } 3908 rcap |= mdi; 3909 3910 memset(&c, 0, sizeof(c)); 3911 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3912 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3913 V_FW_PORT_CMD_PORTID(port)); 3914 if (adap->params.port_caps32) { 3915 c.action_to_len16 = 3916 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3917 FW_LEN16(c)); 3918 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3919 } else { 3920 c.action_to_len16 = 3921 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3922 FW_LEN16(c)); 3923 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3924 } 3925 3926 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3927 } 3928 3929 /** 3930 * t4_restart_aneg - restart autonegotiation 3931 * @adap: the adapter 3932 * @mbox: mbox to use for the FW command 3933 * @port: the port id 3934 * 3935 * Restarts autonegotiation for the selected port. 3936 */ 3937 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3938 { 3939 struct fw_port_cmd c; 3940 3941 memset(&c, 0, sizeof(c)); 3942 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3943 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3944 V_FW_PORT_CMD_PORTID(port)); 3945 c.action_to_len16 = 3946 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3947 FW_LEN16(c)); 3948 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3949 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3950 } 3951 3952 struct intr_details { 3953 u32 mask; 3954 const char *msg; 3955 }; 3956 3957 struct intr_action { 3958 u32 mask; 3959 int arg; 3960 bool (*action)(struct adapter *, int, bool); 3961 }; 3962 3963 #define NONFATAL_IF_DISABLED 1 3964 struct intr_info { 3965 const char *name; /* name of the INT_CAUSE register */ 3966 int cause_reg; /* INT_CAUSE register */ 3967 int enable_reg; /* INT_ENABLE register */ 3968 u32 fatal; /* bits that are fatal */ 3969 int flags; /* hints */ 3970 const struct intr_details *details; 3971 const struct intr_action *actions; 3972 }; 3973 3974 static inline char 3975 intr_alert_char(u32 cause, u32 enable, u32 fatal) 3976 { 3977 3978 if (cause & fatal) 3979 return ('!'); 3980 if (cause & enable) 3981 return ('*'); 3982 return ('-'); 3983 } 3984 3985 static void 3986 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 3987 { 3988 u32 enable, fatal, leftover; 3989 const struct intr_details *details; 3990 char alert; 3991 3992 enable = t4_read_reg(adap, ii->enable_reg); 3993 if (ii->flags & NONFATAL_IF_DISABLED) 3994 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 3995 else 3996 fatal = ii->fatal; 3997 alert = intr_alert_char(cause, enable, fatal); 3998 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 3999 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4000 4001 leftover = cause; 4002 for (details = ii->details; details && details->mask != 0; details++) { 4003 u32 msgbits = details->mask & cause; 4004 if (msgbits == 0) 4005 continue; 4006 alert = intr_alert_char(msgbits, enable, ii->fatal); 4007 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4008 details->msg); 4009 leftover &= ~msgbits; 4010 } 4011 if (leftover != 0 && leftover != cause) 4012 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4013 } 4014 4015 /* 4016 * Returns true for fatal error. 4017 */ 4018 static bool 4019 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4020 u32 additional_cause, bool verbose) 4021 { 4022 u32 cause, fatal; 4023 bool rc; 4024 const struct intr_action *action; 4025 4026 /* read and display cause. */ 4027 cause = t4_read_reg(adap, ii->cause_reg); 4028 if (verbose || cause != 0) 4029 t4_show_intr_info(adap, ii, cause); 4030 /* 4031 * The top level interrupt cause is a bit special and we need to ignore 4032 * the bits that are not in the enable. Note that we did display them 4033 * above in t4_show_intr_info but will not clear them. 4034 */ 4035 if (ii->cause_reg == A_PL_INT_CAUSE) 4036 cause &= t4_read_reg(adap, ii->enable_reg); 4037 fatal = cause & ii->fatal; 4038 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4039 fatal &= t4_read_reg(adap, ii->enable_reg); 4040 cause |= additional_cause; 4041 if (cause == 0) 4042 return (false); 4043 4044 rc = fatal != 0; 4045 for (action = ii->actions; action && action->mask != 0; action++) { 4046 if (!(action->mask & cause)) 4047 continue; 4048 rc |= (action->action)(adap, action->arg, verbose); 4049 } 4050 4051 /* clear */ 4052 t4_write_reg(adap, ii->cause_reg, cause); 4053 (void)t4_read_reg(adap, ii->cause_reg); 4054 4055 return (rc); 4056 } 4057 4058 /* 4059 * Interrupt handler for the PCIE module. 4060 */ 4061 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4062 { 4063 static const struct intr_details sysbus_intr_details[] = { 4064 { F_RNPP, "RXNP array parity error" }, 4065 { F_RPCP, "RXPC array parity error" }, 4066 { F_RCIP, "RXCIF array parity error" }, 4067 { F_RCCP, "Rx completions control array parity error" }, 4068 { F_RFTP, "RXFT array parity error" }, 4069 { 0 } 4070 }; 4071 static const struct intr_info sysbus_intr_info = { 4072 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4073 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4074 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4075 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4076 .flags = 0, 4077 .details = sysbus_intr_details, 4078 .actions = NULL, 4079 }; 4080 static const struct intr_details pcie_port_intr_details[] = { 4081 { F_TPCP, "TXPC array parity error" }, 4082 { F_TNPP, "TXNP array parity error" }, 4083 { F_TFTP, "TXFT array parity error" }, 4084 { F_TCAP, "TXCA array parity error" }, 4085 { F_TCIP, "TXCIF array parity error" }, 4086 { F_RCAP, "RXCA array parity error" }, 4087 { F_OTDD, "outbound request TLP discarded" }, 4088 { F_RDPE, "Rx data parity error" }, 4089 { F_TDUE, "Tx uncorrectable data error" }, 4090 { 0 } 4091 }; 4092 static const struct intr_info pcie_port_intr_info = { 4093 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4094 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4095 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4096 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4097 F_OTDD | F_RDPE | F_TDUE, 4098 .flags = 0, 4099 .details = pcie_port_intr_details, 4100 .actions = NULL, 4101 }; 4102 static const struct intr_details pcie_intr_details[] = { 4103 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4104 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4105 { F_MSIDATAPERR, "MSI data parity error" }, 4106 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4107 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4108 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4109 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4110 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4111 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4112 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4113 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4114 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4115 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4116 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4117 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4118 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4119 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4120 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4121 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4122 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4123 { F_FIDPERR, "PCIe FID parity error" }, 4124 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4125 { F_MATAGPERR, "PCIe MA tag parity error" }, 4126 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4127 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4128 { F_RXWRPERR, "PCIe Rx write parity error" }, 4129 { F_RPLPERR, "PCIe replay buffer parity error" }, 4130 { F_PCIESINT, "PCIe core secondary fault" }, 4131 { F_PCIEPINT, "PCIe core primary fault" }, 4132 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4133 { 0 } 4134 }; 4135 static const struct intr_details t5_pcie_intr_details[] = { 4136 { F_IPGRPPERR, "Parity errors observed by IP" }, 4137 { F_NONFATALERR, "PCIe non-fatal error" }, 4138 { F_READRSPERR, "Outbound read error" }, 4139 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4140 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4141 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4142 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4143 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4144 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4145 { F_MAGRPPERR, "MA group FIFO parity error" }, 4146 { F_VFIDPERR, "VFID SRAM parity error" }, 4147 { F_FIDPERR, "FID SRAM parity error" }, 4148 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4149 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4150 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4151 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4152 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4153 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4154 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4155 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4156 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4157 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4158 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4159 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4160 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4161 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4162 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4163 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4164 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4165 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4166 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4167 { 0 } 4168 }; 4169 struct intr_info pcie_intr_info = { 4170 .name = "PCIE_INT_CAUSE", 4171 .cause_reg = A_PCIE_INT_CAUSE, 4172 .enable_reg = A_PCIE_INT_ENABLE, 4173 .fatal = 0xffffffff, 4174 .flags = NONFATAL_IF_DISABLED, 4175 .details = NULL, 4176 .actions = NULL, 4177 }; 4178 bool fatal = false; 4179 4180 if (is_t4(adap)) { 4181 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4182 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4183 4184 pcie_intr_info.details = pcie_intr_details; 4185 } else { 4186 pcie_intr_info.details = t5_pcie_intr_details; 4187 } 4188 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4189 4190 return (fatal); 4191 } 4192 4193 /* 4194 * TP interrupt handler. 4195 */ 4196 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4197 { 4198 static const struct intr_details tp_intr_details[] = { 4199 { 0x3fffffff, "TP parity error" }, 4200 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4201 { 0 } 4202 }; 4203 static const struct intr_info tp_intr_info = { 4204 .name = "TP_INT_CAUSE", 4205 .cause_reg = A_TP_INT_CAUSE, 4206 .enable_reg = A_TP_INT_ENABLE, 4207 .fatal = 0x7fffffff, 4208 .flags = NONFATAL_IF_DISABLED, 4209 .details = tp_intr_details, 4210 .actions = NULL, 4211 }; 4212 4213 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4214 } 4215 4216 /* 4217 * SGE interrupt handler. 4218 */ 4219 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4220 { 4221 static const struct intr_info sge_int1_info = { 4222 .name = "SGE_INT_CAUSE1", 4223 .cause_reg = A_SGE_INT_CAUSE1, 4224 .enable_reg = A_SGE_INT_ENABLE1, 4225 .fatal = 0xffffffff, 4226 .flags = NONFATAL_IF_DISABLED, 4227 .details = NULL, 4228 .actions = NULL, 4229 }; 4230 static const struct intr_info sge_int2_info = { 4231 .name = "SGE_INT_CAUSE2", 4232 .cause_reg = A_SGE_INT_CAUSE2, 4233 .enable_reg = A_SGE_INT_ENABLE2, 4234 .fatal = 0xffffffff, 4235 .flags = NONFATAL_IF_DISABLED, 4236 .details = NULL, 4237 .actions = NULL, 4238 }; 4239 static const struct intr_details sge_int3_details[] = { 4240 { F_ERR_FLM_DBP, 4241 "DBP pointer delivery for invalid context or QID" }, 4242 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4243 "Invalid QID or header request by IDMA" }, 4244 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4245 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4246 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4247 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4248 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4249 { F_ERR_TIMER_ABOVE_MAX_QID, 4250 "SGE GTS with timer 0-5 for IQID > 1023" }, 4251 { F_ERR_CPL_EXCEED_IQE_SIZE, 4252 "SGE received CPL exceeding IQE size" }, 4253 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4254 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4255 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4256 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4257 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4258 "SGE IQID > 1023 received CPL for FL" }, 4259 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4260 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4261 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4262 { F_ERR_ING_CTXT_PRIO, 4263 "Ingress context manager priority user error" }, 4264 { F_ERR_EGR_CTXT_PRIO, 4265 "Egress context manager priority user error" }, 4266 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4267 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4268 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4269 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4270 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4271 { 0x0000000f, "SGE context access for invalid queue" }, 4272 { 0 } 4273 }; 4274 static const struct intr_details t6_sge_int3_details[] = { 4275 { F_ERR_FLM_DBP, 4276 "DBP pointer delivery for invalid context or QID" }, 4277 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4278 "Invalid QID or header request by IDMA" }, 4279 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4280 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4281 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4282 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4283 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4284 { F_ERR_TIMER_ABOVE_MAX_QID, 4285 "SGE GTS with timer 0-5 for IQID > 1023" }, 4286 { F_ERR_CPL_EXCEED_IQE_SIZE, 4287 "SGE received CPL exceeding IQE size" }, 4288 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4289 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4290 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4291 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4292 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4293 "SGE IQID > 1023 received CPL for FL" }, 4294 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4295 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4296 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4297 { F_ERR_ING_CTXT_PRIO, 4298 "Ingress context manager priority user error" }, 4299 { F_ERR_EGR_CTXT_PRIO, 4300 "Egress context manager priority user error" }, 4301 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4302 { F_FATAL_WRE_LEN, 4303 "SGE WRE packet less than advertized length" }, 4304 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4305 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4306 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4307 { 0x0000000f, "SGE context access for invalid queue" }, 4308 { 0 } 4309 }; 4310 struct intr_info sge_int3_info = { 4311 .name = "SGE_INT_CAUSE3", 4312 .cause_reg = A_SGE_INT_CAUSE3, 4313 .enable_reg = A_SGE_INT_ENABLE3, 4314 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4315 .flags = 0, 4316 .details = NULL, 4317 .actions = NULL, 4318 }; 4319 static const struct intr_info sge_int4_info = { 4320 .name = "SGE_INT_CAUSE4", 4321 .cause_reg = A_SGE_INT_CAUSE4, 4322 .enable_reg = A_SGE_INT_ENABLE4, 4323 .fatal = 0, 4324 .flags = 0, 4325 .details = NULL, 4326 .actions = NULL, 4327 }; 4328 static const struct intr_info sge_int5_info = { 4329 .name = "SGE_INT_CAUSE5", 4330 .cause_reg = A_SGE_INT_CAUSE5, 4331 .enable_reg = A_SGE_INT_ENABLE5, 4332 .fatal = 0xffffffff, 4333 .flags = NONFATAL_IF_DISABLED, 4334 .details = NULL, 4335 .actions = NULL, 4336 }; 4337 static const struct intr_info sge_int6_info = { 4338 .name = "SGE_INT_CAUSE6", 4339 .cause_reg = A_SGE_INT_CAUSE6, 4340 .enable_reg = A_SGE_INT_ENABLE6, 4341 .fatal = 0, 4342 .flags = 0, 4343 .details = NULL, 4344 .actions = NULL, 4345 }; 4346 4347 bool fatal; 4348 u32 v; 4349 4350 if (chip_id(adap) <= CHELSIO_T5) { 4351 sge_int3_info.details = sge_int3_details; 4352 } else { 4353 sge_int3_info.details = t6_sge_int3_details; 4354 } 4355 4356 fatal = false; 4357 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4358 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4359 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4360 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4361 if (chip_id(adap) >= CHELSIO_T5) 4362 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4363 if (chip_id(adap) >= CHELSIO_T6) 4364 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4365 4366 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4367 if (v & F_ERROR_QID_VALID) { 4368 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4369 if (v & F_UNCAPTURED_ERROR) 4370 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4371 t4_write_reg(adap, A_SGE_ERROR_STATS, 4372 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4373 } 4374 4375 return (fatal); 4376 } 4377 4378 /* 4379 * CIM interrupt handler. 4380 */ 4381 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4382 { 4383 static const struct intr_action cim_host_intr_actions[] = { 4384 { F_TIMER0INT, 0, t4_os_dump_cimla }, 4385 { 0 }, 4386 }; 4387 static const struct intr_details cim_host_intr_details[] = { 4388 /* T6+ */ 4389 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4390 4391 /* T5+ */ 4392 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4393 { F_PLCIM_MSTRSPDATAPARERR, 4394 "PL2CIM master response data parity error" }, 4395 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4396 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4397 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4398 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4399 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4400 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4401 4402 /* T4+ */ 4403 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4404 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4405 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4406 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4407 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4408 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4409 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4410 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4411 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4412 "CIM IBQ PCIe/SGE_HI parity error" }, 4413 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4414 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4415 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4416 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4417 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4418 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4419 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4420 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4421 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4422 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4423 { 0} 4424 }; 4425 static const struct intr_info cim_host_intr_info = { 4426 .name = "CIM_HOST_INT_CAUSE", 4427 .cause_reg = A_CIM_HOST_INT_CAUSE, 4428 .enable_reg = A_CIM_HOST_INT_ENABLE, 4429 .fatal = 0x007fffe6, 4430 .flags = NONFATAL_IF_DISABLED, 4431 .details = cim_host_intr_details, 4432 .actions = cim_host_intr_actions, 4433 }; 4434 static const struct intr_details cim_host_upacc_intr_details[] = { 4435 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4436 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4437 { F_TIMEOUTINT, "CIM PIF timeout" }, 4438 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4439 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4440 { F_BLKWRPLINT, "CIM block write to PL space" }, 4441 { F_BLKRDPLINT, "CIM block read from PL space" }, 4442 { F_SGLWRPLINT, 4443 "CIM single write to PL space with illegal BEs" }, 4444 { F_SGLRDPLINT, 4445 "CIM single read from PL space with illegal BEs" }, 4446 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4447 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4448 { F_SGLWRCTLINT, 4449 "CIM single write to CTL space with illegal BEs" }, 4450 { F_SGLRDCTLINT, 4451 "CIM single read from CTL space with illegal BEs" }, 4452 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4453 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4454 { F_SGLWREEPROMINT, 4455 "CIM single write to EEPROM space with illegal BEs" }, 4456 { F_SGLRDEEPROMINT, 4457 "CIM single read from EEPROM space with illegal BEs" }, 4458 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4459 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4460 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4461 { F_SGLRDFLASHINT, 4462 "CIM single read from flash space with illegal BEs" }, 4463 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4464 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4465 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4466 { F_SGLRDBOOTINT, 4467 "CIM single read from boot space with illegal BEs" }, 4468 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4469 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4470 { F_ILLRDINT, "CIM illegal read" }, 4471 { F_ILLWRINT, "CIM illegal write" }, 4472 { F_ILLTRANSINT, "CIM illegal transaction" }, 4473 { F_RSVDSPACEINT, "CIM reserved space access" }, 4474 {0} 4475 }; 4476 static const struct intr_info cim_host_upacc_intr_info = { 4477 .name = "CIM_HOST_UPACC_INT_CAUSE", 4478 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4479 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4480 .fatal = 0x3fffeeff, 4481 .flags = NONFATAL_IF_DISABLED, 4482 .details = cim_host_upacc_intr_details, 4483 .actions = NULL, 4484 }; 4485 static const struct intr_info cim_pf_host_intr_info = { 4486 .name = "CIM_PF_HOST_INT_CAUSE", 4487 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4488 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4489 .fatal = 0, 4490 .flags = 0, 4491 .details = NULL, 4492 .actions = NULL, 4493 }; 4494 u32 val, fw_err; 4495 bool fatal; 4496 4497 fw_err = t4_read_reg(adap, A_PCIE_FW); 4498 if (fw_err & F_PCIE_FW_ERR) 4499 t4_report_fw_error(adap); 4500 4501 /* 4502 * When the Firmware detects an internal error which normally wouldn't 4503 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4504 * to make sure the Host sees the Firmware Crash. So if we have a 4505 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4506 * interrupt. 4507 */ 4508 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4509 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4510 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4511 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4512 } 4513 4514 fatal = false; 4515 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4516 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4517 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4518 4519 return (fatal); 4520 } 4521 4522 /* 4523 * ULP RX interrupt handler. 4524 */ 4525 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4526 { 4527 static const struct intr_details ulprx_intr_details[] = { 4528 /* T5+ */ 4529 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4530 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4531 4532 /* T4+ */ 4533 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4534 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4535 { 0x007fffff, "ULPRX parity error" }, 4536 { 0 } 4537 }; 4538 static const struct intr_info ulprx_intr_info = { 4539 .name = "ULP_RX_INT_CAUSE", 4540 .cause_reg = A_ULP_RX_INT_CAUSE, 4541 .enable_reg = A_ULP_RX_INT_ENABLE, 4542 .fatal = 0x07ffffff, 4543 .flags = NONFATAL_IF_DISABLED, 4544 .details = ulprx_intr_details, 4545 .actions = NULL, 4546 }; 4547 static const struct intr_info ulprx_intr2_info = { 4548 .name = "ULP_RX_INT_CAUSE_2", 4549 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4550 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4551 .fatal = 0, 4552 .flags = 0, 4553 .details = NULL, 4554 .actions = NULL, 4555 }; 4556 bool fatal = false; 4557 4558 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4559 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4560 4561 return (fatal); 4562 } 4563 4564 /* 4565 * ULP TX interrupt handler. 4566 */ 4567 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4568 { 4569 static const struct intr_details ulptx_intr_details[] = { 4570 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4571 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4572 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4573 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4574 { 0x0fffffff, "ULPTX parity error" }, 4575 { 0 } 4576 }; 4577 static const struct intr_info ulptx_intr_info = { 4578 .name = "ULP_TX_INT_CAUSE", 4579 .cause_reg = A_ULP_TX_INT_CAUSE, 4580 .enable_reg = A_ULP_TX_INT_ENABLE, 4581 .fatal = 0x0fffffff, 4582 .flags = NONFATAL_IF_DISABLED, 4583 .details = ulptx_intr_details, 4584 .actions = NULL, 4585 }; 4586 static const struct intr_info ulptx_intr2_info = { 4587 .name = "ULP_TX_INT_CAUSE_2", 4588 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4589 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4590 .fatal = 0xf0, 4591 .flags = NONFATAL_IF_DISABLED, 4592 .details = NULL, 4593 .actions = NULL, 4594 }; 4595 bool fatal = false; 4596 4597 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4598 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4599 4600 return (fatal); 4601 } 4602 4603 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4604 { 4605 int i; 4606 u32 data[17]; 4607 4608 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4609 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4610 for (i = 0; i < ARRAY_SIZE(data); i++) { 4611 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4612 A_PM_TX_DBG_STAT0 + i, data[i]); 4613 } 4614 4615 return (false); 4616 } 4617 4618 /* 4619 * PM TX interrupt handler. 4620 */ 4621 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4622 { 4623 static const struct intr_action pmtx_intr_actions[] = { 4624 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4625 { 0 }, 4626 }; 4627 static const struct intr_details pmtx_intr_details[] = { 4628 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4629 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4630 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4631 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4632 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4633 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4634 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4635 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4636 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4637 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4638 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4639 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4640 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4641 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4642 { 0 } 4643 }; 4644 static const struct intr_info pmtx_intr_info = { 4645 .name = "PM_TX_INT_CAUSE", 4646 .cause_reg = A_PM_TX_INT_CAUSE, 4647 .enable_reg = A_PM_TX_INT_ENABLE, 4648 .fatal = 0xffffffff, 4649 .flags = 0, 4650 .details = pmtx_intr_details, 4651 .actions = pmtx_intr_actions, 4652 }; 4653 4654 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4655 } 4656 4657 /* 4658 * PM RX interrupt handler. 4659 */ 4660 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4661 { 4662 static const struct intr_details pmrx_intr_details[] = { 4663 /* T6+ */ 4664 { 0x18000000, "PMRX ospi overflow" }, 4665 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4666 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4667 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4668 { F_SDC_ERR, "PMRX SDC error" }, 4669 4670 /* T4+ */ 4671 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4672 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4673 { 0x0003c000, "PMRX iespi Rx framing error" }, 4674 { 0x00003c00, "PMRX iespi Tx framing error" }, 4675 { 0x00000300, "PMRX ocspi Rx framing error" }, 4676 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4677 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4678 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4679 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4680 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4681 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4682 { 0 } 4683 }; 4684 static const struct intr_info pmrx_intr_info = { 4685 .name = "PM_RX_INT_CAUSE", 4686 .cause_reg = A_PM_RX_INT_CAUSE, 4687 .enable_reg = A_PM_RX_INT_ENABLE, 4688 .fatal = 0x1fffffff, 4689 .flags = NONFATAL_IF_DISABLED, 4690 .details = pmrx_intr_details, 4691 .actions = NULL, 4692 }; 4693 4694 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4695 } 4696 4697 /* 4698 * CPL switch interrupt handler. 4699 */ 4700 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4701 { 4702 static const struct intr_details cplsw_intr_details[] = { 4703 /* T5+ */ 4704 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4705 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4706 4707 /* T4+ */ 4708 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4709 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4710 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4711 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4712 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4713 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4714 { 0 } 4715 }; 4716 static const struct intr_info cplsw_intr_info = { 4717 .name = "CPL_INTR_CAUSE", 4718 .cause_reg = A_CPL_INTR_CAUSE, 4719 .enable_reg = A_CPL_INTR_ENABLE, 4720 .fatal = 0xff, 4721 .flags = NONFATAL_IF_DISABLED, 4722 .details = cplsw_intr_details, 4723 .actions = NULL, 4724 }; 4725 4726 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4727 } 4728 4729 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4730 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4731 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4732 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4733 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4734 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4735 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4736 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4737 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4738 4739 /* 4740 * LE interrupt handler. 4741 */ 4742 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4743 { 4744 static const struct intr_details le_intr_details[] = { 4745 { F_REQQPARERR, "LE request queue parity error" }, 4746 { F_UNKNOWNCMD, "LE unknown command" }, 4747 { F_ACTRGNFULL, "LE active region full" }, 4748 { F_PARITYERR, "LE parity error" }, 4749 { F_LIPMISS, "LE LIP miss" }, 4750 { F_LIP0, "LE 0 LIP error" }, 4751 { 0 } 4752 }; 4753 static const struct intr_details t6_le_intr_details[] = { 4754 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4755 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4756 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4757 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4758 { F_TOTCNTERR, "LE total active < TCAM count" }, 4759 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4760 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4761 { F_T6_ACTRGNFULL, "LE active region full" }, 4762 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4763 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4764 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4765 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4766 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4767 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4768 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4769 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4770 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4771 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4772 { 0 } 4773 }; 4774 struct intr_info le_intr_info = { 4775 .name = "LE_DB_INT_CAUSE", 4776 .cause_reg = A_LE_DB_INT_CAUSE, 4777 .enable_reg = A_LE_DB_INT_ENABLE, 4778 .fatal = 0, 4779 .flags = NONFATAL_IF_DISABLED, 4780 .details = NULL, 4781 .actions = NULL, 4782 }; 4783 4784 if (chip_id(adap) <= CHELSIO_T5) { 4785 le_intr_info.details = le_intr_details; 4786 le_intr_info.fatal = T5_LE_FATAL_MASK; 4787 } else { 4788 le_intr_info.details = t6_le_intr_details; 4789 le_intr_info.fatal = T6_LE_FATAL_MASK; 4790 } 4791 4792 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4793 } 4794 4795 /* 4796 * MPS interrupt handler. 4797 */ 4798 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4799 { 4800 static const struct intr_details mps_rx_perr_intr_details[] = { 4801 { 0xffffffff, "MPS Rx parity error" }, 4802 { 0 } 4803 }; 4804 static const struct intr_info mps_rx_perr_intr_info = { 4805 .name = "MPS_RX_PERR_INT_CAUSE", 4806 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4807 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4808 .fatal = 0xffffffff, 4809 .flags = NONFATAL_IF_DISABLED, 4810 .details = mps_rx_perr_intr_details, 4811 .actions = NULL, 4812 }; 4813 static const struct intr_details mps_tx_intr_details[] = { 4814 { F_PORTERR, "MPS Tx destination port is disabled" }, 4815 { F_FRMERR, "MPS Tx framing error" }, 4816 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4817 { F_BUBBLE, "MPS Tx underflow" }, 4818 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4819 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4820 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4821 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4822 { 0 } 4823 }; 4824 static const struct intr_info mps_tx_intr_info = { 4825 .name = "MPS_TX_INT_CAUSE", 4826 .cause_reg = A_MPS_TX_INT_CAUSE, 4827 .enable_reg = A_MPS_TX_INT_ENABLE, 4828 .fatal = 0x1ffff, 4829 .flags = NONFATAL_IF_DISABLED, 4830 .details = mps_tx_intr_details, 4831 .actions = NULL, 4832 }; 4833 static const struct intr_details mps_trc_intr_details[] = { 4834 { F_MISCPERR, "MPS TRC misc parity error" }, 4835 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4836 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4837 { 0 } 4838 }; 4839 static const struct intr_info mps_trc_intr_info = { 4840 .name = "MPS_TRC_INT_CAUSE", 4841 .cause_reg = A_MPS_TRC_INT_CAUSE, 4842 .enable_reg = A_MPS_TRC_INT_ENABLE, 4843 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4844 .flags = 0, 4845 .details = mps_trc_intr_details, 4846 .actions = NULL, 4847 }; 4848 static const struct intr_details mps_stat_sram_intr_details[] = { 4849 { 0xffffffff, "MPS statistics SRAM parity error" }, 4850 { 0 } 4851 }; 4852 static const struct intr_info mps_stat_sram_intr_info = { 4853 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4854 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4855 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4856 .fatal = 0x1fffffff, 4857 .flags = NONFATAL_IF_DISABLED, 4858 .details = mps_stat_sram_intr_details, 4859 .actions = NULL, 4860 }; 4861 static const struct intr_details mps_stat_tx_intr_details[] = { 4862 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4863 { 0 } 4864 }; 4865 static const struct intr_info mps_stat_tx_intr_info = { 4866 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4867 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4868 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4869 .fatal = 0xffffff, 4870 .flags = NONFATAL_IF_DISABLED, 4871 .details = mps_stat_tx_intr_details, 4872 .actions = NULL, 4873 }; 4874 static const struct intr_details mps_stat_rx_intr_details[] = { 4875 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4876 { 0 } 4877 }; 4878 static const struct intr_info mps_stat_rx_intr_info = { 4879 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4880 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4881 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4882 .fatal = 0xffffff, 4883 .flags = 0, 4884 .details = mps_stat_rx_intr_details, 4885 .actions = NULL, 4886 }; 4887 static const struct intr_details mps_cls_intr_details[] = { 4888 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4889 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4890 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4891 { 0 } 4892 }; 4893 static const struct intr_info mps_cls_intr_info = { 4894 .name = "MPS_CLS_INT_CAUSE", 4895 .cause_reg = A_MPS_CLS_INT_CAUSE, 4896 .enable_reg = A_MPS_CLS_INT_ENABLE, 4897 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4898 .flags = 0, 4899 .details = mps_cls_intr_details, 4900 .actions = NULL, 4901 }; 4902 static const struct intr_details mps_stat_sram1_intr_details[] = { 4903 { 0xff, "MPS statistics SRAM1 parity error" }, 4904 { 0 } 4905 }; 4906 static const struct intr_info mps_stat_sram1_intr_info = { 4907 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4908 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4909 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4910 .fatal = 0xff, 4911 .flags = 0, 4912 .details = mps_stat_sram1_intr_details, 4913 .actions = NULL, 4914 }; 4915 4916 bool fatal; 4917 4918 fatal = false; 4919 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 4920 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 4921 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 4922 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 4923 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 4924 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 4925 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 4926 if (chip_id(adap) > CHELSIO_T4) { 4927 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 4928 verbose); 4929 } 4930 4931 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 4932 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 4933 4934 return (fatal); 4935 4936 } 4937 4938 /* 4939 * EDC/MC interrupt handler. 4940 */ 4941 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 4942 { 4943 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 4944 unsigned int count_reg, v; 4945 static const struct intr_details mem_intr_details[] = { 4946 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 4947 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 4948 { F_PERR_INT_CAUSE, "FIFO parity error" }, 4949 { 0 } 4950 }; 4951 struct intr_info ii = { 4952 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 4953 .details = mem_intr_details, 4954 .flags = 0, 4955 .actions = NULL, 4956 }; 4957 bool fatal; 4958 4959 switch (idx) { 4960 case MEM_EDC0: 4961 ii.name = "EDC0_INT_CAUSE"; 4962 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 4963 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 4964 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 4965 break; 4966 case MEM_EDC1: 4967 ii.name = "EDC1_INT_CAUSE"; 4968 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 4969 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 4970 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 4971 break; 4972 case MEM_MC0: 4973 ii.name = "MC0_INT_CAUSE"; 4974 if (is_t4(adap)) { 4975 ii.cause_reg = A_MC_INT_CAUSE; 4976 ii.enable_reg = A_MC_INT_ENABLE; 4977 count_reg = A_MC_ECC_STATUS; 4978 } else { 4979 ii.cause_reg = A_MC_P_INT_CAUSE; 4980 ii.enable_reg = A_MC_P_INT_ENABLE; 4981 count_reg = A_MC_P_ECC_STATUS; 4982 } 4983 break; 4984 case MEM_MC1: 4985 ii.name = "MC1_INT_CAUSE"; 4986 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 4987 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 4988 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 4989 break; 4990 } 4991 4992 fatal = t4_handle_intr(adap, &ii, 0, verbose); 4993 4994 v = t4_read_reg(adap, count_reg); 4995 if (v != 0) { 4996 if (G_ECC_UECNT(v) != 0) { 4997 CH_ALERT(adap, 4998 "%s: %u uncorrectable ECC data error(s)\n", 4999 name[idx], G_ECC_UECNT(v)); 5000 } 5001 if (G_ECC_CECNT(v) != 0) { 5002 if (idx <= MEM_EDC1) 5003 t4_edc_err_read(adap, idx); 5004 CH_WARN_RATELIMIT(adap, 5005 "%s: %u correctable ECC data error(s)\n", 5006 name[idx], G_ECC_CECNT(v)); 5007 } 5008 t4_write_reg(adap, count_reg, 0xffffffff); 5009 } 5010 5011 return (fatal); 5012 } 5013 5014 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5015 { 5016 u32 v; 5017 5018 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5019 CH_ALERT(adap, 5020 "MA address wrap-around error by client %u to address %#x\n", 5021 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5022 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5023 5024 return (false); 5025 } 5026 5027 5028 /* 5029 * MA interrupt handler. 5030 */ 5031 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5032 { 5033 static const struct intr_action ma_intr_actions[] = { 5034 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5035 { 0 }, 5036 }; 5037 static const struct intr_info ma_intr_info = { 5038 .name = "MA_INT_CAUSE", 5039 .cause_reg = A_MA_INT_CAUSE, 5040 .enable_reg = A_MA_INT_ENABLE, 5041 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5042 .flags = NONFATAL_IF_DISABLED, 5043 .details = NULL, 5044 .actions = ma_intr_actions, 5045 }; 5046 static const struct intr_info ma_perr_status1 = { 5047 .name = "MA_PARITY_ERROR_STATUS1", 5048 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5049 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5050 .fatal = 0xffffffff, 5051 .flags = 0, 5052 .details = NULL, 5053 .actions = NULL, 5054 }; 5055 static const struct intr_info ma_perr_status2 = { 5056 .name = "MA_PARITY_ERROR_STATUS2", 5057 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5058 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5059 .fatal = 0xffffffff, 5060 .flags = 0, 5061 .details = NULL, 5062 .actions = NULL, 5063 }; 5064 bool fatal; 5065 5066 fatal = false; 5067 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5068 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5069 if (chip_id(adap) > CHELSIO_T4) 5070 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5071 5072 return (fatal); 5073 } 5074 5075 /* 5076 * SMB interrupt handler. 5077 */ 5078 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5079 { 5080 static const struct intr_details smb_intr_details[] = { 5081 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5082 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5083 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5084 { 0 } 5085 }; 5086 static const struct intr_info smb_intr_info = { 5087 .name = "SMB_INT_CAUSE", 5088 .cause_reg = A_SMB_INT_CAUSE, 5089 .enable_reg = A_SMB_INT_ENABLE, 5090 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5091 .flags = 0, 5092 .details = smb_intr_details, 5093 .actions = NULL, 5094 }; 5095 5096 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5097 } 5098 5099 /* 5100 * NC-SI interrupt handler. 5101 */ 5102 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5103 { 5104 static const struct intr_details ncsi_intr_details[] = { 5105 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5106 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5107 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5108 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5109 { 0 } 5110 }; 5111 static const struct intr_info ncsi_intr_info = { 5112 .name = "NCSI_INT_CAUSE", 5113 .cause_reg = A_NCSI_INT_CAUSE, 5114 .enable_reg = A_NCSI_INT_ENABLE, 5115 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5116 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5117 .flags = 0, 5118 .details = ncsi_intr_details, 5119 .actions = NULL, 5120 }; 5121 5122 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5123 } 5124 5125 /* 5126 * MAC interrupt handler. 5127 */ 5128 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5129 { 5130 static const struct intr_details mac_intr_details[] = { 5131 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5132 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5133 { 0 } 5134 }; 5135 char name[32]; 5136 struct intr_info ii; 5137 bool fatal = false; 5138 5139 if (is_t4(adap)) { 5140 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5141 ii.name = &name[0]; 5142 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5143 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5144 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5145 ii.flags = 0; 5146 ii.details = mac_intr_details; 5147 ii.actions = NULL; 5148 } else { 5149 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5150 ii.name = &name[0]; 5151 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5152 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5153 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5154 ii.flags = 0; 5155 ii.details = mac_intr_details; 5156 ii.actions = NULL; 5157 } 5158 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5159 5160 if (chip_id(adap) >= CHELSIO_T5) { 5161 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5162 ii.name = &name[0]; 5163 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5164 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5165 ii.fatal = 0; 5166 ii.flags = 0; 5167 ii.details = NULL; 5168 ii.actions = NULL; 5169 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5170 } 5171 5172 if (chip_id(adap) >= CHELSIO_T6) { 5173 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5174 ii.name = &name[0]; 5175 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5176 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5177 ii.fatal = 0; 5178 ii.flags = 0; 5179 ii.details = NULL; 5180 ii.actions = NULL; 5181 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5182 } 5183 5184 return (fatal); 5185 } 5186 5187 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5188 { 5189 static const struct intr_details plpl_intr_details[] = { 5190 { F_FATALPERR, "Fatal parity error" }, 5191 { F_PERRVFID, "VFID_MAP parity error" }, 5192 { 0 } 5193 }; 5194 static const struct intr_info plpl_intr_info = { 5195 .name = "PL_PL_INT_CAUSE", 5196 .cause_reg = A_PL_PL_INT_CAUSE, 5197 .enable_reg = A_PL_PL_INT_ENABLE, 5198 .fatal = F_FATALPERR | F_PERRVFID, 5199 .flags = NONFATAL_IF_DISABLED, 5200 .details = plpl_intr_details, 5201 .actions = NULL, 5202 }; 5203 5204 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5205 } 5206 5207 /** 5208 * t4_slow_intr_handler - control path interrupt handler 5209 * @adap: the adapter 5210 * @verbose: increased verbosity, for debug 5211 * 5212 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5213 * The designation 'slow' is because it involves register reads, while 5214 * data interrupts typically don't involve any MMIOs. 5215 */ 5216 int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5217 { 5218 static const struct intr_details pl_intr_details[] = { 5219 { F_MC1, "MC1" }, 5220 { F_UART, "UART" }, 5221 { F_ULP_TX, "ULP TX" }, 5222 { F_SGE, "SGE" }, 5223 { F_HMA, "HMA" }, 5224 { F_CPL_SWITCH, "CPL Switch" }, 5225 { F_ULP_RX, "ULP RX" }, 5226 { F_PM_RX, "PM RX" }, 5227 { F_PM_TX, "PM TX" }, 5228 { F_MA, "MA" }, 5229 { F_TP, "TP" }, 5230 { F_LE, "LE" }, 5231 { F_EDC1, "EDC1" }, 5232 { F_EDC0, "EDC0" }, 5233 { F_MC, "MC0" }, 5234 { F_PCIE, "PCIE" }, 5235 { F_PMU, "PMU" }, 5236 { F_MAC3, "MAC3" }, 5237 { F_MAC2, "MAC2" }, 5238 { F_MAC1, "MAC1" }, 5239 { F_MAC0, "MAC0" }, 5240 { F_SMB, "SMB" }, 5241 { F_SF, "SF" }, 5242 { F_PL, "PL" }, 5243 { F_NCSI, "NC-SI" }, 5244 { F_MPS, "MPS" }, 5245 { F_MI, "MI" }, 5246 { F_DBG, "DBG" }, 5247 { F_I2CM, "I2CM" }, 5248 { F_CIM, "CIM" }, 5249 { 0 } 5250 }; 5251 static const struct intr_info pl_perr_cause = { 5252 .name = "PL_PERR_CAUSE", 5253 .cause_reg = A_PL_PERR_CAUSE, 5254 .enable_reg = A_PL_PERR_ENABLE, 5255 .fatal = 0xffffffff, 5256 .flags = 0, 5257 .details = pl_intr_details, 5258 .actions = NULL, 5259 }; 5260 static const struct intr_action pl_intr_action[] = { 5261 { F_MC1, MEM_MC1, mem_intr_handler }, 5262 { F_ULP_TX, -1, ulptx_intr_handler }, 5263 { F_SGE, -1, sge_intr_handler }, 5264 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5265 { F_ULP_RX, -1, ulprx_intr_handler }, 5266 { F_PM_RX, -1, pmrx_intr_handler}, 5267 { F_PM_TX, -1, pmtx_intr_handler}, 5268 { F_MA, -1, ma_intr_handler }, 5269 { F_TP, -1, tp_intr_handler }, 5270 { F_LE, -1, le_intr_handler }, 5271 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5272 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5273 { F_MC0, MEM_MC0, mem_intr_handler }, 5274 { F_PCIE, -1, pcie_intr_handler }, 5275 { F_MAC3, 3, mac_intr_handler}, 5276 { F_MAC2, 2, mac_intr_handler}, 5277 { F_MAC1, 1, mac_intr_handler}, 5278 { F_MAC0, 0, mac_intr_handler}, 5279 { F_SMB, -1, smb_intr_handler}, 5280 { F_PL, -1, plpl_intr_handler }, 5281 { F_NCSI, -1, ncsi_intr_handler}, 5282 { F_MPS, -1, mps_intr_handler }, 5283 { F_CIM, -1, cim_intr_handler }, 5284 { 0 } 5285 }; 5286 static const struct intr_info pl_intr_info = { 5287 .name = "PL_INT_CAUSE", 5288 .cause_reg = A_PL_INT_CAUSE, 5289 .enable_reg = A_PL_INT_ENABLE, 5290 .fatal = 0, 5291 .flags = 0, 5292 .details = pl_intr_details, 5293 .actions = pl_intr_action, 5294 }; 5295 bool fatal; 5296 u32 perr; 5297 5298 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5299 if (verbose || perr != 0) { 5300 t4_show_intr_info(adap, &pl_perr_cause, perr); 5301 if (perr != 0) 5302 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5303 if (verbose) 5304 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5305 } 5306 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5307 if (fatal) 5308 t4_fatal_err(adap, false); 5309 5310 return (0); 5311 } 5312 5313 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5314 5315 /** 5316 * t4_intr_enable - enable interrupts 5317 * @adapter: the adapter whose interrupts should be enabled 5318 * 5319 * Enable PF-specific interrupts for the calling function and the top-level 5320 * interrupt concentrator for global interrupts. Interrupts are already 5321 * enabled at each module, here we just enable the roots of the interrupt 5322 * hierarchies. 5323 * 5324 * Note: this function should be called only when the driver manages 5325 * non PF-specific interrupts from the various HW modules. Only one PCI 5326 * function at a time should be doing this. 5327 */ 5328 void t4_intr_enable(struct adapter *adap) 5329 { 5330 u32 val = 0; 5331 5332 if (chip_id(adap) <= CHELSIO_T5) 5333 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5334 else 5335 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5336 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5337 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5338 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5339 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5340 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5341 F_EGRESS_SIZE_ERR; 5342 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5343 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5344 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5345 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5346 } 5347 5348 /** 5349 * t4_intr_disable - disable interrupts 5350 * @adap: the adapter whose interrupts should be disabled 5351 * 5352 * Disable interrupts. We only disable the top-level interrupt 5353 * concentrators. The caller must be a PCI function managing global 5354 * interrupts. 5355 */ 5356 void t4_intr_disable(struct adapter *adap) 5357 { 5358 5359 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5360 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5361 } 5362 5363 /** 5364 * t4_intr_clear - clear all interrupts 5365 * @adap: the adapter whose interrupts should be cleared 5366 * 5367 * Clears all interrupts. The caller must be a PCI function managing 5368 * global interrupts. 5369 */ 5370 void t4_intr_clear(struct adapter *adap) 5371 { 5372 static const u32 cause_reg[] = { 5373 A_CIM_HOST_INT_CAUSE, 5374 A_CIM_HOST_UPACC_INT_CAUSE, 5375 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5376 A_CPL_INTR_CAUSE, 5377 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5378 A_LE_DB_INT_CAUSE, 5379 A_MA_INT_WRAP_STATUS, 5380 A_MA_PARITY_ERROR_STATUS1, 5381 A_MA_INT_CAUSE, 5382 A_MPS_CLS_INT_CAUSE, 5383 A_MPS_RX_PERR_INT_CAUSE, 5384 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5385 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5386 A_MPS_TRC_INT_CAUSE, 5387 A_MPS_TX_INT_CAUSE, 5388 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5389 A_NCSI_INT_CAUSE, 5390 A_PCIE_INT_CAUSE, 5391 A_PCIE_NONFAT_ERR, 5392 A_PL_PL_INT_CAUSE, 5393 A_PM_RX_INT_CAUSE, 5394 A_PM_TX_INT_CAUSE, 5395 A_SGE_INT_CAUSE1, 5396 A_SGE_INT_CAUSE2, 5397 A_SGE_INT_CAUSE3, 5398 A_SGE_INT_CAUSE4, 5399 A_SMB_INT_CAUSE, 5400 A_TP_INT_CAUSE, 5401 A_ULP_RX_INT_CAUSE, 5402 A_ULP_RX_INT_CAUSE_2, 5403 A_ULP_TX_INT_CAUSE, 5404 A_ULP_TX_INT_CAUSE_2, 5405 5406 MYPF_REG(A_PL_PF_INT_CAUSE), 5407 }; 5408 int i; 5409 const int nchan = adap->chip_params->nchan; 5410 5411 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5412 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5413 5414 if (is_t4(adap)) { 5415 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5416 0xffffffff); 5417 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5418 0xffffffff); 5419 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5420 for (i = 0; i < nchan; i++) { 5421 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5422 0xffffffff); 5423 } 5424 } 5425 if (chip_id(adap) >= CHELSIO_T5) { 5426 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5427 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5428 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5429 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5430 if (is_t5(adap)) { 5431 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5432 0xffffffff); 5433 } 5434 for (i = 0; i < nchan; i++) { 5435 t4_write_reg(adap, T5_PORT_REG(i, 5436 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5437 if (chip_id(adap) > CHELSIO_T5) { 5438 t4_write_reg(adap, T5_PORT_REG(i, 5439 A_MAC_PORT_PERR_INT_CAUSE_100G), 5440 0xffffffff); 5441 } 5442 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5443 0xffffffff); 5444 } 5445 } 5446 if (chip_id(adap) >= CHELSIO_T6) { 5447 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5448 } 5449 5450 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5451 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5452 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5453 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5454 } 5455 5456 /** 5457 * hash_mac_addr - return the hash value of a MAC address 5458 * @addr: the 48-bit Ethernet MAC address 5459 * 5460 * Hashes a MAC address according to the hash function used by HW inexact 5461 * (hash) address matching. 5462 */ 5463 static int hash_mac_addr(const u8 *addr) 5464 { 5465 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5466 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5467 a ^= b; 5468 a ^= (a >> 12); 5469 a ^= (a >> 6); 5470 return a & 0x3f; 5471 } 5472 5473 /** 5474 * t4_config_rss_range - configure a portion of the RSS mapping table 5475 * @adapter: the adapter 5476 * @mbox: mbox to use for the FW command 5477 * @viid: virtual interface whose RSS subtable is to be written 5478 * @start: start entry in the table to write 5479 * @n: how many table entries to write 5480 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5481 * @nrspq: number of values in @rspq 5482 * 5483 * Programs the selected part of the VI's RSS mapping table with the 5484 * provided values. If @nrspq < @n the supplied values are used repeatedly 5485 * until the full table range is populated. 5486 * 5487 * The caller must ensure the values in @rspq are in the range allowed for 5488 * @viid. 5489 */ 5490 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5491 int start, int n, const u16 *rspq, unsigned int nrspq) 5492 { 5493 int ret; 5494 const u16 *rsp = rspq; 5495 const u16 *rsp_end = rspq + nrspq; 5496 struct fw_rss_ind_tbl_cmd cmd; 5497 5498 memset(&cmd, 0, sizeof(cmd)); 5499 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5500 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5501 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5502 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5503 5504 /* 5505 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5506 * Queue Identifiers. These Ingress Queue IDs are packed three to 5507 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5508 * reserved. 5509 */ 5510 while (n > 0) { 5511 int nq = min(n, 32); 5512 int nq_packed = 0; 5513 __be32 *qp = &cmd.iq0_to_iq2; 5514 5515 /* 5516 * Set up the firmware RSS command header to send the next 5517 * "nq" Ingress Queue IDs to the firmware. 5518 */ 5519 cmd.niqid = cpu_to_be16(nq); 5520 cmd.startidx = cpu_to_be16(start); 5521 5522 /* 5523 * "nq" more done for the start of the next loop. 5524 */ 5525 start += nq; 5526 n -= nq; 5527 5528 /* 5529 * While there are still Ingress Queue IDs to stuff into the 5530 * current firmware RSS command, retrieve them from the 5531 * Ingress Queue ID array and insert them into the command. 5532 */ 5533 while (nq > 0) { 5534 /* 5535 * Grab up to the next 3 Ingress Queue IDs (wrapping 5536 * around the Ingress Queue ID array if necessary) and 5537 * insert them into the firmware RSS command at the 5538 * current 3-tuple position within the commad. 5539 */ 5540 u16 qbuf[3]; 5541 u16 *qbp = qbuf; 5542 int nqbuf = min(3, nq); 5543 5544 nq -= nqbuf; 5545 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5546 while (nqbuf && nq_packed < 32) { 5547 nqbuf--; 5548 nq_packed++; 5549 *qbp++ = *rsp++; 5550 if (rsp >= rsp_end) 5551 rsp = rspq; 5552 } 5553 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5554 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5555 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5556 } 5557 5558 /* 5559 * Send this portion of the RRS table update to the firmware; 5560 * bail out on any errors. 5561 */ 5562 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5563 if (ret) 5564 return ret; 5565 } 5566 return 0; 5567 } 5568 5569 /** 5570 * t4_config_glbl_rss - configure the global RSS mode 5571 * @adapter: the adapter 5572 * @mbox: mbox to use for the FW command 5573 * @mode: global RSS mode 5574 * @flags: mode-specific flags 5575 * 5576 * Sets the global RSS mode. 5577 */ 5578 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5579 unsigned int flags) 5580 { 5581 struct fw_rss_glb_config_cmd c; 5582 5583 memset(&c, 0, sizeof(c)); 5584 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5585 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5586 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5587 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5588 c.u.manual.mode_pkd = 5589 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5590 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5591 c.u.basicvirtual.mode_keymode = 5592 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5593 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5594 } else 5595 return -EINVAL; 5596 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5597 } 5598 5599 /** 5600 * t4_config_vi_rss - configure per VI RSS settings 5601 * @adapter: the adapter 5602 * @mbox: mbox to use for the FW command 5603 * @viid: the VI id 5604 * @flags: RSS flags 5605 * @defq: id of the default RSS queue for the VI. 5606 * @skeyidx: RSS secret key table index for non-global mode 5607 * @skey: RSS vf_scramble key for VI. 5608 * 5609 * Configures VI-specific RSS properties. 5610 */ 5611 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5612 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5613 unsigned int skey) 5614 { 5615 struct fw_rss_vi_config_cmd c; 5616 5617 memset(&c, 0, sizeof(c)); 5618 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5619 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5620 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5621 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5622 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5623 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5624 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5625 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5626 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5627 5628 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5629 } 5630 5631 /* Read an RSS table row */ 5632 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5633 { 5634 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5635 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5636 5, 0, val); 5637 } 5638 5639 /** 5640 * t4_read_rss - read the contents of the RSS mapping table 5641 * @adapter: the adapter 5642 * @map: holds the contents of the RSS mapping table 5643 * 5644 * Reads the contents of the RSS hash->queue mapping table. 5645 */ 5646 int t4_read_rss(struct adapter *adapter, u16 *map) 5647 { 5648 u32 val; 5649 int i, ret; 5650 5651 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 5652 ret = rd_rss_row(adapter, i, &val); 5653 if (ret) 5654 return ret; 5655 *map++ = G_LKPTBLQUEUE0(val); 5656 *map++ = G_LKPTBLQUEUE1(val); 5657 } 5658 return 0; 5659 } 5660 5661 /** 5662 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5663 * @adap: the adapter 5664 * @cmd: TP fw ldst address space type 5665 * @vals: where the indirect register values are stored/written 5666 * @nregs: how many indirect registers to read/write 5667 * @start_idx: index of first indirect register to read/write 5668 * @rw: Read (1) or Write (0) 5669 * @sleep_ok: if true we may sleep while awaiting command completion 5670 * 5671 * Access TP indirect registers through LDST 5672 **/ 5673 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5674 unsigned int nregs, unsigned int start_index, 5675 unsigned int rw, bool sleep_ok) 5676 { 5677 int ret = 0; 5678 unsigned int i; 5679 struct fw_ldst_cmd c; 5680 5681 for (i = 0; i < nregs; i++) { 5682 memset(&c, 0, sizeof(c)); 5683 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5684 F_FW_CMD_REQUEST | 5685 (rw ? F_FW_CMD_READ : 5686 F_FW_CMD_WRITE) | 5687 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5688 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5689 5690 c.u.addrval.addr = cpu_to_be32(start_index + i); 5691 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5692 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5693 sleep_ok); 5694 if (ret) 5695 return ret; 5696 5697 if (rw) 5698 vals[i] = be32_to_cpu(c.u.addrval.val); 5699 } 5700 return 0; 5701 } 5702 5703 /** 5704 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5705 * @adap: the adapter 5706 * @reg_addr: Address Register 5707 * @reg_data: Data register 5708 * @buff: where the indirect register values are stored/written 5709 * @nregs: how many indirect registers to read/write 5710 * @start_index: index of first indirect register to read/write 5711 * @rw: READ(1) or WRITE(0) 5712 * @sleep_ok: if true we may sleep while awaiting command completion 5713 * 5714 * Read/Write TP indirect registers through LDST if possible. 5715 * Else, use backdoor access 5716 **/ 5717 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5718 u32 *buff, u32 nregs, u32 start_index, int rw, 5719 bool sleep_ok) 5720 { 5721 int rc = -EINVAL; 5722 int cmd; 5723 5724 switch (reg_addr) { 5725 case A_TP_PIO_ADDR: 5726 cmd = FW_LDST_ADDRSPC_TP_PIO; 5727 break; 5728 case A_TP_TM_PIO_ADDR: 5729 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5730 break; 5731 case A_TP_MIB_INDEX: 5732 cmd = FW_LDST_ADDRSPC_TP_MIB; 5733 break; 5734 default: 5735 goto indirect_access; 5736 } 5737 5738 if (t4_use_ldst(adap)) 5739 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5740 sleep_ok); 5741 5742 indirect_access: 5743 5744 if (rc) { 5745 if (rw) 5746 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5747 start_index); 5748 else 5749 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5750 start_index); 5751 } 5752 } 5753 5754 /** 5755 * t4_tp_pio_read - Read TP PIO registers 5756 * @adap: the adapter 5757 * @buff: where the indirect register values are written 5758 * @nregs: how many indirect registers to read 5759 * @start_index: index of first indirect register to read 5760 * @sleep_ok: if true we may sleep while awaiting command completion 5761 * 5762 * Read TP PIO Registers 5763 **/ 5764 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5765 u32 start_index, bool sleep_ok) 5766 { 5767 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5768 start_index, 1, sleep_ok); 5769 } 5770 5771 /** 5772 * t4_tp_pio_write - Write TP PIO registers 5773 * @adap: the adapter 5774 * @buff: where the indirect register values are stored 5775 * @nregs: how many indirect registers to write 5776 * @start_index: index of first indirect register to write 5777 * @sleep_ok: if true we may sleep while awaiting command completion 5778 * 5779 * Write TP PIO Registers 5780 **/ 5781 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5782 u32 start_index, bool sleep_ok) 5783 { 5784 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5785 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5786 } 5787 5788 /** 5789 * t4_tp_tm_pio_read - Read TP TM PIO registers 5790 * @adap: the adapter 5791 * @buff: where the indirect register values are written 5792 * @nregs: how many indirect registers to read 5793 * @start_index: index of first indirect register to read 5794 * @sleep_ok: if true we may sleep while awaiting command completion 5795 * 5796 * Read TP TM PIO Registers 5797 **/ 5798 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5799 u32 start_index, bool sleep_ok) 5800 { 5801 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5802 nregs, start_index, 1, sleep_ok); 5803 } 5804 5805 /** 5806 * t4_tp_mib_read - Read TP MIB registers 5807 * @adap: the adapter 5808 * @buff: where the indirect register values are written 5809 * @nregs: how many indirect registers to read 5810 * @start_index: index of first indirect register to read 5811 * @sleep_ok: if true we may sleep while awaiting command completion 5812 * 5813 * Read TP MIB Registers 5814 **/ 5815 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5816 bool sleep_ok) 5817 { 5818 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5819 start_index, 1, sleep_ok); 5820 } 5821 5822 /** 5823 * t4_read_rss_key - read the global RSS key 5824 * @adap: the adapter 5825 * @key: 10-entry array holding the 320-bit RSS key 5826 * @sleep_ok: if true we may sleep while awaiting command completion 5827 * 5828 * Reads the global 320-bit RSS key. 5829 */ 5830 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5831 { 5832 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5833 } 5834 5835 /** 5836 * t4_write_rss_key - program one of the RSS keys 5837 * @adap: the adapter 5838 * @key: 10-entry array holding the 320-bit RSS key 5839 * @idx: which RSS key to write 5840 * @sleep_ok: if true we may sleep while awaiting command completion 5841 * 5842 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5843 * 0..15 the corresponding entry in the RSS key table is written, 5844 * otherwise the global RSS key is written. 5845 */ 5846 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5847 bool sleep_ok) 5848 { 5849 u8 rss_key_addr_cnt = 16; 5850 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5851 5852 /* 5853 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5854 * allows access to key addresses 16-63 by using KeyWrAddrX 5855 * as index[5:4](upper 2) into key table 5856 */ 5857 if ((chip_id(adap) > CHELSIO_T5) && 5858 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5859 rss_key_addr_cnt = 32; 5860 5861 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5862 5863 if (idx >= 0 && idx < rss_key_addr_cnt) { 5864 if (rss_key_addr_cnt > 16) 5865 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5866 vrt | V_KEYWRADDRX(idx >> 4) | 5867 V_T6_VFWRADDR(idx) | F_KEYWREN); 5868 else 5869 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5870 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5871 } 5872 } 5873 5874 /** 5875 * t4_read_rss_pf_config - read PF RSS Configuration Table 5876 * @adapter: the adapter 5877 * @index: the entry in the PF RSS table to read 5878 * @valp: where to store the returned value 5879 * @sleep_ok: if true we may sleep while awaiting command completion 5880 * 5881 * Reads the PF RSS Configuration Table at the specified index and returns 5882 * the value found there. 5883 */ 5884 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5885 u32 *valp, bool sleep_ok) 5886 { 5887 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5888 } 5889 5890 /** 5891 * t4_write_rss_pf_config - write PF RSS Configuration Table 5892 * @adapter: the adapter 5893 * @index: the entry in the VF RSS table to read 5894 * @val: the value to store 5895 * @sleep_ok: if true we may sleep while awaiting command completion 5896 * 5897 * Writes the PF RSS Configuration Table at the specified index with the 5898 * specified value. 5899 */ 5900 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5901 u32 val, bool sleep_ok) 5902 { 5903 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5904 sleep_ok); 5905 } 5906 5907 /** 5908 * t4_read_rss_vf_config - read VF RSS Configuration Table 5909 * @adapter: the adapter 5910 * @index: the entry in the VF RSS table to read 5911 * @vfl: where to store the returned VFL 5912 * @vfh: where to store the returned VFH 5913 * @sleep_ok: if true we may sleep while awaiting command completion 5914 * 5915 * Reads the VF RSS Configuration Table at the specified index and returns 5916 * the (VFL, VFH) values found there. 5917 */ 5918 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5919 u32 *vfl, u32 *vfh, bool sleep_ok) 5920 { 5921 u32 vrt, mask, data; 5922 5923 if (chip_id(adapter) <= CHELSIO_T5) { 5924 mask = V_VFWRADDR(M_VFWRADDR); 5925 data = V_VFWRADDR(index); 5926 } else { 5927 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5928 data = V_T6_VFWRADDR(index); 5929 } 5930 /* 5931 * Request that the index'th VF Table values be read into VFL/VFH. 5932 */ 5933 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5934 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5935 vrt |= data | F_VFRDEN; 5936 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5937 5938 /* 5939 * Grab the VFL/VFH values ... 5940 */ 5941 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5942 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5943 } 5944 5945 /** 5946 * t4_write_rss_vf_config - write VF RSS Configuration Table 5947 * 5948 * @adapter: the adapter 5949 * @index: the entry in the VF RSS table to write 5950 * @vfl: the VFL to store 5951 * @vfh: the VFH to store 5952 * 5953 * Writes the VF RSS Configuration Table at the specified index with the 5954 * specified (VFL, VFH) values. 5955 */ 5956 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 5957 u32 vfl, u32 vfh, bool sleep_ok) 5958 { 5959 u32 vrt, mask, data; 5960 5961 if (chip_id(adapter) <= CHELSIO_T5) { 5962 mask = V_VFWRADDR(M_VFWRADDR); 5963 data = V_VFWRADDR(index); 5964 } else { 5965 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5966 data = V_T6_VFWRADDR(index); 5967 } 5968 5969 /* 5970 * Load up VFL/VFH with the values to be written ... 5971 */ 5972 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5973 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5974 5975 /* 5976 * Write the VFL/VFH into the VF Table at index'th location. 5977 */ 5978 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5979 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5980 vrt |= data | F_VFRDEN; 5981 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5982 } 5983 5984 /** 5985 * t4_read_rss_pf_map - read PF RSS Map 5986 * @adapter: the adapter 5987 * @sleep_ok: if true we may sleep while awaiting command completion 5988 * 5989 * Reads the PF RSS Map register and returns its value. 5990 */ 5991 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 5992 { 5993 u32 pfmap; 5994 5995 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5996 5997 return pfmap; 5998 } 5999 6000 /** 6001 * t4_write_rss_pf_map - write PF RSS Map 6002 * @adapter: the adapter 6003 * @pfmap: PF RSS Map value 6004 * 6005 * Writes the specified value to the PF RSS Map register. 6006 */ 6007 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6008 { 6009 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6010 } 6011 6012 /** 6013 * t4_read_rss_pf_mask - read PF RSS Mask 6014 * @adapter: the adapter 6015 * @sleep_ok: if true we may sleep while awaiting command completion 6016 * 6017 * Reads the PF RSS Mask register and returns its value. 6018 */ 6019 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6020 { 6021 u32 pfmask; 6022 6023 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6024 6025 return pfmask; 6026 } 6027 6028 /** 6029 * t4_write_rss_pf_mask - write PF RSS Mask 6030 * @adapter: the adapter 6031 * @pfmask: PF RSS Mask value 6032 * 6033 * Writes the specified value to the PF RSS Mask register. 6034 */ 6035 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6036 { 6037 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6038 } 6039 6040 /** 6041 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6042 * @adap: the adapter 6043 * @v4: holds the TCP/IP counter values 6044 * @v6: holds the TCP/IPv6 counter values 6045 * @sleep_ok: if true we may sleep while awaiting command completion 6046 * 6047 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6048 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6049 */ 6050 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6051 struct tp_tcp_stats *v6, bool sleep_ok) 6052 { 6053 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6054 6055 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6056 #define STAT(x) val[STAT_IDX(x)] 6057 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6058 6059 if (v4) { 6060 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6061 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6062 v4->tcp_out_rsts = STAT(OUT_RST); 6063 v4->tcp_in_segs = STAT64(IN_SEG); 6064 v4->tcp_out_segs = STAT64(OUT_SEG); 6065 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6066 } 6067 if (v6) { 6068 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6069 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6070 v6->tcp_out_rsts = STAT(OUT_RST); 6071 v6->tcp_in_segs = STAT64(IN_SEG); 6072 v6->tcp_out_segs = STAT64(OUT_SEG); 6073 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6074 } 6075 #undef STAT64 6076 #undef STAT 6077 #undef STAT_IDX 6078 } 6079 6080 /** 6081 * t4_tp_get_err_stats - read TP's error MIB counters 6082 * @adap: the adapter 6083 * @st: holds the counter values 6084 * @sleep_ok: if true we may sleep while awaiting command completion 6085 * 6086 * Returns the values of TP's error counters. 6087 */ 6088 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6089 bool sleep_ok) 6090 { 6091 int nchan = adap->chip_params->nchan; 6092 6093 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6094 sleep_ok); 6095 6096 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6097 sleep_ok); 6098 6099 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6100 sleep_ok); 6101 6102 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6103 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6104 6105 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6106 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6107 6108 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6109 sleep_ok); 6110 6111 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6112 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6113 6114 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6115 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6116 6117 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6118 sleep_ok); 6119 } 6120 6121 /** 6122 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6123 * @adap: the adapter 6124 * @st: holds the counter values 6125 * 6126 * Returns the values of TP's proxy counters. 6127 */ 6128 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6129 bool sleep_ok) 6130 { 6131 int nchan = adap->chip_params->nchan; 6132 6133 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6134 } 6135 6136 /** 6137 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6138 * @adap: the adapter 6139 * @st: holds the counter values 6140 * @sleep_ok: if true we may sleep while awaiting command completion 6141 * 6142 * Returns the values of TP's CPL counters. 6143 */ 6144 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6145 bool sleep_ok) 6146 { 6147 int nchan = adap->chip_params->nchan; 6148 6149 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6150 6151 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6152 } 6153 6154 /** 6155 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6156 * @adap: the adapter 6157 * @st: holds the counter values 6158 * 6159 * Returns the values of TP's RDMA counters. 6160 */ 6161 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6162 bool sleep_ok) 6163 { 6164 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6165 sleep_ok); 6166 } 6167 6168 /** 6169 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6170 * @adap: the adapter 6171 * @idx: the port index 6172 * @st: holds the counter values 6173 * @sleep_ok: if true we may sleep while awaiting command completion 6174 * 6175 * Returns the values of TP's FCoE counters for the selected port. 6176 */ 6177 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6178 struct tp_fcoe_stats *st, bool sleep_ok) 6179 { 6180 u32 val[2]; 6181 6182 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6183 sleep_ok); 6184 6185 t4_tp_mib_read(adap, &st->frames_drop, 1, 6186 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6187 6188 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6189 sleep_ok); 6190 6191 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6192 } 6193 6194 /** 6195 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6196 * @adap: the adapter 6197 * @st: holds the counter values 6198 * @sleep_ok: if true we may sleep while awaiting command completion 6199 * 6200 * Returns the values of TP's counters for non-TCP directly-placed packets. 6201 */ 6202 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6203 bool sleep_ok) 6204 { 6205 u32 val[4]; 6206 6207 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6208 6209 st->frames = val[0]; 6210 st->drops = val[1]; 6211 st->octets = ((u64)val[2] << 32) | val[3]; 6212 } 6213 6214 /** 6215 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6216 * @adap: the adapter 6217 * @mtus: where to store the MTU values 6218 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6219 * 6220 * Reads the HW path MTU table. 6221 */ 6222 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6223 { 6224 u32 v; 6225 int i; 6226 6227 for (i = 0; i < NMTUS; ++i) { 6228 t4_write_reg(adap, A_TP_MTU_TABLE, 6229 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6230 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6231 mtus[i] = G_MTUVALUE(v); 6232 if (mtu_log) 6233 mtu_log[i] = G_MTUWIDTH(v); 6234 } 6235 } 6236 6237 /** 6238 * t4_read_cong_tbl - reads the congestion control table 6239 * @adap: the adapter 6240 * @incr: where to store the alpha values 6241 * 6242 * Reads the additive increments programmed into the HW congestion 6243 * control table. 6244 */ 6245 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6246 { 6247 unsigned int mtu, w; 6248 6249 for (mtu = 0; mtu < NMTUS; ++mtu) 6250 for (w = 0; w < NCCTRL_WIN; ++w) { 6251 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6252 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6253 incr[mtu][w] = (u16)t4_read_reg(adap, 6254 A_TP_CCTRL_TABLE) & 0x1fff; 6255 } 6256 } 6257 6258 /** 6259 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6260 * @adap: the adapter 6261 * @addr: the indirect TP register address 6262 * @mask: specifies the field within the register to modify 6263 * @val: new value for the field 6264 * 6265 * Sets a field of an indirect TP register to the given value. 6266 */ 6267 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6268 unsigned int mask, unsigned int val) 6269 { 6270 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6271 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6272 t4_write_reg(adap, A_TP_PIO_DATA, val); 6273 } 6274 6275 /** 6276 * init_cong_ctrl - initialize congestion control parameters 6277 * @a: the alpha values for congestion control 6278 * @b: the beta values for congestion control 6279 * 6280 * Initialize the congestion control parameters. 6281 */ 6282 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6283 { 6284 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6285 a[9] = 2; 6286 a[10] = 3; 6287 a[11] = 4; 6288 a[12] = 5; 6289 a[13] = 6; 6290 a[14] = 7; 6291 a[15] = 8; 6292 a[16] = 9; 6293 a[17] = 10; 6294 a[18] = 14; 6295 a[19] = 17; 6296 a[20] = 21; 6297 a[21] = 25; 6298 a[22] = 30; 6299 a[23] = 35; 6300 a[24] = 45; 6301 a[25] = 60; 6302 a[26] = 80; 6303 a[27] = 100; 6304 a[28] = 200; 6305 a[29] = 300; 6306 a[30] = 400; 6307 a[31] = 500; 6308 6309 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6310 b[9] = b[10] = 1; 6311 b[11] = b[12] = 2; 6312 b[13] = b[14] = b[15] = b[16] = 3; 6313 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6314 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6315 b[28] = b[29] = 6; 6316 b[30] = b[31] = 7; 6317 } 6318 6319 /* The minimum additive increment value for the congestion control table */ 6320 #define CC_MIN_INCR 2U 6321 6322 /** 6323 * t4_load_mtus - write the MTU and congestion control HW tables 6324 * @adap: the adapter 6325 * @mtus: the values for the MTU table 6326 * @alpha: the values for the congestion control alpha parameter 6327 * @beta: the values for the congestion control beta parameter 6328 * 6329 * Write the HW MTU table with the supplied MTUs and the high-speed 6330 * congestion control table with the supplied alpha, beta, and MTUs. 6331 * We write the two tables together because the additive increments 6332 * depend on the MTUs. 6333 */ 6334 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6335 const unsigned short *alpha, const unsigned short *beta) 6336 { 6337 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6338 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6339 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6340 28672, 40960, 57344, 81920, 114688, 163840, 229376 6341 }; 6342 6343 unsigned int i, w; 6344 6345 for (i = 0; i < NMTUS; ++i) { 6346 unsigned int mtu = mtus[i]; 6347 unsigned int log2 = fls(mtu); 6348 6349 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6350 log2--; 6351 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6352 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6353 6354 for (w = 0; w < NCCTRL_WIN; ++w) { 6355 unsigned int inc; 6356 6357 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6358 CC_MIN_INCR); 6359 6360 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6361 (w << 16) | (beta[w] << 13) | inc); 6362 } 6363 } 6364 } 6365 6366 /** 6367 * t4_set_pace_tbl - set the pace table 6368 * @adap: the adapter 6369 * @pace_vals: the pace values in microseconds 6370 * @start: index of the first entry in the HW pace table to set 6371 * @n: how many entries to set 6372 * 6373 * Sets (a subset of the) HW pace table. 6374 */ 6375 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6376 unsigned int start, unsigned int n) 6377 { 6378 unsigned int vals[NTX_SCHED], i; 6379 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6380 6381 if (n > NTX_SCHED) 6382 return -ERANGE; 6383 6384 /* convert values from us to dack ticks, rounding to closest value */ 6385 for (i = 0; i < n; i++, pace_vals++) { 6386 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6387 if (vals[i] > 0x7ff) 6388 return -ERANGE; 6389 if (*pace_vals && vals[i] == 0) 6390 return -ERANGE; 6391 } 6392 for (i = 0; i < n; i++, start++) 6393 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6394 return 0; 6395 } 6396 6397 /** 6398 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6399 * @adap: the adapter 6400 * @kbps: target rate in Kbps 6401 * @sched: the scheduler index 6402 * 6403 * Configure a Tx HW scheduler for the target rate. 6404 */ 6405 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6406 { 6407 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6408 unsigned int clk = adap->params.vpd.cclk * 1000; 6409 unsigned int selected_cpt = 0, selected_bpt = 0; 6410 6411 if (kbps > 0) { 6412 kbps *= 125; /* -> bytes */ 6413 for (cpt = 1; cpt <= 255; cpt++) { 6414 tps = clk / cpt; 6415 bpt = (kbps + tps / 2) / tps; 6416 if (bpt > 0 && bpt <= 255) { 6417 v = bpt * tps; 6418 delta = v >= kbps ? v - kbps : kbps - v; 6419 if (delta < mindelta) { 6420 mindelta = delta; 6421 selected_cpt = cpt; 6422 selected_bpt = bpt; 6423 } 6424 } else if (selected_cpt) 6425 break; 6426 } 6427 if (!selected_cpt) 6428 return -EINVAL; 6429 } 6430 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6431 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6432 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6433 if (sched & 1) 6434 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6435 else 6436 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6437 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6438 return 0; 6439 } 6440 6441 /** 6442 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6443 * @adap: the adapter 6444 * @sched: the scheduler index 6445 * @ipg: the interpacket delay in tenths of nanoseconds 6446 * 6447 * Set the interpacket delay for a HW packet rate scheduler. 6448 */ 6449 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6450 { 6451 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6452 6453 /* convert ipg to nearest number of core clocks */ 6454 ipg *= core_ticks_per_usec(adap); 6455 ipg = (ipg + 5000) / 10000; 6456 if (ipg > M_TXTIMERSEPQ0) 6457 return -EINVAL; 6458 6459 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6460 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6461 if (sched & 1) 6462 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6463 else 6464 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6465 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6466 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6467 return 0; 6468 } 6469 6470 /* 6471 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6472 * clocks. The formula is 6473 * 6474 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6475 * 6476 * which is equivalent to 6477 * 6478 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6479 */ 6480 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6481 { 6482 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6483 6484 return v * 62 + v / 2; 6485 } 6486 6487 /** 6488 * t4_get_chan_txrate - get the current per channel Tx rates 6489 * @adap: the adapter 6490 * @nic_rate: rates for NIC traffic 6491 * @ofld_rate: rates for offloaded traffic 6492 * 6493 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6494 * for each channel. 6495 */ 6496 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6497 { 6498 u32 v; 6499 6500 v = t4_read_reg(adap, A_TP_TX_TRATE); 6501 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6502 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6503 if (adap->chip_params->nchan > 2) { 6504 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6505 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6506 } 6507 6508 v = t4_read_reg(adap, A_TP_TX_ORATE); 6509 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6510 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6511 if (adap->chip_params->nchan > 2) { 6512 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6513 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6514 } 6515 } 6516 6517 /** 6518 * t4_set_trace_filter - configure one of the tracing filters 6519 * @adap: the adapter 6520 * @tp: the desired trace filter parameters 6521 * @idx: which filter to configure 6522 * @enable: whether to enable or disable the filter 6523 * 6524 * Configures one of the tracing filters available in HW. If @tp is %NULL 6525 * it indicates that the filter is already written in the register and it 6526 * just needs to be enabled or disabled. 6527 */ 6528 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6529 int idx, int enable) 6530 { 6531 int i, ofst = idx * 4; 6532 u32 data_reg, mask_reg, cfg; 6533 u32 multitrc = F_TRCMULTIFILTER; 6534 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6535 6536 if (idx < 0 || idx >= NTRACE) 6537 return -EINVAL; 6538 6539 if (tp == NULL || !enable) { 6540 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6541 enable ? en : 0); 6542 return 0; 6543 } 6544 6545 /* 6546 * TODO - After T4 data book is updated, specify the exact 6547 * section below. 6548 * 6549 * See T4 data book - MPS section for a complete description 6550 * of the below if..else handling of A_MPS_TRC_CFG register 6551 * value. 6552 */ 6553 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6554 if (cfg & F_TRCMULTIFILTER) { 6555 /* 6556 * If multiple tracers are enabled, then maximum 6557 * capture size is 2.5KB (FIFO size of a single channel) 6558 * minus 2 flits for CPL_TRACE_PKT header. 6559 */ 6560 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6561 return -EINVAL; 6562 } else { 6563 /* 6564 * If multiple tracers are disabled, to avoid deadlocks 6565 * maximum packet capture size of 9600 bytes is recommended. 6566 * Also in this mode, only trace0 can be enabled and running. 6567 */ 6568 multitrc = 0; 6569 if (tp->snap_len > 9600 || idx) 6570 return -EINVAL; 6571 } 6572 6573 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6574 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6575 tp->min_len > M_TFMINPKTSIZE) 6576 return -EINVAL; 6577 6578 /* stop the tracer we'll be changing */ 6579 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6580 6581 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6582 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6583 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6584 6585 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6586 t4_write_reg(adap, data_reg, tp->data[i]); 6587 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6588 } 6589 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6590 V_TFCAPTUREMAX(tp->snap_len) | 6591 V_TFMINPKTSIZE(tp->min_len)); 6592 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6593 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6594 (is_t4(adap) ? 6595 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6596 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6597 6598 return 0; 6599 } 6600 6601 /** 6602 * t4_get_trace_filter - query one of the tracing filters 6603 * @adap: the adapter 6604 * @tp: the current trace filter parameters 6605 * @idx: which trace filter to query 6606 * @enabled: non-zero if the filter is enabled 6607 * 6608 * Returns the current settings of one of the HW tracing filters. 6609 */ 6610 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6611 int *enabled) 6612 { 6613 u32 ctla, ctlb; 6614 int i, ofst = idx * 4; 6615 u32 data_reg, mask_reg; 6616 6617 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6618 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6619 6620 if (is_t4(adap)) { 6621 *enabled = !!(ctla & F_TFEN); 6622 tp->port = G_TFPORT(ctla); 6623 tp->invert = !!(ctla & F_TFINVERTMATCH); 6624 } else { 6625 *enabled = !!(ctla & F_T5_TFEN); 6626 tp->port = G_T5_TFPORT(ctla); 6627 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6628 } 6629 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6630 tp->min_len = G_TFMINPKTSIZE(ctlb); 6631 tp->skip_ofst = G_TFOFFSET(ctla); 6632 tp->skip_len = G_TFLENGTH(ctla); 6633 6634 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6635 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6636 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6637 6638 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6639 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6640 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6641 } 6642 } 6643 6644 /** 6645 * t4_pmtx_get_stats - returns the HW stats from PMTX 6646 * @adap: the adapter 6647 * @cnt: where to store the count statistics 6648 * @cycles: where to store the cycle statistics 6649 * 6650 * Returns performance statistics from PMTX. 6651 */ 6652 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6653 { 6654 int i; 6655 u32 data[2]; 6656 6657 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6658 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6659 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6660 if (is_t4(adap)) 6661 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6662 else { 6663 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6664 A_PM_TX_DBG_DATA, data, 2, 6665 A_PM_TX_DBG_STAT_MSB); 6666 cycles[i] = (((u64)data[0] << 32) | data[1]); 6667 } 6668 } 6669 } 6670 6671 /** 6672 * t4_pmrx_get_stats - returns the HW stats from PMRX 6673 * @adap: the adapter 6674 * @cnt: where to store the count statistics 6675 * @cycles: where to store the cycle statistics 6676 * 6677 * Returns performance statistics from PMRX. 6678 */ 6679 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6680 { 6681 int i; 6682 u32 data[2]; 6683 6684 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6685 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6686 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6687 if (is_t4(adap)) { 6688 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6689 } else { 6690 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6691 A_PM_RX_DBG_DATA, data, 2, 6692 A_PM_RX_DBG_STAT_MSB); 6693 cycles[i] = (((u64)data[0] << 32) | data[1]); 6694 } 6695 } 6696 } 6697 6698 /** 6699 * t4_get_mps_bg_map - return the buffer groups associated with a port 6700 * @adap: the adapter 6701 * @idx: the port index 6702 * 6703 * Returns a bitmap indicating which MPS buffer groups are associated 6704 * with the given port. Bit i is set if buffer group i is used by the 6705 * port. 6706 */ 6707 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6708 { 6709 u32 n; 6710 6711 if (adap->params.mps_bg_map) 6712 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6713 6714 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6715 if (n == 0) 6716 return idx == 0 ? 0xf : 0; 6717 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6718 return idx < 2 ? (3 << (2 * idx)) : 0; 6719 return 1 << idx; 6720 } 6721 6722 /* 6723 * TP RX e-channels associated with the port. 6724 */ 6725 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6726 { 6727 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6728 6729 if (n == 0) 6730 return idx == 0 ? 0xf : 0; 6731 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6732 return idx < 2 ? (3 << (2 * idx)) : 0; 6733 return 1 << idx; 6734 } 6735 6736 /** 6737 * t4_get_port_type_description - return Port Type string description 6738 * @port_type: firmware Port Type enumeration 6739 */ 6740 const char *t4_get_port_type_description(enum fw_port_type port_type) 6741 { 6742 static const char *const port_type_description[] = { 6743 "Fiber_XFI", 6744 "Fiber_XAUI", 6745 "BT_SGMII", 6746 "BT_XFI", 6747 "BT_XAUI", 6748 "KX4", 6749 "CX4", 6750 "KX", 6751 "KR", 6752 "SFP", 6753 "BP_AP", 6754 "BP4_AP", 6755 "QSFP_10G", 6756 "QSA", 6757 "QSFP", 6758 "BP40_BA", 6759 "KR4_100G", 6760 "CR4_QSFP", 6761 "CR_QSFP", 6762 "CR2_QSFP", 6763 "SFP28", 6764 "KR_SFP28", 6765 }; 6766 6767 if (port_type < ARRAY_SIZE(port_type_description)) 6768 return port_type_description[port_type]; 6769 return "UNKNOWN"; 6770 } 6771 6772 /** 6773 * t4_get_port_stats_offset - collect port stats relative to a previous 6774 * snapshot 6775 * @adap: The adapter 6776 * @idx: The port 6777 * @stats: Current stats to fill 6778 * @offset: Previous stats snapshot 6779 */ 6780 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6781 struct port_stats *stats, 6782 struct port_stats *offset) 6783 { 6784 u64 *s, *o; 6785 int i; 6786 6787 t4_get_port_stats(adap, idx, stats); 6788 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6789 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6790 i++, s++, o++) 6791 *s -= *o; 6792 } 6793 6794 /** 6795 * t4_get_port_stats - collect port statistics 6796 * @adap: the adapter 6797 * @idx: the port index 6798 * @p: the stats structure to fill 6799 * 6800 * Collect statistics related to the given port from HW. 6801 */ 6802 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6803 { 6804 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6805 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6806 6807 #define GET_STAT(name) \ 6808 t4_read_reg64(adap, \ 6809 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6810 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6811 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6812 6813 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6814 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6815 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6816 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6817 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6818 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6819 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6820 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6821 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6822 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6823 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6824 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6825 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6826 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6827 p->tx_drop = GET_STAT(TX_PORT_DROP); 6828 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6829 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6830 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6831 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6832 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6833 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6834 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6835 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6836 6837 if (chip_id(adap) >= CHELSIO_T5) { 6838 if (stat_ctl & F_COUNTPAUSESTATTX) { 6839 p->tx_frames -= p->tx_pause; 6840 p->tx_octets -= p->tx_pause * 64; 6841 } 6842 if (stat_ctl & F_COUNTPAUSEMCTX) 6843 p->tx_mcast_frames -= p->tx_pause; 6844 } 6845 6846 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6847 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6848 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6849 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6850 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6851 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6852 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6853 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6854 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 6855 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6856 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6857 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6858 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6859 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6860 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6861 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6862 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6863 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6864 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6865 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6866 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6867 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6868 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6869 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6870 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6871 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6872 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6873 6874 if (chip_id(adap) >= CHELSIO_T5) { 6875 if (stat_ctl & F_COUNTPAUSESTATRX) { 6876 p->rx_frames -= p->rx_pause; 6877 p->rx_octets -= p->rx_pause * 64; 6878 } 6879 if (stat_ctl & F_COUNTPAUSEMCRX) 6880 p->rx_mcast_frames -= p->rx_pause; 6881 } 6882 6883 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6884 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6885 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6886 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6887 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6888 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6889 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6890 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6891 6892 #undef GET_STAT 6893 #undef GET_STAT_COM 6894 } 6895 6896 /** 6897 * t4_get_lb_stats - collect loopback port statistics 6898 * @adap: the adapter 6899 * @idx: the loopback port index 6900 * @p: the stats structure to fill 6901 * 6902 * Return HW statistics for the given loopback port. 6903 */ 6904 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 6905 { 6906 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6907 6908 #define GET_STAT(name) \ 6909 t4_read_reg64(adap, \ 6910 (is_t4(adap) ? \ 6911 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 6912 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 6913 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6914 6915 p->octets = GET_STAT(BYTES); 6916 p->frames = GET_STAT(FRAMES); 6917 p->bcast_frames = GET_STAT(BCAST); 6918 p->mcast_frames = GET_STAT(MCAST); 6919 p->ucast_frames = GET_STAT(UCAST); 6920 p->error_frames = GET_STAT(ERROR); 6921 6922 p->frames_64 = GET_STAT(64B); 6923 p->frames_65_127 = GET_STAT(65B_127B); 6924 p->frames_128_255 = GET_STAT(128B_255B); 6925 p->frames_256_511 = GET_STAT(256B_511B); 6926 p->frames_512_1023 = GET_STAT(512B_1023B); 6927 p->frames_1024_1518 = GET_STAT(1024B_1518B); 6928 p->frames_1519_max = GET_STAT(1519B_MAX); 6929 p->drop = GET_STAT(DROP_FRAMES); 6930 6931 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 6932 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 6933 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 6934 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 6935 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 6936 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 6937 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 6938 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 6939 6940 #undef GET_STAT 6941 #undef GET_STAT_COM 6942 } 6943 6944 /** 6945 * t4_wol_magic_enable - enable/disable magic packet WoL 6946 * @adap: the adapter 6947 * @port: the physical port index 6948 * @addr: MAC address expected in magic packets, %NULL to disable 6949 * 6950 * Enables/disables magic packet wake-on-LAN for the selected port. 6951 */ 6952 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 6953 const u8 *addr) 6954 { 6955 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 6956 6957 if (is_t4(adap)) { 6958 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 6959 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 6960 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6961 } else { 6962 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 6963 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 6964 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6965 } 6966 6967 if (addr) { 6968 t4_write_reg(adap, mag_id_reg_l, 6969 (addr[2] << 24) | (addr[3] << 16) | 6970 (addr[4] << 8) | addr[5]); 6971 t4_write_reg(adap, mag_id_reg_h, 6972 (addr[0] << 8) | addr[1]); 6973 } 6974 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 6975 V_MAGICEN(addr != NULL)); 6976 } 6977 6978 /** 6979 * t4_wol_pat_enable - enable/disable pattern-based WoL 6980 * @adap: the adapter 6981 * @port: the physical port index 6982 * @map: bitmap of which HW pattern filters to set 6983 * @mask0: byte mask for bytes 0-63 of a packet 6984 * @mask1: byte mask for bytes 64-127 of a packet 6985 * @crc: Ethernet CRC for selected bytes 6986 * @enable: enable/disable switch 6987 * 6988 * Sets the pattern filters indicated in @map to mask out the bytes 6989 * specified in @mask0/@mask1 in received packets and compare the CRC of 6990 * the resulting packet against @crc. If @enable is %true pattern-based 6991 * WoL is enabled, otherwise disabled. 6992 */ 6993 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 6994 u64 mask0, u64 mask1, unsigned int crc, bool enable) 6995 { 6996 int i; 6997 u32 port_cfg_reg; 6998 6999 if (is_t4(adap)) 7000 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7001 else 7002 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7003 7004 if (!enable) { 7005 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7006 return 0; 7007 } 7008 if (map > 0xff) 7009 return -EINVAL; 7010 7011 #define EPIO_REG(name) \ 7012 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7013 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7014 7015 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7016 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7017 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7018 7019 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7020 if (!(map & 1)) 7021 continue; 7022 7023 /* write byte masks */ 7024 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7025 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7026 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7027 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7028 return -ETIMEDOUT; 7029 7030 /* write CRC */ 7031 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7032 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7033 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7034 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7035 return -ETIMEDOUT; 7036 } 7037 #undef EPIO_REG 7038 7039 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7040 return 0; 7041 } 7042 7043 /* t4_mk_filtdelwr - create a delete filter WR 7044 * @ftid: the filter ID 7045 * @wr: the filter work request to populate 7046 * @qid: ingress queue to receive the delete notification 7047 * 7048 * Creates a filter work request to delete the supplied filter. If @qid is 7049 * negative the delete notification is suppressed. 7050 */ 7051 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7052 { 7053 memset(wr, 0, sizeof(*wr)); 7054 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7055 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7056 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7057 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7058 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7059 if (qid >= 0) 7060 wr->rx_chan_rx_rpl_iq = 7061 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7062 } 7063 7064 #define INIT_CMD(var, cmd, rd_wr) do { \ 7065 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7066 F_FW_CMD_REQUEST | \ 7067 F_FW_CMD_##rd_wr); \ 7068 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7069 } while (0) 7070 7071 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7072 u32 addr, u32 val) 7073 { 7074 u32 ldst_addrspace; 7075 struct fw_ldst_cmd c; 7076 7077 memset(&c, 0, sizeof(c)); 7078 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7079 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7080 F_FW_CMD_REQUEST | 7081 F_FW_CMD_WRITE | 7082 ldst_addrspace); 7083 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7084 c.u.addrval.addr = cpu_to_be32(addr); 7085 c.u.addrval.val = cpu_to_be32(val); 7086 7087 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7088 } 7089 7090 /** 7091 * t4_mdio_rd - read a PHY register through MDIO 7092 * @adap: the adapter 7093 * @mbox: mailbox to use for the FW command 7094 * @phy_addr: the PHY address 7095 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7096 * @reg: the register to read 7097 * @valp: where to store the value 7098 * 7099 * Issues a FW command through the given mailbox to read a PHY register. 7100 */ 7101 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7102 unsigned int mmd, unsigned int reg, unsigned int *valp) 7103 { 7104 int ret; 7105 u32 ldst_addrspace; 7106 struct fw_ldst_cmd c; 7107 7108 memset(&c, 0, sizeof(c)); 7109 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7110 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7111 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7112 ldst_addrspace); 7113 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7114 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7115 V_FW_LDST_CMD_MMD(mmd)); 7116 c.u.mdio.raddr = cpu_to_be16(reg); 7117 7118 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7119 if (ret == 0) 7120 *valp = be16_to_cpu(c.u.mdio.rval); 7121 return ret; 7122 } 7123 7124 /** 7125 * t4_mdio_wr - write a PHY register through MDIO 7126 * @adap: the adapter 7127 * @mbox: mailbox to use for the FW command 7128 * @phy_addr: the PHY address 7129 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7130 * @reg: the register to write 7131 * @valp: value to write 7132 * 7133 * Issues a FW command through the given mailbox to write a PHY register. 7134 */ 7135 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7136 unsigned int mmd, unsigned int reg, unsigned int val) 7137 { 7138 u32 ldst_addrspace; 7139 struct fw_ldst_cmd c; 7140 7141 memset(&c, 0, sizeof(c)); 7142 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7143 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7144 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7145 ldst_addrspace); 7146 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7147 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7148 V_FW_LDST_CMD_MMD(mmd)); 7149 c.u.mdio.raddr = cpu_to_be16(reg); 7150 c.u.mdio.rval = cpu_to_be16(val); 7151 7152 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7153 } 7154 7155 /** 7156 * 7157 * t4_sge_decode_idma_state - decode the idma state 7158 * @adap: the adapter 7159 * @state: the state idma is stuck in 7160 */ 7161 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7162 { 7163 static const char * const t4_decode[] = { 7164 "IDMA_IDLE", 7165 "IDMA_PUSH_MORE_CPL_FIFO", 7166 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7167 "Not used", 7168 "IDMA_PHYSADDR_SEND_PCIEHDR", 7169 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7170 "IDMA_PHYSADDR_SEND_PAYLOAD", 7171 "IDMA_SEND_FIFO_TO_IMSG", 7172 "IDMA_FL_REQ_DATA_FL_PREP", 7173 "IDMA_FL_REQ_DATA_FL", 7174 "IDMA_FL_DROP", 7175 "IDMA_FL_H_REQ_HEADER_FL", 7176 "IDMA_FL_H_SEND_PCIEHDR", 7177 "IDMA_FL_H_PUSH_CPL_FIFO", 7178 "IDMA_FL_H_SEND_CPL", 7179 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7180 "IDMA_FL_H_SEND_IP_HDR", 7181 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7182 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7183 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7184 "IDMA_FL_D_SEND_PCIEHDR", 7185 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7186 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7187 "IDMA_FL_SEND_PCIEHDR", 7188 "IDMA_FL_PUSH_CPL_FIFO", 7189 "IDMA_FL_SEND_CPL", 7190 "IDMA_FL_SEND_PAYLOAD_FIRST", 7191 "IDMA_FL_SEND_PAYLOAD", 7192 "IDMA_FL_REQ_NEXT_DATA_FL", 7193 "IDMA_FL_SEND_NEXT_PCIEHDR", 7194 "IDMA_FL_SEND_PADDING", 7195 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7196 "IDMA_FL_SEND_FIFO_TO_IMSG", 7197 "IDMA_FL_REQ_DATAFL_DONE", 7198 "IDMA_FL_REQ_HEADERFL_DONE", 7199 }; 7200 static const char * const t5_decode[] = { 7201 "IDMA_IDLE", 7202 "IDMA_ALMOST_IDLE", 7203 "IDMA_PUSH_MORE_CPL_FIFO", 7204 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7205 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7206 "IDMA_PHYSADDR_SEND_PCIEHDR", 7207 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7208 "IDMA_PHYSADDR_SEND_PAYLOAD", 7209 "IDMA_SEND_FIFO_TO_IMSG", 7210 "IDMA_FL_REQ_DATA_FL", 7211 "IDMA_FL_DROP", 7212 "IDMA_FL_DROP_SEND_INC", 7213 "IDMA_FL_H_REQ_HEADER_FL", 7214 "IDMA_FL_H_SEND_PCIEHDR", 7215 "IDMA_FL_H_PUSH_CPL_FIFO", 7216 "IDMA_FL_H_SEND_CPL", 7217 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7218 "IDMA_FL_H_SEND_IP_HDR", 7219 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7220 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7221 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7222 "IDMA_FL_D_SEND_PCIEHDR", 7223 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7224 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7225 "IDMA_FL_SEND_PCIEHDR", 7226 "IDMA_FL_PUSH_CPL_FIFO", 7227 "IDMA_FL_SEND_CPL", 7228 "IDMA_FL_SEND_PAYLOAD_FIRST", 7229 "IDMA_FL_SEND_PAYLOAD", 7230 "IDMA_FL_REQ_NEXT_DATA_FL", 7231 "IDMA_FL_SEND_NEXT_PCIEHDR", 7232 "IDMA_FL_SEND_PADDING", 7233 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7234 }; 7235 static const char * const t6_decode[] = { 7236 "IDMA_IDLE", 7237 "IDMA_PUSH_MORE_CPL_FIFO", 7238 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7239 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7240 "IDMA_PHYSADDR_SEND_PCIEHDR", 7241 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7242 "IDMA_PHYSADDR_SEND_PAYLOAD", 7243 "IDMA_FL_REQ_DATA_FL", 7244 "IDMA_FL_DROP", 7245 "IDMA_FL_DROP_SEND_INC", 7246 "IDMA_FL_H_REQ_HEADER_FL", 7247 "IDMA_FL_H_SEND_PCIEHDR", 7248 "IDMA_FL_H_PUSH_CPL_FIFO", 7249 "IDMA_FL_H_SEND_CPL", 7250 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7251 "IDMA_FL_H_SEND_IP_HDR", 7252 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7253 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7254 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7255 "IDMA_FL_D_SEND_PCIEHDR", 7256 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7257 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7258 "IDMA_FL_SEND_PCIEHDR", 7259 "IDMA_FL_PUSH_CPL_FIFO", 7260 "IDMA_FL_SEND_CPL", 7261 "IDMA_FL_SEND_PAYLOAD_FIRST", 7262 "IDMA_FL_SEND_PAYLOAD", 7263 "IDMA_FL_REQ_NEXT_DATA_FL", 7264 "IDMA_FL_SEND_NEXT_PCIEHDR", 7265 "IDMA_FL_SEND_PADDING", 7266 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7267 }; 7268 static const u32 sge_regs[] = { 7269 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7270 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7271 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7272 }; 7273 const char * const *sge_idma_decode; 7274 int sge_idma_decode_nstates; 7275 int i; 7276 unsigned int chip_version = chip_id(adapter); 7277 7278 /* Select the right set of decode strings to dump depending on the 7279 * adapter chip type. 7280 */ 7281 switch (chip_version) { 7282 case CHELSIO_T4: 7283 sge_idma_decode = (const char * const *)t4_decode; 7284 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7285 break; 7286 7287 case CHELSIO_T5: 7288 sge_idma_decode = (const char * const *)t5_decode; 7289 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7290 break; 7291 7292 case CHELSIO_T6: 7293 sge_idma_decode = (const char * const *)t6_decode; 7294 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7295 break; 7296 7297 default: 7298 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7299 return; 7300 } 7301 7302 if (state < sge_idma_decode_nstates) 7303 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7304 else 7305 CH_WARN(adapter, "idma state %d unknown\n", state); 7306 7307 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7308 CH_WARN(adapter, "SGE register %#x value %#x\n", 7309 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7310 } 7311 7312 /** 7313 * t4_sge_ctxt_flush - flush the SGE context cache 7314 * @adap: the adapter 7315 * @mbox: mailbox to use for the FW command 7316 * 7317 * Issues a FW command through the given mailbox to flush the 7318 * SGE context cache. 7319 */ 7320 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 7321 { 7322 int ret; 7323 u32 ldst_addrspace; 7324 struct fw_ldst_cmd c; 7325 7326 memset(&c, 0, sizeof(c)); 7327 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC); 7328 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7329 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7330 ldst_addrspace); 7331 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7332 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7333 7334 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7335 return ret; 7336 } 7337 7338 /** 7339 * t4_fw_hello - establish communication with FW 7340 * @adap: the adapter 7341 * @mbox: mailbox to use for the FW command 7342 * @evt_mbox: mailbox to receive async FW events 7343 * @master: specifies the caller's willingness to be the device master 7344 * @state: returns the current device state (if non-NULL) 7345 * 7346 * Issues a command to establish communication with FW. Returns either 7347 * an error (negative integer) or the mailbox of the Master PF. 7348 */ 7349 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7350 enum dev_master master, enum dev_state *state) 7351 { 7352 int ret; 7353 struct fw_hello_cmd c; 7354 u32 v; 7355 unsigned int master_mbox; 7356 int retries = FW_CMD_HELLO_RETRIES; 7357 7358 retry: 7359 memset(&c, 0, sizeof(c)); 7360 INIT_CMD(c, HELLO, WRITE); 7361 c.err_to_clearinit = cpu_to_be32( 7362 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7363 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7364 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7365 mbox : M_FW_HELLO_CMD_MBMASTER) | 7366 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7367 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7368 F_FW_HELLO_CMD_CLEARINIT); 7369 7370 /* 7371 * Issue the HELLO command to the firmware. If it's not successful 7372 * but indicates that we got a "busy" or "timeout" condition, retry 7373 * the HELLO until we exhaust our retry limit. If we do exceed our 7374 * retry limit, check to see if the firmware left us any error 7375 * information and report that if so ... 7376 */ 7377 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7378 if (ret != FW_SUCCESS) { 7379 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7380 goto retry; 7381 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7382 t4_report_fw_error(adap); 7383 return ret; 7384 } 7385 7386 v = be32_to_cpu(c.err_to_clearinit); 7387 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7388 if (state) { 7389 if (v & F_FW_HELLO_CMD_ERR) 7390 *state = DEV_STATE_ERR; 7391 else if (v & F_FW_HELLO_CMD_INIT) 7392 *state = DEV_STATE_INIT; 7393 else 7394 *state = DEV_STATE_UNINIT; 7395 } 7396 7397 /* 7398 * If we're not the Master PF then we need to wait around for the 7399 * Master PF Driver to finish setting up the adapter. 7400 * 7401 * Note that we also do this wait if we're a non-Master-capable PF and 7402 * there is no current Master PF; a Master PF may show up momentarily 7403 * and we wouldn't want to fail pointlessly. (This can happen when an 7404 * OS loads lots of different drivers rapidly at the same time). In 7405 * this case, the Master PF returned by the firmware will be 7406 * M_PCIE_FW_MASTER so the test below will work ... 7407 */ 7408 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7409 master_mbox != mbox) { 7410 int waiting = FW_CMD_HELLO_TIMEOUT; 7411 7412 /* 7413 * Wait for the firmware to either indicate an error or 7414 * initialized state. If we see either of these we bail out 7415 * and report the issue to the caller. If we exhaust the 7416 * "hello timeout" and we haven't exhausted our retries, try 7417 * again. Otherwise bail with a timeout error. 7418 */ 7419 for (;;) { 7420 u32 pcie_fw; 7421 7422 msleep(50); 7423 waiting -= 50; 7424 7425 /* 7426 * If neither Error nor Initialialized are indicated 7427 * by the firmware keep waiting till we exhaust our 7428 * timeout ... and then retry if we haven't exhausted 7429 * our retries ... 7430 */ 7431 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7432 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7433 if (waiting <= 0) { 7434 if (retries-- > 0) 7435 goto retry; 7436 7437 return -ETIMEDOUT; 7438 } 7439 continue; 7440 } 7441 7442 /* 7443 * We either have an Error or Initialized condition 7444 * report errors preferentially. 7445 */ 7446 if (state) { 7447 if (pcie_fw & F_PCIE_FW_ERR) 7448 *state = DEV_STATE_ERR; 7449 else if (pcie_fw & F_PCIE_FW_INIT) 7450 *state = DEV_STATE_INIT; 7451 } 7452 7453 /* 7454 * If we arrived before a Master PF was selected and 7455 * there's not a valid Master PF, grab its identity 7456 * for our caller. 7457 */ 7458 if (master_mbox == M_PCIE_FW_MASTER && 7459 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7460 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7461 break; 7462 } 7463 } 7464 7465 return master_mbox; 7466 } 7467 7468 /** 7469 * t4_fw_bye - end communication with FW 7470 * @adap: the adapter 7471 * @mbox: mailbox to use for the FW command 7472 * 7473 * Issues a command to terminate communication with FW. 7474 */ 7475 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7476 { 7477 struct fw_bye_cmd c; 7478 7479 memset(&c, 0, sizeof(c)); 7480 INIT_CMD(c, BYE, WRITE); 7481 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7482 } 7483 7484 /** 7485 * t4_fw_reset - issue a reset to FW 7486 * @adap: the adapter 7487 * @mbox: mailbox to use for the FW command 7488 * @reset: specifies the type of reset to perform 7489 * 7490 * Issues a reset command of the specified type to FW. 7491 */ 7492 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7493 { 7494 struct fw_reset_cmd c; 7495 7496 memset(&c, 0, sizeof(c)); 7497 INIT_CMD(c, RESET, WRITE); 7498 c.val = cpu_to_be32(reset); 7499 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7500 } 7501 7502 /** 7503 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7504 * @adap: the adapter 7505 * @mbox: mailbox to use for the FW RESET command (if desired) 7506 * @force: force uP into RESET even if FW RESET command fails 7507 * 7508 * Issues a RESET command to firmware (if desired) with a HALT indication 7509 * and then puts the microprocessor into RESET state. The RESET command 7510 * will only be issued if a legitimate mailbox is provided (mbox <= 7511 * M_PCIE_FW_MASTER). 7512 * 7513 * This is generally used in order for the host to safely manipulate the 7514 * adapter without fear of conflicting with whatever the firmware might 7515 * be doing. The only way out of this state is to RESTART the firmware 7516 * ... 7517 */ 7518 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7519 { 7520 int ret = 0; 7521 7522 /* 7523 * If a legitimate mailbox is provided, issue a RESET command 7524 * with a HALT indication. 7525 */ 7526 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7527 struct fw_reset_cmd c; 7528 7529 memset(&c, 0, sizeof(c)); 7530 INIT_CMD(c, RESET, WRITE); 7531 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7532 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7533 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7534 } 7535 7536 /* 7537 * Normally we won't complete the operation if the firmware RESET 7538 * command fails but if our caller insists we'll go ahead and put the 7539 * uP into RESET. This can be useful if the firmware is hung or even 7540 * missing ... We'll have to take the risk of putting the uP into 7541 * RESET without the cooperation of firmware in that case. 7542 * 7543 * We also force the firmware's HALT flag to be on in case we bypassed 7544 * the firmware RESET command above or we're dealing with old firmware 7545 * which doesn't have the HALT capability. This will serve as a flag 7546 * for the incoming firmware to know that it's coming out of a HALT 7547 * rather than a RESET ... if it's new enough to understand that ... 7548 */ 7549 if (ret == 0 || force) { 7550 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7551 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7552 F_PCIE_FW_HALT); 7553 } 7554 7555 /* 7556 * And we always return the result of the firmware RESET command 7557 * even when we force the uP into RESET ... 7558 */ 7559 return ret; 7560 } 7561 7562 /** 7563 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7564 * @adap: the adapter 7565 * 7566 * Restart firmware previously halted by t4_fw_halt(). On successful 7567 * return the previous PF Master remains as the new PF Master and there 7568 * is no need to issue a new HELLO command, etc. 7569 */ 7570 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7571 { 7572 int ms; 7573 7574 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7575 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7576 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7577 return FW_SUCCESS; 7578 msleep(100); 7579 ms += 100; 7580 } 7581 7582 return -ETIMEDOUT; 7583 } 7584 7585 /** 7586 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7587 * @adap: the adapter 7588 * @mbox: mailbox to use for the FW RESET command (if desired) 7589 * @fw_data: the firmware image to write 7590 * @size: image size 7591 * @force: force upgrade even if firmware doesn't cooperate 7592 * 7593 * Perform all of the steps necessary for upgrading an adapter's 7594 * firmware image. Normally this requires the cooperation of the 7595 * existing firmware in order to halt all existing activities 7596 * but if an invalid mailbox token is passed in we skip that step 7597 * (though we'll still put the adapter microprocessor into RESET in 7598 * that case). 7599 * 7600 * On successful return the new firmware will have been loaded and 7601 * the adapter will have been fully RESET losing all previous setup 7602 * state. On unsuccessful return the adapter may be completely hosed ... 7603 * positive errno indicates that the adapter is ~probably~ intact, a 7604 * negative errno indicates that things are looking bad ... 7605 */ 7606 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7607 const u8 *fw_data, unsigned int size, int force) 7608 { 7609 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7610 unsigned int bootstrap = 7611 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7612 int ret; 7613 7614 if (!t4_fw_matches_chip(adap, fw_hdr)) 7615 return -EINVAL; 7616 7617 if (!bootstrap) { 7618 ret = t4_fw_halt(adap, mbox, force); 7619 if (ret < 0 && !force) 7620 return ret; 7621 } 7622 7623 ret = t4_load_fw(adap, fw_data, size); 7624 if (ret < 0 || bootstrap) 7625 return ret; 7626 7627 return t4_fw_restart(adap, mbox); 7628 } 7629 7630 /** 7631 * t4_fw_initialize - ask FW to initialize the device 7632 * @adap: the adapter 7633 * @mbox: mailbox to use for the FW command 7634 * 7635 * Issues a command to FW to partially initialize the device. This 7636 * performs initialization that generally doesn't depend on user input. 7637 */ 7638 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7639 { 7640 struct fw_initialize_cmd c; 7641 7642 memset(&c, 0, sizeof(c)); 7643 INIT_CMD(c, INITIALIZE, WRITE); 7644 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7645 } 7646 7647 /** 7648 * t4_query_params_rw - query FW or device parameters 7649 * @adap: the adapter 7650 * @mbox: mailbox to use for the FW command 7651 * @pf: the PF 7652 * @vf: the VF 7653 * @nparams: the number of parameters 7654 * @params: the parameter names 7655 * @val: the parameter values 7656 * @rw: Write and read flag 7657 * 7658 * Reads the value of FW or device parameters. Up to 7 parameters can be 7659 * queried at once. 7660 */ 7661 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7662 unsigned int vf, unsigned int nparams, const u32 *params, 7663 u32 *val, int rw) 7664 { 7665 int i, ret; 7666 struct fw_params_cmd c; 7667 __be32 *p = &c.param[0].mnem; 7668 7669 if (nparams > 7) 7670 return -EINVAL; 7671 7672 memset(&c, 0, sizeof(c)); 7673 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7674 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7675 V_FW_PARAMS_CMD_PFN(pf) | 7676 V_FW_PARAMS_CMD_VFN(vf)); 7677 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7678 7679 for (i = 0; i < nparams; i++) { 7680 *p++ = cpu_to_be32(*params++); 7681 if (rw) 7682 *p = cpu_to_be32(*(val + i)); 7683 p++; 7684 } 7685 7686 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7687 if (ret == 0) 7688 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7689 *val++ = be32_to_cpu(*p); 7690 return ret; 7691 } 7692 7693 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7694 unsigned int vf, unsigned int nparams, const u32 *params, 7695 u32 *val) 7696 { 7697 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7698 } 7699 7700 /** 7701 * t4_set_params_timeout - sets FW or device parameters 7702 * @adap: the adapter 7703 * @mbox: mailbox to use for the FW command 7704 * @pf: the PF 7705 * @vf: the VF 7706 * @nparams: the number of parameters 7707 * @params: the parameter names 7708 * @val: the parameter values 7709 * @timeout: the timeout time 7710 * 7711 * Sets the value of FW or device parameters. Up to 7 parameters can be 7712 * specified at once. 7713 */ 7714 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7715 unsigned int pf, unsigned int vf, 7716 unsigned int nparams, const u32 *params, 7717 const u32 *val, int timeout) 7718 { 7719 struct fw_params_cmd c; 7720 __be32 *p = &c.param[0].mnem; 7721 7722 if (nparams > 7) 7723 return -EINVAL; 7724 7725 memset(&c, 0, sizeof(c)); 7726 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7727 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7728 V_FW_PARAMS_CMD_PFN(pf) | 7729 V_FW_PARAMS_CMD_VFN(vf)); 7730 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7731 7732 while (nparams--) { 7733 *p++ = cpu_to_be32(*params++); 7734 *p++ = cpu_to_be32(*val++); 7735 } 7736 7737 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7738 } 7739 7740 /** 7741 * t4_set_params - sets FW or device parameters 7742 * @adap: the adapter 7743 * @mbox: mailbox to use for the FW command 7744 * @pf: the PF 7745 * @vf: the VF 7746 * @nparams: the number of parameters 7747 * @params: the parameter names 7748 * @val: the parameter values 7749 * 7750 * Sets the value of FW or device parameters. Up to 7 parameters can be 7751 * specified at once. 7752 */ 7753 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7754 unsigned int vf, unsigned int nparams, const u32 *params, 7755 const u32 *val) 7756 { 7757 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7758 FW_CMD_MAX_TIMEOUT); 7759 } 7760 7761 /** 7762 * t4_cfg_pfvf - configure PF/VF resource limits 7763 * @adap: the adapter 7764 * @mbox: mailbox to use for the FW command 7765 * @pf: the PF being configured 7766 * @vf: the VF being configured 7767 * @txq: the max number of egress queues 7768 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7769 * @rxqi: the max number of interrupt-capable ingress queues 7770 * @rxq: the max number of interruptless ingress queues 7771 * @tc: the PCI traffic class 7772 * @vi: the max number of virtual interfaces 7773 * @cmask: the channel access rights mask for the PF/VF 7774 * @pmask: the port access rights mask for the PF/VF 7775 * @nexact: the maximum number of exact MPS filters 7776 * @rcaps: read capabilities 7777 * @wxcaps: write/execute capabilities 7778 * 7779 * Configures resource limits and capabilities for a physical or virtual 7780 * function. 7781 */ 7782 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7783 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7784 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7785 unsigned int vi, unsigned int cmask, unsigned int pmask, 7786 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7787 { 7788 struct fw_pfvf_cmd c; 7789 7790 memset(&c, 0, sizeof(c)); 7791 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7792 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7793 V_FW_PFVF_CMD_VFN(vf)); 7794 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7795 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7796 V_FW_PFVF_CMD_NIQ(rxq)); 7797 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7798 V_FW_PFVF_CMD_PMASK(pmask) | 7799 V_FW_PFVF_CMD_NEQ(txq)); 7800 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7801 V_FW_PFVF_CMD_NVI(vi) | 7802 V_FW_PFVF_CMD_NEXACTF(nexact)); 7803 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7804 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7805 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7806 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7807 } 7808 7809 /** 7810 * t4_alloc_vi_func - allocate a virtual interface 7811 * @adap: the adapter 7812 * @mbox: mailbox to use for the FW command 7813 * @port: physical port associated with the VI 7814 * @pf: the PF owning the VI 7815 * @vf: the VF owning the VI 7816 * @nmac: number of MAC addresses needed (1 to 5) 7817 * @mac: the MAC addresses of the VI 7818 * @rss_size: size of RSS table slice associated with this VI 7819 * @portfunc: which Port Application Function MAC Address is desired 7820 * @idstype: Intrusion Detection Type 7821 * 7822 * Allocates a virtual interface for the given physical port. If @mac is 7823 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7824 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7825 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7826 * stored consecutively so the space needed is @nmac * 6 bytes. 7827 * Returns a negative error number or the non-negative VI id. 7828 */ 7829 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7830 unsigned int port, unsigned int pf, unsigned int vf, 7831 unsigned int nmac, u8 *mac, u16 *rss_size, 7832 uint8_t *vfvld, uint16_t *vin, 7833 unsigned int portfunc, unsigned int idstype) 7834 { 7835 int ret; 7836 struct fw_vi_cmd c; 7837 7838 memset(&c, 0, sizeof(c)); 7839 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7840 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7841 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7842 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7843 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7844 V_FW_VI_CMD_FUNC(portfunc)); 7845 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7846 c.nmac = nmac - 1; 7847 if(!rss_size) 7848 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7849 7850 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7851 if (ret) 7852 return ret; 7853 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7854 7855 if (mac) { 7856 memcpy(mac, c.mac, sizeof(c.mac)); 7857 switch (nmac) { 7858 case 5: 7859 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7860 case 4: 7861 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7862 case 3: 7863 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7864 case 2: 7865 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7866 } 7867 } 7868 if (rss_size) 7869 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7870 if (vfvld) { 7871 *vfvld = adap->params.viid_smt_extn_support ? 7872 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 7873 G_FW_VIID_VIVLD(ret); 7874 } 7875 if (vin) { 7876 *vin = adap->params.viid_smt_extn_support ? 7877 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 7878 G_FW_VIID_VIN(ret); 7879 } 7880 7881 return ret; 7882 } 7883 7884 /** 7885 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7886 * @adap: the adapter 7887 * @mbox: mailbox to use for the FW command 7888 * @port: physical port associated with the VI 7889 * @pf: the PF owning the VI 7890 * @vf: the VF owning the VI 7891 * @nmac: number of MAC addresses needed (1 to 5) 7892 * @mac: the MAC addresses of the VI 7893 * @rss_size: size of RSS table slice associated with this VI 7894 * 7895 * backwards compatible and convieniance routine to allocate a Virtual 7896 * Interface with a Ethernet Port Application Function and Intrustion 7897 * Detection System disabled. 7898 */ 7899 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 7900 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 7901 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 7902 { 7903 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 7904 vfvld, vin, FW_VI_FUNC_ETH, 0); 7905 } 7906 7907 /** 7908 * t4_free_vi - free a virtual interface 7909 * @adap: the adapter 7910 * @mbox: mailbox to use for the FW command 7911 * @pf: the PF owning the VI 7912 * @vf: the VF owning the VI 7913 * @viid: virtual interface identifiler 7914 * 7915 * Free a previously allocated virtual interface. 7916 */ 7917 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 7918 unsigned int vf, unsigned int viid) 7919 { 7920 struct fw_vi_cmd c; 7921 7922 memset(&c, 0, sizeof(c)); 7923 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 7924 F_FW_CMD_REQUEST | 7925 F_FW_CMD_EXEC | 7926 V_FW_VI_CMD_PFN(pf) | 7927 V_FW_VI_CMD_VFN(vf)); 7928 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 7929 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 7930 7931 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7932 } 7933 7934 /** 7935 * t4_set_rxmode - set Rx properties of a virtual interface 7936 * @adap: the adapter 7937 * @mbox: mailbox to use for the FW command 7938 * @viid: the VI id 7939 * @mtu: the new MTU or -1 7940 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 7941 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 7942 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 7943 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 7944 * @sleep_ok: if true we may sleep while awaiting command completion 7945 * 7946 * Sets Rx properties of a virtual interface. 7947 */ 7948 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 7949 int mtu, int promisc, int all_multi, int bcast, int vlanex, 7950 bool sleep_ok) 7951 { 7952 struct fw_vi_rxmode_cmd c; 7953 7954 /* convert to FW values */ 7955 if (mtu < 0) 7956 mtu = M_FW_VI_RXMODE_CMD_MTU; 7957 if (promisc < 0) 7958 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 7959 if (all_multi < 0) 7960 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 7961 if (bcast < 0) 7962 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 7963 if (vlanex < 0) 7964 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 7965 7966 memset(&c, 0, sizeof(c)); 7967 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 7968 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7969 V_FW_VI_RXMODE_CMD_VIID(viid)); 7970 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7971 c.mtu_to_vlanexen = 7972 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 7973 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 7974 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 7975 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 7976 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 7977 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7978 } 7979 7980 /** 7981 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 7982 * @adap: the adapter 7983 * @mbox: mailbox to use for the FW command 7984 * @viid: the VI id 7985 * @free: if true any existing filters for this VI id are first removed 7986 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 7987 * @addr: the MAC address(es) 7988 * @idx: where to store the index of each allocated filter 7989 * @hash: pointer to hash address filter bitmap 7990 * @sleep_ok: call is allowed to sleep 7991 * 7992 * Allocates an exact-match filter for each of the supplied addresses and 7993 * sets it to the corresponding address. If @idx is not %NULL it should 7994 * have at least @naddr entries, each of which will be set to the index of 7995 * the filter allocated for the corresponding MAC address. If a filter 7996 * could not be allocated for an address its index is set to 0xffff. 7997 * If @hash is not %NULL addresses that fail to allocate an exact filter 7998 * are hashed and update the hash filter bitmap pointed at by @hash. 7999 * 8000 * Returns a negative error number or the number of filters allocated. 8001 */ 8002 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8003 unsigned int viid, bool free, unsigned int naddr, 8004 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8005 { 8006 int offset, ret = 0; 8007 struct fw_vi_mac_cmd c; 8008 unsigned int nfilters = 0; 8009 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8010 unsigned int rem = naddr; 8011 8012 if (naddr > max_naddr) 8013 return -EINVAL; 8014 8015 for (offset = 0; offset < naddr ; /**/) { 8016 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8017 ? rem 8018 : ARRAY_SIZE(c.u.exact)); 8019 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8020 u.exact[fw_naddr]), 16); 8021 struct fw_vi_mac_exact *p; 8022 int i; 8023 8024 memset(&c, 0, sizeof(c)); 8025 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8026 F_FW_CMD_REQUEST | 8027 F_FW_CMD_WRITE | 8028 V_FW_CMD_EXEC(free) | 8029 V_FW_VI_MAC_CMD_VIID(viid)); 8030 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8031 V_FW_CMD_LEN16(len16)); 8032 8033 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8034 p->valid_to_idx = 8035 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8036 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8037 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8038 } 8039 8040 /* 8041 * It's okay if we run out of space in our MAC address arena. 8042 * Some of the addresses we submit may get stored so we need 8043 * to run through the reply to see what the results were ... 8044 */ 8045 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8046 if (ret && ret != -FW_ENOMEM) 8047 break; 8048 8049 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8050 u16 index = G_FW_VI_MAC_CMD_IDX( 8051 be16_to_cpu(p->valid_to_idx)); 8052 8053 if (idx) 8054 idx[offset+i] = (index >= max_naddr 8055 ? 0xffff 8056 : index); 8057 if (index < max_naddr) 8058 nfilters++; 8059 else if (hash) 8060 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8061 } 8062 8063 free = false; 8064 offset += fw_naddr; 8065 rem -= fw_naddr; 8066 } 8067 8068 if (ret == 0 || ret == -FW_ENOMEM) 8069 ret = nfilters; 8070 return ret; 8071 } 8072 8073 /** 8074 * t4_change_mac - modifies the exact-match filter for a MAC address 8075 * @adap: the adapter 8076 * @mbox: mailbox to use for the FW command 8077 * @viid: the VI id 8078 * @idx: index of existing filter for old value of MAC address, or -1 8079 * @addr: the new MAC address value 8080 * @persist: whether a new MAC allocation should be persistent 8081 * @smt_idx: add MAC to SMT and return its index, or NULL 8082 * 8083 * Modifies an exact-match filter and sets it to the new MAC address if 8084 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8085 * latter case the address is added persistently if @persist is %true. 8086 * 8087 * Note that in general it is not possible to modify the value of a given 8088 * filter so the generic way to modify an address filter is to free the one 8089 * being used by the old address value and allocate a new filter for the 8090 * new address value. 8091 * 8092 * Returns a negative error number or the index of the filter with the new 8093 * MAC value. Note that this index may differ from @idx. 8094 */ 8095 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8096 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8097 { 8098 int ret, mode; 8099 struct fw_vi_mac_cmd c; 8100 struct fw_vi_mac_exact *p = c.u.exact; 8101 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8102 8103 if (idx < 0) /* new allocation */ 8104 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8105 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8106 8107 memset(&c, 0, sizeof(c)); 8108 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8109 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8110 V_FW_VI_MAC_CMD_VIID(viid)); 8111 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8112 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8113 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8114 V_FW_VI_MAC_CMD_IDX(idx)); 8115 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8116 8117 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8118 if (ret == 0) { 8119 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8120 if (ret >= max_mac_addr) 8121 ret = -ENOMEM; 8122 if (smt_idx) { 8123 if (adap->params.viid_smt_extn_support) 8124 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8125 else { 8126 if (chip_id(adap) <= CHELSIO_T5) 8127 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8128 else 8129 *smt_idx = viid & M_FW_VIID_VIN; 8130 } 8131 } 8132 } 8133 return ret; 8134 } 8135 8136 /** 8137 * t4_set_addr_hash - program the MAC inexact-match hash filter 8138 * @adap: the adapter 8139 * @mbox: mailbox to use for the FW command 8140 * @viid: the VI id 8141 * @ucast: whether the hash filter should also match unicast addresses 8142 * @vec: the value to be written to the hash filter 8143 * @sleep_ok: call is allowed to sleep 8144 * 8145 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8146 */ 8147 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8148 bool ucast, u64 vec, bool sleep_ok) 8149 { 8150 struct fw_vi_mac_cmd c; 8151 u32 val; 8152 8153 memset(&c, 0, sizeof(c)); 8154 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8155 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8156 V_FW_VI_ENABLE_CMD_VIID(viid)); 8157 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8158 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8159 c.freemacs_to_len16 = cpu_to_be32(val); 8160 c.u.hash.hashvec = cpu_to_be64(vec); 8161 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8162 } 8163 8164 /** 8165 * t4_enable_vi_params - enable/disable a virtual interface 8166 * @adap: the adapter 8167 * @mbox: mailbox to use for the FW command 8168 * @viid: the VI id 8169 * @rx_en: 1=enable Rx, 0=disable Rx 8170 * @tx_en: 1=enable Tx, 0=disable Tx 8171 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8172 * 8173 * Enables/disables a virtual interface. Note that setting DCB Enable 8174 * only makes sense when enabling a Virtual Interface ... 8175 */ 8176 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8177 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8178 { 8179 struct fw_vi_enable_cmd c; 8180 8181 memset(&c, 0, sizeof(c)); 8182 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8183 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8184 V_FW_VI_ENABLE_CMD_VIID(viid)); 8185 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8186 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8187 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8188 FW_LEN16(c)); 8189 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8190 } 8191 8192 /** 8193 * t4_enable_vi - enable/disable a virtual interface 8194 * @adap: the adapter 8195 * @mbox: mailbox to use for the FW command 8196 * @viid: the VI id 8197 * @rx_en: 1=enable Rx, 0=disable Rx 8198 * @tx_en: 1=enable Tx, 0=disable Tx 8199 * 8200 * Enables/disables a virtual interface. Note that setting DCB Enable 8201 * only makes sense when enabling a Virtual Interface ... 8202 */ 8203 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8204 bool rx_en, bool tx_en) 8205 { 8206 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8207 } 8208 8209 /** 8210 * t4_identify_port - identify a VI's port by blinking its LED 8211 * @adap: the adapter 8212 * @mbox: mailbox to use for the FW command 8213 * @viid: the VI id 8214 * @nblinks: how many times to blink LED at 2.5 Hz 8215 * 8216 * Identifies a VI's port by blinking its LED. 8217 */ 8218 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8219 unsigned int nblinks) 8220 { 8221 struct fw_vi_enable_cmd c; 8222 8223 memset(&c, 0, sizeof(c)); 8224 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8225 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8226 V_FW_VI_ENABLE_CMD_VIID(viid)); 8227 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8228 c.blinkdur = cpu_to_be16(nblinks); 8229 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8230 } 8231 8232 /** 8233 * t4_iq_stop - stop an ingress queue and its FLs 8234 * @adap: the adapter 8235 * @mbox: mailbox to use for the FW command 8236 * @pf: the PF owning the queues 8237 * @vf: the VF owning the queues 8238 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8239 * @iqid: ingress queue id 8240 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8241 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8242 * 8243 * Stops an ingress queue and its associated FLs, if any. This causes 8244 * any current or future data/messages destined for these queues to be 8245 * tossed. 8246 */ 8247 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8248 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8249 unsigned int fl0id, unsigned int fl1id) 8250 { 8251 struct fw_iq_cmd c; 8252 8253 memset(&c, 0, sizeof(c)); 8254 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8255 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8256 V_FW_IQ_CMD_VFN(vf)); 8257 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8258 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8259 c.iqid = cpu_to_be16(iqid); 8260 c.fl0id = cpu_to_be16(fl0id); 8261 c.fl1id = cpu_to_be16(fl1id); 8262 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8263 } 8264 8265 /** 8266 * t4_iq_free - free an ingress queue and its FLs 8267 * @adap: the adapter 8268 * @mbox: mailbox to use for the FW command 8269 * @pf: the PF owning the queues 8270 * @vf: the VF owning the queues 8271 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8272 * @iqid: ingress queue id 8273 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8274 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8275 * 8276 * Frees an ingress queue and its associated FLs, if any. 8277 */ 8278 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8279 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8280 unsigned int fl0id, unsigned int fl1id) 8281 { 8282 struct fw_iq_cmd c; 8283 8284 memset(&c, 0, sizeof(c)); 8285 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8286 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8287 V_FW_IQ_CMD_VFN(vf)); 8288 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8289 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8290 c.iqid = cpu_to_be16(iqid); 8291 c.fl0id = cpu_to_be16(fl0id); 8292 c.fl1id = cpu_to_be16(fl1id); 8293 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8294 } 8295 8296 /** 8297 * t4_eth_eq_free - free an Ethernet egress queue 8298 * @adap: the adapter 8299 * @mbox: mailbox to use for the FW command 8300 * @pf: the PF owning the queue 8301 * @vf: the VF owning the queue 8302 * @eqid: egress queue id 8303 * 8304 * Frees an Ethernet egress queue. 8305 */ 8306 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8307 unsigned int vf, unsigned int eqid) 8308 { 8309 struct fw_eq_eth_cmd c; 8310 8311 memset(&c, 0, sizeof(c)); 8312 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8313 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8314 V_FW_EQ_ETH_CMD_PFN(pf) | 8315 V_FW_EQ_ETH_CMD_VFN(vf)); 8316 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8317 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8318 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8319 } 8320 8321 /** 8322 * t4_ctrl_eq_free - free a control egress queue 8323 * @adap: the adapter 8324 * @mbox: mailbox to use for the FW command 8325 * @pf: the PF owning the queue 8326 * @vf: the VF owning the queue 8327 * @eqid: egress queue id 8328 * 8329 * Frees a control egress queue. 8330 */ 8331 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8332 unsigned int vf, unsigned int eqid) 8333 { 8334 struct fw_eq_ctrl_cmd c; 8335 8336 memset(&c, 0, sizeof(c)); 8337 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8338 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8339 V_FW_EQ_CTRL_CMD_PFN(pf) | 8340 V_FW_EQ_CTRL_CMD_VFN(vf)); 8341 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8342 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8343 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8344 } 8345 8346 /** 8347 * t4_ofld_eq_free - free an offload egress queue 8348 * @adap: the adapter 8349 * @mbox: mailbox to use for the FW command 8350 * @pf: the PF owning the queue 8351 * @vf: the VF owning the queue 8352 * @eqid: egress queue id 8353 * 8354 * Frees a control egress queue. 8355 */ 8356 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8357 unsigned int vf, unsigned int eqid) 8358 { 8359 struct fw_eq_ofld_cmd c; 8360 8361 memset(&c, 0, sizeof(c)); 8362 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8363 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8364 V_FW_EQ_OFLD_CMD_PFN(pf) | 8365 V_FW_EQ_OFLD_CMD_VFN(vf)); 8366 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8367 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8368 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8369 } 8370 8371 /** 8372 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8373 * @link_down_rc: Link Down Reason Code 8374 * 8375 * Returns a string representation of the Link Down Reason Code. 8376 */ 8377 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8378 { 8379 static const char *reason[] = { 8380 "Link Down", 8381 "Remote Fault", 8382 "Auto-negotiation Failure", 8383 "Reserved3", 8384 "Insufficient Airflow", 8385 "Unable To Determine Reason", 8386 "No RX Signal Detected", 8387 "Reserved7", 8388 }; 8389 8390 if (link_down_rc >= ARRAY_SIZE(reason)) 8391 return "Bad Reason Code"; 8392 8393 return reason[link_down_rc]; 8394 } 8395 8396 /* 8397 * Return the highest speed set in the port capabilities, in Mb/s. 8398 */ 8399 unsigned int fwcap_to_speed(uint32_t caps) 8400 { 8401 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8402 do { \ 8403 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8404 return __speed; \ 8405 } while (0) 8406 8407 TEST_SPEED_RETURN(400G, 400000); 8408 TEST_SPEED_RETURN(200G, 200000); 8409 TEST_SPEED_RETURN(100G, 100000); 8410 TEST_SPEED_RETURN(50G, 50000); 8411 TEST_SPEED_RETURN(40G, 40000); 8412 TEST_SPEED_RETURN(25G, 25000); 8413 TEST_SPEED_RETURN(10G, 10000); 8414 TEST_SPEED_RETURN(1G, 1000); 8415 TEST_SPEED_RETURN(100M, 100); 8416 8417 #undef TEST_SPEED_RETURN 8418 8419 return 0; 8420 } 8421 8422 /* 8423 * Return the port capabilities bit for the given speed, which is in Mb/s. 8424 */ 8425 uint32_t speed_to_fwcap(unsigned int speed) 8426 { 8427 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8428 do { \ 8429 if (speed == __speed) \ 8430 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8431 } while (0) 8432 8433 TEST_SPEED_RETURN(400G, 400000); 8434 TEST_SPEED_RETURN(200G, 200000); 8435 TEST_SPEED_RETURN(100G, 100000); 8436 TEST_SPEED_RETURN(50G, 50000); 8437 TEST_SPEED_RETURN(40G, 40000); 8438 TEST_SPEED_RETURN(25G, 25000); 8439 TEST_SPEED_RETURN(10G, 10000); 8440 TEST_SPEED_RETURN(1G, 1000); 8441 TEST_SPEED_RETURN(100M, 100); 8442 8443 #undef TEST_SPEED_RETURN 8444 8445 return 0; 8446 } 8447 8448 /* 8449 * Return the port capabilities bit for the highest speed in the capabilities. 8450 */ 8451 uint32_t fwcap_top_speed(uint32_t caps) 8452 { 8453 #define TEST_SPEED_RETURN(__caps_speed) \ 8454 do { \ 8455 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8456 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8457 } while (0) 8458 8459 TEST_SPEED_RETURN(400G); 8460 TEST_SPEED_RETURN(200G); 8461 TEST_SPEED_RETURN(100G); 8462 TEST_SPEED_RETURN(50G); 8463 TEST_SPEED_RETURN(40G); 8464 TEST_SPEED_RETURN(25G); 8465 TEST_SPEED_RETURN(10G); 8466 TEST_SPEED_RETURN(1G); 8467 TEST_SPEED_RETURN(100M); 8468 8469 #undef TEST_SPEED_RETURN 8470 8471 return 0; 8472 } 8473 8474 8475 /** 8476 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8477 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8478 * 8479 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8480 * 32-bit Port Capabilities value. 8481 */ 8482 static uint32_t lstatus_to_fwcap(u32 lstatus) 8483 { 8484 uint32_t linkattr = 0; 8485 8486 /* 8487 * Unfortunately the format of the Link Status in the old 8488 * 16-bit Port Information message isn't the same as the 8489 * 16-bit Port Capabilities bitfield used everywhere else ... 8490 */ 8491 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8492 linkattr |= FW_PORT_CAP32_FC_RX; 8493 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8494 linkattr |= FW_PORT_CAP32_FC_TX; 8495 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8496 linkattr |= FW_PORT_CAP32_SPEED_100M; 8497 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8498 linkattr |= FW_PORT_CAP32_SPEED_1G; 8499 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8500 linkattr |= FW_PORT_CAP32_SPEED_10G; 8501 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8502 linkattr |= FW_PORT_CAP32_SPEED_25G; 8503 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8504 linkattr |= FW_PORT_CAP32_SPEED_40G; 8505 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8506 linkattr |= FW_PORT_CAP32_SPEED_100G; 8507 8508 return linkattr; 8509 } 8510 8511 /* 8512 * Updates all fields owned by the common code in port_info and link_config 8513 * based on information provided by the firmware. Does not touch any 8514 * requested_* field. 8515 */ 8516 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8517 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8518 { 8519 struct link_config old_lc, *lc = &pi->link_cfg; 8520 unsigned char fc, fec; 8521 u32 stat, linkattr; 8522 int old_ptype, old_mtype; 8523 8524 old_ptype = pi->port_type; 8525 old_mtype = pi->mod_type; 8526 old_lc = *lc; 8527 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8528 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8529 8530 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8531 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8532 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8533 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8534 8535 lc->supported = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8536 lc->advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8537 lc->lp_advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8538 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8539 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8540 8541 linkattr = lstatus_to_fwcap(stat); 8542 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8543 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8544 8545 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8546 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8547 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8548 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8549 8550 lc->supported = be32_to_cpu(p->u.info32.pcaps32); 8551 lc->advertising = be32_to_cpu(p->u.info32.acaps32); 8552 lc->lp_advertising = be16_to_cpu(p->u.info32.lpacaps32); 8553 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8554 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8555 8556 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8557 } else { 8558 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8559 return; 8560 } 8561 8562 lc->speed = fwcap_to_speed(linkattr); 8563 8564 fc = 0; 8565 if (linkattr & FW_PORT_CAP32_FC_RX) 8566 fc |= PAUSE_RX; 8567 if (linkattr & FW_PORT_CAP32_FC_TX) 8568 fc |= PAUSE_TX; 8569 lc->fc = fc; 8570 8571 fec = FEC_NONE; 8572 if (linkattr & FW_PORT_CAP32_FEC_RS) 8573 fec |= FEC_RS; 8574 if (linkattr & FW_PORT_CAP32_FEC_BASER_RS) 8575 fec |= FEC_BASER_RS; 8576 lc->fec = fec; 8577 8578 if (mod_changed != NULL) 8579 *mod_changed = false; 8580 if (link_changed != NULL) 8581 *link_changed = false; 8582 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 8583 old_lc.supported != lc->supported) { 8584 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 8585 lc->fec_hint = lc->advertising & 8586 V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC); 8587 } 8588 if (mod_changed != NULL) 8589 *mod_changed = true; 8590 } 8591 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 8592 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 8593 if (link_changed != NULL) 8594 *link_changed = true; 8595 } 8596 } 8597 8598 /** 8599 * t4_update_port_info - retrieve and update port information if changed 8600 * @pi: the port_info 8601 * 8602 * We issue a Get Port Information Command to the Firmware and, if 8603 * successful, we check to see if anything is different from what we 8604 * last recorded and update things accordingly. 8605 */ 8606 int t4_update_port_info(struct port_info *pi) 8607 { 8608 struct adapter *sc = pi->adapter; 8609 struct fw_port_cmd cmd; 8610 enum fw_port_action action; 8611 int ret; 8612 8613 memset(&cmd, 0, sizeof(cmd)); 8614 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 8615 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8616 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 8617 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 8618 FW_PORT_ACTION_GET_PORT_INFO; 8619 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 8620 FW_LEN16(cmd)); 8621 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 8622 if (ret) 8623 return ret; 8624 8625 handle_port_info(pi, &cmd, action, NULL, NULL); 8626 return 0; 8627 } 8628 8629 /** 8630 * t4_handle_fw_rpl - process a FW reply message 8631 * @adap: the adapter 8632 * @rpl: start of the FW message 8633 * 8634 * Processes a FW message, such as link state change messages. 8635 */ 8636 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 8637 { 8638 u8 opcode = *(const u8 *)rpl; 8639 const struct fw_port_cmd *p = (const void *)rpl; 8640 enum fw_port_action action = 8641 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 8642 bool mod_changed, link_changed; 8643 8644 if (opcode == FW_PORT_CMD && 8645 (action == FW_PORT_ACTION_GET_PORT_INFO || 8646 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 8647 /* link/module state change message */ 8648 int i; 8649 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 8650 struct port_info *pi = NULL; 8651 struct link_config *lc; 8652 8653 for_each_port(adap, i) { 8654 pi = adap2pinfo(adap, i); 8655 if (pi->tx_chan == chan) 8656 break; 8657 } 8658 8659 lc = &pi->link_cfg; 8660 PORT_LOCK(pi); 8661 handle_port_info(pi, p, action, &mod_changed, &link_changed); 8662 PORT_UNLOCK(pi); 8663 if (mod_changed) 8664 t4_os_portmod_changed(pi); 8665 if (link_changed) { 8666 PORT_LOCK(pi); 8667 t4_os_link_changed(pi); 8668 PORT_UNLOCK(pi); 8669 } 8670 } else { 8671 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 8672 return -EINVAL; 8673 } 8674 return 0; 8675 } 8676 8677 /** 8678 * get_pci_mode - determine a card's PCI mode 8679 * @adapter: the adapter 8680 * @p: where to store the PCI settings 8681 * 8682 * Determines a card's PCI mode and associated parameters, such as speed 8683 * and width. 8684 */ 8685 static void get_pci_mode(struct adapter *adapter, 8686 struct pci_params *p) 8687 { 8688 u16 val; 8689 u32 pcie_cap; 8690 8691 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8692 if (pcie_cap) { 8693 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 8694 p->speed = val & PCI_EXP_LNKSTA_CLS; 8695 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 8696 } 8697 } 8698 8699 struct flash_desc { 8700 u32 vendor_and_model_id; 8701 u32 size_mb; 8702 }; 8703 8704 int t4_get_flash_params(struct adapter *adapter) 8705 { 8706 /* 8707 * Table for non-standard supported Flash parts. Note, all Flash 8708 * parts must have 64KB sectors. 8709 */ 8710 static struct flash_desc supported_flash[] = { 8711 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 8712 }; 8713 8714 int ret; 8715 u32 flashid = 0; 8716 unsigned int part, manufacturer; 8717 unsigned int density, size = 0; 8718 8719 8720 /* 8721 * Issue a Read ID Command to the Flash part. We decode supported 8722 * Flash parts and their sizes from this. There's a newer Query 8723 * Command which can retrieve detailed geometry information but many 8724 * Flash parts don't support it. 8725 */ 8726 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 8727 if (!ret) 8728 ret = sf1_read(adapter, 3, 0, 1, &flashid); 8729 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 8730 if (ret < 0) 8731 return ret; 8732 8733 /* 8734 * Check to see if it's one of our non-standard supported Flash parts. 8735 */ 8736 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 8737 if (supported_flash[part].vendor_and_model_id == flashid) { 8738 adapter->params.sf_size = 8739 supported_flash[part].size_mb; 8740 adapter->params.sf_nsec = 8741 adapter->params.sf_size / SF_SEC_SIZE; 8742 goto found; 8743 } 8744 8745 /* 8746 * Decode Flash part size. The code below looks repetative with 8747 * common encodings, but that's not guaranteed in the JEDEC 8748 * specification for the Read JADEC ID command. The only thing that 8749 * we're guaranteed by the JADEC specification is where the 8750 * Manufacturer ID is in the returned result. After that each 8751 * Manufacturer ~could~ encode things completely differently. 8752 * Note, all Flash parts must have 64KB sectors. 8753 */ 8754 manufacturer = flashid & 0xff; 8755 switch (manufacturer) { 8756 case 0x20: /* Micron/Numonix */ 8757 /* 8758 * This Density -> Size decoding table is taken from Micron 8759 * Data Sheets. 8760 */ 8761 density = (flashid >> 16) & 0xff; 8762 switch (density) { 8763 case 0x14: size = 1 << 20; break; /* 1MB */ 8764 case 0x15: size = 1 << 21; break; /* 2MB */ 8765 case 0x16: size = 1 << 22; break; /* 4MB */ 8766 case 0x17: size = 1 << 23; break; /* 8MB */ 8767 case 0x18: size = 1 << 24; break; /* 16MB */ 8768 case 0x19: size = 1 << 25; break; /* 32MB */ 8769 case 0x20: size = 1 << 26; break; /* 64MB */ 8770 case 0x21: size = 1 << 27; break; /* 128MB */ 8771 case 0x22: size = 1 << 28; break; /* 256MB */ 8772 } 8773 break; 8774 8775 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 8776 /* 8777 * This Density -> Size decoding table is taken from ISSI 8778 * Data Sheets. 8779 */ 8780 density = (flashid >> 16) & 0xff; 8781 switch (density) { 8782 case 0x16: size = 1 << 25; break; /* 32MB */ 8783 case 0x17: size = 1 << 26; break; /* 64MB */ 8784 } 8785 break; 8786 8787 case 0xc2: /* Macronix */ 8788 /* 8789 * This Density -> Size decoding table is taken from Macronix 8790 * Data Sheets. 8791 */ 8792 density = (flashid >> 16) & 0xff; 8793 switch (density) { 8794 case 0x17: size = 1 << 23; break; /* 8MB */ 8795 case 0x18: size = 1 << 24; break; /* 16MB */ 8796 } 8797 break; 8798 8799 case 0xef: /* Winbond */ 8800 /* 8801 * This Density -> Size decoding table is taken from Winbond 8802 * Data Sheets. 8803 */ 8804 density = (flashid >> 16) & 0xff; 8805 switch (density) { 8806 case 0x17: size = 1 << 23; break; /* 8MB */ 8807 case 0x18: size = 1 << 24; break; /* 16MB */ 8808 } 8809 break; 8810 } 8811 8812 /* If we didn't recognize the FLASH part, that's no real issue: the 8813 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 8814 * use a FLASH part which is at least 4MB in size and has 64KB 8815 * sectors. The unrecognized FLASH part is likely to be much larger 8816 * than 4MB, but that's all we really need. 8817 */ 8818 if (size == 0) { 8819 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 8820 size = 1 << 22; 8821 } 8822 8823 /* 8824 * Store decoded Flash size and fall through into vetting code. 8825 */ 8826 adapter->params.sf_size = size; 8827 adapter->params.sf_nsec = size / SF_SEC_SIZE; 8828 8829 found: 8830 /* 8831 * We should ~probably~ reject adapters with FLASHes which are too 8832 * small but we have some legacy FPGAs with small FLASHes that we'd 8833 * still like to use. So instead we emit a scary message ... 8834 */ 8835 if (adapter->params.sf_size < FLASH_MIN_SIZE) 8836 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 8837 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 8838 8839 return 0; 8840 } 8841 8842 static void set_pcie_completion_timeout(struct adapter *adapter, 8843 u8 range) 8844 { 8845 u16 val; 8846 u32 pcie_cap; 8847 8848 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8849 if (pcie_cap) { 8850 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 8851 val &= 0xfff0; 8852 val |= range ; 8853 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 8854 } 8855 } 8856 8857 const struct chip_params *t4_get_chip_params(int chipid) 8858 { 8859 static const struct chip_params chip_params[] = { 8860 { 8861 /* T4 */ 8862 .nchan = NCHAN, 8863 .pm_stats_cnt = PM_NSTATS, 8864 .cng_ch_bits_log = 2, 8865 .nsched_cls = 15, 8866 .cim_num_obq = CIM_NUM_OBQ, 8867 .mps_rplc_size = 128, 8868 .vfcount = 128, 8869 .sge_fl_db = F_DBPRIO, 8870 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 8871 }, 8872 { 8873 /* T5 */ 8874 .nchan = NCHAN, 8875 .pm_stats_cnt = PM_NSTATS, 8876 .cng_ch_bits_log = 2, 8877 .nsched_cls = 16, 8878 .cim_num_obq = CIM_NUM_OBQ_T5, 8879 .mps_rplc_size = 128, 8880 .vfcount = 128, 8881 .sge_fl_db = F_DBPRIO | F_DBTYPE, 8882 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8883 }, 8884 { 8885 /* T6 */ 8886 .nchan = T6_NCHAN, 8887 .pm_stats_cnt = T6_PM_NSTATS, 8888 .cng_ch_bits_log = 3, 8889 .nsched_cls = 16, 8890 .cim_num_obq = CIM_NUM_OBQ_T5, 8891 .mps_rplc_size = 256, 8892 .vfcount = 256, 8893 .sge_fl_db = 0, 8894 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8895 }, 8896 }; 8897 8898 chipid -= CHELSIO_T4; 8899 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 8900 return NULL; 8901 8902 return &chip_params[chipid]; 8903 } 8904 8905 /** 8906 * t4_prep_adapter - prepare SW and HW for operation 8907 * @adapter: the adapter 8908 * @buf: temporary space of at least VPD_LEN size provided by the caller. 8909 * 8910 * Initialize adapter SW state for the various HW modules, set initial 8911 * values for some adapter tunables, take PHYs out of reset, and 8912 * initialize the MDIO interface. 8913 */ 8914 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 8915 { 8916 int ret; 8917 uint16_t device_id; 8918 uint32_t pl_rev; 8919 8920 get_pci_mode(adapter, &adapter->params.pci); 8921 8922 pl_rev = t4_read_reg(adapter, A_PL_REV); 8923 adapter->params.chipid = G_CHIPID(pl_rev); 8924 adapter->params.rev = G_REV(pl_rev); 8925 if (adapter->params.chipid == 0) { 8926 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 8927 adapter->params.chipid = CHELSIO_T4; 8928 8929 /* T4A1 chip is not supported */ 8930 if (adapter->params.rev == 1) { 8931 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 8932 return -EINVAL; 8933 } 8934 } 8935 8936 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 8937 if (adapter->chip_params == NULL) 8938 return -EINVAL; 8939 8940 adapter->params.pci.vpd_cap_addr = 8941 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 8942 8943 ret = t4_get_flash_params(adapter); 8944 if (ret < 0) 8945 return ret; 8946 8947 /* Cards with real ASICs have the chipid in the PCIe device id */ 8948 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 8949 if (device_id >> 12 == chip_id(adapter)) 8950 adapter->params.cim_la_size = CIMLA_SIZE; 8951 else { 8952 /* FPGA */ 8953 adapter->params.fpga = 1; 8954 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 8955 } 8956 8957 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 8958 if (ret < 0) 8959 return ret; 8960 8961 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 8962 8963 /* 8964 * Default port and clock for debugging in case we can't reach FW. 8965 */ 8966 adapter->params.nports = 1; 8967 adapter->params.portvec = 1; 8968 adapter->params.vpd.cclk = 50000; 8969 8970 /* Set pci completion timeout value to 4 seconds. */ 8971 set_pcie_completion_timeout(adapter, 0xd); 8972 return 0; 8973 } 8974 8975 /** 8976 * t4_shutdown_adapter - shut down adapter, host & wire 8977 * @adapter: the adapter 8978 * 8979 * Perform an emergency shutdown of the adapter and stop it from 8980 * continuing any further communication on the ports or DMA to the 8981 * host. This is typically used when the adapter and/or firmware 8982 * have crashed and we want to prevent any further accidental 8983 * communication with the rest of the world. This will also force 8984 * the port Link Status to go down -- if register writes work -- 8985 * which should help our peers figure out that we're down. 8986 */ 8987 int t4_shutdown_adapter(struct adapter *adapter) 8988 { 8989 int port; 8990 8991 t4_intr_disable(adapter); 8992 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 8993 for_each_port(adapter, port) { 8994 u32 a_port_cfg = is_t4(adapter) ? 8995 PORT_REG(port, A_XGMAC_PORT_CFG) : 8996 T5_PORT_REG(port, A_MAC_PORT_CFG); 8997 8998 t4_write_reg(adapter, a_port_cfg, 8999 t4_read_reg(adapter, a_port_cfg) 9000 & ~V_SIGNAL_DET(1)); 9001 } 9002 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9003 9004 return 0; 9005 } 9006 9007 /** 9008 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9009 * @adapter: the adapter 9010 * @qid: the Queue ID 9011 * @qtype: the Ingress or Egress type for @qid 9012 * @user: true if this request is for a user mode queue 9013 * @pbar2_qoffset: BAR2 Queue Offset 9014 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9015 * 9016 * Returns the BAR2 SGE Queue Registers information associated with the 9017 * indicated Absolute Queue ID. These are passed back in return value 9018 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9019 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9020 * 9021 * This may return an error which indicates that BAR2 SGE Queue 9022 * registers aren't available. If an error is not returned, then the 9023 * following values are returned: 9024 * 9025 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9026 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9027 * 9028 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9029 * require the "Inferred Queue ID" ability may be used. E.g. the 9030 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9031 * then these "Inferred Queue ID" register may not be used. 9032 */ 9033 int t4_bar2_sge_qregs(struct adapter *adapter, 9034 unsigned int qid, 9035 enum t4_bar2_qtype qtype, 9036 int user, 9037 u64 *pbar2_qoffset, 9038 unsigned int *pbar2_qid) 9039 { 9040 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9041 u64 bar2_page_offset, bar2_qoffset; 9042 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9043 9044 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9045 * mode queues. 9046 */ 9047 if (!user && is_t4(adapter)) 9048 return -EINVAL; 9049 9050 /* Get our SGE Page Size parameters. 9051 */ 9052 page_shift = adapter->params.sge.page_shift; 9053 page_size = 1 << page_shift; 9054 9055 /* Get the right Queues per Page parameters for our Queue. 9056 */ 9057 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9058 ? adapter->params.sge.eq_s_qpp 9059 : adapter->params.sge.iq_s_qpp); 9060 qpp_mask = (1 << qpp_shift) - 1; 9061 9062 /* Calculate the basics of the BAR2 SGE Queue register area: 9063 * o The BAR2 page the Queue registers will be in. 9064 * o The BAR2 Queue ID. 9065 * o The BAR2 Queue ID Offset into the BAR2 page. 9066 */ 9067 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9068 bar2_qid = qid & qpp_mask; 9069 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9070 9071 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9072 * hardware will infer the Absolute Queue ID simply from the writes to 9073 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9074 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9075 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9076 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9077 * from the BAR2 Page and BAR2 Queue ID. 9078 * 9079 * One important censequence of this is that some BAR2 SGE registers 9080 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9081 * there. But other registers synthesize the SGE Queue ID purely 9082 * from the writes to the registers -- the Write Combined Doorbell 9083 * Buffer is a good example. These BAR2 SGE Registers are only 9084 * available for those BAR2 SGE Register areas where the SGE Absolute 9085 * Queue ID can be inferred from simple writes. 9086 */ 9087 bar2_qoffset = bar2_page_offset; 9088 bar2_qinferred = (bar2_qid_offset < page_size); 9089 if (bar2_qinferred) { 9090 bar2_qoffset += bar2_qid_offset; 9091 bar2_qid = 0; 9092 } 9093 9094 *pbar2_qoffset = bar2_qoffset; 9095 *pbar2_qid = bar2_qid; 9096 return 0; 9097 } 9098 9099 /** 9100 * t4_init_devlog_params - initialize adapter->params.devlog 9101 * @adap: the adapter 9102 * @fw_attach: whether we can talk to the firmware 9103 * 9104 * Initialize various fields of the adapter's Firmware Device Log 9105 * Parameters structure. 9106 */ 9107 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9108 { 9109 struct devlog_params *dparams = &adap->params.devlog; 9110 u32 pf_dparams; 9111 unsigned int devlog_meminfo; 9112 struct fw_devlog_cmd devlog_cmd; 9113 int ret; 9114 9115 /* If we're dealing with newer firmware, the Device Log Paramerters 9116 * are stored in a designated register which allows us to access the 9117 * Device Log even if we can't talk to the firmware. 9118 */ 9119 pf_dparams = 9120 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9121 if (pf_dparams) { 9122 unsigned int nentries, nentries128; 9123 9124 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9125 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9126 9127 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9128 nentries = (nentries128 + 1) * 128; 9129 dparams->size = nentries * sizeof(struct fw_devlog_e); 9130 9131 return 0; 9132 } 9133 9134 /* 9135 * For any failing returns ... 9136 */ 9137 memset(dparams, 0, sizeof *dparams); 9138 9139 /* 9140 * If we can't talk to the firmware, there's really nothing we can do 9141 * at this point. 9142 */ 9143 if (!fw_attach) 9144 return -ENXIO; 9145 9146 /* Otherwise, ask the firmware for it's Device Log Parameters. 9147 */ 9148 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9149 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9150 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9151 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9152 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9153 &devlog_cmd); 9154 if (ret) 9155 return ret; 9156 9157 devlog_meminfo = 9158 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9159 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9160 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9161 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9162 9163 return 0; 9164 } 9165 9166 /** 9167 * t4_init_sge_params - initialize adap->params.sge 9168 * @adapter: the adapter 9169 * 9170 * Initialize various fields of the adapter's SGE Parameters structure. 9171 */ 9172 int t4_init_sge_params(struct adapter *adapter) 9173 { 9174 u32 r; 9175 struct sge_params *sp = &adapter->params.sge; 9176 unsigned i, tscale = 1; 9177 9178 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9179 sp->counter_val[0] = G_THRESHOLD_0(r); 9180 sp->counter_val[1] = G_THRESHOLD_1(r); 9181 sp->counter_val[2] = G_THRESHOLD_2(r); 9182 sp->counter_val[3] = G_THRESHOLD_3(r); 9183 9184 if (chip_id(adapter) >= CHELSIO_T6) { 9185 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9186 tscale = G_TSCALE(r); 9187 if (tscale == 0) 9188 tscale = 1; 9189 else 9190 tscale += 2; 9191 } 9192 9193 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9194 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9195 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9196 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9197 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9198 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9199 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9200 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9201 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9202 9203 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9204 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9205 if (is_t4(adapter)) 9206 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9207 else if (is_t5(adapter)) 9208 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9209 else 9210 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9211 9212 /* egress queues: log2 of # of doorbells per BAR2 page */ 9213 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9214 r >>= S_QUEUESPERPAGEPF0 + 9215 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9216 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9217 9218 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9219 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9220 r >>= S_QUEUESPERPAGEPF0 + 9221 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9222 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9223 9224 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9225 r >>= S_HOSTPAGESIZEPF0 + 9226 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9227 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9228 9229 r = t4_read_reg(adapter, A_SGE_CONTROL); 9230 sp->sge_control = r; 9231 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9232 sp->fl_pktshift = G_PKTSHIFT(r); 9233 if (chip_id(adapter) <= CHELSIO_T5) { 9234 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9235 X_INGPADBOUNDARY_SHIFT); 9236 } else { 9237 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9238 X_T6_INGPADBOUNDARY_SHIFT); 9239 } 9240 if (is_t4(adapter)) 9241 sp->pack_boundary = sp->pad_boundary; 9242 else { 9243 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9244 if (G_INGPACKBOUNDARY(r) == 0) 9245 sp->pack_boundary = 16; 9246 else 9247 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9248 } 9249 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9250 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9251 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9252 9253 return 0; 9254 } 9255 9256 /* 9257 * Read and cache the adapter's compressed filter mode and ingress config. 9258 */ 9259 static void read_filter_mode_and_ingress_config(struct adapter *adap, 9260 bool sleep_ok) 9261 { 9262 uint32_t v; 9263 struct tp_params *tpp = &adap->params.tp; 9264 9265 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP, 9266 sleep_ok); 9267 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG, 9268 sleep_ok); 9269 9270 /* 9271 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9272 * shift positions of several elements of the Compressed Filter Tuple 9273 * for this adapter which we need frequently ... 9274 */ 9275 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9276 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9277 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9278 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9279 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9280 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9281 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9282 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9283 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9284 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9285 9286 if (chip_id(adap) > CHELSIO_T4) { 9287 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9288 adap->params.tp.hash_filter_mask = v; 9289 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9290 adap->params.tp.hash_filter_mask |= (u64)v << 32; 9291 } 9292 } 9293 9294 /** 9295 * t4_init_tp_params - initialize adap->params.tp 9296 * @adap: the adapter 9297 * 9298 * Initialize various fields of the adapter's TP Parameters structure. 9299 */ 9300 int t4_init_tp_params(struct adapter *adap, bool sleep_ok) 9301 { 9302 int chan; 9303 u32 v; 9304 struct tp_params *tpp = &adap->params.tp; 9305 9306 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9307 tpp->tre = G_TIMERRESOLUTION(v); 9308 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9309 9310 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9311 for (chan = 0; chan < MAX_NCHAN; chan++) 9312 tpp->tx_modq[chan] = chan; 9313 9314 read_filter_mode_and_ingress_config(adap, sleep_ok); 9315 9316 /* 9317 * Cache a mask of the bits that represent the error vector portion of 9318 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room 9319 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE). 9320 */ 9321 tpp->err_vec_mask = htobe16(0xffff); 9322 if (chip_id(adap) > CHELSIO_T5) { 9323 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9324 if (v & F_CRXPKTENC) { 9325 tpp->err_vec_mask = 9326 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC)); 9327 } 9328 } 9329 9330 return 0; 9331 } 9332 9333 /** 9334 * t4_filter_field_shift - calculate filter field shift 9335 * @adap: the adapter 9336 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9337 * 9338 * Return the shift position of a filter field within the Compressed 9339 * Filter Tuple. The filter field is specified via its selection bit 9340 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9341 */ 9342 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9343 { 9344 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 9345 unsigned int sel; 9346 int field_shift; 9347 9348 if ((filter_mode & filter_sel) == 0) 9349 return -1; 9350 9351 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9352 switch (filter_mode & sel) { 9353 case F_FCOE: 9354 field_shift += W_FT_FCOE; 9355 break; 9356 case F_PORT: 9357 field_shift += W_FT_PORT; 9358 break; 9359 case F_VNIC_ID: 9360 field_shift += W_FT_VNIC_ID; 9361 break; 9362 case F_VLAN: 9363 field_shift += W_FT_VLAN; 9364 break; 9365 case F_TOS: 9366 field_shift += W_FT_TOS; 9367 break; 9368 case F_PROTOCOL: 9369 field_shift += W_FT_PROTOCOL; 9370 break; 9371 case F_ETHERTYPE: 9372 field_shift += W_FT_ETHERTYPE; 9373 break; 9374 case F_MACMATCH: 9375 field_shift += W_FT_MACMATCH; 9376 break; 9377 case F_MPSHITTYPE: 9378 field_shift += W_FT_MPSHITTYPE; 9379 break; 9380 case F_FRAGMENTATION: 9381 field_shift += W_FT_FRAGMENTATION; 9382 break; 9383 } 9384 } 9385 return field_shift; 9386 } 9387 9388 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9389 { 9390 u8 addr[6]; 9391 int ret, i, j; 9392 struct port_info *p = adap2pinfo(adap, port_id); 9393 u32 param, val; 9394 struct vi_info *vi = &p->vi[0]; 9395 9396 for (i = 0, j = -1; i <= p->port_id; i++) { 9397 do { 9398 j++; 9399 } while ((adap->params.portvec & (1 << j)) == 0); 9400 } 9401 9402 p->tx_chan = j; 9403 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9404 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9405 p->lport = j; 9406 9407 if (!(adap->flags & IS_VF) || 9408 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9409 t4_update_port_info(p); 9410 } 9411 9412 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9413 &vi->vfvld, &vi->vin); 9414 if (ret < 0) 9415 return ret; 9416 9417 vi->viid = ret; 9418 t4_os_set_hw_addr(p, addr); 9419 9420 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9421 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9422 V_FW_PARAMS_PARAM_YZ(vi->viid); 9423 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9424 if (ret) 9425 vi->rss_base = 0xffff; 9426 else { 9427 /* MPASS((val >> 16) == rss_size); */ 9428 vi->rss_base = val & 0xffff; 9429 } 9430 9431 return 0; 9432 } 9433 9434 /** 9435 * t4_read_cimq_cfg - read CIM queue configuration 9436 * @adap: the adapter 9437 * @base: holds the queue base addresses in bytes 9438 * @size: holds the queue sizes in bytes 9439 * @thres: holds the queue full thresholds in bytes 9440 * 9441 * Returns the current configuration of the CIM queues, starting with 9442 * the IBQs, then the OBQs. 9443 */ 9444 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9445 { 9446 unsigned int i, v; 9447 int cim_num_obq = adap->chip_params->cim_num_obq; 9448 9449 for (i = 0; i < CIM_NUM_IBQ; i++) { 9450 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9451 V_QUENUMSELECT(i)); 9452 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9453 /* value is in 256-byte units */ 9454 *base++ = G_CIMQBASE(v) * 256; 9455 *size++ = G_CIMQSIZE(v) * 256; 9456 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9457 } 9458 for (i = 0; i < cim_num_obq; i++) { 9459 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9460 V_QUENUMSELECT(i)); 9461 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9462 /* value is in 256-byte units */ 9463 *base++ = G_CIMQBASE(v) * 256; 9464 *size++ = G_CIMQSIZE(v) * 256; 9465 } 9466 } 9467 9468 /** 9469 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9470 * @adap: the adapter 9471 * @qid: the queue index 9472 * @data: where to store the queue contents 9473 * @n: capacity of @data in 32-bit words 9474 * 9475 * Reads the contents of the selected CIM queue starting at address 0 up 9476 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9477 * error and the number of 32-bit words actually read on success. 9478 */ 9479 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9480 { 9481 int i, err, attempts; 9482 unsigned int addr; 9483 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9484 9485 if (qid > 5 || (n & 3)) 9486 return -EINVAL; 9487 9488 addr = qid * nwords; 9489 if (n > nwords) 9490 n = nwords; 9491 9492 /* It might take 3-10ms before the IBQ debug read access is allowed. 9493 * Wait for 1 Sec with a delay of 1 usec. 9494 */ 9495 attempts = 1000000; 9496 9497 for (i = 0; i < n; i++, addr++) { 9498 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 9499 F_IBQDBGEN); 9500 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 9501 attempts, 1); 9502 if (err) 9503 return err; 9504 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 9505 } 9506 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 9507 return i; 9508 } 9509 9510 /** 9511 * t4_read_cim_obq - read the contents of a CIM outbound queue 9512 * @adap: the adapter 9513 * @qid: the queue index 9514 * @data: where to store the queue contents 9515 * @n: capacity of @data in 32-bit words 9516 * 9517 * Reads the contents of the selected CIM queue starting at address 0 up 9518 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9519 * error and the number of 32-bit words actually read on success. 9520 */ 9521 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9522 { 9523 int i, err; 9524 unsigned int addr, v, nwords; 9525 int cim_num_obq = adap->chip_params->cim_num_obq; 9526 9527 if ((qid > (cim_num_obq - 1)) || (n & 3)) 9528 return -EINVAL; 9529 9530 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9531 V_QUENUMSELECT(qid)); 9532 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9533 9534 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 9535 nwords = G_CIMQSIZE(v) * 64; /* same */ 9536 if (n > nwords) 9537 n = nwords; 9538 9539 for (i = 0; i < n; i++, addr++) { 9540 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 9541 F_OBQDBGEN); 9542 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 9543 2, 1); 9544 if (err) 9545 return err; 9546 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 9547 } 9548 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 9549 return i; 9550 } 9551 9552 enum { 9553 CIM_QCTL_BASE = 0, 9554 CIM_CTL_BASE = 0x2000, 9555 CIM_PBT_ADDR_BASE = 0x2800, 9556 CIM_PBT_LRF_BASE = 0x3000, 9557 CIM_PBT_DATA_BASE = 0x3800 9558 }; 9559 9560 /** 9561 * t4_cim_read - read a block from CIM internal address space 9562 * @adap: the adapter 9563 * @addr: the start address within the CIM address space 9564 * @n: number of words to read 9565 * @valp: where to store the result 9566 * 9567 * Reads a block of 4-byte words from the CIM intenal address space. 9568 */ 9569 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 9570 unsigned int *valp) 9571 { 9572 int ret = 0; 9573 9574 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 9575 return -EBUSY; 9576 9577 for ( ; !ret && n--; addr += 4) { 9578 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 9579 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 9580 0, 5, 2); 9581 if (!ret) 9582 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 9583 } 9584 return ret; 9585 } 9586 9587 /** 9588 * t4_cim_write - write a block into CIM internal address space 9589 * @adap: the adapter 9590 * @addr: the start address within the CIM address space 9591 * @n: number of words to write 9592 * @valp: set of values to write 9593 * 9594 * Writes a block of 4-byte words into the CIM intenal address space. 9595 */ 9596 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 9597 const unsigned int *valp) 9598 { 9599 int ret = 0; 9600 9601 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 9602 return -EBUSY; 9603 9604 for ( ; !ret && n--; addr += 4) { 9605 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 9606 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 9607 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 9608 0, 5, 2); 9609 } 9610 return ret; 9611 } 9612 9613 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 9614 unsigned int val) 9615 { 9616 return t4_cim_write(adap, addr, 1, &val); 9617 } 9618 9619 /** 9620 * t4_cim_ctl_read - read a block from CIM control region 9621 * @adap: the adapter 9622 * @addr: the start address within the CIM control region 9623 * @n: number of words to read 9624 * @valp: where to store the result 9625 * 9626 * Reads a block of 4-byte words from the CIM control region. 9627 */ 9628 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 9629 unsigned int *valp) 9630 { 9631 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 9632 } 9633 9634 /** 9635 * t4_cim_read_la - read CIM LA capture buffer 9636 * @adap: the adapter 9637 * @la_buf: where to store the LA data 9638 * @wrptr: the HW write pointer within the capture buffer 9639 * 9640 * Reads the contents of the CIM LA buffer with the most recent entry at 9641 * the end of the returned data and with the entry at @wrptr first. 9642 * We try to leave the LA in the running state we find it in. 9643 */ 9644 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 9645 { 9646 int i, ret; 9647 unsigned int cfg, val, idx; 9648 9649 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9650 if (ret) 9651 return ret; 9652 9653 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 9654 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 9655 if (ret) 9656 return ret; 9657 } 9658 9659 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9660 if (ret) 9661 goto restart; 9662 9663 idx = G_UPDBGLAWRPTR(val); 9664 if (wrptr) 9665 *wrptr = idx; 9666 9667 for (i = 0; i < adap->params.cim_la_size; i++) { 9668 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9669 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 9670 if (ret) 9671 break; 9672 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9673 if (ret) 9674 break; 9675 if (val & F_UPDBGLARDEN) { 9676 ret = -ETIMEDOUT; 9677 break; 9678 } 9679 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 9680 if (ret) 9681 break; 9682 9683 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */ 9684 idx = (idx + 1) & M_UPDBGLARDPTR; 9685 /* 9686 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 9687 * identify the 32-bit portion of the full 312-bit data 9688 */ 9689 if (is_t6(adap)) 9690 while ((idx & 0xf) > 9) 9691 idx = (idx + 1) % M_UPDBGLARDPTR; 9692 } 9693 restart: 9694 if (cfg & F_UPDBGLAEN) { 9695 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9696 cfg & ~F_UPDBGLARDEN); 9697 if (!ret) 9698 ret = r; 9699 } 9700 return ret; 9701 } 9702 9703 /** 9704 * t4_tp_read_la - read TP LA capture buffer 9705 * @adap: the adapter 9706 * @la_buf: where to store the LA data 9707 * @wrptr: the HW write pointer within the capture buffer 9708 * 9709 * Reads the contents of the TP LA buffer with the most recent entry at 9710 * the end of the returned data and with the entry at @wrptr first. 9711 * We leave the LA in the running state we find it in. 9712 */ 9713 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 9714 { 9715 bool last_incomplete; 9716 unsigned int i, cfg, val, idx; 9717 9718 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 9719 if (cfg & F_DBGLAENABLE) /* freeze LA */ 9720 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9721 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 9722 9723 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 9724 idx = G_DBGLAWPTR(val); 9725 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 9726 if (last_incomplete) 9727 idx = (idx + 1) & M_DBGLARPTR; 9728 if (wrptr) 9729 *wrptr = idx; 9730 9731 val &= 0xffff; 9732 val &= ~V_DBGLARPTR(M_DBGLARPTR); 9733 val |= adap->params.tp.la_mask; 9734 9735 for (i = 0; i < TPLA_SIZE; i++) { 9736 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 9737 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 9738 idx = (idx + 1) & M_DBGLARPTR; 9739 } 9740 9741 /* Wipe out last entry if it isn't valid */ 9742 if (last_incomplete) 9743 la_buf[TPLA_SIZE - 1] = ~0ULL; 9744 9745 if (cfg & F_DBGLAENABLE) /* restore running state */ 9746 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9747 cfg | adap->params.tp.la_mask); 9748 } 9749 9750 /* 9751 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 9752 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 9753 * state for more than the Warning Threshold then we'll issue a warning about 9754 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 9755 * appears to be hung every Warning Repeat second till the situation clears. 9756 * If the situation clears, we'll note that as well. 9757 */ 9758 #define SGE_IDMA_WARN_THRESH 1 9759 #define SGE_IDMA_WARN_REPEAT 300 9760 9761 /** 9762 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 9763 * @adapter: the adapter 9764 * @idma: the adapter IDMA Monitor state 9765 * 9766 * Initialize the state of an SGE Ingress DMA Monitor. 9767 */ 9768 void t4_idma_monitor_init(struct adapter *adapter, 9769 struct sge_idma_monitor_state *idma) 9770 { 9771 /* Initialize the state variables for detecting an SGE Ingress DMA 9772 * hang. The SGE has internal counters which count up on each clock 9773 * tick whenever the SGE finds its Ingress DMA State Engines in the 9774 * same state they were on the previous clock tick. The clock used is 9775 * the Core Clock so we have a limit on the maximum "time" they can 9776 * record; typically a very small number of seconds. For instance, 9777 * with a 600MHz Core Clock, we can only count up to a bit more than 9778 * 7s. So we'll synthesize a larger counter in order to not run the 9779 * risk of having the "timers" overflow and give us the flexibility to 9780 * maintain a Hung SGE State Machine of our own which operates across 9781 * a longer time frame. 9782 */ 9783 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 9784 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 9785 } 9786 9787 /** 9788 * t4_idma_monitor - monitor SGE Ingress DMA state 9789 * @adapter: the adapter 9790 * @idma: the adapter IDMA Monitor state 9791 * @hz: number of ticks/second 9792 * @ticks: number of ticks since the last IDMA Monitor call 9793 */ 9794 void t4_idma_monitor(struct adapter *adapter, 9795 struct sge_idma_monitor_state *idma, 9796 int hz, int ticks) 9797 { 9798 int i, idma_same_state_cnt[2]; 9799 9800 /* Read the SGE Debug Ingress DMA Same State Count registers. These 9801 * are counters inside the SGE which count up on each clock when the 9802 * SGE finds its Ingress DMA State Engines in the same states they 9803 * were in the previous clock. The counters will peg out at 9804 * 0xffffffff without wrapping around so once they pass the 1s 9805 * threshold they'll stay above that till the IDMA state changes. 9806 */ 9807 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 9808 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 9809 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9810 9811 for (i = 0; i < 2; i++) { 9812 u32 debug0, debug11; 9813 9814 /* If the Ingress DMA Same State Counter ("timer") is less 9815 * than 1s, then we can reset our synthesized Stall Timer and 9816 * continue. If we have previously emitted warnings about a 9817 * potential stalled Ingress Queue, issue a note indicating 9818 * that the Ingress Queue has resumed forward progress. 9819 */ 9820 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 9821 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 9822 CH_WARN(adapter, "SGE idma%d, queue %u, " 9823 "resumed after %d seconds\n", 9824 i, idma->idma_qid[i], 9825 idma->idma_stalled[i]/hz); 9826 idma->idma_stalled[i] = 0; 9827 continue; 9828 } 9829 9830 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 9831 * domain. The first time we get here it'll be because we 9832 * passed the 1s Threshold; each additional time it'll be 9833 * because the RX Timer Callback is being fired on its regular 9834 * schedule. 9835 * 9836 * If the stall is below our Potential Hung Ingress Queue 9837 * Warning Threshold, continue. 9838 */ 9839 if (idma->idma_stalled[i] == 0) { 9840 idma->idma_stalled[i] = hz; 9841 idma->idma_warn[i] = 0; 9842 } else { 9843 idma->idma_stalled[i] += ticks; 9844 idma->idma_warn[i] -= ticks; 9845 } 9846 9847 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 9848 continue; 9849 9850 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 9851 */ 9852 if (idma->idma_warn[i] > 0) 9853 continue; 9854 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 9855 9856 /* Read and save the SGE IDMA State and Queue ID information. 9857 * We do this every time in case it changes across time ... 9858 * can't be too careful ... 9859 */ 9860 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 9861 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9862 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 9863 9864 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 9865 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9866 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 9867 9868 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 9869 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 9870 i, idma->idma_qid[i], idma->idma_state[i], 9871 idma->idma_stalled[i]/hz, 9872 debug0, debug11); 9873 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 9874 } 9875 } 9876 9877 /** 9878 * t4_read_pace_tbl - read the pace table 9879 * @adap: the adapter 9880 * @pace_vals: holds the returned values 9881 * 9882 * Returns the values of TP's pace table in microseconds. 9883 */ 9884 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 9885 { 9886 unsigned int i, v; 9887 9888 for (i = 0; i < NTX_SCHED; i++) { 9889 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 9890 v = t4_read_reg(adap, A_TP_PACE_TABLE); 9891 pace_vals[i] = dack_ticks_to_usec(adap, v); 9892 } 9893 } 9894 9895 /** 9896 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 9897 * @adap: the adapter 9898 * @sched: the scheduler index 9899 * @kbps: the byte rate in Kbps 9900 * @ipg: the interpacket delay in tenths of nanoseconds 9901 * 9902 * Return the current configuration of a HW Tx scheduler. 9903 */ 9904 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 9905 unsigned int *ipg, bool sleep_ok) 9906 { 9907 unsigned int v, addr, bpt, cpt; 9908 9909 if (kbps) { 9910 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 9911 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9912 if (sched & 1) 9913 v >>= 16; 9914 bpt = (v >> 8) & 0xff; 9915 cpt = v & 0xff; 9916 if (!cpt) 9917 *kbps = 0; /* scheduler disabled */ 9918 else { 9919 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 9920 *kbps = (v * bpt) / 125; 9921 } 9922 } 9923 if (ipg) { 9924 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 9925 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9926 if (sched & 1) 9927 v >>= 16; 9928 v &= 0xffff; 9929 *ipg = (10000 * v) / core_ticks_per_usec(adap); 9930 } 9931 } 9932 9933 /** 9934 * t4_load_cfg - download config file 9935 * @adap: the adapter 9936 * @cfg_data: the cfg text file to write 9937 * @size: text file size 9938 * 9939 * Write the supplied config text file to the card's serial flash. 9940 */ 9941 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 9942 { 9943 int ret, i, n, cfg_addr; 9944 unsigned int addr; 9945 unsigned int flash_cfg_start_sec; 9946 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9947 9948 cfg_addr = t4_flash_cfg_addr(adap); 9949 if (cfg_addr < 0) 9950 return cfg_addr; 9951 9952 addr = cfg_addr; 9953 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9954 9955 if (size > FLASH_CFG_MAX_SIZE) { 9956 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 9957 FLASH_CFG_MAX_SIZE); 9958 return -EFBIG; 9959 } 9960 9961 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 9962 sf_sec_size); 9963 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9964 flash_cfg_start_sec + i - 1); 9965 /* 9966 * If size == 0 then we're simply erasing the FLASH sectors associated 9967 * with the on-adapter Firmware Configuration File. 9968 */ 9969 if (ret || size == 0) 9970 goto out; 9971 9972 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9973 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9974 if ( (size - i) < SF_PAGE_SIZE) 9975 n = size - i; 9976 else 9977 n = SF_PAGE_SIZE; 9978 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 9979 if (ret) 9980 goto out; 9981 9982 addr += SF_PAGE_SIZE; 9983 cfg_data += SF_PAGE_SIZE; 9984 } 9985 9986 out: 9987 if (ret) 9988 CH_ERR(adap, "config file %s failed %d\n", 9989 (size == 0 ? "clear" : "download"), ret); 9990 return ret; 9991 } 9992 9993 /** 9994 * t5_fw_init_extern_mem - initialize the external memory 9995 * @adap: the adapter 9996 * 9997 * Initializes the external memory on T5. 9998 */ 9999 int t5_fw_init_extern_mem(struct adapter *adap) 10000 { 10001 u32 params[1], val[1]; 10002 int ret; 10003 10004 if (!is_t5(adap)) 10005 return 0; 10006 10007 val[0] = 0xff; /* Initialize all MCs */ 10008 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10009 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10010 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10011 FW_CMD_MAX_TIMEOUT); 10012 10013 return ret; 10014 } 10015 10016 /* BIOS boot headers */ 10017 typedef struct pci_expansion_rom_header { 10018 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10019 u8 reserved[22]; /* Reserved per processor Architecture data */ 10020 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10021 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10022 10023 /* Legacy PCI Expansion ROM Header */ 10024 typedef struct legacy_pci_expansion_rom_header { 10025 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10026 u8 size512; /* Current Image Size in units of 512 bytes */ 10027 u8 initentry_point[4]; 10028 u8 cksum; /* Checksum computed on the entire Image */ 10029 u8 reserved[16]; /* Reserved */ 10030 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10031 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10032 10033 /* EFI PCI Expansion ROM Header */ 10034 typedef struct efi_pci_expansion_rom_header { 10035 u8 signature[2]; // ROM signature. The value 0xaa55 10036 u8 initialization_size[2]; /* Units 512. Includes this header */ 10037 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10038 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10039 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10040 u8 compression_type[2]; /* Compression type. */ 10041 /* 10042 * Compression type definition 10043 * 0x0: uncompressed 10044 * 0x1: Compressed 10045 * 0x2-0xFFFF: Reserved 10046 */ 10047 u8 reserved[8]; /* Reserved */ 10048 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10049 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10050 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10051 10052 /* PCI Data Structure Format */ 10053 typedef struct pcir_data_structure { /* PCI Data Structure */ 10054 u8 signature[4]; /* Signature. The string "PCIR" */ 10055 u8 vendor_id[2]; /* Vendor Identification */ 10056 u8 device_id[2]; /* Device Identification */ 10057 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10058 u8 length[2]; /* PCIR Data Structure Length */ 10059 u8 revision; /* PCIR Data Structure Revision */ 10060 u8 class_code[3]; /* Class Code */ 10061 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10062 u8 code_revision[2]; /* Revision Level of Code/Data */ 10063 u8 code_type; /* Code Type. */ 10064 /* 10065 * PCI Expansion ROM Code Types 10066 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10067 * 0x01: Open Firmware standard for PCI. FCODE 10068 * 0x02: Hewlett-Packard PA RISC. HP reserved 10069 * 0x03: EFI Image. EFI 10070 * 0x04-0xFF: Reserved. 10071 */ 10072 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10073 u8 reserved[2]; /* Reserved */ 10074 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10075 10076 /* BOOT constants */ 10077 enum { 10078 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10079 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10080 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10081 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10082 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10083 VENDOR_ID = 0x1425, /* Vendor ID */ 10084 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10085 }; 10086 10087 /* 10088 * modify_device_id - Modifies the device ID of the Boot BIOS image 10089 * @adatper: the device ID to write. 10090 * @boot_data: the boot image to modify. 10091 * 10092 * Write the supplied device ID to the boot BIOS image. 10093 */ 10094 static void modify_device_id(int device_id, u8 *boot_data) 10095 { 10096 legacy_pci_exp_rom_header_t *header; 10097 pcir_data_t *pcir_header; 10098 u32 cur_header = 0; 10099 10100 /* 10101 * Loop through all chained images and change the device ID's 10102 */ 10103 while (1) { 10104 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10105 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10106 le16_to_cpu(*(u16*)header->pcir_offset)]; 10107 10108 /* 10109 * Only modify the Device ID if code type is Legacy or HP. 10110 * 0x00: Okay to modify 10111 * 0x01: FCODE. Do not be modify 10112 * 0x03: Okay to modify 10113 * 0x04-0xFF: Do not modify 10114 */ 10115 if (pcir_header->code_type == 0x00) { 10116 u8 csum = 0; 10117 int i; 10118 10119 /* 10120 * Modify Device ID to match current adatper 10121 */ 10122 *(u16*) pcir_header->device_id = device_id; 10123 10124 /* 10125 * Set checksum temporarily to 0. 10126 * We will recalculate it later. 10127 */ 10128 header->cksum = 0x0; 10129 10130 /* 10131 * Calculate and update checksum 10132 */ 10133 for (i = 0; i < (header->size512 * 512); i++) 10134 csum += (u8)boot_data[cur_header + i]; 10135 10136 /* 10137 * Invert summed value to create the checksum 10138 * Writing new checksum value directly to the boot data 10139 */ 10140 boot_data[cur_header + 7] = -csum; 10141 10142 } else if (pcir_header->code_type == 0x03) { 10143 10144 /* 10145 * Modify Device ID to match current adatper 10146 */ 10147 *(u16*) pcir_header->device_id = device_id; 10148 10149 } 10150 10151 10152 /* 10153 * Check indicator element to identify if this is the last 10154 * image in the ROM. 10155 */ 10156 if (pcir_header->indicator & 0x80) 10157 break; 10158 10159 /* 10160 * Move header pointer up to the next image in the ROM. 10161 */ 10162 cur_header += header->size512 * 512; 10163 } 10164 } 10165 10166 /* 10167 * t4_load_boot - download boot flash 10168 * @adapter: the adapter 10169 * @boot_data: the boot image to write 10170 * @boot_addr: offset in flash to write boot_data 10171 * @size: image size 10172 * 10173 * Write the supplied boot image to the card's serial flash. 10174 * The boot image has the following sections: a 28-byte header and the 10175 * boot image. 10176 */ 10177 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10178 unsigned int boot_addr, unsigned int size) 10179 { 10180 pci_exp_rom_header_t *header; 10181 int pcir_offset ; 10182 pcir_data_t *pcir_header; 10183 int ret, addr; 10184 uint16_t device_id; 10185 unsigned int i; 10186 unsigned int boot_sector = (boot_addr * 1024 ); 10187 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10188 10189 /* 10190 * Make sure the boot image does not encroach on the firmware region 10191 */ 10192 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10193 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10194 return -EFBIG; 10195 } 10196 10197 /* 10198 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10199 * and Boot configuration data sections. These 3 boot sections span 10200 * sectors 0 to 7 in flash and live right before the FW image location. 10201 */ 10202 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10203 sf_sec_size); 10204 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10205 (boot_sector >> 16) + i - 1); 10206 10207 /* 10208 * If size == 0 then we're simply erasing the FLASH sectors associated 10209 * with the on-adapter option ROM file 10210 */ 10211 if (ret || (size == 0)) 10212 goto out; 10213 10214 /* Get boot header */ 10215 header = (pci_exp_rom_header_t *)boot_data; 10216 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10217 /* PCIR Data Structure */ 10218 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10219 10220 /* 10221 * Perform some primitive sanity testing to avoid accidentally 10222 * writing garbage over the boot sectors. We ought to check for 10223 * more but it's not worth it for now ... 10224 */ 10225 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10226 CH_ERR(adap, "boot image too small/large\n"); 10227 return -EFBIG; 10228 } 10229 10230 #ifndef CHELSIO_T4_DIAGS 10231 /* 10232 * Check BOOT ROM header signature 10233 */ 10234 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10235 CH_ERR(adap, "Boot image missing signature\n"); 10236 return -EINVAL; 10237 } 10238 10239 /* 10240 * Check PCI header signature 10241 */ 10242 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10243 CH_ERR(adap, "PCI header missing signature\n"); 10244 return -EINVAL; 10245 } 10246 10247 /* 10248 * Check Vendor ID matches Chelsio ID 10249 */ 10250 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10251 CH_ERR(adap, "Vendor ID missing signature\n"); 10252 return -EINVAL; 10253 } 10254 #endif 10255 10256 /* 10257 * Retrieve adapter's device ID 10258 */ 10259 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10260 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10261 device_id = device_id & 0xf0ff; 10262 10263 /* 10264 * Check PCIE Device ID 10265 */ 10266 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10267 /* 10268 * Change the device ID in the Boot BIOS image to match 10269 * the Device ID of the current adapter. 10270 */ 10271 modify_device_id(device_id, boot_data); 10272 } 10273 10274 /* 10275 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10276 * we finish copying the rest of the boot image. This will ensure 10277 * that the BIOS boot header will only be written if the boot image 10278 * was written in full. 10279 */ 10280 addr = boot_sector; 10281 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10282 addr += SF_PAGE_SIZE; 10283 boot_data += SF_PAGE_SIZE; 10284 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10285 if (ret) 10286 goto out; 10287 } 10288 10289 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10290 (const u8 *)header, 0); 10291 10292 out: 10293 if (ret) 10294 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10295 return ret; 10296 } 10297 10298 /* 10299 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10300 * @adapter: the adapter 10301 * 10302 * Return the address within the flash where the OptionROM Configuration 10303 * is stored, or an error if the device FLASH is too small to contain 10304 * a OptionROM Configuration. 10305 */ 10306 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10307 { 10308 /* 10309 * If the device FLASH isn't large enough to hold a Firmware 10310 * Configuration File, return an error. 10311 */ 10312 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10313 return -ENOSPC; 10314 10315 return FLASH_BOOTCFG_START; 10316 } 10317 10318 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10319 { 10320 int ret, i, n, cfg_addr; 10321 unsigned int addr; 10322 unsigned int flash_cfg_start_sec; 10323 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10324 10325 cfg_addr = t4_flash_bootcfg_addr(adap); 10326 if (cfg_addr < 0) 10327 return cfg_addr; 10328 10329 addr = cfg_addr; 10330 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10331 10332 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10333 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10334 FLASH_BOOTCFG_MAX_SIZE); 10335 return -EFBIG; 10336 } 10337 10338 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10339 sf_sec_size); 10340 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10341 flash_cfg_start_sec + i - 1); 10342 10343 /* 10344 * If size == 0 then we're simply erasing the FLASH sectors associated 10345 * with the on-adapter OptionROM Configuration File. 10346 */ 10347 if (ret || size == 0) 10348 goto out; 10349 10350 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10351 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10352 if ( (size - i) < SF_PAGE_SIZE) 10353 n = size - i; 10354 else 10355 n = SF_PAGE_SIZE; 10356 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10357 if (ret) 10358 goto out; 10359 10360 addr += SF_PAGE_SIZE; 10361 cfg_data += SF_PAGE_SIZE; 10362 } 10363 10364 out: 10365 if (ret) 10366 CH_ERR(adap, "boot config data %s failed %d\n", 10367 (size == 0 ? "clear" : "download"), ret); 10368 return ret; 10369 } 10370 10371 /** 10372 * t4_set_filter_mode - configure the optional components of filter tuples 10373 * @adap: the adapter 10374 * @mode_map: a bitmap selcting which optional filter components to enable 10375 * @sleep_ok: if true we may sleep while awaiting command completion 10376 * 10377 * Sets the filter mode by selecting the optional components to enable 10378 * in filter tuples. Returns 0 on success and a negative error if the 10379 * requested mode needs more bits than are available for optional 10380 * components. 10381 */ 10382 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 10383 bool sleep_ok) 10384 { 10385 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 10386 10387 int i, nbits = 0; 10388 10389 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 10390 if (mode_map & (1 << i)) 10391 nbits += width[i]; 10392 if (nbits > FILTER_OPT_LEN) 10393 return -EINVAL; 10394 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok); 10395 read_filter_mode_and_ingress_config(adap, sleep_ok); 10396 10397 return 0; 10398 } 10399 10400 /** 10401 * t4_clr_port_stats - clear port statistics 10402 * @adap: the adapter 10403 * @idx: the port index 10404 * 10405 * Clear HW statistics for the given port. 10406 */ 10407 void t4_clr_port_stats(struct adapter *adap, int idx) 10408 { 10409 unsigned int i; 10410 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 10411 u32 port_base_addr; 10412 10413 if (is_t4(adap)) 10414 port_base_addr = PORT_BASE(idx); 10415 else 10416 port_base_addr = T5_PORT_BASE(idx); 10417 10418 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 10419 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 10420 t4_write_reg(adap, port_base_addr + i, 0); 10421 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 10422 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 10423 t4_write_reg(adap, port_base_addr + i, 0); 10424 for (i = 0; i < 4; i++) 10425 if (bgmap & (1 << i)) { 10426 t4_write_reg(adap, 10427 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 10428 t4_write_reg(adap, 10429 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 10430 } 10431 } 10432 10433 /** 10434 * t4_i2c_rd - read I2C data from adapter 10435 * @adap: the adapter 10436 * @port: Port number if per-port device; <0 if not 10437 * @devid: per-port device ID or absolute device ID 10438 * @offset: byte offset into device I2C space 10439 * @len: byte length of I2C space data 10440 * @buf: buffer in which to return I2C data 10441 * 10442 * Reads the I2C data from the indicated device and location. 10443 */ 10444 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 10445 int port, unsigned int devid, 10446 unsigned int offset, unsigned int len, 10447 u8 *buf) 10448 { 10449 u32 ldst_addrspace; 10450 struct fw_ldst_cmd ldst; 10451 int ret; 10452 10453 if (port >= 4 || 10454 devid >= 256 || 10455 offset >= 256 || 10456 len > sizeof ldst.u.i2c.data) 10457 return -EINVAL; 10458 10459 memset(&ldst, 0, sizeof ldst); 10460 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 10461 ldst.op_to_addrspace = 10462 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 10463 F_FW_CMD_REQUEST | 10464 F_FW_CMD_READ | 10465 ldst_addrspace); 10466 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 10467 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 10468 ldst.u.i2c.did = devid; 10469 ldst.u.i2c.boffset = offset; 10470 ldst.u.i2c.blen = len; 10471 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 10472 if (!ret) 10473 memcpy(buf, ldst.u.i2c.data, len); 10474 return ret; 10475 } 10476 10477 /** 10478 * t4_i2c_wr - write I2C data to adapter 10479 * @adap: the adapter 10480 * @port: Port number if per-port device; <0 if not 10481 * @devid: per-port device ID or absolute device ID 10482 * @offset: byte offset into device I2C space 10483 * @len: byte length of I2C space data 10484 * @buf: buffer containing new I2C data 10485 * 10486 * Write the I2C data to the indicated device and location. 10487 */ 10488 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 10489 int port, unsigned int devid, 10490 unsigned int offset, unsigned int len, 10491 u8 *buf) 10492 { 10493 u32 ldst_addrspace; 10494 struct fw_ldst_cmd ldst; 10495 10496 if (port >= 4 || 10497 devid >= 256 || 10498 offset >= 256 || 10499 len > sizeof ldst.u.i2c.data) 10500 return -EINVAL; 10501 10502 memset(&ldst, 0, sizeof ldst); 10503 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 10504 ldst.op_to_addrspace = 10505 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 10506 F_FW_CMD_REQUEST | 10507 F_FW_CMD_WRITE | 10508 ldst_addrspace); 10509 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 10510 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 10511 ldst.u.i2c.did = devid; 10512 ldst.u.i2c.boffset = offset; 10513 ldst.u.i2c.blen = len; 10514 memcpy(ldst.u.i2c.data, buf, len); 10515 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 10516 } 10517 10518 /** 10519 * t4_sge_ctxt_rd - read an SGE context through FW 10520 * @adap: the adapter 10521 * @mbox: mailbox to use for the FW command 10522 * @cid: the context id 10523 * @ctype: the context type 10524 * @data: where to store the context data 10525 * 10526 * Issues a FW command through the given mailbox to read an SGE context. 10527 */ 10528 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 10529 enum ctxt_type ctype, u32 *data) 10530 { 10531 int ret; 10532 struct fw_ldst_cmd c; 10533 10534 if (ctype == CTXT_EGRESS) 10535 ret = FW_LDST_ADDRSPC_SGE_EGRC; 10536 else if (ctype == CTXT_INGRESS) 10537 ret = FW_LDST_ADDRSPC_SGE_INGC; 10538 else if (ctype == CTXT_FLM) 10539 ret = FW_LDST_ADDRSPC_SGE_FLMC; 10540 else 10541 ret = FW_LDST_ADDRSPC_SGE_CONMC; 10542 10543 memset(&c, 0, sizeof(c)); 10544 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 10545 F_FW_CMD_REQUEST | F_FW_CMD_READ | 10546 V_FW_LDST_CMD_ADDRSPACE(ret)); 10547 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 10548 c.u.idctxt.physid = cpu_to_be32(cid); 10549 10550 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 10551 if (ret == 0) { 10552 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 10553 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 10554 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 10555 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 10556 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 10557 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 10558 } 10559 return ret; 10560 } 10561 10562 /** 10563 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 10564 * @adap: the adapter 10565 * @cid: the context id 10566 * @ctype: the context type 10567 * @data: where to store the context data 10568 * 10569 * Reads an SGE context directly, bypassing FW. This is only for 10570 * debugging when FW is unavailable. 10571 */ 10572 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 10573 u32 *data) 10574 { 10575 int i, ret; 10576 10577 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 10578 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 10579 if (!ret) 10580 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 10581 *data++ = t4_read_reg(adap, i); 10582 return ret; 10583 } 10584 10585 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 10586 int sleep_ok) 10587 { 10588 struct fw_sched_cmd cmd; 10589 10590 memset(&cmd, 0, sizeof(cmd)); 10591 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10592 F_FW_CMD_REQUEST | 10593 F_FW_CMD_WRITE); 10594 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10595 10596 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 10597 cmd.u.config.type = type; 10598 cmd.u.config.minmaxen = minmaxen; 10599 10600 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10601 NULL, sleep_ok); 10602 } 10603 10604 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 10605 int rateunit, int ratemode, int channel, int cl, 10606 int minrate, int maxrate, int weight, int pktsize, 10607 int burstsize, int sleep_ok) 10608 { 10609 struct fw_sched_cmd cmd; 10610 10611 memset(&cmd, 0, sizeof(cmd)); 10612 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10613 F_FW_CMD_REQUEST | 10614 F_FW_CMD_WRITE); 10615 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10616 10617 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10618 cmd.u.params.type = type; 10619 cmd.u.params.level = level; 10620 cmd.u.params.mode = mode; 10621 cmd.u.params.ch = channel; 10622 cmd.u.params.cl = cl; 10623 cmd.u.params.unit = rateunit; 10624 cmd.u.params.rate = ratemode; 10625 cmd.u.params.min = cpu_to_be32(minrate); 10626 cmd.u.params.max = cpu_to_be32(maxrate); 10627 cmd.u.params.weight = cpu_to_be16(weight); 10628 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10629 cmd.u.params.burstsize = cpu_to_be16(burstsize); 10630 10631 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10632 NULL, sleep_ok); 10633 } 10634 10635 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 10636 unsigned int maxrate, int sleep_ok) 10637 { 10638 struct fw_sched_cmd cmd; 10639 10640 memset(&cmd, 0, sizeof(cmd)); 10641 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10642 F_FW_CMD_REQUEST | 10643 F_FW_CMD_WRITE); 10644 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10645 10646 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10647 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10648 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 10649 cmd.u.params.ch = channel; 10650 cmd.u.params.rate = ratemode; /* REL or ABS */ 10651 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 10652 10653 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10654 NULL, sleep_ok); 10655 } 10656 10657 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 10658 int weight, int sleep_ok) 10659 { 10660 struct fw_sched_cmd cmd; 10661 10662 if (weight < 0 || weight > 100) 10663 return -EINVAL; 10664 10665 memset(&cmd, 0, sizeof(cmd)); 10666 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10667 F_FW_CMD_REQUEST | 10668 F_FW_CMD_WRITE); 10669 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10670 10671 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10672 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10673 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 10674 cmd.u.params.ch = channel; 10675 cmd.u.params.cl = cl; 10676 cmd.u.params.weight = cpu_to_be16(weight); 10677 10678 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10679 NULL, sleep_ok); 10680 } 10681 10682 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 10683 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 10684 { 10685 struct fw_sched_cmd cmd; 10686 10687 memset(&cmd, 0, sizeof(cmd)); 10688 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10689 F_FW_CMD_REQUEST | 10690 F_FW_CMD_WRITE); 10691 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10692 10693 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10694 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10695 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 10696 cmd.u.params.mode = mode; 10697 cmd.u.params.ch = channel; 10698 cmd.u.params.cl = cl; 10699 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 10700 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 10701 cmd.u.params.max = cpu_to_be32(maxrate); 10702 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10703 10704 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10705 NULL, sleep_ok); 10706 } 10707 10708 /* 10709 * t4_config_watchdog - configure (enable/disable) a watchdog timer 10710 * @adapter: the adapter 10711 * @mbox: mailbox to use for the FW command 10712 * @pf: the PF owning the queue 10713 * @vf: the VF owning the queue 10714 * @timeout: watchdog timeout in ms 10715 * @action: watchdog timer / action 10716 * 10717 * There are separate watchdog timers for each possible watchdog 10718 * action. Configure one of the watchdog timers by setting a non-zero 10719 * timeout. Disable a watchdog timer by using a timeout of zero. 10720 */ 10721 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 10722 unsigned int pf, unsigned int vf, 10723 unsigned int timeout, unsigned int action) 10724 { 10725 struct fw_watchdog_cmd wdog; 10726 unsigned int ticks; 10727 10728 /* 10729 * The watchdog command expects a timeout in units of 10ms so we need 10730 * to convert it here (via rounding) and force a minimum of one 10ms 10731 * "tick" if the timeout is non-zero but the conversion results in 0 10732 * ticks. 10733 */ 10734 ticks = (timeout + 5)/10; 10735 if (timeout && !ticks) 10736 ticks = 1; 10737 10738 memset(&wdog, 0, sizeof wdog); 10739 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 10740 F_FW_CMD_REQUEST | 10741 F_FW_CMD_WRITE | 10742 V_FW_PARAMS_CMD_PFN(pf) | 10743 V_FW_PARAMS_CMD_VFN(vf)); 10744 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 10745 wdog.timeout = cpu_to_be32(ticks); 10746 wdog.action = cpu_to_be32(action); 10747 10748 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 10749 } 10750 10751 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 10752 { 10753 struct fw_devlog_cmd devlog_cmd; 10754 int ret; 10755 10756 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10757 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10758 F_FW_CMD_REQUEST | F_FW_CMD_READ); 10759 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10760 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10761 sizeof(devlog_cmd), &devlog_cmd); 10762 if (ret) 10763 return ret; 10764 10765 *level = devlog_cmd.level; 10766 return 0; 10767 } 10768 10769 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 10770 { 10771 struct fw_devlog_cmd devlog_cmd; 10772 10773 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10774 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10775 F_FW_CMD_REQUEST | 10776 F_FW_CMD_WRITE); 10777 devlog_cmd.level = level; 10778 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10779 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10780 sizeof(devlog_cmd), &devlog_cmd); 10781 } 10782