1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) 215 CH_ERR(adap, "Firmware reports adapter error: %s\n", 216 reason[G_PCIE_FW_EVAL(pcie_fw)]); 217 } 218 219 /* 220 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 221 */ 222 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 223 u32 mbox_addr) 224 { 225 for ( ; nflit; nflit--, mbox_addr += 8) 226 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 227 } 228 229 /* 230 * Handle a FW assertion reported in a mailbox. 231 */ 232 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 233 { 234 CH_ALERT(adap, 235 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 236 asrt->u.assert.filename_0_7, 237 be32_to_cpu(asrt->u.assert.line), 238 be32_to_cpu(asrt->u.assert.x), 239 be32_to_cpu(asrt->u.assert.y)); 240 } 241 242 struct port_tx_state { 243 uint64_t rx_pause; 244 uint64_t tx_frames; 245 }; 246 247 static void 248 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 249 { 250 uint32_t rx_pause_reg, tx_frames_reg; 251 252 if (is_t4(sc)) { 253 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 254 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 255 } else { 256 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 257 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 258 } 259 260 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 261 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 262 } 263 264 static void 265 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 266 { 267 int i; 268 269 for_each_port(sc, i) 270 read_tx_state_one(sc, i, &tx_state[i]); 271 } 272 273 static void 274 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 275 { 276 uint32_t port_ctl_reg; 277 uint64_t tx_frames, rx_pause; 278 int i; 279 280 for_each_port(sc, i) { 281 rx_pause = tx_state[i].rx_pause; 282 tx_frames = tx_state[i].tx_frames; 283 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 284 285 if (is_t4(sc)) 286 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 287 else 288 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 289 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 290 rx_pause != tx_state[i].rx_pause && 291 tx_frames == tx_state[i].tx_frames) { 292 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 293 mdelay(1); 294 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 295 } 296 } 297 } 298 299 #define X_CIM_PF_NOACCESS 0xeeeeeeee 300 /** 301 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 302 * @adap: the adapter 303 * @mbox: index of the mailbox to use 304 * @cmd: the command to write 305 * @size: command length in bytes 306 * @rpl: where to optionally store the reply 307 * @sleep_ok: if true we may sleep while awaiting command completion 308 * @timeout: time to wait for command to finish before timing out 309 * (negative implies @sleep_ok=false) 310 * 311 * Sends the given command to FW through the selected mailbox and waits 312 * for the FW to execute the command. If @rpl is not %NULL it is used to 313 * store the FW's reply to the command. The command and its optional 314 * reply are of the same length. Some FW commands like RESET and 315 * INITIALIZE can take a considerable amount of time to execute. 316 * @sleep_ok determines whether we may sleep while awaiting the response. 317 * If sleeping is allowed we use progressive backoff otherwise we spin. 318 * Note that passing in a negative @timeout is an alternate mechanism 319 * for specifying @sleep_ok=false. This is useful when a higher level 320 * interface allows for specification of @timeout but not @sleep_ok ... 321 * 322 * The return value is 0 on success or a negative errno on failure. A 323 * failure can happen either because we are not able to execute the 324 * command or FW executes it but signals an error. In the latter case 325 * the return value is the error code indicated by FW (negated). 326 */ 327 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 328 int size, void *rpl, bool sleep_ok, int timeout) 329 { 330 /* 331 * We delay in small increments at first in an effort to maintain 332 * responsiveness for simple, fast executing commands but then back 333 * off to larger delays to a maximum retry delay. 334 */ 335 static const int delay[] = { 336 1, 1, 3, 5, 10, 10, 20, 50, 100 337 }; 338 u32 v; 339 u64 res; 340 int i, ms, delay_idx, ret, next_tx_check; 341 const __be64 *p = cmd; 342 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 343 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 344 u32 ctl; 345 __be64 cmd_rpl[MBOX_LEN/8]; 346 u32 pcie_fw; 347 struct port_tx_state tx_state[MAX_NPORTS]; 348 349 if (adap->flags & CHK_MBOX_ACCESS) 350 ASSERT_SYNCHRONIZED_OP(adap); 351 352 if ((size & 15) || size > MBOX_LEN) 353 return -EINVAL; 354 355 if (adap->flags & IS_VF) { 356 if (is_t6(adap)) 357 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 358 else 359 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 360 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 361 } 362 363 /* 364 * If we have a negative timeout, that implies that we can't sleep. 365 */ 366 if (timeout < 0) { 367 sleep_ok = false; 368 timeout = -timeout; 369 } 370 371 /* 372 * Attempt to gain access to the mailbox. 373 */ 374 for (i = 0; i < 4; i++) { 375 ctl = t4_read_reg(adap, ctl_reg); 376 v = G_MBOWNER(ctl); 377 if (v != X_MBOWNER_NONE) 378 break; 379 } 380 381 /* 382 * If we were unable to gain access, dequeue ourselves from the 383 * mailbox atomic access list and report the error to our caller. 384 */ 385 if (v != X_MBOWNER_PL) { 386 t4_report_fw_error(adap); 387 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 388 return ret; 389 } 390 391 /* 392 * If we gain ownership of the mailbox and there's a "valid" message 393 * in it, this is likely an asynchronous error message from the 394 * firmware. So we'll report that and then proceed on with attempting 395 * to issue our own command ... which may well fail if the error 396 * presaged the firmware crashing ... 397 */ 398 if (ctl & F_MBMSGVALID) { 399 CH_ERR(adap, "found VALID command in mbox %u: %016llx %016llx " 400 "%016llx %016llx %016llx %016llx %016llx %016llx\n", 401 mbox, (unsigned long long)t4_read_reg64(adap, data_reg), 402 (unsigned long long)t4_read_reg64(adap, data_reg + 8), 403 (unsigned long long)t4_read_reg64(adap, data_reg + 16), 404 (unsigned long long)t4_read_reg64(adap, data_reg + 24), 405 (unsigned long long)t4_read_reg64(adap, data_reg + 32), 406 (unsigned long long)t4_read_reg64(adap, data_reg + 40), 407 (unsigned long long)t4_read_reg64(adap, data_reg + 48), 408 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); 409 } 410 411 /* 412 * Copy in the new mailbox command and send it on its way ... 413 */ 414 for (i = 0; i < size; i += 8, p++) 415 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); 416 417 if (adap->flags & IS_VF) { 418 /* 419 * For the VFs, the Mailbox Data "registers" are 420 * actually backed by T4's "MA" interface rather than 421 * PL Registers (as is the case for the PFs). Because 422 * these are in different coherency domains, the write 423 * to the VF's PL-register-backed Mailbox Control can 424 * race in front of the writes to the MA-backed VF 425 * Mailbox Data "registers". So we need to do a 426 * read-back on at least one byte of the VF Mailbox 427 * Data registers before doing the write to the VF 428 * Mailbox Control register. 429 */ 430 t4_read_reg(adap, data_reg); 431 } 432 433 CH_DUMP_MBOX(adap, mbox, data_reg); 434 435 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 436 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 437 next_tx_check = 1000; 438 delay_idx = 0; 439 ms = delay[0]; 440 441 /* 442 * Loop waiting for the reply; bail out if we time out or the firmware 443 * reports an error. 444 */ 445 pcie_fw = 0; 446 for (i = 0; i < timeout; i += ms) { 447 if (!(adap->flags & IS_VF)) { 448 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 449 if (pcie_fw & F_PCIE_FW_ERR) 450 break; 451 } 452 453 if (i >= next_tx_check) { 454 check_tx_state(adap, &tx_state[0]); 455 next_tx_check = i + 1000; 456 } 457 458 if (sleep_ok) { 459 ms = delay[delay_idx]; /* last element may repeat */ 460 if (delay_idx < ARRAY_SIZE(delay) - 1) 461 delay_idx++; 462 msleep(ms); 463 } else { 464 mdelay(ms); 465 } 466 467 v = t4_read_reg(adap, ctl_reg); 468 if (v == X_CIM_PF_NOACCESS) 469 continue; 470 if (G_MBOWNER(v) == X_MBOWNER_PL) { 471 if (!(v & F_MBMSGVALID)) { 472 t4_write_reg(adap, ctl_reg, 473 V_MBOWNER(X_MBOWNER_NONE)); 474 continue; 475 } 476 477 /* 478 * Retrieve the command reply and release the mailbox. 479 */ 480 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 481 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 482 483 CH_DUMP_MBOX(adap, mbox, data_reg); 484 485 res = be64_to_cpu(cmd_rpl[0]); 486 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 487 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 488 res = V_FW_CMD_RETVAL(EIO); 489 } else if (rpl) 490 memcpy(rpl, cmd_rpl, size); 491 return -G_FW_CMD_RETVAL((int)res); 492 } 493 } 494 495 /* 496 * We timed out waiting for a reply to our mailbox command. Report 497 * the error and also check to see if the firmware reported any 498 * errors ... 499 */ 500 ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; 501 CH_ERR(adap, "command %#x in mailbox %d timed out\n", 502 *(const u8 *)cmd, mbox); 503 504 /* If DUMP_MBOX is set the mbox has already been dumped */ 505 if ((adap->debug_flags & DF_DUMP_MBOX) == 0) { 506 p = cmd; 507 CH_ERR(adap, "mbox: %016llx %016llx %016llx %016llx " 508 "%016llx %016llx %016llx %016llx\n", 509 (unsigned long long)be64_to_cpu(p[0]), 510 (unsigned long long)be64_to_cpu(p[1]), 511 (unsigned long long)be64_to_cpu(p[2]), 512 (unsigned long long)be64_to_cpu(p[3]), 513 (unsigned long long)be64_to_cpu(p[4]), 514 (unsigned long long)be64_to_cpu(p[5]), 515 (unsigned long long)be64_to_cpu(p[6]), 516 (unsigned long long)be64_to_cpu(p[7])); 517 } 518 519 t4_report_fw_error(adap); 520 t4_fatal_err(adap); 521 return ret; 522 } 523 524 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 525 void *rpl, bool sleep_ok) 526 { 527 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 528 sleep_ok, FW_CMD_MAX_TIMEOUT); 529 530 } 531 532 static int t4_edc_err_read(struct adapter *adap, int idx) 533 { 534 u32 edc_ecc_err_addr_reg; 535 u32 edc_bist_status_rdata_reg; 536 537 if (is_t4(adap)) { 538 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 539 return 0; 540 } 541 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 542 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 543 return 0; 544 } 545 546 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 547 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 548 549 CH_WARN(adap, 550 "edc%d err addr 0x%x: 0x%x.\n", 551 idx, edc_ecc_err_addr_reg, 552 t4_read_reg(adap, edc_ecc_err_addr_reg)); 553 CH_WARN(adap, 554 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 555 edc_bist_status_rdata_reg, 556 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 557 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 558 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 559 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 560 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 561 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 562 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 563 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 564 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 565 566 return 0; 567 } 568 569 /** 570 * t4_mc_read - read from MC through backdoor accesses 571 * @adap: the adapter 572 * @idx: which MC to access 573 * @addr: address of first byte requested 574 * @data: 64 bytes of data containing the requested address 575 * @ecc: where to store the corresponding 64-bit ECC word 576 * 577 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 578 * that covers the requested address @addr. If @parity is not %NULL it 579 * is assigned the 64-bit ECC word for the read data. 580 */ 581 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 582 { 583 int i; 584 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 585 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 586 587 if (is_t4(adap)) { 588 mc_bist_cmd_reg = A_MC_BIST_CMD; 589 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 590 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 591 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 592 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 593 } else { 594 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 595 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 596 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 597 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 598 idx); 599 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 600 idx); 601 } 602 603 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 604 return -EBUSY; 605 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 606 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 607 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 608 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 609 F_START_BIST | V_BIST_CMD_GAP(1)); 610 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 611 if (i) 612 return i; 613 614 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 615 616 for (i = 15; i >= 0; i--) 617 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 618 if (ecc) 619 *ecc = t4_read_reg64(adap, MC_DATA(16)); 620 #undef MC_DATA 621 return 0; 622 } 623 624 /** 625 * t4_edc_read - read from EDC through backdoor accesses 626 * @adap: the adapter 627 * @idx: which EDC to access 628 * @addr: address of first byte requested 629 * @data: 64 bytes of data containing the requested address 630 * @ecc: where to store the corresponding 64-bit ECC word 631 * 632 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 633 * that covers the requested address @addr. If @parity is not %NULL it 634 * is assigned the 64-bit ECC word for the read data. 635 */ 636 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 637 { 638 int i; 639 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 640 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 641 642 if (is_t4(adap)) { 643 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 649 idx); 650 } else { 651 /* 652 * These macro are missing in t4_regs.h file. 653 * Added temporarily for testing. 654 */ 655 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 656 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 657 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 658 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 659 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 660 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 661 idx); 662 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 663 idx); 664 #undef EDC_REG_T5 665 #undef EDC_STRIDE_T5 666 } 667 668 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 669 return -EBUSY; 670 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 671 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 672 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 673 t4_write_reg(adap, edc_bist_cmd_reg, 674 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 675 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 676 if (i) 677 return i; 678 679 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 680 681 for (i = 15; i >= 0; i--) 682 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 683 if (ecc) 684 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 685 #undef EDC_DATA 686 return 0; 687 } 688 689 /** 690 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 691 * @adap: the adapter 692 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 693 * @addr: address within indicated memory type 694 * @len: amount of memory to read 695 * @buf: host memory buffer 696 * 697 * Reads an [almost] arbitrary memory region in the firmware: the 698 * firmware memory address, length and host buffer must be aligned on 699 * 32-bit boudaries. The memory is returned as a raw byte sequence from 700 * the firmware's memory. If this memory contains data structures which 701 * contain multi-byte integers, it's the callers responsibility to 702 * perform appropriate byte order conversions. 703 */ 704 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 705 __be32 *buf) 706 { 707 u32 pos, start, end, offset; 708 int ret; 709 710 /* 711 * Argument sanity checks ... 712 */ 713 if ((addr & 0x3) || (len & 0x3)) 714 return -EINVAL; 715 716 /* 717 * The underlaying EDC/MC read routines read 64 bytes at a time so we 718 * need to round down the start and round up the end. We'll start 719 * copying out of the first line at (addr - start) a word at a time. 720 */ 721 start = rounddown2(addr, 64); 722 end = roundup2(addr + len, 64); 723 offset = (addr - start)/sizeof(__be32); 724 725 for (pos = start; pos < end; pos += 64, offset = 0) { 726 __be32 data[16]; 727 728 /* 729 * Read the chip's memory block and bail if there's an error. 730 */ 731 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 732 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 733 else 734 ret = t4_edc_read(adap, mtype, pos, data, NULL); 735 if (ret) 736 return ret; 737 738 /* 739 * Copy the data into the caller's memory buffer. 740 */ 741 while (offset < 16 && len > 0) { 742 *buf++ = data[offset++]; 743 len -= sizeof(__be32); 744 } 745 } 746 747 return 0; 748 } 749 750 /* 751 * Return the specified PCI-E Configuration Space register from our Physical 752 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 753 * since we prefer to let the firmware own all of these registers, but if that 754 * fails we go for it directly ourselves. 755 */ 756 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 757 { 758 759 /* 760 * If fw_attach != 0, construct and send the Firmware LDST Command to 761 * retrieve the specified PCI-E Configuration Space register. 762 */ 763 if (drv_fw_attach != 0) { 764 struct fw_ldst_cmd ldst_cmd; 765 int ret; 766 767 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 768 ldst_cmd.op_to_addrspace = 769 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 770 F_FW_CMD_REQUEST | 771 F_FW_CMD_READ | 772 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 773 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 774 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 775 ldst_cmd.u.pcie.ctrl_to_fn = 776 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 777 ldst_cmd.u.pcie.r = reg; 778 779 /* 780 * If the LDST Command succeeds, return the result, otherwise 781 * fall through to reading it directly ourselves ... 782 */ 783 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 784 &ldst_cmd); 785 if (ret == 0) 786 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 787 788 CH_WARN(adap, "Firmware failed to return " 789 "Configuration Space register %d, err = %d\n", 790 reg, -ret); 791 } 792 793 /* 794 * Read the desired Configuration Space register via the PCI-E 795 * Backdoor mechanism. 796 */ 797 return t4_hw_pci_read_cfg4(adap, reg); 798 } 799 800 /** 801 * t4_get_regs_len - return the size of the chips register set 802 * @adapter: the adapter 803 * 804 * Returns the size of the chip's BAR0 register space. 805 */ 806 unsigned int t4_get_regs_len(struct adapter *adapter) 807 { 808 unsigned int chip_version = chip_id(adapter); 809 810 switch (chip_version) { 811 case CHELSIO_T4: 812 if (adapter->flags & IS_VF) 813 return FW_T4VF_REGMAP_SIZE; 814 return T4_REGMAP_SIZE; 815 816 case CHELSIO_T5: 817 case CHELSIO_T6: 818 if (adapter->flags & IS_VF) 819 return FW_T4VF_REGMAP_SIZE; 820 return T5_REGMAP_SIZE; 821 } 822 823 CH_ERR(adapter, 824 "Unsupported chip version %d\n", chip_version); 825 return 0; 826 } 827 828 /** 829 * t4_get_regs - read chip registers into provided buffer 830 * @adap: the adapter 831 * @buf: register buffer 832 * @buf_size: size (in bytes) of register buffer 833 * 834 * If the provided register buffer isn't large enough for the chip's 835 * full register range, the register dump will be truncated to the 836 * register buffer's size. 837 */ 838 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 839 { 840 static const unsigned int t4_reg_ranges[] = { 841 0x1008, 0x1108, 842 0x1180, 0x1184, 843 0x1190, 0x1194, 844 0x11a0, 0x11a4, 845 0x11b0, 0x11b4, 846 0x11fc, 0x123c, 847 0x1300, 0x173c, 848 0x1800, 0x18fc, 849 0x3000, 0x30d8, 850 0x30e0, 0x30e4, 851 0x30ec, 0x5910, 852 0x5920, 0x5924, 853 0x5960, 0x5960, 854 0x5968, 0x5968, 855 0x5970, 0x5970, 856 0x5978, 0x5978, 857 0x5980, 0x5980, 858 0x5988, 0x5988, 859 0x5990, 0x5990, 860 0x5998, 0x5998, 861 0x59a0, 0x59d4, 862 0x5a00, 0x5ae0, 863 0x5ae8, 0x5ae8, 864 0x5af0, 0x5af0, 865 0x5af8, 0x5af8, 866 0x6000, 0x6098, 867 0x6100, 0x6150, 868 0x6200, 0x6208, 869 0x6240, 0x6248, 870 0x6280, 0x62b0, 871 0x62c0, 0x6338, 872 0x6370, 0x638c, 873 0x6400, 0x643c, 874 0x6500, 0x6524, 875 0x6a00, 0x6a04, 876 0x6a14, 0x6a38, 877 0x6a60, 0x6a70, 878 0x6a78, 0x6a78, 879 0x6b00, 0x6b0c, 880 0x6b1c, 0x6b84, 881 0x6bf0, 0x6bf8, 882 0x6c00, 0x6c0c, 883 0x6c1c, 0x6c84, 884 0x6cf0, 0x6cf8, 885 0x6d00, 0x6d0c, 886 0x6d1c, 0x6d84, 887 0x6df0, 0x6df8, 888 0x6e00, 0x6e0c, 889 0x6e1c, 0x6e84, 890 0x6ef0, 0x6ef8, 891 0x6f00, 0x6f0c, 892 0x6f1c, 0x6f84, 893 0x6ff0, 0x6ff8, 894 0x7000, 0x700c, 895 0x701c, 0x7084, 896 0x70f0, 0x70f8, 897 0x7100, 0x710c, 898 0x711c, 0x7184, 899 0x71f0, 0x71f8, 900 0x7200, 0x720c, 901 0x721c, 0x7284, 902 0x72f0, 0x72f8, 903 0x7300, 0x730c, 904 0x731c, 0x7384, 905 0x73f0, 0x73f8, 906 0x7400, 0x7450, 907 0x7500, 0x7530, 908 0x7600, 0x760c, 909 0x7614, 0x761c, 910 0x7680, 0x76cc, 911 0x7700, 0x7798, 912 0x77c0, 0x77fc, 913 0x7900, 0x79fc, 914 0x7b00, 0x7b58, 915 0x7b60, 0x7b84, 916 0x7b8c, 0x7c38, 917 0x7d00, 0x7d38, 918 0x7d40, 0x7d80, 919 0x7d8c, 0x7ddc, 920 0x7de4, 0x7e04, 921 0x7e10, 0x7e1c, 922 0x7e24, 0x7e38, 923 0x7e40, 0x7e44, 924 0x7e4c, 0x7e78, 925 0x7e80, 0x7ea4, 926 0x7eac, 0x7edc, 927 0x7ee8, 0x7efc, 928 0x8dc0, 0x8e04, 929 0x8e10, 0x8e1c, 930 0x8e30, 0x8e78, 931 0x8ea0, 0x8eb8, 932 0x8ec0, 0x8f6c, 933 0x8fc0, 0x9008, 934 0x9010, 0x9058, 935 0x9060, 0x9060, 936 0x9068, 0x9074, 937 0x90fc, 0x90fc, 938 0x9400, 0x9408, 939 0x9410, 0x9458, 940 0x9600, 0x9600, 941 0x9608, 0x9638, 942 0x9640, 0x96bc, 943 0x9800, 0x9808, 944 0x9820, 0x983c, 945 0x9850, 0x9864, 946 0x9c00, 0x9c6c, 947 0x9c80, 0x9cec, 948 0x9d00, 0x9d6c, 949 0x9d80, 0x9dec, 950 0x9e00, 0x9e6c, 951 0x9e80, 0x9eec, 952 0x9f00, 0x9f6c, 953 0x9f80, 0x9fec, 954 0xd004, 0xd004, 955 0xd010, 0xd03c, 956 0xdfc0, 0xdfe0, 957 0xe000, 0xea7c, 958 0xf000, 0x11110, 959 0x11118, 0x11190, 960 0x19040, 0x1906c, 961 0x19078, 0x19080, 962 0x1908c, 0x190e4, 963 0x190f0, 0x190f8, 964 0x19100, 0x19110, 965 0x19120, 0x19124, 966 0x19150, 0x19194, 967 0x1919c, 0x191b0, 968 0x191d0, 0x191e8, 969 0x19238, 0x1924c, 970 0x193f8, 0x1943c, 971 0x1944c, 0x19474, 972 0x19490, 0x194e0, 973 0x194f0, 0x194f8, 974 0x19800, 0x19c08, 975 0x19c10, 0x19c90, 976 0x19ca0, 0x19ce4, 977 0x19cf0, 0x19d40, 978 0x19d50, 0x19d94, 979 0x19da0, 0x19de8, 980 0x19df0, 0x19e40, 981 0x19e50, 0x19e90, 982 0x19ea0, 0x19f4c, 983 0x1a000, 0x1a004, 984 0x1a010, 0x1a06c, 985 0x1a0b0, 0x1a0e4, 986 0x1a0ec, 0x1a0f4, 987 0x1a100, 0x1a108, 988 0x1a114, 0x1a120, 989 0x1a128, 0x1a130, 990 0x1a138, 0x1a138, 991 0x1a190, 0x1a1c4, 992 0x1a1fc, 0x1a1fc, 993 0x1e040, 0x1e04c, 994 0x1e284, 0x1e28c, 995 0x1e2c0, 0x1e2c0, 996 0x1e2e0, 0x1e2e0, 997 0x1e300, 0x1e384, 998 0x1e3c0, 0x1e3c8, 999 0x1e440, 0x1e44c, 1000 0x1e684, 0x1e68c, 1001 0x1e6c0, 0x1e6c0, 1002 0x1e6e0, 0x1e6e0, 1003 0x1e700, 0x1e784, 1004 0x1e7c0, 0x1e7c8, 1005 0x1e840, 0x1e84c, 1006 0x1ea84, 0x1ea8c, 1007 0x1eac0, 0x1eac0, 1008 0x1eae0, 0x1eae0, 1009 0x1eb00, 0x1eb84, 1010 0x1ebc0, 0x1ebc8, 1011 0x1ec40, 0x1ec4c, 1012 0x1ee84, 0x1ee8c, 1013 0x1eec0, 0x1eec0, 1014 0x1eee0, 0x1eee0, 1015 0x1ef00, 0x1ef84, 1016 0x1efc0, 0x1efc8, 1017 0x1f040, 0x1f04c, 1018 0x1f284, 0x1f28c, 1019 0x1f2c0, 0x1f2c0, 1020 0x1f2e0, 0x1f2e0, 1021 0x1f300, 0x1f384, 1022 0x1f3c0, 0x1f3c8, 1023 0x1f440, 0x1f44c, 1024 0x1f684, 0x1f68c, 1025 0x1f6c0, 0x1f6c0, 1026 0x1f6e0, 0x1f6e0, 1027 0x1f700, 0x1f784, 1028 0x1f7c0, 0x1f7c8, 1029 0x1f840, 0x1f84c, 1030 0x1fa84, 0x1fa8c, 1031 0x1fac0, 0x1fac0, 1032 0x1fae0, 0x1fae0, 1033 0x1fb00, 0x1fb84, 1034 0x1fbc0, 0x1fbc8, 1035 0x1fc40, 0x1fc4c, 1036 0x1fe84, 0x1fe8c, 1037 0x1fec0, 0x1fec0, 1038 0x1fee0, 0x1fee0, 1039 0x1ff00, 0x1ff84, 1040 0x1ffc0, 0x1ffc8, 1041 0x20000, 0x2002c, 1042 0x20100, 0x2013c, 1043 0x20190, 0x201a0, 1044 0x201a8, 0x201b8, 1045 0x201c4, 0x201c8, 1046 0x20200, 0x20318, 1047 0x20400, 0x204b4, 1048 0x204c0, 0x20528, 1049 0x20540, 0x20614, 1050 0x21000, 0x21040, 1051 0x2104c, 0x21060, 1052 0x210c0, 0x210ec, 1053 0x21200, 0x21268, 1054 0x21270, 0x21284, 1055 0x212fc, 0x21388, 1056 0x21400, 0x21404, 1057 0x21500, 0x21500, 1058 0x21510, 0x21518, 1059 0x2152c, 0x21530, 1060 0x2153c, 0x2153c, 1061 0x21550, 0x21554, 1062 0x21600, 0x21600, 1063 0x21608, 0x2161c, 1064 0x21624, 0x21628, 1065 0x21630, 0x21634, 1066 0x2163c, 0x2163c, 1067 0x21700, 0x2171c, 1068 0x21780, 0x2178c, 1069 0x21800, 0x21818, 1070 0x21820, 0x21828, 1071 0x21830, 0x21848, 1072 0x21850, 0x21854, 1073 0x21860, 0x21868, 1074 0x21870, 0x21870, 1075 0x21878, 0x21898, 1076 0x218a0, 0x218a8, 1077 0x218b0, 0x218c8, 1078 0x218d0, 0x218d4, 1079 0x218e0, 0x218e8, 1080 0x218f0, 0x218f0, 1081 0x218f8, 0x21a18, 1082 0x21a20, 0x21a28, 1083 0x21a30, 0x21a48, 1084 0x21a50, 0x21a54, 1085 0x21a60, 0x21a68, 1086 0x21a70, 0x21a70, 1087 0x21a78, 0x21a98, 1088 0x21aa0, 0x21aa8, 1089 0x21ab0, 0x21ac8, 1090 0x21ad0, 0x21ad4, 1091 0x21ae0, 0x21ae8, 1092 0x21af0, 0x21af0, 1093 0x21af8, 0x21c18, 1094 0x21c20, 0x21c20, 1095 0x21c28, 0x21c30, 1096 0x21c38, 0x21c38, 1097 0x21c80, 0x21c98, 1098 0x21ca0, 0x21ca8, 1099 0x21cb0, 0x21cc8, 1100 0x21cd0, 0x21cd4, 1101 0x21ce0, 0x21ce8, 1102 0x21cf0, 0x21cf0, 1103 0x21cf8, 0x21d7c, 1104 0x21e00, 0x21e04, 1105 0x22000, 0x2202c, 1106 0x22100, 0x2213c, 1107 0x22190, 0x221a0, 1108 0x221a8, 0x221b8, 1109 0x221c4, 0x221c8, 1110 0x22200, 0x22318, 1111 0x22400, 0x224b4, 1112 0x224c0, 0x22528, 1113 0x22540, 0x22614, 1114 0x23000, 0x23040, 1115 0x2304c, 0x23060, 1116 0x230c0, 0x230ec, 1117 0x23200, 0x23268, 1118 0x23270, 0x23284, 1119 0x232fc, 0x23388, 1120 0x23400, 0x23404, 1121 0x23500, 0x23500, 1122 0x23510, 0x23518, 1123 0x2352c, 0x23530, 1124 0x2353c, 0x2353c, 1125 0x23550, 0x23554, 1126 0x23600, 0x23600, 1127 0x23608, 0x2361c, 1128 0x23624, 0x23628, 1129 0x23630, 0x23634, 1130 0x2363c, 0x2363c, 1131 0x23700, 0x2371c, 1132 0x23780, 0x2378c, 1133 0x23800, 0x23818, 1134 0x23820, 0x23828, 1135 0x23830, 0x23848, 1136 0x23850, 0x23854, 1137 0x23860, 0x23868, 1138 0x23870, 0x23870, 1139 0x23878, 0x23898, 1140 0x238a0, 0x238a8, 1141 0x238b0, 0x238c8, 1142 0x238d0, 0x238d4, 1143 0x238e0, 0x238e8, 1144 0x238f0, 0x238f0, 1145 0x238f8, 0x23a18, 1146 0x23a20, 0x23a28, 1147 0x23a30, 0x23a48, 1148 0x23a50, 0x23a54, 1149 0x23a60, 0x23a68, 1150 0x23a70, 0x23a70, 1151 0x23a78, 0x23a98, 1152 0x23aa0, 0x23aa8, 1153 0x23ab0, 0x23ac8, 1154 0x23ad0, 0x23ad4, 1155 0x23ae0, 0x23ae8, 1156 0x23af0, 0x23af0, 1157 0x23af8, 0x23c18, 1158 0x23c20, 0x23c20, 1159 0x23c28, 0x23c30, 1160 0x23c38, 0x23c38, 1161 0x23c80, 0x23c98, 1162 0x23ca0, 0x23ca8, 1163 0x23cb0, 0x23cc8, 1164 0x23cd0, 0x23cd4, 1165 0x23ce0, 0x23ce8, 1166 0x23cf0, 0x23cf0, 1167 0x23cf8, 0x23d7c, 1168 0x23e00, 0x23e04, 1169 0x24000, 0x2402c, 1170 0x24100, 0x2413c, 1171 0x24190, 0x241a0, 1172 0x241a8, 0x241b8, 1173 0x241c4, 0x241c8, 1174 0x24200, 0x24318, 1175 0x24400, 0x244b4, 1176 0x244c0, 0x24528, 1177 0x24540, 0x24614, 1178 0x25000, 0x25040, 1179 0x2504c, 0x25060, 1180 0x250c0, 0x250ec, 1181 0x25200, 0x25268, 1182 0x25270, 0x25284, 1183 0x252fc, 0x25388, 1184 0x25400, 0x25404, 1185 0x25500, 0x25500, 1186 0x25510, 0x25518, 1187 0x2552c, 0x25530, 1188 0x2553c, 0x2553c, 1189 0x25550, 0x25554, 1190 0x25600, 0x25600, 1191 0x25608, 0x2561c, 1192 0x25624, 0x25628, 1193 0x25630, 0x25634, 1194 0x2563c, 0x2563c, 1195 0x25700, 0x2571c, 1196 0x25780, 0x2578c, 1197 0x25800, 0x25818, 1198 0x25820, 0x25828, 1199 0x25830, 0x25848, 1200 0x25850, 0x25854, 1201 0x25860, 0x25868, 1202 0x25870, 0x25870, 1203 0x25878, 0x25898, 1204 0x258a0, 0x258a8, 1205 0x258b0, 0x258c8, 1206 0x258d0, 0x258d4, 1207 0x258e0, 0x258e8, 1208 0x258f0, 0x258f0, 1209 0x258f8, 0x25a18, 1210 0x25a20, 0x25a28, 1211 0x25a30, 0x25a48, 1212 0x25a50, 0x25a54, 1213 0x25a60, 0x25a68, 1214 0x25a70, 0x25a70, 1215 0x25a78, 0x25a98, 1216 0x25aa0, 0x25aa8, 1217 0x25ab0, 0x25ac8, 1218 0x25ad0, 0x25ad4, 1219 0x25ae0, 0x25ae8, 1220 0x25af0, 0x25af0, 1221 0x25af8, 0x25c18, 1222 0x25c20, 0x25c20, 1223 0x25c28, 0x25c30, 1224 0x25c38, 0x25c38, 1225 0x25c80, 0x25c98, 1226 0x25ca0, 0x25ca8, 1227 0x25cb0, 0x25cc8, 1228 0x25cd0, 0x25cd4, 1229 0x25ce0, 0x25ce8, 1230 0x25cf0, 0x25cf0, 1231 0x25cf8, 0x25d7c, 1232 0x25e00, 0x25e04, 1233 0x26000, 0x2602c, 1234 0x26100, 0x2613c, 1235 0x26190, 0x261a0, 1236 0x261a8, 0x261b8, 1237 0x261c4, 0x261c8, 1238 0x26200, 0x26318, 1239 0x26400, 0x264b4, 1240 0x264c0, 0x26528, 1241 0x26540, 0x26614, 1242 0x27000, 0x27040, 1243 0x2704c, 0x27060, 1244 0x270c0, 0x270ec, 1245 0x27200, 0x27268, 1246 0x27270, 0x27284, 1247 0x272fc, 0x27388, 1248 0x27400, 0x27404, 1249 0x27500, 0x27500, 1250 0x27510, 0x27518, 1251 0x2752c, 0x27530, 1252 0x2753c, 0x2753c, 1253 0x27550, 0x27554, 1254 0x27600, 0x27600, 1255 0x27608, 0x2761c, 1256 0x27624, 0x27628, 1257 0x27630, 0x27634, 1258 0x2763c, 0x2763c, 1259 0x27700, 0x2771c, 1260 0x27780, 0x2778c, 1261 0x27800, 0x27818, 1262 0x27820, 0x27828, 1263 0x27830, 0x27848, 1264 0x27850, 0x27854, 1265 0x27860, 0x27868, 1266 0x27870, 0x27870, 1267 0x27878, 0x27898, 1268 0x278a0, 0x278a8, 1269 0x278b0, 0x278c8, 1270 0x278d0, 0x278d4, 1271 0x278e0, 0x278e8, 1272 0x278f0, 0x278f0, 1273 0x278f8, 0x27a18, 1274 0x27a20, 0x27a28, 1275 0x27a30, 0x27a48, 1276 0x27a50, 0x27a54, 1277 0x27a60, 0x27a68, 1278 0x27a70, 0x27a70, 1279 0x27a78, 0x27a98, 1280 0x27aa0, 0x27aa8, 1281 0x27ab0, 0x27ac8, 1282 0x27ad0, 0x27ad4, 1283 0x27ae0, 0x27ae8, 1284 0x27af0, 0x27af0, 1285 0x27af8, 0x27c18, 1286 0x27c20, 0x27c20, 1287 0x27c28, 0x27c30, 1288 0x27c38, 0x27c38, 1289 0x27c80, 0x27c98, 1290 0x27ca0, 0x27ca8, 1291 0x27cb0, 0x27cc8, 1292 0x27cd0, 0x27cd4, 1293 0x27ce0, 0x27ce8, 1294 0x27cf0, 0x27cf0, 1295 0x27cf8, 0x27d7c, 1296 0x27e00, 0x27e04, 1297 }; 1298 1299 static const unsigned int t4vf_reg_ranges[] = { 1300 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1301 VF_MPS_REG(A_MPS_VF_CTL), 1302 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1303 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1304 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1305 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1306 FW_T4VF_MBDATA_BASE_ADDR, 1307 FW_T4VF_MBDATA_BASE_ADDR + 1308 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1309 }; 1310 1311 static const unsigned int t5_reg_ranges[] = { 1312 0x1008, 0x10c0, 1313 0x10cc, 0x10f8, 1314 0x1100, 0x1100, 1315 0x110c, 0x1148, 1316 0x1180, 0x1184, 1317 0x1190, 0x1194, 1318 0x11a0, 0x11a4, 1319 0x11b0, 0x11b4, 1320 0x11fc, 0x123c, 1321 0x1280, 0x173c, 1322 0x1800, 0x18fc, 1323 0x3000, 0x3028, 1324 0x3060, 0x30b0, 1325 0x30b8, 0x30d8, 1326 0x30e0, 0x30fc, 1327 0x3140, 0x357c, 1328 0x35a8, 0x35cc, 1329 0x35ec, 0x35ec, 1330 0x3600, 0x5624, 1331 0x56cc, 0x56ec, 1332 0x56f4, 0x5720, 1333 0x5728, 0x575c, 1334 0x580c, 0x5814, 1335 0x5890, 0x589c, 1336 0x58a4, 0x58ac, 1337 0x58b8, 0x58bc, 1338 0x5940, 0x59c8, 1339 0x59d0, 0x59dc, 1340 0x59fc, 0x5a18, 1341 0x5a60, 0x5a70, 1342 0x5a80, 0x5a9c, 1343 0x5b94, 0x5bfc, 1344 0x6000, 0x6020, 1345 0x6028, 0x6040, 1346 0x6058, 0x609c, 1347 0x60a8, 0x614c, 1348 0x7700, 0x7798, 1349 0x77c0, 0x78fc, 1350 0x7b00, 0x7b58, 1351 0x7b60, 0x7b84, 1352 0x7b8c, 0x7c54, 1353 0x7d00, 0x7d38, 1354 0x7d40, 0x7d80, 1355 0x7d8c, 0x7ddc, 1356 0x7de4, 0x7e04, 1357 0x7e10, 0x7e1c, 1358 0x7e24, 0x7e38, 1359 0x7e40, 0x7e44, 1360 0x7e4c, 0x7e78, 1361 0x7e80, 0x7edc, 1362 0x7ee8, 0x7efc, 1363 0x8dc0, 0x8de0, 1364 0x8df8, 0x8e04, 1365 0x8e10, 0x8e84, 1366 0x8ea0, 0x8f84, 1367 0x8fc0, 0x9058, 1368 0x9060, 0x9060, 1369 0x9068, 0x90f8, 1370 0x9400, 0x9408, 1371 0x9410, 0x9470, 1372 0x9600, 0x9600, 1373 0x9608, 0x9638, 1374 0x9640, 0x96f4, 1375 0x9800, 0x9808, 1376 0x9820, 0x983c, 1377 0x9850, 0x9864, 1378 0x9c00, 0x9c6c, 1379 0x9c80, 0x9cec, 1380 0x9d00, 0x9d6c, 1381 0x9d80, 0x9dec, 1382 0x9e00, 0x9e6c, 1383 0x9e80, 0x9eec, 1384 0x9f00, 0x9f6c, 1385 0x9f80, 0xa020, 1386 0xd004, 0xd004, 1387 0xd010, 0xd03c, 1388 0xdfc0, 0xdfe0, 1389 0xe000, 0x1106c, 1390 0x11074, 0x11088, 1391 0x1109c, 0x1117c, 1392 0x11190, 0x11204, 1393 0x19040, 0x1906c, 1394 0x19078, 0x19080, 1395 0x1908c, 0x190e8, 1396 0x190f0, 0x190f8, 1397 0x19100, 0x19110, 1398 0x19120, 0x19124, 1399 0x19150, 0x19194, 1400 0x1919c, 0x191b0, 1401 0x191d0, 0x191e8, 1402 0x19238, 0x19290, 1403 0x193f8, 0x19428, 1404 0x19430, 0x19444, 1405 0x1944c, 0x1946c, 1406 0x19474, 0x19474, 1407 0x19490, 0x194cc, 1408 0x194f0, 0x194f8, 1409 0x19c00, 0x19c08, 1410 0x19c10, 0x19c60, 1411 0x19c94, 0x19ce4, 1412 0x19cf0, 0x19d40, 1413 0x19d50, 0x19d94, 1414 0x19da0, 0x19de8, 1415 0x19df0, 0x19e10, 1416 0x19e50, 0x19e90, 1417 0x19ea0, 0x19f24, 1418 0x19f34, 0x19f34, 1419 0x19f40, 0x19f50, 1420 0x19f90, 0x19fb4, 1421 0x19fc4, 0x19fe4, 1422 0x1a000, 0x1a004, 1423 0x1a010, 0x1a06c, 1424 0x1a0b0, 0x1a0e4, 1425 0x1a0ec, 0x1a0f8, 1426 0x1a100, 0x1a108, 1427 0x1a114, 0x1a120, 1428 0x1a128, 0x1a130, 1429 0x1a138, 0x1a138, 1430 0x1a190, 0x1a1c4, 1431 0x1a1fc, 0x1a1fc, 1432 0x1e008, 0x1e00c, 1433 0x1e040, 0x1e044, 1434 0x1e04c, 0x1e04c, 1435 0x1e284, 0x1e290, 1436 0x1e2c0, 0x1e2c0, 1437 0x1e2e0, 0x1e2e0, 1438 0x1e300, 0x1e384, 1439 0x1e3c0, 0x1e3c8, 1440 0x1e408, 0x1e40c, 1441 0x1e440, 0x1e444, 1442 0x1e44c, 0x1e44c, 1443 0x1e684, 0x1e690, 1444 0x1e6c0, 0x1e6c0, 1445 0x1e6e0, 0x1e6e0, 1446 0x1e700, 0x1e784, 1447 0x1e7c0, 0x1e7c8, 1448 0x1e808, 0x1e80c, 1449 0x1e840, 0x1e844, 1450 0x1e84c, 0x1e84c, 1451 0x1ea84, 0x1ea90, 1452 0x1eac0, 0x1eac0, 1453 0x1eae0, 0x1eae0, 1454 0x1eb00, 0x1eb84, 1455 0x1ebc0, 0x1ebc8, 1456 0x1ec08, 0x1ec0c, 1457 0x1ec40, 0x1ec44, 1458 0x1ec4c, 0x1ec4c, 1459 0x1ee84, 0x1ee90, 1460 0x1eec0, 0x1eec0, 1461 0x1eee0, 0x1eee0, 1462 0x1ef00, 0x1ef84, 1463 0x1efc0, 0x1efc8, 1464 0x1f008, 0x1f00c, 1465 0x1f040, 0x1f044, 1466 0x1f04c, 0x1f04c, 1467 0x1f284, 0x1f290, 1468 0x1f2c0, 0x1f2c0, 1469 0x1f2e0, 0x1f2e0, 1470 0x1f300, 0x1f384, 1471 0x1f3c0, 0x1f3c8, 1472 0x1f408, 0x1f40c, 1473 0x1f440, 0x1f444, 1474 0x1f44c, 0x1f44c, 1475 0x1f684, 0x1f690, 1476 0x1f6c0, 0x1f6c0, 1477 0x1f6e0, 0x1f6e0, 1478 0x1f700, 0x1f784, 1479 0x1f7c0, 0x1f7c8, 1480 0x1f808, 0x1f80c, 1481 0x1f840, 0x1f844, 1482 0x1f84c, 0x1f84c, 1483 0x1fa84, 0x1fa90, 1484 0x1fac0, 0x1fac0, 1485 0x1fae0, 0x1fae0, 1486 0x1fb00, 0x1fb84, 1487 0x1fbc0, 0x1fbc8, 1488 0x1fc08, 0x1fc0c, 1489 0x1fc40, 0x1fc44, 1490 0x1fc4c, 0x1fc4c, 1491 0x1fe84, 0x1fe90, 1492 0x1fec0, 0x1fec0, 1493 0x1fee0, 0x1fee0, 1494 0x1ff00, 0x1ff84, 1495 0x1ffc0, 0x1ffc8, 1496 0x30000, 0x30030, 1497 0x30100, 0x30144, 1498 0x30190, 0x301a0, 1499 0x301a8, 0x301b8, 1500 0x301c4, 0x301c8, 1501 0x301d0, 0x301d0, 1502 0x30200, 0x30318, 1503 0x30400, 0x304b4, 1504 0x304c0, 0x3052c, 1505 0x30540, 0x3061c, 1506 0x30800, 0x30828, 1507 0x30834, 0x30834, 1508 0x308c0, 0x30908, 1509 0x30910, 0x309ac, 1510 0x30a00, 0x30a14, 1511 0x30a1c, 0x30a2c, 1512 0x30a44, 0x30a50, 1513 0x30a74, 0x30a74, 1514 0x30a7c, 0x30afc, 1515 0x30b08, 0x30c24, 1516 0x30d00, 0x30d00, 1517 0x30d08, 0x30d14, 1518 0x30d1c, 0x30d20, 1519 0x30d3c, 0x30d3c, 1520 0x30d48, 0x30d50, 1521 0x31200, 0x3120c, 1522 0x31220, 0x31220, 1523 0x31240, 0x31240, 1524 0x31600, 0x3160c, 1525 0x31a00, 0x31a1c, 1526 0x31e00, 0x31e20, 1527 0x31e38, 0x31e3c, 1528 0x31e80, 0x31e80, 1529 0x31e88, 0x31ea8, 1530 0x31eb0, 0x31eb4, 1531 0x31ec8, 0x31ed4, 1532 0x31fb8, 0x32004, 1533 0x32200, 0x32200, 1534 0x32208, 0x32240, 1535 0x32248, 0x32280, 1536 0x32288, 0x322c0, 1537 0x322c8, 0x322fc, 1538 0x32600, 0x32630, 1539 0x32a00, 0x32abc, 1540 0x32b00, 0x32b10, 1541 0x32b20, 0x32b30, 1542 0x32b40, 0x32b50, 1543 0x32b60, 0x32b70, 1544 0x33000, 0x33028, 1545 0x33030, 0x33048, 1546 0x33060, 0x33068, 1547 0x33070, 0x3309c, 1548 0x330f0, 0x33128, 1549 0x33130, 0x33148, 1550 0x33160, 0x33168, 1551 0x33170, 0x3319c, 1552 0x331f0, 0x33238, 1553 0x33240, 0x33240, 1554 0x33248, 0x33250, 1555 0x3325c, 0x33264, 1556 0x33270, 0x332b8, 1557 0x332c0, 0x332e4, 1558 0x332f8, 0x33338, 1559 0x33340, 0x33340, 1560 0x33348, 0x33350, 1561 0x3335c, 0x33364, 1562 0x33370, 0x333b8, 1563 0x333c0, 0x333e4, 1564 0x333f8, 0x33428, 1565 0x33430, 0x33448, 1566 0x33460, 0x33468, 1567 0x33470, 0x3349c, 1568 0x334f0, 0x33528, 1569 0x33530, 0x33548, 1570 0x33560, 0x33568, 1571 0x33570, 0x3359c, 1572 0x335f0, 0x33638, 1573 0x33640, 0x33640, 1574 0x33648, 0x33650, 1575 0x3365c, 0x33664, 1576 0x33670, 0x336b8, 1577 0x336c0, 0x336e4, 1578 0x336f8, 0x33738, 1579 0x33740, 0x33740, 1580 0x33748, 0x33750, 1581 0x3375c, 0x33764, 1582 0x33770, 0x337b8, 1583 0x337c0, 0x337e4, 1584 0x337f8, 0x337fc, 1585 0x33814, 0x33814, 1586 0x3382c, 0x3382c, 1587 0x33880, 0x3388c, 1588 0x338e8, 0x338ec, 1589 0x33900, 0x33928, 1590 0x33930, 0x33948, 1591 0x33960, 0x33968, 1592 0x33970, 0x3399c, 1593 0x339f0, 0x33a38, 1594 0x33a40, 0x33a40, 1595 0x33a48, 0x33a50, 1596 0x33a5c, 0x33a64, 1597 0x33a70, 0x33ab8, 1598 0x33ac0, 0x33ae4, 1599 0x33af8, 0x33b10, 1600 0x33b28, 0x33b28, 1601 0x33b3c, 0x33b50, 1602 0x33bf0, 0x33c10, 1603 0x33c28, 0x33c28, 1604 0x33c3c, 0x33c50, 1605 0x33cf0, 0x33cfc, 1606 0x34000, 0x34030, 1607 0x34100, 0x34144, 1608 0x34190, 0x341a0, 1609 0x341a8, 0x341b8, 1610 0x341c4, 0x341c8, 1611 0x341d0, 0x341d0, 1612 0x34200, 0x34318, 1613 0x34400, 0x344b4, 1614 0x344c0, 0x3452c, 1615 0x34540, 0x3461c, 1616 0x34800, 0x34828, 1617 0x34834, 0x34834, 1618 0x348c0, 0x34908, 1619 0x34910, 0x349ac, 1620 0x34a00, 0x34a14, 1621 0x34a1c, 0x34a2c, 1622 0x34a44, 0x34a50, 1623 0x34a74, 0x34a74, 1624 0x34a7c, 0x34afc, 1625 0x34b08, 0x34c24, 1626 0x34d00, 0x34d00, 1627 0x34d08, 0x34d14, 1628 0x34d1c, 0x34d20, 1629 0x34d3c, 0x34d3c, 1630 0x34d48, 0x34d50, 1631 0x35200, 0x3520c, 1632 0x35220, 0x35220, 1633 0x35240, 0x35240, 1634 0x35600, 0x3560c, 1635 0x35a00, 0x35a1c, 1636 0x35e00, 0x35e20, 1637 0x35e38, 0x35e3c, 1638 0x35e80, 0x35e80, 1639 0x35e88, 0x35ea8, 1640 0x35eb0, 0x35eb4, 1641 0x35ec8, 0x35ed4, 1642 0x35fb8, 0x36004, 1643 0x36200, 0x36200, 1644 0x36208, 0x36240, 1645 0x36248, 0x36280, 1646 0x36288, 0x362c0, 1647 0x362c8, 0x362fc, 1648 0x36600, 0x36630, 1649 0x36a00, 0x36abc, 1650 0x36b00, 0x36b10, 1651 0x36b20, 0x36b30, 1652 0x36b40, 0x36b50, 1653 0x36b60, 0x36b70, 1654 0x37000, 0x37028, 1655 0x37030, 0x37048, 1656 0x37060, 0x37068, 1657 0x37070, 0x3709c, 1658 0x370f0, 0x37128, 1659 0x37130, 0x37148, 1660 0x37160, 0x37168, 1661 0x37170, 0x3719c, 1662 0x371f0, 0x37238, 1663 0x37240, 0x37240, 1664 0x37248, 0x37250, 1665 0x3725c, 0x37264, 1666 0x37270, 0x372b8, 1667 0x372c0, 0x372e4, 1668 0x372f8, 0x37338, 1669 0x37340, 0x37340, 1670 0x37348, 0x37350, 1671 0x3735c, 0x37364, 1672 0x37370, 0x373b8, 1673 0x373c0, 0x373e4, 1674 0x373f8, 0x37428, 1675 0x37430, 0x37448, 1676 0x37460, 0x37468, 1677 0x37470, 0x3749c, 1678 0x374f0, 0x37528, 1679 0x37530, 0x37548, 1680 0x37560, 0x37568, 1681 0x37570, 0x3759c, 1682 0x375f0, 0x37638, 1683 0x37640, 0x37640, 1684 0x37648, 0x37650, 1685 0x3765c, 0x37664, 1686 0x37670, 0x376b8, 1687 0x376c0, 0x376e4, 1688 0x376f8, 0x37738, 1689 0x37740, 0x37740, 1690 0x37748, 0x37750, 1691 0x3775c, 0x37764, 1692 0x37770, 0x377b8, 1693 0x377c0, 0x377e4, 1694 0x377f8, 0x377fc, 1695 0x37814, 0x37814, 1696 0x3782c, 0x3782c, 1697 0x37880, 0x3788c, 1698 0x378e8, 0x378ec, 1699 0x37900, 0x37928, 1700 0x37930, 0x37948, 1701 0x37960, 0x37968, 1702 0x37970, 0x3799c, 1703 0x379f0, 0x37a38, 1704 0x37a40, 0x37a40, 1705 0x37a48, 0x37a50, 1706 0x37a5c, 0x37a64, 1707 0x37a70, 0x37ab8, 1708 0x37ac0, 0x37ae4, 1709 0x37af8, 0x37b10, 1710 0x37b28, 0x37b28, 1711 0x37b3c, 0x37b50, 1712 0x37bf0, 0x37c10, 1713 0x37c28, 0x37c28, 1714 0x37c3c, 0x37c50, 1715 0x37cf0, 0x37cfc, 1716 0x38000, 0x38030, 1717 0x38100, 0x38144, 1718 0x38190, 0x381a0, 1719 0x381a8, 0x381b8, 1720 0x381c4, 0x381c8, 1721 0x381d0, 0x381d0, 1722 0x38200, 0x38318, 1723 0x38400, 0x384b4, 1724 0x384c0, 0x3852c, 1725 0x38540, 0x3861c, 1726 0x38800, 0x38828, 1727 0x38834, 0x38834, 1728 0x388c0, 0x38908, 1729 0x38910, 0x389ac, 1730 0x38a00, 0x38a14, 1731 0x38a1c, 0x38a2c, 1732 0x38a44, 0x38a50, 1733 0x38a74, 0x38a74, 1734 0x38a7c, 0x38afc, 1735 0x38b08, 0x38c24, 1736 0x38d00, 0x38d00, 1737 0x38d08, 0x38d14, 1738 0x38d1c, 0x38d20, 1739 0x38d3c, 0x38d3c, 1740 0x38d48, 0x38d50, 1741 0x39200, 0x3920c, 1742 0x39220, 0x39220, 1743 0x39240, 0x39240, 1744 0x39600, 0x3960c, 1745 0x39a00, 0x39a1c, 1746 0x39e00, 0x39e20, 1747 0x39e38, 0x39e3c, 1748 0x39e80, 0x39e80, 1749 0x39e88, 0x39ea8, 1750 0x39eb0, 0x39eb4, 1751 0x39ec8, 0x39ed4, 1752 0x39fb8, 0x3a004, 1753 0x3a200, 0x3a200, 1754 0x3a208, 0x3a240, 1755 0x3a248, 0x3a280, 1756 0x3a288, 0x3a2c0, 1757 0x3a2c8, 0x3a2fc, 1758 0x3a600, 0x3a630, 1759 0x3aa00, 0x3aabc, 1760 0x3ab00, 0x3ab10, 1761 0x3ab20, 0x3ab30, 1762 0x3ab40, 0x3ab50, 1763 0x3ab60, 0x3ab70, 1764 0x3b000, 0x3b028, 1765 0x3b030, 0x3b048, 1766 0x3b060, 0x3b068, 1767 0x3b070, 0x3b09c, 1768 0x3b0f0, 0x3b128, 1769 0x3b130, 0x3b148, 1770 0x3b160, 0x3b168, 1771 0x3b170, 0x3b19c, 1772 0x3b1f0, 0x3b238, 1773 0x3b240, 0x3b240, 1774 0x3b248, 0x3b250, 1775 0x3b25c, 0x3b264, 1776 0x3b270, 0x3b2b8, 1777 0x3b2c0, 0x3b2e4, 1778 0x3b2f8, 0x3b338, 1779 0x3b340, 0x3b340, 1780 0x3b348, 0x3b350, 1781 0x3b35c, 0x3b364, 1782 0x3b370, 0x3b3b8, 1783 0x3b3c0, 0x3b3e4, 1784 0x3b3f8, 0x3b428, 1785 0x3b430, 0x3b448, 1786 0x3b460, 0x3b468, 1787 0x3b470, 0x3b49c, 1788 0x3b4f0, 0x3b528, 1789 0x3b530, 0x3b548, 1790 0x3b560, 0x3b568, 1791 0x3b570, 0x3b59c, 1792 0x3b5f0, 0x3b638, 1793 0x3b640, 0x3b640, 1794 0x3b648, 0x3b650, 1795 0x3b65c, 0x3b664, 1796 0x3b670, 0x3b6b8, 1797 0x3b6c0, 0x3b6e4, 1798 0x3b6f8, 0x3b738, 1799 0x3b740, 0x3b740, 1800 0x3b748, 0x3b750, 1801 0x3b75c, 0x3b764, 1802 0x3b770, 0x3b7b8, 1803 0x3b7c0, 0x3b7e4, 1804 0x3b7f8, 0x3b7fc, 1805 0x3b814, 0x3b814, 1806 0x3b82c, 0x3b82c, 1807 0x3b880, 0x3b88c, 1808 0x3b8e8, 0x3b8ec, 1809 0x3b900, 0x3b928, 1810 0x3b930, 0x3b948, 1811 0x3b960, 0x3b968, 1812 0x3b970, 0x3b99c, 1813 0x3b9f0, 0x3ba38, 1814 0x3ba40, 0x3ba40, 1815 0x3ba48, 0x3ba50, 1816 0x3ba5c, 0x3ba64, 1817 0x3ba70, 0x3bab8, 1818 0x3bac0, 0x3bae4, 1819 0x3baf8, 0x3bb10, 1820 0x3bb28, 0x3bb28, 1821 0x3bb3c, 0x3bb50, 1822 0x3bbf0, 0x3bc10, 1823 0x3bc28, 0x3bc28, 1824 0x3bc3c, 0x3bc50, 1825 0x3bcf0, 0x3bcfc, 1826 0x3c000, 0x3c030, 1827 0x3c100, 0x3c144, 1828 0x3c190, 0x3c1a0, 1829 0x3c1a8, 0x3c1b8, 1830 0x3c1c4, 0x3c1c8, 1831 0x3c1d0, 0x3c1d0, 1832 0x3c200, 0x3c318, 1833 0x3c400, 0x3c4b4, 1834 0x3c4c0, 0x3c52c, 1835 0x3c540, 0x3c61c, 1836 0x3c800, 0x3c828, 1837 0x3c834, 0x3c834, 1838 0x3c8c0, 0x3c908, 1839 0x3c910, 0x3c9ac, 1840 0x3ca00, 0x3ca14, 1841 0x3ca1c, 0x3ca2c, 1842 0x3ca44, 0x3ca50, 1843 0x3ca74, 0x3ca74, 1844 0x3ca7c, 0x3cafc, 1845 0x3cb08, 0x3cc24, 1846 0x3cd00, 0x3cd00, 1847 0x3cd08, 0x3cd14, 1848 0x3cd1c, 0x3cd20, 1849 0x3cd3c, 0x3cd3c, 1850 0x3cd48, 0x3cd50, 1851 0x3d200, 0x3d20c, 1852 0x3d220, 0x3d220, 1853 0x3d240, 0x3d240, 1854 0x3d600, 0x3d60c, 1855 0x3da00, 0x3da1c, 1856 0x3de00, 0x3de20, 1857 0x3de38, 0x3de3c, 1858 0x3de80, 0x3de80, 1859 0x3de88, 0x3dea8, 1860 0x3deb0, 0x3deb4, 1861 0x3dec8, 0x3ded4, 1862 0x3dfb8, 0x3e004, 1863 0x3e200, 0x3e200, 1864 0x3e208, 0x3e240, 1865 0x3e248, 0x3e280, 1866 0x3e288, 0x3e2c0, 1867 0x3e2c8, 0x3e2fc, 1868 0x3e600, 0x3e630, 1869 0x3ea00, 0x3eabc, 1870 0x3eb00, 0x3eb10, 1871 0x3eb20, 0x3eb30, 1872 0x3eb40, 0x3eb50, 1873 0x3eb60, 0x3eb70, 1874 0x3f000, 0x3f028, 1875 0x3f030, 0x3f048, 1876 0x3f060, 0x3f068, 1877 0x3f070, 0x3f09c, 1878 0x3f0f0, 0x3f128, 1879 0x3f130, 0x3f148, 1880 0x3f160, 0x3f168, 1881 0x3f170, 0x3f19c, 1882 0x3f1f0, 0x3f238, 1883 0x3f240, 0x3f240, 1884 0x3f248, 0x3f250, 1885 0x3f25c, 0x3f264, 1886 0x3f270, 0x3f2b8, 1887 0x3f2c0, 0x3f2e4, 1888 0x3f2f8, 0x3f338, 1889 0x3f340, 0x3f340, 1890 0x3f348, 0x3f350, 1891 0x3f35c, 0x3f364, 1892 0x3f370, 0x3f3b8, 1893 0x3f3c0, 0x3f3e4, 1894 0x3f3f8, 0x3f428, 1895 0x3f430, 0x3f448, 1896 0x3f460, 0x3f468, 1897 0x3f470, 0x3f49c, 1898 0x3f4f0, 0x3f528, 1899 0x3f530, 0x3f548, 1900 0x3f560, 0x3f568, 1901 0x3f570, 0x3f59c, 1902 0x3f5f0, 0x3f638, 1903 0x3f640, 0x3f640, 1904 0x3f648, 0x3f650, 1905 0x3f65c, 0x3f664, 1906 0x3f670, 0x3f6b8, 1907 0x3f6c0, 0x3f6e4, 1908 0x3f6f8, 0x3f738, 1909 0x3f740, 0x3f740, 1910 0x3f748, 0x3f750, 1911 0x3f75c, 0x3f764, 1912 0x3f770, 0x3f7b8, 1913 0x3f7c0, 0x3f7e4, 1914 0x3f7f8, 0x3f7fc, 1915 0x3f814, 0x3f814, 1916 0x3f82c, 0x3f82c, 1917 0x3f880, 0x3f88c, 1918 0x3f8e8, 0x3f8ec, 1919 0x3f900, 0x3f928, 1920 0x3f930, 0x3f948, 1921 0x3f960, 0x3f968, 1922 0x3f970, 0x3f99c, 1923 0x3f9f0, 0x3fa38, 1924 0x3fa40, 0x3fa40, 1925 0x3fa48, 0x3fa50, 1926 0x3fa5c, 0x3fa64, 1927 0x3fa70, 0x3fab8, 1928 0x3fac0, 0x3fae4, 1929 0x3faf8, 0x3fb10, 1930 0x3fb28, 0x3fb28, 1931 0x3fb3c, 0x3fb50, 1932 0x3fbf0, 0x3fc10, 1933 0x3fc28, 0x3fc28, 1934 0x3fc3c, 0x3fc50, 1935 0x3fcf0, 0x3fcfc, 1936 0x40000, 0x4000c, 1937 0x40040, 0x40050, 1938 0x40060, 0x40068, 1939 0x4007c, 0x4008c, 1940 0x40094, 0x400b0, 1941 0x400c0, 0x40144, 1942 0x40180, 0x4018c, 1943 0x40200, 0x40254, 1944 0x40260, 0x40264, 1945 0x40270, 0x40288, 1946 0x40290, 0x40298, 1947 0x402ac, 0x402c8, 1948 0x402d0, 0x402e0, 1949 0x402f0, 0x402f0, 1950 0x40300, 0x4033c, 1951 0x403f8, 0x403fc, 1952 0x41304, 0x413c4, 1953 0x41400, 0x4140c, 1954 0x41414, 0x4141c, 1955 0x41480, 0x414d0, 1956 0x44000, 0x44054, 1957 0x4405c, 0x44078, 1958 0x440c0, 0x44174, 1959 0x44180, 0x441ac, 1960 0x441b4, 0x441b8, 1961 0x441c0, 0x44254, 1962 0x4425c, 0x44278, 1963 0x442c0, 0x44374, 1964 0x44380, 0x443ac, 1965 0x443b4, 0x443b8, 1966 0x443c0, 0x44454, 1967 0x4445c, 0x44478, 1968 0x444c0, 0x44574, 1969 0x44580, 0x445ac, 1970 0x445b4, 0x445b8, 1971 0x445c0, 0x44654, 1972 0x4465c, 0x44678, 1973 0x446c0, 0x44774, 1974 0x44780, 0x447ac, 1975 0x447b4, 0x447b8, 1976 0x447c0, 0x44854, 1977 0x4485c, 0x44878, 1978 0x448c0, 0x44974, 1979 0x44980, 0x449ac, 1980 0x449b4, 0x449b8, 1981 0x449c0, 0x449fc, 1982 0x45000, 0x45004, 1983 0x45010, 0x45030, 1984 0x45040, 0x45060, 1985 0x45068, 0x45068, 1986 0x45080, 0x45084, 1987 0x450a0, 0x450b0, 1988 0x45200, 0x45204, 1989 0x45210, 0x45230, 1990 0x45240, 0x45260, 1991 0x45268, 0x45268, 1992 0x45280, 0x45284, 1993 0x452a0, 0x452b0, 1994 0x460c0, 0x460e4, 1995 0x47000, 0x4703c, 1996 0x47044, 0x4708c, 1997 0x47200, 0x47250, 1998 0x47400, 0x47408, 1999 0x47414, 0x47420, 2000 0x47600, 0x47618, 2001 0x47800, 0x47814, 2002 0x48000, 0x4800c, 2003 0x48040, 0x48050, 2004 0x48060, 0x48068, 2005 0x4807c, 0x4808c, 2006 0x48094, 0x480b0, 2007 0x480c0, 0x48144, 2008 0x48180, 0x4818c, 2009 0x48200, 0x48254, 2010 0x48260, 0x48264, 2011 0x48270, 0x48288, 2012 0x48290, 0x48298, 2013 0x482ac, 0x482c8, 2014 0x482d0, 0x482e0, 2015 0x482f0, 0x482f0, 2016 0x48300, 0x4833c, 2017 0x483f8, 0x483fc, 2018 0x49304, 0x493c4, 2019 0x49400, 0x4940c, 2020 0x49414, 0x4941c, 2021 0x49480, 0x494d0, 2022 0x4c000, 0x4c054, 2023 0x4c05c, 0x4c078, 2024 0x4c0c0, 0x4c174, 2025 0x4c180, 0x4c1ac, 2026 0x4c1b4, 0x4c1b8, 2027 0x4c1c0, 0x4c254, 2028 0x4c25c, 0x4c278, 2029 0x4c2c0, 0x4c374, 2030 0x4c380, 0x4c3ac, 2031 0x4c3b4, 0x4c3b8, 2032 0x4c3c0, 0x4c454, 2033 0x4c45c, 0x4c478, 2034 0x4c4c0, 0x4c574, 2035 0x4c580, 0x4c5ac, 2036 0x4c5b4, 0x4c5b8, 2037 0x4c5c0, 0x4c654, 2038 0x4c65c, 0x4c678, 2039 0x4c6c0, 0x4c774, 2040 0x4c780, 0x4c7ac, 2041 0x4c7b4, 0x4c7b8, 2042 0x4c7c0, 0x4c854, 2043 0x4c85c, 0x4c878, 2044 0x4c8c0, 0x4c974, 2045 0x4c980, 0x4c9ac, 2046 0x4c9b4, 0x4c9b8, 2047 0x4c9c0, 0x4c9fc, 2048 0x4d000, 0x4d004, 2049 0x4d010, 0x4d030, 2050 0x4d040, 0x4d060, 2051 0x4d068, 0x4d068, 2052 0x4d080, 0x4d084, 2053 0x4d0a0, 0x4d0b0, 2054 0x4d200, 0x4d204, 2055 0x4d210, 0x4d230, 2056 0x4d240, 0x4d260, 2057 0x4d268, 0x4d268, 2058 0x4d280, 0x4d284, 2059 0x4d2a0, 0x4d2b0, 2060 0x4e0c0, 0x4e0e4, 2061 0x4f000, 0x4f03c, 2062 0x4f044, 0x4f08c, 2063 0x4f200, 0x4f250, 2064 0x4f400, 0x4f408, 2065 0x4f414, 0x4f420, 2066 0x4f600, 0x4f618, 2067 0x4f800, 0x4f814, 2068 0x50000, 0x50084, 2069 0x50090, 0x500cc, 2070 0x50400, 0x50400, 2071 0x50800, 0x50884, 2072 0x50890, 0x508cc, 2073 0x50c00, 0x50c00, 2074 0x51000, 0x5101c, 2075 0x51300, 0x51308, 2076 }; 2077 2078 static const unsigned int t5vf_reg_ranges[] = { 2079 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2080 VF_MPS_REG(A_MPS_VF_CTL), 2081 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2082 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2083 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2084 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2085 FW_T4VF_MBDATA_BASE_ADDR, 2086 FW_T4VF_MBDATA_BASE_ADDR + 2087 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2088 }; 2089 2090 static const unsigned int t6_reg_ranges[] = { 2091 0x1008, 0x101c, 2092 0x1024, 0x10a8, 2093 0x10b4, 0x10f8, 2094 0x1100, 0x1114, 2095 0x111c, 0x112c, 2096 0x1138, 0x113c, 2097 0x1144, 0x114c, 2098 0x1180, 0x1184, 2099 0x1190, 0x1194, 2100 0x11a0, 0x11a4, 2101 0x11b0, 0x11b4, 2102 0x11fc, 0x1274, 2103 0x1280, 0x133c, 2104 0x1800, 0x18fc, 2105 0x3000, 0x302c, 2106 0x3060, 0x30b0, 2107 0x30b8, 0x30d8, 2108 0x30e0, 0x30fc, 2109 0x3140, 0x357c, 2110 0x35a8, 0x35cc, 2111 0x35ec, 0x35ec, 2112 0x3600, 0x5624, 2113 0x56cc, 0x56ec, 2114 0x56f4, 0x5720, 2115 0x5728, 0x575c, 2116 0x580c, 0x5814, 2117 0x5890, 0x589c, 2118 0x58a4, 0x58ac, 2119 0x58b8, 0x58bc, 2120 0x5940, 0x595c, 2121 0x5980, 0x598c, 2122 0x59b0, 0x59c8, 2123 0x59d0, 0x59dc, 2124 0x59fc, 0x5a18, 2125 0x5a60, 0x5a6c, 2126 0x5a80, 0x5a8c, 2127 0x5a94, 0x5a9c, 2128 0x5b94, 0x5bfc, 2129 0x5c10, 0x5e48, 2130 0x5e50, 0x5e94, 2131 0x5ea0, 0x5eb0, 2132 0x5ec0, 0x5ec0, 2133 0x5ec8, 0x5ed0, 2134 0x5ee0, 0x5ee0, 2135 0x5ef0, 0x5ef0, 2136 0x5f00, 0x5f00, 2137 0x6000, 0x6020, 2138 0x6028, 0x6040, 2139 0x6058, 0x609c, 2140 0x60a8, 0x619c, 2141 0x7700, 0x7798, 2142 0x77c0, 0x7880, 2143 0x78cc, 0x78fc, 2144 0x7b00, 0x7b58, 2145 0x7b60, 0x7b84, 2146 0x7b8c, 0x7c54, 2147 0x7d00, 0x7d38, 2148 0x7d40, 0x7d84, 2149 0x7d8c, 0x7ddc, 2150 0x7de4, 0x7e04, 2151 0x7e10, 0x7e1c, 2152 0x7e24, 0x7e38, 2153 0x7e40, 0x7e44, 2154 0x7e4c, 0x7e78, 2155 0x7e80, 0x7edc, 2156 0x7ee8, 0x7efc, 2157 0x8dc0, 0x8de4, 2158 0x8df8, 0x8e04, 2159 0x8e10, 0x8e84, 2160 0x8ea0, 0x8f88, 2161 0x8fb8, 0x9058, 2162 0x9060, 0x9060, 2163 0x9068, 0x90f8, 2164 0x9100, 0x9124, 2165 0x9400, 0x9470, 2166 0x9600, 0x9600, 2167 0x9608, 0x9638, 2168 0x9640, 0x9704, 2169 0x9710, 0x971c, 2170 0x9800, 0x9808, 2171 0x9820, 0x983c, 2172 0x9850, 0x9864, 2173 0x9c00, 0x9c6c, 2174 0x9c80, 0x9cec, 2175 0x9d00, 0x9d6c, 2176 0x9d80, 0x9dec, 2177 0x9e00, 0x9e6c, 2178 0x9e80, 0x9eec, 2179 0x9f00, 0x9f6c, 2180 0x9f80, 0xa020, 2181 0xd004, 0xd03c, 2182 0xd100, 0xd118, 2183 0xd200, 0xd214, 2184 0xd220, 0xd234, 2185 0xd240, 0xd254, 2186 0xd260, 0xd274, 2187 0xd280, 0xd294, 2188 0xd2a0, 0xd2b4, 2189 0xd2c0, 0xd2d4, 2190 0xd2e0, 0xd2f4, 2191 0xd300, 0xd31c, 2192 0xdfc0, 0xdfe0, 2193 0xe000, 0xf008, 2194 0xf010, 0xf018, 2195 0xf020, 0xf028, 2196 0x11000, 0x11014, 2197 0x11048, 0x1106c, 2198 0x11074, 0x11088, 2199 0x11098, 0x11120, 2200 0x1112c, 0x1117c, 2201 0x11190, 0x112e0, 2202 0x11300, 0x1130c, 2203 0x12000, 0x1206c, 2204 0x19040, 0x1906c, 2205 0x19078, 0x19080, 2206 0x1908c, 0x190e8, 2207 0x190f0, 0x190f8, 2208 0x19100, 0x19110, 2209 0x19120, 0x19124, 2210 0x19150, 0x19194, 2211 0x1919c, 0x191b0, 2212 0x191d0, 0x191e8, 2213 0x19238, 0x19290, 2214 0x192a4, 0x192b0, 2215 0x192bc, 0x192bc, 2216 0x19348, 0x1934c, 2217 0x193f8, 0x19418, 2218 0x19420, 0x19428, 2219 0x19430, 0x19444, 2220 0x1944c, 0x1946c, 2221 0x19474, 0x19474, 2222 0x19490, 0x194cc, 2223 0x194f0, 0x194f8, 2224 0x19c00, 0x19c48, 2225 0x19c50, 0x19c80, 2226 0x19c94, 0x19c98, 2227 0x19ca0, 0x19cbc, 2228 0x19ce4, 0x19ce4, 2229 0x19cf0, 0x19cf8, 2230 0x19d00, 0x19d28, 2231 0x19d50, 0x19d78, 2232 0x19d94, 0x19d98, 2233 0x19da0, 0x19dc8, 2234 0x19df0, 0x19e10, 2235 0x19e50, 0x19e6c, 2236 0x19ea0, 0x19ebc, 2237 0x19ec4, 0x19ef4, 2238 0x19f04, 0x19f2c, 2239 0x19f34, 0x19f34, 2240 0x19f40, 0x19f50, 2241 0x19f90, 0x19fac, 2242 0x19fc4, 0x19fc8, 2243 0x19fd0, 0x19fe4, 2244 0x1a000, 0x1a004, 2245 0x1a010, 0x1a06c, 2246 0x1a0b0, 0x1a0e4, 2247 0x1a0ec, 0x1a0f8, 2248 0x1a100, 0x1a108, 2249 0x1a114, 0x1a120, 2250 0x1a128, 0x1a130, 2251 0x1a138, 0x1a138, 2252 0x1a190, 0x1a1c4, 2253 0x1a1fc, 0x1a1fc, 2254 0x1e008, 0x1e00c, 2255 0x1e040, 0x1e044, 2256 0x1e04c, 0x1e04c, 2257 0x1e284, 0x1e290, 2258 0x1e2c0, 0x1e2c0, 2259 0x1e2e0, 0x1e2e0, 2260 0x1e300, 0x1e384, 2261 0x1e3c0, 0x1e3c8, 2262 0x1e408, 0x1e40c, 2263 0x1e440, 0x1e444, 2264 0x1e44c, 0x1e44c, 2265 0x1e684, 0x1e690, 2266 0x1e6c0, 0x1e6c0, 2267 0x1e6e0, 0x1e6e0, 2268 0x1e700, 0x1e784, 2269 0x1e7c0, 0x1e7c8, 2270 0x1e808, 0x1e80c, 2271 0x1e840, 0x1e844, 2272 0x1e84c, 0x1e84c, 2273 0x1ea84, 0x1ea90, 2274 0x1eac0, 0x1eac0, 2275 0x1eae0, 0x1eae0, 2276 0x1eb00, 0x1eb84, 2277 0x1ebc0, 0x1ebc8, 2278 0x1ec08, 0x1ec0c, 2279 0x1ec40, 0x1ec44, 2280 0x1ec4c, 0x1ec4c, 2281 0x1ee84, 0x1ee90, 2282 0x1eec0, 0x1eec0, 2283 0x1eee0, 0x1eee0, 2284 0x1ef00, 0x1ef84, 2285 0x1efc0, 0x1efc8, 2286 0x1f008, 0x1f00c, 2287 0x1f040, 0x1f044, 2288 0x1f04c, 0x1f04c, 2289 0x1f284, 0x1f290, 2290 0x1f2c0, 0x1f2c0, 2291 0x1f2e0, 0x1f2e0, 2292 0x1f300, 0x1f384, 2293 0x1f3c0, 0x1f3c8, 2294 0x1f408, 0x1f40c, 2295 0x1f440, 0x1f444, 2296 0x1f44c, 0x1f44c, 2297 0x1f684, 0x1f690, 2298 0x1f6c0, 0x1f6c0, 2299 0x1f6e0, 0x1f6e0, 2300 0x1f700, 0x1f784, 2301 0x1f7c0, 0x1f7c8, 2302 0x1f808, 0x1f80c, 2303 0x1f840, 0x1f844, 2304 0x1f84c, 0x1f84c, 2305 0x1fa84, 0x1fa90, 2306 0x1fac0, 0x1fac0, 2307 0x1fae0, 0x1fae0, 2308 0x1fb00, 0x1fb84, 2309 0x1fbc0, 0x1fbc8, 2310 0x1fc08, 0x1fc0c, 2311 0x1fc40, 0x1fc44, 2312 0x1fc4c, 0x1fc4c, 2313 0x1fe84, 0x1fe90, 2314 0x1fec0, 0x1fec0, 2315 0x1fee0, 0x1fee0, 2316 0x1ff00, 0x1ff84, 2317 0x1ffc0, 0x1ffc8, 2318 0x30000, 0x30030, 2319 0x30100, 0x30168, 2320 0x30190, 0x301a0, 2321 0x301a8, 0x301b8, 2322 0x301c4, 0x301c8, 2323 0x301d0, 0x301d0, 2324 0x30200, 0x30320, 2325 0x30400, 0x304b4, 2326 0x304c0, 0x3052c, 2327 0x30540, 0x3061c, 2328 0x30800, 0x308a0, 2329 0x308c0, 0x30908, 2330 0x30910, 0x309b8, 2331 0x30a00, 0x30a04, 2332 0x30a0c, 0x30a14, 2333 0x30a1c, 0x30a2c, 2334 0x30a44, 0x30a50, 2335 0x30a74, 0x30a74, 2336 0x30a7c, 0x30afc, 2337 0x30b08, 0x30c24, 2338 0x30d00, 0x30d14, 2339 0x30d1c, 0x30d3c, 2340 0x30d44, 0x30d4c, 2341 0x30d54, 0x30d74, 2342 0x30d7c, 0x30d7c, 2343 0x30de0, 0x30de0, 2344 0x30e00, 0x30ed4, 2345 0x30f00, 0x30fa4, 2346 0x30fc0, 0x30fc4, 2347 0x31000, 0x31004, 2348 0x31080, 0x310fc, 2349 0x31208, 0x31220, 2350 0x3123c, 0x31254, 2351 0x31300, 0x31300, 2352 0x31308, 0x3131c, 2353 0x31338, 0x3133c, 2354 0x31380, 0x31380, 2355 0x31388, 0x313a8, 2356 0x313b4, 0x313b4, 2357 0x31400, 0x31420, 2358 0x31438, 0x3143c, 2359 0x31480, 0x31480, 2360 0x314a8, 0x314a8, 2361 0x314b0, 0x314b4, 2362 0x314c8, 0x314d4, 2363 0x31a40, 0x31a4c, 2364 0x31af0, 0x31b20, 2365 0x31b38, 0x31b3c, 2366 0x31b80, 0x31b80, 2367 0x31ba8, 0x31ba8, 2368 0x31bb0, 0x31bb4, 2369 0x31bc8, 0x31bd4, 2370 0x32140, 0x3218c, 2371 0x321f0, 0x321f4, 2372 0x32200, 0x32200, 2373 0x32218, 0x32218, 2374 0x32400, 0x32400, 2375 0x32408, 0x3241c, 2376 0x32618, 0x32620, 2377 0x32664, 0x32664, 2378 0x326a8, 0x326a8, 2379 0x326ec, 0x326ec, 2380 0x32a00, 0x32abc, 2381 0x32b00, 0x32b18, 2382 0x32b20, 0x32b38, 2383 0x32b40, 0x32b58, 2384 0x32b60, 0x32b78, 2385 0x32c00, 0x32c00, 2386 0x32c08, 0x32c3c, 2387 0x33000, 0x3302c, 2388 0x33034, 0x33050, 2389 0x33058, 0x33058, 2390 0x33060, 0x3308c, 2391 0x3309c, 0x330ac, 2392 0x330c0, 0x330c0, 2393 0x330c8, 0x330d0, 2394 0x330d8, 0x330e0, 2395 0x330ec, 0x3312c, 2396 0x33134, 0x33150, 2397 0x33158, 0x33158, 2398 0x33160, 0x3318c, 2399 0x3319c, 0x331ac, 2400 0x331c0, 0x331c0, 2401 0x331c8, 0x331d0, 2402 0x331d8, 0x331e0, 2403 0x331ec, 0x33290, 2404 0x33298, 0x332c4, 2405 0x332e4, 0x33390, 2406 0x33398, 0x333c4, 2407 0x333e4, 0x3342c, 2408 0x33434, 0x33450, 2409 0x33458, 0x33458, 2410 0x33460, 0x3348c, 2411 0x3349c, 0x334ac, 2412 0x334c0, 0x334c0, 2413 0x334c8, 0x334d0, 2414 0x334d8, 0x334e0, 2415 0x334ec, 0x3352c, 2416 0x33534, 0x33550, 2417 0x33558, 0x33558, 2418 0x33560, 0x3358c, 2419 0x3359c, 0x335ac, 2420 0x335c0, 0x335c0, 2421 0x335c8, 0x335d0, 2422 0x335d8, 0x335e0, 2423 0x335ec, 0x33690, 2424 0x33698, 0x336c4, 2425 0x336e4, 0x33790, 2426 0x33798, 0x337c4, 2427 0x337e4, 0x337fc, 2428 0x33814, 0x33814, 2429 0x33854, 0x33868, 2430 0x33880, 0x3388c, 2431 0x338c0, 0x338d0, 2432 0x338e8, 0x338ec, 2433 0x33900, 0x3392c, 2434 0x33934, 0x33950, 2435 0x33958, 0x33958, 2436 0x33960, 0x3398c, 2437 0x3399c, 0x339ac, 2438 0x339c0, 0x339c0, 2439 0x339c8, 0x339d0, 2440 0x339d8, 0x339e0, 2441 0x339ec, 0x33a90, 2442 0x33a98, 0x33ac4, 2443 0x33ae4, 0x33b10, 2444 0x33b24, 0x33b28, 2445 0x33b38, 0x33b50, 2446 0x33bf0, 0x33c10, 2447 0x33c24, 0x33c28, 2448 0x33c38, 0x33c50, 2449 0x33cf0, 0x33cfc, 2450 0x34000, 0x34030, 2451 0x34100, 0x34168, 2452 0x34190, 0x341a0, 2453 0x341a8, 0x341b8, 2454 0x341c4, 0x341c8, 2455 0x341d0, 0x341d0, 2456 0x34200, 0x34320, 2457 0x34400, 0x344b4, 2458 0x344c0, 0x3452c, 2459 0x34540, 0x3461c, 2460 0x34800, 0x348a0, 2461 0x348c0, 0x34908, 2462 0x34910, 0x349b8, 2463 0x34a00, 0x34a04, 2464 0x34a0c, 0x34a14, 2465 0x34a1c, 0x34a2c, 2466 0x34a44, 0x34a50, 2467 0x34a74, 0x34a74, 2468 0x34a7c, 0x34afc, 2469 0x34b08, 0x34c24, 2470 0x34d00, 0x34d14, 2471 0x34d1c, 0x34d3c, 2472 0x34d44, 0x34d4c, 2473 0x34d54, 0x34d74, 2474 0x34d7c, 0x34d7c, 2475 0x34de0, 0x34de0, 2476 0x34e00, 0x34ed4, 2477 0x34f00, 0x34fa4, 2478 0x34fc0, 0x34fc4, 2479 0x35000, 0x35004, 2480 0x35080, 0x350fc, 2481 0x35208, 0x35220, 2482 0x3523c, 0x35254, 2483 0x35300, 0x35300, 2484 0x35308, 0x3531c, 2485 0x35338, 0x3533c, 2486 0x35380, 0x35380, 2487 0x35388, 0x353a8, 2488 0x353b4, 0x353b4, 2489 0x35400, 0x35420, 2490 0x35438, 0x3543c, 2491 0x35480, 0x35480, 2492 0x354a8, 0x354a8, 2493 0x354b0, 0x354b4, 2494 0x354c8, 0x354d4, 2495 0x35a40, 0x35a4c, 2496 0x35af0, 0x35b20, 2497 0x35b38, 0x35b3c, 2498 0x35b80, 0x35b80, 2499 0x35ba8, 0x35ba8, 2500 0x35bb0, 0x35bb4, 2501 0x35bc8, 0x35bd4, 2502 0x36140, 0x3618c, 2503 0x361f0, 0x361f4, 2504 0x36200, 0x36200, 2505 0x36218, 0x36218, 2506 0x36400, 0x36400, 2507 0x36408, 0x3641c, 2508 0x36618, 0x36620, 2509 0x36664, 0x36664, 2510 0x366a8, 0x366a8, 2511 0x366ec, 0x366ec, 2512 0x36a00, 0x36abc, 2513 0x36b00, 0x36b18, 2514 0x36b20, 0x36b38, 2515 0x36b40, 0x36b58, 2516 0x36b60, 0x36b78, 2517 0x36c00, 0x36c00, 2518 0x36c08, 0x36c3c, 2519 0x37000, 0x3702c, 2520 0x37034, 0x37050, 2521 0x37058, 0x37058, 2522 0x37060, 0x3708c, 2523 0x3709c, 0x370ac, 2524 0x370c0, 0x370c0, 2525 0x370c8, 0x370d0, 2526 0x370d8, 0x370e0, 2527 0x370ec, 0x3712c, 2528 0x37134, 0x37150, 2529 0x37158, 0x37158, 2530 0x37160, 0x3718c, 2531 0x3719c, 0x371ac, 2532 0x371c0, 0x371c0, 2533 0x371c8, 0x371d0, 2534 0x371d8, 0x371e0, 2535 0x371ec, 0x37290, 2536 0x37298, 0x372c4, 2537 0x372e4, 0x37390, 2538 0x37398, 0x373c4, 2539 0x373e4, 0x3742c, 2540 0x37434, 0x37450, 2541 0x37458, 0x37458, 2542 0x37460, 0x3748c, 2543 0x3749c, 0x374ac, 2544 0x374c0, 0x374c0, 2545 0x374c8, 0x374d0, 2546 0x374d8, 0x374e0, 2547 0x374ec, 0x3752c, 2548 0x37534, 0x37550, 2549 0x37558, 0x37558, 2550 0x37560, 0x3758c, 2551 0x3759c, 0x375ac, 2552 0x375c0, 0x375c0, 2553 0x375c8, 0x375d0, 2554 0x375d8, 0x375e0, 2555 0x375ec, 0x37690, 2556 0x37698, 0x376c4, 2557 0x376e4, 0x37790, 2558 0x37798, 0x377c4, 2559 0x377e4, 0x377fc, 2560 0x37814, 0x37814, 2561 0x37854, 0x37868, 2562 0x37880, 0x3788c, 2563 0x378c0, 0x378d0, 2564 0x378e8, 0x378ec, 2565 0x37900, 0x3792c, 2566 0x37934, 0x37950, 2567 0x37958, 0x37958, 2568 0x37960, 0x3798c, 2569 0x3799c, 0x379ac, 2570 0x379c0, 0x379c0, 2571 0x379c8, 0x379d0, 2572 0x379d8, 0x379e0, 2573 0x379ec, 0x37a90, 2574 0x37a98, 0x37ac4, 2575 0x37ae4, 0x37b10, 2576 0x37b24, 0x37b28, 2577 0x37b38, 0x37b50, 2578 0x37bf0, 0x37c10, 2579 0x37c24, 0x37c28, 2580 0x37c38, 0x37c50, 2581 0x37cf0, 0x37cfc, 2582 0x40040, 0x40040, 2583 0x40080, 0x40084, 2584 0x40100, 0x40100, 2585 0x40140, 0x401bc, 2586 0x40200, 0x40214, 2587 0x40228, 0x40228, 2588 0x40240, 0x40258, 2589 0x40280, 0x40280, 2590 0x40304, 0x40304, 2591 0x40330, 0x4033c, 2592 0x41304, 0x413c8, 2593 0x413d0, 0x413dc, 2594 0x413f0, 0x413f0, 2595 0x41400, 0x4140c, 2596 0x41414, 0x4141c, 2597 0x41480, 0x414d0, 2598 0x44000, 0x4407c, 2599 0x440c0, 0x441ac, 2600 0x441b4, 0x4427c, 2601 0x442c0, 0x443ac, 2602 0x443b4, 0x4447c, 2603 0x444c0, 0x445ac, 2604 0x445b4, 0x4467c, 2605 0x446c0, 0x447ac, 2606 0x447b4, 0x4487c, 2607 0x448c0, 0x449ac, 2608 0x449b4, 0x44a7c, 2609 0x44ac0, 0x44bac, 2610 0x44bb4, 0x44c7c, 2611 0x44cc0, 0x44dac, 2612 0x44db4, 0x44e7c, 2613 0x44ec0, 0x44fac, 2614 0x44fb4, 0x4507c, 2615 0x450c0, 0x451ac, 2616 0x451b4, 0x451fc, 2617 0x45800, 0x45804, 2618 0x45810, 0x45830, 2619 0x45840, 0x45860, 2620 0x45868, 0x45868, 2621 0x45880, 0x45884, 2622 0x458a0, 0x458b0, 2623 0x45a00, 0x45a04, 2624 0x45a10, 0x45a30, 2625 0x45a40, 0x45a60, 2626 0x45a68, 0x45a68, 2627 0x45a80, 0x45a84, 2628 0x45aa0, 0x45ab0, 2629 0x460c0, 0x460e4, 2630 0x47000, 0x4703c, 2631 0x47044, 0x4708c, 2632 0x47200, 0x47250, 2633 0x47400, 0x47408, 2634 0x47414, 0x47420, 2635 0x47600, 0x47618, 2636 0x47800, 0x47814, 2637 0x47820, 0x4782c, 2638 0x50000, 0x50084, 2639 0x50090, 0x500cc, 2640 0x50300, 0x50384, 2641 0x50400, 0x50400, 2642 0x50800, 0x50884, 2643 0x50890, 0x508cc, 2644 0x50b00, 0x50b84, 2645 0x50c00, 0x50c00, 2646 0x51000, 0x51020, 2647 0x51028, 0x510b0, 2648 0x51300, 0x51324, 2649 }; 2650 2651 static const unsigned int t6vf_reg_ranges[] = { 2652 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2653 VF_MPS_REG(A_MPS_VF_CTL), 2654 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2655 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2656 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2657 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2658 FW_T6VF_MBDATA_BASE_ADDR, 2659 FW_T6VF_MBDATA_BASE_ADDR + 2660 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2661 }; 2662 2663 u32 *buf_end = (u32 *)(buf + buf_size); 2664 const unsigned int *reg_ranges; 2665 int reg_ranges_size, range; 2666 unsigned int chip_version = chip_id(adap); 2667 2668 /* 2669 * Select the right set of register ranges to dump depending on the 2670 * adapter chip type. 2671 */ 2672 switch (chip_version) { 2673 case CHELSIO_T4: 2674 if (adap->flags & IS_VF) { 2675 reg_ranges = t4vf_reg_ranges; 2676 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2677 } else { 2678 reg_ranges = t4_reg_ranges; 2679 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2680 } 2681 break; 2682 2683 case CHELSIO_T5: 2684 if (adap->flags & IS_VF) { 2685 reg_ranges = t5vf_reg_ranges; 2686 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2687 } else { 2688 reg_ranges = t5_reg_ranges; 2689 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2690 } 2691 break; 2692 2693 case CHELSIO_T6: 2694 if (adap->flags & IS_VF) { 2695 reg_ranges = t6vf_reg_ranges; 2696 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2697 } else { 2698 reg_ranges = t6_reg_ranges; 2699 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2700 } 2701 break; 2702 2703 default: 2704 CH_ERR(adap, 2705 "Unsupported chip version %d\n", chip_version); 2706 return; 2707 } 2708 2709 /* 2710 * Clear the register buffer and insert the appropriate register 2711 * values selected by the above register ranges. 2712 */ 2713 memset(buf, 0, buf_size); 2714 for (range = 0; range < reg_ranges_size; range += 2) { 2715 unsigned int reg = reg_ranges[range]; 2716 unsigned int last_reg = reg_ranges[range + 1]; 2717 u32 *bufp = (u32 *)(buf + reg); 2718 2719 /* 2720 * Iterate across the register range filling in the register 2721 * buffer but don't write past the end of the register buffer. 2722 */ 2723 while (reg <= last_reg && bufp < buf_end) { 2724 *bufp++ = t4_read_reg(adap, reg); 2725 reg += sizeof(u32); 2726 } 2727 } 2728 } 2729 2730 /* 2731 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2732 * header followed by one or more VPD-R sections, each with its own header. 2733 */ 2734 struct t4_vpd_hdr { 2735 u8 id_tag; 2736 u8 id_len[2]; 2737 u8 id_data[ID_LEN]; 2738 }; 2739 2740 struct t4_vpdr_hdr { 2741 u8 vpdr_tag; 2742 u8 vpdr_len[2]; 2743 }; 2744 2745 /* 2746 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2747 */ 2748 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2749 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2750 2751 #define EEPROM_STAT_ADDR 0x7bfc 2752 #define VPD_SIZE 0x800 2753 #define VPD_BASE 0x400 2754 #define VPD_BASE_OLD 0 2755 #define VPD_LEN 1024 2756 #define VPD_INFO_FLD_HDR_SIZE 3 2757 #define CHELSIO_VPD_UNIQUE_ID 0x82 2758 2759 /* 2760 * Small utility function to wait till any outstanding VPD Access is complete. 2761 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2762 * VPD Access in flight. This allows us to handle the problem of having a 2763 * previous VPD Access time out and prevent an attempt to inject a new VPD 2764 * Request before any in-flight VPD reguest has completed. 2765 */ 2766 static int t4_seeprom_wait(struct adapter *adapter) 2767 { 2768 unsigned int base = adapter->params.pci.vpd_cap_addr; 2769 int max_poll; 2770 2771 /* 2772 * If no VPD Access is in flight, we can just return success right 2773 * away. 2774 */ 2775 if (!adapter->vpd_busy) 2776 return 0; 2777 2778 /* 2779 * Poll the VPD Capability Address/Flag register waiting for it 2780 * to indicate that the operation is complete. 2781 */ 2782 max_poll = EEPROM_MAX_POLL; 2783 do { 2784 u16 val; 2785 2786 udelay(EEPROM_DELAY); 2787 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2788 2789 /* 2790 * If the operation is complete, mark the VPD as no longer 2791 * busy and return success. 2792 */ 2793 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2794 adapter->vpd_busy = 0; 2795 return 0; 2796 } 2797 } while (--max_poll); 2798 2799 /* 2800 * Failure! Note that we leave the VPD Busy status set in order to 2801 * avoid pushing a new VPD Access request into the VPD Capability till 2802 * the current operation eventually succeeds. It's a bug to issue a 2803 * new request when an existing request is in flight and will result 2804 * in corrupt hardware state. 2805 */ 2806 return -ETIMEDOUT; 2807 } 2808 2809 /** 2810 * t4_seeprom_read - read a serial EEPROM location 2811 * @adapter: adapter to read 2812 * @addr: EEPROM virtual address 2813 * @data: where to store the read data 2814 * 2815 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2816 * VPD capability. Note that this function must be called with a virtual 2817 * address. 2818 */ 2819 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2820 { 2821 unsigned int base = adapter->params.pci.vpd_cap_addr; 2822 int ret; 2823 2824 /* 2825 * VPD Accesses must alway be 4-byte aligned! 2826 */ 2827 if (addr >= EEPROMVSIZE || (addr & 3)) 2828 return -EINVAL; 2829 2830 /* 2831 * Wait for any previous operation which may still be in flight to 2832 * complete. 2833 */ 2834 ret = t4_seeprom_wait(adapter); 2835 if (ret) { 2836 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2837 return ret; 2838 } 2839 2840 /* 2841 * Issue our new VPD Read request, mark the VPD as being busy and wait 2842 * for our request to complete. If it doesn't complete, note the 2843 * error and return it to our caller. Note that we do not reset the 2844 * VPD Busy status! 2845 */ 2846 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2847 adapter->vpd_busy = 1; 2848 adapter->vpd_flag = PCI_VPD_ADDR_F; 2849 ret = t4_seeprom_wait(adapter); 2850 if (ret) { 2851 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2852 return ret; 2853 } 2854 2855 /* 2856 * Grab the returned data, swizzle it into our endianness and 2857 * return success. 2858 */ 2859 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2860 *data = le32_to_cpu(*data); 2861 return 0; 2862 } 2863 2864 /** 2865 * t4_seeprom_write - write a serial EEPROM location 2866 * @adapter: adapter to write 2867 * @addr: virtual EEPROM address 2868 * @data: value to write 2869 * 2870 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2871 * VPD capability. Note that this function must be called with a virtual 2872 * address. 2873 */ 2874 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2875 { 2876 unsigned int base = adapter->params.pci.vpd_cap_addr; 2877 int ret; 2878 u32 stats_reg; 2879 int max_poll; 2880 2881 /* 2882 * VPD Accesses must alway be 4-byte aligned! 2883 */ 2884 if (addr >= EEPROMVSIZE || (addr & 3)) 2885 return -EINVAL; 2886 2887 /* 2888 * Wait for any previous operation which may still be in flight to 2889 * complete. 2890 */ 2891 ret = t4_seeprom_wait(adapter); 2892 if (ret) { 2893 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2894 return ret; 2895 } 2896 2897 /* 2898 * Issue our new VPD Read request, mark the VPD as being busy and wait 2899 * for our request to complete. If it doesn't complete, note the 2900 * error and return it to our caller. Note that we do not reset the 2901 * VPD Busy status! 2902 */ 2903 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2904 cpu_to_le32(data)); 2905 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2906 (u16)addr | PCI_VPD_ADDR_F); 2907 adapter->vpd_busy = 1; 2908 adapter->vpd_flag = 0; 2909 ret = t4_seeprom_wait(adapter); 2910 if (ret) { 2911 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2912 return ret; 2913 } 2914 2915 /* 2916 * Reset PCI_VPD_DATA register after a transaction and wait for our 2917 * request to complete. If it doesn't complete, return error. 2918 */ 2919 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2920 max_poll = EEPROM_MAX_POLL; 2921 do { 2922 udelay(EEPROM_DELAY); 2923 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2924 } while ((stats_reg & 0x1) && --max_poll); 2925 if (!max_poll) 2926 return -ETIMEDOUT; 2927 2928 /* Return success! */ 2929 return 0; 2930 } 2931 2932 /** 2933 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2934 * @phys_addr: the physical EEPROM address 2935 * @fn: the PCI function number 2936 * @sz: size of function-specific area 2937 * 2938 * Translate a physical EEPROM address to virtual. The first 1K is 2939 * accessed through virtual addresses starting at 31K, the rest is 2940 * accessed through virtual addresses starting at 0. 2941 * 2942 * The mapping is as follows: 2943 * [0..1K) -> [31K..32K) 2944 * [1K..1K+A) -> [ES-A..ES) 2945 * [1K+A..ES) -> [0..ES-A-1K) 2946 * 2947 * where A = @fn * @sz, and ES = EEPROM size. 2948 */ 2949 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2950 { 2951 fn *= sz; 2952 if (phys_addr < 1024) 2953 return phys_addr + (31 << 10); 2954 if (phys_addr < 1024 + fn) 2955 return EEPROMSIZE - fn + phys_addr - 1024; 2956 if (phys_addr < EEPROMSIZE) 2957 return phys_addr - 1024 - fn; 2958 return -EINVAL; 2959 } 2960 2961 /** 2962 * t4_seeprom_wp - enable/disable EEPROM write protection 2963 * @adapter: the adapter 2964 * @enable: whether to enable or disable write protection 2965 * 2966 * Enables or disables write protection on the serial EEPROM. 2967 */ 2968 int t4_seeprom_wp(struct adapter *adapter, int enable) 2969 { 2970 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2971 } 2972 2973 /** 2974 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2975 * @vpd: Pointer to buffered vpd data structure 2976 * @kw: The keyword to search for 2977 * @region: VPD region to search (starting from 0) 2978 * 2979 * Returns the value of the information field keyword or 2980 * -ENOENT otherwise. 2981 */ 2982 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2983 { 2984 int i, tag; 2985 unsigned int offset, len; 2986 const struct t4_vpdr_hdr *vpdr; 2987 2988 offset = sizeof(struct t4_vpd_hdr); 2989 vpdr = (const void *)(vpd + offset); 2990 tag = vpdr->vpdr_tag; 2991 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2992 while (region--) { 2993 offset += sizeof(struct t4_vpdr_hdr) + len; 2994 vpdr = (const void *)(vpd + offset); 2995 if (++tag != vpdr->vpdr_tag) 2996 return -ENOENT; 2997 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2998 } 2999 offset += sizeof(struct t4_vpdr_hdr); 3000 3001 if (offset + len > VPD_LEN) { 3002 return -ENOENT; 3003 } 3004 3005 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 3006 if (memcmp(vpd + i , kw , 2) == 0){ 3007 i += VPD_INFO_FLD_HDR_SIZE; 3008 return i; 3009 } 3010 3011 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 3012 } 3013 3014 return -ENOENT; 3015 } 3016 3017 3018 /** 3019 * get_vpd_params - read VPD parameters from VPD EEPROM 3020 * @adapter: adapter to read 3021 * @p: where to store the parameters 3022 * @vpd: caller provided temporary space to read the VPD into 3023 * 3024 * Reads card parameters stored in VPD EEPROM. 3025 */ 3026 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3027 uint16_t device_id, u32 *buf) 3028 { 3029 int i, ret, addr; 3030 int ec, sn, pn, na, md; 3031 u8 csum; 3032 const u8 *vpd = (const u8 *)buf; 3033 3034 /* 3035 * Card information normally starts at VPD_BASE but early cards had 3036 * it at 0. 3037 */ 3038 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3039 if (ret) 3040 return (ret); 3041 3042 /* 3043 * The VPD shall have a unique identifier specified by the PCI SIG. 3044 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3045 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3046 * is expected to automatically put this entry at the 3047 * beginning of the VPD. 3048 */ 3049 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3050 3051 for (i = 0; i < VPD_LEN; i += 4) { 3052 ret = t4_seeprom_read(adapter, addr + i, buf++); 3053 if (ret) 3054 return ret; 3055 } 3056 3057 #define FIND_VPD_KW(var,name) do { \ 3058 var = get_vpd_keyword_val(vpd, name, 0); \ 3059 if (var < 0) { \ 3060 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3061 return -EINVAL; \ 3062 } \ 3063 } while (0) 3064 3065 FIND_VPD_KW(i, "RV"); 3066 for (csum = 0; i >= 0; i--) 3067 csum += vpd[i]; 3068 3069 if (csum) { 3070 CH_ERR(adapter, 3071 "corrupted VPD EEPROM, actual csum %u\n", csum); 3072 return -EINVAL; 3073 } 3074 3075 FIND_VPD_KW(ec, "EC"); 3076 FIND_VPD_KW(sn, "SN"); 3077 FIND_VPD_KW(pn, "PN"); 3078 FIND_VPD_KW(na, "NA"); 3079 #undef FIND_VPD_KW 3080 3081 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3082 strstrip(p->id); 3083 memcpy(p->ec, vpd + ec, EC_LEN); 3084 strstrip(p->ec); 3085 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3086 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3087 strstrip(p->sn); 3088 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3089 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3090 strstrip((char *)p->pn); 3091 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3092 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3093 strstrip((char *)p->na); 3094 3095 if (device_id & 0x80) 3096 return 0; /* Custom card */ 3097 3098 md = get_vpd_keyword_val(vpd, "VF", 1); 3099 if (md < 0) { 3100 snprintf(p->md, sizeof(p->md), "unknown"); 3101 } else { 3102 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3103 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3104 strstrip((char *)p->md); 3105 } 3106 3107 return 0; 3108 } 3109 3110 /* serial flash and firmware constants and flash config file constants */ 3111 enum { 3112 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3113 3114 /* flash command opcodes */ 3115 SF_PROG_PAGE = 2, /* program 256B page */ 3116 SF_WR_DISABLE = 4, /* disable writes */ 3117 SF_RD_STATUS = 5, /* read status register */ 3118 SF_WR_ENABLE = 6, /* enable writes */ 3119 SF_RD_DATA_FAST = 0xb, /* read flash */ 3120 SF_RD_ID = 0x9f, /* read ID */ 3121 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3122 }; 3123 3124 /** 3125 * sf1_read - read data from the serial flash 3126 * @adapter: the adapter 3127 * @byte_cnt: number of bytes to read 3128 * @cont: whether another operation will be chained 3129 * @lock: whether to lock SF for PL access only 3130 * @valp: where to store the read data 3131 * 3132 * Reads up to 4 bytes of data from the serial flash. The location of 3133 * the read needs to be specified prior to calling this by issuing the 3134 * appropriate commands to the serial flash. 3135 */ 3136 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3137 int lock, u32 *valp) 3138 { 3139 int ret; 3140 3141 if (!byte_cnt || byte_cnt > 4) 3142 return -EINVAL; 3143 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3144 return -EBUSY; 3145 t4_write_reg(adapter, A_SF_OP, 3146 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3147 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3148 if (!ret) 3149 *valp = t4_read_reg(adapter, A_SF_DATA); 3150 return ret; 3151 } 3152 3153 /** 3154 * sf1_write - write data to the serial flash 3155 * @adapter: the adapter 3156 * @byte_cnt: number of bytes to write 3157 * @cont: whether another operation will be chained 3158 * @lock: whether to lock SF for PL access only 3159 * @val: value to write 3160 * 3161 * Writes up to 4 bytes of data to the serial flash. The location of 3162 * the write needs to be specified prior to calling this by issuing the 3163 * appropriate commands to the serial flash. 3164 */ 3165 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3166 int lock, u32 val) 3167 { 3168 if (!byte_cnt || byte_cnt > 4) 3169 return -EINVAL; 3170 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3171 return -EBUSY; 3172 t4_write_reg(adapter, A_SF_DATA, val); 3173 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3174 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3175 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3176 } 3177 3178 /** 3179 * flash_wait_op - wait for a flash operation to complete 3180 * @adapter: the adapter 3181 * @attempts: max number of polls of the status register 3182 * @delay: delay between polls in ms 3183 * 3184 * Wait for a flash operation to complete by polling the status register. 3185 */ 3186 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3187 { 3188 int ret; 3189 u32 status; 3190 3191 while (1) { 3192 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3193 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3194 return ret; 3195 if (!(status & 1)) 3196 return 0; 3197 if (--attempts == 0) 3198 return -EAGAIN; 3199 if (delay) 3200 msleep(delay); 3201 } 3202 } 3203 3204 /** 3205 * t4_read_flash - read words from serial flash 3206 * @adapter: the adapter 3207 * @addr: the start address for the read 3208 * @nwords: how many 32-bit words to read 3209 * @data: where to store the read data 3210 * @byte_oriented: whether to store data as bytes or as words 3211 * 3212 * Read the specified number of 32-bit words from the serial flash. 3213 * If @byte_oriented is set the read data is stored as a byte array 3214 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3215 * natural endianness. 3216 */ 3217 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3218 unsigned int nwords, u32 *data, int byte_oriented) 3219 { 3220 int ret; 3221 3222 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3223 return -EINVAL; 3224 3225 addr = swab32(addr) | SF_RD_DATA_FAST; 3226 3227 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3228 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3229 return ret; 3230 3231 for ( ; nwords; nwords--, data++) { 3232 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3233 if (nwords == 1) 3234 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3235 if (ret) 3236 return ret; 3237 if (byte_oriented) 3238 *data = (__force __u32)(cpu_to_be32(*data)); 3239 } 3240 return 0; 3241 } 3242 3243 /** 3244 * t4_write_flash - write up to a page of data to the serial flash 3245 * @adapter: the adapter 3246 * @addr: the start address to write 3247 * @n: length of data to write in bytes 3248 * @data: the data to write 3249 * @byte_oriented: whether to store data as bytes or as words 3250 * 3251 * Writes up to a page of data (256 bytes) to the serial flash starting 3252 * at the given address. All the data must be written to the same page. 3253 * If @byte_oriented is set the write data is stored as byte stream 3254 * (i.e. matches what on disk), otherwise in big-endian. 3255 */ 3256 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3257 unsigned int n, const u8 *data, int byte_oriented) 3258 { 3259 int ret; 3260 u32 buf[SF_PAGE_SIZE / 4]; 3261 unsigned int i, c, left, val, offset = addr & 0xff; 3262 3263 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3264 return -EINVAL; 3265 3266 val = swab32(addr) | SF_PROG_PAGE; 3267 3268 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3269 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3270 goto unlock; 3271 3272 for (left = n; left; left -= c) { 3273 c = min(left, 4U); 3274 for (val = 0, i = 0; i < c; ++i) 3275 val = (val << 8) + *data++; 3276 3277 if (!byte_oriented) 3278 val = cpu_to_be32(val); 3279 3280 ret = sf1_write(adapter, c, c != left, 1, val); 3281 if (ret) 3282 goto unlock; 3283 } 3284 ret = flash_wait_op(adapter, 8, 1); 3285 if (ret) 3286 goto unlock; 3287 3288 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3289 3290 /* Read the page to verify the write succeeded */ 3291 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3292 byte_oriented); 3293 if (ret) 3294 return ret; 3295 3296 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3297 CH_ERR(adapter, 3298 "failed to correctly write the flash page at %#x\n", 3299 addr); 3300 return -EIO; 3301 } 3302 return 0; 3303 3304 unlock: 3305 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3306 return ret; 3307 } 3308 3309 /** 3310 * t4_get_fw_version - read the firmware version 3311 * @adapter: the adapter 3312 * @vers: where to place the version 3313 * 3314 * Reads the FW version from flash. 3315 */ 3316 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3317 { 3318 return t4_read_flash(adapter, FLASH_FW_START + 3319 offsetof(struct fw_hdr, fw_ver), 1, 3320 vers, 0); 3321 } 3322 3323 /** 3324 * t4_get_bs_version - read the firmware bootstrap version 3325 * @adapter: the adapter 3326 * @vers: where to place the version 3327 * 3328 * Reads the FW Bootstrap version from flash. 3329 */ 3330 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3331 { 3332 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3333 offsetof(struct fw_hdr, fw_ver), 1, 3334 vers, 0); 3335 } 3336 3337 /** 3338 * t4_get_tp_version - read the TP microcode version 3339 * @adapter: the adapter 3340 * @vers: where to place the version 3341 * 3342 * Reads the TP microcode version from flash. 3343 */ 3344 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3345 { 3346 return t4_read_flash(adapter, FLASH_FW_START + 3347 offsetof(struct fw_hdr, tp_microcode_ver), 3348 1, vers, 0); 3349 } 3350 3351 /** 3352 * t4_get_exprom_version - return the Expansion ROM version (if any) 3353 * @adapter: the adapter 3354 * @vers: where to place the version 3355 * 3356 * Reads the Expansion ROM header from FLASH and returns the version 3357 * number (if present) through the @vers return value pointer. We return 3358 * this in the Firmware Version Format since it's convenient. Return 3359 * 0 on success, -ENOENT if no Expansion ROM is present. 3360 */ 3361 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 3362 { 3363 struct exprom_header { 3364 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3365 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3366 } *hdr; 3367 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3368 sizeof(u32))]; 3369 int ret; 3370 3371 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 3372 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3373 0); 3374 if (ret) 3375 return ret; 3376 3377 hdr = (struct exprom_header *)exprom_header_buf; 3378 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3379 return -ENOENT; 3380 3381 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3382 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3383 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3384 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3385 return 0; 3386 } 3387 3388 /** 3389 * t4_get_scfg_version - return the Serial Configuration version 3390 * @adapter: the adapter 3391 * @vers: where to place the version 3392 * 3393 * Reads the Serial Configuration Version via the Firmware interface 3394 * (thus this can only be called once we're ready to issue Firmware 3395 * commands). The format of the Serial Configuration version is 3396 * adapter specific. Returns 0 on success, an error on failure. 3397 * 3398 * Note that early versions of the Firmware didn't include the ability 3399 * to retrieve the Serial Configuration version, so we zero-out the 3400 * return-value parameter in that case to avoid leaving it with 3401 * garbage in it. 3402 * 3403 * Also note that the Firmware will return its cached copy of the Serial 3404 * Initialization Revision ID, not the actual Revision ID as written in 3405 * the Serial EEPROM. This is only an issue if a new VPD has been written 3406 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3407 * it's best to defer calling this routine till after a FW_RESET_CMD has 3408 * been issued if the Host Driver will be performing a full adapter 3409 * initialization. 3410 */ 3411 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3412 { 3413 u32 scfgrev_param; 3414 int ret; 3415 3416 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3417 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3418 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3419 1, &scfgrev_param, vers); 3420 if (ret) 3421 *vers = 0; 3422 return ret; 3423 } 3424 3425 /** 3426 * t4_get_vpd_version - return the VPD version 3427 * @adapter: the adapter 3428 * @vers: where to place the version 3429 * 3430 * Reads the VPD via the Firmware interface (thus this can only be called 3431 * once we're ready to issue Firmware commands). The format of the 3432 * VPD version is adapter specific. Returns 0 on success, an error on 3433 * failure. 3434 * 3435 * Note that early versions of the Firmware didn't include the ability 3436 * to retrieve the VPD version, so we zero-out the return-value parameter 3437 * in that case to avoid leaving it with garbage in it. 3438 * 3439 * Also note that the Firmware will return its cached copy of the VPD 3440 * Revision ID, not the actual Revision ID as written in the Serial 3441 * EEPROM. This is only an issue if a new VPD has been written and the 3442 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3443 * to defer calling this routine till after a FW_RESET_CMD has been issued 3444 * if the Host Driver will be performing a full adapter initialization. 3445 */ 3446 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3447 { 3448 u32 vpdrev_param; 3449 int ret; 3450 3451 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3452 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3453 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3454 1, &vpdrev_param, vers); 3455 if (ret) 3456 *vers = 0; 3457 return ret; 3458 } 3459 3460 /** 3461 * t4_get_version_info - extract various chip/firmware version information 3462 * @adapter: the adapter 3463 * 3464 * Reads various chip/firmware version numbers and stores them into the 3465 * adapter Adapter Parameters structure. If any of the efforts fails 3466 * the first failure will be returned, but all of the version numbers 3467 * will be read. 3468 */ 3469 int t4_get_version_info(struct adapter *adapter) 3470 { 3471 int ret = 0; 3472 3473 #define FIRST_RET(__getvinfo) \ 3474 do { \ 3475 int __ret = __getvinfo; \ 3476 if (__ret && !ret) \ 3477 ret = __ret; \ 3478 } while (0) 3479 3480 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3481 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3482 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3483 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3484 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3485 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3486 3487 #undef FIRST_RET 3488 3489 return ret; 3490 } 3491 3492 /** 3493 * t4_flash_erase_sectors - erase a range of flash sectors 3494 * @adapter: the adapter 3495 * @start: the first sector to erase 3496 * @end: the last sector to erase 3497 * 3498 * Erases the sectors in the given inclusive range. 3499 */ 3500 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3501 { 3502 int ret = 0; 3503 3504 if (end >= adapter->params.sf_nsec) 3505 return -EINVAL; 3506 3507 while (start <= end) { 3508 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3509 (ret = sf1_write(adapter, 4, 0, 1, 3510 SF_ERASE_SECTOR | (start << 8))) != 0 || 3511 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3512 CH_ERR(adapter, 3513 "erase of flash sector %d failed, error %d\n", 3514 start, ret); 3515 break; 3516 } 3517 start++; 3518 } 3519 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3520 return ret; 3521 } 3522 3523 /** 3524 * t4_flash_cfg_addr - return the address of the flash configuration file 3525 * @adapter: the adapter 3526 * 3527 * Return the address within the flash where the Firmware Configuration 3528 * File is stored, or an error if the device FLASH is too small to contain 3529 * a Firmware Configuration File. 3530 */ 3531 int t4_flash_cfg_addr(struct adapter *adapter) 3532 { 3533 /* 3534 * If the device FLASH isn't large enough to hold a Firmware 3535 * Configuration File, return an error. 3536 */ 3537 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3538 return -ENOSPC; 3539 3540 return FLASH_CFG_START; 3541 } 3542 3543 /* 3544 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3545 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3546 * and emit an error message for mismatched firmware to save our caller the 3547 * effort ... 3548 */ 3549 static int t4_fw_matches_chip(struct adapter *adap, 3550 const struct fw_hdr *hdr) 3551 { 3552 /* 3553 * The expression below will return FALSE for any unsupported adapter 3554 * which will keep us "honest" in the future ... 3555 */ 3556 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3557 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3558 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3559 return 1; 3560 3561 CH_ERR(adap, 3562 "FW image (%d) is not suitable for this adapter (%d)\n", 3563 hdr->chip, chip_id(adap)); 3564 return 0; 3565 } 3566 3567 /** 3568 * t4_load_fw - download firmware 3569 * @adap: the adapter 3570 * @fw_data: the firmware image to write 3571 * @size: image size 3572 * 3573 * Write the supplied firmware image to the card's serial flash. 3574 */ 3575 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3576 { 3577 u32 csum; 3578 int ret, addr; 3579 unsigned int i; 3580 u8 first_page[SF_PAGE_SIZE]; 3581 const u32 *p = (const u32 *)fw_data; 3582 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3583 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3584 unsigned int fw_start_sec; 3585 unsigned int fw_start; 3586 unsigned int fw_size; 3587 3588 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3589 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3590 fw_start = FLASH_FWBOOTSTRAP_START; 3591 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3592 } else { 3593 fw_start_sec = FLASH_FW_START_SEC; 3594 fw_start = FLASH_FW_START; 3595 fw_size = FLASH_FW_MAX_SIZE; 3596 } 3597 3598 if (!size) { 3599 CH_ERR(adap, "FW image has no data\n"); 3600 return -EINVAL; 3601 } 3602 if (size & 511) { 3603 CH_ERR(adap, 3604 "FW image size not multiple of 512 bytes\n"); 3605 return -EINVAL; 3606 } 3607 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3608 CH_ERR(adap, 3609 "FW image size differs from size in FW header\n"); 3610 return -EINVAL; 3611 } 3612 if (size > fw_size) { 3613 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3614 fw_size); 3615 return -EFBIG; 3616 } 3617 if (!t4_fw_matches_chip(adap, hdr)) 3618 return -EINVAL; 3619 3620 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3621 csum += be32_to_cpu(p[i]); 3622 3623 if (csum != 0xffffffff) { 3624 CH_ERR(adap, 3625 "corrupted firmware image, checksum %#x\n", csum); 3626 return -EINVAL; 3627 } 3628 3629 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3630 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3631 if (ret) 3632 goto out; 3633 3634 /* 3635 * We write the correct version at the end so the driver can see a bad 3636 * version if the FW write fails. Start by writing a copy of the 3637 * first page with a bad version. 3638 */ 3639 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3640 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3641 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3642 if (ret) 3643 goto out; 3644 3645 addr = fw_start; 3646 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3647 addr += SF_PAGE_SIZE; 3648 fw_data += SF_PAGE_SIZE; 3649 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3650 if (ret) 3651 goto out; 3652 } 3653 3654 ret = t4_write_flash(adap, 3655 fw_start + offsetof(struct fw_hdr, fw_ver), 3656 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3657 out: 3658 if (ret) 3659 CH_ERR(adap, "firmware download failed, error %d\n", 3660 ret); 3661 return ret; 3662 } 3663 3664 /** 3665 * t4_fwcache - firmware cache operation 3666 * @adap: the adapter 3667 * @op : the operation (flush or flush and invalidate) 3668 */ 3669 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3670 { 3671 struct fw_params_cmd c; 3672 3673 memset(&c, 0, sizeof(c)); 3674 c.op_to_vfn = 3675 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3676 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3677 V_FW_PARAMS_CMD_PFN(adap->pf) | 3678 V_FW_PARAMS_CMD_VFN(0)); 3679 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3680 c.param[0].mnem = 3681 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3682 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3683 c.param[0].val = (__force __be32)op; 3684 3685 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3686 } 3687 3688 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3689 unsigned int *pif_req_wrptr, 3690 unsigned int *pif_rsp_wrptr) 3691 { 3692 int i, j; 3693 u32 cfg, val, req, rsp; 3694 3695 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3696 if (cfg & F_LADBGEN) 3697 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3698 3699 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3700 req = G_POLADBGWRPTR(val); 3701 rsp = G_PILADBGWRPTR(val); 3702 if (pif_req_wrptr) 3703 *pif_req_wrptr = req; 3704 if (pif_rsp_wrptr) 3705 *pif_rsp_wrptr = rsp; 3706 3707 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3708 for (j = 0; j < 6; j++) { 3709 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3710 V_PILADBGRDPTR(rsp)); 3711 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3712 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3713 req++; 3714 rsp++; 3715 } 3716 req = (req + 2) & M_POLADBGRDPTR; 3717 rsp = (rsp + 2) & M_PILADBGRDPTR; 3718 } 3719 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3720 } 3721 3722 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3723 { 3724 u32 cfg; 3725 int i, j, idx; 3726 3727 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3728 if (cfg & F_LADBGEN) 3729 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3730 3731 for (i = 0; i < CIM_MALA_SIZE; i++) { 3732 for (j = 0; j < 5; j++) { 3733 idx = 8 * i + j; 3734 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3735 V_PILADBGRDPTR(idx)); 3736 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3737 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3738 } 3739 } 3740 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3741 } 3742 3743 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3744 { 3745 unsigned int i, j; 3746 3747 for (i = 0; i < 8; i++) { 3748 u32 *p = la_buf + i; 3749 3750 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3751 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3752 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3753 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3754 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3755 } 3756 } 3757 3758 /** 3759 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3760 * @caps16: a 16-bit Port Capabilities value 3761 * 3762 * Returns the equivalent 32-bit Port Capabilities value. 3763 */ 3764 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3765 { 3766 uint32_t caps32 = 0; 3767 3768 #define CAP16_TO_CAP32(__cap) \ 3769 do { \ 3770 if (caps16 & FW_PORT_CAP_##__cap) \ 3771 caps32 |= FW_PORT_CAP32_##__cap; \ 3772 } while (0) 3773 3774 CAP16_TO_CAP32(SPEED_100M); 3775 CAP16_TO_CAP32(SPEED_1G); 3776 CAP16_TO_CAP32(SPEED_25G); 3777 CAP16_TO_CAP32(SPEED_10G); 3778 CAP16_TO_CAP32(SPEED_40G); 3779 CAP16_TO_CAP32(SPEED_100G); 3780 CAP16_TO_CAP32(FC_RX); 3781 CAP16_TO_CAP32(FC_TX); 3782 CAP16_TO_CAP32(ANEG); 3783 CAP16_TO_CAP32(FORCE_PAUSE); 3784 CAP16_TO_CAP32(MDIAUTO); 3785 CAP16_TO_CAP32(MDISTRAIGHT); 3786 CAP16_TO_CAP32(FEC_RS); 3787 CAP16_TO_CAP32(FEC_BASER_RS); 3788 CAP16_TO_CAP32(802_3_PAUSE); 3789 CAP16_TO_CAP32(802_3_ASM_DIR); 3790 3791 #undef CAP16_TO_CAP32 3792 3793 return caps32; 3794 } 3795 3796 /** 3797 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3798 * @caps32: a 32-bit Port Capabilities value 3799 * 3800 * Returns the equivalent 16-bit Port Capabilities value. Note that 3801 * not all 32-bit Port Capabilities can be represented in the 16-bit 3802 * Port Capabilities and some fields/values may not make it. 3803 */ 3804 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3805 { 3806 uint16_t caps16 = 0; 3807 3808 #define CAP32_TO_CAP16(__cap) \ 3809 do { \ 3810 if (caps32 & FW_PORT_CAP32_##__cap) \ 3811 caps16 |= FW_PORT_CAP_##__cap; \ 3812 } while (0) 3813 3814 CAP32_TO_CAP16(SPEED_100M); 3815 CAP32_TO_CAP16(SPEED_1G); 3816 CAP32_TO_CAP16(SPEED_10G); 3817 CAP32_TO_CAP16(SPEED_25G); 3818 CAP32_TO_CAP16(SPEED_40G); 3819 CAP32_TO_CAP16(SPEED_100G); 3820 CAP32_TO_CAP16(FC_RX); 3821 CAP32_TO_CAP16(FC_TX); 3822 CAP32_TO_CAP16(802_3_PAUSE); 3823 CAP32_TO_CAP16(802_3_ASM_DIR); 3824 CAP32_TO_CAP16(ANEG); 3825 CAP32_TO_CAP16(FORCE_PAUSE); 3826 CAP32_TO_CAP16(MDIAUTO); 3827 CAP32_TO_CAP16(MDISTRAIGHT); 3828 CAP32_TO_CAP16(FEC_RS); 3829 CAP32_TO_CAP16(FEC_BASER_RS); 3830 3831 #undef CAP32_TO_CAP16 3832 3833 return caps16; 3834 } 3835 3836 static bool 3837 is_bt(struct port_info *pi) 3838 { 3839 3840 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 3841 pi->port_type == FW_PORT_TYPE_BT_XFI || 3842 pi->port_type == FW_PORT_TYPE_BT_XAUI); 3843 } 3844 3845 /** 3846 * t4_link_l1cfg - apply link configuration to MAC/PHY 3847 * @phy: the PHY to setup 3848 * @mac: the MAC to setup 3849 * @lc: the requested link configuration 3850 * 3851 * Set up a port's MAC and PHY according to a desired link configuration. 3852 * - If the PHY can auto-negotiate first decide what to advertise, then 3853 * enable/disable auto-negotiation as desired, and reset. 3854 * - If the PHY does not auto-negotiate just reset it. 3855 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3856 * otherwise do it later based on the outcome of auto-negotiation. 3857 */ 3858 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3859 struct link_config *lc) 3860 { 3861 struct fw_port_cmd c; 3862 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3863 unsigned int aneg, fc, fec, speed, rcap; 3864 3865 fc = 0; 3866 if (lc->requested_fc & PAUSE_RX) 3867 fc |= FW_PORT_CAP32_FC_RX; 3868 if (lc->requested_fc & PAUSE_TX) 3869 fc |= FW_PORT_CAP32_FC_TX; 3870 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3871 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3872 3873 fec = 0; 3874 if (lc->requested_fec == FEC_AUTO) 3875 fec = lc->fec_hint; 3876 else { 3877 if (lc->requested_fec & FEC_RS) 3878 fec |= FW_PORT_CAP32_FEC_RS; 3879 if (lc->requested_fec & FEC_BASER_RS) 3880 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3881 } 3882 3883 if (lc->requested_aneg == AUTONEG_DISABLE) 3884 aneg = 0; 3885 else if (lc->requested_aneg == AUTONEG_ENABLE) 3886 aneg = FW_PORT_CAP32_ANEG; 3887 else 3888 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3889 3890 if (aneg) { 3891 speed = lc->supported & V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3892 } else if (lc->requested_speed != 0) 3893 speed = speed_to_fwcap(lc->requested_speed); 3894 else 3895 speed = fwcap_top_speed(lc->supported); 3896 3897 /* Force AN on for BT cards. */ 3898 if (is_bt(adap->port[port])) 3899 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3900 3901 rcap = aneg | speed | fc | fec; 3902 if ((rcap | lc->supported) != lc->supported) { 3903 #ifdef INVARIANTS 3904 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x\n", rcap, 3905 lc->supported); 3906 #endif 3907 rcap &= lc->supported; 3908 } 3909 rcap |= mdi; 3910 3911 memset(&c, 0, sizeof(c)); 3912 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3913 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3914 V_FW_PORT_CMD_PORTID(port)); 3915 if (adap->params.port_caps32) { 3916 c.action_to_len16 = 3917 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3918 FW_LEN16(c)); 3919 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3920 } else { 3921 c.action_to_len16 = 3922 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3923 FW_LEN16(c)); 3924 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3925 } 3926 3927 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3928 } 3929 3930 /** 3931 * t4_restart_aneg - restart autonegotiation 3932 * @adap: the adapter 3933 * @mbox: mbox to use for the FW command 3934 * @port: the port id 3935 * 3936 * Restarts autonegotiation for the selected port. 3937 */ 3938 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3939 { 3940 struct fw_port_cmd c; 3941 3942 memset(&c, 0, sizeof(c)); 3943 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3944 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3945 V_FW_PORT_CMD_PORTID(port)); 3946 c.action_to_len16 = 3947 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3948 FW_LEN16(c)); 3949 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3950 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3951 } 3952 3953 typedef void (*int_handler_t)(struct adapter *adap); 3954 3955 struct intr_info { 3956 unsigned int mask; /* bits to check in interrupt status */ 3957 const char *msg; /* message to print or NULL */ 3958 short stat_idx; /* stat counter to increment or -1 */ 3959 unsigned short fatal; /* whether the condition reported is fatal */ 3960 int_handler_t int_handler; /* platform-specific int handler */ 3961 }; 3962 3963 /** 3964 * t4_handle_intr_status - table driven interrupt handler 3965 * @adapter: the adapter that generated the interrupt 3966 * @reg: the interrupt status register to process 3967 * @acts: table of interrupt actions 3968 * 3969 * A table driven interrupt handler that applies a set of masks to an 3970 * interrupt status word and performs the corresponding actions if the 3971 * interrupts described by the mask have occurred. The actions include 3972 * optionally emitting a warning or alert message. The table is terminated 3973 * by an entry specifying mask 0. Returns the number of fatal interrupt 3974 * conditions. 3975 */ 3976 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 3977 const struct intr_info *acts) 3978 { 3979 int fatal = 0; 3980 unsigned int mask = 0; 3981 unsigned int status = t4_read_reg(adapter, reg); 3982 3983 for ( ; acts->mask; ++acts) { 3984 if (!(status & acts->mask)) 3985 continue; 3986 if (acts->fatal) { 3987 fatal++; 3988 CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, 3989 status & acts->mask); 3990 } else if (acts->msg) 3991 CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg, 3992 status & acts->mask); 3993 if (acts->int_handler) 3994 acts->int_handler(adapter); 3995 mask |= acts->mask; 3996 } 3997 status &= mask; 3998 if (status) /* clear processed interrupts */ 3999 t4_write_reg(adapter, reg, status); 4000 return fatal; 4001 } 4002 4003 /* 4004 * Interrupt handler for the PCIE module. 4005 */ 4006 static void pcie_intr_handler(struct adapter *adapter) 4007 { 4008 static const struct intr_info sysbus_intr_info[] = { 4009 { F_RNPP, "RXNP array parity error", -1, 1 }, 4010 { F_RPCP, "RXPC array parity error", -1, 1 }, 4011 { F_RCIP, "RXCIF array parity error", -1, 1 }, 4012 { F_RCCP, "Rx completions control array parity error", -1, 1 }, 4013 { F_RFTP, "RXFT array parity error", -1, 1 }, 4014 { 0 } 4015 }; 4016 static const struct intr_info pcie_port_intr_info[] = { 4017 { F_TPCP, "TXPC array parity error", -1, 1 }, 4018 { F_TNPP, "TXNP array parity error", -1, 1 }, 4019 { F_TFTP, "TXFT array parity error", -1, 1 }, 4020 { F_TCAP, "TXCA array parity error", -1, 1 }, 4021 { F_TCIP, "TXCIF array parity error", -1, 1 }, 4022 { F_RCAP, "RXCA array parity error", -1, 1 }, 4023 { F_OTDD, "outbound request TLP discarded", -1, 1 }, 4024 { F_RDPE, "Rx data parity error", -1, 1 }, 4025 { F_TDUE, "Tx uncorrectable data error", -1, 1 }, 4026 { 0 } 4027 }; 4028 static const struct intr_info pcie_intr_info[] = { 4029 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 4030 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 4031 { F_MSIDATAPERR, "MSI data parity error", -1, 1 }, 4032 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 4033 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 4034 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 4035 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 4036 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 4037 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 4038 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 4039 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 4040 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 4041 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 4042 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 4043 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 4044 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 4045 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 4046 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 4047 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 4048 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 4049 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 4050 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 4051 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 }, 4052 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 4053 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 4054 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 }, 4055 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 }, 4056 { F_PCIESINT, "PCI core secondary fault", -1, 1 }, 4057 { F_PCIEPINT, "PCI core primary fault", -1, 1 }, 4058 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1, 4059 0 }, 4060 { 0 } 4061 }; 4062 4063 static const struct intr_info t5_pcie_intr_info[] = { 4064 { F_MSTGRPPERR, "Master Response Read Queue parity error", 4065 -1, 1 }, 4066 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 4067 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 4068 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 4069 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 4070 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 4071 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 4072 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 4073 -1, 1 }, 4074 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 4075 -1, 1 }, 4076 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 4077 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 4078 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 4079 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 4080 { F_DREQWRPERR, "PCI DMA channel write request parity error", 4081 -1, 1 }, 4082 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 4083 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 4084 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 4085 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 4086 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 4087 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 4088 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 4089 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 4090 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 4091 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 4092 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 4093 -1, 1 }, 4094 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 4095 -1, 1 }, 4096 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 4097 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 4098 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 4099 { F_READRSPERR, "Outbound read error", -1, 4100 0 }, 4101 { 0 } 4102 }; 4103 4104 int fat; 4105 4106 if (is_t4(adapter)) 4107 fat = t4_handle_intr_status(adapter, 4108 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4109 sysbus_intr_info) + 4110 t4_handle_intr_status(adapter, 4111 A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4112 pcie_port_intr_info) + 4113 t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 4114 pcie_intr_info); 4115 else 4116 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 4117 t5_pcie_intr_info); 4118 if (fat) 4119 t4_fatal_err(adapter); 4120 } 4121 4122 /* 4123 * TP interrupt handler. 4124 */ 4125 static void tp_intr_handler(struct adapter *adapter) 4126 { 4127 static const struct intr_info tp_intr_info[] = { 4128 { 0x3fffffff, "TP parity error", -1, 1 }, 4129 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 4130 { 0 } 4131 }; 4132 4133 if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info)) 4134 t4_fatal_err(adapter); 4135 } 4136 4137 /* 4138 * SGE interrupt handler. 4139 */ 4140 static void sge_intr_handler(struct adapter *adapter) 4141 { 4142 u64 v; 4143 u32 err; 4144 4145 static const struct intr_info sge_intr_info[] = { 4146 { F_ERR_CPL_EXCEED_IQE_SIZE, 4147 "SGE received CPL exceeding IQE size", -1, 1 }, 4148 { F_ERR_INVALID_CIDX_INC, 4149 "SGE GTS CIDX increment too large", -1, 0 }, 4150 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 4151 { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, 4152 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4153 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 4154 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 4155 0 }, 4156 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 4157 0 }, 4158 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 4159 0 }, 4160 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 4161 0 }, 4162 { F_ERR_ING_CTXT_PRIO, 4163 "SGE too many priority ingress contexts", -1, 0 }, 4164 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 4165 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 4166 { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | 4167 F_ERR_PCIE_ERROR2 | F_ERR_PCIE_ERROR3, 4168 "SGE PCIe error for a DBP thread", -1, 0 }, 4169 { 0 } 4170 }; 4171 4172 static const struct intr_info t4t5_sge_intr_info[] = { 4173 { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, 4174 { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, 4175 { F_ERR_EGR_CTXT_PRIO, 4176 "SGE too many priority egress contexts", -1, 0 }, 4177 { 0 } 4178 }; 4179 4180 /* 4181 * For now, treat below interrupts as fatal so that we disable SGE and 4182 * get better debug */ 4183 static const struct intr_info t6_sge_intr_info[] = { 4184 { F_FATAL_WRE_LEN, 4185 "SGE Actual WRE packet is less than advertized length", 4186 -1, 1 }, 4187 { 0 } 4188 }; 4189 4190 v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | 4191 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); 4192 if (v) { 4193 CH_ALERT(adapter, "SGE parity error (%#llx)\n", 4194 (unsigned long long)v); 4195 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); 4196 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); 4197 } 4198 4199 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info); 4200 if (chip_id(adapter) <= CHELSIO_T5) 4201 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4202 t4t5_sge_intr_info); 4203 else 4204 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4205 t6_sge_intr_info); 4206 4207 err = t4_read_reg(adapter, A_SGE_ERROR_STATS); 4208 if (err & F_ERROR_QID_VALID) { 4209 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err)); 4210 if (err & F_UNCAPTURED_ERROR) 4211 CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4212 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID | 4213 F_UNCAPTURED_ERROR); 4214 } 4215 4216 if (v != 0) 4217 t4_fatal_err(adapter); 4218 } 4219 4220 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\ 4221 F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR) 4222 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\ 4223 F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR) 4224 4225 /* 4226 * CIM interrupt handler. 4227 */ 4228 static void cim_intr_handler(struct adapter *adapter) 4229 { 4230 static const struct intr_info cim_intr_info[] = { 4231 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 4232 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 4233 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 4234 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 4235 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 4236 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 4237 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 4238 { F_TIMER0INT, "CIM TIMER0 interrupt", -1, 1 }, 4239 { 0 } 4240 }; 4241 static const struct intr_info cim_upintr_info[] = { 4242 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 4243 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 4244 { F_ILLWRINT, "CIM illegal write", -1, 1 }, 4245 { F_ILLRDINT, "CIM illegal read", -1, 1 }, 4246 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 4247 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 4248 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 4249 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 4250 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 4251 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 4252 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 4253 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 4254 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 4255 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 4256 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 4257 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 4258 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 4259 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 4260 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 4261 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 4262 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 4263 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 4264 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 4265 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 4266 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 4267 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 4268 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 4269 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 4270 { 0 } 4271 }; 4272 u32 val, fw_err; 4273 int fat; 4274 4275 fw_err = t4_read_reg(adapter, A_PCIE_FW); 4276 if (fw_err & F_PCIE_FW_ERR) 4277 t4_report_fw_error(adapter); 4278 4279 /* When the Firmware detects an internal error which normally wouldn't 4280 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4281 * to make sure the Host sees the Firmware Crash. So if we have a 4282 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4283 * interrupt. 4284 */ 4285 val = t4_read_reg(adapter, A_CIM_HOST_INT_CAUSE); 4286 if (val & F_TIMER0INT) 4287 if (!(fw_err & F_PCIE_FW_ERR) || 4288 (G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) 4289 t4_write_reg(adapter, A_CIM_HOST_INT_CAUSE, 4290 F_TIMER0INT); 4291 4292 fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 4293 cim_intr_info) + 4294 t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE, 4295 cim_upintr_info); 4296 if (fat) 4297 t4_fatal_err(adapter); 4298 } 4299 4300 /* 4301 * ULP RX interrupt handler. 4302 */ 4303 static void ulprx_intr_handler(struct adapter *adapter) 4304 { 4305 static const struct intr_info ulprx_intr_info[] = { 4306 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 }, 4307 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 }, 4308 { 0x7fffff, "ULPRX parity error", -1, 1 }, 4309 { 0 } 4310 }; 4311 4312 if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info)) 4313 t4_fatal_err(adapter); 4314 } 4315 4316 /* 4317 * ULP TX interrupt handler. 4318 */ 4319 static void ulptx_intr_handler(struct adapter *adapter) 4320 { 4321 static const struct intr_info ulptx_intr_info[] = { 4322 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 4323 0 }, 4324 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 4325 0 }, 4326 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 4327 0 }, 4328 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 4329 0 }, 4330 { 0xfffffff, "ULPTX parity error", -1, 1 }, 4331 { 0 } 4332 }; 4333 4334 if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info)) 4335 t4_fatal_err(adapter); 4336 } 4337 4338 /* 4339 * PM TX interrupt handler. 4340 */ 4341 static void pmtx_intr_handler(struct adapter *adapter) 4342 { 4343 static const struct intr_info pmtx_intr_info[] = { 4344 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 4345 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 4346 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 4347 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 4348 { 0xffffff0, "PMTX framing error", -1, 1 }, 4349 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 4350 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 4351 1 }, 4352 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 4353 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 4354 { 0 } 4355 }; 4356 4357 if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info)) 4358 t4_fatal_err(adapter); 4359 } 4360 4361 /* 4362 * PM RX interrupt handler. 4363 */ 4364 static void pmrx_intr_handler(struct adapter *adapter) 4365 { 4366 static const struct intr_info pmrx_intr_info[] = { 4367 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 4368 { 0x3ffff0, "PMRX framing error", -1, 1 }, 4369 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 4370 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 4371 1 }, 4372 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 4373 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 4374 { 0 } 4375 }; 4376 4377 if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info)) 4378 t4_fatal_err(adapter); 4379 } 4380 4381 /* 4382 * CPL switch interrupt handler. 4383 */ 4384 static void cplsw_intr_handler(struct adapter *adapter) 4385 { 4386 static const struct intr_info cplsw_intr_info[] = { 4387 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 4388 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 4389 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 4390 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 4391 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 4392 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 4393 { 0 } 4394 }; 4395 4396 if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info)) 4397 t4_fatal_err(adapter); 4398 } 4399 4400 /* 4401 * LE interrupt handler. 4402 */ 4403 static void le_intr_handler(struct adapter *adap) 4404 { 4405 unsigned int chip_ver = chip_id(adap); 4406 static const struct intr_info le_intr_info[] = { 4407 { F_LIPMISS, "LE LIP miss", -1, 0 }, 4408 { F_LIP0, "LE 0 LIP error", -1, 0 }, 4409 { F_PARITYERR, "LE parity error", -1, 1 }, 4410 { F_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4411 { F_REQQPARERR, "LE request queue parity error", -1, 1 }, 4412 { 0 } 4413 }; 4414 4415 static const struct intr_info t6_le_intr_info[] = { 4416 { F_T6_LIPMISS, "LE LIP miss", -1, 0 }, 4417 { F_T6_LIP0, "LE 0 LIP error", -1, 0 }, 4418 { F_TCAMINTPERR, "LE parity error", -1, 1 }, 4419 { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4420 { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 }, 4421 { 0 } 4422 }; 4423 4424 if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, 4425 (chip_ver <= CHELSIO_T5) ? 4426 le_intr_info : t6_le_intr_info)) 4427 t4_fatal_err(adap); 4428 } 4429 4430 /* 4431 * MPS interrupt handler. 4432 */ 4433 static void mps_intr_handler(struct adapter *adapter) 4434 { 4435 static const struct intr_info mps_rx_intr_info[] = { 4436 { 0xffffff, "MPS Rx parity error", -1, 1 }, 4437 { 0 } 4438 }; 4439 static const struct intr_info mps_tx_intr_info[] = { 4440 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 }, 4441 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 4442 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error", 4443 -1, 1 }, 4444 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error", 4445 -1, 1 }, 4446 { F_BUBBLE, "MPS Tx underflow", -1, 1 }, 4447 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 4448 { F_FRMERR, "MPS Tx framing error", -1, 1 }, 4449 { 0 } 4450 }; 4451 static const struct intr_info mps_trc_intr_info[] = { 4452 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 }, 4453 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1, 4454 1 }, 4455 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 }, 4456 { 0 } 4457 }; 4458 static const struct intr_info mps_stat_sram_intr_info[] = { 4459 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 4460 { 0 } 4461 }; 4462 static const struct intr_info mps_stat_tx_intr_info[] = { 4463 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 4464 { 0 } 4465 }; 4466 static const struct intr_info mps_stat_rx_intr_info[] = { 4467 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 4468 { 0 } 4469 }; 4470 static const struct intr_info mps_cls_intr_info[] = { 4471 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 4472 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 4473 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 4474 { 0 } 4475 }; 4476 4477 int fat; 4478 4479 fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE, 4480 mps_rx_intr_info) + 4481 t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE, 4482 mps_tx_intr_info) + 4483 t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE, 4484 mps_trc_intr_info) + 4485 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4486 mps_stat_sram_intr_info) + 4487 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4488 mps_stat_tx_intr_info) + 4489 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4490 mps_stat_rx_intr_info) + 4491 t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE, 4492 mps_cls_intr_info); 4493 4494 t4_write_reg(adapter, A_MPS_INT_CAUSE, 0); 4495 t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ 4496 if (fat) 4497 t4_fatal_err(adapter); 4498 } 4499 4500 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \ 4501 F_ECC_UE_INT_CAUSE) 4502 4503 /* 4504 * EDC/MC interrupt handler. 4505 */ 4506 static void mem_intr_handler(struct adapter *adapter, int idx) 4507 { 4508 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; 4509 4510 unsigned int addr, cnt_addr, v; 4511 4512 if (idx <= MEM_EDC1) { 4513 addr = EDC_REG(A_EDC_INT_CAUSE, idx); 4514 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); 4515 } else if (idx == MEM_MC) { 4516 if (is_t4(adapter)) { 4517 addr = A_MC_INT_CAUSE; 4518 cnt_addr = A_MC_ECC_STATUS; 4519 } else { 4520 addr = A_MC_P_INT_CAUSE; 4521 cnt_addr = A_MC_P_ECC_STATUS; 4522 } 4523 } else { 4524 addr = MC_REG(A_MC_P_INT_CAUSE, 1); 4525 cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1); 4526 } 4527 4528 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 4529 if (v & F_PERR_INT_CAUSE) 4530 CH_ALERT(adapter, "%s FIFO parity error\n", 4531 name[idx]); 4532 if (v & F_ECC_CE_INT_CAUSE) { 4533 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); 4534 4535 if (idx <= MEM_EDC1) 4536 t4_edc_err_read(adapter, idx); 4537 4538 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); 4539 CH_WARN_RATELIMIT(adapter, 4540 "%u %s correctable ECC data error%s\n", 4541 cnt, name[idx], cnt > 1 ? "s" : ""); 4542 } 4543 if (v & F_ECC_UE_INT_CAUSE) 4544 CH_ALERT(adapter, 4545 "%s uncorrectable ECC data error\n", name[idx]); 4546 4547 t4_write_reg(adapter, addr, v); 4548 if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE)) 4549 t4_fatal_err(adapter); 4550 } 4551 4552 /* 4553 * MA interrupt handler. 4554 */ 4555 static void ma_intr_handler(struct adapter *adapter) 4556 { 4557 u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); 4558 4559 if (status & F_MEM_PERR_INT_CAUSE) { 4560 CH_ALERT(adapter, 4561 "MA parity error, parity status %#x\n", 4562 t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); 4563 if (is_t5(adapter)) 4564 CH_ALERT(adapter, 4565 "MA parity error, parity status %#x\n", 4566 t4_read_reg(adapter, 4567 A_MA_PARITY_ERROR_STATUS2)); 4568 } 4569 if (status & F_MEM_WRAP_INT_CAUSE) { 4570 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); 4571 CH_ALERT(adapter, "MA address wrap-around error by " 4572 "client %u to address %#x\n", 4573 G_MEM_WRAP_CLIENT_NUM(v), 4574 G_MEM_WRAP_ADDRESS(v) << 4); 4575 } 4576 t4_write_reg(adapter, A_MA_INT_CAUSE, status); 4577 t4_fatal_err(adapter); 4578 } 4579 4580 /* 4581 * SMB interrupt handler. 4582 */ 4583 static void smb_intr_handler(struct adapter *adap) 4584 { 4585 static const struct intr_info smb_intr_info[] = { 4586 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 4587 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 4588 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 4589 { 0 } 4590 }; 4591 4592 if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info)) 4593 t4_fatal_err(adap); 4594 } 4595 4596 /* 4597 * NC-SI interrupt handler. 4598 */ 4599 static void ncsi_intr_handler(struct adapter *adap) 4600 { 4601 static const struct intr_info ncsi_intr_info[] = { 4602 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 4603 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 4604 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 4605 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 4606 { 0 } 4607 }; 4608 4609 if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info)) 4610 t4_fatal_err(adap); 4611 } 4612 4613 /* 4614 * XGMAC interrupt handler. 4615 */ 4616 static void xgmac_intr_handler(struct adapter *adap, int port) 4617 { 4618 u32 v, int_cause_reg; 4619 4620 if (is_t4(adap)) 4621 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 4622 else 4623 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 4624 4625 v = t4_read_reg(adap, int_cause_reg); 4626 4627 v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); 4628 if (!v) 4629 return; 4630 4631 if (v & F_TXFIFO_PRTY_ERR) 4632 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", 4633 port); 4634 if (v & F_RXFIFO_PRTY_ERR) 4635 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", 4636 port); 4637 t4_write_reg(adap, int_cause_reg, v); 4638 t4_fatal_err(adap); 4639 } 4640 4641 /* 4642 * PL interrupt handler. 4643 */ 4644 static void pl_intr_handler(struct adapter *adap) 4645 { 4646 static const struct intr_info pl_intr_info[] = { 4647 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4648 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 4649 { 0 } 4650 }; 4651 4652 static const struct intr_info t5_pl_intr_info[] = { 4653 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4654 { 0 } 4655 }; 4656 4657 if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, 4658 is_t4(adap) ? 4659 pl_intr_info : t5_pl_intr_info)) 4660 t4_fatal_err(adap); 4661 } 4662 4663 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 4664 4665 /** 4666 * t4_slow_intr_handler - control path interrupt handler 4667 * @adapter: the adapter 4668 * 4669 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 4670 * The designation 'slow' is because it involves register reads, while 4671 * data interrupts typically don't involve any MMIOs. 4672 */ 4673 int t4_slow_intr_handler(struct adapter *adapter) 4674 { 4675 u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE); 4676 4677 if (!(cause & GLBL_INTR_MASK)) 4678 return 0; 4679 if (cause & F_CIM) 4680 cim_intr_handler(adapter); 4681 if (cause & F_MPS) 4682 mps_intr_handler(adapter); 4683 if (cause & F_NCSI) 4684 ncsi_intr_handler(adapter); 4685 if (cause & F_PL) 4686 pl_intr_handler(adapter); 4687 if (cause & F_SMB) 4688 smb_intr_handler(adapter); 4689 if (cause & F_MAC0) 4690 xgmac_intr_handler(adapter, 0); 4691 if (cause & F_MAC1) 4692 xgmac_intr_handler(adapter, 1); 4693 if (cause & F_MAC2) 4694 xgmac_intr_handler(adapter, 2); 4695 if (cause & F_MAC3) 4696 xgmac_intr_handler(adapter, 3); 4697 if (cause & F_PCIE) 4698 pcie_intr_handler(adapter); 4699 if (cause & F_MC0) 4700 mem_intr_handler(adapter, MEM_MC); 4701 if (is_t5(adapter) && (cause & F_MC1)) 4702 mem_intr_handler(adapter, MEM_MC1); 4703 if (cause & F_EDC0) 4704 mem_intr_handler(adapter, MEM_EDC0); 4705 if (cause & F_EDC1) 4706 mem_intr_handler(adapter, MEM_EDC1); 4707 if (cause & F_LE) 4708 le_intr_handler(adapter); 4709 if (cause & F_TP) 4710 tp_intr_handler(adapter); 4711 if (cause & F_MA) 4712 ma_intr_handler(adapter); 4713 if (cause & F_PM_TX) 4714 pmtx_intr_handler(adapter); 4715 if (cause & F_PM_RX) 4716 pmrx_intr_handler(adapter); 4717 if (cause & F_ULP_RX) 4718 ulprx_intr_handler(adapter); 4719 if (cause & F_CPL_SWITCH) 4720 cplsw_intr_handler(adapter); 4721 if (cause & F_SGE) 4722 sge_intr_handler(adapter); 4723 if (cause & F_ULP_TX) 4724 ulptx_intr_handler(adapter); 4725 4726 /* Clear the interrupts just processed for which we are the master. */ 4727 t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK); 4728 (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4729 return 1; 4730 } 4731 4732 /** 4733 * t4_intr_enable - enable interrupts 4734 * @adapter: the adapter whose interrupts should be enabled 4735 * 4736 * Enable PF-specific interrupts for the calling function and the top-level 4737 * interrupt concentrator for global interrupts. Interrupts are already 4738 * enabled at each module, here we just enable the roots of the interrupt 4739 * hierarchies. 4740 * 4741 * Note: this function should be called only when the driver manages 4742 * non PF-specific interrupts from the various HW modules. Only one PCI 4743 * function at a time should be doing this. 4744 */ 4745 void t4_intr_enable(struct adapter *adapter) 4746 { 4747 u32 val = 0; 4748 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4749 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4750 ? G_SOURCEPF(whoami) 4751 : G_T6_SOURCEPF(whoami)); 4752 4753 if (chip_id(adapter) <= CHELSIO_T5) 4754 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 4755 else 4756 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 4757 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE | 4758 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 | 4759 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR | 4760 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 | 4761 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4762 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | 4763 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val); 4764 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 4765 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf); 4766 } 4767 4768 /** 4769 * t4_intr_disable - disable interrupts 4770 * @adapter: the adapter whose interrupts should be disabled 4771 * 4772 * Disable interrupts. We only disable the top-level interrupt 4773 * concentrators. The caller must be a PCI function managing global 4774 * interrupts. 4775 */ 4776 void t4_intr_disable(struct adapter *adapter) 4777 { 4778 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4779 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4780 ? G_SOURCEPF(whoami) 4781 : G_T6_SOURCEPF(whoami)); 4782 4783 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 4784 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0); 4785 } 4786 4787 /** 4788 * t4_intr_clear - clear all interrupts 4789 * @adapter: the adapter whose interrupts should be cleared 4790 * 4791 * Clears all interrupts. The caller must be a PCI function managing 4792 * global interrupts. 4793 */ 4794 void t4_intr_clear(struct adapter *adapter) 4795 { 4796 static const unsigned int cause_reg[] = { 4797 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3, 4798 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, 4799 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE, 4800 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), 4801 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, 4802 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4803 A_TP_INT_CAUSE, 4804 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE, 4805 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE, 4806 A_MPS_RX_PERR_INT_CAUSE, 4807 A_CPL_INTR_CAUSE, 4808 MYPF_REG(A_PL_PF_INT_CAUSE), 4809 A_PL_PL_INT_CAUSE, 4810 A_LE_DB_INT_CAUSE, 4811 }; 4812 4813 unsigned int i; 4814 4815 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) 4816 t4_write_reg(adapter, cause_reg[i], 0xffffffff); 4817 4818 t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : 4819 A_MC_P_INT_CAUSE, 0xffffffff); 4820 4821 if (is_t4(adapter)) { 4822 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4823 0xffffffff); 4824 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4825 0xffffffff); 4826 } else 4827 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 4828 4829 t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); 4830 (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4831 } 4832 4833 /** 4834 * hash_mac_addr - return the hash value of a MAC address 4835 * @addr: the 48-bit Ethernet MAC address 4836 * 4837 * Hashes a MAC address according to the hash function used by HW inexact 4838 * (hash) address matching. 4839 */ 4840 static int hash_mac_addr(const u8 *addr) 4841 { 4842 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 4843 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 4844 a ^= b; 4845 a ^= (a >> 12); 4846 a ^= (a >> 6); 4847 return a & 0x3f; 4848 } 4849 4850 /** 4851 * t4_config_rss_range - configure a portion of the RSS mapping table 4852 * @adapter: the adapter 4853 * @mbox: mbox to use for the FW command 4854 * @viid: virtual interface whose RSS subtable is to be written 4855 * @start: start entry in the table to write 4856 * @n: how many table entries to write 4857 * @rspq: values for the "response queue" (Ingress Queue) lookup table 4858 * @nrspq: number of values in @rspq 4859 * 4860 * Programs the selected part of the VI's RSS mapping table with the 4861 * provided values. If @nrspq < @n the supplied values are used repeatedly 4862 * until the full table range is populated. 4863 * 4864 * The caller must ensure the values in @rspq are in the range allowed for 4865 * @viid. 4866 */ 4867 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 4868 int start, int n, const u16 *rspq, unsigned int nrspq) 4869 { 4870 int ret; 4871 const u16 *rsp = rspq; 4872 const u16 *rsp_end = rspq + nrspq; 4873 struct fw_rss_ind_tbl_cmd cmd; 4874 4875 memset(&cmd, 0, sizeof(cmd)); 4876 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 4877 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4878 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 4879 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 4880 4881 /* 4882 * Each firmware RSS command can accommodate up to 32 RSS Ingress 4883 * Queue Identifiers. These Ingress Queue IDs are packed three to 4884 * a 32-bit word as 10-bit values with the upper remaining 2 bits 4885 * reserved. 4886 */ 4887 while (n > 0) { 4888 int nq = min(n, 32); 4889 int nq_packed = 0; 4890 __be32 *qp = &cmd.iq0_to_iq2; 4891 4892 /* 4893 * Set up the firmware RSS command header to send the next 4894 * "nq" Ingress Queue IDs to the firmware. 4895 */ 4896 cmd.niqid = cpu_to_be16(nq); 4897 cmd.startidx = cpu_to_be16(start); 4898 4899 /* 4900 * "nq" more done for the start of the next loop. 4901 */ 4902 start += nq; 4903 n -= nq; 4904 4905 /* 4906 * While there are still Ingress Queue IDs to stuff into the 4907 * current firmware RSS command, retrieve them from the 4908 * Ingress Queue ID array and insert them into the command. 4909 */ 4910 while (nq > 0) { 4911 /* 4912 * Grab up to the next 3 Ingress Queue IDs (wrapping 4913 * around the Ingress Queue ID array if necessary) and 4914 * insert them into the firmware RSS command at the 4915 * current 3-tuple position within the commad. 4916 */ 4917 u16 qbuf[3]; 4918 u16 *qbp = qbuf; 4919 int nqbuf = min(3, nq); 4920 4921 nq -= nqbuf; 4922 qbuf[0] = qbuf[1] = qbuf[2] = 0; 4923 while (nqbuf && nq_packed < 32) { 4924 nqbuf--; 4925 nq_packed++; 4926 *qbp++ = *rsp++; 4927 if (rsp >= rsp_end) 4928 rsp = rspq; 4929 } 4930 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 4931 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 4932 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 4933 } 4934 4935 /* 4936 * Send this portion of the RRS table update to the firmware; 4937 * bail out on any errors. 4938 */ 4939 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 4940 if (ret) 4941 return ret; 4942 } 4943 return 0; 4944 } 4945 4946 /** 4947 * t4_config_glbl_rss - configure the global RSS mode 4948 * @adapter: the adapter 4949 * @mbox: mbox to use for the FW command 4950 * @mode: global RSS mode 4951 * @flags: mode-specific flags 4952 * 4953 * Sets the global RSS mode. 4954 */ 4955 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 4956 unsigned int flags) 4957 { 4958 struct fw_rss_glb_config_cmd c; 4959 4960 memset(&c, 0, sizeof(c)); 4961 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 4962 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 4963 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4964 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 4965 c.u.manual.mode_pkd = 4966 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4967 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 4968 c.u.basicvirtual.mode_keymode = 4969 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4970 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 4971 } else 4972 return -EINVAL; 4973 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4974 } 4975 4976 /** 4977 * t4_config_vi_rss - configure per VI RSS settings 4978 * @adapter: the adapter 4979 * @mbox: mbox to use for the FW command 4980 * @viid: the VI id 4981 * @flags: RSS flags 4982 * @defq: id of the default RSS queue for the VI. 4983 * @skeyidx: RSS secret key table index for non-global mode 4984 * @skey: RSS vf_scramble key for VI. 4985 * 4986 * Configures VI-specific RSS properties. 4987 */ 4988 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 4989 unsigned int flags, unsigned int defq, unsigned int skeyidx, 4990 unsigned int skey) 4991 { 4992 struct fw_rss_vi_config_cmd c; 4993 4994 memset(&c, 0, sizeof(c)); 4995 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 4996 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4997 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 4998 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4999 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5000 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5001 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5002 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5003 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5004 5005 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5006 } 5007 5008 /* Read an RSS table row */ 5009 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5010 { 5011 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5012 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5013 5, 0, val); 5014 } 5015 5016 /** 5017 * t4_read_rss - read the contents of the RSS mapping table 5018 * @adapter: the adapter 5019 * @map: holds the contents of the RSS mapping table 5020 * 5021 * Reads the contents of the RSS hash->queue mapping table. 5022 */ 5023 int t4_read_rss(struct adapter *adapter, u16 *map) 5024 { 5025 u32 val; 5026 int i, ret; 5027 5028 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 5029 ret = rd_rss_row(adapter, i, &val); 5030 if (ret) 5031 return ret; 5032 *map++ = G_LKPTBLQUEUE0(val); 5033 *map++ = G_LKPTBLQUEUE1(val); 5034 } 5035 return 0; 5036 } 5037 5038 /** 5039 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5040 * @adap: the adapter 5041 * @cmd: TP fw ldst address space type 5042 * @vals: where the indirect register values are stored/written 5043 * @nregs: how many indirect registers to read/write 5044 * @start_idx: index of first indirect register to read/write 5045 * @rw: Read (1) or Write (0) 5046 * @sleep_ok: if true we may sleep while awaiting command completion 5047 * 5048 * Access TP indirect registers through LDST 5049 **/ 5050 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5051 unsigned int nregs, unsigned int start_index, 5052 unsigned int rw, bool sleep_ok) 5053 { 5054 int ret = 0; 5055 unsigned int i; 5056 struct fw_ldst_cmd c; 5057 5058 for (i = 0; i < nregs; i++) { 5059 memset(&c, 0, sizeof(c)); 5060 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5061 F_FW_CMD_REQUEST | 5062 (rw ? F_FW_CMD_READ : 5063 F_FW_CMD_WRITE) | 5064 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5065 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5066 5067 c.u.addrval.addr = cpu_to_be32(start_index + i); 5068 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5069 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5070 sleep_ok); 5071 if (ret) 5072 return ret; 5073 5074 if (rw) 5075 vals[i] = be32_to_cpu(c.u.addrval.val); 5076 } 5077 return 0; 5078 } 5079 5080 /** 5081 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5082 * @adap: the adapter 5083 * @reg_addr: Address Register 5084 * @reg_data: Data register 5085 * @buff: where the indirect register values are stored/written 5086 * @nregs: how many indirect registers to read/write 5087 * @start_index: index of first indirect register to read/write 5088 * @rw: READ(1) or WRITE(0) 5089 * @sleep_ok: if true we may sleep while awaiting command completion 5090 * 5091 * Read/Write TP indirect registers through LDST if possible. 5092 * Else, use backdoor access 5093 **/ 5094 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5095 u32 *buff, u32 nregs, u32 start_index, int rw, 5096 bool sleep_ok) 5097 { 5098 int rc = -EINVAL; 5099 int cmd; 5100 5101 switch (reg_addr) { 5102 case A_TP_PIO_ADDR: 5103 cmd = FW_LDST_ADDRSPC_TP_PIO; 5104 break; 5105 case A_TP_TM_PIO_ADDR: 5106 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5107 break; 5108 case A_TP_MIB_INDEX: 5109 cmd = FW_LDST_ADDRSPC_TP_MIB; 5110 break; 5111 default: 5112 goto indirect_access; 5113 } 5114 5115 if (t4_use_ldst(adap)) 5116 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5117 sleep_ok); 5118 5119 indirect_access: 5120 5121 if (rc) { 5122 if (rw) 5123 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5124 start_index); 5125 else 5126 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5127 start_index); 5128 } 5129 } 5130 5131 /** 5132 * t4_tp_pio_read - Read TP PIO registers 5133 * @adap: the adapter 5134 * @buff: where the indirect register values are written 5135 * @nregs: how many indirect registers to read 5136 * @start_index: index of first indirect register to read 5137 * @sleep_ok: if true we may sleep while awaiting command completion 5138 * 5139 * Read TP PIO Registers 5140 **/ 5141 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5142 u32 start_index, bool sleep_ok) 5143 { 5144 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5145 start_index, 1, sleep_ok); 5146 } 5147 5148 /** 5149 * t4_tp_pio_write - Write TP PIO registers 5150 * @adap: the adapter 5151 * @buff: where the indirect register values are stored 5152 * @nregs: how many indirect registers to write 5153 * @start_index: index of first indirect register to write 5154 * @sleep_ok: if true we may sleep while awaiting command completion 5155 * 5156 * Write TP PIO Registers 5157 **/ 5158 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5159 u32 start_index, bool sleep_ok) 5160 { 5161 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5162 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5163 } 5164 5165 /** 5166 * t4_tp_tm_pio_read - Read TP TM PIO registers 5167 * @adap: the adapter 5168 * @buff: where the indirect register values are written 5169 * @nregs: how many indirect registers to read 5170 * @start_index: index of first indirect register to read 5171 * @sleep_ok: if true we may sleep while awaiting command completion 5172 * 5173 * Read TP TM PIO Registers 5174 **/ 5175 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5176 u32 start_index, bool sleep_ok) 5177 { 5178 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5179 nregs, start_index, 1, sleep_ok); 5180 } 5181 5182 /** 5183 * t4_tp_mib_read - Read TP MIB registers 5184 * @adap: the adapter 5185 * @buff: where the indirect register values are written 5186 * @nregs: how many indirect registers to read 5187 * @start_index: index of first indirect register to read 5188 * @sleep_ok: if true we may sleep while awaiting command completion 5189 * 5190 * Read TP MIB Registers 5191 **/ 5192 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5193 bool sleep_ok) 5194 { 5195 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5196 start_index, 1, sleep_ok); 5197 } 5198 5199 /** 5200 * t4_read_rss_key - read the global RSS key 5201 * @adap: the adapter 5202 * @key: 10-entry array holding the 320-bit RSS key 5203 * @sleep_ok: if true we may sleep while awaiting command completion 5204 * 5205 * Reads the global 320-bit RSS key. 5206 */ 5207 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5208 { 5209 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5210 } 5211 5212 /** 5213 * t4_write_rss_key - program one of the RSS keys 5214 * @adap: the adapter 5215 * @key: 10-entry array holding the 320-bit RSS key 5216 * @idx: which RSS key to write 5217 * @sleep_ok: if true we may sleep while awaiting command completion 5218 * 5219 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5220 * 0..15 the corresponding entry in the RSS key table is written, 5221 * otherwise the global RSS key is written. 5222 */ 5223 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5224 bool sleep_ok) 5225 { 5226 u8 rss_key_addr_cnt = 16; 5227 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5228 5229 /* 5230 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5231 * allows access to key addresses 16-63 by using KeyWrAddrX 5232 * as index[5:4](upper 2) into key table 5233 */ 5234 if ((chip_id(adap) > CHELSIO_T5) && 5235 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5236 rss_key_addr_cnt = 32; 5237 5238 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5239 5240 if (idx >= 0 && idx < rss_key_addr_cnt) { 5241 if (rss_key_addr_cnt > 16) 5242 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5243 vrt | V_KEYWRADDRX(idx >> 4) | 5244 V_T6_VFWRADDR(idx) | F_KEYWREN); 5245 else 5246 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5247 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5248 } 5249 } 5250 5251 /** 5252 * t4_read_rss_pf_config - read PF RSS Configuration Table 5253 * @adapter: the adapter 5254 * @index: the entry in the PF RSS table to read 5255 * @valp: where to store the returned value 5256 * @sleep_ok: if true we may sleep while awaiting command completion 5257 * 5258 * Reads the PF RSS Configuration Table at the specified index and returns 5259 * the value found there. 5260 */ 5261 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5262 u32 *valp, bool sleep_ok) 5263 { 5264 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5265 } 5266 5267 /** 5268 * t4_write_rss_pf_config - write PF RSS Configuration Table 5269 * @adapter: the adapter 5270 * @index: the entry in the VF RSS table to read 5271 * @val: the value to store 5272 * @sleep_ok: if true we may sleep while awaiting command completion 5273 * 5274 * Writes the PF RSS Configuration Table at the specified index with the 5275 * specified value. 5276 */ 5277 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5278 u32 val, bool sleep_ok) 5279 { 5280 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5281 sleep_ok); 5282 } 5283 5284 /** 5285 * t4_read_rss_vf_config - read VF RSS Configuration Table 5286 * @adapter: the adapter 5287 * @index: the entry in the VF RSS table to read 5288 * @vfl: where to store the returned VFL 5289 * @vfh: where to store the returned VFH 5290 * @sleep_ok: if true we may sleep while awaiting command completion 5291 * 5292 * Reads the VF RSS Configuration Table at the specified index and returns 5293 * the (VFL, VFH) values found there. 5294 */ 5295 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5296 u32 *vfl, u32 *vfh, bool sleep_ok) 5297 { 5298 u32 vrt, mask, data; 5299 5300 if (chip_id(adapter) <= CHELSIO_T5) { 5301 mask = V_VFWRADDR(M_VFWRADDR); 5302 data = V_VFWRADDR(index); 5303 } else { 5304 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5305 data = V_T6_VFWRADDR(index); 5306 } 5307 /* 5308 * Request that the index'th VF Table values be read into VFL/VFH. 5309 */ 5310 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5311 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5312 vrt |= data | F_VFRDEN; 5313 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5314 5315 /* 5316 * Grab the VFL/VFH values ... 5317 */ 5318 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5319 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5320 } 5321 5322 /** 5323 * t4_write_rss_vf_config - write VF RSS Configuration Table 5324 * 5325 * @adapter: the adapter 5326 * @index: the entry in the VF RSS table to write 5327 * @vfl: the VFL to store 5328 * @vfh: the VFH to store 5329 * 5330 * Writes the VF RSS Configuration Table at the specified index with the 5331 * specified (VFL, VFH) values. 5332 */ 5333 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 5334 u32 vfl, u32 vfh, bool sleep_ok) 5335 { 5336 u32 vrt, mask, data; 5337 5338 if (chip_id(adapter) <= CHELSIO_T5) { 5339 mask = V_VFWRADDR(M_VFWRADDR); 5340 data = V_VFWRADDR(index); 5341 } else { 5342 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5343 data = V_T6_VFWRADDR(index); 5344 } 5345 5346 /* 5347 * Load up VFL/VFH with the values to be written ... 5348 */ 5349 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5350 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5351 5352 /* 5353 * Write the VFL/VFH into the VF Table at index'th location. 5354 */ 5355 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5356 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5357 vrt |= data | F_VFRDEN; 5358 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5359 } 5360 5361 /** 5362 * t4_read_rss_pf_map - read PF RSS Map 5363 * @adapter: the adapter 5364 * @sleep_ok: if true we may sleep while awaiting command completion 5365 * 5366 * Reads the PF RSS Map register and returns its value. 5367 */ 5368 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 5369 { 5370 u32 pfmap; 5371 5372 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5373 5374 return pfmap; 5375 } 5376 5377 /** 5378 * t4_write_rss_pf_map - write PF RSS Map 5379 * @adapter: the adapter 5380 * @pfmap: PF RSS Map value 5381 * 5382 * Writes the specified value to the PF RSS Map register. 5383 */ 5384 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 5385 { 5386 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5387 } 5388 5389 /** 5390 * t4_read_rss_pf_mask - read PF RSS Mask 5391 * @adapter: the adapter 5392 * @sleep_ok: if true we may sleep while awaiting command completion 5393 * 5394 * Reads the PF RSS Mask register and returns its value. 5395 */ 5396 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 5397 { 5398 u32 pfmask; 5399 5400 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5401 5402 return pfmask; 5403 } 5404 5405 /** 5406 * t4_write_rss_pf_mask - write PF RSS Mask 5407 * @adapter: the adapter 5408 * @pfmask: PF RSS Mask value 5409 * 5410 * Writes the specified value to the PF RSS Mask register. 5411 */ 5412 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 5413 { 5414 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5415 } 5416 5417 /** 5418 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 5419 * @adap: the adapter 5420 * @v4: holds the TCP/IP counter values 5421 * @v6: holds the TCP/IPv6 counter values 5422 * @sleep_ok: if true we may sleep while awaiting command completion 5423 * 5424 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 5425 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 5426 */ 5427 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 5428 struct tp_tcp_stats *v6, bool sleep_ok) 5429 { 5430 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 5431 5432 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 5433 #define STAT(x) val[STAT_IDX(x)] 5434 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 5435 5436 if (v4) { 5437 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5438 A_TP_MIB_TCP_OUT_RST, sleep_ok); 5439 v4->tcp_out_rsts = STAT(OUT_RST); 5440 v4->tcp_in_segs = STAT64(IN_SEG); 5441 v4->tcp_out_segs = STAT64(OUT_SEG); 5442 v4->tcp_retrans_segs = STAT64(RXT_SEG); 5443 } 5444 if (v6) { 5445 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5446 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 5447 v6->tcp_out_rsts = STAT(OUT_RST); 5448 v6->tcp_in_segs = STAT64(IN_SEG); 5449 v6->tcp_out_segs = STAT64(OUT_SEG); 5450 v6->tcp_retrans_segs = STAT64(RXT_SEG); 5451 } 5452 #undef STAT64 5453 #undef STAT 5454 #undef STAT_IDX 5455 } 5456 5457 /** 5458 * t4_tp_get_err_stats - read TP's error MIB counters 5459 * @adap: the adapter 5460 * @st: holds the counter values 5461 * @sleep_ok: if true we may sleep while awaiting command completion 5462 * 5463 * Returns the values of TP's error counters. 5464 */ 5465 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 5466 bool sleep_ok) 5467 { 5468 int nchan = adap->chip_params->nchan; 5469 5470 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 5471 sleep_ok); 5472 5473 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 5474 sleep_ok); 5475 5476 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 5477 sleep_ok); 5478 5479 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 5480 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 5481 5482 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 5483 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 5484 5485 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 5486 sleep_ok); 5487 5488 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 5489 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 5490 5491 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 5492 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 5493 5494 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 5495 sleep_ok); 5496 } 5497 5498 /** 5499 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 5500 * @adap: the adapter 5501 * @st: holds the counter values 5502 * 5503 * Returns the values of TP's proxy counters. 5504 */ 5505 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 5506 bool sleep_ok) 5507 { 5508 int nchan = adap->chip_params->nchan; 5509 5510 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 5511 } 5512 5513 /** 5514 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 5515 * @adap: the adapter 5516 * @st: holds the counter values 5517 * @sleep_ok: if true we may sleep while awaiting command completion 5518 * 5519 * Returns the values of TP's CPL counters. 5520 */ 5521 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 5522 bool sleep_ok) 5523 { 5524 int nchan = adap->chip_params->nchan; 5525 5526 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 5527 5528 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 5529 } 5530 5531 /** 5532 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 5533 * @adap: the adapter 5534 * @st: holds the counter values 5535 * 5536 * Returns the values of TP's RDMA counters. 5537 */ 5538 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 5539 bool sleep_ok) 5540 { 5541 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 5542 sleep_ok); 5543 } 5544 5545 /** 5546 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 5547 * @adap: the adapter 5548 * @idx: the port index 5549 * @st: holds the counter values 5550 * @sleep_ok: if true we may sleep while awaiting command completion 5551 * 5552 * Returns the values of TP's FCoE counters for the selected port. 5553 */ 5554 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 5555 struct tp_fcoe_stats *st, bool sleep_ok) 5556 { 5557 u32 val[2]; 5558 5559 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 5560 sleep_ok); 5561 5562 t4_tp_mib_read(adap, &st->frames_drop, 1, 5563 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 5564 5565 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 5566 sleep_ok); 5567 5568 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 5569 } 5570 5571 /** 5572 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 5573 * @adap: the adapter 5574 * @st: holds the counter values 5575 * @sleep_ok: if true we may sleep while awaiting command completion 5576 * 5577 * Returns the values of TP's counters for non-TCP directly-placed packets. 5578 */ 5579 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 5580 bool sleep_ok) 5581 { 5582 u32 val[4]; 5583 5584 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 5585 5586 st->frames = val[0]; 5587 st->drops = val[1]; 5588 st->octets = ((u64)val[2] << 32) | val[3]; 5589 } 5590 5591 /** 5592 * t4_read_mtu_tbl - returns the values in the HW path MTU table 5593 * @adap: the adapter 5594 * @mtus: where to store the MTU values 5595 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 5596 * 5597 * Reads the HW path MTU table. 5598 */ 5599 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 5600 { 5601 u32 v; 5602 int i; 5603 5604 for (i = 0; i < NMTUS; ++i) { 5605 t4_write_reg(adap, A_TP_MTU_TABLE, 5606 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 5607 v = t4_read_reg(adap, A_TP_MTU_TABLE); 5608 mtus[i] = G_MTUVALUE(v); 5609 if (mtu_log) 5610 mtu_log[i] = G_MTUWIDTH(v); 5611 } 5612 } 5613 5614 /** 5615 * t4_read_cong_tbl - reads the congestion control table 5616 * @adap: the adapter 5617 * @incr: where to store the alpha values 5618 * 5619 * Reads the additive increments programmed into the HW congestion 5620 * control table. 5621 */ 5622 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 5623 { 5624 unsigned int mtu, w; 5625 5626 for (mtu = 0; mtu < NMTUS; ++mtu) 5627 for (w = 0; w < NCCTRL_WIN; ++w) { 5628 t4_write_reg(adap, A_TP_CCTRL_TABLE, 5629 V_ROWINDEX(0xffff) | (mtu << 5) | w); 5630 incr[mtu][w] = (u16)t4_read_reg(adap, 5631 A_TP_CCTRL_TABLE) & 0x1fff; 5632 } 5633 } 5634 5635 /** 5636 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 5637 * @adap: the adapter 5638 * @addr: the indirect TP register address 5639 * @mask: specifies the field within the register to modify 5640 * @val: new value for the field 5641 * 5642 * Sets a field of an indirect TP register to the given value. 5643 */ 5644 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 5645 unsigned int mask, unsigned int val) 5646 { 5647 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 5648 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 5649 t4_write_reg(adap, A_TP_PIO_DATA, val); 5650 } 5651 5652 /** 5653 * init_cong_ctrl - initialize congestion control parameters 5654 * @a: the alpha values for congestion control 5655 * @b: the beta values for congestion control 5656 * 5657 * Initialize the congestion control parameters. 5658 */ 5659 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 5660 { 5661 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 5662 a[9] = 2; 5663 a[10] = 3; 5664 a[11] = 4; 5665 a[12] = 5; 5666 a[13] = 6; 5667 a[14] = 7; 5668 a[15] = 8; 5669 a[16] = 9; 5670 a[17] = 10; 5671 a[18] = 14; 5672 a[19] = 17; 5673 a[20] = 21; 5674 a[21] = 25; 5675 a[22] = 30; 5676 a[23] = 35; 5677 a[24] = 45; 5678 a[25] = 60; 5679 a[26] = 80; 5680 a[27] = 100; 5681 a[28] = 200; 5682 a[29] = 300; 5683 a[30] = 400; 5684 a[31] = 500; 5685 5686 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 5687 b[9] = b[10] = 1; 5688 b[11] = b[12] = 2; 5689 b[13] = b[14] = b[15] = b[16] = 3; 5690 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 5691 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 5692 b[28] = b[29] = 6; 5693 b[30] = b[31] = 7; 5694 } 5695 5696 /* The minimum additive increment value for the congestion control table */ 5697 #define CC_MIN_INCR 2U 5698 5699 /** 5700 * t4_load_mtus - write the MTU and congestion control HW tables 5701 * @adap: the adapter 5702 * @mtus: the values for the MTU table 5703 * @alpha: the values for the congestion control alpha parameter 5704 * @beta: the values for the congestion control beta parameter 5705 * 5706 * Write the HW MTU table with the supplied MTUs and the high-speed 5707 * congestion control table with the supplied alpha, beta, and MTUs. 5708 * We write the two tables together because the additive increments 5709 * depend on the MTUs. 5710 */ 5711 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 5712 const unsigned short *alpha, const unsigned short *beta) 5713 { 5714 static const unsigned int avg_pkts[NCCTRL_WIN] = { 5715 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 5716 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 5717 28672, 40960, 57344, 81920, 114688, 163840, 229376 5718 }; 5719 5720 unsigned int i, w; 5721 5722 for (i = 0; i < NMTUS; ++i) { 5723 unsigned int mtu = mtus[i]; 5724 unsigned int log2 = fls(mtu); 5725 5726 if (!(mtu & ((1 << log2) >> 2))) /* round */ 5727 log2--; 5728 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 5729 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 5730 5731 for (w = 0; w < NCCTRL_WIN; ++w) { 5732 unsigned int inc; 5733 5734 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 5735 CC_MIN_INCR); 5736 5737 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 5738 (w << 16) | (beta[w] << 13) | inc); 5739 } 5740 } 5741 } 5742 5743 /** 5744 * t4_set_pace_tbl - set the pace table 5745 * @adap: the adapter 5746 * @pace_vals: the pace values in microseconds 5747 * @start: index of the first entry in the HW pace table to set 5748 * @n: how many entries to set 5749 * 5750 * Sets (a subset of the) HW pace table. 5751 */ 5752 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 5753 unsigned int start, unsigned int n) 5754 { 5755 unsigned int vals[NTX_SCHED], i; 5756 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 5757 5758 if (n > NTX_SCHED) 5759 return -ERANGE; 5760 5761 /* convert values from us to dack ticks, rounding to closest value */ 5762 for (i = 0; i < n; i++, pace_vals++) { 5763 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 5764 if (vals[i] > 0x7ff) 5765 return -ERANGE; 5766 if (*pace_vals && vals[i] == 0) 5767 return -ERANGE; 5768 } 5769 for (i = 0; i < n; i++, start++) 5770 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 5771 return 0; 5772 } 5773 5774 /** 5775 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 5776 * @adap: the adapter 5777 * @kbps: target rate in Kbps 5778 * @sched: the scheduler index 5779 * 5780 * Configure a Tx HW scheduler for the target rate. 5781 */ 5782 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 5783 { 5784 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 5785 unsigned int clk = adap->params.vpd.cclk * 1000; 5786 unsigned int selected_cpt = 0, selected_bpt = 0; 5787 5788 if (kbps > 0) { 5789 kbps *= 125; /* -> bytes */ 5790 for (cpt = 1; cpt <= 255; cpt++) { 5791 tps = clk / cpt; 5792 bpt = (kbps + tps / 2) / tps; 5793 if (bpt > 0 && bpt <= 255) { 5794 v = bpt * tps; 5795 delta = v >= kbps ? v - kbps : kbps - v; 5796 if (delta < mindelta) { 5797 mindelta = delta; 5798 selected_cpt = cpt; 5799 selected_bpt = bpt; 5800 } 5801 } else if (selected_cpt) 5802 break; 5803 } 5804 if (!selected_cpt) 5805 return -EINVAL; 5806 } 5807 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 5808 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 5809 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5810 if (sched & 1) 5811 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 5812 else 5813 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 5814 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5815 return 0; 5816 } 5817 5818 /** 5819 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 5820 * @adap: the adapter 5821 * @sched: the scheduler index 5822 * @ipg: the interpacket delay in tenths of nanoseconds 5823 * 5824 * Set the interpacket delay for a HW packet rate scheduler. 5825 */ 5826 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 5827 { 5828 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 5829 5830 /* convert ipg to nearest number of core clocks */ 5831 ipg *= core_ticks_per_usec(adap); 5832 ipg = (ipg + 5000) / 10000; 5833 if (ipg > M_TXTIMERSEPQ0) 5834 return -EINVAL; 5835 5836 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 5837 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5838 if (sched & 1) 5839 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 5840 else 5841 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 5842 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5843 t4_read_reg(adap, A_TP_TM_PIO_DATA); 5844 return 0; 5845 } 5846 5847 /* 5848 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 5849 * clocks. The formula is 5850 * 5851 * bytes/s = bytes256 * 256 * ClkFreq / 4096 5852 * 5853 * which is equivalent to 5854 * 5855 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 5856 */ 5857 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 5858 { 5859 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 5860 5861 return v * 62 + v / 2; 5862 } 5863 5864 /** 5865 * t4_get_chan_txrate - get the current per channel Tx rates 5866 * @adap: the adapter 5867 * @nic_rate: rates for NIC traffic 5868 * @ofld_rate: rates for offloaded traffic 5869 * 5870 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 5871 * for each channel. 5872 */ 5873 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 5874 { 5875 u32 v; 5876 5877 v = t4_read_reg(adap, A_TP_TX_TRATE); 5878 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 5879 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 5880 if (adap->chip_params->nchan > 2) { 5881 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 5882 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 5883 } 5884 5885 v = t4_read_reg(adap, A_TP_TX_ORATE); 5886 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 5887 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 5888 if (adap->chip_params->nchan > 2) { 5889 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 5890 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 5891 } 5892 } 5893 5894 /** 5895 * t4_set_trace_filter - configure one of the tracing filters 5896 * @adap: the adapter 5897 * @tp: the desired trace filter parameters 5898 * @idx: which filter to configure 5899 * @enable: whether to enable or disable the filter 5900 * 5901 * Configures one of the tracing filters available in HW. If @tp is %NULL 5902 * it indicates that the filter is already written in the register and it 5903 * just needs to be enabled or disabled. 5904 */ 5905 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 5906 int idx, int enable) 5907 { 5908 int i, ofst = idx * 4; 5909 u32 data_reg, mask_reg, cfg; 5910 u32 multitrc = F_TRCMULTIFILTER; 5911 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 5912 5913 if (idx < 0 || idx >= NTRACE) 5914 return -EINVAL; 5915 5916 if (tp == NULL || !enable) { 5917 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 5918 enable ? en : 0); 5919 return 0; 5920 } 5921 5922 /* 5923 * TODO - After T4 data book is updated, specify the exact 5924 * section below. 5925 * 5926 * See T4 data book - MPS section for a complete description 5927 * of the below if..else handling of A_MPS_TRC_CFG register 5928 * value. 5929 */ 5930 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 5931 if (cfg & F_TRCMULTIFILTER) { 5932 /* 5933 * If multiple tracers are enabled, then maximum 5934 * capture size is 2.5KB (FIFO size of a single channel) 5935 * minus 2 flits for CPL_TRACE_PKT header. 5936 */ 5937 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 5938 return -EINVAL; 5939 } else { 5940 /* 5941 * If multiple tracers are disabled, to avoid deadlocks 5942 * maximum packet capture size of 9600 bytes is recommended. 5943 * Also in this mode, only trace0 can be enabled and running. 5944 */ 5945 multitrc = 0; 5946 if (tp->snap_len > 9600 || idx) 5947 return -EINVAL; 5948 } 5949 5950 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 5951 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 5952 tp->min_len > M_TFMINPKTSIZE) 5953 return -EINVAL; 5954 5955 /* stop the tracer we'll be changing */ 5956 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 5957 5958 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 5959 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 5960 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 5961 5962 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5963 t4_write_reg(adap, data_reg, tp->data[i]); 5964 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 5965 } 5966 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 5967 V_TFCAPTUREMAX(tp->snap_len) | 5968 V_TFMINPKTSIZE(tp->min_len)); 5969 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 5970 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 5971 (is_t4(adap) ? 5972 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 5973 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 5974 5975 return 0; 5976 } 5977 5978 /** 5979 * t4_get_trace_filter - query one of the tracing filters 5980 * @adap: the adapter 5981 * @tp: the current trace filter parameters 5982 * @idx: which trace filter to query 5983 * @enabled: non-zero if the filter is enabled 5984 * 5985 * Returns the current settings of one of the HW tracing filters. 5986 */ 5987 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 5988 int *enabled) 5989 { 5990 u32 ctla, ctlb; 5991 int i, ofst = idx * 4; 5992 u32 data_reg, mask_reg; 5993 5994 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 5995 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 5996 5997 if (is_t4(adap)) { 5998 *enabled = !!(ctla & F_TFEN); 5999 tp->port = G_TFPORT(ctla); 6000 tp->invert = !!(ctla & F_TFINVERTMATCH); 6001 } else { 6002 *enabled = !!(ctla & F_T5_TFEN); 6003 tp->port = G_T5_TFPORT(ctla); 6004 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6005 } 6006 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6007 tp->min_len = G_TFMINPKTSIZE(ctlb); 6008 tp->skip_ofst = G_TFOFFSET(ctla); 6009 tp->skip_len = G_TFLENGTH(ctla); 6010 6011 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6012 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6013 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6014 6015 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6016 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6017 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6018 } 6019 } 6020 6021 /** 6022 * t4_pmtx_get_stats - returns the HW stats from PMTX 6023 * @adap: the adapter 6024 * @cnt: where to store the count statistics 6025 * @cycles: where to store the cycle statistics 6026 * 6027 * Returns performance statistics from PMTX. 6028 */ 6029 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6030 { 6031 int i; 6032 u32 data[2]; 6033 6034 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6035 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6036 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6037 if (is_t4(adap)) 6038 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6039 else { 6040 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6041 A_PM_TX_DBG_DATA, data, 2, 6042 A_PM_TX_DBG_STAT_MSB); 6043 cycles[i] = (((u64)data[0] << 32) | data[1]); 6044 } 6045 } 6046 } 6047 6048 /** 6049 * t4_pmrx_get_stats - returns the HW stats from PMRX 6050 * @adap: the adapter 6051 * @cnt: where to store the count statistics 6052 * @cycles: where to store the cycle statistics 6053 * 6054 * Returns performance statistics from PMRX. 6055 */ 6056 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6057 { 6058 int i; 6059 u32 data[2]; 6060 6061 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6062 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6063 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6064 if (is_t4(adap)) { 6065 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6066 } else { 6067 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6068 A_PM_RX_DBG_DATA, data, 2, 6069 A_PM_RX_DBG_STAT_MSB); 6070 cycles[i] = (((u64)data[0] << 32) | data[1]); 6071 } 6072 } 6073 } 6074 6075 /** 6076 * t4_get_mps_bg_map - return the buffer groups associated with a port 6077 * @adap: the adapter 6078 * @idx: the port index 6079 * 6080 * Returns a bitmap indicating which MPS buffer groups are associated 6081 * with the given port. Bit i is set if buffer group i is used by the 6082 * port. 6083 */ 6084 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6085 { 6086 u32 n; 6087 6088 if (adap->params.mps_bg_map) 6089 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6090 6091 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6092 if (n == 0) 6093 return idx == 0 ? 0xf : 0; 6094 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6095 return idx < 2 ? (3 << (2 * idx)) : 0; 6096 return 1 << idx; 6097 } 6098 6099 /* 6100 * TP RX e-channels associated with the port. 6101 */ 6102 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6103 { 6104 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6105 6106 if (n == 0) 6107 return idx == 0 ? 0xf : 0; 6108 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6109 return idx < 2 ? (3 << (2 * idx)) : 0; 6110 return 1 << idx; 6111 } 6112 6113 /** 6114 * t4_get_port_type_description - return Port Type string description 6115 * @port_type: firmware Port Type enumeration 6116 */ 6117 const char *t4_get_port_type_description(enum fw_port_type port_type) 6118 { 6119 static const char *const port_type_description[] = { 6120 "Fiber_XFI", 6121 "Fiber_XAUI", 6122 "BT_SGMII", 6123 "BT_XFI", 6124 "BT_XAUI", 6125 "KX4", 6126 "CX4", 6127 "KX", 6128 "KR", 6129 "SFP", 6130 "BP_AP", 6131 "BP4_AP", 6132 "QSFP_10G", 6133 "QSA", 6134 "QSFP", 6135 "BP40_BA", 6136 "KR4_100G", 6137 "CR4_QSFP", 6138 "CR_QSFP", 6139 "CR2_QSFP", 6140 "SFP28", 6141 "KR_SFP28", 6142 }; 6143 6144 if (port_type < ARRAY_SIZE(port_type_description)) 6145 return port_type_description[port_type]; 6146 return "UNKNOWN"; 6147 } 6148 6149 /** 6150 * t4_get_port_stats_offset - collect port stats relative to a previous 6151 * snapshot 6152 * @adap: The adapter 6153 * @idx: The port 6154 * @stats: Current stats to fill 6155 * @offset: Previous stats snapshot 6156 */ 6157 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6158 struct port_stats *stats, 6159 struct port_stats *offset) 6160 { 6161 u64 *s, *o; 6162 int i; 6163 6164 t4_get_port_stats(adap, idx, stats); 6165 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6166 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6167 i++, s++, o++) 6168 *s -= *o; 6169 } 6170 6171 /** 6172 * t4_get_port_stats - collect port statistics 6173 * @adap: the adapter 6174 * @idx: the port index 6175 * @p: the stats structure to fill 6176 * 6177 * Collect statistics related to the given port from HW. 6178 */ 6179 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6180 { 6181 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6182 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6183 6184 #define GET_STAT(name) \ 6185 t4_read_reg64(adap, \ 6186 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6187 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6188 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6189 6190 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6191 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6192 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6193 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6194 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6195 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6196 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6197 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6198 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6199 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6200 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6201 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6202 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6203 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6204 p->tx_drop = GET_STAT(TX_PORT_DROP); 6205 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6206 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6207 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6208 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6209 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6210 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6211 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6212 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6213 6214 if (chip_id(adap) >= CHELSIO_T5) { 6215 if (stat_ctl & F_COUNTPAUSESTATTX) { 6216 p->tx_frames -= p->tx_pause; 6217 p->tx_octets -= p->tx_pause * 64; 6218 } 6219 if (stat_ctl & F_COUNTPAUSEMCTX) 6220 p->tx_mcast_frames -= p->tx_pause; 6221 } 6222 6223 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6224 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6225 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6226 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6227 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6228 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6229 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6230 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6231 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 6232 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6233 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6234 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6235 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6236 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6237 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6238 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6239 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6240 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6241 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6242 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6243 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6244 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6245 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6246 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6247 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6248 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6249 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6250 6251 if (chip_id(adap) >= CHELSIO_T5) { 6252 if (stat_ctl & F_COUNTPAUSESTATRX) { 6253 p->rx_frames -= p->rx_pause; 6254 p->rx_octets -= p->rx_pause * 64; 6255 } 6256 if (stat_ctl & F_COUNTPAUSEMCRX) 6257 p->rx_mcast_frames -= p->rx_pause; 6258 } 6259 6260 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6261 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6262 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6263 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6264 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6265 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6266 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6267 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6268 6269 #undef GET_STAT 6270 #undef GET_STAT_COM 6271 } 6272 6273 /** 6274 * t4_get_lb_stats - collect loopback port statistics 6275 * @adap: the adapter 6276 * @idx: the loopback port index 6277 * @p: the stats structure to fill 6278 * 6279 * Return HW statistics for the given loopback port. 6280 */ 6281 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 6282 { 6283 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6284 6285 #define GET_STAT(name) \ 6286 t4_read_reg64(adap, \ 6287 (is_t4(adap) ? \ 6288 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 6289 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 6290 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6291 6292 p->octets = GET_STAT(BYTES); 6293 p->frames = GET_STAT(FRAMES); 6294 p->bcast_frames = GET_STAT(BCAST); 6295 p->mcast_frames = GET_STAT(MCAST); 6296 p->ucast_frames = GET_STAT(UCAST); 6297 p->error_frames = GET_STAT(ERROR); 6298 6299 p->frames_64 = GET_STAT(64B); 6300 p->frames_65_127 = GET_STAT(65B_127B); 6301 p->frames_128_255 = GET_STAT(128B_255B); 6302 p->frames_256_511 = GET_STAT(256B_511B); 6303 p->frames_512_1023 = GET_STAT(512B_1023B); 6304 p->frames_1024_1518 = GET_STAT(1024B_1518B); 6305 p->frames_1519_max = GET_STAT(1519B_MAX); 6306 p->drop = GET_STAT(DROP_FRAMES); 6307 6308 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 6309 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 6310 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 6311 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 6312 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 6313 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 6314 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 6315 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 6316 6317 #undef GET_STAT 6318 #undef GET_STAT_COM 6319 } 6320 6321 /** 6322 * t4_wol_magic_enable - enable/disable magic packet WoL 6323 * @adap: the adapter 6324 * @port: the physical port index 6325 * @addr: MAC address expected in magic packets, %NULL to disable 6326 * 6327 * Enables/disables magic packet wake-on-LAN for the selected port. 6328 */ 6329 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 6330 const u8 *addr) 6331 { 6332 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 6333 6334 if (is_t4(adap)) { 6335 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 6336 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 6337 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6338 } else { 6339 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 6340 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 6341 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6342 } 6343 6344 if (addr) { 6345 t4_write_reg(adap, mag_id_reg_l, 6346 (addr[2] << 24) | (addr[3] << 16) | 6347 (addr[4] << 8) | addr[5]); 6348 t4_write_reg(adap, mag_id_reg_h, 6349 (addr[0] << 8) | addr[1]); 6350 } 6351 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 6352 V_MAGICEN(addr != NULL)); 6353 } 6354 6355 /** 6356 * t4_wol_pat_enable - enable/disable pattern-based WoL 6357 * @adap: the adapter 6358 * @port: the physical port index 6359 * @map: bitmap of which HW pattern filters to set 6360 * @mask0: byte mask for bytes 0-63 of a packet 6361 * @mask1: byte mask for bytes 64-127 of a packet 6362 * @crc: Ethernet CRC for selected bytes 6363 * @enable: enable/disable switch 6364 * 6365 * Sets the pattern filters indicated in @map to mask out the bytes 6366 * specified in @mask0/@mask1 in received packets and compare the CRC of 6367 * the resulting packet against @crc. If @enable is %true pattern-based 6368 * WoL is enabled, otherwise disabled. 6369 */ 6370 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 6371 u64 mask0, u64 mask1, unsigned int crc, bool enable) 6372 { 6373 int i; 6374 u32 port_cfg_reg; 6375 6376 if (is_t4(adap)) 6377 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6378 else 6379 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6380 6381 if (!enable) { 6382 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 6383 return 0; 6384 } 6385 if (map > 0xff) 6386 return -EINVAL; 6387 6388 #define EPIO_REG(name) \ 6389 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 6390 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 6391 6392 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 6393 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 6394 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 6395 6396 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 6397 if (!(map & 1)) 6398 continue; 6399 6400 /* write byte masks */ 6401 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 6402 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 6403 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6404 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6405 return -ETIMEDOUT; 6406 6407 /* write CRC */ 6408 t4_write_reg(adap, EPIO_REG(DATA0), crc); 6409 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 6410 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6411 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6412 return -ETIMEDOUT; 6413 } 6414 #undef EPIO_REG 6415 6416 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 6417 return 0; 6418 } 6419 6420 /* t4_mk_filtdelwr - create a delete filter WR 6421 * @ftid: the filter ID 6422 * @wr: the filter work request to populate 6423 * @qid: ingress queue to receive the delete notification 6424 * 6425 * Creates a filter work request to delete the supplied filter. If @qid is 6426 * negative the delete notification is suppressed. 6427 */ 6428 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 6429 { 6430 memset(wr, 0, sizeof(*wr)); 6431 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 6432 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 6433 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 6434 V_FW_FILTER_WR_NOREPLY(qid < 0)); 6435 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 6436 if (qid >= 0) 6437 wr->rx_chan_rx_rpl_iq = 6438 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 6439 } 6440 6441 #define INIT_CMD(var, cmd, rd_wr) do { \ 6442 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 6443 F_FW_CMD_REQUEST | \ 6444 F_FW_CMD_##rd_wr); \ 6445 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 6446 } while (0) 6447 6448 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 6449 u32 addr, u32 val) 6450 { 6451 u32 ldst_addrspace; 6452 struct fw_ldst_cmd c; 6453 6454 memset(&c, 0, sizeof(c)); 6455 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 6456 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6457 F_FW_CMD_REQUEST | 6458 F_FW_CMD_WRITE | 6459 ldst_addrspace); 6460 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6461 c.u.addrval.addr = cpu_to_be32(addr); 6462 c.u.addrval.val = cpu_to_be32(val); 6463 6464 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6465 } 6466 6467 /** 6468 * t4_mdio_rd - read a PHY register through MDIO 6469 * @adap: the adapter 6470 * @mbox: mailbox to use for the FW command 6471 * @phy_addr: the PHY address 6472 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6473 * @reg: the register to read 6474 * @valp: where to store the value 6475 * 6476 * Issues a FW command through the given mailbox to read a PHY register. 6477 */ 6478 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6479 unsigned int mmd, unsigned int reg, unsigned int *valp) 6480 { 6481 int ret; 6482 u32 ldst_addrspace; 6483 struct fw_ldst_cmd c; 6484 6485 memset(&c, 0, sizeof(c)); 6486 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6487 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6488 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6489 ldst_addrspace); 6490 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6491 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6492 V_FW_LDST_CMD_MMD(mmd)); 6493 c.u.mdio.raddr = cpu_to_be16(reg); 6494 6495 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6496 if (ret == 0) 6497 *valp = be16_to_cpu(c.u.mdio.rval); 6498 return ret; 6499 } 6500 6501 /** 6502 * t4_mdio_wr - write a PHY register through MDIO 6503 * @adap: the adapter 6504 * @mbox: mailbox to use for the FW command 6505 * @phy_addr: the PHY address 6506 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6507 * @reg: the register to write 6508 * @valp: value to write 6509 * 6510 * Issues a FW command through the given mailbox to write a PHY register. 6511 */ 6512 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6513 unsigned int mmd, unsigned int reg, unsigned int val) 6514 { 6515 u32 ldst_addrspace; 6516 struct fw_ldst_cmd c; 6517 6518 memset(&c, 0, sizeof(c)); 6519 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6520 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6521 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 6522 ldst_addrspace); 6523 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6524 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6525 V_FW_LDST_CMD_MMD(mmd)); 6526 c.u.mdio.raddr = cpu_to_be16(reg); 6527 c.u.mdio.rval = cpu_to_be16(val); 6528 6529 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6530 } 6531 6532 /** 6533 * 6534 * t4_sge_decode_idma_state - decode the idma state 6535 * @adap: the adapter 6536 * @state: the state idma is stuck in 6537 */ 6538 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 6539 { 6540 static const char * const t4_decode[] = { 6541 "IDMA_IDLE", 6542 "IDMA_PUSH_MORE_CPL_FIFO", 6543 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6544 "Not used", 6545 "IDMA_PHYSADDR_SEND_PCIEHDR", 6546 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6547 "IDMA_PHYSADDR_SEND_PAYLOAD", 6548 "IDMA_SEND_FIFO_TO_IMSG", 6549 "IDMA_FL_REQ_DATA_FL_PREP", 6550 "IDMA_FL_REQ_DATA_FL", 6551 "IDMA_FL_DROP", 6552 "IDMA_FL_H_REQ_HEADER_FL", 6553 "IDMA_FL_H_SEND_PCIEHDR", 6554 "IDMA_FL_H_PUSH_CPL_FIFO", 6555 "IDMA_FL_H_SEND_CPL", 6556 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6557 "IDMA_FL_H_SEND_IP_HDR", 6558 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6559 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6560 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6561 "IDMA_FL_D_SEND_PCIEHDR", 6562 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6563 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6564 "IDMA_FL_SEND_PCIEHDR", 6565 "IDMA_FL_PUSH_CPL_FIFO", 6566 "IDMA_FL_SEND_CPL", 6567 "IDMA_FL_SEND_PAYLOAD_FIRST", 6568 "IDMA_FL_SEND_PAYLOAD", 6569 "IDMA_FL_REQ_NEXT_DATA_FL", 6570 "IDMA_FL_SEND_NEXT_PCIEHDR", 6571 "IDMA_FL_SEND_PADDING", 6572 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6573 "IDMA_FL_SEND_FIFO_TO_IMSG", 6574 "IDMA_FL_REQ_DATAFL_DONE", 6575 "IDMA_FL_REQ_HEADERFL_DONE", 6576 }; 6577 static const char * const t5_decode[] = { 6578 "IDMA_IDLE", 6579 "IDMA_ALMOST_IDLE", 6580 "IDMA_PUSH_MORE_CPL_FIFO", 6581 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6582 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6583 "IDMA_PHYSADDR_SEND_PCIEHDR", 6584 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6585 "IDMA_PHYSADDR_SEND_PAYLOAD", 6586 "IDMA_SEND_FIFO_TO_IMSG", 6587 "IDMA_FL_REQ_DATA_FL", 6588 "IDMA_FL_DROP", 6589 "IDMA_FL_DROP_SEND_INC", 6590 "IDMA_FL_H_REQ_HEADER_FL", 6591 "IDMA_FL_H_SEND_PCIEHDR", 6592 "IDMA_FL_H_PUSH_CPL_FIFO", 6593 "IDMA_FL_H_SEND_CPL", 6594 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6595 "IDMA_FL_H_SEND_IP_HDR", 6596 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6597 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6598 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6599 "IDMA_FL_D_SEND_PCIEHDR", 6600 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6601 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6602 "IDMA_FL_SEND_PCIEHDR", 6603 "IDMA_FL_PUSH_CPL_FIFO", 6604 "IDMA_FL_SEND_CPL", 6605 "IDMA_FL_SEND_PAYLOAD_FIRST", 6606 "IDMA_FL_SEND_PAYLOAD", 6607 "IDMA_FL_REQ_NEXT_DATA_FL", 6608 "IDMA_FL_SEND_NEXT_PCIEHDR", 6609 "IDMA_FL_SEND_PADDING", 6610 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6611 }; 6612 static const char * const t6_decode[] = { 6613 "IDMA_IDLE", 6614 "IDMA_PUSH_MORE_CPL_FIFO", 6615 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6616 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6617 "IDMA_PHYSADDR_SEND_PCIEHDR", 6618 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6619 "IDMA_PHYSADDR_SEND_PAYLOAD", 6620 "IDMA_FL_REQ_DATA_FL", 6621 "IDMA_FL_DROP", 6622 "IDMA_FL_DROP_SEND_INC", 6623 "IDMA_FL_H_REQ_HEADER_FL", 6624 "IDMA_FL_H_SEND_PCIEHDR", 6625 "IDMA_FL_H_PUSH_CPL_FIFO", 6626 "IDMA_FL_H_SEND_CPL", 6627 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6628 "IDMA_FL_H_SEND_IP_HDR", 6629 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6630 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6631 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6632 "IDMA_FL_D_SEND_PCIEHDR", 6633 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6634 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6635 "IDMA_FL_SEND_PCIEHDR", 6636 "IDMA_FL_PUSH_CPL_FIFO", 6637 "IDMA_FL_SEND_CPL", 6638 "IDMA_FL_SEND_PAYLOAD_FIRST", 6639 "IDMA_FL_SEND_PAYLOAD", 6640 "IDMA_FL_REQ_NEXT_DATA_FL", 6641 "IDMA_FL_SEND_NEXT_PCIEHDR", 6642 "IDMA_FL_SEND_PADDING", 6643 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6644 }; 6645 static const u32 sge_regs[] = { 6646 A_SGE_DEBUG_DATA_LOW_INDEX_2, 6647 A_SGE_DEBUG_DATA_LOW_INDEX_3, 6648 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 6649 }; 6650 const char * const *sge_idma_decode; 6651 int sge_idma_decode_nstates; 6652 int i; 6653 unsigned int chip_version = chip_id(adapter); 6654 6655 /* Select the right set of decode strings to dump depending on the 6656 * adapter chip type. 6657 */ 6658 switch (chip_version) { 6659 case CHELSIO_T4: 6660 sge_idma_decode = (const char * const *)t4_decode; 6661 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 6662 break; 6663 6664 case CHELSIO_T5: 6665 sge_idma_decode = (const char * const *)t5_decode; 6666 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 6667 break; 6668 6669 case CHELSIO_T6: 6670 sge_idma_decode = (const char * const *)t6_decode; 6671 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 6672 break; 6673 6674 default: 6675 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 6676 return; 6677 } 6678 6679 if (state < sge_idma_decode_nstates) 6680 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 6681 else 6682 CH_WARN(adapter, "idma state %d unknown\n", state); 6683 6684 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 6685 CH_WARN(adapter, "SGE register %#x value %#x\n", 6686 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 6687 } 6688 6689 /** 6690 * t4_sge_ctxt_flush - flush the SGE context cache 6691 * @adap: the adapter 6692 * @mbox: mailbox to use for the FW command 6693 * 6694 * Issues a FW command through the given mailbox to flush the 6695 * SGE context cache. 6696 */ 6697 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 6698 { 6699 int ret; 6700 u32 ldst_addrspace; 6701 struct fw_ldst_cmd c; 6702 6703 memset(&c, 0, sizeof(c)); 6704 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC); 6705 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6706 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6707 ldst_addrspace); 6708 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6709 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 6710 6711 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6712 return ret; 6713 } 6714 6715 /** 6716 * t4_fw_hello - establish communication with FW 6717 * @adap: the adapter 6718 * @mbox: mailbox to use for the FW command 6719 * @evt_mbox: mailbox to receive async FW events 6720 * @master: specifies the caller's willingness to be the device master 6721 * @state: returns the current device state (if non-NULL) 6722 * 6723 * Issues a command to establish communication with FW. Returns either 6724 * an error (negative integer) or the mailbox of the Master PF. 6725 */ 6726 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 6727 enum dev_master master, enum dev_state *state) 6728 { 6729 int ret; 6730 struct fw_hello_cmd c; 6731 u32 v; 6732 unsigned int master_mbox; 6733 int retries = FW_CMD_HELLO_RETRIES; 6734 6735 retry: 6736 memset(&c, 0, sizeof(c)); 6737 INIT_CMD(c, HELLO, WRITE); 6738 c.err_to_clearinit = cpu_to_be32( 6739 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 6740 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 6741 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 6742 mbox : M_FW_HELLO_CMD_MBMASTER) | 6743 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 6744 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 6745 F_FW_HELLO_CMD_CLEARINIT); 6746 6747 /* 6748 * Issue the HELLO command to the firmware. If it's not successful 6749 * but indicates that we got a "busy" or "timeout" condition, retry 6750 * the HELLO until we exhaust our retry limit. If we do exceed our 6751 * retry limit, check to see if the firmware left us any error 6752 * information and report that if so ... 6753 */ 6754 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6755 if (ret != FW_SUCCESS) { 6756 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 6757 goto retry; 6758 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 6759 t4_report_fw_error(adap); 6760 return ret; 6761 } 6762 6763 v = be32_to_cpu(c.err_to_clearinit); 6764 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 6765 if (state) { 6766 if (v & F_FW_HELLO_CMD_ERR) 6767 *state = DEV_STATE_ERR; 6768 else if (v & F_FW_HELLO_CMD_INIT) 6769 *state = DEV_STATE_INIT; 6770 else 6771 *state = DEV_STATE_UNINIT; 6772 } 6773 6774 /* 6775 * If we're not the Master PF then we need to wait around for the 6776 * Master PF Driver to finish setting up the adapter. 6777 * 6778 * Note that we also do this wait if we're a non-Master-capable PF and 6779 * there is no current Master PF; a Master PF may show up momentarily 6780 * and we wouldn't want to fail pointlessly. (This can happen when an 6781 * OS loads lots of different drivers rapidly at the same time). In 6782 * this case, the Master PF returned by the firmware will be 6783 * M_PCIE_FW_MASTER so the test below will work ... 6784 */ 6785 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 6786 master_mbox != mbox) { 6787 int waiting = FW_CMD_HELLO_TIMEOUT; 6788 6789 /* 6790 * Wait for the firmware to either indicate an error or 6791 * initialized state. If we see either of these we bail out 6792 * and report the issue to the caller. If we exhaust the 6793 * "hello timeout" and we haven't exhausted our retries, try 6794 * again. Otherwise bail with a timeout error. 6795 */ 6796 for (;;) { 6797 u32 pcie_fw; 6798 6799 msleep(50); 6800 waiting -= 50; 6801 6802 /* 6803 * If neither Error nor Initialialized are indicated 6804 * by the firmware keep waiting till we exhaust our 6805 * timeout ... and then retry if we haven't exhausted 6806 * our retries ... 6807 */ 6808 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 6809 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 6810 if (waiting <= 0) { 6811 if (retries-- > 0) 6812 goto retry; 6813 6814 return -ETIMEDOUT; 6815 } 6816 continue; 6817 } 6818 6819 /* 6820 * We either have an Error or Initialized condition 6821 * report errors preferentially. 6822 */ 6823 if (state) { 6824 if (pcie_fw & F_PCIE_FW_ERR) 6825 *state = DEV_STATE_ERR; 6826 else if (pcie_fw & F_PCIE_FW_INIT) 6827 *state = DEV_STATE_INIT; 6828 } 6829 6830 /* 6831 * If we arrived before a Master PF was selected and 6832 * there's not a valid Master PF, grab its identity 6833 * for our caller. 6834 */ 6835 if (master_mbox == M_PCIE_FW_MASTER && 6836 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 6837 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 6838 break; 6839 } 6840 } 6841 6842 return master_mbox; 6843 } 6844 6845 /** 6846 * t4_fw_bye - end communication with FW 6847 * @adap: the adapter 6848 * @mbox: mailbox to use for the FW command 6849 * 6850 * Issues a command to terminate communication with FW. 6851 */ 6852 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 6853 { 6854 struct fw_bye_cmd c; 6855 6856 memset(&c, 0, sizeof(c)); 6857 INIT_CMD(c, BYE, WRITE); 6858 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6859 } 6860 6861 /** 6862 * t4_fw_reset - issue a reset to FW 6863 * @adap: the adapter 6864 * @mbox: mailbox to use for the FW command 6865 * @reset: specifies the type of reset to perform 6866 * 6867 * Issues a reset command of the specified type to FW. 6868 */ 6869 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 6870 { 6871 struct fw_reset_cmd c; 6872 6873 memset(&c, 0, sizeof(c)); 6874 INIT_CMD(c, RESET, WRITE); 6875 c.val = cpu_to_be32(reset); 6876 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6877 } 6878 6879 /** 6880 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 6881 * @adap: the adapter 6882 * @mbox: mailbox to use for the FW RESET command (if desired) 6883 * @force: force uP into RESET even if FW RESET command fails 6884 * 6885 * Issues a RESET command to firmware (if desired) with a HALT indication 6886 * and then puts the microprocessor into RESET state. The RESET command 6887 * will only be issued if a legitimate mailbox is provided (mbox <= 6888 * M_PCIE_FW_MASTER). 6889 * 6890 * This is generally used in order for the host to safely manipulate the 6891 * adapter without fear of conflicting with whatever the firmware might 6892 * be doing. The only way out of this state is to RESTART the firmware 6893 * ... 6894 */ 6895 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 6896 { 6897 int ret = 0; 6898 6899 /* 6900 * If a legitimate mailbox is provided, issue a RESET command 6901 * with a HALT indication. 6902 */ 6903 if (mbox <= M_PCIE_FW_MASTER) { 6904 struct fw_reset_cmd c; 6905 6906 memset(&c, 0, sizeof(c)); 6907 INIT_CMD(c, RESET, WRITE); 6908 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 6909 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 6910 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6911 } 6912 6913 /* 6914 * Normally we won't complete the operation if the firmware RESET 6915 * command fails but if our caller insists we'll go ahead and put the 6916 * uP into RESET. This can be useful if the firmware is hung or even 6917 * missing ... We'll have to take the risk of putting the uP into 6918 * RESET without the cooperation of firmware in that case. 6919 * 6920 * We also force the firmware's HALT flag to be on in case we bypassed 6921 * the firmware RESET command above or we're dealing with old firmware 6922 * which doesn't have the HALT capability. This will serve as a flag 6923 * for the incoming firmware to know that it's coming out of a HALT 6924 * rather than a RESET ... if it's new enough to understand that ... 6925 */ 6926 if (ret == 0 || force) { 6927 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 6928 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 6929 F_PCIE_FW_HALT); 6930 } 6931 6932 /* 6933 * And we always return the result of the firmware RESET command 6934 * even when we force the uP into RESET ... 6935 */ 6936 return ret; 6937 } 6938 6939 /** 6940 * t4_fw_restart - restart the firmware by taking the uP out of RESET 6941 * @adap: the adapter 6942 * @reset: if we want to do a RESET to restart things 6943 * 6944 * Restart firmware previously halted by t4_fw_halt(). On successful 6945 * return the previous PF Master remains as the new PF Master and there 6946 * is no need to issue a new HELLO command, etc. 6947 * 6948 * We do this in two ways: 6949 * 6950 * 1. If we're dealing with newer firmware we'll simply want to take 6951 * the chip's microprocessor out of RESET. This will cause the 6952 * firmware to start up from its start vector. And then we'll loop 6953 * until the firmware indicates it's started again (PCIE_FW.HALT 6954 * reset to 0) or we timeout. 6955 * 6956 * 2. If we're dealing with older firmware then we'll need to RESET 6957 * the chip since older firmware won't recognize the PCIE_FW.HALT 6958 * flag and automatically RESET itself on startup. 6959 */ 6960 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 6961 { 6962 if (reset) { 6963 /* 6964 * Since we're directing the RESET instead of the firmware 6965 * doing it automatically, we need to clear the PCIE_FW.HALT 6966 * bit. 6967 */ 6968 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0); 6969 6970 /* 6971 * If we've been given a valid mailbox, first try to get the 6972 * firmware to do the RESET. If that works, great and we can 6973 * return success. Otherwise, if we haven't been given a 6974 * valid mailbox or the RESET command failed, fall back to 6975 * hitting the chip with a hammer. 6976 */ 6977 if (mbox <= M_PCIE_FW_MASTER) { 6978 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6979 msleep(100); 6980 if (t4_fw_reset(adap, mbox, 6981 F_PIORST | F_PIORSTMODE) == 0) 6982 return 0; 6983 } 6984 6985 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 6986 msleep(2000); 6987 } else { 6988 int ms; 6989 6990 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6991 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 6992 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 6993 return FW_SUCCESS; 6994 msleep(100); 6995 ms += 100; 6996 } 6997 return -ETIMEDOUT; 6998 } 6999 return 0; 7000 } 7001 7002 /** 7003 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7004 * @adap: the adapter 7005 * @mbox: mailbox to use for the FW RESET command (if desired) 7006 * @fw_data: the firmware image to write 7007 * @size: image size 7008 * @force: force upgrade even if firmware doesn't cooperate 7009 * 7010 * Perform all of the steps necessary for upgrading an adapter's 7011 * firmware image. Normally this requires the cooperation of the 7012 * existing firmware in order to halt all existing activities 7013 * but if an invalid mailbox token is passed in we skip that step 7014 * (though we'll still put the adapter microprocessor into RESET in 7015 * that case). 7016 * 7017 * On successful return the new firmware will have been loaded and 7018 * the adapter will have been fully RESET losing all previous setup 7019 * state. On unsuccessful return the adapter may be completely hosed ... 7020 * positive errno indicates that the adapter is ~probably~ intact, a 7021 * negative errno indicates that things are looking bad ... 7022 */ 7023 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7024 const u8 *fw_data, unsigned int size, int force) 7025 { 7026 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7027 unsigned int bootstrap = 7028 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7029 int reset, ret; 7030 7031 if (!t4_fw_matches_chip(adap, fw_hdr)) 7032 return -EINVAL; 7033 7034 if (!bootstrap) { 7035 ret = t4_fw_halt(adap, mbox, force); 7036 if (ret < 0 && !force) 7037 return ret; 7038 } 7039 7040 ret = t4_load_fw(adap, fw_data, size); 7041 if (ret < 0 || bootstrap) 7042 return ret; 7043 7044 /* 7045 * Older versions of the firmware don't understand the new 7046 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 7047 * restart. So for newly loaded older firmware we'll have to do the 7048 * RESET for it so it starts up on a clean slate. We can tell if 7049 * the newly loaded firmware will handle this right by checking 7050 * its header flags to see if it advertises the capability. 7051 */ 7052 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 7053 return t4_fw_restart(adap, mbox, reset); 7054 } 7055 7056 /* 7057 * Card doesn't have a firmware, install one. 7058 */ 7059 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data, 7060 unsigned int size) 7061 { 7062 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7063 unsigned int bootstrap = 7064 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7065 int ret; 7066 7067 if (!t4_fw_matches_chip(adap, fw_hdr) || bootstrap) 7068 return -EINVAL; 7069 7070 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7071 t4_write_reg(adap, A_PCIE_FW, 0); /* Clobber internal state */ 7072 ret = t4_load_fw(adap, fw_data, size); 7073 if (ret < 0) 7074 return ret; 7075 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 7076 msleep(1000); 7077 7078 return (0); 7079 } 7080 7081 /** 7082 * t4_fw_initialize - ask FW to initialize the device 7083 * @adap: the adapter 7084 * @mbox: mailbox to use for the FW command 7085 * 7086 * Issues a command to FW to partially initialize the device. This 7087 * performs initialization that generally doesn't depend on user input. 7088 */ 7089 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7090 { 7091 struct fw_initialize_cmd c; 7092 7093 memset(&c, 0, sizeof(c)); 7094 INIT_CMD(c, INITIALIZE, WRITE); 7095 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7096 } 7097 7098 /** 7099 * t4_query_params_rw - query FW or device parameters 7100 * @adap: the adapter 7101 * @mbox: mailbox to use for the FW command 7102 * @pf: the PF 7103 * @vf: the VF 7104 * @nparams: the number of parameters 7105 * @params: the parameter names 7106 * @val: the parameter values 7107 * @rw: Write and read flag 7108 * 7109 * Reads the value of FW or device parameters. Up to 7 parameters can be 7110 * queried at once. 7111 */ 7112 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7113 unsigned int vf, unsigned int nparams, const u32 *params, 7114 u32 *val, int rw) 7115 { 7116 int i, ret; 7117 struct fw_params_cmd c; 7118 __be32 *p = &c.param[0].mnem; 7119 7120 if (nparams > 7) 7121 return -EINVAL; 7122 7123 memset(&c, 0, sizeof(c)); 7124 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7125 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7126 V_FW_PARAMS_CMD_PFN(pf) | 7127 V_FW_PARAMS_CMD_VFN(vf)); 7128 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7129 7130 for (i = 0; i < nparams; i++) { 7131 *p++ = cpu_to_be32(*params++); 7132 if (rw) 7133 *p = cpu_to_be32(*(val + i)); 7134 p++; 7135 } 7136 7137 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7138 if (ret == 0) 7139 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7140 *val++ = be32_to_cpu(*p); 7141 return ret; 7142 } 7143 7144 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7145 unsigned int vf, unsigned int nparams, const u32 *params, 7146 u32 *val) 7147 { 7148 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7149 } 7150 7151 /** 7152 * t4_set_params_timeout - sets FW or device parameters 7153 * @adap: the adapter 7154 * @mbox: mailbox to use for the FW command 7155 * @pf: the PF 7156 * @vf: the VF 7157 * @nparams: the number of parameters 7158 * @params: the parameter names 7159 * @val: the parameter values 7160 * @timeout: the timeout time 7161 * 7162 * Sets the value of FW or device parameters. Up to 7 parameters can be 7163 * specified at once. 7164 */ 7165 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7166 unsigned int pf, unsigned int vf, 7167 unsigned int nparams, const u32 *params, 7168 const u32 *val, int timeout) 7169 { 7170 struct fw_params_cmd c; 7171 __be32 *p = &c.param[0].mnem; 7172 7173 if (nparams > 7) 7174 return -EINVAL; 7175 7176 memset(&c, 0, sizeof(c)); 7177 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7178 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7179 V_FW_PARAMS_CMD_PFN(pf) | 7180 V_FW_PARAMS_CMD_VFN(vf)); 7181 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7182 7183 while (nparams--) { 7184 *p++ = cpu_to_be32(*params++); 7185 *p++ = cpu_to_be32(*val++); 7186 } 7187 7188 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7189 } 7190 7191 /** 7192 * t4_set_params - sets FW or device parameters 7193 * @adap: the adapter 7194 * @mbox: mailbox to use for the FW command 7195 * @pf: the PF 7196 * @vf: the VF 7197 * @nparams: the number of parameters 7198 * @params: the parameter names 7199 * @val: the parameter values 7200 * 7201 * Sets the value of FW or device parameters. Up to 7 parameters can be 7202 * specified at once. 7203 */ 7204 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7205 unsigned int vf, unsigned int nparams, const u32 *params, 7206 const u32 *val) 7207 { 7208 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7209 FW_CMD_MAX_TIMEOUT); 7210 } 7211 7212 /** 7213 * t4_cfg_pfvf - configure PF/VF resource limits 7214 * @adap: the adapter 7215 * @mbox: mailbox to use for the FW command 7216 * @pf: the PF being configured 7217 * @vf: the VF being configured 7218 * @txq: the max number of egress queues 7219 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7220 * @rxqi: the max number of interrupt-capable ingress queues 7221 * @rxq: the max number of interruptless ingress queues 7222 * @tc: the PCI traffic class 7223 * @vi: the max number of virtual interfaces 7224 * @cmask: the channel access rights mask for the PF/VF 7225 * @pmask: the port access rights mask for the PF/VF 7226 * @nexact: the maximum number of exact MPS filters 7227 * @rcaps: read capabilities 7228 * @wxcaps: write/execute capabilities 7229 * 7230 * Configures resource limits and capabilities for a physical or virtual 7231 * function. 7232 */ 7233 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7234 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7235 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7236 unsigned int vi, unsigned int cmask, unsigned int pmask, 7237 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7238 { 7239 struct fw_pfvf_cmd c; 7240 7241 memset(&c, 0, sizeof(c)); 7242 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7243 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7244 V_FW_PFVF_CMD_VFN(vf)); 7245 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7246 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7247 V_FW_PFVF_CMD_NIQ(rxq)); 7248 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7249 V_FW_PFVF_CMD_PMASK(pmask) | 7250 V_FW_PFVF_CMD_NEQ(txq)); 7251 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7252 V_FW_PFVF_CMD_NVI(vi) | 7253 V_FW_PFVF_CMD_NEXACTF(nexact)); 7254 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7255 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7256 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7257 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7258 } 7259 7260 /** 7261 * t4_alloc_vi_func - allocate a virtual interface 7262 * @adap: the adapter 7263 * @mbox: mailbox to use for the FW command 7264 * @port: physical port associated with the VI 7265 * @pf: the PF owning the VI 7266 * @vf: the VF owning the VI 7267 * @nmac: number of MAC addresses needed (1 to 5) 7268 * @mac: the MAC addresses of the VI 7269 * @rss_size: size of RSS table slice associated with this VI 7270 * @portfunc: which Port Application Function MAC Address is desired 7271 * @idstype: Intrusion Detection Type 7272 * 7273 * Allocates a virtual interface for the given physical port. If @mac is 7274 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7275 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7276 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7277 * stored consecutively so the space needed is @nmac * 6 bytes. 7278 * Returns a negative error number or the non-negative VI id. 7279 */ 7280 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7281 unsigned int port, unsigned int pf, unsigned int vf, 7282 unsigned int nmac, u8 *mac, u16 *rss_size, 7283 unsigned int portfunc, unsigned int idstype) 7284 { 7285 int ret; 7286 struct fw_vi_cmd c; 7287 7288 memset(&c, 0, sizeof(c)); 7289 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7290 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7291 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7292 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7293 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7294 V_FW_VI_CMD_FUNC(portfunc)); 7295 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7296 c.nmac = nmac - 1; 7297 if(!rss_size) 7298 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7299 7300 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7301 if (ret) 7302 return ret; 7303 7304 if (mac) { 7305 memcpy(mac, c.mac, sizeof(c.mac)); 7306 switch (nmac) { 7307 case 5: 7308 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7309 case 4: 7310 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7311 case 3: 7312 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7313 case 2: 7314 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7315 } 7316 } 7317 if (rss_size) 7318 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7319 return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7320 } 7321 7322 /** 7323 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7324 * @adap: the adapter 7325 * @mbox: mailbox to use for the FW command 7326 * @port: physical port associated with the VI 7327 * @pf: the PF owning the VI 7328 * @vf: the VF owning the VI 7329 * @nmac: number of MAC addresses needed (1 to 5) 7330 * @mac: the MAC addresses of the VI 7331 * @rss_size: size of RSS table slice associated with this VI 7332 * 7333 * backwards compatible and convieniance routine to allocate a Virtual 7334 * Interface with a Ethernet Port Application Function and Intrustion 7335 * Detection System disabled. 7336 */ 7337 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 7338 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 7339 u16 *rss_size) 7340 { 7341 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 7342 FW_VI_FUNC_ETH, 0); 7343 } 7344 7345 /** 7346 * t4_free_vi - free a virtual interface 7347 * @adap: the adapter 7348 * @mbox: mailbox to use for the FW command 7349 * @pf: the PF owning the VI 7350 * @vf: the VF owning the VI 7351 * @viid: virtual interface identifiler 7352 * 7353 * Free a previously allocated virtual interface. 7354 */ 7355 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 7356 unsigned int vf, unsigned int viid) 7357 { 7358 struct fw_vi_cmd c; 7359 7360 memset(&c, 0, sizeof(c)); 7361 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 7362 F_FW_CMD_REQUEST | 7363 F_FW_CMD_EXEC | 7364 V_FW_VI_CMD_PFN(pf) | 7365 V_FW_VI_CMD_VFN(vf)); 7366 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 7367 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 7368 7369 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7370 } 7371 7372 /** 7373 * t4_set_rxmode - set Rx properties of a virtual interface 7374 * @adap: the adapter 7375 * @mbox: mailbox to use for the FW command 7376 * @viid: the VI id 7377 * @mtu: the new MTU or -1 7378 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 7379 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 7380 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 7381 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 7382 * @sleep_ok: if true we may sleep while awaiting command completion 7383 * 7384 * Sets Rx properties of a virtual interface. 7385 */ 7386 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 7387 int mtu, int promisc, int all_multi, int bcast, int vlanex, 7388 bool sleep_ok) 7389 { 7390 struct fw_vi_rxmode_cmd c; 7391 7392 /* convert to FW values */ 7393 if (mtu < 0) 7394 mtu = M_FW_VI_RXMODE_CMD_MTU; 7395 if (promisc < 0) 7396 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 7397 if (all_multi < 0) 7398 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 7399 if (bcast < 0) 7400 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 7401 if (vlanex < 0) 7402 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 7403 7404 memset(&c, 0, sizeof(c)); 7405 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 7406 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7407 V_FW_VI_RXMODE_CMD_VIID(viid)); 7408 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7409 c.mtu_to_vlanexen = 7410 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 7411 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 7412 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 7413 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 7414 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 7415 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7416 } 7417 7418 /** 7419 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 7420 * @adap: the adapter 7421 * @mbox: mailbox to use for the FW command 7422 * @viid: the VI id 7423 * @free: if true any existing filters for this VI id are first removed 7424 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 7425 * @addr: the MAC address(es) 7426 * @idx: where to store the index of each allocated filter 7427 * @hash: pointer to hash address filter bitmap 7428 * @sleep_ok: call is allowed to sleep 7429 * 7430 * Allocates an exact-match filter for each of the supplied addresses and 7431 * sets it to the corresponding address. If @idx is not %NULL it should 7432 * have at least @naddr entries, each of which will be set to the index of 7433 * the filter allocated for the corresponding MAC address. If a filter 7434 * could not be allocated for an address its index is set to 0xffff. 7435 * If @hash is not %NULL addresses that fail to allocate an exact filter 7436 * are hashed and update the hash filter bitmap pointed at by @hash. 7437 * 7438 * Returns a negative error number or the number of filters allocated. 7439 */ 7440 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 7441 unsigned int viid, bool free, unsigned int naddr, 7442 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 7443 { 7444 int offset, ret = 0; 7445 struct fw_vi_mac_cmd c; 7446 unsigned int nfilters = 0; 7447 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 7448 unsigned int rem = naddr; 7449 7450 if (naddr > max_naddr) 7451 return -EINVAL; 7452 7453 for (offset = 0; offset < naddr ; /**/) { 7454 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 7455 ? rem 7456 : ARRAY_SIZE(c.u.exact)); 7457 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 7458 u.exact[fw_naddr]), 16); 7459 struct fw_vi_mac_exact *p; 7460 int i; 7461 7462 memset(&c, 0, sizeof(c)); 7463 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7464 F_FW_CMD_REQUEST | 7465 F_FW_CMD_WRITE | 7466 V_FW_CMD_EXEC(free) | 7467 V_FW_VI_MAC_CMD_VIID(viid)); 7468 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 7469 V_FW_CMD_LEN16(len16)); 7470 7471 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7472 p->valid_to_idx = 7473 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7474 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 7475 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 7476 } 7477 7478 /* 7479 * It's okay if we run out of space in our MAC address arena. 7480 * Some of the addresses we submit may get stored so we need 7481 * to run through the reply to see what the results were ... 7482 */ 7483 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 7484 if (ret && ret != -FW_ENOMEM) 7485 break; 7486 7487 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7488 u16 index = G_FW_VI_MAC_CMD_IDX( 7489 be16_to_cpu(p->valid_to_idx)); 7490 7491 if (idx) 7492 idx[offset+i] = (index >= max_naddr 7493 ? 0xffff 7494 : index); 7495 if (index < max_naddr) 7496 nfilters++; 7497 else if (hash) 7498 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 7499 } 7500 7501 free = false; 7502 offset += fw_naddr; 7503 rem -= fw_naddr; 7504 } 7505 7506 if (ret == 0 || ret == -FW_ENOMEM) 7507 ret = nfilters; 7508 return ret; 7509 } 7510 7511 /** 7512 * t4_change_mac - modifies the exact-match filter for a MAC address 7513 * @adap: the adapter 7514 * @mbox: mailbox to use for the FW command 7515 * @viid: the VI id 7516 * @idx: index of existing filter for old value of MAC address, or -1 7517 * @addr: the new MAC address value 7518 * @persist: whether a new MAC allocation should be persistent 7519 * @add_smt: if true also add the address to the HW SMT 7520 * 7521 * Modifies an exact-match filter and sets it to the new MAC address if 7522 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 7523 * latter case the address is added persistently if @persist is %true. 7524 * 7525 * Note that in general it is not possible to modify the value of a given 7526 * filter so the generic way to modify an address filter is to free the one 7527 * being used by the old address value and allocate a new filter for the 7528 * new address value. 7529 * 7530 * Returns a negative error number or the index of the filter with the new 7531 * MAC value. Note that this index may differ from @idx. 7532 */ 7533 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 7534 int idx, const u8 *addr, bool persist, bool add_smt) 7535 { 7536 int ret, mode; 7537 struct fw_vi_mac_cmd c; 7538 struct fw_vi_mac_exact *p = c.u.exact; 7539 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 7540 7541 if (idx < 0) /* new allocation */ 7542 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 7543 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 7544 7545 memset(&c, 0, sizeof(c)); 7546 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7547 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7548 V_FW_VI_MAC_CMD_VIID(viid)); 7549 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 7550 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7551 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 7552 V_FW_VI_MAC_CMD_IDX(idx)); 7553 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 7554 7555 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7556 if (ret == 0) { 7557 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 7558 if (ret >= max_mac_addr) 7559 ret = -ENOMEM; 7560 } 7561 return ret; 7562 } 7563 7564 /** 7565 * t4_set_addr_hash - program the MAC inexact-match hash filter 7566 * @adap: the adapter 7567 * @mbox: mailbox to use for the FW command 7568 * @viid: the VI id 7569 * @ucast: whether the hash filter should also match unicast addresses 7570 * @vec: the value to be written to the hash filter 7571 * @sleep_ok: call is allowed to sleep 7572 * 7573 * Sets the 64-bit inexact-match hash filter for a virtual interface. 7574 */ 7575 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 7576 bool ucast, u64 vec, bool sleep_ok) 7577 { 7578 struct fw_vi_mac_cmd c; 7579 u32 val; 7580 7581 memset(&c, 0, sizeof(c)); 7582 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7583 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7584 V_FW_VI_ENABLE_CMD_VIID(viid)); 7585 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 7586 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 7587 c.freemacs_to_len16 = cpu_to_be32(val); 7588 c.u.hash.hashvec = cpu_to_be64(vec); 7589 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7590 } 7591 7592 /** 7593 * t4_enable_vi_params - enable/disable a virtual interface 7594 * @adap: the adapter 7595 * @mbox: mailbox to use for the FW command 7596 * @viid: the VI id 7597 * @rx_en: 1=enable Rx, 0=disable Rx 7598 * @tx_en: 1=enable Tx, 0=disable Tx 7599 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 7600 * 7601 * Enables/disables a virtual interface. Note that setting DCB Enable 7602 * only makes sense when enabling a Virtual Interface ... 7603 */ 7604 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 7605 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 7606 { 7607 struct fw_vi_enable_cmd c; 7608 7609 memset(&c, 0, sizeof(c)); 7610 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7611 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7612 V_FW_VI_ENABLE_CMD_VIID(viid)); 7613 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 7614 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 7615 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 7616 FW_LEN16(c)); 7617 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 7618 } 7619 7620 /** 7621 * t4_enable_vi - enable/disable a virtual interface 7622 * @adap: the adapter 7623 * @mbox: mailbox to use for the FW command 7624 * @viid: the VI id 7625 * @rx_en: 1=enable Rx, 0=disable Rx 7626 * @tx_en: 1=enable Tx, 0=disable Tx 7627 * 7628 * Enables/disables a virtual interface. Note that setting DCB Enable 7629 * only makes sense when enabling a Virtual Interface ... 7630 */ 7631 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 7632 bool rx_en, bool tx_en) 7633 { 7634 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 7635 } 7636 7637 /** 7638 * t4_identify_port - identify a VI's port by blinking its LED 7639 * @adap: the adapter 7640 * @mbox: mailbox to use for the FW command 7641 * @viid: the VI id 7642 * @nblinks: how many times to blink LED at 2.5 Hz 7643 * 7644 * Identifies a VI's port by blinking its LED. 7645 */ 7646 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 7647 unsigned int nblinks) 7648 { 7649 struct fw_vi_enable_cmd c; 7650 7651 memset(&c, 0, sizeof(c)); 7652 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7653 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7654 V_FW_VI_ENABLE_CMD_VIID(viid)); 7655 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 7656 c.blinkdur = cpu_to_be16(nblinks); 7657 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7658 } 7659 7660 /** 7661 * t4_iq_stop - stop an ingress queue and its FLs 7662 * @adap: the adapter 7663 * @mbox: mailbox to use for the FW command 7664 * @pf: the PF owning the queues 7665 * @vf: the VF owning the queues 7666 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7667 * @iqid: ingress queue id 7668 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7669 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7670 * 7671 * Stops an ingress queue and its associated FLs, if any. This causes 7672 * any current or future data/messages destined for these queues to be 7673 * tossed. 7674 */ 7675 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 7676 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7677 unsigned int fl0id, unsigned int fl1id) 7678 { 7679 struct fw_iq_cmd c; 7680 7681 memset(&c, 0, sizeof(c)); 7682 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7683 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7684 V_FW_IQ_CMD_VFN(vf)); 7685 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 7686 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7687 c.iqid = cpu_to_be16(iqid); 7688 c.fl0id = cpu_to_be16(fl0id); 7689 c.fl1id = cpu_to_be16(fl1id); 7690 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7691 } 7692 7693 /** 7694 * t4_iq_free - free an ingress queue and its FLs 7695 * @adap: the adapter 7696 * @mbox: mailbox to use for the FW command 7697 * @pf: the PF owning the queues 7698 * @vf: the VF owning the queues 7699 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7700 * @iqid: ingress queue id 7701 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7702 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7703 * 7704 * Frees an ingress queue and its associated FLs, if any. 7705 */ 7706 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7707 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7708 unsigned int fl0id, unsigned int fl1id) 7709 { 7710 struct fw_iq_cmd c; 7711 7712 memset(&c, 0, sizeof(c)); 7713 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7714 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7715 V_FW_IQ_CMD_VFN(vf)); 7716 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 7717 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7718 c.iqid = cpu_to_be16(iqid); 7719 c.fl0id = cpu_to_be16(fl0id); 7720 c.fl1id = cpu_to_be16(fl1id); 7721 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7722 } 7723 7724 /** 7725 * t4_eth_eq_free - free an Ethernet egress queue 7726 * @adap: the adapter 7727 * @mbox: mailbox to use for the FW command 7728 * @pf: the PF owning the queue 7729 * @vf: the VF owning the queue 7730 * @eqid: egress queue id 7731 * 7732 * Frees an Ethernet egress queue. 7733 */ 7734 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7735 unsigned int vf, unsigned int eqid) 7736 { 7737 struct fw_eq_eth_cmd c; 7738 7739 memset(&c, 0, sizeof(c)); 7740 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 7741 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7742 V_FW_EQ_ETH_CMD_PFN(pf) | 7743 V_FW_EQ_ETH_CMD_VFN(vf)); 7744 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 7745 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 7746 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7747 } 7748 7749 /** 7750 * t4_ctrl_eq_free - free a control egress queue 7751 * @adap: the adapter 7752 * @mbox: mailbox to use for the FW command 7753 * @pf: the PF owning the queue 7754 * @vf: the VF owning the queue 7755 * @eqid: egress queue id 7756 * 7757 * Frees a control egress queue. 7758 */ 7759 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7760 unsigned int vf, unsigned int eqid) 7761 { 7762 struct fw_eq_ctrl_cmd c; 7763 7764 memset(&c, 0, sizeof(c)); 7765 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 7766 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7767 V_FW_EQ_CTRL_CMD_PFN(pf) | 7768 V_FW_EQ_CTRL_CMD_VFN(vf)); 7769 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 7770 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 7771 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7772 } 7773 7774 /** 7775 * t4_ofld_eq_free - free an offload egress queue 7776 * @adap: the adapter 7777 * @mbox: mailbox to use for the FW command 7778 * @pf: the PF owning the queue 7779 * @vf: the VF owning the queue 7780 * @eqid: egress queue id 7781 * 7782 * Frees a control egress queue. 7783 */ 7784 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7785 unsigned int vf, unsigned int eqid) 7786 { 7787 struct fw_eq_ofld_cmd c; 7788 7789 memset(&c, 0, sizeof(c)); 7790 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 7791 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7792 V_FW_EQ_OFLD_CMD_PFN(pf) | 7793 V_FW_EQ_OFLD_CMD_VFN(vf)); 7794 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 7795 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 7796 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7797 } 7798 7799 /** 7800 * t4_link_down_rc_str - return a string for a Link Down Reason Code 7801 * @link_down_rc: Link Down Reason Code 7802 * 7803 * Returns a string representation of the Link Down Reason Code. 7804 */ 7805 const char *t4_link_down_rc_str(unsigned char link_down_rc) 7806 { 7807 static const char *reason[] = { 7808 "Link Down", 7809 "Remote Fault", 7810 "Auto-negotiation Failure", 7811 "Reserved3", 7812 "Insufficient Airflow", 7813 "Unable To Determine Reason", 7814 "No RX Signal Detected", 7815 "Reserved7", 7816 }; 7817 7818 if (link_down_rc >= ARRAY_SIZE(reason)) 7819 return "Bad Reason Code"; 7820 7821 return reason[link_down_rc]; 7822 } 7823 7824 /* 7825 * Return the highest speed set in the port capabilities, in Mb/s. 7826 */ 7827 unsigned int fwcap_to_speed(uint32_t caps) 7828 { 7829 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 7830 do { \ 7831 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 7832 return __speed; \ 7833 } while (0) 7834 7835 TEST_SPEED_RETURN(400G, 400000); 7836 TEST_SPEED_RETURN(200G, 200000); 7837 TEST_SPEED_RETURN(100G, 100000); 7838 TEST_SPEED_RETURN(50G, 50000); 7839 TEST_SPEED_RETURN(40G, 40000); 7840 TEST_SPEED_RETURN(25G, 25000); 7841 TEST_SPEED_RETURN(10G, 10000); 7842 TEST_SPEED_RETURN(1G, 1000); 7843 TEST_SPEED_RETURN(100M, 100); 7844 7845 #undef TEST_SPEED_RETURN 7846 7847 return 0; 7848 } 7849 7850 /* 7851 * Return the port capabilities bit for the given speed, which is in Mb/s. 7852 */ 7853 uint32_t speed_to_fwcap(unsigned int speed) 7854 { 7855 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 7856 do { \ 7857 if (speed == __speed) \ 7858 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 7859 } while (0) 7860 7861 TEST_SPEED_RETURN(400G, 400000); 7862 TEST_SPEED_RETURN(200G, 200000); 7863 TEST_SPEED_RETURN(100G, 100000); 7864 TEST_SPEED_RETURN(50G, 50000); 7865 TEST_SPEED_RETURN(40G, 40000); 7866 TEST_SPEED_RETURN(25G, 25000); 7867 TEST_SPEED_RETURN(10G, 10000); 7868 TEST_SPEED_RETURN(1G, 1000); 7869 TEST_SPEED_RETURN(100M, 100); 7870 7871 #undef TEST_SPEED_RETURN 7872 7873 return 0; 7874 } 7875 7876 /* 7877 * Return the port capabilities bit for the highest speed in the capabilities. 7878 */ 7879 uint32_t fwcap_top_speed(uint32_t caps) 7880 { 7881 #define TEST_SPEED_RETURN(__caps_speed) \ 7882 do { \ 7883 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 7884 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 7885 } while (0) 7886 7887 TEST_SPEED_RETURN(400G); 7888 TEST_SPEED_RETURN(200G); 7889 TEST_SPEED_RETURN(100G); 7890 TEST_SPEED_RETURN(50G); 7891 TEST_SPEED_RETURN(40G); 7892 TEST_SPEED_RETURN(25G); 7893 TEST_SPEED_RETURN(10G); 7894 TEST_SPEED_RETURN(1G); 7895 TEST_SPEED_RETURN(100M); 7896 7897 #undef TEST_SPEED_RETURN 7898 7899 return 0; 7900 } 7901 7902 7903 /** 7904 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 7905 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 7906 * 7907 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 7908 * 32-bit Port Capabilities value. 7909 */ 7910 static uint32_t lstatus_to_fwcap(u32 lstatus) 7911 { 7912 uint32_t linkattr = 0; 7913 7914 /* 7915 * Unfortunately the format of the Link Status in the old 7916 * 16-bit Port Information message isn't the same as the 7917 * 16-bit Port Capabilities bitfield used everywhere else ... 7918 */ 7919 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 7920 linkattr |= FW_PORT_CAP32_FC_RX; 7921 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 7922 linkattr |= FW_PORT_CAP32_FC_TX; 7923 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 7924 linkattr |= FW_PORT_CAP32_SPEED_100M; 7925 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 7926 linkattr |= FW_PORT_CAP32_SPEED_1G; 7927 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 7928 linkattr |= FW_PORT_CAP32_SPEED_10G; 7929 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 7930 linkattr |= FW_PORT_CAP32_SPEED_25G; 7931 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 7932 linkattr |= FW_PORT_CAP32_SPEED_40G; 7933 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 7934 linkattr |= FW_PORT_CAP32_SPEED_100G; 7935 7936 return linkattr; 7937 } 7938 7939 /* 7940 * Updates all fields owned by the common code in port_info and link_config 7941 * based on information provided by the firmware. Does not touch any 7942 * requested_* field. 7943 */ 7944 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 7945 enum fw_port_action action, bool *mod_changed, bool *link_changed) 7946 { 7947 struct link_config old_lc, *lc = &pi->link_cfg; 7948 unsigned char fc, fec; 7949 u32 stat, linkattr; 7950 int old_ptype, old_mtype; 7951 7952 old_ptype = pi->port_type; 7953 old_mtype = pi->mod_type; 7954 old_lc = *lc; 7955 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 7956 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 7957 7958 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 7959 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 7960 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 7961 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 7962 7963 lc->supported = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 7964 lc->advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 7965 lc->lp_advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 7966 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 7967 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 7968 7969 linkattr = lstatus_to_fwcap(stat); 7970 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 7971 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 7972 7973 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 7974 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 7975 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 7976 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 7977 7978 lc->supported = be32_to_cpu(p->u.info32.pcaps32); 7979 lc->advertising = be32_to_cpu(p->u.info32.acaps32); 7980 lc->lp_advertising = be16_to_cpu(p->u.info32.lpacaps32); 7981 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 7982 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 7983 7984 linkattr = be32_to_cpu(p->u.info32.linkattr32); 7985 } else { 7986 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 7987 return; 7988 } 7989 7990 lc->speed = fwcap_to_speed(linkattr); 7991 7992 fc = 0; 7993 if (linkattr & FW_PORT_CAP32_FC_RX) 7994 fc |= PAUSE_RX; 7995 if (linkattr & FW_PORT_CAP32_FC_TX) 7996 fc |= PAUSE_TX; 7997 lc->fc = fc; 7998 7999 fec = FEC_NONE; 8000 if (linkattr & FW_PORT_CAP32_FEC_RS) 8001 fec |= FEC_RS; 8002 if (linkattr & FW_PORT_CAP32_FEC_BASER_RS) 8003 fec |= FEC_BASER_RS; 8004 lc->fec = fec; 8005 8006 if (mod_changed != NULL) 8007 *mod_changed = false; 8008 if (link_changed != NULL) 8009 *link_changed = false; 8010 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 8011 old_lc.supported != lc->supported) { 8012 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 8013 lc->fec_hint = lc->advertising & 8014 V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC); 8015 } 8016 if (mod_changed != NULL) 8017 *mod_changed = true; 8018 } 8019 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 8020 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 8021 if (link_changed != NULL) 8022 *link_changed = true; 8023 } 8024 } 8025 8026 /** 8027 * t4_update_port_info - retrieve and update port information if changed 8028 * @pi: the port_info 8029 * 8030 * We issue a Get Port Information Command to the Firmware and, if 8031 * successful, we check to see if anything is different from what we 8032 * last recorded and update things accordingly. 8033 */ 8034 int t4_update_port_info(struct port_info *pi) 8035 { 8036 struct adapter *sc = pi->adapter; 8037 struct fw_port_cmd cmd; 8038 enum fw_port_action action; 8039 int ret; 8040 8041 memset(&cmd, 0, sizeof(cmd)); 8042 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 8043 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8044 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 8045 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 8046 FW_PORT_ACTION_GET_PORT_INFO; 8047 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 8048 FW_LEN16(cmd)); 8049 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 8050 if (ret) 8051 return ret; 8052 8053 handle_port_info(pi, &cmd, action, NULL, NULL); 8054 return 0; 8055 } 8056 8057 /** 8058 * t4_handle_fw_rpl - process a FW reply message 8059 * @adap: the adapter 8060 * @rpl: start of the FW message 8061 * 8062 * Processes a FW message, such as link state change messages. 8063 */ 8064 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 8065 { 8066 u8 opcode = *(const u8 *)rpl; 8067 const struct fw_port_cmd *p = (const void *)rpl; 8068 enum fw_port_action action = 8069 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 8070 bool mod_changed, link_changed; 8071 8072 if (opcode == FW_PORT_CMD && 8073 (action == FW_PORT_ACTION_GET_PORT_INFO || 8074 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 8075 /* link/module state change message */ 8076 int i; 8077 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 8078 struct port_info *pi = NULL; 8079 struct link_config *lc; 8080 8081 for_each_port(adap, i) { 8082 pi = adap2pinfo(adap, i); 8083 if (pi->tx_chan == chan) 8084 break; 8085 } 8086 8087 lc = &pi->link_cfg; 8088 PORT_LOCK(pi); 8089 handle_port_info(pi, p, action, &mod_changed, &link_changed); 8090 PORT_UNLOCK(pi); 8091 if (mod_changed) 8092 t4_os_portmod_changed(pi); 8093 if (link_changed) { 8094 PORT_LOCK(pi); 8095 t4_os_link_changed(pi); 8096 PORT_UNLOCK(pi); 8097 } 8098 } else { 8099 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 8100 return -EINVAL; 8101 } 8102 return 0; 8103 } 8104 8105 /** 8106 * get_pci_mode - determine a card's PCI mode 8107 * @adapter: the adapter 8108 * @p: where to store the PCI settings 8109 * 8110 * Determines a card's PCI mode and associated parameters, such as speed 8111 * and width. 8112 */ 8113 static void get_pci_mode(struct adapter *adapter, 8114 struct pci_params *p) 8115 { 8116 u16 val; 8117 u32 pcie_cap; 8118 8119 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8120 if (pcie_cap) { 8121 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 8122 p->speed = val & PCI_EXP_LNKSTA_CLS; 8123 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 8124 } 8125 } 8126 8127 struct flash_desc { 8128 u32 vendor_and_model_id; 8129 u32 size_mb; 8130 }; 8131 8132 int t4_get_flash_params(struct adapter *adapter) 8133 { 8134 /* 8135 * Table for non-standard supported Flash parts. Note, all Flash 8136 * parts must have 64KB sectors. 8137 */ 8138 static struct flash_desc supported_flash[] = { 8139 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 8140 }; 8141 8142 int ret; 8143 u32 flashid = 0; 8144 unsigned int part, manufacturer; 8145 unsigned int density, size = 0; 8146 8147 8148 /* 8149 * Issue a Read ID Command to the Flash part. We decode supported 8150 * Flash parts and their sizes from this. There's a newer Query 8151 * Command which can retrieve detailed geometry information but many 8152 * Flash parts don't support it. 8153 */ 8154 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 8155 if (!ret) 8156 ret = sf1_read(adapter, 3, 0, 1, &flashid); 8157 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 8158 if (ret < 0) 8159 return ret; 8160 8161 /* 8162 * Check to see if it's one of our non-standard supported Flash parts. 8163 */ 8164 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 8165 if (supported_flash[part].vendor_and_model_id == flashid) { 8166 adapter->params.sf_size = 8167 supported_flash[part].size_mb; 8168 adapter->params.sf_nsec = 8169 adapter->params.sf_size / SF_SEC_SIZE; 8170 goto found; 8171 } 8172 8173 /* 8174 * Decode Flash part size. The code below looks repetative with 8175 * common encodings, but that's not guaranteed in the JEDEC 8176 * specification for the Read JADEC ID command. The only thing that 8177 * we're guaranteed by the JADEC specification is where the 8178 * Manufacturer ID is in the returned result. After that each 8179 * Manufacturer ~could~ encode things completely differently. 8180 * Note, all Flash parts must have 64KB sectors. 8181 */ 8182 manufacturer = flashid & 0xff; 8183 switch (manufacturer) { 8184 case 0x20: /* Micron/Numonix */ 8185 /* 8186 * This Density -> Size decoding table is taken from Micron 8187 * Data Sheets. 8188 */ 8189 density = (flashid >> 16) & 0xff; 8190 switch (density) { 8191 case 0x14: size = 1 << 20; break; /* 1MB */ 8192 case 0x15: size = 1 << 21; break; /* 2MB */ 8193 case 0x16: size = 1 << 22; break; /* 4MB */ 8194 case 0x17: size = 1 << 23; break; /* 8MB */ 8195 case 0x18: size = 1 << 24; break; /* 16MB */ 8196 case 0x19: size = 1 << 25; break; /* 32MB */ 8197 case 0x20: size = 1 << 26; break; /* 64MB */ 8198 case 0x21: size = 1 << 27; break; /* 128MB */ 8199 case 0x22: size = 1 << 28; break; /* 256MB */ 8200 } 8201 break; 8202 8203 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 8204 /* 8205 * This Density -> Size decoding table is taken from ISSI 8206 * Data Sheets. 8207 */ 8208 density = (flashid >> 16) & 0xff; 8209 switch (density) { 8210 case 0x16: size = 1 << 25; break; /* 32MB */ 8211 case 0x17: size = 1 << 26; break; /* 64MB */ 8212 } 8213 break; 8214 8215 case 0xc2: /* Macronix */ 8216 /* 8217 * This Density -> Size decoding table is taken from Macronix 8218 * Data Sheets. 8219 */ 8220 density = (flashid >> 16) & 0xff; 8221 switch (density) { 8222 case 0x17: size = 1 << 23; break; /* 8MB */ 8223 case 0x18: size = 1 << 24; break; /* 16MB */ 8224 } 8225 break; 8226 8227 case 0xef: /* Winbond */ 8228 /* 8229 * This Density -> Size decoding table is taken from Winbond 8230 * Data Sheets. 8231 */ 8232 density = (flashid >> 16) & 0xff; 8233 switch (density) { 8234 case 0x17: size = 1 << 23; break; /* 8MB */ 8235 case 0x18: size = 1 << 24; break; /* 16MB */ 8236 } 8237 break; 8238 } 8239 8240 /* If we didn't recognize the FLASH part, that's no real issue: the 8241 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 8242 * use a FLASH part which is at least 4MB in size and has 64KB 8243 * sectors. The unrecognized FLASH part is likely to be much larger 8244 * than 4MB, but that's all we really need. 8245 */ 8246 if (size == 0) { 8247 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 8248 size = 1 << 22; 8249 } 8250 8251 /* 8252 * Store decoded Flash size and fall through into vetting code. 8253 */ 8254 adapter->params.sf_size = size; 8255 adapter->params.sf_nsec = size / SF_SEC_SIZE; 8256 8257 found: 8258 /* 8259 * We should ~probably~ reject adapters with FLASHes which are too 8260 * small but we have some legacy FPGAs with small FLASHes that we'd 8261 * still like to use. So instead we emit a scary message ... 8262 */ 8263 if (adapter->params.sf_size < FLASH_MIN_SIZE) 8264 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 8265 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 8266 8267 return 0; 8268 } 8269 8270 static void set_pcie_completion_timeout(struct adapter *adapter, 8271 u8 range) 8272 { 8273 u16 val; 8274 u32 pcie_cap; 8275 8276 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8277 if (pcie_cap) { 8278 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 8279 val &= 0xfff0; 8280 val |= range ; 8281 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 8282 } 8283 } 8284 8285 const struct chip_params *t4_get_chip_params(int chipid) 8286 { 8287 static const struct chip_params chip_params[] = { 8288 { 8289 /* T4 */ 8290 .nchan = NCHAN, 8291 .pm_stats_cnt = PM_NSTATS, 8292 .cng_ch_bits_log = 2, 8293 .nsched_cls = 15, 8294 .cim_num_obq = CIM_NUM_OBQ, 8295 .mps_rplc_size = 128, 8296 .vfcount = 128, 8297 .sge_fl_db = F_DBPRIO, 8298 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 8299 }, 8300 { 8301 /* T5 */ 8302 .nchan = NCHAN, 8303 .pm_stats_cnt = PM_NSTATS, 8304 .cng_ch_bits_log = 2, 8305 .nsched_cls = 16, 8306 .cim_num_obq = CIM_NUM_OBQ_T5, 8307 .mps_rplc_size = 128, 8308 .vfcount = 128, 8309 .sge_fl_db = F_DBPRIO | F_DBTYPE, 8310 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8311 }, 8312 { 8313 /* T6 */ 8314 .nchan = T6_NCHAN, 8315 .pm_stats_cnt = T6_PM_NSTATS, 8316 .cng_ch_bits_log = 3, 8317 .nsched_cls = 16, 8318 .cim_num_obq = CIM_NUM_OBQ_T5, 8319 .mps_rplc_size = 256, 8320 .vfcount = 256, 8321 .sge_fl_db = 0, 8322 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8323 }, 8324 }; 8325 8326 chipid -= CHELSIO_T4; 8327 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 8328 return NULL; 8329 8330 return &chip_params[chipid]; 8331 } 8332 8333 /** 8334 * t4_prep_adapter - prepare SW and HW for operation 8335 * @adapter: the adapter 8336 * @buf: temporary space of at least VPD_LEN size provided by the caller. 8337 * 8338 * Initialize adapter SW state for the various HW modules, set initial 8339 * values for some adapter tunables, take PHYs out of reset, and 8340 * initialize the MDIO interface. 8341 */ 8342 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 8343 { 8344 int ret; 8345 uint16_t device_id; 8346 uint32_t pl_rev; 8347 8348 get_pci_mode(adapter, &adapter->params.pci); 8349 8350 pl_rev = t4_read_reg(adapter, A_PL_REV); 8351 adapter->params.chipid = G_CHIPID(pl_rev); 8352 adapter->params.rev = G_REV(pl_rev); 8353 if (adapter->params.chipid == 0) { 8354 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 8355 adapter->params.chipid = CHELSIO_T4; 8356 8357 /* T4A1 chip is not supported */ 8358 if (adapter->params.rev == 1) { 8359 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 8360 return -EINVAL; 8361 } 8362 } 8363 8364 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 8365 if (adapter->chip_params == NULL) 8366 return -EINVAL; 8367 8368 adapter->params.pci.vpd_cap_addr = 8369 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 8370 8371 ret = t4_get_flash_params(adapter); 8372 if (ret < 0) 8373 return ret; 8374 8375 /* Cards with real ASICs have the chipid in the PCIe device id */ 8376 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 8377 if (device_id >> 12 == chip_id(adapter)) 8378 adapter->params.cim_la_size = CIMLA_SIZE; 8379 else { 8380 /* FPGA */ 8381 adapter->params.fpga = 1; 8382 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 8383 } 8384 8385 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 8386 if (ret < 0) 8387 return ret; 8388 8389 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 8390 8391 /* 8392 * Default port and clock for debugging in case we can't reach FW. 8393 */ 8394 adapter->params.nports = 1; 8395 adapter->params.portvec = 1; 8396 adapter->params.vpd.cclk = 50000; 8397 8398 /* Set pci completion timeout value to 4 seconds. */ 8399 set_pcie_completion_timeout(adapter, 0xd); 8400 return 0; 8401 } 8402 8403 /** 8404 * t4_shutdown_adapter - shut down adapter, host & wire 8405 * @adapter: the adapter 8406 * 8407 * Perform an emergency shutdown of the adapter and stop it from 8408 * continuing any further communication on the ports or DMA to the 8409 * host. This is typically used when the adapter and/or firmware 8410 * have crashed and we want to prevent any further accidental 8411 * communication with the rest of the world. This will also force 8412 * the port Link Status to go down -- if register writes work -- 8413 * which should help our peers figure out that we're down. 8414 */ 8415 int t4_shutdown_adapter(struct adapter *adapter) 8416 { 8417 int port; 8418 8419 t4_intr_disable(adapter); 8420 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 8421 for_each_port(adapter, port) { 8422 u32 a_port_cfg = is_t4(adapter) ? 8423 PORT_REG(port, A_XGMAC_PORT_CFG) : 8424 T5_PORT_REG(port, A_MAC_PORT_CFG); 8425 8426 t4_write_reg(adapter, a_port_cfg, 8427 t4_read_reg(adapter, a_port_cfg) 8428 & ~V_SIGNAL_DET(1)); 8429 } 8430 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 8431 8432 return 0; 8433 } 8434 8435 /** 8436 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 8437 * @adapter: the adapter 8438 * @qid: the Queue ID 8439 * @qtype: the Ingress or Egress type for @qid 8440 * @user: true if this request is for a user mode queue 8441 * @pbar2_qoffset: BAR2 Queue Offset 8442 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 8443 * 8444 * Returns the BAR2 SGE Queue Registers information associated with the 8445 * indicated Absolute Queue ID. These are passed back in return value 8446 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 8447 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 8448 * 8449 * This may return an error which indicates that BAR2 SGE Queue 8450 * registers aren't available. If an error is not returned, then the 8451 * following values are returned: 8452 * 8453 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 8454 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 8455 * 8456 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 8457 * require the "Inferred Queue ID" ability may be used. E.g. the 8458 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 8459 * then these "Inferred Queue ID" register may not be used. 8460 */ 8461 int t4_bar2_sge_qregs(struct adapter *adapter, 8462 unsigned int qid, 8463 enum t4_bar2_qtype qtype, 8464 int user, 8465 u64 *pbar2_qoffset, 8466 unsigned int *pbar2_qid) 8467 { 8468 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 8469 u64 bar2_page_offset, bar2_qoffset; 8470 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 8471 8472 /* T4 doesn't support BAR2 SGE Queue registers for kernel 8473 * mode queues. 8474 */ 8475 if (!user && is_t4(adapter)) 8476 return -EINVAL; 8477 8478 /* Get our SGE Page Size parameters. 8479 */ 8480 page_shift = adapter->params.sge.page_shift; 8481 page_size = 1 << page_shift; 8482 8483 /* Get the right Queues per Page parameters for our Queue. 8484 */ 8485 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 8486 ? adapter->params.sge.eq_s_qpp 8487 : adapter->params.sge.iq_s_qpp); 8488 qpp_mask = (1 << qpp_shift) - 1; 8489 8490 /* Calculate the basics of the BAR2 SGE Queue register area: 8491 * o The BAR2 page the Queue registers will be in. 8492 * o The BAR2 Queue ID. 8493 * o The BAR2 Queue ID Offset into the BAR2 page. 8494 */ 8495 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 8496 bar2_qid = qid & qpp_mask; 8497 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 8498 8499 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 8500 * hardware will infer the Absolute Queue ID simply from the writes to 8501 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 8502 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 8503 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 8504 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 8505 * from the BAR2 Page and BAR2 Queue ID. 8506 * 8507 * One important censequence of this is that some BAR2 SGE registers 8508 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 8509 * there. But other registers synthesize the SGE Queue ID purely 8510 * from the writes to the registers -- the Write Combined Doorbell 8511 * Buffer is a good example. These BAR2 SGE Registers are only 8512 * available for those BAR2 SGE Register areas where the SGE Absolute 8513 * Queue ID can be inferred from simple writes. 8514 */ 8515 bar2_qoffset = bar2_page_offset; 8516 bar2_qinferred = (bar2_qid_offset < page_size); 8517 if (bar2_qinferred) { 8518 bar2_qoffset += bar2_qid_offset; 8519 bar2_qid = 0; 8520 } 8521 8522 *pbar2_qoffset = bar2_qoffset; 8523 *pbar2_qid = bar2_qid; 8524 return 0; 8525 } 8526 8527 /** 8528 * t4_init_devlog_params - initialize adapter->params.devlog 8529 * @adap: the adapter 8530 * @fw_attach: whether we can talk to the firmware 8531 * 8532 * Initialize various fields of the adapter's Firmware Device Log 8533 * Parameters structure. 8534 */ 8535 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 8536 { 8537 struct devlog_params *dparams = &adap->params.devlog; 8538 u32 pf_dparams; 8539 unsigned int devlog_meminfo; 8540 struct fw_devlog_cmd devlog_cmd; 8541 int ret; 8542 8543 /* If we're dealing with newer firmware, the Device Log Paramerters 8544 * are stored in a designated register which allows us to access the 8545 * Device Log even if we can't talk to the firmware. 8546 */ 8547 pf_dparams = 8548 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 8549 if (pf_dparams) { 8550 unsigned int nentries, nentries128; 8551 8552 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 8553 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 8554 8555 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 8556 nentries = (nentries128 + 1) * 128; 8557 dparams->size = nentries * sizeof(struct fw_devlog_e); 8558 8559 return 0; 8560 } 8561 8562 /* 8563 * For any failing returns ... 8564 */ 8565 memset(dparams, 0, sizeof *dparams); 8566 8567 /* 8568 * If we can't talk to the firmware, there's really nothing we can do 8569 * at this point. 8570 */ 8571 if (!fw_attach) 8572 return -ENXIO; 8573 8574 /* Otherwise, ask the firmware for it's Device Log Parameters. 8575 */ 8576 memset(&devlog_cmd, 0, sizeof devlog_cmd); 8577 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 8578 F_FW_CMD_REQUEST | F_FW_CMD_READ); 8579 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 8580 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 8581 &devlog_cmd); 8582 if (ret) 8583 return ret; 8584 8585 devlog_meminfo = 8586 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 8587 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 8588 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 8589 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 8590 8591 return 0; 8592 } 8593 8594 /** 8595 * t4_init_sge_params - initialize adap->params.sge 8596 * @adapter: the adapter 8597 * 8598 * Initialize various fields of the adapter's SGE Parameters structure. 8599 */ 8600 int t4_init_sge_params(struct adapter *adapter) 8601 { 8602 u32 r; 8603 struct sge_params *sp = &adapter->params.sge; 8604 unsigned i, tscale = 1; 8605 8606 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 8607 sp->counter_val[0] = G_THRESHOLD_0(r); 8608 sp->counter_val[1] = G_THRESHOLD_1(r); 8609 sp->counter_val[2] = G_THRESHOLD_2(r); 8610 sp->counter_val[3] = G_THRESHOLD_3(r); 8611 8612 if (chip_id(adapter) >= CHELSIO_T6) { 8613 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 8614 tscale = G_TSCALE(r); 8615 if (tscale == 0) 8616 tscale = 1; 8617 else 8618 tscale += 2; 8619 } 8620 8621 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 8622 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 8623 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 8624 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 8625 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 8626 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 8627 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 8628 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 8629 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 8630 8631 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 8632 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 8633 if (is_t4(adapter)) 8634 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 8635 else if (is_t5(adapter)) 8636 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 8637 else 8638 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 8639 8640 /* egress queues: log2 of # of doorbells per BAR2 page */ 8641 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 8642 r >>= S_QUEUESPERPAGEPF0 + 8643 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8644 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 8645 8646 /* ingress queues: log2 of # of doorbells per BAR2 page */ 8647 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 8648 r >>= S_QUEUESPERPAGEPF0 + 8649 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8650 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 8651 8652 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 8653 r >>= S_HOSTPAGESIZEPF0 + 8654 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 8655 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 8656 8657 r = t4_read_reg(adapter, A_SGE_CONTROL); 8658 sp->sge_control = r; 8659 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 8660 sp->fl_pktshift = G_PKTSHIFT(r); 8661 if (chip_id(adapter) <= CHELSIO_T5) { 8662 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8663 X_INGPADBOUNDARY_SHIFT); 8664 } else { 8665 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8666 X_T6_INGPADBOUNDARY_SHIFT); 8667 } 8668 if (is_t4(adapter)) 8669 sp->pack_boundary = sp->pad_boundary; 8670 else { 8671 r = t4_read_reg(adapter, A_SGE_CONTROL2); 8672 if (G_INGPACKBOUNDARY(r) == 0) 8673 sp->pack_boundary = 16; 8674 else 8675 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 8676 } 8677 for (i = 0; i < SGE_FLBUF_SIZES; i++) 8678 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 8679 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 8680 8681 return 0; 8682 } 8683 8684 /* 8685 * Read and cache the adapter's compressed filter mode and ingress config. 8686 */ 8687 static void read_filter_mode_and_ingress_config(struct adapter *adap, 8688 bool sleep_ok) 8689 { 8690 uint32_t v; 8691 struct tp_params *tpp = &adap->params.tp; 8692 8693 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP, 8694 sleep_ok); 8695 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG, 8696 sleep_ok); 8697 8698 /* 8699 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 8700 * shift positions of several elements of the Compressed Filter Tuple 8701 * for this adapter which we need frequently ... 8702 */ 8703 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 8704 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 8705 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 8706 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 8707 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 8708 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 8709 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 8710 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 8711 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 8712 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 8713 8714 if (chip_id(adap) > CHELSIO_T4) { 8715 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 8716 adap->params.tp.hash_filter_mask = v; 8717 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 8718 adap->params.tp.hash_filter_mask |= (u64)v << 32; 8719 } 8720 } 8721 8722 /** 8723 * t4_init_tp_params - initialize adap->params.tp 8724 * @adap: the adapter 8725 * 8726 * Initialize various fields of the adapter's TP Parameters structure. 8727 */ 8728 int t4_init_tp_params(struct adapter *adap, bool sleep_ok) 8729 { 8730 int chan; 8731 u32 v; 8732 struct tp_params *tpp = &adap->params.tp; 8733 8734 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 8735 tpp->tre = G_TIMERRESOLUTION(v); 8736 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 8737 8738 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 8739 for (chan = 0; chan < MAX_NCHAN; chan++) 8740 tpp->tx_modq[chan] = chan; 8741 8742 read_filter_mode_and_ingress_config(adap, sleep_ok); 8743 8744 /* 8745 * Cache a mask of the bits that represent the error vector portion of 8746 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room 8747 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE). 8748 */ 8749 tpp->err_vec_mask = htobe16(0xffff); 8750 if (chip_id(adap) > CHELSIO_T5) { 8751 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 8752 if (v & F_CRXPKTENC) { 8753 tpp->err_vec_mask = 8754 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC)); 8755 } 8756 } 8757 8758 return 0; 8759 } 8760 8761 /** 8762 * t4_filter_field_shift - calculate filter field shift 8763 * @adap: the adapter 8764 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 8765 * 8766 * Return the shift position of a filter field within the Compressed 8767 * Filter Tuple. The filter field is specified via its selection bit 8768 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 8769 */ 8770 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 8771 { 8772 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 8773 unsigned int sel; 8774 int field_shift; 8775 8776 if ((filter_mode & filter_sel) == 0) 8777 return -1; 8778 8779 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 8780 switch (filter_mode & sel) { 8781 case F_FCOE: 8782 field_shift += W_FT_FCOE; 8783 break; 8784 case F_PORT: 8785 field_shift += W_FT_PORT; 8786 break; 8787 case F_VNIC_ID: 8788 field_shift += W_FT_VNIC_ID; 8789 break; 8790 case F_VLAN: 8791 field_shift += W_FT_VLAN; 8792 break; 8793 case F_TOS: 8794 field_shift += W_FT_TOS; 8795 break; 8796 case F_PROTOCOL: 8797 field_shift += W_FT_PROTOCOL; 8798 break; 8799 case F_ETHERTYPE: 8800 field_shift += W_FT_ETHERTYPE; 8801 break; 8802 case F_MACMATCH: 8803 field_shift += W_FT_MACMATCH; 8804 break; 8805 case F_MPSHITTYPE: 8806 field_shift += W_FT_MPSHITTYPE; 8807 break; 8808 case F_FRAGMENTATION: 8809 field_shift += W_FT_FRAGMENTATION; 8810 break; 8811 } 8812 } 8813 return field_shift; 8814 } 8815 8816 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 8817 { 8818 u8 addr[6]; 8819 int ret, i, j; 8820 u16 rss_size; 8821 struct port_info *p = adap2pinfo(adap, port_id); 8822 u32 param, val; 8823 8824 for (i = 0, j = -1; i <= p->port_id; i++) { 8825 do { 8826 j++; 8827 } while ((adap->params.portvec & (1 << j)) == 0); 8828 } 8829 8830 p->tx_chan = j; 8831 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 8832 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 8833 p->lport = j; 8834 8835 if (!(adap->flags & IS_VF) || 8836 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 8837 t4_update_port_info(p); 8838 } 8839 8840 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 8841 if (ret < 0) 8842 return ret; 8843 8844 p->vi[0].viid = ret; 8845 if (chip_id(adap) <= CHELSIO_T5) 8846 p->vi[0].smt_idx = (ret & 0x7f) << 1; 8847 else 8848 p->vi[0].smt_idx = (ret & 0x7f); 8849 p->vi[0].rss_size = rss_size; 8850 t4_os_set_hw_addr(p, addr); 8851 8852 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8853 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 8854 V_FW_PARAMS_PARAM_YZ(p->vi[0].viid); 8855 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 8856 if (ret) 8857 p->vi[0].rss_base = 0xffff; 8858 else { 8859 /* MPASS((val >> 16) == rss_size); */ 8860 p->vi[0].rss_base = val & 0xffff; 8861 } 8862 8863 return 0; 8864 } 8865 8866 /** 8867 * t4_read_cimq_cfg - read CIM queue configuration 8868 * @adap: the adapter 8869 * @base: holds the queue base addresses in bytes 8870 * @size: holds the queue sizes in bytes 8871 * @thres: holds the queue full thresholds in bytes 8872 * 8873 * Returns the current configuration of the CIM queues, starting with 8874 * the IBQs, then the OBQs. 8875 */ 8876 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 8877 { 8878 unsigned int i, v; 8879 int cim_num_obq = adap->chip_params->cim_num_obq; 8880 8881 for (i = 0; i < CIM_NUM_IBQ; i++) { 8882 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 8883 V_QUENUMSELECT(i)); 8884 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8885 /* value is in 256-byte units */ 8886 *base++ = G_CIMQBASE(v) * 256; 8887 *size++ = G_CIMQSIZE(v) * 256; 8888 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 8889 } 8890 for (i = 0; i < cim_num_obq; i++) { 8891 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8892 V_QUENUMSELECT(i)); 8893 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8894 /* value is in 256-byte units */ 8895 *base++ = G_CIMQBASE(v) * 256; 8896 *size++ = G_CIMQSIZE(v) * 256; 8897 } 8898 } 8899 8900 /** 8901 * t4_read_cim_ibq - read the contents of a CIM inbound queue 8902 * @adap: the adapter 8903 * @qid: the queue index 8904 * @data: where to store the queue contents 8905 * @n: capacity of @data in 32-bit words 8906 * 8907 * Reads the contents of the selected CIM queue starting at address 0 up 8908 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8909 * error and the number of 32-bit words actually read on success. 8910 */ 8911 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8912 { 8913 int i, err, attempts; 8914 unsigned int addr; 8915 const unsigned int nwords = CIM_IBQ_SIZE * 4; 8916 8917 if (qid > 5 || (n & 3)) 8918 return -EINVAL; 8919 8920 addr = qid * nwords; 8921 if (n > nwords) 8922 n = nwords; 8923 8924 /* It might take 3-10ms before the IBQ debug read access is allowed. 8925 * Wait for 1 Sec with a delay of 1 usec. 8926 */ 8927 attempts = 1000000; 8928 8929 for (i = 0; i < n; i++, addr++) { 8930 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 8931 F_IBQDBGEN); 8932 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 8933 attempts, 1); 8934 if (err) 8935 return err; 8936 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 8937 } 8938 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 8939 return i; 8940 } 8941 8942 /** 8943 * t4_read_cim_obq - read the contents of a CIM outbound queue 8944 * @adap: the adapter 8945 * @qid: the queue index 8946 * @data: where to store the queue contents 8947 * @n: capacity of @data in 32-bit words 8948 * 8949 * Reads the contents of the selected CIM queue starting at address 0 up 8950 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8951 * error and the number of 32-bit words actually read on success. 8952 */ 8953 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8954 { 8955 int i, err; 8956 unsigned int addr, v, nwords; 8957 int cim_num_obq = adap->chip_params->cim_num_obq; 8958 8959 if ((qid > (cim_num_obq - 1)) || (n & 3)) 8960 return -EINVAL; 8961 8962 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8963 V_QUENUMSELECT(qid)); 8964 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8965 8966 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 8967 nwords = G_CIMQSIZE(v) * 64; /* same */ 8968 if (n > nwords) 8969 n = nwords; 8970 8971 for (i = 0; i < n; i++, addr++) { 8972 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 8973 F_OBQDBGEN); 8974 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 8975 2, 1); 8976 if (err) 8977 return err; 8978 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 8979 } 8980 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 8981 return i; 8982 } 8983 8984 enum { 8985 CIM_QCTL_BASE = 0, 8986 CIM_CTL_BASE = 0x2000, 8987 CIM_PBT_ADDR_BASE = 0x2800, 8988 CIM_PBT_LRF_BASE = 0x3000, 8989 CIM_PBT_DATA_BASE = 0x3800 8990 }; 8991 8992 /** 8993 * t4_cim_read - read a block from CIM internal address space 8994 * @adap: the adapter 8995 * @addr: the start address within the CIM address space 8996 * @n: number of words to read 8997 * @valp: where to store the result 8998 * 8999 * Reads a block of 4-byte words from the CIM intenal address space. 9000 */ 9001 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 9002 unsigned int *valp) 9003 { 9004 int ret = 0; 9005 9006 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 9007 return -EBUSY; 9008 9009 for ( ; !ret && n--; addr += 4) { 9010 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 9011 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 9012 0, 5, 2); 9013 if (!ret) 9014 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 9015 } 9016 return ret; 9017 } 9018 9019 /** 9020 * t4_cim_write - write a block into CIM internal address space 9021 * @adap: the adapter 9022 * @addr: the start address within the CIM address space 9023 * @n: number of words to write 9024 * @valp: set of values to write 9025 * 9026 * Writes a block of 4-byte words into the CIM intenal address space. 9027 */ 9028 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 9029 const unsigned int *valp) 9030 { 9031 int ret = 0; 9032 9033 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 9034 return -EBUSY; 9035 9036 for ( ; !ret && n--; addr += 4) { 9037 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 9038 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 9039 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 9040 0, 5, 2); 9041 } 9042 return ret; 9043 } 9044 9045 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 9046 unsigned int val) 9047 { 9048 return t4_cim_write(adap, addr, 1, &val); 9049 } 9050 9051 /** 9052 * t4_cim_ctl_read - read a block from CIM control region 9053 * @adap: the adapter 9054 * @addr: the start address within the CIM control region 9055 * @n: number of words to read 9056 * @valp: where to store the result 9057 * 9058 * Reads a block of 4-byte words from the CIM control region. 9059 */ 9060 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 9061 unsigned int *valp) 9062 { 9063 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 9064 } 9065 9066 /** 9067 * t4_cim_read_la - read CIM LA capture buffer 9068 * @adap: the adapter 9069 * @la_buf: where to store the LA data 9070 * @wrptr: the HW write pointer within the capture buffer 9071 * 9072 * Reads the contents of the CIM LA buffer with the most recent entry at 9073 * the end of the returned data and with the entry at @wrptr first. 9074 * We try to leave the LA in the running state we find it in. 9075 */ 9076 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 9077 { 9078 int i, ret; 9079 unsigned int cfg, val, idx; 9080 9081 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9082 if (ret) 9083 return ret; 9084 9085 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 9086 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 9087 if (ret) 9088 return ret; 9089 } 9090 9091 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9092 if (ret) 9093 goto restart; 9094 9095 idx = G_UPDBGLAWRPTR(val); 9096 if (wrptr) 9097 *wrptr = idx; 9098 9099 for (i = 0; i < adap->params.cim_la_size; i++) { 9100 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9101 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 9102 if (ret) 9103 break; 9104 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9105 if (ret) 9106 break; 9107 if (val & F_UPDBGLARDEN) { 9108 ret = -ETIMEDOUT; 9109 break; 9110 } 9111 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 9112 if (ret) 9113 break; 9114 9115 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */ 9116 idx = (idx + 1) & M_UPDBGLARDPTR; 9117 /* 9118 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 9119 * identify the 32-bit portion of the full 312-bit data 9120 */ 9121 if (is_t6(adap)) 9122 while ((idx & 0xf) > 9) 9123 idx = (idx + 1) % M_UPDBGLARDPTR; 9124 } 9125 restart: 9126 if (cfg & F_UPDBGLAEN) { 9127 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9128 cfg & ~F_UPDBGLARDEN); 9129 if (!ret) 9130 ret = r; 9131 } 9132 return ret; 9133 } 9134 9135 /** 9136 * t4_tp_read_la - read TP LA capture buffer 9137 * @adap: the adapter 9138 * @la_buf: where to store the LA data 9139 * @wrptr: the HW write pointer within the capture buffer 9140 * 9141 * Reads the contents of the TP LA buffer with the most recent entry at 9142 * the end of the returned data and with the entry at @wrptr first. 9143 * We leave the LA in the running state we find it in. 9144 */ 9145 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 9146 { 9147 bool last_incomplete; 9148 unsigned int i, cfg, val, idx; 9149 9150 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 9151 if (cfg & F_DBGLAENABLE) /* freeze LA */ 9152 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9153 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 9154 9155 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 9156 idx = G_DBGLAWPTR(val); 9157 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 9158 if (last_incomplete) 9159 idx = (idx + 1) & M_DBGLARPTR; 9160 if (wrptr) 9161 *wrptr = idx; 9162 9163 val &= 0xffff; 9164 val &= ~V_DBGLARPTR(M_DBGLARPTR); 9165 val |= adap->params.tp.la_mask; 9166 9167 for (i = 0; i < TPLA_SIZE; i++) { 9168 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 9169 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 9170 idx = (idx + 1) & M_DBGLARPTR; 9171 } 9172 9173 /* Wipe out last entry if it isn't valid */ 9174 if (last_incomplete) 9175 la_buf[TPLA_SIZE - 1] = ~0ULL; 9176 9177 if (cfg & F_DBGLAENABLE) /* restore running state */ 9178 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9179 cfg | adap->params.tp.la_mask); 9180 } 9181 9182 /* 9183 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 9184 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 9185 * state for more than the Warning Threshold then we'll issue a warning about 9186 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 9187 * appears to be hung every Warning Repeat second till the situation clears. 9188 * If the situation clears, we'll note that as well. 9189 */ 9190 #define SGE_IDMA_WARN_THRESH 1 9191 #define SGE_IDMA_WARN_REPEAT 300 9192 9193 /** 9194 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 9195 * @adapter: the adapter 9196 * @idma: the adapter IDMA Monitor state 9197 * 9198 * Initialize the state of an SGE Ingress DMA Monitor. 9199 */ 9200 void t4_idma_monitor_init(struct adapter *adapter, 9201 struct sge_idma_monitor_state *idma) 9202 { 9203 /* Initialize the state variables for detecting an SGE Ingress DMA 9204 * hang. The SGE has internal counters which count up on each clock 9205 * tick whenever the SGE finds its Ingress DMA State Engines in the 9206 * same state they were on the previous clock tick. The clock used is 9207 * the Core Clock so we have a limit on the maximum "time" they can 9208 * record; typically a very small number of seconds. For instance, 9209 * with a 600MHz Core Clock, we can only count up to a bit more than 9210 * 7s. So we'll synthesize a larger counter in order to not run the 9211 * risk of having the "timers" overflow and give us the flexibility to 9212 * maintain a Hung SGE State Machine of our own which operates across 9213 * a longer time frame. 9214 */ 9215 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 9216 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 9217 } 9218 9219 /** 9220 * t4_idma_monitor - monitor SGE Ingress DMA state 9221 * @adapter: the adapter 9222 * @idma: the adapter IDMA Monitor state 9223 * @hz: number of ticks/second 9224 * @ticks: number of ticks since the last IDMA Monitor call 9225 */ 9226 void t4_idma_monitor(struct adapter *adapter, 9227 struct sge_idma_monitor_state *idma, 9228 int hz, int ticks) 9229 { 9230 int i, idma_same_state_cnt[2]; 9231 9232 /* Read the SGE Debug Ingress DMA Same State Count registers. These 9233 * are counters inside the SGE which count up on each clock when the 9234 * SGE finds its Ingress DMA State Engines in the same states they 9235 * were in the previous clock. The counters will peg out at 9236 * 0xffffffff without wrapping around so once they pass the 1s 9237 * threshold they'll stay above that till the IDMA state changes. 9238 */ 9239 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 9240 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 9241 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9242 9243 for (i = 0; i < 2; i++) { 9244 u32 debug0, debug11; 9245 9246 /* If the Ingress DMA Same State Counter ("timer") is less 9247 * than 1s, then we can reset our synthesized Stall Timer and 9248 * continue. If we have previously emitted warnings about a 9249 * potential stalled Ingress Queue, issue a note indicating 9250 * that the Ingress Queue has resumed forward progress. 9251 */ 9252 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 9253 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 9254 CH_WARN(adapter, "SGE idma%d, queue %u, " 9255 "resumed after %d seconds\n", 9256 i, idma->idma_qid[i], 9257 idma->idma_stalled[i]/hz); 9258 idma->idma_stalled[i] = 0; 9259 continue; 9260 } 9261 9262 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 9263 * domain. The first time we get here it'll be because we 9264 * passed the 1s Threshold; each additional time it'll be 9265 * because the RX Timer Callback is being fired on its regular 9266 * schedule. 9267 * 9268 * If the stall is below our Potential Hung Ingress Queue 9269 * Warning Threshold, continue. 9270 */ 9271 if (idma->idma_stalled[i] == 0) { 9272 idma->idma_stalled[i] = hz; 9273 idma->idma_warn[i] = 0; 9274 } else { 9275 idma->idma_stalled[i] += ticks; 9276 idma->idma_warn[i] -= ticks; 9277 } 9278 9279 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 9280 continue; 9281 9282 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 9283 */ 9284 if (idma->idma_warn[i] > 0) 9285 continue; 9286 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 9287 9288 /* Read and save the SGE IDMA State and Queue ID information. 9289 * We do this every time in case it changes across time ... 9290 * can't be too careful ... 9291 */ 9292 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 9293 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9294 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 9295 9296 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 9297 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9298 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 9299 9300 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 9301 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 9302 i, idma->idma_qid[i], idma->idma_state[i], 9303 idma->idma_stalled[i]/hz, 9304 debug0, debug11); 9305 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 9306 } 9307 } 9308 9309 /** 9310 * t4_read_pace_tbl - read the pace table 9311 * @adap: the adapter 9312 * @pace_vals: holds the returned values 9313 * 9314 * Returns the values of TP's pace table in microseconds. 9315 */ 9316 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 9317 { 9318 unsigned int i, v; 9319 9320 for (i = 0; i < NTX_SCHED; i++) { 9321 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 9322 v = t4_read_reg(adap, A_TP_PACE_TABLE); 9323 pace_vals[i] = dack_ticks_to_usec(adap, v); 9324 } 9325 } 9326 9327 /** 9328 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 9329 * @adap: the adapter 9330 * @sched: the scheduler index 9331 * @kbps: the byte rate in Kbps 9332 * @ipg: the interpacket delay in tenths of nanoseconds 9333 * 9334 * Return the current configuration of a HW Tx scheduler. 9335 */ 9336 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 9337 unsigned int *ipg, bool sleep_ok) 9338 { 9339 unsigned int v, addr, bpt, cpt; 9340 9341 if (kbps) { 9342 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 9343 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9344 if (sched & 1) 9345 v >>= 16; 9346 bpt = (v >> 8) & 0xff; 9347 cpt = v & 0xff; 9348 if (!cpt) 9349 *kbps = 0; /* scheduler disabled */ 9350 else { 9351 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 9352 *kbps = (v * bpt) / 125; 9353 } 9354 } 9355 if (ipg) { 9356 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 9357 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9358 if (sched & 1) 9359 v >>= 16; 9360 v &= 0xffff; 9361 *ipg = (10000 * v) / core_ticks_per_usec(adap); 9362 } 9363 } 9364 9365 /** 9366 * t4_load_cfg - download config file 9367 * @adap: the adapter 9368 * @cfg_data: the cfg text file to write 9369 * @size: text file size 9370 * 9371 * Write the supplied config text file to the card's serial flash. 9372 */ 9373 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 9374 { 9375 int ret, i, n, cfg_addr; 9376 unsigned int addr; 9377 unsigned int flash_cfg_start_sec; 9378 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9379 9380 cfg_addr = t4_flash_cfg_addr(adap); 9381 if (cfg_addr < 0) 9382 return cfg_addr; 9383 9384 addr = cfg_addr; 9385 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9386 9387 if (size > FLASH_CFG_MAX_SIZE) { 9388 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 9389 FLASH_CFG_MAX_SIZE); 9390 return -EFBIG; 9391 } 9392 9393 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 9394 sf_sec_size); 9395 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9396 flash_cfg_start_sec + i - 1); 9397 /* 9398 * If size == 0 then we're simply erasing the FLASH sectors associated 9399 * with the on-adapter Firmware Configuration File. 9400 */ 9401 if (ret || size == 0) 9402 goto out; 9403 9404 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9405 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9406 if ( (size - i) < SF_PAGE_SIZE) 9407 n = size - i; 9408 else 9409 n = SF_PAGE_SIZE; 9410 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 9411 if (ret) 9412 goto out; 9413 9414 addr += SF_PAGE_SIZE; 9415 cfg_data += SF_PAGE_SIZE; 9416 } 9417 9418 out: 9419 if (ret) 9420 CH_ERR(adap, "config file %s failed %d\n", 9421 (size == 0 ? "clear" : "download"), ret); 9422 return ret; 9423 } 9424 9425 /** 9426 * t5_fw_init_extern_mem - initialize the external memory 9427 * @adap: the adapter 9428 * 9429 * Initializes the external memory on T5. 9430 */ 9431 int t5_fw_init_extern_mem(struct adapter *adap) 9432 { 9433 u32 params[1], val[1]; 9434 int ret; 9435 9436 if (!is_t5(adap)) 9437 return 0; 9438 9439 val[0] = 0xff; /* Initialize all MCs */ 9440 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9441 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 9442 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 9443 FW_CMD_MAX_TIMEOUT); 9444 9445 return ret; 9446 } 9447 9448 /* BIOS boot headers */ 9449 typedef struct pci_expansion_rom_header { 9450 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9451 u8 reserved[22]; /* Reserved per processor Architecture data */ 9452 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9453 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 9454 9455 /* Legacy PCI Expansion ROM Header */ 9456 typedef struct legacy_pci_expansion_rom_header { 9457 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9458 u8 size512; /* Current Image Size in units of 512 bytes */ 9459 u8 initentry_point[4]; 9460 u8 cksum; /* Checksum computed on the entire Image */ 9461 u8 reserved[16]; /* Reserved */ 9462 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 9463 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 9464 9465 /* EFI PCI Expansion ROM Header */ 9466 typedef struct efi_pci_expansion_rom_header { 9467 u8 signature[2]; // ROM signature. The value 0xaa55 9468 u8 initialization_size[2]; /* Units 512. Includes this header */ 9469 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 9470 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 9471 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 9472 u8 compression_type[2]; /* Compression type. */ 9473 /* 9474 * Compression type definition 9475 * 0x0: uncompressed 9476 * 0x1: Compressed 9477 * 0x2-0xFFFF: Reserved 9478 */ 9479 u8 reserved[8]; /* Reserved */ 9480 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 9481 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9482 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 9483 9484 /* PCI Data Structure Format */ 9485 typedef struct pcir_data_structure { /* PCI Data Structure */ 9486 u8 signature[4]; /* Signature. The string "PCIR" */ 9487 u8 vendor_id[2]; /* Vendor Identification */ 9488 u8 device_id[2]; /* Device Identification */ 9489 u8 vital_product[2]; /* Pointer to Vital Product Data */ 9490 u8 length[2]; /* PCIR Data Structure Length */ 9491 u8 revision; /* PCIR Data Structure Revision */ 9492 u8 class_code[3]; /* Class Code */ 9493 u8 image_length[2]; /* Image Length. Multiple of 512B */ 9494 u8 code_revision[2]; /* Revision Level of Code/Data */ 9495 u8 code_type; /* Code Type. */ 9496 /* 9497 * PCI Expansion ROM Code Types 9498 * 0x00: Intel IA-32, PC-AT compatible. Legacy 9499 * 0x01: Open Firmware standard for PCI. FCODE 9500 * 0x02: Hewlett-Packard PA RISC. HP reserved 9501 * 0x03: EFI Image. EFI 9502 * 0x04-0xFF: Reserved. 9503 */ 9504 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 9505 u8 reserved[2]; /* Reserved */ 9506 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 9507 9508 /* BOOT constants */ 9509 enum { 9510 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 9511 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 9512 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 9513 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 9514 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 9515 VENDOR_ID = 0x1425, /* Vendor ID */ 9516 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 9517 }; 9518 9519 /* 9520 * modify_device_id - Modifies the device ID of the Boot BIOS image 9521 * @adatper: the device ID to write. 9522 * @boot_data: the boot image to modify. 9523 * 9524 * Write the supplied device ID to the boot BIOS image. 9525 */ 9526 static void modify_device_id(int device_id, u8 *boot_data) 9527 { 9528 legacy_pci_exp_rom_header_t *header; 9529 pcir_data_t *pcir_header; 9530 u32 cur_header = 0; 9531 9532 /* 9533 * Loop through all chained images and change the device ID's 9534 */ 9535 while (1) { 9536 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 9537 pcir_header = (pcir_data_t *) &boot_data[cur_header + 9538 le16_to_cpu(*(u16*)header->pcir_offset)]; 9539 9540 /* 9541 * Only modify the Device ID if code type is Legacy or HP. 9542 * 0x00: Okay to modify 9543 * 0x01: FCODE. Do not be modify 9544 * 0x03: Okay to modify 9545 * 0x04-0xFF: Do not modify 9546 */ 9547 if (pcir_header->code_type == 0x00) { 9548 u8 csum = 0; 9549 int i; 9550 9551 /* 9552 * Modify Device ID to match current adatper 9553 */ 9554 *(u16*) pcir_header->device_id = device_id; 9555 9556 /* 9557 * Set checksum temporarily to 0. 9558 * We will recalculate it later. 9559 */ 9560 header->cksum = 0x0; 9561 9562 /* 9563 * Calculate and update checksum 9564 */ 9565 for (i = 0; i < (header->size512 * 512); i++) 9566 csum += (u8)boot_data[cur_header + i]; 9567 9568 /* 9569 * Invert summed value to create the checksum 9570 * Writing new checksum value directly to the boot data 9571 */ 9572 boot_data[cur_header + 7] = -csum; 9573 9574 } else if (pcir_header->code_type == 0x03) { 9575 9576 /* 9577 * Modify Device ID to match current adatper 9578 */ 9579 *(u16*) pcir_header->device_id = device_id; 9580 9581 } 9582 9583 9584 /* 9585 * Check indicator element to identify if this is the last 9586 * image in the ROM. 9587 */ 9588 if (pcir_header->indicator & 0x80) 9589 break; 9590 9591 /* 9592 * Move header pointer up to the next image in the ROM. 9593 */ 9594 cur_header += header->size512 * 512; 9595 } 9596 } 9597 9598 /* 9599 * t4_load_boot - download boot flash 9600 * @adapter: the adapter 9601 * @boot_data: the boot image to write 9602 * @boot_addr: offset in flash to write boot_data 9603 * @size: image size 9604 * 9605 * Write the supplied boot image to the card's serial flash. 9606 * The boot image has the following sections: a 28-byte header and the 9607 * boot image. 9608 */ 9609 int t4_load_boot(struct adapter *adap, u8 *boot_data, 9610 unsigned int boot_addr, unsigned int size) 9611 { 9612 pci_exp_rom_header_t *header; 9613 int pcir_offset ; 9614 pcir_data_t *pcir_header; 9615 int ret, addr; 9616 uint16_t device_id; 9617 unsigned int i; 9618 unsigned int boot_sector = (boot_addr * 1024 ); 9619 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9620 9621 /* 9622 * Make sure the boot image does not encroach on the firmware region 9623 */ 9624 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 9625 CH_ERR(adap, "boot image encroaching on firmware region\n"); 9626 return -EFBIG; 9627 } 9628 9629 /* 9630 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 9631 * and Boot configuration data sections. These 3 boot sections span 9632 * sectors 0 to 7 in flash and live right before the FW image location. 9633 */ 9634 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 9635 sf_sec_size); 9636 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 9637 (boot_sector >> 16) + i - 1); 9638 9639 /* 9640 * If size == 0 then we're simply erasing the FLASH sectors associated 9641 * with the on-adapter option ROM file 9642 */ 9643 if (ret || (size == 0)) 9644 goto out; 9645 9646 /* Get boot header */ 9647 header = (pci_exp_rom_header_t *)boot_data; 9648 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 9649 /* PCIR Data Structure */ 9650 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 9651 9652 /* 9653 * Perform some primitive sanity testing to avoid accidentally 9654 * writing garbage over the boot sectors. We ought to check for 9655 * more but it's not worth it for now ... 9656 */ 9657 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 9658 CH_ERR(adap, "boot image too small/large\n"); 9659 return -EFBIG; 9660 } 9661 9662 #ifndef CHELSIO_T4_DIAGS 9663 /* 9664 * Check BOOT ROM header signature 9665 */ 9666 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 9667 CH_ERR(adap, "Boot image missing signature\n"); 9668 return -EINVAL; 9669 } 9670 9671 /* 9672 * Check PCI header signature 9673 */ 9674 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 9675 CH_ERR(adap, "PCI header missing signature\n"); 9676 return -EINVAL; 9677 } 9678 9679 /* 9680 * Check Vendor ID matches Chelsio ID 9681 */ 9682 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 9683 CH_ERR(adap, "Vendor ID missing signature\n"); 9684 return -EINVAL; 9685 } 9686 #endif 9687 9688 /* 9689 * Retrieve adapter's device ID 9690 */ 9691 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 9692 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 9693 device_id = device_id & 0xf0ff; 9694 9695 /* 9696 * Check PCIE Device ID 9697 */ 9698 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 9699 /* 9700 * Change the device ID in the Boot BIOS image to match 9701 * the Device ID of the current adapter. 9702 */ 9703 modify_device_id(device_id, boot_data); 9704 } 9705 9706 /* 9707 * Skip over the first SF_PAGE_SIZE worth of data and write it after 9708 * we finish copying the rest of the boot image. This will ensure 9709 * that the BIOS boot header will only be written if the boot image 9710 * was written in full. 9711 */ 9712 addr = boot_sector; 9713 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 9714 addr += SF_PAGE_SIZE; 9715 boot_data += SF_PAGE_SIZE; 9716 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 9717 if (ret) 9718 goto out; 9719 } 9720 9721 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 9722 (const u8 *)header, 0); 9723 9724 out: 9725 if (ret) 9726 CH_ERR(adap, "boot image download failed, error %d\n", ret); 9727 return ret; 9728 } 9729 9730 /* 9731 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 9732 * @adapter: the adapter 9733 * 9734 * Return the address within the flash where the OptionROM Configuration 9735 * is stored, or an error if the device FLASH is too small to contain 9736 * a OptionROM Configuration. 9737 */ 9738 static int t4_flash_bootcfg_addr(struct adapter *adapter) 9739 { 9740 /* 9741 * If the device FLASH isn't large enough to hold a Firmware 9742 * Configuration File, return an error. 9743 */ 9744 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 9745 return -ENOSPC; 9746 9747 return FLASH_BOOTCFG_START; 9748 } 9749 9750 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 9751 { 9752 int ret, i, n, cfg_addr; 9753 unsigned int addr; 9754 unsigned int flash_cfg_start_sec; 9755 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9756 9757 cfg_addr = t4_flash_bootcfg_addr(adap); 9758 if (cfg_addr < 0) 9759 return cfg_addr; 9760 9761 addr = cfg_addr; 9762 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9763 9764 if (size > FLASH_BOOTCFG_MAX_SIZE) { 9765 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 9766 FLASH_BOOTCFG_MAX_SIZE); 9767 return -EFBIG; 9768 } 9769 9770 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 9771 sf_sec_size); 9772 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9773 flash_cfg_start_sec + i - 1); 9774 9775 /* 9776 * If size == 0 then we're simply erasing the FLASH sectors associated 9777 * with the on-adapter OptionROM Configuration File. 9778 */ 9779 if (ret || size == 0) 9780 goto out; 9781 9782 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9783 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9784 if ( (size - i) < SF_PAGE_SIZE) 9785 n = size - i; 9786 else 9787 n = SF_PAGE_SIZE; 9788 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 9789 if (ret) 9790 goto out; 9791 9792 addr += SF_PAGE_SIZE; 9793 cfg_data += SF_PAGE_SIZE; 9794 } 9795 9796 out: 9797 if (ret) 9798 CH_ERR(adap, "boot config data %s failed %d\n", 9799 (size == 0 ? "clear" : "download"), ret); 9800 return ret; 9801 } 9802 9803 /** 9804 * t4_set_filter_mode - configure the optional components of filter tuples 9805 * @adap: the adapter 9806 * @mode_map: a bitmap selcting which optional filter components to enable 9807 * @sleep_ok: if true we may sleep while awaiting command completion 9808 * 9809 * Sets the filter mode by selecting the optional components to enable 9810 * in filter tuples. Returns 0 on success and a negative error if the 9811 * requested mode needs more bits than are available for optional 9812 * components. 9813 */ 9814 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 9815 bool sleep_ok) 9816 { 9817 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 9818 9819 int i, nbits = 0; 9820 9821 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 9822 if (mode_map & (1 << i)) 9823 nbits += width[i]; 9824 if (nbits > FILTER_OPT_LEN) 9825 return -EINVAL; 9826 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok); 9827 read_filter_mode_and_ingress_config(adap, sleep_ok); 9828 9829 return 0; 9830 } 9831 9832 /** 9833 * t4_clr_port_stats - clear port statistics 9834 * @adap: the adapter 9835 * @idx: the port index 9836 * 9837 * Clear HW statistics for the given port. 9838 */ 9839 void t4_clr_port_stats(struct adapter *adap, int idx) 9840 { 9841 unsigned int i; 9842 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 9843 u32 port_base_addr; 9844 9845 if (is_t4(adap)) 9846 port_base_addr = PORT_BASE(idx); 9847 else 9848 port_base_addr = T5_PORT_BASE(idx); 9849 9850 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 9851 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 9852 t4_write_reg(adap, port_base_addr + i, 0); 9853 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 9854 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 9855 t4_write_reg(adap, port_base_addr + i, 0); 9856 for (i = 0; i < 4; i++) 9857 if (bgmap & (1 << i)) { 9858 t4_write_reg(adap, 9859 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 9860 t4_write_reg(adap, 9861 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 9862 } 9863 } 9864 9865 /** 9866 * t4_i2c_rd - read I2C data from adapter 9867 * @adap: the adapter 9868 * @port: Port number if per-port device; <0 if not 9869 * @devid: per-port device ID or absolute device ID 9870 * @offset: byte offset into device I2C space 9871 * @len: byte length of I2C space data 9872 * @buf: buffer in which to return I2C data 9873 * 9874 * Reads the I2C data from the indicated device and location. 9875 */ 9876 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 9877 int port, unsigned int devid, 9878 unsigned int offset, unsigned int len, 9879 u8 *buf) 9880 { 9881 u32 ldst_addrspace; 9882 struct fw_ldst_cmd ldst; 9883 int ret; 9884 9885 if (port >= 4 || 9886 devid >= 256 || 9887 offset >= 256 || 9888 len > sizeof ldst.u.i2c.data) 9889 return -EINVAL; 9890 9891 memset(&ldst, 0, sizeof ldst); 9892 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9893 ldst.op_to_addrspace = 9894 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9895 F_FW_CMD_REQUEST | 9896 F_FW_CMD_READ | 9897 ldst_addrspace); 9898 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9899 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9900 ldst.u.i2c.did = devid; 9901 ldst.u.i2c.boffset = offset; 9902 ldst.u.i2c.blen = len; 9903 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9904 if (!ret) 9905 memcpy(buf, ldst.u.i2c.data, len); 9906 return ret; 9907 } 9908 9909 /** 9910 * t4_i2c_wr - write I2C data to adapter 9911 * @adap: the adapter 9912 * @port: Port number if per-port device; <0 if not 9913 * @devid: per-port device ID or absolute device ID 9914 * @offset: byte offset into device I2C space 9915 * @len: byte length of I2C space data 9916 * @buf: buffer containing new I2C data 9917 * 9918 * Write the I2C data to the indicated device and location. 9919 */ 9920 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 9921 int port, unsigned int devid, 9922 unsigned int offset, unsigned int len, 9923 u8 *buf) 9924 { 9925 u32 ldst_addrspace; 9926 struct fw_ldst_cmd ldst; 9927 9928 if (port >= 4 || 9929 devid >= 256 || 9930 offset >= 256 || 9931 len > sizeof ldst.u.i2c.data) 9932 return -EINVAL; 9933 9934 memset(&ldst, 0, sizeof ldst); 9935 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9936 ldst.op_to_addrspace = 9937 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9938 F_FW_CMD_REQUEST | 9939 F_FW_CMD_WRITE | 9940 ldst_addrspace); 9941 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9942 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9943 ldst.u.i2c.did = devid; 9944 ldst.u.i2c.boffset = offset; 9945 ldst.u.i2c.blen = len; 9946 memcpy(ldst.u.i2c.data, buf, len); 9947 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9948 } 9949 9950 /** 9951 * t4_sge_ctxt_rd - read an SGE context through FW 9952 * @adap: the adapter 9953 * @mbox: mailbox to use for the FW command 9954 * @cid: the context id 9955 * @ctype: the context type 9956 * @data: where to store the context data 9957 * 9958 * Issues a FW command through the given mailbox to read an SGE context. 9959 */ 9960 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 9961 enum ctxt_type ctype, u32 *data) 9962 { 9963 int ret; 9964 struct fw_ldst_cmd c; 9965 9966 if (ctype == CTXT_EGRESS) 9967 ret = FW_LDST_ADDRSPC_SGE_EGRC; 9968 else if (ctype == CTXT_INGRESS) 9969 ret = FW_LDST_ADDRSPC_SGE_INGC; 9970 else if (ctype == CTXT_FLM) 9971 ret = FW_LDST_ADDRSPC_SGE_FLMC; 9972 else 9973 ret = FW_LDST_ADDRSPC_SGE_CONMC; 9974 9975 memset(&c, 0, sizeof(c)); 9976 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9977 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9978 V_FW_LDST_CMD_ADDRSPACE(ret)); 9979 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 9980 c.u.idctxt.physid = cpu_to_be32(cid); 9981 9982 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 9983 if (ret == 0) { 9984 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 9985 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 9986 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 9987 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 9988 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 9989 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 9990 } 9991 return ret; 9992 } 9993 9994 /** 9995 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 9996 * @adap: the adapter 9997 * @cid: the context id 9998 * @ctype: the context type 9999 * @data: where to store the context data 10000 * 10001 * Reads an SGE context directly, bypassing FW. This is only for 10002 * debugging when FW is unavailable. 10003 */ 10004 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 10005 u32 *data) 10006 { 10007 int i, ret; 10008 10009 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 10010 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 10011 if (!ret) 10012 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 10013 *data++ = t4_read_reg(adap, i); 10014 return ret; 10015 } 10016 10017 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 10018 int sleep_ok) 10019 { 10020 struct fw_sched_cmd cmd; 10021 10022 memset(&cmd, 0, sizeof(cmd)); 10023 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10024 F_FW_CMD_REQUEST | 10025 F_FW_CMD_WRITE); 10026 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10027 10028 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 10029 cmd.u.config.type = type; 10030 cmd.u.config.minmaxen = minmaxen; 10031 10032 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10033 NULL, sleep_ok); 10034 } 10035 10036 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 10037 int rateunit, int ratemode, int channel, int cl, 10038 int minrate, int maxrate, int weight, int pktsize, 10039 int burstsize, int sleep_ok) 10040 { 10041 struct fw_sched_cmd cmd; 10042 10043 memset(&cmd, 0, sizeof(cmd)); 10044 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10045 F_FW_CMD_REQUEST | 10046 F_FW_CMD_WRITE); 10047 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10048 10049 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10050 cmd.u.params.type = type; 10051 cmd.u.params.level = level; 10052 cmd.u.params.mode = mode; 10053 cmd.u.params.ch = channel; 10054 cmd.u.params.cl = cl; 10055 cmd.u.params.unit = rateunit; 10056 cmd.u.params.rate = ratemode; 10057 cmd.u.params.min = cpu_to_be32(minrate); 10058 cmd.u.params.max = cpu_to_be32(maxrate); 10059 cmd.u.params.weight = cpu_to_be16(weight); 10060 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10061 cmd.u.params.burstsize = cpu_to_be16(burstsize); 10062 10063 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10064 NULL, sleep_ok); 10065 } 10066 10067 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 10068 unsigned int maxrate, int sleep_ok) 10069 { 10070 struct fw_sched_cmd cmd; 10071 10072 memset(&cmd, 0, sizeof(cmd)); 10073 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10074 F_FW_CMD_REQUEST | 10075 F_FW_CMD_WRITE); 10076 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10077 10078 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10079 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10080 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 10081 cmd.u.params.ch = channel; 10082 cmd.u.params.rate = ratemode; /* REL or ABS */ 10083 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 10084 10085 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10086 NULL, sleep_ok); 10087 } 10088 10089 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 10090 int weight, int sleep_ok) 10091 { 10092 struct fw_sched_cmd cmd; 10093 10094 if (weight < 0 || weight > 100) 10095 return -EINVAL; 10096 10097 memset(&cmd, 0, sizeof(cmd)); 10098 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10099 F_FW_CMD_REQUEST | 10100 F_FW_CMD_WRITE); 10101 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10102 10103 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10104 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10105 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 10106 cmd.u.params.ch = channel; 10107 cmd.u.params.cl = cl; 10108 cmd.u.params.weight = cpu_to_be16(weight); 10109 10110 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10111 NULL, sleep_ok); 10112 } 10113 10114 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 10115 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 10116 { 10117 struct fw_sched_cmd cmd; 10118 10119 memset(&cmd, 0, sizeof(cmd)); 10120 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10121 F_FW_CMD_REQUEST | 10122 F_FW_CMD_WRITE); 10123 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10124 10125 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10126 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10127 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 10128 cmd.u.params.mode = mode; 10129 cmd.u.params.ch = channel; 10130 cmd.u.params.cl = cl; 10131 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 10132 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 10133 cmd.u.params.max = cpu_to_be32(maxrate); 10134 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10135 10136 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10137 NULL, sleep_ok); 10138 } 10139 10140 /* 10141 * t4_config_watchdog - configure (enable/disable) a watchdog timer 10142 * @adapter: the adapter 10143 * @mbox: mailbox to use for the FW command 10144 * @pf: the PF owning the queue 10145 * @vf: the VF owning the queue 10146 * @timeout: watchdog timeout in ms 10147 * @action: watchdog timer / action 10148 * 10149 * There are separate watchdog timers for each possible watchdog 10150 * action. Configure one of the watchdog timers by setting a non-zero 10151 * timeout. Disable a watchdog timer by using a timeout of zero. 10152 */ 10153 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 10154 unsigned int pf, unsigned int vf, 10155 unsigned int timeout, unsigned int action) 10156 { 10157 struct fw_watchdog_cmd wdog; 10158 unsigned int ticks; 10159 10160 /* 10161 * The watchdog command expects a timeout in units of 10ms so we need 10162 * to convert it here (via rounding) and force a minimum of one 10ms 10163 * "tick" if the timeout is non-zero but the conversion results in 0 10164 * ticks. 10165 */ 10166 ticks = (timeout + 5)/10; 10167 if (timeout && !ticks) 10168 ticks = 1; 10169 10170 memset(&wdog, 0, sizeof wdog); 10171 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 10172 F_FW_CMD_REQUEST | 10173 F_FW_CMD_WRITE | 10174 V_FW_PARAMS_CMD_PFN(pf) | 10175 V_FW_PARAMS_CMD_VFN(vf)); 10176 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 10177 wdog.timeout = cpu_to_be32(ticks); 10178 wdog.action = cpu_to_be32(action); 10179 10180 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 10181 } 10182 10183 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 10184 { 10185 struct fw_devlog_cmd devlog_cmd; 10186 int ret; 10187 10188 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10189 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10190 F_FW_CMD_REQUEST | F_FW_CMD_READ); 10191 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10192 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10193 sizeof(devlog_cmd), &devlog_cmd); 10194 if (ret) 10195 return ret; 10196 10197 *level = devlog_cmd.level; 10198 return 0; 10199 } 10200 10201 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 10202 { 10203 struct fw_devlog_cmd devlog_cmd; 10204 10205 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10206 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10207 F_FW_CMD_REQUEST | 10208 F_FW_CMD_WRITE); 10209 devlog_cmd.level = level; 10210 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10211 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10212 sizeof(devlog_cmd), &devlog_cmd); 10213 } 10214