xref: /freebsd/sys/dev/cxgbe/common/t4_hw.c (revision c57c26179033f64c2011a2d2a904ee3fa62e826a)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #include <sys/cdefs.h>
30 #include "opt_inet.h"
31 
32 #include <sys/param.h>
33 #include <sys/eventhandler.h>
34 
35 #include "common.h"
36 #include "t4_regs.h"
37 #include "t4_regs_values.h"
38 #include "firmware/t4fw_interface.h"
39 
40 #undef msleep
41 #define msleep(x) do { \
42 	if (cold) \
43 		DELAY((x) * 1000); \
44 	else \
45 		pause("t4hw", (x) * hz / 1000); \
46 } while (0)
47 
48 /**
49  *	t4_wait_op_done_val - wait until an operation is completed
50  *	@adapter: the adapter performing the operation
51  *	@reg: the register to check for completion
52  *	@mask: a single-bit field within @reg that indicates completion
53  *	@polarity: the value of the field when the operation is completed
54  *	@attempts: number of check iterations
55  *	@delay: delay in usecs between iterations
56  *	@valp: where to store the value of the register at completion time
57  *
58  *	Wait until an operation is completed by checking a bit in a register
59  *	up to @attempts times.  If @valp is not NULL the value of the register
60  *	at the time it indicated completion is stored there.  Returns 0 if the
61  *	operation completes and	-EAGAIN	otherwise.
62  */
63 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
64 			       int polarity, int attempts, int delay, u32 *valp)
65 {
66 	while (1) {
67 		u32 val = t4_read_reg(adapter, reg);
68 
69 		if (!!(val & mask) == polarity) {
70 			if (valp)
71 				*valp = val;
72 			return 0;
73 		}
74 		if (--attempts == 0)
75 			return -EAGAIN;
76 		if (delay)
77 			udelay(delay);
78 	}
79 }
80 
81 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
82 				  int polarity, int attempts, int delay)
83 {
84 	return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
85 				   delay, NULL);
86 }
87 
88 /**
89  *	t4_set_reg_field - set a register field to a value
90  *	@adapter: the adapter to program
91  *	@addr: the register address
92  *	@mask: specifies the portion of the register to modify
93  *	@val: the new value for the register field
94  *
95  *	Sets a register field specified by the supplied mask to the
96  *	given value.
97  */
98 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
99 		      u32 val)
100 {
101 	u32 v = t4_read_reg(adapter, addr) & ~mask;
102 
103 	t4_write_reg(adapter, addr, v | val);
104 	(void) t4_read_reg(adapter, addr);      /* flush */
105 }
106 
107 /**
108  *	t4_read_indirect - read indirectly addressed registers
109  *	@adap: the adapter
110  *	@addr_reg: register holding the indirect address
111  *	@data_reg: register holding the value of the indirect register
112  *	@vals: where the read register values are stored
113  *	@nregs: how many indirect registers to read
114  *	@start_idx: index of first indirect register to read
115  *
116  *	Reads registers that are accessed indirectly through an address/data
117  *	register pair.
118  */
119 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
120 			     unsigned int data_reg, u32 *vals,
121 			     unsigned int nregs, unsigned int start_idx)
122 {
123 	while (nregs--) {
124 		t4_write_reg(adap, addr_reg, start_idx);
125 		*vals++ = t4_read_reg(adap, data_reg);
126 		start_idx++;
127 	}
128 }
129 
130 /**
131  *	t4_write_indirect - write indirectly addressed registers
132  *	@adap: the adapter
133  *	@addr_reg: register holding the indirect addresses
134  *	@data_reg: register holding the value for the indirect registers
135  *	@vals: values to write
136  *	@nregs: how many indirect registers to write
137  *	@start_idx: address of first indirect register to write
138  *
139  *	Writes a sequential block of registers that are accessed indirectly
140  *	through an address/data register pair.
141  */
142 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
143 		       unsigned int data_reg, const u32 *vals,
144 		       unsigned int nregs, unsigned int start_idx)
145 {
146 	while (nregs--) {
147 		t4_write_reg(adap, addr_reg, start_idx++);
148 		t4_write_reg(adap, data_reg, *vals++);
149 	}
150 }
151 
152 /*
153  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
154  * mechanism.  This guarantees that we get the real value even if we're
155  * operating within a Virtual Machine and the Hypervisor is trapping our
156  * Configuration Space accesses.
157  *
158  * N.B. This routine should only be used as a last resort: the firmware uses
159  *      the backdoor registers on a regular basis and we can end up
160  *      conflicting with it's uses!
161  */
162 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
163 {
164 	u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
165 	u32 val;
166 
167 	if (chip_id(adap) <= CHELSIO_T5)
168 		req |= F_ENABLE;
169 	else
170 		req |= F_T6_ENABLE;
171 
172 	if (is_t4(adap))
173 		req |= F_LOCALCFG;
174 
175 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
176 	val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
177 
178 	/*
179 	 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
180 	 * Configuration Space read.  (None of the other fields matter when
181 	 * F_ENABLE is 0 so a simple register write is easier than a
182 	 * read-modify-write via t4_set_reg_field().)
183 	 */
184 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
185 
186 	return val;
187 }
188 
189 /*
190  * t4_report_fw_error - report firmware error
191  * @adap: the adapter
192  *
193  * The adapter firmware can indicate error conditions to the host.
194  * If the firmware has indicated an error, print out the reason for
195  * the firmware error.
196  */
197 void t4_report_fw_error(struct adapter *adap)
198 {
199 	static const char *const reason[] = {
200 		"Crash",			/* PCIE_FW_EVAL_CRASH */
201 		"During Device Preparation",	/* PCIE_FW_EVAL_PREP */
202 		"During Device Configuration",	/* PCIE_FW_EVAL_CONF */
203 		"During Device Initialization",	/* PCIE_FW_EVAL_INIT */
204 		"Unexpected Event",		/* PCIE_FW_EVAL_UNEXPECTEDEVENT */
205 		"Insufficient Airflow",		/* PCIE_FW_EVAL_OVERHEAT */
206 		"Device Shutdown",		/* PCIE_FW_EVAL_DEVICESHUTDOWN */
207 		"Reserved",			/* reserved */
208 	};
209 	u32 pcie_fw;
210 
211 	pcie_fw = t4_read_reg(adap, A_PCIE_FW);
212 	if (pcie_fw & F_PCIE_FW_ERR) {
213 		CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n",
214 		    reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw);
215 	}
216 }
217 
218 /*
219  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
220  */
221 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
222 			 u32 mbox_addr)
223 {
224 	for ( ; nflit; nflit--, mbox_addr += 8)
225 		*rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
226 }
227 
228 /*
229  * Handle a FW assertion reported in a mailbox.
230  */
231 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
232 {
233 	CH_ALERT(adap,
234 		  "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
235 		  asrt->u.assert.filename_0_7,
236 		  be32_to_cpu(asrt->u.assert.line),
237 		  be32_to_cpu(asrt->u.assert.x),
238 		  be32_to_cpu(asrt->u.assert.y));
239 }
240 
241 struct port_tx_state {
242 	uint64_t rx_pause;
243 	uint64_t tx_frames;
244 };
245 
246 u32
247 t4_port_reg(struct adapter *adap, u8 port, u32 reg)
248 {
249 	if (chip_id(adap) > CHELSIO_T4)
250 		return T5_PORT_REG(port, reg);
251 	return PORT_REG(port, reg);
252 }
253 
254 static void
255 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state)
256 {
257 	uint32_t rx_pause_reg, tx_frames_reg;
258 
259 	rx_pause_reg = t4_port_reg(sc, i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L);
260 	tx_frames_reg = t4_port_reg(sc, i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L);
261 
262 	tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg);
263 	tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg);
264 }
265 
266 static void
267 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
268 {
269 	int i;
270 
271 	for_each_port(sc, i)
272 		read_tx_state_one(sc, i, &tx_state[i]);
273 }
274 
275 static void
276 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state)
277 {
278 	uint32_t port_ctl_reg;
279 	uint64_t tx_frames, rx_pause;
280 	int i;
281 
282 	for_each_port(sc, i) {
283 		rx_pause = tx_state[i].rx_pause;
284 		tx_frames = tx_state[i].tx_frames;
285 		read_tx_state_one(sc, i, &tx_state[i]);	/* update */
286 
287 		port_ctl_reg = t4_port_reg(sc, i, A_MPS_PORT_CTL);
288 		if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN &&
289 		    rx_pause != tx_state[i].rx_pause &&
290 		    tx_frames == tx_state[i].tx_frames) {
291 			t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0);
292 			mdelay(1);
293 			t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN);
294 		}
295 	}
296 }
297 
298 #define X_CIM_PF_NOACCESS 0xeeeeeeee
299 /**
300  *	t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
301  *	@adap: the adapter
302  *	@mbox: index of the mailbox to use
303  *	@cmd: the command to write
304  *	@size: command length in bytes
305  *	@rpl: where to optionally store the reply
306  *	@sleep_ok: if true we may sleep while awaiting command completion
307  *	@timeout: time to wait for command to finish before timing out
308  *		(negative implies @sleep_ok=false)
309  *
310  *	Sends the given command to FW through the selected mailbox and waits
311  *	for the FW to execute the command.  If @rpl is not %NULL it is used to
312  *	store the FW's reply to the command.  The command and its optional
313  *	reply are of the same length.  Some FW commands like RESET and
314  *	INITIALIZE can take a considerable amount of time to execute.
315  *	@sleep_ok determines whether we may sleep while awaiting the response.
316  *	If sleeping is allowed we use progressive backoff otherwise we spin.
317  *	Note that passing in a negative @timeout is an alternate mechanism
318  *	for specifying @sleep_ok=false.  This is useful when a higher level
319  *	interface allows for specification of @timeout but not @sleep_ok ...
320  *
321  *	The return value is 0 on success or a negative errno on failure.  A
322  *	failure can happen either because we are not able to execute the
323  *	command or FW executes it but signals an error.  In the latter case
324  *	the return value is the error code indicated by FW (negated).
325  */
326 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
327 			    int size, void *rpl, bool sleep_ok, int timeout)
328 {
329 	/*
330 	 * We delay in small increments at first in an effort to maintain
331 	 * responsiveness for simple, fast executing commands but then back
332 	 * off to larger delays to a maximum retry delay.
333 	 */
334 	static const int delay[] = {
335 		1, 1, 3, 5, 10, 10, 20, 50, 100
336 	};
337 	u32 v;
338 	u64 res;
339 	int i, ms, delay_idx, ret, next_tx_check;
340 	u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
341 	u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
342 	u32 ctl;
343 	__be64 cmd_rpl[MBOX_LEN/8];
344 	u32 pcie_fw;
345 	struct port_tx_state tx_state[MAX_NPORTS];
346 
347 	if (adap->flags & CHK_MBOX_ACCESS)
348 		ASSERT_SYNCHRONIZED_OP(adap);
349 
350 	if (size <= 0 || (size & 15) || size > MBOX_LEN)
351 		return -EINVAL;
352 
353 	if (adap->flags & IS_VF) {
354 		if (is_t6(adap))
355 			data_reg = FW_T6VF_MBDATA_BASE_ADDR;
356 		else
357 			data_reg = FW_T4VF_MBDATA_BASE_ADDR;
358 		ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
359 	}
360 
361 	/*
362 	 * If we have a negative timeout, that implies that we can't sleep.
363 	 */
364 	if (timeout < 0) {
365 		sleep_ok = false;
366 		timeout = -timeout;
367 	}
368 
369 	/*
370 	 * Attempt to gain access to the mailbox.
371 	 */
372 	pcie_fw = 0;
373 	if (!(adap->flags & IS_VF)) {
374 		pcie_fw = t4_read_reg(adap, A_PCIE_FW);
375 		if (pcie_fw & F_PCIE_FW_ERR)
376 			goto failed;
377 	}
378 	for (i = 0; i < 4; i++) {
379 		ctl = t4_read_reg(adap, ctl_reg);
380 		v = G_MBOWNER(ctl);
381 		if (v != X_MBOWNER_NONE)
382 			break;
383 	}
384 
385 	/*
386 	 * If we were unable to gain access, report the error to our caller.
387 	 */
388 	if (v != X_MBOWNER_PL) {
389 		if (!(adap->flags & IS_VF)) {
390 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
391 			if (pcie_fw & F_PCIE_FW_ERR)
392 				goto failed;
393 		}
394 		ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
395 		return ret;
396 	}
397 
398 	/*
399 	 * If we gain ownership of the mailbox and there's a "valid" message
400 	 * in it, this is likely an asynchronous error message from the
401 	 * firmware.  So we'll report that and then proceed on with attempting
402 	 * to issue our own command ... which may well fail if the error
403 	 * presaged the firmware crashing ...
404 	 */
405 	if (ctl & F_MBMSGVALID) {
406 		CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true);
407 	}
408 
409 	/*
410 	 * Copy in the new mailbox command and send it on its way ...
411 	 */
412 	memset(cmd_rpl, 0, sizeof(cmd_rpl));
413 	memcpy(cmd_rpl, cmd, size);
414 	CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false);
415 	for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++)
416 		t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i]));
417 
418 	if (adap->flags & IS_VF) {
419 		/*
420 		 * For the VFs, the Mailbox Data "registers" are
421 		 * actually backed by T4's "MA" interface rather than
422 		 * PL Registers (as is the case for the PFs).  Because
423 		 * these are in different coherency domains, the write
424 		 * to the VF's PL-register-backed Mailbox Control can
425 		 * race in front of the writes to the MA-backed VF
426 		 * Mailbox Data "registers".  So we need to do a
427 		 * read-back on at least one byte of the VF Mailbox
428 		 * Data registers before doing the write to the VF
429 		 * Mailbox Control register.
430 		 */
431 		t4_read_reg(adap, data_reg);
432 	}
433 
434 	t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
435 	read_tx_state(adap, &tx_state[0]);	/* also flushes the write_reg */
436 	next_tx_check = 1000;
437 	delay_idx = 0;
438 	ms = delay[0];
439 
440 	/*
441 	 * Loop waiting for the reply; bail out if we time out or the firmware
442 	 * reports an error.
443 	 */
444 	for (i = 0; i < timeout; i += ms) {
445 		if (!(adap->flags & IS_VF)) {
446 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
447 			if (pcie_fw & F_PCIE_FW_ERR)
448 				break;
449 		}
450 
451 		if (i >= next_tx_check) {
452 			check_tx_state(adap, &tx_state[0]);
453 			next_tx_check = i + 1000;
454 		}
455 
456 		if (sleep_ok) {
457 			ms = delay[delay_idx];  /* last element may repeat */
458 			if (delay_idx < ARRAY_SIZE(delay) - 1)
459 				delay_idx++;
460 			msleep(ms);
461 		} else {
462 			mdelay(ms);
463 		}
464 
465 		v = t4_read_reg(adap, ctl_reg);
466 		if (v == X_CIM_PF_NOACCESS)
467 			continue;
468 		if (G_MBOWNER(v) == X_MBOWNER_PL) {
469 			if (!(v & F_MBMSGVALID)) {
470 				t4_write_reg(adap, ctl_reg,
471 					     V_MBOWNER(X_MBOWNER_NONE));
472 				continue;
473 			}
474 
475 			/*
476 			 * Retrieve the command reply and release the mailbox.
477 			 */
478 			get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
479 			CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false);
480 			t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
481 
482 			res = be64_to_cpu(cmd_rpl[0]);
483 			if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
484 				fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
485 				res = V_FW_CMD_RETVAL(EIO);
486 			} else if (rpl)
487 				memcpy(rpl, cmd_rpl, size);
488 			return -G_FW_CMD_RETVAL((int)res);
489 		}
490 	}
491 
492 	/*
493 	 * We timed out waiting for a reply to our mailbox command.  Report
494 	 * the error and also check to see if the firmware reported any
495 	 * errors ...
496 	 */
497 	CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n",
498 	    *(const u8 *)cmd, mbox, pcie_fw);
499 	CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true);
500 	CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true);
501 failed:
502 	adap->flags &= ~FW_OK;
503 	ret = pcie_fw & F_PCIE_FW_ERR ? -ENXIO : -ETIMEDOUT;
504 	t4_fatal_err(adap, true);
505 	return ret;
506 }
507 
508 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
509 		    void *rpl, bool sleep_ok)
510 {
511 		return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
512 					       sleep_ok, FW_CMD_MAX_TIMEOUT);
513 
514 }
515 
516 static int t4_edc_err_read(struct adapter *adap, int idx)
517 {
518 	u32 edc_ecc_err_addr_reg;
519 	u32 edc_bist_status_rdata_reg;
520 
521 	if (is_t4(adap)) {
522 		CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
523 		return 0;
524 	}
525 	if (idx != MEM_EDC0 && idx != MEM_EDC1) {
526 		CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
527 		return 0;
528 	}
529 
530 	edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
531 	edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
532 
533 	CH_WARN(adap,
534 		"edc%d err addr 0x%x: 0x%x.\n",
535 		idx, edc_ecc_err_addr_reg,
536 		t4_read_reg(adap, edc_ecc_err_addr_reg));
537 	CH_WARN(adap,
538 	 	"bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
539 		edc_bist_status_rdata_reg,
540 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
541 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
542 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
543 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
544 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
545 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
546 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
547 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
548 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
549 
550 	return 0;
551 }
552 
553 /**
554  *	t4_mc_read - read from MC through backdoor accesses
555  *	@adap: the adapter
556  *	@idx: which MC to access
557  *	@addr: address of first byte requested
558  *	@data: 64 bytes of data containing the requested address
559  *	@ecc: where to store the corresponding 64-bit ECC word
560  *
561  *	Read 64 bytes of data from MC starting at a 64-byte-aligned address
562  *	that covers the requested address @addr.  If @parity is not %NULL it
563  *	is assigned the 64-bit ECC word for the read data.
564  */
565 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
566 {
567 	int i;
568 	u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
569 	u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
570 
571 	if (is_t4(adap)) {
572 		mc_bist_cmd_reg = A_MC_BIST_CMD;
573 		mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
574 		mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
575 		mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
576 		mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
577 	} else {
578 		mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
579 		mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
580 		mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
581 		mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
582 						  idx);
583 		mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
584 						  idx);
585 	}
586 
587 	if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
588 		return -EBUSY;
589 	t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
590 	t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
591 	t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
592 	t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
593 		     F_START_BIST | V_BIST_CMD_GAP(1));
594 	i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
595 	if (i)
596 		return i;
597 
598 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
599 
600 	for (i = 15; i >= 0; i--)
601 		*data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
602 	if (ecc)
603 		*ecc = t4_read_reg64(adap, MC_DATA(16));
604 #undef MC_DATA
605 	return 0;
606 }
607 
608 /**
609  *	t4_edc_read - read from EDC through backdoor accesses
610  *	@adap: the adapter
611  *	@idx: which EDC to access
612  *	@addr: address of first byte requested
613  *	@data: 64 bytes of data containing the requested address
614  *	@ecc: where to store the corresponding 64-bit ECC word
615  *
616  *	Read 64 bytes of data from EDC starting at a 64-byte-aligned address
617  *	that covers the requested address @addr.  If @parity is not %NULL it
618  *	is assigned the 64-bit ECC word for the read data.
619  */
620 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
621 {
622 	int i;
623 	u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
624 	u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
625 
626 	if (is_t4(adap)) {
627 		edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
628 		edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
629 		edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
630 		edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
631 						    idx);
632 		edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
633 						    idx);
634 	} else {
635 /*
636  * These macro are missing in t4_regs.h file.
637  * Added temporarily for testing.
638  */
639 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
640 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
641 		edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
642 		edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
643 		edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
644 		edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
645 						    idx);
646 		edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
647 						    idx);
648 #undef EDC_REG_T5
649 #undef EDC_STRIDE_T5
650 	}
651 
652 	if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
653 		return -EBUSY;
654 	t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
655 	t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
656 	t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
657 	t4_write_reg(adap, edc_bist_cmd_reg,
658 		     V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
659 	i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
660 	if (i)
661 		return i;
662 
663 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
664 
665 	for (i = 15; i >= 0; i--)
666 		*data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
667 	if (ecc)
668 		*ecc = t4_read_reg64(adap, EDC_DATA(16));
669 #undef EDC_DATA
670 	return 0;
671 }
672 
673 /**
674  *	t4_mem_read - read EDC 0, EDC 1 or MC into buffer
675  *	@adap: the adapter
676  *	@mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
677  *	@addr: address within indicated memory type
678  *	@len: amount of memory to read
679  *	@buf: host memory buffer
680  *
681  *	Reads an [almost] arbitrary memory region in the firmware: the
682  *	firmware memory address, length and host buffer must be aligned on
683  *	32-bit boudaries.  The memory is returned as a raw byte sequence from
684  *	the firmware's memory.  If this memory contains data structures which
685  *	contain multi-byte integers, it's the callers responsibility to
686  *	perform appropriate byte order conversions.
687  */
688 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
689 		__be32 *buf)
690 {
691 	u32 pos, start, end, offset;
692 	int ret;
693 
694 	/*
695 	 * Argument sanity checks ...
696 	 */
697 	if ((addr & 0x3) || (len & 0x3))
698 		return -EINVAL;
699 
700 	/*
701 	 * The underlaying EDC/MC read routines read 64 bytes at a time so we
702 	 * need to round down the start and round up the end.  We'll start
703 	 * copying out of the first line at (addr - start) a word at a time.
704 	 */
705 	start = rounddown2(addr, 64);
706 	end = roundup2(addr + len, 64);
707 	offset = (addr - start)/sizeof(__be32);
708 
709 	for (pos = start; pos < end; pos += 64, offset = 0) {
710 		__be32 data[16];
711 
712 		/*
713 		 * Read the chip's memory block and bail if there's an error.
714 		 */
715 		if ((mtype == MEM_MC) || (mtype == MEM_MC1))
716 			ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
717 		else
718 			ret = t4_edc_read(adap, mtype, pos, data, NULL);
719 		if (ret)
720 			return ret;
721 
722 		/*
723 		 * Copy the data into the caller's memory buffer.
724 		 */
725 		while (offset < 16 && len > 0) {
726 			*buf++ = data[offset++];
727 			len -= sizeof(__be32);
728 		}
729 	}
730 
731 	return 0;
732 }
733 
734 /*
735  * Return the specified PCI-E Configuration Space register from our Physical
736  * Function.  We try first via a Firmware LDST Command (if fw_attach != 0)
737  * since we prefer to let the firmware own all of these registers, but if that
738  * fails we go for it directly ourselves.
739  */
740 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
741 {
742 
743 	/*
744 	 * If fw_attach != 0, construct and send the Firmware LDST Command to
745 	 * retrieve the specified PCI-E Configuration Space register.
746 	 */
747 	if (drv_fw_attach != 0) {
748 		struct fw_ldst_cmd ldst_cmd;
749 		int ret;
750 
751 		memset(&ldst_cmd, 0, sizeof(ldst_cmd));
752 		ldst_cmd.op_to_addrspace =
753 			cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
754 				    F_FW_CMD_REQUEST |
755 				    F_FW_CMD_READ |
756 				    V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
757 		ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
758 		ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
759 		ldst_cmd.u.pcie.ctrl_to_fn =
760 			(F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
761 		ldst_cmd.u.pcie.r = reg;
762 
763 		/*
764 		 * If the LDST Command succeeds, return the result, otherwise
765 		 * fall through to reading it directly ourselves ...
766 		 */
767 		ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
768 				 &ldst_cmd);
769 		if (ret == 0)
770 			return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
771 
772 		CH_WARN(adap, "Firmware failed to return "
773 			"Configuration Space register %d, err = %d\n",
774 			reg, -ret);
775 	}
776 
777 	/*
778 	 * Read the desired Configuration Space register via the PCI-E
779 	 * Backdoor mechanism.
780 	 */
781 	return t4_hw_pci_read_cfg4(adap, reg);
782 }
783 
784 /**
785  *	t4_get_regs_len - return the size of the chips register set
786  *	@adapter: the adapter
787  *
788  *	Returns the size of the chip's BAR0 register space.
789  */
790 unsigned int t4_get_regs_len(struct adapter *adapter)
791 {
792 	unsigned int chip_version = chip_id(adapter);
793 
794 	switch (chip_version) {
795 	case CHELSIO_T4:
796 		if (adapter->flags & IS_VF)
797 			return FW_T4VF_REGMAP_SIZE;
798 		return T4_REGMAP_SIZE;
799 
800 	case CHELSIO_T5:
801 	case CHELSIO_T6:
802 		if (adapter->flags & IS_VF)
803 			return FW_T4VF_REGMAP_SIZE;
804 		return T5_REGMAP_SIZE;
805 	}
806 
807 	CH_ERR(adapter,
808 		"Unsupported chip version %d\n", chip_version);
809 	return 0;
810 }
811 
812 /**
813  *	t4_get_regs - read chip registers into provided buffer
814  *	@adap: the adapter
815  *	@buf: register buffer
816  *	@buf_size: size (in bytes) of register buffer
817  *
818  *	If the provided register buffer isn't large enough for the chip's
819  *	full register range, the register dump will be truncated to the
820  *	register buffer's size.
821  */
822 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
823 {
824 	static const unsigned int t4_reg_ranges[] = {
825 		0x1008, 0x1108,
826 		0x1180, 0x1184,
827 		0x1190, 0x1194,
828 		0x11a0, 0x11a4,
829 		0x11b0, 0x11b4,
830 		0x11fc, 0x123c,
831 		0x1300, 0x173c,
832 		0x1800, 0x18fc,
833 		0x3000, 0x30d8,
834 		0x30e0, 0x30e4,
835 		0x30ec, 0x5910,
836 		0x5920, 0x5924,
837 		0x5960, 0x5960,
838 		0x5968, 0x5968,
839 		0x5970, 0x5970,
840 		0x5978, 0x5978,
841 		0x5980, 0x5980,
842 		0x5988, 0x5988,
843 		0x5990, 0x5990,
844 		0x5998, 0x5998,
845 		0x59a0, 0x59d4,
846 		0x5a00, 0x5ae0,
847 		0x5ae8, 0x5ae8,
848 		0x5af0, 0x5af0,
849 		0x5af8, 0x5af8,
850 		0x6000, 0x6098,
851 		0x6100, 0x6150,
852 		0x6200, 0x6208,
853 		0x6240, 0x6248,
854 		0x6280, 0x62b0,
855 		0x62c0, 0x6338,
856 		0x6370, 0x638c,
857 		0x6400, 0x643c,
858 		0x6500, 0x6524,
859 		0x6a00, 0x6a04,
860 		0x6a14, 0x6a38,
861 		0x6a60, 0x6a70,
862 		0x6a78, 0x6a78,
863 		0x6b00, 0x6b0c,
864 		0x6b1c, 0x6b84,
865 		0x6bf0, 0x6bf8,
866 		0x6c00, 0x6c0c,
867 		0x6c1c, 0x6c84,
868 		0x6cf0, 0x6cf8,
869 		0x6d00, 0x6d0c,
870 		0x6d1c, 0x6d84,
871 		0x6df0, 0x6df8,
872 		0x6e00, 0x6e0c,
873 		0x6e1c, 0x6e84,
874 		0x6ef0, 0x6ef8,
875 		0x6f00, 0x6f0c,
876 		0x6f1c, 0x6f84,
877 		0x6ff0, 0x6ff8,
878 		0x7000, 0x700c,
879 		0x701c, 0x7084,
880 		0x70f0, 0x70f8,
881 		0x7100, 0x710c,
882 		0x711c, 0x7184,
883 		0x71f0, 0x71f8,
884 		0x7200, 0x720c,
885 		0x721c, 0x7284,
886 		0x72f0, 0x72f8,
887 		0x7300, 0x730c,
888 		0x731c, 0x7384,
889 		0x73f0, 0x73f8,
890 		0x7400, 0x7450,
891 		0x7500, 0x7530,
892 		0x7600, 0x760c,
893 		0x7614, 0x761c,
894 		0x7680, 0x76cc,
895 		0x7700, 0x7798,
896 		0x77c0, 0x77fc,
897 		0x7900, 0x79fc,
898 		0x7b00, 0x7b58,
899 		0x7b60, 0x7b84,
900 		0x7b8c, 0x7c38,
901 		0x7d00, 0x7d38,
902 		0x7d40, 0x7d80,
903 		0x7d8c, 0x7ddc,
904 		0x7de4, 0x7e04,
905 		0x7e10, 0x7e1c,
906 		0x7e24, 0x7e38,
907 		0x7e40, 0x7e44,
908 		0x7e4c, 0x7e78,
909 		0x7e80, 0x7ea4,
910 		0x7eac, 0x7edc,
911 		0x7ee8, 0x7efc,
912 		0x8dc0, 0x8e04,
913 		0x8e10, 0x8e1c,
914 		0x8e30, 0x8e78,
915 		0x8ea0, 0x8eb8,
916 		0x8ec0, 0x8f6c,
917 		0x8fc0, 0x9008,
918 		0x9010, 0x9058,
919 		0x9060, 0x9060,
920 		0x9068, 0x9074,
921 		0x90fc, 0x90fc,
922 		0x9400, 0x9408,
923 		0x9410, 0x9458,
924 		0x9600, 0x9600,
925 		0x9608, 0x9638,
926 		0x9640, 0x96bc,
927 		0x9800, 0x9808,
928 		0x9820, 0x983c,
929 		0x9850, 0x9864,
930 		0x9c00, 0x9c6c,
931 		0x9c80, 0x9cec,
932 		0x9d00, 0x9d6c,
933 		0x9d80, 0x9dec,
934 		0x9e00, 0x9e6c,
935 		0x9e80, 0x9eec,
936 		0x9f00, 0x9f6c,
937 		0x9f80, 0x9fec,
938 		0xd004, 0xd004,
939 		0xd010, 0xd03c,
940 		0xdfc0, 0xdfe0,
941 		0xe000, 0xea7c,
942 		0xf000, 0x11110,
943 		0x11118, 0x11190,
944 		0x19040, 0x1906c,
945 		0x19078, 0x19080,
946 		0x1908c, 0x190e4,
947 		0x190f0, 0x190f8,
948 		0x19100, 0x19110,
949 		0x19120, 0x19124,
950 		0x19150, 0x19194,
951 		0x1919c, 0x191b0,
952 		0x191d0, 0x191e8,
953 		0x19238, 0x1924c,
954 		0x193f8, 0x1943c,
955 		0x1944c, 0x19474,
956 		0x19490, 0x194e0,
957 		0x194f0, 0x194f8,
958 		0x19800, 0x19c08,
959 		0x19c10, 0x19c90,
960 		0x19ca0, 0x19ce4,
961 		0x19cf0, 0x19d40,
962 		0x19d50, 0x19d94,
963 		0x19da0, 0x19de8,
964 		0x19df0, 0x19e40,
965 		0x19e50, 0x19e90,
966 		0x19ea0, 0x19f4c,
967 		0x1a000, 0x1a004,
968 		0x1a010, 0x1a06c,
969 		0x1a0b0, 0x1a0e4,
970 		0x1a0ec, 0x1a0f4,
971 		0x1a100, 0x1a108,
972 		0x1a114, 0x1a120,
973 		0x1a128, 0x1a130,
974 		0x1a138, 0x1a138,
975 		0x1a190, 0x1a1c4,
976 		0x1a1fc, 0x1a1fc,
977 		0x1e040, 0x1e04c,
978 		0x1e284, 0x1e28c,
979 		0x1e2c0, 0x1e2c0,
980 		0x1e2e0, 0x1e2e0,
981 		0x1e300, 0x1e384,
982 		0x1e3c0, 0x1e3c8,
983 		0x1e440, 0x1e44c,
984 		0x1e684, 0x1e68c,
985 		0x1e6c0, 0x1e6c0,
986 		0x1e6e0, 0x1e6e0,
987 		0x1e700, 0x1e784,
988 		0x1e7c0, 0x1e7c8,
989 		0x1e840, 0x1e84c,
990 		0x1ea84, 0x1ea8c,
991 		0x1eac0, 0x1eac0,
992 		0x1eae0, 0x1eae0,
993 		0x1eb00, 0x1eb84,
994 		0x1ebc0, 0x1ebc8,
995 		0x1ec40, 0x1ec4c,
996 		0x1ee84, 0x1ee8c,
997 		0x1eec0, 0x1eec0,
998 		0x1eee0, 0x1eee0,
999 		0x1ef00, 0x1ef84,
1000 		0x1efc0, 0x1efc8,
1001 		0x1f040, 0x1f04c,
1002 		0x1f284, 0x1f28c,
1003 		0x1f2c0, 0x1f2c0,
1004 		0x1f2e0, 0x1f2e0,
1005 		0x1f300, 0x1f384,
1006 		0x1f3c0, 0x1f3c8,
1007 		0x1f440, 0x1f44c,
1008 		0x1f684, 0x1f68c,
1009 		0x1f6c0, 0x1f6c0,
1010 		0x1f6e0, 0x1f6e0,
1011 		0x1f700, 0x1f784,
1012 		0x1f7c0, 0x1f7c8,
1013 		0x1f840, 0x1f84c,
1014 		0x1fa84, 0x1fa8c,
1015 		0x1fac0, 0x1fac0,
1016 		0x1fae0, 0x1fae0,
1017 		0x1fb00, 0x1fb84,
1018 		0x1fbc0, 0x1fbc8,
1019 		0x1fc40, 0x1fc4c,
1020 		0x1fe84, 0x1fe8c,
1021 		0x1fec0, 0x1fec0,
1022 		0x1fee0, 0x1fee0,
1023 		0x1ff00, 0x1ff84,
1024 		0x1ffc0, 0x1ffc8,
1025 		0x20000, 0x2002c,
1026 		0x20100, 0x2013c,
1027 		0x20190, 0x201a0,
1028 		0x201a8, 0x201b8,
1029 		0x201c4, 0x201c8,
1030 		0x20200, 0x20318,
1031 		0x20400, 0x204b4,
1032 		0x204c0, 0x20528,
1033 		0x20540, 0x20614,
1034 		0x21000, 0x21040,
1035 		0x2104c, 0x21060,
1036 		0x210c0, 0x210ec,
1037 		0x21200, 0x21268,
1038 		0x21270, 0x21284,
1039 		0x212fc, 0x21388,
1040 		0x21400, 0x21404,
1041 		0x21500, 0x21500,
1042 		0x21510, 0x21518,
1043 		0x2152c, 0x21530,
1044 		0x2153c, 0x2153c,
1045 		0x21550, 0x21554,
1046 		0x21600, 0x21600,
1047 		0x21608, 0x2161c,
1048 		0x21624, 0x21628,
1049 		0x21630, 0x21634,
1050 		0x2163c, 0x2163c,
1051 		0x21700, 0x2171c,
1052 		0x21780, 0x2178c,
1053 		0x21800, 0x21818,
1054 		0x21820, 0x21828,
1055 		0x21830, 0x21848,
1056 		0x21850, 0x21854,
1057 		0x21860, 0x21868,
1058 		0x21870, 0x21870,
1059 		0x21878, 0x21898,
1060 		0x218a0, 0x218a8,
1061 		0x218b0, 0x218c8,
1062 		0x218d0, 0x218d4,
1063 		0x218e0, 0x218e8,
1064 		0x218f0, 0x218f0,
1065 		0x218f8, 0x21a18,
1066 		0x21a20, 0x21a28,
1067 		0x21a30, 0x21a48,
1068 		0x21a50, 0x21a54,
1069 		0x21a60, 0x21a68,
1070 		0x21a70, 0x21a70,
1071 		0x21a78, 0x21a98,
1072 		0x21aa0, 0x21aa8,
1073 		0x21ab0, 0x21ac8,
1074 		0x21ad0, 0x21ad4,
1075 		0x21ae0, 0x21ae8,
1076 		0x21af0, 0x21af0,
1077 		0x21af8, 0x21c18,
1078 		0x21c20, 0x21c20,
1079 		0x21c28, 0x21c30,
1080 		0x21c38, 0x21c38,
1081 		0x21c80, 0x21c98,
1082 		0x21ca0, 0x21ca8,
1083 		0x21cb0, 0x21cc8,
1084 		0x21cd0, 0x21cd4,
1085 		0x21ce0, 0x21ce8,
1086 		0x21cf0, 0x21cf0,
1087 		0x21cf8, 0x21d7c,
1088 		0x21e00, 0x21e04,
1089 		0x22000, 0x2202c,
1090 		0x22100, 0x2213c,
1091 		0x22190, 0x221a0,
1092 		0x221a8, 0x221b8,
1093 		0x221c4, 0x221c8,
1094 		0x22200, 0x22318,
1095 		0x22400, 0x224b4,
1096 		0x224c0, 0x22528,
1097 		0x22540, 0x22614,
1098 		0x23000, 0x23040,
1099 		0x2304c, 0x23060,
1100 		0x230c0, 0x230ec,
1101 		0x23200, 0x23268,
1102 		0x23270, 0x23284,
1103 		0x232fc, 0x23388,
1104 		0x23400, 0x23404,
1105 		0x23500, 0x23500,
1106 		0x23510, 0x23518,
1107 		0x2352c, 0x23530,
1108 		0x2353c, 0x2353c,
1109 		0x23550, 0x23554,
1110 		0x23600, 0x23600,
1111 		0x23608, 0x2361c,
1112 		0x23624, 0x23628,
1113 		0x23630, 0x23634,
1114 		0x2363c, 0x2363c,
1115 		0x23700, 0x2371c,
1116 		0x23780, 0x2378c,
1117 		0x23800, 0x23818,
1118 		0x23820, 0x23828,
1119 		0x23830, 0x23848,
1120 		0x23850, 0x23854,
1121 		0x23860, 0x23868,
1122 		0x23870, 0x23870,
1123 		0x23878, 0x23898,
1124 		0x238a0, 0x238a8,
1125 		0x238b0, 0x238c8,
1126 		0x238d0, 0x238d4,
1127 		0x238e0, 0x238e8,
1128 		0x238f0, 0x238f0,
1129 		0x238f8, 0x23a18,
1130 		0x23a20, 0x23a28,
1131 		0x23a30, 0x23a48,
1132 		0x23a50, 0x23a54,
1133 		0x23a60, 0x23a68,
1134 		0x23a70, 0x23a70,
1135 		0x23a78, 0x23a98,
1136 		0x23aa0, 0x23aa8,
1137 		0x23ab0, 0x23ac8,
1138 		0x23ad0, 0x23ad4,
1139 		0x23ae0, 0x23ae8,
1140 		0x23af0, 0x23af0,
1141 		0x23af8, 0x23c18,
1142 		0x23c20, 0x23c20,
1143 		0x23c28, 0x23c30,
1144 		0x23c38, 0x23c38,
1145 		0x23c80, 0x23c98,
1146 		0x23ca0, 0x23ca8,
1147 		0x23cb0, 0x23cc8,
1148 		0x23cd0, 0x23cd4,
1149 		0x23ce0, 0x23ce8,
1150 		0x23cf0, 0x23cf0,
1151 		0x23cf8, 0x23d7c,
1152 		0x23e00, 0x23e04,
1153 		0x24000, 0x2402c,
1154 		0x24100, 0x2413c,
1155 		0x24190, 0x241a0,
1156 		0x241a8, 0x241b8,
1157 		0x241c4, 0x241c8,
1158 		0x24200, 0x24318,
1159 		0x24400, 0x244b4,
1160 		0x244c0, 0x24528,
1161 		0x24540, 0x24614,
1162 		0x25000, 0x25040,
1163 		0x2504c, 0x25060,
1164 		0x250c0, 0x250ec,
1165 		0x25200, 0x25268,
1166 		0x25270, 0x25284,
1167 		0x252fc, 0x25388,
1168 		0x25400, 0x25404,
1169 		0x25500, 0x25500,
1170 		0x25510, 0x25518,
1171 		0x2552c, 0x25530,
1172 		0x2553c, 0x2553c,
1173 		0x25550, 0x25554,
1174 		0x25600, 0x25600,
1175 		0x25608, 0x2561c,
1176 		0x25624, 0x25628,
1177 		0x25630, 0x25634,
1178 		0x2563c, 0x2563c,
1179 		0x25700, 0x2571c,
1180 		0x25780, 0x2578c,
1181 		0x25800, 0x25818,
1182 		0x25820, 0x25828,
1183 		0x25830, 0x25848,
1184 		0x25850, 0x25854,
1185 		0x25860, 0x25868,
1186 		0x25870, 0x25870,
1187 		0x25878, 0x25898,
1188 		0x258a0, 0x258a8,
1189 		0x258b0, 0x258c8,
1190 		0x258d0, 0x258d4,
1191 		0x258e0, 0x258e8,
1192 		0x258f0, 0x258f0,
1193 		0x258f8, 0x25a18,
1194 		0x25a20, 0x25a28,
1195 		0x25a30, 0x25a48,
1196 		0x25a50, 0x25a54,
1197 		0x25a60, 0x25a68,
1198 		0x25a70, 0x25a70,
1199 		0x25a78, 0x25a98,
1200 		0x25aa0, 0x25aa8,
1201 		0x25ab0, 0x25ac8,
1202 		0x25ad0, 0x25ad4,
1203 		0x25ae0, 0x25ae8,
1204 		0x25af0, 0x25af0,
1205 		0x25af8, 0x25c18,
1206 		0x25c20, 0x25c20,
1207 		0x25c28, 0x25c30,
1208 		0x25c38, 0x25c38,
1209 		0x25c80, 0x25c98,
1210 		0x25ca0, 0x25ca8,
1211 		0x25cb0, 0x25cc8,
1212 		0x25cd0, 0x25cd4,
1213 		0x25ce0, 0x25ce8,
1214 		0x25cf0, 0x25cf0,
1215 		0x25cf8, 0x25d7c,
1216 		0x25e00, 0x25e04,
1217 		0x26000, 0x2602c,
1218 		0x26100, 0x2613c,
1219 		0x26190, 0x261a0,
1220 		0x261a8, 0x261b8,
1221 		0x261c4, 0x261c8,
1222 		0x26200, 0x26318,
1223 		0x26400, 0x264b4,
1224 		0x264c0, 0x26528,
1225 		0x26540, 0x26614,
1226 		0x27000, 0x27040,
1227 		0x2704c, 0x27060,
1228 		0x270c0, 0x270ec,
1229 		0x27200, 0x27268,
1230 		0x27270, 0x27284,
1231 		0x272fc, 0x27388,
1232 		0x27400, 0x27404,
1233 		0x27500, 0x27500,
1234 		0x27510, 0x27518,
1235 		0x2752c, 0x27530,
1236 		0x2753c, 0x2753c,
1237 		0x27550, 0x27554,
1238 		0x27600, 0x27600,
1239 		0x27608, 0x2761c,
1240 		0x27624, 0x27628,
1241 		0x27630, 0x27634,
1242 		0x2763c, 0x2763c,
1243 		0x27700, 0x2771c,
1244 		0x27780, 0x2778c,
1245 		0x27800, 0x27818,
1246 		0x27820, 0x27828,
1247 		0x27830, 0x27848,
1248 		0x27850, 0x27854,
1249 		0x27860, 0x27868,
1250 		0x27870, 0x27870,
1251 		0x27878, 0x27898,
1252 		0x278a0, 0x278a8,
1253 		0x278b0, 0x278c8,
1254 		0x278d0, 0x278d4,
1255 		0x278e0, 0x278e8,
1256 		0x278f0, 0x278f0,
1257 		0x278f8, 0x27a18,
1258 		0x27a20, 0x27a28,
1259 		0x27a30, 0x27a48,
1260 		0x27a50, 0x27a54,
1261 		0x27a60, 0x27a68,
1262 		0x27a70, 0x27a70,
1263 		0x27a78, 0x27a98,
1264 		0x27aa0, 0x27aa8,
1265 		0x27ab0, 0x27ac8,
1266 		0x27ad0, 0x27ad4,
1267 		0x27ae0, 0x27ae8,
1268 		0x27af0, 0x27af0,
1269 		0x27af8, 0x27c18,
1270 		0x27c20, 0x27c20,
1271 		0x27c28, 0x27c30,
1272 		0x27c38, 0x27c38,
1273 		0x27c80, 0x27c98,
1274 		0x27ca0, 0x27ca8,
1275 		0x27cb0, 0x27cc8,
1276 		0x27cd0, 0x27cd4,
1277 		0x27ce0, 0x27ce8,
1278 		0x27cf0, 0x27cf0,
1279 		0x27cf8, 0x27d7c,
1280 		0x27e00, 0x27e04,
1281 	};
1282 
1283 	static const unsigned int t4vf_reg_ranges[] = {
1284 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1285 		VF_MPS_REG(A_MPS_VF_CTL),
1286 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1287 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1288 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1289 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1290 		FW_T4VF_MBDATA_BASE_ADDR,
1291 		FW_T4VF_MBDATA_BASE_ADDR +
1292 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1293 	};
1294 
1295 	static const unsigned int t5_reg_ranges[] = {
1296 		0x1008, 0x10c0,
1297 		0x10cc, 0x10f8,
1298 		0x1100, 0x1100,
1299 		0x110c, 0x1148,
1300 		0x1180, 0x1184,
1301 		0x1190, 0x1194,
1302 		0x11a0, 0x11a4,
1303 		0x11b0, 0x11b4,
1304 		0x11fc, 0x123c,
1305 		0x1280, 0x173c,
1306 		0x1800, 0x18fc,
1307 		0x3000, 0x3028,
1308 		0x3060, 0x30b0,
1309 		0x30b8, 0x30d8,
1310 		0x30e0, 0x30fc,
1311 		0x3140, 0x357c,
1312 		0x35a8, 0x35cc,
1313 		0x35ec, 0x35ec,
1314 		0x3600, 0x5624,
1315 		0x56cc, 0x56ec,
1316 		0x56f4, 0x5720,
1317 		0x5728, 0x575c,
1318 		0x580c, 0x5814,
1319 		0x5890, 0x589c,
1320 		0x58a4, 0x58ac,
1321 		0x58b8, 0x58bc,
1322 		0x5940, 0x59c8,
1323 		0x59d0, 0x59dc,
1324 		0x59fc, 0x5a18,
1325 		0x5a60, 0x5a70,
1326 		0x5a80, 0x5a9c,
1327 		0x5b94, 0x5bfc,
1328 		0x6000, 0x6020,
1329 		0x6028, 0x6040,
1330 		0x6058, 0x609c,
1331 		0x60a8, 0x614c,
1332 		0x7700, 0x7798,
1333 		0x77c0, 0x78fc,
1334 		0x7b00, 0x7b58,
1335 		0x7b60, 0x7b84,
1336 		0x7b8c, 0x7c54,
1337 		0x7d00, 0x7d38,
1338 		0x7d40, 0x7d80,
1339 		0x7d8c, 0x7ddc,
1340 		0x7de4, 0x7e04,
1341 		0x7e10, 0x7e1c,
1342 		0x7e24, 0x7e38,
1343 		0x7e40, 0x7e44,
1344 		0x7e4c, 0x7e78,
1345 		0x7e80, 0x7edc,
1346 		0x7ee8, 0x7efc,
1347 		0x8dc0, 0x8de0,
1348 		0x8df8, 0x8e04,
1349 		0x8e10, 0x8e84,
1350 		0x8ea0, 0x8f84,
1351 		0x8fc0, 0x9058,
1352 		0x9060, 0x9060,
1353 		0x9068, 0x90f8,
1354 		0x9400, 0x9408,
1355 		0x9410, 0x9470,
1356 		0x9600, 0x9600,
1357 		0x9608, 0x9638,
1358 		0x9640, 0x96f4,
1359 		0x9800, 0x9808,
1360 		0x9810, 0x9864,
1361 		0x9c00, 0x9c6c,
1362 		0x9c80, 0x9cec,
1363 		0x9d00, 0x9d6c,
1364 		0x9d80, 0x9dec,
1365 		0x9e00, 0x9e6c,
1366 		0x9e80, 0x9eec,
1367 		0x9f00, 0x9f6c,
1368 		0x9f80, 0xa020,
1369 		0xd000, 0xd004,
1370 		0xd010, 0xd03c,
1371 		0xdfc0, 0xdfe0,
1372 		0xe000, 0x1106c,
1373 		0x11074, 0x11088,
1374 		0x1109c, 0x11110,
1375 		0x11118, 0x1117c,
1376 		0x11190, 0x11204,
1377 		0x19040, 0x1906c,
1378 		0x19078, 0x19080,
1379 		0x1908c, 0x190e8,
1380 		0x190f0, 0x190f8,
1381 		0x19100, 0x19110,
1382 		0x19120, 0x19124,
1383 		0x19150, 0x19194,
1384 		0x1919c, 0x191b0,
1385 		0x191d0, 0x191e8,
1386 		0x19238, 0x19290,
1387 		0x193f8, 0x19428,
1388 		0x19430, 0x19444,
1389 		0x1944c, 0x1946c,
1390 		0x19474, 0x19474,
1391 		0x19490, 0x194cc,
1392 		0x194f0, 0x194f8,
1393 		0x19c00, 0x19c08,
1394 		0x19c10, 0x19c60,
1395 		0x19c94, 0x19ce4,
1396 		0x19cf0, 0x19d40,
1397 		0x19d50, 0x19d94,
1398 		0x19da0, 0x19de8,
1399 		0x19df0, 0x19e10,
1400 		0x19e50, 0x19e90,
1401 		0x19ea0, 0x19f24,
1402 		0x19f34, 0x19f34,
1403 		0x19f40, 0x19f50,
1404 		0x19f90, 0x19fb4,
1405 		0x19fc4, 0x19fe4,
1406 		0x1a000, 0x1a004,
1407 		0x1a010, 0x1a06c,
1408 		0x1a0b0, 0x1a0e4,
1409 		0x1a0ec, 0x1a0f8,
1410 		0x1a100, 0x1a108,
1411 		0x1a114, 0x1a130,
1412 		0x1a138, 0x1a1c4,
1413 		0x1a1fc, 0x1a1fc,
1414 		0x1e008, 0x1e00c,
1415 		0x1e040, 0x1e044,
1416 		0x1e04c, 0x1e04c,
1417 		0x1e284, 0x1e290,
1418 		0x1e2c0, 0x1e2c0,
1419 		0x1e2e0, 0x1e2e0,
1420 		0x1e300, 0x1e384,
1421 		0x1e3c0, 0x1e3c8,
1422 		0x1e408, 0x1e40c,
1423 		0x1e440, 0x1e444,
1424 		0x1e44c, 0x1e44c,
1425 		0x1e684, 0x1e690,
1426 		0x1e6c0, 0x1e6c0,
1427 		0x1e6e0, 0x1e6e0,
1428 		0x1e700, 0x1e784,
1429 		0x1e7c0, 0x1e7c8,
1430 		0x1e808, 0x1e80c,
1431 		0x1e840, 0x1e844,
1432 		0x1e84c, 0x1e84c,
1433 		0x1ea84, 0x1ea90,
1434 		0x1eac0, 0x1eac0,
1435 		0x1eae0, 0x1eae0,
1436 		0x1eb00, 0x1eb84,
1437 		0x1ebc0, 0x1ebc8,
1438 		0x1ec08, 0x1ec0c,
1439 		0x1ec40, 0x1ec44,
1440 		0x1ec4c, 0x1ec4c,
1441 		0x1ee84, 0x1ee90,
1442 		0x1eec0, 0x1eec0,
1443 		0x1eee0, 0x1eee0,
1444 		0x1ef00, 0x1ef84,
1445 		0x1efc0, 0x1efc8,
1446 		0x1f008, 0x1f00c,
1447 		0x1f040, 0x1f044,
1448 		0x1f04c, 0x1f04c,
1449 		0x1f284, 0x1f290,
1450 		0x1f2c0, 0x1f2c0,
1451 		0x1f2e0, 0x1f2e0,
1452 		0x1f300, 0x1f384,
1453 		0x1f3c0, 0x1f3c8,
1454 		0x1f408, 0x1f40c,
1455 		0x1f440, 0x1f444,
1456 		0x1f44c, 0x1f44c,
1457 		0x1f684, 0x1f690,
1458 		0x1f6c0, 0x1f6c0,
1459 		0x1f6e0, 0x1f6e0,
1460 		0x1f700, 0x1f784,
1461 		0x1f7c0, 0x1f7c8,
1462 		0x1f808, 0x1f80c,
1463 		0x1f840, 0x1f844,
1464 		0x1f84c, 0x1f84c,
1465 		0x1fa84, 0x1fa90,
1466 		0x1fac0, 0x1fac0,
1467 		0x1fae0, 0x1fae0,
1468 		0x1fb00, 0x1fb84,
1469 		0x1fbc0, 0x1fbc8,
1470 		0x1fc08, 0x1fc0c,
1471 		0x1fc40, 0x1fc44,
1472 		0x1fc4c, 0x1fc4c,
1473 		0x1fe84, 0x1fe90,
1474 		0x1fec0, 0x1fec0,
1475 		0x1fee0, 0x1fee0,
1476 		0x1ff00, 0x1ff84,
1477 		0x1ffc0, 0x1ffc8,
1478 		0x30000, 0x30030,
1479 		0x30100, 0x30144,
1480 		0x30190, 0x301a0,
1481 		0x301a8, 0x301b8,
1482 		0x301c4, 0x301c8,
1483 		0x301d0, 0x301d0,
1484 		0x30200, 0x30318,
1485 		0x30400, 0x304b4,
1486 		0x304c0, 0x3052c,
1487 		0x30540, 0x3061c,
1488 		0x30800, 0x30828,
1489 		0x30834, 0x30834,
1490 		0x308c0, 0x30908,
1491 		0x30910, 0x309ac,
1492 		0x30a00, 0x30a14,
1493 		0x30a1c, 0x30a2c,
1494 		0x30a44, 0x30a50,
1495 		0x30a74, 0x30a74,
1496 		0x30a7c, 0x30afc,
1497 		0x30b08, 0x30c24,
1498 		0x30d00, 0x30d00,
1499 		0x30d08, 0x30d14,
1500 		0x30d1c, 0x30d20,
1501 		0x30d3c, 0x30d3c,
1502 		0x30d48, 0x30d50,
1503 		0x31200, 0x3120c,
1504 		0x31220, 0x31220,
1505 		0x31240, 0x31240,
1506 		0x31600, 0x3160c,
1507 		0x31a00, 0x31a1c,
1508 		0x31e00, 0x31e20,
1509 		0x31e38, 0x31e3c,
1510 		0x31e80, 0x31e80,
1511 		0x31e88, 0x31ea8,
1512 		0x31eb0, 0x31eb4,
1513 		0x31ec8, 0x31ed4,
1514 		0x31fb8, 0x32004,
1515 		0x32200, 0x32200,
1516 		0x32208, 0x32240,
1517 		0x32248, 0x32280,
1518 		0x32288, 0x322c0,
1519 		0x322c8, 0x322fc,
1520 		0x32600, 0x32630,
1521 		0x32a00, 0x32abc,
1522 		0x32b00, 0x32b10,
1523 		0x32b20, 0x32b30,
1524 		0x32b40, 0x32b50,
1525 		0x32b60, 0x32b70,
1526 		0x33000, 0x33028,
1527 		0x33030, 0x33048,
1528 		0x33060, 0x33068,
1529 		0x33070, 0x3309c,
1530 		0x330f0, 0x33128,
1531 		0x33130, 0x33148,
1532 		0x33160, 0x33168,
1533 		0x33170, 0x3319c,
1534 		0x331f0, 0x33238,
1535 		0x33240, 0x33240,
1536 		0x33248, 0x33250,
1537 		0x3325c, 0x33264,
1538 		0x33270, 0x332b8,
1539 		0x332c0, 0x332e4,
1540 		0x332f8, 0x33338,
1541 		0x33340, 0x33340,
1542 		0x33348, 0x33350,
1543 		0x3335c, 0x33364,
1544 		0x33370, 0x333b8,
1545 		0x333c0, 0x333e4,
1546 		0x333f8, 0x33428,
1547 		0x33430, 0x33448,
1548 		0x33460, 0x33468,
1549 		0x33470, 0x3349c,
1550 		0x334f0, 0x33528,
1551 		0x33530, 0x33548,
1552 		0x33560, 0x33568,
1553 		0x33570, 0x3359c,
1554 		0x335f0, 0x33638,
1555 		0x33640, 0x33640,
1556 		0x33648, 0x33650,
1557 		0x3365c, 0x33664,
1558 		0x33670, 0x336b8,
1559 		0x336c0, 0x336e4,
1560 		0x336f8, 0x33738,
1561 		0x33740, 0x33740,
1562 		0x33748, 0x33750,
1563 		0x3375c, 0x33764,
1564 		0x33770, 0x337b8,
1565 		0x337c0, 0x337e4,
1566 		0x337f8, 0x337fc,
1567 		0x33814, 0x33814,
1568 		0x3382c, 0x3382c,
1569 		0x33880, 0x3388c,
1570 		0x338e8, 0x338ec,
1571 		0x33900, 0x33928,
1572 		0x33930, 0x33948,
1573 		0x33960, 0x33968,
1574 		0x33970, 0x3399c,
1575 		0x339f0, 0x33a38,
1576 		0x33a40, 0x33a40,
1577 		0x33a48, 0x33a50,
1578 		0x33a5c, 0x33a64,
1579 		0x33a70, 0x33ab8,
1580 		0x33ac0, 0x33ae4,
1581 		0x33af8, 0x33b10,
1582 		0x33b28, 0x33b28,
1583 		0x33b3c, 0x33b50,
1584 		0x33bf0, 0x33c10,
1585 		0x33c28, 0x33c28,
1586 		0x33c3c, 0x33c50,
1587 		0x33cf0, 0x33cfc,
1588 		0x34000, 0x34030,
1589 		0x34100, 0x34144,
1590 		0x34190, 0x341a0,
1591 		0x341a8, 0x341b8,
1592 		0x341c4, 0x341c8,
1593 		0x341d0, 0x341d0,
1594 		0x34200, 0x34318,
1595 		0x34400, 0x344b4,
1596 		0x344c0, 0x3452c,
1597 		0x34540, 0x3461c,
1598 		0x34800, 0x34828,
1599 		0x34834, 0x34834,
1600 		0x348c0, 0x34908,
1601 		0x34910, 0x349ac,
1602 		0x34a00, 0x34a14,
1603 		0x34a1c, 0x34a2c,
1604 		0x34a44, 0x34a50,
1605 		0x34a74, 0x34a74,
1606 		0x34a7c, 0x34afc,
1607 		0x34b08, 0x34c24,
1608 		0x34d00, 0x34d00,
1609 		0x34d08, 0x34d14,
1610 		0x34d1c, 0x34d20,
1611 		0x34d3c, 0x34d3c,
1612 		0x34d48, 0x34d50,
1613 		0x35200, 0x3520c,
1614 		0x35220, 0x35220,
1615 		0x35240, 0x35240,
1616 		0x35600, 0x3560c,
1617 		0x35a00, 0x35a1c,
1618 		0x35e00, 0x35e20,
1619 		0x35e38, 0x35e3c,
1620 		0x35e80, 0x35e80,
1621 		0x35e88, 0x35ea8,
1622 		0x35eb0, 0x35eb4,
1623 		0x35ec8, 0x35ed4,
1624 		0x35fb8, 0x36004,
1625 		0x36200, 0x36200,
1626 		0x36208, 0x36240,
1627 		0x36248, 0x36280,
1628 		0x36288, 0x362c0,
1629 		0x362c8, 0x362fc,
1630 		0x36600, 0x36630,
1631 		0x36a00, 0x36abc,
1632 		0x36b00, 0x36b10,
1633 		0x36b20, 0x36b30,
1634 		0x36b40, 0x36b50,
1635 		0x36b60, 0x36b70,
1636 		0x37000, 0x37028,
1637 		0x37030, 0x37048,
1638 		0x37060, 0x37068,
1639 		0x37070, 0x3709c,
1640 		0x370f0, 0x37128,
1641 		0x37130, 0x37148,
1642 		0x37160, 0x37168,
1643 		0x37170, 0x3719c,
1644 		0x371f0, 0x37238,
1645 		0x37240, 0x37240,
1646 		0x37248, 0x37250,
1647 		0x3725c, 0x37264,
1648 		0x37270, 0x372b8,
1649 		0x372c0, 0x372e4,
1650 		0x372f8, 0x37338,
1651 		0x37340, 0x37340,
1652 		0x37348, 0x37350,
1653 		0x3735c, 0x37364,
1654 		0x37370, 0x373b8,
1655 		0x373c0, 0x373e4,
1656 		0x373f8, 0x37428,
1657 		0x37430, 0x37448,
1658 		0x37460, 0x37468,
1659 		0x37470, 0x3749c,
1660 		0x374f0, 0x37528,
1661 		0x37530, 0x37548,
1662 		0x37560, 0x37568,
1663 		0x37570, 0x3759c,
1664 		0x375f0, 0x37638,
1665 		0x37640, 0x37640,
1666 		0x37648, 0x37650,
1667 		0x3765c, 0x37664,
1668 		0x37670, 0x376b8,
1669 		0x376c0, 0x376e4,
1670 		0x376f8, 0x37738,
1671 		0x37740, 0x37740,
1672 		0x37748, 0x37750,
1673 		0x3775c, 0x37764,
1674 		0x37770, 0x377b8,
1675 		0x377c0, 0x377e4,
1676 		0x377f8, 0x377fc,
1677 		0x37814, 0x37814,
1678 		0x3782c, 0x3782c,
1679 		0x37880, 0x3788c,
1680 		0x378e8, 0x378ec,
1681 		0x37900, 0x37928,
1682 		0x37930, 0x37948,
1683 		0x37960, 0x37968,
1684 		0x37970, 0x3799c,
1685 		0x379f0, 0x37a38,
1686 		0x37a40, 0x37a40,
1687 		0x37a48, 0x37a50,
1688 		0x37a5c, 0x37a64,
1689 		0x37a70, 0x37ab8,
1690 		0x37ac0, 0x37ae4,
1691 		0x37af8, 0x37b10,
1692 		0x37b28, 0x37b28,
1693 		0x37b3c, 0x37b50,
1694 		0x37bf0, 0x37c10,
1695 		0x37c28, 0x37c28,
1696 		0x37c3c, 0x37c50,
1697 		0x37cf0, 0x37cfc,
1698 		0x38000, 0x38030,
1699 		0x38100, 0x38144,
1700 		0x38190, 0x381a0,
1701 		0x381a8, 0x381b8,
1702 		0x381c4, 0x381c8,
1703 		0x381d0, 0x381d0,
1704 		0x38200, 0x38318,
1705 		0x38400, 0x384b4,
1706 		0x384c0, 0x3852c,
1707 		0x38540, 0x3861c,
1708 		0x38800, 0x38828,
1709 		0x38834, 0x38834,
1710 		0x388c0, 0x38908,
1711 		0x38910, 0x389ac,
1712 		0x38a00, 0x38a14,
1713 		0x38a1c, 0x38a2c,
1714 		0x38a44, 0x38a50,
1715 		0x38a74, 0x38a74,
1716 		0x38a7c, 0x38afc,
1717 		0x38b08, 0x38c24,
1718 		0x38d00, 0x38d00,
1719 		0x38d08, 0x38d14,
1720 		0x38d1c, 0x38d20,
1721 		0x38d3c, 0x38d3c,
1722 		0x38d48, 0x38d50,
1723 		0x39200, 0x3920c,
1724 		0x39220, 0x39220,
1725 		0x39240, 0x39240,
1726 		0x39600, 0x3960c,
1727 		0x39a00, 0x39a1c,
1728 		0x39e00, 0x39e20,
1729 		0x39e38, 0x39e3c,
1730 		0x39e80, 0x39e80,
1731 		0x39e88, 0x39ea8,
1732 		0x39eb0, 0x39eb4,
1733 		0x39ec8, 0x39ed4,
1734 		0x39fb8, 0x3a004,
1735 		0x3a200, 0x3a200,
1736 		0x3a208, 0x3a240,
1737 		0x3a248, 0x3a280,
1738 		0x3a288, 0x3a2c0,
1739 		0x3a2c8, 0x3a2fc,
1740 		0x3a600, 0x3a630,
1741 		0x3aa00, 0x3aabc,
1742 		0x3ab00, 0x3ab10,
1743 		0x3ab20, 0x3ab30,
1744 		0x3ab40, 0x3ab50,
1745 		0x3ab60, 0x3ab70,
1746 		0x3b000, 0x3b028,
1747 		0x3b030, 0x3b048,
1748 		0x3b060, 0x3b068,
1749 		0x3b070, 0x3b09c,
1750 		0x3b0f0, 0x3b128,
1751 		0x3b130, 0x3b148,
1752 		0x3b160, 0x3b168,
1753 		0x3b170, 0x3b19c,
1754 		0x3b1f0, 0x3b238,
1755 		0x3b240, 0x3b240,
1756 		0x3b248, 0x3b250,
1757 		0x3b25c, 0x3b264,
1758 		0x3b270, 0x3b2b8,
1759 		0x3b2c0, 0x3b2e4,
1760 		0x3b2f8, 0x3b338,
1761 		0x3b340, 0x3b340,
1762 		0x3b348, 0x3b350,
1763 		0x3b35c, 0x3b364,
1764 		0x3b370, 0x3b3b8,
1765 		0x3b3c0, 0x3b3e4,
1766 		0x3b3f8, 0x3b428,
1767 		0x3b430, 0x3b448,
1768 		0x3b460, 0x3b468,
1769 		0x3b470, 0x3b49c,
1770 		0x3b4f0, 0x3b528,
1771 		0x3b530, 0x3b548,
1772 		0x3b560, 0x3b568,
1773 		0x3b570, 0x3b59c,
1774 		0x3b5f0, 0x3b638,
1775 		0x3b640, 0x3b640,
1776 		0x3b648, 0x3b650,
1777 		0x3b65c, 0x3b664,
1778 		0x3b670, 0x3b6b8,
1779 		0x3b6c0, 0x3b6e4,
1780 		0x3b6f8, 0x3b738,
1781 		0x3b740, 0x3b740,
1782 		0x3b748, 0x3b750,
1783 		0x3b75c, 0x3b764,
1784 		0x3b770, 0x3b7b8,
1785 		0x3b7c0, 0x3b7e4,
1786 		0x3b7f8, 0x3b7fc,
1787 		0x3b814, 0x3b814,
1788 		0x3b82c, 0x3b82c,
1789 		0x3b880, 0x3b88c,
1790 		0x3b8e8, 0x3b8ec,
1791 		0x3b900, 0x3b928,
1792 		0x3b930, 0x3b948,
1793 		0x3b960, 0x3b968,
1794 		0x3b970, 0x3b99c,
1795 		0x3b9f0, 0x3ba38,
1796 		0x3ba40, 0x3ba40,
1797 		0x3ba48, 0x3ba50,
1798 		0x3ba5c, 0x3ba64,
1799 		0x3ba70, 0x3bab8,
1800 		0x3bac0, 0x3bae4,
1801 		0x3baf8, 0x3bb10,
1802 		0x3bb28, 0x3bb28,
1803 		0x3bb3c, 0x3bb50,
1804 		0x3bbf0, 0x3bc10,
1805 		0x3bc28, 0x3bc28,
1806 		0x3bc3c, 0x3bc50,
1807 		0x3bcf0, 0x3bcfc,
1808 		0x3c000, 0x3c030,
1809 		0x3c100, 0x3c144,
1810 		0x3c190, 0x3c1a0,
1811 		0x3c1a8, 0x3c1b8,
1812 		0x3c1c4, 0x3c1c8,
1813 		0x3c1d0, 0x3c1d0,
1814 		0x3c200, 0x3c318,
1815 		0x3c400, 0x3c4b4,
1816 		0x3c4c0, 0x3c52c,
1817 		0x3c540, 0x3c61c,
1818 		0x3c800, 0x3c828,
1819 		0x3c834, 0x3c834,
1820 		0x3c8c0, 0x3c908,
1821 		0x3c910, 0x3c9ac,
1822 		0x3ca00, 0x3ca14,
1823 		0x3ca1c, 0x3ca2c,
1824 		0x3ca44, 0x3ca50,
1825 		0x3ca74, 0x3ca74,
1826 		0x3ca7c, 0x3cafc,
1827 		0x3cb08, 0x3cc24,
1828 		0x3cd00, 0x3cd00,
1829 		0x3cd08, 0x3cd14,
1830 		0x3cd1c, 0x3cd20,
1831 		0x3cd3c, 0x3cd3c,
1832 		0x3cd48, 0x3cd50,
1833 		0x3d200, 0x3d20c,
1834 		0x3d220, 0x3d220,
1835 		0x3d240, 0x3d240,
1836 		0x3d600, 0x3d60c,
1837 		0x3da00, 0x3da1c,
1838 		0x3de00, 0x3de20,
1839 		0x3de38, 0x3de3c,
1840 		0x3de80, 0x3de80,
1841 		0x3de88, 0x3dea8,
1842 		0x3deb0, 0x3deb4,
1843 		0x3dec8, 0x3ded4,
1844 		0x3dfb8, 0x3e004,
1845 		0x3e200, 0x3e200,
1846 		0x3e208, 0x3e240,
1847 		0x3e248, 0x3e280,
1848 		0x3e288, 0x3e2c0,
1849 		0x3e2c8, 0x3e2fc,
1850 		0x3e600, 0x3e630,
1851 		0x3ea00, 0x3eabc,
1852 		0x3eb00, 0x3eb10,
1853 		0x3eb20, 0x3eb30,
1854 		0x3eb40, 0x3eb50,
1855 		0x3eb60, 0x3eb70,
1856 		0x3f000, 0x3f028,
1857 		0x3f030, 0x3f048,
1858 		0x3f060, 0x3f068,
1859 		0x3f070, 0x3f09c,
1860 		0x3f0f0, 0x3f128,
1861 		0x3f130, 0x3f148,
1862 		0x3f160, 0x3f168,
1863 		0x3f170, 0x3f19c,
1864 		0x3f1f0, 0x3f238,
1865 		0x3f240, 0x3f240,
1866 		0x3f248, 0x3f250,
1867 		0x3f25c, 0x3f264,
1868 		0x3f270, 0x3f2b8,
1869 		0x3f2c0, 0x3f2e4,
1870 		0x3f2f8, 0x3f338,
1871 		0x3f340, 0x3f340,
1872 		0x3f348, 0x3f350,
1873 		0x3f35c, 0x3f364,
1874 		0x3f370, 0x3f3b8,
1875 		0x3f3c0, 0x3f3e4,
1876 		0x3f3f8, 0x3f428,
1877 		0x3f430, 0x3f448,
1878 		0x3f460, 0x3f468,
1879 		0x3f470, 0x3f49c,
1880 		0x3f4f0, 0x3f528,
1881 		0x3f530, 0x3f548,
1882 		0x3f560, 0x3f568,
1883 		0x3f570, 0x3f59c,
1884 		0x3f5f0, 0x3f638,
1885 		0x3f640, 0x3f640,
1886 		0x3f648, 0x3f650,
1887 		0x3f65c, 0x3f664,
1888 		0x3f670, 0x3f6b8,
1889 		0x3f6c0, 0x3f6e4,
1890 		0x3f6f8, 0x3f738,
1891 		0x3f740, 0x3f740,
1892 		0x3f748, 0x3f750,
1893 		0x3f75c, 0x3f764,
1894 		0x3f770, 0x3f7b8,
1895 		0x3f7c0, 0x3f7e4,
1896 		0x3f7f8, 0x3f7fc,
1897 		0x3f814, 0x3f814,
1898 		0x3f82c, 0x3f82c,
1899 		0x3f880, 0x3f88c,
1900 		0x3f8e8, 0x3f8ec,
1901 		0x3f900, 0x3f928,
1902 		0x3f930, 0x3f948,
1903 		0x3f960, 0x3f968,
1904 		0x3f970, 0x3f99c,
1905 		0x3f9f0, 0x3fa38,
1906 		0x3fa40, 0x3fa40,
1907 		0x3fa48, 0x3fa50,
1908 		0x3fa5c, 0x3fa64,
1909 		0x3fa70, 0x3fab8,
1910 		0x3fac0, 0x3fae4,
1911 		0x3faf8, 0x3fb10,
1912 		0x3fb28, 0x3fb28,
1913 		0x3fb3c, 0x3fb50,
1914 		0x3fbf0, 0x3fc10,
1915 		0x3fc28, 0x3fc28,
1916 		0x3fc3c, 0x3fc50,
1917 		0x3fcf0, 0x3fcfc,
1918 		0x40000, 0x4000c,
1919 		0x40040, 0x40050,
1920 		0x40060, 0x40068,
1921 		0x4007c, 0x4008c,
1922 		0x40094, 0x400b0,
1923 		0x400c0, 0x40144,
1924 		0x40180, 0x4018c,
1925 		0x40200, 0x40254,
1926 		0x40260, 0x40264,
1927 		0x40270, 0x40288,
1928 		0x40290, 0x40298,
1929 		0x402ac, 0x402c8,
1930 		0x402d0, 0x402e0,
1931 		0x402f0, 0x402f0,
1932 		0x40300, 0x4033c,
1933 		0x403f8, 0x403fc,
1934 		0x41304, 0x413c4,
1935 		0x41400, 0x4140c,
1936 		0x41414, 0x4141c,
1937 		0x41480, 0x414d0,
1938 		0x44000, 0x44054,
1939 		0x4405c, 0x44078,
1940 		0x440c0, 0x44174,
1941 		0x44180, 0x441ac,
1942 		0x441b4, 0x441b8,
1943 		0x441c0, 0x44254,
1944 		0x4425c, 0x44278,
1945 		0x442c0, 0x44374,
1946 		0x44380, 0x443ac,
1947 		0x443b4, 0x443b8,
1948 		0x443c0, 0x44454,
1949 		0x4445c, 0x44478,
1950 		0x444c0, 0x44574,
1951 		0x44580, 0x445ac,
1952 		0x445b4, 0x445b8,
1953 		0x445c0, 0x44654,
1954 		0x4465c, 0x44678,
1955 		0x446c0, 0x44774,
1956 		0x44780, 0x447ac,
1957 		0x447b4, 0x447b8,
1958 		0x447c0, 0x44854,
1959 		0x4485c, 0x44878,
1960 		0x448c0, 0x44974,
1961 		0x44980, 0x449ac,
1962 		0x449b4, 0x449b8,
1963 		0x449c0, 0x449fc,
1964 		0x45000, 0x45004,
1965 		0x45010, 0x45030,
1966 		0x45040, 0x45060,
1967 		0x45068, 0x45068,
1968 		0x45080, 0x45084,
1969 		0x450a0, 0x450b0,
1970 		0x45200, 0x45204,
1971 		0x45210, 0x45230,
1972 		0x45240, 0x45260,
1973 		0x45268, 0x45268,
1974 		0x45280, 0x45284,
1975 		0x452a0, 0x452b0,
1976 		0x460c0, 0x460e4,
1977 		0x47000, 0x4703c,
1978 		0x47044, 0x4708c,
1979 		0x47200, 0x47250,
1980 		0x47400, 0x47408,
1981 		0x47414, 0x47420,
1982 		0x47600, 0x47618,
1983 		0x47800, 0x47814,
1984 		0x48000, 0x4800c,
1985 		0x48040, 0x48050,
1986 		0x48060, 0x48068,
1987 		0x4807c, 0x4808c,
1988 		0x48094, 0x480b0,
1989 		0x480c0, 0x48144,
1990 		0x48180, 0x4818c,
1991 		0x48200, 0x48254,
1992 		0x48260, 0x48264,
1993 		0x48270, 0x48288,
1994 		0x48290, 0x48298,
1995 		0x482ac, 0x482c8,
1996 		0x482d0, 0x482e0,
1997 		0x482f0, 0x482f0,
1998 		0x48300, 0x4833c,
1999 		0x483f8, 0x483fc,
2000 		0x49304, 0x493c4,
2001 		0x49400, 0x4940c,
2002 		0x49414, 0x4941c,
2003 		0x49480, 0x494d0,
2004 		0x4c000, 0x4c054,
2005 		0x4c05c, 0x4c078,
2006 		0x4c0c0, 0x4c174,
2007 		0x4c180, 0x4c1ac,
2008 		0x4c1b4, 0x4c1b8,
2009 		0x4c1c0, 0x4c254,
2010 		0x4c25c, 0x4c278,
2011 		0x4c2c0, 0x4c374,
2012 		0x4c380, 0x4c3ac,
2013 		0x4c3b4, 0x4c3b8,
2014 		0x4c3c0, 0x4c454,
2015 		0x4c45c, 0x4c478,
2016 		0x4c4c0, 0x4c574,
2017 		0x4c580, 0x4c5ac,
2018 		0x4c5b4, 0x4c5b8,
2019 		0x4c5c0, 0x4c654,
2020 		0x4c65c, 0x4c678,
2021 		0x4c6c0, 0x4c774,
2022 		0x4c780, 0x4c7ac,
2023 		0x4c7b4, 0x4c7b8,
2024 		0x4c7c0, 0x4c854,
2025 		0x4c85c, 0x4c878,
2026 		0x4c8c0, 0x4c974,
2027 		0x4c980, 0x4c9ac,
2028 		0x4c9b4, 0x4c9b8,
2029 		0x4c9c0, 0x4c9fc,
2030 		0x4d000, 0x4d004,
2031 		0x4d010, 0x4d030,
2032 		0x4d040, 0x4d060,
2033 		0x4d068, 0x4d068,
2034 		0x4d080, 0x4d084,
2035 		0x4d0a0, 0x4d0b0,
2036 		0x4d200, 0x4d204,
2037 		0x4d210, 0x4d230,
2038 		0x4d240, 0x4d260,
2039 		0x4d268, 0x4d268,
2040 		0x4d280, 0x4d284,
2041 		0x4d2a0, 0x4d2b0,
2042 		0x4e0c0, 0x4e0e4,
2043 		0x4f000, 0x4f03c,
2044 		0x4f044, 0x4f08c,
2045 		0x4f200, 0x4f250,
2046 		0x4f400, 0x4f408,
2047 		0x4f414, 0x4f420,
2048 		0x4f600, 0x4f618,
2049 		0x4f800, 0x4f814,
2050 		0x50000, 0x50084,
2051 		0x50090, 0x500cc,
2052 		0x50400, 0x50400,
2053 		0x50800, 0x50884,
2054 		0x50890, 0x508cc,
2055 		0x50c00, 0x50c00,
2056 		0x51000, 0x5101c,
2057 		0x51300, 0x51308,
2058 	};
2059 
2060 	static const unsigned int t5vf_reg_ranges[] = {
2061 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2062 		VF_MPS_REG(A_MPS_VF_CTL),
2063 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2064 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2065 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2066 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2067 		FW_T4VF_MBDATA_BASE_ADDR,
2068 		FW_T4VF_MBDATA_BASE_ADDR +
2069 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2070 	};
2071 
2072 	static const unsigned int t6_reg_ranges[] = {
2073 		0x1008, 0x101c,
2074 		0x1024, 0x10a8,
2075 		0x10b4, 0x10f8,
2076 		0x1100, 0x1114,
2077 		0x111c, 0x112c,
2078 		0x1138, 0x113c,
2079 		0x1144, 0x114c,
2080 		0x1180, 0x1184,
2081 		0x1190, 0x1194,
2082 		0x11a0, 0x11a4,
2083 		0x11b0, 0x11c4,
2084 		0x11fc, 0x123c,
2085 		0x1254, 0x1274,
2086 		0x1280, 0x133c,
2087 		0x1800, 0x18fc,
2088 		0x3000, 0x302c,
2089 		0x3060, 0x30b0,
2090 		0x30b8, 0x30d8,
2091 		0x30e0, 0x30fc,
2092 		0x3140, 0x357c,
2093 		0x35a8, 0x35cc,
2094 		0x35ec, 0x35ec,
2095 		0x3600, 0x5624,
2096 		0x56cc, 0x56ec,
2097 		0x56f4, 0x5720,
2098 		0x5728, 0x575c,
2099 		0x580c, 0x5814,
2100 		0x5890, 0x589c,
2101 		0x58a4, 0x58ac,
2102 		0x58b8, 0x58bc,
2103 		0x5940, 0x595c,
2104 		0x5980, 0x598c,
2105 		0x59b0, 0x59c8,
2106 		0x59d0, 0x59dc,
2107 		0x59fc, 0x5a18,
2108 		0x5a60, 0x5a6c,
2109 		0x5a80, 0x5a8c,
2110 		0x5a94, 0x5a9c,
2111 		0x5b94, 0x5bfc,
2112 		0x5c10, 0x5e48,
2113 		0x5e50, 0x5e94,
2114 		0x5ea0, 0x5eb0,
2115 		0x5ec0, 0x5ec0,
2116 		0x5ec8, 0x5ed0,
2117 		0x5ee0, 0x5ee0,
2118 		0x5ef0, 0x5ef0,
2119 		0x5f00, 0x5f00,
2120 		0x6000, 0x6020,
2121 		0x6028, 0x6040,
2122 		0x6058, 0x609c,
2123 		0x60a8, 0x619c,
2124 		0x7700, 0x7798,
2125 		0x77c0, 0x7880,
2126 		0x78cc, 0x78fc,
2127 		0x7b00, 0x7b58,
2128 		0x7b60, 0x7b84,
2129 		0x7b8c, 0x7c54,
2130 		0x7d00, 0x7d38,
2131 		0x7d40, 0x7d84,
2132 		0x7d8c, 0x7ddc,
2133 		0x7de4, 0x7e04,
2134 		0x7e10, 0x7e1c,
2135 		0x7e24, 0x7e38,
2136 		0x7e40, 0x7e44,
2137 		0x7e4c, 0x7e78,
2138 		0x7e80, 0x7edc,
2139 		0x7ee8, 0x7efc,
2140 		0x8dc0, 0x8de0,
2141 		0x8df8, 0x8e04,
2142 		0x8e10, 0x8e84,
2143 		0x8ea0, 0x8f88,
2144 		0x8fb8, 0x9058,
2145 		0x9060, 0x9060,
2146 		0x9068, 0x90f8,
2147 		0x9100, 0x9124,
2148 		0x9400, 0x9470,
2149 		0x9600, 0x9600,
2150 		0x9608, 0x9638,
2151 		0x9640, 0x9704,
2152 		0x9710, 0x971c,
2153 		0x9800, 0x9808,
2154 		0x9810, 0x9864,
2155 		0x9c00, 0x9c6c,
2156 		0x9c80, 0x9cec,
2157 		0x9d00, 0x9d6c,
2158 		0x9d80, 0x9dec,
2159 		0x9e00, 0x9e6c,
2160 		0x9e80, 0x9eec,
2161 		0x9f00, 0x9f6c,
2162 		0x9f80, 0xa020,
2163 		0xd000, 0xd03c,
2164 		0xd100, 0xd118,
2165 		0xd200, 0xd214,
2166 		0xd220, 0xd234,
2167 		0xd240, 0xd254,
2168 		0xd260, 0xd274,
2169 		0xd280, 0xd294,
2170 		0xd2a0, 0xd2b4,
2171 		0xd2c0, 0xd2d4,
2172 		0xd2e0, 0xd2f4,
2173 		0xd300, 0xd31c,
2174 		0xdfc0, 0xdfe0,
2175 		0xe000, 0xf008,
2176 		0xf010, 0xf018,
2177 		0xf020, 0xf028,
2178 		0x11000, 0x11014,
2179 		0x11048, 0x1106c,
2180 		0x11074, 0x11088,
2181 		0x11098, 0x11120,
2182 		0x1112c, 0x1117c,
2183 		0x11190, 0x112e0,
2184 		0x11300, 0x1130c,
2185 		0x12000, 0x1206c,
2186 		0x19040, 0x1906c,
2187 		0x19078, 0x19080,
2188 		0x1908c, 0x190e8,
2189 		0x190f0, 0x190f8,
2190 		0x19100, 0x19110,
2191 		0x19120, 0x19124,
2192 		0x19150, 0x19194,
2193 		0x1919c, 0x191b0,
2194 		0x191d0, 0x191e8,
2195 		0x19238, 0x19290,
2196 		0x192a4, 0x192b0,
2197 		0x19348, 0x1934c,
2198 		0x193f8, 0x19418,
2199 		0x19420, 0x19428,
2200 		0x19430, 0x19444,
2201 		0x1944c, 0x1946c,
2202 		0x19474, 0x19474,
2203 		0x19490, 0x194cc,
2204 		0x194f0, 0x194f8,
2205 		0x19c00, 0x19c48,
2206 		0x19c50, 0x19c80,
2207 		0x19c94, 0x19c98,
2208 		0x19ca0, 0x19cbc,
2209 		0x19ce4, 0x19ce4,
2210 		0x19cf0, 0x19cf8,
2211 		0x19d00, 0x19d28,
2212 		0x19d50, 0x19d78,
2213 		0x19d94, 0x19d98,
2214 		0x19da0, 0x19de0,
2215 		0x19df0, 0x19e10,
2216 		0x19e50, 0x19e6c,
2217 		0x19ea0, 0x19ebc,
2218 		0x19ec4, 0x19ef4,
2219 		0x19f04, 0x19f2c,
2220 		0x19f34, 0x19f34,
2221 		0x19f40, 0x19f50,
2222 		0x19f90, 0x19fac,
2223 		0x19fc4, 0x19fc8,
2224 		0x19fd0, 0x19fe4,
2225 		0x1a000, 0x1a004,
2226 		0x1a010, 0x1a06c,
2227 		0x1a0b0, 0x1a0e4,
2228 		0x1a0ec, 0x1a0f8,
2229 		0x1a100, 0x1a108,
2230 		0x1a114, 0x1a130,
2231 		0x1a138, 0x1a1c4,
2232 		0x1a1fc, 0x1a1fc,
2233 		0x1e008, 0x1e00c,
2234 		0x1e040, 0x1e044,
2235 		0x1e04c, 0x1e04c,
2236 		0x1e284, 0x1e290,
2237 		0x1e2c0, 0x1e2c0,
2238 		0x1e2e0, 0x1e2e0,
2239 		0x1e300, 0x1e384,
2240 		0x1e3c0, 0x1e3c8,
2241 		0x1e408, 0x1e40c,
2242 		0x1e440, 0x1e444,
2243 		0x1e44c, 0x1e44c,
2244 		0x1e684, 0x1e690,
2245 		0x1e6c0, 0x1e6c0,
2246 		0x1e6e0, 0x1e6e0,
2247 		0x1e700, 0x1e784,
2248 		0x1e7c0, 0x1e7c8,
2249 		0x1e808, 0x1e80c,
2250 		0x1e840, 0x1e844,
2251 		0x1e84c, 0x1e84c,
2252 		0x1ea84, 0x1ea90,
2253 		0x1eac0, 0x1eac0,
2254 		0x1eae0, 0x1eae0,
2255 		0x1eb00, 0x1eb84,
2256 		0x1ebc0, 0x1ebc8,
2257 		0x1ec08, 0x1ec0c,
2258 		0x1ec40, 0x1ec44,
2259 		0x1ec4c, 0x1ec4c,
2260 		0x1ee84, 0x1ee90,
2261 		0x1eec0, 0x1eec0,
2262 		0x1eee0, 0x1eee0,
2263 		0x1ef00, 0x1ef84,
2264 		0x1efc0, 0x1efc8,
2265 		0x1f008, 0x1f00c,
2266 		0x1f040, 0x1f044,
2267 		0x1f04c, 0x1f04c,
2268 		0x1f284, 0x1f290,
2269 		0x1f2c0, 0x1f2c0,
2270 		0x1f2e0, 0x1f2e0,
2271 		0x1f300, 0x1f384,
2272 		0x1f3c0, 0x1f3c8,
2273 		0x1f408, 0x1f40c,
2274 		0x1f440, 0x1f444,
2275 		0x1f44c, 0x1f44c,
2276 		0x1f684, 0x1f690,
2277 		0x1f6c0, 0x1f6c0,
2278 		0x1f6e0, 0x1f6e0,
2279 		0x1f700, 0x1f784,
2280 		0x1f7c0, 0x1f7c8,
2281 		0x1f808, 0x1f80c,
2282 		0x1f840, 0x1f844,
2283 		0x1f84c, 0x1f84c,
2284 		0x1fa84, 0x1fa90,
2285 		0x1fac0, 0x1fac0,
2286 		0x1fae0, 0x1fae0,
2287 		0x1fb00, 0x1fb84,
2288 		0x1fbc0, 0x1fbc8,
2289 		0x1fc08, 0x1fc0c,
2290 		0x1fc40, 0x1fc44,
2291 		0x1fc4c, 0x1fc4c,
2292 		0x1fe84, 0x1fe90,
2293 		0x1fec0, 0x1fec0,
2294 		0x1fee0, 0x1fee0,
2295 		0x1ff00, 0x1ff84,
2296 		0x1ffc0, 0x1ffc8,
2297 		0x30000, 0x30030,
2298 		0x30100, 0x30168,
2299 		0x30190, 0x301a0,
2300 		0x301a8, 0x301b8,
2301 		0x301c4, 0x301c8,
2302 		0x301d0, 0x301d0,
2303 		0x30200, 0x30320,
2304 		0x30400, 0x304b4,
2305 		0x304c0, 0x3052c,
2306 		0x30540, 0x3061c,
2307 		0x30800, 0x308a0,
2308 		0x308c0, 0x30908,
2309 		0x30910, 0x309b8,
2310 		0x30a00, 0x30a04,
2311 		0x30a0c, 0x30a14,
2312 		0x30a1c, 0x30a2c,
2313 		0x30a44, 0x30a50,
2314 		0x30a74, 0x30a74,
2315 		0x30a7c, 0x30afc,
2316 		0x30b08, 0x30c24,
2317 		0x30d00, 0x30d14,
2318 		0x30d1c, 0x30d3c,
2319 		0x30d44, 0x30d4c,
2320 		0x30d54, 0x30d74,
2321 		0x30d7c, 0x30d7c,
2322 		0x30de0, 0x30de0,
2323 		0x30e00, 0x30ed4,
2324 		0x30f00, 0x30fa4,
2325 		0x30fc0, 0x30fc4,
2326 		0x31000, 0x31004,
2327 		0x31080, 0x310fc,
2328 		0x31208, 0x31220,
2329 		0x3123c, 0x31254,
2330 		0x31300, 0x31300,
2331 		0x31308, 0x3131c,
2332 		0x31338, 0x3133c,
2333 		0x31380, 0x31380,
2334 		0x31388, 0x313a8,
2335 		0x313b4, 0x313b4,
2336 		0x31400, 0x31420,
2337 		0x31438, 0x3143c,
2338 		0x31480, 0x31480,
2339 		0x314a8, 0x314a8,
2340 		0x314b0, 0x314b4,
2341 		0x314c8, 0x314d4,
2342 		0x31a40, 0x31a4c,
2343 		0x31af0, 0x31b20,
2344 		0x31b38, 0x31b3c,
2345 		0x31b80, 0x31b80,
2346 		0x31ba8, 0x31ba8,
2347 		0x31bb0, 0x31bb4,
2348 		0x31bc8, 0x31bd4,
2349 		0x32140, 0x3218c,
2350 		0x321f0, 0x321f4,
2351 		0x32200, 0x32200,
2352 		0x32218, 0x32218,
2353 		0x32400, 0x32400,
2354 		0x32408, 0x3241c,
2355 		0x32618, 0x32620,
2356 		0x32664, 0x32664,
2357 		0x326a8, 0x326a8,
2358 		0x326ec, 0x326ec,
2359 		0x32a00, 0x32abc,
2360 		0x32b00, 0x32b18,
2361 		0x32b20, 0x32b38,
2362 		0x32b40, 0x32b58,
2363 		0x32b60, 0x32b78,
2364 		0x32c00, 0x32c00,
2365 		0x32c08, 0x32c3c,
2366 		0x33000, 0x3302c,
2367 		0x33034, 0x33050,
2368 		0x33058, 0x33058,
2369 		0x33060, 0x3308c,
2370 		0x3309c, 0x330ac,
2371 		0x330c0, 0x330c0,
2372 		0x330c8, 0x330d0,
2373 		0x330d8, 0x330e0,
2374 		0x330ec, 0x3312c,
2375 		0x33134, 0x33150,
2376 		0x33158, 0x33158,
2377 		0x33160, 0x3318c,
2378 		0x3319c, 0x331ac,
2379 		0x331c0, 0x331c0,
2380 		0x331c8, 0x331d0,
2381 		0x331d8, 0x331e0,
2382 		0x331ec, 0x33290,
2383 		0x33298, 0x332c4,
2384 		0x332e4, 0x33390,
2385 		0x33398, 0x333c4,
2386 		0x333e4, 0x3342c,
2387 		0x33434, 0x33450,
2388 		0x33458, 0x33458,
2389 		0x33460, 0x3348c,
2390 		0x3349c, 0x334ac,
2391 		0x334c0, 0x334c0,
2392 		0x334c8, 0x334d0,
2393 		0x334d8, 0x334e0,
2394 		0x334ec, 0x3352c,
2395 		0x33534, 0x33550,
2396 		0x33558, 0x33558,
2397 		0x33560, 0x3358c,
2398 		0x3359c, 0x335ac,
2399 		0x335c0, 0x335c0,
2400 		0x335c8, 0x335d0,
2401 		0x335d8, 0x335e0,
2402 		0x335ec, 0x33690,
2403 		0x33698, 0x336c4,
2404 		0x336e4, 0x33790,
2405 		0x33798, 0x337c4,
2406 		0x337e4, 0x337fc,
2407 		0x33814, 0x33814,
2408 		0x33854, 0x33868,
2409 		0x33880, 0x3388c,
2410 		0x338c0, 0x338d0,
2411 		0x338e8, 0x338ec,
2412 		0x33900, 0x3392c,
2413 		0x33934, 0x33950,
2414 		0x33958, 0x33958,
2415 		0x33960, 0x3398c,
2416 		0x3399c, 0x339ac,
2417 		0x339c0, 0x339c0,
2418 		0x339c8, 0x339d0,
2419 		0x339d8, 0x339e0,
2420 		0x339ec, 0x33a90,
2421 		0x33a98, 0x33ac4,
2422 		0x33ae4, 0x33b10,
2423 		0x33b24, 0x33b28,
2424 		0x33b38, 0x33b50,
2425 		0x33bf0, 0x33c10,
2426 		0x33c24, 0x33c28,
2427 		0x33c38, 0x33c50,
2428 		0x33cf0, 0x33cfc,
2429 		0x34000, 0x34030,
2430 		0x34100, 0x34168,
2431 		0x34190, 0x341a0,
2432 		0x341a8, 0x341b8,
2433 		0x341c4, 0x341c8,
2434 		0x341d0, 0x341d0,
2435 		0x34200, 0x34320,
2436 		0x34400, 0x344b4,
2437 		0x344c0, 0x3452c,
2438 		0x34540, 0x3461c,
2439 		0x34800, 0x348a0,
2440 		0x348c0, 0x34908,
2441 		0x34910, 0x349b8,
2442 		0x34a00, 0x34a04,
2443 		0x34a0c, 0x34a14,
2444 		0x34a1c, 0x34a2c,
2445 		0x34a44, 0x34a50,
2446 		0x34a74, 0x34a74,
2447 		0x34a7c, 0x34afc,
2448 		0x34b08, 0x34c24,
2449 		0x34d00, 0x34d14,
2450 		0x34d1c, 0x34d3c,
2451 		0x34d44, 0x34d4c,
2452 		0x34d54, 0x34d74,
2453 		0x34d7c, 0x34d7c,
2454 		0x34de0, 0x34de0,
2455 		0x34e00, 0x34ed4,
2456 		0x34f00, 0x34fa4,
2457 		0x34fc0, 0x34fc4,
2458 		0x35000, 0x35004,
2459 		0x35080, 0x350fc,
2460 		0x35208, 0x35220,
2461 		0x3523c, 0x35254,
2462 		0x35300, 0x35300,
2463 		0x35308, 0x3531c,
2464 		0x35338, 0x3533c,
2465 		0x35380, 0x35380,
2466 		0x35388, 0x353a8,
2467 		0x353b4, 0x353b4,
2468 		0x35400, 0x35420,
2469 		0x35438, 0x3543c,
2470 		0x35480, 0x35480,
2471 		0x354a8, 0x354a8,
2472 		0x354b0, 0x354b4,
2473 		0x354c8, 0x354d4,
2474 		0x35a40, 0x35a4c,
2475 		0x35af0, 0x35b20,
2476 		0x35b38, 0x35b3c,
2477 		0x35b80, 0x35b80,
2478 		0x35ba8, 0x35ba8,
2479 		0x35bb0, 0x35bb4,
2480 		0x35bc8, 0x35bd4,
2481 		0x36140, 0x3618c,
2482 		0x361f0, 0x361f4,
2483 		0x36200, 0x36200,
2484 		0x36218, 0x36218,
2485 		0x36400, 0x36400,
2486 		0x36408, 0x3641c,
2487 		0x36618, 0x36620,
2488 		0x36664, 0x36664,
2489 		0x366a8, 0x366a8,
2490 		0x366ec, 0x366ec,
2491 		0x36a00, 0x36abc,
2492 		0x36b00, 0x36b18,
2493 		0x36b20, 0x36b38,
2494 		0x36b40, 0x36b58,
2495 		0x36b60, 0x36b78,
2496 		0x36c00, 0x36c00,
2497 		0x36c08, 0x36c3c,
2498 		0x37000, 0x3702c,
2499 		0x37034, 0x37050,
2500 		0x37058, 0x37058,
2501 		0x37060, 0x3708c,
2502 		0x3709c, 0x370ac,
2503 		0x370c0, 0x370c0,
2504 		0x370c8, 0x370d0,
2505 		0x370d8, 0x370e0,
2506 		0x370ec, 0x3712c,
2507 		0x37134, 0x37150,
2508 		0x37158, 0x37158,
2509 		0x37160, 0x3718c,
2510 		0x3719c, 0x371ac,
2511 		0x371c0, 0x371c0,
2512 		0x371c8, 0x371d0,
2513 		0x371d8, 0x371e0,
2514 		0x371ec, 0x37290,
2515 		0x37298, 0x372c4,
2516 		0x372e4, 0x37390,
2517 		0x37398, 0x373c4,
2518 		0x373e4, 0x3742c,
2519 		0x37434, 0x37450,
2520 		0x37458, 0x37458,
2521 		0x37460, 0x3748c,
2522 		0x3749c, 0x374ac,
2523 		0x374c0, 0x374c0,
2524 		0x374c8, 0x374d0,
2525 		0x374d8, 0x374e0,
2526 		0x374ec, 0x3752c,
2527 		0x37534, 0x37550,
2528 		0x37558, 0x37558,
2529 		0x37560, 0x3758c,
2530 		0x3759c, 0x375ac,
2531 		0x375c0, 0x375c0,
2532 		0x375c8, 0x375d0,
2533 		0x375d8, 0x375e0,
2534 		0x375ec, 0x37690,
2535 		0x37698, 0x376c4,
2536 		0x376e4, 0x37790,
2537 		0x37798, 0x377c4,
2538 		0x377e4, 0x377fc,
2539 		0x37814, 0x37814,
2540 		0x37854, 0x37868,
2541 		0x37880, 0x3788c,
2542 		0x378c0, 0x378d0,
2543 		0x378e8, 0x378ec,
2544 		0x37900, 0x3792c,
2545 		0x37934, 0x37950,
2546 		0x37958, 0x37958,
2547 		0x37960, 0x3798c,
2548 		0x3799c, 0x379ac,
2549 		0x379c0, 0x379c0,
2550 		0x379c8, 0x379d0,
2551 		0x379d8, 0x379e0,
2552 		0x379ec, 0x37a90,
2553 		0x37a98, 0x37ac4,
2554 		0x37ae4, 0x37b10,
2555 		0x37b24, 0x37b28,
2556 		0x37b38, 0x37b50,
2557 		0x37bf0, 0x37c10,
2558 		0x37c24, 0x37c28,
2559 		0x37c38, 0x37c50,
2560 		0x37cf0, 0x37cfc,
2561 		0x40040, 0x40040,
2562 		0x40080, 0x40084,
2563 		0x40100, 0x40100,
2564 		0x40140, 0x401bc,
2565 		0x40200, 0x40214,
2566 		0x40228, 0x40228,
2567 		0x40240, 0x40258,
2568 		0x40280, 0x40280,
2569 		0x40304, 0x40304,
2570 		0x40330, 0x4033c,
2571 		0x41304, 0x413c8,
2572 		0x413d0, 0x413dc,
2573 		0x413f0, 0x413f0,
2574 		0x41400, 0x4140c,
2575 		0x41414, 0x4141c,
2576 		0x41480, 0x414d0,
2577 		0x44000, 0x4407c,
2578 		0x440c0, 0x441ac,
2579 		0x441b4, 0x4427c,
2580 		0x442c0, 0x443ac,
2581 		0x443b4, 0x4447c,
2582 		0x444c0, 0x445ac,
2583 		0x445b4, 0x4467c,
2584 		0x446c0, 0x447ac,
2585 		0x447b4, 0x4487c,
2586 		0x448c0, 0x449ac,
2587 		0x449b4, 0x44a7c,
2588 		0x44ac0, 0x44bac,
2589 		0x44bb4, 0x44c7c,
2590 		0x44cc0, 0x44dac,
2591 		0x44db4, 0x44e7c,
2592 		0x44ec0, 0x44fac,
2593 		0x44fb4, 0x4507c,
2594 		0x450c0, 0x451ac,
2595 		0x451b4, 0x451fc,
2596 		0x45800, 0x45804,
2597 		0x45810, 0x45830,
2598 		0x45840, 0x45860,
2599 		0x45868, 0x45868,
2600 		0x45880, 0x45884,
2601 		0x458a0, 0x458b0,
2602 		0x45a00, 0x45a04,
2603 		0x45a10, 0x45a30,
2604 		0x45a40, 0x45a60,
2605 		0x45a68, 0x45a68,
2606 		0x45a80, 0x45a84,
2607 		0x45aa0, 0x45ab0,
2608 		0x460c0, 0x460e4,
2609 		0x47000, 0x4703c,
2610 		0x47044, 0x4708c,
2611 		0x47200, 0x47250,
2612 		0x47400, 0x47408,
2613 		0x47414, 0x47420,
2614 		0x47600, 0x47618,
2615 		0x47800, 0x47814,
2616 		0x47820, 0x4782c,
2617 		0x50000, 0x50084,
2618 		0x50090, 0x500cc,
2619 		0x50300, 0x50384,
2620 		0x50400, 0x50400,
2621 		0x50800, 0x50884,
2622 		0x50890, 0x508cc,
2623 		0x50b00, 0x50b84,
2624 		0x50c00, 0x50c00,
2625 		0x51000, 0x51020,
2626 		0x51028, 0x510b0,
2627 		0x51300, 0x51324,
2628 	};
2629 
2630 	static const unsigned int t6vf_reg_ranges[] = {
2631 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2632 		VF_MPS_REG(A_MPS_VF_CTL),
2633 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2634 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2635 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2636 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2637 		FW_T6VF_MBDATA_BASE_ADDR,
2638 		FW_T6VF_MBDATA_BASE_ADDR +
2639 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2640 	};
2641 
2642 	u32 *buf_end = (u32 *)(buf + buf_size);
2643 	const unsigned int *reg_ranges;
2644 	int reg_ranges_size, range;
2645 	unsigned int chip_version = chip_id(adap);
2646 
2647 	/*
2648 	 * Select the right set of register ranges to dump depending on the
2649 	 * adapter chip type.
2650 	 */
2651 	switch (chip_version) {
2652 	case CHELSIO_T4:
2653 		if (adap->flags & IS_VF) {
2654 			reg_ranges = t4vf_reg_ranges;
2655 			reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2656 		} else {
2657 			reg_ranges = t4_reg_ranges;
2658 			reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2659 		}
2660 		break;
2661 
2662 	case CHELSIO_T5:
2663 		if (adap->flags & IS_VF) {
2664 			reg_ranges = t5vf_reg_ranges;
2665 			reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2666 		} else {
2667 			reg_ranges = t5_reg_ranges;
2668 			reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2669 		}
2670 		break;
2671 
2672 	case CHELSIO_T6:
2673 		if (adap->flags & IS_VF) {
2674 			reg_ranges = t6vf_reg_ranges;
2675 			reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2676 		} else {
2677 			reg_ranges = t6_reg_ranges;
2678 			reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2679 		}
2680 		break;
2681 
2682 	default:
2683 		CH_ERR(adap,
2684 			"Unsupported chip version %d\n", chip_version);
2685 		return;
2686 	}
2687 
2688 	/*
2689 	 * Clear the register buffer and insert the appropriate register
2690 	 * values selected by the above register ranges.
2691 	 */
2692 	memset(buf, 0, buf_size);
2693 	for (range = 0; range < reg_ranges_size; range += 2) {
2694 		unsigned int reg = reg_ranges[range];
2695 		unsigned int last_reg = reg_ranges[range + 1];
2696 		u32 *bufp = (u32 *)(buf + reg);
2697 
2698 		/*
2699 		 * Iterate across the register range filling in the register
2700 		 * buffer but don't write past the end of the register buffer.
2701 		 */
2702 		while (reg <= last_reg && bufp < buf_end) {
2703 			*bufp++ = t4_read_reg(adap, reg);
2704 			reg += sizeof(u32);
2705 		}
2706 	}
2707 }
2708 
2709 /*
2710  * Partial EEPROM Vital Product Data structure.  The VPD starts with one ID
2711  * header followed by one or more VPD-R sections, each with its own header.
2712  */
2713 struct t4_vpd_hdr {
2714 	u8  id_tag;
2715 	u8  id_len[2];
2716 	u8  id_data[ID_LEN];
2717 };
2718 
2719 struct t4_vpdr_hdr {
2720 	u8  vpdr_tag;
2721 	u8  vpdr_len[2];
2722 };
2723 
2724 /*
2725  * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2726  */
2727 #define EEPROM_DELAY		10		/* 10us per poll spin */
2728 #define EEPROM_MAX_POLL		5000		/* x 5000 == 50ms */
2729 
2730 #define EEPROM_STAT_ADDR	0x7bfc
2731 #define VPD_SIZE		0x800
2732 #define VPD_BASE		0x400
2733 #define VPD_BASE_OLD		0
2734 #define VPD_LEN			1024
2735 #define VPD_INFO_FLD_HDR_SIZE	3
2736 #define CHELSIO_VPD_UNIQUE_ID	0x82
2737 
2738 /*
2739  * Small utility function to wait till any outstanding VPD Access is complete.
2740  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2741  * VPD Access in flight.  This allows us to handle the problem of having a
2742  * previous VPD Access time out and prevent an attempt to inject a new VPD
2743  * Request before any in-flight VPD reguest has completed.
2744  */
2745 static int t4_seeprom_wait(struct adapter *adapter)
2746 {
2747 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2748 	int max_poll;
2749 
2750 	/*
2751 	 * If no VPD Access is in flight, we can just return success right
2752 	 * away.
2753 	 */
2754 	if (!adapter->vpd_busy)
2755 		return 0;
2756 
2757 	/*
2758 	 * Poll the VPD Capability Address/Flag register waiting for it
2759 	 * to indicate that the operation is complete.
2760 	 */
2761 	max_poll = EEPROM_MAX_POLL;
2762 	do {
2763 		u16 val;
2764 
2765 		udelay(EEPROM_DELAY);
2766 		t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2767 
2768 		/*
2769 		 * If the operation is complete, mark the VPD as no longer
2770 		 * busy and return success.
2771 		 */
2772 		if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2773 			adapter->vpd_busy = 0;
2774 			return 0;
2775 		}
2776 	} while (--max_poll);
2777 
2778 	/*
2779 	 * Failure!  Note that we leave the VPD Busy status set in order to
2780 	 * avoid pushing a new VPD Access request into the VPD Capability till
2781 	 * the current operation eventually succeeds.  It's a bug to issue a
2782 	 * new request when an existing request is in flight and will result
2783 	 * in corrupt hardware state.
2784 	 */
2785 	return -ETIMEDOUT;
2786 }
2787 
2788 /**
2789  *	t4_seeprom_read - read a serial EEPROM location
2790  *	@adapter: adapter to read
2791  *	@addr: EEPROM virtual address
2792  *	@data: where to store the read data
2793  *
2794  *	Read a 32-bit word from a location in serial EEPROM using the card's PCI
2795  *	VPD capability.  Note that this function must be called with a virtual
2796  *	address.
2797  */
2798 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2799 {
2800 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2801 	int ret;
2802 
2803 	/*
2804 	 * VPD Accesses must alway be 4-byte aligned!
2805 	 */
2806 	if (addr >= EEPROMVSIZE || (addr & 3))
2807 		return -EINVAL;
2808 
2809 	/*
2810 	 * Wait for any previous operation which may still be in flight to
2811 	 * complete.
2812 	 */
2813 	ret = t4_seeprom_wait(adapter);
2814 	if (ret) {
2815 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2816 		return ret;
2817 	}
2818 
2819 	/*
2820 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2821 	 * for our request to complete.  If it doesn't complete, note the
2822 	 * error and return it to our caller.  Note that we do not reset the
2823 	 * VPD Busy status!
2824 	 */
2825 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2826 	adapter->vpd_busy = 1;
2827 	adapter->vpd_flag = PCI_VPD_ADDR_F;
2828 	ret = t4_seeprom_wait(adapter);
2829 	if (ret) {
2830 		CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2831 		return ret;
2832 	}
2833 
2834 	/*
2835 	 * Grab the returned data, swizzle it into our endianness and
2836 	 * return success.
2837 	 */
2838 	t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2839 	*data = le32_to_cpu(*data);
2840 	return 0;
2841 }
2842 
2843 /**
2844  *	t4_seeprom_write - write a serial EEPROM location
2845  *	@adapter: adapter to write
2846  *	@addr: virtual EEPROM address
2847  *	@data: value to write
2848  *
2849  *	Write a 32-bit word to a location in serial EEPROM using the card's PCI
2850  *	VPD capability.  Note that this function must be called with a virtual
2851  *	address.
2852  */
2853 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2854 {
2855 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2856 	int ret;
2857 	u32 stats_reg;
2858 	int max_poll;
2859 
2860 	/*
2861 	 * VPD Accesses must alway be 4-byte aligned!
2862 	 */
2863 	if (addr >= EEPROMVSIZE || (addr & 3))
2864 		return -EINVAL;
2865 
2866 	/*
2867 	 * Wait for any previous operation which may still be in flight to
2868 	 * complete.
2869 	 */
2870 	ret = t4_seeprom_wait(adapter);
2871 	if (ret) {
2872 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2873 		return ret;
2874 	}
2875 
2876 	/*
2877 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2878 	 * for our request to complete.  If it doesn't complete, note the
2879 	 * error and return it to our caller.  Note that we do not reset the
2880 	 * VPD Busy status!
2881 	 */
2882 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2883 				 cpu_to_le32(data));
2884 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2885 				 (u16)addr | PCI_VPD_ADDR_F);
2886 	adapter->vpd_busy = 1;
2887 	adapter->vpd_flag = 0;
2888 	ret = t4_seeprom_wait(adapter);
2889 	if (ret) {
2890 		CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2891 		return ret;
2892 	}
2893 
2894 	/*
2895 	 * Reset PCI_VPD_DATA register after a transaction and wait for our
2896 	 * request to complete. If it doesn't complete, return error.
2897 	 */
2898 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2899 	max_poll = EEPROM_MAX_POLL;
2900 	do {
2901 		udelay(EEPROM_DELAY);
2902 		t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2903 	} while ((stats_reg & 0x1) && --max_poll);
2904 	if (!max_poll)
2905 		return -ETIMEDOUT;
2906 
2907 	/* Return success! */
2908 	return 0;
2909 }
2910 
2911 /**
2912  *	t4_eeprom_ptov - translate a physical EEPROM address to virtual
2913  *	@phys_addr: the physical EEPROM address
2914  *	@fn: the PCI function number
2915  *	@sz: size of function-specific area
2916  *
2917  *	Translate a physical EEPROM address to virtual.  The first 1K is
2918  *	accessed through virtual addresses starting at 31K, the rest is
2919  *	accessed through virtual addresses starting at 0.
2920  *
2921  *	The mapping is as follows:
2922  *	[0..1K) -> [31K..32K)
2923  *	[1K..1K+A) -> [ES-A..ES)
2924  *	[1K+A..ES) -> [0..ES-A-1K)
2925  *
2926  *	where A = @fn * @sz, and ES = EEPROM size.
2927  */
2928 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2929 {
2930 	fn *= sz;
2931 	if (phys_addr < 1024)
2932 		return phys_addr + (31 << 10);
2933 	if (phys_addr < 1024 + fn)
2934 		return EEPROMSIZE - fn + phys_addr - 1024;
2935 	if (phys_addr < EEPROMSIZE)
2936 		return phys_addr - 1024 - fn;
2937 	return -EINVAL;
2938 }
2939 
2940 /**
2941  *	t4_seeprom_wp - enable/disable EEPROM write protection
2942  *	@adapter: the adapter
2943  *	@enable: whether to enable or disable write protection
2944  *
2945  *	Enables or disables write protection on the serial EEPROM.
2946  */
2947 int t4_seeprom_wp(struct adapter *adapter, int enable)
2948 {
2949 	return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2950 }
2951 
2952 /**
2953  *	get_vpd_keyword_val - Locates an information field keyword in the VPD
2954  *	@vpd: Pointer to buffered vpd data structure
2955  *	@kw: The keyword to search for
2956  *	@region: VPD region to search (starting from 0)
2957  *
2958  *	Returns the value of the information field keyword or
2959  *	-ENOENT otherwise.
2960  */
2961 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region)
2962 {
2963 	int i, tag;
2964 	unsigned int offset, len;
2965 	const struct t4_vpdr_hdr *vpdr;
2966 
2967 	offset = sizeof(struct t4_vpd_hdr);
2968 	vpdr = (const void *)(vpd + offset);
2969 	tag = vpdr->vpdr_tag;
2970 	len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2971 	while (region--) {
2972 		offset += sizeof(struct t4_vpdr_hdr) + len;
2973 		vpdr = (const void *)(vpd + offset);
2974 		if (++tag != vpdr->vpdr_tag)
2975 			return -ENOENT;
2976 		len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8);
2977 	}
2978 	offset += sizeof(struct t4_vpdr_hdr);
2979 
2980 	if (offset + len > VPD_LEN) {
2981 		return -ENOENT;
2982 	}
2983 
2984 	for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2985 		if (memcmp(vpd + i , kw , 2) == 0){
2986 			i += VPD_INFO_FLD_HDR_SIZE;
2987 			return i;
2988 		}
2989 
2990 		i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2];
2991 	}
2992 
2993 	return -ENOENT;
2994 }
2995 
2996 
2997 /**
2998  *	get_vpd_params - read VPD parameters from VPD EEPROM
2999  *	@adapter: adapter to read
3000  *	@p: where to store the parameters
3001  *	@vpd: caller provided temporary space to read the VPD into
3002  *
3003  *	Reads card parameters stored in VPD EEPROM.
3004  */
3005 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
3006     uint16_t device_id, u32 *buf)
3007 {
3008 	int i, ret, addr;
3009 	int ec, sn, pn, na, md;
3010 	u8 csum;
3011 	const u8 *vpd = (const u8 *)buf;
3012 
3013 	/*
3014 	 * Card information normally starts at VPD_BASE but early cards had
3015 	 * it at 0.
3016 	 */
3017 	ret = t4_seeprom_read(adapter, VPD_BASE, buf);
3018 	if (ret)
3019 		return (ret);
3020 
3021 	/*
3022 	 * The VPD shall have a unique identifier specified by the PCI SIG.
3023 	 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
3024 	 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
3025 	 * is expected to automatically put this entry at the
3026 	 * beginning of the VPD.
3027 	 */
3028 	addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
3029 
3030 	for (i = 0; i < VPD_LEN; i += 4) {
3031 		ret = t4_seeprom_read(adapter, addr + i, buf++);
3032 		if (ret)
3033 			return ret;
3034 	}
3035 
3036 #define FIND_VPD_KW(var,name) do { \
3037 	var = get_vpd_keyword_val(vpd, name, 0); \
3038 	if (var < 0) { \
3039 		CH_ERR(adapter, "missing VPD keyword " name "\n"); \
3040 		return -EINVAL; \
3041 	} \
3042 } while (0)
3043 
3044 	FIND_VPD_KW(i, "RV");
3045 	for (csum = 0; i >= 0; i--)
3046 		csum += vpd[i];
3047 
3048 	if (csum) {
3049 		CH_ERR(adapter,
3050 			"corrupted VPD EEPROM, actual csum %u\n", csum);
3051 		return -EINVAL;
3052 	}
3053 
3054 	FIND_VPD_KW(ec, "EC");
3055 	FIND_VPD_KW(sn, "SN");
3056 	FIND_VPD_KW(pn, "PN");
3057 	FIND_VPD_KW(na, "NA");
3058 #undef FIND_VPD_KW
3059 
3060 	memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN);
3061 	strstrip(p->id);
3062 	memcpy(p->ec, vpd + ec, EC_LEN);
3063 	strstrip(p->ec);
3064 	i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3065 	memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3066 	strstrip(p->sn);
3067 	i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3068 	memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3069 	strstrip((char *)p->pn);
3070 	i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3071 	memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3072 	strstrip((char *)p->na);
3073 
3074 	if (device_id & 0x80)
3075 		return 0;	/* Custom card */
3076 
3077 	md = get_vpd_keyword_val(vpd, "VF", 1);
3078 	if (md < 0) {
3079 		snprintf(p->md, sizeof(p->md), "unknown");
3080 	} else {
3081 		i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2];
3082 		memcpy(p->md, vpd + md, min(i, MD_LEN));
3083 		strstrip((char *)p->md);
3084 	}
3085 
3086 	return 0;
3087 }
3088 
3089 /* serial flash and firmware constants and flash config file constants */
3090 enum {
3091 	SF_ATTEMPTS = 10,	/* max retries for SF operations */
3092 
3093 	/* flash command opcodes */
3094 	SF_PROG_PAGE    = 2,	/* program 256B page */
3095 	SF_WR_DISABLE   = 4,	/* disable writes */
3096 	SF_RD_STATUS    = 5,	/* read status register */
3097 	SF_WR_ENABLE    = 6,	/* enable writes */
3098 	SF_RD_DATA_FAST = 0xb,	/* read flash */
3099 	SF_RD_ID	= 0x9f,	/* read ID */
3100 	SF_ERASE_SECTOR = 0xd8,	/* erase 64KB sector */
3101 };
3102 
3103 /**
3104  *	sf1_read - read data from the serial flash
3105  *	@adapter: the adapter
3106  *	@byte_cnt: number of bytes to read
3107  *	@cont: whether another operation will be chained
3108  *	@lock: whether to lock SF for PL access only
3109  *	@valp: where to store the read data
3110  *
3111  *	Reads up to 4 bytes of data from the serial flash.  The location of
3112  *	the read needs to be specified prior to calling this by issuing the
3113  *	appropriate commands to the serial flash.
3114  */
3115 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3116 		    int lock, u32 *valp)
3117 {
3118 	int ret;
3119 
3120 	if (!byte_cnt || byte_cnt > 4)
3121 		return -EINVAL;
3122 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3123 		return -EBUSY;
3124 	t4_write_reg(adapter, A_SF_OP,
3125 		     V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3126 	ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3127 	if (!ret)
3128 		*valp = t4_read_reg(adapter, A_SF_DATA);
3129 	return ret;
3130 }
3131 
3132 /**
3133  *	sf1_write - write data to the serial flash
3134  *	@adapter: the adapter
3135  *	@byte_cnt: number of bytes to write
3136  *	@cont: whether another operation will be chained
3137  *	@lock: whether to lock SF for PL access only
3138  *	@val: value to write
3139  *
3140  *	Writes up to 4 bytes of data to the serial flash.  The location of
3141  *	the write needs to be specified prior to calling this by issuing the
3142  *	appropriate commands to the serial flash.
3143  */
3144 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3145 		     int lock, u32 val)
3146 {
3147 	if (!byte_cnt || byte_cnt > 4)
3148 		return -EINVAL;
3149 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3150 		return -EBUSY;
3151 	t4_write_reg(adapter, A_SF_DATA, val);
3152 	t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3153 		     V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3154 	return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3155 }
3156 
3157 /**
3158  *	flash_wait_op - wait for a flash operation to complete
3159  *	@adapter: the adapter
3160  *	@attempts: max number of polls of the status register
3161  *	@delay: delay between polls in ms
3162  *
3163  *	Wait for a flash operation to complete by polling the status register.
3164  */
3165 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3166 {
3167 	int ret;
3168 	u32 status;
3169 
3170 	while (1) {
3171 		if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3172 		    (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3173 			return ret;
3174 		if (!(status & 1))
3175 			return 0;
3176 		if (--attempts == 0)
3177 			return -EAGAIN;
3178 		if (delay)
3179 			msleep(delay);
3180 	}
3181 }
3182 
3183 /**
3184  *	t4_read_flash - read words from serial flash
3185  *	@adapter: the adapter
3186  *	@addr: the start address for the read
3187  *	@nwords: how many 32-bit words to read
3188  *	@data: where to store the read data
3189  *	@byte_oriented: whether to store data as bytes or as words
3190  *
3191  *	Read the specified number of 32-bit words from the serial flash.
3192  *	If @byte_oriented is set the read data is stored as a byte array
3193  *	(i.e., big-endian), otherwise as 32-bit words in the platform's
3194  *	natural endianness.
3195  */
3196 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3197 		  unsigned int nwords, u32 *data, int byte_oriented)
3198 {
3199 	int ret;
3200 
3201 	if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3202 		return -EINVAL;
3203 
3204 	addr = swab32(addr) | SF_RD_DATA_FAST;
3205 
3206 	if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3207 	    (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3208 		return ret;
3209 
3210 	for ( ; nwords; nwords--, data++) {
3211 		ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3212 		if (nwords == 1)
3213 			t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3214 		if (ret)
3215 			return ret;
3216 		if (byte_oriented)
3217 			*data = (__force __u32)(cpu_to_be32(*data));
3218 	}
3219 	return 0;
3220 }
3221 
3222 /**
3223  *	t4_write_flash - write up to a page of data to the serial flash
3224  *	@adapter: the adapter
3225  *	@addr: the start address to write
3226  *	@n: length of data to write in bytes
3227  *	@data: the data to write
3228  *	@byte_oriented: whether to store data as bytes or as words
3229  *
3230  *	Writes up to a page of data (256 bytes) to the serial flash starting
3231  *	at the given address.  All the data must be written to the same page.
3232  *	If @byte_oriented is set the write data is stored as byte stream
3233  *	(i.e. matches what on disk), otherwise in big-endian.
3234  */
3235 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3236 			  unsigned int n, const u8 *data, int byte_oriented)
3237 {
3238 	int ret;
3239 	u32 buf[SF_PAGE_SIZE / 4];
3240 	unsigned int i, c, left, val, offset = addr & 0xff;
3241 
3242 	if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3243 		return -EINVAL;
3244 
3245 	val = swab32(addr) | SF_PROG_PAGE;
3246 
3247 	if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3248 	    (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3249 		goto unlock;
3250 
3251 	for (left = n; left; left -= c) {
3252 		c = min(left, 4U);
3253 		for (val = 0, i = 0; i < c; ++i)
3254 			val = (val << 8) + *data++;
3255 
3256 		if (!byte_oriented)
3257 			val = cpu_to_be32(val);
3258 
3259 		ret = sf1_write(adapter, c, c != left, 1, val);
3260 		if (ret)
3261 			goto unlock;
3262 	}
3263 	ret = flash_wait_op(adapter, 8, 1);
3264 	if (ret)
3265 		goto unlock;
3266 
3267 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3268 
3269 	/* Read the page to verify the write succeeded */
3270 	ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3271 			    byte_oriented);
3272 	if (ret)
3273 		return ret;
3274 
3275 	if (memcmp(data - n, (u8 *)buf + offset, n)) {
3276 		CH_ERR(adapter,
3277 			"failed to correctly write the flash page at %#x\n",
3278 			addr);
3279 		return -EIO;
3280 	}
3281 	return 0;
3282 
3283 unlock:
3284 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3285 	return ret;
3286 }
3287 
3288 /**
3289  *	t4_get_fw_version - read the firmware version
3290  *	@adapter: the adapter
3291  *	@vers: where to place the version
3292  *
3293  *	Reads the FW version from flash.
3294  */
3295 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3296 {
3297 	return t4_read_flash(adapter, FLASH_FW_START +
3298 			     offsetof(struct fw_hdr, fw_ver), 1,
3299 			     vers, 0);
3300 }
3301 
3302 /**
3303  *	t4_get_fw_hdr - read the firmware header
3304  *	@adapter: the adapter
3305  *	@hdr: where to place the version
3306  *
3307  *	Reads the FW header from flash into caller provided buffer.
3308  */
3309 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr)
3310 {
3311 	return t4_read_flash(adapter, FLASH_FW_START,
3312 	    sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1);
3313 }
3314 
3315 /**
3316  *	t4_get_bs_version - read the firmware bootstrap version
3317  *	@adapter: the adapter
3318  *	@vers: where to place the version
3319  *
3320  *	Reads the FW Bootstrap version from flash.
3321  */
3322 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3323 {
3324 	return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3325 			     offsetof(struct fw_hdr, fw_ver), 1,
3326 			     vers, 0);
3327 }
3328 
3329 /**
3330  *	t4_get_tp_version - read the TP microcode version
3331  *	@adapter: the adapter
3332  *	@vers: where to place the version
3333  *
3334  *	Reads the TP microcode version from flash.
3335  */
3336 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3337 {
3338 	return t4_read_flash(adapter, FLASH_FW_START +
3339 			     offsetof(struct fw_hdr, tp_microcode_ver),
3340 			     1, vers, 0);
3341 }
3342 
3343 /**
3344  *	t4_get_exprom_version - return the Expansion ROM version (if any)
3345  *	@adapter: the adapter
3346  *	@vers: where to place the version
3347  *
3348  *	Reads the Expansion ROM header from FLASH and returns the version
3349  *	number (if present) through the @vers return value pointer.  We return
3350  *	this in the Firmware Version Format since it's convenient.  Return
3351  *	0 on success, -ENOENT if no Expansion ROM is present.
3352  */
3353 int t4_get_exprom_version(struct adapter *adapter, u32 *vers)
3354 {
3355 	struct exprom_header {
3356 		unsigned char hdr_arr[16];	/* must start with 0x55aa */
3357 		unsigned char hdr_ver[4];	/* Expansion ROM version */
3358 	} *hdr;
3359 	u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3360 					   sizeof(u32))];
3361 	int ret;
3362 
3363 	ret = t4_read_flash(adapter, FLASH_EXP_ROM_START,
3364 			    ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3365 			    0);
3366 	if (ret)
3367 		return ret;
3368 
3369 	hdr = (struct exprom_header *)exprom_header_buf;
3370 	if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3371 		return -ENOENT;
3372 
3373 	*vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3374 		 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3375 		 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3376 		 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3377 	return 0;
3378 }
3379 
3380 /**
3381  *	t4_get_scfg_version - return the Serial Configuration version
3382  *	@adapter: the adapter
3383  *	@vers: where to place the version
3384  *
3385  *	Reads the Serial Configuration Version via the Firmware interface
3386  *	(thus this can only be called once we're ready to issue Firmware
3387  *	commands).  The format of the Serial Configuration version is
3388  *	adapter specific.  Returns 0 on success, an error on failure.
3389  *
3390  *	Note that early versions of the Firmware didn't include the ability
3391  *	to retrieve the Serial Configuration version, so we zero-out the
3392  *	return-value parameter in that case to avoid leaving it with
3393  *	garbage in it.
3394  *
3395  *	Also note that the Firmware will return its cached copy of the Serial
3396  *	Initialization Revision ID, not the actual Revision ID as written in
3397  *	the Serial EEPROM.  This is only an issue if a new VPD has been written
3398  *	and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3399  *	it's best to defer calling this routine till after a FW_RESET_CMD has
3400  *	been issued if the Host Driver will be performing a full adapter
3401  *	initialization.
3402  */
3403 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3404 {
3405 	u32 scfgrev_param;
3406 	int ret;
3407 
3408 	scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3409 			 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3410 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3411 			      1, &scfgrev_param, vers);
3412 	if (ret)
3413 		*vers = 0;
3414 	return ret;
3415 }
3416 
3417 /**
3418  *	t4_get_vpd_version - return the VPD version
3419  *	@adapter: the adapter
3420  *	@vers: where to place the version
3421  *
3422  *	Reads the VPD via the Firmware interface (thus this can only be called
3423  *	once we're ready to issue Firmware commands).  The format of the
3424  *	VPD version is adapter specific.  Returns 0 on success, an error on
3425  *	failure.
3426  *
3427  *	Note that early versions of the Firmware didn't include the ability
3428  *	to retrieve the VPD version, so we zero-out the return-value parameter
3429  *	in that case to avoid leaving it with garbage in it.
3430  *
3431  *	Also note that the Firmware will return its cached copy of the VPD
3432  *	Revision ID, not the actual Revision ID as written in the Serial
3433  *	EEPROM.  This is only an issue if a new VPD has been written and the
3434  *	Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3435  *	to defer calling this routine till after a FW_RESET_CMD has been issued
3436  *	if the Host Driver will be performing a full adapter initialization.
3437  */
3438 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3439 {
3440 	u32 vpdrev_param;
3441 	int ret;
3442 
3443 	vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3444 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3445 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3446 			      1, &vpdrev_param, vers);
3447 	if (ret)
3448 		*vers = 0;
3449 	return ret;
3450 }
3451 
3452 /**
3453  *	t4_get_version_info - extract various chip/firmware version information
3454  *	@adapter: the adapter
3455  *
3456  *	Reads various chip/firmware version numbers and stores them into the
3457  *	adapter Adapter Parameters structure.  If any of the efforts fails
3458  *	the first failure will be returned, but all of the version numbers
3459  *	will be read.
3460  */
3461 int t4_get_version_info(struct adapter *adapter)
3462 {
3463 	int ret = 0;
3464 
3465 	#define FIRST_RET(__getvinfo) \
3466 	do { \
3467 		int __ret = __getvinfo; \
3468 		if (__ret && !ret) \
3469 			ret = __ret; \
3470 	} while (0)
3471 
3472 	FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3473 	FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3474 	FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3475 	FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3476 	FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3477 	FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3478 
3479 	#undef FIRST_RET
3480 
3481 	return ret;
3482 }
3483 
3484 /**
3485  *	t4_flash_erase_sectors - erase a range of flash sectors
3486  *	@adapter: the adapter
3487  *	@start: the first sector to erase
3488  *	@end: the last sector to erase
3489  *
3490  *	Erases the sectors in the given inclusive range.
3491  */
3492 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3493 {
3494 	int ret = 0;
3495 
3496 	if (end >= adapter->params.sf_nsec)
3497 		return -EINVAL;
3498 
3499 	while (start <= end) {
3500 		if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3501 		    (ret = sf1_write(adapter, 4, 0, 1,
3502 				     SF_ERASE_SECTOR | (start << 8))) != 0 ||
3503 		    (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3504 			CH_ERR(adapter,
3505 				"erase of flash sector %d failed, error %d\n",
3506 				start, ret);
3507 			break;
3508 		}
3509 		start++;
3510 	}
3511 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3512 	return ret;
3513 }
3514 
3515 /**
3516  *	t4_flash_cfg_addr - return the address of the flash configuration file
3517  *	@adapter: the adapter
3518  *
3519  *	Return the address within the flash where the Firmware Configuration
3520  *	File is stored, or an error if the device FLASH is too small to contain
3521  *	a Firmware Configuration File.
3522  */
3523 int t4_flash_cfg_addr(struct adapter *adapter)
3524 {
3525 	/*
3526 	 * If the device FLASH isn't large enough to hold a Firmware
3527 	 * Configuration File, return an error.
3528 	 */
3529 	if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3530 		return -ENOSPC;
3531 
3532 	return FLASH_CFG_START;
3533 }
3534 
3535 /*
3536  * Return TRUE if the specified firmware matches the adapter.  I.e. T4
3537  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3538  * and emit an error message for mismatched firmware to save our caller the
3539  * effort ...
3540  */
3541 static int t4_fw_matches_chip(struct adapter *adap,
3542 			      const struct fw_hdr *hdr)
3543 {
3544 	/*
3545 	 * The expression below will return FALSE for any unsupported adapter
3546 	 * which will keep us "honest" in the future ...
3547 	 */
3548 	if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3549 	    (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3550 	    (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3551 		return 1;
3552 
3553 	CH_ERR(adap,
3554 		"FW image (%d) is not suitable for this adapter (%d)\n",
3555 		hdr->chip, chip_id(adap));
3556 	return 0;
3557 }
3558 
3559 /**
3560  *	t4_load_fw - download firmware
3561  *	@adap: the adapter
3562  *	@fw_data: the firmware image to write
3563  *	@size: image size
3564  *
3565  *	Write the supplied firmware image to the card's serial flash.
3566  */
3567 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3568 {
3569 	u32 csum;
3570 	int ret, addr;
3571 	unsigned int i;
3572 	u8 first_page[SF_PAGE_SIZE];
3573 	const u32 *p = (const u32 *)fw_data;
3574 	const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3575 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3576 	unsigned int fw_start_sec;
3577 	unsigned int fw_start;
3578 	unsigned int fw_size;
3579 
3580 	if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3581 		fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3582 		fw_start = FLASH_FWBOOTSTRAP_START;
3583 		fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3584 	} else {
3585 		fw_start_sec = FLASH_FW_START_SEC;
3586  		fw_start = FLASH_FW_START;
3587 		fw_size = FLASH_FW_MAX_SIZE;
3588 	}
3589 
3590 	if (!size) {
3591 		CH_ERR(adap, "FW image has no data\n");
3592 		return -EINVAL;
3593 	}
3594 	if (size & 511) {
3595 		CH_ERR(adap,
3596 			"FW image size not multiple of 512 bytes\n");
3597 		return -EINVAL;
3598 	}
3599 	if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3600 		CH_ERR(adap,
3601 			"FW image size differs from size in FW header\n");
3602 		return -EINVAL;
3603 	}
3604 	if (size > fw_size) {
3605 		CH_ERR(adap, "FW image too large, max is %u bytes\n",
3606 			fw_size);
3607 		return -EFBIG;
3608 	}
3609 	if (!t4_fw_matches_chip(adap, hdr))
3610 		return -EINVAL;
3611 
3612 	for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3613 		csum += be32_to_cpu(p[i]);
3614 
3615 	if (csum != 0xffffffff) {
3616 		CH_ERR(adap,
3617 			"corrupted firmware image, checksum %#x\n", csum);
3618 		return -EINVAL;
3619 	}
3620 
3621 	i = DIV_ROUND_UP(size, sf_sec_size);	/* # of sectors spanned */
3622 	ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3623 	if (ret)
3624 		goto out;
3625 
3626 	/*
3627 	 * We write the correct version at the end so the driver can see a bad
3628 	 * version if the FW write fails.  Start by writing a copy of the
3629 	 * first page with a bad version.
3630 	 */
3631 	memcpy(first_page, fw_data, SF_PAGE_SIZE);
3632 	((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3633 	ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3634 	if (ret)
3635 		goto out;
3636 
3637 	addr = fw_start;
3638 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3639 		addr += SF_PAGE_SIZE;
3640 		fw_data += SF_PAGE_SIZE;
3641 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3642 		if (ret)
3643 			goto out;
3644 	}
3645 
3646 	ret = t4_write_flash(adap,
3647 			     fw_start + offsetof(struct fw_hdr, fw_ver),
3648 			     sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3649 out:
3650 	if (ret)
3651 		CH_ERR(adap, "firmware download failed, error %d\n",
3652 			ret);
3653 	return ret;
3654 }
3655 
3656 /**
3657  *	t4_fwcache - firmware cache operation
3658  *	@adap: the adapter
3659  *	@op  : the operation (flush or flush and invalidate)
3660  */
3661 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3662 {
3663 	struct fw_params_cmd c;
3664 
3665 	memset(&c, 0, sizeof(c));
3666 	c.op_to_vfn =
3667 	    cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3668 			    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3669 				V_FW_PARAMS_CMD_PFN(adap->pf) |
3670 				V_FW_PARAMS_CMD_VFN(0));
3671 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3672 	c.param[0].mnem =
3673 	    cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3674 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3675 	c.param[0].val = (__force __be32)op;
3676 
3677 	return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3678 }
3679 
3680 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3681 			unsigned int *pif_req_wrptr,
3682 			unsigned int *pif_rsp_wrptr)
3683 {
3684 	int i, j;
3685 	u32 cfg, val, req, rsp;
3686 
3687 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3688 	if (cfg & F_LADBGEN)
3689 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3690 
3691 	val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3692 	req = G_POLADBGWRPTR(val);
3693 	rsp = G_PILADBGWRPTR(val);
3694 	if (pif_req_wrptr)
3695 		*pif_req_wrptr = req;
3696 	if (pif_rsp_wrptr)
3697 		*pif_rsp_wrptr = rsp;
3698 
3699 	for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3700 		for (j = 0; j < 6; j++) {
3701 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3702 				     V_PILADBGRDPTR(rsp));
3703 			*pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3704 			*pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3705 			req++;
3706 			rsp++;
3707 		}
3708 		req = (req + 2) & M_POLADBGRDPTR;
3709 		rsp = (rsp + 2) & M_PILADBGRDPTR;
3710 	}
3711 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3712 }
3713 
3714 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3715 {
3716 	u32 cfg;
3717 	int i, j, idx;
3718 
3719 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3720 	if (cfg & F_LADBGEN)
3721 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3722 
3723 	for (i = 0; i < CIM_MALA_SIZE; i++) {
3724 		for (j = 0; j < 5; j++) {
3725 			idx = 8 * i + j;
3726 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3727 				     V_PILADBGRDPTR(idx));
3728 			*ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3729 			*ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3730 		}
3731 	}
3732 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3733 }
3734 
3735 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3736 {
3737 	unsigned int i, j;
3738 
3739 	for (i = 0; i < 8; i++) {
3740 		u32 *p = la_buf + i;
3741 
3742 		t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3743 		j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3744 		t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3745 		for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3746 			*p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3747 	}
3748 }
3749 
3750 /**
3751  *	fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3752  *	@caps16: a 16-bit Port Capabilities value
3753  *
3754  *	Returns the equivalent 32-bit Port Capabilities value.
3755  */
3756 static uint32_t fwcaps16_to_caps32(uint16_t caps16)
3757 {
3758 	uint32_t caps32 = 0;
3759 
3760 	#define CAP16_TO_CAP32(__cap) \
3761 		do { \
3762 			if (caps16 & FW_PORT_CAP_##__cap) \
3763 				caps32 |= FW_PORT_CAP32_##__cap; \
3764 		} while (0)
3765 
3766 	CAP16_TO_CAP32(SPEED_100M);
3767 	CAP16_TO_CAP32(SPEED_1G);
3768 	CAP16_TO_CAP32(SPEED_25G);
3769 	CAP16_TO_CAP32(SPEED_10G);
3770 	CAP16_TO_CAP32(SPEED_40G);
3771 	CAP16_TO_CAP32(SPEED_100G);
3772 	CAP16_TO_CAP32(FC_RX);
3773 	CAP16_TO_CAP32(FC_TX);
3774 	CAP16_TO_CAP32(ANEG);
3775 	CAP16_TO_CAP32(FORCE_PAUSE);
3776 	CAP16_TO_CAP32(MDIAUTO);
3777 	CAP16_TO_CAP32(MDISTRAIGHT);
3778 	CAP16_TO_CAP32(FEC_RS);
3779 	CAP16_TO_CAP32(FEC_BASER_RS);
3780 	CAP16_TO_CAP32(802_3_PAUSE);
3781 	CAP16_TO_CAP32(802_3_ASM_DIR);
3782 
3783 	#undef CAP16_TO_CAP32
3784 
3785 	return caps32;
3786 }
3787 
3788 /**
3789  *	fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3790  *	@caps32: a 32-bit Port Capabilities value
3791  *
3792  *	Returns the equivalent 16-bit Port Capabilities value.  Note that
3793  *	not all 32-bit Port Capabilities can be represented in the 16-bit
3794  *	Port Capabilities and some fields/values may not make it.
3795  */
3796 static uint16_t fwcaps32_to_caps16(uint32_t caps32)
3797 {
3798 	uint16_t caps16 = 0;
3799 
3800 	#define CAP32_TO_CAP16(__cap) \
3801 		do { \
3802 			if (caps32 & FW_PORT_CAP32_##__cap) \
3803 				caps16 |= FW_PORT_CAP_##__cap; \
3804 		} while (0)
3805 
3806 	CAP32_TO_CAP16(SPEED_100M);
3807 	CAP32_TO_CAP16(SPEED_1G);
3808 	CAP32_TO_CAP16(SPEED_10G);
3809 	CAP32_TO_CAP16(SPEED_25G);
3810 	CAP32_TO_CAP16(SPEED_40G);
3811 	CAP32_TO_CAP16(SPEED_100G);
3812 	CAP32_TO_CAP16(FC_RX);
3813 	CAP32_TO_CAP16(FC_TX);
3814 	CAP32_TO_CAP16(802_3_PAUSE);
3815 	CAP32_TO_CAP16(802_3_ASM_DIR);
3816 	CAP32_TO_CAP16(ANEG);
3817 	CAP32_TO_CAP16(FORCE_PAUSE);
3818 	CAP32_TO_CAP16(MDIAUTO);
3819 	CAP32_TO_CAP16(MDISTRAIGHT);
3820 	CAP32_TO_CAP16(FEC_RS);
3821 	CAP32_TO_CAP16(FEC_BASER_RS);
3822 
3823 	#undef CAP32_TO_CAP16
3824 
3825 	return caps16;
3826 }
3827 
3828 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none)
3829 {
3830 	int8_t fec = 0;
3831 
3832 	if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0)
3833 		return (unset_means_none ? FEC_NONE : 0);
3834 
3835 	if (caps & FW_PORT_CAP32_FEC_RS)
3836 		fec |= FEC_RS;
3837 	if (caps & FW_PORT_CAP32_FEC_BASER_RS)
3838 		fec |= FEC_BASER_RS;
3839 	if (caps & FW_PORT_CAP32_FEC_NO_FEC)
3840 		fec |= FEC_NONE;
3841 
3842 	return (fec);
3843 }
3844 
3845 /*
3846  * Note that 0 is not translated to NO_FEC.
3847  */
3848 static uint32_t fec_to_fwcap(int8_t fec)
3849 {
3850 	uint32_t caps = 0;
3851 
3852 	/* Only real FECs allowed. */
3853 	MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0);
3854 
3855 	if (fec & FEC_RS)
3856 		caps |= FW_PORT_CAP32_FEC_RS;
3857 	if (fec & FEC_BASER_RS)
3858 		caps |= FW_PORT_CAP32_FEC_BASER_RS;
3859 	if (fec & FEC_NONE)
3860 		caps |= FW_PORT_CAP32_FEC_NO_FEC;
3861 
3862 	return (caps);
3863 }
3864 
3865 /**
3866  *	t4_link_l1cfg - apply link configuration to MAC/PHY
3867  *	@phy: the PHY to setup
3868  *	@mac: the MAC to setup
3869  *	@lc: the requested link configuration
3870  *
3871  *	Set up a port's MAC and PHY according to a desired link configuration.
3872  *	- If the PHY can auto-negotiate first decide what to advertise, then
3873  *	  enable/disable auto-negotiation as desired, and reset.
3874  *	- If the PHY does not auto-negotiate just reset it.
3875  *	- If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3876  *	  otherwise do it later based on the outcome of auto-negotiation.
3877  */
3878 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3879 		  struct link_config *lc)
3880 {
3881 	struct fw_port_cmd c;
3882 	unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO);
3883 	unsigned int aneg, fc, fec, speed, rcap;
3884 
3885 	fc = 0;
3886 	if (lc->requested_fc & PAUSE_RX)
3887 		fc |= FW_PORT_CAP32_FC_RX;
3888 	if (lc->requested_fc & PAUSE_TX)
3889 		fc |= FW_PORT_CAP32_FC_TX;
3890 	if (!(lc->requested_fc & PAUSE_AUTONEG))
3891 		fc |= FW_PORT_CAP32_FORCE_PAUSE;
3892 
3893 	if (lc->requested_aneg == AUTONEG_DISABLE)
3894 		aneg = 0;
3895 	else if (lc->requested_aneg == AUTONEG_ENABLE)
3896 		aneg = FW_PORT_CAP32_ANEG;
3897 	else
3898 		aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3899 
3900 	if (aneg) {
3901 		speed = lc->pcaps &
3902 		    V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED);
3903 	} else if (lc->requested_speed != 0)
3904 		speed = speed_to_fwcap(lc->requested_speed);
3905 	else
3906 		speed = fwcap_top_speed(lc->pcaps);
3907 
3908 	fec = 0;
3909 	if (fec_supported(speed)) {
3910 		int force_fec;
3911 
3912 		if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC)
3913 			force_fec = lc->force_fec;
3914 		else
3915 			force_fec = 0;
3916 
3917 		if (lc->requested_fec == FEC_AUTO) {
3918 			if (force_fec > 0) {
3919 				/*
3920 				 * Must use FORCE_FEC even though requested FEC
3921 				 * is AUTO. Set all the FEC bits valid for the
3922 				 * speed and let the firmware pick one.
3923 				 */
3924 				fec |= FW_PORT_CAP32_FORCE_FEC;
3925 				if (speed & FW_PORT_CAP32_SPEED_100G) {
3926 					fec |= FW_PORT_CAP32_FEC_RS;
3927 					fec |= FW_PORT_CAP32_FEC_NO_FEC;
3928 				} else if (speed & FW_PORT_CAP32_SPEED_50G) {
3929 					fec |= FW_PORT_CAP32_FEC_BASER_RS;
3930 					fec |= FW_PORT_CAP32_FEC_NO_FEC;
3931 				} else {
3932 					fec |= FW_PORT_CAP32_FEC_RS;
3933 					fec |= FW_PORT_CAP32_FEC_BASER_RS;
3934 					fec |= FW_PORT_CAP32_FEC_NO_FEC;
3935 				}
3936 			} else {
3937 				/*
3938 				 * Set only 1b. Old firmwares can't deal with
3939 				 * multiple bits and new firmwares are free to
3940 				 * ignore this and try whatever FECs they want
3941 				 * because we aren't setting FORCE_FEC here.
3942 				 */
3943 				fec |= fec_to_fwcap(lc->fec_hint);
3944 				MPASS(powerof2(fec));
3945 
3946 				/*
3947 				 * Override the hint if the FEC is not valid for
3948 				 * the potential top speed.  Request the best
3949 				 * FEC at that speed instead.
3950 				 */
3951 				if (speed & FW_PORT_CAP32_SPEED_100G) {
3952 					if (fec == FW_PORT_CAP32_FEC_BASER_RS)
3953 						fec = FW_PORT_CAP32_FEC_RS;
3954 				} else if (speed & FW_PORT_CAP32_SPEED_50G) {
3955 					if (fec == FW_PORT_CAP32_FEC_RS)
3956 						fec = FW_PORT_CAP32_FEC_BASER_RS;
3957 				}
3958 			}
3959 		} else {
3960 			/*
3961 			 * User has explicitly requested some FEC(s). Set
3962 			 * FORCE_FEC unless prohibited from using it.
3963 			 */
3964 			if (force_fec != 0)
3965 				fec |= FW_PORT_CAP32_FORCE_FEC;
3966 			fec |= fec_to_fwcap(lc->requested_fec &
3967 			    M_FW_PORT_CAP32_FEC);
3968 			if (lc->requested_fec & FEC_MODULE)
3969 				fec |= fec_to_fwcap(lc->fec_hint);
3970 		}
3971 
3972 		/*
3973 		 * This is for compatibility with old firmwares. The original
3974 		 * way to request NO_FEC was to not set any of the FEC bits. New
3975 		 * firmwares understand this too.
3976 		 */
3977 		if (fec == FW_PORT_CAP32_FEC_NO_FEC)
3978 			fec = 0;
3979 	}
3980 
3981 	/* Force AN on for BT cards. */
3982 	if (isset(&adap->bt_map, port))
3983 		aneg = lc->pcaps & FW_PORT_CAP32_ANEG;
3984 
3985 	rcap = aneg | speed | fc | fec;
3986 	if ((rcap | lc->pcaps) != lc->pcaps) {
3987 #ifdef INVARIANTS
3988 		CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap,
3989 		    lc->pcaps, rcap & (rcap ^ lc->pcaps));
3990 #endif
3991 		rcap &= lc->pcaps;
3992 	}
3993 	rcap |= mdi;
3994 
3995 	memset(&c, 0, sizeof(c));
3996 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3997 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3998 				     V_FW_PORT_CMD_PORTID(port));
3999 	if (adap->params.port_caps32) {
4000 		c.action_to_len16 =
4001 		    cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) |
4002 			FW_LEN16(c));
4003 		c.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4004 	} else {
4005 		c.action_to_len16 =
4006 		    cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
4007 			    FW_LEN16(c));
4008 		c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4009 	}
4010 
4011 	lc->requested_caps = rcap;
4012 	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
4013 }
4014 
4015 /**
4016  *	t4_restart_aneg - restart autonegotiation
4017  *	@adap: the adapter
4018  *	@mbox: mbox to use for the FW command
4019  *	@port: the port id
4020  *
4021  *	Restarts autonegotiation for the selected port.
4022  */
4023 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4024 {
4025 	struct fw_port_cmd c;
4026 
4027 	memset(&c, 0, sizeof(c));
4028 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
4029 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
4030 				     V_FW_PORT_CMD_PORTID(port));
4031 	c.action_to_len16 =
4032 		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
4033 			    FW_LEN16(c));
4034 	c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4035 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4036 }
4037 
4038 struct intr_details {
4039 	u32 mask;
4040 	const char *msg;
4041 };
4042 
4043 struct intr_action {
4044 	u32 mask;
4045 	int arg;
4046 	bool (*action)(struct adapter *, int, bool);
4047 };
4048 
4049 #define NONFATAL_IF_DISABLED 1
4050 struct intr_info {
4051 	const char *name;	/* name of the INT_CAUSE register */
4052 	int cause_reg;		/* INT_CAUSE register */
4053 	int enable_reg;		/* INT_ENABLE register */
4054 	u32 fatal;		/* bits that are fatal */
4055 	int flags;		/* hints */
4056 	const struct intr_details *details;
4057 	const struct intr_action *actions;
4058 };
4059 
4060 static inline char
4061 intr_alert_char(u32 cause, u32 enable, u32 fatal)
4062 {
4063 
4064 	if (cause & fatal)
4065 		return ('!');
4066 	if (cause & enable)
4067 		return ('*');
4068 	return ('-');
4069 }
4070 
4071 static void
4072 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause)
4073 {
4074 	u32 enable, fatal, leftover;
4075 	const struct intr_details *details;
4076 	char alert;
4077 
4078 	enable = t4_read_reg(adap, ii->enable_reg);
4079 	if (ii->flags & NONFATAL_IF_DISABLED)
4080 		fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg);
4081 	else
4082 		fatal = ii->fatal;
4083 	alert = intr_alert_char(cause, enable, fatal);
4084 	CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n",
4085 	    alert, ii->name, ii->cause_reg, cause, enable, fatal);
4086 
4087 	leftover = cause;
4088 	for (details = ii->details; details && details->mask != 0; details++) {
4089 		u32 msgbits = details->mask & cause;
4090 		if (msgbits == 0)
4091 			continue;
4092 		alert = intr_alert_char(msgbits, enable, ii->fatal);
4093 		CH_ALERT(adap, "  %c [0x%08x] %s\n", alert, msgbits,
4094 		    details->msg);
4095 		leftover &= ~msgbits;
4096 	}
4097 	if (leftover != 0 && leftover != cause)
4098 		CH_ALERT(adap, "  ? [0x%08x]\n", leftover);
4099 }
4100 
4101 /*
4102  * Returns true for fatal error.
4103  */
4104 static bool
4105 t4_handle_intr(struct adapter *adap, const struct intr_info *ii,
4106     u32 additional_cause, bool verbose)
4107 {
4108 	u32 cause, fatal;
4109 	bool rc;
4110 	const struct intr_action *action;
4111 
4112 	/*
4113 	 * Read and display cause.  Note that the top level PL_INT_CAUSE is a
4114 	 * bit special and we need to completely ignore the bits that are not in
4115 	 * PL_INT_ENABLE.
4116 	 */
4117 	cause = t4_read_reg(adap, ii->cause_reg);
4118 	if (ii->cause_reg == A_PL_INT_CAUSE)
4119 		cause &= t4_read_reg(adap, ii->enable_reg);
4120 	if (verbose || cause != 0)
4121 		t4_show_intr_info(adap, ii, cause);
4122 	fatal = cause & ii->fatal;
4123 	if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED)
4124 		fatal &= t4_read_reg(adap, ii->enable_reg);
4125 	cause |= additional_cause;
4126 	if (cause == 0)
4127 		return (false);
4128 
4129 	rc = fatal != 0;
4130 	for (action = ii->actions; action && action->mask != 0; action++) {
4131 		if (!(action->mask & cause))
4132 			continue;
4133 		rc |= (action->action)(adap, action->arg, verbose);
4134 	}
4135 
4136 	/* clear */
4137 	t4_write_reg(adap, ii->cause_reg, cause);
4138 	(void)t4_read_reg(adap, ii->cause_reg);
4139 
4140 	return (rc);
4141 }
4142 
4143 /*
4144  * Interrupt handler for the PCIE module.
4145  */
4146 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose)
4147 {
4148 	static const struct intr_details sysbus_intr_details[] = {
4149 		{ F_RNPP, "RXNP array parity error" },
4150 		{ F_RPCP, "RXPC array parity error" },
4151 		{ F_RCIP, "RXCIF array parity error" },
4152 		{ F_RCCP, "Rx completions control array parity error" },
4153 		{ F_RFTP, "RXFT array parity error" },
4154 		{ 0 }
4155 	};
4156 	static const struct intr_info sysbus_intr_info = {
4157 		.name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS",
4158 		.cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4159 		.enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE,
4160 		.fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP,
4161 		.flags = 0,
4162 		.details = sysbus_intr_details,
4163 		.actions = NULL,
4164 	};
4165 	static const struct intr_details pcie_port_intr_details[] = {
4166 		{ F_TPCP, "TXPC array parity error" },
4167 		{ F_TNPP, "TXNP array parity error" },
4168 		{ F_TFTP, "TXFT array parity error" },
4169 		{ F_TCAP, "TXCA array parity error" },
4170 		{ F_TCIP, "TXCIF array parity error" },
4171 		{ F_RCAP, "RXCA array parity error" },
4172 		{ F_OTDD, "outbound request TLP discarded" },
4173 		{ F_RDPE, "Rx data parity error" },
4174 		{ F_TDUE, "Tx uncorrectable data error" },
4175 		{ 0 }
4176 	};
4177 	static const struct intr_info pcie_port_intr_info = {
4178 		.name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS",
4179 		.cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4180 		.enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE,
4181 		.fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP |
4182 		    F_OTDD | F_RDPE | F_TDUE,
4183 		.flags = 0,
4184 		.details = pcie_port_intr_details,
4185 		.actions = NULL,
4186 	};
4187 	static const struct intr_details pcie_intr_details[] = {
4188 		{ F_MSIADDRLPERR, "MSI AddrL parity error" },
4189 		{ F_MSIADDRHPERR, "MSI AddrH parity error" },
4190 		{ F_MSIDATAPERR, "MSI data parity error" },
4191 		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error" },
4192 		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error" },
4193 		{ F_MSIXDATAPERR, "MSI-X data parity error" },
4194 		{ F_MSIXDIPERR, "MSI-X DI parity error" },
4195 		{ F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" },
4196 		{ F_PIOREQPERR, "PCIe PIO request FIFO parity error" },
4197 		{ F_TARTAGPERR, "PCIe target tag FIFO parity error" },
4198 		{ F_CCNTPERR, "PCIe CMD channel count parity error" },
4199 		{ F_CREQPERR, "PCIe CMD channel request parity error" },
4200 		{ F_CRSPPERR, "PCIe CMD channel response parity error" },
4201 		{ F_DCNTPERR, "PCIe DMA channel count parity error" },
4202 		{ F_DREQPERR, "PCIe DMA channel request parity error" },
4203 		{ F_DRSPPERR, "PCIe DMA channel response parity error" },
4204 		{ F_HCNTPERR, "PCIe HMA channel count parity error" },
4205 		{ F_HREQPERR, "PCIe HMA channel request parity error" },
4206 		{ F_HRSPPERR, "PCIe HMA channel response parity error" },
4207 		{ F_CFGSNPPERR, "PCIe config snoop FIFO parity error" },
4208 		{ F_FIDPERR, "PCIe FID parity error" },
4209 		{ F_INTXCLRPERR, "PCIe INTx clear parity error" },
4210 		{ F_MATAGPERR, "PCIe MA tag parity error" },
4211 		{ F_PIOTAGPERR, "PCIe PIO tag parity error" },
4212 		{ F_RXCPLPERR, "PCIe Rx completion parity error" },
4213 		{ F_RXWRPERR, "PCIe Rx write parity error" },
4214 		{ F_RPLPERR, "PCIe replay buffer parity error" },
4215 		{ F_PCIESINT, "PCIe core secondary fault" },
4216 		{ F_PCIEPINT, "PCIe core primary fault" },
4217 		{ F_UNXSPLCPLERR, "PCIe unexpected split completion error" },
4218 		{ 0 }
4219 	};
4220 	static const struct intr_details t5_pcie_intr_details[] = {
4221 		{ F_IPGRPPERR, "Parity errors observed by IP" },
4222 		{ F_NONFATALERR, "PCIe non-fatal error" },
4223 		{ F_READRSPERR, "Outbound read error" },
4224 		{ F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" },
4225 		{ F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" },
4226 		{ F_IPRETRYPERR, "PCIe IP replay buffer parity error" },
4227 		{ F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" },
4228 		{ F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" },
4229 		{ F_PIOTAGQPERR, "PIO tag queue FIFO parity error" },
4230 		{ F_MAGRPPERR, "MA group FIFO parity error" },
4231 		{ F_VFIDPERR, "VFID SRAM parity error" },
4232 		{ F_FIDPERR, "FID SRAM parity error" },
4233 		{ F_CFGSNPPERR, "config snoop FIFO parity error" },
4234 		{ F_HRSPPERR, "HMA channel response data SRAM parity error" },
4235 		{ F_HREQRDPERR, "HMA channel read request SRAM parity error" },
4236 		{ F_HREQWRPERR, "HMA channel write request SRAM parity error" },
4237 		{ F_DRSPPERR, "DMA channel response data SRAM parity error" },
4238 		{ F_DREQRDPERR, "DMA channel write request SRAM parity error" },
4239 		{ F_CRSPPERR, "CMD channel response data SRAM parity error" },
4240 		{ F_CREQRDPERR, "CMD channel read request SRAM parity error" },
4241 		{ F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" },
4242 		{ F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" },
4243 		{ F_PIOREQGRPPERR, "PIO request group FIFOs parity error" },
4244 		{ F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" },
4245 		{ F_MSIXDIPERR, "MSI-X DI SRAM parity error" },
4246 		{ F_MSIXDATAPERR, "MSI-X data SRAM parity error" },
4247 		{ F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" },
4248 		{ F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" },
4249 		{ F_MSIXSTIPERR, "MSI-X STI SRAM parity error" },
4250 		{ F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" },
4251 		{ F_MSTGRPPERR, "Master response read queue SRAM parity error" },
4252 		{ 0 }
4253 	};
4254 	struct intr_info pcie_intr_info = {
4255 		.name = "PCIE_INT_CAUSE",
4256 		.cause_reg = A_PCIE_INT_CAUSE,
4257 		.enable_reg = A_PCIE_INT_ENABLE,
4258 		.fatal = 0xffffffff,
4259 		.flags = NONFATAL_IF_DISABLED,
4260 		.details = NULL,
4261 		.actions = NULL,
4262 	};
4263 	bool fatal = false;
4264 
4265 	if (is_t4(adap)) {
4266 		fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose);
4267 		fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose);
4268 
4269 		pcie_intr_info.details = pcie_intr_details;
4270 	} else {
4271 		pcie_intr_info.details = t5_pcie_intr_details;
4272 	}
4273 	fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose);
4274 
4275 	return (fatal);
4276 }
4277 
4278 /*
4279  * TP interrupt handler.
4280  */
4281 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose)
4282 {
4283 	static const struct intr_details tp_intr_details[] = {
4284 		{ 0x3fffffff, "TP parity error" },
4285 		{ F_FLMTXFLSTEMPTY, "TP out of Tx pages" },
4286 		{ 0 }
4287 	};
4288 	static const struct intr_info tp_intr_info = {
4289 		.name = "TP_INT_CAUSE",
4290 		.cause_reg = A_TP_INT_CAUSE,
4291 		.enable_reg = A_TP_INT_ENABLE,
4292 		.fatal = 0x7fffffff,
4293 		.flags = NONFATAL_IF_DISABLED,
4294 		.details = tp_intr_details,
4295 		.actions = NULL,
4296 	};
4297 
4298 	return (t4_handle_intr(adap, &tp_intr_info, 0, verbose));
4299 }
4300 
4301 /*
4302  * SGE interrupt handler.
4303  */
4304 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose)
4305 {
4306 	static const struct intr_info sge_int1_info = {
4307 		.name = "SGE_INT_CAUSE1",
4308 		.cause_reg = A_SGE_INT_CAUSE1,
4309 		.enable_reg = A_SGE_INT_ENABLE1,
4310 		.fatal = 0xffffffff,
4311 		.flags = NONFATAL_IF_DISABLED,
4312 		.details = NULL,
4313 		.actions = NULL,
4314 	};
4315 	static const struct intr_info sge_int2_info = {
4316 		.name = "SGE_INT_CAUSE2",
4317 		.cause_reg = A_SGE_INT_CAUSE2,
4318 		.enable_reg = A_SGE_INT_ENABLE2,
4319 		.fatal = 0xffffffff,
4320 		.flags = NONFATAL_IF_DISABLED,
4321 		.details = NULL,
4322 		.actions = NULL,
4323 	};
4324 	static const struct intr_details sge_int3_details[] = {
4325 		{ F_ERR_FLM_DBP,
4326 			"DBP pointer delivery for invalid context or QID" },
4327 		{ F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4328 			"Invalid QID or header request by IDMA" },
4329 		{ F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4330 		{ F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4331 		{ F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4332 		{ F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4333 		{ F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4334 		{ F_ERR_TIMER_ABOVE_MAX_QID,
4335 			"SGE GTS with timer 0-5 for IQID > 1023" },
4336 		{ F_ERR_CPL_EXCEED_IQE_SIZE,
4337 			"SGE received CPL exceeding IQE size" },
4338 		{ F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4339 		{ F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4340 		{ F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4341 		{ F_ERR_DROPPED_DB, "SGE DB dropped" },
4342 		{ F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4343 		  "SGE IQID > 1023 received CPL for FL" },
4344 		{ F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4345 			F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4346 		{ F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4347 		{ F_ERR_ING_CTXT_PRIO,
4348 			"Ingress context manager priority user error" },
4349 		{ F_ERR_EGR_CTXT_PRIO,
4350 			"Egress context manager priority user error" },
4351 		{ F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" },
4352 		{ F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" },
4353 		{ F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4354 		{ F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4355 		{ F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4356 		{ 0x0000000f, "SGE context access for invalid queue" },
4357 		{ 0 }
4358 	};
4359 	static const struct intr_details t6_sge_int3_details[] = {
4360 		{ F_ERR_FLM_DBP,
4361 			"DBP pointer delivery for invalid context or QID" },
4362 		{ F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0,
4363 			"Invalid QID or header request by IDMA" },
4364 		{ F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" },
4365 		{ F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" },
4366 		{ F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" },
4367 		{ F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" },
4368 		{ F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" },
4369 		{ F_ERR_TIMER_ABOVE_MAX_QID,
4370 			"SGE GTS with timer 0-5 for IQID > 1023" },
4371 		{ F_ERR_CPL_EXCEED_IQE_SIZE,
4372 			"SGE received CPL exceeding IQE size" },
4373 		{ F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" },
4374 		{ F_ERR_ITP_TIME_PAUSED, "SGE ITP error" },
4375 		{ F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" },
4376 		{ F_ERR_DROPPED_DB, "SGE DB dropped" },
4377 		{ F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
4378 			"SGE IQID > 1023 received CPL for FL" },
4379 		{ F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4380 			F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" },
4381 		{ F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" },
4382 		{ F_ERR_ING_CTXT_PRIO,
4383 			"Ingress context manager priority user error" },
4384 		{ F_ERR_EGR_CTXT_PRIO,
4385 			"Egress context manager priority user error" },
4386 		{ F_DBP_TBUF_FULL, "SGE DBP tbuf full" },
4387 		{ F_FATAL_WRE_LEN,
4388 			"SGE WRE packet less than advertized length" },
4389 		{ F_REG_ADDRESS_ERR, "Undefined SGE register accessed" },
4390 		{ F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" },
4391 		{ F_EGRESS_SIZE_ERR, "SGE illegal egress QID" },
4392 		{ 0x0000000f, "SGE context access for invalid queue" },
4393 		{ 0 }
4394 	};
4395 	struct intr_info sge_int3_info = {
4396 		.name = "SGE_INT_CAUSE3",
4397 		.cause_reg = A_SGE_INT_CAUSE3,
4398 		.enable_reg = A_SGE_INT_ENABLE3,
4399 		.fatal = F_ERR_CPL_EXCEED_IQE_SIZE,
4400 		.flags = 0,
4401 		.details = NULL,
4402 		.actions = NULL,
4403 	};
4404 	static const struct intr_info sge_int4_info = {
4405 		.name = "SGE_INT_CAUSE4",
4406 		.cause_reg = A_SGE_INT_CAUSE4,
4407 		.enable_reg = A_SGE_INT_ENABLE4,
4408 		.fatal = 0,
4409 		.flags = 0,
4410 		.details = NULL,
4411 		.actions = NULL,
4412 	};
4413 	static const struct intr_info sge_int5_info = {
4414 		.name = "SGE_INT_CAUSE5",
4415 		.cause_reg = A_SGE_INT_CAUSE5,
4416 		.enable_reg = A_SGE_INT_ENABLE5,
4417 		.fatal = 0xffffffff,
4418 		.flags = NONFATAL_IF_DISABLED,
4419 		.details = NULL,
4420 		.actions = NULL,
4421 	};
4422 	static const struct intr_info sge_int6_info = {
4423 		.name = "SGE_INT_CAUSE6",
4424 		.cause_reg = A_SGE_INT_CAUSE6,
4425 		.enable_reg = A_SGE_INT_ENABLE6,
4426 		.fatal = 0,
4427 		.flags = 0,
4428 		.details = NULL,
4429 		.actions = NULL,
4430 	};
4431 
4432 	bool fatal;
4433 	u32 v;
4434 
4435 	if (chip_id(adap) <= CHELSIO_T5) {
4436 		sge_int3_info.details = sge_int3_details;
4437 	} else {
4438 		sge_int3_info.details = t6_sge_int3_details;
4439 	}
4440 
4441 	fatal = false;
4442 	fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose);
4443 	fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose);
4444 	fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose);
4445 	fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose);
4446 	if (chip_id(adap) >= CHELSIO_T5)
4447 		fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose);
4448 	if (chip_id(adap) >= CHELSIO_T6)
4449 		fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose);
4450 
4451 	v = t4_read_reg(adap, A_SGE_ERROR_STATS);
4452 	if (v & F_ERROR_QID_VALID) {
4453 		CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v));
4454 		if (v & F_UNCAPTURED_ERROR)
4455 			CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n");
4456 		t4_write_reg(adap, A_SGE_ERROR_STATS,
4457 		    F_ERROR_QID_VALID | F_UNCAPTURED_ERROR);
4458 	}
4459 
4460 	return (fatal);
4461 }
4462 
4463 /*
4464  * CIM interrupt handler.
4465  */
4466 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose)
4467 {
4468 	static const struct intr_details cim_host_intr_details[] = {
4469 		/* T6+ */
4470 		{ F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" },
4471 
4472 		/* T5+ */
4473 		{ F_MA_CIM_INTFPERR, "MA2CIM interface parity error" },
4474 		{ F_PLCIM_MSTRSPDATAPARERR,
4475 			"PL2CIM master response data parity error" },
4476 		{ F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" },
4477 		{ F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" },
4478 		{ F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" },
4479 		{ F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" },
4480 		{ F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" },
4481 		{ F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" },
4482 
4483 		/* T4+ */
4484 		{ F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" },
4485 		{ F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" },
4486 		{ F_MBHOSTPARERR, "CIM mailbox host read parity error" },
4487 		{ F_MBUPPARERR, "CIM mailbox uP parity error" },
4488 		{ F_IBQTP0PARERR, "CIM IBQ TP0 parity error" },
4489 		{ F_IBQTP1PARERR, "CIM IBQ TP1 parity error" },
4490 		{ F_IBQULPPARERR, "CIM IBQ ULP parity error" },
4491 		{ F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" },
4492 		{ F_IBQSGEHIPARERR | F_IBQPCIEPARERR,	/* same bit */
4493 			"CIM IBQ PCIe/SGE_HI parity error" },
4494 		{ F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" },
4495 		{ F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" },
4496 		{ F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" },
4497 		{ F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" },
4498 		{ F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" },
4499 		{ F_OBQSGEPARERR, "CIM OBQ SGE parity error" },
4500 		{ F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" },
4501 		{ F_TIMER1INT, "CIM TIMER0 interrupt" },
4502 		{ F_TIMER0INT, "CIM TIMER0 interrupt" },
4503 		{ F_PREFDROPINT, "CIM control register prefetch drop" },
4504 		{ 0}
4505 	};
4506 	static const struct intr_info cim_host_intr_info = {
4507 		.name = "CIM_HOST_INT_CAUSE",
4508 		.cause_reg = A_CIM_HOST_INT_CAUSE,
4509 		.enable_reg = A_CIM_HOST_INT_ENABLE,
4510 		.fatal = 0x007fffe6,
4511 		.flags = NONFATAL_IF_DISABLED,
4512 		.details = cim_host_intr_details,
4513 		.actions = NULL,
4514 	};
4515 	static const struct intr_details cim_host_upacc_intr_details[] = {
4516 		{ F_EEPROMWRINT, "CIM EEPROM came out of busy state" },
4517 		{ F_TIMEOUTMAINT, "CIM PIF MA timeout" },
4518 		{ F_TIMEOUTINT, "CIM PIF timeout" },
4519 		{ F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" },
4520 		{ F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" },
4521 		{ F_BLKWRPLINT, "CIM block write to PL space" },
4522 		{ F_BLKRDPLINT, "CIM block read from PL space" },
4523 		{ F_SGLWRPLINT,
4524 			"CIM single write to PL space with illegal BEs" },
4525 		{ F_SGLRDPLINT,
4526 			"CIM single read from PL space with illegal BEs" },
4527 		{ F_BLKWRCTLINT, "CIM block write to CTL space" },
4528 		{ F_BLKRDCTLINT, "CIM block read from CTL space" },
4529 		{ F_SGLWRCTLINT,
4530 			"CIM single write to CTL space with illegal BEs" },
4531 		{ F_SGLRDCTLINT,
4532 			"CIM single read from CTL space with illegal BEs" },
4533 		{ F_BLKWREEPROMINT, "CIM block write to EEPROM space" },
4534 		{ F_BLKRDEEPROMINT, "CIM block read from EEPROM space" },
4535 		{ F_SGLWREEPROMINT,
4536 			"CIM single write to EEPROM space with illegal BEs" },
4537 		{ F_SGLRDEEPROMINT,
4538 			"CIM single read from EEPROM space with illegal BEs" },
4539 		{ F_BLKWRFLASHINT, "CIM block write to flash space" },
4540 		{ F_BLKRDFLASHINT, "CIM block read from flash space" },
4541 		{ F_SGLWRFLASHINT, "CIM single write to flash space" },
4542 		{ F_SGLRDFLASHINT,
4543 			"CIM single read from flash space with illegal BEs" },
4544 		{ F_BLKWRBOOTINT, "CIM block write to boot space" },
4545 		{ F_BLKRDBOOTINT, "CIM block read from boot space" },
4546 		{ F_SGLWRBOOTINT, "CIM single write to boot space" },
4547 		{ F_SGLRDBOOTINT,
4548 			"CIM single read from boot space with illegal BEs" },
4549 		{ F_ILLWRBEINT, "CIM illegal write BEs" },
4550 		{ F_ILLRDBEINT, "CIM illegal read BEs" },
4551 		{ F_ILLRDINT, "CIM illegal read" },
4552 		{ F_ILLWRINT, "CIM illegal write" },
4553 		{ F_ILLTRANSINT, "CIM illegal transaction" },
4554 		{ F_RSVDSPACEINT, "CIM reserved space access" },
4555 		{0}
4556 	};
4557 	static const struct intr_info cim_host_upacc_intr_info = {
4558 		.name = "CIM_HOST_UPACC_INT_CAUSE",
4559 		.cause_reg = A_CIM_HOST_UPACC_INT_CAUSE,
4560 		.enable_reg = A_CIM_HOST_UPACC_INT_ENABLE,
4561 		.fatal = 0x3fffeeff,
4562 		.flags = NONFATAL_IF_DISABLED,
4563 		.details = cim_host_upacc_intr_details,
4564 		.actions = NULL,
4565 	};
4566 	static const struct intr_info cim_pf_host_intr_info = {
4567 		.name = "CIM_PF_HOST_INT_CAUSE",
4568 		.cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4569 		.enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE),
4570 		.fatal = 0,
4571 		.flags = 0,
4572 		.details = NULL,
4573 		.actions = NULL,
4574 	};
4575 	u32 val, fw_err;
4576 	bool fatal;
4577 
4578 	/*
4579 	 * When the Firmware detects an internal error which normally wouldn't
4580 	 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order
4581 	 * to make sure the Host sees the Firmware Crash.  So if we have a
4582 	 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0
4583 	 * interrupt.
4584 	 */
4585 	fw_err = t4_read_reg(adap, A_PCIE_FW);
4586 	val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE);
4587 	if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) ||
4588 	    G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) {
4589 		t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT);
4590 	}
4591 
4592 	fatal = (fw_err & F_PCIE_FW_ERR) != 0;
4593 	fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose);
4594 	fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose);
4595 	fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose);
4596 	if (fatal)
4597 		t4_os_cim_err(adap);
4598 
4599 	return (fatal);
4600 }
4601 
4602 /*
4603  * ULP RX interrupt handler.
4604  */
4605 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose)
4606 {
4607 	static const struct intr_details ulprx_intr_details[] = {
4608 		/* T5+ */
4609 		{ F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" },
4610 		{ F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" },
4611 
4612 		/* T4+ */
4613 		{ F_CAUSE_CTX_1, "ULPRX channel 1 context error" },
4614 		{ F_CAUSE_CTX_0, "ULPRX channel 0 context error" },
4615 		{ 0x007fffff, "ULPRX parity error" },
4616 		{ 0 }
4617 	};
4618 	static const struct intr_info ulprx_intr_info = {
4619 		.name = "ULP_RX_INT_CAUSE",
4620 		.cause_reg = A_ULP_RX_INT_CAUSE,
4621 		.enable_reg = A_ULP_RX_INT_ENABLE,
4622 		.fatal = 0x07ffffff,
4623 		.flags = NONFATAL_IF_DISABLED,
4624 		.details = ulprx_intr_details,
4625 		.actions = NULL,
4626 	};
4627 	static const struct intr_info ulprx_intr2_info = {
4628 		.name = "ULP_RX_INT_CAUSE_2",
4629 		.cause_reg = A_ULP_RX_INT_CAUSE_2,
4630 		.enable_reg = A_ULP_RX_INT_ENABLE_2,
4631 		.fatal = 0,
4632 		.flags = 0,
4633 		.details = NULL,
4634 		.actions = NULL,
4635 	};
4636 	bool fatal = false;
4637 
4638 	fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose);
4639 	fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose);
4640 
4641 	return (fatal);
4642 }
4643 
4644 /*
4645  * ULP TX interrupt handler.
4646  */
4647 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose)
4648 {
4649 	static const struct intr_details ulptx_intr_details[] = {
4650 		{ F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" },
4651 		{ F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" },
4652 		{ F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" },
4653 		{ F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" },
4654 		{ 0x0fffffff, "ULPTX parity error" },
4655 		{ 0 }
4656 	};
4657 	static const struct intr_info ulptx_intr_info = {
4658 		.name = "ULP_TX_INT_CAUSE",
4659 		.cause_reg = A_ULP_TX_INT_CAUSE,
4660 		.enable_reg = A_ULP_TX_INT_ENABLE,
4661 		.fatal = 0x0fffffff,
4662 		.flags = NONFATAL_IF_DISABLED,
4663 		.details = ulptx_intr_details,
4664 		.actions = NULL,
4665 	};
4666 	static const struct intr_info ulptx_intr2_info = {
4667 		.name = "ULP_TX_INT_CAUSE_2",
4668 		.cause_reg = A_ULP_TX_INT_CAUSE_2,
4669 		.enable_reg = A_ULP_TX_INT_ENABLE_2,
4670 		.fatal = 0xf0,
4671 		.flags = NONFATAL_IF_DISABLED,
4672 		.details = NULL,
4673 		.actions = NULL,
4674 	};
4675 	bool fatal = false;
4676 
4677 	fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose);
4678 	fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose);
4679 
4680 	return (fatal);
4681 }
4682 
4683 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose)
4684 {
4685 	int i;
4686 	u32 data[17];
4687 
4688 	t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0],
4689 	    ARRAY_SIZE(data), A_PM_TX_DBG_STAT0);
4690 	for (i = 0; i < ARRAY_SIZE(data); i++) {
4691 		CH_ALERT(adap, "  - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i,
4692 		    A_PM_TX_DBG_STAT0 + i, data[i]);
4693 	}
4694 
4695 	return (false);
4696 }
4697 
4698 /*
4699  * PM TX interrupt handler.
4700  */
4701 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose)
4702 {
4703 	static const struct intr_action pmtx_intr_actions[] = {
4704 		{ 0xffffffff, 0, pmtx_dump_dbg_stats },
4705 		{ 0 },
4706 	};
4707 	static const struct intr_details pmtx_intr_details[] = {
4708 		{ F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" },
4709 		{ F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" },
4710 		{ F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" },
4711 		{ F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" },
4712 		{ 0x0f000000, "PMTX icspi FIFO2X Rx framing error" },
4713 		{ 0x00f00000, "PMTX icspi FIFO Rx framing error" },
4714 		{ 0x000f0000, "PMTX icspi FIFO Tx framing error" },
4715 		{ 0x0000f000, "PMTX oespi FIFO Rx framing error" },
4716 		{ 0x00000f00, "PMTX oespi FIFO Tx framing error" },
4717 		{ 0x000000f0, "PMTX oespi FIFO2X Tx framing error" },
4718 		{ F_OESPI_PAR_ERROR, "PMTX oespi parity error" },
4719 		{ F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" },
4720 		{ F_ICSPI_PAR_ERROR, "PMTX icspi parity error" },
4721 		{ F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" },
4722 		{ 0 }
4723 	};
4724 	static const struct intr_info pmtx_intr_info = {
4725 		.name = "PM_TX_INT_CAUSE",
4726 		.cause_reg = A_PM_TX_INT_CAUSE,
4727 		.enable_reg = A_PM_TX_INT_ENABLE,
4728 		.fatal = 0xffffffff,
4729 		.flags = 0,
4730 		.details = pmtx_intr_details,
4731 		.actions = pmtx_intr_actions,
4732 	};
4733 
4734 	return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose));
4735 }
4736 
4737 /*
4738  * PM RX interrupt handler.
4739  */
4740 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose)
4741 {
4742 	static const struct intr_details pmrx_intr_details[] = {
4743 		/* T6+ */
4744 		{ 0x18000000, "PMRX ospi overflow" },
4745 		{ F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" },
4746 		{ F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" },
4747 		{ F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" },
4748 		{ F_SDC_ERR, "PMRX SDC error" },
4749 
4750 		/* T4+ */
4751 		{ F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" },
4752 		{ 0x003c0000, "PMRX iespi FIFO2X Rx framing error" },
4753 		{ 0x0003c000, "PMRX iespi Rx framing error" },
4754 		{ 0x00003c00, "PMRX iespi Tx framing error" },
4755 		{ 0x00000300, "PMRX ocspi Rx framing error" },
4756 		{ 0x000000c0, "PMRX ocspi Tx framing error" },
4757 		{ 0x00000030, "PMRX ocspi FIFO2X Tx framing error" },
4758 		{ F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" },
4759 		{ F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" },
4760 		{ F_IESPI_PAR_ERROR, "PMRX iespi parity error" },
4761 		{ F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"},
4762 		{ 0 }
4763 	};
4764 	static const struct intr_info pmrx_intr_info = {
4765 		.name = "PM_RX_INT_CAUSE",
4766 		.cause_reg = A_PM_RX_INT_CAUSE,
4767 		.enable_reg = A_PM_RX_INT_ENABLE,
4768 		.fatal = 0x1fffffff,
4769 		.flags = NONFATAL_IF_DISABLED,
4770 		.details = pmrx_intr_details,
4771 		.actions = NULL,
4772 	};
4773 
4774 	return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose));
4775 }
4776 
4777 /*
4778  * CPL switch interrupt handler.
4779  */
4780 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose)
4781 {
4782 	static const struct intr_details cplsw_intr_details[] = {
4783 		/* T5+ */
4784 		{ F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" },
4785 		{ F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" },
4786 
4787 		/* T4+ */
4788 		{ F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" },
4789 		{ F_CIM_OVFL_ERROR, "CPLSW CIM overflow" },
4790 		{ F_TP_FRAMING_ERROR, "CPLSW TP framing error" },
4791 		{ F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" },
4792 		{ F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" },
4793 		{ F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" },
4794 		{ 0 }
4795 	};
4796 	static const struct intr_info cplsw_intr_info = {
4797 		.name = "CPL_INTR_CAUSE",
4798 		.cause_reg = A_CPL_INTR_CAUSE,
4799 		.enable_reg = A_CPL_INTR_ENABLE,
4800 		.fatal = 0xff,
4801 		.flags = NONFATAL_IF_DISABLED,
4802 		.details = cplsw_intr_details,
4803 		.actions = NULL,
4804 	};
4805 
4806 	return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose));
4807 }
4808 
4809 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR)
4810 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR)
4811 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \
4812     F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \
4813     F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \
4814     F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR)
4815 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \
4816     F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \
4817     F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR)
4818 
4819 /*
4820  * LE interrupt handler.
4821  */
4822 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose)
4823 {
4824 	static const struct intr_details le_intr_details[] = {
4825 		{ F_REQQPARERR, "LE request queue parity error" },
4826 		{ F_UNKNOWNCMD, "LE unknown command" },
4827 		{ F_ACTRGNFULL, "LE active region full" },
4828 		{ F_PARITYERR, "LE parity error" },
4829 		{ F_LIPMISS, "LE LIP miss" },
4830 		{ F_LIP0, "LE 0 LIP error" },
4831 		{ 0 }
4832 	};
4833 	static const struct intr_details t6_le_intr_details[] = {
4834 		{ F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" },
4835 		{ F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" },
4836 		{ F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" },
4837 		{ F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" },
4838 		{ F_TOTCNTERR, "LE total active < TCAM count" },
4839 		{ F_CMDPRSRINTERR, "LE internal error in parser" },
4840 		{ F_CMDTIDERR, "Incorrect tid in LE command" },
4841 		{ F_T6_ACTRGNFULL, "LE active region full" },
4842 		{ F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" },
4843 		{ F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" },
4844 		{ F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" },
4845 		{ F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" },
4846 		{ F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" },
4847 		{ F_TCAMACCFAIL, "LE TCAM access failure" },
4848 		{ F_T6_UNKNOWNCMD, "LE unknown command" },
4849 		{ F_T6_LIP0, "LE found 0 LIP during CLIP substitution" },
4850 		{ F_T6_LIPMISS, "LE CLIP lookup miss" },
4851 		{ T6_LE_PERRCRC_MASK, "LE parity/CRC error" },
4852 		{ 0 }
4853 	};
4854 	struct intr_info le_intr_info = {
4855 		.name = "LE_DB_INT_CAUSE",
4856 		.cause_reg = A_LE_DB_INT_CAUSE,
4857 		.enable_reg = A_LE_DB_INT_ENABLE,
4858 		.fatal = 0,
4859 		.flags = NONFATAL_IF_DISABLED,
4860 		.details = NULL,
4861 		.actions = NULL,
4862 	};
4863 
4864 	if (chip_id(adap) <= CHELSIO_T5) {
4865 		le_intr_info.details = le_intr_details;
4866 		le_intr_info.fatal = T5_LE_FATAL_MASK;
4867 	} else {
4868 		le_intr_info.details = t6_le_intr_details;
4869 		le_intr_info.fatal = T6_LE_FATAL_MASK;
4870 	}
4871 
4872 	return (t4_handle_intr(adap, &le_intr_info, 0, verbose));
4873 }
4874 
4875 /*
4876  * MPS interrupt handler.
4877  */
4878 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose)
4879 {
4880 	static const struct intr_details mps_rx_perr_intr_details[] = {
4881 		{ 0xffffffff, "MPS Rx parity error" },
4882 		{ 0 }
4883 	};
4884 	static const struct intr_info mps_rx_perr_intr_info = {
4885 		.name = "MPS_RX_PERR_INT_CAUSE",
4886 		.cause_reg = A_MPS_RX_PERR_INT_CAUSE,
4887 		.enable_reg = A_MPS_RX_PERR_INT_ENABLE,
4888 		.fatal = 0xffffffff,
4889 		.flags = NONFATAL_IF_DISABLED,
4890 		.details = mps_rx_perr_intr_details,
4891 		.actions = NULL,
4892 	};
4893 	static const struct intr_details mps_tx_intr_details[] = {
4894 		{ F_PORTERR, "MPS Tx destination port is disabled" },
4895 		{ F_FRMERR, "MPS Tx framing error" },
4896 		{ F_SECNTERR, "MPS Tx SOP/EOP error" },
4897 		{ F_BUBBLE, "MPS Tx underflow" },
4898 		{ V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" },
4899 		{ V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" },
4900 		{ F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" },
4901 		{ V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" },
4902 		{ 0 }
4903 	};
4904 	static const struct intr_info mps_tx_intr_info = {
4905 		.name = "MPS_TX_INT_CAUSE",
4906 		.cause_reg = A_MPS_TX_INT_CAUSE,
4907 		.enable_reg = A_MPS_TX_INT_ENABLE,
4908 		.fatal = 0x1ffff,
4909 		.flags = NONFATAL_IF_DISABLED,
4910 		.details = mps_tx_intr_details,
4911 		.actions = NULL,
4912 	};
4913 	static const struct intr_details mps_trc_intr_details[] = {
4914 		{ F_MISCPERR, "MPS TRC misc parity error" },
4915 		{ V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" },
4916 		{ V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" },
4917 		{ 0 }
4918 	};
4919 	static const struct intr_info mps_trc_intr_info = {
4920 		.name = "MPS_TRC_INT_CAUSE",
4921 		.cause_reg = A_MPS_TRC_INT_CAUSE,
4922 		.enable_reg = A_MPS_TRC_INT_ENABLE,
4923 		.fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM),
4924 		.flags = 0,
4925 		.details = mps_trc_intr_details,
4926 		.actions = NULL,
4927 	};
4928 	static const struct intr_details mps_stat_sram_intr_details[] = {
4929 		{ 0xffffffff, "MPS statistics SRAM parity error" },
4930 		{ 0 }
4931 	};
4932 	static const struct intr_info mps_stat_sram_intr_info = {
4933 		.name = "MPS_STAT_PERR_INT_CAUSE_SRAM",
4934 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4935 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM,
4936 		.fatal = 0x1fffffff,
4937 		.flags = NONFATAL_IF_DISABLED,
4938 		.details = mps_stat_sram_intr_details,
4939 		.actions = NULL,
4940 	};
4941 	static const struct intr_details mps_stat_tx_intr_details[] = {
4942 		{ 0xffffff, "MPS statistics Tx FIFO parity error" },
4943 		{ 0 }
4944 	};
4945 	static const struct intr_info mps_stat_tx_intr_info = {
4946 		.name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO",
4947 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4948 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO,
4949 		.fatal =  0xffffff,
4950 		.flags = NONFATAL_IF_DISABLED,
4951 		.details = mps_stat_tx_intr_details,
4952 		.actions = NULL,
4953 	};
4954 	static const struct intr_details mps_stat_rx_intr_details[] = {
4955 		{ 0xffffff, "MPS statistics Rx FIFO parity error" },
4956 		{ 0 }
4957 	};
4958 	static const struct intr_info mps_stat_rx_intr_info = {
4959 		.name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO",
4960 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4961 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO,
4962 		.fatal =  0xffffff,
4963 		.flags = 0,
4964 		.details = mps_stat_rx_intr_details,
4965 		.actions = NULL,
4966 	};
4967 	static const struct intr_details mps_cls_intr_details[] = {
4968 		{ F_HASHSRAM, "MPS hash SRAM parity error" },
4969 		{ F_MATCHTCAM, "MPS match TCAM parity error" },
4970 		{ F_MATCHSRAM, "MPS match SRAM parity error" },
4971 		{ 0 }
4972 	};
4973 	static const struct intr_info mps_cls_intr_info = {
4974 		.name = "MPS_CLS_INT_CAUSE",
4975 		.cause_reg = A_MPS_CLS_INT_CAUSE,
4976 		.enable_reg = A_MPS_CLS_INT_ENABLE,
4977 		.fatal =  F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM,
4978 		.flags = 0,
4979 		.details = mps_cls_intr_details,
4980 		.actions = NULL,
4981 	};
4982 	static const struct intr_details mps_stat_sram1_intr_details[] = {
4983 		{ 0xff, "MPS statistics SRAM1 parity error" },
4984 		{ 0 }
4985 	};
4986 	static const struct intr_info mps_stat_sram1_intr_info = {
4987 		.name = "MPS_STAT_PERR_INT_CAUSE_SRAM1",
4988 		.cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1,
4989 		.enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1,
4990 		.fatal = 0xff,
4991 		.flags = 0,
4992 		.details = mps_stat_sram1_intr_details,
4993 		.actions = NULL,
4994 	};
4995 
4996 	bool fatal;
4997 
4998 	fatal = false;
4999 	fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose);
5000 	fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose);
5001 	fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose);
5002 	fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose);
5003 	fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose);
5004 	fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose);
5005 	fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose);
5006 	if (chip_id(adap) > CHELSIO_T4) {
5007 		fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0,
5008 		    verbose);
5009 	}
5010 
5011 	t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff);
5012 	t4_read_reg(adap, A_MPS_INT_CAUSE);	/* flush */
5013 
5014 	return (fatal);
5015 
5016 }
5017 
5018 /*
5019  * EDC/MC interrupt handler.
5020  */
5021 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose)
5022 {
5023 	static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" };
5024 	unsigned int count_reg, v;
5025 	static const struct intr_details mem_intr_details[] = {
5026 		{ F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" },
5027 		{ F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" },
5028 		{ F_PERR_INT_CAUSE, "FIFO parity error" },
5029 		{ 0 }
5030 	};
5031 	struct intr_info ii = {
5032 		.fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE,
5033 		.details = mem_intr_details,
5034 		.flags = 0,
5035 		.actions = NULL,
5036 	};
5037 	bool fatal;
5038 
5039 	switch (idx) {
5040 	case MEM_EDC0:
5041 		ii.name = "EDC0_INT_CAUSE";
5042 		ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0);
5043 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0);
5044 		count_reg = EDC_REG(A_EDC_ECC_STATUS, 0);
5045 		break;
5046 	case MEM_EDC1:
5047 		ii.name = "EDC1_INT_CAUSE";
5048 		ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1);
5049 		ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1);
5050 		count_reg = EDC_REG(A_EDC_ECC_STATUS, 1);
5051 		break;
5052 	case MEM_MC0:
5053 		ii.name = "MC0_INT_CAUSE";
5054 		if (is_t4(adap)) {
5055 			ii.cause_reg = A_MC_INT_CAUSE;
5056 			ii.enable_reg = A_MC_INT_ENABLE;
5057 			count_reg = A_MC_ECC_STATUS;
5058 		} else {
5059 			ii.cause_reg = A_MC_P_INT_CAUSE;
5060 			ii.enable_reg = A_MC_P_INT_ENABLE;
5061 			count_reg = A_MC_P_ECC_STATUS;
5062 		}
5063 		break;
5064 	case MEM_MC1:
5065 		ii.name = "MC1_INT_CAUSE";
5066 		ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1);
5067 		ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1);
5068 		count_reg = MC_REG(A_MC_P_ECC_STATUS, 1);
5069 		break;
5070 	}
5071 
5072 	fatal = t4_handle_intr(adap, &ii, 0, verbose);
5073 
5074 	v = t4_read_reg(adap, count_reg);
5075 	if (v != 0) {
5076 		if (G_ECC_UECNT(v) != 0) {
5077 			CH_ALERT(adap,
5078 			    "%s: %u uncorrectable ECC data error(s)\n",
5079 			    name[idx], G_ECC_UECNT(v));
5080 		}
5081 		if (G_ECC_CECNT(v) != 0) {
5082 			if (idx <= MEM_EDC1)
5083 				t4_edc_err_read(adap, idx);
5084 			CH_WARN_RATELIMIT(adap,
5085 			    "%s: %u correctable ECC data error(s)\n",
5086 			    name[idx], G_ECC_CECNT(v));
5087 		}
5088 		t4_write_reg(adap, count_reg, 0xffffffff);
5089 	}
5090 
5091 	return (fatal);
5092 }
5093 
5094 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose)
5095 {
5096 	u32 v;
5097 
5098 	v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS);
5099 	CH_ALERT(adap,
5100 	    "MA address wrap-around error by client %u to address %#x\n",
5101 	    G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4);
5102 	t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v);
5103 
5104 	return (false);
5105 }
5106 
5107 
5108 /*
5109  * MA interrupt handler.
5110  */
5111 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose)
5112 {
5113 	static const struct intr_action ma_intr_actions[] = {
5114 		{ F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status },
5115 		{ 0 },
5116 	};
5117 	static const struct intr_info ma_intr_info = {
5118 		.name = "MA_INT_CAUSE",
5119 		.cause_reg = A_MA_INT_CAUSE,
5120 		.enable_reg = A_MA_INT_ENABLE,
5121 		.fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE,
5122 		.flags = NONFATAL_IF_DISABLED,
5123 		.details = NULL,
5124 		.actions = ma_intr_actions,
5125 	};
5126 	static const struct intr_info ma_perr_status1 = {
5127 		.name = "MA_PARITY_ERROR_STATUS1",
5128 		.cause_reg = A_MA_PARITY_ERROR_STATUS1,
5129 		.enable_reg = A_MA_PARITY_ERROR_ENABLE1,
5130 		.fatal = 0xffffffff,
5131 		.flags = 0,
5132 		.details = NULL,
5133 		.actions = NULL,
5134 	};
5135 	static const struct intr_info ma_perr_status2 = {
5136 		.name = "MA_PARITY_ERROR_STATUS2",
5137 		.cause_reg = A_MA_PARITY_ERROR_STATUS2,
5138 		.enable_reg = A_MA_PARITY_ERROR_ENABLE2,
5139 		.fatal = 0xffffffff,
5140 		.flags = 0,
5141 		.details = NULL,
5142 		.actions = NULL,
5143 	};
5144 	bool fatal;
5145 
5146 	fatal = false;
5147 	fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose);
5148 	fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose);
5149 	if (chip_id(adap) > CHELSIO_T4)
5150 		fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose);
5151 
5152 	return (fatal);
5153 }
5154 
5155 /*
5156  * SMB interrupt handler.
5157  */
5158 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose)
5159 {
5160 	static const struct intr_details smb_intr_details[] = {
5161 		{ F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" },
5162 		{ F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" },
5163 		{ F_SLVFIFOPARINT, "SMB slave FIFO parity error" },
5164 		{ 0 }
5165 	};
5166 	static const struct intr_info smb_intr_info = {
5167 		.name = "SMB_INT_CAUSE",
5168 		.cause_reg = A_SMB_INT_CAUSE,
5169 		.enable_reg = A_SMB_INT_ENABLE,
5170 		.fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT,
5171 		.flags = 0,
5172 		.details = smb_intr_details,
5173 		.actions = NULL,
5174 	};
5175 
5176 	return (t4_handle_intr(adap, &smb_intr_info, 0, verbose));
5177 }
5178 
5179 /*
5180  * NC-SI interrupt handler.
5181  */
5182 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose)
5183 {
5184 	static const struct intr_details ncsi_intr_details[] = {
5185 		{ F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" },
5186 		{ F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" },
5187 		{ F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" },
5188 		{ F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" },
5189 		{ 0 }
5190 	};
5191 	static const struct intr_info ncsi_intr_info = {
5192 		.name = "NCSI_INT_CAUSE",
5193 		.cause_reg = A_NCSI_INT_CAUSE,
5194 		.enable_reg = A_NCSI_INT_ENABLE,
5195 		.fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR |
5196 		    F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR,
5197 		.flags = 0,
5198 		.details = ncsi_intr_details,
5199 		.actions = NULL,
5200 	};
5201 
5202 	return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose));
5203 }
5204 
5205 /*
5206  * MAC interrupt handler.
5207  */
5208 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose)
5209 {
5210 	static const struct intr_details mac_intr_details[] = {
5211 		{ F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" },
5212 		{ F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" },
5213 		{ 0 }
5214 	};
5215 	char name[32];
5216 	struct intr_info ii;
5217 	bool fatal = false;
5218 
5219 	if (is_t4(adap)) {
5220 		snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port);
5221 		ii.name = &name[0];
5222 		ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
5223 		ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN);
5224 		ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5225 		ii.flags = 0;
5226 		ii.details = mac_intr_details;
5227 		ii.actions = NULL;
5228 	} else {
5229 		snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port);
5230 		ii.name = &name[0];
5231 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
5232 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN);
5233 		ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR;
5234 		ii.flags = 0;
5235 		ii.details = mac_intr_details;
5236 		ii.actions = NULL;
5237 	}
5238 	fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5239 
5240 	if (chip_id(adap) >= CHELSIO_T5) {
5241 		snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port);
5242 		ii.name = &name[0];
5243 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE);
5244 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN);
5245 		ii.fatal = 0;
5246 		ii.flags = 0;
5247 		ii.details = NULL;
5248 		ii.actions = NULL;
5249 		fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5250 	}
5251 
5252 	if (chip_id(adap) >= CHELSIO_T6) {
5253 		snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port);
5254 		ii.name = &name[0];
5255 		ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G);
5256 		ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G);
5257 		ii.fatal = 0;
5258 		ii.flags = 0;
5259 		ii.details = NULL;
5260 		ii.actions = NULL;
5261 		fatal |= t4_handle_intr(adap, &ii, 0, verbose);
5262 	}
5263 
5264 	return (fatal);
5265 }
5266 
5267 static bool pl_timeout_status(struct adapter *adap, int arg, bool verbose)
5268 {
5269 
5270 	CH_ALERT(adap, "    PL_TIMEOUT_STATUS 0x%08x 0x%08x\n",
5271 	    t4_read_reg(adap, A_PL_TIMEOUT_STATUS0),
5272 	    t4_read_reg(adap, A_PL_TIMEOUT_STATUS1));
5273 
5274 	return (false);
5275 }
5276 
5277 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose)
5278 {
5279 	static const struct intr_action plpl_intr_actions[] = {
5280 		{ F_TIMEOUT, 0, pl_timeout_status },
5281 		{ 0 },
5282 	};
5283 	static const struct intr_details plpl_intr_details[] = {
5284 		{ F_PL_BUSPERR, "Bus parity error" },
5285 		{ F_FATALPERR, "Fatal parity error" },
5286 		{ F_INVALIDACCESS, "Global reserved memory access" },
5287 		{ F_TIMEOUT,  "Bus timeout" },
5288 		{ F_PLERR, "Module reserved access" },
5289 		{ F_PERRVFID, "VFID_MAP parity error" },
5290 		{ 0 }
5291 	};
5292 	static const struct intr_info plpl_intr_info = {
5293 		.name = "PL_PL_INT_CAUSE",
5294 		.cause_reg = A_PL_PL_INT_CAUSE,
5295 		.enable_reg = A_PL_PL_INT_ENABLE,
5296 		.fatal = F_FATALPERR | F_PERRVFID,
5297 		.flags = NONFATAL_IF_DISABLED,
5298 		.details = plpl_intr_details,
5299 		.actions = plpl_intr_actions,
5300 	};
5301 
5302 	return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose));
5303 }
5304 
5305 /**
5306  *	t4_slow_intr_handler - control path interrupt handler
5307  *	@adap: the adapter
5308  *	@verbose: increased verbosity, for debug
5309  *
5310  *	T4 interrupt handler for non-data global interrupt events, e.g., errors.
5311  *	The designation 'slow' is because it involves register reads, while
5312  *	data interrupts typically don't involve any MMIOs.
5313  */
5314 bool t4_slow_intr_handler(struct adapter *adap, bool verbose)
5315 {
5316 	static const struct intr_details pl_intr_details[] = {
5317 		{ F_MC1, "MC1" },
5318 		{ F_UART, "UART" },
5319 		{ F_ULP_TX, "ULP TX" },
5320 		{ F_SGE, "SGE" },
5321 		{ F_HMA, "HMA" },
5322 		{ F_CPL_SWITCH, "CPL Switch" },
5323 		{ F_ULP_RX, "ULP RX" },
5324 		{ F_PM_RX, "PM RX" },
5325 		{ F_PM_TX, "PM TX" },
5326 		{ F_MA, "MA" },
5327 		{ F_TP, "TP" },
5328 		{ F_LE, "LE" },
5329 		{ F_EDC1, "EDC1" },
5330 		{ F_EDC0, "EDC0" },
5331 		{ F_MC, "MC0" },
5332 		{ F_PCIE, "PCIE" },
5333 		{ F_PMU, "PMU" },
5334 		{ F_MAC3, "MAC3" },
5335 		{ F_MAC2, "MAC2" },
5336 		{ F_MAC1, "MAC1" },
5337 		{ F_MAC0, "MAC0" },
5338 		{ F_SMB, "SMB" },
5339 		{ F_SF, "SF" },
5340 		{ F_PL, "PL" },
5341 		{ F_NCSI, "NC-SI" },
5342 		{ F_MPS, "MPS" },
5343 		{ F_MI, "MI" },
5344 		{ F_DBG, "DBG" },
5345 		{ F_I2CM, "I2CM" },
5346 		{ F_CIM, "CIM" },
5347 		{ 0 }
5348 	};
5349 	static const struct intr_info pl_perr_cause = {
5350 		.name = "PL_PERR_CAUSE",
5351 		.cause_reg = A_PL_PERR_CAUSE,
5352 		.enable_reg = A_PL_PERR_ENABLE,
5353 		.fatal = 0xffffffff,
5354 		.flags = 0,
5355 		.details = pl_intr_details,
5356 		.actions = NULL,
5357 	};
5358 	static const struct intr_action pl_intr_action[] = {
5359 		{ F_MC1, MEM_MC1, mem_intr_handler },
5360 		{ F_ULP_TX, -1, ulptx_intr_handler },
5361 		{ F_SGE, -1, sge_intr_handler },
5362 		{ F_CPL_SWITCH, -1, cplsw_intr_handler },
5363 		{ F_ULP_RX, -1, ulprx_intr_handler },
5364 		{ F_PM_RX, -1, pmrx_intr_handler},
5365 		{ F_PM_TX, -1, pmtx_intr_handler},
5366 		{ F_MA, -1, ma_intr_handler },
5367 		{ F_TP, -1, tp_intr_handler },
5368 		{ F_LE, -1, le_intr_handler },
5369 		{ F_EDC1, MEM_EDC1, mem_intr_handler },
5370 		{ F_EDC0, MEM_EDC0, mem_intr_handler },
5371 		{ F_MC0, MEM_MC0, mem_intr_handler },
5372 		{ F_PCIE, -1, pcie_intr_handler },
5373 		{ F_MAC3, 3, mac_intr_handler},
5374 		{ F_MAC2, 2, mac_intr_handler},
5375 		{ F_MAC1, 1, mac_intr_handler},
5376 		{ F_MAC0, 0, mac_intr_handler},
5377 		{ F_SMB, -1, smb_intr_handler},
5378 		{ F_PL, -1, plpl_intr_handler },
5379 		{ F_NCSI, -1, ncsi_intr_handler},
5380 		{ F_MPS, -1, mps_intr_handler },
5381 		{ F_CIM, -1, cim_intr_handler },
5382 		{ 0 }
5383 	};
5384 	static const struct intr_info pl_intr_info = {
5385 		.name = "PL_INT_CAUSE",
5386 		.cause_reg = A_PL_INT_CAUSE,
5387 		.enable_reg = A_PL_INT_ENABLE,
5388 		.fatal = 0,
5389 		.flags = 0,
5390 		.details = pl_intr_details,
5391 		.actions = pl_intr_action,
5392 	};
5393 	u32 perr;
5394 
5395 	perr = t4_read_reg(adap, pl_perr_cause.cause_reg);
5396 	if (verbose || perr != 0) {
5397 		t4_show_intr_info(adap, &pl_perr_cause, perr);
5398 		if (perr != 0)
5399 			t4_write_reg(adap, pl_perr_cause.cause_reg, perr);
5400 		if (verbose)
5401 			perr |= t4_read_reg(adap, pl_intr_info.enable_reg);
5402 	}
5403 
5404 	return (t4_handle_intr(adap, &pl_intr_info, perr, verbose));
5405 }
5406 
5407 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
5408 
5409 /**
5410  *	t4_intr_enable - enable interrupts
5411  *	@adapter: the adapter whose interrupts should be enabled
5412  *
5413  *	Enable PF-specific interrupts for the calling function and the top-level
5414  *	interrupt concentrator for global interrupts.  Interrupts are already
5415  *	enabled at each module,	here we just enable the roots of the interrupt
5416  *	hierarchies.
5417  *
5418  *	Note: this function should be called only when the driver manages
5419  *	non PF-specific interrupts from the various HW modules.  Only one PCI
5420  *	function at a time should be doing this.
5421  */
5422 void t4_intr_enable(struct adapter *adap)
5423 {
5424 	u32 val = 0;
5425 
5426 	if (chip_id(adap) <= CHELSIO_T5)
5427 		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
5428 	else
5429 		val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
5430 	val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC |
5431 	    F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 |
5432 	    F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 |
5433 	    F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
5434 	    F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT |
5435 	    F_EGRESS_SIZE_ERR;
5436 	t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val);
5437 	t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
5438 	t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0);
5439 	t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf);
5440 }
5441 
5442 /**
5443  *	t4_intr_disable - disable interrupts
5444  *	@adap: the adapter whose interrupts should be disabled
5445  *
5446  *	Disable interrupts.  We only disable the top-level interrupt
5447  *	concentrators.  The caller must be a PCI function managing global
5448  *	interrupts.
5449  */
5450 void t4_intr_disable(struct adapter *adap)
5451 {
5452 
5453 	t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
5454 	t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0);
5455 }
5456 
5457 /**
5458  *	hash_mac_addr - return the hash value of a MAC address
5459  *	@addr: the 48-bit Ethernet MAC address
5460  *
5461  *	Hashes a MAC address according to the hash function used by HW inexact
5462  *	(hash) address matching.
5463  */
5464 static int hash_mac_addr(const u8 *addr)
5465 {
5466 	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
5467 	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
5468 	a ^= b;
5469 	a ^= (a >> 12);
5470 	a ^= (a >> 6);
5471 	return a & 0x3f;
5472 }
5473 
5474 /**
5475  *	t4_config_rss_range - configure a portion of the RSS mapping table
5476  *	@adapter: the adapter
5477  *	@mbox: mbox to use for the FW command
5478  *	@viid: virtual interface whose RSS subtable is to be written
5479  *	@start: start entry in the table to write
5480  *	@n: how many table entries to write
5481  *	@rspq: values for the "response queue" (Ingress Queue) lookup table
5482  *	@nrspq: number of values in @rspq
5483  *
5484  *	Programs the selected part of the VI's RSS mapping table with the
5485  *	provided values.  If @nrspq < @n the supplied values are used repeatedly
5486  *	until the full table range is populated.
5487  *
5488  *	The caller must ensure the values in @rspq are in the range allowed for
5489  *	@viid.
5490  */
5491 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5492 			int start, int n, const u16 *rspq, unsigned int nrspq)
5493 {
5494 	int ret;
5495 	const u16 *rsp = rspq;
5496 	const u16 *rsp_end = rspq + nrspq;
5497 	struct fw_rss_ind_tbl_cmd cmd;
5498 
5499 	memset(&cmd, 0, sizeof(cmd));
5500 	cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
5501 				     F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5502 				     V_FW_RSS_IND_TBL_CMD_VIID(viid));
5503 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5504 
5505 	/*
5506 	 * Each firmware RSS command can accommodate up to 32 RSS Ingress
5507 	 * Queue Identifiers.  These Ingress Queue IDs are packed three to
5508 	 * a 32-bit word as 10-bit values with the upper remaining 2 bits
5509 	 * reserved.
5510 	 */
5511 	while (n > 0) {
5512 		int nq = min(n, 32);
5513 		int nq_packed = 0;
5514 		__be32 *qp = &cmd.iq0_to_iq2;
5515 
5516 		/*
5517 		 * Set up the firmware RSS command header to send the next
5518 		 * "nq" Ingress Queue IDs to the firmware.
5519 		 */
5520 		cmd.niqid = cpu_to_be16(nq);
5521 		cmd.startidx = cpu_to_be16(start);
5522 
5523 		/*
5524 		 * "nq" more done for the start of the next loop.
5525 		 */
5526 		start += nq;
5527 		n -= nq;
5528 
5529 		/*
5530 		 * While there are still Ingress Queue IDs to stuff into the
5531 		 * current firmware RSS command, retrieve them from the
5532 		 * Ingress Queue ID array and insert them into the command.
5533 		 */
5534 		while (nq > 0) {
5535 			/*
5536 			 * Grab up to the next 3 Ingress Queue IDs (wrapping
5537 			 * around the Ingress Queue ID array if necessary) and
5538 			 * insert them into the firmware RSS command at the
5539 			 * current 3-tuple position within the commad.
5540 			 */
5541 			u16 qbuf[3];
5542 			u16 *qbp = qbuf;
5543 			int nqbuf = min(3, nq);
5544 
5545 			nq -= nqbuf;
5546 			qbuf[0] = qbuf[1] = qbuf[2] = 0;
5547 			while (nqbuf && nq_packed < 32) {
5548 				nqbuf--;
5549 				nq_packed++;
5550 				*qbp++ = *rsp++;
5551 				if (rsp >= rsp_end)
5552 					rsp = rspq;
5553 			}
5554 			*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
5555 					    V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
5556 					    V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
5557 		}
5558 
5559 		/*
5560 		 * Send this portion of the RRS table update to the firmware;
5561 		 * bail out on any errors.
5562 		 */
5563 		ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5564 		if (ret)
5565 			return ret;
5566 	}
5567 	return 0;
5568 }
5569 
5570 /**
5571  *	t4_config_glbl_rss - configure the global RSS mode
5572  *	@adapter: the adapter
5573  *	@mbox: mbox to use for the FW command
5574  *	@mode: global RSS mode
5575  *	@flags: mode-specific flags
5576  *
5577  *	Sets the global RSS mode.
5578  */
5579 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5580 		       unsigned int flags)
5581 {
5582 	struct fw_rss_glb_config_cmd c;
5583 
5584 	memset(&c, 0, sizeof(c));
5585 	c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
5586 				    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
5587 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5588 	if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5589 		c.u.manual.mode_pkd =
5590 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5591 	} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5592 		c.u.basicvirtual.mode_keymode =
5593 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
5594 		c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5595 	} else
5596 		return -EINVAL;
5597 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5598 }
5599 
5600 /**
5601  *	t4_config_vi_rss - configure per VI RSS settings
5602  *	@adapter: the adapter
5603  *	@mbox: mbox to use for the FW command
5604  *	@viid: the VI id
5605  *	@flags: RSS flags
5606  *	@defq: id of the default RSS queue for the VI.
5607  *	@skeyidx: RSS secret key table index for non-global mode
5608  *	@skey: RSS vf_scramble key for VI.
5609  *
5610  *	Configures VI-specific RSS properties.
5611  */
5612 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5613 		     unsigned int flags, unsigned int defq, unsigned int skeyidx,
5614 		     unsigned int skey)
5615 {
5616 	struct fw_rss_vi_config_cmd c;
5617 
5618 	memset(&c, 0, sizeof(c));
5619 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
5620 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
5621 				   V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
5622 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5623 	c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5624 					V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
5625 	c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32(
5626 					V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx));
5627 	c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey);
5628 
5629 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5630 }
5631 
5632 /* Read an RSS table row */
5633 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5634 {
5635 	t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
5636 	return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
5637 				   5, 0, val);
5638 }
5639 
5640 /**
5641  *	t4_read_rss - read the contents of the RSS mapping table
5642  *	@adapter: the adapter
5643  *	@map: holds the contents of the RSS mapping table
5644  *
5645  *	Reads the contents of the RSS hash->queue mapping table.
5646  */
5647 int t4_read_rss(struct adapter *adapter, u16 *map)
5648 {
5649 	u32 val;
5650 	int i, ret;
5651 	int rss_nentries = adapter->chip_params->rss_nentries;
5652 
5653 	for (i = 0; i < rss_nentries / 2; ++i) {
5654 		ret = rd_rss_row(adapter, i, &val);
5655 		if (ret)
5656 			return ret;
5657 		*map++ = G_LKPTBLQUEUE0(val);
5658 		*map++ = G_LKPTBLQUEUE1(val);
5659 	}
5660 	return 0;
5661 }
5662 
5663 /**
5664  * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5665  * @adap: the adapter
5666  * @cmd: TP fw ldst address space type
5667  * @vals: where the indirect register values are stored/written
5668  * @nregs: how many indirect registers to read/write
5669  * @start_idx: index of first indirect register to read/write
5670  * @rw: Read (1) or Write (0)
5671  * @sleep_ok: if true we may sleep while awaiting command completion
5672  *
5673  * Access TP indirect registers through LDST
5674  **/
5675 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5676 			    unsigned int nregs, unsigned int start_index,
5677 			    unsigned int rw, bool sleep_ok)
5678 {
5679 	int ret = 0;
5680 	unsigned int i;
5681 	struct fw_ldst_cmd c;
5682 
5683 	for (i = 0; i < nregs; i++) {
5684 		memset(&c, 0, sizeof(c));
5685 		c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
5686 						F_FW_CMD_REQUEST |
5687 						(rw ? F_FW_CMD_READ :
5688 						      F_FW_CMD_WRITE) |
5689 						V_FW_LDST_CMD_ADDRSPACE(cmd));
5690 		c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5691 
5692 		c.u.addrval.addr = cpu_to_be32(start_index + i);
5693 		c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
5694 		ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5695 				      sleep_ok);
5696 		if (ret)
5697 			return ret;
5698 
5699 		if (rw)
5700 			vals[i] = be32_to_cpu(c.u.addrval.val);
5701 	}
5702 	return 0;
5703 }
5704 
5705 /**
5706  * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5707  * @adap: the adapter
5708  * @reg_addr: Address Register
5709  * @reg_data: Data register
5710  * @buff: where the indirect register values are stored/written
5711  * @nregs: how many indirect registers to read/write
5712  * @start_index: index of first indirect register to read/write
5713  * @rw: READ(1) or WRITE(0)
5714  * @sleep_ok: if true we may sleep while awaiting command completion
5715  *
5716  * Read/Write TP indirect registers through LDST if possible.
5717  * Else, use backdoor access
5718  **/
5719 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5720 			      u32 *buff, u32 nregs, u32 start_index, int rw,
5721 			      bool sleep_ok)
5722 {
5723 	int rc = -EINVAL;
5724 	int cmd;
5725 
5726 	switch (reg_addr) {
5727 	case A_TP_PIO_ADDR:
5728 		cmd = FW_LDST_ADDRSPC_TP_PIO;
5729 		break;
5730 	case A_TP_TM_PIO_ADDR:
5731 		cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5732 		break;
5733 	case A_TP_MIB_INDEX:
5734 		cmd = FW_LDST_ADDRSPC_TP_MIB;
5735 		break;
5736 	default:
5737 		goto indirect_access;
5738 	}
5739 
5740 	if (t4_use_ldst(adap))
5741 		rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5742 				      sleep_ok);
5743 
5744 indirect_access:
5745 
5746 	if (rc) {
5747 		if (rw)
5748 			t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5749 					 start_index);
5750 		else
5751 			t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5752 					  start_index);
5753 	}
5754 }
5755 
5756 /**
5757  * t4_tp_pio_read - Read TP PIO registers
5758  * @adap: the adapter
5759  * @buff: where the indirect register values are written
5760  * @nregs: how many indirect registers to read
5761  * @start_index: index of first indirect register to read
5762  * @sleep_ok: if true we may sleep while awaiting command completion
5763  *
5764  * Read TP PIO Registers
5765  **/
5766 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5767 		    u32 start_index, bool sleep_ok)
5768 {
5769 	t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs,
5770 			  start_index, 1, sleep_ok);
5771 }
5772 
5773 /**
5774  * t4_tp_pio_write - Write TP PIO registers
5775  * @adap: the adapter
5776  * @buff: where the indirect register values are stored
5777  * @nregs: how many indirect registers to write
5778  * @start_index: index of first indirect register to write
5779  * @sleep_ok: if true we may sleep while awaiting command completion
5780  *
5781  * Write TP PIO Registers
5782  **/
5783 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
5784 		     u32 start_index, bool sleep_ok)
5785 {
5786 	t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5787 	    __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok);
5788 }
5789 
5790 /**
5791  * t4_tp_tm_pio_read - Read TP TM PIO registers
5792  * @adap: the adapter
5793  * @buff: where the indirect register values are written
5794  * @nregs: how many indirect registers to read
5795  * @start_index: index of first indirect register to read
5796  * @sleep_ok: if true we may sleep while awaiting command completion
5797  *
5798  * Read TP TM PIO Registers
5799  **/
5800 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5801 		       u32 start_index, bool sleep_ok)
5802 {
5803 	t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff,
5804 			  nregs, start_index, 1, sleep_ok);
5805 }
5806 
5807 /**
5808  * t4_tp_mib_read - Read TP MIB registers
5809  * @adap: the adapter
5810  * @buff: where the indirect register values are written
5811  * @nregs: how many indirect registers to read
5812  * @start_index: index of first indirect register to read
5813  * @sleep_ok: if true we may sleep while awaiting command completion
5814  *
5815  * Read TP MIB Registers
5816  **/
5817 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5818 		    bool sleep_ok)
5819 {
5820 	t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs,
5821 			  start_index, 1, sleep_ok);
5822 }
5823 
5824 /**
5825  *	t4_read_rss_key - read the global RSS key
5826  *	@adap: the adapter
5827  *	@key: 10-entry array holding the 320-bit RSS key
5828  * 	@sleep_ok: if true we may sleep while awaiting command completion
5829  *
5830  *	Reads the global 320-bit RSS key.
5831  */
5832 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5833 {
5834 	t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5835 }
5836 
5837 /**
5838  *	t4_write_rss_key - program one of the RSS keys
5839  *	@adap: the adapter
5840  *	@key: 10-entry array holding the 320-bit RSS key
5841  *	@idx: which RSS key to write
5842  * 	@sleep_ok: if true we may sleep while awaiting command completion
5843  *
5844  *	Writes one of the RSS keys with the given 320-bit value.  If @idx is
5845  *	0..15 the corresponding entry in the RSS key table is written,
5846  *	otherwise the global RSS key is written.
5847  */
5848 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5849 		      bool sleep_ok)
5850 {
5851 	u8 rss_key_addr_cnt = 16;
5852 	u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
5853 
5854 	/*
5855 	 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5856 	 * allows access to key addresses 16-63 by using KeyWrAddrX
5857 	 * as index[5:4](upper 2) into key table
5858 	 */
5859 	if ((chip_id(adap) > CHELSIO_T5) &&
5860 	    (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
5861 		rss_key_addr_cnt = 32;
5862 
5863 	t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok);
5864 
5865 	if (idx >= 0 && idx < rss_key_addr_cnt) {
5866 		if (rss_key_addr_cnt > 16)
5867 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5868 				     vrt | V_KEYWRADDRX(idx >> 4) |
5869 				     V_T6_VFWRADDR(idx) | F_KEYWREN);
5870 		else
5871 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
5872 				     vrt| V_KEYWRADDR(idx) | F_KEYWREN);
5873 	}
5874 }
5875 
5876 /**
5877  *	t4_read_rss_pf_config - read PF RSS Configuration Table
5878  *	@adapter: the adapter
5879  *	@index: the entry in the PF RSS table to read
5880  *	@valp: where to store the returned value
5881  * 	@sleep_ok: if true we may sleep while awaiting command completion
5882  *
5883  *	Reads the PF RSS Configuration Table at the specified index and returns
5884  *	the value found there.
5885  */
5886 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5887 			   u32 *valp, bool sleep_ok)
5888 {
5889 	t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok);
5890 }
5891 
5892 /**
5893  *	t4_write_rss_pf_config - write PF RSS Configuration Table
5894  *	@adapter: the adapter
5895  *	@index: the entry in the VF RSS table to read
5896  *	@val: the value to store
5897  * 	@sleep_ok: if true we may sleep while awaiting command completion
5898  *
5899  *	Writes the PF RSS Configuration Table at the specified index with the
5900  *	specified value.
5901  */
5902 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
5903 			    u32 val, bool sleep_ok)
5904 {
5905 	t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index,
5906 			sleep_ok);
5907 }
5908 
5909 /**
5910  *	t4_read_rss_vf_config - read VF RSS Configuration Table
5911  *	@adapter: the adapter
5912  *	@index: the entry in the VF RSS table to read
5913  *	@vfl: where to store the returned VFL
5914  *	@vfh: where to store the returned VFH
5915  * 	@sleep_ok: if true we may sleep while awaiting command completion
5916  *
5917  *	Reads the VF RSS Configuration Table at the specified index and returns
5918  *	the (VFL, VFH) values found there.
5919  */
5920 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5921 			   u32 *vfl, u32 *vfh, bool sleep_ok)
5922 {
5923 	u32 vrt, mask, data;
5924 
5925 	if (chip_id(adapter) <= CHELSIO_T5) {
5926 		mask = V_VFWRADDR(M_VFWRADDR);
5927 		data = V_VFWRADDR(index);
5928 	} else {
5929 		 mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5930 		 data = V_T6_VFWRADDR(index);
5931 	}
5932 	/*
5933 	 * Request that the index'th VF Table values be read into VFL/VFH.
5934 	 */
5935 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5936 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5937 	vrt |= data | F_VFRDEN;
5938 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5939 
5940 	/*
5941 	 * Grab the VFL/VFH values ...
5942 	 */
5943 	t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5944 	t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5945 }
5946 
5947 /**
5948  *	t4_write_rss_vf_config - write VF RSS Configuration Table
5949  *
5950  *	@adapter: the adapter
5951  *	@index: the entry in the VF RSS table to write
5952  *	@vfl: the VFL to store
5953  *	@vfh: the VFH to store
5954  *
5955  *	Writes the VF RSS Configuration Table at the specified index with the
5956  *	specified (VFL, VFH) values.
5957  */
5958 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
5959 			    u32 vfl, u32 vfh, bool sleep_ok)
5960 {
5961 	u32 vrt, mask, data;
5962 
5963 	if (chip_id(adapter) <= CHELSIO_T5) {
5964 		mask = V_VFWRADDR(M_VFWRADDR);
5965 		data = V_VFWRADDR(index);
5966 	} else {
5967 		mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5968 		data = V_T6_VFWRADDR(index);
5969 	}
5970 
5971 	/*
5972 	 * Load up VFL/VFH with the values to be written ...
5973 	 */
5974 	t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok);
5975 	t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok);
5976 
5977 	/*
5978 	 * Write the VFL/VFH into the VF Table at index'th location.
5979 	 */
5980 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5981 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5982 	vrt |= data | F_VFRDEN;
5983 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5984 }
5985 
5986 /**
5987  *	t4_read_rss_pf_map - read PF RSS Map
5988  *	@adapter: the adapter
5989  * 	@sleep_ok: if true we may sleep while awaiting command completion
5990  *
5991  *	Reads the PF RSS Map register and returns its value.
5992  */
5993 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5994 {
5995 	u32 pfmap;
5996 
5997 	t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
5998 
5999 	return pfmap;
6000 }
6001 
6002 /**
6003  *	t4_write_rss_pf_map - write PF RSS Map
6004  *	@adapter: the adapter
6005  *	@pfmap: PF RSS Map value
6006  *
6007  *	Writes the specified value to the PF RSS Map register.
6008  */
6009 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok)
6010 {
6011 	t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok);
6012 }
6013 
6014 /**
6015  *	t4_read_rss_pf_mask - read PF RSS Mask
6016  *	@adapter: the adapter
6017  * 	@sleep_ok: if true we may sleep while awaiting command completion
6018  *
6019  *	Reads the PF RSS Mask register and returns its value.
6020  */
6021 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
6022 {
6023 	u32 pfmask;
6024 
6025 	t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6026 
6027 	return pfmask;
6028 }
6029 
6030 /**
6031  *	t4_write_rss_pf_mask - write PF RSS Mask
6032  *	@adapter: the adapter
6033  *	@pfmask: PF RSS Mask value
6034  *
6035  *	Writes the specified value to the PF RSS Mask register.
6036  */
6037 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok)
6038 {
6039 	t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok);
6040 }
6041 
6042 /**
6043  *	t4_tp_get_tcp_stats - read TP's TCP MIB counters
6044  *	@adap: the adapter
6045  *	@v4: holds the TCP/IP counter values
6046  *	@v6: holds the TCP/IPv6 counter values
6047  * 	@sleep_ok: if true we may sleep while awaiting command completion
6048  *
6049  *	Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
6050  *	Either @v4 or @v6 may be %NULL to skip the corresponding stats.
6051  */
6052 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
6053 			 struct tp_tcp_stats *v6, bool sleep_ok)
6054 {
6055 	u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
6056 
6057 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
6058 #define STAT(x)     val[STAT_IDX(x)]
6059 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
6060 
6061 	if (v4) {
6062 		t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6063 			       A_TP_MIB_TCP_OUT_RST, sleep_ok);
6064 		v4->tcp_out_rsts = STAT(OUT_RST);
6065 		v4->tcp_in_segs  = STAT64(IN_SEG);
6066 		v4->tcp_out_segs = STAT64(OUT_SEG);
6067 		v4->tcp_retrans_segs = STAT64(RXT_SEG);
6068 	}
6069 	if (v6) {
6070 		t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
6071 			       A_TP_MIB_TCP_V6OUT_RST, sleep_ok);
6072 		v6->tcp_out_rsts = STAT(OUT_RST);
6073 		v6->tcp_in_segs  = STAT64(IN_SEG);
6074 		v6->tcp_out_segs = STAT64(OUT_SEG);
6075 		v6->tcp_retrans_segs = STAT64(RXT_SEG);
6076 	}
6077 #undef STAT64
6078 #undef STAT
6079 #undef STAT_IDX
6080 }
6081 
6082 /**
6083  *	t4_tp_get_err_stats - read TP's error MIB counters
6084  *	@adap: the adapter
6085  *	@st: holds the counter values
6086  * 	@sleep_ok: if true we may sleep while awaiting command completion
6087  *
6088  *	Returns the values of TP's error counters.
6089  */
6090 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
6091 			 bool sleep_ok)
6092 {
6093 	int nchan = adap->chip_params->nchan;
6094 
6095 	t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0,
6096 		       sleep_ok);
6097 
6098 	t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0,
6099 		       sleep_ok);
6100 
6101 	t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0,
6102 		       sleep_ok);
6103 
6104 	t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
6105 		       A_TP_MIB_TNL_CNG_DROP_0, sleep_ok);
6106 
6107 	t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
6108 		       A_TP_MIB_OFD_CHN_DROP_0, sleep_ok);
6109 
6110 	t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0,
6111 		       sleep_ok);
6112 
6113 	t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
6114 		       A_TP_MIB_OFD_VLN_DROP_0, sleep_ok);
6115 
6116 	t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
6117 		       A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok);
6118 
6119 	t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP,
6120 		       sleep_ok);
6121 }
6122 
6123 /**
6124  *	t4_tp_get_err_stats - read TP's error MIB counters
6125  *	@adap: the adapter
6126  *	@st: holds the counter values
6127  * 	@sleep_ok: if true we may sleep while awaiting command completion
6128  *
6129  *	Returns the values of TP's error counters.
6130  */
6131 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st,
6132 			 bool sleep_ok)
6133 {
6134 	int nchan = adap->chip_params->nchan;
6135 
6136 	t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0,
6137 		       sleep_ok);
6138 	t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0,
6139 		       sleep_ok);
6140 }
6141 
6142 /**
6143  *	t4_tp_get_proxy_stats - read TP's proxy MIB counters
6144  *	@adap: the adapter
6145  *	@st: holds the counter values
6146  *
6147  *	Returns the values of TP's proxy counters.
6148  */
6149 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
6150     bool sleep_ok)
6151 {
6152 	int nchan = adap->chip_params->nchan;
6153 
6154 	t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok);
6155 }
6156 
6157 /**
6158  *	t4_tp_get_cpl_stats - read TP's CPL MIB counters
6159  *	@adap: the adapter
6160  *	@st: holds the counter values
6161  * 	@sleep_ok: if true we may sleep while awaiting command completion
6162  *
6163  *	Returns the values of TP's CPL counters.
6164  */
6165 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
6166 			 bool sleep_ok)
6167 {
6168 	int nchan = adap->chip_params->nchan;
6169 
6170 	t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok);
6171 
6172 	t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok);
6173 }
6174 
6175 /**
6176  *	t4_tp_get_rdma_stats - read TP's RDMA MIB counters
6177  *	@adap: the adapter
6178  *	@st: holds the counter values
6179  *
6180  *	Returns the values of TP's RDMA counters.
6181  */
6182 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
6183 			  bool sleep_ok)
6184 {
6185 	t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT,
6186 		       sleep_ok);
6187 }
6188 
6189 /**
6190  *	t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
6191  *	@adap: the adapter
6192  *	@idx: the port index
6193  *	@st: holds the counter values
6194  * 	@sleep_ok: if true we may sleep while awaiting command completion
6195  *
6196  *	Returns the values of TP's FCoE counters for the selected port.
6197  */
6198 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
6199 		       struct tp_fcoe_stats *st, bool sleep_ok)
6200 {
6201 	u32 val[2];
6202 
6203 	t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx,
6204 		       sleep_ok);
6205 
6206 	t4_tp_mib_read(adap, &st->frames_drop, 1,
6207 		       A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok);
6208 
6209 	t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx,
6210 		       sleep_ok);
6211 
6212 	st->octets_ddp = ((u64)val[0] << 32) | val[1];
6213 }
6214 
6215 /**
6216  *	t4_get_usm_stats - read TP's non-TCP DDP MIB counters
6217  *	@adap: the adapter
6218  *	@st: holds the counter values
6219  * 	@sleep_ok: if true we may sleep while awaiting command completion
6220  *
6221  *	Returns the values of TP's counters for non-TCP directly-placed packets.
6222  */
6223 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
6224 		      bool sleep_ok)
6225 {
6226 	u32 val[4];
6227 
6228 	t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok);
6229 
6230 	st->frames = val[0];
6231 	st->drops = val[1];
6232 	st->octets = ((u64)val[2] << 32) | val[3];
6233 }
6234 
6235 /**
6236  *	t4_tp_get_tid_stats - read TP's tid MIB counters.
6237  *	@adap: the adapter
6238  *	@st: holds the counter values
6239  * 	@sleep_ok: if true we may sleep while awaiting command completion
6240  *
6241  *	Returns the values of TP's counters for tids.
6242  */
6243 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st,
6244 		      bool sleep_ok)
6245 {
6246 
6247 	t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok);
6248 }
6249 
6250 /**
6251  *	t4_read_mtu_tbl - returns the values in the HW path MTU table
6252  *	@adap: the adapter
6253  *	@mtus: where to store the MTU values
6254  *	@mtu_log: where to store the MTU base-2 log (may be %NULL)
6255  *
6256  *	Reads the HW path MTU table.
6257  */
6258 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
6259 {
6260 	u32 v;
6261 	int i;
6262 
6263 	for (i = 0; i < NMTUS; ++i) {
6264 		t4_write_reg(adap, A_TP_MTU_TABLE,
6265 			     V_MTUINDEX(0xff) | V_MTUVALUE(i));
6266 		v = t4_read_reg(adap, A_TP_MTU_TABLE);
6267 		mtus[i] = G_MTUVALUE(v);
6268 		if (mtu_log)
6269 			mtu_log[i] = G_MTUWIDTH(v);
6270 	}
6271 }
6272 
6273 /**
6274  *	t4_read_cong_tbl - reads the congestion control table
6275  *	@adap: the adapter
6276  *	@incr: where to store the alpha values
6277  *
6278  *	Reads the additive increments programmed into the HW congestion
6279  *	control table.
6280  */
6281 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
6282 {
6283 	unsigned int mtu, w;
6284 
6285 	for (mtu = 0; mtu < NMTUS; ++mtu)
6286 		for (w = 0; w < NCCTRL_WIN; ++w) {
6287 			t4_write_reg(adap, A_TP_CCTRL_TABLE,
6288 				     V_ROWINDEX(0xffff) | (mtu << 5) | w);
6289 			incr[mtu][w] = (u16)t4_read_reg(adap,
6290 						A_TP_CCTRL_TABLE) & 0x1fff;
6291 		}
6292 }
6293 
6294 /**
6295  *	t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
6296  *	@adap: the adapter
6297  *	@addr: the indirect TP register address
6298  *	@mask: specifies the field within the register to modify
6299  *	@val: new value for the field
6300  *
6301  *	Sets a field of an indirect TP register to the given value.
6302  */
6303 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
6304 			    unsigned int mask, unsigned int val)
6305 {
6306 	t4_write_reg(adap, A_TP_PIO_ADDR, addr);
6307 	val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
6308 	t4_write_reg(adap, A_TP_PIO_DATA, val);
6309 }
6310 
6311 /**
6312  *	init_cong_ctrl - initialize congestion control parameters
6313  *	@a: the alpha values for congestion control
6314  *	@b: the beta values for congestion control
6315  *
6316  *	Initialize the congestion control parameters.
6317  */
6318 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
6319 {
6320 	a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
6321 	a[9] = 2;
6322 	a[10] = 3;
6323 	a[11] = 4;
6324 	a[12] = 5;
6325 	a[13] = 6;
6326 	a[14] = 7;
6327 	a[15] = 8;
6328 	a[16] = 9;
6329 	a[17] = 10;
6330 	a[18] = 14;
6331 	a[19] = 17;
6332 	a[20] = 21;
6333 	a[21] = 25;
6334 	a[22] = 30;
6335 	a[23] = 35;
6336 	a[24] = 45;
6337 	a[25] = 60;
6338 	a[26] = 80;
6339 	a[27] = 100;
6340 	a[28] = 200;
6341 	a[29] = 300;
6342 	a[30] = 400;
6343 	a[31] = 500;
6344 
6345 	b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
6346 	b[9] = b[10] = 1;
6347 	b[11] = b[12] = 2;
6348 	b[13] = b[14] = b[15] = b[16] = 3;
6349 	b[17] = b[18] = b[19] = b[20] = b[21] = 4;
6350 	b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
6351 	b[28] = b[29] = 6;
6352 	b[30] = b[31] = 7;
6353 }
6354 
6355 /* The minimum additive increment value for the congestion control table */
6356 #define CC_MIN_INCR 2U
6357 
6358 /**
6359  *	t4_load_mtus - write the MTU and congestion control HW tables
6360  *	@adap: the adapter
6361  *	@mtus: the values for the MTU table
6362  *	@alpha: the values for the congestion control alpha parameter
6363  *	@beta: the values for the congestion control beta parameter
6364  *
6365  *	Write the HW MTU table with the supplied MTUs and the high-speed
6366  *	congestion control table with the supplied alpha, beta, and MTUs.
6367  *	We write the two tables together because the additive increments
6368  *	depend on the MTUs.
6369  */
6370 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
6371 		  const unsigned short *alpha, const unsigned short *beta)
6372 {
6373 	static const unsigned int avg_pkts[NCCTRL_WIN] = {
6374 		2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
6375 		896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
6376 		28672, 40960, 57344, 81920, 114688, 163840, 229376
6377 	};
6378 
6379 	unsigned int i, w;
6380 
6381 	for (i = 0; i < NMTUS; ++i) {
6382 		unsigned int mtu = mtus[i];
6383 		unsigned int log2 = fls(mtu);
6384 
6385 		if (!(mtu & ((1 << log2) >> 2)))     /* round */
6386 			log2--;
6387 		t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
6388 			     V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
6389 
6390 		for (w = 0; w < NCCTRL_WIN; ++w) {
6391 			unsigned int inc;
6392 
6393 			inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
6394 				  CC_MIN_INCR);
6395 
6396 			t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
6397 				     (w << 16) | (beta[w] << 13) | inc);
6398 		}
6399 	}
6400 }
6401 
6402 /**
6403  *	t4_set_pace_tbl - set the pace table
6404  *	@adap: the adapter
6405  *	@pace_vals: the pace values in microseconds
6406  *	@start: index of the first entry in the HW pace table to set
6407  *	@n: how many entries to set
6408  *
6409  *	Sets (a subset of the) HW pace table.
6410  */
6411 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
6412 		     unsigned int start, unsigned int n)
6413 {
6414 	unsigned int vals[NTX_SCHED], i;
6415 	unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
6416 
6417 	if (n > NTX_SCHED)
6418 	    return -ERANGE;
6419 
6420 	/* convert values from us to dack ticks, rounding to closest value */
6421 	for (i = 0; i < n; i++, pace_vals++) {
6422 		vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
6423 		if (vals[i] > 0x7ff)
6424 			return -ERANGE;
6425 		if (*pace_vals && vals[i] == 0)
6426 			return -ERANGE;
6427 	}
6428 	for (i = 0; i < n; i++, start++)
6429 		t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
6430 	return 0;
6431 }
6432 
6433 /**
6434  *	t4_set_sched_bps - set the bit rate for a HW traffic scheduler
6435  *	@adap: the adapter
6436  *	@kbps: target rate in Kbps
6437  *	@sched: the scheduler index
6438  *
6439  *	Configure a Tx HW scheduler for the target rate.
6440  */
6441 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
6442 {
6443 	unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
6444 	unsigned int clk = adap->params.vpd.cclk * 1000;
6445 	unsigned int selected_cpt = 0, selected_bpt = 0;
6446 
6447 	if (kbps > 0) {
6448 		kbps *= 125;     /* -> bytes */
6449 		for (cpt = 1; cpt <= 255; cpt++) {
6450 			tps = clk / cpt;
6451 			bpt = (kbps + tps / 2) / tps;
6452 			if (bpt > 0 && bpt <= 255) {
6453 				v = bpt * tps;
6454 				delta = v >= kbps ? v - kbps : kbps - v;
6455 				if (delta < mindelta) {
6456 					mindelta = delta;
6457 					selected_cpt = cpt;
6458 					selected_bpt = bpt;
6459 				}
6460 			} else if (selected_cpt)
6461 				break;
6462 		}
6463 		if (!selected_cpt)
6464 			return -EINVAL;
6465 	}
6466 	t4_write_reg(adap, A_TP_TM_PIO_ADDR,
6467 		     A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
6468 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6469 	if (sched & 1)
6470 		v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
6471 	else
6472 		v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
6473 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6474 	return 0;
6475 }
6476 
6477 /**
6478  *	t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
6479  *	@adap: the adapter
6480  *	@sched: the scheduler index
6481  *	@ipg: the interpacket delay in tenths of nanoseconds
6482  *
6483  *	Set the interpacket delay for a HW packet rate scheduler.
6484  */
6485 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
6486 {
6487 	unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
6488 
6489 	/* convert ipg to nearest number of core clocks */
6490 	ipg *= core_ticks_per_usec(adap);
6491 	ipg = (ipg + 5000) / 10000;
6492 	if (ipg > M_TXTIMERSEPQ0)
6493 		return -EINVAL;
6494 
6495 	t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
6496 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
6497 	if (sched & 1)
6498 		v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
6499 	else
6500 		v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
6501 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
6502 	t4_read_reg(adap, A_TP_TM_PIO_DATA);
6503 	return 0;
6504 }
6505 
6506 /*
6507  * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
6508  * clocks.  The formula is
6509  *
6510  * bytes/s = bytes256 * 256 * ClkFreq / 4096
6511  *
6512  * which is equivalent to
6513  *
6514  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
6515  */
6516 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
6517 {
6518 	u64 v = (u64)bytes256 * adap->params.vpd.cclk;
6519 
6520 	return v * 62 + v / 2;
6521 }
6522 
6523 /**
6524  *	t4_get_chan_txrate - get the current per channel Tx rates
6525  *	@adap: the adapter
6526  *	@nic_rate: rates for NIC traffic
6527  *	@ofld_rate: rates for offloaded traffic
6528  *
6529  *	Return the current Tx rates in bytes/s for NIC and offloaded traffic
6530  *	for each channel.
6531  */
6532 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
6533 {
6534 	u32 v;
6535 
6536 	v = t4_read_reg(adap, A_TP_TX_TRATE);
6537 	nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
6538 	nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
6539 	if (adap->chip_params->nchan > 2) {
6540 		nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
6541 		nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
6542 	}
6543 
6544 	v = t4_read_reg(adap, A_TP_TX_ORATE);
6545 	ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
6546 	ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
6547 	if (adap->chip_params->nchan > 2) {
6548 		ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
6549 		ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
6550 	}
6551 }
6552 
6553 /**
6554  *	t4_set_trace_filter - configure one of the tracing filters
6555  *	@adap: the adapter
6556  *	@tp: the desired trace filter parameters
6557  *	@idx: which filter to configure
6558  *	@enable: whether to enable or disable the filter
6559  *
6560  *	Configures one of the tracing filters available in HW.  If @tp is %NULL
6561  *	it indicates that the filter is already written in the register and it
6562  *	just needs to be enabled or disabled.
6563  */
6564 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
6565     int idx, int enable)
6566 {
6567 	int i, ofst = idx * 4;
6568 	u32 data_reg, mask_reg, cfg;
6569 	u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
6570 
6571 	if (idx < 0 || idx >= NTRACE)
6572 		return -EINVAL;
6573 
6574 	if (tp == NULL || !enable) {
6575 		t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
6576 		    enable ? en : 0);
6577 		return 0;
6578 	}
6579 
6580 	/*
6581 	 * TODO - After T4 data book is updated, specify the exact
6582 	 * section below.
6583 	 *
6584 	 * See T4 data book - MPS section for a complete description
6585 	 * of the below if..else handling of A_MPS_TRC_CFG register
6586 	 * value.
6587 	 */
6588 	cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
6589 	if (cfg & F_TRCMULTIFILTER) {
6590 		/*
6591 		 * If multiple tracers are enabled, then maximum
6592 		 * capture size is 2.5KB (FIFO size of a single channel)
6593 		 * minus 2 flits for CPL_TRACE_PKT header.
6594 		 */
6595 		if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
6596 			return -EINVAL;
6597 	} else {
6598 		/*
6599 		 * If multiple tracers are disabled, to avoid deadlocks
6600 		 * maximum packet capture size of 9600 bytes is recommended.
6601 		 * Also in this mode, only trace0 can be enabled and running.
6602 		 */
6603 		if (tp->snap_len > 9600 || idx)
6604 			return -EINVAL;
6605 	}
6606 
6607 	if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
6608 	    tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
6609 	    tp->min_len > M_TFMINPKTSIZE)
6610 		return -EINVAL;
6611 
6612 	/* stop the tracer we'll be changing */
6613 	t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
6614 
6615 	idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
6616 	data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
6617 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
6618 
6619 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6620 		t4_write_reg(adap, data_reg, tp->data[i]);
6621 		t4_write_reg(adap, mask_reg, ~tp->mask[i]);
6622 	}
6623 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
6624 		     V_TFCAPTUREMAX(tp->snap_len) |
6625 		     V_TFMINPKTSIZE(tp->min_len));
6626 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
6627 		     V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
6628 		     (is_t4(adap) ?
6629 		     V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
6630 		     V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
6631 
6632 	return 0;
6633 }
6634 
6635 /**
6636  *	t4_get_trace_filter - query one of the tracing filters
6637  *	@adap: the adapter
6638  *	@tp: the current trace filter parameters
6639  *	@idx: which trace filter to query
6640  *	@enabled: non-zero if the filter is enabled
6641  *
6642  *	Returns the current settings of one of the HW tracing filters.
6643  */
6644 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6645 			 int *enabled)
6646 {
6647 	u32 ctla, ctlb;
6648 	int i, ofst = idx * 4;
6649 	u32 data_reg, mask_reg;
6650 
6651 	ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
6652 	ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
6653 
6654 	if (is_t4(adap)) {
6655 		*enabled = !!(ctla & F_TFEN);
6656 		tp->port =  G_TFPORT(ctla);
6657 		tp->invert = !!(ctla & F_TFINVERTMATCH);
6658 	} else {
6659 		*enabled = !!(ctla & F_T5_TFEN);
6660 		tp->port = G_T5_TFPORT(ctla);
6661 		tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
6662 	}
6663 	tp->snap_len = G_TFCAPTUREMAX(ctlb);
6664 	tp->min_len = G_TFMINPKTSIZE(ctlb);
6665 	tp->skip_ofst = G_TFOFFSET(ctla);
6666 	tp->skip_len = G_TFLENGTH(ctla);
6667 
6668 	ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
6669 	data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
6670 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
6671 
6672 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6673 		tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6674 		tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6675 	}
6676 }
6677 
6678 /**
6679  *	t4_pmtx_get_stats - returns the HW stats from PMTX
6680  *	@adap: the adapter
6681  *	@cnt: where to store the count statistics
6682  *	@cycles: where to store the cycle statistics
6683  *
6684  *	Returns performance statistics from PMTX.
6685  */
6686 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6687 {
6688 	int i;
6689 	u32 data[2];
6690 
6691 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6692 		t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
6693 		cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
6694 		if (is_t4(adap))
6695 			cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
6696 		else {
6697 			t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
6698 					 A_PM_TX_DBG_DATA, data, 2,
6699 					 A_PM_TX_DBG_STAT_MSB);
6700 			cycles[i] = (((u64)data[0] << 32) | data[1]);
6701 		}
6702 	}
6703 }
6704 
6705 /**
6706  *	t4_pmrx_get_stats - returns the HW stats from PMRX
6707  *	@adap: the adapter
6708  *	@cnt: where to store the count statistics
6709  *	@cycles: where to store the cycle statistics
6710  *
6711  *	Returns performance statistics from PMRX.
6712  */
6713 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6714 {
6715 	int i;
6716 	u32 data[2];
6717 
6718 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
6719 		t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
6720 		cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
6721 		if (is_t4(adap)) {
6722 			cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
6723 		} else {
6724 			t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
6725 					 A_PM_RX_DBG_DATA, data, 2,
6726 					 A_PM_RX_DBG_STAT_MSB);
6727 			cycles[i] = (((u64)data[0] << 32) | data[1]);
6728 		}
6729 	}
6730 }
6731 
6732 /**
6733  *	t4_get_mps_bg_map - return the buffer groups associated with a port
6734  *	@adap: the adapter
6735  *	@idx: the port index
6736  *
6737  *	Returns a bitmap indicating which MPS buffer groups are associated
6738  *	with the given port.  Bit i is set if buffer group i is used by the
6739  *	port.
6740  */
6741 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
6742 {
6743 	u32 n;
6744 
6745 	if (adap->params.mps_bg_map != UINT32_MAX)
6746 		return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff);
6747 
6748 	n = adap->params.nports;
6749 	MPASS(n > 0 && n <= MAX_NPORTS);
6750 	if (n == 1)
6751 		return idx == 0 ? 0xf : 0;
6752 	if (n == 2 && chip_id(adap) <= CHELSIO_T5)
6753 		return idx < 2 ? (3 << (2 * idx)) : 0;
6754 	return 1 << idx;
6755 }
6756 
6757 /*
6758  * TP RX e-channels associated with the port.
6759  */
6760 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx)
6761 {
6762 	const u32 n = adap->params.nports;
6763 	const u32 all_chan = (1 << adap->chip_params->nchan) - 1;
6764 
6765 	if (n == 1)
6766 		return idx == 0 ? all_chan : 0;
6767 	if (n == 2 && chip_id(adap) <= CHELSIO_T5)
6768 		return idx < 2 ? (3 << (2 * idx)) : 0;
6769 	return 1 << idx;
6770 }
6771 
6772 /*
6773  * TP RX c-channel associated with the port.
6774  */
6775 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx)
6776 {
6777 	if (adap->params.tp_ch_map != UINT32_MAX)
6778 		return (adap->params.tp_ch_map >> (8 * idx)) & 0xff;
6779         return 0;
6780 }
6781 
6782 /*
6783  * TP TX c-channel associated with the port.
6784  */
6785 static unsigned int t4_get_tx_c_chan(struct adapter *adap, int idx)
6786 {
6787 	return idx;
6788 }
6789 
6790 /**
6791  *      t4_get_port_type_description - return Port Type string description
6792  *      @port_type: firmware Port Type enumeration
6793  */
6794 const char *t4_get_port_type_description(enum fw_port_type port_type)
6795 {
6796 	static const char *const port_type_description[] = {
6797 		"Fiber_XFI",
6798 		"Fiber_XAUI",
6799 		"BT_SGMII",
6800 		"BT_XFI",
6801 		"BT_XAUI",
6802 		"KX4",
6803 		"CX4",
6804 		"KX",
6805 		"KR",
6806 		"SFP",
6807 		"BP_AP",
6808 		"BP4_AP",
6809 		"QSFP_10G",
6810 		"QSA",
6811 		"QSFP",
6812 		"BP40_BA",
6813 		"KR4_100G",
6814 		"CR4_QSFP",
6815 		"CR_QSFP",
6816 		"CR2_QSFP",
6817 		"SFP28",
6818 		"KR_SFP28",
6819 		"KR_XLAUI",
6820 	};
6821 
6822 	if (port_type < ARRAY_SIZE(port_type_description))
6823 		return port_type_description[port_type];
6824 	return "UNKNOWN";
6825 }
6826 
6827 /**
6828  *      t4_get_port_stats_offset - collect port stats relative to a previous
6829  *				   snapshot
6830  *      @adap: The adapter
6831  *      @idx: The port
6832  *      @stats: Current stats to fill
6833  *      @offset: Previous stats snapshot
6834  */
6835 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6836 		struct port_stats *stats,
6837 		struct port_stats *offset)
6838 {
6839 	u64 *s, *o;
6840 	int i;
6841 
6842 	t4_get_port_stats(adap, idx, stats);
6843 	for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
6844 			i < (sizeof(struct port_stats)/sizeof(u64)) ;
6845 			i++, s++, o++)
6846 		*s -= *o;
6847 }
6848 
6849 /**
6850  *	t4_get_port_stats - collect port statistics
6851  *	@adap: the adapter
6852  *	@idx: the port index
6853  *	@p: the stats structure to fill
6854  *
6855  *	Collect statistics related to the given port from HW.
6856  */
6857 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6858 {
6859 	struct port_info *pi = adap->port[idx];
6860 	u32 bgmap = pi->mps_bg_map;
6861 	u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
6862 
6863 #define GET_STAT(name) \
6864 	t4_read_reg64(adap, \
6865 	    t4_port_reg(adap, pi->tx_chan, A_MPS_PORT_STAT_##name##_L));
6866 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6867 
6868 	p->tx_pause		= GET_STAT(TX_PORT_PAUSE);
6869 	p->tx_octets		= GET_STAT(TX_PORT_BYTES);
6870 	p->tx_frames		= GET_STAT(TX_PORT_FRAMES);
6871 	p->tx_bcast_frames	= GET_STAT(TX_PORT_BCAST);
6872 	p->tx_mcast_frames	= GET_STAT(TX_PORT_MCAST);
6873 	p->tx_ucast_frames	= GET_STAT(TX_PORT_UCAST);
6874 	p->tx_error_frames	= GET_STAT(TX_PORT_ERROR);
6875 	p->tx_frames_64		= GET_STAT(TX_PORT_64B);
6876 	p->tx_frames_65_127	= GET_STAT(TX_PORT_65B_127B);
6877 	p->tx_frames_128_255	= GET_STAT(TX_PORT_128B_255B);
6878 	p->tx_frames_256_511	= GET_STAT(TX_PORT_256B_511B);
6879 	p->tx_frames_512_1023	= GET_STAT(TX_PORT_512B_1023B);
6880 	p->tx_frames_1024_1518	= GET_STAT(TX_PORT_1024B_1518B);
6881 	p->tx_frames_1519_max	= GET_STAT(TX_PORT_1519B_MAX);
6882 	p->tx_drop		= GET_STAT(TX_PORT_DROP);
6883 	p->tx_ppp0		= GET_STAT(TX_PORT_PPP0);
6884 	p->tx_ppp1		= GET_STAT(TX_PORT_PPP1);
6885 	p->tx_ppp2		= GET_STAT(TX_PORT_PPP2);
6886 	p->tx_ppp3		= GET_STAT(TX_PORT_PPP3);
6887 	p->tx_ppp4		= GET_STAT(TX_PORT_PPP4);
6888 	p->tx_ppp5		= GET_STAT(TX_PORT_PPP5);
6889 	p->tx_ppp6		= GET_STAT(TX_PORT_PPP6);
6890 	p->tx_ppp7		= GET_STAT(TX_PORT_PPP7);
6891 
6892 	if (chip_id(adap) >= CHELSIO_T5) {
6893 		if (stat_ctl & F_COUNTPAUSESTATTX) {
6894 			p->tx_frames -= p->tx_pause;
6895 			p->tx_octets -= p->tx_pause * 64;
6896 		}
6897 		if (stat_ctl & F_COUNTPAUSEMCTX)
6898 			p->tx_mcast_frames -= p->tx_pause;
6899 	}
6900 
6901 	p->rx_pause		= GET_STAT(RX_PORT_PAUSE);
6902 	p->rx_octets		= GET_STAT(RX_PORT_BYTES);
6903 	p->rx_frames		= GET_STAT(RX_PORT_FRAMES);
6904 	p->rx_bcast_frames	= GET_STAT(RX_PORT_BCAST);
6905 	p->rx_mcast_frames	= GET_STAT(RX_PORT_MCAST);
6906 	p->rx_ucast_frames	= GET_STAT(RX_PORT_UCAST);
6907 	p->rx_too_long		= GET_STAT(RX_PORT_MTU_ERROR);
6908 	p->rx_jabber		= GET_STAT(RX_PORT_MTU_CRC_ERROR);
6909 	p->rx_len_err		= GET_STAT(RX_PORT_LEN_ERROR);
6910 	p->rx_symbol_err	= GET_STAT(RX_PORT_SYM_ERROR);
6911 	p->rx_runt		= GET_STAT(RX_PORT_LESS_64B);
6912 	p->rx_frames_64		= GET_STAT(RX_PORT_64B);
6913 	p->rx_frames_65_127	= GET_STAT(RX_PORT_65B_127B);
6914 	p->rx_frames_128_255	= GET_STAT(RX_PORT_128B_255B);
6915 	p->rx_frames_256_511	= GET_STAT(RX_PORT_256B_511B);
6916 	p->rx_frames_512_1023	= GET_STAT(RX_PORT_512B_1023B);
6917 	p->rx_frames_1024_1518	= GET_STAT(RX_PORT_1024B_1518B);
6918 	p->rx_frames_1519_max	= GET_STAT(RX_PORT_1519B_MAX);
6919 	p->rx_ppp0		= GET_STAT(RX_PORT_PPP0);
6920 	p->rx_ppp1		= GET_STAT(RX_PORT_PPP1);
6921 	p->rx_ppp2		= GET_STAT(RX_PORT_PPP2);
6922 	p->rx_ppp3		= GET_STAT(RX_PORT_PPP3);
6923 	p->rx_ppp4		= GET_STAT(RX_PORT_PPP4);
6924 	p->rx_ppp5		= GET_STAT(RX_PORT_PPP5);
6925 	p->rx_ppp6		= GET_STAT(RX_PORT_PPP6);
6926 	p->rx_ppp7		= GET_STAT(RX_PORT_PPP7);
6927 
6928 	if (pi->fcs_reg != -1)
6929 		p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base;
6930 
6931 	if (chip_id(adap) >= CHELSIO_T5) {
6932 		if (stat_ctl & F_COUNTPAUSESTATRX) {
6933 			p->rx_frames -= p->rx_pause;
6934 			p->rx_octets -= p->rx_pause * 64;
6935 		}
6936 		if (stat_ctl & F_COUNTPAUSEMCRX)
6937 			p->rx_mcast_frames -= p->rx_pause;
6938 	}
6939 
6940 	p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6941 	p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6942 	p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6943 	p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6944 	p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6945 	p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6946 	p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6947 	p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6948 
6949 #undef GET_STAT
6950 #undef GET_STAT_COM
6951 }
6952 
6953 /**
6954  *	t4_get_lb_stats - collect loopback port statistics
6955  *	@adap: the adapter
6956  *	@idx: the loopback port index
6957  *	@p: the stats structure to fill
6958  *
6959  *	Return HW statistics for the given loopback port.
6960  */
6961 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6962 {
6963 
6964 #define GET_STAT(name) \
6965 	t4_read_reg64(adap, \
6966 	    t4_port_reg(adap, idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))
6967 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
6968 
6969 	p->octets	= GET_STAT(BYTES);
6970 	p->frames	= GET_STAT(FRAMES);
6971 	p->bcast_frames	= GET_STAT(BCAST);
6972 	p->mcast_frames	= GET_STAT(MCAST);
6973 	p->ucast_frames	= GET_STAT(UCAST);
6974 	p->error_frames	= GET_STAT(ERROR);
6975 
6976 	p->frames_64		= GET_STAT(64B);
6977 	p->frames_65_127	= GET_STAT(65B_127B);
6978 	p->frames_128_255	= GET_STAT(128B_255B);
6979 	p->frames_256_511	= GET_STAT(256B_511B);
6980 	p->frames_512_1023	= GET_STAT(512B_1023B);
6981 	p->frames_1024_1518	= GET_STAT(1024B_1518B);
6982 	p->frames_1519_max	= GET_STAT(1519B_MAX);
6983 	p->drop			= GET_STAT(DROP_FRAMES);
6984 
6985 	if (idx < adap->params.nports) {
6986 		u32 bg = adap2pinfo(adap, idx)->mps_bg_map;
6987 
6988 		p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6989 		p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6990 		p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6991 		p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6992 		p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6993 		p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6994 		p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6995 		p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6996 	}
6997 
6998 #undef GET_STAT
6999 #undef GET_STAT_COM
7000 }
7001 
7002 /**
7003  *	t4_wol_magic_enable - enable/disable magic packet WoL
7004  *	@adap: the adapter
7005  *	@port: the physical port index
7006  *	@addr: MAC address expected in magic packets, %NULL to disable
7007  *
7008  *	Enables/disables magic packet wake-on-LAN for the selected port.
7009  */
7010 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
7011 			 const u8 *addr)
7012 {
7013 	u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
7014 
7015 	if (is_t4(adap)) {
7016 		mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
7017 		mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
7018 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7019 	} else {
7020 		mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
7021 		mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
7022 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7023 	}
7024 
7025 	if (addr) {
7026 		t4_write_reg(adap, mag_id_reg_l,
7027 			     (addr[2] << 24) | (addr[3] << 16) |
7028 			     (addr[4] << 8) | addr[5]);
7029 		t4_write_reg(adap, mag_id_reg_h,
7030 			     (addr[0] << 8) | addr[1]);
7031 	}
7032 	t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
7033 			 V_MAGICEN(addr != NULL));
7034 }
7035 
7036 /**
7037  *	t4_wol_pat_enable - enable/disable pattern-based WoL
7038  *	@adap: the adapter
7039  *	@port: the physical port index
7040  *	@map: bitmap of which HW pattern filters to set
7041  *	@mask0: byte mask for bytes 0-63 of a packet
7042  *	@mask1: byte mask for bytes 64-127 of a packet
7043  *	@crc: Ethernet CRC for selected bytes
7044  *	@enable: enable/disable switch
7045  *
7046  *	Sets the pattern filters indicated in @map to mask out the bytes
7047  *	specified in @mask0/@mask1 in received packets and compare the CRC of
7048  *	the resulting packet against @crc.  If @enable is %true pattern-based
7049  *	WoL is enabled, otherwise disabled.
7050  */
7051 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
7052 		      u64 mask0, u64 mask1, unsigned int crc, bool enable)
7053 {
7054 	int i;
7055 	u32 port_cfg_reg;
7056 
7057 	if (is_t4(adap))
7058 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
7059 	else
7060 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
7061 
7062 	if (!enable) {
7063 		t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
7064 		return 0;
7065 	}
7066 	if (map > 0xff)
7067 		return -EINVAL;
7068 
7069 #define EPIO_REG(name) \
7070 	(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
7071 	T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
7072 
7073 	t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
7074 	t4_write_reg(adap, EPIO_REG(DATA2), mask1);
7075 	t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
7076 
7077 	for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
7078 		if (!(map & 1))
7079 			continue;
7080 
7081 		/* write byte masks */
7082 		t4_write_reg(adap, EPIO_REG(DATA0), mask0);
7083 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
7084 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
7085 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7086 			return -ETIMEDOUT;
7087 
7088 		/* write CRC */
7089 		t4_write_reg(adap, EPIO_REG(DATA0), crc);
7090 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
7091 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
7092 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
7093 			return -ETIMEDOUT;
7094 	}
7095 #undef EPIO_REG
7096 
7097 	t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
7098 	return 0;
7099 }
7100 
7101 /*     t4_mk_filtdelwr - create a delete filter WR
7102  *     @ftid: the filter ID
7103  *     @wr: the filter work request to populate
7104  *     @qid: ingress queue to receive the delete notification
7105  *
7106  *     Creates a filter work request to delete the supplied filter.  If @qid is
7107  *     negative the delete notification is suppressed.
7108  */
7109 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
7110 {
7111 	memset(wr, 0, sizeof(*wr));
7112 	wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
7113 	wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
7114 	wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
7115 				    V_FW_FILTER_WR_NOREPLY(qid < 0));
7116 	wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
7117 	if (qid >= 0)
7118 		wr->rx_chan_rx_rpl_iq =
7119 				cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
7120 }
7121 
7122 #define INIT_CMD(var, cmd, rd_wr) do { \
7123 	(var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
7124 					F_FW_CMD_REQUEST | \
7125 					F_FW_CMD_##rd_wr); \
7126 	(var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
7127 } while (0)
7128 
7129 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
7130 			  u32 addr, u32 val)
7131 {
7132 	u32 ldst_addrspace;
7133 	struct fw_ldst_cmd c;
7134 
7135 	memset(&c, 0, sizeof(c));
7136 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
7137 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7138 					F_FW_CMD_REQUEST |
7139 					F_FW_CMD_WRITE |
7140 					ldst_addrspace);
7141 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7142 	c.u.addrval.addr = cpu_to_be32(addr);
7143 	c.u.addrval.val = cpu_to_be32(val);
7144 
7145 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7146 }
7147 
7148 /**
7149  *	t4_mdio_rd - read a PHY register through MDIO
7150  *	@adap: the adapter
7151  *	@mbox: mailbox to use for the FW command
7152  *	@phy_addr: the PHY address
7153  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
7154  *	@reg: the register to read
7155  *	@valp: where to store the value
7156  *
7157  *	Issues a FW command through the given mailbox to read a PHY register.
7158  */
7159 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7160 	       unsigned int mmd, unsigned int reg, unsigned int *valp)
7161 {
7162 	int ret;
7163 	u32 ldst_addrspace;
7164 	struct fw_ldst_cmd c;
7165 
7166 	memset(&c, 0, sizeof(c));
7167 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7168 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7169 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
7170 					ldst_addrspace);
7171 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7172 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7173 					 V_FW_LDST_CMD_MMD(mmd));
7174 	c.u.mdio.raddr = cpu_to_be16(reg);
7175 
7176 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7177 	if (ret == 0)
7178 		*valp = be16_to_cpu(c.u.mdio.rval);
7179 	return ret;
7180 }
7181 
7182 /**
7183  *	t4_mdio_wr - write a PHY register through MDIO
7184  *	@adap: the adapter
7185  *	@mbox: mailbox to use for the FW command
7186  *	@phy_addr: the PHY address
7187  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
7188  *	@reg: the register to write
7189  *	@valp: value to write
7190  *
7191  *	Issues a FW command through the given mailbox to write a PHY register.
7192  */
7193 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
7194 	       unsigned int mmd, unsigned int reg, unsigned int val)
7195 {
7196 	u32 ldst_addrspace;
7197 	struct fw_ldst_cmd c;
7198 
7199 	memset(&c, 0, sizeof(c));
7200 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
7201 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7202 					F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7203 					ldst_addrspace);
7204 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7205 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
7206 					 V_FW_LDST_CMD_MMD(mmd));
7207 	c.u.mdio.raddr = cpu_to_be16(reg);
7208 	c.u.mdio.rval = cpu_to_be16(val);
7209 
7210 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7211 }
7212 
7213 /**
7214  *
7215  *	t4_sge_decode_idma_state - decode the idma state
7216  *	@adap: the adapter
7217  *	@state: the state idma is stuck in
7218  */
7219 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
7220 {
7221 	static const char * const t4_decode[] = {
7222 		"IDMA_IDLE",
7223 		"IDMA_PUSH_MORE_CPL_FIFO",
7224 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7225 		"Not used",
7226 		"IDMA_PHYSADDR_SEND_PCIEHDR",
7227 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7228 		"IDMA_PHYSADDR_SEND_PAYLOAD",
7229 		"IDMA_SEND_FIFO_TO_IMSG",
7230 		"IDMA_FL_REQ_DATA_FL_PREP",
7231 		"IDMA_FL_REQ_DATA_FL",
7232 		"IDMA_FL_DROP",
7233 		"IDMA_FL_H_REQ_HEADER_FL",
7234 		"IDMA_FL_H_SEND_PCIEHDR",
7235 		"IDMA_FL_H_PUSH_CPL_FIFO",
7236 		"IDMA_FL_H_SEND_CPL",
7237 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
7238 		"IDMA_FL_H_SEND_IP_HDR",
7239 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
7240 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
7241 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
7242 		"IDMA_FL_D_SEND_PCIEHDR",
7243 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7244 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
7245 		"IDMA_FL_SEND_PCIEHDR",
7246 		"IDMA_FL_PUSH_CPL_FIFO",
7247 		"IDMA_FL_SEND_CPL",
7248 		"IDMA_FL_SEND_PAYLOAD_FIRST",
7249 		"IDMA_FL_SEND_PAYLOAD",
7250 		"IDMA_FL_REQ_NEXT_DATA_FL",
7251 		"IDMA_FL_SEND_NEXT_PCIEHDR",
7252 		"IDMA_FL_SEND_PADDING",
7253 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
7254 		"IDMA_FL_SEND_FIFO_TO_IMSG",
7255 		"IDMA_FL_REQ_DATAFL_DONE",
7256 		"IDMA_FL_REQ_HEADERFL_DONE",
7257 	};
7258 	static const char * const t5_decode[] = {
7259 		"IDMA_IDLE",
7260 		"IDMA_ALMOST_IDLE",
7261 		"IDMA_PUSH_MORE_CPL_FIFO",
7262 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7263 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7264 		"IDMA_PHYSADDR_SEND_PCIEHDR",
7265 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7266 		"IDMA_PHYSADDR_SEND_PAYLOAD",
7267 		"IDMA_SEND_FIFO_TO_IMSG",
7268 		"IDMA_FL_REQ_DATA_FL",
7269 		"IDMA_FL_DROP",
7270 		"IDMA_FL_DROP_SEND_INC",
7271 		"IDMA_FL_H_REQ_HEADER_FL",
7272 		"IDMA_FL_H_SEND_PCIEHDR",
7273 		"IDMA_FL_H_PUSH_CPL_FIFO",
7274 		"IDMA_FL_H_SEND_CPL",
7275 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
7276 		"IDMA_FL_H_SEND_IP_HDR",
7277 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
7278 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
7279 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
7280 		"IDMA_FL_D_SEND_PCIEHDR",
7281 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7282 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
7283 		"IDMA_FL_SEND_PCIEHDR",
7284 		"IDMA_FL_PUSH_CPL_FIFO",
7285 		"IDMA_FL_SEND_CPL",
7286 		"IDMA_FL_SEND_PAYLOAD_FIRST",
7287 		"IDMA_FL_SEND_PAYLOAD",
7288 		"IDMA_FL_REQ_NEXT_DATA_FL",
7289 		"IDMA_FL_SEND_NEXT_PCIEHDR",
7290 		"IDMA_FL_SEND_PADDING",
7291 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
7292 	};
7293 	static const char * const t6_decode[] = {
7294 		"IDMA_IDLE",
7295 		"IDMA_PUSH_MORE_CPL_FIFO",
7296 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
7297 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
7298 		"IDMA_PHYSADDR_SEND_PCIEHDR",
7299 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
7300 		"IDMA_PHYSADDR_SEND_PAYLOAD",
7301 		"IDMA_FL_REQ_DATA_FL",
7302 		"IDMA_FL_DROP",
7303 		"IDMA_FL_DROP_SEND_INC",
7304 		"IDMA_FL_H_REQ_HEADER_FL",
7305 		"IDMA_FL_H_SEND_PCIEHDR",
7306 		"IDMA_FL_H_PUSH_CPL_FIFO",
7307 		"IDMA_FL_H_SEND_CPL",
7308 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
7309 		"IDMA_FL_H_SEND_IP_HDR",
7310 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
7311 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
7312 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
7313 		"IDMA_FL_D_SEND_PCIEHDR",
7314 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
7315 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
7316 		"IDMA_FL_SEND_PCIEHDR",
7317 		"IDMA_FL_PUSH_CPL_FIFO",
7318 		"IDMA_FL_SEND_CPL",
7319 		"IDMA_FL_SEND_PAYLOAD_FIRST",
7320 		"IDMA_FL_SEND_PAYLOAD",
7321 		"IDMA_FL_REQ_NEXT_DATA_FL",
7322 		"IDMA_FL_SEND_NEXT_PCIEHDR",
7323 		"IDMA_FL_SEND_PADDING",
7324 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
7325 	};
7326 	static const u32 sge_regs[] = {
7327 		A_SGE_DEBUG_DATA_LOW_INDEX_2,
7328 		A_SGE_DEBUG_DATA_LOW_INDEX_3,
7329 		A_SGE_DEBUG_DATA_HIGH_INDEX_10,
7330 	};
7331 	const char * const *sge_idma_decode;
7332 	int sge_idma_decode_nstates;
7333 	int i;
7334 	unsigned int chip_version = chip_id(adapter);
7335 
7336 	/* Select the right set of decode strings to dump depending on the
7337 	 * adapter chip type.
7338 	 */
7339 	switch (chip_version) {
7340 	case CHELSIO_T4:
7341 		sge_idma_decode = (const char * const *)t4_decode;
7342 		sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
7343 		break;
7344 
7345 	case CHELSIO_T5:
7346 		sge_idma_decode = (const char * const *)t5_decode;
7347 		sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
7348 		break;
7349 
7350 	case CHELSIO_T6:
7351 		sge_idma_decode = (const char * const *)t6_decode;
7352 		sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
7353 		break;
7354 
7355 	default:
7356 		CH_ERR(adapter,	"Unsupported chip version %d\n", chip_version);
7357 		return;
7358 	}
7359 
7360 	if (state < sge_idma_decode_nstates)
7361 		CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
7362 	else
7363 		CH_WARN(adapter, "idma state %d unknown\n", state);
7364 
7365 	for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
7366 		CH_WARN(adapter, "SGE register %#x value %#x\n",
7367 			sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
7368 }
7369 
7370 /**
7371  *      t4_sge_ctxt_flush - flush the SGE context cache
7372  *      @adap: the adapter
7373  *      @mbox: mailbox to use for the FW command
7374  *
7375  *      Issues a FW command through the given mailbox to flush the
7376  *      SGE context cache.
7377  */
7378 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
7379 {
7380 	int ret;
7381 	u32 ldst_addrspace;
7382 	struct fw_ldst_cmd c;
7383 
7384 	memset(&c, 0, sizeof(c));
7385 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ?
7386 						 FW_LDST_ADDRSPC_SGE_EGRC :
7387 						 FW_LDST_ADDRSPC_SGE_INGC);
7388 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
7389 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
7390 					ldst_addrspace);
7391 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
7392 	c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
7393 
7394 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7395 	return ret;
7396 }
7397 
7398 /**
7399  *      t4_fw_hello - establish communication with FW
7400  *      @adap: the adapter
7401  *      @mbox: mailbox to use for the FW command
7402  *      @evt_mbox: mailbox to receive async FW events
7403  *      @master: specifies the caller's willingness to be the device master
7404  *	@state: returns the current device state (if non-NULL)
7405  *
7406  *	Issues a command to establish communication with FW.  Returns either
7407  *	an error (negative integer) or the mailbox of the Master PF.
7408  */
7409 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
7410 		enum dev_master master, enum dev_state *state)
7411 {
7412 	int ret;
7413 	struct fw_hello_cmd c;
7414 	u32 v;
7415 	unsigned int master_mbox;
7416 	int retries = FW_CMD_HELLO_RETRIES;
7417 
7418 retry:
7419 	memset(&c, 0, sizeof(c));
7420 	INIT_CMD(c, HELLO, WRITE);
7421 	c.err_to_clearinit = cpu_to_be32(
7422 		V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
7423 		V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
7424 		V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
7425 					mbox : M_FW_HELLO_CMD_MBMASTER) |
7426 		V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
7427 		V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
7428 		F_FW_HELLO_CMD_CLEARINIT);
7429 
7430 	/*
7431 	 * Issue the HELLO command to the firmware.  If it's not successful
7432 	 * but indicates that we got a "busy" or "timeout" condition, retry
7433 	 * the HELLO until we exhaust our retry limit.  If we do exceed our
7434 	 * retry limit, check to see if the firmware left us any error
7435 	 * information and report that if so ...
7436 	 */
7437 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7438 	if (ret != FW_SUCCESS) {
7439 		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
7440 			goto retry;
7441 		return ret;
7442 	}
7443 
7444 	v = be32_to_cpu(c.err_to_clearinit);
7445 	master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
7446 	if (state) {
7447 		if (v & F_FW_HELLO_CMD_ERR)
7448 			*state = DEV_STATE_ERR;
7449 		else if (v & F_FW_HELLO_CMD_INIT)
7450 			*state = DEV_STATE_INIT;
7451 		else
7452 			*state = DEV_STATE_UNINIT;
7453 	}
7454 
7455 	/*
7456 	 * If we're not the Master PF then we need to wait around for the
7457 	 * Master PF Driver to finish setting up the adapter.
7458 	 *
7459 	 * Note that we also do this wait if we're a non-Master-capable PF and
7460 	 * there is no current Master PF; a Master PF may show up momentarily
7461 	 * and we wouldn't want to fail pointlessly.  (This can happen when an
7462 	 * OS loads lots of different drivers rapidly at the same time).  In
7463 	 * this case, the Master PF returned by the firmware will be
7464 	 * M_PCIE_FW_MASTER so the test below will work ...
7465 	 */
7466 	if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
7467 	    master_mbox != mbox) {
7468 		int waiting = FW_CMD_HELLO_TIMEOUT;
7469 
7470 		/*
7471 		 * Wait for the firmware to either indicate an error or
7472 		 * initialized state.  If we see either of these we bail out
7473 		 * and report the issue to the caller.  If we exhaust the
7474 		 * "hello timeout" and we haven't exhausted our retries, try
7475 		 * again.  Otherwise bail with a timeout error.
7476 		 */
7477 		for (;;) {
7478 			u32 pcie_fw;
7479 
7480 			msleep(50);
7481 			waiting -= 50;
7482 
7483 			/*
7484 			 * If neither Error nor Initialialized are indicated
7485 			 * by the firmware keep waiting till we exhaust our
7486 			 * timeout ... and then retry if we haven't exhausted
7487 			 * our retries ...
7488 			 */
7489 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
7490 			if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
7491 				if (waiting <= 0) {
7492 					if (retries-- > 0)
7493 						goto retry;
7494 
7495 					return -ETIMEDOUT;
7496 				}
7497 				continue;
7498 			}
7499 
7500 			/*
7501 			 * We either have an Error or Initialized condition
7502 			 * report errors preferentially.
7503 			 */
7504 			if (state) {
7505 				if (pcie_fw & F_PCIE_FW_ERR)
7506 					*state = DEV_STATE_ERR;
7507 				else if (pcie_fw & F_PCIE_FW_INIT)
7508 					*state = DEV_STATE_INIT;
7509 			}
7510 
7511 			/*
7512 			 * If we arrived before a Master PF was selected and
7513 			 * there's not a valid Master PF, grab its identity
7514 			 * for our caller.
7515 			 */
7516 			if (master_mbox == M_PCIE_FW_MASTER &&
7517 			    (pcie_fw & F_PCIE_FW_MASTER_VLD))
7518 				master_mbox = G_PCIE_FW_MASTER(pcie_fw);
7519 			break;
7520 		}
7521 	}
7522 
7523 	return master_mbox;
7524 }
7525 
7526 /**
7527  *	t4_fw_bye - end communication with FW
7528  *	@adap: the adapter
7529  *	@mbox: mailbox to use for the FW command
7530  *
7531  *	Issues a command to terminate communication with FW.
7532  */
7533 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
7534 {
7535 	struct fw_bye_cmd c;
7536 
7537 	memset(&c, 0, sizeof(c));
7538 	INIT_CMD(c, BYE, WRITE);
7539 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7540 }
7541 
7542 /**
7543  *	t4_fw_reset - issue a reset to FW
7544  *	@adap: the adapter
7545  *	@mbox: mailbox to use for the FW command
7546  *	@reset: specifies the type of reset to perform
7547  *
7548  *	Issues a reset command of the specified type to FW.
7549  */
7550 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
7551 {
7552 	struct fw_reset_cmd c;
7553 
7554 	memset(&c, 0, sizeof(c));
7555 	INIT_CMD(c, RESET, WRITE);
7556 	c.val = cpu_to_be32(reset);
7557 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7558 }
7559 
7560 /**
7561  *	t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7562  *	@adap: the adapter
7563  *	@mbox: mailbox to use for the FW RESET command (if desired)
7564  *	@force: force uP into RESET even if FW RESET command fails
7565  *
7566  *	Issues a RESET command to firmware (if desired) with a HALT indication
7567  *	and then puts the microprocessor into RESET state.  The RESET command
7568  *	will only be issued if a legitimate mailbox is provided (mbox <=
7569  *	M_PCIE_FW_MASTER).
7570  *
7571  *	This is generally used in order for the host to safely manipulate the
7572  *	adapter without fear of conflicting with whatever the firmware might
7573  *	be doing.  The only way out of this state is to RESTART the firmware
7574  *	...
7575  */
7576 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7577 {
7578 	int ret = 0;
7579 
7580 	/*
7581 	 * If a legitimate mailbox is provided, issue a RESET command
7582 	 * with a HALT indication.
7583 	 */
7584 	if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) {
7585 		struct fw_reset_cmd c;
7586 
7587 		memset(&c, 0, sizeof(c));
7588 		INIT_CMD(c, RESET, WRITE);
7589 		c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
7590 		c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
7591 		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7592 	}
7593 
7594 	/*
7595 	 * Normally we won't complete the operation if the firmware RESET
7596 	 * command fails but if our caller insists we'll go ahead and put the
7597 	 * uP into RESET.  This can be useful if the firmware is hung or even
7598 	 * missing ...  We'll have to take the risk of putting the uP into
7599 	 * RESET without the cooperation of firmware in that case.
7600 	 *
7601 	 * We also force the firmware's HALT flag to be on in case we bypassed
7602 	 * the firmware RESET command above or we're dealing with old firmware
7603 	 * which doesn't have the HALT capability.  This will serve as a flag
7604 	 * for the incoming firmware to know that it's coming out of a HALT
7605 	 * rather than a RESET ... if it's new enough to understand that ...
7606 	 */
7607 	if (ret == 0 || force) {
7608 		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
7609 		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
7610 				 F_PCIE_FW_HALT);
7611 	}
7612 
7613 	/*
7614 	 * And we always return the result of the firmware RESET command
7615 	 * even when we force the uP into RESET ...
7616 	 */
7617 	return ret;
7618 }
7619 
7620 /**
7621  *	t4_fw_restart - restart the firmware by taking the uP out of RESET
7622  *	@adap: the adapter
7623  *
7624  *	Restart firmware previously halted by t4_fw_halt().  On successful
7625  *	return the previous PF Master remains as the new PF Master and there
7626  *	is no need to issue a new HELLO command, etc.
7627  */
7628 int t4_fw_restart(struct adapter *adap, unsigned int mbox)
7629 {
7630 	int ms;
7631 
7632 	t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
7633 	for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7634 		if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
7635 			return FW_SUCCESS;
7636 		msleep(100);
7637 		ms += 100;
7638 	}
7639 
7640 	return -ETIMEDOUT;
7641 }
7642 
7643 /**
7644  *	t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7645  *	@adap: the adapter
7646  *	@mbox: mailbox to use for the FW RESET command (if desired)
7647  *	@fw_data: the firmware image to write
7648  *	@size: image size
7649  *	@force: force upgrade even if firmware doesn't cooperate
7650  *
7651  *	Perform all of the steps necessary for upgrading an adapter's
7652  *	firmware image.  Normally this requires the cooperation of the
7653  *	existing firmware in order to halt all existing activities
7654  *	but if an invalid mailbox token is passed in we skip that step
7655  *	(though we'll still put the adapter microprocessor into RESET in
7656  *	that case).
7657  *
7658  *	On successful return the new firmware will have been loaded and
7659  *	the adapter will have been fully RESET losing all previous setup
7660  *	state.  On unsuccessful return the adapter may be completely hosed ...
7661  *	positive errno indicates that the adapter is ~probably~ intact, a
7662  *	negative errno indicates that things are looking bad ...
7663  */
7664 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7665 		  const u8 *fw_data, unsigned int size, int force)
7666 {
7667 	const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7668 	unsigned int bootstrap =
7669 	    be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
7670 	int ret;
7671 
7672 	if (!t4_fw_matches_chip(adap, fw_hdr))
7673 		return -EINVAL;
7674 
7675 	if (!bootstrap) {
7676 		ret = t4_fw_halt(adap, mbox, force);
7677 		if (ret < 0 && !force)
7678 			return ret;
7679 	}
7680 
7681 	ret = t4_load_fw(adap, fw_data, size);
7682 	if (ret < 0 || bootstrap)
7683 		return ret;
7684 
7685 	return t4_fw_restart(adap, mbox);
7686 }
7687 
7688 /**
7689  *	t4_fw_initialize - ask FW to initialize the device
7690  *	@adap: the adapter
7691  *	@mbox: mailbox to use for the FW command
7692  *
7693  *	Issues a command to FW to partially initialize the device.  This
7694  *	performs initialization that generally doesn't depend on user input.
7695  */
7696 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7697 {
7698 	struct fw_initialize_cmd c;
7699 
7700 	memset(&c, 0, sizeof(c));
7701 	INIT_CMD(c, INITIALIZE, WRITE);
7702 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7703 }
7704 
7705 /**
7706  *	t4_query_params_rw - query FW or device parameters
7707  *	@adap: the adapter
7708  *	@mbox: mailbox to use for the FW command
7709  *	@pf: the PF
7710  *	@vf: the VF
7711  *	@nparams: the number of parameters
7712  *	@params: the parameter names
7713  *	@val: the parameter values
7714  *	@rw: Write and read flag
7715  *
7716  *	Reads the value of FW or device parameters.  Up to 7 parameters can be
7717  *	queried at once.
7718  */
7719 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7720 		       unsigned int vf, unsigned int nparams, const u32 *params,
7721 		       u32 *val, int rw)
7722 {
7723 	int i, ret;
7724 	struct fw_params_cmd c;
7725 	__be32 *p = &c.param[0].mnem;
7726 
7727 	if (nparams > 7)
7728 		return -EINVAL;
7729 
7730 	memset(&c, 0, sizeof(c));
7731 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7732 				  F_FW_CMD_REQUEST | F_FW_CMD_READ |
7733 				  V_FW_PARAMS_CMD_PFN(pf) |
7734 				  V_FW_PARAMS_CMD_VFN(vf));
7735 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7736 
7737 	for (i = 0; i < nparams; i++) {
7738 		*p++ = cpu_to_be32(*params++);
7739 		if (rw)
7740 			*p = cpu_to_be32(*(val + i));
7741 		p++;
7742 	}
7743 
7744 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7745 
7746 	/*
7747 	 * We always copy back the results, even if there's an error.  We'll
7748 	 * get an error if any of the parameters was unknown to the Firmware,
7749 	 * but there will be results for the others ...  (Older Firmware
7750 	 * stopped at the first unknown parameter; newer Firmware processes
7751 	 * them all and flags the unknown parameters with a return value of
7752 	 * ~0UL.)
7753 	 */
7754 	for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7755 		*val++ = be32_to_cpu(*p);
7756 
7757 	return ret;
7758 }
7759 
7760 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7761 		    unsigned int vf, unsigned int nparams, const u32 *params,
7762 		    u32 *val)
7763 {
7764 	return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
7765 }
7766 
7767 /**
7768  *      t4_set_params_timeout - sets FW or device parameters
7769  *      @adap: the adapter
7770  *      @mbox: mailbox to use for the FW command
7771  *      @pf: the PF
7772  *      @vf: the VF
7773  *      @nparams: the number of parameters
7774  *      @params: the parameter names
7775  *      @val: the parameter values
7776  *      @timeout: the timeout time
7777  *
7778  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
7779  *      specified at once.
7780  */
7781 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7782 			  unsigned int pf, unsigned int vf,
7783 			  unsigned int nparams, const u32 *params,
7784 			  const u32 *val, int timeout)
7785 {
7786 	struct fw_params_cmd c;
7787 	__be32 *p = &c.param[0].mnem;
7788 
7789 	if (nparams > 7)
7790 		return -EINVAL;
7791 
7792 	memset(&c, 0, sizeof(c));
7793 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
7794 				  F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7795 				  V_FW_PARAMS_CMD_PFN(pf) |
7796 				  V_FW_PARAMS_CMD_VFN(vf));
7797 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7798 
7799 	while (nparams--) {
7800 		*p++ = cpu_to_be32(*params++);
7801 		*p++ = cpu_to_be32(*val++);
7802 	}
7803 
7804 	return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7805 }
7806 
7807 /**
7808  *	t4_set_params - sets FW or device parameters
7809  *	@adap: the adapter
7810  *	@mbox: mailbox to use for the FW command
7811  *	@pf: the PF
7812  *	@vf: the VF
7813  *	@nparams: the number of parameters
7814  *	@params: the parameter names
7815  *	@val: the parameter values
7816  *
7817  *	Sets the value of FW or device parameters.  Up to 7 parameters can be
7818  *	specified at once.
7819  */
7820 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7821 		  unsigned int vf, unsigned int nparams, const u32 *params,
7822 		  const u32 *val)
7823 {
7824 	return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7825 				     FW_CMD_MAX_TIMEOUT);
7826 }
7827 
7828 /**
7829  *	t4_cfg_pfvf - configure PF/VF resource limits
7830  *	@adap: the adapter
7831  *	@mbox: mailbox to use for the FW command
7832  *	@pf: the PF being configured
7833  *	@vf: the VF being configured
7834  *	@txq: the max number of egress queues
7835  *	@txq_eth_ctrl: the max number of egress Ethernet or control queues
7836  *	@rxqi: the max number of interrupt-capable ingress queues
7837  *	@rxq: the max number of interruptless ingress queues
7838  *	@tc: the PCI traffic class
7839  *	@vi: the max number of virtual interfaces
7840  *	@cmask: the channel access rights mask for the PF/VF
7841  *	@pmask: the port access rights mask for the PF/VF
7842  *	@nexact: the maximum number of exact MPS filters
7843  *	@rcaps: read capabilities
7844  *	@wxcaps: write/execute capabilities
7845  *
7846  *	Configures resource limits and capabilities for a physical or virtual
7847  *	function.
7848  */
7849 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7850 		unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7851 		unsigned int rxqi, unsigned int rxq, unsigned int tc,
7852 		unsigned int vi, unsigned int cmask, unsigned int pmask,
7853 		unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7854 {
7855 	struct fw_pfvf_cmd c;
7856 
7857 	memset(&c, 0, sizeof(c));
7858 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
7859 				  F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
7860 				  V_FW_PFVF_CMD_VFN(vf));
7861 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7862 	c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
7863 				     V_FW_PFVF_CMD_NIQ(rxq));
7864 	c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
7865 				    V_FW_PFVF_CMD_PMASK(pmask) |
7866 				    V_FW_PFVF_CMD_NEQ(txq));
7867 	c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
7868 				      V_FW_PFVF_CMD_NVI(vi) |
7869 				      V_FW_PFVF_CMD_NEXACTF(nexact));
7870 	c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
7871 				     V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
7872 				     V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
7873 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7874 }
7875 
7876 /**
7877  *	t4_alloc_vi_func - allocate a virtual interface
7878  *	@adap: the adapter
7879  *	@mbox: mailbox to use for the FW command
7880  *	@port: physical port associated with the VI
7881  *	@pf: the PF owning the VI
7882  *	@vf: the VF owning the VI
7883  *	@nmac: number of MAC addresses needed (1 to 5)
7884  *	@mac: the MAC addresses of the VI
7885  *	@rss_size: size of RSS table slice associated with this VI
7886  *	@portfunc: which Port Application Function MAC Address is desired
7887  *	@idstype: Intrusion Detection Type
7888  *
7889  *	Allocates a virtual interface for the given physical port.  If @mac is
7890  *	not %NULL it contains the MAC addresses of the VI as assigned by FW.
7891  *	If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
7892  *	@mac should be large enough to hold @nmac Ethernet addresses, they are
7893  *	stored consecutively so the space needed is @nmac * 6 bytes.
7894  *	Returns a negative error number or the non-negative VI id.
7895  */
7896 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
7897 		     unsigned int port, unsigned int pf, unsigned int vf,
7898 		     unsigned int nmac, u8 *mac, u16 *rss_size,
7899 		     uint8_t *vfvld, uint16_t *vin,
7900 		     unsigned int portfunc, unsigned int idstype)
7901 {
7902 	int ret;
7903 	struct fw_vi_cmd c;
7904 
7905 	memset(&c, 0, sizeof(c));
7906 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
7907 				  F_FW_CMD_WRITE | F_FW_CMD_EXEC |
7908 				  V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
7909 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
7910 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
7911 				     V_FW_VI_CMD_FUNC(portfunc));
7912 	c.portid_pkd = V_FW_VI_CMD_PORTID(port);
7913 	c.nmac = nmac - 1;
7914 	if(!rss_size)
7915 		c.norss_rsssize = F_FW_VI_CMD_NORSS;
7916 
7917 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7918 	if (ret)
7919 		return ret;
7920 	ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
7921 
7922 	if (mac) {
7923 		memcpy(mac, c.mac, sizeof(c.mac));
7924 		switch (nmac) {
7925 		case 5:
7926 			memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7927 		case 4:
7928 			memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7929 		case 3:
7930 			memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7931 		case 2:
7932 			memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
7933 		}
7934 	}
7935 	if (rss_size)
7936 		*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
7937 	if (vfvld) {
7938 		*vfvld = adap->params.viid_smt_extn_support ?
7939 		    G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) :
7940 		    G_FW_VIID_VIVLD(ret);
7941 	}
7942 	if (vin) {
7943 		*vin = adap->params.viid_smt_extn_support ?
7944 		    G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) :
7945 		    G_FW_VIID_VIN(ret);
7946 	}
7947 
7948 	return ret;
7949 }
7950 
7951 /**
7952  *      t4_alloc_vi - allocate an [Ethernet Function] virtual interface
7953  *      @adap: the adapter
7954  *      @mbox: mailbox to use for the FW command
7955  *      @port: physical port associated with the VI
7956  *      @pf: the PF owning the VI
7957  *      @vf: the VF owning the VI
7958  *      @nmac: number of MAC addresses needed (1 to 5)
7959  *      @mac: the MAC addresses of the VI
7960  *      @rss_size: size of RSS table slice associated with this VI
7961  *
7962  *	backwards compatible and convieniance routine to allocate a Virtual
7963  *	Interface with a Ethernet Port Application Function and Intrustion
7964  *	Detection System disabled.
7965  */
7966 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7967 		unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7968 		u16 *rss_size, uint8_t *vfvld, uint16_t *vin)
7969 {
7970 	return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
7971 				vfvld, vin, FW_VI_FUNC_ETH, 0);
7972 }
7973 
7974 /**
7975  * 	t4_free_vi - free a virtual interface
7976  * 	@adap: the adapter
7977  * 	@mbox: mailbox to use for the FW command
7978  * 	@pf: the PF owning the VI
7979  * 	@vf: the VF owning the VI
7980  * 	@viid: virtual interface identifiler
7981  *
7982  * 	Free a previously allocated virtual interface.
7983  */
7984 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7985 	       unsigned int vf, unsigned int viid)
7986 {
7987 	struct fw_vi_cmd c;
7988 
7989 	memset(&c, 0, sizeof(c));
7990 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
7991 				  F_FW_CMD_REQUEST |
7992 				  F_FW_CMD_EXEC |
7993 				  V_FW_VI_CMD_PFN(pf) |
7994 				  V_FW_VI_CMD_VFN(vf));
7995 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
7996 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
7997 
7998 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7999 }
8000 
8001 /**
8002  *	t4_set_rxmode - set Rx properties of a virtual interface
8003  *	@adap: the adapter
8004  *	@mbox: mailbox to use for the FW command
8005  *	@viid: the VI id
8006  *	@mtu: the new MTU or -1
8007  *	@promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
8008  *	@all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
8009  *	@bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
8010  *	@vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
8011  *	@sleep_ok: if true we may sleep while awaiting command completion
8012  *
8013  *	Sets Rx properties of a virtual interface.
8014  */
8015 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
8016 		  int mtu, int promisc, int all_multi, int bcast, int vlanex,
8017 		  bool sleep_ok)
8018 {
8019 	struct fw_vi_rxmode_cmd c;
8020 
8021 	/* convert to FW values */
8022 	if (mtu < 0)
8023 		mtu = M_FW_VI_RXMODE_CMD_MTU;
8024 	if (promisc < 0)
8025 		promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
8026 	if (all_multi < 0)
8027 		all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
8028 	if (bcast < 0)
8029 		bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
8030 	if (vlanex < 0)
8031 		vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
8032 
8033 	memset(&c, 0, sizeof(c));
8034 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
8035 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8036 				   V_FW_VI_RXMODE_CMD_VIID(viid));
8037 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
8038 	c.mtu_to_vlanexen =
8039 		cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
8040 			    V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
8041 			    V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
8042 			    V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
8043 			    V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
8044 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8045 }
8046 
8047 /**
8048  *	t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
8049  *	@adap: the adapter
8050  *	@viid: the VI id
8051  *	@mac: the MAC address
8052  *	@mask: the mask
8053  *	@vni: the VNI id for the tunnel protocol
8054  *	@vni_mask: mask for the VNI id
8055  *	@dip_hit: to enable DIP match for the MPS entry
8056  *	@lookup_type: MAC address for inner (1) or outer (0) header
8057  *	@sleep_ok: call is allowed to sleep
8058  *
8059  *	Allocates an MPS entry with specified MAC address and VNI value.
8060  *
8061  *	Returns a negative error number or the allocated index for this mac.
8062  */
8063 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
8064 			    const u8 *addr, const u8 *mask, unsigned int vni,
8065 			    unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
8066 			    bool sleep_ok)
8067 {
8068 	struct fw_vi_mac_cmd c;
8069 	struct fw_vi_mac_vni *p = c.u.exact_vni;
8070 	int ret = 0;
8071 	u32 val;
8072 
8073 	memset(&c, 0, sizeof(c));
8074 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8075 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8076 				   V_FW_VI_MAC_CMD_VIID(viid));
8077 	val = V_FW_CMD_LEN16(1) |
8078 	      V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI);
8079 	c.freemacs_to_len16 = cpu_to_be32(val);
8080 	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8081 				      V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8082 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
8083 	memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
8084 
8085 	p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) |
8086 					    V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) |
8087 					    V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type));
8088 	p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask));
8089 
8090 	ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8091 	if (ret == 0)
8092 		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8093 	return ret;
8094 }
8095 
8096 /**
8097  *	t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
8098  *	@adap: the adapter
8099  *	@viid: the VI id
8100  *	@mac: the MAC address
8101  *	@mask: the mask
8102  *	@idx: index at which to add this entry
8103  *	@port_id: the port index
8104  *	@lookup_type: MAC address for inner (1) or outer (0) header
8105  *	@sleep_ok: call is allowed to sleep
8106  *
8107  *	Adds the mac entry at the specified index using raw mac interface.
8108  *
8109  *	Returns a negative error number or the allocated index for this mac.
8110  */
8111 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
8112 			  const u8 *addr, const u8 *mask, unsigned int idx,
8113 			  u8 lookup_type, u8 port_id, bool sleep_ok)
8114 {
8115 	int ret = 0;
8116 	struct fw_vi_mac_cmd c;
8117 	struct fw_vi_mac_raw *p = &c.u.raw;
8118 	u32 val;
8119 
8120 	memset(&c, 0, sizeof(c));
8121 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8122 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8123 				   V_FW_VI_MAC_CMD_VIID(viid));
8124 	val = V_FW_CMD_LEN16(1) |
8125 	      V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
8126 	c.freemacs_to_len16 = cpu_to_be32(val);
8127 
8128 	/* Specify that this is an inner mac address */
8129 	p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx));
8130 
8131 	/* Lookup Type. Outer header: 0, Inner header: 1 */
8132 	p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
8133 				   V_DATAPORTNUM(port_id));
8134 	/* Lookup mask and port mask */
8135 	p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
8136 				    V_DATAPORTNUM(M_DATAPORTNUM));
8137 
8138 	/* Copy the address and the mask */
8139 	memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
8140 	memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
8141 
8142 	ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8143 	if (ret == 0) {
8144 		ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd));
8145 		if (ret != idx)
8146 			ret = -ENOMEM;
8147 	}
8148 
8149 	return ret;
8150 }
8151 
8152 /**
8153  *	t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
8154  *	@adap: the adapter
8155  *	@mbox: mailbox to use for the FW command
8156  *	@viid: the VI id
8157  *	@free: if true any existing filters for this VI id are first removed
8158  *	@naddr: the number of MAC addresses to allocate filters for (up to 7)
8159  *	@addr: the MAC address(es)
8160  *	@idx: where to store the index of each allocated filter
8161  *	@hash: pointer to hash address filter bitmap
8162  *	@sleep_ok: call is allowed to sleep
8163  *
8164  *	Allocates an exact-match filter for each of the supplied addresses and
8165  *	sets it to the corresponding address.  If @idx is not %NULL it should
8166  *	have at least @naddr entries, each of which will be set to the index of
8167  *	the filter allocated for the corresponding MAC address.  If a filter
8168  *	could not be allocated for an address its index is set to 0xffff.
8169  *	If @hash is not %NULL addresses that fail to allocate an exact filter
8170  *	are hashed and update the hash filter bitmap pointed at by @hash.
8171  *
8172  *	Returns a negative error number or the number of filters allocated.
8173  */
8174 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
8175 		      unsigned int viid, bool free, unsigned int naddr,
8176 		      const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
8177 {
8178 	int offset, ret = 0;
8179 	struct fw_vi_mac_cmd c;
8180 	unsigned int nfilters = 0;
8181 	unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8182 	unsigned int rem = naddr;
8183 
8184 	if (naddr > max_naddr)
8185 		return -EINVAL;
8186 
8187 	for (offset = 0; offset < naddr ; /**/) {
8188 		unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8189 					 ? rem
8190 					 : ARRAY_SIZE(c.u.exact));
8191 		size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8192 						     u.exact[fw_naddr]), 16);
8193 		struct fw_vi_mac_exact *p;
8194 		int i;
8195 
8196 		memset(&c, 0, sizeof(c));
8197 		c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8198 					   F_FW_CMD_REQUEST |
8199 					   F_FW_CMD_WRITE |
8200 					   V_FW_CMD_EXEC(free) |
8201 					   V_FW_VI_MAC_CMD_VIID(viid));
8202 		c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
8203 						  V_FW_CMD_LEN16(len16));
8204 
8205 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8206 			p->valid_to_idx =
8207 				cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8208 					    V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
8209 			memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8210 		}
8211 
8212 		/*
8213 		 * It's okay if we run out of space in our MAC address arena.
8214 		 * Some of the addresses we submit may get stored so we need
8215 		 * to run through the reply to see what the results were ...
8216 		 */
8217 		ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8218 		if (ret && ret != -FW_ENOMEM)
8219 			break;
8220 
8221 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8222 			u16 index = G_FW_VI_MAC_CMD_IDX(
8223 						be16_to_cpu(p->valid_to_idx));
8224 
8225 			if (idx)
8226 				idx[offset+i] = (index >=  max_naddr
8227 						 ? 0xffff
8228 						 : index);
8229 			if (index < max_naddr)
8230 				nfilters++;
8231 			else if (hash)
8232 				*hash |= (1ULL << hash_mac_addr(addr[offset+i]));
8233 		}
8234 
8235 		free = false;
8236 		offset += fw_naddr;
8237 		rem -= fw_naddr;
8238 	}
8239 
8240 	if (ret == 0 || ret == -FW_ENOMEM)
8241 		ret = nfilters;
8242 	return ret;
8243 }
8244 
8245 /**
8246  *	t4_free_encap_mac_filt - frees MPS entry at given index
8247  *	@adap: the adapter
8248  *	@viid: the VI id
8249  *	@idx: index of MPS entry to be freed
8250  *	@sleep_ok: call is allowed to sleep
8251  *
8252  *	Frees the MPS entry at supplied index
8253  *
8254  *	Returns a negative error number or zero on success
8255  */
8256 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
8257 			   int idx, bool sleep_ok)
8258 {
8259 	struct fw_vi_mac_exact *p;
8260 	struct fw_vi_mac_cmd c;
8261 	u8 addr[] = {0,0,0,0,0,0};
8262 	int ret = 0;
8263 	u32 exact;
8264 
8265 	memset(&c, 0, sizeof(c));
8266 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8267 				   F_FW_CMD_REQUEST |
8268 				   F_FW_CMD_WRITE |
8269 				   V_FW_CMD_EXEC(0) |
8270 				   V_FW_VI_MAC_CMD_VIID(viid));
8271 	exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC);
8272 	c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8273 					  exact |
8274 					  V_FW_CMD_LEN16(1));
8275 	p = c.u.exact;
8276 	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8277 				      V_FW_VI_MAC_CMD_IDX(idx));
8278 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
8279 
8280 	ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8281 	return ret;
8282 }
8283 
8284 /**
8285  *	t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
8286  *	@adap: the adapter
8287  *	@viid: the VI id
8288  *	@addr: the MAC address
8289  *	@mask: the mask
8290  *	@idx: index of the entry in mps tcam
8291  *	@lookup_type: MAC address for inner (1) or outer (0) header
8292  *	@port_id: the port index
8293  *	@sleep_ok: call is allowed to sleep
8294  *
8295  *	Removes the mac entry at the specified index using raw mac interface.
8296  *
8297  *	Returns a negative error number on failure.
8298  */
8299 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
8300 			 const u8 *addr, const u8 *mask, unsigned int idx,
8301 			 u8 lookup_type, u8 port_id, bool sleep_ok)
8302 {
8303 	struct fw_vi_mac_cmd c;
8304 	struct fw_vi_mac_raw *p = &c.u.raw;
8305 	u32 raw;
8306 
8307 	memset(&c, 0, sizeof(c));
8308 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8309 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8310 				   V_FW_CMD_EXEC(0) |
8311 				   V_FW_VI_MAC_CMD_VIID(viid));
8312 	raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW);
8313 	c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8314 					  raw |
8315 					  V_FW_CMD_LEN16(1));
8316 
8317 	p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) |
8318 				     FW_VI_MAC_ID_BASED_FREE);
8319 
8320 	/* Lookup Type. Outer header: 0, Inner header: 1 */
8321 	p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) |
8322 				   V_DATAPORTNUM(port_id));
8323 	/* Lookup mask and port mask */
8324 	p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) |
8325 				    V_DATAPORTNUM(M_DATAPORTNUM));
8326 
8327 	/* Copy the address and the mask */
8328 	memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN);
8329 	memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN);
8330 
8331 	return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
8332 }
8333 
8334 /**
8335  *	t4_free_mac_filt - frees exact-match filters of given MAC addresses
8336  *	@adap: the adapter
8337  *	@mbox: mailbox to use for the FW command
8338  *	@viid: the VI id
8339  *	@naddr: the number of MAC addresses to allocate filters for (up to 7)
8340  *	@addr: the MAC address(es)
8341  *	@sleep_ok: call is allowed to sleep
8342  *
8343  *	Frees the exact-match filter for each of the supplied addresses
8344  *
8345  *	Returns a negative error number or the number of filters freed.
8346  */
8347 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8348 		      unsigned int viid, unsigned int naddr,
8349 		      const u8 **addr, bool sleep_ok)
8350 {
8351 	int offset, ret = 0;
8352 	struct fw_vi_mac_cmd c;
8353 	unsigned int nfilters = 0;
8354 	unsigned int max_naddr = adap->chip_params->mps_tcam_size;
8355 	unsigned int rem = naddr;
8356 
8357 	if (naddr > max_naddr)
8358 		return -EINVAL;
8359 
8360 	for (offset = 0; offset < (int)naddr ; /**/) {
8361 		unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8362 					 ? rem
8363 					 : ARRAY_SIZE(c.u.exact));
8364 		size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8365 						     u.exact[fw_naddr]), 16);
8366 		struct fw_vi_mac_exact *p;
8367 		int i;
8368 
8369 		memset(&c, 0, sizeof(c));
8370 		c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8371 				     F_FW_CMD_REQUEST |
8372 				     F_FW_CMD_WRITE |
8373 				     V_FW_CMD_EXEC(0) |
8374 				     V_FW_VI_MAC_CMD_VIID(viid));
8375 		c.freemacs_to_len16 =
8376 				cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) |
8377 					    V_FW_CMD_LEN16(len16));
8378 
8379 		for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8380 			p->valid_to_idx = cpu_to_be16(
8381 				F_FW_VI_MAC_CMD_VALID |
8382 				V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
8383 			memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8384 		}
8385 
8386 		ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8387 		if (ret)
8388 			break;
8389 
8390 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8391 			u16 index = G_FW_VI_MAC_CMD_IDX(
8392 						be16_to_cpu(p->valid_to_idx));
8393 
8394 			if (index < max_naddr)
8395 				nfilters++;
8396 		}
8397 
8398 		offset += fw_naddr;
8399 		rem -= fw_naddr;
8400 	}
8401 
8402 	if (ret == 0)
8403 		ret = nfilters;
8404 	return ret;
8405 }
8406 
8407 /**
8408  *	t4_change_mac - modifies the exact-match filter for a MAC address
8409  *	@adap: the adapter
8410  *	@mbox: mailbox to use for the FW command
8411  *	@viid: the VI id
8412  *	@idx: index of existing filter for old value of MAC address, or -1
8413  *	@addr: the new MAC address value
8414  *	@persist: whether a new MAC allocation should be persistent
8415  *	@smt_idx: add MAC to SMT and return its index, or NULL
8416  *
8417  *	Modifies an exact-match filter and sets it to the new MAC address if
8418  *	@idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
8419  *	latter case the address is added persistently if @persist is %true.
8420  *
8421  *	Note that in general it is not possible to modify the value of a given
8422  *	filter so the generic way to modify an address filter is to free the one
8423  *	being used by the old address value and allocate a new filter for the
8424  *	new address value.
8425  *
8426  *	Returns a negative error number or the index of the filter with the new
8427  *	MAC value.  Note that this index may differ from @idx.
8428  */
8429 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8430 		  int idx, const u8 *addr, bool persist, uint16_t *smt_idx)
8431 {
8432 	int ret, mode;
8433 	struct fw_vi_mac_cmd c;
8434 	struct fw_vi_mac_exact *p = c.u.exact;
8435 	unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
8436 
8437 	if (idx < 0)		/* new allocation */
8438 		idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8439 	mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8440 
8441 	memset(&c, 0, sizeof(c));
8442 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8443 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8444 				   V_FW_VI_MAC_CMD_VIID(viid));
8445 	c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
8446 	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
8447 				      V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
8448 				      V_FW_VI_MAC_CMD_IDX(idx));
8449 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
8450 
8451 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8452 	if (ret == 0) {
8453 		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
8454 		if (ret >= max_mac_addr)
8455 			ret = -ENOMEM;
8456 		if (smt_idx) {
8457 			if (adap->params.viid_smt_extn_support)
8458 				*smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
8459 			else {
8460 				if (chip_id(adap) <= CHELSIO_T5)
8461 					*smt_idx = (viid & M_FW_VIID_VIN) << 1;
8462 				else
8463 					*smt_idx = viid & M_FW_VIID_VIN;
8464 			}
8465 		}
8466 	}
8467 	return ret;
8468 }
8469 
8470 /**
8471  *	t4_set_addr_hash - program the MAC inexact-match hash filter
8472  *	@adap: the adapter
8473  *	@mbox: mailbox to use for the FW command
8474  *	@viid: the VI id
8475  *	@ucast: whether the hash filter should also match unicast addresses
8476  *	@vec: the value to be written to the hash filter
8477  *	@sleep_ok: call is allowed to sleep
8478  *
8479  *	Sets the 64-bit inexact-match hash filter for a virtual interface.
8480  */
8481 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8482 		     bool ucast, u64 vec, bool sleep_ok)
8483 {
8484 	struct fw_vi_mac_cmd c;
8485 	u32 val;
8486 
8487 	memset(&c, 0, sizeof(c));
8488 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
8489 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
8490 				   V_FW_VI_ENABLE_CMD_VIID(viid));
8491 	val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
8492 	      V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
8493 	c.freemacs_to_len16 = cpu_to_be32(val);
8494 	c.u.hash.hashvec = cpu_to_be64(vec);
8495 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8496 }
8497 
8498 /**
8499  *      t4_enable_vi_params - enable/disable a virtual interface
8500  *      @adap: the adapter
8501  *      @mbox: mailbox to use for the FW command
8502  *      @viid: the VI id
8503  *      @rx_en: 1=enable Rx, 0=disable Rx
8504  *      @tx_en: 1=enable Tx, 0=disable Tx
8505  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
8506  *
8507  *      Enables/disables a virtual interface.  Note that setting DCB Enable
8508  *      only makes sense when enabling a Virtual Interface ...
8509  */
8510 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8511 			unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8512 {
8513 	struct fw_vi_enable_cmd c;
8514 
8515 	memset(&c, 0, sizeof(c));
8516 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8517 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8518 				   V_FW_VI_ENABLE_CMD_VIID(viid));
8519 	c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
8520 				     V_FW_VI_ENABLE_CMD_EEN(tx_en) |
8521 				     V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
8522 				     FW_LEN16(c));
8523 	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8524 }
8525 
8526 /**
8527  *	t4_enable_vi - enable/disable a virtual interface
8528  *	@adap: the adapter
8529  *	@mbox: mailbox to use for the FW command
8530  *	@viid: the VI id
8531  *	@rx_en: 1=enable Rx, 0=disable Rx
8532  *	@tx_en: 1=enable Tx, 0=disable Tx
8533  *
8534  *	Enables/disables a virtual interface.  Note that setting DCB Enable
8535  *	only makes sense when enabling a Virtual Interface ...
8536  */
8537 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8538 		 bool rx_en, bool tx_en)
8539 {
8540 	return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8541 }
8542 
8543 /**
8544  *	t4_identify_port - identify a VI's port by blinking its LED
8545  *	@adap: the adapter
8546  *	@mbox: mailbox to use for the FW command
8547  *	@viid: the VI id
8548  *	@nblinks: how many times to blink LED at 2.5 Hz
8549  *
8550  *	Identifies a VI's port by blinking its LED.
8551  */
8552 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8553 		     unsigned int nblinks)
8554 {
8555 	struct fw_vi_enable_cmd c;
8556 
8557 	memset(&c, 0, sizeof(c));
8558 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
8559 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8560 				   V_FW_VI_ENABLE_CMD_VIID(viid));
8561 	c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
8562 	c.blinkdur = cpu_to_be16(nblinks);
8563 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8564 }
8565 
8566 /**
8567  *	t4_iq_stop - stop an ingress queue and its FLs
8568  *	@adap: the adapter
8569  *	@mbox: mailbox to use for the FW command
8570  *	@pf: the PF owning the queues
8571  *	@vf: the VF owning the queues
8572  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8573  *	@iqid: ingress queue id
8574  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
8575  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
8576  *
8577  *	Stops an ingress queue and its associated FLs, if any.  This causes
8578  *	any current or future data/messages destined for these queues to be
8579  *	tossed.
8580  */
8581 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8582 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
8583 	       unsigned int fl0id, unsigned int fl1id)
8584 {
8585 	struct fw_iq_cmd c;
8586 
8587 	memset(&c, 0, sizeof(c));
8588 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8589 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8590 				  V_FW_IQ_CMD_VFN(vf));
8591 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
8592 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8593 	c.iqid = cpu_to_be16(iqid);
8594 	c.fl0id = cpu_to_be16(fl0id);
8595 	c.fl1id = cpu_to_be16(fl1id);
8596 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8597 }
8598 
8599 /**
8600  *	t4_iq_free - free an ingress queue and its FLs
8601  *	@adap: the adapter
8602  *	@mbox: mailbox to use for the FW command
8603  *	@pf: the PF owning the queues
8604  *	@vf: the VF owning the queues
8605  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8606  *	@iqid: ingress queue id
8607  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
8608  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
8609  *
8610  *	Frees an ingress queue and its associated FLs, if any.
8611  */
8612 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8613 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
8614 	       unsigned int fl0id, unsigned int fl1id)
8615 {
8616 	struct fw_iq_cmd c;
8617 
8618 	memset(&c, 0, sizeof(c));
8619 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
8620 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
8621 				  V_FW_IQ_CMD_VFN(vf));
8622 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
8623 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
8624 	c.iqid = cpu_to_be16(iqid);
8625 	c.fl0id = cpu_to_be16(fl0id);
8626 	c.fl1id = cpu_to_be16(fl1id);
8627 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8628 }
8629 
8630 /**
8631  *	t4_eth_eq_stop - stop an Ethernet egress queue
8632  *	@adap: the adapter
8633  *	@mbox: mailbox to use for the FW command
8634  *	@pf: the PF owning the queues
8635  *	@vf: the VF owning the queues
8636  *	@eqid: egress queue id
8637  *
8638  *	Stops an Ethernet egress queue.  The queue can be reinitialized or
8639  *	freed but is not otherwise functional after this call.
8640  */
8641 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8642                    unsigned int vf, unsigned int eqid)
8643 {
8644 	struct fw_eq_eth_cmd c;
8645 
8646 	memset(&c, 0, sizeof(c));
8647 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8648 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8649 				  V_FW_EQ_ETH_CMD_PFN(pf) |
8650 				  V_FW_EQ_ETH_CMD_VFN(vf));
8651 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c));
8652 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8653 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8654 }
8655 
8656 /**
8657  *	t4_eth_eq_free - free an Ethernet egress queue
8658  *	@adap: the adapter
8659  *	@mbox: mailbox to use for the FW command
8660  *	@pf: the PF owning the queue
8661  *	@vf: the VF owning the queue
8662  *	@eqid: egress queue id
8663  *
8664  *	Frees an Ethernet egress queue.
8665  */
8666 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8667 		   unsigned int vf, unsigned int eqid)
8668 {
8669 	struct fw_eq_eth_cmd c;
8670 
8671 	memset(&c, 0, sizeof(c));
8672 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
8673 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8674 				  V_FW_EQ_ETH_CMD_PFN(pf) |
8675 				  V_FW_EQ_ETH_CMD_VFN(vf));
8676 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
8677 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
8678 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8679 }
8680 
8681 /**
8682  *	t4_ctrl_eq_free - free a control egress queue
8683  *	@adap: the adapter
8684  *	@mbox: mailbox to use for the FW command
8685  *	@pf: the PF owning the queue
8686  *	@vf: the VF owning the queue
8687  *	@eqid: egress queue id
8688  *
8689  *	Frees a control egress queue.
8690  */
8691 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8692 		    unsigned int vf, unsigned int eqid)
8693 {
8694 	struct fw_eq_ctrl_cmd c;
8695 
8696 	memset(&c, 0, sizeof(c));
8697 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
8698 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8699 				  V_FW_EQ_CTRL_CMD_PFN(pf) |
8700 				  V_FW_EQ_CTRL_CMD_VFN(vf));
8701 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
8702 	c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
8703 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8704 }
8705 
8706 /**
8707  *	t4_ofld_eq_free - free an offload egress queue
8708  *	@adap: the adapter
8709  *	@mbox: mailbox to use for the FW command
8710  *	@pf: the PF owning the queue
8711  *	@vf: the VF owning the queue
8712  *	@eqid: egress queue id
8713  *
8714  *	Frees a control egress queue.
8715  */
8716 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8717 		    unsigned int vf, unsigned int eqid)
8718 {
8719 	struct fw_eq_ofld_cmd c;
8720 
8721 	memset(&c, 0, sizeof(c));
8722 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
8723 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
8724 				  V_FW_EQ_OFLD_CMD_PFN(pf) |
8725 				  V_FW_EQ_OFLD_CMD_VFN(vf));
8726 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
8727 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
8728 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8729 }
8730 
8731 /**
8732  *	t4_link_down_rc_str - return a string for a Link Down Reason Code
8733  *	@link_down_rc: Link Down Reason Code
8734  *
8735  *	Returns a string representation of the Link Down Reason Code.
8736  */
8737 const char *t4_link_down_rc_str(unsigned char link_down_rc)
8738 {
8739 	static const char *reason[] = {
8740 		"Link Down",
8741 		"Remote Fault",
8742 		"Auto-negotiation Failure",
8743 		"Reserved3",
8744 		"Insufficient Airflow",
8745 		"Unable To Determine Reason",
8746 		"No RX Signal Detected",
8747 		"Reserved7",
8748 	};
8749 
8750 	if (link_down_rc >= ARRAY_SIZE(reason))
8751 		return "Bad Reason Code";
8752 
8753 	return reason[link_down_rc];
8754 }
8755 
8756 /*
8757  * Return the highest speed set in the port capabilities, in Mb/s.
8758  */
8759 unsigned int fwcap_to_speed(uint32_t caps)
8760 {
8761 	#define TEST_SPEED_RETURN(__caps_speed, __speed) \
8762 		do { \
8763 			if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8764 				return __speed; \
8765 		} while (0)
8766 
8767 	TEST_SPEED_RETURN(400G, 400000);
8768 	TEST_SPEED_RETURN(200G, 200000);
8769 	TEST_SPEED_RETURN(100G, 100000);
8770 	TEST_SPEED_RETURN(50G,   50000);
8771 	TEST_SPEED_RETURN(40G,   40000);
8772 	TEST_SPEED_RETURN(25G,   25000);
8773 	TEST_SPEED_RETURN(10G,   10000);
8774 	TEST_SPEED_RETURN(1G,     1000);
8775 	TEST_SPEED_RETURN(100M,    100);
8776 
8777 	#undef TEST_SPEED_RETURN
8778 
8779 	return 0;
8780 }
8781 
8782 /*
8783  * Return the port capabilities bit for the given speed, which is in Mb/s.
8784  */
8785 uint32_t speed_to_fwcap(unsigned int speed)
8786 {
8787 	#define TEST_SPEED_RETURN(__caps_speed, __speed) \
8788 		do { \
8789 			if (speed == __speed) \
8790 				return FW_PORT_CAP32_SPEED_##__caps_speed; \
8791 		} while (0)
8792 
8793 	TEST_SPEED_RETURN(400G, 400000);
8794 	TEST_SPEED_RETURN(200G, 200000);
8795 	TEST_SPEED_RETURN(100G, 100000);
8796 	TEST_SPEED_RETURN(50G,   50000);
8797 	TEST_SPEED_RETURN(40G,   40000);
8798 	TEST_SPEED_RETURN(25G,   25000);
8799 	TEST_SPEED_RETURN(10G,   10000);
8800 	TEST_SPEED_RETURN(1G,     1000);
8801 	TEST_SPEED_RETURN(100M,    100);
8802 
8803 	#undef TEST_SPEED_RETURN
8804 
8805 	return 0;
8806 }
8807 
8808 /*
8809  * Return the port capabilities bit for the highest speed in the capabilities.
8810  */
8811 uint32_t fwcap_top_speed(uint32_t caps)
8812 {
8813 	#define TEST_SPEED_RETURN(__caps_speed) \
8814 		do { \
8815 			if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8816 				return FW_PORT_CAP32_SPEED_##__caps_speed; \
8817 		} while (0)
8818 
8819 	TEST_SPEED_RETURN(400G);
8820 	TEST_SPEED_RETURN(200G);
8821 	TEST_SPEED_RETURN(100G);
8822 	TEST_SPEED_RETURN(50G);
8823 	TEST_SPEED_RETURN(40G);
8824 	TEST_SPEED_RETURN(25G);
8825 	TEST_SPEED_RETURN(10G);
8826 	TEST_SPEED_RETURN(1G);
8827 	TEST_SPEED_RETURN(100M);
8828 
8829 	#undef TEST_SPEED_RETURN
8830 
8831 	return 0;
8832 }
8833 
8834 /**
8835  *	lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8836  *	@lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8837  *
8838  *	Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8839  *	32-bit Port Capabilities value.
8840  */
8841 static uint32_t lstatus_to_fwcap(u32 lstatus)
8842 {
8843 	uint32_t linkattr = 0;
8844 
8845 	/*
8846 	 * Unfortunately the format of the Link Status in the old
8847 	 * 16-bit Port Information message isn't the same as the
8848 	 * 16-bit Port Capabilities bitfield used everywhere else ...
8849 	 */
8850 	if (lstatus & F_FW_PORT_CMD_RXPAUSE)
8851 		linkattr |= FW_PORT_CAP32_FC_RX;
8852 	if (lstatus & F_FW_PORT_CMD_TXPAUSE)
8853 		linkattr |= FW_PORT_CAP32_FC_TX;
8854 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
8855 		linkattr |= FW_PORT_CAP32_SPEED_100M;
8856 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
8857 		linkattr |= FW_PORT_CAP32_SPEED_1G;
8858 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
8859 		linkattr |= FW_PORT_CAP32_SPEED_10G;
8860 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
8861 		linkattr |= FW_PORT_CAP32_SPEED_25G;
8862 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
8863 		linkattr |= FW_PORT_CAP32_SPEED_40G;
8864 	if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
8865 		linkattr |= FW_PORT_CAP32_SPEED_100G;
8866 
8867 	return linkattr;
8868 }
8869 
8870 /*
8871  * Updates all fields owned by the common code in port_info and link_config
8872  * based on information provided by the firmware.  Does not touch any
8873  * requested_* field.
8874  */
8875 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p,
8876     enum fw_port_action action, bool *mod_changed, bool *link_changed)
8877 {
8878 	struct link_config old_lc, *lc = &pi->link_cfg;
8879 	unsigned char fc;
8880 	u32 stat, linkattr;
8881 	int old_ptype, old_mtype;
8882 
8883 	old_ptype = pi->port_type;
8884 	old_mtype = pi->mod_type;
8885 	old_lc = *lc;
8886 	if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8887 		stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
8888 
8889 		pi->port_type = G_FW_PORT_CMD_PTYPE(stat);
8890 		pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat);
8891 		pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ?
8892 		    G_FW_PORT_CMD_MDIOADDR(stat) : -1;
8893 
8894 		lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap));
8895 		lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap));
8896 		lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap));
8897 		lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
8898 		lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat);
8899 
8900 		linkattr = lstatus_to_fwcap(stat);
8901 	} else if (action == FW_PORT_ACTION_GET_PORT_INFO32) {
8902 		stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32);
8903 
8904 		pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat);
8905 		pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat);
8906 		pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ?
8907 		    G_FW_PORT_CMD_MDIOADDR32(stat) : -1;
8908 
8909 		lc->pcaps = be32_to_cpu(p->u.info32.pcaps32);
8910 		lc->acaps = be32_to_cpu(p->u.info32.acaps32);
8911 		lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32);
8912 		lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0;
8913 		lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat);
8914 
8915 		linkattr = be32_to_cpu(p->u.info32.linkattr32);
8916 	} else {
8917 		CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action);
8918 		return;
8919 	}
8920 
8921 	lc->speed = fwcap_to_speed(linkattr);
8922 	lc->fec = fwcap_to_fec(linkattr, true);
8923 
8924 	fc = 0;
8925 	if (linkattr & FW_PORT_CAP32_FC_RX)
8926 		fc |= PAUSE_RX;
8927 	if (linkattr & FW_PORT_CAP32_FC_TX)
8928 		fc |= PAUSE_TX;
8929 	lc->fc = fc;
8930 
8931 	if (mod_changed != NULL)
8932 		*mod_changed = false;
8933 	if (link_changed != NULL)
8934 		*link_changed = false;
8935 	if (old_ptype != pi->port_type || old_mtype != pi->mod_type ||
8936 	    old_lc.pcaps != lc->pcaps) {
8937 		if (pi->mod_type != FW_PORT_MOD_TYPE_NONE)
8938 			lc->fec_hint = fwcap_to_fec(lc->acaps, true);
8939 		if (mod_changed != NULL)
8940 			*mod_changed = true;
8941 	}
8942 	if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed ||
8943 	    old_lc.fec != lc->fec || old_lc.fc != lc->fc) {
8944 		if (link_changed != NULL)
8945 			*link_changed = true;
8946 	}
8947 }
8948 
8949 /**
8950  *	t4_update_port_info - retrieve and update port information if changed
8951  *	@pi: the port_info
8952  *
8953  *	We issue a Get Port Information Command to the Firmware and, if
8954  *	successful, we check to see if anything is different from what we
8955  *	last recorded and update things accordingly.
8956  */
8957  int t4_update_port_info(struct port_info *pi)
8958  {
8959 	struct adapter *sc = pi->adapter;
8960 	struct fw_port_cmd cmd;
8961 	enum fw_port_action action;
8962 	int ret;
8963 
8964 	memset(&cmd, 0, sizeof(cmd));
8965 	cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
8966 	    F_FW_CMD_REQUEST | F_FW_CMD_READ |
8967 	    V_FW_PORT_CMD_PORTID(pi->tx_chan));
8968 	action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 :
8969 	    FW_PORT_ACTION_GET_PORT_INFO;
8970 	cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) |
8971 	    FW_LEN16(cmd));
8972 	ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
8973 	if (ret)
8974 		return ret;
8975 
8976 	handle_port_info(pi, &cmd, action, NULL, NULL);
8977 	return 0;
8978 }
8979 
8980 /**
8981  *	t4_handle_fw_rpl - process a FW reply message
8982  *	@adap: the adapter
8983  *	@rpl: start of the FW message
8984  *
8985  *	Processes a FW message, such as link state change messages.
8986  */
8987 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8988 {
8989 	u8 opcode = *(const u8 *)rpl;
8990 	const struct fw_port_cmd *p = (const void *)rpl;
8991 	enum fw_port_action action =
8992 	    G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
8993 	bool mod_changed, link_changed;
8994 
8995 	if (opcode == FW_PORT_CMD &&
8996 	    (action == FW_PORT_ACTION_GET_PORT_INFO ||
8997 	    action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8998 		/* link/module state change message */
8999 		int i;
9000 		int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
9001 		struct port_info *pi = NULL;
9002 
9003 		for_each_port(adap, i) {
9004 			pi = adap2pinfo(adap, i);
9005 			if (pi->tx_chan == chan)
9006 				break;
9007 		}
9008 
9009 		PORT_LOCK(pi);
9010 		handle_port_info(pi, p, action, &mod_changed, &link_changed);
9011 		PORT_UNLOCK(pi);
9012 		if (mod_changed)
9013 			t4_os_portmod_changed(pi);
9014 		if (link_changed) {
9015 			PORT_LOCK(pi);
9016 			t4_os_link_changed(pi);
9017 			PORT_UNLOCK(pi);
9018 		}
9019 	} else {
9020 		CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
9021 		return -EINVAL;
9022 	}
9023 	return 0;
9024 }
9025 
9026 /**
9027  *	get_pci_mode - determine a card's PCI mode
9028  *	@adapter: the adapter
9029  *	@p: where to store the PCI settings
9030  *
9031  *	Determines a card's PCI mode and associated parameters, such as speed
9032  *	and width.
9033  */
9034 static void get_pci_mode(struct adapter *adapter,
9035 				   struct pci_params *p)
9036 {
9037 	u16 val;
9038 	u32 pcie_cap;
9039 
9040 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
9041 	if (pcie_cap) {
9042 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
9043 		p->speed = val & PCI_EXP_LNKSTA_CLS;
9044 		p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
9045 	}
9046 }
9047 
9048 struct flash_desc {
9049 	u32 vendor_and_model_id;
9050 	u32 size_mb;
9051 };
9052 
9053 int t4_get_flash_params(struct adapter *adapter)
9054 {
9055 	/*
9056 	 * Table for non-standard supported Flash parts.  Note, all Flash
9057 	 * parts must have 64KB sectors.
9058 	 */
9059 	static struct flash_desc supported_flash[] = {
9060 		{ 0x00150201, 4 << 20 },	/* Spansion 4MB S25FL032P */
9061 	};
9062 
9063 	int ret;
9064 	u32 flashid = 0;
9065 	unsigned int part, manufacturer;
9066 	unsigned int density, size = 0;
9067 
9068 
9069 	/*
9070 	 * Issue a Read ID Command to the Flash part.  We decode supported
9071 	 * Flash parts and their sizes from this.  There's a newer Query
9072 	 * Command which can retrieve detailed geometry information but many
9073 	 * Flash parts don't support it.
9074 	 */
9075 	ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
9076 	if (!ret)
9077 		ret = sf1_read(adapter, 3, 0, 1, &flashid);
9078 	t4_write_reg(adapter, A_SF_OP, 0);	/* unlock SF */
9079 	if (ret < 0)
9080 		return ret;
9081 
9082 	/*
9083 	 * Check to see if it's one of our non-standard supported Flash parts.
9084 	 */
9085 	for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
9086 		if (supported_flash[part].vendor_and_model_id == flashid) {
9087 			adapter->params.sf_size =
9088 				supported_flash[part].size_mb;
9089 			adapter->params.sf_nsec =
9090 				adapter->params.sf_size / SF_SEC_SIZE;
9091 			goto found;
9092 		}
9093 
9094 	/*
9095 	 * Decode Flash part size.  The code below looks repetative with
9096 	 * common encodings, but that's not guaranteed in the JEDEC
9097 	 * specification for the Read JADEC ID command.  The only thing that
9098 	 * we're guaranteed by the JADEC specification is where the
9099 	 * Manufacturer ID is in the returned result.  After that each
9100 	 * Manufacturer ~could~ encode things completely differently.
9101 	 * Note, all Flash parts must have 64KB sectors.
9102 	 */
9103 	manufacturer = flashid & 0xff;
9104 	switch (manufacturer) {
9105 	case 0x20: /* Micron/Numonix */
9106 		/*
9107 		 * This Density -> Size decoding table is taken from Micron
9108 		 * Data Sheets.
9109 		 */
9110 		density = (flashid >> 16) & 0xff;
9111 		switch (density) {
9112 		case 0x14: size = 1 << 20; break; /*   1MB */
9113 		case 0x15: size = 1 << 21; break; /*   2MB */
9114 		case 0x16: size = 1 << 22; break; /*   4MB */
9115 		case 0x17: size = 1 << 23; break; /*   8MB */
9116 		case 0x18: size = 1 << 24; break; /*  16MB */
9117 		case 0x19: size = 1 << 25; break; /*  32MB */
9118 		case 0x20: size = 1 << 26; break; /*  64MB */
9119 		case 0x21: size = 1 << 27; break; /* 128MB */
9120 		case 0x22: size = 1 << 28; break; /* 256MB */
9121 		}
9122 		break;
9123 
9124 	case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */
9125 		/*
9126 		 * This Density -> Size decoding table is taken from ISSI
9127 		 * Data Sheets.
9128 		 */
9129 		density = (flashid >> 16) & 0xff;
9130 		switch (density) {
9131 		case 0x16: size = 1 << 25; break; /*  32MB */
9132 		case 0x17: size = 1 << 26; break; /*  64MB */
9133 		}
9134 		break;
9135 
9136 	case 0xc2: /* Macronix */
9137 		/*
9138 		 * This Density -> Size decoding table is taken from Macronix
9139 		 * Data Sheets.
9140 		 */
9141 		density = (flashid >> 16) & 0xff;
9142 		switch (density) {
9143 		case 0x17: size = 1 << 23; break; /*   8MB */
9144 		case 0x18: size = 1 << 24; break; /*  16MB */
9145 		}
9146 		break;
9147 
9148 	case 0xef: /* Winbond */
9149 		/*
9150 		 * This Density -> Size decoding table is taken from Winbond
9151 		 * Data Sheets.
9152 		 */
9153 		density = (flashid >> 16) & 0xff;
9154 		switch (density) {
9155 		case 0x17: size = 1 << 23; break; /*   8MB */
9156 		case 0x18: size = 1 << 24; break; /*  16MB */
9157 		}
9158 		break;
9159 	}
9160 
9161 	/* If we didn't recognize the FLASH part, that's no real issue: the
9162 	 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9163 	 * use a FLASH part which is at least 4MB in size and has 64KB
9164 	 * sectors.  The unrecognized FLASH part is likely to be much larger
9165 	 * than 4MB, but that's all we really need.
9166 	 */
9167 	if (size == 0) {
9168 		CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid);
9169 		size = 1 << 22;
9170 	}
9171 
9172 	/*
9173 	 * Store decoded Flash size and fall through into vetting code.
9174 	 */
9175 	adapter->params.sf_size = size;
9176 	adapter->params.sf_nsec = size / SF_SEC_SIZE;
9177 
9178  found:
9179 	/*
9180 	 * We should ~probably~ reject adapters with FLASHes which are too
9181 	 * small but we have some legacy FPGAs with small FLASHes that we'd
9182 	 * still like to use.  So instead we emit a scary message ...
9183 	 */
9184 	if (adapter->params.sf_size < FLASH_MIN_SIZE)
9185 		CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9186 			flashid, adapter->params.sf_size, FLASH_MIN_SIZE);
9187 
9188 	return 0;
9189 }
9190 
9191 static void set_pcie_completion_timeout(struct adapter *adapter,
9192 						  u8 range)
9193 {
9194 	u16 val;
9195 	u32 pcie_cap;
9196 
9197 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
9198 	if (pcie_cap) {
9199 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
9200 		val &= 0xfff0;
9201 		val |= range ;
9202 		t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
9203 	}
9204 }
9205 
9206 const struct chip_params *t4_get_chip_params(int chipid)
9207 {
9208 	static const struct chip_params chip_params[] = {
9209 		{
9210 			/* T4 */
9211 			.nchan = NCHAN,
9212 			.pm_stats_cnt = PM_NSTATS,
9213 			.cng_ch_bits_log = 2,
9214 			.nsched_cls = 15,
9215 			.cim_num_obq = CIM_NUM_OBQ,
9216 			.filter_opt_len = FILTER_OPT_LEN,
9217 			.mps_rplc_size = 128,
9218 			.vfcount = 128,
9219 			.sge_fl_db = F_DBPRIO,
9220 			.mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
9221 			.rss_nentries = RSS_NENTRIES,
9222 			.cim_la_size = CIMLA_SIZE,
9223 		},
9224 		{
9225 			/* T5 */
9226 			.nchan = NCHAN,
9227 			.pm_stats_cnt = PM_NSTATS,
9228 			.cng_ch_bits_log = 2,
9229 			.nsched_cls = 16,
9230 			.cim_num_obq = CIM_NUM_OBQ_T5,
9231 			.filter_opt_len = T5_FILTER_OPT_LEN,
9232 			.mps_rplc_size = 128,
9233 			.vfcount = 128,
9234 			.sge_fl_db = F_DBPRIO | F_DBTYPE,
9235 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
9236 			.rss_nentries = RSS_NENTRIES,
9237 			.cim_la_size = CIMLA_SIZE,
9238 		},
9239 		{
9240 			/* T6 */
9241 			.nchan = T6_NCHAN,
9242 			.pm_stats_cnt = T6_PM_NSTATS,
9243 			.cng_ch_bits_log = 3,
9244 			.nsched_cls = 16,
9245 			.cim_num_obq = CIM_NUM_OBQ_T5,
9246 			.filter_opt_len = T5_FILTER_OPT_LEN,
9247 			.mps_rplc_size = 256,
9248 			.vfcount = 256,
9249 			.sge_fl_db = 0,
9250 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
9251 			.rss_nentries = T6_RSS_NENTRIES,
9252 			.cim_la_size = CIMLA_SIZE_T6,
9253 		},
9254 	};
9255 
9256 	chipid -= CHELSIO_T4;
9257 	if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
9258 		return NULL;
9259 
9260 	return &chip_params[chipid];
9261 }
9262 
9263 /**
9264  *	t4_prep_adapter - prepare SW and HW for operation
9265  *	@adapter: the adapter
9266  *	@buf: temporary space of at least VPD_LEN size provided by the caller.
9267  *
9268  *	Initialize adapter SW state for the various HW modules, set initial
9269  *	values for some adapter tunables, take PHYs out of reset, and
9270  *	initialize the MDIO interface.
9271  */
9272 int t4_prep_adapter(struct adapter *adapter, u32 *buf)
9273 {
9274 	int ret;
9275 	uint16_t device_id;
9276 	uint32_t pl_rev;
9277 
9278 	get_pci_mode(adapter, &adapter->params.pci);
9279 
9280 	pl_rev = t4_read_reg(adapter, A_PL_REV);
9281 	adapter->params.chipid = G_CHIPID(pl_rev);
9282 	adapter->params.rev = G_REV(pl_rev);
9283 	if (adapter->params.chipid == 0) {
9284 		/* T4 did not have chipid in PL_REV (T5 onwards do) */
9285 		adapter->params.chipid = CHELSIO_T4;
9286 
9287 		/* T4A1 chip is not supported */
9288 		if (adapter->params.rev == 1) {
9289 			CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
9290 			return -EINVAL;
9291 		}
9292 	}
9293 
9294 	adapter->chip_params = t4_get_chip_params(chip_id(adapter));
9295 	if (adapter->chip_params == NULL)
9296 		return -EINVAL;
9297 
9298 	adapter->params.pci.vpd_cap_addr =
9299 	    t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
9300 
9301 	ret = t4_get_flash_params(adapter);
9302 	if (ret < 0)
9303 		return ret;
9304 
9305 	/* Cards with real ASICs have the chipid in the PCIe device id */
9306 	t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
9307 	if (device_id >> 12 == chip_id(adapter))
9308 		adapter->params.cim_la_size = adapter->chip_params->cim_la_size;
9309 	else {
9310 		/* FPGA */
9311 		adapter->params.fpga = 1;
9312 		adapter->params.cim_la_size = 2 * adapter->chip_params->cim_la_size;
9313 	}
9314 
9315 	ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf);
9316 	if (ret < 0)
9317 		return ret;
9318 
9319 	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9320 
9321 	/*
9322 	 * Default port and clock for debugging in case we can't reach FW.
9323 	 */
9324 	adapter->params.nports = 1;
9325 	adapter->params.portvec = 1;
9326 	adapter->params.vpd.cclk = 50000;
9327 
9328 	/* Set pci completion timeout value to 4 seconds. */
9329 	set_pcie_completion_timeout(adapter, 0xd);
9330 	return 0;
9331 }
9332 
9333 /**
9334  *	t4_shutdown_adapter - shut down adapter, host & wire
9335  *	@adapter: the adapter
9336  *
9337  *	Perform an emergency shutdown of the adapter and stop it from
9338  *	continuing any further communication on the ports or DMA to the
9339  *	host.  This is typically used when the adapter and/or firmware
9340  *	have crashed and we want to prevent any further accidental
9341  *	communication with the rest of the world.  This will also force
9342  *	the port Link Status to go down -- if register writes work --
9343  *	which should help our peers figure out that we're down.
9344  */
9345 int t4_shutdown_adapter(struct adapter *adapter)
9346 {
9347 	int port;
9348 	const bool bt = adapter->bt_map != 0;
9349 
9350 	t4_intr_disable(adapter);
9351 	if (bt)
9352 		t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000);
9353 	for_each_port(adapter, port) {
9354 		u32 a_port_cfg = is_t4(adapter) ?
9355 		    t4_port_reg(adapter, port, A_XGMAC_PORT_CFG) :
9356 		    t4_port_reg(adapter, port, A_MAC_PORT_CFG);
9357 
9358 		t4_write_reg(adapter, a_port_cfg,
9359 			     t4_read_reg(adapter, a_port_cfg)
9360 			     & ~V_SIGNAL_DET(1));
9361 		if (!bt) {
9362 			u32 hss_cfg0 = is_t4(adapter) ?
9363 			    t4_port_reg(adapter, port, A_XGMAC_PORT_HSS_CFG0) :
9364 			    t4_port_reg(adapter, port, A_MAC_PORT_HSS_CFG0);
9365 			t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB |
9366 			    F_HSSPDWNPLLA | F_HSSPLLBYPB | F_HSSPLLBYPA,
9367 			    F_HSSPDWNPLLB | F_HSSPDWNPLLA | F_HSSPLLBYPB |
9368 			    F_HSSPLLBYPA);
9369 		}
9370 	}
9371 	t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
9372 
9373 	return 0;
9374 }
9375 
9376 /**
9377  *	t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9378  *	@adapter: the adapter
9379  *	@qid: the Queue ID
9380  *	@qtype: the Ingress or Egress type for @qid
9381  *	@user: true if this request is for a user mode queue
9382  *	@pbar2_qoffset: BAR2 Queue Offset
9383  *	@pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9384  *
9385  *	Returns the BAR2 SGE Queue Registers information associated with the
9386  *	indicated Absolute Queue ID.  These are passed back in return value
9387  *	pointers.  @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9388  *	and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9389  *
9390  *	This may return an error which indicates that BAR2 SGE Queue
9391  *	registers aren't available.  If an error is not returned, then the
9392  *	following values are returned:
9393  *
9394  *	  *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9395  *	  *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9396  *
9397  *	If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9398  *	require the "Inferred Queue ID" ability may be used.  E.g. the
9399  *	Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9400  *	then these "Inferred Queue ID" register may not be used.
9401  */
9402 int t4_bar2_sge_qregs(struct adapter *adapter,
9403 		      unsigned int qid,
9404 		      enum t4_bar2_qtype qtype,
9405 		      int user,
9406 		      u64 *pbar2_qoffset,
9407 		      unsigned int *pbar2_qid)
9408 {
9409 	unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9410 	u64 bar2_page_offset, bar2_qoffset;
9411 	unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9412 
9413 	/* T4 doesn't support BAR2 SGE Queue registers for kernel
9414 	 * mode queues.
9415 	 */
9416 	if (!user && is_t4(adapter))
9417 		return -EINVAL;
9418 
9419 	/* Get our SGE Page Size parameters.
9420 	 */
9421 	page_shift = adapter->params.sge.page_shift;
9422 	page_size = 1 << page_shift;
9423 
9424 	/* Get the right Queues per Page parameters for our Queue.
9425 	 */
9426 	qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9427 		     ? adapter->params.sge.eq_s_qpp
9428 		     : adapter->params.sge.iq_s_qpp);
9429 	qpp_mask = (1 << qpp_shift) - 1;
9430 
9431 	/* Calculate the basics of the BAR2 SGE Queue register area:
9432 	 *  o The BAR2 page the Queue registers will be in.
9433 	 *  o The BAR2 Queue ID.
9434 	 *  o The BAR2 Queue ID Offset into the BAR2 page.
9435 	 */
9436 	bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9437 	bar2_qid = qid & qpp_mask;
9438 	bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9439 
9440 	/* If the BAR2 Queue ID Offset is less than the Page Size, then the
9441 	 * hardware will infer the Absolute Queue ID simply from the writes to
9442 	 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9443 	 * BAR2 Queue ID of 0 for those writes).  Otherwise, we'll simply
9444 	 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9445 	 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9446 	 * from the BAR2 Page and BAR2 Queue ID.
9447 	 *
9448 	 * One important censequence of this is that some BAR2 SGE registers
9449 	 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9450 	 * there.  But other registers synthesize the SGE Queue ID purely
9451 	 * from the writes to the registers -- the Write Combined Doorbell
9452 	 * Buffer is a good example.  These BAR2 SGE Registers are only
9453 	 * available for those BAR2 SGE Register areas where the SGE Absolute
9454 	 * Queue ID can be inferred from simple writes.
9455 	 */
9456 	bar2_qoffset = bar2_page_offset;
9457 	bar2_qinferred = (bar2_qid_offset < page_size);
9458 	if (bar2_qinferred) {
9459 		bar2_qoffset += bar2_qid_offset;
9460 		bar2_qid = 0;
9461 	}
9462 
9463 	*pbar2_qoffset = bar2_qoffset;
9464 	*pbar2_qid = bar2_qid;
9465 	return 0;
9466 }
9467 
9468 /**
9469  *	t4_init_devlog_params - initialize adapter->params.devlog
9470  *	@adap: the adapter
9471  *	@fw_attach: whether we can talk to the firmware
9472  *
9473  *	Initialize various fields of the adapter's Firmware Device Log
9474  *	Parameters structure.
9475  */
9476 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
9477 {
9478 	struct devlog_params *dparams = &adap->params.devlog;
9479 	u32 pf_dparams;
9480 	unsigned int devlog_meminfo;
9481 	struct fw_devlog_cmd devlog_cmd;
9482 	int ret;
9483 
9484 	/* If we're dealing with newer firmware, the Device Log Paramerters
9485 	 * are stored in a designated register which allows us to access the
9486 	 * Device Log even if we can't talk to the firmware.
9487 	 */
9488 	pf_dparams =
9489 		t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
9490 	if (pf_dparams) {
9491 		unsigned int nentries, nentries128;
9492 
9493 		dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
9494 		dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
9495 
9496 		nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
9497 		nentries = (nentries128 + 1) * 128;
9498 		dparams->size = nentries * sizeof(struct fw_devlog_e);
9499 
9500 		return 0;
9501 	}
9502 
9503 	/*
9504 	 * For any failing returns ...
9505 	 */
9506 	memset(dparams, 0, sizeof *dparams);
9507 
9508 	/*
9509 	 * If we can't talk to the firmware, there's really nothing we can do
9510 	 * at this point.
9511 	 */
9512 	if (!fw_attach)
9513 		return -ENXIO;
9514 
9515 	/* Otherwise, ask the firmware for it's Device Log Parameters.
9516 	 */
9517 	memset(&devlog_cmd, 0, sizeof devlog_cmd);
9518 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9519 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
9520 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9521 	ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9522 			 &devlog_cmd);
9523 	if (ret)
9524 		return ret;
9525 
9526 	devlog_meminfo =
9527 		be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9528 	dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
9529 	dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
9530 	dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9531 
9532 	return 0;
9533 }
9534 
9535 /**
9536  *	t4_init_sge_params - initialize adap->params.sge
9537  *	@adapter: the adapter
9538  *
9539  *	Initialize various fields of the adapter's SGE Parameters structure.
9540  */
9541 int t4_init_sge_params(struct adapter *adapter)
9542 {
9543 	u32 r;
9544 	struct sge_params *sp = &adapter->params.sge;
9545 	unsigned i, tscale = 1;
9546 
9547 	r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
9548 	sp->counter_val[0] = G_THRESHOLD_0(r);
9549 	sp->counter_val[1] = G_THRESHOLD_1(r);
9550 	sp->counter_val[2] = G_THRESHOLD_2(r);
9551 	sp->counter_val[3] = G_THRESHOLD_3(r);
9552 
9553 	if (chip_id(adapter) >= CHELSIO_T6) {
9554 		r = t4_read_reg(adapter, A_SGE_ITP_CONTROL);
9555 		tscale = G_TSCALE(r);
9556 		if (tscale == 0)
9557 			tscale = 1;
9558 		else
9559 			tscale += 2;
9560 	}
9561 
9562 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
9563 	sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale;
9564 	sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale;
9565 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
9566 	sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale;
9567 	sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale;
9568 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
9569 	sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale;
9570 	sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale;
9571 
9572 	r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
9573 	sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
9574 	if (is_t4(adapter))
9575 		sp->fl_starve_threshold2 = sp->fl_starve_threshold;
9576 	else if (is_t5(adapter))
9577 		sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
9578 	else
9579 		sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
9580 
9581 	/* egress queues: log2 of # of doorbells per BAR2 page */
9582 	r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
9583 	r >>= S_QUEUESPERPAGEPF0 +
9584 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9585 	sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
9586 
9587 	/* ingress queues: log2 of # of doorbells per BAR2 page */
9588 	r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
9589 	r >>= S_QUEUESPERPAGEPF0 +
9590 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
9591 	sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
9592 
9593 	r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
9594 	r >>= S_HOSTPAGESIZEPF0 +
9595 	    (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
9596 	sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
9597 
9598 	r = t4_read_reg(adapter, A_SGE_CONTROL);
9599 	sp->sge_control = r;
9600 	sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
9601 	sp->fl_pktshift = G_PKTSHIFT(r);
9602 	if (chip_id(adapter) <= CHELSIO_T5) {
9603 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9604 		    X_INGPADBOUNDARY_SHIFT);
9605 	} else {
9606 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
9607 		    X_T6_INGPADBOUNDARY_SHIFT);
9608 	}
9609 	if (is_t4(adapter))
9610 		sp->pack_boundary = sp->pad_boundary;
9611 	else {
9612 		r = t4_read_reg(adapter, A_SGE_CONTROL2);
9613 		if (G_INGPACKBOUNDARY(r) == 0)
9614 			sp->pack_boundary = 16;
9615 		else
9616 			sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
9617 	}
9618 	for (i = 0; i < SGE_FLBUF_SIZES; i++)
9619 		sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
9620 		    A_SGE_FL_BUFFER_SIZE0 + (4 * i));
9621 
9622 	return 0;
9623 }
9624 
9625 /* Convert the LE's hardware hash mask to a shorter filter mask. */
9626 static inline uint16_t
9627 hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode)
9628 {
9629 	static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1};
9630 	int i;
9631 	uint16_t filter_mask;
9632 	uint64_t mask;		/* field mask */
9633 
9634 	filter_mask = 0;
9635 	for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
9636 		if ((filter_mode & (1 << i)) == 0)
9637 			continue;
9638 		mask = (1 << width[i]) - 1;
9639 		if ((hashmask & mask) == mask)
9640 			filter_mask |= 1 << i;
9641 		hashmask >>= width[i];
9642 	}
9643 
9644 	return (filter_mask);
9645 }
9646 
9647 /*
9648  * Read and cache the adapter's compressed filter mode and ingress config.
9649  */
9650 static void
9651 read_filter_mode_and_ingress_config(struct adapter *adap)
9652 {
9653 	int rc;
9654 	uint32_t v, param[2], val[2];
9655 	struct tp_params *tpp = &adap->params.tp;
9656 	uint64_t hash_mask;
9657 
9658 	param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9659 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
9660 	    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
9661 	param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9662 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
9663 	    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
9664 	rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val);
9665 	if (rc == 0) {
9666 		tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]);
9667 		tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]);
9668 		tpp->vnic_mode = val[1];
9669 	} else {
9670 		/*
9671 		 * Old firmware.  Read filter mode/mask and ingress config
9672 		 * straight from the hardware.
9673 		 */
9674 		t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true);
9675 		tpp->filter_mode = v & 0xffff;
9676 
9677 		hash_mask = 0;
9678 		if (chip_id(adap) > CHELSIO_T4) {
9679 			v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3));
9680 			hash_mask = v;
9681 			v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4));
9682 			hash_mask |= (u64)v << 32;
9683 		}
9684 		tpp->filter_mask = hashmask_to_filtermask(hash_mask,
9685 		    tpp->filter_mode);
9686 
9687 		t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true);
9688 		if (v & F_VNIC)
9689 			tpp->vnic_mode = FW_VNIC_MODE_PF_VF;
9690 		else
9691 			tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN;
9692 	}
9693 
9694 	/*
9695 	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9696 	 * shift positions of several elements of the Compressed Filter Tuple
9697 	 * for this adapter which we need frequently ...
9698 	 */
9699 	tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
9700 	tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
9701 	tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
9702 	tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
9703 	tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
9704 	tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
9705 	tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
9706 	tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
9707 	tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
9708 	tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
9709 }
9710 
9711 /**
9712  *      t4_init_tp_params - initialize adap->params.tp
9713  *      @adap: the adapter
9714  *
9715  *      Initialize various fields of the adapter's TP Parameters structure.
9716  */
9717 int t4_init_tp_params(struct adapter *adap)
9718 {
9719 	u32 tx_len, rx_len, r, v;
9720 	struct tp_params *tpp = &adap->params.tp;
9721 
9722 	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
9723 	tpp->tre = G_TIMERRESOLUTION(v);
9724 	tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
9725 
9726 	read_filter_mode_and_ingress_config(adap);
9727 
9728 	if (chip_id(adap) > CHELSIO_T5) {
9729 		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
9730 		tpp->rx_pkt_encap = v & F_CRXPKTENC;
9731 	} else
9732 		tpp->rx_pkt_encap = false;
9733 
9734 	rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE);
9735 	tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE);
9736 
9737 	r = t4_read_reg(adap, A_TP_PARA_REG2);
9738 	rx_len = min(rx_len, G_MAXRXDATA(r));
9739 	tx_len = min(tx_len, G_MAXRXDATA(r));
9740 
9741 	r = t4_read_reg(adap, A_TP_PARA_REG7);
9742 	v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r));
9743 	rx_len = min(rx_len, v);
9744 	tx_len = min(tx_len, v);
9745 
9746 	tpp->max_tx_pdu = tx_len;
9747 	tpp->max_rx_pdu = rx_len;
9748 
9749 	return 0;
9750 }
9751 
9752 /**
9753  *      t4_filter_field_shift - calculate filter field shift
9754  *      @adap: the adapter
9755  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9756  *
9757  *      Return the shift position of a filter field within the Compressed
9758  *      Filter Tuple.  The filter field is specified via its selection bit
9759  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
9760  */
9761 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9762 {
9763 	const unsigned int filter_mode = adap->params.tp.filter_mode;
9764 	unsigned int sel;
9765 	int field_shift;
9766 
9767 	if ((filter_mode & filter_sel) == 0)
9768 		return -1;
9769 
9770 	for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9771 		switch (filter_mode & sel) {
9772 		case F_FCOE:
9773 			field_shift += W_FT_FCOE;
9774 			break;
9775 		case F_PORT:
9776 			field_shift += W_FT_PORT;
9777 			break;
9778 		case F_VNIC_ID:
9779 			field_shift += W_FT_VNIC_ID;
9780 			break;
9781 		case F_VLAN:
9782 			field_shift += W_FT_VLAN;
9783 			break;
9784 		case F_TOS:
9785 			field_shift += W_FT_TOS;
9786 			break;
9787 		case F_PROTOCOL:
9788 			field_shift += W_FT_PROTOCOL;
9789 			break;
9790 		case F_ETHERTYPE:
9791 			field_shift += W_FT_ETHERTYPE;
9792 			break;
9793 		case F_MACMATCH:
9794 			field_shift += W_FT_MACMATCH;
9795 			break;
9796 		case F_MPSHITTYPE:
9797 			field_shift += W_FT_MPSHITTYPE;
9798 			break;
9799 		case F_FRAGMENTATION:
9800 			field_shift += W_FT_FRAGMENTATION;
9801 			break;
9802 		}
9803 	}
9804 	return field_shift;
9805 }
9806 
9807 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
9808 {
9809 	u8 addr[6];
9810 	int ret, i, j;
9811 	struct port_info *p = adap2pinfo(adap, port_id);
9812 	u32 param, val;
9813 	struct vi_info *vi = &p->vi[0];
9814 
9815 	for (i = 0, j = -1; i <= p->port_id; i++) {
9816 		do {
9817 			j++;
9818 		} while ((adap->params.portvec & (1 << j)) == 0);
9819 	}
9820 
9821 	p->tx_chan = t4_get_tx_c_chan(adap, j);
9822 	p->rx_chan = t4_get_rx_c_chan(adap, j);
9823 	p->mps_bg_map = t4_get_mps_bg_map(adap, j);
9824 	p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j);
9825 	p->lport = j;
9826 
9827 	if (!(adap->flags & IS_VF) ||
9828 	    adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
9829  		t4_update_port_info(p);
9830 	}
9831 
9832 	ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size,
9833 	    &vi->vfvld, &vi->vin);
9834 	if (ret < 0)
9835 		return ret;
9836 
9837 	vi->viid = ret;
9838 	t4_os_set_hw_addr(p, addr);
9839 
9840 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
9841 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
9842 	    V_FW_PARAMS_PARAM_YZ(vi->viid);
9843 	ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
9844 	if (ret)
9845 		vi->rss_base = 0xffff;
9846 	else {
9847 		/* MPASS((val >> 16) == rss_size); */
9848 		vi->rss_base = val & 0xffff;
9849 	}
9850 
9851 	return 0;
9852 }
9853 
9854 /**
9855  *	t4_read_cimq_cfg - read CIM queue configuration
9856  *	@adap: the adapter
9857  *	@base: holds the queue base addresses in bytes
9858  *	@size: holds the queue sizes in bytes
9859  *	@thres: holds the queue full thresholds in bytes
9860  *
9861  *	Returns the current configuration of the CIM queues, starting with
9862  *	the IBQs, then the OBQs.
9863  */
9864 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9865 {
9866 	unsigned int i, v;
9867 	int cim_num_obq = adap->chip_params->cim_num_obq;
9868 
9869 	for (i = 0; i < CIM_NUM_IBQ; i++) {
9870 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
9871 			     V_QUENUMSELECT(i));
9872 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9873 		/* value is in 256-byte units */
9874 		*base++ = G_CIMQBASE(v) * 256;
9875 		*size++ = G_CIMQSIZE(v) * 256;
9876 		*thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
9877 	}
9878 	for (i = 0; i < cim_num_obq; i++) {
9879 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9880 			     V_QUENUMSELECT(i));
9881 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9882 		/* value is in 256-byte units */
9883 		*base++ = G_CIMQBASE(v) * 256;
9884 		*size++ = G_CIMQSIZE(v) * 256;
9885 	}
9886 }
9887 
9888 /**
9889  *	t4_read_cim_ibq - read the contents of a CIM inbound queue
9890  *	@adap: the adapter
9891  *	@qid: the queue index
9892  *	@data: where to store the queue contents
9893  *	@n: capacity of @data in 32-bit words
9894  *
9895  *	Reads the contents of the selected CIM queue starting at address 0 up
9896  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9897  *	error and the number of 32-bit words actually read on success.
9898  */
9899 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9900 {
9901 	int i, err, attempts;
9902 	unsigned int addr;
9903 	const unsigned int nwords = CIM_IBQ_SIZE * 4;
9904 
9905 	if (qid > 5 || (n & 3))
9906 		return -EINVAL;
9907 
9908 	addr = qid * nwords;
9909 	if (n > nwords)
9910 		n = nwords;
9911 
9912 	/* It might take 3-10ms before the IBQ debug read access is allowed.
9913 	 * Wait for 1 Sec with a delay of 1 usec.
9914 	 */
9915 	attempts = 1000000;
9916 
9917 	for (i = 0; i < n; i++, addr++) {
9918 		t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
9919 			     F_IBQDBGEN);
9920 		err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
9921 				      attempts, 1);
9922 		if (err)
9923 			return err;
9924 		*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
9925 	}
9926 	t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
9927 	return i;
9928 }
9929 
9930 /**
9931  *	t4_read_cim_obq - read the contents of a CIM outbound queue
9932  *	@adap: the adapter
9933  *	@qid: the queue index
9934  *	@data: where to store the queue contents
9935  *	@n: capacity of @data in 32-bit words
9936  *
9937  *	Reads the contents of the selected CIM queue starting at address 0 up
9938  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
9939  *	error and the number of 32-bit words actually read on success.
9940  */
9941 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9942 {
9943 	int i, err;
9944 	unsigned int addr, v, nwords;
9945 	int cim_num_obq = adap->chip_params->cim_num_obq;
9946 
9947 	if ((qid > (cim_num_obq - 1)) || (n & 3))
9948 		return -EINVAL;
9949 
9950 	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
9951 		     V_QUENUMSELECT(qid));
9952 	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
9953 
9954 	addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
9955 	nwords = G_CIMQSIZE(v) * 64;  /* same */
9956 	if (n > nwords)
9957 		n = nwords;
9958 
9959 	for (i = 0; i < n; i++, addr++) {
9960 		t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
9961 			     F_OBQDBGEN);
9962 		err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
9963 				      2, 1);
9964 		if (err)
9965 			return err;
9966 		*data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
9967 	}
9968 	t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
9969 	return i;
9970 }
9971 
9972 enum {
9973 	CIM_QCTL_BASE     = 0,
9974 	CIM_CTL_BASE      = 0x2000,
9975 	CIM_PBT_ADDR_BASE = 0x2800,
9976 	CIM_PBT_LRF_BASE  = 0x3000,
9977 	CIM_PBT_DATA_BASE = 0x3800
9978 };
9979 
9980 /**
9981  *	t4_cim_read - read a block from CIM internal address space
9982  *	@adap: the adapter
9983  *	@addr: the start address within the CIM address space
9984  *	@n: number of words to read
9985  *	@valp: where to store the result
9986  *
9987  *	Reads a block of 4-byte words from the CIM intenal address space.
9988  */
9989 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9990 		unsigned int *valp)
9991 {
9992 	int ret = 0;
9993 
9994 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
9995 		return -EBUSY;
9996 
9997 	for ( ; !ret && n--; addr += 4) {
9998 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
9999 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
10000 				      0, 5, 2);
10001 		if (!ret)
10002 			*valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
10003 	}
10004 	return ret;
10005 }
10006 
10007 /**
10008  *	t4_cim_write - write a block into CIM internal address space
10009  *	@adap: the adapter
10010  *	@addr: the start address within the CIM address space
10011  *	@n: number of words to write
10012  *	@valp: set of values to write
10013  *
10014  *	Writes a block of 4-byte words into the CIM intenal address space.
10015  */
10016 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
10017 		 const unsigned int *valp)
10018 {
10019 	int ret = 0;
10020 
10021 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
10022 		return -EBUSY;
10023 
10024 	for ( ; !ret && n--; addr += 4) {
10025 		t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
10026 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
10027 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
10028 				      0, 5, 2);
10029 	}
10030 	return ret;
10031 }
10032 
10033 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
10034 			 unsigned int val)
10035 {
10036 	return t4_cim_write(adap, addr, 1, &val);
10037 }
10038 
10039 /**
10040  *	t4_cim_ctl_read - read a block from CIM control region
10041  *	@adap: the adapter
10042  *	@addr: the start address within the CIM control region
10043  *	@n: number of words to read
10044  *	@valp: where to store the result
10045  *
10046  *	Reads a block of 4-byte words from the CIM control region.
10047  */
10048 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
10049 		    unsigned int *valp)
10050 {
10051 	return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
10052 }
10053 
10054 /**
10055  *	t4_cim_read_la - read CIM LA capture buffer
10056  *	@adap: the adapter
10057  *	@la_buf: where to store the LA data
10058  *	@wrptr: the HW write pointer within the capture buffer
10059  *
10060  *	Reads the contents of the CIM LA buffer with the most recent entry at
10061  *	the end	of the returned data and with the entry at @wrptr first.
10062  *	We try to leave the LA in the running state we find it in.
10063  */
10064 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
10065 {
10066 	int i, ret;
10067 	unsigned int cfg, val, idx;
10068 
10069 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
10070 	if (ret)
10071 		return ret;
10072 
10073 	if (cfg & F_UPDBGLAEN) {	/* LA is running, freeze it */
10074 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
10075 		if (ret)
10076 			return ret;
10077 	}
10078 
10079 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
10080 	if (ret)
10081 		goto restart;
10082 
10083 	idx = G_UPDBGLAWRPTR(val);
10084 	if (wrptr)
10085 		*wrptr = idx;
10086 
10087 	for (i = 0; i < adap->params.cim_la_size; i++) {
10088 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
10089 				    V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
10090 		if (ret)
10091 			break;
10092 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
10093 		if (ret)
10094 			break;
10095 		if (val & F_UPDBGLARDEN) {
10096 			ret = -ETIMEDOUT;
10097 			break;
10098 		}
10099 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
10100 		if (ret)
10101 			break;
10102 
10103 		/* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
10104 		 * identify the 32-bit portion of the full 312-bit data
10105 		 */
10106 		if (is_t6(adap) && (idx & 0xf) >= 9)
10107 			idx = (idx & 0xff0) + 0x10;
10108 		else
10109 			idx++;
10110 		/* address can't exceed 0xfff */
10111 		idx &= M_UPDBGLARDPTR;
10112 	}
10113 restart:
10114 	if (cfg & F_UPDBGLAEN) {
10115 		int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
10116 				      cfg & ~F_UPDBGLARDEN);
10117 		if (!ret)
10118 			ret = r;
10119 	}
10120 	return ret;
10121 }
10122 
10123 /**
10124  *	t4_tp_read_la - read TP LA capture buffer
10125  *	@adap: the adapter
10126  *	@la_buf: where to store the LA data
10127  *	@wrptr: the HW write pointer within the capture buffer
10128  *
10129  *	Reads the contents of the TP LA buffer with the most recent entry at
10130  *	the end	of the returned data and with the entry at @wrptr first.
10131  *	We leave the LA in the running state we find it in.
10132  */
10133 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
10134 {
10135 	bool last_incomplete;
10136 	unsigned int i, cfg, val, idx;
10137 
10138 	cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
10139 	if (cfg & F_DBGLAENABLE)			/* freeze LA */
10140 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
10141 			     adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
10142 
10143 	val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
10144 	idx = G_DBGLAWPTR(val);
10145 	last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
10146 	if (last_incomplete)
10147 		idx = (idx + 1) & M_DBGLARPTR;
10148 	if (wrptr)
10149 		*wrptr = idx;
10150 
10151 	val &= 0xffff;
10152 	val &= ~V_DBGLARPTR(M_DBGLARPTR);
10153 	val |= adap->params.tp.la_mask;
10154 
10155 	for (i = 0; i < TPLA_SIZE; i++) {
10156 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
10157 		la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
10158 		idx = (idx + 1) & M_DBGLARPTR;
10159 	}
10160 
10161 	/* Wipe out last entry if it isn't valid */
10162 	if (last_incomplete)
10163 		la_buf[TPLA_SIZE - 1] = ~0ULL;
10164 
10165 	if (cfg & F_DBGLAENABLE)		/* restore running state */
10166 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
10167 			     cfg | adap->params.tp.la_mask);
10168 }
10169 
10170 /*
10171  * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10172  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
10173  * state for more than the Warning Threshold then we'll issue a warning about
10174  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
10175  * appears to be hung every Warning Repeat second till the situation clears.
10176  * If the situation clears, we'll note that as well.
10177  */
10178 #define SGE_IDMA_WARN_THRESH 1
10179 #define SGE_IDMA_WARN_REPEAT 300
10180 
10181 /**
10182  *	t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10183  *	@adapter: the adapter
10184  *	@idma: the adapter IDMA Monitor state
10185  *
10186  *	Initialize the state of an SGE Ingress DMA Monitor.
10187  */
10188 void t4_idma_monitor_init(struct adapter *adapter,
10189 			  struct sge_idma_monitor_state *idma)
10190 {
10191 	/* Initialize the state variables for detecting an SGE Ingress DMA
10192 	 * hang.  The SGE has internal counters which count up on each clock
10193 	 * tick whenever the SGE finds its Ingress DMA State Engines in the
10194 	 * same state they were on the previous clock tick.  The clock used is
10195 	 * the Core Clock so we have a limit on the maximum "time" they can
10196 	 * record; typically a very small number of seconds.  For instance,
10197 	 * with a 600MHz Core Clock, we can only count up to a bit more than
10198 	 * 7s.  So we'll synthesize a larger counter in order to not run the
10199 	 * risk of having the "timers" overflow and give us the flexibility to
10200 	 * maintain a Hung SGE State Machine of our own which operates across
10201 	 * a longer time frame.
10202 	 */
10203 	idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10204 	idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
10205 }
10206 
10207 /**
10208  *	t4_idma_monitor - monitor SGE Ingress DMA state
10209  *	@adapter: the adapter
10210  *	@idma: the adapter IDMA Monitor state
10211  *	@hz: number of ticks/second
10212  *	@ticks: number of ticks since the last IDMA Monitor call
10213  */
10214 void t4_idma_monitor(struct adapter *adapter,
10215 		     struct sge_idma_monitor_state *idma,
10216 		     int hz, int ticks)
10217 {
10218 	int i, idma_same_state_cnt[2];
10219 
10220 	 /* Read the SGE Debug Ingress DMA Same State Count registers.  These
10221 	  * are counters inside the SGE which count up on each clock when the
10222 	  * SGE finds its Ingress DMA State Engines in the same states they
10223 	  * were in the previous clock.  The counters will peg out at
10224 	  * 0xffffffff without wrapping around so once they pass the 1s
10225 	  * threshold they'll stay above that till the IDMA state changes.
10226 	  */
10227 	t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
10228 	idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
10229 	idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10230 
10231 	for (i = 0; i < 2; i++) {
10232 		u32 debug0, debug11;
10233 
10234 		/* If the Ingress DMA Same State Counter ("timer") is less
10235 		 * than 1s, then we can reset our synthesized Stall Timer and
10236 		 * continue.  If we have previously emitted warnings about a
10237 		 * potential stalled Ingress Queue, issue a note indicating
10238 		 * that the Ingress Queue has resumed forward progress.
10239 		 */
10240 		if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10241 			if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
10242 				CH_WARN(adapter, "SGE idma%d, queue %u, "
10243 					"resumed after %d seconds\n",
10244 					i, idma->idma_qid[i],
10245 					idma->idma_stalled[i]/hz);
10246 			idma->idma_stalled[i] = 0;
10247 			continue;
10248 		}
10249 
10250 		/* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10251 		 * domain.  The first time we get here it'll be because we
10252 		 * passed the 1s Threshold; each additional time it'll be
10253 		 * because the RX Timer Callback is being fired on its regular
10254 		 * schedule.
10255 		 *
10256 		 * If the stall is below our Potential Hung Ingress Queue
10257 		 * Warning Threshold, continue.
10258 		 */
10259 		if (idma->idma_stalled[i] == 0) {
10260 			idma->idma_stalled[i] = hz;
10261 			idma->idma_warn[i] = 0;
10262 		} else {
10263 			idma->idma_stalled[i] += ticks;
10264 			idma->idma_warn[i] -= ticks;
10265 		}
10266 
10267 		if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
10268 			continue;
10269 
10270 		/* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10271 		 */
10272 		if (idma->idma_warn[i] > 0)
10273 			continue;
10274 		idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
10275 
10276 		/* Read and save the SGE IDMA State and Queue ID information.
10277 		 * We do this every time in case it changes across time ...
10278 		 * can't be too careful ...
10279 		 */
10280 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
10281 		debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10282 		idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10283 
10284 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
10285 		debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
10286 		idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10287 
10288 		CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
10289 			" state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10290 			i, idma->idma_qid[i], idma->idma_state[i],
10291 			idma->idma_stalled[i]/hz,
10292 			debug0, debug11);
10293 		t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10294 	}
10295 }
10296 
10297 /**
10298  *     t4_set_vf_mac - Set MAC address for the specified VF
10299  *     @adapter: The adapter
10300  *     @pf: the PF used to instantiate the VFs
10301  *     @vf: one of the VFs instantiated by the specified PF
10302  *     @naddr: the number of MAC addresses
10303  *     @addr: the MAC address(es) to be set to the specified VF
10304  */
10305 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf,
10306 		  unsigned int naddr, u8 *addr)
10307 {
10308 	struct fw_acl_mac_cmd cmd;
10309 
10310 	memset(&cmd, 0, sizeof(cmd));
10311 	cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) |
10312 				    F_FW_CMD_REQUEST |
10313 				    F_FW_CMD_WRITE |
10314 				    V_FW_ACL_MAC_CMD_PFN(pf) |
10315 				    V_FW_ACL_MAC_CMD_VFN(vf));
10316 
10317 	/* Note: Do not enable the ACL */
10318 	cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10319 	cmd.nmac = naddr;
10320 
10321 	switch (pf) {
10322 	case 3:
10323 		memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10324 		break;
10325 	case 2:
10326 		memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10327 		break;
10328 	case 1:
10329 		memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10330 		break;
10331 	case 0:
10332 		memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10333 		break;
10334 	}
10335 
10336 	return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10337 }
10338 
10339 /**
10340  *	t4_read_pace_tbl - read the pace table
10341  *	@adap: the adapter
10342  *	@pace_vals: holds the returned values
10343  *
10344  *	Returns the values of TP's pace table in microseconds.
10345  */
10346 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10347 {
10348 	unsigned int i, v;
10349 
10350 	for (i = 0; i < NTX_SCHED; i++) {
10351 		t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
10352 		v = t4_read_reg(adap, A_TP_PACE_TABLE);
10353 		pace_vals[i] = dack_ticks_to_usec(adap, v);
10354 	}
10355 }
10356 
10357 /**
10358  *	t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10359  *	@adap: the adapter
10360  *	@sched: the scheduler index
10361  *	@kbps: the byte rate in Kbps
10362  *	@ipg: the interpacket delay in tenths of nanoseconds
10363  *
10364  *	Return the current configuration of a HW Tx scheduler.
10365  */
10366 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
10367 		     unsigned int *ipg, bool sleep_ok)
10368 {
10369 	unsigned int v, addr, bpt, cpt;
10370 
10371 	if (kbps) {
10372 		addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
10373 		t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10374 		if (sched & 1)
10375 			v >>= 16;
10376 		bpt = (v >> 8) & 0xff;
10377 		cpt = v & 0xff;
10378 		if (!cpt)
10379 			*kbps = 0;	/* scheduler disabled */
10380 		else {
10381 			v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10382 			*kbps = (v * bpt) / 125;
10383 		}
10384 	}
10385 	if (ipg) {
10386 		addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
10387 		t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10388 		if (sched & 1)
10389 			v >>= 16;
10390 		v &= 0xffff;
10391 		*ipg = (10000 * v) / core_ticks_per_usec(adap);
10392 	}
10393 }
10394 
10395 /**
10396  *	t4_load_cfg - download config file
10397  *	@adap: the adapter
10398  *	@cfg_data: the cfg text file to write
10399  *	@size: text file size
10400  *
10401  *	Write the supplied config text file to the card's serial flash.
10402  */
10403 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10404 {
10405 	int ret, i, n, cfg_addr;
10406 	unsigned int addr;
10407 	unsigned int flash_cfg_start_sec;
10408 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10409 
10410 	cfg_addr = t4_flash_cfg_addr(adap);
10411 	if (cfg_addr < 0)
10412 		return cfg_addr;
10413 
10414 	addr = cfg_addr;
10415 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
10416 
10417 	if (size > FLASH_CFG_MAX_SIZE) {
10418 		CH_ERR(adap, "cfg file too large, max is %u bytes\n",
10419 		       FLASH_CFG_MAX_SIZE);
10420 		return -EFBIG;
10421 	}
10422 
10423 	i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,	/* # of sectors spanned */
10424 			 sf_sec_size);
10425 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10426 				     flash_cfg_start_sec + i - 1);
10427 	/*
10428 	 * If size == 0 then we're simply erasing the FLASH sectors associated
10429 	 * with the on-adapter Firmware Configuration File.
10430 	 */
10431 	if (ret || size == 0)
10432 		goto out;
10433 
10434 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
10435 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10436 		if ( (size - i) <  SF_PAGE_SIZE)
10437 			n = size - i;
10438 		else
10439 			n = SF_PAGE_SIZE;
10440 		ret = t4_write_flash(adap, addr, n, cfg_data, 1);
10441 		if (ret)
10442 			goto out;
10443 
10444 		addr += SF_PAGE_SIZE;
10445 		cfg_data += SF_PAGE_SIZE;
10446 	}
10447 
10448 out:
10449 	if (ret)
10450 		CH_ERR(adap, "config file %s failed %d\n",
10451 		       (size == 0 ? "clear" : "download"), ret);
10452 	return ret;
10453 }
10454 
10455 /**
10456  *	t5_fw_init_extern_mem - initialize the external memory
10457  *	@adap: the adapter
10458  *
10459  *	Initializes the external memory on T5.
10460  */
10461 int t5_fw_init_extern_mem(struct adapter *adap)
10462 {
10463 	u32 params[1], val[1];
10464 	int ret;
10465 
10466 	if (!is_t5(adap))
10467 		return 0;
10468 
10469 	val[0] = 0xff; /* Initialize all MCs */
10470 	params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10471 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
10472 	ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
10473 			FW_CMD_MAX_TIMEOUT);
10474 
10475 	return ret;
10476 }
10477 
10478 /* BIOS boot headers */
10479 typedef struct pci_expansion_rom_header {
10480 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
10481 	u8	reserved[22]; /* Reserved per processor Architecture data */
10482 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
10483 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
10484 
10485 /* Legacy PCI Expansion ROM Header */
10486 typedef struct legacy_pci_expansion_rom_header {
10487 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
10488 	u8	size512; /* Current Image Size in units of 512 bytes */
10489 	u8	initentry_point[4];
10490 	u8	cksum; /* Checksum computed on the entire Image */
10491 	u8	reserved[16]; /* Reserved */
10492 	u8	pcir_offset[2]; /* Offset to PCI Data Struture */
10493 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
10494 
10495 /* EFI PCI Expansion ROM Header */
10496 typedef struct efi_pci_expansion_rom_header {
10497 	u8	signature[2]; // ROM signature. The value 0xaa55
10498 	u8	initialization_size[2]; /* Units 512. Includes this header */
10499 	u8	efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
10500 	u8	efi_subsystem[2]; /* Subsystem value for EFI image header */
10501 	u8	efi_machine_type[2]; /* Machine type from EFI image header */
10502 	u8	compression_type[2]; /* Compression type. */
10503 		/*
10504 		 * Compression type definition
10505 		 * 0x0: uncompressed
10506 		 * 0x1: Compressed
10507 		 * 0x2-0xFFFF: Reserved
10508 		 */
10509 	u8	reserved[8]; /* Reserved */
10510 	u8	efi_image_header_offset[2]; /* Offset to EFI Image */
10511 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
10512 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
10513 
10514 /* PCI Data Structure Format */
10515 typedef struct pcir_data_structure { /* PCI Data Structure */
10516 	u8	signature[4]; /* Signature. The string "PCIR" */
10517 	u8	vendor_id[2]; /* Vendor Identification */
10518 	u8	device_id[2]; /* Device Identification */
10519 	u8	vital_product[2]; /* Pointer to Vital Product Data */
10520 	u8	length[2]; /* PCIR Data Structure Length */
10521 	u8	revision; /* PCIR Data Structure Revision */
10522 	u8	class_code[3]; /* Class Code */
10523 	u8	image_length[2]; /* Image Length. Multiple of 512B */
10524 	u8	code_revision[2]; /* Revision Level of Code/Data */
10525 	u8	code_type; /* Code Type. */
10526 		/*
10527 		 * PCI Expansion ROM Code Types
10528 		 * 0x00: Intel IA-32, PC-AT compatible. Legacy
10529 		 * 0x01: Open Firmware standard for PCI. FCODE
10530 		 * 0x02: Hewlett-Packard PA RISC. HP reserved
10531 		 * 0x03: EFI Image. EFI
10532 		 * 0x04-0xFF: Reserved.
10533 		 */
10534 	u8	indicator; /* Indicator. Identifies the last image in the ROM */
10535 	u8	reserved[2]; /* Reserved */
10536 } pcir_data_t; /* PCI__DATA_STRUCTURE */
10537 
10538 /* BOOT constants */
10539 enum {
10540 	BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
10541 	BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
10542 	BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
10543 	BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
10544 	BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment  */
10545 	VENDOR_ID = 0x1425, /* Vendor ID */
10546 	PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
10547 };
10548 
10549 /*
10550  *	modify_device_id - Modifies the device ID of the Boot BIOS image
10551  *	@adatper: the device ID to write.
10552  *	@boot_data: the boot image to modify.
10553  *
10554  *	Write the supplied device ID to the boot BIOS image.
10555  */
10556 static void modify_device_id(int device_id, u8 *boot_data)
10557 {
10558 	legacy_pci_exp_rom_header_t *header;
10559 	pcir_data_t *pcir_header;
10560 	u32 cur_header = 0;
10561 
10562 	/*
10563 	 * Loop through all chained images and change the device ID's
10564 	 */
10565 	while (1) {
10566 		header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
10567 		pcir_header = (pcir_data_t *) &boot_data[cur_header +
10568 			      le16_to_cpu(*(u16*)header->pcir_offset)];
10569 
10570 		/*
10571 		 * Only modify the Device ID if code type is Legacy or HP.
10572 		 * 0x00: Okay to modify
10573 		 * 0x01: FCODE. Do not be modify
10574 		 * 0x03: Okay to modify
10575 		 * 0x04-0xFF: Do not modify
10576 		 */
10577 		if (pcir_header->code_type == 0x00) {
10578 			u8 csum = 0;
10579 			int i;
10580 
10581 			/*
10582 			 * Modify Device ID to match current adatper
10583 			 */
10584 			*(u16*) pcir_header->device_id = device_id;
10585 
10586 			/*
10587 			 * Set checksum temporarily to 0.
10588 			 * We will recalculate it later.
10589 			 */
10590 			header->cksum = 0x0;
10591 
10592 			/*
10593 			 * Calculate and update checksum
10594 			 */
10595 			for (i = 0; i < (header->size512 * 512); i++)
10596 				csum += (u8)boot_data[cur_header + i];
10597 
10598 			/*
10599 			 * Invert summed value to create the checksum
10600 			 * Writing new checksum value directly to the boot data
10601 			 */
10602 			boot_data[cur_header + 7] = -csum;
10603 
10604 		} else if (pcir_header->code_type == 0x03) {
10605 
10606 			/*
10607 			 * Modify Device ID to match current adatper
10608 			 */
10609 			*(u16*) pcir_header->device_id = device_id;
10610 
10611 		}
10612 
10613 
10614 		/*
10615 		 * Check indicator element to identify if this is the last
10616 		 * image in the ROM.
10617 		 */
10618 		if (pcir_header->indicator & 0x80)
10619 			break;
10620 
10621 		/*
10622 		 * Move header pointer up to the next image in the ROM.
10623 		 */
10624 		cur_header += header->size512 * 512;
10625 	}
10626 }
10627 
10628 /*
10629  *	t4_load_boot - download boot flash
10630  *	@adapter: the adapter
10631  *	@boot_data: the boot image to write
10632  *	@boot_addr: offset in flash to write boot_data
10633  *	@size: image size
10634  *
10635  *	Write the supplied boot image to the card's serial flash.
10636  *	The boot image has the following sections: a 28-byte header and the
10637  *	boot image.
10638  */
10639 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10640 		 unsigned int boot_addr, unsigned int size)
10641 {
10642 	pci_exp_rom_header_t *header;
10643 	int pcir_offset ;
10644 	pcir_data_t *pcir_header;
10645 	int ret, addr;
10646 	uint16_t device_id;
10647 	unsigned int i;
10648 	unsigned int boot_sector = (boot_addr * 1024 );
10649 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10650 
10651 	/*
10652 	 * Make sure the boot image does not encroach on the firmware region
10653 	 */
10654 	if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10655 		CH_ERR(adap, "boot image encroaching on firmware region\n");
10656 		return -EFBIG;
10657 	}
10658 
10659 	/*
10660 	 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10661 	 * and Boot configuration data sections. These 3 boot sections span
10662 	 * sectors 0 to 7 in flash and live right before the FW image location.
10663 	 */
10664 	i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
10665 			sf_sec_size);
10666 	ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10667 				     (boot_sector >> 16) + i - 1);
10668 
10669 	/*
10670 	 * If size == 0 then we're simply erasing the FLASH sectors associated
10671 	 * with the on-adapter option ROM file
10672 	 */
10673 	if (ret || (size == 0))
10674 		goto out;
10675 
10676 	/* Get boot header */
10677 	header = (pci_exp_rom_header_t *)boot_data;
10678 	pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
10679 	/* PCIR Data Structure */
10680 	pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
10681 
10682 	/*
10683 	 * Perform some primitive sanity testing to avoid accidentally
10684 	 * writing garbage over the boot sectors.  We ought to check for
10685 	 * more but it's not worth it for now ...
10686 	 */
10687 	if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10688 		CH_ERR(adap, "boot image too small/large\n");
10689 		return -EFBIG;
10690 	}
10691 
10692 #ifndef CHELSIO_T4_DIAGS
10693 	/*
10694 	 * Check BOOT ROM header signature
10695 	 */
10696 	if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
10697 		CH_ERR(adap, "Boot image missing signature\n");
10698 		return -EINVAL;
10699 	}
10700 
10701 	/*
10702 	 * Check PCI header signature
10703 	 */
10704 	if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
10705 		CH_ERR(adap, "PCI header missing signature\n");
10706 		return -EINVAL;
10707 	}
10708 
10709 	/*
10710 	 * Check Vendor ID matches Chelsio ID
10711 	 */
10712 	if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
10713 		CH_ERR(adap, "Vendor ID missing signature\n");
10714 		return -EINVAL;
10715 	}
10716 #endif
10717 
10718 	/*
10719 	 * Retrieve adapter's device ID
10720 	 */
10721 	t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
10722 	/* Want to deal with PF 0 so I strip off PF 4 indicator */
10723 	device_id = device_id & 0xf0ff;
10724 
10725 	/*
10726 	 * Check PCIE Device ID
10727 	 */
10728 	if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
10729 		/*
10730 		 * Change the device ID in the Boot BIOS image to match
10731 		 * the Device ID of the current adapter.
10732 		 */
10733 		modify_device_id(device_id, boot_data);
10734 	}
10735 
10736 	/*
10737 	 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10738 	 * we finish copying the rest of the boot image. This will ensure
10739 	 * that the BIOS boot header will only be written if the boot image
10740 	 * was written in full.
10741 	 */
10742 	addr = boot_sector;
10743 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10744 		addr += SF_PAGE_SIZE;
10745 		boot_data += SF_PAGE_SIZE;
10746 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
10747 		if (ret)
10748 			goto out;
10749 	}
10750 
10751 	ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10752 			     (const u8 *)header, 0);
10753 
10754 out:
10755 	if (ret)
10756 		CH_ERR(adap, "boot image download failed, error %d\n", ret);
10757 	return ret;
10758 }
10759 
10760 /*
10761  *	t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
10762  *	@adapter: the adapter
10763  *
10764  *	Return the address within the flash where the OptionROM Configuration
10765  *	is stored, or an error if the device FLASH is too small to contain
10766  *	a OptionROM Configuration.
10767  */
10768 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10769 {
10770 	/*
10771 	 * If the device FLASH isn't large enough to hold a Firmware
10772 	 * Configuration File, return an error.
10773 	 */
10774 	if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10775 		return -ENOSPC;
10776 
10777 	return FLASH_BOOTCFG_START;
10778 }
10779 
10780 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
10781 {
10782 	int ret, i, n, cfg_addr;
10783 	unsigned int addr;
10784 	unsigned int flash_cfg_start_sec;
10785 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10786 
10787 	cfg_addr = t4_flash_bootcfg_addr(adap);
10788 	if (cfg_addr < 0)
10789 		return cfg_addr;
10790 
10791 	addr = cfg_addr;
10792 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
10793 
10794 	if (size > FLASH_BOOTCFG_MAX_SIZE) {
10795 		CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
10796 			FLASH_BOOTCFG_MAX_SIZE);
10797 		return -EFBIG;
10798 	}
10799 
10800 	i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
10801 			 sf_sec_size);
10802 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10803 					flash_cfg_start_sec + i - 1);
10804 
10805 	/*
10806 	 * If size == 0 then we're simply erasing the FLASH sectors associated
10807 	 * with the on-adapter OptionROM Configuration File.
10808 	 */
10809 	if (ret || size == 0)
10810 		goto out;
10811 
10812 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
10813 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
10814 		if ( (size - i) <  SF_PAGE_SIZE)
10815 			n = size - i;
10816 		else
10817 			n = SF_PAGE_SIZE;
10818 		ret = t4_write_flash(adap, addr, n, cfg_data, 0);
10819 		if (ret)
10820 			goto out;
10821 
10822 		addr += SF_PAGE_SIZE;
10823 		cfg_data += SF_PAGE_SIZE;
10824 	}
10825 
10826 out:
10827 	if (ret)
10828 		CH_ERR(adap, "boot config data %s failed %d\n",
10829 				(size == 0 ? "clear" : "download"), ret);
10830 	return ret;
10831 }
10832 
10833 /**
10834  *	t4_set_filter_cfg - set up filter mode/mask and ingress config.
10835  *	@adap: the adapter
10836  *	@mode: a bitmap selecting which optional filter components to enable
10837  *	@mask: a bitmap selecting which components to enable in filter mask
10838  *	@vnic_mode: the ingress config/vnic mode setting
10839  *
10840  *	Sets the filter mode and mask by selecting the optional components to
10841  *	enable in filter tuples.  Returns 0 on success and a negative error if
10842  *	the requested mode needs more bits than are available for optional
10843  *	components.  The filter mask must be a subset of the filter mode.
10844  */
10845 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode)
10846 {
10847 	static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1};
10848 	int i, nbits, rc;
10849 	uint32_t param, val;
10850 	uint16_t fmode, fmask;
10851 	const int maxbits = adap->chip_params->filter_opt_len;
10852 
10853 	if (mode != -1 || mask != -1) {
10854 		if (mode != -1) {
10855 			fmode = mode;
10856 			nbits = 0;
10857 			for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
10858 				if (fmode & (1 << i))
10859 					nbits += width[i];
10860 			}
10861 			if (nbits > maxbits) {
10862 				CH_ERR(adap, "optional fields in the filter "
10863 				    "mode (0x%x) add up to %d bits "
10864 				    "(must be <= %db).  Remove some fields and "
10865 				    "try again.\n", fmode, nbits, maxbits);
10866 				return -E2BIG;
10867 			}
10868 
10869 			/*
10870 			 * Hardware wants the bits to be maxed out.  Keep
10871 			 * setting them until there's no room for more.
10872 			 */
10873 			for (i = S_FCOE; i <= S_FRAGMENTATION; i++) {
10874 				if (fmode & (1 << i))
10875 					continue;
10876 				if (nbits + width[i] <= maxbits) {
10877 					fmode |= 1 << i;
10878 					nbits += width[i];
10879 					if (nbits == maxbits)
10880 						break;
10881 				}
10882 			}
10883 
10884 			fmask = fmode & adap->params.tp.filter_mask;
10885 			if (fmask != adap->params.tp.filter_mask) {
10886 				CH_WARN(adap,
10887 				    "filter mask will be changed from 0x%x to "
10888 				    "0x%x to comply with the filter mode (0x%x).\n",
10889 				    adap->params.tp.filter_mask, fmask, fmode);
10890 			}
10891 		} else {
10892 			fmode = adap->params.tp.filter_mode;
10893 			fmask = mask;
10894 			if ((fmode | fmask) != fmode) {
10895 				CH_ERR(adap,
10896 				    "filter mask (0x%x) must be a subset of "
10897 				    "the filter mode (0x%x).\n", fmask, fmode);
10898 				return -EINVAL;
10899 			}
10900 		}
10901 
10902 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10903 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
10904 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK);
10905 		val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) |
10906 		    V_FW_PARAMS_PARAM_FILTER_MASK(fmask);
10907 		rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param,
10908 		    &val);
10909 		if (rc < 0)
10910 			return rc;
10911 	}
10912 
10913 	if (vnic_mode != -1) {
10914 		param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
10915 		    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) |
10916 		    V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE);
10917 		val = vnic_mode;
10918 		rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param,
10919 		    &val);
10920 		if (rc < 0)
10921 			return rc;
10922 	}
10923 
10924 	/* Refresh. */
10925 	read_filter_mode_and_ingress_config(adap);
10926 
10927 	return 0;
10928 }
10929 
10930 /**
10931  *	t4_clr_port_stats - clear port statistics
10932  *	@adap: the adapter
10933  *	@idx: the port index
10934  *
10935  *	Clear HW statistics for the given port.
10936  */
10937 void t4_clr_port_stats(struct adapter *adap, int idx)
10938 {
10939 	unsigned int i;
10940 	u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map;
10941 	u32 port_base_addr;
10942 
10943 	if (is_t4(adap))
10944 		port_base_addr = PORT_BASE(idx);
10945 	else
10946 		port_base_addr = T5_PORT_BASE(idx);
10947 
10948 	for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
10949 			i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
10950 		t4_write_reg(adap, port_base_addr + i, 0);
10951 	for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
10952 			i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
10953 		t4_write_reg(adap, port_base_addr + i, 0);
10954 	for (i = 0; i < 4; i++)
10955 		if (bgmap & (1 << i)) {
10956 			t4_write_reg(adap,
10957 			A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
10958 			t4_write_reg(adap,
10959 			A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
10960 		}
10961 }
10962 
10963 /**
10964  *	t4_i2c_io - read/write I2C data from adapter
10965  *	@adap: the adapter
10966  *	@port: Port number if per-port device; <0 if not
10967  *	@devid: per-port device ID or absolute device ID
10968  *	@offset: byte offset into device I2C space
10969  *	@len: byte length of I2C space data
10970  *	@buf: buffer in which to return I2C data for read
10971  *	      buffer which holds the I2C data for write
10972  *	@write: if true, do a write; else do a read
10973  *	Reads/Writes the I2C data from/to the indicated device and location.
10974  */
10975 int t4_i2c_io(struct adapter *adap, unsigned int mbox,
10976 	      int port, unsigned int devid,
10977 	      unsigned int offset, unsigned int len,
10978 	      u8 *buf, bool write)
10979 {
10980 	struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10981 	unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10982 	int ret = 0;
10983 
10984 	if (len > I2C_PAGE_SIZE)
10985 		return -EINVAL;
10986 
10987 	/* Dont allow reads that spans multiple pages */
10988 	if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10989 		return -EINVAL;
10990 
10991 	memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10992 	ldst_cmd.op_to_addrspace =
10993 		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
10994 			    F_FW_CMD_REQUEST |
10995 			    (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) |
10996 			    V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C));
10997 	ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10998 	ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10999 	ldst_cmd.u.i2c.did = devid;
11000 
11001 	while (len > 0) {
11002 		unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
11003 
11004 		ldst_cmd.u.i2c.boffset = offset;
11005 		ldst_cmd.u.i2c.blen = i2c_len;
11006 
11007 		if (write)
11008 			memcpy(ldst_cmd.u.i2c.data, buf, i2c_len);
11009 
11010 		ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
11011 				 write ? NULL : &ldst_rpl);
11012 		if (ret)
11013 			break;
11014 
11015 		if (!write)
11016 			memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
11017 		offset += i2c_len;
11018 		buf += i2c_len;
11019 		len -= i2c_len;
11020 	}
11021 
11022 	return ret;
11023 }
11024 
11025 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
11026 	      int port, unsigned int devid,
11027 	      unsigned int offset, unsigned int len,
11028 	      u8 *buf)
11029 {
11030 	return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false);
11031 }
11032 
11033 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
11034 	      int port, unsigned int devid,
11035 	      unsigned int offset, unsigned int len,
11036 	      u8 *buf)
11037 {
11038 	return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true);
11039 }
11040 
11041 /**
11042  * 	t4_sge_ctxt_rd - read an SGE context through FW
11043  * 	@adap: the adapter
11044  * 	@mbox: mailbox to use for the FW command
11045  * 	@cid: the context id
11046  * 	@ctype: the context type
11047  * 	@data: where to store the context data
11048  *
11049  * 	Issues a FW command through the given mailbox to read an SGE context.
11050  */
11051 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
11052 		   enum ctxt_type ctype, u32 *data)
11053 {
11054 	int ret;
11055 	struct fw_ldst_cmd c;
11056 
11057 	if (ctype == CTXT_EGRESS)
11058 		ret = FW_LDST_ADDRSPC_SGE_EGRC;
11059 	else if (ctype == CTXT_INGRESS)
11060 		ret = FW_LDST_ADDRSPC_SGE_INGC;
11061 	else if (ctype == CTXT_FLM)
11062 		ret = FW_LDST_ADDRSPC_SGE_FLMC;
11063 	else
11064 		ret = FW_LDST_ADDRSPC_SGE_CONMC;
11065 
11066 	memset(&c, 0, sizeof(c));
11067 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
11068 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
11069 					V_FW_LDST_CMD_ADDRSPACE(ret));
11070 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
11071 	c.u.idctxt.physid = cpu_to_be32(cid);
11072 
11073 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11074 	if (ret == 0) {
11075 		data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
11076 		data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
11077 		data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
11078 		data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
11079 		data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
11080 		data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
11081 	}
11082 	return ret;
11083 }
11084 
11085 /**
11086  * 	t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
11087  * 	@adap: the adapter
11088  * 	@cid: the context id
11089  * 	@ctype: the context type
11090  * 	@data: where to store the context data
11091  *
11092  * 	Reads an SGE context directly, bypassing FW.  This is only for
11093  * 	debugging when FW is unavailable.
11094  */
11095 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
11096 		      u32 *data)
11097 {
11098 	int i, ret;
11099 
11100 	t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
11101 	ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
11102 	if (!ret)
11103 		for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
11104 			*data++ = t4_read_reg(adap, i);
11105 	return ret;
11106 }
11107 
11108 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
11109     int sleep_ok)
11110 {
11111 	struct fw_sched_cmd cmd;
11112 
11113 	memset(&cmd, 0, sizeof(cmd));
11114 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11115 				      F_FW_CMD_REQUEST |
11116 				      F_FW_CMD_WRITE);
11117 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11118 
11119 	cmd.u.config.sc = FW_SCHED_SC_CONFIG;
11120 	cmd.u.config.type = type;
11121 	cmd.u.config.minmaxen = minmaxen;
11122 
11123 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11124 			       NULL, sleep_ok);
11125 }
11126 
11127 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
11128 		    int rateunit, int ratemode, int channel, int cl,
11129 		    int minrate, int maxrate, int weight, int pktsize,
11130 		    int burstsize, int sleep_ok)
11131 {
11132 	struct fw_sched_cmd cmd;
11133 
11134 	memset(&cmd, 0, sizeof(cmd));
11135 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11136 				      F_FW_CMD_REQUEST |
11137 				      F_FW_CMD_WRITE);
11138 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11139 
11140 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11141 	cmd.u.params.type = type;
11142 	cmd.u.params.level = level;
11143 	cmd.u.params.mode = mode;
11144 	cmd.u.params.ch = channel;
11145 	cmd.u.params.cl = cl;
11146 	cmd.u.params.unit = rateunit;
11147 	cmd.u.params.rate = ratemode;
11148 	cmd.u.params.min = cpu_to_be32(minrate);
11149 	cmd.u.params.max = cpu_to_be32(maxrate);
11150 	cmd.u.params.weight = cpu_to_be16(weight);
11151 	cmd.u.params.pktsize = cpu_to_be16(pktsize);
11152 	cmd.u.params.burstsize = cpu_to_be16(burstsize);
11153 
11154 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11155 			       NULL, sleep_ok);
11156 }
11157 
11158 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
11159     unsigned int maxrate, int sleep_ok)
11160 {
11161 	struct fw_sched_cmd cmd;
11162 
11163 	memset(&cmd, 0, sizeof(cmd));
11164 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11165 				      F_FW_CMD_REQUEST |
11166 				      F_FW_CMD_WRITE);
11167 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11168 
11169 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11170 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11171 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL;
11172 	cmd.u.params.ch = channel;
11173 	cmd.u.params.rate = ratemode;		/* REL or ABS */
11174 	cmd.u.params.max = cpu_to_be32(maxrate);/*  %  or kbps */
11175 
11176 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11177 			       NULL, sleep_ok);
11178 }
11179 
11180 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
11181     int weight, int sleep_ok)
11182 {
11183 	struct fw_sched_cmd cmd;
11184 
11185 	if (weight < 0 || weight > 100)
11186 		return -EINVAL;
11187 
11188 	memset(&cmd, 0, sizeof(cmd));
11189 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11190 				      F_FW_CMD_REQUEST |
11191 				      F_FW_CMD_WRITE);
11192 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11193 
11194 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11195 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11196 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
11197 	cmd.u.params.ch = channel;
11198 	cmd.u.params.cl = cl;
11199 	cmd.u.params.weight = cpu_to_be16(weight);
11200 
11201 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11202 			       NULL, sleep_ok);
11203 }
11204 
11205 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
11206     int mode, unsigned int maxrate, int pktsize, int sleep_ok)
11207 {
11208 	struct fw_sched_cmd cmd;
11209 
11210 	memset(&cmd, 0, sizeof(cmd));
11211 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
11212 				      F_FW_CMD_REQUEST |
11213 				      F_FW_CMD_WRITE);
11214 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
11215 
11216 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
11217 	cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED;
11218 	cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL;
11219 	cmd.u.params.mode = mode;
11220 	cmd.u.params.ch = channel;
11221 	cmd.u.params.cl = cl;
11222 	cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE;
11223 	cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS;
11224 	cmd.u.params.max = cpu_to_be32(maxrate);
11225 	cmd.u.params.pktsize = cpu_to_be16(pktsize);
11226 
11227 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
11228 			       NULL, sleep_ok);
11229 }
11230 
11231 /*
11232  *	t4_config_watchdog - configure (enable/disable) a watchdog timer
11233  *	@adapter: the adapter
11234  * 	@mbox: mailbox to use for the FW command
11235  * 	@pf: the PF owning the queue
11236  * 	@vf: the VF owning the queue
11237  *	@timeout: watchdog timeout in ms
11238  *	@action: watchdog timer / action
11239  *
11240  *	There are separate watchdog timers for each possible watchdog
11241  *	action.  Configure one of the watchdog timers by setting a non-zero
11242  *	timeout.  Disable a watchdog timer by using a timeout of zero.
11243  */
11244 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
11245 		       unsigned int pf, unsigned int vf,
11246 		       unsigned int timeout, unsigned int action)
11247 {
11248 	struct fw_watchdog_cmd wdog;
11249 	unsigned int ticks;
11250 
11251 	/*
11252 	 * The watchdog command expects a timeout in units of 10ms so we need
11253 	 * to convert it here (via rounding) and force a minimum of one 10ms
11254 	 * "tick" if the timeout is non-zero but the conversion results in 0
11255 	 * ticks.
11256 	 */
11257 	ticks = (timeout + 5)/10;
11258 	if (timeout && !ticks)
11259 		ticks = 1;
11260 
11261 	memset(&wdog, 0, sizeof wdog);
11262 	wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
11263 				     F_FW_CMD_REQUEST |
11264 				     F_FW_CMD_WRITE |
11265 				     V_FW_PARAMS_CMD_PFN(pf) |
11266 				     V_FW_PARAMS_CMD_VFN(vf));
11267 	wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
11268 	wdog.timeout = cpu_to_be32(ticks);
11269 	wdog.action = cpu_to_be32(action);
11270 
11271 	return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
11272 }
11273 
11274 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
11275 {
11276 	struct fw_devlog_cmd devlog_cmd;
11277 	int ret;
11278 
11279 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
11280 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
11281 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
11282 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
11283 	ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
11284 			 sizeof(devlog_cmd), &devlog_cmd);
11285 	if (ret)
11286 		return ret;
11287 
11288 	*level = devlog_cmd.level;
11289 	return 0;
11290 }
11291 
11292 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
11293 {
11294 	struct fw_devlog_cmd devlog_cmd;
11295 
11296 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
11297 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
11298 					     F_FW_CMD_REQUEST |
11299 					     F_FW_CMD_WRITE);
11300 	devlog_cmd.level = level;
11301 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
11302 	return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
11303 			  sizeof(devlog_cmd), &devlog_cmd);
11304 }
11305 
11306 int t4_configure_add_smac(struct adapter *adap)
11307 {
11308 	unsigned int param, val;
11309 	int ret = 0;
11310 
11311 	adap->params.smac_add_support = 0;
11312 	param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11313 		  V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC));
11314 	/* Query FW to check if FW supports adding source mac address
11315 	 * to TCAM feature or not.
11316 	 * If FW returns 1, driver can use this feature and driver need to send
11317 	 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to
11318 	 * enable adding smac to TCAM.
11319 	 */
11320 	ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
11321 	if (ret)
11322 		return ret;
11323 
11324 	if (val == 1) {
11325 		ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
11326 				    &param, &val);
11327 		if (!ret)
11328 			/* Firmware allows adding explicit TCAM entries.
11329 			 * Save this internally.
11330 			 */
11331 			adap->params.smac_add_support = 1;
11332 	}
11333 
11334 	return ret;
11335 }
11336 
11337 int t4_configure_ringbb(struct adapter *adap)
11338 {
11339 	unsigned int param, val;
11340 	int ret = 0;
11341 
11342 	param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
11343 		  V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE));
11344 	/* Query FW to check if FW supports ring switch feature or not.
11345 	 * If FW returns 1, driver can use this feature and driver need to send
11346 	 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to
11347 	 * enable the ring backbone configuration.
11348 	 */
11349 	ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
11350 	if (ret < 0) {
11351 		CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n",
11352 			ret);
11353 		goto out;
11354 	}
11355 
11356 	if (val != 1) {
11357 		CH_ERR(adap, "FW doesnot support ringbackbone features\n");
11358 		goto out;
11359 	}
11360 
11361 	ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, &param, &val);
11362 	if (ret < 0) {
11363 		CH_ERR(adap, "Could not set Ringbackbone, err= %d\n",
11364 			ret);
11365 		goto out;
11366 	}
11367 
11368 out:
11369 	return ret;
11370 }
11371 
11372 /*
11373  *	t4_set_vlan_acl - Set a VLAN id for the specified VF
11374  *	@adapter: the adapter
11375  *	@mbox: mailbox to use for the FW command
11376  *	@vf: one of the VFs instantiated by the specified PF
11377  *	@vlan: The vlanid to be set
11378  *
11379  */
11380 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
11381 		    u16 vlan)
11382 {
11383 	struct fw_acl_vlan_cmd vlan_cmd;
11384 	unsigned int enable;
11385 
11386 	enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0);
11387 	memset(&vlan_cmd, 0, sizeof(vlan_cmd));
11388 	vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) |
11389 					 F_FW_CMD_REQUEST |
11390 					 F_FW_CMD_WRITE |
11391 					 F_FW_CMD_EXEC |
11392 					 V_FW_ACL_VLAN_CMD_PFN(adap->pf) |
11393 					 V_FW_ACL_VLAN_CMD_VFN(vf));
11394 	vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
11395 	/* Drop all packets that donot match vlan id */
11396 	vlan_cmd.dropnovlan_fm = (enable
11397 				  ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN |
11398 				     F_FW_ACL_VLAN_CMD_FM)
11399 				  : 0);
11400 	if (enable != 0) {
11401 		vlan_cmd.nvlan = 1;
11402 		vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
11403 	}
11404 
11405 	return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
11406 }
11407 
11408 /**
11409  *	t4_del_mac - Removes the exact-match filter for a MAC address
11410  *	@adap: the adapter
11411  *	@mbox: mailbox to use for the FW command
11412  *	@viid: the VI id
11413  *	@addr: the MAC address value
11414  *	@smac: if true, delete from only the smac region of MPS
11415  *
11416  *	Modifies an exact-match filter and sets it to the new MAC address if
11417  *	@idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
11418  *	latter case the address is added persistently if @persist is %true.
11419  *
11420  *	Returns a negative error number or the index of the filter with the new
11421  *	MAC value.  Note that this index may differ from @idx.
11422  */
11423 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
11424 	       const u8 *addr, bool smac)
11425 {
11426 	int ret;
11427 	struct fw_vi_mac_cmd c;
11428 	struct fw_vi_mac_exact *p = c.u.exact;
11429 	unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
11430 
11431 	memset(&c, 0, sizeof(c));
11432 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
11433 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
11434 				   V_FW_VI_MAC_CMD_VIID(viid));
11435 	c.freemacs_to_len16 = cpu_to_be32(
11436 					V_FW_CMD_LEN16(1) |
11437 					(smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
11438 
11439 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
11440 	p->valid_to_idx = cpu_to_be16(
11441 				F_FW_VI_MAC_CMD_VALID |
11442 				V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE));
11443 
11444 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11445 	if (ret == 0) {
11446 		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
11447 		if (ret < max_mac_addr)
11448 			return -ENOMEM;
11449 	}
11450 
11451 	return ret;
11452 }
11453 
11454 /**
11455  *	t4_add_mac - Adds an exact-match filter for a MAC address
11456  *	@adap: the adapter
11457  *	@mbox: mailbox to use for the FW command
11458  *	@viid: the VI id
11459  *	@idx: index of existing filter for old value of MAC address, or -1
11460  *	@addr: the new MAC address value
11461  *	@persist: whether a new MAC allocation should be persistent
11462  *	@add_smt: if true also add the address to the HW SMT
11463  *	@smac: if true, update only the smac region of MPS
11464  *
11465  *	Modifies an exact-match filter and sets it to the new MAC address if
11466  *	@idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
11467  *	latter case the address is added persistently if @persist is %true.
11468  *
11469  *	Returns a negative error number or the index of the filter with the new
11470  *	MAC value.  Note that this index may differ from @idx.
11471  */
11472 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
11473 	       int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac)
11474 {
11475 	int ret, mode;
11476 	struct fw_vi_mac_cmd c;
11477 	struct fw_vi_mac_exact *p = c.u.exact;
11478 	unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
11479 
11480 	if (idx < 0)		/* new allocation */
11481 		idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
11482 	mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
11483 
11484 	memset(&c, 0, sizeof(c));
11485 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
11486 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
11487 				   V_FW_VI_MAC_CMD_VIID(viid));
11488 	c.freemacs_to_len16 = cpu_to_be32(
11489 				V_FW_CMD_LEN16(1) |
11490 				(smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0));
11491 	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
11492 				      V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
11493 				      V_FW_VI_MAC_CMD_IDX(idx));
11494 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
11495 
11496 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
11497 	if (ret == 0) {
11498 		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
11499 		if (ret >= max_mac_addr)
11500 			return -ENOMEM;
11501 		if (smt_idx) {
11502 			/* Does fw supports returning smt_idx? */
11503 			if (adap->params.viid_smt_extn_support)
11504 				*smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid));
11505 			else {
11506 				/* In T4/T5, SMT contains 256 SMAC entries
11507 				 * organized in 128 rows of 2 entries each.
11508 				 * In T6, SMT contains 256 SMAC entries in
11509 				 * 256 rows.
11510 				 */
11511 				if (chip_id(adap) <= CHELSIO_T5)
11512 					*smt_idx = ((viid & M_FW_VIID_VIN) << 1);
11513 				else
11514 					*smt_idx = (viid & M_FW_VIID_VIN);
11515 			}
11516 		}
11517 	}
11518 
11519 	return ret;
11520 }
11521