1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 adap->flags &= ~FW_OK; 216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 218 if (pcie_fw != 0xffffffff) 219 t4_os_dump_devlog(adap); 220 } 221 } 222 223 /* 224 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 225 */ 226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 227 u32 mbox_addr) 228 { 229 for ( ; nflit; nflit--, mbox_addr += 8) 230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 231 } 232 233 /* 234 * Handle a FW assertion reported in a mailbox. 235 */ 236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 237 { 238 CH_ALERT(adap, 239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 240 asrt->u.assert.filename_0_7, 241 be32_to_cpu(asrt->u.assert.line), 242 be32_to_cpu(asrt->u.assert.x), 243 be32_to_cpu(asrt->u.assert.y)); 244 } 245 246 struct port_tx_state { 247 uint64_t rx_pause; 248 uint64_t tx_frames; 249 }; 250 251 static void 252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 253 { 254 uint32_t rx_pause_reg, tx_frames_reg; 255 256 if (is_t4(sc)) { 257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 259 } else { 260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 262 } 263 264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 266 } 267 268 static void 269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 270 { 271 int i; 272 273 for_each_port(sc, i) 274 read_tx_state_one(sc, i, &tx_state[i]); 275 } 276 277 static void 278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 279 { 280 uint32_t port_ctl_reg; 281 uint64_t tx_frames, rx_pause; 282 int i; 283 284 for_each_port(sc, i) { 285 rx_pause = tx_state[i].rx_pause; 286 tx_frames = tx_state[i].tx_frames; 287 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 288 289 if (is_t4(sc)) 290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 291 else 292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 294 rx_pause != tx_state[i].rx_pause && 295 tx_frames == tx_state[i].tx_frames) { 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 297 mdelay(1); 298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 299 } 300 } 301 } 302 303 #define X_CIM_PF_NOACCESS 0xeeeeeeee 304 /** 305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 306 * @adap: the adapter 307 * @mbox: index of the mailbox to use 308 * @cmd: the command to write 309 * @size: command length in bytes 310 * @rpl: where to optionally store the reply 311 * @sleep_ok: if true we may sleep while awaiting command completion 312 * @timeout: time to wait for command to finish before timing out 313 * (negative implies @sleep_ok=false) 314 * 315 * Sends the given command to FW through the selected mailbox and waits 316 * for the FW to execute the command. If @rpl is not %NULL it is used to 317 * store the FW's reply to the command. The command and its optional 318 * reply are of the same length. Some FW commands like RESET and 319 * INITIALIZE can take a considerable amount of time to execute. 320 * @sleep_ok determines whether we may sleep while awaiting the response. 321 * If sleeping is allowed we use progressive backoff otherwise we spin. 322 * Note that passing in a negative @timeout is an alternate mechanism 323 * for specifying @sleep_ok=false. This is useful when a higher level 324 * interface allows for specification of @timeout but not @sleep_ok ... 325 * 326 * The return value is 0 on success or a negative errno on failure. A 327 * failure can happen either because we are not able to execute the 328 * command or FW executes it but signals an error. In the latter case 329 * the return value is the error code indicated by FW (negated). 330 */ 331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 332 int size, void *rpl, bool sleep_ok, int timeout) 333 { 334 /* 335 * We delay in small increments at first in an effort to maintain 336 * responsiveness for simple, fast executing commands but then back 337 * off to larger delays to a maximum retry delay. 338 */ 339 static const int delay[] = { 340 1, 1, 3, 5, 10, 10, 20, 50, 100 341 }; 342 u32 v; 343 u64 res; 344 int i, ms, delay_idx, ret, next_tx_check; 345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 347 u32 ctl; 348 __be64 cmd_rpl[MBOX_LEN/8]; 349 u32 pcie_fw; 350 struct port_tx_state tx_state[MAX_NPORTS]; 351 352 if (adap->flags & CHK_MBOX_ACCESS) 353 ASSERT_SYNCHRONIZED_OP(adap); 354 355 if (size <= 0 || (size & 15) || size > MBOX_LEN) 356 return -EINVAL; 357 358 if (adap->flags & IS_VF) { 359 if (is_t6(adap)) 360 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 361 else 362 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 364 } 365 366 /* 367 * If we have a negative timeout, that implies that we can't sleep. 368 */ 369 if (timeout < 0) { 370 sleep_ok = false; 371 timeout = -timeout; 372 } 373 374 /* 375 * Attempt to gain access to the mailbox. 376 */ 377 for (i = 0; i < 4; i++) { 378 ctl = t4_read_reg(adap, ctl_reg); 379 v = G_MBOWNER(ctl); 380 if (v != X_MBOWNER_NONE) 381 break; 382 } 383 384 /* 385 * If we were unable to gain access, report the error to our caller. 386 */ 387 if (v != X_MBOWNER_PL) { 388 t4_report_fw_error(adap); 389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 390 return ret; 391 } 392 393 /* 394 * If we gain ownership of the mailbox and there's a "valid" message 395 * in it, this is likely an asynchronous error message from the 396 * firmware. So we'll report that and then proceed on with attempting 397 * to issue our own command ... which may well fail if the error 398 * presaged the firmware crashing ... 399 */ 400 if (ctl & F_MBMSGVALID) { 401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 402 } 403 404 /* 405 * Copy in the new mailbox command and send it on its way ... 406 */ 407 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 408 memcpy(cmd_rpl, cmd, size); 409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 412 413 if (adap->flags & IS_VF) { 414 /* 415 * For the VFs, the Mailbox Data "registers" are 416 * actually backed by T4's "MA" interface rather than 417 * PL Registers (as is the case for the PFs). Because 418 * these are in different coherency domains, the write 419 * to the VF's PL-register-backed Mailbox Control can 420 * race in front of the writes to the MA-backed VF 421 * Mailbox Data "registers". So we need to do a 422 * read-back on at least one byte of the VF Mailbox 423 * Data registers before doing the write to the VF 424 * Mailbox Control register. 425 */ 426 t4_read_reg(adap, data_reg); 427 } 428 429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 431 next_tx_check = 1000; 432 delay_idx = 0; 433 ms = delay[0]; 434 435 /* 436 * Loop waiting for the reply; bail out if we time out or the firmware 437 * reports an error. 438 */ 439 pcie_fw = 0; 440 for (i = 0; i < timeout; i += ms) { 441 if (!(adap->flags & IS_VF)) { 442 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 443 if (pcie_fw & F_PCIE_FW_ERR) 444 break; 445 } 446 447 if (i >= next_tx_check) { 448 check_tx_state(adap, &tx_state[0]); 449 next_tx_check = i + 1000; 450 } 451 452 if (sleep_ok) { 453 ms = delay[delay_idx]; /* last element may repeat */ 454 if (delay_idx < ARRAY_SIZE(delay) - 1) 455 delay_idx++; 456 msleep(ms); 457 } else { 458 mdelay(ms); 459 } 460 461 v = t4_read_reg(adap, ctl_reg); 462 if (v == X_CIM_PF_NOACCESS) 463 continue; 464 if (G_MBOWNER(v) == X_MBOWNER_PL) { 465 if (!(v & F_MBMSGVALID)) { 466 t4_write_reg(adap, ctl_reg, 467 V_MBOWNER(X_MBOWNER_NONE)); 468 continue; 469 } 470 471 /* 472 * Retrieve the command reply and release the mailbox. 473 */ 474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 477 478 res = be64_to_cpu(cmd_rpl[0]); 479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 481 res = V_FW_CMD_RETVAL(EIO); 482 } else if (rpl) 483 memcpy(rpl, cmd_rpl, size); 484 return -G_FW_CMD_RETVAL((int)res); 485 } 486 } 487 488 /* 489 * We timed out waiting for a reply to our mailbox command. Report 490 * the error and also check to see if the firmware reported any 491 * errors ... 492 */ 493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 494 *(const u8 *)cmd, mbox, pcie_fw); 495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 497 498 if (pcie_fw & F_PCIE_FW_ERR) { 499 ret = -ENXIO; 500 t4_report_fw_error(adap); 501 } else { 502 ret = -ETIMEDOUT; 503 t4_os_dump_devlog(adap); 504 } 505 506 t4_fatal_err(adap, true); 507 return ret; 508 } 509 510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 511 void *rpl, bool sleep_ok) 512 { 513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 514 sleep_ok, FW_CMD_MAX_TIMEOUT); 515 516 } 517 518 static int t4_edc_err_read(struct adapter *adap, int idx) 519 { 520 u32 edc_ecc_err_addr_reg; 521 u32 edc_bist_status_rdata_reg; 522 523 if (is_t4(adap)) { 524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 525 return 0; 526 } 527 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 529 return 0; 530 } 531 532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 534 535 CH_WARN(adap, 536 "edc%d err addr 0x%x: 0x%x.\n", 537 idx, edc_ecc_err_addr_reg, 538 t4_read_reg(adap, edc_ecc_err_addr_reg)); 539 CH_WARN(adap, 540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 541 edc_bist_status_rdata_reg, 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 551 552 return 0; 553 } 554 555 /** 556 * t4_mc_read - read from MC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which MC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568 { 569 int i; 570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 572 573 if (is_t4(adap)) { 574 mc_bist_cmd_reg = A_MC_BIST_CMD; 575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 579 } else { 580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 584 idx); 585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 586 idx); 587 } 588 589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 590 return -EBUSY; 591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 595 F_START_BIST | V_BIST_CMD_GAP(1)); 596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 597 if (i) 598 return i; 599 600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 601 602 for (i = 15; i >= 0; i--) 603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 604 if (ecc) 605 *ecc = t4_read_reg64(adap, MC_DATA(16)); 606 #undef MC_DATA 607 return 0; 608 } 609 610 /** 611 * t4_edc_read - read from EDC through backdoor accesses 612 * @adap: the adapter 613 * @idx: which EDC to access 614 * @addr: address of first byte requested 615 * @data: 64 bytes of data containing the requested address 616 * @ecc: where to store the corresponding 64-bit ECC word 617 * 618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 619 * that covers the requested address @addr. If @parity is not %NULL it 620 * is assigned the 64-bit ECC word for the read data. 621 */ 622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 623 { 624 int i; 625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 627 628 if (is_t4(adap)) { 629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 633 idx); 634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 635 idx); 636 } else { 637 /* 638 * These macro are missing in t4_regs.h file. 639 * Added temporarily for testing. 640 */ 641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 649 idx); 650 #undef EDC_REG_T5 651 #undef EDC_STRIDE_T5 652 } 653 654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 655 return -EBUSY; 656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 659 t4_write_reg(adap, edc_bist_cmd_reg, 660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 662 if (i) 663 return i; 664 665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 666 667 for (i = 15; i >= 0; i--) 668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 669 if (ecc) 670 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 671 #undef EDC_DATA 672 return 0; 673 } 674 675 /** 676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 677 * @adap: the adapter 678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 679 * @addr: address within indicated memory type 680 * @len: amount of memory to read 681 * @buf: host memory buffer 682 * 683 * Reads an [almost] arbitrary memory region in the firmware: the 684 * firmware memory address, length and host buffer must be aligned on 685 * 32-bit boudaries. The memory is returned as a raw byte sequence from 686 * the firmware's memory. If this memory contains data structures which 687 * contain multi-byte integers, it's the callers responsibility to 688 * perform appropriate byte order conversions. 689 */ 690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 691 __be32 *buf) 692 { 693 u32 pos, start, end, offset; 694 int ret; 695 696 /* 697 * Argument sanity checks ... 698 */ 699 if ((addr & 0x3) || (len & 0x3)) 700 return -EINVAL; 701 702 /* 703 * The underlaying EDC/MC read routines read 64 bytes at a time so we 704 * need to round down the start and round up the end. We'll start 705 * copying out of the first line at (addr - start) a word at a time. 706 */ 707 start = rounddown2(addr, 64); 708 end = roundup2(addr + len, 64); 709 offset = (addr - start)/sizeof(__be32); 710 711 for (pos = start; pos < end; pos += 64, offset = 0) { 712 __be32 data[16]; 713 714 /* 715 * Read the chip's memory block and bail if there's an error. 716 */ 717 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 719 else 720 ret = t4_edc_read(adap, mtype, pos, data, NULL); 721 if (ret) 722 return ret; 723 724 /* 725 * Copy the data into the caller's memory buffer. 726 */ 727 while (offset < 16 && len > 0) { 728 *buf++ = data[offset++]; 729 len -= sizeof(__be32); 730 } 731 } 732 733 return 0; 734 } 735 736 /* 737 * Return the specified PCI-E Configuration Space register from our Physical 738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 739 * since we prefer to let the firmware own all of these registers, but if that 740 * fails we go for it directly ourselves. 741 */ 742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 743 { 744 745 /* 746 * If fw_attach != 0, construct and send the Firmware LDST Command to 747 * retrieve the specified PCI-E Configuration Space register. 748 */ 749 if (drv_fw_attach != 0) { 750 struct fw_ldst_cmd ldst_cmd; 751 int ret; 752 753 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 754 ldst_cmd.op_to_addrspace = 755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 756 F_FW_CMD_REQUEST | 757 F_FW_CMD_READ | 758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 761 ldst_cmd.u.pcie.ctrl_to_fn = 762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 763 ldst_cmd.u.pcie.r = reg; 764 765 /* 766 * If the LDST Command succeeds, return the result, otherwise 767 * fall through to reading it directly ourselves ... 768 */ 769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 770 &ldst_cmd); 771 if (ret == 0) 772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 773 774 CH_WARN(adap, "Firmware failed to return " 775 "Configuration Space register %d, err = %d\n", 776 reg, -ret); 777 } 778 779 /* 780 * Read the desired Configuration Space register via the PCI-E 781 * Backdoor mechanism. 782 */ 783 return t4_hw_pci_read_cfg4(adap, reg); 784 } 785 786 /** 787 * t4_get_regs_len - return the size of the chips register set 788 * @adapter: the adapter 789 * 790 * Returns the size of the chip's BAR0 register space. 791 */ 792 unsigned int t4_get_regs_len(struct adapter *adapter) 793 { 794 unsigned int chip_version = chip_id(adapter); 795 796 switch (chip_version) { 797 case CHELSIO_T4: 798 if (adapter->flags & IS_VF) 799 return FW_T4VF_REGMAP_SIZE; 800 return T4_REGMAP_SIZE; 801 802 case CHELSIO_T5: 803 case CHELSIO_T6: 804 if (adapter->flags & IS_VF) 805 return FW_T4VF_REGMAP_SIZE; 806 return T5_REGMAP_SIZE; 807 } 808 809 CH_ERR(adapter, 810 "Unsupported chip version %d\n", chip_version); 811 return 0; 812 } 813 814 /** 815 * t4_get_regs - read chip registers into provided buffer 816 * @adap: the adapter 817 * @buf: register buffer 818 * @buf_size: size (in bytes) of register buffer 819 * 820 * If the provided register buffer isn't large enough for the chip's 821 * full register range, the register dump will be truncated to the 822 * register buffer's size. 823 */ 824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 825 { 826 static const unsigned int t4_reg_ranges[] = { 827 0x1008, 0x1108, 828 0x1180, 0x1184, 829 0x1190, 0x1194, 830 0x11a0, 0x11a4, 831 0x11b0, 0x11b4, 832 0x11fc, 0x123c, 833 0x1300, 0x173c, 834 0x1800, 0x18fc, 835 0x3000, 0x30d8, 836 0x30e0, 0x30e4, 837 0x30ec, 0x5910, 838 0x5920, 0x5924, 839 0x5960, 0x5960, 840 0x5968, 0x5968, 841 0x5970, 0x5970, 842 0x5978, 0x5978, 843 0x5980, 0x5980, 844 0x5988, 0x5988, 845 0x5990, 0x5990, 846 0x5998, 0x5998, 847 0x59a0, 0x59d4, 848 0x5a00, 0x5ae0, 849 0x5ae8, 0x5ae8, 850 0x5af0, 0x5af0, 851 0x5af8, 0x5af8, 852 0x6000, 0x6098, 853 0x6100, 0x6150, 854 0x6200, 0x6208, 855 0x6240, 0x6248, 856 0x6280, 0x62b0, 857 0x62c0, 0x6338, 858 0x6370, 0x638c, 859 0x6400, 0x643c, 860 0x6500, 0x6524, 861 0x6a00, 0x6a04, 862 0x6a14, 0x6a38, 863 0x6a60, 0x6a70, 864 0x6a78, 0x6a78, 865 0x6b00, 0x6b0c, 866 0x6b1c, 0x6b84, 867 0x6bf0, 0x6bf8, 868 0x6c00, 0x6c0c, 869 0x6c1c, 0x6c84, 870 0x6cf0, 0x6cf8, 871 0x6d00, 0x6d0c, 872 0x6d1c, 0x6d84, 873 0x6df0, 0x6df8, 874 0x6e00, 0x6e0c, 875 0x6e1c, 0x6e84, 876 0x6ef0, 0x6ef8, 877 0x6f00, 0x6f0c, 878 0x6f1c, 0x6f84, 879 0x6ff0, 0x6ff8, 880 0x7000, 0x700c, 881 0x701c, 0x7084, 882 0x70f0, 0x70f8, 883 0x7100, 0x710c, 884 0x711c, 0x7184, 885 0x71f0, 0x71f8, 886 0x7200, 0x720c, 887 0x721c, 0x7284, 888 0x72f0, 0x72f8, 889 0x7300, 0x730c, 890 0x731c, 0x7384, 891 0x73f0, 0x73f8, 892 0x7400, 0x7450, 893 0x7500, 0x7530, 894 0x7600, 0x760c, 895 0x7614, 0x761c, 896 0x7680, 0x76cc, 897 0x7700, 0x7798, 898 0x77c0, 0x77fc, 899 0x7900, 0x79fc, 900 0x7b00, 0x7b58, 901 0x7b60, 0x7b84, 902 0x7b8c, 0x7c38, 903 0x7d00, 0x7d38, 904 0x7d40, 0x7d80, 905 0x7d8c, 0x7ddc, 906 0x7de4, 0x7e04, 907 0x7e10, 0x7e1c, 908 0x7e24, 0x7e38, 909 0x7e40, 0x7e44, 910 0x7e4c, 0x7e78, 911 0x7e80, 0x7ea4, 912 0x7eac, 0x7edc, 913 0x7ee8, 0x7efc, 914 0x8dc0, 0x8e04, 915 0x8e10, 0x8e1c, 916 0x8e30, 0x8e78, 917 0x8ea0, 0x8eb8, 918 0x8ec0, 0x8f6c, 919 0x8fc0, 0x9008, 920 0x9010, 0x9058, 921 0x9060, 0x9060, 922 0x9068, 0x9074, 923 0x90fc, 0x90fc, 924 0x9400, 0x9408, 925 0x9410, 0x9458, 926 0x9600, 0x9600, 927 0x9608, 0x9638, 928 0x9640, 0x96bc, 929 0x9800, 0x9808, 930 0x9820, 0x983c, 931 0x9850, 0x9864, 932 0x9c00, 0x9c6c, 933 0x9c80, 0x9cec, 934 0x9d00, 0x9d6c, 935 0x9d80, 0x9dec, 936 0x9e00, 0x9e6c, 937 0x9e80, 0x9eec, 938 0x9f00, 0x9f6c, 939 0x9f80, 0x9fec, 940 0xd004, 0xd004, 941 0xd010, 0xd03c, 942 0xdfc0, 0xdfe0, 943 0xe000, 0xea7c, 944 0xf000, 0x11110, 945 0x11118, 0x11190, 946 0x19040, 0x1906c, 947 0x19078, 0x19080, 948 0x1908c, 0x190e4, 949 0x190f0, 0x190f8, 950 0x19100, 0x19110, 951 0x19120, 0x19124, 952 0x19150, 0x19194, 953 0x1919c, 0x191b0, 954 0x191d0, 0x191e8, 955 0x19238, 0x1924c, 956 0x193f8, 0x1943c, 957 0x1944c, 0x19474, 958 0x19490, 0x194e0, 959 0x194f0, 0x194f8, 960 0x19800, 0x19c08, 961 0x19c10, 0x19c90, 962 0x19ca0, 0x19ce4, 963 0x19cf0, 0x19d40, 964 0x19d50, 0x19d94, 965 0x19da0, 0x19de8, 966 0x19df0, 0x19e40, 967 0x19e50, 0x19e90, 968 0x19ea0, 0x19f4c, 969 0x1a000, 0x1a004, 970 0x1a010, 0x1a06c, 971 0x1a0b0, 0x1a0e4, 972 0x1a0ec, 0x1a0f4, 973 0x1a100, 0x1a108, 974 0x1a114, 0x1a120, 975 0x1a128, 0x1a130, 976 0x1a138, 0x1a138, 977 0x1a190, 0x1a1c4, 978 0x1a1fc, 0x1a1fc, 979 0x1e040, 0x1e04c, 980 0x1e284, 0x1e28c, 981 0x1e2c0, 0x1e2c0, 982 0x1e2e0, 0x1e2e0, 983 0x1e300, 0x1e384, 984 0x1e3c0, 0x1e3c8, 985 0x1e440, 0x1e44c, 986 0x1e684, 0x1e68c, 987 0x1e6c0, 0x1e6c0, 988 0x1e6e0, 0x1e6e0, 989 0x1e700, 0x1e784, 990 0x1e7c0, 0x1e7c8, 991 0x1e840, 0x1e84c, 992 0x1ea84, 0x1ea8c, 993 0x1eac0, 0x1eac0, 994 0x1eae0, 0x1eae0, 995 0x1eb00, 0x1eb84, 996 0x1ebc0, 0x1ebc8, 997 0x1ec40, 0x1ec4c, 998 0x1ee84, 0x1ee8c, 999 0x1eec0, 0x1eec0, 1000 0x1eee0, 0x1eee0, 1001 0x1ef00, 0x1ef84, 1002 0x1efc0, 0x1efc8, 1003 0x1f040, 0x1f04c, 1004 0x1f284, 0x1f28c, 1005 0x1f2c0, 0x1f2c0, 1006 0x1f2e0, 0x1f2e0, 1007 0x1f300, 0x1f384, 1008 0x1f3c0, 0x1f3c8, 1009 0x1f440, 0x1f44c, 1010 0x1f684, 0x1f68c, 1011 0x1f6c0, 0x1f6c0, 1012 0x1f6e0, 0x1f6e0, 1013 0x1f700, 0x1f784, 1014 0x1f7c0, 0x1f7c8, 1015 0x1f840, 0x1f84c, 1016 0x1fa84, 0x1fa8c, 1017 0x1fac0, 0x1fac0, 1018 0x1fae0, 0x1fae0, 1019 0x1fb00, 0x1fb84, 1020 0x1fbc0, 0x1fbc8, 1021 0x1fc40, 0x1fc4c, 1022 0x1fe84, 0x1fe8c, 1023 0x1fec0, 0x1fec0, 1024 0x1fee0, 0x1fee0, 1025 0x1ff00, 0x1ff84, 1026 0x1ffc0, 0x1ffc8, 1027 0x20000, 0x2002c, 1028 0x20100, 0x2013c, 1029 0x20190, 0x201a0, 1030 0x201a8, 0x201b8, 1031 0x201c4, 0x201c8, 1032 0x20200, 0x20318, 1033 0x20400, 0x204b4, 1034 0x204c0, 0x20528, 1035 0x20540, 0x20614, 1036 0x21000, 0x21040, 1037 0x2104c, 0x21060, 1038 0x210c0, 0x210ec, 1039 0x21200, 0x21268, 1040 0x21270, 0x21284, 1041 0x212fc, 0x21388, 1042 0x21400, 0x21404, 1043 0x21500, 0x21500, 1044 0x21510, 0x21518, 1045 0x2152c, 0x21530, 1046 0x2153c, 0x2153c, 1047 0x21550, 0x21554, 1048 0x21600, 0x21600, 1049 0x21608, 0x2161c, 1050 0x21624, 0x21628, 1051 0x21630, 0x21634, 1052 0x2163c, 0x2163c, 1053 0x21700, 0x2171c, 1054 0x21780, 0x2178c, 1055 0x21800, 0x21818, 1056 0x21820, 0x21828, 1057 0x21830, 0x21848, 1058 0x21850, 0x21854, 1059 0x21860, 0x21868, 1060 0x21870, 0x21870, 1061 0x21878, 0x21898, 1062 0x218a0, 0x218a8, 1063 0x218b0, 0x218c8, 1064 0x218d0, 0x218d4, 1065 0x218e0, 0x218e8, 1066 0x218f0, 0x218f0, 1067 0x218f8, 0x21a18, 1068 0x21a20, 0x21a28, 1069 0x21a30, 0x21a48, 1070 0x21a50, 0x21a54, 1071 0x21a60, 0x21a68, 1072 0x21a70, 0x21a70, 1073 0x21a78, 0x21a98, 1074 0x21aa0, 0x21aa8, 1075 0x21ab0, 0x21ac8, 1076 0x21ad0, 0x21ad4, 1077 0x21ae0, 0x21ae8, 1078 0x21af0, 0x21af0, 1079 0x21af8, 0x21c18, 1080 0x21c20, 0x21c20, 1081 0x21c28, 0x21c30, 1082 0x21c38, 0x21c38, 1083 0x21c80, 0x21c98, 1084 0x21ca0, 0x21ca8, 1085 0x21cb0, 0x21cc8, 1086 0x21cd0, 0x21cd4, 1087 0x21ce0, 0x21ce8, 1088 0x21cf0, 0x21cf0, 1089 0x21cf8, 0x21d7c, 1090 0x21e00, 0x21e04, 1091 0x22000, 0x2202c, 1092 0x22100, 0x2213c, 1093 0x22190, 0x221a0, 1094 0x221a8, 0x221b8, 1095 0x221c4, 0x221c8, 1096 0x22200, 0x22318, 1097 0x22400, 0x224b4, 1098 0x224c0, 0x22528, 1099 0x22540, 0x22614, 1100 0x23000, 0x23040, 1101 0x2304c, 0x23060, 1102 0x230c0, 0x230ec, 1103 0x23200, 0x23268, 1104 0x23270, 0x23284, 1105 0x232fc, 0x23388, 1106 0x23400, 0x23404, 1107 0x23500, 0x23500, 1108 0x23510, 0x23518, 1109 0x2352c, 0x23530, 1110 0x2353c, 0x2353c, 1111 0x23550, 0x23554, 1112 0x23600, 0x23600, 1113 0x23608, 0x2361c, 1114 0x23624, 0x23628, 1115 0x23630, 0x23634, 1116 0x2363c, 0x2363c, 1117 0x23700, 0x2371c, 1118 0x23780, 0x2378c, 1119 0x23800, 0x23818, 1120 0x23820, 0x23828, 1121 0x23830, 0x23848, 1122 0x23850, 0x23854, 1123 0x23860, 0x23868, 1124 0x23870, 0x23870, 1125 0x23878, 0x23898, 1126 0x238a0, 0x238a8, 1127 0x238b0, 0x238c8, 1128 0x238d0, 0x238d4, 1129 0x238e0, 0x238e8, 1130 0x238f0, 0x238f0, 1131 0x238f8, 0x23a18, 1132 0x23a20, 0x23a28, 1133 0x23a30, 0x23a48, 1134 0x23a50, 0x23a54, 1135 0x23a60, 0x23a68, 1136 0x23a70, 0x23a70, 1137 0x23a78, 0x23a98, 1138 0x23aa0, 0x23aa8, 1139 0x23ab0, 0x23ac8, 1140 0x23ad0, 0x23ad4, 1141 0x23ae0, 0x23ae8, 1142 0x23af0, 0x23af0, 1143 0x23af8, 0x23c18, 1144 0x23c20, 0x23c20, 1145 0x23c28, 0x23c30, 1146 0x23c38, 0x23c38, 1147 0x23c80, 0x23c98, 1148 0x23ca0, 0x23ca8, 1149 0x23cb0, 0x23cc8, 1150 0x23cd0, 0x23cd4, 1151 0x23ce0, 0x23ce8, 1152 0x23cf0, 0x23cf0, 1153 0x23cf8, 0x23d7c, 1154 0x23e00, 0x23e04, 1155 0x24000, 0x2402c, 1156 0x24100, 0x2413c, 1157 0x24190, 0x241a0, 1158 0x241a8, 0x241b8, 1159 0x241c4, 0x241c8, 1160 0x24200, 0x24318, 1161 0x24400, 0x244b4, 1162 0x244c0, 0x24528, 1163 0x24540, 0x24614, 1164 0x25000, 0x25040, 1165 0x2504c, 0x25060, 1166 0x250c0, 0x250ec, 1167 0x25200, 0x25268, 1168 0x25270, 0x25284, 1169 0x252fc, 0x25388, 1170 0x25400, 0x25404, 1171 0x25500, 0x25500, 1172 0x25510, 0x25518, 1173 0x2552c, 0x25530, 1174 0x2553c, 0x2553c, 1175 0x25550, 0x25554, 1176 0x25600, 0x25600, 1177 0x25608, 0x2561c, 1178 0x25624, 0x25628, 1179 0x25630, 0x25634, 1180 0x2563c, 0x2563c, 1181 0x25700, 0x2571c, 1182 0x25780, 0x2578c, 1183 0x25800, 0x25818, 1184 0x25820, 0x25828, 1185 0x25830, 0x25848, 1186 0x25850, 0x25854, 1187 0x25860, 0x25868, 1188 0x25870, 0x25870, 1189 0x25878, 0x25898, 1190 0x258a0, 0x258a8, 1191 0x258b0, 0x258c8, 1192 0x258d0, 0x258d4, 1193 0x258e0, 0x258e8, 1194 0x258f0, 0x258f0, 1195 0x258f8, 0x25a18, 1196 0x25a20, 0x25a28, 1197 0x25a30, 0x25a48, 1198 0x25a50, 0x25a54, 1199 0x25a60, 0x25a68, 1200 0x25a70, 0x25a70, 1201 0x25a78, 0x25a98, 1202 0x25aa0, 0x25aa8, 1203 0x25ab0, 0x25ac8, 1204 0x25ad0, 0x25ad4, 1205 0x25ae0, 0x25ae8, 1206 0x25af0, 0x25af0, 1207 0x25af8, 0x25c18, 1208 0x25c20, 0x25c20, 1209 0x25c28, 0x25c30, 1210 0x25c38, 0x25c38, 1211 0x25c80, 0x25c98, 1212 0x25ca0, 0x25ca8, 1213 0x25cb0, 0x25cc8, 1214 0x25cd0, 0x25cd4, 1215 0x25ce0, 0x25ce8, 1216 0x25cf0, 0x25cf0, 1217 0x25cf8, 0x25d7c, 1218 0x25e00, 0x25e04, 1219 0x26000, 0x2602c, 1220 0x26100, 0x2613c, 1221 0x26190, 0x261a0, 1222 0x261a8, 0x261b8, 1223 0x261c4, 0x261c8, 1224 0x26200, 0x26318, 1225 0x26400, 0x264b4, 1226 0x264c0, 0x26528, 1227 0x26540, 0x26614, 1228 0x27000, 0x27040, 1229 0x2704c, 0x27060, 1230 0x270c0, 0x270ec, 1231 0x27200, 0x27268, 1232 0x27270, 0x27284, 1233 0x272fc, 0x27388, 1234 0x27400, 0x27404, 1235 0x27500, 0x27500, 1236 0x27510, 0x27518, 1237 0x2752c, 0x27530, 1238 0x2753c, 0x2753c, 1239 0x27550, 0x27554, 1240 0x27600, 0x27600, 1241 0x27608, 0x2761c, 1242 0x27624, 0x27628, 1243 0x27630, 0x27634, 1244 0x2763c, 0x2763c, 1245 0x27700, 0x2771c, 1246 0x27780, 0x2778c, 1247 0x27800, 0x27818, 1248 0x27820, 0x27828, 1249 0x27830, 0x27848, 1250 0x27850, 0x27854, 1251 0x27860, 0x27868, 1252 0x27870, 0x27870, 1253 0x27878, 0x27898, 1254 0x278a0, 0x278a8, 1255 0x278b0, 0x278c8, 1256 0x278d0, 0x278d4, 1257 0x278e0, 0x278e8, 1258 0x278f0, 0x278f0, 1259 0x278f8, 0x27a18, 1260 0x27a20, 0x27a28, 1261 0x27a30, 0x27a48, 1262 0x27a50, 0x27a54, 1263 0x27a60, 0x27a68, 1264 0x27a70, 0x27a70, 1265 0x27a78, 0x27a98, 1266 0x27aa0, 0x27aa8, 1267 0x27ab0, 0x27ac8, 1268 0x27ad0, 0x27ad4, 1269 0x27ae0, 0x27ae8, 1270 0x27af0, 0x27af0, 1271 0x27af8, 0x27c18, 1272 0x27c20, 0x27c20, 1273 0x27c28, 0x27c30, 1274 0x27c38, 0x27c38, 1275 0x27c80, 0x27c98, 1276 0x27ca0, 0x27ca8, 1277 0x27cb0, 0x27cc8, 1278 0x27cd0, 0x27cd4, 1279 0x27ce0, 0x27ce8, 1280 0x27cf0, 0x27cf0, 1281 0x27cf8, 0x27d7c, 1282 0x27e00, 0x27e04, 1283 }; 1284 1285 static const unsigned int t4vf_reg_ranges[] = { 1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1287 VF_MPS_REG(A_MPS_VF_CTL), 1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1292 FW_T4VF_MBDATA_BASE_ADDR, 1293 FW_T4VF_MBDATA_BASE_ADDR + 1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1295 }; 1296 1297 static const unsigned int t5_reg_ranges[] = { 1298 0x1008, 0x10c0, 1299 0x10cc, 0x10f8, 1300 0x1100, 0x1100, 1301 0x110c, 0x1148, 1302 0x1180, 0x1184, 1303 0x1190, 0x1194, 1304 0x11a0, 0x11a4, 1305 0x11b0, 0x11b4, 1306 0x11fc, 0x123c, 1307 0x1280, 0x173c, 1308 0x1800, 0x18fc, 1309 0x3000, 0x3028, 1310 0x3060, 0x30b0, 1311 0x30b8, 0x30d8, 1312 0x30e0, 0x30fc, 1313 0x3140, 0x357c, 1314 0x35a8, 0x35cc, 1315 0x35ec, 0x35ec, 1316 0x3600, 0x5624, 1317 0x56cc, 0x56ec, 1318 0x56f4, 0x5720, 1319 0x5728, 0x575c, 1320 0x580c, 0x5814, 1321 0x5890, 0x589c, 1322 0x58a4, 0x58ac, 1323 0x58b8, 0x58bc, 1324 0x5940, 0x59c8, 1325 0x59d0, 0x59dc, 1326 0x59fc, 0x5a18, 1327 0x5a60, 0x5a70, 1328 0x5a80, 0x5a9c, 1329 0x5b94, 0x5bfc, 1330 0x6000, 0x6020, 1331 0x6028, 0x6040, 1332 0x6058, 0x609c, 1333 0x60a8, 0x614c, 1334 0x7700, 0x7798, 1335 0x77c0, 0x78fc, 1336 0x7b00, 0x7b58, 1337 0x7b60, 0x7b84, 1338 0x7b8c, 0x7c54, 1339 0x7d00, 0x7d38, 1340 0x7d40, 0x7d80, 1341 0x7d8c, 0x7ddc, 1342 0x7de4, 0x7e04, 1343 0x7e10, 0x7e1c, 1344 0x7e24, 0x7e38, 1345 0x7e40, 0x7e44, 1346 0x7e4c, 0x7e78, 1347 0x7e80, 0x7edc, 1348 0x7ee8, 0x7efc, 1349 0x8dc0, 0x8de0, 1350 0x8df8, 0x8e04, 1351 0x8e10, 0x8e84, 1352 0x8ea0, 0x8f84, 1353 0x8fc0, 0x9058, 1354 0x9060, 0x9060, 1355 0x9068, 0x90f8, 1356 0x9400, 0x9408, 1357 0x9410, 0x9470, 1358 0x9600, 0x9600, 1359 0x9608, 0x9638, 1360 0x9640, 0x96f4, 1361 0x9800, 0x9808, 1362 0x9810, 0x9864, 1363 0x9c00, 0x9c6c, 1364 0x9c80, 0x9cec, 1365 0x9d00, 0x9d6c, 1366 0x9d80, 0x9dec, 1367 0x9e00, 0x9e6c, 1368 0x9e80, 0x9eec, 1369 0x9f00, 0x9f6c, 1370 0x9f80, 0xa020, 1371 0xd000, 0xd004, 1372 0xd010, 0xd03c, 1373 0xdfc0, 0xdfe0, 1374 0xe000, 0x1106c, 1375 0x11074, 0x11088, 1376 0x1109c, 0x11110, 1377 0x11118, 0x1117c, 1378 0x11190, 0x11204, 1379 0x19040, 0x1906c, 1380 0x19078, 0x19080, 1381 0x1908c, 0x190e8, 1382 0x190f0, 0x190f8, 1383 0x19100, 0x19110, 1384 0x19120, 0x19124, 1385 0x19150, 0x19194, 1386 0x1919c, 0x191b0, 1387 0x191d0, 0x191e8, 1388 0x19238, 0x19290, 1389 0x193f8, 0x19428, 1390 0x19430, 0x19444, 1391 0x1944c, 0x1946c, 1392 0x19474, 0x19474, 1393 0x19490, 0x194cc, 1394 0x194f0, 0x194f8, 1395 0x19c00, 0x19c08, 1396 0x19c10, 0x19c60, 1397 0x19c94, 0x19ce4, 1398 0x19cf0, 0x19d40, 1399 0x19d50, 0x19d94, 1400 0x19da0, 0x19de8, 1401 0x19df0, 0x19e10, 1402 0x19e50, 0x19e90, 1403 0x19ea0, 0x19f24, 1404 0x19f34, 0x19f34, 1405 0x19f40, 0x19f50, 1406 0x19f90, 0x19fb4, 1407 0x19fc4, 0x19fe4, 1408 0x1a000, 0x1a004, 1409 0x1a010, 0x1a06c, 1410 0x1a0b0, 0x1a0e4, 1411 0x1a0ec, 0x1a0f8, 1412 0x1a100, 0x1a108, 1413 0x1a114, 0x1a130, 1414 0x1a138, 0x1a1c4, 1415 0x1a1fc, 0x1a1fc, 1416 0x1e008, 0x1e00c, 1417 0x1e040, 0x1e044, 1418 0x1e04c, 0x1e04c, 1419 0x1e284, 0x1e290, 1420 0x1e2c0, 0x1e2c0, 1421 0x1e2e0, 0x1e2e0, 1422 0x1e300, 0x1e384, 1423 0x1e3c0, 0x1e3c8, 1424 0x1e408, 0x1e40c, 1425 0x1e440, 0x1e444, 1426 0x1e44c, 0x1e44c, 1427 0x1e684, 0x1e690, 1428 0x1e6c0, 0x1e6c0, 1429 0x1e6e0, 0x1e6e0, 1430 0x1e700, 0x1e784, 1431 0x1e7c0, 0x1e7c8, 1432 0x1e808, 0x1e80c, 1433 0x1e840, 0x1e844, 1434 0x1e84c, 0x1e84c, 1435 0x1ea84, 0x1ea90, 1436 0x1eac0, 0x1eac0, 1437 0x1eae0, 0x1eae0, 1438 0x1eb00, 0x1eb84, 1439 0x1ebc0, 0x1ebc8, 1440 0x1ec08, 0x1ec0c, 1441 0x1ec40, 0x1ec44, 1442 0x1ec4c, 0x1ec4c, 1443 0x1ee84, 0x1ee90, 1444 0x1eec0, 0x1eec0, 1445 0x1eee0, 0x1eee0, 1446 0x1ef00, 0x1ef84, 1447 0x1efc0, 0x1efc8, 1448 0x1f008, 0x1f00c, 1449 0x1f040, 0x1f044, 1450 0x1f04c, 0x1f04c, 1451 0x1f284, 0x1f290, 1452 0x1f2c0, 0x1f2c0, 1453 0x1f2e0, 0x1f2e0, 1454 0x1f300, 0x1f384, 1455 0x1f3c0, 0x1f3c8, 1456 0x1f408, 0x1f40c, 1457 0x1f440, 0x1f444, 1458 0x1f44c, 0x1f44c, 1459 0x1f684, 0x1f690, 1460 0x1f6c0, 0x1f6c0, 1461 0x1f6e0, 0x1f6e0, 1462 0x1f700, 0x1f784, 1463 0x1f7c0, 0x1f7c8, 1464 0x1f808, 0x1f80c, 1465 0x1f840, 0x1f844, 1466 0x1f84c, 0x1f84c, 1467 0x1fa84, 0x1fa90, 1468 0x1fac0, 0x1fac0, 1469 0x1fae0, 0x1fae0, 1470 0x1fb00, 0x1fb84, 1471 0x1fbc0, 0x1fbc8, 1472 0x1fc08, 0x1fc0c, 1473 0x1fc40, 0x1fc44, 1474 0x1fc4c, 0x1fc4c, 1475 0x1fe84, 0x1fe90, 1476 0x1fec0, 0x1fec0, 1477 0x1fee0, 0x1fee0, 1478 0x1ff00, 0x1ff84, 1479 0x1ffc0, 0x1ffc8, 1480 0x30000, 0x30030, 1481 0x30100, 0x30144, 1482 0x30190, 0x301a0, 1483 0x301a8, 0x301b8, 1484 0x301c4, 0x301c8, 1485 0x301d0, 0x301d0, 1486 0x30200, 0x30318, 1487 0x30400, 0x304b4, 1488 0x304c0, 0x3052c, 1489 0x30540, 0x3061c, 1490 0x30800, 0x30828, 1491 0x30834, 0x30834, 1492 0x308c0, 0x30908, 1493 0x30910, 0x309ac, 1494 0x30a00, 0x30a14, 1495 0x30a1c, 0x30a2c, 1496 0x30a44, 0x30a50, 1497 0x30a74, 0x30a74, 1498 0x30a7c, 0x30afc, 1499 0x30b08, 0x30c24, 1500 0x30d00, 0x30d00, 1501 0x30d08, 0x30d14, 1502 0x30d1c, 0x30d20, 1503 0x30d3c, 0x30d3c, 1504 0x30d48, 0x30d50, 1505 0x31200, 0x3120c, 1506 0x31220, 0x31220, 1507 0x31240, 0x31240, 1508 0x31600, 0x3160c, 1509 0x31a00, 0x31a1c, 1510 0x31e00, 0x31e20, 1511 0x31e38, 0x31e3c, 1512 0x31e80, 0x31e80, 1513 0x31e88, 0x31ea8, 1514 0x31eb0, 0x31eb4, 1515 0x31ec8, 0x31ed4, 1516 0x31fb8, 0x32004, 1517 0x32200, 0x32200, 1518 0x32208, 0x32240, 1519 0x32248, 0x32280, 1520 0x32288, 0x322c0, 1521 0x322c8, 0x322fc, 1522 0x32600, 0x32630, 1523 0x32a00, 0x32abc, 1524 0x32b00, 0x32b10, 1525 0x32b20, 0x32b30, 1526 0x32b40, 0x32b50, 1527 0x32b60, 0x32b70, 1528 0x33000, 0x33028, 1529 0x33030, 0x33048, 1530 0x33060, 0x33068, 1531 0x33070, 0x3309c, 1532 0x330f0, 0x33128, 1533 0x33130, 0x33148, 1534 0x33160, 0x33168, 1535 0x33170, 0x3319c, 1536 0x331f0, 0x33238, 1537 0x33240, 0x33240, 1538 0x33248, 0x33250, 1539 0x3325c, 0x33264, 1540 0x33270, 0x332b8, 1541 0x332c0, 0x332e4, 1542 0x332f8, 0x33338, 1543 0x33340, 0x33340, 1544 0x33348, 0x33350, 1545 0x3335c, 0x33364, 1546 0x33370, 0x333b8, 1547 0x333c0, 0x333e4, 1548 0x333f8, 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1722 0x38d1c, 0x38d20, 1723 0x38d3c, 0x38d3c, 1724 0x38d48, 0x38d50, 1725 0x39200, 0x3920c, 1726 0x39220, 0x39220, 1727 0x39240, 0x39240, 1728 0x39600, 0x3960c, 1729 0x39a00, 0x39a1c, 1730 0x39e00, 0x39e20, 1731 0x39e38, 0x39e3c, 1732 0x39e80, 0x39e80, 1733 0x39e88, 0x39ea8, 1734 0x39eb0, 0x39eb4, 1735 0x39ec8, 0x39ed4, 1736 0x39fb8, 0x3a004, 1737 0x3a200, 0x3a200, 1738 0x3a208, 0x3a240, 1739 0x3a248, 0x3a280, 1740 0x3a288, 0x3a2c0, 1741 0x3a2c8, 0x3a2fc, 1742 0x3a600, 0x3a630, 1743 0x3aa00, 0x3aabc, 1744 0x3ab00, 0x3ab10, 1745 0x3ab20, 0x3ab30, 1746 0x3ab40, 0x3ab50, 1747 0x3ab60, 0x3ab70, 1748 0x3b000, 0x3b028, 1749 0x3b030, 0x3b048, 1750 0x3b060, 0x3b068, 1751 0x3b070, 0x3b09c, 1752 0x3b0f0, 0x3b128, 1753 0x3b130, 0x3b148, 1754 0x3b160, 0x3b168, 1755 0x3b170, 0x3b19c, 1756 0x3b1f0, 0x3b238, 1757 0x3b240, 0x3b240, 1758 0x3b248, 0x3b250, 1759 0x3b25c, 0x3b264, 1760 0x3b270, 0x3b2b8, 1761 0x3b2c0, 0x3b2e4, 1762 0x3b2f8, 0x3b338, 1763 0x3b340, 0x3b340, 1764 0x3b348, 0x3b350, 1765 0x3b35c, 0x3b364, 1766 0x3b370, 0x3b3b8, 1767 0x3b3c0, 0x3b3e4, 1768 0x3b3f8, 0x3b428, 1769 0x3b430, 0x3b448, 1770 0x3b460, 0x3b468, 1771 0x3b470, 0x3b49c, 1772 0x3b4f0, 0x3b528, 1773 0x3b530, 0x3b548, 1774 0x3b560, 0x3b568, 1775 0x3b570, 0x3b59c, 1776 0x3b5f0, 0x3b638, 1777 0x3b640, 0x3b640, 1778 0x3b648, 0x3b650, 1779 0x3b65c, 0x3b664, 1780 0x3b670, 0x3b6b8, 1781 0x3b6c0, 0x3b6e4, 1782 0x3b6f8, 0x3b738, 1783 0x3b740, 0x3b740, 1784 0x3b748, 0x3b750, 1785 0x3b75c, 0x3b764, 1786 0x3b770, 0x3b7b8, 1787 0x3b7c0, 0x3b7e4, 1788 0x3b7f8, 0x3b7fc, 1789 0x3b814, 0x3b814, 1790 0x3b82c, 0x3b82c, 1791 0x3b880, 0x3b88c, 1792 0x3b8e8, 0x3b8ec, 1793 0x3b900, 0x3b928, 1794 0x3b930, 0x3b948, 1795 0x3b960, 0x3b968, 1796 0x3b970, 0x3b99c, 1797 0x3b9f0, 0x3ba38, 1798 0x3ba40, 0x3ba40, 1799 0x3ba48, 0x3ba50, 1800 0x3ba5c, 0x3ba64, 1801 0x3ba70, 0x3bab8, 1802 0x3bac0, 0x3bae4, 1803 0x3baf8, 0x3bb10, 1804 0x3bb28, 0x3bb28, 1805 0x3bb3c, 0x3bb50, 1806 0x3bbf0, 0x3bc10, 1807 0x3bc28, 0x3bc28, 1808 0x3bc3c, 0x3bc50, 1809 0x3bcf0, 0x3bcfc, 1810 0x3c000, 0x3c030, 1811 0x3c100, 0x3c144, 1812 0x3c190, 0x3c1a0, 1813 0x3c1a8, 0x3c1b8, 1814 0x3c1c4, 0x3c1c8, 1815 0x3c1d0, 0x3c1d0, 1816 0x3c200, 0x3c318, 1817 0x3c400, 0x3c4b4, 1818 0x3c4c0, 0x3c52c, 1819 0x3c540, 0x3c61c, 1820 0x3c800, 0x3c828, 1821 0x3c834, 0x3c834, 1822 0x3c8c0, 0x3c908, 1823 0x3c910, 0x3c9ac, 1824 0x3ca00, 0x3ca14, 1825 0x3ca1c, 0x3ca2c, 1826 0x3ca44, 0x3ca50, 1827 0x3ca74, 0x3ca74, 1828 0x3ca7c, 0x3cafc, 1829 0x3cb08, 0x3cc24, 1830 0x3cd00, 0x3cd00, 1831 0x3cd08, 0x3cd14, 1832 0x3cd1c, 0x3cd20, 1833 0x3cd3c, 0x3cd3c, 1834 0x3cd48, 0x3cd50, 1835 0x3d200, 0x3d20c, 1836 0x3d220, 0x3d220, 1837 0x3d240, 0x3d240, 1838 0x3d600, 0x3d60c, 1839 0x3da00, 0x3da1c, 1840 0x3de00, 0x3de20, 1841 0x3de38, 0x3de3c, 1842 0x3de80, 0x3de80, 1843 0x3de88, 0x3dea8, 1844 0x3deb0, 0x3deb4, 1845 0x3dec8, 0x3ded4, 1846 0x3dfb8, 0x3e004, 1847 0x3e200, 0x3e200, 1848 0x3e208, 0x3e240, 1849 0x3e248, 0x3e280, 1850 0x3e288, 0x3e2c0, 1851 0x3e2c8, 0x3e2fc, 1852 0x3e600, 0x3e630, 1853 0x3ea00, 0x3eabc, 1854 0x3eb00, 0x3eb10, 1855 0x3eb20, 0x3eb30, 1856 0x3eb40, 0x3eb50, 1857 0x3eb60, 0x3eb70, 1858 0x3f000, 0x3f028, 1859 0x3f030, 0x3f048, 1860 0x3f060, 0x3f068, 1861 0x3f070, 0x3f09c, 1862 0x3f0f0, 0x3f128, 1863 0x3f130, 0x3f148, 1864 0x3f160, 0x3f168, 1865 0x3f170, 0x3f19c, 1866 0x3f1f0, 0x3f238, 1867 0x3f240, 0x3f240, 1868 0x3f248, 0x3f250, 1869 0x3f25c, 0x3f264, 1870 0x3f270, 0x3f2b8, 1871 0x3f2c0, 0x3f2e4, 1872 0x3f2f8, 0x3f338, 1873 0x3f340, 0x3f340, 1874 0x3f348, 0x3f350, 1875 0x3f35c, 0x3f364, 1876 0x3f370, 0x3f3b8, 1877 0x3f3c0, 0x3f3e4, 1878 0x3f3f8, 0x3f428, 1879 0x3f430, 0x3f448, 1880 0x3f460, 0x3f468, 1881 0x3f470, 0x3f49c, 1882 0x3f4f0, 0x3f528, 1883 0x3f530, 0x3f548, 1884 0x3f560, 0x3f568, 1885 0x3f570, 0x3f59c, 1886 0x3f5f0, 0x3f638, 1887 0x3f640, 0x3f640, 1888 0x3f648, 0x3f650, 1889 0x3f65c, 0x3f664, 1890 0x3f670, 0x3f6b8, 1891 0x3f6c0, 0x3f6e4, 1892 0x3f6f8, 0x3f738, 1893 0x3f740, 0x3f740, 1894 0x3f748, 0x3f750, 1895 0x3f75c, 0x3f764, 1896 0x3f770, 0x3f7b8, 1897 0x3f7c0, 0x3f7e4, 1898 0x3f7f8, 0x3f7fc, 1899 0x3f814, 0x3f814, 1900 0x3f82c, 0x3f82c, 1901 0x3f880, 0x3f88c, 1902 0x3f8e8, 0x3f8ec, 1903 0x3f900, 0x3f928, 1904 0x3f930, 0x3f948, 1905 0x3f960, 0x3f968, 1906 0x3f970, 0x3f99c, 1907 0x3f9f0, 0x3fa38, 1908 0x3fa40, 0x3fa40, 1909 0x3fa48, 0x3fa50, 1910 0x3fa5c, 0x3fa64, 1911 0x3fa70, 0x3fab8, 1912 0x3fac0, 0x3fae4, 1913 0x3faf8, 0x3fb10, 1914 0x3fb28, 0x3fb28, 1915 0x3fb3c, 0x3fb50, 1916 0x3fbf0, 0x3fc10, 1917 0x3fc28, 0x3fc28, 1918 0x3fc3c, 0x3fc50, 1919 0x3fcf0, 0x3fcfc, 1920 0x40000, 0x4000c, 1921 0x40040, 0x40050, 1922 0x40060, 0x40068, 1923 0x4007c, 0x4008c, 1924 0x40094, 0x400b0, 1925 0x400c0, 0x40144, 1926 0x40180, 0x4018c, 1927 0x40200, 0x40254, 1928 0x40260, 0x40264, 1929 0x40270, 0x40288, 1930 0x40290, 0x40298, 1931 0x402ac, 0x402c8, 1932 0x402d0, 0x402e0, 1933 0x402f0, 0x402f0, 1934 0x40300, 0x4033c, 1935 0x403f8, 0x403fc, 1936 0x41304, 0x413c4, 1937 0x41400, 0x4140c, 1938 0x41414, 0x4141c, 1939 0x41480, 0x414d0, 1940 0x44000, 0x44054, 1941 0x4405c, 0x44078, 1942 0x440c0, 0x44174, 1943 0x44180, 0x441ac, 1944 0x441b4, 0x441b8, 1945 0x441c0, 0x44254, 1946 0x4425c, 0x44278, 1947 0x442c0, 0x44374, 1948 0x44380, 0x443ac, 1949 0x443b4, 0x443b8, 1950 0x443c0, 0x44454, 1951 0x4445c, 0x44478, 1952 0x444c0, 0x44574, 1953 0x44580, 0x445ac, 1954 0x445b4, 0x445b8, 1955 0x445c0, 0x44654, 1956 0x4465c, 0x44678, 1957 0x446c0, 0x44774, 1958 0x44780, 0x447ac, 1959 0x447b4, 0x447b8, 1960 0x447c0, 0x44854, 1961 0x4485c, 0x44878, 1962 0x448c0, 0x44974, 1963 0x44980, 0x449ac, 1964 0x449b4, 0x449b8, 1965 0x449c0, 0x449fc, 1966 0x45000, 0x45004, 1967 0x45010, 0x45030, 1968 0x45040, 0x45060, 1969 0x45068, 0x45068, 1970 0x45080, 0x45084, 1971 0x450a0, 0x450b0, 1972 0x45200, 0x45204, 1973 0x45210, 0x45230, 1974 0x45240, 0x45260, 1975 0x45268, 0x45268, 1976 0x45280, 0x45284, 1977 0x452a0, 0x452b0, 1978 0x460c0, 0x460e4, 1979 0x47000, 0x4703c, 1980 0x47044, 0x4708c, 1981 0x47200, 0x47250, 1982 0x47400, 0x47408, 1983 0x47414, 0x47420, 1984 0x47600, 0x47618, 1985 0x47800, 0x47814, 1986 0x48000, 0x4800c, 1987 0x48040, 0x48050, 1988 0x48060, 0x48068, 1989 0x4807c, 0x4808c, 1990 0x48094, 0x480b0, 1991 0x480c0, 0x48144, 1992 0x48180, 0x4818c, 1993 0x48200, 0x48254, 1994 0x48260, 0x48264, 1995 0x48270, 0x48288, 1996 0x48290, 0x48298, 1997 0x482ac, 0x482c8, 1998 0x482d0, 0x482e0, 1999 0x482f0, 0x482f0, 2000 0x48300, 0x4833c, 2001 0x483f8, 0x483fc, 2002 0x49304, 0x493c4, 2003 0x49400, 0x4940c, 2004 0x49414, 0x4941c, 2005 0x49480, 0x494d0, 2006 0x4c000, 0x4c054, 2007 0x4c05c, 0x4c078, 2008 0x4c0c0, 0x4c174, 2009 0x4c180, 0x4c1ac, 2010 0x4c1b4, 0x4c1b8, 2011 0x4c1c0, 0x4c254, 2012 0x4c25c, 0x4c278, 2013 0x4c2c0, 0x4c374, 2014 0x4c380, 0x4c3ac, 2015 0x4c3b4, 0x4c3b8, 2016 0x4c3c0, 0x4c454, 2017 0x4c45c, 0x4c478, 2018 0x4c4c0, 0x4c574, 2019 0x4c580, 0x4c5ac, 2020 0x4c5b4, 0x4c5b8, 2021 0x4c5c0, 0x4c654, 2022 0x4c65c, 0x4c678, 2023 0x4c6c0, 0x4c774, 2024 0x4c780, 0x4c7ac, 2025 0x4c7b4, 0x4c7b8, 2026 0x4c7c0, 0x4c854, 2027 0x4c85c, 0x4c878, 2028 0x4c8c0, 0x4c974, 2029 0x4c980, 0x4c9ac, 2030 0x4c9b4, 0x4c9b8, 2031 0x4c9c0, 0x4c9fc, 2032 0x4d000, 0x4d004, 2033 0x4d010, 0x4d030, 2034 0x4d040, 0x4d060, 2035 0x4d068, 0x4d068, 2036 0x4d080, 0x4d084, 2037 0x4d0a0, 0x4d0b0, 2038 0x4d200, 0x4d204, 2039 0x4d210, 0x4d230, 2040 0x4d240, 0x4d260, 2041 0x4d268, 0x4d268, 2042 0x4d280, 0x4d284, 2043 0x4d2a0, 0x4d2b0, 2044 0x4e0c0, 0x4e0e4, 2045 0x4f000, 0x4f03c, 2046 0x4f044, 0x4f08c, 2047 0x4f200, 0x4f250, 2048 0x4f400, 0x4f408, 2049 0x4f414, 0x4f420, 2050 0x4f600, 0x4f618, 2051 0x4f800, 0x4f814, 2052 0x50000, 0x50084, 2053 0x50090, 0x500cc, 2054 0x50400, 0x50400, 2055 0x50800, 0x50884, 2056 0x50890, 0x508cc, 2057 0x50c00, 0x50c00, 2058 0x51000, 0x5101c, 2059 0x51300, 0x51308, 2060 }; 2061 2062 static const unsigned int t5vf_reg_ranges[] = { 2063 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2064 VF_MPS_REG(A_MPS_VF_CTL), 2065 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2066 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2068 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2069 FW_T4VF_MBDATA_BASE_ADDR, 2070 FW_T4VF_MBDATA_BASE_ADDR + 2071 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2072 }; 2073 2074 static const unsigned int t6_reg_ranges[] = { 2075 0x1008, 0x101c, 2076 0x1024, 0x10a8, 2077 0x10b4, 0x10f8, 2078 0x1100, 0x1114, 2079 0x111c, 0x112c, 2080 0x1138, 0x113c, 2081 0x1144, 0x114c, 2082 0x1180, 0x1184, 2083 0x1190, 0x1194, 2084 0x11a0, 0x11a4, 2085 0x11b0, 0x11c4, 2086 0x11fc, 0x123c, 2087 0x1254, 0x1274, 2088 0x1280, 0x133c, 2089 0x1800, 0x18fc, 2090 0x3000, 0x302c, 2091 0x3060, 0x30b0, 2092 0x30b8, 0x30d8, 2093 0x30e0, 0x30fc, 2094 0x3140, 0x357c, 2095 0x35a8, 0x35cc, 2096 0x35ec, 0x35ec, 2097 0x3600, 0x5624, 2098 0x56cc, 0x56ec, 2099 0x56f4, 0x5720, 2100 0x5728, 0x575c, 2101 0x580c, 0x5814, 2102 0x5890, 0x589c, 2103 0x58a4, 0x58ac, 2104 0x58b8, 0x58bc, 2105 0x5940, 0x595c, 2106 0x5980, 0x598c, 2107 0x59b0, 0x59c8, 2108 0x59d0, 0x59dc, 2109 0x59fc, 0x5a18, 2110 0x5a60, 0x5a6c, 2111 0x5a80, 0x5a8c, 2112 0x5a94, 0x5a9c, 2113 0x5b94, 0x5bfc, 2114 0x5c10, 0x5e48, 2115 0x5e50, 0x5e94, 2116 0x5ea0, 0x5eb0, 2117 0x5ec0, 0x5ec0, 2118 0x5ec8, 0x5ed0, 2119 0x5ee0, 0x5ee0, 2120 0x5ef0, 0x5ef0, 2121 0x5f00, 0x5f00, 2122 0x6000, 0x6020, 2123 0x6028, 0x6040, 2124 0x6058, 0x609c, 2125 0x60a8, 0x619c, 2126 0x7700, 0x7798, 2127 0x77c0, 0x7880, 2128 0x78cc, 0x78fc, 2129 0x7b00, 0x7b58, 2130 0x7b60, 0x7b84, 2131 0x7b8c, 0x7c54, 2132 0x7d00, 0x7d38, 2133 0x7d40, 0x7d84, 2134 0x7d8c, 0x7ddc, 2135 0x7de4, 0x7e04, 2136 0x7e10, 0x7e1c, 2137 0x7e24, 0x7e38, 2138 0x7e40, 0x7e44, 2139 0x7e4c, 0x7e78, 2140 0x7e80, 0x7edc, 2141 0x7ee8, 0x7efc, 2142 0x8dc0, 0x8de0, 2143 0x8df8, 0x8e04, 2144 0x8e10, 0x8e84, 2145 0x8ea0, 0x8f88, 2146 0x8fb8, 0x9058, 2147 0x9060, 0x9060, 2148 0x9068, 0x90f8, 2149 0x9100, 0x9124, 2150 0x9400, 0x9470, 2151 0x9600, 0x9600, 2152 0x9608, 0x9638, 2153 0x9640, 0x9704, 2154 0x9710, 0x971c, 2155 0x9800, 0x9808, 2156 0x9810, 0x9864, 2157 0x9c00, 0x9c6c, 2158 0x9c80, 0x9cec, 2159 0x9d00, 0x9d6c, 2160 0x9d80, 0x9dec, 2161 0x9e00, 0x9e6c, 2162 0x9e80, 0x9eec, 2163 0x9f00, 0x9f6c, 2164 0x9f80, 0xa020, 2165 0xd000, 0xd03c, 2166 0xd100, 0xd118, 2167 0xd200, 0xd214, 2168 0xd220, 0xd234, 2169 0xd240, 0xd254, 2170 0xd260, 0xd274, 2171 0xd280, 0xd294, 2172 0xd2a0, 0xd2b4, 2173 0xd2c0, 0xd2d4, 2174 0xd2e0, 0xd2f4, 2175 0xd300, 0xd31c, 2176 0xdfc0, 0xdfe0, 2177 0xe000, 0xf008, 2178 0xf010, 0xf018, 2179 0xf020, 0xf028, 2180 0x11000, 0x11014, 2181 0x11048, 0x1106c, 2182 0x11074, 0x11088, 2183 0x11098, 0x11120, 2184 0x1112c, 0x1117c, 2185 0x11190, 0x112e0, 2186 0x11300, 0x1130c, 2187 0x12000, 0x1206c, 2188 0x19040, 0x1906c, 2189 0x19078, 0x19080, 2190 0x1908c, 0x190e8, 2191 0x190f0, 0x190f8, 2192 0x19100, 0x19110, 2193 0x19120, 0x19124, 2194 0x19150, 0x19194, 2195 0x1919c, 0x191b0, 2196 0x191d0, 0x191e8, 2197 0x19238, 0x19290, 2198 0x192a4, 0x192b0, 2199 0x19348, 0x1934c, 2200 0x193f8, 0x19418, 2201 0x19420, 0x19428, 2202 0x19430, 0x19444, 2203 0x1944c, 0x1946c, 2204 0x19474, 0x19474, 2205 0x19490, 0x194cc, 2206 0x194f0, 0x194f8, 2207 0x19c00, 0x19c48, 2208 0x19c50, 0x19c80, 2209 0x19c94, 0x19c98, 2210 0x19ca0, 0x19cbc, 2211 0x19ce4, 0x19ce4, 2212 0x19cf0, 0x19cf8, 2213 0x19d00, 0x19d28, 2214 0x19d50, 0x19d78, 2215 0x19d94, 0x19d98, 2216 0x19da0, 0x19de0, 2217 0x19df0, 0x19e10, 2218 0x19e50, 0x19e6c, 2219 0x19ea0, 0x19ebc, 2220 0x19ec4, 0x19ef4, 2221 0x19f04, 0x19f2c, 2222 0x19f34, 0x19f34, 2223 0x19f40, 0x19f50, 2224 0x19f90, 0x19fac, 2225 0x19fc4, 0x19fc8, 2226 0x19fd0, 0x19fe4, 2227 0x1a000, 0x1a004, 2228 0x1a010, 0x1a06c, 2229 0x1a0b0, 0x1a0e4, 2230 0x1a0ec, 0x1a0f8, 2231 0x1a100, 0x1a108, 2232 0x1a114, 0x1a130, 2233 0x1a138, 0x1a1c4, 2234 0x1a1fc, 0x1a1fc, 2235 0x1e008, 0x1e00c, 2236 0x1e040, 0x1e044, 2237 0x1e04c, 0x1e04c, 2238 0x1e284, 0x1e290, 2239 0x1e2c0, 0x1e2c0, 2240 0x1e2e0, 0x1e2e0, 2241 0x1e300, 0x1e384, 2242 0x1e3c0, 0x1e3c8, 2243 0x1e408, 0x1e40c, 2244 0x1e440, 0x1e444, 2245 0x1e44c, 0x1e44c, 2246 0x1e684, 0x1e690, 2247 0x1e6c0, 0x1e6c0, 2248 0x1e6e0, 0x1e6e0, 2249 0x1e700, 0x1e784, 2250 0x1e7c0, 0x1e7c8, 2251 0x1e808, 0x1e80c, 2252 0x1e840, 0x1e844, 2253 0x1e84c, 0x1e84c, 2254 0x1ea84, 0x1ea90, 2255 0x1eac0, 0x1eac0, 2256 0x1eae0, 0x1eae0, 2257 0x1eb00, 0x1eb84, 2258 0x1ebc0, 0x1ebc8, 2259 0x1ec08, 0x1ec0c, 2260 0x1ec40, 0x1ec44, 2261 0x1ec4c, 0x1ec4c, 2262 0x1ee84, 0x1ee90, 2263 0x1eec0, 0x1eec0, 2264 0x1eee0, 0x1eee0, 2265 0x1ef00, 0x1ef84, 2266 0x1efc0, 0x1efc8, 2267 0x1f008, 0x1f00c, 2268 0x1f040, 0x1f044, 2269 0x1f04c, 0x1f04c, 2270 0x1f284, 0x1f290, 2271 0x1f2c0, 0x1f2c0, 2272 0x1f2e0, 0x1f2e0, 2273 0x1f300, 0x1f384, 2274 0x1f3c0, 0x1f3c8, 2275 0x1f408, 0x1f40c, 2276 0x1f440, 0x1f444, 2277 0x1f44c, 0x1f44c, 2278 0x1f684, 0x1f690, 2279 0x1f6c0, 0x1f6c0, 2280 0x1f6e0, 0x1f6e0, 2281 0x1f700, 0x1f784, 2282 0x1f7c0, 0x1f7c8, 2283 0x1f808, 0x1f80c, 2284 0x1f840, 0x1f844, 2285 0x1f84c, 0x1f84c, 2286 0x1fa84, 0x1fa90, 2287 0x1fac0, 0x1fac0, 2288 0x1fae0, 0x1fae0, 2289 0x1fb00, 0x1fb84, 2290 0x1fbc0, 0x1fbc8, 2291 0x1fc08, 0x1fc0c, 2292 0x1fc40, 0x1fc44, 2293 0x1fc4c, 0x1fc4c, 2294 0x1fe84, 0x1fe90, 2295 0x1fec0, 0x1fec0, 2296 0x1fee0, 0x1fee0, 2297 0x1ff00, 0x1ff84, 2298 0x1ffc0, 0x1ffc8, 2299 0x30000, 0x30030, 2300 0x30100, 0x30168, 2301 0x30190, 0x301a0, 2302 0x301a8, 0x301b8, 2303 0x301c4, 0x301c8, 2304 0x301d0, 0x301d0, 2305 0x30200, 0x30320, 2306 0x30400, 0x304b4, 2307 0x304c0, 0x3052c, 2308 0x30540, 0x3061c, 2309 0x30800, 0x308a0, 2310 0x308c0, 0x30908, 2311 0x30910, 0x309b8, 2312 0x30a00, 0x30a04, 2313 0x30a0c, 0x30a14, 2314 0x30a1c, 0x30a2c, 2315 0x30a44, 0x30a50, 2316 0x30a74, 0x30a74, 2317 0x30a7c, 0x30afc, 2318 0x30b08, 0x30c24, 2319 0x30d00, 0x30d14, 2320 0x30d1c, 0x30d3c, 2321 0x30d44, 0x30d4c, 2322 0x30d54, 0x30d74, 2323 0x30d7c, 0x30d7c, 2324 0x30de0, 0x30de0, 2325 0x30e00, 0x30ed4, 2326 0x30f00, 0x30fa4, 2327 0x30fc0, 0x30fc4, 2328 0x31000, 0x31004, 2329 0x31080, 0x310fc, 2330 0x31208, 0x31220, 2331 0x3123c, 0x31254, 2332 0x31300, 0x31300, 2333 0x31308, 0x3131c, 2334 0x31338, 0x3133c, 2335 0x31380, 0x31380, 2336 0x31388, 0x313a8, 2337 0x313b4, 0x313b4, 2338 0x31400, 0x31420, 2339 0x31438, 0x3143c, 2340 0x31480, 0x31480, 2341 0x314a8, 0x314a8, 2342 0x314b0, 0x314b4, 2343 0x314c8, 0x314d4, 2344 0x31a40, 0x31a4c, 2345 0x31af0, 0x31b20, 2346 0x31b38, 0x31b3c, 2347 0x31b80, 0x31b80, 2348 0x31ba8, 0x31ba8, 2349 0x31bb0, 0x31bb4, 2350 0x31bc8, 0x31bd4, 2351 0x32140, 0x3218c, 2352 0x321f0, 0x321f4, 2353 0x32200, 0x32200, 2354 0x32218, 0x32218, 2355 0x32400, 0x32400, 2356 0x32408, 0x3241c, 2357 0x32618, 0x32620, 2358 0x32664, 0x32664, 2359 0x326a8, 0x326a8, 2360 0x326ec, 0x326ec, 2361 0x32a00, 0x32abc, 2362 0x32b00, 0x32b18, 2363 0x32b20, 0x32b38, 2364 0x32b40, 0x32b58, 2365 0x32b60, 0x32b78, 2366 0x32c00, 0x32c00, 2367 0x32c08, 0x32c3c, 2368 0x33000, 0x3302c, 2369 0x33034, 0x33050, 2370 0x33058, 0x33058, 2371 0x33060, 0x3308c, 2372 0x3309c, 0x330ac, 2373 0x330c0, 0x330c0, 2374 0x330c8, 0x330d0, 2375 0x330d8, 0x330e0, 2376 0x330ec, 0x3312c, 2377 0x33134, 0x33150, 2378 0x33158, 0x33158, 2379 0x33160, 0x3318c, 2380 0x3319c, 0x331ac, 2381 0x331c0, 0x331c0, 2382 0x331c8, 0x331d0, 2383 0x331d8, 0x331e0, 2384 0x331ec, 0x33290, 2385 0x33298, 0x332c4, 2386 0x332e4, 0x33390, 2387 0x33398, 0x333c4, 2388 0x333e4, 0x3342c, 2389 0x33434, 0x33450, 2390 0x33458, 0x33458, 2391 0x33460, 0x3348c, 2392 0x3349c, 0x334ac, 2393 0x334c0, 0x334c0, 2394 0x334c8, 0x334d0, 2395 0x334d8, 0x334e0, 2396 0x334ec, 0x3352c, 2397 0x33534, 0x33550, 2398 0x33558, 0x33558, 2399 0x33560, 0x3358c, 2400 0x3359c, 0x335ac, 2401 0x335c0, 0x335c0, 2402 0x335c8, 0x335d0, 2403 0x335d8, 0x335e0, 2404 0x335ec, 0x33690, 2405 0x33698, 0x336c4, 2406 0x336e4, 0x33790, 2407 0x33798, 0x337c4, 2408 0x337e4, 0x337fc, 2409 0x33814, 0x33814, 2410 0x33854, 0x33868, 2411 0x33880, 0x3388c, 2412 0x338c0, 0x338d0, 2413 0x338e8, 0x338ec, 2414 0x33900, 0x3392c, 2415 0x33934, 0x33950, 2416 0x33958, 0x33958, 2417 0x33960, 0x3398c, 2418 0x3399c, 0x339ac, 2419 0x339c0, 0x339c0, 2420 0x339c8, 0x339d0, 2421 0x339d8, 0x339e0, 2422 0x339ec, 0x33a90, 2423 0x33a98, 0x33ac4, 2424 0x33ae4, 0x33b10, 2425 0x33b24, 0x33b28, 2426 0x33b38, 0x33b50, 2427 0x33bf0, 0x33c10, 2428 0x33c24, 0x33c28, 2429 0x33c38, 0x33c50, 2430 0x33cf0, 0x33cfc, 2431 0x34000, 0x34030, 2432 0x34100, 0x34168, 2433 0x34190, 0x341a0, 2434 0x341a8, 0x341b8, 2435 0x341c4, 0x341c8, 2436 0x341d0, 0x341d0, 2437 0x34200, 0x34320, 2438 0x34400, 0x344b4, 2439 0x344c0, 0x3452c, 2440 0x34540, 0x3461c, 2441 0x34800, 0x348a0, 2442 0x348c0, 0x34908, 2443 0x34910, 0x349b8, 2444 0x34a00, 0x34a04, 2445 0x34a0c, 0x34a14, 2446 0x34a1c, 0x34a2c, 2447 0x34a44, 0x34a50, 2448 0x34a74, 0x34a74, 2449 0x34a7c, 0x34afc, 2450 0x34b08, 0x34c24, 2451 0x34d00, 0x34d14, 2452 0x34d1c, 0x34d3c, 2453 0x34d44, 0x34d4c, 2454 0x34d54, 0x34d74, 2455 0x34d7c, 0x34d7c, 2456 0x34de0, 0x34de0, 2457 0x34e00, 0x34ed4, 2458 0x34f00, 0x34fa4, 2459 0x34fc0, 0x34fc4, 2460 0x35000, 0x35004, 2461 0x35080, 0x350fc, 2462 0x35208, 0x35220, 2463 0x3523c, 0x35254, 2464 0x35300, 0x35300, 2465 0x35308, 0x3531c, 2466 0x35338, 0x3533c, 2467 0x35380, 0x35380, 2468 0x35388, 0x353a8, 2469 0x353b4, 0x353b4, 2470 0x35400, 0x35420, 2471 0x35438, 0x3543c, 2472 0x35480, 0x35480, 2473 0x354a8, 0x354a8, 2474 0x354b0, 0x354b4, 2475 0x354c8, 0x354d4, 2476 0x35a40, 0x35a4c, 2477 0x35af0, 0x35b20, 2478 0x35b38, 0x35b3c, 2479 0x35b80, 0x35b80, 2480 0x35ba8, 0x35ba8, 2481 0x35bb0, 0x35bb4, 2482 0x35bc8, 0x35bd4, 2483 0x36140, 0x3618c, 2484 0x361f0, 0x361f4, 2485 0x36200, 0x36200, 2486 0x36218, 0x36218, 2487 0x36400, 0x36400, 2488 0x36408, 0x3641c, 2489 0x36618, 0x36620, 2490 0x36664, 0x36664, 2491 0x366a8, 0x366a8, 2492 0x366ec, 0x366ec, 2493 0x36a00, 0x36abc, 2494 0x36b00, 0x36b18, 2495 0x36b20, 0x36b38, 2496 0x36b40, 0x36b58, 2497 0x36b60, 0x36b78, 2498 0x36c00, 0x36c00, 2499 0x36c08, 0x36c3c, 2500 0x37000, 0x3702c, 2501 0x37034, 0x37050, 2502 0x37058, 0x37058, 2503 0x37060, 0x3708c, 2504 0x3709c, 0x370ac, 2505 0x370c0, 0x370c0, 2506 0x370c8, 0x370d0, 2507 0x370d8, 0x370e0, 2508 0x370ec, 0x3712c, 2509 0x37134, 0x37150, 2510 0x37158, 0x37158, 2511 0x37160, 0x3718c, 2512 0x3719c, 0x371ac, 2513 0x371c0, 0x371c0, 2514 0x371c8, 0x371d0, 2515 0x371d8, 0x371e0, 2516 0x371ec, 0x37290, 2517 0x37298, 0x372c4, 2518 0x372e4, 0x37390, 2519 0x37398, 0x373c4, 2520 0x373e4, 0x3742c, 2521 0x37434, 0x37450, 2522 0x37458, 0x37458, 2523 0x37460, 0x3748c, 2524 0x3749c, 0x374ac, 2525 0x374c0, 0x374c0, 2526 0x374c8, 0x374d0, 2527 0x374d8, 0x374e0, 2528 0x374ec, 0x3752c, 2529 0x37534, 0x37550, 2530 0x37558, 0x37558, 2531 0x37560, 0x3758c, 2532 0x3759c, 0x375ac, 2533 0x375c0, 0x375c0, 2534 0x375c8, 0x375d0, 2535 0x375d8, 0x375e0, 2536 0x375ec, 0x37690, 2537 0x37698, 0x376c4, 2538 0x376e4, 0x37790, 2539 0x37798, 0x377c4, 2540 0x377e4, 0x377fc, 2541 0x37814, 0x37814, 2542 0x37854, 0x37868, 2543 0x37880, 0x3788c, 2544 0x378c0, 0x378d0, 2545 0x378e8, 0x378ec, 2546 0x37900, 0x3792c, 2547 0x37934, 0x37950, 2548 0x37958, 0x37958, 2549 0x37960, 0x3798c, 2550 0x3799c, 0x379ac, 2551 0x379c0, 0x379c0, 2552 0x379c8, 0x379d0, 2553 0x379d8, 0x379e0, 2554 0x379ec, 0x37a90, 2555 0x37a98, 0x37ac4, 2556 0x37ae4, 0x37b10, 2557 0x37b24, 0x37b28, 2558 0x37b38, 0x37b50, 2559 0x37bf0, 0x37c10, 2560 0x37c24, 0x37c28, 2561 0x37c38, 0x37c50, 2562 0x37cf0, 0x37cfc, 2563 0x40040, 0x40040, 2564 0x40080, 0x40084, 2565 0x40100, 0x40100, 2566 0x40140, 0x401bc, 2567 0x40200, 0x40214, 2568 0x40228, 0x40228, 2569 0x40240, 0x40258, 2570 0x40280, 0x40280, 2571 0x40304, 0x40304, 2572 0x40330, 0x4033c, 2573 0x41304, 0x413c8, 2574 0x413d0, 0x413dc, 2575 0x413f0, 0x413f0, 2576 0x41400, 0x4140c, 2577 0x41414, 0x4141c, 2578 0x41480, 0x414d0, 2579 0x44000, 0x4407c, 2580 0x440c0, 0x441ac, 2581 0x441b4, 0x4427c, 2582 0x442c0, 0x443ac, 2583 0x443b4, 0x4447c, 2584 0x444c0, 0x445ac, 2585 0x445b4, 0x4467c, 2586 0x446c0, 0x447ac, 2587 0x447b4, 0x4487c, 2588 0x448c0, 0x449ac, 2589 0x449b4, 0x44a7c, 2590 0x44ac0, 0x44bac, 2591 0x44bb4, 0x44c7c, 2592 0x44cc0, 0x44dac, 2593 0x44db4, 0x44e7c, 2594 0x44ec0, 0x44fac, 2595 0x44fb4, 0x4507c, 2596 0x450c0, 0x451ac, 2597 0x451b4, 0x451fc, 2598 0x45800, 0x45804, 2599 0x45810, 0x45830, 2600 0x45840, 0x45860, 2601 0x45868, 0x45868, 2602 0x45880, 0x45884, 2603 0x458a0, 0x458b0, 2604 0x45a00, 0x45a04, 2605 0x45a10, 0x45a30, 2606 0x45a40, 0x45a60, 2607 0x45a68, 0x45a68, 2608 0x45a80, 0x45a84, 2609 0x45aa0, 0x45ab0, 2610 0x460c0, 0x460e4, 2611 0x47000, 0x4703c, 2612 0x47044, 0x4708c, 2613 0x47200, 0x47250, 2614 0x47400, 0x47408, 2615 0x47414, 0x47420, 2616 0x47600, 0x47618, 2617 0x47800, 0x47814, 2618 0x47820, 0x4782c, 2619 0x50000, 0x50084, 2620 0x50090, 0x500cc, 2621 0x50300, 0x50384, 2622 0x50400, 0x50400, 2623 0x50800, 0x50884, 2624 0x50890, 0x508cc, 2625 0x50b00, 0x50b84, 2626 0x50c00, 0x50c00, 2627 0x51000, 0x51020, 2628 0x51028, 0x510b0, 2629 0x51300, 0x51324, 2630 }; 2631 2632 static const unsigned int t6vf_reg_ranges[] = { 2633 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2634 VF_MPS_REG(A_MPS_VF_CTL), 2635 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2636 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2637 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2638 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2639 FW_T6VF_MBDATA_BASE_ADDR, 2640 FW_T6VF_MBDATA_BASE_ADDR + 2641 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2642 }; 2643 2644 u32 *buf_end = (u32 *)(buf + buf_size); 2645 const unsigned int *reg_ranges; 2646 int reg_ranges_size, range; 2647 unsigned int chip_version = chip_id(adap); 2648 2649 /* 2650 * Select the right set of register ranges to dump depending on the 2651 * adapter chip type. 2652 */ 2653 switch (chip_version) { 2654 case CHELSIO_T4: 2655 if (adap->flags & IS_VF) { 2656 reg_ranges = t4vf_reg_ranges; 2657 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2658 } else { 2659 reg_ranges = t4_reg_ranges; 2660 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2661 } 2662 break; 2663 2664 case CHELSIO_T5: 2665 if (adap->flags & IS_VF) { 2666 reg_ranges = t5vf_reg_ranges; 2667 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2668 } else { 2669 reg_ranges = t5_reg_ranges; 2670 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2671 } 2672 break; 2673 2674 case CHELSIO_T6: 2675 if (adap->flags & IS_VF) { 2676 reg_ranges = t6vf_reg_ranges; 2677 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2678 } else { 2679 reg_ranges = t6_reg_ranges; 2680 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2681 } 2682 break; 2683 2684 default: 2685 CH_ERR(adap, 2686 "Unsupported chip version %d\n", chip_version); 2687 return; 2688 } 2689 2690 /* 2691 * Clear the register buffer and insert the appropriate register 2692 * values selected by the above register ranges. 2693 */ 2694 memset(buf, 0, buf_size); 2695 for (range = 0; range < reg_ranges_size; range += 2) { 2696 unsigned int reg = reg_ranges[range]; 2697 unsigned int last_reg = reg_ranges[range + 1]; 2698 u32 *bufp = (u32 *)(buf + reg); 2699 2700 /* 2701 * Iterate across the register range filling in the register 2702 * buffer but don't write past the end of the register buffer. 2703 */ 2704 while (reg <= last_reg && bufp < buf_end) { 2705 *bufp++ = t4_read_reg(adap, reg); 2706 reg += sizeof(u32); 2707 } 2708 } 2709 } 2710 2711 /* 2712 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2713 * header followed by one or more VPD-R sections, each with its own header. 2714 */ 2715 struct t4_vpd_hdr { 2716 u8 id_tag; 2717 u8 id_len[2]; 2718 u8 id_data[ID_LEN]; 2719 }; 2720 2721 struct t4_vpdr_hdr { 2722 u8 vpdr_tag; 2723 u8 vpdr_len[2]; 2724 }; 2725 2726 /* 2727 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2728 */ 2729 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2730 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2731 2732 #define EEPROM_STAT_ADDR 0x7bfc 2733 #define VPD_SIZE 0x800 2734 #define VPD_BASE 0x400 2735 #define VPD_BASE_OLD 0 2736 #define VPD_LEN 1024 2737 #define VPD_INFO_FLD_HDR_SIZE 3 2738 #define CHELSIO_VPD_UNIQUE_ID 0x82 2739 2740 /* 2741 * Small utility function to wait till any outstanding VPD Access is complete. 2742 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2743 * VPD Access in flight. This allows us to handle the problem of having a 2744 * previous VPD Access time out and prevent an attempt to inject a new VPD 2745 * Request before any in-flight VPD reguest has completed. 2746 */ 2747 static int t4_seeprom_wait(struct adapter *adapter) 2748 { 2749 unsigned int base = adapter->params.pci.vpd_cap_addr; 2750 int max_poll; 2751 2752 /* 2753 * If no VPD Access is in flight, we can just return success right 2754 * away. 2755 */ 2756 if (!adapter->vpd_busy) 2757 return 0; 2758 2759 /* 2760 * Poll the VPD Capability Address/Flag register waiting for it 2761 * to indicate that the operation is complete. 2762 */ 2763 max_poll = EEPROM_MAX_POLL; 2764 do { 2765 u16 val; 2766 2767 udelay(EEPROM_DELAY); 2768 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2769 2770 /* 2771 * If the operation is complete, mark the VPD as no longer 2772 * busy and return success. 2773 */ 2774 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2775 adapter->vpd_busy = 0; 2776 return 0; 2777 } 2778 } while (--max_poll); 2779 2780 /* 2781 * Failure! Note that we leave the VPD Busy status set in order to 2782 * avoid pushing a new VPD Access request into the VPD Capability till 2783 * the current operation eventually succeeds. It's a bug to issue a 2784 * new request when an existing request is in flight and will result 2785 * in corrupt hardware state. 2786 */ 2787 return -ETIMEDOUT; 2788 } 2789 2790 /** 2791 * t4_seeprom_read - read a serial EEPROM location 2792 * @adapter: adapter to read 2793 * @addr: EEPROM virtual address 2794 * @data: where to store the read data 2795 * 2796 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2797 * VPD capability. Note that this function must be called with a virtual 2798 * address. 2799 */ 2800 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2801 { 2802 unsigned int base = adapter->params.pci.vpd_cap_addr; 2803 int ret; 2804 2805 /* 2806 * VPD Accesses must alway be 4-byte aligned! 2807 */ 2808 if (addr >= EEPROMVSIZE || (addr & 3)) 2809 return -EINVAL; 2810 2811 /* 2812 * Wait for any previous operation which may still be in flight to 2813 * complete. 2814 */ 2815 ret = t4_seeprom_wait(adapter); 2816 if (ret) { 2817 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2818 return ret; 2819 } 2820 2821 /* 2822 * Issue our new VPD Read request, mark the VPD as being busy and wait 2823 * for our request to complete. If it doesn't complete, note the 2824 * error and return it to our caller. Note that we do not reset the 2825 * VPD Busy status! 2826 */ 2827 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2828 adapter->vpd_busy = 1; 2829 adapter->vpd_flag = PCI_VPD_ADDR_F; 2830 ret = t4_seeprom_wait(adapter); 2831 if (ret) { 2832 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2833 return ret; 2834 } 2835 2836 /* 2837 * Grab the returned data, swizzle it into our endianness and 2838 * return success. 2839 */ 2840 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2841 *data = le32_to_cpu(*data); 2842 return 0; 2843 } 2844 2845 /** 2846 * t4_seeprom_write - write a serial EEPROM location 2847 * @adapter: adapter to write 2848 * @addr: virtual EEPROM address 2849 * @data: value to write 2850 * 2851 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2852 * VPD capability. Note that this function must be called with a virtual 2853 * address. 2854 */ 2855 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2856 { 2857 unsigned int base = adapter->params.pci.vpd_cap_addr; 2858 int ret; 2859 u32 stats_reg; 2860 int max_poll; 2861 2862 /* 2863 * VPD Accesses must alway be 4-byte aligned! 2864 */ 2865 if (addr >= EEPROMVSIZE || (addr & 3)) 2866 return -EINVAL; 2867 2868 /* 2869 * Wait for any previous operation which may still be in flight to 2870 * complete. 2871 */ 2872 ret = t4_seeprom_wait(adapter); 2873 if (ret) { 2874 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2875 return ret; 2876 } 2877 2878 /* 2879 * Issue our new VPD Read request, mark the VPD as being busy and wait 2880 * for our request to complete. If it doesn't complete, note the 2881 * error and return it to our caller. Note that we do not reset the 2882 * VPD Busy status! 2883 */ 2884 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2885 cpu_to_le32(data)); 2886 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2887 (u16)addr | PCI_VPD_ADDR_F); 2888 adapter->vpd_busy = 1; 2889 adapter->vpd_flag = 0; 2890 ret = t4_seeprom_wait(adapter); 2891 if (ret) { 2892 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2893 return ret; 2894 } 2895 2896 /* 2897 * Reset PCI_VPD_DATA register after a transaction and wait for our 2898 * request to complete. If it doesn't complete, return error. 2899 */ 2900 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2901 max_poll = EEPROM_MAX_POLL; 2902 do { 2903 udelay(EEPROM_DELAY); 2904 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2905 } while ((stats_reg & 0x1) && --max_poll); 2906 if (!max_poll) 2907 return -ETIMEDOUT; 2908 2909 /* Return success! */ 2910 return 0; 2911 } 2912 2913 /** 2914 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2915 * @phys_addr: the physical EEPROM address 2916 * @fn: the PCI function number 2917 * @sz: size of function-specific area 2918 * 2919 * Translate a physical EEPROM address to virtual. The first 1K is 2920 * accessed through virtual addresses starting at 31K, the rest is 2921 * accessed through virtual addresses starting at 0. 2922 * 2923 * The mapping is as follows: 2924 * [0..1K) -> [31K..32K) 2925 * [1K..1K+A) -> [ES-A..ES) 2926 * [1K+A..ES) -> [0..ES-A-1K) 2927 * 2928 * where A = @fn * @sz, and ES = EEPROM size. 2929 */ 2930 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2931 { 2932 fn *= sz; 2933 if (phys_addr < 1024) 2934 return phys_addr + (31 << 10); 2935 if (phys_addr < 1024 + fn) 2936 return EEPROMSIZE - fn + phys_addr - 1024; 2937 if (phys_addr < EEPROMSIZE) 2938 return phys_addr - 1024 - fn; 2939 return -EINVAL; 2940 } 2941 2942 /** 2943 * t4_seeprom_wp - enable/disable EEPROM write protection 2944 * @adapter: the adapter 2945 * @enable: whether to enable or disable write protection 2946 * 2947 * Enables or disables write protection on the serial EEPROM. 2948 */ 2949 int t4_seeprom_wp(struct adapter *adapter, int enable) 2950 { 2951 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2952 } 2953 2954 /** 2955 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2956 * @vpd: Pointer to buffered vpd data structure 2957 * @kw: The keyword to search for 2958 * @region: VPD region to search (starting from 0) 2959 * 2960 * Returns the value of the information field keyword or 2961 * -ENOENT otherwise. 2962 */ 2963 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2964 { 2965 int i, tag; 2966 unsigned int offset, len; 2967 const struct t4_vpdr_hdr *vpdr; 2968 2969 offset = sizeof(struct t4_vpd_hdr); 2970 vpdr = (const void *)(vpd + offset); 2971 tag = vpdr->vpdr_tag; 2972 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2973 while (region--) { 2974 offset += sizeof(struct t4_vpdr_hdr) + len; 2975 vpdr = (const void *)(vpd + offset); 2976 if (++tag != vpdr->vpdr_tag) 2977 return -ENOENT; 2978 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2979 } 2980 offset += sizeof(struct t4_vpdr_hdr); 2981 2982 if (offset + len > VPD_LEN) { 2983 return -ENOENT; 2984 } 2985 2986 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2987 if (memcmp(vpd + i , kw , 2) == 0){ 2988 i += VPD_INFO_FLD_HDR_SIZE; 2989 return i; 2990 } 2991 2992 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2993 } 2994 2995 return -ENOENT; 2996 } 2997 2998 2999 /** 3000 * get_vpd_params - read VPD parameters from VPD EEPROM 3001 * @adapter: adapter to read 3002 * @p: where to store the parameters 3003 * @vpd: caller provided temporary space to read the VPD into 3004 * 3005 * Reads card parameters stored in VPD EEPROM. 3006 */ 3007 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3008 uint16_t device_id, u32 *buf) 3009 { 3010 int i, ret, addr; 3011 int ec, sn, pn, na, md; 3012 u8 csum; 3013 const u8 *vpd = (const u8 *)buf; 3014 3015 /* 3016 * Card information normally starts at VPD_BASE but early cards had 3017 * it at 0. 3018 */ 3019 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3020 if (ret) 3021 return (ret); 3022 3023 /* 3024 * The VPD shall have a unique identifier specified by the PCI SIG. 3025 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3026 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3027 * is expected to automatically put this entry at the 3028 * beginning of the VPD. 3029 */ 3030 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3031 3032 for (i = 0; i < VPD_LEN; i += 4) { 3033 ret = t4_seeprom_read(adapter, addr + i, buf++); 3034 if (ret) 3035 return ret; 3036 } 3037 3038 #define FIND_VPD_KW(var,name) do { \ 3039 var = get_vpd_keyword_val(vpd, name, 0); \ 3040 if (var < 0) { \ 3041 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3042 return -EINVAL; \ 3043 } \ 3044 } while (0) 3045 3046 FIND_VPD_KW(i, "RV"); 3047 for (csum = 0; i >= 0; i--) 3048 csum += vpd[i]; 3049 3050 if (csum) { 3051 CH_ERR(adapter, 3052 "corrupted VPD EEPROM, actual csum %u\n", csum); 3053 return -EINVAL; 3054 } 3055 3056 FIND_VPD_KW(ec, "EC"); 3057 FIND_VPD_KW(sn, "SN"); 3058 FIND_VPD_KW(pn, "PN"); 3059 FIND_VPD_KW(na, "NA"); 3060 #undef FIND_VPD_KW 3061 3062 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3063 strstrip(p->id); 3064 memcpy(p->ec, vpd + ec, EC_LEN); 3065 strstrip(p->ec); 3066 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3067 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3068 strstrip(p->sn); 3069 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3070 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3071 strstrip((char *)p->pn); 3072 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3073 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3074 strstrip((char *)p->na); 3075 3076 if (device_id & 0x80) 3077 return 0; /* Custom card */ 3078 3079 md = get_vpd_keyword_val(vpd, "VF", 1); 3080 if (md < 0) { 3081 snprintf(p->md, sizeof(p->md), "unknown"); 3082 } else { 3083 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3084 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3085 strstrip((char *)p->md); 3086 } 3087 3088 return 0; 3089 } 3090 3091 /* serial flash and firmware constants and flash config file constants */ 3092 enum { 3093 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3094 3095 /* flash command opcodes */ 3096 SF_PROG_PAGE = 2, /* program 256B page */ 3097 SF_WR_DISABLE = 4, /* disable writes */ 3098 SF_RD_STATUS = 5, /* read status register */ 3099 SF_WR_ENABLE = 6, /* enable writes */ 3100 SF_RD_DATA_FAST = 0xb, /* read flash */ 3101 SF_RD_ID = 0x9f, /* read ID */ 3102 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3103 }; 3104 3105 /** 3106 * sf1_read - read data from the serial flash 3107 * @adapter: the adapter 3108 * @byte_cnt: number of bytes to read 3109 * @cont: whether another operation will be chained 3110 * @lock: whether to lock SF for PL access only 3111 * @valp: where to store the read data 3112 * 3113 * Reads up to 4 bytes of data from the serial flash. The location of 3114 * the read needs to be specified prior to calling this by issuing the 3115 * appropriate commands to the serial flash. 3116 */ 3117 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3118 int lock, u32 *valp) 3119 { 3120 int ret; 3121 3122 if (!byte_cnt || byte_cnt > 4) 3123 return -EINVAL; 3124 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3125 return -EBUSY; 3126 t4_write_reg(adapter, A_SF_OP, 3127 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3128 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3129 if (!ret) 3130 *valp = t4_read_reg(adapter, A_SF_DATA); 3131 return ret; 3132 } 3133 3134 /** 3135 * sf1_write - write data to the serial flash 3136 * @adapter: the adapter 3137 * @byte_cnt: number of bytes to write 3138 * @cont: whether another operation will be chained 3139 * @lock: whether to lock SF for PL access only 3140 * @val: value to write 3141 * 3142 * Writes up to 4 bytes of data to the serial flash. The location of 3143 * the write needs to be specified prior to calling this by issuing the 3144 * appropriate commands to the serial flash. 3145 */ 3146 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3147 int lock, u32 val) 3148 { 3149 if (!byte_cnt || byte_cnt > 4) 3150 return -EINVAL; 3151 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3152 return -EBUSY; 3153 t4_write_reg(adapter, A_SF_DATA, val); 3154 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3155 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3156 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3157 } 3158 3159 /** 3160 * flash_wait_op - wait for a flash operation to complete 3161 * @adapter: the adapter 3162 * @attempts: max number of polls of the status register 3163 * @delay: delay between polls in ms 3164 * 3165 * Wait for a flash operation to complete by polling the status register. 3166 */ 3167 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3168 { 3169 int ret; 3170 u32 status; 3171 3172 while (1) { 3173 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3174 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3175 return ret; 3176 if (!(status & 1)) 3177 return 0; 3178 if (--attempts == 0) 3179 return -EAGAIN; 3180 if (delay) 3181 msleep(delay); 3182 } 3183 } 3184 3185 /** 3186 * t4_read_flash - read words from serial flash 3187 * @adapter: the adapter 3188 * @addr: the start address for the read 3189 * @nwords: how many 32-bit words to read 3190 * @data: where to store the read data 3191 * @byte_oriented: whether to store data as bytes or as words 3192 * 3193 * Read the specified number of 32-bit words from the serial flash. 3194 * If @byte_oriented is set the read data is stored as a byte array 3195 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3196 * natural endianness. 3197 */ 3198 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3199 unsigned int nwords, u32 *data, int byte_oriented) 3200 { 3201 int ret; 3202 3203 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3204 return -EINVAL; 3205 3206 addr = swab32(addr) | SF_RD_DATA_FAST; 3207 3208 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3209 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3210 return ret; 3211 3212 for ( ; nwords; nwords--, data++) { 3213 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3214 if (nwords == 1) 3215 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3216 if (ret) 3217 return ret; 3218 if (byte_oriented) 3219 *data = (__force __u32)(cpu_to_be32(*data)); 3220 } 3221 return 0; 3222 } 3223 3224 /** 3225 * t4_write_flash - write up to a page of data to the serial flash 3226 * @adapter: the adapter 3227 * @addr: the start address to write 3228 * @n: length of data to write in bytes 3229 * @data: the data to write 3230 * @byte_oriented: whether to store data as bytes or as words 3231 * 3232 * Writes up to a page of data (256 bytes) to the serial flash starting 3233 * at the given address. All the data must be written to the same page. 3234 * If @byte_oriented is set the write data is stored as byte stream 3235 * (i.e. matches what on disk), otherwise in big-endian. 3236 */ 3237 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3238 unsigned int n, const u8 *data, int byte_oriented) 3239 { 3240 int ret; 3241 u32 buf[SF_PAGE_SIZE / 4]; 3242 unsigned int i, c, left, val, offset = addr & 0xff; 3243 3244 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3245 return -EINVAL; 3246 3247 val = swab32(addr) | SF_PROG_PAGE; 3248 3249 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3250 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3251 goto unlock; 3252 3253 for (left = n; left; left -= c) { 3254 c = min(left, 4U); 3255 for (val = 0, i = 0; i < c; ++i) 3256 val = (val << 8) + *data++; 3257 3258 if (!byte_oriented) 3259 val = cpu_to_be32(val); 3260 3261 ret = sf1_write(adapter, c, c != left, 1, val); 3262 if (ret) 3263 goto unlock; 3264 } 3265 ret = flash_wait_op(adapter, 8, 1); 3266 if (ret) 3267 goto unlock; 3268 3269 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3270 3271 /* Read the page to verify the write succeeded */ 3272 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3273 byte_oriented); 3274 if (ret) 3275 return ret; 3276 3277 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3278 CH_ERR(adapter, 3279 "failed to correctly write the flash page at %#x\n", 3280 addr); 3281 return -EIO; 3282 } 3283 return 0; 3284 3285 unlock: 3286 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3287 return ret; 3288 } 3289 3290 /** 3291 * t4_get_fw_version - read the firmware version 3292 * @adapter: the adapter 3293 * @vers: where to place the version 3294 * 3295 * Reads the FW version from flash. 3296 */ 3297 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3298 { 3299 return t4_read_flash(adapter, FLASH_FW_START + 3300 offsetof(struct fw_hdr, fw_ver), 1, 3301 vers, 0); 3302 } 3303 3304 /** 3305 * t4_get_fw_hdr - read the firmware header 3306 * @adapter: the adapter 3307 * @hdr: where to place the version 3308 * 3309 * Reads the FW header from flash into caller provided buffer. 3310 */ 3311 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3312 { 3313 return t4_read_flash(adapter, FLASH_FW_START, 3314 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3315 } 3316 3317 /** 3318 * t4_get_bs_version - read the firmware bootstrap version 3319 * @adapter: the adapter 3320 * @vers: where to place the version 3321 * 3322 * Reads the FW Bootstrap version from flash. 3323 */ 3324 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3325 { 3326 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3327 offsetof(struct fw_hdr, fw_ver), 1, 3328 vers, 0); 3329 } 3330 3331 /** 3332 * t4_get_tp_version - read the TP microcode version 3333 * @adapter: the adapter 3334 * @vers: where to place the version 3335 * 3336 * Reads the TP microcode version from flash. 3337 */ 3338 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3339 { 3340 return t4_read_flash(adapter, FLASH_FW_START + 3341 offsetof(struct fw_hdr, tp_microcode_ver), 3342 1, vers, 0); 3343 } 3344 3345 /** 3346 * t4_get_exprom_version - return the Expansion ROM version (if any) 3347 * @adapter: the adapter 3348 * @vers: where to place the version 3349 * 3350 * Reads the Expansion ROM header from FLASH and returns the version 3351 * number (if present) through the @vers return value pointer. We return 3352 * this in the Firmware Version Format since it's convenient. Return 3353 * 0 on success, -ENOENT if no Expansion ROM is present. 3354 */ 3355 int t4_get_exprom_version(struct adapter *adapter, u32 *vers) 3356 { 3357 struct exprom_header { 3358 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3359 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3360 } *hdr; 3361 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3362 sizeof(u32))]; 3363 int ret; 3364 3365 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START, 3366 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3367 0); 3368 if (ret) 3369 return ret; 3370 3371 hdr = (struct exprom_header *)exprom_header_buf; 3372 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3373 return -ENOENT; 3374 3375 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3376 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3377 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3378 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3379 return 0; 3380 } 3381 3382 /** 3383 * t4_get_scfg_version - return the Serial Configuration version 3384 * @adapter: the adapter 3385 * @vers: where to place the version 3386 * 3387 * Reads the Serial Configuration Version via the Firmware interface 3388 * (thus this can only be called once we're ready to issue Firmware 3389 * commands). The format of the Serial Configuration version is 3390 * adapter specific. Returns 0 on success, an error on failure. 3391 * 3392 * Note that early versions of the Firmware didn't include the ability 3393 * to retrieve the Serial Configuration version, so we zero-out the 3394 * return-value parameter in that case to avoid leaving it with 3395 * garbage in it. 3396 * 3397 * Also note that the Firmware will return its cached copy of the Serial 3398 * Initialization Revision ID, not the actual Revision ID as written in 3399 * the Serial EEPROM. This is only an issue if a new VPD has been written 3400 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3401 * it's best to defer calling this routine till after a FW_RESET_CMD has 3402 * been issued if the Host Driver will be performing a full adapter 3403 * initialization. 3404 */ 3405 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3406 { 3407 u32 scfgrev_param; 3408 int ret; 3409 3410 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3411 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3412 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3413 1, &scfgrev_param, vers); 3414 if (ret) 3415 *vers = 0; 3416 return ret; 3417 } 3418 3419 /** 3420 * t4_get_vpd_version - return the VPD version 3421 * @adapter: the adapter 3422 * @vers: where to place the version 3423 * 3424 * Reads the VPD via the Firmware interface (thus this can only be called 3425 * once we're ready to issue Firmware commands). The format of the 3426 * VPD version is adapter specific. Returns 0 on success, an error on 3427 * failure. 3428 * 3429 * Note that early versions of the Firmware didn't include the ability 3430 * to retrieve the VPD version, so we zero-out the return-value parameter 3431 * in that case to avoid leaving it with garbage in it. 3432 * 3433 * Also note that the Firmware will return its cached copy of the VPD 3434 * Revision ID, not the actual Revision ID as written in the Serial 3435 * EEPROM. This is only an issue if a new VPD has been written and the 3436 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3437 * to defer calling this routine till after a FW_RESET_CMD has been issued 3438 * if the Host Driver will be performing a full adapter initialization. 3439 */ 3440 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3441 { 3442 u32 vpdrev_param; 3443 int ret; 3444 3445 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3446 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3447 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3448 1, &vpdrev_param, vers); 3449 if (ret) 3450 *vers = 0; 3451 return ret; 3452 } 3453 3454 /** 3455 * t4_get_version_info - extract various chip/firmware version information 3456 * @adapter: the adapter 3457 * 3458 * Reads various chip/firmware version numbers and stores them into the 3459 * adapter Adapter Parameters structure. If any of the efforts fails 3460 * the first failure will be returned, but all of the version numbers 3461 * will be read. 3462 */ 3463 int t4_get_version_info(struct adapter *adapter) 3464 { 3465 int ret = 0; 3466 3467 #define FIRST_RET(__getvinfo) \ 3468 do { \ 3469 int __ret = __getvinfo; \ 3470 if (__ret && !ret) \ 3471 ret = __ret; \ 3472 } while (0) 3473 3474 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3475 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3476 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3477 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3478 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3479 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3480 3481 #undef FIRST_RET 3482 3483 return ret; 3484 } 3485 3486 /** 3487 * t4_flash_erase_sectors - erase a range of flash sectors 3488 * @adapter: the adapter 3489 * @start: the first sector to erase 3490 * @end: the last sector to erase 3491 * 3492 * Erases the sectors in the given inclusive range. 3493 */ 3494 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3495 { 3496 int ret = 0; 3497 3498 if (end >= adapter->params.sf_nsec) 3499 return -EINVAL; 3500 3501 while (start <= end) { 3502 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3503 (ret = sf1_write(adapter, 4, 0, 1, 3504 SF_ERASE_SECTOR | (start << 8))) != 0 || 3505 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3506 CH_ERR(adapter, 3507 "erase of flash sector %d failed, error %d\n", 3508 start, ret); 3509 break; 3510 } 3511 start++; 3512 } 3513 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3514 return ret; 3515 } 3516 3517 /** 3518 * t4_flash_cfg_addr - return the address of the flash configuration file 3519 * @adapter: the adapter 3520 * 3521 * Return the address within the flash where the Firmware Configuration 3522 * File is stored, or an error if the device FLASH is too small to contain 3523 * a Firmware Configuration File. 3524 */ 3525 int t4_flash_cfg_addr(struct adapter *adapter) 3526 { 3527 /* 3528 * If the device FLASH isn't large enough to hold a Firmware 3529 * Configuration File, return an error. 3530 */ 3531 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3532 return -ENOSPC; 3533 3534 return FLASH_CFG_START; 3535 } 3536 3537 /* 3538 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3539 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3540 * and emit an error message for mismatched firmware to save our caller the 3541 * effort ... 3542 */ 3543 static int t4_fw_matches_chip(struct adapter *adap, 3544 const struct fw_hdr *hdr) 3545 { 3546 /* 3547 * The expression below will return FALSE for any unsupported adapter 3548 * which will keep us "honest" in the future ... 3549 */ 3550 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3551 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3552 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3553 return 1; 3554 3555 CH_ERR(adap, 3556 "FW image (%d) is not suitable for this adapter (%d)\n", 3557 hdr->chip, chip_id(adap)); 3558 return 0; 3559 } 3560 3561 /** 3562 * t4_load_fw - download firmware 3563 * @adap: the adapter 3564 * @fw_data: the firmware image to write 3565 * @size: image size 3566 * 3567 * Write the supplied firmware image to the card's serial flash. 3568 */ 3569 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3570 { 3571 u32 csum; 3572 int ret, addr; 3573 unsigned int i; 3574 u8 first_page[SF_PAGE_SIZE]; 3575 const u32 *p = (const u32 *)fw_data; 3576 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3577 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3578 unsigned int fw_start_sec; 3579 unsigned int fw_start; 3580 unsigned int fw_size; 3581 3582 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3583 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3584 fw_start = FLASH_FWBOOTSTRAP_START; 3585 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3586 } else { 3587 fw_start_sec = FLASH_FW_START_SEC; 3588 fw_start = FLASH_FW_START; 3589 fw_size = FLASH_FW_MAX_SIZE; 3590 } 3591 3592 if (!size) { 3593 CH_ERR(adap, "FW image has no data\n"); 3594 return -EINVAL; 3595 } 3596 if (size & 511) { 3597 CH_ERR(adap, 3598 "FW image size not multiple of 512 bytes\n"); 3599 return -EINVAL; 3600 } 3601 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3602 CH_ERR(adap, 3603 "FW image size differs from size in FW header\n"); 3604 return -EINVAL; 3605 } 3606 if (size > fw_size) { 3607 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3608 fw_size); 3609 return -EFBIG; 3610 } 3611 if (!t4_fw_matches_chip(adap, hdr)) 3612 return -EINVAL; 3613 3614 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3615 csum += be32_to_cpu(p[i]); 3616 3617 if (csum != 0xffffffff) { 3618 CH_ERR(adap, 3619 "corrupted firmware image, checksum %#x\n", csum); 3620 return -EINVAL; 3621 } 3622 3623 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3624 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3625 if (ret) 3626 goto out; 3627 3628 /* 3629 * We write the correct version at the end so the driver can see a bad 3630 * version if the FW write fails. Start by writing a copy of the 3631 * first page with a bad version. 3632 */ 3633 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3634 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3635 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3636 if (ret) 3637 goto out; 3638 3639 addr = fw_start; 3640 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3641 addr += SF_PAGE_SIZE; 3642 fw_data += SF_PAGE_SIZE; 3643 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3644 if (ret) 3645 goto out; 3646 } 3647 3648 ret = t4_write_flash(adap, 3649 fw_start + offsetof(struct fw_hdr, fw_ver), 3650 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3651 out: 3652 if (ret) 3653 CH_ERR(adap, "firmware download failed, error %d\n", 3654 ret); 3655 return ret; 3656 } 3657 3658 /** 3659 * t4_fwcache - firmware cache operation 3660 * @adap: the adapter 3661 * @op : the operation (flush or flush and invalidate) 3662 */ 3663 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3664 { 3665 struct fw_params_cmd c; 3666 3667 memset(&c, 0, sizeof(c)); 3668 c.op_to_vfn = 3669 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3670 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3671 V_FW_PARAMS_CMD_PFN(adap->pf) | 3672 V_FW_PARAMS_CMD_VFN(0)); 3673 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3674 c.param[0].mnem = 3675 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3676 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3677 c.param[0].val = (__force __be32)op; 3678 3679 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3680 } 3681 3682 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3683 unsigned int *pif_req_wrptr, 3684 unsigned int *pif_rsp_wrptr) 3685 { 3686 int i, j; 3687 u32 cfg, val, req, rsp; 3688 3689 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3690 if (cfg & F_LADBGEN) 3691 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3692 3693 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3694 req = G_POLADBGWRPTR(val); 3695 rsp = G_PILADBGWRPTR(val); 3696 if (pif_req_wrptr) 3697 *pif_req_wrptr = req; 3698 if (pif_rsp_wrptr) 3699 *pif_rsp_wrptr = rsp; 3700 3701 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3702 for (j = 0; j < 6; j++) { 3703 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3704 V_PILADBGRDPTR(rsp)); 3705 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3706 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3707 req++; 3708 rsp++; 3709 } 3710 req = (req + 2) & M_POLADBGRDPTR; 3711 rsp = (rsp + 2) & M_PILADBGRDPTR; 3712 } 3713 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3714 } 3715 3716 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3717 { 3718 u32 cfg; 3719 int i, j, idx; 3720 3721 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3722 if (cfg & F_LADBGEN) 3723 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3724 3725 for (i = 0; i < CIM_MALA_SIZE; i++) { 3726 for (j = 0; j < 5; j++) { 3727 idx = 8 * i + j; 3728 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3729 V_PILADBGRDPTR(idx)); 3730 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3731 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3732 } 3733 } 3734 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3735 } 3736 3737 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3738 { 3739 unsigned int i, j; 3740 3741 for (i = 0; i < 8; i++) { 3742 u32 *p = la_buf + i; 3743 3744 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3745 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3746 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3747 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3748 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3749 } 3750 } 3751 3752 /** 3753 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3754 * @caps16: a 16-bit Port Capabilities value 3755 * 3756 * Returns the equivalent 32-bit Port Capabilities value. 3757 */ 3758 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3759 { 3760 uint32_t caps32 = 0; 3761 3762 #define CAP16_TO_CAP32(__cap) \ 3763 do { \ 3764 if (caps16 & FW_PORT_CAP_##__cap) \ 3765 caps32 |= FW_PORT_CAP32_##__cap; \ 3766 } while (0) 3767 3768 CAP16_TO_CAP32(SPEED_100M); 3769 CAP16_TO_CAP32(SPEED_1G); 3770 CAP16_TO_CAP32(SPEED_25G); 3771 CAP16_TO_CAP32(SPEED_10G); 3772 CAP16_TO_CAP32(SPEED_40G); 3773 CAP16_TO_CAP32(SPEED_100G); 3774 CAP16_TO_CAP32(FC_RX); 3775 CAP16_TO_CAP32(FC_TX); 3776 CAP16_TO_CAP32(ANEG); 3777 CAP16_TO_CAP32(FORCE_PAUSE); 3778 CAP16_TO_CAP32(MDIAUTO); 3779 CAP16_TO_CAP32(MDISTRAIGHT); 3780 CAP16_TO_CAP32(FEC_RS); 3781 CAP16_TO_CAP32(FEC_BASER_RS); 3782 CAP16_TO_CAP32(802_3_PAUSE); 3783 CAP16_TO_CAP32(802_3_ASM_DIR); 3784 3785 #undef CAP16_TO_CAP32 3786 3787 return caps32; 3788 } 3789 3790 /** 3791 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3792 * @caps32: a 32-bit Port Capabilities value 3793 * 3794 * Returns the equivalent 16-bit Port Capabilities value. Note that 3795 * not all 32-bit Port Capabilities can be represented in the 16-bit 3796 * Port Capabilities and some fields/values may not make it. 3797 */ 3798 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3799 { 3800 uint16_t caps16 = 0; 3801 3802 #define CAP32_TO_CAP16(__cap) \ 3803 do { \ 3804 if (caps32 & FW_PORT_CAP32_##__cap) \ 3805 caps16 |= FW_PORT_CAP_##__cap; \ 3806 } while (0) 3807 3808 CAP32_TO_CAP16(SPEED_100M); 3809 CAP32_TO_CAP16(SPEED_1G); 3810 CAP32_TO_CAP16(SPEED_10G); 3811 CAP32_TO_CAP16(SPEED_25G); 3812 CAP32_TO_CAP16(SPEED_40G); 3813 CAP32_TO_CAP16(SPEED_100G); 3814 CAP32_TO_CAP16(FC_RX); 3815 CAP32_TO_CAP16(FC_TX); 3816 CAP32_TO_CAP16(802_3_PAUSE); 3817 CAP32_TO_CAP16(802_3_ASM_DIR); 3818 CAP32_TO_CAP16(ANEG); 3819 CAP32_TO_CAP16(FORCE_PAUSE); 3820 CAP32_TO_CAP16(MDIAUTO); 3821 CAP32_TO_CAP16(MDISTRAIGHT); 3822 CAP32_TO_CAP16(FEC_RS); 3823 CAP32_TO_CAP16(FEC_BASER_RS); 3824 3825 #undef CAP32_TO_CAP16 3826 3827 return caps16; 3828 } 3829 3830 static bool 3831 is_bt(struct port_info *pi) 3832 { 3833 3834 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 3835 pi->port_type == FW_PORT_TYPE_BT_XFI || 3836 pi->port_type == FW_PORT_TYPE_BT_XAUI); 3837 } 3838 3839 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none) 3840 { 3841 int8_t fec = 0; 3842 3843 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) 3844 return (unset_means_none ? FEC_NONE : 0); 3845 3846 if (caps & FW_PORT_CAP32_FEC_RS) 3847 fec |= FEC_RS; 3848 if (caps & FW_PORT_CAP32_FEC_BASER_RS) 3849 fec |= FEC_BASER_RS; 3850 if (caps & FW_PORT_CAP32_FEC_NO_FEC) 3851 fec |= FEC_NONE; 3852 3853 return (fec); 3854 } 3855 3856 /* 3857 * Note that 0 is not translated to NO_FEC. 3858 */ 3859 static uint32_t fec_to_fwcap(int8_t fec) 3860 { 3861 uint32_t caps = 0; 3862 3863 /* Only real FECs allowed. */ 3864 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); 3865 3866 if (fec & FEC_RS) 3867 caps |= FW_PORT_CAP32_FEC_RS; 3868 if (fec & FEC_BASER_RS) 3869 caps |= FW_PORT_CAP32_FEC_BASER_RS; 3870 if (fec & FEC_NONE) 3871 caps |= FW_PORT_CAP32_FEC_NO_FEC; 3872 3873 return (caps); 3874 } 3875 3876 /** 3877 * t4_link_l1cfg - apply link configuration to MAC/PHY 3878 * @phy: the PHY to setup 3879 * @mac: the MAC to setup 3880 * @lc: the requested link configuration 3881 * 3882 * Set up a port's MAC and PHY according to a desired link configuration. 3883 * - If the PHY can auto-negotiate first decide what to advertise, then 3884 * enable/disable auto-negotiation as desired, and reset. 3885 * - If the PHY does not auto-negotiate just reset it. 3886 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3887 * otherwise do it later based on the outcome of auto-negotiation. 3888 */ 3889 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3890 struct link_config *lc) 3891 { 3892 struct fw_port_cmd c; 3893 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3894 unsigned int aneg, fc, fec, speed, rcap; 3895 3896 fc = 0; 3897 if (lc->requested_fc & PAUSE_RX) 3898 fc |= FW_PORT_CAP32_FC_RX; 3899 if (lc->requested_fc & PAUSE_TX) 3900 fc |= FW_PORT_CAP32_FC_TX; 3901 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3902 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3903 3904 if (lc->requested_aneg == AUTONEG_DISABLE) 3905 aneg = 0; 3906 else if (lc->requested_aneg == AUTONEG_ENABLE) 3907 aneg = FW_PORT_CAP32_ANEG; 3908 else 3909 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3910 3911 if (aneg) { 3912 speed = lc->pcaps & 3913 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3914 } else if (lc->requested_speed != 0) 3915 speed = speed_to_fwcap(lc->requested_speed); 3916 else 3917 speed = fwcap_top_speed(lc->pcaps); 3918 3919 fec = 0; 3920 if (fec_supported(speed)) { 3921 if (lc->requested_fec == FEC_AUTO) { 3922 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) { 3923 if (speed & FW_PORT_CAP32_SPEED_100G) { 3924 fec |= FW_PORT_CAP32_FEC_RS; 3925 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3926 } else { 3927 fec |= FW_PORT_CAP32_FEC_RS; 3928 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3929 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3930 } 3931 } else { 3932 /* Set only 1b with old firmwares. */ 3933 fec |= fec_to_fwcap(lc->fec_hint); 3934 } 3935 } else { 3936 fec |= fec_to_fwcap(lc->requested_fec & 3937 M_FW_PORT_CAP32_FEC); 3938 if (lc->requested_fec & FEC_MODULE) 3939 fec |= fec_to_fwcap(lc->fec_hint); 3940 } 3941 3942 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 3943 fec |= FW_PORT_CAP32_FORCE_FEC; 3944 else if (fec == FW_PORT_CAP32_FEC_NO_FEC) 3945 fec = 0; 3946 } 3947 3948 /* Force AN on for BT cards. */ 3949 if (is_bt(adap->port[adap->chan_map[port]])) 3950 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3951 3952 rcap = aneg | speed | fc | fec; 3953 if ((rcap | lc->pcaps) != lc->pcaps) { 3954 #ifdef INVARIANTS 3955 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, 3956 lc->pcaps, rcap & (rcap ^ lc->pcaps)); 3957 #endif 3958 rcap &= lc->pcaps; 3959 } 3960 rcap |= mdi; 3961 3962 memset(&c, 0, sizeof(c)); 3963 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3964 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3965 V_FW_PORT_CMD_PORTID(port)); 3966 if (adap->params.port_caps32) { 3967 c.action_to_len16 = 3968 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3969 FW_LEN16(c)); 3970 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3971 } else { 3972 c.action_to_len16 = 3973 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3974 FW_LEN16(c)); 3975 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3976 } 3977 3978 lc->requested_caps = rcap; 3979 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3980 } 3981 3982 /** 3983 * t4_restart_aneg - restart autonegotiation 3984 * @adap: the adapter 3985 * @mbox: mbox to use for the FW command 3986 * @port: the port id 3987 * 3988 * Restarts autonegotiation for the selected port. 3989 */ 3990 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3991 { 3992 struct fw_port_cmd c; 3993 3994 memset(&c, 0, sizeof(c)); 3995 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3996 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3997 V_FW_PORT_CMD_PORTID(port)); 3998 c.action_to_len16 = 3999 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4000 FW_LEN16(c)); 4001 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 4002 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4003 } 4004 4005 struct intr_details { 4006 u32 mask; 4007 const char *msg; 4008 }; 4009 4010 struct intr_action { 4011 u32 mask; 4012 int arg; 4013 bool (*action)(struct adapter *, int, bool); 4014 }; 4015 4016 #define NONFATAL_IF_DISABLED 1 4017 struct intr_info { 4018 const char *name; /* name of the INT_CAUSE register */ 4019 int cause_reg; /* INT_CAUSE register */ 4020 int enable_reg; /* INT_ENABLE register */ 4021 u32 fatal; /* bits that are fatal */ 4022 int flags; /* hints */ 4023 const struct intr_details *details; 4024 const struct intr_action *actions; 4025 }; 4026 4027 static inline char 4028 intr_alert_char(u32 cause, u32 enable, u32 fatal) 4029 { 4030 4031 if (cause & fatal) 4032 return ('!'); 4033 if (cause & enable) 4034 return ('*'); 4035 return ('-'); 4036 } 4037 4038 static void 4039 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 4040 { 4041 u32 enable, fatal, leftover; 4042 const struct intr_details *details; 4043 char alert; 4044 4045 enable = t4_read_reg(adap, ii->enable_reg); 4046 if (ii->flags & NONFATAL_IF_DISABLED) 4047 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 4048 else 4049 fatal = ii->fatal; 4050 alert = intr_alert_char(cause, enable, fatal); 4051 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 4052 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4053 4054 leftover = cause; 4055 for (details = ii->details; details && details->mask != 0; details++) { 4056 u32 msgbits = details->mask & cause; 4057 if (msgbits == 0) 4058 continue; 4059 alert = intr_alert_char(msgbits, enable, ii->fatal); 4060 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4061 details->msg); 4062 leftover &= ~msgbits; 4063 } 4064 if (leftover != 0 && leftover != cause) 4065 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4066 } 4067 4068 /* 4069 * Returns true for fatal error. 4070 */ 4071 static bool 4072 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4073 u32 additional_cause, bool verbose) 4074 { 4075 u32 cause, fatal; 4076 bool rc; 4077 const struct intr_action *action; 4078 4079 /* 4080 * Read and display cause. Note that the top level PL_INT_CAUSE is a 4081 * bit special and we need to completely ignore the bits that are not in 4082 * PL_INT_ENABLE. 4083 */ 4084 cause = t4_read_reg(adap, ii->cause_reg); 4085 if (ii->cause_reg == A_PL_INT_CAUSE) 4086 cause &= t4_read_reg(adap, ii->enable_reg); 4087 if (verbose || cause != 0) 4088 t4_show_intr_info(adap, ii, cause); 4089 fatal = cause & ii->fatal; 4090 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4091 fatal &= t4_read_reg(adap, ii->enable_reg); 4092 cause |= additional_cause; 4093 if (cause == 0) 4094 return (false); 4095 4096 rc = fatal != 0; 4097 for (action = ii->actions; action && action->mask != 0; action++) { 4098 if (!(action->mask & cause)) 4099 continue; 4100 rc |= (action->action)(adap, action->arg, verbose); 4101 } 4102 4103 /* clear */ 4104 t4_write_reg(adap, ii->cause_reg, cause); 4105 (void)t4_read_reg(adap, ii->cause_reg); 4106 4107 return (rc); 4108 } 4109 4110 /* 4111 * Interrupt handler for the PCIE module. 4112 */ 4113 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4114 { 4115 static const struct intr_details sysbus_intr_details[] = { 4116 { F_RNPP, "RXNP array parity error" }, 4117 { F_RPCP, "RXPC array parity error" }, 4118 { F_RCIP, "RXCIF array parity error" }, 4119 { F_RCCP, "Rx completions control array parity error" }, 4120 { F_RFTP, "RXFT array parity error" }, 4121 { 0 } 4122 }; 4123 static const struct intr_info sysbus_intr_info = { 4124 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4125 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4126 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4127 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4128 .flags = 0, 4129 .details = sysbus_intr_details, 4130 .actions = NULL, 4131 }; 4132 static const struct intr_details pcie_port_intr_details[] = { 4133 { F_TPCP, "TXPC array parity error" }, 4134 { F_TNPP, "TXNP array parity error" }, 4135 { F_TFTP, "TXFT array parity error" }, 4136 { F_TCAP, "TXCA array parity error" }, 4137 { F_TCIP, "TXCIF array parity error" }, 4138 { F_RCAP, "RXCA array parity error" }, 4139 { F_OTDD, "outbound request TLP discarded" }, 4140 { F_RDPE, "Rx data parity error" }, 4141 { F_TDUE, "Tx uncorrectable data error" }, 4142 { 0 } 4143 }; 4144 static const struct intr_info pcie_port_intr_info = { 4145 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4146 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4147 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4148 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4149 F_OTDD | F_RDPE | F_TDUE, 4150 .flags = 0, 4151 .details = pcie_port_intr_details, 4152 .actions = NULL, 4153 }; 4154 static const struct intr_details pcie_intr_details[] = { 4155 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4156 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4157 { F_MSIDATAPERR, "MSI data parity error" }, 4158 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4159 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4160 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4161 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4162 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4163 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4164 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4165 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4166 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4167 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4168 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4169 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4170 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4171 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4172 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4173 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4174 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4175 { F_FIDPERR, "PCIe FID parity error" }, 4176 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4177 { F_MATAGPERR, "PCIe MA tag parity error" }, 4178 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4179 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4180 { F_RXWRPERR, "PCIe Rx write parity error" }, 4181 { F_RPLPERR, "PCIe replay buffer parity error" }, 4182 { F_PCIESINT, "PCIe core secondary fault" }, 4183 { F_PCIEPINT, "PCIe core primary fault" }, 4184 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4185 { 0 } 4186 }; 4187 static const struct intr_details t5_pcie_intr_details[] = { 4188 { F_IPGRPPERR, "Parity errors observed by IP" }, 4189 { F_NONFATALERR, "PCIe non-fatal error" }, 4190 { F_READRSPERR, "Outbound read error" }, 4191 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4192 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4193 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4194 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4195 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4196 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4197 { F_MAGRPPERR, "MA group FIFO parity error" }, 4198 { F_VFIDPERR, "VFID SRAM parity error" }, 4199 { F_FIDPERR, "FID SRAM parity error" }, 4200 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4201 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4202 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4203 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4204 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4205 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4206 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4207 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4208 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4209 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4210 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4211 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4212 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4213 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4214 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4215 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4216 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4217 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4218 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4219 { 0 } 4220 }; 4221 struct intr_info pcie_intr_info = { 4222 .name = "PCIE_INT_CAUSE", 4223 .cause_reg = A_PCIE_INT_CAUSE, 4224 .enable_reg = A_PCIE_INT_ENABLE, 4225 .fatal = 0xffffffff, 4226 .flags = NONFATAL_IF_DISABLED, 4227 .details = NULL, 4228 .actions = NULL, 4229 }; 4230 bool fatal = false; 4231 4232 if (is_t4(adap)) { 4233 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4234 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4235 4236 pcie_intr_info.details = pcie_intr_details; 4237 } else { 4238 pcie_intr_info.details = t5_pcie_intr_details; 4239 } 4240 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4241 4242 return (fatal); 4243 } 4244 4245 /* 4246 * TP interrupt handler. 4247 */ 4248 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4249 { 4250 static const struct intr_details tp_intr_details[] = { 4251 { 0x3fffffff, "TP parity error" }, 4252 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4253 { 0 } 4254 }; 4255 static const struct intr_info tp_intr_info = { 4256 .name = "TP_INT_CAUSE", 4257 .cause_reg = A_TP_INT_CAUSE, 4258 .enable_reg = A_TP_INT_ENABLE, 4259 .fatal = 0x7fffffff, 4260 .flags = NONFATAL_IF_DISABLED, 4261 .details = tp_intr_details, 4262 .actions = NULL, 4263 }; 4264 4265 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4266 } 4267 4268 /* 4269 * SGE interrupt handler. 4270 */ 4271 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4272 { 4273 static const struct intr_info sge_int1_info = { 4274 .name = "SGE_INT_CAUSE1", 4275 .cause_reg = A_SGE_INT_CAUSE1, 4276 .enable_reg = A_SGE_INT_ENABLE1, 4277 .fatal = 0xffffffff, 4278 .flags = NONFATAL_IF_DISABLED, 4279 .details = NULL, 4280 .actions = NULL, 4281 }; 4282 static const struct intr_info sge_int2_info = { 4283 .name = "SGE_INT_CAUSE2", 4284 .cause_reg = A_SGE_INT_CAUSE2, 4285 .enable_reg = A_SGE_INT_ENABLE2, 4286 .fatal = 0xffffffff, 4287 .flags = NONFATAL_IF_DISABLED, 4288 .details = NULL, 4289 .actions = NULL, 4290 }; 4291 static const struct intr_details sge_int3_details[] = { 4292 { F_ERR_FLM_DBP, 4293 "DBP pointer delivery for invalid context or QID" }, 4294 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4295 "Invalid QID or header request by IDMA" }, 4296 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4297 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4298 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4299 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4300 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4301 { F_ERR_TIMER_ABOVE_MAX_QID, 4302 "SGE GTS with timer 0-5 for IQID > 1023" }, 4303 { F_ERR_CPL_EXCEED_IQE_SIZE, 4304 "SGE received CPL exceeding IQE size" }, 4305 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4306 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4307 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4308 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4309 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4310 "SGE IQID > 1023 received CPL for FL" }, 4311 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4312 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4313 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4314 { F_ERR_ING_CTXT_PRIO, 4315 "Ingress context manager priority user error" }, 4316 { F_ERR_EGR_CTXT_PRIO, 4317 "Egress context manager priority user error" }, 4318 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4319 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4320 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4321 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4322 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4323 { 0x0000000f, "SGE context access for invalid queue" }, 4324 { 0 } 4325 }; 4326 static const struct intr_details t6_sge_int3_details[] = { 4327 { F_ERR_FLM_DBP, 4328 "DBP pointer delivery for invalid context or QID" }, 4329 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4330 "Invalid QID or header request by IDMA" }, 4331 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4332 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4333 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4334 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4335 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4336 { F_ERR_TIMER_ABOVE_MAX_QID, 4337 "SGE GTS with timer 0-5 for IQID > 1023" }, 4338 { F_ERR_CPL_EXCEED_IQE_SIZE, 4339 "SGE received CPL exceeding IQE size" }, 4340 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4341 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4342 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4343 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4344 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4345 "SGE IQID > 1023 received CPL for FL" }, 4346 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4347 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4348 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4349 { F_ERR_ING_CTXT_PRIO, 4350 "Ingress context manager priority user error" }, 4351 { F_ERR_EGR_CTXT_PRIO, 4352 "Egress context manager priority user error" }, 4353 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4354 { F_FATAL_WRE_LEN, 4355 "SGE WRE packet less than advertized length" }, 4356 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4357 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4358 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4359 { 0x0000000f, "SGE context access for invalid queue" }, 4360 { 0 } 4361 }; 4362 struct intr_info sge_int3_info = { 4363 .name = "SGE_INT_CAUSE3", 4364 .cause_reg = A_SGE_INT_CAUSE3, 4365 .enable_reg = A_SGE_INT_ENABLE3, 4366 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4367 .flags = 0, 4368 .details = NULL, 4369 .actions = NULL, 4370 }; 4371 static const struct intr_info sge_int4_info = { 4372 .name = "SGE_INT_CAUSE4", 4373 .cause_reg = A_SGE_INT_CAUSE4, 4374 .enable_reg = A_SGE_INT_ENABLE4, 4375 .fatal = 0, 4376 .flags = 0, 4377 .details = NULL, 4378 .actions = NULL, 4379 }; 4380 static const struct intr_info sge_int5_info = { 4381 .name = "SGE_INT_CAUSE5", 4382 .cause_reg = A_SGE_INT_CAUSE5, 4383 .enable_reg = A_SGE_INT_ENABLE5, 4384 .fatal = 0xffffffff, 4385 .flags = NONFATAL_IF_DISABLED, 4386 .details = NULL, 4387 .actions = NULL, 4388 }; 4389 static const struct intr_info sge_int6_info = { 4390 .name = "SGE_INT_CAUSE6", 4391 .cause_reg = A_SGE_INT_CAUSE6, 4392 .enable_reg = A_SGE_INT_ENABLE6, 4393 .fatal = 0, 4394 .flags = 0, 4395 .details = NULL, 4396 .actions = NULL, 4397 }; 4398 4399 bool fatal; 4400 u32 v; 4401 4402 if (chip_id(adap) <= CHELSIO_T5) { 4403 sge_int3_info.details = sge_int3_details; 4404 } else { 4405 sge_int3_info.details = t6_sge_int3_details; 4406 } 4407 4408 fatal = false; 4409 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4410 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4411 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4412 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4413 if (chip_id(adap) >= CHELSIO_T5) 4414 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4415 if (chip_id(adap) >= CHELSIO_T6) 4416 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4417 4418 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4419 if (v & F_ERROR_QID_VALID) { 4420 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4421 if (v & F_UNCAPTURED_ERROR) 4422 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4423 t4_write_reg(adap, A_SGE_ERROR_STATS, 4424 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4425 } 4426 4427 return (fatal); 4428 } 4429 4430 /* 4431 * CIM interrupt handler. 4432 */ 4433 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4434 { 4435 static const struct intr_action cim_host_intr_actions[] = { 4436 { F_TIMER0INT, 0, t4_os_dump_cimla }, 4437 { 0 }, 4438 }; 4439 static const struct intr_details cim_host_intr_details[] = { 4440 /* T6+ */ 4441 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4442 4443 /* T5+ */ 4444 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4445 { F_PLCIM_MSTRSPDATAPARERR, 4446 "PL2CIM master response data parity error" }, 4447 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4448 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4449 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4450 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4451 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4452 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4453 4454 /* T4+ */ 4455 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4456 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4457 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4458 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4459 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4460 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4461 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4462 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4463 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4464 "CIM IBQ PCIe/SGE_HI parity error" }, 4465 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4466 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4467 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4468 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4469 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4470 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4471 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4472 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4473 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4474 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4475 { 0} 4476 }; 4477 static const struct intr_info cim_host_intr_info = { 4478 .name = "CIM_HOST_INT_CAUSE", 4479 .cause_reg = A_CIM_HOST_INT_CAUSE, 4480 .enable_reg = A_CIM_HOST_INT_ENABLE, 4481 .fatal = 0x007fffe6, 4482 .flags = NONFATAL_IF_DISABLED, 4483 .details = cim_host_intr_details, 4484 .actions = cim_host_intr_actions, 4485 }; 4486 static const struct intr_details cim_host_upacc_intr_details[] = { 4487 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4488 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4489 { F_TIMEOUTINT, "CIM PIF timeout" }, 4490 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4491 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4492 { F_BLKWRPLINT, "CIM block write to PL space" }, 4493 { F_BLKRDPLINT, "CIM block read from PL space" }, 4494 { F_SGLWRPLINT, 4495 "CIM single write to PL space with illegal BEs" }, 4496 { F_SGLRDPLINT, 4497 "CIM single read from PL space with illegal BEs" }, 4498 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4499 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4500 { F_SGLWRCTLINT, 4501 "CIM single write to CTL space with illegal BEs" }, 4502 { F_SGLRDCTLINT, 4503 "CIM single read from CTL space with illegal BEs" }, 4504 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4505 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4506 { F_SGLWREEPROMINT, 4507 "CIM single write to EEPROM space with illegal BEs" }, 4508 { F_SGLRDEEPROMINT, 4509 "CIM single read from EEPROM space with illegal BEs" }, 4510 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4511 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4512 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4513 { F_SGLRDFLASHINT, 4514 "CIM single read from flash space with illegal BEs" }, 4515 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4516 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4517 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4518 { F_SGLRDBOOTINT, 4519 "CIM single read from boot space with illegal BEs" }, 4520 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4521 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4522 { F_ILLRDINT, "CIM illegal read" }, 4523 { F_ILLWRINT, "CIM illegal write" }, 4524 { F_ILLTRANSINT, "CIM illegal transaction" }, 4525 { F_RSVDSPACEINT, "CIM reserved space access" }, 4526 {0} 4527 }; 4528 static const struct intr_info cim_host_upacc_intr_info = { 4529 .name = "CIM_HOST_UPACC_INT_CAUSE", 4530 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4531 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4532 .fatal = 0x3fffeeff, 4533 .flags = NONFATAL_IF_DISABLED, 4534 .details = cim_host_upacc_intr_details, 4535 .actions = NULL, 4536 }; 4537 static const struct intr_info cim_pf_host_intr_info = { 4538 .name = "CIM_PF_HOST_INT_CAUSE", 4539 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4540 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4541 .fatal = 0, 4542 .flags = 0, 4543 .details = NULL, 4544 .actions = NULL, 4545 }; 4546 u32 val, fw_err; 4547 bool fatal; 4548 4549 fw_err = t4_read_reg(adap, A_PCIE_FW); 4550 if (fw_err & F_PCIE_FW_ERR) 4551 t4_report_fw_error(adap); 4552 4553 /* 4554 * When the Firmware detects an internal error which normally wouldn't 4555 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4556 * to make sure the Host sees the Firmware Crash. So if we have a 4557 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4558 * interrupt. 4559 */ 4560 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4561 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4562 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4563 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4564 } 4565 4566 fatal = false; 4567 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4568 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4569 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4570 4571 return (fatal); 4572 } 4573 4574 /* 4575 * ULP RX interrupt handler. 4576 */ 4577 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4578 { 4579 static const struct intr_details ulprx_intr_details[] = { 4580 /* T5+ */ 4581 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4582 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4583 4584 /* T4+ */ 4585 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4586 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4587 { 0x007fffff, "ULPRX parity error" }, 4588 { 0 } 4589 }; 4590 static const struct intr_info ulprx_intr_info = { 4591 .name = "ULP_RX_INT_CAUSE", 4592 .cause_reg = A_ULP_RX_INT_CAUSE, 4593 .enable_reg = A_ULP_RX_INT_ENABLE, 4594 .fatal = 0x07ffffff, 4595 .flags = NONFATAL_IF_DISABLED, 4596 .details = ulprx_intr_details, 4597 .actions = NULL, 4598 }; 4599 static const struct intr_info ulprx_intr2_info = { 4600 .name = "ULP_RX_INT_CAUSE_2", 4601 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4602 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4603 .fatal = 0, 4604 .flags = 0, 4605 .details = NULL, 4606 .actions = NULL, 4607 }; 4608 bool fatal = false; 4609 4610 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4611 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4612 4613 return (fatal); 4614 } 4615 4616 /* 4617 * ULP TX interrupt handler. 4618 */ 4619 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4620 { 4621 static const struct intr_details ulptx_intr_details[] = { 4622 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4623 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4624 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4625 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4626 { 0x0fffffff, "ULPTX parity error" }, 4627 { 0 } 4628 }; 4629 static const struct intr_info ulptx_intr_info = { 4630 .name = "ULP_TX_INT_CAUSE", 4631 .cause_reg = A_ULP_TX_INT_CAUSE, 4632 .enable_reg = A_ULP_TX_INT_ENABLE, 4633 .fatal = 0x0fffffff, 4634 .flags = NONFATAL_IF_DISABLED, 4635 .details = ulptx_intr_details, 4636 .actions = NULL, 4637 }; 4638 static const struct intr_info ulptx_intr2_info = { 4639 .name = "ULP_TX_INT_CAUSE_2", 4640 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4641 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4642 .fatal = 0xf0, 4643 .flags = NONFATAL_IF_DISABLED, 4644 .details = NULL, 4645 .actions = NULL, 4646 }; 4647 bool fatal = false; 4648 4649 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4650 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4651 4652 return (fatal); 4653 } 4654 4655 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4656 { 4657 int i; 4658 u32 data[17]; 4659 4660 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4661 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4662 for (i = 0; i < ARRAY_SIZE(data); i++) { 4663 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4664 A_PM_TX_DBG_STAT0 + i, data[i]); 4665 } 4666 4667 return (false); 4668 } 4669 4670 /* 4671 * PM TX interrupt handler. 4672 */ 4673 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4674 { 4675 static const struct intr_action pmtx_intr_actions[] = { 4676 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4677 { 0 }, 4678 }; 4679 static const struct intr_details pmtx_intr_details[] = { 4680 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4681 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4682 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4683 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4684 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4685 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4686 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4687 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4688 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4689 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4690 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4691 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4692 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4693 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4694 { 0 } 4695 }; 4696 static const struct intr_info pmtx_intr_info = { 4697 .name = "PM_TX_INT_CAUSE", 4698 .cause_reg = A_PM_TX_INT_CAUSE, 4699 .enable_reg = A_PM_TX_INT_ENABLE, 4700 .fatal = 0xffffffff, 4701 .flags = 0, 4702 .details = pmtx_intr_details, 4703 .actions = pmtx_intr_actions, 4704 }; 4705 4706 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4707 } 4708 4709 /* 4710 * PM RX interrupt handler. 4711 */ 4712 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4713 { 4714 static const struct intr_details pmrx_intr_details[] = { 4715 /* T6+ */ 4716 { 0x18000000, "PMRX ospi overflow" }, 4717 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4718 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4719 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4720 { F_SDC_ERR, "PMRX SDC error" }, 4721 4722 /* T4+ */ 4723 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4724 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4725 { 0x0003c000, "PMRX iespi Rx framing error" }, 4726 { 0x00003c00, "PMRX iespi Tx framing error" }, 4727 { 0x00000300, "PMRX ocspi Rx framing error" }, 4728 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4729 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4730 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4731 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4732 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4733 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4734 { 0 } 4735 }; 4736 static const struct intr_info pmrx_intr_info = { 4737 .name = "PM_RX_INT_CAUSE", 4738 .cause_reg = A_PM_RX_INT_CAUSE, 4739 .enable_reg = A_PM_RX_INT_ENABLE, 4740 .fatal = 0x1fffffff, 4741 .flags = NONFATAL_IF_DISABLED, 4742 .details = pmrx_intr_details, 4743 .actions = NULL, 4744 }; 4745 4746 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4747 } 4748 4749 /* 4750 * CPL switch interrupt handler. 4751 */ 4752 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4753 { 4754 static const struct intr_details cplsw_intr_details[] = { 4755 /* T5+ */ 4756 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4757 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4758 4759 /* T4+ */ 4760 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4761 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4762 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4763 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4764 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4765 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4766 { 0 } 4767 }; 4768 static const struct intr_info cplsw_intr_info = { 4769 .name = "CPL_INTR_CAUSE", 4770 .cause_reg = A_CPL_INTR_CAUSE, 4771 .enable_reg = A_CPL_INTR_ENABLE, 4772 .fatal = 0xff, 4773 .flags = NONFATAL_IF_DISABLED, 4774 .details = cplsw_intr_details, 4775 .actions = NULL, 4776 }; 4777 4778 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4779 } 4780 4781 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4782 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4783 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4784 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4785 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4786 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4787 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4788 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4789 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4790 4791 /* 4792 * LE interrupt handler. 4793 */ 4794 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4795 { 4796 static const struct intr_details le_intr_details[] = { 4797 { F_REQQPARERR, "LE request queue parity error" }, 4798 { F_UNKNOWNCMD, "LE unknown command" }, 4799 { F_ACTRGNFULL, "LE active region full" }, 4800 { F_PARITYERR, "LE parity error" }, 4801 { F_LIPMISS, "LE LIP miss" }, 4802 { F_LIP0, "LE 0 LIP error" }, 4803 { 0 } 4804 }; 4805 static const struct intr_details t6_le_intr_details[] = { 4806 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4807 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4808 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4809 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4810 { F_TOTCNTERR, "LE total active < TCAM count" }, 4811 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4812 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4813 { F_T6_ACTRGNFULL, "LE active region full" }, 4814 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4815 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4816 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4817 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4818 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4819 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4820 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4821 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4822 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4823 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4824 { 0 } 4825 }; 4826 struct intr_info le_intr_info = { 4827 .name = "LE_DB_INT_CAUSE", 4828 .cause_reg = A_LE_DB_INT_CAUSE, 4829 .enable_reg = A_LE_DB_INT_ENABLE, 4830 .fatal = 0, 4831 .flags = NONFATAL_IF_DISABLED, 4832 .details = NULL, 4833 .actions = NULL, 4834 }; 4835 4836 if (chip_id(adap) <= CHELSIO_T5) { 4837 le_intr_info.details = le_intr_details; 4838 le_intr_info.fatal = T5_LE_FATAL_MASK; 4839 } else { 4840 le_intr_info.details = t6_le_intr_details; 4841 le_intr_info.fatal = T6_LE_FATAL_MASK; 4842 } 4843 4844 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4845 } 4846 4847 /* 4848 * MPS interrupt handler. 4849 */ 4850 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4851 { 4852 static const struct intr_details mps_rx_perr_intr_details[] = { 4853 { 0xffffffff, "MPS Rx parity error" }, 4854 { 0 } 4855 }; 4856 static const struct intr_info mps_rx_perr_intr_info = { 4857 .name = "MPS_RX_PERR_INT_CAUSE", 4858 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4859 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4860 .fatal = 0xffffffff, 4861 .flags = NONFATAL_IF_DISABLED, 4862 .details = mps_rx_perr_intr_details, 4863 .actions = NULL, 4864 }; 4865 static const struct intr_details mps_tx_intr_details[] = { 4866 { F_PORTERR, "MPS Tx destination port is disabled" }, 4867 { F_FRMERR, "MPS Tx framing error" }, 4868 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4869 { F_BUBBLE, "MPS Tx underflow" }, 4870 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4871 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4872 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4873 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4874 { 0 } 4875 }; 4876 static const struct intr_info mps_tx_intr_info = { 4877 .name = "MPS_TX_INT_CAUSE", 4878 .cause_reg = A_MPS_TX_INT_CAUSE, 4879 .enable_reg = A_MPS_TX_INT_ENABLE, 4880 .fatal = 0x1ffff, 4881 .flags = NONFATAL_IF_DISABLED, 4882 .details = mps_tx_intr_details, 4883 .actions = NULL, 4884 }; 4885 static const struct intr_details mps_trc_intr_details[] = { 4886 { F_MISCPERR, "MPS TRC misc parity error" }, 4887 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4888 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4889 { 0 } 4890 }; 4891 static const struct intr_info mps_trc_intr_info = { 4892 .name = "MPS_TRC_INT_CAUSE", 4893 .cause_reg = A_MPS_TRC_INT_CAUSE, 4894 .enable_reg = A_MPS_TRC_INT_ENABLE, 4895 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4896 .flags = 0, 4897 .details = mps_trc_intr_details, 4898 .actions = NULL, 4899 }; 4900 static const struct intr_details mps_stat_sram_intr_details[] = { 4901 { 0xffffffff, "MPS statistics SRAM parity error" }, 4902 { 0 } 4903 }; 4904 static const struct intr_info mps_stat_sram_intr_info = { 4905 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4906 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4907 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4908 .fatal = 0x1fffffff, 4909 .flags = NONFATAL_IF_DISABLED, 4910 .details = mps_stat_sram_intr_details, 4911 .actions = NULL, 4912 }; 4913 static const struct intr_details mps_stat_tx_intr_details[] = { 4914 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4915 { 0 } 4916 }; 4917 static const struct intr_info mps_stat_tx_intr_info = { 4918 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4919 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4920 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4921 .fatal = 0xffffff, 4922 .flags = NONFATAL_IF_DISABLED, 4923 .details = mps_stat_tx_intr_details, 4924 .actions = NULL, 4925 }; 4926 static const struct intr_details mps_stat_rx_intr_details[] = { 4927 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4928 { 0 } 4929 }; 4930 static const struct intr_info mps_stat_rx_intr_info = { 4931 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4932 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4933 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4934 .fatal = 0xffffff, 4935 .flags = 0, 4936 .details = mps_stat_rx_intr_details, 4937 .actions = NULL, 4938 }; 4939 static const struct intr_details mps_cls_intr_details[] = { 4940 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4941 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4942 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4943 { 0 } 4944 }; 4945 static const struct intr_info mps_cls_intr_info = { 4946 .name = "MPS_CLS_INT_CAUSE", 4947 .cause_reg = A_MPS_CLS_INT_CAUSE, 4948 .enable_reg = A_MPS_CLS_INT_ENABLE, 4949 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4950 .flags = 0, 4951 .details = mps_cls_intr_details, 4952 .actions = NULL, 4953 }; 4954 static const struct intr_details mps_stat_sram1_intr_details[] = { 4955 { 0xff, "MPS statistics SRAM1 parity error" }, 4956 { 0 } 4957 }; 4958 static const struct intr_info mps_stat_sram1_intr_info = { 4959 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4960 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4961 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4962 .fatal = 0xff, 4963 .flags = 0, 4964 .details = mps_stat_sram1_intr_details, 4965 .actions = NULL, 4966 }; 4967 4968 bool fatal; 4969 4970 fatal = false; 4971 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 4972 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 4973 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 4974 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 4975 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 4976 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 4977 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 4978 if (chip_id(adap) > CHELSIO_T4) { 4979 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 4980 verbose); 4981 } 4982 4983 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 4984 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 4985 4986 return (fatal); 4987 4988 } 4989 4990 /* 4991 * EDC/MC interrupt handler. 4992 */ 4993 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 4994 { 4995 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 4996 unsigned int count_reg, v; 4997 static const struct intr_details mem_intr_details[] = { 4998 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 4999 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 5000 { F_PERR_INT_CAUSE, "FIFO parity error" }, 5001 { 0 } 5002 }; 5003 struct intr_info ii = { 5004 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 5005 .details = mem_intr_details, 5006 .flags = 0, 5007 .actions = NULL, 5008 }; 5009 bool fatal; 5010 5011 switch (idx) { 5012 case MEM_EDC0: 5013 ii.name = "EDC0_INT_CAUSE"; 5014 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 5015 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 5016 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 5017 break; 5018 case MEM_EDC1: 5019 ii.name = "EDC1_INT_CAUSE"; 5020 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 5021 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 5022 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 5023 break; 5024 case MEM_MC0: 5025 ii.name = "MC0_INT_CAUSE"; 5026 if (is_t4(adap)) { 5027 ii.cause_reg = A_MC_INT_CAUSE; 5028 ii.enable_reg = A_MC_INT_ENABLE; 5029 count_reg = A_MC_ECC_STATUS; 5030 } else { 5031 ii.cause_reg = A_MC_P_INT_CAUSE; 5032 ii.enable_reg = A_MC_P_INT_ENABLE; 5033 count_reg = A_MC_P_ECC_STATUS; 5034 } 5035 break; 5036 case MEM_MC1: 5037 ii.name = "MC1_INT_CAUSE"; 5038 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 5039 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 5040 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 5041 break; 5042 } 5043 5044 fatal = t4_handle_intr(adap, &ii, 0, verbose); 5045 5046 v = t4_read_reg(adap, count_reg); 5047 if (v != 0) { 5048 if (G_ECC_UECNT(v) != 0) { 5049 CH_ALERT(adap, 5050 "%s: %u uncorrectable ECC data error(s)\n", 5051 name[idx], G_ECC_UECNT(v)); 5052 } 5053 if (G_ECC_CECNT(v) != 0) { 5054 if (idx <= MEM_EDC1) 5055 t4_edc_err_read(adap, idx); 5056 CH_WARN_RATELIMIT(adap, 5057 "%s: %u correctable ECC data error(s)\n", 5058 name[idx], G_ECC_CECNT(v)); 5059 } 5060 t4_write_reg(adap, count_reg, 0xffffffff); 5061 } 5062 5063 return (fatal); 5064 } 5065 5066 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5067 { 5068 u32 v; 5069 5070 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5071 CH_ALERT(adap, 5072 "MA address wrap-around error by client %u to address %#x\n", 5073 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5074 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5075 5076 return (false); 5077 } 5078 5079 5080 /* 5081 * MA interrupt handler. 5082 */ 5083 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5084 { 5085 static const struct intr_action ma_intr_actions[] = { 5086 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5087 { 0 }, 5088 }; 5089 static const struct intr_info ma_intr_info = { 5090 .name = "MA_INT_CAUSE", 5091 .cause_reg = A_MA_INT_CAUSE, 5092 .enable_reg = A_MA_INT_ENABLE, 5093 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5094 .flags = NONFATAL_IF_DISABLED, 5095 .details = NULL, 5096 .actions = ma_intr_actions, 5097 }; 5098 static const struct intr_info ma_perr_status1 = { 5099 .name = "MA_PARITY_ERROR_STATUS1", 5100 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5101 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5102 .fatal = 0xffffffff, 5103 .flags = 0, 5104 .details = NULL, 5105 .actions = NULL, 5106 }; 5107 static const struct intr_info ma_perr_status2 = { 5108 .name = "MA_PARITY_ERROR_STATUS2", 5109 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5110 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5111 .fatal = 0xffffffff, 5112 .flags = 0, 5113 .details = NULL, 5114 .actions = NULL, 5115 }; 5116 bool fatal; 5117 5118 fatal = false; 5119 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5120 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5121 if (chip_id(adap) > CHELSIO_T4) 5122 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5123 5124 return (fatal); 5125 } 5126 5127 /* 5128 * SMB interrupt handler. 5129 */ 5130 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5131 { 5132 static const struct intr_details smb_intr_details[] = { 5133 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5134 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5135 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5136 { 0 } 5137 }; 5138 static const struct intr_info smb_intr_info = { 5139 .name = "SMB_INT_CAUSE", 5140 .cause_reg = A_SMB_INT_CAUSE, 5141 .enable_reg = A_SMB_INT_ENABLE, 5142 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5143 .flags = 0, 5144 .details = smb_intr_details, 5145 .actions = NULL, 5146 }; 5147 5148 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5149 } 5150 5151 /* 5152 * NC-SI interrupt handler. 5153 */ 5154 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5155 { 5156 static const struct intr_details ncsi_intr_details[] = { 5157 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5158 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5159 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5160 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5161 { 0 } 5162 }; 5163 static const struct intr_info ncsi_intr_info = { 5164 .name = "NCSI_INT_CAUSE", 5165 .cause_reg = A_NCSI_INT_CAUSE, 5166 .enable_reg = A_NCSI_INT_ENABLE, 5167 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5168 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5169 .flags = 0, 5170 .details = ncsi_intr_details, 5171 .actions = NULL, 5172 }; 5173 5174 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5175 } 5176 5177 /* 5178 * MAC interrupt handler. 5179 */ 5180 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5181 { 5182 static const struct intr_details mac_intr_details[] = { 5183 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5184 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5185 { 0 } 5186 }; 5187 char name[32]; 5188 struct intr_info ii; 5189 bool fatal = false; 5190 5191 if (is_t4(adap)) { 5192 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5193 ii.name = &name[0]; 5194 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5195 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5196 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5197 ii.flags = 0; 5198 ii.details = mac_intr_details; 5199 ii.actions = NULL; 5200 } else { 5201 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5202 ii.name = &name[0]; 5203 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5204 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5205 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5206 ii.flags = 0; 5207 ii.details = mac_intr_details; 5208 ii.actions = NULL; 5209 } 5210 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5211 5212 if (chip_id(adap) >= CHELSIO_T5) { 5213 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5214 ii.name = &name[0]; 5215 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5216 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5217 ii.fatal = 0; 5218 ii.flags = 0; 5219 ii.details = NULL; 5220 ii.actions = NULL; 5221 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5222 } 5223 5224 if (chip_id(adap) >= CHELSIO_T6) { 5225 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5226 ii.name = &name[0]; 5227 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5228 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5229 ii.fatal = 0; 5230 ii.flags = 0; 5231 ii.details = NULL; 5232 ii.actions = NULL; 5233 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5234 } 5235 5236 return (fatal); 5237 } 5238 5239 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5240 { 5241 static const struct intr_details plpl_intr_details[] = { 5242 { F_FATALPERR, "Fatal parity error" }, 5243 { F_PERRVFID, "VFID_MAP parity error" }, 5244 { 0 } 5245 }; 5246 static const struct intr_info plpl_intr_info = { 5247 .name = "PL_PL_INT_CAUSE", 5248 .cause_reg = A_PL_PL_INT_CAUSE, 5249 .enable_reg = A_PL_PL_INT_ENABLE, 5250 .fatal = F_FATALPERR | F_PERRVFID, 5251 .flags = NONFATAL_IF_DISABLED, 5252 .details = plpl_intr_details, 5253 .actions = NULL, 5254 }; 5255 5256 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5257 } 5258 5259 /** 5260 * t4_slow_intr_handler - control path interrupt handler 5261 * @adap: the adapter 5262 * @verbose: increased verbosity, for debug 5263 * 5264 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5265 * The designation 'slow' is because it involves register reads, while 5266 * data interrupts typically don't involve any MMIOs. 5267 */ 5268 int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5269 { 5270 static const struct intr_details pl_intr_details[] = { 5271 { F_MC1, "MC1" }, 5272 { F_UART, "UART" }, 5273 { F_ULP_TX, "ULP TX" }, 5274 { F_SGE, "SGE" }, 5275 { F_HMA, "HMA" }, 5276 { F_CPL_SWITCH, "CPL Switch" }, 5277 { F_ULP_RX, "ULP RX" }, 5278 { F_PM_RX, "PM RX" }, 5279 { F_PM_TX, "PM TX" }, 5280 { F_MA, "MA" }, 5281 { F_TP, "TP" }, 5282 { F_LE, "LE" }, 5283 { F_EDC1, "EDC1" }, 5284 { F_EDC0, "EDC0" }, 5285 { F_MC, "MC0" }, 5286 { F_PCIE, "PCIE" }, 5287 { F_PMU, "PMU" }, 5288 { F_MAC3, "MAC3" }, 5289 { F_MAC2, "MAC2" }, 5290 { F_MAC1, "MAC1" }, 5291 { F_MAC0, "MAC0" }, 5292 { F_SMB, "SMB" }, 5293 { F_SF, "SF" }, 5294 { F_PL, "PL" }, 5295 { F_NCSI, "NC-SI" }, 5296 { F_MPS, "MPS" }, 5297 { F_MI, "MI" }, 5298 { F_DBG, "DBG" }, 5299 { F_I2CM, "I2CM" }, 5300 { F_CIM, "CIM" }, 5301 { 0 } 5302 }; 5303 static const struct intr_info pl_perr_cause = { 5304 .name = "PL_PERR_CAUSE", 5305 .cause_reg = A_PL_PERR_CAUSE, 5306 .enable_reg = A_PL_PERR_ENABLE, 5307 .fatal = 0xffffffff, 5308 .flags = 0, 5309 .details = pl_intr_details, 5310 .actions = NULL, 5311 }; 5312 static const struct intr_action pl_intr_action[] = { 5313 { F_MC1, MEM_MC1, mem_intr_handler }, 5314 { F_ULP_TX, -1, ulptx_intr_handler }, 5315 { F_SGE, -1, sge_intr_handler }, 5316 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5317 { F_ULP_RX, -1, ulprx_intr_handler }, 5318 { F_PM_RX, -1, pmrx_intr_handler}, 5319 { F_PM_TX, -1, pmtx_intr_handler}, 5320 { F_MA, -1, ma_intr_handler }, 5321 { F_TP, -1, tp_intr_handler }, 5322 { F_LE, -1, le_intr_handler }, 5323 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5324 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5325 { F_MC0, MEM_MC0, mem_intr_handler }, 5326 { F_PCIE, -1, pcie_intr_handler }, 5327 { F_MAC3, 3, mac_intr_handler}, 5328 { F_MAC2, 2, mac_intr_handler}, 5329 { F_MAC1, 1, mac_intr_handler}, 5330 { F_MAC0, 0, mac_intr_handler}, 5331 { F_SMB, -1, smb_intr_handler}, 5332 { F_PL, -1, plpl_intr_handler }, 5333 { F_NCSI, -1, ncsi_intr_handler}, 5334 { F_MPS, -1, mps_intr_handler }, 5335 { F_CIM, -1, cim_intr_handler }, 5336 { 0 } 5337 }; 5338 static const struct intr_info pl_intr_info = { 5339 .name = "PL_INT_CAUSE", 5340 .cause_reg = A_PL_INT_CAUSE, 5341 .enable_reg = A_PL_INT_ENABLE, 5342 .fatal = 0, 5343 .flags = 0, 5344 .details = pl_intr_details, 5345 .actions = pl_intr_action, 5346 }; 5347 bool fatal; 5348 u32 perr; 5349 5350 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5351 if (verbose || perr != 0) { 5352 t4_show_intr_info(adap, &pl_perr_cause, perr); 5353 if (perr != 0) 5354 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5355 if (verbose) 5356 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5357 } 5358 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5359 if (fatal) 5360 t4_fatal_err(adap, false); 5361 5362 return (0); 5363 } 5364 5365 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5366 5367 /** 5368 * t4_intr_enable - enable interrupts 5369 * @adapter: the adapter whose interrupts should be enabled 5370 * 5371 * Enable PF-specific interrupts for the calling function and the top-level 5372 * interrupt concentrator for global interrupts. Interrupts are already 5373 * enabled at each module, here we just enable the roots of the interrupt 5374 * hierarchies. 5375 * 5376 * Note: this function should be called only when the driver manages 5377 * non PF-specific interrupts from the various HW modules. Only one PCI 5378 * function at a time should be doing this. 5379 */ 5380 void t4_intr_enable(struct adapter *adap) 5381 { 5382 u32 val = 0; 5383 5384 if (chip_id(adap) <= CHELSIO_T5) 5385 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5386 else 5387 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5388 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5389 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5390 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5391 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5392 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5393 F_EGRESS_SIZE_ERR; 5394 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5395 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5396 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5397 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5398 } 5399 5400 /** 5401 * t4_intr_disable - disable interrupts 5402 * @adap: the adapter whose interrupts should be disabled 5403 * 5404 * Disable interrupts. We only disable the top-level interrupt 5405 * concentrators. The caller must be a PCI function managing global 5406 * interrupts. 5407 */ 5408 void t4_intr_disable(struct adapter *adap) 5409 { 5410 5411 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5412 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5413 } 5414 5415 /** 5416 * t4_intr_clear - clear all interrupts 5417 * @adap: the adapter whose interrupts should be cleared 5418 * 5419 * Clears all interrupts. The caller must be a PCI function managing 5420 * global interrupts. 5421 */ 5422 void t4_intr_clear(struct adapter *adap) 5423 { 5424 static const u32 cause_reg[] = { 5425 A_CIM_HOST_INT_CAUSE, 5426 A_CIM_HOST_UPACC_INT_CAUSE, 5427 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5428 A_CPL_INTR_CAUSE, 5429 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5430 A_LE_DB_INT_CAUSE, 5431 A_MA_INT_WRAP_STATUS, 5432 A_MA_PARITY_ERROR_STATUS1, 5433 A_MA_INT_CAUSE, 5434 A_MPS_CLS_INT_CAUSE, 5435 A_MPS_RX_PERR_INT_CAUSE, 5436 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5437 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5438 A_MPS_TRC_INT_CAUSE, 5439 A_MPS_TX_INT_CAUSE, 5440 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5441 A_NCSI_INT_CAUSE, 5442 A_PCIE_INT_CAUSE, 5443 A_PCIE_NONFAT_ERR, 5444 A_PL_PL_INT_CAUSE, 5445 A_PM_RX_INT_CAUSE, 5446 A_PM_TX_INT_CAUSE, 5447 A_SGE_INT_CAUSE1, 5448 A_SGE_INT_CAUSE2, 5449 A_SGE_INT_CAUSE3, 5450 A_SGE_INT_CAUSE4, 5451 A_SMB_INT_CAUSE, 5452 A_TP_INT_CAUSE, 5453 A_ULP_RX_INT_CAUSE, 5454 A_ULP_RX_INT_CAUSE_2, 5455 A_ULP_TX_INT_CAUSE, 5456 A_ULP_TX_INT_CAUSE_2, 5457 5458 MYPF_REG(A_PL_PF_INT_CAUSE), 5459 }; 5460 int i; 5461 const int nchan = adap->chip_params->nchan; 5462 5463 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5464 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5465 5466 if (is_t4(adap)) { 5467 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5468 0xffffffff); 5469 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5470 0xffffffff); 5471 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5472 for (i = 0; i < nchan; i++) { 5473 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5474 0xffffffff); 5475 } 5476 } 5477 if (chip_id(adap) >= CHELSIO_T5) { 5478 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5479 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5480 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5481 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5482 if (is_t5(adap)) { 5483 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5484 0xffffffff); 5485 } 5486 for (i = 0; i < nchan; i++) { 5487 t4_write_reg(adap, T5_PORT_REG(i, 5488 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5489 if (chip_id(adap) > CHELSIO_T5) { 5490 t4_write_reg(adap, T5_PORT_REG(i, 5491 A_MAC_PORT_PERR_INT_CAUSE_100G), 5492 0xffffffff); 5493 } 5494 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5495 0xffffffff); 5496 } 5497 } 5498 if (chip_id(adap) >= CHELSIO_T6) { 5499 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5500 } 5501 5502 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5503 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5504 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5505 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5506 } 5507 5508 /** 5509 * hash_mac_addr - return the hash value of a MAC address 5510 * @addr: the 48-bit Ethernet MAC address 5511 * 5512 * Hashes a MAC address according to the hash function used by HW inexact 5513 * (hash) address matching. 5514 */ 5515 static int hash_mac_addr(const u8 *addr) 5516 { 5517 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5518 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5519 a ^= b; 5520 a ^= (a >> 12); 5521 a ^= (a >> 6); 5522 return a & 0x3f; 5523 } 5524 5525 /** 5526 * t4_config_rss_range - configure a portion of the RSS mapping table 5527 * @adapter: the adapter 5528 * @mbox: mbox to use for the FW command 5529 * @viid: virtual interface whose RSS subtable is to be written 5530 * @start: start entry in the table to write 5531 * @n: how many table entries to write 5532 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5533 * @nrspq: number of values in @rspq 5534 * 5535 * Programs the selected part of the VI's RSS mapping table with the 5536 * provided values. If @nrspq < @n the supplied values are used repeatedly 5537 * until the full table range is populated. 5538 * 5539 * The caller must ensure the values in @rspq are in the range allowed for 5540 * @viid. 5541 */ 5542 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5543 int start, int n, const u16 *rspq, unsigned int nrspq) 5544 { 5545 int ret; 5546 const u16 *rsp = rspq; 5547 const u16 *rsp_end = rspq + nrspq; 5548 struct fw_rss_ind_tbl_cmd cmd; 5549 5550 memset(&cmd, 0, sizeof(cmd)); 5551 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5552 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5553 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5554 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5555 5556 /* 5557 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5558 * Queue Identifiers. These Ingress Queue IDs are packed three to 5559 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5560 * reserved. 5561 */ 5562 while (n > 0) { 5563 int nq = min(n, 32); 5564 int nq_packed = 0; 5565 __be32 *qp = &cmd.iq0_to_iq2; 5566 5567 /* 5568 * Set up the firmware RSS command header to send the next 5569 * "nq" Ingress Queue IDs to the firmware. 5570 */ 5571 cmd.niqid = cpu_to_be16(nq); 5572 cmd.startidx = cpu_to_be16(start); 5573 5574 /* 5575 * "nq" more done for the start of the next loop. 5576 */ 5577 start += nq; 5578 n -= nq; 5579 5580 /* 5581 * While there are still Ingress Queue IDs to stuff into the 5582 * current firmware RSS command, retrieve them from the 5583 * Ingress Queue ID array and insert them into the command. 5584 */ 5585 while (nq > 0) { 5586 /* 5587 * Grab up to the next 3 Ingress Queue IDs (wrapping 5588 * around the Ingress Queue ID array if necessary) and 5589 * insert them into the firmware RSS command at the 5590 * current 3-tuple position within the commad. 5591 */ 5592 u16 qbuf[3]; 5593 u16 *qbp = qbuf; 5594 int nqbuf = min(3, nq); 5595 5596 nq -= nqbuf; 5597 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5598 while (nqbuf && nq_packed < 32) { 5599 nqbuf--; 5600 nq_packed++; 5601 *qbp++ = *rsp++; 5602 if (rsp >= rsp_end) 5603 rsp = rspq; 5604 } 5605 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5606 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5607 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5608 } 5609 5610 /* 5611 * Send this portion of the RRS table update to the firmware; 5612 * bail out on any errors. 5613 */ 5614 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5615 if (ret) 5616 return ret; 5617 } 5618 return 0; 5619 } 5620 5621 /** 5622 * t4_config_glbl_rss - configure the global RSS mode 5623 * @adapter: the adapter 5624 * @mbox: mbox to use for the FW command 5625 * @mode: global RSS mode 5626 * @flags: mode-specific flags 5627 * 5628 * Sets the global RSS mode. 5629 */ 5630 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5631 unsigned int flags) 5632 { 5633 struct fw_rss_glb_config_cmd c; 5634 5635 memset(&c, 0, sizeof(c)); 5636 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5637 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5638 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5639 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5640 c.u.manual.mode_pkd = 5641 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5642 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5643 c.u.basicvirtual.mode_keymode = 5644 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5645 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5646 } else 5647 return -EINVAL; 5648 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5649 } 5650 5651 /** 5652 * t4_config_vi_rss - configure per VI RSS settings 5653 * @adapter: the adapter 5654 * @mbox: mbox to use for the FW command 5655 * @viid: the VI id 5656 * @flags: RSS flags 5657 * @defq: id of the default RSS queue for the VI. 5658 * @skeyidx: RSS secret key table index for non-global mode 5659 * @skey: RSS vf_scramble key for VI. 5660 * 5661 * Configures VI-specific RSS properties. 5662 */ 5663 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5664 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5665 unsigned int skey) 5666 { 5667 struct fw_rss_vi_config_cmd c; 5668 5669 memset(&c, 0, sizeof(c)); 5670 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5671 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5672 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5673 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5674 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5675 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5676 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5677 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5678 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5679 5680 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5681 } 5682 5683 /* Read an RSS table row */ 5684 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5685 { 5686 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5687 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5688 5, 0, val); 5689 } 5690 5691 /** 5692 * t4_read_rss - read the contents of the RSS mapping table 5693 * @adapter: the adapter 5694 * @map: holds the contents of the RSS mapping table 5695 * 5696 * Reads the contents of the RSS hash->queue mapping table. 5697 */ 5698 int t4_read_rss(struct adapter *adapter, u16 *map) 5699 { 5700 u32 val; 5701 int i, ret; 5702 int rss_nentries = adapter->chip_params->rss_nentries; 5703 5704 for (i = 0; i < rss_nentries / 2; ++i) { 5705 ret = rd_rss_row(adapter, i, &val); 5706 if (ret) 5707 return ret; 5708 *map++ = G_LKPTBLQUEUE0(val); 5709 *map++ = G_LKPTBLQUEUE1(val); 5710 } 5711 return 0; 5712 } 5713 5714 /** 5715 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5716 * @adap: the adapter 5717 * @cmd: TP fw ldst address space type 5718 * @vals: where the indirect register values are stored/written 5719 * @nregs: how many indirect registers to read/write 5720 * @start_idx: index of first indirect register to read/write 5721 * @rw: Read (1) or Write (0) 5722 * @sleep_ok: if true we may sleep while awaiting command completion 5723 * 5724 * Access TP indirect registers through LDST 5725 **/ 5726 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5727 unsigned int nregs, unsigned int start_index, 5728 unsigned int rw, bool sleep_ok) 5729 { 5730 int ret = 0; 5731 unsigned int i; 5732 struct fw_ldst_cmd c; 5733 5734 for (i = 0; i < nregs; i++) { 5735 memset(&c, 0, sizeof(c)); 5736 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5737 F_FW_CMD_REQUEST | 5738 (rw ? F_FW_CMD_READ : 5739 F_FW_CMD_WRITE) | 5740 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5741 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5742 5743 c.u.addrval.addr = cpu_to_be32(start_index + i); 5744 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5745 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5746 sleep_ok); 5747 if (ret) 5748 return ret; 5749 5750 if (rw) 5751 vals[i] = be32_to_cpu(c.u.addrval.val); 5752 } 5753 return 0; 5754 } 5755 5756 /** 5757 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5758 * @adap: the adapter 5759 * @reg_addr: Address Register 5760 * @reg_data: Data register 5761 * @buff: where the indirect register values are stored/written 5762 * @nregs: how many indirect registers to read/write 5763 * @start_index: index of first indirect register to read/write 5764 * @rw: READ(1) or WRITE(0) 5765 * @sleep_ok: if true we may sleep while awaiting command completion 5766 * 5767 * Read/Write TP indirect registers through LDST if possible. 5768 * Else, use backdoor access 5769 **/ 5770 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5771 u32 *buff, u32 nregs, u32 start_index, int rw, 5772 bool sleep_ok) 5773 { 5774 int rc = -EINVAL; 5775 int cmd; 5776 5777 switch (reg_addr) { 5778 case A_TP_PIO_ADDR: 5779 cmd = FW_LDST_ADDRSPC_TP_PIO; 5780 break; 5781 case A_TP_TM_PIO_ADDR: 5782 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5783 break; 5784 case A_TP_MIB_INDEX: 5785 cmd = FW_LDST_ADDRSPC_TP_MIB; 5786 break; 5787 default: 5788 goto indirect_access; 5789 } 5790 5791 if (t4_use_ldst(adap)) 5792 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5793 sleep_ok); 5794 5795 indirect_access: 5796 5797 if (rc) { 5798 if (rw) 5799 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5800 start_index); 5801 else 5802 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5803 start_index); 5804 } 5805 } 5806 5807 /** 5808 * t4_tp_pio_read - Read TP PIO registers 5809 * @adap: the adapter 5810 * @buff: where the indirect register values are written 5811 * @nregs: how many indirect registers to read 5812 * @start_index: index of first indirect register to read 5813 * @sleep_ok: if true we may sleep while awaiting command completion 5814 * 5815 * Read TP PIO Registers 5816 **/ 5817 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5818 u32 start_index, bool sleep_ok) 5819 { 5820 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5821 start_index, 1, sleep_ok); 5822 } 5823 5824 /** 5825 * t4_tp_pio_write - Write TP PIO registers 5826 * @adap: the adapter 5827 * @buff: where the indirect register values are stored 5828 * @nregs: how many indirect registers to write 5829 * @start_index: index of first indirect register to write 5830 * @sleep_ok: if true we may sleep while awaiting command completion 5831 * 5832 * Write TP PIO Registers 5833 **/ 5834 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5835 u32 start_index, bool sleep_ok) 5836 { 5837 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5838 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5839 } 5840 5841 /** 5842 * t4_tp_tm_pio_read - Read TP TM PIO registers 5843 * @adap: the adapter 5844 * @buff: where the indirect register values are written 5845 * @nregs: how many indirect registers to read 5846 * @start_index: index of first indirect register to read 5847 * @sleep_ok: if true we may sleep while awaiting command completion 5848 * 5849 * Read TP TM PIO Registers 5850 **/ 5851 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5852 u32 start_index, bool sleep_ok) 5853 { 5854 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5855 nregs, start_index, 1, sleep_ok); 5856 } 5857 5858 /** 5859 * t4_tp_mib_read - Read TP MIB registers 5860 * @adap: the adapter 5861 * @buff: where the indirect register values are written 5862 * @nregs: how many indirect registers to read 5863 * @start_index: index of first indirect register to read 5864 * @sleep_ok: if true we may sleep while awaiting command completion 5865 * 5866 * Read TP MIB Registers 5867 **/ 5868 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5869 bool sleep_ok) 5870 { 5871 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5872 start_index, 1, sleep_ok); 5873 } 5874 5875 /** 5876 * t4_read_rss_key - read the global RSS key 5877 * @adap: the adapter 5878 * @key: 10-entry array holding the 320-bit RSS key 5879 * @sleep_ok: if true we may sleep while awaiting command completion 5880 * 5881 * Reads the global 320-bit RSS key. 5882 */ 5883 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5884 { 5885 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5886 } 5887 5888 /** 5889 * t4_write_rss_key - program one of the RSS keys 5890 * @adap: the adapter 5891 * @key: 10-entry array holding the 320-bit RSS key 5892 * @idx: which RSS key to write 5893 * @sleep_ok: if true we may sleep while awaiting command completion 5894 * 5895 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5896 * 0..15 the corresponding entry in the RSS key table is written, 5897 * otherwise the global RSS key is written. 5898 */ 5899 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5900 bool sleep_ok) 5901 { 5902 u8 rss_key_addr_cnt = 16; 5903 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5904 5905 /* 5906 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5907 * allows access to key addresses 16-63 by using KeyWrAddrX 5908 * as index[5:4](upper 2) into key table 5909 */ 5910 if ((chip_id(adap) > CHELSIO_T5) && 5911 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5912 rss_key_addr_cnt = 32; 5913 5914 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5915 5916 if (idx >= 0 && idx < rss_key_addr_cnt) { 5917 if (rss_key_addr_cnt > 16) 5918 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5919 vrt | V_KEYWRADDRX(idx >> 4) | 5920 V_T6_VFWRADDR(idx) | F_KEYWREN); 5921 else 5922 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5923 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5924 } 5925 } 5926 5927 /** 5928 * t4_read_rss_pf_config - read PF RSS Configuration Table 5929 * @adapter: the adapter 5930 * @index: the entry in the PF RSS table to read 5931 * @valp: where to store the returned value 5932 * @sleep_ok: if true we may sleep while awaiting command completion 5933 * 5934 * Reads the PF RSS Configuration Table at the specified index and returns 5935 * the value found there. 5936 */ 5937 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5938 u32 *valp, bool sleep_ok) 5939 { 5940 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5941 } 5942 5943 /** 5944 * t4_write_rss_pf_config - write PF RSS Configuration Table 5945 * @adapter: the adapter 5946 * @index: the entry in the VF RSS table to read 5947 * @val: the value to store 5948 * @sleep_ok: if true we may sleep while awaiting command completion 5949 * 5950 * Writes the PF RSS Configuration Table at the specified index with the 5951 * specified value. 5952 */ 5953 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5954 u32 val, bool sleep_ok) 5955 { 5956 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5957 sleep_ok); 5958 } 5959 5960 /** 5961 * t4_read_rss_vf_config - read VF RSS Configuration Table 5962 * @adapter: the adapter 5963 * @index: the entry in the VF RSS table to read 5964 * @vfl: where to store the returned VFL 5965 * @vfh: where to store the returned VFH 5966 * @sleep_ok: if true we may sleep while awaiting command completion 5967 * 5968 * Reads the VF RSS Configuration Table at the specified index and returns 5969 * the (VFL, VFH) values found there. 5970 */ 5971 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5972 u32 *vfl, u32 *vfh, bool sleep_ok) 5973 { 5974 u32 vrt, mask, data; 5975 5976 if (chip_id(adapter) <= CHELSIO_T5) { 5977 mask = V_VFWRADDR(M_VFWRADDR); 5978 data = V_VFWRADDR(index); 5979 } else { 5980 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5981 data = V_T6_VFWRADDR(index); 5982 } 5983 /* 5984 * Request that the index'th VF Table values be read into VFL/VFH. 5985 */ 5986 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5987 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5988 vrt |= data | F_VFRDEN; 5989 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5990 5991 /* 5992 * Grab the VFL/VFH values ... 5993 */ 5994 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5995 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5996 } 5997 5998 /** 5999 * t4_write_rss_vf_config - write VF RSS Configuration Table 6000 * 6001 * @adapter: the adapter 6002 * @index: the entry in the VF RSS table to write 6003 * @vfl: the VFL to store 6004 * @vfh: the VFH to store 6005 * 6006 * Writes the VF RSS Configuration Table at the specified index with the 6007 * specified (VFL, VFH) values. 6008 */ 6009 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 6010 u32 vfl, u32 vfh, bool sleep_ok) 6011 { 6012 u32 vrt, mask, data; 6013 6014 if (chip_id(adapter) <= CHELSIO_T5) { 6015 mask = V_VFWRADDR(M_VFWRADDR); 6016 data = V_VFWRADDR(index); 6017 } else { 6018 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6019 data = V_T6_VFWRADDR(index); 6020 } 6021 6022 /* 6023 * Load up VFL/VFH with the values to be written ... 6024 */ 6025 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6026 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6027 6028 /* 6029 * Write the VFL/VFH into the VF Table at index'th location. 6030 */ 6031 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6032 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6033 vrt |= data | F_VFRDEN; 6034 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6035 } 6036 6037 /** 6038 * t4_read_rss_pf_map - read PF RSS Map 6039 * @adapter: the adapter 6040 * @sleep_ok: if true we may sleep while awaiting command completion 6041 * 6042 * Reads the PF RSS Map register and returns its value. 6043 */ 6044 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 6045 { 6046 u32 pfmap; 6047 6048 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6049 6050 return pfmap; 6051 } 6052 6053 /** 6054 * t4_write_rss_pf_map - write PF RSS Map 6055 * @adapter: the adapter 6056 * @pfmap: PF RSS Map value 6057 * 6058 * Writes the specified value to the PF RSS Map register. 6059 */ 6060 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6061 { 6062 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6063 } 6064 6065 /** 6066 * t4_read_rss_pf_mask - read PF RSS Mask 6067 * @adapter: the adapter 6068 * @sleep_ok: if true we may sleep while awaiting command completion 6069 * 6070 * Reads the PF RSS Mask register and returns its value. 6071 */ 6072 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6073 { 6074 u32 pfmask; 6075 6076 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6077 6078 return pfmask; 6079 } 6080 6081 /** 6082 * t4_write_rss_pf_mask - write PF RSS Mask 6083 * @adapter: the adapter 6084 * @pfmask: PF RSS Mask value 6085 * 6086 * Writes the specified value to the PF RSS Mask register. 6087 */ 6088 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6089 { 6090 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6091 } 6092 6093 /** 6094 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6095 * @adap: the adapter 6096 * @v4: holds the TCP/IP counter values 6097 * @v6: holds the TCP/IPv6 counter values 6098 * @sleep_ok: if true we may sleep while awaiting command completion 6099 * 6100 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6101 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6102 */ 6103 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6104 struct tp_tcp_stats *v6, bool sleep_ok) 6105 { 6106 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6107 6108 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6109 #define STAT(x) val[STAT_IDX(x)] 6110 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6111 6112 if (v4) { 6113 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6114 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6115 v4->tcp_out_rsts = STAT(OUT_RST); 6116 v4->tcp_in_segs = STAT64(IN_SEG); 6117 v4->tcp_out_segs = STAT64(OUT_SEG); 6118 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6119 } 6120 if (v6) { 6121 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6122 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6123 v6->tcp_out_rsts = STAT(OUT_RST); 6124 v6->tcp_in_segs = STAT64(IN_SEG); 6125 v6->tcp_out_segs = STAT64(OUT_SEG); 6126 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6127 } 6128 #undef STAT64 6129 #undef STAT 6130 #undef STAT_IDX 6131 } 6132 6133 /** 6134 * t4_tp_get_err_stats - read TP's error MIB counters 6135 * @adap: the adapter 6136 * @st: holds the counter values 6137 * @sleep_ok: if true we may sleep while awaiting command completion 6138 * 6139 * Returns the values of TP's error counters. 6140 */ 6141 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6142 bool sleep_ok) 6143 { 6144 int nchan = adap->chip_params->nchan; 6145 6146 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6147 sleep_ok); 6148 6149 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6150 sleep_ok); 6151 6152 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6153 sleep_ok); 6154 6155 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6156 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6157 6158 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6159 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6160 6161 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6162 sleep_ok); 6163 6164 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6165 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6166 6167 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6168 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6169 6170 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6171 sleep_ok); 6172 } 6173 6174 /** 6175 * t4_tp_get_err_stats - read TP's error MIB counters 6176 * @adap: the adapter 6177 * @st: holds the counter values 6178 * @sleep_ok: if true we may sleep while awaiting command completion 6179 * 6180 * Returns the values of TP's error counters. 6181 */ 6182 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, 6183 bool sleep_ok) 6184 { 6185 int nchan = adap->chip_params->nchan; 6186 6187 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, 6188 sleep_ok); 6189 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, 6190 sleep_ok); 6191 } 6192 6193 /** 6194 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6195 * @adap: the adapter 6196 * @st: holds the counter values 6197 * 6198 * Returns the values of TP's proxy counters. 6199 */ 6200 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6201 bool sleep_ok) 6202 { 6203 int nchan = adap->chip_params->nchan; 6204 6205 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6206 } 6207 6208 /** 6209 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6210 * @adap: the adapter 6211 * @st: holds the counter values 6212 * @sleep_ok: if true we may sleep while awaiting command completion 6213 * 6214 * Returns the values of TP's CPL counters. 6215 */ 6216 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6217 bool sleep_ok) 6218 { 6219 int nchan = adap->chip_params->nchan; 6220 6221 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6222 6223 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6224 } 6225 6226 /** 6227 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6228 * @adap: the adapter 6229 * @st: holds the counter values 6230 * 6231 * Returns the values of TP's RDMA counters. 6232 */ 6233 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6234 bool sleep_ok) 6235 { 6236 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6237 sleep_ok); 6238 } 6239 6240 /** 6241 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6242 * @adap: the adapter 6243 * @idx: the port index 6244 * @st: holds the counter values 6245 * @sleep_ok: if true we may sleep while awaiting command completion 6246 * 6247 * Returns the values of TP's FCoE counters for the selected port. 6248 */ 6249 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6250 struct tp_fcoe_stats *st, bool sleep_ok) 6251 { 6252 u32 val[2]; 6253 6254 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6255 sleep_ok); 6256 6257 t4_tp_mib_read(adap, &st->frames_drop, 1, 6258 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6259 6260 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6261 sleep_ok); 6262 6263 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6264 } 6265 6266 /** 6267 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6268 * @adap: the adapter 6269 * @st: holds the counter values 6270 * @sleep_ok: if true we may sleep while awaiting command completion 6271 * 6272 * Returns the values of TP's counters for non-TCP directly-placed packets. 6273 */ 6274 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6275 bool sleep_ok) 6276 { 6277 u32 val[4]; 6278 6279 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6280 6281 st->frames = val[0]; 6282 st->drops = val[1]; 6283 st->octets = ((u64)val[2] << 32) | val[3]; 6284 } 6285 6286 /** 6287 * t4_tp_get_tid_stats - read TP's tid MIB counters. 6288 * @adap: the adapter 6289 * @st: holds the counter values 6290 * @sleep_ok: if true we may sleep while awaiting command completion 6291 * 6292 * Returns the values of TP's counters for tids. 6293 */ 6294 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, 6295 bool sleep_ok) 6296 { 6297 6298 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); 6299 } 6300 6301 /** 6302 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6303 * @adap: the adapter 6304 * @mtus: where to store the MTU values 6305 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6306 * 6307 * Reads the HW path MTU table. 6308 */ 6309 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6310 { 6311 u32 v; 6312 int i; 6313 6314 for (i = 0; i < NMTUS; ++i) { 6315 t4_write_reg(adap, A_TP_MTU_TABLE, 6316 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6317 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6318 mtus[i] = G_MTUVALUE(v); 6319 if (mtu_log) 6320 mtu_log[i] = G_MTUWIDTH(v); 6321 } 6322 } 6323 6324 /** 6325 * t4_read_cong_tbl - reads the congestion control table 6326 * @adap: the adapter 6327 * @incr: where to store the alpha values 6328 * 6329 * Reads the additive increments programmed into the HW congestion 6330 * control table. 6331 */ 6332 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6333 { 6334 unsigned int mtu, w; 6335 6336 for (mtu = 0; mtu < NMTUS; ++mtu) 6337 for (w = 0; w < NCCTRL_WIN; ++w) { 6338 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6339 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6340 incr[mtu][w] = (u16)t4_read_reg(adap, 6341 A_TP_CCTRL_TABLE) & 0x1fff; 6342 } 6343 } 6344 6345 /** 6346 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6347 * @adap: the adapter 6348 * @addr: the indirect TP register address 6349 * @mask: specifies the field within the register to modify 6350 * @val: new value for the field 6351 * 6352 * Sets a field of an indirect TP register to the given value. 6353 */ 6354 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6355 unsigned int mask, unsigned int val) 6356 { 6357 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6358 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6359 t4_write_reg(adap, A_TP_PIO_DATA, val); 6360 } 6361 6362 /** 6363 * init_cong_ctrl - initialize congestion control parameters 6364 * @a: the alpha values for congestion control 6365 * @b: the beta values for congestion control 6366 * 6367 * Initialize the congestion control parameters. 6368 */ 6369 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6370 { 6371 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6372 a[9] = 2; 6373 a[10] = 3; 6374 a[11] = 4; 6375 a[12] = 5; 6376 a[13] = 6; 6377 a[14] = 7; 6378 a[15] = 8; 6379 a[16] = 9; 6380 a[17] = 10; 6381 a[18] = 14; 6382 a[19] = 17; 6383 a[20] = 21; 6384 a[21] = 25; 6385 a[22] = 30; 6386 a[23] = 35; 6387 a[24] = 45; 6388 a[25] = 60; 6389 a[26] = 80; 6390 a[27] = 100; 6391 a[28] = 200; 6392 a[29] = 300; 6393 a[30] = 400; 6394 a[31] = 500; 6395 6396 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6397 b[9] = b[10] = 1; 6398 b[11] = b[12] = 2; 6399 b[13] = b[14] = b[15] = b[16] = 3; 6400 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6401 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6402 b[28] = b[29] = 6; 6403 b[30] = b[31] = 7; 6404 } 6405 6406 /* The minimum additive increment value for the congestion control table */ 6407 #define CC_MIN_INCR 2U 6408 6409 /** 6410 * t4_load_mtus - write the MTU and congestion control HW tables 6411 * @adap: the adapter 6412 * @mtus: the values for the MTU table 6413 * @alpha: the values for the congestion control alpha parameter 6414 * @beta: the values for the congestion control beta parameter 6415 * 6416 * Write the HW MTU table with the supplied MTUs and the high-speed 6417 * congestion control table with the supplied alpha, beta, and MTUs. 6418 * We write the two tables together because the additive increments 6419 * depend on the MTUs. 6420 */ 6421 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6422 const unsigned short *alpha, const unsigned short *beta) 6423 { 6424 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6425 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6426 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6427 28672, 40960, 57344, 81920, 114688, 163840, 229376 6428 }; 6429 6430 unsigned int i, w; 6431 6432 for (i = 0; i < NMTUS; ++i) { 6433 unsigned int mtu = mtus[i]; 6434 unsigned int log2 = fls(mtu); 6435 6436 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6437 log2--; 6438 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6439 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6440 6441 for (w = 0; w < NCCTRL_WIN; ++w) { 6442 unsigned int inc; 6443 6444 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6445 CC_MIN_INCR); 6446 6447 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6448 (w << 16) | (beta[w] << 13) | inc); 6449 } 6450 } 6451 } 6452 6453 /** 6454 * t4_set_pace_tbl - set the pace table 6455 * @adap: the adapter 6456 * @pace_vals: the pace values in microseconds 6457 * @start: index of the first entry in the HW pace table to set 6458 * @n: how many entries to set 6459 * 6460 * Sets (a subset of the) HW pace table. 6461 */ 6462 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6463 unsigned int start, unsigned int n) 6464 { 6465 unsigned int vals[NTX_SCHED], i; 6466 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6467 6468 if (n > NTX_SCHED) 6469 return -ERANGE; 6470 6471 /* convert values from us to dack ticks, rounding to closest value */ 6472 for (i = 0; i < n; i++, pace_vals++) { 6473 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6474 if (vals[i] > 0x7ff) 6475 return -ERANGE; 6476 if (*pace_vals && vals[i] == 0) 6477 return -ERANGE; 6478 } 6479 for (i = 0; i < n; i++, start++) 6480 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6481 return 0; 6482 } 6483 6484 /** 6485 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6486 * @adap: the adapter 6487 * @kbps: target rate in Kbps 6488 * @sched: the scheduler index 6489 * 6490 * Configure a Tx HW scheduler for the target rate. 6491 */ 6492 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6493 { 6494 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6495 unsigned int clk = adap->params.vpd.cclk * 1000; 6496 unsigned int selected_cpt = 0, selected_bpt = 0; 6497 6498 if (kbps > 0) { 6499 kbps *= 125; /* -> bytes */ 6500 for (cpt = 1; cpt <= 255; cpt++) { 6501 tps = clk / cpt; 6502 bpt = (kbps + tps / 2) / tps; 6503 if (bpt > 0 && bpt <= 255) { 6504 v = bpt * tps; 6505 delta = v >= kbps ? v - kbps : kbps - v; 6506 if (delta < mindelta) { 6507 mindelta = delta; 6508 selected_cpt = cpt; 6509 selected_bpt = bpt; 6510 } 6511 } else if (selected_cpt) 6512 break; 6513 } 6514 if (!selected_cpt) 6515 return -EINVAL; 6516 } 6517 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6518 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6519 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6520 if (sched & 1) 6521 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6522 else 6523 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6524 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6525 return 0; 6526 } 6527 6528 /** 6529 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6530 * @adap: the adapter 6531 * @sched: the scheduler index 6532 * @ipg: the interpacket delay in tenths of nanoseconds 6533 * 6534 * Set the interpacket delay for a HW packet rate scheduler. 6535 */ 6536 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6537 { 6538 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6539 6540 /* convert ipg to nearest number of core clocks */ 6541 ipg *= core_ticks_per_usec(adap); 6542 ipg = (ipg + 5000) / 10000; 6543 if (ipg > M_TXTIMERSEPQ0) 6544 return -EINVAL; 6545 6546 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6547 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6548 if (sched & 1) 6549 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6550 else 6551 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6552 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6553 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6554 return 0; 6555 } 6556 6557 /* 6558 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6559 * clocks. The formula is 6560 * 6561 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6562 * 6563 * which is equivalent to 6564 * 6565 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6566 */ 6567 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6568 { 6569 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6570 6571 return v * 62 + v / 2; 6572 } 6573 6574 /** 6575 * t4_get_chan_txrate - get the current per channel Tx rates 6576 * @adap: the adapter 6577 * @nic_rate: rates for NIC traffic 6578 * @ofld_rate: rates for offloaded traffic 6579 * 6580 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6581 * for each channel. 6582 */ 6583 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6584 { 6585 u32 v; 6586 6587 v = t4_read_reg(adap, A_TP_TX_TRATE); 6588 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6589 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6590 if (adap->chip_params->nchan > 2) { 6591 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6592 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6593 } 6594 6595 v = t4_read_reg(adap, A_TP_TX_ORATE); 6596 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6597 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6598 if (adap->chip_params->nchan > 2) { 6599 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6600 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6601 } 6602 } 6603 6604 /** 6605 * t4_set_trace_filter - configure one of the tracing filters 6606 * @adap: the adapter 6607 * @tp: the desired trace filter parameters 6608 * @idx: which filter to configure 6609 * @enable: whether to enable or disable the filter 6610 * 6611 * Configures one of the tracing filters available in HW. If @tp is %NULL 6612 * it indicates that the filter is already written in the register and it 6613 * just needs to be enabled or disabled. 6614 */ 6615 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6616 int idx, int enable) 6617 { 6618 int i, ofst = idx * 4; 6619 u32 data_reg, mask_reg, cfg; 6620 u32 multitrc = F_TRCMULTIFILTER; 6621 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6622 6623 if (idx < 0 || idx >= NTRACE) 6624 return -EINVAL; 6625 6626 if (tp == NULL || !enable) { 6627 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6628 enable ? en : 0); 6629 return 0; 6630 } 6631 6632 /* 6633 * TODO - After T4 data book is updated, specify the exact 6634 * section below. 6635 * 6636 * See T4 data book - MPS section for a complete description 6637 * of the below if..else handling of A_MPS_TRC_CFG register 6638 * value. 6639 */ 6640 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6641 if (cfg & F_TRCMULTIFILTER) { 6642 /* 6643 * If multiple tracers are enabled, then maximum 6644 * capture size is 2.5KB (FIFO size of a single channel) 6645 * minus 2 flits for CPL_TRACE_PKT header. 6646 */ 6647 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6648 return -EINVAL; 6649 } else { 6650 /* 6651 * If multiple tracers are disabled, to avoid deadlocks 6652 * maximum packet capture size of 9600 bytes is recommended. 6653 * Also in this mode, only trace0 can be enabled and running. 6654 */ 6655 multitrc = 0; 6656 if (tp->snap_len > 9600 || idx) 6657 return -EINVAL; 6658 } 6659 6660 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6661 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6662 tp->min_len > M_TFMINPKTSIZE) 6663 return -EINVAL; 6664 6665 /* stop the tracer we'll be changing */ 6666 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6667 6668 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6669 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6670 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6671 6672 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6673 t4_write_reg(adap, data_reg, tp->data[i]); 6674 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6675 } 6676 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6677 V_TFCAPTUREMAX(tp->snap_len) | 6678 V_TFMINPKTSIZE(tp->min_len)); 6679 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6680 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6681 (is_t4(adap) ? 6682 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6683 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6684 6685 return 0; 6686 } 6687 6688 /** 6689 * t4_get_trace_filter - query one of the tracing filters 6690 * @adap: the adapter 6691 * @tp: the current trace filter parameters 6692 * @idx: which trace filter to query 6693 * @enabled: non-zero if the filter is enabled 6694 * 6695 * Returns the current settings of one of the HW tracing filters. 6696 */ 6697 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6698 int *enabled) 6699 { 6700 u32 ctla, ctlb; 6701 int i, ofst = idx * 4; 6702 u32 data_reg, mask_reg; 6703 6704 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6705 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6706 6707 if (is_t4(adap)) { 6708 *enabled = !!(ctla & F_TFEN); 6709 tp->port = G_TFPORT(ctla); 6710 tp->invert = !!(ctla & F_TFINVERTMATCH); 6711 } else { 6712 *enabled = !!(ctla & F_T5_TFEN); 6713 tp->port = G_T5_TFPORT(ctla); 6714 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6715 } 6716 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6717 tp->min_len = G_TFMINPKTSIZE(ctlb); 6718 tp->skip_ofst = G_TFOFFSET(ctla); 6719 tp->skip_len = G_TFLENGTH(ctla); 6720 6721 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6722 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6723 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6724 6725 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6726 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6727 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6728 } 6729 } 6730 6731 /** 6732 * t4_pmtx_get_stats - returns the HW stats from PMTX 6733 * @adap: the adapter 6734 * @cnt: where to store the count statistics 6735 * @cycles: where to store the cycle statistics 6736 * 6737 * Returns performance statistics from PMTX. 6738 */ 6739 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6740 { 6741 int i; 6742 u32 data[2]; 6743 6744 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6745 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6746 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6747 if (is_t4(adap)) 6748 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6749 else { 6750 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6751 A_PM_TX_DBG_DATA, data, 2, 6752 A_PM_TX_DBG_STAT_MSB); 6753 cycles[i] = (((u64)data[0] << 32) | data[1]); 6754 } 6755 } 6756 } 6757 6758 /** 6759 * t4_pmrx_get_stats - returns the HW stats from PMRX 6760 * @adap: the adapter 6761 * @cnt: where to store the count statistics 6762 * @cycles: where to store the cycle statistics 6763 * 6764 * Returns performance statistics from PMRX. 6765 */ 6766 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6767 { 6768 int i; 6769 u32 data[2]; 6770 6771 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6772 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6773 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6774 if (is_t4(adap)) { 6775 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6776 } else { 6777 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6778 A_PM_RX_DBG_DATA, data, 2, 6779 A_PM_RX_DBG_STAT_MSB); 6780 cycles[i] = (((u64)data[0] << 32) | data[1]); 6781 } 6782 } 6783 } 6784 6785 /** 6786 * t4_get_mps_bg_map - return the buffer groups associated with a port 6787 * @adap: the adapter 6788 * @idx: the port index 6789 * 6790 * Returns a bitmap indicating which MPS buffer groups are associated 6791 * with the given port. Bit i is set if buffer group i is used by the 6792 * port. 6793 */ 6794 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6795 { 6796 u32 n; 6797 6798 if (adap->params.mps_bg_map) 6799 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6800 6801 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6802 if (n == 0) 6803 return idx == 0 ? 0xf : 0; 6804 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6805 return idx < 2 ? (3 << (2 * idx)) : 0; 6806 return 1 << idx; 6807 } 6808 6809 /* 6810 * TP RX e-channels associated with the port. 6811 */ 6812 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6813 { 6814 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6815 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; 6816 6817 if (n == 0) 6818 return idx == 0 ? all_chan : 0; 6819 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6820 return idx < 2 ? (3 << (2 * idx)) : 0; 6821 return 1 << idx; 6822 } 6823 6824 /* 6825 * TP RX c-channel associated with the port. 6826 */ 6827 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx) 6828 { 6829 u32 param, val; 6830 int ret; 6831 6832 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6833 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP)); 6834 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 6835 if (!ret) 6836 return (val >> (8 * idx)) & 0xff; 6837 6838 return 0; 6839 } 6840 6841 /** 6842 * t4_get_port_type_description - return Port Type string description 6843 * @port_type: firmware Port Type enumeration 6844 */ 6845 const char *t4_get_port_type_description(enum fw_port_type port_type) 6846 { 6847 static const char *const port_type_description[] = { 6848 "Fiber_XFI", 6849 "Fiber_XAUI", 6850 "BT_SGMII", 6851 "BT_XFI", 6852 "BT_XAUI", 6853 "KX4", 6854 "CX4", 6855 "KX", 6856 "KR", 6857 "SFP", 6858 "BP_AP", 6859 "BP4_AP", 6860 "QSFP_10G", 6861 "QSA", 6862 "QSFP", 6863 "BP40_BA", 6864 "KR4_100G", 6865 "CR4_QSFP", 6866 "CR_QSFP", 6867 "CR2_QSFP", 6868 "SFP28", 6869 "KR_SFP28", 6870 }; 6871 6872 if (port_type < ARRAY_SIZE(port_type_description)) 6873 return port_type_description[port_type]; 6874 return "UNKNOWN"; 6875 } 6876 6877 /** 6878 * t4_get_port_stats_offset - collect port stats relative to a previous 6879 * snapshot 6880 * @adap: The adapter 6881 * @idx: The port 6882 * @stats: Current stats to fill 6883 * @offset: Previous stats snapshot 6884 */ 6885 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6886 struct port_stats *stats, 6887 struct port_stats *offset) 6888 { 6889 u64 *s, *o; 6890 int i; 6891 6892 t4_get_port_stats(adap, idx, stats); 6893 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6894 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6895 i++, s++, o++) 6896 *s -= *o; 6897 } 6898 6899 /** 6900 * t4_get_port_stats - collect port statistics 6901 * @adap: the adapter 6902 * @idx: the port index 6903 * @p: the stats structure to fill 6904 * 6905 * Collect statistics related to the given port from HW. 6906 */ 6907 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6908 { 6909 struct port_info *pi = adap->port[idx]; 6910 u32 bgmap = pi->mps_bg_map; 6911 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6912 6913 #define GET_STAT(name) \ 6914 t4_read_reg64(adap, \ 6915 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6916 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6917 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6918 6919 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6920 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6921 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6922 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6923 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6924 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6925 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6926 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6927 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6928 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6929 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6930 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6931 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6932 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6933 p->tx_drop = GET_STAT(TX_PORT_DROP); 6934 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6935 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6936 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6937 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6938 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6939 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6940 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6941 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6942 6943 if (chip_id(adap) >= CHELSIO_T5) { 6944 if (stat_ctl & F_COUNTPAUSESTATTX) { 6945 p->tx_frames -= p->tx_pause; 6946 p->tx_octets -= p->tx_pause * 64; 6947 } 6948 if (stat_ctl & F_COUNTPAUSEMCTX) 6949 p->tx_mcast_frames -= p->tx_pause; 6950 } 6951 6952 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6953 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6954 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6955 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6956 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6957 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6958 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6959 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6960 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6961 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6962 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6963 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6964 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6965 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6966 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6967 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6968 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6969 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6970 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6971 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6972 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6973 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6974 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6975 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6976 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6977 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6978 6979 if (pi->fcs_reg != -1) 6980 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; 6981 6982 if (chip_id(adap) >= CHELSIO_T5) { 6983 if (stat_ctl & F_COUNTPAUSESTATRX) { 6984 p->rx_frames -= p->rx_pause; 6985 p->rx_octets -= p->rx_pause * 64; 6986 } 6987 if (stat_ctl & F_COUNTPAUSEMCRX) 6988 p->rx_mcast_frames -= p->rx_pause; 6989 } 6990 6991 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6992 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6993 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6994 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6995 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6996 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6997 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6998 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6999 7000 #undef GET_STAT 7001 #undef GET_STAT_COM 7002 } 7003 7004 /** 7005 * t4_get_lb_stats - collect loopback port statistics 7006 * @adap: the adapter 7007 * @idx: the loopback port index 7008 * @p: the stats structure to fill 7009 * 7010 * Return HW statistics for the given loopback port. 7011 */ 7012 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 7013 { 7014 7015 #define GET_STAT(name) \ 7016 t4_read_reg64(adap, \ 7017 (is_t4(adap) ? \ 7018 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 7019 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 7020 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 7021 7022 p->octets = GET_STAT(BYTES); 7023 p->frames = GET_STAT(FRAMES); 7024 p->bcast_frames = GET_STAT(BCAST); 7025 p->mcast_frames = GET_STAT(MCAST); 7026 p->ucast_frames = GET_STAT(UCAST); 7027 p->error_frames = GET_STAT(ERROR); 7028 7029 p->frames_64 = GET_STAT(64B); 7030 p->frames_65_127 = GET_STAT(65B_127B); 7031 p->frames_128_255 = GET_STAT(128B_255B); 7032 p->frames_256_511 = GET_STAT(256B_511B); 7033 p->frames_512_1023 = GET_STAT(512B_1023B); 7034 p->frames_1024_1518 = GET_STAT(1024B_1518B); 7035 p->frames_1519_max = GET_STAT(1519B_MAX); 7036 p->drop = GET_STAT(DROP_FRAMES); 7037 7038 if (idx < adap->params.nports) { 7039 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; 7040 7041 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 7042 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 7043 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 7044 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 7045 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 7046 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 7047 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 7048 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 7049 } 7050 7051 #undef GET_STAT 7052 #undef GET_STAT_COM 7053 } 7054 7055 /** 7056 * t4_wol_magic_enable - enable/disable magic packet WoL 7057 * @adap: the adapter 7058 * @port: the physical port index 7059 * @addr: MAC address expected in magic packets, %NULL to disable 7060 * 7061 * Enables/disables magic packet wake-on-LAN for the selected port. 7062 */ 7063 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 7064 const u8 *addr) 7065 { 7066 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 7067 7068 if (is_t4(adap)) { 7069 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 7070 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 7071 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7072 } else { 7073 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 7074 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 7075 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7076 } 7077 7078 if (addr) { 7079 t4_write_reg(adap, mag_id_reg_l, 7080 (addr[2] << 24) | (addr[3] << 16) | 7081 (addr[4] << 8) | addr[5]); 7082 t4_write_reg(adap, mag_id_reg_h, 7083 (addr[0] << 8) | addr[1]); 7084 } 7085 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 7086 V_MAGICEN(addr != NULL)); 7087 } 7088 7089 /** 7090 * t4_wol_pat_enable - enable/disable pattern-based WoL 7091 * @adap: the adapter 7092 * @port: the physical port index 7093 * @map: bitmap of which HW pattern filters to set 7094 * @mask0: byte mask for bytes 0-63 of a packet 7095 * @mask1: byte mask for bytes 64-127 of a packet 7096 * @crc: Ethernet CRC for selected bytes 7097 * @enable: enable/disable switch 7098 * 7099 * Sets the pattern filters indicated in @map to mask out the bytes 7100 * specified in @mask0/@mask1 in received packets and compare the CRC of 7101 * the resulting packet against @crc. If @enable is %true pattern-based 7102 * WoL is enabled, otherwise disabled. 7103 */ 7104 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 7105 u64 mask0, u64 mask1, unsigned int crc, bool enable) 7106 { 7107 int i; 7108 u32 port_cfg_reg; 7109 7110 if (is_t4(adap)) 7111 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7112 else 7113 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7114 7115 if (!enable) { 7116 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7117 return 0; 7118 } 7119 if (map > 0xff) 7120 return -EINVAL; 7121 7122 #define EPIO_REG(name) \ 7123 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7124 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7125 7126 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7127 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7128 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7129 7130 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7131 if (!(map & 1)) 7132 continue; 7133 7134 /* write byte masks */ 7135 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7136 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7137 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7138 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7139 return -ETIMEDOUT; 7140 7141 /* write CRC */ 7142 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7143 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7144 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7145 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7146 return -ETIMEDOUT; 7147 } 7148 #undef EPIO_REG 7149 7150 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7151 return 0; 7152 } 7153 7154 /* t4_mk_filtdelwr - create a delete filter WR 7155 * @ftid: the filter ID 7156 * @wr: the filter work request to populate 7157 * @qid: ingress queue to receive the delete notification 7158 * 7159 * Creates a filter work request to delete the supplied filter. If @qid is 7160 * negative the delete notification is suppressed. 7161 */ 7162 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7163 { 7164 memset(wr, 0, sizeof(*wr)); 7165 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7166 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7167 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7168 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7169 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7170 if (qid >= 0) 7171 wr->rx_chan_rx_rpl_iq = 7172 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7173 } 7174 7175 #define INIT_CMD(var, cmd, rd_wr) do { \ 7176 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7177 F_FW_CMD_REQUEST | \ 7178 F_FW_CMD_##rd_wr); \ 7179 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7180 } while (0) 7181 7182 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7183 u32 addr, u32 val) 7184 { 7185 u32 ldst_addrspace; 7186 struct fw_ldst_cmd c; 7187 7188 memset(&c, 0, sizeof(c)); 7189 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7190 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7191 F_FW_CMD_REQUEST | 7192 F_FW_CMD_WRITE | 7193 ldst_addrspace); 7194 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7195 c.u.addrval.addr = cpu_to_be32(addr); 7196 c.u.addrval.val = cpu_to_be32(val); 7197 7198 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7199 } 7200 7201 /** 7202 * t4_mdio_rd - read a PHY register through MDIO 7203 * @adap: the adapter 7204 * @mbox: mailbox to use for the FW command 7205 * @phy_addr: the PHY address 7206 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7207 * @reg: the register to read 7208 * @valp: where to store the value 7209 * 7210 * Issues a FW command through the given mailbox to read a PHY register. 7211 */ 7212 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7213 unsigned int mmd, unsigned int reg, unsigned int *valp) 7214 { 7215 int ret; 7216 u32 ldst_addrspace; 7217 struct fw_ldst_cmd c; 7218 7219 memset(&c, 0, sizeof(c)); 7220 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7221 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7222 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7223 ldst_addrspace); 7224 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7225 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7226 V_FW_LDST_CMD_MMD(mmd)); 7227 c.u.mdio.raddr = cpu_to_be16(reg); 7228 7229 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7230 if (ret == 0) 7231 *valp = be16_to_cpu(c.u.mdio.rval); 7232 return ret; 7233 } 7234 7235 /** 7236 * t4_mdio_wr - write a PHY register through MDIO 7237 * @adap: the adapter 7238 * @mbox: mailbox to use for the FW command 7239 * @phy_addr: the PHY address 7240 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7241 * @reg: the register to write 7242 * @valp: value to write 7243 * 7244 * Issues a FW command through the given mailbox to write a PHY register. 7245 */ 7246 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7247 unsigned int mmd, unsigned int reg, unsigned int val) 7248 { 7249 u32 ldst_addrspace; 7250 struct fw_ldst_cmd c; 7251 7252 memset(&c, 0, sizeof(c)); 7253 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7254 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7255 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7256 ldst_addrspace); 7257 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7258 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7259 V_FW_LDST_CMD_MMD(mmd)); 7260 c.u.mdio.raddr = cpu_to_be16(reg); 7261 c.u.mdio.rval = cpu_to_be16(val); 7262 7263 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7264 } 7265 7266 /** 7267 * 7268 * t4_sge_decode_idma_state - decode the idma state 7269 * @adap: the adapter 7270 * @state: the state idma is stuck in 7271 */ 7272 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7273 { 7274 static const char * const t4_decode[] = { 7275 "IDMA_IDLE", 7276 "IDMA_PUSH_MORE_CPL_FIFO", 7277 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7278 "Not used", 7279 "IDMA_PHYSADDR_SEND_PCIEHDR", 7280 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7281 "IDMA_PHYSADDR_SEND_PAYLOAD", 7282 "IDMA_SEND_FIFO_TO_IMSG", 7283 "IDMA_FL_REQ_DATA_FL_PREP", 7284 "IDMA_FL_REQ_DATA_FL", 7285 "IDMA_FL_DROP", 7286 "IDMA_FL_H_REQ_HEADER_FL", 7287 "IDMA_FL_H_SEND_PCIEHDR", 7288 "IDMA_FL_H_PUSH_CPL_FIFO", 7289 "IDMA_FL_H_SEND_CPL", 7290 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7291 "IDMA_FL_H_SEND_IP_HDR", 7292 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7293 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7294 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7295 "IDMA_FL_D_SEND_PCIEHDR", 7296 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7297 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7298 "IDMA_FL_SEND_PCIEHDR", 7299 "IDMA_FL_PUSH_CPL_FIFO", 7300 "IDMA_FL_SEND_CPL", 7301 "IDMA_FL_SEND_PAYLOAD_FIRST", 7302 "IDMA_FL_SEND_PAYLOAD", 7303 "IDMA_FL_REQ_NEXT_DATA_FL", 7304 "IDMA_FL_SEND_NEXT_PCIEHDR", 7305 "IDMA_FL_SEND_PADDING", 7306 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7307 "IDMA_FL_SEND_FIFO_TO_IMSG", 7308 "IDMA_FL_REQ_DATAFL_DONE", 7309 "IDMA_FL_REQ_HEADERFL_DONE", 7310 }; 7311 static const char * const t5_decode[] = { 7312 "IDMA_IDLE", 7313 "IDMA_ALMOST_IDLE", 7314 "IDMA_PUSH_MORE_CPL_FIFO", 7315 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7316 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7317 "IDMA_PHYSADDR_SEND_PCIEHDR", 7318 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7319 "IDMA_PHYSADDR_SEND_PAYLOAD", 7320 "IDMA_SEND_FIFO_TO_IMSG", 7321 "IDMA_FL_REQ_DATA_FL", 7322 "IDMA_FL_DROP", 7323 "IDMA_FL_DROP_SEND_INC", 7324 "IDMA_FL_H_REQ_HEADER_FL", 7325 "IDMA_FL_H_SEND_PCIEHDR", 7326 "IDMA_FL_H_PUSH_CPL_FIFO", 7327 "IDMA_FL_H_SEND_CPL", 7328 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7329 "IDMA_FL_H_SEND_IP_HDR", 7330 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7331 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7332 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7333 "IDMA_FL_D_SEND_PCIEHDR", 7334 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7335 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7336 "IDMA_FL_SEND_PCIEHDR", 7337 "IDMA_FL_PUSH_CPL_FIFO", 7338 "IDMA_FL_SEND_CPL", 7339 "IDMA_FL_SEND_PAYLOAD_FIRST", 7340 "IDMA_FL_SEND_PAYLOAD", 7341 "IDMA_FL_REQ_NEXT_DATA_FL", 7342 "IDMA_FL_SEND_NEXT_PCIEHDR", 7343 "IDMA_FL_SEND_PADDING", 7344 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7345 }; 7346 static const char * const t6_decode[] = { 7347 "IDMA_IDLE", 7348 "IDMA_PUSH_MORE_CPL_FIFO", 7349 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7350 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7351 "IDMA_PHYSADDR_SEND_PCIEHDR", 7352 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7353 "IDMA_PHYSADDR_SEND_PAYLOAD", 7354 "IDMA_FL_REQ_DATA_FL", 7355 "IDMA_FL_DROP", 7356 "IDMA_FL_DROP_SEND_INC", 7357 "IDMA_FL_H_REQ_HEADER_FL", 7358 "IDMA_FL_H_SEND_PCIEHDR", 7359 "IDMA_FL_H_PUSH_CPL_FIFO", 7360 "IDMA_FL_H_SEND_CPL", 7361 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7362 "IDMA_FL_H_SEND_IP_HDR", 7363 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7364 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7365 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7366 "IDMA_FL_D_SEND_PCIEHDR", 7367 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7368 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7369 "IDMA_FL_SEND_PCIEHDR", 7370 "IDMA_FL_PUSH_CPL_FIFO", 7371 "IDMA_FL_SEND_CPL", 7372 "IDMA_FL_SEND_PAYLOAD_FIRST", 7373 "IDMA_FL_SEND_PAYLOAD", 7374 "IDMA_FL_REQ_NEXT_DATA_FL", 7375 "IDMA_FL_SEND_NEXT_PCIEHDR", 7376 "IDMA_FL_SEND_PADDING", 7377 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7378 }; 7379 static const u32 sge_regs[] = { 7380 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7381 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7382 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7383 }; 7384 const char * const *sge_idma_decode; 7385 int sge_idma_decode_nstates; 7386 int i; 7387 unsigned int chip_version = chip_id(adapter); 7388 7389 /* Select the right set of decode strings to dump depending on the 7390 * adapter chip type. 7391 */ 7392 switch (chip_version) { 7393 case CHELSIO_T4: 7394 sge_idma_decode = (const char * const *)t4_decode; 7395 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7396 break; 7397 7398 case CHELSIO_T5: 7399 sge_idma_decode = (const char * const *)t5_decode; 7400 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7401 break; 7402 7403 case CHELSIO_T6: 7404 sge_idma_decode = (const char * const *)t6_decode; 7405 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7406 break; 7407 7408 default: 7409 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7410 return; 7411 } 7412 7413 if (state < sge_idma_decode_nstates) 7414 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7415 else 7416 CH_WARN(adapter, "idma state %d unknown\n", state); 7417 7418 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7419 CH_WARN(adapter, "SGE register %#x value %#x\n", 7420 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7421 } 7422 7423 /** 7424 * t4_sge_ctxt_flush - flush the SGE context cache 7425 * @adap: the adapter 7426 * @mbox: mailbox to use for the FW command 7427 * 7428 * Issues a FW command through the given mailbox to flush the 7429 * SGE context cache. 7430 */ 7431 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type) 7432 { 7433 int ret; 7434 u32 ldst_addrspace; 7435 struct fw_ldst_cmd c; 7436 7437 memset(&c, 0, sizeof(c)); 7438 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ? 7439 FW_LDST_ADDRSPC_SGE_EGRC : 7440 FW_LDST_ADDRSPC_SGE_INGC); 7441 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7442 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7443 ldst_addrspace); 7444 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7445 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7446 7447 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7448 return ret; 7449 } 7450 7451 /** 7452 * t4_fw_hello - establish communication with FW 7453 * @adap: the adapter 7454 * @mbox: mailbox to use for the FW command 7455 * @evt_mbox: mailbox to receive async FW events 7456 * @master: specifies the caller's willingness to be the device master 7457 * @state: returns the current device state (if non-NULL) 7458 * 7459 * Issues a command to establish communication with FW. Returns either 7460 * an error (negative integer) or the mailbox of the Master PF. 7461 */ 7462 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7463 enum dev_master master, enum dev_state *state) 7464 { 7465 int ret; 7466 struct fw_hello_cmd c; 7467 u32 v; 7468 unsigned int master_mbox; 7469 int retries = FW_CMD_HELLO_RETRIES; 7470 7471 retry: 7472 memset(&c, 0, sizeof(c)); 7473 INIT_CMD(c, HELLO, WRITE); 7474 c.err_to_clearinit = cpu_to_be32( 7475 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7476 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7477 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7478 mbox : M_FW_HELLO_CMD_MBMASTER) | 7479 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7480 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7481 F_FW_HELLO_CMD_CLEARINIT); 7482 7483 /* 7484 * Issue the HELLO command to the firmware. If it's not successful 7485 * but indicates that we got a "busy" or "timeout" condition, retry 7486 * the HELLO until we exhaust our retry limit. If we do exceed our 7487 * retry limit, check to see if the firmware left us any error 7488 * information and report that if so ... 7489 */ 7490 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7491 if (ret != FW_SUCCESS) { 7492 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7493 goto retry; 7494 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7495 t4_report_fw_error(adap); 7496 return ret; 7497 } 7498 7499 v = be32_to_cpu(c.err_to_clearinit); 7500 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7501 if (state) { 7502 if (v & F_FW_HELLO_CMD_ERR) 7503 *state = DEV_STATE_ERR; 7504 else if (v & F_FW_HELLO_CMD_INIT) 7505 *state = DEV_STATE_INIT; 7506 else 7507 *state = DEV_STATE_UNINIT; 7508 } 7509 7510 /* 7511 * If we're not the Master PF then we need to wait around for the 7512 * Master PF Driver to finish setting up the adapter. 7513 * 7514 * Note that we also do this wait if we're a non-Master-capable PF and 7515 * there is no current Master PF; a Master PF may show up momentarily 7516 * and we wouldn't want to fail pointlessly. (This can happen when an 7517 * OS loads lots of different drivers rapidly at the same time). In 7518 * this case, the Master PF returned by the firmware will be 7519 * M_PCIE_FW_MASTER so the test below will work ... 7520 */ 7521 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7522 master_mbox != mbox) { 7523 int waiting = FW_CMD_HELLO_TIMEOUT; 7524 7525 /* 7526 * Wait for the firmware to either indicate an error or 7527 * initialized state. If we see either of these we bail out 7528 * and report the issue to the caller. If we exhaust the 7529 * "hello timeout" and we haven't exhausted our retries, try 7530 * again. Otherwise bail with a timeout error. 7531 */ 7532 for (;;) { 7533 u32 pcie_fw; 7534 7535 msleep(50); 7536 waiting -= 50; 7537 7538 /* 7539 * If neither Error nor Initialialized are indicated 7540 * by the firmware keep waiting till we exhaust our 7541 * timeout ... and then retry if we haven't exhausted 7542 * our retries ... 7543 */ 7544 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7545 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7546 if (waiting <= 0) { 7547 if (retries-- > 0) 7548 goto retry; 7549 7550 return -ETIMEDOUT; 7551 } 7552 continue; 7553 } 7554 7555 /* 7556 * We either have an Error or Initialized condition 7557 * report errors preferentially. 7558 */ 7559 if (state) { 7560 if (pcie_fw & F_PCIE_FW_ERR) 7561 *state = DEV_STATE_ERR; 7562 else if (pcie_fw & F_PCIE_FW_INIT) 7563 *state = DEV_STATE_INIT; 7564 } 7565 7566 /* 7567 * If we arrived before a Master PF was selected and 7568 * there's not a valid Master PF, grab its identity 7569 * for our caller. 7570 */ 7571 if (master_mbox == M_PCIE_FW_MASTER && 7572 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7573 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7574 break; 7575 } 7576 } 7577 7578 return master_mbox; 7579 } 7580 7581 /** 7582 * t4_fw_bye - end communication with FW 7583 * @adap: the adapter 7584 * @mbox: mailbox to use for the FW command 7585 * 7586 * Issues a command to terminate communication with FW. 7587 */ 7588 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7589 { 7590 struct fw_bye_cmd c; 7591 7592 memset(&c, 0, sizeof(c)); 7593 INIT_CMD(c, BYE, WRITE); 7594 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7595 } 7596 7597 /** 7598 * t4_fw_reset - issue a reset to FW 7599 * @adap: the adapter 7600 * @mbox: mailbox to use for the FW command 7601 * @reset: specifies the type of reset to perform 7602 * 7603 * Issues a reset command of the specified type to FW. 7604 */ 7605 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7606 { 7607 struct fw_reset_cmd c; 7608 7609 memset(&c, 0, sizeof(c)); 7610 INIT_CMD(c, RESET, WRITE); 7611 c.val = cpu_to_be32(reset); 7612 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7613 } 7614 7615 /** 7616 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7617 * @adap: the adapter 7618 * @mbox: mailbox to use for the FW RESET command (if desired) 7619 * @force: force uP into RESET even if FW RESET command fails 7620 * 7621 * Issues a RESET command to firmware (if desired) with a HALT indication 7622 * and then puts the microprocessor into RESET state. The RESET command 7623 * will only be issued if a legitimate mailbox is provided (mbox <= 7624 * M_PCIE_FW_MASTER). 7625 * 7626 * This is generally used in order for the host to safely manipulate the 7627 * adapter without fear of conflicting with whatever the firmware might 7628 * be doing. The only way out of this state is to RESTART the firmware 7629 * ... 7630 */ 7631 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7632 { 7633 int ret = 0; 7634 7635 /* 7636 * If a legitimate mailbox is provided, issue a RESET command 7637 * with a HALT indication. 7638 */ 7639 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7640 struct fw_reset_cmd c; 7641 7642 memset(&c, 0, sizeof(c)); 7643 INIT_CMD(c, RESET, WRITE); 7644 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7645 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7646 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7647 } 7648 7649 /* 7650 * Normally we won't complete the operation if the firmware RESET 7651 * command fails but if our caller insists we'll go ahead and put the 7652 * uP into RESET. This can be useful if the firmware is hung or even 7653 * missing ... We'll have to take the risk of putting the uP into 7654 * RESET without the cooperation of firmware in that case. 7655 * 7656 * We also force the firmware's HALT flag to be on in case we bypassed 7657 * the firmware RESET command above or we're dealing with old firmware 7658 * which doesn't have the HALT capability. This will serve as a flag 7659 * for the incoming firmware to know that it's coming out of a HALT 7660 * rather than a RESET ... if it's new enough to understand that ... 7661 */ 7662 if (ret == 0 || force) { 7663 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7664 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7665 F_PCIE_FW_HALT); 7666 } 7667 7668 /* 7669 * And we always return the result of the firmware RESET command 7670 * even when we force the uP into RESET ... 7671 */ 7672 return ret; 7673 } 7674 7675 /** 7676 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7677 * @adap: the adapter 7678 * 7679 * Restart firmware previously halted by t4_fw_halt(). On successful 7680 * return the previous PF Master remains as the new PF Master and there 7681 * is no need to issue a new HELLO command, etc. 7682 */ 7683 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7684 { 7685 int ms; 7686 7687 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7688 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7689 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7690 return FW_SUCCESS; 7691 msleep(100); 7692 ms += 100; 7693 } 7694 7695 return -ETIMEDOUT; 7696 } 7697 7698 /** 7699 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7700 * @adap: the adapter 7701 * @mbox: mailbox to use for the FW RESET command (if desired) 7702 * @fw_data: the firmware image to write 7703 * @size: image size 7704 * @force: force upgrade even if firmware doesn't cooperate 7705 * 7706 * Perform all of the steps necessary for upgrading an adapter's 7707 * firmware image. Normally this requires the cooperation of the 7708 * existing firmware in order to halt all existing activities 7709 * but if an invalid mailbox token is passed in we skip that step 7710 * (though we'll still put the adapter microprocessor into RESET in 7711 * that case). 7712 * 7713 * On successful return the new firmware will have been loaded and 7714 * the adapter will have been fully RESET losing all previous setup 7715 * state. On unsuccessful return the adapter may be completely hosed ... 7716 * positive errno indicates that the adapter is ~probably~ intact, a 7717 * negative errno indicates that things are looking bad ... 7718 */ 7719 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7720 const u8 *fw_data, unsigned int size, int force) 7721 { 7722 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7723 unsigned int bootstrap = 7724 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7725 int ret; 7726 7727 if (!t4_fw_matches_chip(adap, fw_hdr)) 7728 return -EINVAL; 7729 7730 if (!bootstrap) { 7731 ret = t4_fw_halt(adap, mbox, force); 7732 if (ret < 0 && !force) 7733 return ret; 7734 } 7735 7736 ret = t4_load_fw(adap, fw_data, size); 7737 if (ret < 0 || bootstrap) 7738 return ret; 7739 7740 return t4_fw_restart(adap, mbox); 7741 } 7742 7743 /** 7744 * t4_fw_initialize - ask FW to initialize the device 7745 * @adap: the adapter 7746 * @mbox: mailbox to use for the FW command 7747 * 7748 * Issues a command to FW to partially initialize the device. This 7749 * performs initialization that generally doesn't depend on user input. 7750 */ 7751 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7752 { 7753 struct fw_initialize_cmd c; 7754 7755 memset(&c, 0, sizeof(c)); 7756 INIT_CMD(c, INITIALIZE, WRITE); 7757 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7758 } 7759 7760 /** 7761 * t4_query_params_rw - query FW or device parameters 7762 * @adap: the adapter 7763 * @mbox: mailbox to use for the FW command 7764 * @pf: the PF 7765 * @vf: the VF 7766 * @nparams: the number of parameters 7767 * @params: the parameter names 7768 * @val: the parameter values 7769 * @rw: Write and read flag 7770 * 7771 * Reads the value of FW or device parameters. Up to 7 parameters can be 7772 * queried at once. 7773 */ 7774 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7775 unsigned int vf, unsigned int nparams, const u32 *params, 7776 u32 *val, int rw) 7777 { 7778 int i, ret; 7779 struct fw_params_cmd c; 7780 __be32 *p = &c.param[0].mnem; 7781 7782 if (nparams > 7) 7783 return -EINVAL; 7784 7785 memset(&c, 0, sizeof(c)); 7786 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7787 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7788 V_FW_PARAMS_CMD_PFN(pf) | 7789 V_FW_PARAMS_CMD_VFN(vf)); 7790 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7791 7792 for (i = 0; i < nparams; i++) { 7793 *p++ = cpu_to_be32(*params++); 7794 if (rw) 7795 *p = cpu_to_be32(*(val + i)); 7796 p++; 7797 } 7798 7799 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7800 if (ret == 0) 7801 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7802 *val++ = be32_to_cpu(*p); 7803 return ret; 7804 } 7805 7806 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7807 unsigned int vf, unsigned int nparams, const u32 *params, 7808 u32 *val) 7809 { 7810 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7811 } 7812 7813 /** 7814 * t4_set_params_timeout - sets FW or device parameters 7815 * @adap: the adapter 7816 * @mbox: mailbox to use for the FW command 7817 * @pf: the PF 7818 * @vf: the VF 7819 * @nparams: the number of parameters 7820 * @params: the parameter names 7821 * @val: the parameter values 7822 * @timeout: the timeout time 7823 * 7824 * Sets the value of FW or device parameters. Up to 7 parameters can be 7825 * specified at once. 7826 */ 7827 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7828 unsigned int pf, unsigned int vf, 7829 unsigned int nparams, const u32 *params, 7830 const u32 *val, int timeout) 7831 { 7832 struct fw_params_cmd c; 7833 __be32 *p = &c.param[0].mnem; 7834 7835 if (nparams > 7) 7836 return -EINVAL; 7837 7838 memset(&c, 0, sizeof(c)); 7839 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7840 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7841 V_FW_PARAMS_CMD_PFN(pf) | 7842 V_FW_PARAMS_CMD_VFN(vf)); 7843 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7844 7845 while (nparams--) { 7846 *p++ = cpu_to_be32(*params++); 7847 *p++ = cpu_to_be32(*val++); 7848 } 7849 7850 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7851 } 7852 7853 /** 7854 * t4_set_params - sets FW or device parameters 7855 * @adap: the adapter 7856 * @mbox: mailbox to use for the FW command 7857 * @pf: the PF 7858 * @vf: the VF 7859 * @nparams: the number of parameters 7860 * @params: the parameter names 7861 * @val: the parameter values 7862 * 7863 * Sets the value of FW or device parameters. Up to 7 parameters can be 7864 * specified at once. 7865 */ 7866 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7867 unsigned int vf, unsigned int nparams, const u32 *params, 7868 const u32 *val) 7869 { 7870 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7871 FW_CMD_MAX_TIMEOUT); 7872 } 7873 7874 /** 7875 * t4_cfg_pfvf - configure PF/VF resource limits 7876 * @adap: the adapter 7877 * @mbox: mailbox to use for the FW command 7878 * @pf: the PF being configured 7879 * @vf: the VF being configured 7880 * @txq: the max number of egress queues 7881 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7882 * @rxqi: the max number of interrupt-capable ingress queues 7883 * @rxq: the max number of interruptless ingress queues 7884 * @tc: the PCI traffic class 7885 * @vi: the max number of virtual interfaces 7886 * @cmask: the channel access rights mask for the PF/VF 7887 * @pmask: the port access rights mask for the PF/VF 7888 * @nexact: the maximum number of exact MPS filters 7889 * @rcaps: read capabilities 7890 * @wxcaps: write/execute capabilities 7891 * 7892 * Configures resource limits and capabilities for a physical or virtual 7893 * function. 7894 */ 7895 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7896 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7897 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7898 unsigned int vi, unsigned int cmask, unsigned int pmask, 7899 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7900 { 7901 struct fw_pfvf_cmd c; 7902 7903 memset(&c, 0, sizeof(c)); 7904 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7905 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7906 V_FW_PFVF_CMD_VFN(vf)); 7907 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7908 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7909 V_FW_PFVF_CMD_NIQ(rxq)); 7910 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7911 V_FW_PFVF_CMD_PMASK(pmask) | 7912 V_FW_PFVF_CMD_NEQ(txq)); 7913 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7914 V_FW_PFVF_CMD_NVI(vi) | 7915 V_FW_PFVF_CMD_NEXACTF(nexact)); 7916 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7917 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7918 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7919 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7920 } 7921 7922 /** 7923 * t4_alloc_vi_func - allocate a virtual interface 7924 * @adap: the adapter 7925 * @mbox: mailbox to use for the FW command 7926 * @port: physical port associated with the VI 7927 * @pf: the PF owning the VI 7928 * @vf: the VF owning the VI 7929 * @nmac: number of MAC addresses needed (1 to 5) 7930 * @mac: the MAC addresses of the VI 7931 * @rss_size: size of RSS table slice associated with this VI 7932 * @portfunc: which Port Application Function MAC Address is desired 7933 * @idstype: Intrusion Detection Type 7934 * 7935 * Allocates a virtual interface for the given physical port. If @mac is 7936 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7937 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7938 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7939 * stored consecutively so the space needed is @nmac * 6 bytes. 7940 * Returns a negative error number or the non-negative VI id. 7941 */ 7942 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7943 unsigned int port, unsigned int pf, unsigned int vf, 7944 unsigned int nmac, u8 *mac, u16 *rss_size, 7945 uint8_t *vfvld, uint16_t *vin, 7946 unsigned int portfunc, unsigned int idstype) 7947 { 7948 int ret; 7949 struct fw_vi_cmd c; 7950 7951 memset(&c, 0, sizeof(c)); 7952 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7953 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7954 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7955 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7956 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7957 V_FW_VI_CMD_FUNC(portfunc)); 7958 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7959 c.nmac = nmac - 1; 7960 if(!rss_size) 7961 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7962 7963 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7964 if (ret) 7965 return ret; 7966 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7967 7968 if (mac) { 7969 memcpy(mac, c.mac, sizeof(c.mac)); 7970 switch (nmac) { 7971 case 5: 7972 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7973 case 4: 7974 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7975 case 3: 7976 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7977 case 2: 7978 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7979 } 7980 } 7981 if (rss_size) 7982 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7983 if (vfvld) { 7984 *vfvld = adap->params.viid_smt_extn_support ? 7985 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 7986 G_FW_VIID_VIVLD(ret); 7987 } 7988 if (vin) { 7989 *vin = adap->params.viid_smt_extn_support ? 7990 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 7991 G_FW_VIID_VIN(ret); 7992 } 7993 7994 return ret; 7995 } 7996 7997 /** 7998 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7999 * @adap: the adapter 8000 * @mbox: mailbox to use for the FW command 8001 * @port: physical port associated with the VI 8002 * @pf: the PF owning the VI 8003 * @vf: the VF owning the VI 8004 * @nmac: number of MAC addresses needed (1 to 5) 8005 * @mac: the MAC addresses of the VI 8006 * @rss_size: size of RSS table slice associated with this VI 8007 * 8008 * backwards compatible and convieniance routine to allocate a Virtual 8009 * Interface with a Ethernet Port Application Function and Intrustion 8010 * Detection System disabled. 8011 */ 8012 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 8013 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 8014 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 8015 { 8016 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 8017 vfvld, vin, FW_VI_FUNC_ETH, 0); 8018 } 8019 8020 /** 8021 * t4_free_vi - free a virtual interface 8022 * @adap: the adapter 8023 * @mbox: mailbox to use for the FW command 8024 * @pf: the PF owning the VI 8025 * @vf: the VF owning the VI 8026 * @viid: virtual interface identifiler 8027 * 8028 * Free a previously allocated virtual interface. 8029 */ 8030 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 8031 unsigned int vf, unsigned int viid) 8032 { 8033 struct fw_vi_cmd c; 8034 8035 memset(&c, 0, sizeof(c)); 8036 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 8037 F_FW_CMD_REQUEST | 8038 F_FW_CMD_EXEC | 8039 V_FW_VI_CMD_PFN(pf) | 8040 V_FW_VI_CMD_VFN(vf)); 8041 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 8042 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 8043 8044 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8045 } 8046 8047 /** 8048 * t4_set_rxmode - set Rx properties of a virtual interface 8049 * @adap: the adapter 8050 * @mbox: mailbox to use for the FW command 8051 * @viid: the VI id 8052 * @mtu: the new MTU or -1 8053 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 8054 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 8055 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 8056 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 8057 * @sleep_ok: if true we may sleep while awaiting command completion 8058 * 8059 * Sets Rx properties of a virtual interface. 8060 */ 8061 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 8062 int mtu, int promisc, int all_multi, int bcast, int vlanex, 8063 bool sleep_ok) 8064 { 8065 struct fw_vi_rxmode_cmd c; 8066 8067 /* convert to FW values */ 8068 if (mtu < 0) 8069 mtu = M_FW_VI_RXMODE_CMD_MTU; 8070 if (promisc < 0) 8071 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 8072 if (all_multi < 0) 8073 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 8074 if (bcast < 0) 8075 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 8076 if (vlanex < 0) 8077 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 8078 8079 memset(&c, 0, sizeof(c)); 8080 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 8081 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8082 V_FW_VI_RXMODE_CMD_VIID(viid)); 8083 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 8084 c.mtu_to_vlanexen = 8085 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 8086 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 8087 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 8088 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 8089 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 8090 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8091 } 8092 8093 /** 8094 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support 8095 * @adap: the adapter 8096 * @viid: the VI id 8097 * @mac: the MAC address 8098 * @mask: the mask 8099 * @vni: the VNI id for the tunnel protocol 8100 * @vni_mask: mask for the VNI id 8101 * @dip_hit: to enable DIP match for the MPS entry 8102 * @lookup_type: MAC address for inner (1) or outer (0) header 8103 * @sleep_ok: call is allowed to sleep 8104 * 8105 * Allocates an MPS entry with specified MAC address and VNI value. 8106 * 8107 * Returns a negative error number or the allocated index for this mac. 8108 */ 8109 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 8110 const u8 *addr, const u8 *mask, unsigned int vni, 8111 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 8112 bool sleep_ok) 8113 { 8114 struct fw_vi_mac_cmd c; 8115 struct fw_vi_mac_vni *p = c.u.exact_vni; 8116 int ret = 0; 8117 u32 val; 8118 8119 memset(&c, 0, sizeof(c)); 8120 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8121 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8122 V_FW_VI_MAC_CMD_VIID(viid)); 8123 val = V_FW_CMD_LEN16(1) | 8124 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI); 8125 c.freemacs_to_len16 = cpu_to_be32(val); 8126 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8127 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8128 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8129 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); 8130 8131 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | 8132 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) | 8133 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type)); 8134 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); 8135 8136 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8137 if (ret == 0) 8138 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8139 return ret; 8140 } 8141 8142 /** 8143 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam 8144 * @adap: the adapter 8145 * @viid: the VI id 8146 * @mac: the MAC address 8147 * @mask: the mask 8148 * @idx: index at which to add this entry 8149 * @port_id: the port index 8150 * @lookup_type: MAC address for inner (1) or outer (0) header 8151 * @sleep_ok: call is allowed to sleep 8152 * 8153 * Adds the mac entry at the specified index using raw mac interface. 8154 * 8155 * Returns a negative error number or the allocated index for this mac. 8156 */ 8157 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 8158 const u8 *addr, const u8 *mask, unsigned int idx, 8159 u8 lookup_type, u8 port_id, bool sleep_ok) 8160 { 8161 int ret = 0; 8162 struct fw_vi_mac_cmd c; 8163 struct fw_vi_mac_raw *p = &c.u.raw; 8164 u32 val; 8165 8166 memset(&c, 0, sizeof(c)); 8167 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8168 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8169 V_FW_VI_MAC_CMD_VIID(viid)); 8170 val = V_FW_CMD_LEN16(1) | 8171 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8172 c.freemacs_to_len16 = cpu_to_be32(val); 8173 8174 /* Specify that this is an inner mac address */ 8175 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); 8176 8177 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8178 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8179 V_DATAPORTNUM(port_id)); 8180 /* Lookup mask and port mask */ 8181 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8182 V_DATAPORTNUM(M_DATAPORTNUM)); 8183 8184 /* Copy the address and the mask */ 8185 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8186 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8187 8188 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8189 if (ret == 0) { 8190 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); 8191 if (ret != idx) 8192 ret = -ENOMEM; 8193 } 8194 8195 return ret; 8196 } 8197 8198 /** 8199 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 8200 * @adap: the adapter 8201 * @mbox: mailbox to use for the FW command 8202 * @viid: the VI id 8203 * @free: if true any existing filters for this VI id are first removed 8204 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8205 * @addr: the MAC address(es) 8206 * @idx: where to store the index of each allocated filter 8207 * @hash: pointer to hash address filter bitmap 8208 * @sleep_ok: call is allowed to sleep 8209 * 8210 * Allocates an exact-match filter for each of the supplied addresses and 8211 * sets it to the corresponding address. If @idx is not %NULL it should 8212 * have at least @naddr entries, each of which will be set to the index of 8213 * the filter allocated for the corresponding MAC address. If a filter 8214 * could not be allocated for an address its index is set to 0xffff. 8215 * If @hash is not %NULL addresses that fail to allocate an exact filter 8216 * are hashed and update the hash filter bitmap pointed at by @hash. 8217 * 8218 * Returns a negative error number or the number of filters allocated. 8219 */ 8220 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8221 unsigned int viid, bool free, unsigned int naddr, 8222 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8223 { 8224 int offset, ret = 0; 8225 struct fw_vi_mac_cmd c; 8226 unsigned int nfilters = 0; 8227 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8228 unsigned int rem = naddr; 8229 8230 if (naddr > max_naddr) 8231 return -EINVAL; 8232 8233 for (offset = 0; offset < naddr ; /**/) { 8234 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8235 ? rem 8236 : ARRAY_SIZE(c.u.exact)); 8237 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8238 u.exact[fw_naddr]), 16); 8239 struct fw_vi_mac_exact *p; 8240 int i; 8241 8242 memset(&c, 0, sizeof(c)); 8243 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8244 F_FW_CMD_REQUEST | 8245 F_FW_CMD_WRITE | 8246 V_FW_CMD_EXEC(free) | 8247 V_FW_VI_MAC_CMD_VIID(viid)); 8248 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8249 V_FW_CMD_LEN16(len16)); 8250 8251 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8252 p->valid_to_idx = 8253 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8254 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8255 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8256 } 8257 8258 /* 8259 * It's okay if we run out of space in our MAC address arena. 8260 * Some of the addresses we submit may get stored so we need 8261 * to run through the reply to see what the results were ... 8262 */ 8263 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8264 if (ret && ret != -FW_ENOMEM) 8265 break; 8266 8267 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8268 u16 index = G_FW_VI_MAC_CMD_IDX( 8269 be16_to_cpu(p->valid_to_idx)); 8270 8271 if (idx) 8272 idx[offset+i] = (index >= max_naddr 8273 ? 0xffff 8274 : index); 8275 if (index < max_naddr) 8276 nfilters++; 8277 else if (hash) 8278 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8279 } 8280 8281 free = false; 8282 offset += fw_naddr; 8283 rem -= fw_naddr; 8284 } 8285 8286 if (ret == 0 || ret == -FW_ENOMEM) 8287 ret = nfilters; 8288 return ret; 8289 } 8290 8291 /** 8292 * t4_free_encap_mac_filt - frees MPS entry at given index 8293 * @adap: the adapter 8294 * @viid: the VI id 8295 * @idx: index of MPS entry to be freed 8296 * @sleep_ok: call is allowed to sleep 8297 * 8298 * Frees the MPS entry at supplied index 8299 * 8300 * Returns a negative error number or zero on success 8301 */ 8302 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 8303 int idx, bool sleep_ok) 8304 { 8305 struct fw_vi_mac_exact *p; 8306 struct fw_vi_mac_cmd c; 8307 u8 addr[] = {0,0,0,0,0,0}; 8308 int ret = 0; 8309 u32 exact; 8310 8311 memset(&c, 0, sizeof(c)); 8312 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8313 F_FW_CMD_REQUEST | 8314 F_FW_CMD_WRITE | 8315 V_FW_CMD_EXEC(0) | 8316 V_FW_VI_MAC_CMD_VIID(viid)); 8317 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC); 8318 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8319 exact | 8320 V_FW_CMD_LEN16(1)); 8321 p = c.u.exact; 8322 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8323 V_FW_VI_MAC_CMD_IDX(idx)); 8324 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8325 8326 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8327 return ret; 8328 } 8329 8330 /** 8331 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam 8332 * @adap: the adapter 8333 * @viid: the VI id 8334 * @addr: the MAC address 8335 * @mask: the mask 8336 * @idx: index of the entry in mps tcam 8337 * @lookup_type: MAC address for inner (1) or outer (0) header 8338 * @port_id: the port index 8339 * @sleep_ok: call is allowed to sleep 8340 * 8341 * Removes the mac entry at the specified index using raw mac interface. 8342 * 8343 * Returns a negative error number on failure. 8344 */ 8345 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 8346 const u8 *addr, const u8 *mask, unsigned int idx, 8347 u8 lookup_type, u8 port_id, bool sleep_ok) 8348 { 8349 struct fw_vi_mac_cmd c; 8350 struct fw_vi_mac_raw *p = &c.u.raw; 8351 u32 raw; 8352 8353 memset(&c, 0, sizeof(c)); 8354 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8355 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8356 V_FW_CMD_EXEC(0) | 8357 V_FW_VI_MAC_CMD_VIID(viid)); 8358 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8359 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8360 raw | 8361 V_FW_CMD_LEN16(1)); 8362 8363 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | 8364 FW_VI_MAC_ID_BASED_FREE); 8365 8366 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8367 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8368 V_DATAPORTNUM(port_id)); 8369 /* Lookup mask and port mask */ 8370 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8371 V_DATAPORTNUM(M_DATAPORTNUM)); 8372 8373 /* Copy the address and the mask */ 8374 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8375 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8376 8377 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8378 } 8379 8380 /** 8381 * t4_free_mac_filt - frees exact-match filters of given MAC addresses 8382 * @adap: the adapter 8383 * @mbox: mailbox to use for the FW command 8384 * @viid: the VI id 8385 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8386 * @addr: the MAC address(es) 8387 * @sleep_ok: call is allowed to sleep 8388 * 8389 * Frees the exact-match filter for each of the supplied addresses 8390 * 8391 * Returns a negative error number or the number of filters freed. 8392 */ 8393 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 8394 unsigned int viid, unsigned int naddr, 8395 const u8 **addr, bool sleep_ok) 8396 { 8397 int offset, ret = 0; 8398 struct fw_vi_mac_cmd c; 8399 unsigned int nfilters = 0; 8400 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8401 unsigned int rem = naddr; 8402 8403 if (naddr > max_naddr) 8404 return -EINVAL; 8405 8406 for (offset = 0; offset < (int)naddr ; /**/) { 8407 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8408 ? rem 8409 : ARRAY_SIZE(c.u.exact)); 8410 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8411 u.exact[fw_naddr]), 16); 8412 struct fw_vi_mac_exact *p; 8413 int i; 8414 8415 memset(&c, 0, sizeof(c)); 8416 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8417 F_FW_CMD_REQUEST | 8418 F_FW_CMD_WRITE | 8419 V_FW_CMD_EXEC(0) | 8420 V_FW_VI_MAC_CMD_VIID(viid)); 8421 c.freemacs_to_len16 = 8422 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8423 V_FW_CMD_LEN16(len16)); 8424 8425 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { 8426 p->valid_to_idx = cpu_to_be16( 8427 F_FW_VI_MAC_CMD_VALID | 8428 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 8429 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8430 } 8431 8432 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8433 if (ret) 8434 break; 8435 8436 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8437 u16 index = G_FW_VI_MAC_CMD_IDX( 8438 be16_to_cpu(p->valid_to_idx)); 8439 8440 if (index < max_naddr) 8441 nfilters++; 8442 } 8443 8444 offset += fw_naddr; 8445 rem -= fw_naddr; 8446 } 8447 8448 if (ret == 0) 8449 ret = nfilters; 8450 return ret; 8451 } 8452 8453 /** 8454 * t4_change_mac - modifies the exact-match filter for a MAC address 8455 * @adap: the adapter 8456 * @mbox: mailbox to use for the FW command 8457 * @viid: the VI id 8458 * @idx: index of existing filter for old value of MAC address, or -1 8459 * @addr: the new MAC address value 8460 * @persist: whether a new MAC allocation should be persistent 8461 * @smt_idx: add MAC to SMT and return its index, or NULL 8462 * 8463 * Modifies an exact-match filter and sets it to the new MAC address if 8464 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8465 * latter case the address is added persistently if @persist is %true. 8466 * 8467 * Note that in general it is not possible to modify the value of a given 8468 * filter so the generic way to modify an address filter is to free the one 8469 * being used by the old address value and allocate a new filter for the 8470 * new address value. 8471 * 8472 * Returns a negative error number or the index of the filter with the new 8473 * MAC value. Note that this index may differ from @idx. 8474 */ 8475 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8476 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8477 { 8478 int ret, mode; 8479 struct fw_vi_mac_cmd c; 8480 struct fw_vi_mac_exact *p = c.u.exact; 8481 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8482 8483 if (idx < 0) /* new allocation */ 8484 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8485 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8486 8487 memset(&c, 0, sizeof(c)); 8488 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8489 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8490 V_FW_VI_MAC_CMD_VIID(viid)); 8491 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8492 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8493 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8494 V_FW_VI_MAC_CMD_IDX(idx)); 8495 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8496 8497 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8498 if (ret == 0) { 8499 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8500 if (ret >= max_mac_addr) 8501 ret = -ENOMEM; 8502 if (smt_idx) { 8503 if (adap->params.viid_smt_extn_support) 8504 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8505 else { 8506 if (chip_id(adap) <= CHELSIO_T5) 8507 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8508 else 8509 *smt_idx = viid & M_FW_VIID_VIN; 8510 } 8511 } 8512 } 8513 return ret; 8514 } 8515 8516 /** 8517 * t4_set_addr_hash - program the MAC inexact-match hash filter 8518 * @adap: the adapter 8519 * @mbox: mailbox to use for the FW command 8520 * @viid: the VI id 8521 * @ucast: whether the hash filter should also match unicast addresses 8522 * @vec: the value to be written to the hash filter 8523 * @sleep_ok: call is allowed to sleep 8524 * 8525 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8526 */ 8527 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8528 bool ucast, u64 vec, bool sleep_ok) 8529 { 8530 struct fw_vi_mac_cmd c; 8531 u32 val; 8532 8533 memset(&c, 0, sizeof(c)); 8534 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8535 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8536 V_FW_VI_ENABLE_CMD_VIID(viid)); 8537 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8538 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8539 c.freemacs_to_len16 = cpu_to_be32(val); 8540 c.u.hash.hashvec = cpu_to_be64(vec); 8541 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8542 } 8543 8544 /** 8545 * t4_enable_vi_params - enable/disable a virtual interface 8546 * @adap: the adapter 8547 * @mbox: mailbox to use for the FW command 8548 * @viid: the VI id 8549 * @rx_en: 1=enable Rx, 0=disable Rx 8550 * @tx_en: 1=enable Tx, 0=disable Tx 8551 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8552 * 8553 * Enables/disables a virtual interface. Note that setting DCB Enable 8554 * only makes sense when enabling a Virtual Interface ... 8555 */ 8556 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8557 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8558 { 8559 struct fw_vi_enable_cmd c; 8560 8561 memset(&c, 0, sizeof(c)); 8562 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8563 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8564 V_FW_VI_ENABLE_CMD_VIID(viid)); 8565 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8566 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8567 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8568 FW_LEN16(c)); 8569 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8570 } 8571 8572 /** 8573 * t4_enable_vi - enable/disable a virtual interface 8574 * @adap: the adapter 8575 * @mbox: mailbox to use for the FW command 8576 * @viid: the VI id 8577 * @rx_en: 1=enable Rx, 0=disable Rx 8578 * @tx_en: 1=enable Tx, 0=disable Tx 8579 * 8580 * Enables/disables a virtual interface. Note that setting DCB Enable 8581 * only makes sense when enabling a Virtual Interface ... 8582 */ 8583 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8584 bool rx_en, bool tx_en) 8585 { 8586 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8587 } 8588 8589 /** 8590 * t4_identify_port - identify a VI's port by blinking its LED 8591 * @adap: the adapter 8592 * @mbox: mailbox to use for the FW command 8593 * @viid: the VI id 8594 * @nblinks: how many times to blink LED at 2.5 Hz 8595 * 8596 * Identifies a VI's port by blinking its LED. 8597 */ 8598 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8599 unsigned int nblinks) 8600 { 8601 struct fw_vi_enable_cmd c; 8602 8603 memset(&c, 0, sizeof(c)); 8604 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8605 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8606 V_FW_VI_ENABLE_CMD_VIID(viid)); 8607 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8608 c.blinkdur = cpu_to_be16(nblinks); 8609 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8610 } 8611 8612 /** 8613 * t4_iq_stop - stop an ingress queue and its FLs 8614 * @adap: the adapter 8615 * @mbox: mailbox to use for the FW command 8616 * @pf: the PF owning the queues 8617 * @vf: the VF owning the queues 8618 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8619 * @iqid: ingress queue id 8620 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8621 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8622 * 8623 * Stops an ingress queue and its associated FLs, if any. This causes 8624 * any current or future data/messages destined for these queues to be 8625 * tossed. 8626 */ 8627 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8628 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8629 unsigned int fl0id, unsigned int fl1id) 8630 { 8631 struct fw_iq_cmd c; 8632 8633 memset(&c, 0, sizeof(c)); 8634 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8635 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8636 V_FW_IQ_CMD_VFN(vf)); 8637 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8638 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8639 c.iqid = cpu_to_be16(iqid); 8640 c.fl0id = cpu_to_be16(fl0id); 8641 c.fl1id = cpu_to_be16(fl1id); 8642 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8643 } 8644 8645 /** 8646 * t4_iq_free - free an ingress queue and its FLs 8647 * @adap: the adapter 8648 * @mbox: mailbox to use for the FW command 8649 * @pf: the PF owning the queues 8650 * @vf: the VF owning the queues 8651 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8652 * @iqid: ingress queue id 8653 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8654 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8655 * 8656 * Frees an ingress queue and its associated FLs, if any. 8657 */ 8658 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8659 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8660 unsigned int fl0id, unsigned int fl1id) 8661 { 8662 struct fw_iq_cmd c; 8663 8664 memset(&c, 0, sizeof(c)); 8665 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8666 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8667 V_FW_IQ_CMD_VFN(vf)); 8668 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8669 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8670 c.iqid = cpu_to_be16(iqid); 8671 c.fl0id = cpu_to_be16(fl0id); 8672 c.fl1id = cpu_to_be16(fl1id); 8673 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8674 } 8675 8676 /** 8677 * t4_eth_eq_stop - stop an Ethernet egress queue 8678 * @adap: the adapter 8679 * @mbox: mailbox to use for the FW command 8680 * @pf: the PF owning the queues 8681 * @vf: the VF owning the queues 8682 * @eqid: egress queue id 8683 * 8684 * Stops an Ethernet egress queue. The queue can be reinitialized or 8685 * freed but is not otherwise functional after this call. 8686 */ 8687 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8688 unsigned int vf, unsigned int eqid) 8689 { 8690 struct fw_eq_eth_cmd c; 8691 8692 memset(&c, 0, sizeof(c)); 8693 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8694 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8695 V_FW_EQ_ETH_CMD_PFN(pf) | 8696 V_FW_EQ_ETH_CMD_VFN(vf)); 8697 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c)); 8698 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8699 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8700 } 8701 8702 /** 8703 * t4_eth_eq_free - free an Ethernet egress queue 8704 * @adap: the adapter 8705 * @mbox: mailbox to use for the FW command 8706 * @pf: the PF owning the queue 8707 * @vf: the VF owning the queue 8708 * @eqid: egress queue id 8709 * 8710 * Frees an Ethernet egress queue. 8711 */ 8712 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8713 unsigned int vf, unsigned int eqid) 8714 { 8715 struct fw_eq_eth_cmd c; 8716 8717 memset(&c, 0, sizeof(c)); 8718 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8719 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8720 V_FW_EQ_ETH_CMD_PFN(pf) | 8721 V_FW_EQ_ETH_CMD_VFN(vf)); 8722 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8723 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8724 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8725 } 8726 8727 /** 8728 * t4_ctrl_eq_free - free a control egress queue 8729 * @adap: the adapter 8730 * @mbox: mailbox to use for the FW command 8731 * @pf: the PF owning the queue 8732 * @vf: the VF owning the queue 8733 * @eqid: egress queue id 8734 * 8735 * Frees a control egress queue. 8736 */ 8737 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8738 unsigned int vf, unsigned int eqid) 8739 { 8740 struct fw_eq_ctrl_cmd c; 8741 8742 memset(&c, 0, sizeof(c)); 8743 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8744 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8745 V_FW_EQ_CTRL_CMD_PFN(pf) | 8746 V_FW_EQ_CTRL_CMD_VFN(vf)); 8747 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8748 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8749 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8750 } 8751 8752 /** 8753 * t4_ofld_eq_free - free an offload egress queue 8754 * @adap: the adapter 8755 * @mbox: mailbox to use for the FW command 8756 * @pf: the PF owning the queue 8757 * @vf: the VF owning the queue 8758 * @eqid: egress queue id 8759 * 8760 * Frees a control egress queue. 8761 */ 8762 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8763 unsigned int vf, unsigned int eqid) 8764 { 8765 struct fw_eq_ofld_cmd c; 8766 8767 memset(&c, 0, sizeof(c)); 8768 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8769 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8770 V_FW_EQ_OFLD_CMD_PFN(pf) | 8771 V_FW_EQ_OFLD_CMD_VFN(vf)); 8772 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8773 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8774 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8775 } 8776 8777 /** 8778 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8779 * @link_down_rc: Link Down Reason Code 8780 * 8781 * Returns a string representation of the Link Down Reason Code. 8782 */ 8783 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8784 { 8785 static const char *reason[] = { 8786 "Link Down", 8787 "Remote Fault", 8788 "Auto-negotiation Failure", 8789 "Reserved3", 8790 "Insufficient Airflow", 8791 "Unable To Determine Reason", 8792 "No RX Signal Detected", 8793 "Reserved7", 8794 }; 8795 8796 if (link_down_rc >= ARRAY_SIZE(reason)) 8797 return "Bad Reason Code"; 8798 8799 return reason[link_down_rc]; 8800 } 8801 8802 /* 8803 * Return the highest speed set in the port capabilities, in Mb/s. 8804 */ 8805 unsigned int fwcap_to_speed(uint32_t caps) 8806 { 8807 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8808 do { \ 8809 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8810 return __speed; \ 8811 } while (0) 8812 8813 TEST_SPEED_RETURN(400G, 400000); 8814 TEST_SPEED_RETURN(200G, 200000); 8815 TEST_SPEED_RETURN(100G, 100000); 8816 TEST_SPEED_RETURN(50G, 50000); 8817 TEST_SPEED_RETURN(40G, 40000); 8818 TEST_SPEED_RETURN(25G, 25000); 8819 TEST_SPEED_RETURN(10G, 10000); 8820 TEST_SPEED_RETURN(1G, 1000); 8821 TEST_SPEED_RETURN(100M, 100); 8822 8823 #undef TEST_SPEED_RETURN 8824 8825 return 0; 8826 } 8827 8828 /* 8829 * Return the port capabilities bit for the given speed, which is in Mb/s. 8830 */ 8831 uint32_t speed_to_fwcap(unsigned int speed) 8832 { 8833 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8834 do { \ 8835 if (speed == __speed) \ 8836 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8837 } while (0) 8838 8839 TEST_SPEED_RETURN(400G, 400000); 8840 TEST_SPEED_RETURN(200G, 200000); 8841 TEST_SPEED_RETURN(100G, 100000); 8842 TEST_SPEED_RETURN(50G, 50000); 8843 TEST_SPEED_RETURN(40G, 40000); 8844 TEST_SPEED_RETURN(25G, 25000); 8845 TEST_SPEED_RETURN(10G, 10000); 8846 TEST_SPEED_RETURN(1G, 1000); 8847 TEST_SPEED_RETURN(100M, 100); 8848 8849 #undef TEST_SPEED_RETURN 8850 8851 return 0; 8852 } 8853 8854 /* 8855 * Return the port capabilities bit for the highest speed in the capabilities. 8856 */ 8857 uint32_t fwcap_top_speed(uint32_t caps) 8858 { 8859 #define TEST_SPEED_RETURN(__caps_speed) \ 8860 do { \ 8861 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8862 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8863 } while (0) 8864 8865 TEST_SPEED_RETURN(400G); 8866 TEST_SPEED_RETURN(200G); 8867 TEST_SPEED_RETURN(100G); 8868 TEST_SPEED_RETURN(50G); 8869 TEST_SPEED_RETURN(40G); 8870 TEST_SPEED_RETURN(25G); 8871 TEST_SPEED_RETURN(10G); 8872 TEST_SPEED_RETURN(1G); 8873 TEST_SPEED_RETURN(100M); 8874 8875 #undef TEST_SPEED_RETURN 8876 8877 return 0; 8878 } 8879 8880 /** 8881 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8882 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8883 * 8884 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8885 * 32-bit Port Capabilities value. 8886 */ 8887 static uint32_t lstatus_to_fwcap(u32 lstatus) 8888 { 8889 uint32_t linkattr = 0; 8890 8891 /* 8892 * Unfortunately the format of the Link Status in the old 8893 * 16-bit Port Information message isn't the same as the 8894 * 16-bit Port Capabilities bitfield used everywhere else ... 8895 */ 8896 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8897 linkattr |= FW_PORT_CAP32_FC_RX; 8898 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8899 linkattr |= FW_PORT_CAP32_FC_TX; 8900 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8901 linkattr |= FW_PORT_CAP32_SPEED_100M; 8902 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8903 linkattr |= FW_PORT_CAP32_SPEED_1G; 8904 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8905 linkattr |= FW_PORT_CAP32_SPEED_10G; 8906 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8907 linkattr |= FW_PORT_CAP32_SPEED_25G; 8908 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8909 linkattr |= FW_PORT_CAP32_SPEED_40G; 8910 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8911 linkattr |= FW_PORT_CAP32_SPEED_100G; 8912 8913 return linkattr; 8914 } 8915 8916 /* 8917 * Updates all fields owned by the common code in port_info and link_config 8918 * based on information provided by the firmware. Does not touch any 8919 * requested_* field. 8920 */ 8921 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8922 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8923 { 8924 struct link_config old_lc, *lc = &pi->link_cfg; 8925 unsigned char fc; 8926 u32 stat, linkattr; 8927 int old_ptype, old_mtype; 8928 8929 old_ptype = pi->port_type; 8930 old_mtype = pi->mod_type; 8931 old_lc = *lc; 8932 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8933 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8934 8935 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8936 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8937 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8938 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8939 8940 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8941 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8942 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8943 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8944 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8945 8946 linkattr = lstatus_to_fwcap(stat); 8947 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8948 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8949 8950 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8951 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8952 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8953 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8954 8955 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); 8956 lc->acaps = be32_to_cpu(p->u.info32.acaps32); 8957 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); 8958 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8959 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8960 8961 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8962 } else { 8963 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8964 return; 8965 } 8966 8967 lc->speed = fwcap_to_speed(linkattr); 8968 lc->fec = fwcap_to_fec(linkattr, true); 8969 8970 fc = 0; 8971 if (linkattr & FW_PORT_CAP32_FC_RX) 8972 fc |= PAUSE_RX; 8973 if (linkattr & FW_PORT_CAP32_FC_TX) 8974 fc |= PAUSE_TX; 8975 lc->fc = fc; 8976 8977 if (mod_changed != NULL) 8978 *mod_changed = false; 8979 if (link_changed != NULL) 8980 *link_changed = false; 8981 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 8982 old_lc.pcaps != lc->pcaps) { 8983 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) 8984 lc->fec_hint = fwcap_to_fec(lc->acaps, true); 8985 if (mod_changed != NULL) 8986 *mod_changed = true; 8987 } 8988 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 8989 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 8990 if (link_changed != NULL) 8991 *link_changed = true; 8992 } 8993 } 8994 8995 /** 8996 * t4_update_port_info - retrieve and update port information if changed 8997 * @pi: the port_info 8998 * 8999 * We issue a Get Port Information Command to the Firmware and, if 9000 * successful, we check to see if anything is different from what we 9001 * last recorded and update things accordingly. 9002 */ 9003 int t4_update_port_info(struct port_info *pi) 9004 { 9005 struct adapter *sc = pi->adapter; 9006 struct fw_port_cmd cmd; 9007 enum fw_port_action action; 9008 int ret; 9009 9010 memset(&cmd, 0, sizeof(cmd)); 9011 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 9012 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9013 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 9014 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 9015 FW_PORT_ACTION_GET_PORT_INFO; 9016 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 9017 FW_LEN16(cmd)); 9018 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 9019 if (ret) 9020 return ret; 9021 9022 handle_port_info(pi, &cmd, action, NULL, NULL); 9023 return 0; 9024 } 9025 9026 /** 9027 * t4_handle_fw_rpl - process a FW reply message 9028 * @adap: the adapter 9029 * @rpl: start of the FW message 9030 * 9031 * Processes a FW message, such as link state change messages. 9032 */ 9033 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 9034 { 9035 u8 opcode = *(const u8 *)rpl; 9036 const struct fw_port_cmd *p = (const void *)rpl; 9037 enum fw_port_action action = 9038 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 9039 bool mod_changed, link_changed; 9040 9041 if (opcode == FW_PORT_CMD && 9042 (action == FW_PORT_ACTION_GET_PORT_INFO || 9043 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 9044 /* link/module state change message */ 9045 int i; 9046 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 9047 struct port_info *pi = NULL; 9048 struct link_config *lc; 9049 9050 for_each_port(adap, i) { 9051 pi = adap2pinfo(adap, i); 9052 if (pi->tx_chan == chan) 9053 break; 9054 } 9055 9056 lc = &pi->link_cfg; 9057 PORT_LOCK(pi); 9058 handle_port_info(pi, p, action, &mod_changed, &link_changed); 9059 PORT_UNLOCK(pi); 9060 if (mod_changed) 9061 t4_os_portmod_changed(pi); 9062 if (link_changed) { 9063 PORT_LOCK(pi); 9064 t4_os_link_changed(pi); 9065 PORT_UNLOCK(pi); 9066 } 9067 } else { 9068 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 9069 return -EINVAL; 9070 } 9071 return 0; 9072 } 9073 9074 /** 9075 * get_pci_mode - determine a card's PCI mode 9076 * @adapter: the adapter 9077 * @p: where to store the PCI settings 9078 * 9079 * Determines a card's PCI mode and associated parameters, such as speed 9080 * and width. 9081 */ 9082 static void get_pci_mode(struct adapter *adapter, 9083 struct pci_params *p) 9084 { 9085 u16 val; 9086 u32 pcie_cap; 9087 9088 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9089 if (pcie_cap) { 9090 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 9091 p->speed = val & PCI_EXP_LNKSTA_CLS; 9092 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 9093 } 9094 } 9095 9096 struct flash_desc { 9097 u32 vendor_and_model_id; 9098 u32 size_mb; 9099 }; 9100 9101 int t4_get_flash_params(struct adapter *adapter) 9102 { 9103 /* 9104 * Table for non-standard supported Flash parts. Note, all Flash 9105 * parts must have 64KB sectors. 9106 */ 9107 static struct flash_desc supported_flash[] = { 9108 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 9109 }; 9110 9111 int ret; 9112 u32 flashid = 0; 9113 unsigned int part, manufacturer; 9114 unsigned int density, size = 0; 9115 9116 9117 /* 9118 * Issue a Read ID Command to the Flash part. We decode supported 9119 * Flash parts and their sizes from this. There's a newer Query 9120 * Command which can retrieve detailed geometry information but many 9121 * Flash parts don't support it. 9122 */ 9123 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 9124 if (!ret) 9125 ret = sf1_read(adapter, 3, 0, 1, &flashid); 9126 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 9127 if (ret < 0) 9128 return ret; 9129 9130 /* 9131 * Check to see if it's one of our non-standard supported Flash parts. 9132 */ 9133 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 9134 if (supported_flash[part].vendor_and_model_id == flashid) { 9135 adapter->params.sf_size = 9136 supported_flash[part].size_mb; 9137 adapter->params.sf_nsec = 9138 adapter->params.sf_size / SF_SEC_SIZE; 9139 goto found; 9140 } 9141 9142 /* 9143 * Decode Flash part size. The code below looks repetative with 9144 * common encodings, but that's not guaranteed in the JEDEC 9145 * specification for the Read JADEC ID command. The only thing that 9146 * we're guaranteed by the JADEC specification is where the 9147 * Manufacturer ID is in the returned result. After that each 9148 * Manufacturer ~could~ encode things completely differently. 9149 * Note, all Flash parts must have 64KB sectors. 9150 */ 9151 manufacturer = flashid & 0xff; 9152 switch (manufacturer) { 9153 case 0x20: /* Micron/Numonix */ 9154 /* 9155 * This Density -> Size decoding table is taken from Micron 9156 * Data Sheets. 9157 */ 9158 density = (flashid >> 16) & 0xff; 9159 switch (density) { 9160 case 0x14: size = 1 << 20; break; /* 1MB */ 9161 case 0x15: size = 1 << 21; break; /* 2MB */ 9162 case 0x16: size = 1 << 22; break; /* 4MB */ 9163 case 0x17: size = 1 << 23; break; /* 8MB */ 9164 case 0x18: size = 1 << 24; break; /* 16MB */ 9165 case 0x19: size = 1 << 25; break; /* 32MB */ 9166 case 0x20: size = 1 << 26; break; /* 64MB */ 9167 case 0x21: size = 1 << 27; break; /* 128MB */ 9168 case 0x22: size = 1 << 28; break; /* 256MB */ 9169 } 9170 break; 9171 9172 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 9173 /* 9174 * This Density -> Size decoding table is taken from ISSI 9175 * Data Sheets. 9176 */ 9177 density = (flashid >> 16) & 0xff; 9178 switch (density) { 9179 case 0x16: size = 1 << 25; break; /* 32MB */ 9180 case 0x17: size = 1 << 26; break; /* 64MB */ 9181 } 9182 break; 9183 9184 case 0xc2: /* Macronix */ 9185 /* 9186 * This Density -> Size decoding table is taken from Macronix 9187 * Data Sheets. 9188 */ 9189 density = (flashid >> 16) & 0xff; 9190 switch (density) { 9191 case 0x17: size = 1 << 23; break; /* 8MB */ 9192 case 0x18: size = 1 << 24; break; /* 16MB */ 9193 } 9194 break; 9195 9196 case 0xef: /* Winbond */ 9197 /* 9198 * This Density -> Size decoding table is taken from Winbond 9199 * Data Sheets. 9200 */ 9201 density = (flashid >> 16) & 0xff; 9202 switch (density) { 9203 case 0x17: size = 1 << 23; break; /* 8MB */ 9204 case 0x18: size = 1 << 24; break; /* 16MB */ 9205 } 9206 break; 9207 } 9208 9209 /* If we didn't recognize the FLASH part, that's no real issue: the 9210 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 9211 * use a FLASH part which is at least 4MB in size and has 64KB 9212 * sectors. The unrecognized FLASH part is likely to be much larger 9213 * than 4MB, but that's all we really need. 9214 */ 9215 if (size == 0) { 9216 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 9217 size = 1 << 22; 9218 } 9219 9220 /* 9221 * Store decoded Flash size and fall through into vetting code. 9222 */ 9223 adapter->params.sf_size = size; 9224 adapter->params.sf_nsec = size / SF_SEC_SIZE; 9225 9226 found: 9227 /* 9228 * We should ~probably~ reject adapters with FLASHes which are too 9229 * small but we have some legacy FPGAs with small FLASHes that we'd 9230 * still like to use. So instead we emit a scary message ... 9231 */ 9232 if (adapter->params.sf_size < FLASH_MIN_SIZE) 9233 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 9234 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 9235 9236 return 0; 9237 } 9238 9239 static void set_pcie_completion_timeout(struct adapter *adapter, 9240 u8 range) 9241 { 9242 u16 val; 9243 u32 pcie_cap; 9244 9245 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9246 if (pcie_cap) { 9247 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 9248 val &= 0xfff0; 9249 val |= range ; 9250 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 9251 } 9252 } 9253 9254 const struct chip_params *t4_get_chip_params(int chipid) 9255 { 9256 static const struct chip_params chip_params[] = { 9257 { 9258 /* T4 */ 9259 .nchan = NCHAN, 9260 .pm_stats_cnt = PM_NSTATS, 9261 .cng_ch_bits_log = 2, 9262 .nsched_cls = 15, 9263 .cim_num_obq = CIM_NUM_OBQ, 9264 .filter_opt_len = FILTER_OPT_LEN, 9265 .mps_rplc_size = 128, 9266 .vfcount = 128, 9267 .sge_fl_db = F_DBPRIO, 9268 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 9269 .rss_nentries = RSS_NENTRIES, 9270 }, 9271 { 9272 /* T5 */ 9273 .nchan = NCHAN, 9274 .pm_stats_cnt = PM_NSTATS, 9275 .cng_ch_bits_log = 2, 9276 .nsched_cls = 16, 9277 .cim_num_obq = CIM_NUM_OBQ_T5, 9278 .filter_opt_len = T5_FILTER_OPT_LEN, 9279 .mps_rplc_size = 128, 9280 .vfcount = 128, 9281 .sge_fl_db = F_DBPRIO | F_DBTYPE, 9282 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9283 .rss_nentries = RSS_NENTRIES, 9284 }, 9285 { 9286 /* T6 */ 9287 .nchan = T6_NCHAN, 9288 .pm_stats_cnt = T6_PM_NSTATS, 9289 .cng_ch_bits_log = 3, 9290 .nsched_cls = 16, 9291 .cim_num_obq = CIM_NUM_OBQ_T5, 9292 .filter_opt_len = T5_FILTER_OPT_LEN, 9293 .mps_rplc_size = 256, 9294 .vfcount = 256, 9295 .sge_fl_db = 0, 9296 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9297 .rss_nentries = T6_RSS_NENTRIES, 9298 }, 9299 }; 9300 9301 chipid -= CHELSIO_T4; 9302 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 9303 return NULL; 9304 9305 return &chip_params[chipid]; 9306 } 9307 9308 /** 9309 * t4_prep_adapter - prepare SW and HW for operation 9310 * @adapter: the adapter 9311 * @buf: temporary space of at least VPD_LEN size provided by the caller. 9312 * 9313 * Initialize adapter SW state for the various HW modules, set initial 9314 * values for some adapter tunables, take PHYs out of reset, and 9315 * initialize the MDIO interface. 9316 */ 9317 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 9318 { 9319 int ret; 9320 uint16_t device_id; 9321 uint32_t pl_rev; 9322 9323 get_pci_mode(adapter, &adapter->params.pci); 9324 9325 pl_rev = t4_read_reg(adapter, A_PL_REV); 9326 adapter->params.chipid = G_CHIPID(pl_rev); 9327 adapter->params.rev = G_REV(pl_rev); 9328 if (adapter->params.chipid == 0) { 9329 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 9330 adapter->params.chipid = CHELSIO_T4; 9331 9332 /* T4A1 chip is not supported */ 9333 if (adapter->params.rev == 1) { 9334 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 9335 return -EINVAL; 9336 } 9337 } 9338 9339 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 9340 if (adapter->chip_params == NULL) 9341 return -EINVAL; 9342 9343 adapter->params.pci.vpd_cap_addr = 9344 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 9345 9346 ret = t4_get_flash_params(adapter); 9347 if (ret < 0) 9348 return ret; 9349 9350 /* Cards with real ASICs have the chipid in the PCIe device id */ 9351 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 9352 if (device_id >> 12 == chip_id(adapter)) 9353 adapter->params.cim_la_size = CIMLA_SIZE; 9354 else { 9355 /* FPGA */ 9356 adapter->params.fpga = 1; 9357 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 9358 } 9359 9360 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 9361 if (ret < 0) 9362 return ret; 9363 9364 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 9365 9366 /* 9367 * Default port and clock for debugging in case we can't reach FW. 9368 */ 9369 adapter->params.nports = 1; 9370 adapter->params.portvec = 1; 9371 adapter->params.vpd.cclk = 50000; 9372 9373 /* Set pci completion timeout value to 4 seconds. */ 9374 set_pcie_completion_timeout(adapter, 0xd); 9375 return 0; 9376 } 9377 9378 /** 9379 * t4_shutdown_adapter - shut down adapter, host & wire 9380 * @adapter: the adapter 9381 * 9382 * Perform an emergency shutdown of the adapter and stop it from 9383 * continuing any further communication on the ports or DMA to the 9384 * host. This is typically used when the adapter and/or firmware 9385 * have crashed and we want to prevent any further accidental 9386 * communication with the rest of the world. This will also force 9387 * the port Link Status to go down -- if register writes work -- 9388 * which should help our peers figure out that we're down. 9389 */ 9390 int t4_shutdown_adapter(struct adapter *adapter) 9391 { 9392 int port; 9393 9394 t4_intr_disable(adapter); 9395 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 9396 for_each_port(adapter, port) { 9397 u32 a_port_cfg = is_t4(adapter) ? 9398 PORT_REG(port, A_XGMAC_PORT_CFG) : 9399 T5_PORT_REG(port, A_MAC_PORT_CFG); 9400 9401 t4_write_reg(adapter, a_port_cfg, 9402 t4_read_reg(adapter, a_port_cfg) 9403 & ~V_SIGNAL_DET(1)); 9404 } 9405 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9406 9407 return 0; 9408 } 9409 9410 /** 9411 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9412 * @adapter: the adapter 9413 * @qid: the Queue ID 9414 * @qtype: the Ingress or Egress type for @qid 9415 * @user: true if this request is for a user mode queue 9416 * @pbar2_qoffset: BAR2 Queue Offset 9417 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9418 * 9419 * Returns the BAR2 SGE Queue Registers information associated with the 9420 * indicated Absolute Queue ID. These are passed back in return value 9421 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9422 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9423 * 9424 * This may return an error which indicates that BAR2 SGE Queue 9425 * registers aren't available. If an error is not returned, then the 9426 * following values are returned: 9427 * 9428 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9429 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9430 * 9431 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9432 * require the "Inferred Queue ID" ability may be used. E.g. the 9433 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9434 * then these "Inferred Queue ID" register may not be used. 9435 */ 9436 int t4_bar2_sge_qregs(struct adapter *adapter, 9437 unsigned int qid, 9438 enum t4_bar2_qtype qtype, 9439 int user, 9440 u64 *pbar2_qoffset, 9441 unsigned int *pbar2_qid) 9442 { 9443 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9444 u64 bar2_page_offset, bar2_qoffset; 9445 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9446 9447 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9448 * mode queues. 9449 */ 9450 if (!user && is_t4(adapter)) 9451 return -EINVAL; 9452 9453 /* Get our SGE Page Size parameters. 9454 */ 9455 page_shift = adapter->params.sge.page_shift; 9456 page_size = 1 << page_shift; 9457 9458 /* Get the right Queues per Page parameters for our Queue. 9459 */ 9460 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9461 ? adapter->params.sge.eq_s_qpp 9462 : adapter->params.sge.iq_s_qpp); 9463 qpp_mask = (1 << qpp_shift) - 1; 9464 9465 /* Calculate the basics of the BAR2 SGE Queue register area: 9466 * o The BAR2 page the Queue registers will be in. 9467 * o The BAR2 Queue ID. 9468 * o The BAR2 Queue ID Offset into the BAR2 page. 9469 */ 9470 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9471 bar2_qid = qid & qpp_mask; 9472 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9473 9474 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9475 * hardware will infer the Absolute Queue ID simply from the writes to 9476 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9477 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9478 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9479 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9480 * from the BAR2 Page and BAR2 Queue ID. 9481 * 9482 * One important censequence of this is that some BAR2 SGE registers 9483 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9484 * there. But other registers synthesize the SGE Queue ID purely 9485 * from the writes to the registers -- the Write Combined Doorbell 9486 * Buffer is a good example. These BAR2 SGE Registers are only 9487 * available for those BAR2 SGE Register areas where the SGE Absolute 9488 * Queue ID can be inferred from simple writes. 9489 */ 9490 bar2_qoffset = bar2_page_offset; 9491 bar2_qinferred = (bar2_qid_offset < page_size); 9492 if (bar2_qinferred) { 9493 bar2_qoffset += bar2_qid_offset; 9494 bar2_qid = 0; 9495 } 9496 9497 *pbar2_qoffset = bar2_qoffset; 9498 *pbar2_qid = bar2_qid; 9499 return 0; 9500 } 9501 9502 /** 9503 * t4_init_devlog_params - initialize adapter->params.devlog 9504 * @adap: the adapter 9505 * @fw_attach: whether we can talk to the firmware 9506 * 9507 * Initialize various fields of the adapter's Firmware Device Log 9508 * Parameters structure. 9509 */ 9510 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9511 { 9512 struct devlog_params *dparams = &adap->params.devlog; 9513 u32 pf_dparams; 9514 unsigned int devlog_meminfo; 9515 struct fw_devlog_cmd devlog_cmd; 9516 int ret; 9517 9518 /* If we're dealing with newer firmware, the Device Log Paramerters 9519 * are stored in a designated register which allows us to access the 9520 * Device Log even if we can't talk to the firmware. 9521 */ 9522 pf_dparams = 9523 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9524 if (pf_dparams) { 9525 unsigned int nentries, nentries128; 9526 9527 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9528 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9529 9530 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9531 nentries = (nentries128 + 1) * 128; 9532 dparams->size = nentries * sizeof(struct fw_devlog_e); 9533 9534 return 0; 9535 } 9536 9537 /* 9538 * For any failing returns ... 9539 */ 9540 memset(dparams, 0, sizeof *dparams); 9541 9542 /* 9543 * If we can't talk to the firmware, there's really nothing we can do 9544 * at this point. 9545 */ 9546 if (!fw_attach) 9547 return -ENXIO; 9548 9549 /* Otherwise, ask the firmware for it's Device Log Parameters. 9550 */ 9551 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9552 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9553 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9554 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9555 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9556 &devlog_cmd); 9557 if (ret) 9558 return ret; 9559 9560 devlog_meminfo = 9561 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9562 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9563 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9564 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9565 9566 return 0; 9567 } 9568 9569 /** 9570 * t4_init_sge_params - initialize adap->params.sge 9571 * @adapter: the adapter 9572 * 9573 * Initialize various fields of the adapter's SGE Parameters structure. 9574 */ 9575 int t4_init_sge_params(struct adapter *adapter) 9576 { 9577 u32 r; 9578 struct sge_params *sp = &adapter->params.sge; 9579 unsigned i, tscale = 1; 9580 9581 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9582 sp->counter_val[0] = G_THRESHOLD_0(r); 9583 sp->counter_val[1] = G_THRESHOLD_1(r); 9584 sp->counter_val[2] = G_THRESHOLD_2(r); 9585 sp->counter_val[3] = G_THRESHOLD_3(r); 9586 9587 if (chip_id(adapter) >= CHELSIO_T6) { 9588 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9589 tscale = G_TSCALE(r); 9590 if (tscale == 0) 9591 tscale = 1; 9592 else 9593 tscale += 2; 9594 } 9595 9596 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9597 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9598 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9599 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9600 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9601 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9602 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9603 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9604 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9605 9606 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9607 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9608 if (is_t4(adapter)) 9609 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9610 else if (is_t5(adapter)) 9611 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9612 else 9613 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9614 9615 /* egress queues: log2 of # of doorbells per BAR2 page */ 9616 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9617 r >>= S_QUEUESPERPAGEPF0 + 9618 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9619 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9620 9621 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9622 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9623 r >>= S_QUEUESPERPAGEPF0 + 9624 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9625 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9626 9627 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9628 r >>= S_HOSTPAGESIZEPF0 + 9629 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9630 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9631 9632 r = t4_read_reg(adapter, A_SGE_CONTROL); 9633 sp->sge_control = r; 9634 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9635 sp->fl_pktshift = G_PKTSHIFT(r); 9636 if (chip_id(adapter) <= CHELSIO_T5) { 9637 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9638 X_INGPADBOUNDARY_SHIFT); 9639 } else { 9640 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9641 X_T6_INGPADBOUNDARY_SHIFT); 9642 } 9643 if (is_t4(adapter)) 9644 sp->pack_boundary = sp->pad_boundary; 9645 else { 9646 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9647 if (G_INGPACKBOUNDARY(r) == 0) 9648 sp->pack_boundary = 16; 9649 else 9650 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9651 } 9652 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9653 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9654 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9655 9656 return 0; 9657 } 9658 9659 /* Convert the LE's hardware hash mask to a shorter filter mask. */ 9660 static inline uint16_t 9661 hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode) 9662 { 9663 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 9664 int i; 9665 uint16_t filter_mask; 9666 uint64_t mask; /* field mask */ 9667 9668 filter_mask = 0; 9669 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 9670 if ((filter_mode & (1 << i)) == 0) 9671 continue; 9672 mask = (1 << width[i]) - 1; 9673 if ((hashmask & mask) == mask) 9674 filter_mask |= 1 << i; 9675 hashmask >>= width[i]; 9676 } 9677 9678 return (filter_mask); 9679 } 9680 9681 /* 9682 * Read and cache the adapter's compressed filter mode and ingress config. 9683 */ 9684 static void 9685 read_filter_mode_and_ingress_config(struct adapter *adap) 9686 { 9687 int rc; 9688 uint32_t v, param[2], val[2]; 9689 struct tp_params *tpp = &adap->params.tp; 9690 uint64_t hash_mask; 9691 9692 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9693 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9694 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 9695 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9696 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9697 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 9698 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); 9699 if (rc == 0) { 9700 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); 9701 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); 9702 tpp->vnic_mode = val[1]; 9703 } else { 9704 /* 9705 * Old firmware. Read filter mode/mask and ingress config 9706 * straight from the hardware. 9707 */ 9708 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true); 9709 tpp->filter_mode = v & 0xffff; 9710 9711 hash_mask = 0; 9712 if (chip_id(adap) > CHELSIO_T4) { 9713 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9714 hash_mask = v; 9715 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9716 hash_mask |= (u64)v << 32; 9717 } 9718 tpp->filter_mask = hashmask_to_filtermask(hash_mask, 9719 tpp->filter_mode); 9720 9721 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true); 9722 if (v & F_VNIC) 9723 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; 9724 else 9725 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; 9726 } 9727 9728 /* 9729 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9730 * shift positions of several elements of the Compressed Filter Tuple 9731 * for this adapter which we need frequently ... 9732 */ 9733 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9734 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9735 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9736 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9737 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9738 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9739 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9740 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9741 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9742 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9743 } 9744 9745 /** 9746 * t4_init_tp_params - initialize adap->params.tp 9747 * @adap: the adapter 9748 * 9749 * Initialize various fields of the adapter's TP Parameters structure. 9750 */ 9751 int t4_init_tp_params(struct adapter *adap) 9752 { 9753 int chan; 9754 u32 tx_len, rx_len, r, v; 9755 struct tp_params *tpp = &adap->params.tp; 9756 9757 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9758 tpp->tre = G_TIMERRESOLUTION(v); 9759 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9760 9761 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9762 for (chan = 0; chan < MAX_NCHAN; chan++) 9763 tpp->tx_modq[chan] = chan; 9764 9765 read_filter_mode_and_ingress_config(adap); 9766 9767 if (chip_id(adap) > CHELSIO_T5) { 9768 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9769 tpp->rx_pkt_encap = v & F_CRXPKTENC; 9770 } else 9771 tpp->rx_pkt_encap = false; 9772 9773 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE); 9774 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE); 9775 9776 r = t4_read_reg(adap, A_TP_PARA_REG2); 9777 rx_len = min(rx_len, G_MAXRXDATA(r)); 9778 tx_len = min(tx_len, G_MAXRXDATA(r)); 9779 9780 r = t4_read_reg(adap, A_TP_PARA_REG7); 9781 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 9782 rx_len = min(rx_len, v); 9783 tx_len = min(tx_len, v); 9784 9785 tpp->max_tx_pdu = tx_len; 9786 tpp->max_rx_pdu = rx_len; 9787 9788 return 0; 9789 } 9790 9791 /** 9792 * t4_filter_field_shift - calculate filter field shift 9793 * @adap: the adapter 9794 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9795 * 9796 * Return the shift position of a filter field within the Compressed 9797 * Filter Tuple. The filter field is specified via its selection bit 9798 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9799 */ 9800 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9801 { 9802 const unsigned int filter_mode = adap->params.tp.filter_mode; 9803 unsigned int sel; 9804 int field_shift; 9805 9806 if ((filter_mode & filter_sel) == 0) 9807 return -1; 9808 9809 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9810 switch (filter_mode & sel) { 9811 case F_FCOE: 9812 field_shift += W_FT_FCOE; 9813 break; 9814 case F_PORT: 9815 field_shift += W_FT_PORT; 9816 break; 9817 case F_VNIC_ID: 9818 field_shift += W_FT_VNIC_ID; 9819 break; 9820 case F_VLAN: 9821 field_shift += W_FT_VLAN; 9822 break; 9823 case F_TOS: 9824 field_shift += W_FT_TOS; 9825 break; 9826 case F_PROTOCOL: 9827 field_shift += W_FT_PROTOCOL; 9828 break; 9829 case F_ETHERTYPE: 9830 field_shift += W_FT_ETHERTYPE; 9831 break; 9832 case F_MACMATCH: 9833 field_shift += W_FT_MACMATCH; 9834 break; 9835 case F_MPSHITTYPE: 9836 field_shift += W_FT_MPSHITTYPE; 9837 break; 9838 case F_FRAGMENTATION: 9839 field_shift += W_FT_FRAGMENTATION; 9840 break; 9841 } 9842 } 9843 return field_shift; 9844 } 9845 9846 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9847 { 9848 u8 addr[6]; 9849 int ret, i, j; 9850 struct port_info *p = adap2pinfo(adap, port_id); 9851 u32 param, val; 9852 struct vi_info *vi = &p->vi[0]; 9853 9854 for (i = 0, j = -1; i <= p->port_id; i++) { 9855 do { 9856 j++; 9857 } while ((adap->params.portvec & (1 << j)) == 0); 9858 } 9859 9860 p->tx_chan = j; 9861 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9862 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9863 p->rx_c_chan = t4_get_rx_c_chan(adap, j); 9864 p->lport = j; 9865 9866 if (!(adap->flags & IS_VF) || 9867 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9868 t4_update_port_info(p); 9869 } 9870 9871 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9872 &vi->vfvld, &vi->vin); 9873 if (ret < 0) 9874 return ret; 9875 9876 vi->viid = ret; 9877 t4_os_set_hw_addr(p, addr); 9878 9879 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9880 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9881 V_FW_PARAMS_PARAM_YZ(vi->viid); 9882 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9883 if (ret) 9884 vi->rss_base = 0xffff; 9885 else { 9886 /* MPASS((val >> 16) == rss_size); */ 9887 vi->rss_base = val & 0xffff; 9888 } 9889 9890 return 0; 9891 } 9892 9893 /** 9894 * t4_read_cimq_cfg - read CIM queue configuration 9895 * @adap: the adapter 9896 * @base: holds the queue base addresses in bytes 9897 * @size: holds the queue sizes in bytes 9898 * @thres: holds the queue full thresholds in bytes 9899 * 9900 * Returns the current configuration of the CIM queues, starting with 9901 * the IBQs, then the OBQs. 9902 */ 9903 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9904 { 9905 unsigned int i, v; 9906 int cim_num_obq = adap->chip_params->cim_num_obq; 9907 9908 for (i = 0; i < CIM_NUM_IBQ; i++) { 9909 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9910 V_QUENUMSELECT(i)); 9911 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9912 /* value is in 256-byte units */ 9913 *base++ = G_CIMQBASE(v) * 256; 9914 *size++ = G_CIMQSIZE(v) * 256; 9915 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9916 } 9917 for (i = 0; i < cim_num_obq; i++) { 9918 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9919 V_QUENUMSELECT(i)); 9920 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9921 /* value is in 256-byte units */ 9922 *base++ = G_CIMQBASE(v) * 256; 9923 *size++ = G_CIMQSIZE(v) * 256; 9924 } 9925 } 9926 9927 /** 9928 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9929 * @adap: the adapter 9930 * @qid: the queue index 9931 * @data: where to store the queue contents 9932 * @n: capacity of @data in 32-bit words 9933 * 9934 * Reads the contents of the selected CIM queue starting at address 0 up 9935 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9936 * error and the number of 32-bit words actually read on success. 9937 */ 9938 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9939 { 9940 int i, err, attempts; 9941 unsigned int addr; 9942 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9943 9944 if (qid > 5 || (n & 3)) 9945 return -EINVAL; 9946 9947 addr = qid * nwords; 9948 if (n > nwords) 9949 n = nwords; 9950 9951 /* It might take 3-10ms before the IBQ debug read access is allowed. 9952 * Wait for 1 Sec with a delay of 1 usec. 9953 */ 9954 attempts = 1000000; 9955 9956 for (i = 0; i < n; i++, addr++) { 9957 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 9958 F_IBQDBGEN); 9959 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 9960 attempts, 1); 9961 if (err) 9962 return err; 9963 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 9964 } 9965 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 9966 return i; 9967 } 9968 9969 /** 9970 * t4_read_cim_obq - read the contents of a CIM outbound queue 9971 * @adap: the adapter 9972 * @qid: the queue index 9973 * @data: where to store the queue contents 9974 * @n: capacity of @data in 32-bit words 9975 * 9976 * Reads the contents of the selected CIM queue starting at address 0 up 9977 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9978 * error and the number of 32-bit words actually read on success. 9979 */ 9980 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9981 { 9982 int i, err; 9983 unsigned int addr, v, nwords; 9984 int cim_num_obq = adap->chip_params->cim_num_obq; 9985 9986 if ((qid > (cim_num_obq - 1)) || (n & 3)) 9987 return -EINVAL; 9988 9989 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9990 V_QUENUMSELECT(qid)); 9991 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9992 9993 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 9994 nwords = G_CIMQSIZE(v) * 64; /* same */ 9995 if (n > nwords) 9996 n = nwords; 9997 9998 for (i = 0; i < n; i++, addr++) { 9999 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 10000 F_OBQDBGEN); 10001 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 10002 2, 1); 10003 if (err) 10004 return err; 10005 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 10006 } 10007 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 10008 return i; 10009 } 10010 10011 enum { 10012 CIM_QCTL_BASE = 0, 10013 CIM_CTL_BASE = 0x2000, 10014 CIM_PBT_ADDR_BASE = 0x2800, 10015 CIM_PBT_LRF_BASE = 0x3000, 10016 CIM_PBT_DATA_BASE = 0x3800 10017 }; 10018 10019 /** 10020 * t4_cim_read - read a block from CIM internal address space 10021 * @adap: the adapter 10022 * @addr: the start address within the CIM address space 10023 * @n: number of words to read 10024 * @valp: where to store the result 10025 * 10026 * Reads a block of 4-byte words from the CIM intenal address space. 10027 */ 10028 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 10029 unsigned int *valp) 10030 { 10031 int ret = 0; 10032 10033 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10034 return -EBUSY; 10035 10036 for ( ; !ret && n--; addr += 4) { 10037 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 10038 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10039 0, 5, 2); 10040 if (!ret) 10041 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 10042 } 10043 return ret; 10044 } 10045 10046 /** 10047 * t4_cim_write - write a block into CIM internal address space 10048 * @adap: the adapter 10049 * @addr: the start address within the CIM address space 10050 * @n: number of words to write 10051 * @valp: set of values to write 10052 * 10053 * Writes a block of 4-byte words into the CIM intenal address space. 10054 */ 10055 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 10056 const unsigned int *valp) 10057 { 10058 int ret = 0; 10059 10060 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10061 return -EBUSY; 10062 10063 for ( ; !ret && n--; addr += 4) { 10064 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 10065 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 10066 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10067 0, 5, 2); 10068 } 10069 return ret; 10070 } 10071 10072 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 10073 unsigned int val) 10074 { 10075 return t4_cim_write(adap, addr, 1, &val); 10076 } 10077 10078 /** 10079 * t4_cim_ctl_read - read a block from CIM control region 10080 * @adap: the adapter 10081 * @addr: the start address within the CIM control region 10082 * @n: number of words to read 10083 * @valp: where to store the result 10084 * 10085 * Reads a block of 4-byte words from the CIM control region. 10086 */ 10087 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 10088 unsigned int *valp) 10089 { 10090 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 10091 } 10092 10093 /** 10094 * t4_cim_read_la - read CIM LA capture buffer 10095 * @adap: the adapter 10096 * @la_buf: where to store the LA data 10097 * @wrptr: the HW write pointer within the capture buffer 10098 * 10099 * Reads the contents of the CIM LA buffer with the most recent entry at 10100 * the end of the returned data and with the entry at @wrptr first. 10101 * We try to leave the LA in the running state we find it in. 10102 */ 10103 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 10104 { 10105 int i, ret; 10106 unsigned int cfg, val, idx; 10107 10108 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 10109 if (ret) 10110 return ret; 10111 10112 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 10113 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 10114 if (ret) 10115 return ret; 10116 } 10117 10118 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10119 if (ret) 10120 goto restart; 10121 10122 idx = G_UPDBGLAWRPTR(val); 10123 if (wrptr) 10124 *wrptr = idx; 10125 10126 for (i = 0; i < adap->params.cim_la_size; i++) { 10127 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10128 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 10129 if (ret) 10130 break; 10131 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10132 if (ret) 10133 break; 10134 if (val & F_UPDBGLARDEN) { 10135 ret = -ETIMEDOUT; 10136 break; 10137 } 10138 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 10139 if (ret) 10140 break; 10141 10142 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 10143 * identify the 32-bit portion of the full 312-bit data 10144 */ 10145 if (is_t6(adap) && (idx & 0xf) >= 9) 10146 idx = (idx & 0xff0) + 0x10; 10147 else 10148 idx++; 10149 /* address can't exceed 0xfff */ 10150 idx &= M_UPDBGLARDPTR; 10151 } 10152 restart: 10153 if (cfg & F_UPDBGLAEN) { 10154 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10155 cfg & ~F_UPDBGLARDEN); 10156 if (!ret) 10157 ret = r; 10158 } 10159 return ret; 10160 } 10161 10162 /** 10163 * t4_tp_read_la - read TP LA capture buffer 10164 * @adap: the adapter 10165 * @la_buf: where to store the LA data 10166 * @wrptr: the HW write pointer within the capture buffer 10167 * 10168 * Reads the contents of the TP LA buffer with the most recent entry at 10169 * the end of the returned data and with the entry at @wrptr first. 10170 * We leave the LA in the running state we find it in. 10171 */ 10172 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 10173 { 10174 bool last_incomplete; 10175 unsigned int i, cfg, val, idx; 10176 10177 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 10178 if (cfg & F_DBGLAENABLE) /* freeze LA */ 10179 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10180 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 10181 10182 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 10183 idx = G_DBGLAWPTR(val); 10184 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 10185 if (last_incomplete) 10186 idx = (idx + 1) & M_DBGLARPTR; 10187 if (wrptr) 10188 *wrptr = idx; 10189 10190 val &= 0xffff; 10191 val &= ~V_DBGLARPTR(M_DBGLARPTR); 10192 val |= adap->params.tp.la_mask; 10193 10194 for (i = 0; i < TPLA_SIZE; i++) { 10195 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 10196 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 10197 idx = (idx + 1) & M_DBGLARPTR; 10198 } 10199 10200 /* Wipe out last entry if it isn't valid */ 10201 if (last_incomplete) 10202 la_buf[TPLA_SIZE - 1] = ~0ULL; 10203 10204 if (cfg & F_DBGLAENABLE) /* restore running state */ 10205 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10206 cfg | adap->params.tp.la_mask); 10207 } 10208 10209 /* 10210 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 10211 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 10212 * state for more than the Warning Threshold then we'll issue a warning about 10213 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 10214 * appears to be hung every Warning Repeat second till the situation clears. 10215 * If the situation clears, we'll note that as well. 10216 */ 10217 #define SGE_IDMA_WARN_THRESH 1 10218 #define SGE_IDMA_WARN_REPEAT 300 10219 10220 /** 10221 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 10222 * @adapter: the adapter 10223 * @idma: the adapter IDMA Monitor state 10224 * 10225 * Initialize the state of an SGE Ingress DMA Monitor. 10226 */ 10227 void t4_idma_monitor_init(struct adapter *adapter, 10228 struct sge_idma_monitor_state *idma) 10229 { 10230 /* Initialize the state variables for detecting an SGE Ingress DMA 10231 * hang. The SGE has internal counters which count up on each clock 10232 * tick whenever the SGE finds its Ingress DMA State Engines in the 10233 * same state they were on the previous clock tick. The clock used is 10234 * the Core Clock so we have a limit on the maximum "time" they can 10235 * record; typically a very small number of seconds. For instance, 10236 * with a 600MHz Core Clock, we can only count up to a bit more than 10237 * 7s. So we'll synthesize a larger counter in order to not run the 10238 * risk of having the "timers" overflow and give us the flexibility to 10239 * maintain a Hung SGE State Machine of our own which operates across 10240 * a longer time frame. 10241 */ 10242 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 10243 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 10244 } 10245 10246 /** 10247 * t4_idma_monitor - monitor SGE Ingress DMA state 10248 * @adapter: the adapter 10249 * @idma: the adapter IDMA Monitor state 10250 * @hz: number of ticks/second 10251 * @ticks: number of ticks since the last IDMA Monitor call 10252 */ 10253 void t4_idma_monitor(struct adapter *adapter, 10254 struct sge_idma_monitor_state *idma, 10255 int hz, int ticks) 10256 { 10257 int i, idma_same_state_cnt[2]; 10258 10259 /* Read the SGE Debug Ingress DMA Same State Count registers. These 10260 * are counters inside the SGE which count up on each clock when the 10261 * SGE finds its Ingress DMA State Engines in the same states they 10262 * were in the previous clock. The counters will peg out at 10263 * 0xffffffff without wrapping around so once they pass the 1s 10264 * threshold they'll stay above that till the IDMA state changes. 10265 */ 10266 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 10267 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 10268 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10269 10270 for (i = 0; i < 2; i++) { 10271 u32 debug0, debug11; 10272 10273 /* If the Ingress DMA Same State Counter ("timer") is less 10274 * than 1s, then we can reset our synthesized Stall Timer and 10275 * continue. If we have previously emitted warnings about a 10276 * potential stalled Ingress Queue, issue a note indicating 10277 * that the Ingress Queue has resumed forward progress. 10278 */ 10279 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 10280 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 10281 CH_WARN(adapter, "SGE idma%d, queue %u, " 10282 "resumed after %d seconds\n", 10283 i, idma->idma_qid[i], 10284 idma->idma_stalled[i]/hz); 10285 idma->idma_stalled[i] = 0; 10286 continue; 10287 } 10288 10289 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 10290 * domain. The first time we get here it'll be because we 10291 * passed the 1s Threshold; each additional time it'll be 10292 * because the RX Timer Callback is being fired on its regular 10293 * schedule. 10294 * 10295 * If the stall is below our Potential Hung Ingress Queue 10296 * Warning Threshold, continue. 10297 */ 10298 if (idma->idma_stalled[i] == 0) { 10299 idma->idma_stalled[i] = hz; 10300 idma->idma_warn[i] = 0; 10301 } else { 10302 idma->idma_stalled[i] += ticks; 10303 idma->idma_warn[i] -= ticks; 10304 } 10305 10306 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 10307 continue; 10308 10309 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 10310 */ 10311 if (idma->idma_warn[i] > 0) 10312 continue; 10313 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 10314 10315 /* Read and save the SGE IDMA State and Queue ID information. 10316 * We do this every time in case it changes across time ... 10317 * can't be too careful ... 10318 */ 10319 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 10320 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10321 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 10322 10323 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 10324 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10325 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 10326 10327 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 10328 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 10329 i, idma->idma_qid[i], idma->idma_state[i], 10330 idma->idma_stalled[i]/hz, 10331 debug0, debug11); 10332 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 10333 } 10334 } 10335 10336 /** 10337 * t4_set_vf_mac - Set MAC address for the specified VF 10338 * @adapter: The adapter 10339 * @pf: the PF used to instantiate the VFs 10340 * @vf: one of the VFs instantiated by the specified PF 10341 * @naddr: the number of MAC addresses 10342 * @addr: the MAC address(es) to be set to the specified VF 10343 */ 10344 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, 10345 unsigned int naddr, u8 *addr) 10346 { 10347 struct fw_acl_mac_cmd cmd; 10348 10349 memset(&cmd, 0, sizeof(cmd)); 10350 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | 10351 F_FW_CMD_REQUEST | 10352 F_FW_CMD_WRITE | 10353 V_FW_ACL_MAC_CMD_PFN(pf) | 10354 V_FW_ACL_MAC_CMD_VFN(vf)); 10355 10356 /* Note: Do not enable the ACL */ 10357 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); 10358 cmd.nmac = naddr; 10359 10360 switch (pf) { 10361 case 3: 10362 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); 10363 break; 10364 case 2: 10365 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); 10366 break; 10367 case 1: 10368 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); 10369 break; 10370 case 0: 10371 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); 10372 break; 10373 } 10374 10375 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); 10376 } 10377 10378 /** 10379 * t4_read_pace_tbl - read the pace table 10380 * @adap: the adapter 10381 * @pace_vals: holds the returned values 10382 * 10383 * Returns the values of TP's pace table in microseconds. 10384 */ 10385 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 10386 { 10387 unsigned int i, v; 10388 10389 for (i = 0; i < NTX_SCHED; i++) { 10390 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 10391 v = t4_read_reg(adap, A_TP_PACE_TABLE); 10392 pace_vals[i] = dack_ticks_to_usec(adap, v); 10393 } 10394 } 10395 10396 /** 10397 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 10398 * @adap: the adapter 10399 * @sched: the scheduler index 10400 * @kbps: the byte rate in Kbps 10401 * @ipg: the interpacket delay in tenths of nanoseconds 10402 * 10403 * Return the current configuration of a HW Tx scheduler. 10404 */ 10405 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 10406 unsigned int *ipg, bool sleep_ok) 10407 { 10408 unsigned int v, addr, bpt, cpt; 10409 10410 if (kbps) { 10411 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 10412 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10413 if (sched & 1) 10414 v >>= 16; 10415 bpt = (v >> 8) & 0xff; 10416 cpt = v & 0xff; 10417 if (!cpt) 10418 *kbps = 0; /* scheduler disabled */ 10419 else { 10420 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 10421 *kbps = (v * bpt) / 125; 10422 } 10423 } 10424 if (ipg) { 10425 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 10426 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10427 if (sched & 1) 10428 v >>= 16; 10429 v &= 0xffff; 10430 *ipg = (10000 * v) / core_ticks_per_usec(adap); 10431 } 10432 } 10433 10434 /** 10435 * t4_load_cfg - download config file 10436 * @adap: the adapter 10437 * @cfg_data: the cfg text file to write 10438 * @size: text file size 10439 * 10440 * Write the supplied config text file to the card's serial flash. 10441 */ 10442 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 10443 { 10444 int ret, i, n, cfg_addr; 10445 unsigned int addr; 10446 unsigned int flash_cfg_start_sec; 10447 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10448 10449 cfg_addr = t4_flash_cfg_addr(adap); 10450 if (cfg_addr < 0) 10451 return cfg_addr; 10452 10453 addr = cfg_addr; 10454 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10455 10456 if (size > FLASH_CFG_MAX_SIZE) { 10457 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 10458 FLASH_CFG_MAX_SIZE); 10459 return -EFBIG; 10460 } 10461 10462 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 10463 sf_sec_size); 10464 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10465 flash_cfg_start_sec + i - 1); 10466 /* 10467 * If size == 0 then we're simply erasing the FLASH sectors associated 10468 * with the on-adapter Firmware Configuration File. 10469 */ 10470 if (ret || size == 0) 10471 goto out; 10472 10473 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10474 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10475 if ( (size - i) < SF_PAGE_SIZE) 10476 n = size - i; 10477 else 10478 n = SF_PAGE_SIZE; 10479 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 10480 if (ret) 10481 goto out; 10482 10483 addr += SF_PAGE_SIZE; 10484 cfg_data += SF_PAGE_SIZE; 10485 } 10486 10487 out: 10488 if (ret) 10489 CH_ERR(adap, "config file %s failed %d\n", 10490 (size == 0 ? "clear" : "download"), ret); 10491 return ret; 10492 } 10493 10494 /** 10495 * t5_fw_init_extern_mem - initialize the external memory 10496 * @adap: the adapter 10497 * 10498 * Initializes the external memory on T5. 10499 */ 10500 int t5_fw_init_extern_mem(struct adapter *adap) 10501 { 10502 u32 params[1], val[1]; 10503 int ret; 10504 10505 if (!is_t5(adap)) 10506 return 0; 10507 10508 val[0] = 0xff; /* Initialize all MCs */ 10509 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10510 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10511 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10512 FW_CMD_MAX_TIMEOUT); 10513 10514 return ret; 10515 } 10516 10517 /* BIOS boot headers */ 10518 typedef struct pci_expansion_rom_header { 10519 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10520 u8 reserved[22]; /* Reserved per processor Architecture data */ 10521 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10522 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10523 10524 /* Legacy PCI Expansion ROM Header */ 10525 typedef struct legacy_pci_expansion_rom_header { 10526 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10527 u8 size512; /* Current Image Size in units of 512 bytes */ 10528 u8 initentry_point[4]; 10529 u8 cksum; /* Checksum computed on the entire Image */ 10530 u8 reserved[16]; /* Reserved */ 10531 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10532 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10533 10534 /* EFI PCI Expansion ROM Header */ 10535 typedef struct efi_pci_expansion_rom_header { 10536 u8 signature[2]; // ROM signature. The value 0xaa55 10537 u8 initialization_size[2]; /* Units 512. Includes this header */ 10538 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10539 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10540 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10541 u8 compression_type[2]; /* Compression type. */ 10542 /* 10543 * Compression type definition 10544 * 0x0: uncompressed 10545 * 0x1: Compressed 10546 * 0x2-0xFFFF: Reserved 10547 */ 10548 u8 reserved[8]; /* Reserved */ 10549 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10550 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10551 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10552 10553 /* PCI Data Structure Format */ 10554 typedef struct pcir_data_structure { /* PCI Data Structure */ 10555 u8 signature[4]; /* Signature. The string "PCIR" */ 10556 u8 vendor_id[2]; /* Vendor Identification */ 10557 u8 device_id[2]; /* Device Identification */ 10558 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10559 u8 length[2]; /* PCIR Data Structure Length */ 10560 u8 revision; /* PCIR Data Structure Revision */ 10561 u8 class_code[3]; /* Class Code */ 10562 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10563 u8 code_revision[2]; /* Revision Level of Code/Data */ 10564 u8 code_type; /* Code Type. */ 10565 /* 10566 * PCI Expansion ROM Code Types 10567 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10568 * 0x01: Open Firmware standard for PCI. FCODE 10569 * 0x02: Hewlett-Packard PA RISC. HP reserved 10570 * 0x03: EFI Image. EFI 10571 * 0x04-0xFF: Reserved. 10572 */ 10573 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10574 u8 reserved[2]; /* Reserved */ 10575 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10576 10577 /* BOOT constants */ 10578 enum { 10579 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10580 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10581 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10582 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10583 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10584 VENDOR_ID = 0x1425, /* Vendor ID */ 10585 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10586 }; 10587 10588 /* 10589 * modify_device_id - Modifies the device ID of the Boot BIOS image 10590 * @adatper: the device ID to write. 10591 * @boot_data: the boot image to modify. 10592 * 10593 * Write the supplied device ID to the boot BIOS image. 10594 */ 10595 static void modify_device_id(int device_id, u8 *boot_data) 10596 { 10597 legacy_pci_exp_rom_header_t *header; 10598 pcir_data_t *pcir_header; 10599 u32 cur_header = 0; 10600 10601 /* 10602 * Loop through all chained images and change the device ID's 10603 */ 10604 while (1) { 10605 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10606 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10607 le16_to_cpu(*(u16*)header->pcir_offset)]; 10608 10609 /* 10610 * Only modify the Device ID if code type is Legacy or HP. 10611 * 0x00: Okay to modify 10612 * 0x01: FCODE. Do not be modify 10613 * 0x03: Okay to modify 10614 * 0x04-0xFF: Do not modify 10615 */ 10616 if (pcir_header->code_type == 0x00) { 10617 u8 csum = 0; 10618 int i; 10619 10620 /* 10621 * Modify Device ID to match current adatper 10622 */ 10623 *(u16*) pcir_header->device_id = device_id; 10624 10625 /* 10626 * Set checksum temporarily to 0. 10627 * We will recalculate it later. 10628 */ 10629 header->cksum = 0x0; 10630 10631 /* 10632 * Calculate and update checksum 10633 */ 10634 for (i = 0; i < (header->size512 * 512); i++) 10635 csum += (u8)boot_data[cur_header + i]; 10636 10637 /* 10638 * Invert summed value to create the checksum 10639 * Writing new checksum value directly to the boot data 10640 */ 10641 boot_data[cur_header + 7] = -csum; 10642 10643 } else if (pcir_header->code_type == 0x03) { 10644 10645 /* 10646 * Modify Device ID to match current adatper 10647 */ 10648 *(u16*) pcir_header->device_id = device_id; 10649 10650 } 10651 10652 10653 /* 10654 * Check indicator element to identify if this is the last 10655 * image in the ROM. 10656 */ 10657 if (pcir_header->indicator & 0x80) 10658 break; 10659 10660 /* 10661 * Move header pointer up to the next image in the ROM. 10662 */ 10663 cur_header += header->size512 * 512; 10664 } 10665 } 10666 10667 /* 10668 * t4_load_boot - download boot flash 10669 * @adapter: the adapter 10670 * @boot_data: the boot image to write 10671 * @boot_addr: offset in flash to write boot_data 10672 * @size: image size 10673 * 10674 * Write the supplied boot image to the card's serial flash. 10675 * The boot image has the following sections: a 28-byte header and the 10676 * boot image. 10677 */ 10678 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10679 unsigned int boot_addr, unsigned int size) 10680 { 10681 pci_exp_rom_header_t *header; 10682 int pcir_offset ; 10683 pcir_data_t *pcir_header; 10684 int ret, addr; 10685 uint16_t device_id; 10686 unsigned int i; 10687 unsigned int boot_sector = (boot_addr * 1024 ); 10688 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10689 10690 /* 10691 * Make sure the boot image does not encroach on the firmware region 10692 */ 10693 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10694 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10695 return -EFBIG; 10696 } 10697 10698 /* 10699 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10700 * and Boot configuration data sections. These 3 boot sections span 10701 * sectors 0 to 7 in flash and live right before the FW image location. 10702 */ 10703 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10704 sf_sec_size); 10705 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10706 (boot_sector >> 16) + i - 1); 10707 10708 /* 10709 * If size == 0 then we're simply erasing the FLASH sectors associated 10710 * with the on-adapter option ROM file 10711 */ 10712 if (ret || (size == 0)) 10713 goto out; 10714 10715 /* Get boot header */ 10716 header = (pci_exp_rom_header_t *)boot_data; 10717 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10718 /* PCIR Data Structure */ 10719 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10720 10721 /* 10722 * Perform some primitive sanity testing to avoid accidentally 10723 * writing garbage over the boot sectors. We ought to check for 10724 * more but it's not worth it for now ... 10725 */ 10726 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10727 CH_ERR(adap, "boot image too small/large\n"); 10728 return -EFBIG; 10729 } 10730 10731 #ifndef CHELSIO_T4_DIAGS 10732 /* 10733 * Check BOOT ROM header signature 10734 */ 10735 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10736 CH_ERR(adap, "Boot image missing signature\n"); 10737 return -EINVAL; 10738 } 10739 10740 /* 10741 * Check PCI header signature 10742 */ 10743 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10744 CH_ERR(adap, "PCI header missing signature\n"); 10745 return -EINVAL; 10746 } 10747 10748 /* 10749 * Check Vendor ID matches Chelsio ID 10750 */ 10751 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10752 CH_ERR(adap, "Vendor ID missing signature\n"); 10753 return -EINVAL; 10754 } 10755 #endif 10756 10757 /* 10758 * Retrieve adapter's device ID 10759 */ 10760 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10761 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10762 device_id = device_id & 0xf0ff; 10763 10764 /* 10765 * Check PCIE Device ID 10766 */ 10767 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10768 /* 10769 * Change the device ID in the Boot BIOS image to match 10770 * the Device ID of the current adapter. 10771 */ 10772 modify_device_id(device_id, boot_data); 10773 } 10774 10775 /* 10776 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10777 * we finish copying the rest of the boot image. This will ensure 10778 * that the BIOS boot header will only be written if the boot image 10779 * was written in full. 10780 */ 10781 addr = boot_sector; 10782 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10783 addr += SF_PAGE_SIZE; 10784 boot_data += SF_PAGE_SIZE; 10785 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10786 if (ret) 10787 goto out; 10788 } 10789 10790 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10791 (const u8 *)header, 0); 10792 10793 out: 10794 if (ret) 10795 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10796 return ret; 10797 } 10798 10799 /* 10800 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10801 * @adapter: the adapter 10802 * 10803 * Return the address within the flash where the OptionROM Configuration 10804 * is stored, or an error if the device FLASH is too small to contain 10805 * a OptionROM Configuration. 10806 */ 10807 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10808 { 10809 /* 10810 * If the device FLASH isn't large enough to hold a Firmware 10811 * Configuration File, return an error. 10812 */ 10813 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10814 return -ENOSPC; 10815 10816 return FLASH_BOOTCFG_START; 10817 } 10818 10819 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10820 { 10821 int ret, i, n, cfg_addr; 10822 unsigned int addr; 10823 unsigned int flash_cfg_start_sec; 10824 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10825 10826 cfg_addr = t4_flash_bootcfg_addr(adap); 10827 if (cfg_addr < 0) 10828 return cfg_addr; 10829 10830 addr = cfg_addr; 10831 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10832 10833 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10834 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10835 FLASH_BOOTCFG_MAX_SIZE); 10836 return -EFBIG; 10837 } 10838 10839 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10840 sf_sec_size); 10841 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10842 flash_cfg_start_sec + i - 1); 10843 10844 /* 10845 * If size == 0 then we're simply erasing the FLASH sectors associated 10846 * with the on-adapter OptionROM Configuration File. 10847 */ 10848 if (ret || size == 0) 10849 goto out; 10850 10851 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10852 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10853 if ( (size - i) < SF_PAGE_SIZE) 10854 n = size - i; 10855 else 10856 n = SF_PAGE_SIZE; 10857 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10858 if (ret) 10859 goto out; 10860 10861 addr += SF_PAGE_SIZE; 10862 cfg_data += SF_PAGE_SIZE; 10863 } 10864 10865 out: 10866 if (ret) 10867 CH_ERR(adap, "boot config data %s failed %d\n", 10868 (size == 0 ? "clear" : "download"), ret); 10869 return ret; 10870 } 10871 10872 /** 10873 * t4_set_filter_cfg - set up filter mode/mask and ingress config. 10874 * @adap: the adapter 10875 * @mode: a bitmap selecting which optional filter components to enable 10876 * @mask: a bitmap selecting which components to enable in filter mask 10877 * @vnic_mode: the ingress config/vnic mode setting 10878 * 10879 * Sets the filter mode and mask by selecting the optional components to 10880 * enable in filter tuples. Returns 0 on success and a negative error if 10881 * the requested mode needs more bits than are available for optional 10882 * components. The filter mask must be a subset of the filter mode. 10883 */ 10884 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) 10885 { 10886 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 10887 int i, nbits, rc; 10888 uint32_t param, val; 10889 uint16_t fmode, fmask; 10890 const int maxbits = adap->chip_params->filter_opt_len; 10891 10892 if (mode != -1 || mask != -1) { 10893 if (mode != -1) { 10894 fmode = mode; 10895 nbits = 0; 10896 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10897 if (fmode & (1 << i)) 10898 nbits += width[i]; 10899 } 10900 if (nbits > maxbits) { 10901 CH_ERR(adap, "optional fields in the filter " 10902 "mode (0x%x) add up to %d bits " 10903 "(must be <= %db). Remove some fields and " 10904 "try again.\n", fmode, nbits, maxbits); 10905 return -E2BIG; 10906 } 10907 10908 /* 10909 * Hardware wants the bits to be maxed out. Keep 10910 * setting them until there's no room for more. 10911 */ 10912 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10913 if (fmode & (1 << i)) 10914 continue; 10915 if (nbits + width[i] <= maxbits) { 10916 fmode |= 1 << i; 10917 nbits += width[i]; 10918 if (nbits == maxbits) 10919 break; 10920 } 10921 } 10922 10923 fmask = fmode & adap->params.tp.filter_mask; 10924 if (fmask != adap->params.tp.filter_mask) { 10925 CH_WARN(adap, 10926 "filter mask will be changed from 0x%x to " 10927 "0x%x to comply with the filter mode (0x%x).\n", 10928 adap->params.tp.filter_mask, fmask, fmode); 10929 } 10930 } else { 10931 fmode = adap->params.tp.filter_mode; 10932 fmask = mask; 10933 if ((fmode | fmask) != fmode) { 10934 CH_ERR(adap, 10935 "filter mask (0x%x) must be a subset of " 10936 "the filter mode (0x%x).\n", fmask, fmode); 10937 return -EINVAL; 10938 } 10939 } 10940 10941 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10942 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10943 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 10944 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) | 10945 V_FW_PARAMS_PARAM_FILTER_MASK(fmask); 10946 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10947 &val); 10948 if (rc < 0) 10949 return rc; 10950 } 10951 10952 if (vnic_mode != -1) { 10953 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10954 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10955 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 10956 val = vnic_mode; 10957 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10958 &val); 10959 if (rc < 0) 10960 return rc; 10961 } 10962 10963 /* Refresh. */ 10964 read_filter_mode_and_ingress_config(adap); 10965 10966 return 0; 10967 } 10968 10969 /** 10970 * t4_clr_port_stats - clear port statistics 10971 * @adap: the adapter 10972 * @idx: the port index 10973 * 10974 * Clear HW statistics for the given port. 10975 */ 10976 void t4_clr_port_stats(struct adapter *adap, int idx) 10977 { 10978 unsigned int i; 10979 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 10980 u32 port_base_addr; 10981 10982 if (is_t4(adap)) 10983 port_base_addr = PORT_BASE(idx); 10984 else 10985 port_base_addr = T5_PORT_BASE(idx); 10986 10987 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 10988 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 10989 t4_write_reg(adap, port_base_addr + i, 0); 10990 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 10991 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 10992 t4_write_reg(adap, port_base_addr + i, 0); 10993 for (i = 0; i < 4; i++) 10994 if (bgmap & (1 << i)) { 10995 t4_write_reg(adap, 10996 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 10997 t4_write_reg(adap, 10998 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 10999 } 11000 } 11001 11002 /** 11003 * t4_i2c_io - read/write I2C data from adapter 11004 * @adap: the adapter 11005 * @port: Port number if per-port device; <0 if not 11006 * @devid: per-port device ID or absolute device ID 11007 * @offset: byte offset into device I2C space 11008 * @len: byte length of I2C space data 11009 * @buf: buffer in which to return I2C data for read 11010 * buffer which holds the I2C data for write 11011 * @write: if true, do a write; else do a read 11012 * Reads/Writes the I2C data from/to the indicated device and location. 11013 */ 11014 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 11015 int port, unsigned int devid, 11016 unsigned int offset, unsigned int len, 11017 u8 *buf, bool write) 11018 { 11019 struct fw_ldst_cmd ldst_cmd, ldst_rpl; 11020 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data); 11021 int ret = 0; 11022 11023 if (len > I2C_PAGE_SIZE) 11024 return -EINVAL; 11025 11026 /* Dont allow reads that spans multiple pages */ 11027 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) 11028 return -EINVAL; 11029 11030 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 11031 ldst_cmd.op_to_addrspace = 11032 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11033 F_FW_CMD_REQUEST | 11034 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) | 11035 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 11036 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 11037 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); 11038 ldst_cmd.u.i2c.did = devid; 11039 11040 while (len > 0) { 11041 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max; 11042 11043 ldst_cmd.u.i2c.boffset = offset; 11044 ldst_cmd.u.i2c.blen = i2c_len; 11045 11046 if (write) 11047 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len); 11048 11049 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd), 11050 write ? NULL : &ldst_rpl); 11051 if (ret) 11052 break; 11053 11054 if (!write) 11055 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len); 11056 offset += i2c_len; 11057 buf += i2c_len; 11058 len -= i2c_len; 11059 } 11060 11061 return ret; 11062 } 11063 11064 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 11065 int port, unsigned int devid, 11066 unsigned int offset, unsigned int len, 11067 u8 *buf) 11068 { 11069 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false); 11070 } 11071 11072 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 11073 int port, unsigned int devid, 11074 unsigned int offset, unsigned int len, 11075 u8 *buf) 11076 { 11077 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true); 11078 } 11079 11080 /** 11081 * t4_sge_ctxt_rd - read an SGE context through FW 11082 * @adap: the adapter 11083 * @mbox: mailbox to use for the FW command 11084 * @cid: the context id 11085 * @ctype: the context type 11086 * @data: where to store the context data 11087 * 11088 * Issues a FW command through the given mailbox to read an SGE context. 11089 */ 11090 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 11091 enum ctxt_type ctype, u32 *data) 11092 { 11093 int ret; 11094 struct fw_ldst_cmd c; 11095 11096 if (ctype == CTXT_EGRESS) 11097 ret = FW_LDST_ADDRSPC_SGE_EGRC; 11098 else if (ctype == CTXT_INGRESS) 11099 ret = FW_LDST_ADDRSPC_SGE_INGC; 11100 else if (ctype == CTXT_FLM) 11101 ret = FW_LDST_ADDRSPC_SGE_FLMC; 11102 else 11103 ret = FW_LDST_ADDRSPC_SGE_CONMC; 11104 11105 memset(&c, 0, sizeof(c)); 11106 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11107 F_FW_CMD_REQUEST | F_FW_CMD_READ | 11108 V_FW_LDST_CMD_ADDRSPACE(ret)); 11109 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 11110 c.u.idctxt.physid = cpu_to_be32(cid); 11111 11112 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11113 if (ret == 0) { 11114 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 11115 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 11116 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 11117 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 11118 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 11119 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 11120 } 11121 return ret; 11122 } 11123 11124 /** 11125 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 11126 * @adap: the adapter 11127 * @cid: the context id 11128 * @ctype: the context type 11129 * @data: where to store the context data 11130 * 11131 * Reads an SGE context directly, bypassing FW. This is only for 11132 * debugging when FW is unavailable. 11133 */ 11134 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 11135 u32 *data) 11136 { 11137 int i, ret; 11138 11139 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 11140 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 11141 if (!ret) 11142 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 11143 *data++ = t4_read_reg(adap, i); 11144 return ret; 11145 } 11146 11147 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 11148 int sleep_ok) 11149 { 11150 struct fw_sched_cmd cmd; 11151 11152 memset(&cmd, 0, sizeof(cmd)); 11153 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11154 F_FW_CMD_REQUEST | 11155 F_FW_CMD_WRITE); 11156 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11157 11158 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 11159 cmd.u.config.type = type; 11160 cmd.u.config.minmaxen = minmaxen; 11161 11162 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11163 NULL, sleep_ok); 11164 } 11165 11166 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 11167 int rateunit, int ratemode, int channel, int cl, 11168 int minrate, int maxrate, int weight, int pktsize, 11169 int burstsize, int sleep_ok) 11170 { 11171 struct fw_sched_cmd cmd; 11172 11173 memset(&cmd, 0, sizeof(cmd)); 11174 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11175 F_FW_CMD_REQUEST | 11176 F_FW_CMD_WRITE); 11177 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11178 11179 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11180 cmd.u.params.type = type; 11181 cmd.u.params.level = level; 11182 cmd.u.params.mode = mode; 11183 cmd.u.params.ch = channel; 11184 cmd.u.params.cl = cl; 11185 cmd.u.params.unit = rateunit; 11186 cmd.u.params.rate = ratemode; 11187 cmd.u.params.min = cpu_to_be32(minrate); 11188 cmd.u.params.max = cpu_to_be32(maxrate); 11189 cmd.u.params.weight = cpu_to_be16(weight); 11190 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11191 cmd.u.params.burstsize = cpu_to_be16(burstsize); 11192 11193 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11194 NULL, sleep_ok); 11195 } 11196 11197 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 11198 unsigned int maxrate, int sleep_ok) 11199 { 11200 struct fw_sched_cmd cmd; 11201 11202 memset(&cmd, 0, sizeof(cmd)); 11203 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11204 F_FW_CMD_REQUEST | 11205 F_FW_CMD_WRITE); 11206 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11207 11208 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11209 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11210 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 11211 cmd.u.params.ch = channel; 11212 cmd.u.params.rate = ratemode; /* REL or ABS */ 11213 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 11214 11215 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11216 NULL, sleep_ok); 11217 } 11218 11219 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 11220 int weight, int sleep_ok) 11221 { 11222 struct fw_sched_cmd cmd; 11223 11224 if (weight < 0 || weight > 100) 11225 return -EINVAL; 11226 11227 memset(&cmd, 0, sizeof(cmd)); 11228 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11229 F_FW_CMD_REQUEST | 11230 F_FW_CMD_WRITE); 11231 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11232 11233 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11234 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11235 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 11236 cmd.u.params.ch = channel; 11237 cmd.u.params.cl = cl; 11238 cmd.u.params.weight = cpu_to_be16(weight); 11239 11240 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11241 NULL, sleep_ok); 11242 } 11243 11244 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 11245 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 11246 { 11247 struct fw_sched_cmd cmd; 11248 11249 memset(&cmd, 0, sizeof(cmd)); 11250 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11251 F_FW_CMD_REQUEST | 11252 F_FW_CMD_WRITE); 11253 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11254 11255 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11256 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11257 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 11258 cmd.u.params.mode = mode; 11259 cmd.u.params.ch = channel; 11260 cmd.u.params.cl = cl; 11261 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 11262 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 11263 cmd.u.params.max = cpu_to_be32(maxrate); 11264 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11265 11266 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11267 NULL, sleep_ok); 11268 } 11269 11270 /* 11271 * t4_config_watchdog - configure (enable/disable) a watchdog timer 11272 * @adapter: the adapter 11273 * @mbox: mailbox to use for the FW command 11274 * @pf: the PF owning the queue 11275 * @vf: the VF owning the queue 11276 * @timeout: watchdog timeout in ms 11277 * @action: watchdog timer / action 11278 * 11279 * There are separate watchdog timers for each possible watchdog 11280 * action. Configure one of the watchdog timers by setting a non-zero 11281 * timeout. Disable a watchdog timer by using a timeout of zero. 11282 */ 11283 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 11284 unsigned int pf, unsigned int vf, 11285 unsigned int timeout, unsigned int action) 11286 { 11287 struct fw_watchdog_cmd wdog; 11288 unsigned int ticks; 11289 11290 /* 11291 * The watchdog command expects a timeout in units of 10ms so we need 11292 * to convert it here (via rounding) and force a minimum of one 10ms 11293 * "tick" if the timeout is non-zero but the conversion results in 0 11294 * ticks. 11295 */ 11296 ticks = (timeout + 5)/10; 11297 if (timeout && !ticks) 11298 ticks = 1; 11299 11300 memset(&wdog, 0, sizeof wdog); 11301 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 11302 F_FW_CMD_REQUEST | 11303 F_FW_CMD_WRITE | 11304 V_FW_PARAMS_CMD_PFN(pf) | 11305 V_FW_PARAMS_CMD_VFN(vf)); 11306 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 11307 wdog.timeout = cpu_to_be32(ticks); 11308 wdog.action = cpu_to_be32(action); 11309 11310 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 11311 } 11312 11313 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 11314 { 11315 struct fw_devlog_cmd devlog_cmd; 11316 int ret; 11317 11318 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11319 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11320 F_FW_CMD_REQUEST | F_FW_CMD_READ); 11321 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11322 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11323 sizeof(devlog_cmd), &devlog_cmd); 11324 if (ret) 11325 return ret; 11326 11327 *level = devlog_cmd.level; 11328 return 0; 11329 } 11330 11331 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 11332 { 11333 struct fw_devlog_cmd devlog_cmd; 11334 11335 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11336 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11337 F_FW_CMD_REQUEST | 11338 F_FW_CMD_WRITE); 11339 devlog_cmd.level = level; 11340 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11341 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11342 sizeof(devlog_cmd), &devlog_cmd); 11343 } 11344 11345 int t4_configure_add_smac(struct adapter *adap) 11346 { 11347 unsigned int param, val; 11348 int ret = 0; 11349 11350 adap->params.smac_add_support = 0; 11351 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11352 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC)); 11353 /* Query FW to check if FW supports adding source mac address 11354 * to TCAM feature or not. 11355 * If FW returns 1, driver can use this feature and driver need to send 11356 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to 11357 * enable adding smac to TCAM. 11358 */ 11359 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11360 if (ret) 11361 return ret; 11362 11363 if (val == 1) { 11364 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 11365 ¶m, &val); 11366 if (!ret) 11367 /* Firmware allows adding explicit TCAM entries. 11368 * Save this internally. 11369 */ 11370 adap->params.smac_add_support = 1; 11371 } 11372 11373 return ret; 11374 } 11375 11376 int t4_configure_ringbb(struct adapter *adap) 11377 { 11378 unsigned int param, val; 11379 int ret = 0; 11380 11381 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11382 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE)); 11383 /* Query FW to check if FW supports ring switch feature or not. 11384 * If FW returns 1, driver can use this feature and driver need to send 11385 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to 11386 * enable the ring backbone configuration. 11387 */ 11388 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11389 if (ret < 0) { 11390 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n", 11391 ret); 11392 goto out; 11393 } 11394 11395 if (val != 1) { 11396 CH_ERR(adap, "FW doesnot support ringbackbone features\n"); 11397 goto out; 11398 } 11399 11400 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11401 if (ret < 0) { 11402 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n", 11403 ret); 11404 goto out; 11405 } 11406 11407 out: 11408 return ret; 11409 } 11410 11411 /* 11412 * t4_set_vlan_acl - Set a VLAN id for the specified VF 11413 * @adapter: the adapter 11414 * @mbox: mailbox to use for the FW command 11415 * @vf: one of the VFs instantiated by the specified PF 11416 * @vlan: The vlanid to be set 11417 * 11418 */ 11419 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 11420 u16 vlan) 11421 { 11422 struct fw_acl_vlan_cmd vlan_cmd; 11423 unsigned int enable; 11424 11425 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); 11426 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); 11427 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) | 11428 F_FW_CMD_REQUEST | 11429 F_FW_CMD_WRITE | 11430 F_FW_CMD_EXEC | 11431 V_FW_ACL_VLAN_CMD_PFN(adap->pf) | 11432 V_FW_ACL_VLAN_CMD_VFN(vf)); 11433 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd)); 11434 /* Drop all packets that donot match vlan id */ 11435 vlan_cmd.dropnovlan_fm = (enable 11436 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN | 11437 F_FW_ACL_VLAN_CMD_FM) 11438 : 0); 11439 if (enable != 0) { 11440 vlan_cmd.nvlan = 1; 11441 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); 11442 } 11443 11444 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); 11445 } 11446 11447 /** 11448 * t4_del_mac - Removes the exact-match filter for a MAC address 11449 * @adap: the adapter 11450 * @mbox: mailbox to use for the FW command 11451 * @viid: the VI id 11452 * @addr: the MAC address value 11453 * @smac: if true, delete from only the smac region of MPS 11454 * 11455 * Modifies an exact-match filter and sets it to the new MAC address if 11456 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11457 * latter case the address is added persistently if @persist is %true. 11458 * 11459 * Returns a negative error number or the index of the filter with the new 11460 * MAC value. Note that this index may differ from @idx. 11461 */ 11462 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11463 const u8 *addr, bool smac) 11464 { 11465 int ret; 11466 struct fw_vi_mac_cmd c; 11467 struct fw_vi_mac_exact *p = c.u.exact; 11468 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11469 11470 memset(&c, 0, sizeof(c)); 11471 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11472 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11473 V_FW_VI_MAC_CMD_VIID(viid)); 11474 c.freemacs_to_len16 = cpu_to_be32( 11475 V_FW_CMD_LEN16(1) | 11476 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11477 11478 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11479 p->valid_to_idx = cpu_to_be16( 11480 F_FW_VI_MAC_CMD_VALID | 11481 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 11482 11483 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11484 if (ret == 0) { 11485 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11486 if (ret < max_mac_addr) 11487 return -ENOMEM; 11488 } 11489 11490 return ret; 11491 } 11492 11493 /** 11494 * t4_add_mac - Adds an exact-match filter for a MAC address 11495 * @adap: the adapter 11496 * @mbox: mailbox to use for the FW command 11497 * @viid: the VI id 11498 * @idx: index of existing filter for old value of MAC address, or -1 11499 * @addr: the new MAC address value 11500 * @persist: whether a new MAC allocation should be persistent 11501 * @add_smt: if true also add the address to the HW SMT 11502 * @smac: if true, update only the smac region of MPS 11503 * 11504 * Modifies an exact-match filter and sets it to the new MAC address if 11505 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11506 * latter case the address is added persistently if @persist is %true. 11507 * 11508 * Returns a negative error number or the index of the filter with the new 11509 * MAC value. Note that this index may differ from @idx. 11510 */ 11511 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11512 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac) 11513 { 11514 int ret, mode; 11515 struct fw_vi_mac_cmd c; 11516 struct fw_vi_mac_exact *p = c.u.exact; 11517 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11518 11519 if (idx < 0) /* new allocation */ 11520 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 11521 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 11522 11523 memset(&c, 0, sizeof(c)); 11524 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11525 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11526 V_FW_VI_MAC_CMD_VIID(viid)); 11527 c.freemacs_to_len16 = cpu_to_be32( 11528 V_FW_CMD_LEN16(1) | 11529 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11530 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 11531 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 11532 V_FW_VI_MAC_CMD_IDX(idx)); 11533 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11534 11535 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11536 if (ret == 0) { 11537 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11538 if (ret >= max_mac_addr) 11539 return -ENOMEM; 11540 if (smt_idx) { 11541 /* Does fw supports returning smt_idx? */ 11542 if (adap->params.viid_smt_extn_support) 11543 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 11544 else { 11545 /* In T4/T5, SMT contains 256 SMAC entries 11546 * organized in 128 rows of 2 entries each. 11547 * In T6, SMT contains 256 SMAC entries in 11548 * 256 rows. 11549 */ 11550 if (chip_id(adap) <= CHELSIO_T5) 11551 *smt_idx = ((viid & M_FW_VIID_VIN) << 1); 11552 else 11553 *smt_idx = (viid & M_FW_VIID_VIN); 11554 } 11555 } 11556 } 11557 11558 return ret; 11559 } 11560