1 /*- 2 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_inet.h" 31 32 #include <sys/param.h> 33 #include <sys/eventhandler.h> 34 35 #include "common.h" 36 #include "t4_regs.h" 37 #include "t4_regs_values.h" 38 #include "firmware/t4fw_interface.h" 39 40 #undef msleep 41 #define msleep(x) do { \ 42 if (cold) \ 43 DELAY((x) * 1000); \ 44 else \ 45 pause("t4hw", (x) * hz / 1000); \ 46 } while (0) 47 48 /** 49 * t4_wait_op_done_val - wait until an operation is completed 50 * @adapter: the adapter performing the operation 51 * @reg: the register to check for completion 52 * @mask: a single-bit field within @reg that indicates completion 53 * @polarity: the value of the field when the operation is completed 54 * @attempts: number of check iterations 55 * @delay: delay in usecs between iterations 56 * @valp: where to store the value of the register at completion time 57 * 58 * Wait until an operation is completed by checking a bit in a register 59 * up to @attempts times. If @valp is not NULL the value of the register 60 * at the time it indicated completion is stored there. Returns 0 if the 61 * operation completes and -EAGAIN otherwise. 62 */ 63 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 64 int polarity, int attempts, int delay, u32 *valp) 65 { 66 while (1) { 67 u32 val = t4_read_reg(adapter, reg); 68 69 if (!!(val & mask) == polarity) { 70 if (valp) 71 *valp = val; 72 return 0; 73 } 74 if (--attempts == 0) 75 return -EAGAIN; 76 if (delay) 77 udelay(delay); 78 } 79 } 80 81 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 82 int polarity, int attempts, int delay) 83 { 84 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 85 delay, NULL); 86 } 87 88 /** 89 * t4_set_reg_field - set a register field to a value 90 * @adapter: the adapter to program 91 * @addr: the register address 92 * @mask: specifies the portion of the register to modify 93 * @val: the new value for the register field 94 * 95 * Sets a register field specified by the supplied mask to the 96 * given value. 97 */ 98 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 99 u32 val) 100 { 101 u32 v = t4_read_reg(adapter, addr) & ~mask; 102 103 t4_write_reg(adapter, addr, v | val); 104 (void) t4_read_reg(adapter, addr); /* flush */ 105 } 106 107 /** 108 * t4_read_indirect - read indirectly addressed registers 109 * @adap: the adapter 110 * @addr_reg: register holding the indirect address 111 * @data_reg: register holding the value of the indirect register 112 * @vals: where the read register values are stored 113 * @nregs: how many indirect registers to read 114 * @start_idx: index of first indirect register to read 115 * 116 * Reads registers that are accessed indirectly through an address/data 117 * register pair. 118 */ 119 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 120 unsigned int data_reg, u32 *vals, 121 unsigned int nregs, unsigned int start_idx) 122 { 123 while (nregs--) { 124 t4_write_reg(adap, addr_reg, start_idx); 125 *vals++ = t4_read_reg(adap, data_reg); 126 start_idx++; 127 } 128 } 129 130 /** 131 * t4_write_indirect - write indirectly addressed registers 132 * @adap: the adapter 133 * @addr_reg: register holding the indirect addresses 134 * @data_reg: register holding the value for the indirect registers 135 * @vals: values to write 136 * @nregs: how many indirect registers to write 137 * @start_idx: address of first indirect register to write 138 * 139 * Writes a sequential block of registers that are accessed indirectly 140 * through an address/data register pair. 141 */ 142 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 143 unsigned int data_reg, const u32 *vals, 144 unsigned int nregs, unsigned int start_idx) 145 { 146 while (nregs--) { 147 t4_write_reg(adap, addr_reg, start_idx++); 148 t4_write_reg(adap, data_reg, *vals++); 149 } 150 } 151 152 /* 153 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 154 * mechanism. This guarantees that we get the real value even if we're 155 * operating within a Virtual Machine and the Hypervisor is trapping our 156 * Configuration Space accesses. 157 * 158 * N.B. This routine should only be used as a last resort: the firmware uses 159 * the backdoor registers on a regular basis and we can end up 160 * conflicting with it's uses! 161 */ 162 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 163 { 164 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 165 u32 val; 166 167 if (chip_id(adap) <= CHELSIO_T5) 168 req |= F_ENABLE; 169 else 170 req |= F_T6_ENABLE; 171 172 if (is_t4(adap)) 173 req |= F_LOCALCFG; 174 175 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 176 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 177 178 /* 179 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 180 * Configuration Space read. (None of the other fields matter when 181 * F_ENABLE is 0 so a simple register write is easier than a 182 * read-modify-write via t4_set_reg_field().) 183 */ 184 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 185 186 return val; 187 } 188 189 /* 190 * t4_report_fw_error - report firmware error 191 * @adap: the adapter 192 * 193 * The adapter firmware can indicate error conditions to the host. 194 * If the firmware has indicated an error, print out the reason for 195 * the firmware error. 196 */ 197 static void t4_report_fw_error(struct adapter *adap) 198 { 199 static const char *const reason[] = { 200 "Crash", /* PCIE_FW_EVAL_CRASH */ 201 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 202 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 203 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 204 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 205 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 206 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 207 "Reserved", /* reserved */ 208 }; 209 u32 pcie_fw; 210 211 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 212 if (pcie_fw & F_PCIE_FW_ERR) 213 CH_ERR(adap, "Firmware reports adapter error: %s\n", 214 reason[G_PCIE_FW_EVAL(pcie_fw)]); 215 } 216 217 /* 218 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 219 */ 220 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 221 u32 mbox_addr) 222 { 223 for ( ; nflit; nflit--, mbox_addr += 8) 224 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 225 } 226 227 /* 228 * Handle a FW assertion reported in a mailbox. 229 */ 230 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 231 { 232 CH_ALERT(adap, 233 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 234 asrt->u.assert.filename_0_7, 235 be32_to_cpu(asrt->u.assert.line), 236 be32_to_cpu(asrt->u.assert.x), 237 be32_to_cpu(asrt->u.assert.y)); 238 } 239 240 #define X_CIM_PF_NOACCESS 0xeeeeeeee 241 /** 242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 243 * @adap: the adapter 244 * @mbox: index of the mailbox to use 245 * @cmd: the command to write 246 * @size: command length in bytes 247 * @rpl: where to optionally store the reply 248 * @sleep_ok: if true we may sleep while awaiting command completion 249 * @timeout: time to wait for command to finish before timing out 250 * (negative implies @sleep_ok=false) 251 * 252 * Sends the given command to FW through the selected mailbox and waits 253 * for the FW to execute the command. If @rpl is not %NULL it is used to 254 * store the FW's reply to the command. The command and its optional 255 * reply are of the same length. Some FW commands like RESET and 256 * INITIALIZE can take a considerable amount of time to execute. 257 * @sleep_ok determines whether we may sleep while awaiting the response. 258 * If sleeping is allowed we use progressive backoff otherwise we spin. 259 * Note that passing in a negative @timeout is an alternate mechanism 260 * for specifying @sleep_ok=false. This is useful when a higher level 261 * interface allows for specification of @timeout but not @sleep_ok ... 262 * 263 * The return value is 0 on success or a negative errno on failure. A 264 * failure can happen either because we are not able to execute the 265 * command or FW executes it but signals an error. In the latter case 266 * the return value is the error code indicated by FW (negated). 267 */ 268 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 269 int size, void *rpl, bool sleep_ok, int timeout) 270 { 271 /* 272 * We delay in small increments at first in an effort to maintain 273 * responsiveness for simple, fast executing commands but then back 274 * off to larger delays to a maximum retry delay. 275 */ 276 static const int delay[] = { 277 1, 1, 3, 5, 10, 10, 20, 50, 100 278 }; 279 u32 v; 280 u64 res; 281 int i, ms, delay_idx, ret; 282 const __be64 *p = cmd; 283 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 284 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 285 u32 ctl; 286 __be64 cmd_rpl[MBOX_LEN/8]; 287 u32 pcie_fw; 288 289 if ((size & 15) || size > MBOX_LEN) 290 return -EINVAL; 291 292 if (adap->flags & IS_VF) { 293 if (is_t6(adap)) 294 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 295 else 296 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 297 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 298 } 299 300 /* 301 * If we have a negative timeout, that implies that we can't sleep. 302 */ 303 if (timeout < 0) { 304 sleep_ok = false; 305 timeout = -timeout; 306 } 307 308 /* 309 * Attempt to gain access to the mailbox. 310 */ 311 for (i = 0; i < 4; i++) { 312 ctl = t4_read_reg(adap, ctl_reg); 313 v = G_MBOWNER(ctl); 314 if (v != X_MBOWNER_NONE) 315 break; 316 } 317 318 /* 319 * If we were unable to gain access, dequeue ourselves from the 320 * mailbox atomic access list and report the error to our caller. 321 */ 322 if (v != X_MBOWNER_PL) { 323 t4_report_fw_error(adap); 324 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 325 return ret; 326 } 327 328 /* 329 * If we gain ownership of the mailbox and there's a "valid" message 330 * in it, this is likely an asynchronous error message from the 331 * firmware. So we'll report that and then proceed on with attempting 332 * to issue our own command ... which may well fail if the error 333 * presaged the firmware crashing ... 334 */ 335 if (ctl & F_MBMSGVALID) { 336 CH_ERR(adap, "found VALID command in mbox %u: " 337 "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox, 338 (unsigned long long)t4_read_reg64(adap, data_reg), 339 (unsigned long long)t4_read_reg64(adap, data_reg + 8), 340 (unsigned long long)t4_read_reg64(adap, data_reg + 16), 341 (unsigned long long)t4_read_reg64(adap, data_reg + 24), 342 (unsigned long long)t4_read_reg64(adap, data_reg + 32), 343 (unsigned long long)t4_read_reg64(adap, data_reg + 40), 344 (unsigned long long)t4_read_reg64(adap, data_reg + 48), 345 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); 346 } 347 348 /* 349 * Copy in the new mailbox command and send it on its way ... 350 */ 351 for (i = 0; i < size; i += 8, p++) 352 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); 353 354 if (adap->flags & IS_VF) { 355 /* 356 * For the VFs, the Mailbox Data "registers" are 357 * actually backed by T4's "MA" interface rather than 358 * PL Registers (as is the case for the PFs). Because 359 * these are in different coherency domains, the write 360 * to the VF's PL-register-backed Mailbox Control can 361 * race in front of the writes to the MA-backed VF 362 * Mailbox Data "registers". So we need to do a 363 * read-back on at least one byte of the VF Mailbox 364 * Data registers before doing the write to the VF 365 * Mailbox Control register. 366 */ 367 t4_read_reg(adap, data_reg); 368 } 369 370 CH_DUMP_MBOX(adap, mbox, data_reg); 371 372 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 373 t4_read_reg(adap, ctl_reg); /* flush write */ 374 375 delay_idx = 0; 376 ms = delay[0]; 377 378 /* 379 * Loop waiting for the reply; bail out if we time out or the firmware 380 * reports an error. 381 */ 382 pcie_fw = 0; 383 for (i = 0; i < timeout; i += ms) { 384 if (!(adap->flags & IS_VF)) { 385 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 386 if (pcie_fw & F_PCIE_FW_ERR) 387 break; 388 } 389 if (sleep_ok) { 390 ms = delay[delay_idx]; /* last element may repeat */ 391 if (delay_idx < ARRAY_SIZE(delay) - 1) 392 delay_idx++; 393 msleep(ms); 394 } else { 395 mdelay(ms); 396 } 397 398 v = t4_read_reg(adap, ctl_reg); 399 if (v == X_CIM_PF_NOACCESS) 400 continue; 401 if (G_MBOWNER(v) == X_MBOWNER_PL) { 402 if (!(v & F_MBMSGVALID)) { 403 t4_write_reg(adap, ctl_reg, 404 V_MBOWNER(X_MBOWNER_NONE)); 405 continue; 406 } 407 408 /* 409 * Retrieve the command reply and release the mailbox. 410 */ 411 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 412 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 413 414 CH_DUMP_MBOX(adap, mbox, data_reg); 415 416 res = be64_to_cpu(cmd_rpl[0]); 417 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 418 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 419 res = V_FW_CMD_RETVAL(EIO); 420 } else if (rpl) 421 memcpy(rpl, cmd_rpl, size); 422 return -G_FW_CMD_RETVAL((int)res); 423 } 424 } 425 426 /* 427 * We timed out waiting for a reply to our mailbox command. Report 428 * the error and also check to see if the firmware reported any 429 * errors ... 430 */ 431 ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; 432 CH_ERR(adap, "command %#x in mailbox %d timed out\n", 433 *(const u8 *)cmd, mbox); 434 435 /* If DUMP_MBOX is set the mbox has already been dumped */ 436 if ((adap->debug_flags & DF_DUMP_MBOX) == 0) { 437 p = cmd; 438 CH_ERR(adap, "mbox: %016llx %016llx %016llx %016llx " 439 "%016llx %016llx %016llx %016llx\n", 440 (unsigned long long)be64_to_cpu(p[0]), 441 (unsigned long long)be64_to_cpu(p[1]), 442 (unsigned long long)be64_to_cpu(p[2]), 443 (unsigned long long)be64_to_cpu(p[3]), 444 (unsigned long long)be64_to_cpu(p[4]), 445 (unsigned long long)be64_to_cpu(p[5]), 446 (unsigned long long)be64_to_cpu(p[6]), 447 (unsigned long long)be64_to_cpu(p[7])); 448 } 449 450 t4_report_fw_error(adap); 451 t4_fatal_err(adap); 452 return ret; 453 } 454 455 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 456 void *rpl, bool sleep_ok) 457 { 458 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 459 sleep_ok, FW_CMD_MAX_TIMEOUT); 460 461 } 462 463 static int t4_edc_err_read(struct adapter *adap, int idx) 464 { 465 u32 edc_ecc_err_addr_reg; 466 u32 edc_bist_status_rdata_reg; 467 468 if (is_t4(adap)) { 469 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 470 return 0; 471 } 472 if (idx != 0 && idx != 1) { 473 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 474 return 0; 475 } 476 477 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 478 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 479 480 CH_WARN(adap, 481 "edc%d err addr 0x%x: 0x%x.\n", 482 idx, edc_ecc_err_addr_reg, 483 t4_read_reg(adap, edc_ecc_err_addr_reg)); 484 CH_WARN(adap, 485 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 486 edc_bist_status_rdata_reg, 487 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 488 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 489 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 490 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 491 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 492 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 493 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 494 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 495 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 496 497 return 0; 498 } 499 500 /** 501 * t4_mc_read - read from MC through backdoor accesses 502 * @adap: the adapter 503 * @idx: which MC to access 504 * @addr: address of first byte requested 505 * @data: 64 bytes of data containing the requested address 506 * @ecc: where to store the corresponding 64-bit ECC word 507 * 508 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 509 * that covers the requested address @addr. If @parity is not %NULL it 510 * is assigned the 64-bit ECC word for the read data. 511 */ 512 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 513 { 514 int i; 515 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 516 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 517 518 if (is_t4(adap)) { 519 mc_bist_cmd_reg = A_MC_BIST_CMD; 520 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 521 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 522 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 523 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 524 } else { 525 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 526 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 527 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 528 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 529 idx); 530 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 531 idx); 532 } 533 534 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 535 return -EBUSY; 536 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 537 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 538 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 539 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 540 F_START_BIST | V_BIST_CMD_GAP(1)); 541 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 542 if (i) 543 return i; 544 545 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 546 547 for (i = 15; i >= 0; i--) 548 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 549 if (ecc) 550 *ecc = t4_read_reg64(adap, MC_DATA(16)); 551 #undef MC_DATA 552 return 0; 553 } 554 555 /** 556 * t4_edc_read - read from EDC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which EDC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568 { 569 int i; 570 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 571 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 572 573 if (is_t4(adap)) { 574 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 575 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 576 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 577 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 578 idx); 579 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 580 idx); 581 } else { 582 /* 583 * These macro are missing in t4_regs.h file. 584 * Added temporarily for testing. 585 */ 586 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 587 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 588 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 589 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 590 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 591 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 592 idx); 593 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 594 idx); 595 #undef EDC_REG_T5 596 #undef EDC_STRIDE_T5 597 } 598 599 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 600 return -EBUSY; 601 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 602 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 603 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 604 t4_write_reg(adap, edc_bist_cmd_reg, 605 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 606 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 607 if (i) 608 return i; 609 610 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 611 612 for (i = 15; i >= 0; i--) 613 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 614 if (ecc) 615 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 616 #undef EDC_DATA 617 return 0; 618 } 619 620 /** 621 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 622 * @adap: the adapter 623 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 624 * @addr: address within indicated memory type 625 * @len: amount of memory to read 626 * @buf: host memory buffer 627 * 628 * Reads an [almost] arbitrary memory region in the firmware: the 629 * firmware memory address, length and host buffer must be aligned on 630 * 32-bit boudaries. The memory is returned as a raw byte sequence from 631 * the firmware's memory. If this memory contains data structures which 632 * contain multi-byte integers, it's the callers responsibility to 633 * perform appropriate byte order conversions. 634 */ 635 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 636 __be32 *buf) 637 { 638 u32 pos, start, end, offset; 639 int ret; 640 641 /* 642 * Argument sanity checks ... 643 */ 644 if ((addr & 0x3) || (len & 0x3)) 645 return -EINVAL; 646 647 /* 648 * The underlaying EDC/MC read routines read 64 bytes at a time so we 649 * need to round down the start and round up the end. We'll start 650 * copying out of the first line at (addr - start) a word at a time. 651 */ 652 start = rounddown2(addr, 64); 653 end = roundup2(addr + len, 64); 654 offset = (addr - start)/sizeof(__be32); 655 656 for (pos = start; pos < end; pos += 64, offset = 0) { 657 __be32 data[16]; 658 659 /* 660 * Read the chip's memory block and bail if there's an error. 661 */ 662 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 663 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 664 else 665 ret = t4_edc_read(adap, mtype, pos, data, NULL); 666 if (ret) 667 return ret; 668 669 /* 670 * Copy the data into the caller's memory buffer. 671 */ 672 while (offset < 16 && len > 0) { 673 *buf++ = data[offset++]; 674 len -= sizeof(__be32); 675 } 676 } 677 678 return 0; 679 } 680 681 /* 682 * Return the specified PCI-E Configuration Space register from our Physical 683 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 684 * since we prefer to let the firmware own all of these registers, but if that 685 * fails we go for it directly ourselves. 686 */ 687 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 688 { 689 690 /* 691 * If fw_attach != 0, construct and send the Firmware LDST Command to 692 * retrieve the specified PCI-E Configuration Space register. 693 */ 694 if (drv_fw_attach != 0) { 695 struct fw_ldst_cmd ldst_cmd; 696 int ret; 697 698 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 699 ldst_cmd.op_to_addrspace = 700 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 701 F_FW_CMD_REQUEST | 702 F_FW_CMD_READ | 703 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 704 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 705 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 706 ldst_cmd.u.pcie.ctrl_to_fn = 707 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 708 ldst_cmd.u.pcie.r = reg; 709 710 /* 711 * If the LDST Command succeeds, return the result, otherwise 712 * fall through to reading it directly ourselves ... 713 */ 714 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 715 &ldst_cmd); 716 if (ret == 0) 717 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 718 719 CH_WARN(adap, "Firmware failed to return " 720 "Configuration Space register %d, err = %d\n", 721 reg, -ret); 722 } 723 724 /* 725 * Read the desired Configuration Space register via the PCI-E 726 * Backdoor mechanism. 727 */ 728 return t4_hw_pci_read_cfg4(adap, reg); 729 } 730 731 /** 732 * t4_get_regs_len - return the size of the chips register set 733 * @adapter: the adapter 734 * 735 * Returns the size of the chip's BAR0 register space. 736 */ 737 unsigned int t4_get_regs_len(struct adapter *adapter) 738 { 739 unsigned int chip_version = chip_id(adapter); 740 741 switch (chip_version) { 742 case CHELSIO_T4: 743 if (adapter->flags & IS_VF) 744 return FW_T4VF_REGMAP_SIZE; 745 return T4_REGMAP_SIZE; 746 747 case CHELSIO_T5: 748 case CHELSIO_T6: 749 if (adapter->flags & IS_VF) 750 return FW_T4VF_REGMAP_SIZE; 751 return T5_REGMAP_SIZE; 752 } 753 754 CH_ERR(adapter, 755 "Unsupported chip version %d\n", chip_version); 756 return 0; 757 } 758 759 /** 760 * t4_get_regs - read chip registers into provided buffer 761 * @adap: the adapter 762 * @buf: register buffer 763 * @buf_size: size (in bytes) of register buffer 764 * 765 * If the provided register buffer isn't large enough for the chip's 766 * full register range, the register dump will be truncated to the 767 * register buffer's size. 768 */ 769 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 770 { 771 static const unsigned int t4_reg_ranges[] = { 772 0x1008, 0x1108, 773 0x1180, 0x1184, 774 0x1190, 0x1194, 775 0x11a0, 0x11a4, 776 0x11b0, 0x11b4, 777 0x11fc, 0x123c, 778 0x1300, 0x173c, 779 0x1800, 0x18fc, 780 0x3000, 0x30d8, 781 0x30e0, 0x30e4, 782 0x30ec, 0x5910, 783 0x5920, 0x5924, 784 0x5960, 0x5960, 785 0x5968, 0x5968, 786 0x5970, 0x5970, 787 0x5978, 0x5978, 788 0x5980, 0x5980, 789 0x5988, 0x5988, 790 0x5990, 0x5990, 791 0x5998, 0x5998, 792 0x59a0, 0x59d4, 793 0x5a00, 0x5ae0, 794 0x5ae8, 0x5ae8, 795 0x5af0, 0x5af0, 796 0x5af8, 0x5af8, 797 0x6000, 0x6098, 798 0x6100, 0x6150, 799 0x6200, 0x6208, 800 0x6240, 0x6248, 801 0x6280, 0x62b0, 802 0x62c0, 0x6338, 803 0x6370, 0x638c, 804 0x6400, 0x643c, 805 0x6500, 0x6524, 806 0x6a00, 0x6a04, 807 0x6a14, 0x6a38, 808 0x6a60, 0x6a70, 809 0x6a78, 0x6a78, 810 0x6b00, 0x6b0c, 811 0x6b1c, 0x6b84, 812 0x6bf0, 0x6bf8, 813 0x6c00, 0x6c0c, 814 0x6c1c, 0x6c84, 815 0x6cf0, 0x6cf8, 816 0x6d00, 0x6d0c, 817 0x6d1c, 0x6d84, 818 0x6df0, 0x6df8, 819 0x6e00, 0x6e0c, 820 0x6e1c, 0x6e84, 821 0x6ef0, 0x6ef8, 822 0x6f00, 0x6f0c, 823 0x6f1c, 0x6f84, 824 0x6ff0, 0x6ff8, 825 0x7000, 0x700c, 826 0x701c, 0x7084, 827 0x70f0, 0x70f8, 828 0x7100, 0x710c, 829 0x711c, 0x7184, 830 0x71f0, 0x71f8, 831 0x7200, 0x720c, 832 0x721c, 0x7284, 833 0x72f0, 0x72f8, 834 0x7300, 0x730c, 835 0x731c, 0x7384, 836 0x73f0, 0x73f8, 837 0x7400, 0x7450, 838 0x7500, 0x7530, 839 0x7600, 0x760c, 840 0x7614, 0x761c, 841 0x7680, 0x76cc, 842 0x7700, 0x7798, 843 0x77c0, 0x77fc, 844 0x7900, 0x79fc, 845 0x7b00, 0x7b58, 846 0x7b60, 0x7b84, 847 0x7b8c, 0x7c38, 848 0x7d00, 0x7d38, 849 0x7d40, 0x7d80, 850 0x7d8c, 0x7ddc, 851 0x7de4, 0x7e04, 852 0x7e10, 0x7e1c, 853 0x7e24, 0x7e38, 854 0x7e40, 0x7e44, 855 0x7e4c, 0x7e78, 856 0x7e80, 0x7ea4, 857 0x7eac, 0x7edc, 858 0x7ee8, 0x7efc, 859 0x8dc0, 0x8e04, 860 0x8e10, 0x8e1c, 861 0x8e30, 0x8e78, 862 0x8ea0, 0x8eb8, 863 0x8ec0, 0x8f6c, 864 0x8fc0, 0x9008, 865 0x9010, 0x9058, 866 0x9060, 0x9060, 867 0x9068, 0x9074, 868 0x90fc, 0x90fc, 869 0x9400, 0x9408, 870 0x9410, 0x9458, 871 0x9600, 0x9600, 872 0x9608, 0x9638, 873 0x9640, 0x96bc, 874 0x9800, 0x9808, 875 0x9820, 0x983c, 876 0x9850, 0x9864, 877 0x9c00, 0x9c6c, 878 0x9c80, 0x9cec, 879 0x9d00, 0x9d6c, 880 0x9d80, 0x9dec, 881 0x9e00, 0x9e6c, 882 0x9e80, 0x9eec, 883 0x9f00, 0x9f6c, 884 0x9f80, 0x9fec, 885 0xd004, 0xd004, 886 0xd010, 0xd03c, 887 0xdfc0, 0xdfe0, 888 0xe000, 0xea7c, 889 0xf000, 0x11190, 890 0x19040, 0x1906c, 891 0x19078, 0x19080, 892 0x1908c, 0x190e4, 893 0x190f0, 0x190f8, 894 0x19100, 0x19110, 895 0x19120, 0x19124, 896 0x19150, 0x19194, 897 0x1919c, 0x191b0, 898 0x191d0, 0x191e8, 899 0x19238, 0x1924c, 900 0x193f8, 0x1943c, 901 0x1944c, 0x19474, 902 0x19490, 0x194e0, 903 0x194f0, 0x194f8, 904 0x19800, 0x19c08, 905 0x19c10, 0x19c90, 906 0x19ca0, 0x19ce4, 907 0x19cf0, 0x19d40, 908 0x19d50, 0x19d94, 909 0x19da0, 0x19de8, 910 0x19df0, 0x19e40, 911 0x19e50, 0x19e90, 912 0x19ea0, 0x19f4c, 913 0x1a000, 0x1a004, 914 0x1a010, 0x1a06c, 915 0x1a0b0, 0x1a0e4, 916 0x1a0ec, 0x1a0f4, 917 0x1a100, 0x1a108, 918 0x1a114, 0x1a120, 919 0x1a128, 0x1a130, 920 0x1a138, 0x1a138, 921 0x1a190, 0x1a1c4, 922 0x1a1fc, 0x1a1fc, 923 0x1e040, 0x1e04c, 924 0x1e284, 0x1e28c, 925 0x1e2c0, 0x1e2c0, 926 0x1e2e0, 0x1e2e0, 927 0x1e300, 0x1e384, 928 0x1e3c0, 0x1e3c8, 929 0x1e440, 0x1e44c, 930 0x1e684, 0x1e68c, 931 0x1e6c0, 0x1e6c0, 932 0x1e6e0, 0x1e6e0, 933 0x1e700, 0x1e784, 934 0x1e7c0, 0x1e7c8, 935 0x1e840, 0x1e84c, 936 0x1ea84, 0x1ea8c, 937 0x1eac0, 0x1eac0, 938 0x1eae0, 0x1eae0, 939 0x1eb00, 0x1eb84, 940 0x1ebc0, 0x1ebc8, 941 0x1ec40, 0x1ec4c, 942 0x1ee84, 0x1ee8c, 943 0x1eec0, 0x1eec0, 944 0x1eee0, 0x1eee0, 945 0x1ef00, 0x1ef84, 946 0x1efc0, 0x1efc8, 947 0x1f040, 0x1f04c, 948 0x1f284, 0x1f28c, 949 0x1f2c0, 0x1f2c0, 950 0x1f2e0, 0x1f2e0, 951 0x1f300, 0x1f384, 952 0x1f3c0, 0x1f3c8, 953 0x1f440, 0x1f44c, 954 0x1f684, 0x1f68c, 955 0x1f6c0, 0x1f6c0, 956 0x1f6e0, 0x1f6e0, 957 0x1f700, 0x1f784, 958 0x1f7c0, 0x1f7c8, 959 0x1f840, 0x1f84c, 960 0x1fa84, 0x1fa8c, 961 0x1fac0, 0x1fac0, 962 0x1fae0, 0x1fae0, 963 0x1fb00, 0x1fb84, 964 0x1fbc0, 0x1fbc8, 965 0x1fc40, 0x1fc4c, 966 0x1fe84, 0x1fe8c, 967 0x1fec0, 0x1fec0, 968 0x1fee0, 0x1fee0, 969 0x1ff00, 0x1ff84, 970 0x1ffc0, 0x1ffc8, 971 0x20000, 0x2002c, 972 0x20100, 0x2013c, 973 0x20190, 0x201a0, 974 0x201a8, 0x201b8, 975 0x201c4, 0x201c8, 976 0x20200, 0x20318, 977 0x20400, 0x204b4, 978 0x204c0, 0x20528, 979 0x20540, 0x20614, 980 0x21000, 0x21040, 981 0x2104c, 0x21060, 982 0x210c0, 0x210ec, 983 0x21200, 0x21268, 984 0x21270, 0x21284, 985 0x212fc, 0x21388, 986 0x21400, 0x21404, 987 0x21500, 0x21500, 988 0x21510, 0x21518, 989 0x2152c, 0x21530, 990 0x2153c, 0x2153c, 991 0x21550, 0x21554, 992 0x21600, 0x21600, 993 0x21608, 0x2161c, 994 0x21624, 0x21628, 995 0x21630, 0x21634, 996 0x2163c, 0x2163c, 997 0x21700, 0x2171c, 998 0x21780, 0x2178c, 999 0x21800, 0x21818, 1000 0x21820, 0x21828, 1001 0x21830, 0x21848, 1002 0x21850, 0x21854, 1003 0x21860, 0x21868, 1004 0x21870, 0x21870, 1005 0x21878, 0x21898, 1006 0x218a0, 0x218a8, 1007 0x218b0, 0x218c8, 1008 0x218d0, 0x218d4, 1009 0x218e0, 0x218e8, 1010 0x218f0, 0x218f0, 1011 0x218f8, 0x21a18, 1012 0x21a20, 0x21a28, 1013 0x21a30, 0x21a48, 1014 0x21a50, 0x21a54, 1015 0x21a60, 0x21a68, 1016 0x21a70, 0x21a70, 1017 0x21a78, 0x21a98, 1018 0x21aa0, 0x21aa8, 1019 0x21ab0, 0x21ac8, 1020 0x21ad0, 0x21ad4, 1021 0x21ae0, 0x21ae8, 1022 0x21af0, 0x21af0, 1023 0x21af8, 0x21c18, 1024 0x21c20, 0x21c20, 1025 0x21c28, 0x21c30, 1026 0x21c38, 0x21c38, 1027 0x21c80, 0x21c98, 1028 0x21ca0, 0x21ca8, 1029 0x21cb0, 0x21cc8, 1030 0x21cd0, 0x21cd4, 1031 0x21ce0, 0x21ce8, 1032 0x21cf0, 0x21cf0, 1033 0x21cf8, 0x21d7c, 1034 0x21e00, 0x21e04, 1035 0x22000, 0x2202c, 1036 0x22100, 0x2213c, 1037 0x22190, 0x221a0, 1038 0x221a8, 0x221b8, 1039 0x221c4, 0x221c8, 1040 0x22200, 0x22318, 1041 0x22400, 0x224b4, 1042 0x224c0, 0x22528, 1043 0x22540, 0x22614, 1044 0x23000, 0x23040, 1045 0x2304c, 0x23060, 1046 0x230c0, 0x230ec, 1047 0x23200, 0x23268, 1048 0x23270, 0x23284, 1049 0x232fc, 0x23388, 1050 0x23400, 0x23404, 1051 0x23500, 0x23500, 1052 0x23510, 0x23518, 1053 0x2352c, 0x23530, 1054 0x2353c, 0x2353c, 1055 0x23550, 0x23554, 1056 0x23600, 0x23600, 1057 0x23608, 0x2361c, 1058 0x23624, 0x23628, 1059 0x23630, 0x23634, 1060 0x2363c, 0x2363c, 1061 0x23700, 0x2371c, 1062 0x23780, 0x2378c, 1063 0x23800, 0x23818, 1064 0x23820, 0x23828, 1065 0x23830, 0x23848, 1066 0x23850, 0x23854, 1067 0x23860, 0x23868, 1068 0x23870, 0x23870, 1069 0x23878, 0x23898, 1070 0x238a0, 0x238a8, 1071 0x238b0, 0x238c8, 1072 0x238d0, 0x238d4, 1073 0x238e0, 0x238e8, 1074 0x238f0, 0x238f0, 1075 0x238f8, 0x23a18, 1076 0x23a20, 0x23a28, 1077 0x23a30, 0x23a48, 1078 0x23a50, 0x23a54, 1079 0x23a60, 0x23a68, 1080 0x23a70, 0x23a70, 1081 0x23a78, 0x23a98, 1082 0x23aa0, 0x23aa8, 1083 0x23ab0, 0x23ac8, 1084 0x23ad0, 0x23ad4, 1085 0x23ae0, 0x23ae8, 1086 0x23af0, 0x23af0, 1087 0x23af8, 0x23c18, 1088 0x23c20, 0x23c20, 1089 0x23c28, 0x23c30, 1090 0x23c38, 0x23c38, 1091 0x23c80, 0x23c98, 1092 0x23ca0, 0x23ca8, 1093 0x23cb0, 0x23cc8, 1094 0x23cd0, 0x23cd4, 1095 0x23ce0, 0x23ce8, 1096 0x23cf0, 0x23cf0, 1097 0x23cf8, 0x23d7c, 1098 0x23e00, 0x23e04, 1099 0x24000, 0x2402c, 1100 0x24100, 0x2413c, 1101 0x24190, 0x241a0, 1102 0x241a8, 0x241b8, 1103 0x241c4, 0x241c8, 1104 0x24200, 0x24318, 1105 0x24400, 0x244b4, 1106 0x244c0, 0x24528, 1107 0x24540, 0x24614, 1108 0x25000, 0x25040, 1109 0x2504c, 0x25060, 1110 0x250c0, 0x250ec, 1111 0x25200, 0x25268, 1112 0x25270, 0x25284, 1113 0x252fc, 0x25388, 1114 0x25400, 0x25404, 1115 0x25500, 0x25500, 1116 0x25510, 0x25518, 1117 0x2552c, 0x25530, 1118 0x2553c, 0x2553c, 1119 0x25550, 0x25554, 1120 0x25600, 0x25600, 1121 0x25608, 0x2561c, 1122 0x25624, 0x25628, 1123 0x25630, 0x25634, 1124 0x2563c, 0x2563c, 1125 0x25700, 0x2571c, 1126 0x25780, 0x2578c, 1127 0x25800, 0x25818, 1128 0x25820, 0x25828, 1129 0x25830, 0x25848, 1130 0x25850, 0x25854, 1131 0x25860, 0x25868, 1132 0x25870, 0x25870, 1133 0x25878, 0x25898, 1134 0x258a0, 0x258a8, 1135 0x258b0, 0x258c8, 1136 0x258d0, 0x258d4, 1137 0x258e0, 0x258e8, 1138 0x258f0, 0x258f0, 1139 0x258f8, 0x25a18, 1140 0x25a20, 0x25a28, 1141 0x25a30, 0x25a48, 1142 0x25a50, 0x25a54, 1143 0x25a60, 0x25a68, 1144 0x25a70, 0x25a70, 1145 0x25a78, 0x25a98, 1146 0x25aa0, 0x25aa8, 1147 0x25ab0, 0x25ac8, 1148 0x25ad0, 0x25ad4, 1149 0x25ae0, 0x25ae8, 1150 0x25af0, 0x25af0, 1151 0x25af8, 0x25c18, 1152 0x25c20, 0x25c20, 1153 0x25c28, 0x25c30, 1154 0x25c38, 0x25c38, 1155 0x25c80, 0x25c98, 1156 0x25ca0, 0x25ca8, 1157 0x25cb0, 0x25cc8, 1158 0x25cd0, 0x25cd4, 1159 0x25ce0, 0x25ce8, 1160 0x25cf0, 0x25cf0, 1161 0x25cf8, 0x25d7c, 1162 0x25e00, 0x25e04, 1163 0x26000, 0x2602c, 1164 0x26100, 0x2613c, 1165 0x26190, 0x261a0, 1166 0x261a8, 0x261b8, 1167 0x261c4, 0x261c8, 1168 0x26200, 0x26318, 1169 0x26400, 0x264b4, 1170 0x264c0, 0x26528, 1171 0x26540, 0x26614, 1172 0x27000, 0x27040, 1173 0x2704c, 0x27060, 1174 0x270c0, 0x270ec, 1175 0x27200, 0x27268, 1176 0x27270, 0x27284, 1177 0x272fc, 0x27388, 1178 0x27400, 0x27404, 1179 0x27500, 0x27500, 1180 0x27510, 0x27518, 1181 0x2752c, 0x27530, 1182 0x2753c, 0x2753c, 1183 0x27550, 0x27554, 1184 0x27600, 0x27600, 1185 0x27608, 0x2761c, 1186 0x27624, 0x27628, 1187 0x27630, 0x27634, 1188 0x2763c, 0x2763c, 1189 0x27700, 0x2771c, 1190 0x27780, 0x2778c, 1191 0x27800, 0x27818, 1192 0x27820, 0x27828, 1193 0x27830, 0x27848, 1194 0x27850, 0x27854, 1195 0x27860, 0x27868, 1196 0x27870, 0x27870, 1197 0x27878, 0x27898, 1198 0x278a0, 0x278a8, 1199 0x278b0, 0x278c8, 1200 0x278d0, 0x278d4, 1201 0x278e0, 0x278e8, 1202 0x278f0, 0x278f0, 1203 0x278f8, 0x27a18, 1204 0x27a20, 0x27a28, 1205 0x27a30, 0x27a48, 1206 0x27a50, 0x27a54, 1207 0x27a60, 0x27a68, 1208 0x27a70, 0x27a70, 1209 0x27a78, 0x27a98, 1210 0x27aa0, 0x27aa8, 1211 0x27ab0, 0x27ac8, 1212 0x27ad0, 0x27ad4, 1213 0x27ae0, 0x27ae8, 1214 0x27af0, 0x27af0, 1215 0x27af8, 0x27c18, 1216 0x27c20, 0x27c20, 1217 0x27c28, 0x27c30, 1218 0x27c38, 0x27c38, 1219 0x27c80, 0x27c98, 1220 0x27ca0, 0x27ca8, 1221 0x27cb0, 0x27cc8, 1222 0x27cd0, 0x27cd4, 1223 0x27ce0, 0x27ce8, 1224 0x27cf0, 0x27cf0, 1225 0x27cf8, 0x27d7c, 1226 0x27e00, 0x27e04, 1227 }; 1228 1229 static const unsigned int t4vf_reg_ranges[] = { 1230 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1231 VF_MPS_REG(A_MPS_VF_CTL), 1232 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1233 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1234 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1235 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1236 FW_T4VF_MBDATA_BASE_ADDR, 1237 FW_T4VF_MBDATA_BASE_ADDR + 1238 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1239 }; 1240 1241 static const unsigned int t5_reg_ranges[] = { 1242 0x1008, 0x10c0, 1243 0x10cc, 0x10f8, 1244 0x1100, 0x1100, 1245 0x110c, 0x1148, 1246 0x1180, 0x1184, 1247 0x1190, 0x1194, 1248 0x11a0, 0x11a4, 1249 0x11b0, 0x11b4, 1250 0x11fc, 0x123c, 1251 0x1280, 0x173c, 1252 0x1800, 0x18fc, 1253 0x3000, 0x3028, 1254 0x3060, 0x30b0, 1255 0x30b8, 0x30d8, 1256 0x30e0, 0x30fc, 1257 0x3140, 0x357c, 1258 0x35a8, 0x35cc, 1259 0x35ec, 0x35ec, 1260 0x3600, 0x5624, 1261 0x56cc, 0x56ec, 1262 0x56f4, 0x5720, 1263 0x5728, 0x575c, 1264 0x580c, 0x5814, 1265 0x5890, 0x589c, 1266 0x58a4, 0x58ac, 1267 0x58b8, 0x58bc, 1268 0x5940, 0x59c8, 1269 0x59d0, 0x59dc, 1270 0x59fc, 0x5a18, 1271 0x5a60, 0x5a70, 1272 0x5a80, 0x5a9c, 1273 0x5b94, 0x5bfc, 1274 0x6000, 0x6020, 1275 0x6028, 0x6040, 1276 0x6058, 0x609c, 1277 0x60a8, 0x614c, 1278 0x7700, 0x7798, 1279 0x77c0, 0x78fc, 1280 0x7b00, 0x7b58, 1281 0x7b60, 0x7b84, 1282 0x7b8c, 0x7c54, 1283 0x7d00, 0x7d38, 1284 0x7d40, 0x7d80, 1285 0x7d8c, 0x7ddc, 1286 0x7de4, 0x7e04, 1287 0x7e10, 0x7e1c, 1288 0x7e24, 0x7e38, 1289 0x7e40, 0x7e44, 1290 0x7e4c, 0x7e78, 1291 0x7e80, 0x7edc, 1292 0x7ee8, 0x7efc, 1293 0x8dc0, 0x8de0, 1294 0x8df8, 0x8e04, 1295 0x8e10, 0x8e84, 1296 0x8ea0, 0x8f84, 1297 0x8fc0, 0x9058, 1298 0x9060, 0x9060, 1299 0x9068, 0x90f8, 1300 0x9400, 0x9408, 1301 0x9410, 0x9470, 1302 0x9600, 0x9600, 1303 0x9608, 0x9638, 1304 0x9640, 0x96f4, 1305 0x9800, 0x9808, 1306 0x9820, 0x983c, 1307 0x9850, 0x9864, 1308 0x9c00, 0x9c6c, 1309 0x9c80, 0x9cec, 1310 0x9d00, 0x9d6c, 1311 0x9d80, 0x9dec, 1312 0x9e00, 0x9e6c, 1313 0x9e80, 0x9eec, 1314 0x9f00, 0x9f6c, 1315 0x9f80, 0xa020, 1316 0xd004, 0xd004, 1317 0xd010, 0xd03c, 1318 0xdfc0, 0xdfe0, 1319 0xe000, 0x1106c, 1320 0x11074, 0x11088, 1321 0x1109c, 0x1117c, 1322 0x11190, 0x11204, 1323 0x19040, 0x1906c, 1324 0x19078, 0x19080, 1325 0x1908c, 0x190e8, 1326 0x190f0, 0x190f8, 1327 0x19100, 0x19110, 1328 0x19120, 0x19124, 1329 0x19150, 0x19194, 1330 0x1919c, 0x191b0, 1331 0x191d0, 0x191e8, 1332 0x19238, 0x19290, 1333 0x193f8, 0x19428, 1334 0x19430, 0x19444, 1335 0x1944c, 0x1946c, 1336 0x19474, 0x19474, 1337 0x19490, 0x194cc, 1338 0x194f0, 0x194f8, 1339 0x19c00, 0x19c08, 1340 0x19c10, 0x19c60, 1341 0x19c94, 0x19ce4, 1342 0x19cf0, 0x19d40, 1343 0x19d50, 0x19d94, 1344 0x19da0, 0x19de8, 1345 0x19df0, 0x19e10, 1346 0x19e50, 0x19e90, 1347 0x19ea0, 0x19f24, 1348 0x19f34, 0x19f34, 1349 0x19f40, 0x19f50, 1350 0x19f90, 0x19fb4, 1351 0x19fc4, 0x19fe4, 1352 0x1a000, 0x1a004, 1353 0x1a010, 0x1a06c, 1354 0x1a0b0, 0x1a0e4, 1355 0x1a0ec, 0x1a0f8, 1356 0x1a100, 0x1a108, 1357 0x1a114, 0x1a120, 1358 0x1a128, 0x1a130, 1359 0x1a138, 0x1a138, 1360 0x1a190, 0x1a1c4, 1361 0x1a1fc, 0x1a1fc, 1362 0x1e008, 0x1e00c, 1363 0x1e040, 0x1e044, 1364 0x1e04c, 0x1e04c, 1365 0x1e284, 0x1e290, 1366 0x1e2c0, 0x1e2c0, 1367 0x1e2e0, 0x1e2e0, 1368 0x1e300, 0x1e384, 1369 0x1e3c0, 0x1e3c8, 1370 0x1e408, 0x1e40c, 1371 0x1e440, 0x1e444, 1372 0x1e44c, 0x1e44c, 1373 0x1e684, 0x1e690, 1374 0x1e6c0, 0x1e6c0, 1375 0x1e6e0, 0x1e6e0, 1376 0x1e700, 0x1e784, 1377 0x1e7c0, 0x1e7c8, 1378 0x1e808, 0x1e80c, 1379 0x1e840, 0x1e844, 1380 0x1e84c, 0x1e84c, 1381 0x1ea84, 0x1ea90, 1382 0x1eac0, 0x1eac0, 1383 0x1eae0, 0x1eae0, 1384 0x1eb00, 0x1eb84, 1385 0x1ebc0, 0x1ebc8, 1386 0x1ec08, 0x1ec0c, 1387 0x1ec40, 0x1ec44, 1388 0x1ec4c, 0x1ec4c, 1389 0x1ee84, 0x1ee90, 1390 0x1eec0, 0x1eec0, 1391 0x1eee0, 0x1eee0, 1392 0x1ef00, 0x1ef84, 1393 0x1efc0, 0x1efc8, 1394 0x1f008, 0x1f00c, 1395 0x1f040, 0x1f044, 1396 0x1f04c, 0x1f04c, 1397 0x1f284, 0x1f290, 1398 0x1f2c0, 0x1f2c0, 1399 0x1f2e0, 0x1f2e0, 1400 0x1f300, 0x1f384, 1401 0x1f3c0, 0x1f3c8, 1402 0x1f408, 0x1f40c, 1403 0x1f440, 0x1f444, 1404 0x1f44c, 0x1f44c, 1405 0x1f684, 0x1f690, 1406 0x1f6c0, 0x1f6c0, 1407 0x1f6e0, 0x1f6e0, 1408 0x1f700, 0x1f784, 1409 0x1f7c0, 0x1f7c8, 1410 0x1f808, 0x1f80c, 1411 0x1f840, 0x1f844, 1412 0x1f84c, 0x1f84c, 1413 0x1fa84, 0x1fa90, 1414 0x1fac0, 0x1fac0, 1415 0x1fae0, 0x1fae0, 1416 0x1fb00, 0x1fb84, 1417 0x1fbc0, 0x1fbc8, 1418 0x1fc08, 0x1fc0c, 1419 0x1fc40, 0x1fc44, 1420 0x1fc4c, 0x1fc4c, 1421 0x1fe84, 0x1fe90, 1422 0x1fec0, 0x1fec0, 1423 0x1fee0, 0x1fee0, 1424 0x1ff00, 0x1ff84, 1425 0x1ffc0, 0x1ffc8, 1426 0x30000, 0x30030, 1427 0x30038, 0x30038, 1428 0x30040, 0x30040, 1429 0x30100, 0x30144, 1430 0x30190, 0x301a0, 1431 0x301a8, 0x301b8, 1432 0x301c4, 0x301c8, 1433 0x301d0, 0x301d0, 1434 0x30200, 0x30318, 1435 0x30400, 0x304b4, 1436 0x304c0, 0x3052c, 1437 0x30540, 0x3061c, 1438 0x30800, 0x30828, 1439 0x30834, 0x30834, 1440 0x308c0, 0x30908, 1441 0x30910, 0x309ac, 1442 0x30a00, 0x30a14, 1443 0x30a1c, 0x30a2c, 1444 0x30a44, 0x30a50, 1445 0x30a74, 0x30a74, 1446 0x30a7c, 0x30afc, 1447 0x30b08, 0x30c24, 1448 0x30d00, 0x30d00, 1449 0x30d08, 0x30d14, 1450 0x30d1c, 0x30d20, 1451 0x30d3c, 0x30d3c, 1452 0x30d48, 0x30d50, 1453 0x31200, 0x3120c, 1454 0x31220, 0x31220, 1455 0x31240, 0x31240, 1456 0x31600, 0x3160c, 1457 0x31a00, 0x31a1c, 1458 0x31e00, 0x31e20, 1459 0x31e38, 0x31e3c, 1460 0x31e80, 0x31e80, 1461 0x31e88, 0x31ea8, 1462 0x31eb0, 0x31eb4, 1463 0x31ec8, 0x31ed4, 1464 0x31fb8, 0x32004, 1465 0x32200, 0x32200, 1466 0x32208, 0x32240, 1467 0x32248, 0x32280, 1468 0x32288, 0x322c0, 1469 0x322c8, 0x322fc, 1470 0x32600, 0x32630, 1471 0x32a00, 0x32abc, 1472 0x32b00, 0x32b10, 1473 0x32b20, 0x32b30, 1474 0x32b40, 0x32b50, 1475 0x32b60, 0x32b70, 1476 0x33000, 0x33028, 1477 0x33030, 0x33048, 1478 0x33060, 0x33068, 1479 0x33070, 0x3309c, 1480 0x330f0, 0x33128, 1481 0x33130, 0x33148, 1482 0x33160, 0x33168, 1483 0x33170, 0x3319c, 1484 0x331f0, 0x33238, 1485 0x33240, 0x33240, 1486 0x33248, 0x33250, 1487 0x3325c, 0x33264, 1488 0x33270, 0x332b8, 1489 0x332c0, 0x332e4, 1490 0x332f8, 0x33338, 1491 0x33340, 0x33340, 1492 0x33348, 0x33350, 1493 0x3335c, 0x33364, 1494 0x33370, 0x333b8, 1495 0x333c0, 0x333e4, 1496 0x333f8, 0x33428, 1497 0x33430, 0x33448, 1498 0x33460, 0x33468, 1499 0x33470, 0x3349c, 1500 0x334f0, 0x33528, 1501 0x33530, 0x33548, 1502 0x33560, 0x33568, 1503 0x33570, 0x3359c, 1504 0x335f0, 0x33638, 1505 0x33640, 0x33640, 1506 0x33648, 0x33650, 1507 0x3365c, 0x33664, 1508 0x33670, 0x336b8, 1509 0x336c0, 0x336e4, 1510 0x336f8, 0x33738, 1511 0x33740, 0x33740, 1512 0x33748, 0x33750, 1513 0x3375c, 0x33764, 1514 0x33770, 0x337b8, 1515 0x337c0, 0x337e4, 1516 0x337f8, 0x337fc, 1517 0x33814, 0x33814, 1518 0x3382c, 0x3382c, 1519 0x33880, 0x3388c, 1520 0x338e8, 0x338ec, 1521 0x33900, 0x33928, 1522 0x33930, 0x33948, 1523 0x33960, 0x33968, 1524 0x33970, 0x3399c, 1525 0x339f0, 0x33a38, 1526 0x33a40, 0x33a40, 1527 0x33a48, 0x33a50, 1528 0x33a5c, 0x33a64, 1529 0x33a70, 0x33ab8, 1530 0x33ac0, 0x33ae4, 1531 0x33af8, 0x33b10, 1532 0x33b28, 0x33b28, 1533 0x33b3c, 0x33b50, 1534 0x33bf0, 0x33c10, 1535 0x33c28, 0x33c28, 1536 0x33c3c, 0x33c50, 1537 0x33cf0, 0x33cfc, 1538 0x34000, 0x34030, 1539 0x34038, 0x34038, 1540 0x34040, 0x34040, 1541 0x34100, 0x34144, 1542 0x34190, 0x341a0, 1543 0x341a8, 0x341b8, 1544 0x341c4, 0x341c8, 1545 0x341d0, 0x341d0, 1546 0x34200, 0x34318, 1547 0x34400, 0x344b4, 1548 0x344c0, 0x3452c, 1549 0x34540, 0x3461c, 1550 0x34800, 0x34828, 1551 0x34834, 0x34834, 1552 0x348c0, 0x34908, 1553 0x34910, 0x349ac, 1554 0x34a00, 0x34a14, 1555 0x34a1c, 0x34a2c, 1556 0x34a44, 0x34a50, 1557 0x34a74, 0x34a74, 1558 0x34a7c, 0x34afc, 1559 0x34b08, 0x34c24, 1560 0x34d00, 0x34d00, 1561 0x34d08, 0x34d14, 1562 0x34d1c, 0x34d20, 1563 0x34d3c, 0x34d3c, 1564 0x34d48, 0x34d50, 1565 0x35200, 0x3520c, 1566 0x35220, 0x35220, 1567 0x35240, 0x35240, 1568 0x35600, 0x3560c, 1569 0x35a00, 0x35a1c, 1570 0x35e00, 0x35e20, 1571 0x35e38, 0x35e3c, 1572 0x35e80, 0x35e80, 1573 0x35e88, 0x35ea8, 1574 0x35eb0, 0x35eb4, 1575 0x35ec8, 0x35ed4, 1576 0x35fb8, 0x36004, 1577 0x36200, 0x36200, 1578 0x36208, 0x36240, 1579 0x36248, 0x36280, 1580 0x36288, 0x362c0, 1581 0x362c8, 0x362fc, 1582 0x36600, 0x36630, 1583 0x36a00, 0x36abc, 1584 0x36b00, 0x36b10, 1585 0x36b20, 0x36b30, 1586 0x36b40, 0x36b50, 1587 0x36b60, 0x36b70, 1588 0x37000, 0x37028, 1589 0x37030, 0x37048, 1590 0x37060, 0x37068, 1591 0x37070, 0x3709c, 1592 0x370f0, 0x37128, 1593 0x37130, 0x37148, 1594 0x37160, 0x37168, 1595 0x37170, 0x3719c, 1596 0x371f0, 0x37238, 1597 0x37240, 0x37240, 1598 0x37248, 0x37250, 1599 0x3725c, 0x37264, 1600 0x37270, 0x372b8, 1601 0x372c0, 0x372e4, 1602 0x372f8, 0x37338, 1603 0x37340, 0x37340, 1604 0x37348, 0x37350, 1605 0x3735c, 0x37364, 1606 0x37370, 0x373b8, 1607 0x373c0, 0x373e4, 1608 0x373f8, 0x37428, 1609 0x37430, 0x37448, 1610 0x37460, 0x37468, 1611 0x37470, 0x3749c, 1612 0x374f0, 0x37528, 1613 0x37530, 0x37548, 1614 0x37560, 0x37568, 1615 0x37570, 0x3759c, 1616 0x375f0, 0x37638, 1617 0x37640, 0x37640, 1618 0x37648, 0x37650, 1619 0x3765c, 0x37664, 1620 0x37670, 0x376b8, 1621 0x376c0, 0x376e4, 1622 0x376f8, 0x37738, 1623 0x37740, 0x37740, 1624 0x37748, 0x37750, 1625 0x3775c, 0x37764, 1626 0x37770, 0x377b8, 1627 0x377c0, 0x377e4, 1628 0x377f8, 0x377fc, 1629 0x37814, 0x37814, 1630 0x3782c, 0x3782c, 1631 0x37880, 0x3788c, 1632 0x378e8, 0x378ec, 1633 0x37900, 0x37928, 1634 0x37930, 0x37948, 1635 0x37960, 0x37968, 1636 0x37970, 0x3799c, 1637 0x379f0, 0x37a38, 1638 0x37a40, 0x37a40, 1639 0x37a48, 0x37a50, 1640 0x37a5c, 0x37a64, 1641 0x37a70, 0x37ab8, 1642 0x37ac0, 0x37ae4, 1643 0x37af8, 0x37b10, 1644 0x37b28, 0x37b28, 1645 0x37b3c, 0x37b50, 1646 0x37bf0, 0x37c10, 1647 0x37c28, 0x37c28, 1648 0x37c3c, 0x37c50, 1649 0x37cf0, 0x37cfc, 1650 0x38000, 0x38030, 1651 0x38038, 0x38038, 1652 0x38040, 0x38040, 1653 0x38100, 0x38144, 1654 0x38190, 0x381a0, 1655 0x381a8, 0x381b8, 1656 0x381c4, 0x381c8, 1657 0x381d0, 0x381d0, 1658 0x38200, 0x38318, 1659 0x38400, 0x384b4, 1660 0x384c0, 0x3852c, 1661 0x38540, 0x3861c, 1662 0x38800, 0x38828, 1663 0x38834, 0x38834, 1664 0x388c0, 0x38908, 1665 0x38910, 0x389ac, 1666 0x38a00, 0x38a14, 1667 0x38a1c, 0x38a2c, 1668 0x38a44, 0x38a50, 1669 0x38a74, 0x38a74, 1670 0x38a7c, 0x38afc, 1671 0x38b08, 0x38c24, 1672 0x38d00, 0x38d00, 1673 0x38d08, 0x38d14, 1674 0x38d1c, 0x38d20, 1675 0x38d3c, 0x38d3c, 1676 0x38d48, 0x38d50, 1677 0x39200, 0x3920c, 1678 0x39220, 0x39220, 1679 0x39240, 0x39240, 1680 0x39600, 0x3960c, 1681 0x39a00, 0x39a1c, 1682 0x39e00, 0x39e20, 1683 0x39e38, 0x39e3c, 1684 0x39e80, 0x39e80, 1685 0x39e88, 0x39ea8, 1686 0x39eb0, 0x39eb4, 1687 0x39ec8, 0x39ed4, 1688 0x39fb8, 0x3a004, 1689 0x3a200, 0x3a200, 1690 0x3a208, 0x3a240, 1691 0x3a248, 0x3a280, 1692 0x3a288, 0x3a2c0, 1693 0x3a2c8, 0x3a2fc, 1694 0x3a600, 0x3a630, 1695 0x3aa00, 0x3aabc, 1696 0x3ab00, 0x3ab10, 1697 0x3ab20, 0x3ab30, 1698 0x3ab40, 0x3ab50, 1699 0x3ab60, 0x3ab70, 1700 0x3b000, 0x3b028, 1701 0x3b030, 0x3b048, 1702 0x3b060, 0x3b068, 1703 0x3b070, 0x3b09c, 1704 0x3b0f0, 0x3b128, 1705 0x3b130, 0x3b148, 1706 0x3b160, 0x3b168, 1707 0x3b170, 0x3b19c, 1708 0x3b1f0, 0x3b238, 1709 0x3b240, 0x3b240, 1710 0x3b248, 0x3b250, 1711 0x3b25c, 0x3b264, 1712 0x3b270, 0x3b2b8, 1713 0x3b2c0, 0x3b2e4, 1714 0x3b2f8, 0x3b338, 1715 0x3b340, 0x3b340, 1716 0x3b348, 0x3b350, 1717 0x3b35c, 0x3b364, 1718 0x3b370, 0x3b3b8, 1719 0x3b3c0, 0x3b3e4, 1720 0x3b3f8, 0x3b428, 1721 0x3b430, 0x3b448, 1722 0x3b460, 0x3b468, 1723 0x3b470, 0x3b49c, 1724 0x3b4f0, 0x3b528, 1725 0x3b530, 0x3b548, 1726 0x3b560, 0x3b568, 1727 0x3b570, 0x3b59c, 1728 0x3b5f0, 0x3b638, 1729 0x3b640, 0x3b640, 1730 0x3b648, 0x3b650, 1731 0x3b65c, 0x3b664, 1732 0x3b670, 0x3b6b8, 1733 0x3b6c0, 0x3b6e4, 1734 0x3b6f8, 0x3b738, 1735 0x3b740, 0x3b740, 1736 0x3b748, 0x3b750, 1737 0x3b75c, 0x3b764, 1738 0x3b770, 0x3b7b8, 1739 0x3b7c0, 0x3b7e4, 1740 0x3b7f8, 0x3b7fc, 1741 0x3b814, 0x3b814, 1742 0x3b82c, 0x3b82c, 1743 0x3b880, 0x3b88c, 1744 0x3b8e8, 0x3b8ec, 1745 0x3b900, 0x3b928, 1746 0x3b930, 0x3b948, 1747 0x3b960, 0x3b968, 1748 0x3b970, 0x3b99c, 1749 0x3b9f0, 0x3ba38, 1750 0x3ba40, 0x3ba40, 1751 0x3ba48, 0x3ba50, 1752 0x3ba5c, 0x3ba64, 1753 0x3ba70, 0x3bab8, 1754 0x3bac0, 0x3bae4, 1755 0x3baf8, 0x3bb10, 1756 0x3bb28, 0x3bb28, 1757 0x3bb3c, 0x3bb50, 1758 0x3bbf0, 0x3bc10, 1759 0x3bc28, 0x3bc28, 1760 0x3bc3c, 0x3bc50, 1761 0x3bcf0, 0x3bcfc, 1762 0x3c000, 0x3c030, 1763 0x3c038, 0x3c038, 1764 0x3c040, 0x3c040, 1765 0x3c100, 0x3c144, 1766 0x3c190, 0x3c1a0, 1767 0x3c1a8, 0x3c1b8, 1768 0x3c1c4, 0x3c1c8, 1769 0x3c1d0, 0x3c1d0, 1770 0x3c200, 0x3c318, 1771 0x3c400, 0x3c4b4, 1772 0x3c4c0, 0x3c52c, 1773 0x3c540, 0x3c61c, 1774 0x3c800, 0x3c828, 1775 0x3c834, 0x3c834, 1776 0x3c8c0, 0x3c908, 1777 0x3c910, 0x3c9ac, 1778 0x3ca00, 0x3ca14, 1779 0x3ca1c, 0x3ca2c, 1780 0x3ca44, 0x3ca50, 1781 0x3ca74, 0x3ca74, 1782 0x3ca7c, 0x3cafc, 1783 0x3cb08, 0x3cc24, 1784 0x3cd00, 0x3cd00, 1785 0x3cd08, 0x3cd14, 1786 0x3cd1c, 0x3cd20, 1787 0x3cd3c, 0x3cd3c, 1788 0x3cd48, 0x3cd50, 1789 0x3d200, 0x3d20c, 1790 0x3d220, 0x3d220, 1791 0x3d240, 0x3d240, 1792 0x3d600, 0x3d60c, 1793 0x3da00, 0x3da1c, 1794 0x3de00, 0x3de20, 1795 0x3de38, 0x3de3c, 1796 0x3de80, 0x3de80, 1797 0x3de88, 0x3dea8, 1798 0x3deb0, 0x3deb4, 1799 0x3dec8, 0x3ded4, 1800 0x3dfb8, 0x3e004, 1801 0x3e200, 0x3e200, 1802 0x3e208, 0x3e240, 1803 0x3e248, 0x3e280, 1804 0x3e288, 0x3e2c0, 1805 0x3e2c8, 0x3e2fc, 1806 0x3e600, 0x3e630, 1807 0x3ea00, 0x3eabc, 1808 0x3eb00, 0x3eb10, 1809 0x3eb20, 0x3eb30, 1810 0x3eb40, 0x3eb50, 1811 0x3eb60, 0x3eb70, 1812 0x3f000, 0x3f028, 1813 0x3f030, 0x3f048, 1814 0x3f060, 0x3f068, 1815 0x3f070, 0x3f09c, 1816 0x3f0f0, 0x3f128, 1817 0x3f130, 0x3f148, 1818 0x3f160, 0x3f168, 1819 0x3f170, 0x3f19c, 1820 0x3f1f0, 0x3f238, 1821 0x3f240, 0x3f240, 1822 0x3f248, 0x3f250, 1823 0x3f25c, 0x3f264, 1824 0x3f270, 0x3f2b8, 1825 0x3f2c0, 0x3f2e4, 1826 0x3f2f8, 0x3f338, 1827 0x3f340, 0x3f340, 1828 0x3f348, 0x3f350, 1829 0x3f35c, 0x3f364, 1830 0x3f370, 0x3f3b8, 1831 0x3f3c0, 0x3f3e4, 1832 0x3f3f8, 0x3f428, 1833 0x3f430, 0x3f448, 1834 0x3f460, 0x3f468, 1835 0x3f470, 0x3f49c, 1836 0x3f4f0, 0x3f528, 1837 0x3f530, 0x3f548, 1838 0x3f560, 0x3f568, 1839 0x3f570, 0x3f59c, 1840 0x3f5f0, 0x3f638, 1841 0x3f640, 0x3f640, 1842 0x3f648, 0x3f650, 1843 0x3f65c, 0x3f664, 1844 0x3f670, 0x3f6b8, 1845 0x3f6c0, 0x3f6e4, 1846 0x3f6f8, 0x3f738, 1847 0x3f740, 0x3f740, 1848 0x3f748, 0x3f750, 1849 0x3f75c, 0x3f764, 1850 0x3f770, 0x3f7b8, 1851 0x3f7c0, 0x3f7e4, 1852 0x3f7f8, 0x3f7fc, 1853 0x3f814, 0x3f814, 1854 0x3f82c, 0x3f82c, 1855 0x3f880, 0x3f88c, 1856 0x3f8e8, 0x3f8ec, 1857 0x3f900, 0x3f928, 1858 0x3f930, 0x3f948, 1859 0x3f960, 0x3f968, 1860 0x3f970, 0x3f99c, 1861 0x3f9f0, 0x3fa38, 1862 0x3fa40, 0x3fa40, 1863 0x3fa48, 0x3fa50, 1864 0x3fa5c, 0x3fa64, 1865 0x3fa70, 0x3fab8, 1866 0x3fac0, 0x3fae4, 1867 0x3faf8, 0x3fb10, 1868 0x3fb28, 0x3fb28, 1869 0x3fb3c, 0x3fb50, 1870 0x3fbf0, 0x3fc10, 1871 0x3fc28, 0x3fc28, 1872 0x3fc3c, 0x3fc50, 1873 0x3fcf0, 0x3fcfc, 1874 0x40000, 0x4000c, 1875 0x40040, 0x40050, 1876 0x40060, 0x40068, 1877 0x4007c, 0x4008c, 1878 0x40094, 0x400b0, 1879 0x400c0, 0x40144, 1880 0x40180, 0x4018c, 1881 0x40200, 0x40254, 1882 0x40260, 0x40264, 1883 0x40270, 0x40288, 1884 0x40290, 0x40298, 1885 0x402ac, 0x402c8, 1886 0x402d0, 0x402e0, 1887 0x402f0, 0x402f0, 1888 0x40300, 0x4033c, 1889 0x403f8, 0x403fc, 1890 0x41304, 0x413c4, 1891 0x41400, 0x4140c, 1892 0x41414, 0x4141c, 1893 0x41480, 0x414d0, 1894 0x44000, 0x44054, 1895 0x4405c, 0x44078, 1896 0x440c0, 0x44174, 1897 0x44180, 0x441ac, 1898 0x441b4, 0x441b8, 1899 0x441c0, 0x44254, 1900 0x4425c, 0x44278, 1901 0x442c0, 0x44374, 1902 0x44380, 0x443ac, 1903 0x443b4, 0x443b8, 1904 0x443c0, 0x44454, 1905 0x4445c, 0x44478, 1906 0x444c0, 0x44574, 1907 0x44580, 0x445ac, 1908 0x445b4, 0x445b8, 1909 0x445c0, 0x44654, 1910 0x4465c, 0x44678, 1911 0x446c0, 0x44774, 1912 0x44780, 0x447ac, 1913 0x447b4, 0x447b8, 1914 0x447c0, 0x44854, 1915 0x4485c, 0x44878, 1916 0x448c0, 0x44974, 1917 0x44980, 0x449ac, 1918 0x449b4, 0x449b8, 1919 0x449c0, 0x449fc, 1920 0x45000, 0x45004, 1921 0x45010, 0x45030, 1922 0x45040, 0x45060, 1923 0x45068, 0x45068, 1924 0x45080, 0x45084, 1925 0x450a0, 0x450b0, 1926 0x45200, 0x45204, 1927 0x45210, 0x45230, 1928 0x45240, 0x45260, 1929 0x45268, 0x45268, 1930 0x45280, 0x45284, 1931 0x452a0, 0x452b0, 1932 0x460c0, 0x460e4, 1933 0x47000, 0x4703c, 1934 0x47044, 0x4708c, 1935 0x47200, 0x47250, 1936 0x47400, 0x47408, 1937 0x47414, 0x47420, 1938 0x47600, 0x47618, 1939 0x47800, 0x47814, 1940 0x48000, 0x4800c, 1941 0x48040, 0x48050, 1942 0x48060, 0x48068, 1943 0x4807c, 0x4808c, 1944 0x48094, 0x480b0, 1945 0x480c0, 0x48144, 1946 0x48180, 0x4818c, 1947 0x48200, 0x48254, 1948 0x48260, 0x48264, 1949 0x48270, 0x48288, 1950 0x48290, 0x48298, 1951 0x482ac, 0x482c8, 1952 0x482d0, 0x482e0, 1953 0x482f0, 0x482f0, 1954 0x48300, 0x4833c, 1955 0x483f8, 0x483fc, 1956 0x49304, 0x493c4, 1957 0x49400, 0x4940c, 1958 0x49414, 0x4941c, 1959 0x49480, 0x494d0, 1960 0x4c000, 0x4c054, 1961 0x4c05c, 0x4c078, 1962 0x4c0c0, 0x4c174, 1963 0x4c180, 0x4c1ac, 1964 0x4c1b4, 0x4c1b8, 1965 0x4c1c0, 0x4c254, 1966 0x4c25c, 0x4c278, 1967 0x4c2c0, 0x4c374, 1968 0x4c380, 0x4c3ac, 1969 0x4c3b4, 0x4c3b8, 1970 0x4c3c0, 0x4c454, 1971 0x4c45c, 0x4c478, 1972 0x4c4c0, 0x4c574, 1973 0x4c580, 0x4c5ac, 1974 0x4c5b4, 0x4c5b8, 1975 0x4c5c0, 0x4c654, 1976 0x4c65c, 0x4c678, 1977 0x4c6c0, 0x4c774, 1978 0x4c780, 0x4c7ac, 1979 0x4c7b4, 0x4c7b8, 1980 0x4c7c0, 0x4c854, 1981 0x4c85c, 0x4c878, 1982 0x4c8c0, 0x4c974, 1983 0x4c980, 0x4c9ac, 1984 0x4c9b4, 0x4c9b8, 1985 0x4c9c0, 0x4c9fc, 1986 0x4d000, 0x4d004, 1987 0x4d010, 0x4d030, 1988 0x4d040, 0x4d060, 1989 0x4d068, 0x4d068, 1990 0x4d080, 0x4d084, 1991 0x4d0a0, 0x4d0b0, 1992 0x4d200, 0x4d204, 1993 0x4d210, 0x4d230, 1994 0x4d240, 0x4d260, 1995 0x4d268, 0x4d268, 1996 0x4d280, 0x4d284, 1997 0x4d2a0, 0x4d2b0, 1998 0x4e0c0, 0x4e0e4, 1999 0x4f000, 0x4f03c, 2000 0x4f044, 0x4f08c, 2001 0x4f200, 0x4f250, 2002 0x4f400, 0x4f408, 2003 0x4f414, 0x4f420, 2004 0x4f600, 0x4f618, 2005 0x4f800, 0x4f814, 2006 0x50000, 0x50084, 2007 0x50090, 0x500cc, 2008 0x50400, 0x50400, 2009 0x50800, 0x50884, 2010 0x50890, 0x508cc, 2011 0x50c00, 0x50c00, 2012 0x51000, 0x5101c, 2013 0x51300, 0x51308, 2014 }; 2015 2016 static const unsigned int t5vf_reg_ranges[] = { 2017 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2018 VF_MPS_REG(A_MPS_VF_CTL), 2019 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2020 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2021 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2022 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2023 FW_T4VF_MBDATA_BASE_ADDR, 2024 FW_T4VF_MBDATA_BASE_ADDR + 2025 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2026 }; 2027 2028 static const unsigned int t6_reg_ranges[] = { 2029 0x1008, 0x101c, 2030 0x1024, 0x10a8, 2031 0x10b4, 0x10f8, 2032 0x1100, 0x1114, 2033 0x111c, 0x112c, 2034 0x1138, 0x113c, 2035 0x1144, 0x114c, 2036 0x1180, 0x1184, 2037 0x1190, 0x1194, 2038 0x11a0, 0x11a4, 2039 0x11b0, 0x11b4, 2040 0x11fc, 0x1274, 2041 0x1280, 0x133c, 2042 0x1800, 0x18fc, 2043 0x3000, 0x302c, 2044 0x3060, 0x30b0, 2045 0x30b8, 0x30d8, 2046 0x30e0, 0x30fc, 2047 0x3140, 0x357c, 2048 0x35a8, 0x35cc, 2049 0x35ec, 0x35ec, 2050 0x3600, 0x5624, 2051 0x56cc, 0x56ec, 2052 0x56f4, 0x5720, 2053 0x5728, 0x575c, 2054 0x580c, 0x5814, 2055 0x5890, 0x589c, 2056 0x58a4, 0x58ac, 2057 0x58b8, 0x58bc, 2058 0x5940, 0x595c, 2059 0x5980, 0x598c, 2060 0x59b0, 0x59c8, 2061 0x59d0, 0x59dc, 2062 0x59fc, 0x5a18, 2063 0x5a60, 0x5a6c, 2064 0x5a80, 0x5a8c, 2065 0x5a94, 0x5a9c, 2066 0x5b94, 0x5bfc, 2067 0x5c10, 0x5e48, 2068 0x5e50, 0x5e94, 2069 0x5ea0, 0x5eb0, 2070 0x5ec0, 0x5ec0, 2071 0x5ec8, 0x5ed0, 2072 0x5ee0, 0x5ee0, 2073 0x5ef0, 0x5ef0, 2074 0x5f00, 0x5f00, 2075 0x6000, 0x6020, 2076 0x6028, 0x6040, 2077 0x6058, 0x609c, 2078 0x60a8, 0x619c, 2079 0x7700, 0x7798, 2080 0x77c0, 0x7880, 2081 0x78cc, 0x78fc, 2082 0x7b00, 0x7b58, 2083 0x7b60, 0x7b84, 2084 0x7b8c, 0x7c54, 2085 0x7d00, 0x7d38, 2086 0x7d40, 0x7d84, 2087 0x7d8c, 0x7ddc, 2088 0x7de4, 0x7e04, 2089 0x7e10, 0x7e1c, 2090 0x7e24, 0x7e38, 2091 0x7e40, 0x7e44, 2092 0x7e4c, 0x7e78, 2093 0x7e80, 0x7edc, 2094 0x7ee8, 0x7efc, 2095 0x8dc0, 0x8de4, 2096 0x8df8, 0x8e04, 2097 0x8e10, 0x8e84, 2098 0x8ea0, 0x8f88, 2099 0x8fb8, 0x9058, 2100 0x9060, 0x9060, 2101 0x9068, 0x90f8, 2102 0x9100, 0x9124, 2103 0x9400, 0x9470, 2104 0x9600, 0x9600, 2105 0x9608, 0x9638, 2106 0x9640, 0x9704, 2107 0x9710, 0x971c, 2108 0x9800, 0x9808, 2109 0x9820, 0x983c, 2110 0x9850, 0x9864, 2111 0x9c00, 0x9c6c, 2112 0x9c80, 0x9cec, 2113 0x9d00, 0x9d6c, 2114 0x9d80, 0x9dec, 2115 0x9e00, 0x9e6c, 2116 0x9e80, 0x9eec, 2117 0x9f00, 0x9f6c, 2118 0x9f80, 0xa020, 2119 0xd004, 0xd03c, 2120 0xd100, 0xd118, 2121 0xd200, 0xd214, 2122 0xd220, 0xd234, 2123 0xd240, 0xd254, 2124 0xd260, 0xd274, 2125 0xd280, 0xd294, 2126 0xd2a0, 0xd2b4, 2127 0xd2c0, 0xd2d4, 2128 0xd2e0, 0xd2f4, 2129 0xd300, 0xd31c, 2130 0xdfc0, 0xdfe0, 2131 0xe000, 0xf008, 2132 0xf010, 0xf018, 2133 0xf020, 0xf028, 2134 0x11000, 0x11014, 2135 0x11048, 0x1106c, 2136 0x11074, 0x11088, 2137 0x11098, 0x11120, 2138 0x1112c, 0x1117c, 2139 0x11190, 0x112e0, 2140 0x11300, 0x1130c, 2141 0x12000, 0x1206c, 2142 0x19040, 0x1906c, 2143 0x19078, 0x19080, 2144 0x1908c, 0x190e8, 2145 0x190f0, 0x190f8, 2146 0x19100, 0x19110, 2147 0x19120, 0x19124, 2148 0x19150, 0x19194, 2149 0x1919c, 0x191b0, 2150 0x191d0, 0x191e8, 2151 0x19238, 0x19290, 2152 0x192a4, 0x192b0, 2153 0x192bc, 0x192bc, 2154 0x19348, 0x1934c, 2155 0x193f8, 0x19418, 2156 0x19420, 0x19428, 2157 0x19430, 0x19444, 2158 0x1944c, 0x1946c, 2159 0x19474, 0x19474, 2160 0x19490, 0x194cc, 2161 0x194f0, 0x194f8, 2162 0x19c00, 0x19c48, 2163 0x19c50, 0x19c80, 2164 0x19c94, 0x19c98, 2165 0x19ca0, 0x19cbc, 2166 0x19ce4, 0x19ce4, 2167 0x19cf0, 0x19cf8, 2168 0x19d00, 0x19d28, 2169 0x19d50, 0x19d78, 2170 0x19d94, 0x19d98, 2171 0x19da0, 0x19dc8, 2172 0x19df0, 0x19e10, 2173 0x19e50, 0x19e6c, 2174 0x19ea0, 0x19ebc, 2175 0x19ec4, 0x19ef4, 2176 0x19f04, 0x19f2c, 2177 0x19f34, 0x19f34, 2178 0x19f40, 0x19f50, 2179 0x19f90, 0x19fac, 2180 0x19fc4, 0x19fc8, 2181 0x19fd0, 0x19fe4, 2182 0x1a000, 0x1a004, 2183 0x1a010, 0x1a06c, 2184 0x1a0b0, 0x1a0e4, 2185 0x1a0ec, 0x1a0f8, 2186 0x1a100, 0x1a108, 2187 0x1a114, 0x1a120, 2188 0x1a128, 0x1a130, 2189 0x1a138, 0x1a138, 2190 0x1a190, 0x1a1c4, 2191 0x1a1fc, 0x1a1fc, 2192 0x1e008, 0x1e00c, 2193 0x1e040, 0x1e044, 2194 0x1e04c, 0x1e04c, 2195 0x1e284, 0x1e290, 2196 0x1e2c0, 0x1e2c0, 2197 0x1e2e0, 0x1e2e0, 2198 0x1e300, 0x1e384, 2199 0x1e3c0, 0x1e3c8, 2200 0x1e408, 0x1e40c, 2201 0x1e440, 0x1e444, 2202 0x1e44c, 0x1e44c, 2203 0x1e684, 0x1e690, 2204 0x1e6c0, 0x1e6c0, 2205 0x1e6e0, 0x1e6e0, 2206 0x1e700, 0x1e784, 2207 0x1e7c0, 0x1e7c8, 2208 0x1e808, 0x1e80c, 2209 0x1e840, 0x1e844, 2210 0x1e84c, 0x1e84c, 2211 0x1ea84, 0x1ea90, 2212 0x1eac0, 0x1eac0, 2213 0x1eae0, 0x1eae0, 2214 0x1eb00, 0x1eb84, 2215 0x1ebc0, 0x1ebc8, 2216 0x1ec08, 0x1ec0c, 2217 0x1ec40, 0x1ec44, 2218 0x1ec4c, 0x1ec4c, 2219 0x1ee84, 0x1ee90, 2220 0x1eec0, 0x1eec0, 2221 0x1eee0, 0x1eee0, 2222 0x1ef00, 0x1ef84, 2223 0x1efc0, 0x1efc8, 2224 0x1f008, 0x1f00c, 2225 0x1f040, 0x1f044, 2226 0x1f04c, 0x1f04c, 2227 0x1f284, 0x1f290, 2228 0x1f2c0, 0x1f2c0, 2229 0x1f2e0, 0x1f2e0, 2230 0x1f300, 0x1f384, 2231 0x1f3c0, 0x1f3c8, 2232 0x1f408, 0x1f40c, 2233 0x1f440, 0x1f444, 2234 0x1f44c, 0x1f44c, 2235 0x1f684, 0x1f690, 2236 0x1f6c0, 0x1f6c0, 2237 0x1f6e0, 0x1f6e0, 2238 0x1f700, 0x1f784, 2239 0x1f7c0, 0x1f7c8, 2240 0x1f808, 0x1f80c, 2241 0x1f840, 0x1f844, 2242 0x1f84c, 0x1f84c, 2243 0x1fa84, 0x1fa90, 2244 0x1fac0, 0x1fac0, 2245 0x1fae0, 0x1fae0, 2246 0x1fb00, 0x1fb84, 2247 0x1fbc0, 0x1fbc8, 2248 0x1fc08, 0x1fc0c, 2249 0x1fc40, 0x1fc44, 2250 0x1fc4c, 0x1fc4c, 2251 0x1fe84, 0x1fe90, 2252 0x1fec0, 0x1fec0, 2253 0x1fee0, 0x1fee0, 2254 0x1ff00, 0x1ff84, 2255 0x1ffc0, 0x1ffc8, 2256 0x30000, 0x30030, 2257 0x30038, 0x30038, 2258 0x30040, 0x30040, 2259 0x30048, 0x30048, 2260 0x30050, 0x30050, 2261 0x3005c, 0x30060, 2262 0x30068, 0x30068, 2263 0x30070, 0x30070, 2264 0x30100, 0x30168, 2265 0x30190, 0x301a0, 2266 0x301a8, 0x301b8, 2267 0x301c4, 0x301c8, 2268 0x301d0, 0x301d0, 2269 0x30200, 0x30320, 2270 0x30400, 0x304b4, 2271 0x304c0, 0x3052c, 2272 0x30540, 0x3061c, 2273 0x30800, 0x308a0, 2274 0x308c0, 0x30908, 2275 0x30910, 0x309b8, 2276 0x30a00, 0x30a04, 2277 0x30a0c, 0x30a14, 2278 0x30a1c, 0x30a2c, 2279 0x30a44, 0x30a50, 2280 0x30a74, 0x30a74, 2281 0x30a7c, 0x30afc, 2282 0x30b08, 0x30c24, 2283 0x30d00, 0x30d14, 2284 0x30d1c, 0x30d3c, 2285 0x30d44, 0x30d4c, 2286 0x30d54, 0x30d74, 2287 0x30d7c, 0x30d7c, 2288 0x30de0, 0x30de0, 2289 0x30e00, 0x30ed4, 2290 0x30f00, 0x30fa4, 2291 0x30fc0, 0x30fc4, 2292 0x31000, 0x31004, 2293 0x31080, 0x310fc, 2294 0x31208, 0x31220, 2295 0x3123c, 0x31254, 2296 0x31300, 0x31300, 2297 0x31308, 0x3131c, 2298 0x31338, 0x3133c, 2299 0x31380, 0x31380, 2300 0x31388, 0x313a8, 2301 0x313b4, 0x313b4, 2302 0x31400, 0x31420, 2303 0x31438, 0x3143c, 2304 0x31480, 0x31480, 2305 0x314a8, 0x314a8, 2306 0x314b0, 0x314b4, 2307 0x314c8, 0x314d4, 2308 0x31a40, 0x31a4c, 2309 0x31af0, 0x31b20, 2310 0x31b38, 0x31b3c, 2311 0x31b80, 0x31b80, 2312 0x31ba8, 0x31ba8, 2313 0x31bb0, 0x31bb4, 2314 0x31bc8, 0x31bd4, 2315 0x32140, 0x3218c, 2316 0x321f0, 0x321f4, 2317 0x32200, 0x32200, 2318 0x32218, 0x32218, 2319 0x32400, 0x32400, 2320 0x32408, 0x3241c, 2321 0x32618, 0x32620, 2322 0x32664, 0x32664, 2323 0x326a8, 0x326a8, 2324 0x326ec, 0x326ec, 2325 0x32a00, 0x32abc, 2326 0x32b00, 0x32b38, 2327 0x32b40, 0x32b58, 2328 0x32b60, 0x32b78, 2329 0x32c00, 0x32c00, 2330 0x32c08, 0x32c3c, 2331 0x32e00, 0x32e2c, 2332 0x32f00, 0x32f2c, 2333 0x33000, 0x3302c, 2334 0x33034, 0x33050, 2335 0x33058, 0x33058, 2336 0x33060, 0x3308c, 2337 0x3309c, 0x330ac, 2338 0x330c0, 0x330c0, 2339 0x330c8, 0x330d0, 2340 0x330d8, 0x330e0, 2341 0x330ec, 0x3312c, 2342 0x33134, 0x33150, 2343 0x33158, 0x33158, 2344 0x33160, 0x3318c, 2345 0x3319c, 0x331ac, 2346 0x331c0, 0x331c0, 2347 0x331c8, 0x331d0, 2348 0x331d8, 0x331e0, 2349 0x331ec, 0x33290, 2350 0x33298, 0x332c4, 2351 0x332e4, 0x33390, 2352 0x33398, 0x333c4, 2353 0x333e4, 0x3342c, 2354 0x33434, 0x33450, 2355 0x33458, 0x33458, 2356 0x33460, 0x3348c, 2357 0x3349c, 0x334ac, 2358 0x334c0, 0x334c0, 2359 0x334c8, 0x334d0, 2360 0x334d8, 0x334e0, 2361 0x334ec, 0x3352c, 2362 0x33534, 0x33550, 2363 0x33558, 0x33558, 2364 0x33560, 0x3358c, 2365 0x3359c, 0x335ac, 2366 0x335c0, 0x335c0, 2367 0x335c8, 0x335d0, 2368 0x335d8, 0x335e0, 2369 0x335ec, 0x33690, 2370 0x33698, 0x336c4, 2371 0x336e4, 0x33790, 2372 0x33798, 0x337c4, 2373 0x337e4, 0x337fc, 2374 0x33814, 0x33814, 2375 0x33854, 0x33868, 2376 0x33880, 0x3388c, 2377 0x338c0, 0x338d0, 2378 0x338e8, 0x338ec, 2379 0x33900, 0x3392c, 2380 0x33934, 0x33950, 2381 0x33958, 0x33958, 2382 0x33960, 0x3398c, 2383 0x3399c, 0x339ac, 2384 0x339c0, 0x339c0, 2385 0x339c8, 0x339d0, 2386 0x339d8, 0x339e0, 2387 0x339ec, 0x33a90, 2388 0x33a98, 0x33ac4, 2389 0x33ae4, 0x33b10, 2390 0x33b24, 0x33b28, 2391 0x33b38, 0x33b50, 2392 0x33bf0, 0x33c10, 2393 0x33c24, 0x33c28, 2394 0x33c38, 0x33c50, 2395 0x33cf0, 0x33cfc, 2396 0x34000, 0x34030, 2397 0x34038, 0x34038, 2398 0x34040, 0x34040, 2399 0x34048, 0x34048, 2400 0x34050, 0x34050, 2401 0x3405c, 0x34060, 2402 0x34068, 0x34068, 2403 0x34070, 0x34070, 2404 0x34100, 0x34168, 2405 0x34190, 0x341a0, 2406 0x341a8, 0x341b8, 2407 0x341c4, 0x341c8, 2408 0x341d0, 0x341d0, 2409 0x34200, 0x34320, 2410 0x34400, 0x344b4, 2411 0x344c0, 0x3452c, 2412 0x34540, 0x3461c, 2413 0x34800, 0x348a0, 2414 0x348c0, 0x34908, 2415 0x34910, 0x349b8, 2416 0x34a00, 0x34a04, 2417 0x34a0c, 0x34a14, 2418 0x34a1c, 0x34a2c, 2419 0x34a44, 0x34a50, 2420 0x34a74, 0x34a74, 2421 0x34a7c, 0x34afc, 2422 0x34b08, 0x34c24, 2423 0x34d00, 0x34d14, 2424 0x34d1c, 0x34d3c, 2425 0x34d44, 0x34d4c, 2426 0x34d54, 0x34d74, 2427 0x34d7c, 0x34d7c, 2428 0x34de0, 0x34de0, 2429 0x34e00, 0x34ed4, 2430 0x34f00, 0x34fa4, 2431 0x34fc0, 0x34fc4, 2432 0x35000, 0x35004, 2433 0x35080, 0x350fc, 2434 0x35208, 0x35220, 2435 0x3523c, 0x35254, 2436 0x35300, 0x35300, 2437 0x35308, 0x3531c, 2438 0x35338, 0x3533c, 2439 0x35380, 0x35380, 2440 0x35388, 0x353a8, 2441 0x353b4, 0x353b4, 2442 0x35400, 0x35420, 2443 0x35438, 0x3543c, 2444 0x35480, 0x35480, 2445 0x354a8, 0x354a8, 2446 0x354b0, 0x354b4, 2447 0x354c8, 0x354d4, 2448 0x35a40, 0x35a4c, 2449 0x35af0, 0x35b20, 2450 0x35b38, 0x35b3c, 2451 0x35b80, 0x35b80, 2452 0x35ba8, 0x35ba8, 2453 0x35bb0, 0x35bb4, 2454 0x35bc8, 0x35bd4, 2455 0x36140, 0x3618c, 2456 0x361f0, 0x361f4, 2457 0x36200, 0x36200, 2458 0x36218, 0x36218, 2459 0x36400, 0x36400, 2460 0x36408, 0x3641c, 2461 0x36618, 0x36620, 2462 0x36664, 0x36664, 2463 0x366a8, 0x366a8, 2464 0x366ec, 0x366ec, 2465 0x36a00, 0x36abc, 2466 0x36b00, 0x36b38, 2467 0x36b40, 0x36b58, 2468 0x36b60, 0x36b78, 2469 0x36c00, 0x36c00, 2470 0x36c08, 0x36c3c, 2471 0x36e00, 0x36e2c, 2472 0x36f00, 0x36f2c, 2473 0x37000, 0x3702c, 2474 0x37034, 0x37050, 2475 0x37058, 0x37058, 2476 0x37060, 0x3708c, 2477 0x3709c, 0x370ac, 2478 0x370c0, 0x370c0, 2479 0x370c8, 0x370d0, 2480 0x370d8, 0x370e0, 2481 0x370ec, 0x3712c, 2482 0x37134, 0x37150, 2483 0x37158, 0x37158, 2484 0x37160, 0x3718c, 2485 0x3719c, 0x371ac, 2486 0x371c0, 0x371c0, 2487 0x371c8, 0x371d0, 2488 0x371d8, 0x371e0, 2489 0x371ec, 0x37290, 2490 0x37298, 0x372c4, 2491 0x372e4, 0x37390, 2492 0x37398, 0x373c4, 2493 0x373e4, 0x3742c, 2494 0x37434, 0x37450, 2495 0x37458, 0x37458, 2496 0x37460, 0x3748c, 2497 0x3749c, 0x374ac, 2498 0x374c0, 0x374c0, 2499 0x374c8, 0x374d0, 2500 0x374d8, 0x374e0, 2501 0x374ec, 0x3752c, 2502 0x37534, 0x37550, 2503 0x37558, 0x37558, 2504 0x37560, 0x3758c, 2505 0x3759c, 0x375ac, 2506 0x375c0, 0x375c0, 2507 0x375c8, 0x375d0, 2508 0x375d8, 0x375e0, 2509 0x375ec, 0x37690, 2510 0x37698, 0x376c4, 2511 0x376e4, 0x37790, 2512 0x37798, 0x377c4, 2513 0x377e4, 0x377fc, 2514 0x37814, 0x37814, 2515 0x37854, 0x37868, 2516 0x37880, 0x3788c, 2517 0x378c0, 0x378d0, 2518 0x378e8, 0x378ec, 2519 0x37900, 0x3792c, 2520 0x37934, 0x37950, 2521 0x37958, 0x37958, 2522 0x37960, 0x3798c, 2523 0x3799c, 0x379ac, 2524 0x379c0, 0x379c0, 2525 0x379c8, 0x379d0, 2526 0x379d8, 0x379e0, 2527 0x379ec, 0x37a90, 2528 0x37a98, 0x37ac4, 2529 0x37ae4, 0x37b10, 2530 0x37b24, 0x37b28, 2531 0x37b38, 0x37b50, 2532 0x37bf0, 0x37c10, 2533 0x37c24, 0x37c28, 2534 0x37c38, 0x37c50, 2535 0x37cf0, 0x37cfc, 2536 0x40040, 0x40040, 2537 0x40080, 0x40084, 2538 0x40100, 0x40100, 2539 0x40140, 0x401bc, 2540 0x40200, 0x40214, 2541 0x40228, 0x40228, 2542 0x40240, 0x40258, 2543 0x40280, 0x40280, 2544 0x40304, 0x40304, 2545 0x40330, 0x4033c, 2546 0x41304, 0x413c8, 2547 0x413d0, 0x413dc, 2548 0x413f0, 0x413f0, 2549 0x41400, 0x4140c, 2550 0x41414, 0x4141c, 2551 0x41480, 0x414d0, 2552 0x44000, 0x4407c, 2553 0x440c0, 0x441ac, 2554 0x441b4, 0x4427c, 2555 0x442c0, 0x443ac, 2556 0x443b4, 0x4447c, 2557 0x444c0, 0x445ac, 2558 0x445b4, 0x4467c, 2559 0x446c0, 0x447ac, 2560 0x447b4, 0x4487c, 2561 0x448c0, 0x449ac, 2562 0x449b4, 0x44a7c, 2563 0x44ac0, 0x44bac, 2564 0x44bb4, 0x44c7c, 2565 0x44cc0, 0x44dac, 2566 0x44db4, 0x44e7c, 2567 0x44ec0, 0x44fac, 2568 0x44fb4, 0x4507c, 2569 0x450c0, 0x451ac, 2570 0x451b4, 0x451fc, 2571 0x45800, 0x45804, 2572 0x45810, 0x45830, 2573 0x45840, 0x45860, 2574 0x45868, 0x45868, 2575 0x45880, 0x45884, 2576 0x458a0, 0x458b0, 2577 0x45a00, 0x45a04, 2578 0x45a10, 0x45a30, 2579 0x45a40, 0x45a60, 2580 0x45a68, 0x45a68, 2581 0x45a80, 0x45a84, 2582 0x45aa0, 0x45ab0, 2583 0x460c0, 0x460e4, 2584 0x47000, 0x4703c, 2585 0x47044, 0x4708c, 2586 0x47200, 0x47250, 2587 0x47400, 0x47408, 2588 0x47414, 0x47420, 2589 0x47600, 0x47618, 2590 0x47800, 0x47814, 2591 0x47820, 0x4782c, 2592 0x50000, 0x50084, 2593 0x50090, 0x500cc, 2594 0x50300, 0x50384, 2595 0x50400, 0x50400, 2596 0x50800, 0x50884, 2597 0x50890, 0x508cc, 2598 0x50b00, 0x50b84, 2599 0x50c00, 0x50c00, 2600 0x51000, 0x51020, 2601 0x51028, 0x510b0, 2602 0x51300, 0x51324, 2603 }; 2604 2605 static const unsigned int t6vf_reg_ranges[] = { 2606 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2607 VF_MPS_REG(A_MPS_VF_CTL), 2608 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2609 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2610 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2611 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2612 FW_T6VF_MBDATA_BASE_ADDR, 2613 FW_T6VF_MBDATA_BASE_ADDR + 2614 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2615 }; 2616 2617 u32 *buf_end = (u32 *)(buf + buf_size); 2618 const unsigned int *reg_ranges; 2619 int reg_ranges_size, range; 2620 unsigned int chip_version = chip_id(adap); 2621 2622 /* 2623 * Select the right set of register ranges to dump depending on the 2624 * adapter chip type. 2625 */ 2626 switch (chip_version) { 2627 case CHELSIO_T4: 2628 if (adap->flags & IS_VF) { 2629 reg_ranges = t4vf_reg_ranges; 2630 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2631 } else { 2632 reg_ranges = t4_reg_ranges; 2633 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2634 } 2635 break; 2636 2637 case CHELSIO_T5: 2638 if (adap->flags & IS_VF) { 2639 reg_ranges = t5vf_reg_ranges; 2640 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2641 } else { 2642 reg_ranges = t5_reg_ranges; 2643 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2644 } 2645 break; 2646 2647 case CHELSIO_T6: 2648 if (adap->flags & IS_VF) { 2649 reg_ranges = t6vf_reg_ranges; 2650 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2651 } else { 2652 reg_ranges = t6_reg_ranges; 2653 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2654 } 2655 break; 2656 2657 default: 2658 CH_ERR(adap, 2659 "Unsupported chip version %d\n", chip_version); 2660 return; 2661 } 2662 2663 /* 2664 * Clear the register buffer and insert the appropriate register 2665 * values selected by the above register ranges. 2666 */ 2667 memset(buf, 0, buf_size); 2668 for (range = 0; range < reg_ranges_size; range += 2) { 2669 unsigned int reg = reg_ranges[range]; 2670 unsigned int last_reg = reg_ranges[range + 1]; 2671 u32 *bufp = (u32 *)(buf + reg); 2672 2673 /* 2674 * Iterate across the register range filling in the register 2675 * buffer but don't write past the end of the register buffer. 2676 */ 2677 while (reg <= last_reg && bufp < buf_end) { 2678 *bufp++ = t4_read_reg(adap, reg); 2679 reg += sizeof(u32); 2680 } 2681 } 2682 } 2683 2684 /* 2685 * Partial EEPROM Vital Product Data structure. Includes only the ID and 2686 * VPD-R sections. 2687 */ 2688 struct t4_vpd_hdr { 2689 u8 id_tag; 2690 u8 id_len[2]; 2691 u8 id_data[ID_LEN]; 2692 u8 vpdr_tag; 2693 u8 vpdr_len[2]; 2694 }; 2695 2696 /* 2697 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2698 */ 2699 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2700 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2701 2702 #define EEPROM_STAT_ADDR 0x7bfc 2703 #define VPD_BASE 0x400 2704 #define VPD_BASE_OLD 0 2705 #define VPD_LEN 1024 2706 #define VPD_INFO_FLD_HDR_SIZE 3 2707 #define CHELSIO_VPD_UNIQUE_ID 0x82 2708 2709 /* 2710 * Small utility function to wait till any outstanding VPD Access is complete. 2711 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2712 * VPD Access in flight. This allows us to handle the problem of having a 2713 * previous VPD Access time out and prevent an attempt to inject a new VPD 2714 * Request before any in-flight VPD reguest has completed. 2715 */ 2716 static int t4_seeprom_wait(struct adapter *adapter) 2717 { 2718 unsigned int base = adapter->params.pci.vpd_cap_addr; 2719 int max_poll; 2720 2721 /* 2722 * If no VPD Access is in flight, we can just return success right 2723 * away. 2724 */ 2725 if (!adapter->vpd_busy) 2726 return 0; 2727 2728 /* 2729 * Poll the VPD Capability Address/Flag register waiting for it 2730 * to indicate that the operation is complete. 2731 */ 2732 max_poll = EEPROM_MAX_POLL; 2733 do { 2734 u16 val; 2735 2736 udelay(EEPROM_DELAY); 2737 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2738 2739 /* 2740 * If the operation is complete, mark the VPD as no longer 2741 * busy and return success. 2742 */ 2743 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2744 adapter->vpd_busy = 0; 2745 return 0; 2746 } 2747 } while (--max_poll); 2748 2749 /* 2750 * Failure! Note that we leave the VPD Busy status set in order to 2751 * avoid pushing a new VPD Access request into the VPD Capability till 2752 * the current operation eventually succeeds. It's a bug to issue a 2753 * new request when an existing request is in flight and will result 2754 * in corrupt hardware state. 2755 */ 2756 return -ETIMEDOUT; 2757 } 2758 2759 /** 2760 * t4_seeprom_read - read a serial EEPROM location 2761 * @adapter: adapter to read 2762 * @addr: EEPROM virtual address 2763 * @data: where to store the read data 2764 * 2765 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2766 * VPD capability. Note that this function must be called with a virtual 2767 * address. 2768 */ 2769 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2770 { 2771 unsigned int base = adapter->params.pci.vpd_cap_addr; 2772 int ret; 2773 2774 /* 2775 * VPD Accesses must alway be 4-byte aligned! 2776 */ 2777 if (addr >= EEPROMVSIZE || (addr & 3)) 2778 return -EINVAL; 2779 2780 /* 2781 * Wait for any previous operation which may still be in flight to 2782 * complete. 2783 */ 2784 ret = t4_seeprom_wait(adapter); 2785 if (ret) { 2786 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2787 return ret; 2788 } 2789 2790 /* 2791 * Issue our new VPD Read request, mark the VPD as being busy and wait 2792 * for our request to complete. If it doesn't complete, note the 2793 * error and return it to our caller. Note that we do not reset the 2794 * VPD Busy status! 2795 */ 2796 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2797 adapter->vpd_busy = 1; 2798 adapter->vpd_flag = PCI_VPD_ADDR_F; 2799 ret = t4_seeprom_wait(adapter); 2800 if (ret) { 2801 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2802 return ret; 2803 } 2804 2805 /* 2806 * Grab the returned data, swizzle it into our endianness and 2807 * return success. 2808 */ 2809 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2810 *data = le32_to_cpu(*data); 2811 return 0; 2812 } 2813 2814 /** 2815 * t4_seeprom_write - write a serial EEPROM location 2816 * @adapter: adapter to write 2817 * @addr: virtual EEPROM address 2818 * @data: value to write 2819 * 2820 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2821 * VPD capability. Note that this function must be called with a virtual 2822 * address. 2823 */ 2824 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2825 { 2826 unsigned int base = adapter->params.pci.vpd_cap_addr; 2827 int ret; 2828 u32 stats_reg; 2829 int max_poll; 2830 2831 /* 2832 * VPD Accesses must alway be 4-byte aligned! 2833 */ 2834 if (addr >= EEPROMVSIZE || (addr & 3)) 2835 return -EINVAL; 2836 2837 /* 2838 * Wait for any previous operation which may still be in flight to 2839 * complete. 2840 */ 2841 ret = t4_seeprom_wait(adapter); 2842 if (ret) { 2843 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2844 return ret; 2845 } 2846 2847 /* 2848 * Issue our new VPD Read request, mark the VPD as being busy and wait 2849 * for our request to complete. If it doesn't complete, note the 2850 * error and return it to our caller. Note that we do not reset the 2851 * VPD Busy status! 2852 */ 2853 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2854 cpu_to_le32(data)); 2855 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2856 (u16)addr | PCI_VPD_ADDR_F); 2857 adapter->vpd_busy = 1; 2858 adapter->vpd_flag = 0; 2859 ret = t4_seeprom_wait(adapter); 2860 if (ret) { 2861 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2862 return ret; 2863 } 2864 2865 /* 2866 * Reset PCI_VPD_DATA register after a transaction and wait for our 2867 * request to complete. If it doesn't complete, return error. 2868 */ 2869 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2870 max_poll = EEPROM_MAX_POLL; 2871 do { 2872 udelay(EEPROM_DELAY); 2873 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2874 } while ((stats_reg & 0x1) && --max_poll); 2875 if (!max_poll) 2876 return -ETIMEDOUT; 2877 2878 /* Return success! */ 2879 return 0; 2880 } 2881 2882 /** 2883 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2884 * @phys_addr: the physical EEPROM address 2885 * @fn: the PCI function number 2886 * @sz: size of function-specific area 2887 * 2888 * Translate a physical EEPROM address to virtual. The first 1K is 2889 * accessed through virtual addresses starting at 31K, the rest is 2890 * accessed through virtual addresses starting at 0. 2891 * 2892 * The mapping is as follows: 2893 * [0..1K) -> [31K..32K) 2894 * [1K..1K+A) -> [ES-A..ES) 2895 * [1K+A..ES) -> [0..ES-A-1K) 2896 * 2897 * where A = @fn * @sz, and ES = EEPROM size. 2898 */ 2899 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2900 { 2901 fn *= sz; 2902 if (phys_addr < 1024) 2903 return phys_addr + (31 << 10); 2904 if (phys_addr < 1024 + fn) 2905 return EEPROMSIZE - fn + phys_addr - 1024; 2906 if (phys_addr < EEPROMSIZE) 2907 return phys_addr - 1024 - fn; 2908 return -EINVAL; 2909 } 2910 2911 /** 2912 * t4_seeprom_wp - enable/disable EEPROM write protection 2913 * @adapter: the adapter 2914 * @enable: whether to enable or disable write protection 2915 * 2916 * Enables or disables write protection on the serial EEPROM. 2917 */ 2918 int t4_seeprom_wp(struct adapter *adapter, int enable) 2919 { 2920 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2921 } 2922 2923 /** 2924 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2925 * @v: Pointer to buffered vpd data structure 2926 * @kw: The keyword to search for 2927 * 2928 * Returns the value of the information field keyword or 2929 * -ENOENT otherwise. 2930 */ 2931 static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw) 2932 { 2933 int i; 2934 unsigned int offset , len; 2935 const u8 *buf = (const u8 *)v; 2936 const u8 *vpdr_len = &v->vpdr_len[0]; 2937 offset = sizeof(struct t4_vpd_hdr); 2938 len = (u16)vpdr_len[0] + ((u16)vpdr_len[1] << 8); 2939 2940 if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) { 2941 return -ENOENT; 2942 } 2943 2944 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2945 if(memcmp(buf + i , kw , 2) == 0){ 2946 i += VPD_INFO_FLD_HDR_SIZE; 2947 return i; 2948 } 2949 2950 i += VPD_INFO_FLD_HDR_SIZE + buf[i+2]; 2951 } 2952 2953 return -ENOENT; 2954 } 2955 2956 2957 /** 2958 * get_vpd_params - read VPD parameters from VPD EEPROM 2959 * @adapter: adapter to read 2960 * @p: where to store the parameters 2961 * @vpd: caller provided temporary space to read the VPD into 2962 * 2963 * Reads card parameters stored in VPD EEPROM. 2964 */ 2965 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 2966 u8 *vpd) 2967 { 2968 int i, ret, addr; 2969 int ec, sn, pn, na; 2970 u8 csum; 2971 const struct t4_vpd_hdr *v; 2972 2973 /* 2974 * Card information normally starts at VPD_BASE but early cards had 2975 * it at 0. 2976 */ 2977 ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd)); 2978 if (ret) 2979 return (ret); 2980 2981 /* 2982 * The VPD shall have a unique identifier specified by the PCI SIG. 2983 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 2984 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 2985 * is expected to automatically put this entry at the 2986 * beginning of the VPD. 2987 */ 2988 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 2989 2990 for (i = 0; i < VPD_LEN; i += 4) { 2991 ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i)); 2992 if (ret) 2993 return ret; 2994 } 2995 v = (const struct t4_vpd_hdr *)vpd; 2996 2997 #define FIND_VPD_KW(var,name) do { \ 2998 var = get_vpd_keyword_val(v , name); \ 2999 if (var < 0) { \ 3000 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3001 return -EINVAL; \ 3002 } \ 3003 } while (0) 3004 3005 FIND_VPD_KW(i, "RV"); 3006 for (csum = 0; i >= 0; i--) 3007 csum += vpd[i]; 3008 3009 if (csum) { 3010 CH_ERR(adapter, 3011 "corrupted VPD EEPROM, actual csum %u\n", csum); 3012 return -EINVAL; 3013 } 3014 3015 FIND_VPD_KW(ec, "EC"); 3016 FIND_VPD_KW(sn, "SN"); 3017 FIND_VPD_KW(pn, "PN"); 3018 FIND_VPD_KW(na, "NA"); 3019 #undef FIND_VPD_KW 3020 3021 memcpy(p->id, v->id_data, ID_LEN); 3022 strstrip(p->id); 3023 memcpy(p->ec, vpd + ec, EC_LEN); 3024 strstrip(p->ec); 3025 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3026 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3027 strstrip(p->sn); 3028 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3029 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3030 strstrip((char *)p->pn); 3031 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3032 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3033 strstrip((char *)p->na); 3034 3035 return 0; 3036 } 3037 3038 /* serial flash and firmware constants and flash config file constants */ 3039 enum { 3040 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3041 3042 /* flash command opcodes */ 3043 SF_PROG_PAGE = 2, /* program page */ 3044 SF_WR_DISABLE = 4, /* disable writes */ 3045 SF_RD_STATUS = 5, /* read status register */ 3046 SF_WR_ENABLE = 6, /* enable writes */ 3047 SF_RD_DATA_FAST = 0xb, /* read flash */ 3048 SF_RD_ID = 0x9f, /* read ID */ 3049 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 3050 }; 3051 3052 /** 3053 * sf1_read - read data from the serial flash 3054 * @adapter: the adapter 3055 * @byte_cnt: number of bytes to read 3056 * @cont: whether another operation will be chained 3057 * @lock: whether to lock SF for PL access only 3058 * @valp: where to store the read data 3059 * 3060 * Reads up to 4 bytes of data from the serial flash. The location of 3061 * the read needs to be specified prior to calling this by issuing the 3062 * appropriate commands to the serial flash. 3063 */ 3064 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3065 int lock, u32 *valp) 3066 { 3067 int ret; 3068 3069 if (!byte_cnt || byte_cnt > 4) 3070 return -EINVAL; 3071 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3072 return -EBUSY; 3073 t4_write_reg(adapter, A_SF_OP, 3074 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3075 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3076 if (!ret) 3077 *valp = t4_read_reg(adapter, A_SF_DATA); 3078 return ret; 3079 } 3080 3081 /** 3082 * sf1_write - write data to the serial flash 3083 * @adapter: the adapter 3084 * @byte_cnt: number of bytes to write 3085 * @cont: whether another operation will be chained 3086 * @lock: whether to lock SF for PL access only 3087 * @val: value to write 3088 * 3089 * Writes up to 4 bytes of data to the serial flash. The location of 3090 * the write needs to be specified prior to calling this by issuing the 3091 * appropriate commands to the serial flash. 3092 */ 3093 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3094 int lock, u32 val) 3095 { 3096 if (!byte_cnt || byte_cnt > 4) 3097 return -EINVAL; 3098 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3099 return -EBUSY; 3100 t4_write_reg(adapter, A_SF_DATA, val); 3101 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3102 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3103 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3104 } 3105 3106 /** 3107 * flash_wait_op - wait for a flash operation to complete 3108 * @adapter: the adapter 3109 * @attempts: max number of polls of the status register 3110 * @delay: delay between polls in ms 3111 * 3112 * Wait for a flash operation to complete by polling the status register. 3113 */ 3114 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3115 { 3116 int ret; 3117 u32 status; 3118 3119 while (1) { 3120 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3121 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3122 return ret; 3123 if (!(status & 1)) 3124 return 0; 3125 if (--attempts == 0) 3126 return -EAGAIN; 3127 if (delay) 3128 msleep(delay); 3129 } 3130 } 3131 3132 /** 3133 * t4_read_flash - read words from serial flash 3134 * @adapter: the adapter 3135 * @addr: the start address for the read 3136 * @nwords: how many 32-bit words to read 3137 * @data: where to store the read data 3138 * @byte_oriented: whether to store data as bytes or as words 3139 * 3140 * Read the specified number of 32-bit words from the serial flash. 3141 * If @byte_oriented is set the read data is stored as a byte array 3142 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3143 * natural endianness. 3144 */ 3145 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3146 unsigned int nwords, u32 *data, int byte_oriented) 3147 { 3148 int ret; 3149 3150 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3151 return -EINVAL; 3152 3153 addr = swab32(addr) | SF_RD_DATA_FAST; 3154 3155 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3156 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3157 return ret; 3158 3159 for ( ; nwords; nwords--, data++) { 3160 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3161 if (nwords == 1) 3162 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3163 if (ret) 3164 return ret; 3165 if (byte_oriented) 3166 *data = (__force __u32)(cpu_to_be32(*data)); 3167 } 3168 return 0; 3169 } 3170 3171 /** 3172 * t4_write_flash - write up to a page of data to the serial flash 3173 * @adapter: the adapter 3174 * @addr: the start address to write 3175 * @n: length of data to write in bytes 3176 * @data: the data to write 3177 * @byte_oriented: whether to store data as bytes or as words 3178 * 3179 * Writes up to a page of data (256 bytes) to the serial flash starting 3180 * at the given address. All the data must be written to the same page. 3181 * If @byte_oriented is set the write data is stored as byte stream 3182 * (i.e. matches what on disk), otherwise in big-endian. 3183 */ 3184 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3185 unsigned int n, const u8 *data, int byte_oriented) 3186 { 3187 int ret; 3188 u32 buf[SF_PAGE_SIZE / 4]; 3189 unsigned int i, c, left, val, offset = addr & 0xff; 3190 3191 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3192 return -EINVAL; 3193 3194 val = swab32(addr) | SF_PROG_PAGE; 3195 3196 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3197 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3198 goto unlock; 3199 3200 for (left = n; left; left -= c) { 3201 c = min(left, 4U); 3202 for (val = 0, i = 0; i < c; ++i) 3203 val = (val << 8) + *data++; 3204 3205 if (!byte_oriented) 3206 val = cpu_to_be32(val); 3207 3208 ret = sf1_write(adapter, c, c != left, 1, val); 3209 if (ret) 3210 goto unlock; 3211 } 3212 ret = flash_wait_op(adapter, 8, 1); 3213 if (ret) 3214 goto unlock; 3215 3216 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3217 3218 /* Read the page to verify the write succeeded */ 3219 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3220 byte_oriented); 3221 if (ret) 3222 return ret; 3223 3224 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3225 CH_ERR(adapter, 3226 "failed to correctly write the flash page at %#x\n", 3227 addr); 3228 return -EIO; 3229 } 3230 return 0; 3231 3232 unlock: 3233 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3234 return ret; 3235 } 3236 3237 /** 3238 * t4_get_fw_version - read the firmware version 3239 * @adapter: the adapter 3240 * @vers: where to place the version 3241 * 3242 * Reads the FW version from flash. 3243 */ 3244 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3245 { 3246 return t4_read_flash(adapter, FLASH_FW_START + 3247 offsetof(struct fw_hdr, fw_ver), 1, 3248 vers, 0); 3249 } 3250 3251 /** 3252 * t4_get_bs_version - read the firmware bootstrap version 3253 * @adapter: the adapter 3254 * @vers: where to place the version 3255 * 3256 * Reads the FW Bootstrap version from flash. 3257 */ 3258 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3259 { 3260 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3261 offsetof(struct fw_hdr, fw_ver), 1, 3262 vers, 0); 3263 } 3264 3265 /** 3266 * t4_get_tp_version - read the TP microcode version 3267 * @adapter: the adapter 3268 * @vers: where to place the version 3269 * 3270 * Reads the TP microcode version from flash. 3271 */ 3272 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3273 { 3274 return t4_read_flash(adapter, FLASH_FW_START + 3275 offsetof(struct fw_hdr, tp_microcode_ver), 3276 1, vers, 0); 3277 } 3278 3279 /** 3280 * t4_get_exprom_version - return the Expansion ROM version (if any) 3281 * @adapter: the adapter 3282 * @vers: where to place the version 3283 * 3284 * Reads the Expansion ROM header from FLASH and returns the version 3285 * number (if present) through the @vers return value pointer. We return 3286 * this in the Firmware Version Format since it's convenient. Return 3287 * 0 on success, -ENOENT if no Expansion ROM is present. 3288 */ 3289 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 3290 { 3291 struct exprom_header { 3292 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3293 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3294 } *hdr; 3295 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3296 sizeof(u32))]; 3297 int ret; 3298 3299 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 3300 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3301 0); 3302 if (ret) 3303 return ret; 3304 3305 hdr = (struct exprom_header *)exprom_header_buf; 3306 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3307 return -ENOENT; 3308 3309 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3310 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3311 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3312 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3313 return 0; 3314 } 3315 3316 /** 3317 * t4_get_scfg_version - return the Serial Configuration version 3318 * @adapter: the adapter 3319 * @vers: where to place the version 3320 * 3321 * Reads the Serial Configuration Version via the Firmware interface 3322 * (thus this can only be called once we're ready to issue Firmware 3323 * commands). The format of the Serial Configuration version is 3324 * adapter specific. Returns 0 on success, an error on failure. 3325 * 3326 * Note that early versions of the Firmware didn't include the ability 3327 * to retrieve the Serial Configuration version, so we zero-out the 3328 * return-value parameter in that case to avoid leaving it with 3329 * garbage in it. 3330 * 3331 * Also note that the Firmware will return its cached copy of the Serial 3332 * Initialization Revision ID, not the actual Revision ID as written in 3333 * the Serial EEPROM. This is only an issue if a new VPD has been written 3334 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3335 * it's best to defer calling this routine till after a FW_RESET_CMD has 3336 * been issued if the Host Driver will be performing a full adapter 3337 * initialization. 3338 */ 3339 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3340 { 3341 u32 scfgrev_param; 3342 int ret; 3343 3344 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3345 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3346 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3347 1, &scfgrev_param, vers); 3348 if (ret) 3349 *vers = 0; 3350 return ret; 3351 } 3352 3353 /** 3354 * t4_get_vpd_version - return the VPD version 3355 * @adapter: the adapter 3356 * @vers: where to place the version 3357 * 3358 * Reads the VPD via the Firmware interface (thus this can only be called 3359 * once we're ready to issue Firmware commands). The format of the 3360 * VPD version is adapter specific. Returns 0 on success, an error on 3361 * failure. 3362 * 3363 * Note that early versions of the Firmware didn't include the ability 3364 * to retrieve the VPD version, so we zero-out the return-value parameter 3365 * in that case to avoid leaving it with garbage in it. 3366 * 3367 * Also note that the Firmware will return its cached copy of the VPD 3368 * Revision ID, not the actual Revision ID as written in the Serial 3369 * EEPROM. This is only an issue if a new VPD has been written and the 3370 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3371 * to defer calling this routine till after a FW_RESET_CMD has been issued 3372 * if the Host Driver will be performing a full adapter initialization. 3373 */ 3374 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3375 { 3376 u32 vpdrev_param; 3377 int ret; 3378 3379 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3380 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3381 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3382 1, &vpdrev_param, vers); 3383 if (ret) 3384 *vers = 0; 3385 return ret; 3386 } 3387 3388 /** 3389 * t4_get_version_info - extract various chip/firmware version information 3390 * @adapter: the adapter 3391 * 3392 * Reads various chip/firmware version numbers and stores them into the 3393 * adapter Adapter Parameters structure. If any of the efforts fails 3394 * the first failure will be returned, but all of the version numbers 3395 * will be read. 3396 */ 3397 int t4_get_version_info(struct adapter *adapter) 3398 { 3399 int ret = 0; 3400 3401 #define FIRST_RET(__getvinfo) \ 3402 do { \ 3403 int __ret = __getvinfo; \ 3404 if (__ret && !ret) \ 3405 ret = __ret; \ 3406 } while (0) 3407 3408 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3409 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3410 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3411 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3412 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3413 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3414 3415 #undef FIRST_RET 3416 3417 return ret; 3418 } 3419 3420 /** 3421 * t4_flash_erase_sectors - erase a range of flash sectors 3422 * @adapter: the adapter 3423 * @start: the first sector to erase 3424 * @end: the last sector to erase 3425 * 3426 * Erases the sectors in the given inclusive range. 3427 */ 3428 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3429 { 3430 int ret = 0; 3431 3432 if (end >= adapter->params.sf_nsec) 3433 return -EINVAL; 3434 3435 while (start <= end) { 3436 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3437 (ret = sf1_write(adapter, 4, 0, 1, 3438 SF_ERASE_SECTOR | (start << 8))) != 0 || 3439 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3440 CH_ERR(adapter, 3441 "erase of flash sector %d failed, error %d\n", 3442 start, ret); 3443 break; 3444 } 3445 start++; 3446 } 3447 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3448 return ret; 3449 } 3450 3451 /** 3452 * t4_flash_cfg_addr - return the address of the flash configuration file 3453 * @adapter: the adapter 3454 * 3455 * Return the address within the flash where the Firmware Configuration 3456 * File is stored, or an error if the device FLASH is too small to contain 3457 * a Firmware Configuration File. 3458 */ 3459 int t4_flash_cfg_addr(struct adapter *adapter) 3460 { 3461 /* 3462 * If the device FLASH isn't large enough to hold a Firmware 3463 * Configuration File, return an error. 3464 */ 3465 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3466 return -ENOSPC; 3467 3468 return FLASH_CFG_START; 3469 } 3470 3471 /* 3472 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3473 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3474 * and emit an error message for mismatched firmware to save our caller the 3475 * effort ... 3476 */ 3477 static int t4_fw_matches_chip(struct adapter *adap, 3478 const struct fw_hdr *hdr) 3479 { 3480 /* 3481 * The expression below will return FALSE for any unsupported adapter 3482 * which will keep us "honest" in the future ... 3483 */ 3484 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3485 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3486 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3487 return 1; 3488 3489 CH_ERR(adap, 3490 "FW image (%d) is not suitable for this adapter (%d)\n", 3491 hdr->chip, chip_id(adap)); 3492 return 0; 3493 } 3494 3495 /** 3496 * t4_load_fw - download firmware 3497 * @adap: the adapter 3498 * @fw_data: the firmware image to write 3499 * @size: image size 3500 * 3501 * Write the supplied firmware image to the card's serial flash. 3502 */ 3503 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3504 { 3505 u32 csum; 3506 int ret, addr; 3507 unsigned int i; 3508 u8 first_page[SF_PAGE_SIZE]; 3509 const u32 *p = (const u32 *)fw_data; 3510 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3511 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3512 unsigned int fw_start_sec; 3513 unsigned int fw_start; 3514 unsigned int fw_size; 3515 3516 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3517 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3518 fw_start = FLASH_FWBOOTSTRAP_START; 3519 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3520 } else { 3521 fw_start_sec = FLASH_FW_START_SEC; 3522 fw_start = FLASH_FW_START; 3523 fw_size = FLASH_FW_MAX_SIZE; 3524 } 3525 3526 if (!size) { 3527 CH_ERR(adap, "FW image has no data\n"); 3528 return -EINVAL; 3529 } 3530 if (size & 511) { 3531 CH_ERR(adap, 3532 "FW image size not multiple of 512 bytes\n"); 3533 return -EINVAL; 3534 } 3535 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3536 CH_ERR(adap, 3537 "FW image size differs from size in FW header\n"); 3538 return -EINVAL; 3539 } 3540 if (size > fw_size) { 3541 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3542 fw_size); 3543 return -EFBIG; 3544 } 3545 if (!t4_fw_matches_chip(adap, hdr)) 3546 return -EINVAL; 3547 3548 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3549 csum += be32_to_cpu(p[i]); 3550 3551 if (csum != 0xffffffff) { 3552 CH_ERR(adap, 3553 "corrupted firmware image, checksum %#x\n", csum); 3554 return -EINVAL; 3555 } 3556 3557 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3558 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3559 if (ret) 3560 goto out; 3561 3562 /* 3563 * We write the correct version at the end so the driver can see a bad 3564 * version if the FW write fails. Start by writing a copy of the 3565 * first page with a bad version. 3566 */ 3567 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3568 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3569 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3570 if (ret) 3571 goto out; 3572 3573 addr = fw_start; 3574 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3575 addr += SF_PAGE_SIZE; 3576 fw_data += SF_PAGE_SIZE; 3577 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3578 if (ret) 3579 goto out; 3580 } 3581 3582 ret = t4_write_flash(adap, 3583 fw_start + offsetof(struct fw_hdr, fw_ver), 3584 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3585 out: 3586 if (ret) 3587 CH_ERR(adap, "firmware download failed, error %d\n", 3588 ret); 3589 return ret; 3590 } 3591 3592 /** 3593 * t4_fwcache - firmware cache operation 3594 * @adap: the adapter 3595 * @op : the operation (flush or flush and invalidate) 3596 */ 3597 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3598 { 3599 struct fw_params_cmd c; 3600 3601 memset(&c, 0, sizeof(c)); 3602 c.op_to_vfn = 3603 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3604 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3605 V_FW_PARAMS_CMD_PFN(adap->pf) | 3606 V_FW_PARAMS_CMD_VFN(0)); 3607 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3608 c.param[0].mnem = 3609 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3610 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3611 c.param[0].val = (__force __be32)op; 3612 3613 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3614 } 3615 3616 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3617 unsigned int *pif_req_wrptr, 3618 unsigned int *pif_rsp_wrptr) 3619 { 3620 int i, j; 3621 u32 cfg, val, req, rsp; 3622 3623 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3624 if (cfg & F_LADBGEN) 3625 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3626 3627 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3628 req = G_POLADBGWRPTR(val); 3629 rsp = G_PILADBGWRPTR(val); 3630 if (pif_req_wrptr) 3631 *pif_req_wrptr = req; 3632 if (pif_rsp_wrptr) 3633 *pif_rsp_wrptr = rsp; 3634 3635 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3636 for (j = 0; j < 6; j++) { 3637 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3638 V_PILADBGRDPTR(rsp)); 3639 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3640 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3641 req++; 3642 rsp++; 3643 } 3644 req = (req + 2) & M_POLADBGRDPTR; 3645 rsp = (rsp + 2) & M_PILADBGRDPTR; 3646 } 3647 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3648 } 3649 3650 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3651 { 3652 u32 cfg; 3653 int i, j, idx; 3654 3655 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3656 if (cfg & F_LADBGEN) 3657 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3658 3659 for (i = 0; i < CIM_MALA_SIZE; i++) { 3660 for (j = 0; j < 5; j++) { 3661 idx = 8 * i + j; 3662 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3663 V_PILADBGRDPTR(idx)); 3664 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3665 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3666 } 3667 } 3668 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3669 } 3670 3671 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3672 { 3673 unsigned int i, j; 3674 3675 for (i = 0; i < 8; i++) { 3676 u32 *p = la_buf + i; 3677 3678 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3679 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3680 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3681 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3682 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3683 } 3684 } 3685 3686 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ 3687 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \ 3688 FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \ 3689 FW_PORT_CAP_ANEG) 3690 3691 /** 3692 * t4_link_l1cfg - apply link configuration to MAC/PHY 3693 * @phy: the PHY to setup 3694 * @mac: the MAC to setup 3695 * @lc: the requested link configuration 3696 * 3697 * Set up a port's MAC and PHY according to a desired link configuration. 3698 * - If the PHY can auto-negotiate first decide what to advertise, then 3699 * enable/disable auto-negotiation as desired, and reset. 3700 * - If the PHY does not auto-negotiate just reset it. 3701 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3702 * otherwise do it later based on the outcome of auto-negotiation. 3703 */ 3704 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3705 struct link_config *lc) 3706 { 3707 struct fw_port_cmd c; 3708 unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO); 3709 3710 lc->link_ok = 0; 3711 if (lc->requested_fc & PAUSE_RX) 3712 fc |= FW_PORT_CAP_FC_RX; 3713 if (lc->requested_fc & PAUSE_TX) 3714 fc |= FW_PORT_CAP_FC_TX; 3715 3716 memset(&c, 0, sizeof(c)); 3717 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3718 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3719 V_FW_PORT_CMD_PORTID(port)); 3720 c.action_to_len16 = 3721 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3722 FW_LEN16(c)); 3723 3724 if (!(lc->supported & FW_PORT_CAP_ANEG)) { 3725 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) | 3726 fc); 3727 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 3728 } else if (lc->autoneg == AUTONEG_DISABLE) { 3729 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi); 3730 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX); 3731 } else 3732 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi); 3733 3734 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3735 } 3736 3737 /** 3738 * t4_restart_aneg - restart autonegotiation 3739 * @adap: the adapter 3740 * @mbox: mbox to use for the FW command 3741 * @port: the port id 3742 * 3743 * Restarts autonegotiation for the selected port. 3744 */ 3745 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3746 { 3747 struct fw_port_cmd c; 3748 3749 memset(&c, 0, sizeof(c)); 3750 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3751 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3752 V_FW_PORT_CMD_PORTID(port)); 3753 c.action_to_len16 = 3754 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3755 FW_LEN16(c)); 3756 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3757 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3758 } 3759 3760 typedef void (*int_handler_t)(struct adapter *adap); 3761 3762 struct intr_info { 3763 unsigned int mask; /* bits to check in interrupt status */ 3764 const char *msg; /* message to print or NULL */ 3765 short stat_idx; /* stat counter to increment or -1 */ 3766 unsigned short fatal; /* whether the condition reported is fatal */ 3767 int_handler_t int_handler; /* platform-specific int handler */ 3768 }; 3769 3770 /** 3771 * t4_handle_intr_status - table driven interrupt handler 3772 * @adapter: the adapter that generated the interrupt 3773 * @reg: the interrupt status register to process 3774 * @acts: table of interrupt actions 3775 * 3776 * A table driven interrupt handler that applies a set of masks to an 3777 * interrupt status word and performs the corresponding actions if the 3778 * interrupts described by the mask have occurred. The actions include 3779 * optionally emitting a warning or alert message. The table is terminated 3780 * by an entry specifying mask 0. Returns the number of fatal interrupt 3781 * conditions. 3782 */ 3783 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 3784 const struct intr_info *acts) 3785 { 3786 int fatal = 0; 3787 unsigned int mask = 0; 3788 unsigned int status = t4_read_reg(adapter, reg); 3789 3790 for ( ; acts->mask; ++acts) { 3791 if (!(status & acts->mask)) 3792 continue; 3793 if (acts->fatal) { 3794 fatal++; 3795 CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, 3796 status & acts->mask); 3797 } else if (acts->msg) 3798 CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg, 3799 status & acts->mask); 3800 if (acts->int_handler) 3801 acts->int_handler(adapter); 3802 mask |= acts->mask; 3803 } 3804 status &= mask; 3805 if (status) /* clear processed interrupts */ 3806 t4_write_reg(adapter, reg, status); 3807 return fatal; 3808 } 3809 3810 /* 3811 * Interrupt handler for the PCIE module. 3812 */ 3813 static void pcie_intr_handler(struct adapter *adapter) 3814 { 3815 static const struct intr_info sysbus_intr_info[] = { 3816 { F_RNPP, "RXNP array parity error", -1, 1 }, 3817 { F_RPCP, "RXPC array parity error", -1, 1 }, 3818 { F_RCIP, "RXCIF array parity error", -1, 1 }, 3819 { F_RCCP, "Rx completions control array parity error", -1, 1 }, 3820 { F_RFTP, "RXFT array parity error", -1, 1 }, 3821 { 0 } 3822 }; 3823 static const struct intr_info pcie_port_intr_info[] = { 3824 { F_TPCP, "TXPC array parity error", -1, 1 }, 3825 { F_TNPP, "TXNP array parity error", -1, 1 }, 3826 { F_TFTP, "TXFT array parity error", -1, 1 }, 3827 { F_TCAP, "TXCA array parity error", -1, 1 }, 3828 { F_TCIP, "TXCIF array parity error", -1, 1 }, 3829 { F_RCAP, "RXCA array parity error", -1, 1 }, 3830 { F_OTDD, "outbound request TLP discarded", -1, 1 }, 3831 { F_RDPE, "Rx data parity error", -1, 1 }, 3832 { F_TDUE, "Tx uncorrectable data error", -1, 1 }, 3833 { 0 } 3834 }; 3835 static const struct intr_info pcie_intr_info[] = { 3836 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 3837 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 3838 { F_MSIDATAPERR, "MSI data parity error", -1, 1 }, 3839 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 3840 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 3841 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 3842 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 3843 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 3844 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 3845 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 3846 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 3847 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 3848 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 3849 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 3850 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 3851 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 3852 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 3853 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 3854 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 3855 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 3856 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 3857 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 3858 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 }, 3859 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 3860 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 3861 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 }, 3862 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 }, 3863 { F_PCIESINT, "PCI core secondary fault", -1, 1 }, 3864 { F_PCIEPINT, "PCI core primary fault", -1, 1 }, 3865 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1, 3866 0 }, 3867 { 0 } 3868 }; 3869 3870 static const struct intr_info t5_pcie_intr_info[] = { 3871 { F_MSTGRPPERR, "Master Response Read Queue parity error", 3872 -1, 1 }, 3873 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 3874 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 3875 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 3876 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 3877 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 3878 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 3879 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 3880 -1, 1 }, 3881 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 3882 -1, 1 }, 3883 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 3884 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 3885 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 3886 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 3887 { F_DREQWRPERR, "PCI DMA channel write request parity error", 3888 -1, 1 }, 3889 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 3890 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 3891 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 3892 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 3893 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 3894 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 3895 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 3896 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 3897 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 3898 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 3899 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 3900 -1, 1 }, 3901 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 3902 -1, 1 }, 3903 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 3904 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 3905 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 3906 { F_READRSPERR, "Outbound read error", -1, 3907 0 }, 3908 { 0 } 3909 }; 3910 3911 int fat; 3912 3913 if (is_t4(adapter)) 3914 fat = t4_handle_intr_status(adapter, 3915 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 3916 sysbus_intr_info) + 3917 t4_handle_intr_status(adapter, 3918 A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 3919 pcie_port_intr_info) + 3920 t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 3921 pcie_intr_info); 3922 else 3923 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 3924 t5_pcie_intr_info); 3925 if (fat) 3926 t4_fatal_err(adapter); 3927 } 3928 3929 /* 3930 * TP interrupt handler. 3931 */ 3932 static void tp_intr_handler(struct adapter *adapter) 3933 { 3934 static const struct intr_info tp_intr_info[] = { 3935 { 0x3fffffff, "TP parity error", -1, 1 }, 3936 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 3937 { 0 } 3938 }; 3939 3940 if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info)) 3941 t4_fatal_err(adapter); 3942 } 3943 3944 /* 3945 * SGE interrupt handler. 3946 */ 3947 static void sge_intr_handler(struct adapter *adapter) 3948 { 3949 u64 v; 3950 u32 err; 3951 3952 static const struct intr_info sge_intr_info[] = { 3953 { F_ERR_CPL_EXCEED_IQE_SIZE, 3954 "SGE received CPL exceeding IQE size", -1, 1 }, 3955 { F_ERR_INVALID_CIDX_INC, 3956 "SGE GTS CIDX increment too large", -1, 0 }, 3957 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 3958 { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, 3959 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 3960 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 3961 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 3962 0 }, 3963 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 3964 0 }, 3965 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 3966 0 }, 3967 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 3968 0 }, 3969 { F_ERR_ING_CTXT_PRIO, 3970 "SGE too many priority ingress contexts", -1, 0 }, 3971 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 3972 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 3973 { 0 } 3974 }; 3975 3976 static const struct intr_info t4t5_sge_intr_info[] = { 3977 { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, 3978 { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, 3979 { F_ERR_EGR_CTXT_PRIO, 3980 "SGE too many priority egress contexts", -1, 0 }, 3981 { 0 } 3982 }; 3983 3984 /* 3985 * For now, treat below interrupts as fatal so that we disable SGE and 3986 * get better debug */ 3987 static const struct intr_info t6_sge_intr_info[] = { 3988 { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1, 3989 "SGE PCIe error for a DBP thread", -1, 1 }, 3990 { F_FATAL_WRE_LEN, 3991 "SGE Actual WRE packet is less than advertized length", 3992 -1, 1 }, 3993 { 0 } 3994 }; 3995 3996 v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | 3997 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); 3998 if (v) { 3999 CH_ALERT(adapter, "SGE parity error (%#llx)\n", 4000 (unsigned long long)v); 4001 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); 4002 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); 4003 } 4004 4005 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info); 4006 if (chip_id(adapter) <= CHELSIO_T5) 4007 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4008 t4t5_sge_intr_info); 4009 else 4010 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4011 t6_sge_intr_info); 4012 4013 err = t4_read_reg(adapter, A_SGE_ERROR_STATS); 4014 if (err & F_ERROR_QID_VALID) { 4015 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err)); 4016 if (err & F_UNCAPTURED_ERROR) 4017 CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4018 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID | 4019 F_UNCAPTURED_ERROR); 4020 } 4021 4022 if (v != 0) 4023 t4_fatal_err(adapter); 4024 } 4025 4026 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\ 4027 F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR) 4028 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\ 4029 F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR) 4030 4031 /* 4032 * CIM interrupt handler. 4033 */ 4034 static void cim_intr_handler(struct adapter *adapter) 4035 { 4036 static const struct intr_info cim_intr_info[] = { 4037 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 4038 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 4039 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 4040 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 4041 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 4042 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 4043 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 4044 { 0 } 4045 }; 4046 static const struct intr_info cim_upintr_info[] = { 4047 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 4048 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 4049 { F_ILLWRINT, "CIM illegal write", -1, 1 }, 4050 { F_ILLRDINT, "CIM illegal read", -1, 1 }, 4051 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 4052 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 4053 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 4054 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 4055 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 4056 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 4057 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 4058 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 4059 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 4060 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 4061 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 4062 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 4063 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 4064 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 4065 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 4066 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 4067 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 4068 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 4069 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 4070 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 4071 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 4072 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 4073 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 4074 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 4075 { 0 } 4076 }; 4077 int fat; 4078 4079 if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR) 4080 t4_report_fw_error(adapter); 4081 4082 fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 4083 cim_intr_info) + 4084 t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE, 4085 cim_upintr_info); 4086 if (fat) 4087 t4_fatal_err(adapter); 4088 } 4089 4090 /* 4091 * ULP RX interrupt handler. 4092 */ 4093 static void ulprx_intr_handler(struct adapter *adapter) 4094 { 4095 static const struct intr_info ulprx_intr_info[] = { 4096 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 }, 4097 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 }, 4098 { 0x7fffff, "ULPRX parity error", -1, 1 }, 4099 { 0 } 4100 }; 4101 4102 if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info)) 4103 t4_fatal_err(adapter); 4104 } 4105 4106 /* 4107 * ULP TX interrupt handler. 4108 */ 4109 static void ulptx_intr_handler(struct adapter *adapter) 4110 { 4111 static const struct intr_info ulptx_intr_info[] = { 4112 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 4113 0 }, 4114 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 4115 0 }, 4116 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 4117 0 }, 4118 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 4119 0 }, 4120 { 0xfffffff, "ULPTX parity error", -1, 1 }, 4121 { 0 } 4122 }; 4123 4124 if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info)) 4125 t4_fatal_err(adapter); 4126 } 4127 4128 /* 4129 * PM TX interrupt handler. 4130 */ 4131 static void pmtx_intr_handler(struct adapter *adapter) 4132 { 4133 static const struct intr_info pmtx_intr_info[] = { 4134 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 4135 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 4136 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 4137 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 4138 { 0xffffff0, "PMTX framing error", -1, 1 }, 4139 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 4140 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 4141 1 }, 4142 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 4143 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 4144 { 0 } 4145 }; 4146 4147 if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info)) 4148 t4_fatal_err(adapter); 4149 } 4150 4151 /* 4152 * PM RX interrupt handler. 4153 */ 4154 static void pmrx_intr_handler(struct adapter *adapter) 4155 { 4156 static const struct intr_info pmrx_intr_info[] = { 4157 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 4158 { 0x3ffff0, "PMRX framing error", -1, 1 }, 4159 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 4160 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 4161 1 }, 4162 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 4163 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 4164 { 0 } 4165 }; 4166 4167 if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info)) 4168 t4_fatal_err(adapter); 4169 } 4170 4171 /* 4172 * CPL switch interrupt handler. 4173 */ 4174 static void cplsw_intr_handler(struct adapter *adapter) 4175 { 4176 static const struct intr_info cplsw_intr_info[] = { 4177 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 4178 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 4179 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 4180 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 4181 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 4182 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 4183 { 0 } 4184 }; 4185 4186 if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info)) 4187 t4_fatal_err(adapter); 4188 } 4189 4190 /* 4191 * LE interrupt handler. 4192 */ 4193 static void le_intr_handler(struct adapter *adap) 4194 { 4195 unsigned int chip_ver = chip_id(adap); 4196 static const struct intr_info le_intr_info[] = { 4197 { F_LIPMISS, "LE LIP miss", -1, 0 }, 4198 { F_LIP0, "LE 0 LIP error", -1, 0 }, 4199 { F_PARITYERR, "LE parity error", -1, 1 }, 4200 { F_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4201 { F_REQQPARERR, "LE request queue parity error", -1, 1 }, 4202 { 0 } 4203 }; 4204 4205 static const struct intr_info t6_le_intr_info[] = { 4206 { F_T6_LIPMISS, "LE LIP miss", -1, 0 }, 4207 { F_T6_LIP0, "LE 0 LIP error", -1, 0 }, 4208 { F_TCAMINTPERR, "LE parity error", -1, 1 }, 4209 { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4210 { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 }, 4211 { 0 } 4212 }; 4213 4214 if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, 4215 (chip_ver <= CHELSIO_T5) ? 4216 le_intr_info : t6_le_intr_info)) 4217 t4_fatal_err(adap); 4218 } 4219 4220 /* 4221 * MPS interrupt handler. 4222 */ 4223 static void mps_intr_handler(struct adapter *adapter) 4224 { 4225 static const struct intr_info mps_rx_intr_info[] = { 4226 { 0xffffff, "MPS Rx parity error", -1, 1 }, 4227 { 0 } 4228 }; 4229 static const struct intr_info mps_tx_intr_info[] = { 4230 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 }, 4231 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 4232 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error", 4233 -1, 1 }, 4234 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error", 4235 -1, 1 }, 4236 { F_BUBBLE, "MPS Tx underflow", -1, 1 }, 4237 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 4238 { F_FRMERR, "MPS Tx framing error", -1, 1 }, 4239 { 0 } 4240 }; 4241 static const struct intr_info mps_trc_intr_info[] = { 4242 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 }, 4243 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1, 4244 1 }, 4245 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 }, 4246 { 0 } 4247 }; 4248 static const struct intr_info mps_stat_sram_intr_info[] = { 4249 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 4250 { 0 } 4251 }; 4252 static const struct intr_info mps_stat_tx_intr_info[] = { 4253 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 4254 { 0 } 4255 }; 4256 static const struct intr_info mps_stat_rx_intr_info[] = { 4257 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 4258 { 0 } 4259 }; 4260 static const struct intr_info mps_cls_intr_info[] = { 4261 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 4262 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 4263 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 4264 { 0 } 4265 }; 4266 4267 int fat; 4268 4269 fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE, 4270 mps_rx_intr_info) + 4271 t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE, 4272 mps_tx_intr_info) + 4273 t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE, 4274 mps_trc_intr_info) + 4275 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4276 mps_stat_sram_intr_info) + 4277 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4278 mps_stat_tx_intr_info) + 4279 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4280 mps_stat_rx_intr_info) + 4281 t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE, 4282 mps_cls_intr_info); 4283 4284 t4_write_reg(adapter, A_MPS_INT_CAUSE, 0); 4285 t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ 4286 if (fat) 4287 t4_fatal_err(adapter); 4288 } 4289 4290 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \ 4291 F_ECC_UE_INT_CAUSE) 4292 4293 /* 4294 * EDC/MC interrupt handler. 4295 */ 4296 static void mem_intr_handler(struct adapter *adapter, int idx) 4297 { 4298 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; 4299 4300 unsigned int addr, cnt_addr, v; 4301 4302 if (idx <= MEM_EDC1) { 4303 addr = EDC_REG(A_EDC_INT_CAUSE, idx); 4304 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); 4305 } else if (idx == MEM_MC) { 4306 if (is_t4(adapter)) { 4307 addr = A_MC_INT_CAUSE; 4308 cnt_addr = A_MC_ECC_STATUS; 4309 } else { 4310 addr = A_MC_P_INT_CAUSE; 4311 cnt_addr = A_MC_P_ECC_STATUS; 4312 } 4313 } else { 4314 addr = MC_REG(A_MC_P_INT_CAUSE, 1); 4315 cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1); 4316 } 4317 4318 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 4319 if (v & F_PERR_INT_CAUSE) 4320 CH_ALERT(adapter, "%s FIFO parity error\n", 4321 name[idx]); 4322 if (v & F_ECC_CE_INT_CAUSE) { 4323 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); 4324 4325 t4_edc_err_read(adapter, idx); 4326 4327 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); 4328 CH_WARN_RATELIMIT(adapter, 4329 "%u %s correctable ECC data error%s\n", 4330 cnt, name[idx], cnt > 1 ? "s" : ""); 4331 } 4332 if (v & F_ECC_UE_INT_CAUSE) 4333 CH_ALERT(adapter, 4334 "%s uncorrectable ECC data error\n", name[idx]); 4335 4336 t4_write_reg(adapter, addr, v); 4337 if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE)) 4338 t4_fatal_err(adapter); 4339 } 4340 4341 /* 4342 * MA interrupt handler. 4343 */ 4344 static void ma_intr_handler(struct adapter *adapter) 4345 { 4346 u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); 4347 4348 if (status & F_MEM_PERR_INT_CAUSE) { 4349 CH_ALERT(adapter, 4350 "MA parity error, parity status %#x\n", 4351 t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); 4352 if (is_t5(adapter)) 4353 CH_ALERT(adapter, 4354 "MA parity error, parity status %#x\n", 4355 t4_read_reg(adapter, 4356 A_MA_PARITY_ERROR_STATUS2)); 4357 } 4358 if (status & F_MEM_WRAP_INT_CAUSE) { 4359 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); 4360 CH_ALERT(adapter, "MA address wrap-around error by " 4361 "client %u to address %#x\n", 4362 G_MEM_WRAP_CLIENT_NUM(v), 4363 G_MEM_WRAP_ADDRESS(v) << 4); 4364 } 4365 t4_write_reg(adapter, A_MA_INT_CAUSE, status); 4366 t4_fatal_err(adapter); 4367 } 4368 4369 /* 4370 * SMB interrupt handler. 4371 */ 4372 static void smb_intr_handler(struct adapter *adap) 4373 { 4374 static const struct intr_info smb_intr_info[] = { 4375 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 4376 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 4377 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 4378 { 0 } 4379 }; 4380 4381 if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info)) 4382 t4_fatal_err(adap); 4383 } 4384 4385 /* 4386 * NC-SI interrupt handler. 4387 */ 4388 static void ncsi_intr_handler(struct adapter *adap) 4389 { 4390 static const struct intr_info ncsi_intr_info[] = { 4391 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 4392 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 4393 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 4394 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 4395 { 0 } 4396 }; 4397 4398 if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info)) 4399 t4_fatal_err(adap); 4400 } 4401 4402 /* 4403 * XGMAC interrupt handler. 4404 */ 4405 static void xgmac_intr_handler(struct adapter *adap, int port) 4406 { 4407 u32 v, int_cause_reg; 4408 4409 if (is_t4(adap)) 4410 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 4411 else 4412 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 4413 4414 v = t4_read_reg(adap, int_cause_reg); 4415 4416 v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); 4417 if (!v) 4418 return; 4419 4420 if (v & F_TXFIFO_PRTY_ERR) 4421 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", 4422 port); 4423 if (v & F_RXFIFO_PRTY_ERR) 4424 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", 4425 port); 4426 t4_write_reg(adap, int_cause_reg, v); 4427 t4_fatal_err(adap); 4428 } 4429 4430 /* 4431 * PL interrupt handler. 4432 */ 4433 static void pl_intr_handler(struct adapter *adap) 4434 { 4435 static const struct intr_info pl_intr_info[] = { 4436 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4437 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 4438 { 0 } 4439 }; 4440 4441 static const struct intr_info t5_pl_intr_info[] = { 4442 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4443 { 0 } 4444 }; 4445 4446 if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, 4447 is_t4(adap) ? 4448 pl_intr_info : t5_pl_intr_info)) 4449 t4_fatal_err(adap); 4450 } 4451 4452 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 4453 4454 /** 4455 * t4_slow_intr_handler - control path interrupt handler 4456 * @adapter: the adapter 4457 * 4458 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 4459 * The designation 'slow' is because it involves register reads, while 4460 * data interrupts typically don't involve any MMIOs. 4461 */ 4462 int t4_slow_intr_handler(struct adapter *adapter) 4463 { 4464 u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE); 4465 4466 if (!(cause & GLBL_INTR_MASK)) 4467 return 0; 4468 if (cause & F_CIM) 4469 cim_intr_handler(adapter); 4470 if (cause & F_MPS) 4471 mps_intr_handler(adapter); 4472 if (cause & F_NCSI) 4473 ncsi_intr_handler(adapter); 4474 if (cause & F_PL) 4475 pl_intr_handler(adapter); 4476 if (cause & F_SMB) 4477 smb_intr_handler(adapter); 4478 if (cause & F_MAC0) 4479 xgmac_intr_handler(adapter, 0); 4480 if (cause & F_MAC1) 4481 xgmac_intr_handler(adapter, 1); 4482 if (cause & F_MAC2) 4483 xgmac_intr_handler(adapter, 2); 4484 if (cause & F_MAC3) 4485 xgmac_intr_handler(adapter, 3); 4486 if (cause & F_PCIE) 4487 pcie_intr_handler(adapter); 4488 if (cause & F_MC0) 4489 mem_intr_handler(adapter, MEM_MC); 4490 if (is_t5(adapter) && (cause & F_MC1)) 4491 mem_intr_handler(adapter, MEM_MC1); 4492 if (cause & F_EDC0) 4493 mem_intr_handler(adapter, MEM_EDC0); 4494 if (cause & F_EDC1) 4495 mem_intr_handler(adapter, MEM_EDC1); 4496 if (cause & F_LE) 4497 le_intr_handler(adapter); 4498 if (cause & F_TP) 4499 tp_intr_handler(adapter); 4500 if (cause & F_MA) 4501 ma_intr_handler(adapter); 4502 if (cause & F_PM_TX) 4503 pmtx_intr_handler(adapter); 4504 if (cause & F_PM_RX) 4505 pmrx_intr_handler(adapter); 4506 if (cause & F_ULP_RX) 4507 ulprx_intr_handler(adapter); 4508 if (cause & F_CPL_SWITCH) 4509 cplsw_intr_handler(adapter); 4510 if (cause & F_SGE) 4511 sge_intr_handler(adapter); 4512 if (cause & F_ULP_TX) 4513 ulptx_intr_handler(adapter); 4514 4515 /* Clear the interrupts just processed for which we are the master. */ 4516 t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK); 4517 (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4518 return 1; 4519 } 4520 4521 /** 4522 * t4_intr_enable - enable interrupts 4523 * @adapter: the adapter whose interrupts should be enabled 4524 * 4525 * Enable PF-specific interrupts for the calling function and the top-level 4526 * interrupt concentrator for global interrupts. Interrupts are already 4527 * enabled at each module, here we just enable the roots of the interrupt 4528 * hierarchies. 4529 * 4530 * Note: this function should be called only when the driver manages 4531 * non PF-specific interrupts from the various HW modules. Only one PCI 4532 * function at a time should be doing this. 4533 */ 4534 void t4_intr_enable(struct adapter *adapter) 4535 { 4536 u32 val = 0; 4537 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4538 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4539 ? G_SOURCEPF(whoami) 4540 : G_T6_SOURCEPF(whoami)); 4541 4542 if (chip_id(adapter) <= CHELSIO_T5) 4543 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 4544 else 4545 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 4546 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE | 4547 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 | 4548 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR | 4549 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 | 4550 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4551 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | 4552 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val); 4553 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 4554 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf); 4555 } 4556 4557 /** 4558 * t4_intr_disable - disable interrupts 4559 * @adapter: the adapter whose interrupts should be disabled 4560 * 4561 * Disable interrupts. We only disable the top-level interrupt 4562 * concentrators. The caller must be a PCI function managing global 4563 * interrupts. 4564 */ 4565 void t4_intr_disable(struct adapter *adapter) 4566 { 4567 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4568 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4569 ? G_SOURCEPF(whoami) 4570 : G_T6_SOURCEPF(whoami)); 4571 4572 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 4573 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0); 4574 } 4575 4576 /** 4577 * t4_intr_clear - clear all interrupts 4578 * @adapter: the adapter whose interrupts should be cleared 4579 * 4580 * Clears all interrupts. The caller must be a PCI function managing 4581 * global interrupts. 4582 */ 4583 void t4_intr_clear(struct adapter *adapter) 4584 { 4585 static const unsigned int cause_reg[] = { 4586 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3, 4587 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, 4588 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE, 4589 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), 4590 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, 4591 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4592 A_TP_INT_CAUSE, 4593 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE, 4594 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE, 4595 A_MPS_RX_PERR_INT_CAUSE, 4596 A_CPL_INTR_CAUSE, 4597 MYPF_REG(A_PL_PF_INT_CAUSE), 4598 A_PL_PL_INT_CAUSE, 4599 A_LE_DB_INT_CAUSE, 4600 }; 4601 4602 unsigned int i; 4603 4604 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) 4605 t4_write_reg(adapter, cause_reg[i], 0xffffffff); 4606 4607 t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : 4608 A_MC_P_INT_CAUSE, 0xffffffff); 4609 4610 if (is_t4(adapter)) { 4611 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4612 0xffffffff); 4613 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4614 0xffffffff); 4615 } else 4616 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 4617 4618 t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); 4619 (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4620 } 4621 4622 /** 4623 * hash_mac_addr - return the hash value of a MAC address 4624 * @addr: the 48-bit Ethernet MAC address 4625 * 4626 * Hashes a MAC address according to the hash function used by HW inexact 4627 * (hash) address matching. 4628 */ 4629 static int hash_mac_addr(const u8 *addr) 4630 { 4631 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 4632 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 4633 a ^= b; 4634 a ^= (a >> 12); 4635 a ^= (a >> 6); 4636 return a & 0x3f; 4637 } 4638 4639 /** 4640 * t4_config_rss_range - configure a portion of the RSS mapping table 4641 * @adapter: the adapter 4642 * @mbox: mbox to use for the FW command 4643 * @viid: virtual interface whose RSS subtable is to be written 4644 * @start: start entry in the table to write 4645 * @n: how many table entries to write 4646 * @rspq: values for the "response queue" (Ingress Queue) lookup table 4647 * @nrspq: number of values in @rspq 4648 * 4649 * Programs the selected part of the VI's RSS mapping table with the 4650 * provided values. If @nrspq < @n the supplied values are used repeatedly 4651 * until the full table range is populated. 4652 * 4653 * The caller must ensure the values in @rspq are in the range allowed for 4654 * @viid. 4655 */ 4656 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 4657 int start, int n, const u16 *rspq, unsigned int nrspq) 4658 { 4659 int ret; 4660 const u16 *rsp = rspq; 4661 const u16 *rsp_end = rspq + nrspq; 4662 struct fw_rss_ind_tbl_cmd cmd; 4663 4664 memset(&cmd, 0, sizeof(cmd)); 4665 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 4666 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4667 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 4668 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 4669 4670 /* 4671 * Each firmware RSS command can accommodate up to 32 RSS Ingress 4672 * Queue Identifiers. These Ingress Queue IDs are packed three to 4673 * a 32-bit word as 10-bit values with the upper remaining 2 bits 4674 * reserved. 4675 */ 4676 while (n > 0) { 4677 int nq = min(n, 32); 4678 int nq_packed = 0; 4679 __be32 *qp = &cmd.iq0_to_iq2; 4680 4681 /* 4682 * Set up the firmware RSS command header to send the next 4683 * "nq" Ingress Queue IDs to the firmware. 4684 */ 4685 cmd.niqid = cpu_to_be16(nq); 4686 cmd.startidx = cpu_to_be16(start); 4687 4688 /* 4689 * "nq" more done for the start of the next loop. 4690 */ 4691 start += nq; 4692 n -= nq; 4693 4694 /* 4695 * While there are still Ingress Queue IDs to stuff into the 4696 * current firmware RSS command, retrieve them from the 4697 * Ingress Queue ID array and insert them into the command. 4698 */ 4699 while (nq > 0) { 4700 /* 4701 * Grab up to the next 3 Ingress Queue IDs (wrapping 4702 * around the Ingress Queue ID array if necessary) and 4703 * insert them into the firmware RSS command at the 4704 * current 3-tuple position within the commad. 4705 */ 4706 u16 qbuf[3]; 4707 u16 *qbp = qbuf; 4708 int nqbuf = min(3, nq); 4709 4710 nq -= nqbuf; 4711 qbuf[0] = qbuf[1] = qbuf[2] = 0; 4712 while (nqbuf && nq_packed < 32) { 4713 nqbuf--; 4714 nq_packed++; 4715 *qbp++ = *rsp++; 4716 if (rsp >= rsp_end) 4717 rsp = rspq; 4718 } 4719 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 4720 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 4721 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 4722 } 4723 4724 /* 4725 * Send this portion of the RRS table update to the firmware; 4726 * bail out on any errors. 4727 */ 4728 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 4729 if (ret) 4730 return ret; 4731 } 4732 return 0; 4733 } 4734 4735 /** 4736 * t4_config_glbl_rss - configure the global RSS mode 4737 * @adapter: the adapter 4738 * @mbox: mbox to use for the FW command 4739 * @mode: global RSS mode 4740 * @flags: mode-specific flags 4741 * 4742 * Sets the global RSS mode. 4743 */ 4744 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 4745 unsigned int flags) 4746 { 4747 struct fw_rss_glb_config_cmd c; 4748 4749 memset(&c, 0, sizeof(c)); 4750 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 4751 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 4752 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4753 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 4754 c.u.manual.mode_pkd = 4755 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4756 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 4757 c.u.basicvirtual.mode_keymode = 4758 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4759 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 4760 } else 4761 return -EINVAL; 4762 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4763 } 4764 4765 /** 4766 * t4_config_vi_rss - configure per VI RSS settings 4767 * @adapter: the adapter 4768 * @mbox: mbox to use for the FW command 4769 * @viid: the VI id 4770 * @flags: RSS flags 4771 * @defq: id of the default RSS queue for the VI. 4772 * @skeyidx: RSS secret key table index for non-global mode 4773 * @skey: RSS vf_scramble key for VI. 4774 * 4775 * Configures VI-specific RSS properties. 4776 */ 4777 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 4778 unsigned int flags, unsigned int defq, unsigned int skeyidx, 4779 unsigned int skey) 4780 { 4781 struct fw_rss_vi_config_cmd c; 4782 4783 memset(&c, 0, sizeof(c)); 4784 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 4785 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4786 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 4787 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4788 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 4789 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 4790 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 4791 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 4792 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 4793 4794 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4795 } 4796 4797 /* Read an RSS table row */ 4798 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 4799 { 4800 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 4801 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 4802 5, 0, val); 4803 } 4804 4805 /** 4806 * t4_read_rss - read the contents of the RSS mapping table 4807 * @adapter: the adapter 4808 * @map: holds the contents of the RSS mapping table 4809 * 4810 * Reads the contents of the RSS hash->queue mapping table. 4811 */ 4812 int t4_read_rss(struct adapter *adapter, u16 *map) 4813 { 4814 u32 val; 4815 int i, ret; 4816 4817 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 4818 ret = rd_rss_row(adapter, i, &val); 4819 if (ret) 4820 return ret; 4821 *map++ = G_LKPTBLQUEUE0(val); 4822 *map++ = G_LKPTBLQUEUE1(val); 4823 } 4824 return 0; 4825 } 4826 4827 /** 4828 * t4_fw_tp_pio_rw - Access TP PIO through LDST 4829 * @adap: the adapter 4830 * @vals: where the indirect register values are stored/written 4831 * @nregs: how many indirect registers to read/write 4832 * @start_idx: index of first indirect register to read/write 4833 * @rw: Read (1) or Write (0) 4834 * 4835 * Access TP PIO registers through LDST 4836 */ 4837 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 4838 unsigned int start_index, unsigned int rw) 4839 { 4840 int ret, i; 4841 int cmd = FW_LDST_ADDRSPC_TP_PIO; 4842 struct fw_ldst_cmd c; 4843 4844 for (i = 0 ; i < nregs; i++) { 4845 memset(&c, 0, sizeof(c)); 4846 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 4847 F_FW_CMD_REQUEST | 4848 (rw ? F_FW_CMD_READ : 4849 F_FW_CMD_WRITE) | 4850 V_FW_LDST_CMD_ADDRSPACE(cmd)); 4851 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4852 4853 c.u.addrval.addr = cpu_to_be32(start_index + i); 4854 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 4855 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); 4856 if (ret == 0) { 4857 if (rw) 4858 vals[i] = be32_to_cpu(c.u.addrval.val); 4859 } 4860 } 4861 } 4862 4863 /** 4864 * t4_read_rss_key - read the global RSS key 4865 * @adap: the adapter 4866 * @key: 10-entry array holding the 320-bit RSS key 4867 * 4868 * Reads the global 320-bit RSS key. 4869 */ 4870 void t4_read_rss_key(struct adapter *adap, u32 *key) 4871 { 4872 if (t4_use_ldst(adap)) 4873 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1); 4874 else 4875 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10, 4876 A_TP_RSS_SECRET_KEY0); 4877 } 4878 4879 /** 4880 * t4_write_rss_key - program one of the RSS keys 4881 * @adap: the adapter 4882 * @key: 10-entry array holding the 320-bit RSS key 4883 * @idx: which RSS key to write 4884 * 4885 * Writes one of the RSS keys with the given 320-bit value. If @idx is 4886 * 0..15 the corresponding entry in the RSS key table is written, 4887 * otherwise the global RSS key is written. 4888 */ 4889 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx) 4890 { 4891 u8 rss_key_addr_cnt = 16; 4892 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 4893 4894 /* 4895 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 4896 * allows access to key addresses 16-63 by using KeyWrAddrX 4897 * as index[5:4](upper 2) into key table 4898 */ 4899 if ((chip_id(adap) > CHELSIO_T5) && 4900 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 4901 rss_key_addr_cnt = 32; 4902 4903 if (t4_use_ldst(adap)) 4904 t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0); 4905 else 4906 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10, 4907 A_TP_RSS_SECRET_KEY0); 4908 4909 if (idx >= 0 && idx < rss_key_addr_cnt) { 4910 if (rss_key_addr_cnt > 16) 4911 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 4912 vrt | V_KEYWRADDRX(idx >> 4) | 4913 V_T6_VFWRADDR(idx) | F_KEYWREN); 4914 else 4915 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 4916 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 4917 } 4918 } 4919 4920 /** 4921 * t4_read_rss_pf_config - read PF RSS Configuration Table 4922 * @adapter: the adapter 4923 * @index: the entry in the PF RSS table to read 4924 * @valp: where to store the returned value 4925 * 4926 * Reads the PF RSS Configuration Table at the specified index and returns 4927 * the value found there. 4928 */ 4929 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 4930 u32 *valp) 4931 { 4932 if (t4_use_ldst(adapter)) 4933 t4_fw_tp_pio_rw(adapter, valp, 1, 4934 A_TP_RSS_PF0_CONFIG + index, 1); 4935 else 4936 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 4937 valp, 1, A_TP_RSS_PF0_CONFIG + index); 4938 } 4939 4940 /** 4941 * t4_write_rss_pf_config - write PF RSS Configuration Table 4942 * @adapter: the adapter 4943 * @index: the entry in the VF RSS table to read 4944 * @val: the value to store 4945 * 4946 * Writes the PF RSS Configuration Table at the specified index with the 4947 * specified value. 4948 */ 4949 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 4950 u32 val) 4951 { 4952 if (t4_use_ldst(adapter)) 4953 t4_fw_tp_pio_rw(adapter, &val, 1, 4954 A_TP_RSS_PF0_CONFIG + index, 0); 4955 else 4956 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 4957 &val, 1, A_TP_RSS_PF0_CONFIG + index); 4958 } 4959 4960 /** 4961 * t4_read_rss_vf_config - read VF RSS Configuration Table 4962 * @adapter: the adapter 4963 * @index: the entry in the VF RSS table to read 4964 * @vfl: where to store the returned VFL 4965 * @vfh: where to store the returned VFH 4966 * 4967 * Reads the VF RSS Configuration Table at the specified index and returns 4968 * the (VFL, VFH) values found there. 4969 */ 4970 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 4971 u32 *vfl, u32 *vfh) 4972 { 4973 u32 vrt, mask, data; 4974 4975 if (chip_id(adapter) <= CHELSIO_T5) { 4976 mask = V_VFWRADDR(M_VFWRADDR); 4977 data = V_VFWRADDR(index); 4978 } else { 4979 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 4980 data = V_T6_VFWRADDR(index); 4981 } 4982 /* 4983 * Request that the index'th VF Table values be read into VFL/VFH. 4984 */ 4985 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 4986 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 4987 vrt |= data | F_VFRDEN; 4988 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 4989 4990 /* 4991 * Grab the VFL/VFH values ... 4992 */ 4993 if (t4_use_ldst(adapter)) { 4994 t4_fw_tp_pio_rw(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, 1); 4995 t4_fw_tp_pio_rw(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, 1); 4996 } else { 4997 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 4998 vfl, 1, A_TP_RSS_VFL_CONFIG); 4999 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5000 vfh, 1, A_TP_RSS_VFH_CONFIG); 5001 } 5002 } 5003 5004 /** 5005 * t4_write_rss_vf_config - write VF RSS Configuration Table 5006 * 5007 * @adapter: the adapter 5008 * @index: the entry in the VF RSS table to write 5009 * @vfl: the VFL to store 5010 * @vfh: the VFH to store 5011 * 5012 * Writes the VF RSS Configuration Table at the specified index with the 5013 * specified (VFL, VFH) values. 5014 */ 5015 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 5016 u32 vfl, u32 vfh) 5017 { 5018 u32 vrt, mask, data; 5019 5020 if (chip_id(adapter) <= CHELSIO_T5) { 5021 mask = V_VFWRADDR(M_VFWRADDR); 5022 data = V_VFWRADDR(index); 5023 } else { 5024 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5025 data = V_T6_VFWRADDR(index); 5026 } 5027 5028 /* 5029 * Load up VFL/VFH with the values to be written ... 5030 */ 5031 if (t4_use_ldst(adapter)) { 5032 t4_fw_tp_pio_rw(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, 0); 5033 t4_fw_tp_pio_rw(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, 0); 5034 } else { 5035 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5036 &vfl, 1, A_TP_RSS_VFL_CONFIG); 5037 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5038 &vfh, 1, A_TP_RSS_VFH_CONFIG); 5039 } 5040 5041 /* 5042 * Write the VFL/VFH into the VF Table at index'th location. 5043 */ 5044 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5045 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5046 vrt |= data | F_VFRDEN; 5047 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5048 } 5049 5050 /** 5051 * t4_read_rss_pf_map - read PF RSS Map 5052 * @adapter: the adapter 5053 * 5054 * Reads the PF RSS Map register and returns its value. 5055 */ 5056 u32 t4_read_rss_pf_map(struct adapter *adapter) 5057 { 5058 u32 pfmap; 5059 5060 if (t4_use_ldst(adapter)) 5061 t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 1); 5062 else 5063 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5064 &pfmap, 1, A_TP_RSS_PF_MAP); 5065 return pfmap; 5066 } 5067 5068 /** 5069 * t4_write_rss_pf_map - write PF RSS Map 5070 * @adapter: the adapter 5071 * @pfmap: PF RSS Map value 5072 * 5073 * Writes the specified value to the PF RSS Map register. 5074 */ 5075 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap) 5076 { 5077 if (t4_use_ldst(adapter)) 5078 t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 0); 5079 else 5080 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5081 &pfmap, 1, A_TP_RSS_PF_MAP); 5082 } 5083 5084 /** 5085 * t4_read_rss_pf_mask - read PF RSS Mask 5086 * @adapter: the adapter 5087 * 5088 * Reads the PF RSS Mask register and returns its value. 5089 */ 5090 u32 t4_read_rss_pf_mask(struct adapter *adapter) 5091 { 5092 u32 pfmask; 5093 5094 if (t4_use_ldst(adapter)) 5095 t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 1); 5096 else 5097 t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5098 &pfmask, 1, A_TP_RSS_PF_MSK); 5099 return pfmask; 5100 } 5101 5102 /** 5103 * t4_write_rss_pf_mask - write PF RSS Mask 5104 * @adapter: the adapter 5105 * @pfmask: PF RSS Mask value 5106 * 5107 * Writes the specified value to the PF RSS Mask register. 5108 */ 5109 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask) 5110 { 5111 if (t4_use_ldst(adapter)) 5112 t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 0); 5113 else 5114 t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5115 &pfmask, 1, A_TP_RSS_PF_MSK); 5116 } 5117 5118 /** 5119 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 5120 * @adap: the adapter 5121 * @v4: holds the TCP/IP counter values 5122 * @v6: holds the TCP/IPv6 counter values 5123 * 5124 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 5125 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 5126 */ 5127 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 5128 struct tp_tcp_stats *v6) 5129 { 5130 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 5131 5132 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 5133 #define STAT(x) val[STAT_IDX(x)] 5134 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 5135 5136 if (v4) { 5137 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 5138 ARRAY_SIZE(val), A_TP_MIB_TCP_OUT_RST); 5139 v4->tcp_out_rsts = STAT(OUT_RST); 5140 v4->tcp_in_segs = STAT64(IN_SEG); 5141 v4->tcp_out_segs = STAT64(OUT_SEG); 5142 v4->tcp_retrans_segs = STAT64(RXT_SEG); 5143 } 5144 if (v6) { 5145 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 5146 ARRAY_SIZE(val), A_TP_MIB_TCP_V6OUT_RST); 5147 v6->tcp_out_rsts = STAT(OUT_RST); 5148 v6->tcp_in_segs = STAT64(IN_SEG); 5149 v6->tcp_out_segs = STAT64(OUT_SEG); 5150 v6->tcp_retrans_segs = STAT64(RXT_SEG); 5151 } 5152 #undef STAT64 5153 #undef STAT 5154 #undef STAT_IDX 5155 } 5156 5157 /** 5158 * t4_tp_get_err_stats - read TP's error MIB counters 5159 * @adap: the adapter 5160 * @st: holds the counter values 5161 * 5162 * Returns the values of TP's error counters. 5163 */ 5164 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) 5165 { 5166 int nchan = adap->chip_params->nchan; 5167 5168 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5169 st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0); 5170 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5171 st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0); 5172 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5173 st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0); 5174 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5175 st->tnl_cong_drops, nchan, A_TP_MIB_TNL_CNG_DROP_0); 5176 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5177 st->ofld_chan_drops, nchan, A_TP_MIB_OFD_CHN_DROP_0); 5178 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5179 st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0); 5180 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5181 st->ofld_vlan_drops, nchan, A_TP_MIB_OFD_VLN_DROP_0); 5182 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5183 st->tcp6_in_errs, nchan, A_TP_MIB_TCP_V6IN_ERR_0); 5184 5185 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, 5186 &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP); 5187 } 5188 5189 /** 5190 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 5191 * @adap: the adapter 5192 * @st: holds the counter values 5193 * 5194 * Returns the values of TP's proxy counters. 5195 */ 5196 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st) 5197 { 5198 int nchan = adap->chip_params->nchan; 5199 5200 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->proxy, 5201 nchan, A_TP_MIB_TNL_LPBK_0); 5202 } 5203 5204 /** 5205 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 5206 * @adap: the adapter 5207 * @st: holds the counter values 5208 * 5209 * Returns the values of TP's CPL counters. 5210 */ 5211 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) 5212 { 5213 int nchan = adap->chip_params->nchan; 5214 5215 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req, 5216 nchan, A_TP_MIB_CPL_IN_REQ_0); 5217 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->rsp, 5218 nchan, A_TP_MIB_CPL_OUT_RSP_0); 5219 } 5220 5221 /** 5222 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 5223 * @adap: the adapter 5224 * @st: holds the counter values 5225 * 5226 * Returns the values of TP's RDMA counters. 5227 */ 5228 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st) 5229 { 5230 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->rqe_dfr_pkt, 5231 2, A_TP_MIB_RQE_DFR_PKT); 5232 } 5233 5234 /** 5235 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 5236 * @adap: the adapter 5237 * @idx: the port index 5238 * @st: holds the counter values 5239 * 5240 * Returns the values of TP's FCoE counters for the selected port. 5241 */ 5242 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 5243 struct tp_fcoe_stats *st) 5244 { 5245 u32 val[2]; 5246 5247 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_ddp, 5248 1, A_TP_MIB_FCOE_DDP_0 + idx); 5249 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_drop, 5250 1, A_TP_MIB_FCOE_DROP_0 + idx); 5251 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 5252 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx); 5253 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 5254 } 5255 5256 /** 5257 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 5258 * @adap: the adapter 5259 * @st: holds the counter values 5260 * 5261 * Returns the values of TP's counters for non-TCP directly-placed packets. 5262 */ 5263 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st) 5264 { 5265 u32 val[4]; 5266 5267 t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 4, 5268 A_TP_MIB_USM_PKTS); 5269 st->frames = val[0]; 5270 st->drops = val[1]; 5271 st->octets = ((u64)val[2] << 32) | val[3]; 5272 } 5273 5274 /** 5275 * t4_read_mtu_tbl - returns the values in the HW path MTU table 5276 * @adap: the adapter 5277 * @mtus: where to store the MTU values 5278 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 5279 * 5280 * Reads the HW path MTU table. 5281 */ 5282 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 5283 { 5284 u32 v; 5285 int i; 5286 5287 for (i = 0; i < NMTUS; ++i) { 5288 t4_write_reg(adap, A_TP_MTU_TABLE, 5289 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 5290 v = t4_read_reg(adap, A_TP_MTU_TABLE); 5291 mtus[i] = G_MTUVALUE(v); 5292 if (mtu_log) 5293 mtu_log[i] = G_MTUWIDTH(v); 5294 } 5295 } 5296 5297 /** 5298 * t4_read_cong_tbl - reads the congestion control table 5299 * @adap: the adapter 5300 * @incr: where to store the alpha values 5301 * 5302 * Reads the additive increments programmed into the HW congestion 5303 * control table. 5304 */ 5305 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 5306 { 5307 unsigned int mtu, w; 5308 5309 for (mtu = 0; mtu < NMTUS; ++mtu) 5310 for (w = 0; w < NCCTRL_WIN; ++w) { 5311 t4_write_reg(adap, A_TP_CCTRL_TABLE, 5312 V_ROWINDEX(0xffff) | (mtu << 5) | w); 5313 incr[mtu][w] = (u16)t4_read_reg(adap, 5314 A_TP_CCTRL_TABLE) & 0x1fff; 5315 } 5316 } 5317 5318 /** 5319 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 5320 * @adap: the adapter 5321 * @addr: the indirect TP register address 5322 * @mask: specifies the field within the register to modify 5323 * @val: new value for the field 5324 * 5325 * Sets a field of an indirect TP register to the given value. 5326 */ 5327 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 5328 unsigned int mask, unsigned int val) 5329 { 5330 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 5331 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 5332 t4_write_reg(adap, A_TP_PIO_DATA, val); 5333 } 5334 5335 /** 5336 * init_cong_ctrl - initialize congestion control parameters 5337 * @a: the alpha values for congestion control 5338 * @b: the beta values for congestion control 5339 * 5340 * Initialize the congestion control parameters. 5341 */ 5342 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 5343 { 5344 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 5345 a[9] = 2; 5346 a[10] = 3; 5347 a[11] = 4; 5348 a[12] = 5; 5349 a[13] = 6; 5350 a[14] = 7; 5351 a[15] = 8; 5352 a[16] = 9; 5353 a[17] = 10; 5354 a[18] = 14; 5355 a[19] = 17; 5356 a[20] = 21; 5357 a[21] = 25; 5358 a[22] = 30; 5359 a[23] = 35; 5360 a[24] = 45; 5361 a[25] = 60; 5362 a[26] = 80; 5363 a[27] = 100; 5364 a[28] = 200; 5365 a[29] = 300; 5366 a[30] = 400; 5367 a[31] = 500; 5368 5369 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 5370 b[9] = b[10] = 1; 5371 b[11] = b[12] = 2; 5372 b[13] = b[14] = b[15] = b[16] = 3; 5373 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 5374 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 5375 b[28] = b[29] = 6; 5376 b[30] = b[31] = 7; 5377 } 5378 5379 /* The minimum additive increment value for the congestion control table */ 5380 #define CC_MIN_INCR 2U 5381 5382 /** 5383 * t4_load_mtus - write the MTU and congestion control HW tables 5384 * @adap: the adapter 5385 * @mtus: the values for the MTU table 5386 * @alpha: the values for the congestion control alpha parameter 5387 * @beta: the values for the congestion control beta parameter 5388 * 5389 * Write the HW MTU table with the supplied MTUs and the high-speed 5390 * congestion control table with the supplied alpha, beta, and MTUs. 5391 * We write the two tables together because the additive increments 5392 * depend on the MTUs. 5393 */ 5394 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 5395 const unsigned short *alpha, const unsigned short *beta) 5396 { 5397 static const unsigned int avg_pkts[NCCTRL_WIN] = { 5398 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 5399 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 5400 28672, 40960, 57344, 81920, 114688, 163840, 229376 5401 }; 5402 5403 unsigned int i, w; 5404 5405 for (i = 0; i < NMTUS; ++i) { 5406 unsigned int mtu = mtus[i]; 5407 unsigned int log2 = fls(mtu); 5408 5409 if (!(mtu & ((1 << log2) >> 2))) /* round */ 5410 log2--; 5411 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 5412 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 5413 5414 for (w = 0; w < NCCTRL_WIN; ++w) { 5415 unsigned int inc; 5416 5417 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 5418 CC_MIN_INCR); 5419 5420 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 5421 (w << 16) | (beta[w] << 13) | inc); 5422 } 5423 } 5424 } 5425 5426 /** 5427 * t4_set_pace_tbl - set the pace table 5428 * @adap: the adapter 5429 * @pace_vals: the pace values in microseconds 5430 * @start: index of the first entry in the HW pace table to set 5431 * @n: how many entries to set 5432 * 5433 * Sets (a subset of the) HW pace table. 5434 */ 5435 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 5436 unsigned int start, unsigned int n) 5437 { 5438 unsigned int vals[NTX_SCHED], i; 5439 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 5440 5441 if (n > NTX_SCHED) 5442 return -ERANGE; 5443 5444 /* convert values from us to dack ticks, rounding to closest value */ 5445 for (i = 0; i < n; i++, pace_vals++) { 5446 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 5447 if (vals[i] > 0x7ff) 5448 return -ERANGE; 5449 if (*pace_vals && vals[i] == 0) 5450 return -ERANGE; 5451 } 5452 for (i = 0; i < n; i++, start++) 5453 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 5454 return 0; 5455 } 5456 5457 /** 5458 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 5459 * @adap: the adapter 5460 * @kbps: target rate in Kbps 5461 * @sched: the scheduler index 5462 * 5463 * Configure a Tx HW scheduler for the target rate. 5464 */ 5465 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 5466 { 5467 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 5468 unsigned int clk = adap->params.vpd.cclk * 1000; 5469 unsigned int selected_cpt = 0, selected_bpt = 0; 5470 5471 if (kbps > 0) { 5472 kbps *= 125; /* -> bytes */ 5473 for (cpt = 1; cpt <= 255; cpt++) { 5474 tps = clk / cpt; 5475 bpt = (kbps + tps / 2) / tps; 5476 if (bpt > 0 && bpt <= 255) { 5477 v = bpt * tps; 5478 delta = v >= kbps ? v - kbps : kbps - v; 5479 if (delta < mindelta) { 5480 mindelta = delta; 5481 selected_cpt = cpt; 5482 selected_bpt = bpt; 5483 } 5484 } else if (selected_cpt) 5485 break; 5486 } 5487 if (!selected_cpt) 5488 return -EINVAL; 5489 } 5490 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 5491 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 5492 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5493 if (sched & 1) 5494 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 5495 else 5496 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 5497 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5498 return 0; 5499 } 5500 5501 /** 5502 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 5503 * @adap: the adapter 5504 * @sched: the scheduler index 5505 * @ipg: the interpacket delay in tenths of nanoseconds 5506 * 5507 * Set the interpacket delay for a HW packet rate scheduler. 5508 */ 5509 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 5510 { 5511 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 5512 5513 /* convert ipg to nearest number of core clocks */ 5514 ipg *= core_ticks_per_usec(adap); 5515 ipg = (ipg + 5000) / 10000; 5516 if (ipg > M_TXTIMERSEPQ0) 5517 return -EINVAL; 5518 5519 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 5520 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5521 if (sched & 1) 5522 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 5523 else 5524 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 5525 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5526 t4_read_reg(adap, A_TP_TM_PIO_DATA); 5527 return 0; 5528 } 5529 5530 /* 5531 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 5532 * clocks. The formula is 5533 * 5534 * bytes/s = bytes256 * 256 * ClkFreq / 4096 5535 * 5536 * which is equivalent to 5537 * 5538 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 5539 */ 5540 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 5541 { 5542 u64 v = bytes256 * adap->params.vpd.cclk; 5543 5544 return v * 62 + v / 2; 5545 } 5546 5547 /** 5548 * t4_get_chan_txrate - get the current per channel Tx rates 5549 * @adap: the adapter 5550 * @nic_rate: rates for NIC traffic 5551 * @ofld_rate: rates for offloaded traffic 5552 * 5553 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 5554 * for each channel. 5555 */ 5556 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 5557 { 5558 u32 v; 5559 5560 v = t4_read_reg(adap, A_TP_TX_TRATE); 5561 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 5562 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 5563 if (adap->chip_params->nchan > 2) { 5564 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 5565 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 5566 } 5567 5568 v = t4_read_reg(adap, A_TP_TX_ORATE); 5569 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 5570 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 5571 if (adap->chip_params->nchan > 2) { 5572 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 5573 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 5574 } 5575 } 5576 5577 /** 5578 * t4_set_trace_filter - configure one of the tracing filters 5579 * @adap: the adapter 5580 * @tp: the desired trace filter parameters 5581 * @idx: which filter to configure 5582 * @enable: whether to enable or disable the filter 5583 * 5584 * Configures one of the tracing filters available in HW. If @tp is %NULL 5585 * it indicates that the filter is already written in the register and it 5586 * just needs to be enabled or disabled. 5587 */ 5588 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 5589 int idx, int enable) 5590 { 5591 int i, ofst = idx * 4; 5592 u32 data_reg, mask_reg, cfg; 5593 u32 multitrc = F_TRCMULTIFILTER; 5594 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 5595 5596 if (idx < 0 || idx >= NTRACE) 5597 return -EINVAL; 5598 5599 if (tp == NULL || !enable) { 5600 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 5601 enable ? en : 0); 5602 return 0; 5603 } 5604 5605 /* 5606 * TODO - After T4 data book is updated, specify the exact 5607 * section below. 5608 * 5609 * See T4 data book - MPS section for a complete description 5610 * of the below if..else handling of A_MPS_TRC_CFG register 5611 * value. 5612 */ 5613 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 5614 if (cfg & F_TRCMULTIFILTER) { 5615 /* 5616 * If multiple tracers are enabled, then maximum 5617 * capture size is 2.5KB (FIFO size of a single channel) 5618 * minus 2 flits for CPL_TRACE_PKT header. 5619 */ 5620 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 5621 return -EINVAL; 5622 } else { 5623 /* 5624 * If multiple tracers are disabled, to avoid deadlocks 5625 * maximum packet capture size of 9600 bytes is recommended. 5626 * Also in this mode, only trace0 can be enabled and running. 5627 */ 5628 multitrc = 0; 5629 if (tp->snap_len > 9600 || idx) 5630 return -EINVAL; 5631 } 5632 5633 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 5634 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 5635 tp->min_len > M_TFMINPKTSIZE) 5636 return -EINVAL; 5637 5638 /* stop the tracer we'll be changing */ 5639 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 5640 5641 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 5642 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 5643 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 5644 5645 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5646 t4_write_reg(adap, data_reg, tp->data[i]); 5647 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 5648 } 5649 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 5650 V_TFCAPTUREMAX(tp->snap_len) | 5651 V_TFMINPKTSIZE(tp->min_len)); 5652 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 5653 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 5654 (is_t4(adap) ? 5655 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 5656 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 5657 5658 return 0; 5659 } 5660 5661 /** 5662 * t4_get_trace_filter - query one of the tracing filters 5663 * @adap: the adapter 5664 * @tp: the current trace filter parameters 5665 * @idx: which trace filter to query 5666 * @enabled: non-zero if the filter is enabled 5667 * 5668 * Returns the current settings of one of the HW tracing filters. 5669 */ 5670 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 5671 int *enabled) 5672 { 5673 u32 ctla, ctlb; 5674 int i, ofst = idx * 4; 5675 u32 data_reg, mask_reg; 5676 5677 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 5678 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 5679 5680 if (is_t4(adap)) { 5681 *enabled = !!(ctla & F_TFEN); 5682 tp->port = G_TFPORT(ctla); 5683 tp->invert = !!(ctla & F_TFINVERTMATCH); 5684 } else { 5685 *enabled = !!(ctla & F_T5_TFEN); 5686 tp->port = G_T5_TFPORT(ctla); 5687 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 5688 } 5689 tp->snap_len = G_TFCAPTUREMAX(ctlb); 5690 tp->min_len = G_TFMINPKTSIZE(ctlb); 5691 tp->skip_ofst = G_TFOFFSET(ctla); 5692 tp->skip_len = G_TFLENGTH(ctla); 5693 5694 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 5695 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 5696 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 5697 5698 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5699 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 5700 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 5701 } 5702 } 5703 5704 /** 5705 * t4_pmtx_get_stats - returns the HW stats from PMTX 5706 * @adap: the adapter 5707 * @cnt: where to store the count statistics 5708 * @cycles: where to store the cycle statistics 5709 * 5710 * Returns performance statistics from PMTX. 5711 */ 5712 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 5713 { 5714 int i; 5715 u32 data[2]; 5716 5717 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 5718 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 5719 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 5720 if (is_t4(adap)) 5721 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 5722 else { 5723 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 5724 A_PM_TX_DBG_DATA, data, 2, 5725 A_PM_TX_DBG_STAT_MSB); 5726 cycles[i] = (((u64)data[0] << 32) | data[1]); 5727 } 5728 } 5729 } 5730 5731 /** 5732 * t4_pmrx_get_stats - returns the HW stats from PMRX 5733 * @adap: the adapter 5734 * @cnt: where to store the count statistics 5735 * @cycles: where to store the cycle statistics 5736 * 5737 * Returns performance statistics from PMRX. 5738 */ 5739 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 5740 { 5741 int i; 5742 u32 data[2]; 5743 5744 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 5745 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 5746 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 5747 if (is_t4(adap)) { 5748 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 5749 } else { 5750 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 5751 A_PM_RX_DBG_DATA, data, 2, 5752 A_PM_RX_DBG_STAT_MSB); 5753 cycles[i] = (((u64)data[0] << 32) | data[1]); 5754 } 5755 } 5756 } 5757 5758 /** 5759 * t4_get_mps_bg_map - return the buffer groups associated with a port 5760 * @adap: the adapter 5761 * @idx: the port index 5762 * 5763 * Returns a bitmap indicating which MPS buffer groups are associated 5764 * with the given port. Bit i is set if buffer group i is used by the 5765 * port. 5766 */ 5767 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 5768 { 5769 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 5770 5771 if (n == 0) 5772 return idx == 0 ? 0xf : 0; 5773 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 5774 return idx < 2 ? (3 << (2 * idx)) : 0; 5775 return 1 << idx; 5776 } 5777 5778 /** 5779 * t4_get_port_type_description - return Port Type string description 5780 * @port_type: firmware Port Type enumeration 5781 */ 5782 const char *t4_get_port_type_description(enum fw_port_type port_type) 5783 { 5784 static const char *const port_type_description[] = { 5785 "Fiber_XFI", 5786 "Fiber_XAUI", 5787 "BT_SGMII", 5788 "BT_XFI", 5789 "BT_XAUI", 5790 "KX4", 5791 "CX4", 5792 "KX", 5793 "KR", 5794 "SFP", 5795 "BP_AP", 5796 "BP4_AP", 5797 "QSFP_10G", 5798 "QSA", 5799 "QSFP", 5800 "BP40_BA", 5801 "KR4_100G", 5802 "CR4_QSFP", 5803 "CR_QSFP", 5804 "CR_SFP28", 5805 "SFP28", 5806 "KR_SFP28", 5807 "CR2_QSFP", 5808 }; 5809 5810 if (port_type < ARRAY_SIZE(port_type_description)) 5811 return port_type_description[port_type]; 5812 return "UNKNOWN"; 5813 } 5814 5815 /** 5816 * t4_get_port_stats_offset - collect port stats relative to a previous 5817 * snapshot 5818 * @adap: The adapter 5819 * @idx: The port 5820 * @stats: Current stats to fill 5821 * @offset: Previous stats snapshot 5822 */ 5823 void t4_get_port_stats_offset(struct adapter *adap, int idx, 5824 struct port_stats *stats, 5825 struct port_stats *offset) 5826 { 5827 u64 *s, *o; 5828 int i; 5829 5830 t4_get_port_stats(adap, idx, stats); 5831 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 5832 i < (sizeof(struct port_stats)/sizeof(u64)) ; 5833 i++, s++, o++) 5834 *s -= *o; 5835 } 5836 5837 /** 5838 * t4_get_port_stats - collect port statistics 5839 * @adap: the adapter 5840 * @idx: the port index 5841 * @p: the stats structure to fill 5842 * 5843 * Collect statistics related to the given port from HW. 5844 */ 5845 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 5846 { 5847 u32 bgmap = t4_get_mps_bg_map(adap, idx); 5848 u32 stat_ctl; 5849 5850 #define GET_STAT(name) \ 5851 t4_read_reg64(adap, \ 5852 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 5853 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 5854 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 5855 5856 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 5857 5858 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 5859 p->tx_octets = GET_STAT(TX_PORT_BYTES); 5860 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 5861 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 5862 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 5863 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 5864 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 5865 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 5866 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 5867 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 5868 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 5869 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 5870 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 5871 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 5872 p->tx_drop = GET_STAT(TX_PORT_DROP); 5873 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 5874 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 5875 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 5876 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 5877 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 5878 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 5879 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 5880 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 5881 5882 if (chip_id(adap) >= CHELSIO_T5) { 5883 if (stat_ctl & F_COUNTPAUSESTATTX) { 5884 p->tx_frames -= p->tx_pause; 5885 p->tx_octets -= p->tx_pause * 64; 5886 } 5887 if (stat_ctl & F_COUNTPAUSEMCTX) 5888 p->tx_mcast_frames -= p->tx_pause; 5889 } 5890 5891 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 5892 p->rx_octets = GET_STAT(RX_PORT_BYTES); 5893 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 5894 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 5895 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 5896 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 5897 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 5898 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 5899 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 5900 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 5901 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 5902 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 5903 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 5904 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 5905 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 5906 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 5907 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 5908 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 5909 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 5910 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 5911 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 5912 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 5913 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 5914 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 5915 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 5916 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 5917 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 5918 5919 if (chip_id(adap) >= CHELSIO_T5) { 5920 if (stat_ctl & F_COUNTPAUSESTATRX) { 5921 p->rx_frames -= p->rx_pause; 5922 p->rx_octets -= p->rx_pause * 64; 5923 } 5924 if (stat_ctl & F_COUNTPAUSEMCRX) 5925 p->rx_mcast_frames -= p->rx_pause; 5926 } 5927 5928 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 5929 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 5930 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 5931 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 5932 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 5933 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 5934 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 5935 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 5936 5937 #undef GET_STAT 5938 #undef GET_STAT_COM 5939 } 5940 5941 /** 5942 * t4_get_lb_stats - collect loopback port statistics 5943 * @adap: the adapter 5944 * @idx: the loopback port index 5945 * @p: the stats structure to fill 5946 * 5947 * Return HW statistics for the given loopback port. 5948 */ 5949 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 5950 { 5951 u32 bgmap = t4_get_mps_bg_map(adap, idx); 5952 5953 #define GET_STAT(name) \ 5954 t4_read_reg64(adap, \ 5955 (is_t4(adap) ? \ 5956 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 5957 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 5958 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 5959 5960 p->octets = GET_STAT(BYTES); 5961 p->frames = GET_STAT(FRAMES); 5962 p->bcast_frames = GET_STAT(BCAST); 5963 p->mcast_frames = GET_STAT(MCAST); 5964 p->ucast_frames = GET_STAT(UCAST); 5965 p->error_frames = GET_STAT(ERROR); 5966 5967 p->frames_64 = GET_STAT(64B); 5968 p->frames_65_127 = GET_STAT(65B_127B); 5969 p->frames_128_255 = GET_STAT(128B_255B); 5970 p->frames_256_511 = GET_STAT(256B_511B); 5971 p->frames_512_1023 = GET_STAT(512B_1023B); 5972 p->frames_1024_1518 = GET_STAT(1024B_1518B); 5973 p->frames_1519_max = GET_STAT(1519B_MAX); 5974 p->drop = GET_STAT(DROP_FRAMES); 5975 5976 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 5977 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 5978 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 5979 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 5980 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 5981 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 5982 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 5983 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 5984 5985 #undef GET_STAT 5986 #undef GET_STAT_COM 5987 } 5988 5989 /** 5990 * t4_wol_magic_enable - enable/disable magic packet WoL 5991 * @adap: the adapter 5992 * @port: the physical port index 5993 * @addr: MAC address expected in magic packets, %NULL to disable 5994 * 5995 * Enables/disables magic packet wake-on-LAN for the selected port. 5996 */ 5997 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 5998 const u8 *addr) 5999 { 6000 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 6001 6002 if (is_t4(adap)) { 6003 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 6004 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 6005 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6006 } else { 6007 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 6008 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 6009 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6010 } 6011 6012 if (addr) { 6013 t4_write_reg(adap, mag_id_reg_l, 6014 (addr[2] << 24) | (addr[3] << 16) | 6015 (addr[4] << 8) | addr[5]); 6016 t4_write_reg(adap, mag_id_reg_h, 6017 (addr[0] << 8) | addr[1]); 6018 } 6019 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 6020 V_MAGICEN(addr != NULL)); 6021 } 6022 6023 /** 6024 * t4_wol_pat_enable - enable/disable pattern-based WoL 6025 * @adap: the adapter 6026 * @port: the physical port index 6027 * @map: bitmap of which HW pattern filters to set 6028 * @mask0: byte mask for bytes 0-63 of a packet 6029 * @mask1: byte mask for bytes 64-127 of a packet 6030 * @crc: Ethernet CRC for selected bytes 6031 * @enable: enable/disable switch 6032 * 6033 * Sets the pattern filters indicated in @map to mask out the bytes 6034 * specified in @mask0/@mask1 in received packets and compare the CRC of 6035 * the resulting packet against @crc. If @enable is %true pattern-based 6036 * WoL is enabled, otherwise disabled. 6037 */ 6038 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 6039 u64 mask0, u64 mask1, unsigned int crc, bool enable) 6040 { 6041 int i; 6042 u32 port_cfg_reg; 6043 6044 if (is_t4(adap)) 6045 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6046 else 6047 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6048 6049 if (!enable) { 6050 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 6051 return 0; 6052 } 6053 if (map > 0xff) 6054 return -EINVAL; 6055 6056 #define EPIO_REG(name) \ 6057 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 6058 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 6059 6060 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 6061 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 6062 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 6063 6064 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 6065 if (!(map & 1)) 6066 continue; 6067 6068 /* write byte masks */ 6069 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 6070 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 6071 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6072 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6073 return -ETIMEDOUT; 6074 6075 /* write CRC */ 6076 t4_write_reg(adap, EPIO_REG(DATA0), crc); 6077 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 6078 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6079 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6080 return -ETIMEDOUT; 6081 } 6082 #undef EPIO_REG 6083 6084 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 6085 return 0; 6086 } 6087 6088 /* t4_mk_filtdelwr - create a delete filter WR 6089 * @ftid: the filter ID 6090 * @wr: the filter work request to populate 6091 * @qid: ingress queue to receive the delete notification 6092 * 6093 * Creates a filter work request to delete the supplied filter. If @qid is 6094 * negative the delete notification is suppressed. 6095 */ 6096 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 6097 { 6098 memset(wr, 0, sizeof(*wr)); 6099 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 6100 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 6101 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 6102 V_FW_FILTER_WR_NOREPLY(qid < 0)); 6103 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 6104 if (qid >= 0) 6105 wr->rx_chan_rx_rpl_iq = 6106 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 6107 } 6108 6109 #define INIT_CMD(var, cmd, rd_wr) do { \ 6110 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 6111 F_FW_CMD_REQUEST | \ 6112 F_FW_CMD_##rd_wr); \ 6113 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 6114 } while (0) 6115 6116 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 6117 u32 addr, u32 val) 6118 { 6119 u32 ldst_addrspace; 6120 struct fw_ldst_cmd c; 6121 6122 memset(&c, 0, sizeof(c)); 6123 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 6124 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6125 F_FW_CMD_REQUEST | 6126 F_FW_CMD_WRITE | 6127 ldst_addrspace); 6128 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6129 c.u.addrval.addr = cpu_to_be32(addr); 6130 c.u.addrval.val = cpu_to_be32(val); 6131 6132 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6133 } 6134 6135 /** 6136 * t4_mdio_rd - read a PHY register through MDIO 6137 * @adap: the adapter 6138 * @mbox: mailbox to use for the FW command 6139 * @phy_addr: the PHY address 6140 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6141 * @reg: the register to read 6142 * @valp: where to store the value 6143 * 6144 * Issues a FW command through the given mailbox to read a PHY register. 6145 */ 6146 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6147 unsigned int mmd, unsigned int reg, unsigned int *valp) 6148 { 6149 int ret; 6150 u32 ldst_addrspace; 6151 struct fw_ldst_cmd c; 6152 6153 memset(&c, 0, sizeof(c)); 6154 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6155 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6156 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6157 ldst_addrspace); 6158 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6159 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6160 V_FW_LDST_CMD_MMD(mmd)); 6161 c.u.mdio.raddr = cpu_to_be16(reg); 6162 6163 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6164 if (ret == 0) 6165 *valp = be16_to_cpu(c.u.mdio.rval); 6166 return ret; 6167 } 6168 6169 /** 6170 * t4_mdio_wr - write a PHY register through MDIO 6171 * @adap: the adapter 6172 * @mbox: mailbox to use for the FW command 6173 * @phy_addr: the PHY address 6174 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6175 * @reg: the register to write 6176 * @valp: value to write 6177 * 6178 * Issues a FW command through the given mailbox to write a PHY register. 6179 */ 6180 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6181 unsigned int mmd, unsigned int reg, unsigned int val) 6182 { 6183 u32 ldst_addrspace; 6184 struct fw_ldst_cmd c; 6185 6186 memset(&c, 0, sizeof(c)); 6187 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6188 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6189 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 6190 ldst_addrspace); 6191 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6192 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6193 V_FW_LDST_CMD_MMD(mmd)); 6194 c.u.mdio.raddr = cpu_to_be16(reg); 6195 c.u.mdio.rval = cpu_to_be16(val); 6196 6197 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6198 } 6199 6200 /** 6201 * 6202 * t4_sge_decode_idma_state - decode the idma state 6203 * @adap: the adapter 6204 * @state: the state idma is stuck in 6205 */ 6206 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 6207 { 6208 static const char * const t4_decode[] = { 6209 "IDMA_IDLE", 6210 "IDMA_PUSH_MORE_CPL_FIFO", 6211 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6212 "Not used", 6213 "IDMA_PHYSADDR_SEND_PCIEHDR", 6214 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6215 "IDMA_PHYSADDR_SEND_PAYLOAD", 6216 "IDMA_SEND_FIFO_TO_IMSG", 6217 "IDMA_FL_REQ_DATA_FL_PREP", 6218 "IDMA_FL_REQ_DATA_FL", 6219 "IDMA_FL_DROP", 6220 "IDMA_FL_H_REQ_HEADER_FL", 6221 "IDMA_FL_H_SEND_PCIEHDR", 6222 "IDMA_FL_H_PUSH_CPL_FIFO", 6223 "IDMA_FL_H_SEND_CPL", 6224 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6225 "IDMA_FL_H_SEND_IP_HDR", 6226 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6227 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6228 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6229 "IDMA_FL_D_SEND_PCIEHDR", 6230 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6231 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6232 "IDMA_FL_SEND_PCIEHDR", 6233 "IDMA_FL_PUSH_CPL_FIFO", 6234 "IDMA_FL_SEND_CPL", 6235 "IDMA_FL_SEND_PAYLOAD_FIRST", 6236 "IDMA_FL_SEND_PAYLOAD", 6237 "IDMA_FL_REQ_NEXT_DATA_FL", 6238 "IDMA_FL_SEND_NEXT_PCIEHDR", 6239 "IDMA_FL_SEND_PADDING", 6240 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6241 "IDMA_FL_SEND_FIFO_TO_IMSG", 6242 "IDMA_FL_REQ_DATAFL_DONE", 6243 "IDMA_FL_REQ_HEADERFL_DONE", 6244 }; 6245 static const char * const t5_decode[] = { 6246 "IDMA_IDLE", 6247 "IDMA_ALMOST_IDLE", 6248 "IDMA_PUSH_MORE_CPL_FIFO", 6249 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6250 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6251 "IDMA_PHYSADDR_SEND_PCIEHDR", 6252 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6253 "IDMA_PHYSADDR_SEND_PAYLOAD", 6254 "IDMA_SEND_FIFO_TO_IMSG", 6255 "IDMA_FL_REQ_DATA_FL", 6256 "IDMA_FL_DROP", 6257 "IDMA_FL_DROP_SEND_INC", 6258 "IDMA_FL_H_REQ_HEADER_FL", 6259 "IDMA_FL_H_SEND_PCIEHDR", 6260 "IDMA_FL_H_PUSH_CPL_FIFO", 6261 "IDMA_FL_H_SEND_CPL", 6262 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6263 "IDMA_FL_H_SEND_IP_HDR", 6264 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6265 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6266 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6267 "IDMA_FL_D_SEND_PCIEHDR", 6268 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6269 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6270 "IDMA_FL_SEND_PCIEHDR", 6271 "IDMA_FL_PUSH_CPL_FIFO", 6272 "IDMA_FL_SEND_CPL", 6273 "IDMA_FL_SEND_PAYLOAD_FIRST", 6274 "IDMA_FL_SEND_PAYLOAD", 6275 "IDMA_FL_REQ_NEXT_DATA_FL", 6276 "IDMA_FL_SEND_NEXT_PCIEHDR", 6277 "IDMA_FL_SEND_PADDING", 6278 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6279 }; 6280 static const char * const t6_decode[] = { 6281 "IDMA_IDLE", 6282 "IDMA_PUSH_MORE_CPL_FIFO", 6283 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6284 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6285 "IDMA_PHYSADDR_SEND_PCIEHDR", 6286 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6287 "IDMA_PHYSADDR_SEND_PAYLOAD", 6288 "IDMA_FL_REQ_DATA_FL", 6289 "IDMA_FL_DROP", 6290 "IDMA_FL_DROP_SEND_INC", 6291 "IDMA_FL_H_REQ_HEADER_FL", 6292 "IDMA_FL_H_SEND_PCIEHDR", 6293 "IDMA_FL_H_PUSH_CPL_FIFO", 6294 "IDMA_FL_H_SEND_CPL", 6295 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6296 "IDMA_FL_H_SEND_IP_HDR", 6297 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6298 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6299 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6300 "IDMA_FL_D_SEND_PCIEHDR", 6301 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6302 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6303 "IDMA_FL_SEND_PCIEHDR", 6304 "IDMA_FL_PUSH_CPL_FIFO", 6305 "IDMA_FL_SEND_CPL", 6306 "IDMA_FL_SEND_PAYLOAD_FIRST", 6307 "IDMA_FL_SEND_PAYLOAD", 6308 "IDMA_FL_REQ_NEXT_DATA_FL", 6309 "IDMA_FL_SEND_NEXT_PCIEHDR", 6310 "IDMA_FL_SEND_PADDING", 6311 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6312 }; 6313 static const u32 sge_regs[] = { 6314 A_SGE_DEBUG_DATA_LOW_INDEX_2, 6315 A_SGE_DEBUG_DATA_LOW_INDEX_3, 6316 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 6317 }; 6318 const char * const *sge_idma_decode; 6319 int sge_idma_decode_nstates; 6320 int i; 6321 unsigned int chip_version = chip_id(adapter); 6322 6323 /* Select the right set of decode strings to dump depending on the 6324 * adapter chip type. 6325 */ 6326 switch (chip_version) { 6327 case CHELSIO_T4: 6328 sge_idma_decode = (const char * const *)t4_decode; 6329 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 6330 break; 6331 6332 case CHELSIO_T5: 6333 sge_idma_decode = (const char * const *)t5_decode; 6334 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 6335 break; 6336 6337 case CHELSIO_T6: 6338 sge_idma_decode = (const char * const *)t6_decode; 6339 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 6340 break; 6341 6342 default: 6343 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 6344 return; 6345 } 6346 6347 if (state < sge_idma_decode_nstates) 6348 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 6349 else 6350 CH_WARN(adapter, "idma state %d unknown\n", state); 6351 6352 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 6353 CH_WARN(adapter, "SGE register %#x value %#x\n", 6354 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 6355 } 6356 6357 /** 6358 * t4_sge_ctxt_flush - flush the SGE context cache 6359 * @adap: the adapter 6360 * @mbox: mailbox to use for the FW command 6361 * 6362 * Issues a FW command through the given mailbox to flush the 6363 * SGE context cache. 6364 */ 6365 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 6366 { 6367 int ret; 6368 u32 ldst_addrspace; 6369 struct fw_ldst_cmd c; 6370 6371 memset(&c, 0, sizeof(c)); 6372 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC); 6373 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6374 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6375 ldst_addrspace); 6376 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6377 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 6378 6379 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6380 return ret; 6381 } 6382 6383 /** 6384 * t4_fw_hello - establish communication with FW 6385 * @adap: the adapter 6386 * @mbox: mailbox to use for the FW command 6387 * @evt_mbox: mailbox to receive async FW events 6388 * @master: specifies the caller's willingness to be the device master 6389 * @state: returns the current device state (if non-NULL) 6390 * 6391 * Issues a command to establish communication with FW. Returns either 6392 * an error (negative integer) or the mailbox of the Master PF. 6393 */ 6394 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 6395 enum dev_master master, enum dev_state *state) 6396 { 6397 int ret; 6398 struct fw_hello_cmd c; 6399 u32 v; 6400 unsigned int master_mbox; 6401 int retries = FW_CMD_HELLO_RETRIES; 6402 6403 retry: 6404 memset(&c, 0, sizeof(c)); 6405 INIT_CMD(c, HELLO, WRITE); 6406 c.err_to_clearinit = cpu_to_be32( 6407 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 6408 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 6409 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 6410 mbox : M_FW_HELLO_CMD_MBMASTER) | 6411 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 6412 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 6413 F_FW_HELLO_CMD_CLEARINIT); 6414 6415 /* 6416 * Issue the HELLO command to the firmware. If it's not successful 6417 * but indicates that we got a "busy" or "timeout" condition, retry 6418 * the HELLO until we exhaust our retry limit. If we do exceed our 6419 * retry limit, check to see if the firmware left us any error 6420 * information and report that if so ... 6421 */ 6422 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6423 if (ret != FW_SUCCESS) { 6424 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 6425 goto retry; 6426 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 6427 t4_report_fw_error(adap); 6428 return ret; 6429 } 6430 6431 v = be32_to_cpu(c.err_to_clearinit); 6432 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 6433 if (state) { 6434 if (v & F_FW_HELLO_CMD_ERR) 6435 *state = DEV_STATE_ERR; 6436 else if (v & F_FW_HELLO_CMD_INIT) 6437 *state = DEV_STATE_INIT; 6438 else 6439 *state = DEV_STATE_UNINIT; 6440 } 6441 6442 /* 6443 * If we're not the Master PF then we need to wait around for the 6444 * Master PF Driver to finish setting up the adapter. 6445 * 6446 * Note that we also do this wait if we're a non-Master-capable PF and 6447 * there is no current Master PF; a Master PF may show up momentarily 6448 * and we wouldn't want to fail pointlessly. (This can happen when an 6449 * OS loads lots of different drivers rapidly at the same time). In 6450 * this case, the Master PF returned by the firmware will be 6451 * M_PCIE_FW_MASTER so the test below will work ... 6452 */ 6453 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 6454 master_mbox != mbox) { 6455 int waiting = FW_CMD_HELLO_TIMEOUT; 6456 6457 /* 6458 * Wait for the firmware to either indicate an error or 6459 * initialized state. If we see either of these we bail out 6460 * and report the issue to the caller. If we exhaust the 6461 * "hello timeout" and we haven't exhausted our retries, try 6462 * again. Otherwise bail with a timeout error. 6463 */ 6464 for (;;) { 6465 u32 pcie_fw; 6466 6467 msleep(50); 6468 waiting -= 50; 6469 6470 /* 6471 * If neither Error nor Initialialized are indicated 6472 * by the firmware keep waiting till we exhaust our 6473 * timeout ... and then retry if we haven't exhausted 6474 * our retries ... 6475 */ 6476 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 6477 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 6478 if (waiting <= 0) { 6479 if (retries-- > 0) 6480 goto retry; 6481 6482 return -ETIMEDOUT; 6483 } 6484 continue; 6485 } 6486 6487 /* 6488 * We either have an Error or Initialized condition 6489 * report errors preferentially. 6490 */ 6491 if (state) { 6492 if (pcie_fw & F_PCIE_FW_ERR) 6493 *state = DEV_STATE_ERR; 6494 else if (pcie_fw & F_PCIE_FW_INIT) 6495 *state = DEV_STATE_INIT; 6496 } 6497 6498 /* 6499 * If we arrived before a Master PF was selected and 6500 * there's not a valid Master PF, grab its identity 6501 * for our caller. 6502 */ 6503 if (master_mbox == M_PCIE_FW_MASTER && 6504 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 6505 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 6506 break; 6507 } 6508 } 6509 6510 return master_mbox; 6511 } 6512 6513 /** 6514 * t4_fw_bye - end communication with FW 6515 * @adap: the adapter 6516 * @mbox: mailbox to use for the FW command 6517 * 6518 * Issues a command to terminate communication with FW. 6519 */ 6520 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 6521 { 6522 struct fw_bye_cmd c; 6523 6524 memset(&c, 0, sizeof(c)); 6525 INIT_CMD(c, BYE, WRITE); 6526 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6527 } 6528 6529 /** 6530 * t4_fw_reset - issue a reset to FW 6531 * @adap: the adapter 6532 * @mbox: mailbox to use for the FW command 6533 * @reset: specifies the type of reset to perform 6534 * 6535 * Issues a reset command of the specified type to FW. 6536 */ 6537 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 6538 { 6539 struct fw_reset_cmd c; 6540 6541 memset(&c, 0, sizeof(c)); 6542 INIT_CMD(c, RESET, WRITE); 6543 c.val = cpu_to_be32(reset); 6544 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6545 } 6546 6547 /** 6548 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 6549 * @adap: the adapter 6550 * @mbox: mailbox to use for the FW RESET command (if desired) 6551 * @force: force uP into RESET even if FW RESET command fails 6552 * 6553 * Issues a RESET command to firmware (if desired) with a HALT indication 6554 * and then puts the microprocessor into RESET state. The RESET command 6555 * will only be issued if a legitimate mailbox is provided (mbox <= 6556 * M_PCIE_FW_MASTER). 6557 * 6558 * This is generally used in order for the host to safely manipulate the 6559 * adapter without fear of conflicting with whatever the firmware might 6560 * be doing. The only way out of this state is to RESTART the firmware 6561 * ... 6562 */ 6563 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 6564 { 6565 int ret = 0; 6566 6567 /* 6568 * If a legitimate mailbox is provided, issue a RESET command 6569 * with a HALT indication. 6570 */ 6571 if (mbox <= M_PCIE_FW_MASTER) { 6572 struct fw_reset_cmd c; 6573 6574 memset(&c, 0, sizeof(c)); 6575 INIT_CMD(c, RESET, WRITE); 6576 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 6577 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 6578 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6579 } 6580 6581 /* 6582 * Normally we won't complete the operation if the firmware RESET 6583 * command fails but if our caller insists we'll go ahead and put the 6584 * uP into RESET. This can be useful if the firmware is hung or even 6585 * missing ... We'll have to take the risk of putting the uP into 6586 * RESET without the cooperation of firmware in that case. 6587 * 6588 * We also force the firmware's HALT flag to be on in case we bypassed 6589 * the firmware RESET command above or we're dealing with old firmware 6590 * which doesn't have the HALT capability. This will serve as a flag 6591 * for the incoming firmware to know that it's coming out of a HALT 6592 * rather than a RESET ... if it's new enough to understand that ... 6593 */ 6594 if (ret == 0 || force) { 6595 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 6596 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 6597 F_PCIE_FW_HALT); 6598 } 6599 6600 /* 6601 * And we always return the result of the firmware RESET command 6602 * even when we force the uP into RESET ... 6603 */ 6604 return ret; 6605 } 6606 6607 /** 6608 * t4_fw_restart - restart the firmware by taking the uP out of RESET 6609 * @adap: the adapter 6610 * @reset: if we want to do a RESET to restart things 6611 * 6612 * Restart firmware previously halted by t4_fw_halt(). On successful 6613 * return the previous PF Master remains as the new PF Master and there 6614 * is no need to issue a new HELLO command, etc. 6615 * 6616 * We do this in two ways: 6617 * 6618 * 1. If we're dealing with newer firmware we'll simply want to take 6619 * the chip's microprocessor out of RESET. This will cause the 6620 * firmware to start up from its start vector. And then we'll loop 6621 * until the firmware indicates it's started again (PCIE_FW.HALT 6622 * reset to 0) or we timeout. 6623 * 6624 * 2. If we're dealing with older firmware then we'll need to RESET 6625 * the chip since older firmware won't recognize the PCIE_FW.HALT 6626 * flag and automatically RESET itself on startup. 6627 */ 6628 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 6629 { 6630 if (reset) { 6631 /* 6632 * Since we're directing the RESET instead of the firmware 6633 * doing it automatically, we need to clear the PCIE_FW.HALT 6634 * bit. 6635 */ 6636 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0); 6637 6638 /* 6639 * If we've been given a valid mailbox, first try to get the 6640 * firmware to do the RESET. If that works, great and we can 6641 * return success. Otherwise, if we haven't been given a 6642 * valid mailbox or the RESET command failed, fall back to 6643 * hitting the chip with a hammer. 6644 */ 6645 if (mbox <= M_PCIE_FW_MASTER) { 6646 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6647 msleep(100); 6648 if (t4_fw_reset(adap, mbox, 6649 F_PIORST | F_PIORSTMODE) == 0) 6650 return 0; 6651 } 6652 6653 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 6654 msleep(2000); 6655 } else { 6656 int ms; 6657 6658 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6659 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 6660 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 6661 return FW_SUCCESS; 6662 msleep(100); 6663 ms += 100; 6664 } 6665 return -ETIMEDOUT; 6666 } 6667 return 0; 6668 } 6669 6670 /** 6671 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 6672 * @adap: the adapter 6673 * @mbox: mailbox to use for the FW RESET command (if desired) 6674 * @fw_data: the firmware image to write 6675 * @size: image size 6676 * @force: force upgrade even if firmware doesn't cooperate 6677 * 6678 * Perform all of the steps necessary for upgrading an adapter's 6679 * firmware image. Normally this requires the cooperation of the 6680 * existing firmware in order to halt all existing activities 6681 * but if an invalid mailbox token is passed in we skip that step 6682 * (though we'll still put the adapter microprocessor into RESET in 6683 * that case). 6684 * 6685 * On successful return the new firmware will have been loaded and 6686 * the adapter will have been fully RESET losing all previous setup 6687 * state. On unsuccessful return the adapter may be completely hosed ... 6688 * positive errno indicates that the adapter is ~probably~ intact, a 6689 * negative errno indicates that things are looking bad ... 6690 */ 6691 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 6692 const u8 *fw_data, unsigned int size, int force) 6693 { 6694 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 6695 unsigned int bootstrap = 6696 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 6697 int reset, ret; 6698 6699 if (!t4_fw_matches_chip(adap, fw_hdr)) 6700 return -EINVAL; 6701 6702 if (!bootstrap) { 6703 ret = t4_fw_halt(adap, mbox, force); 6704 if (ret < 0 && !force) 6705 return ret; 6706 } 6707 6708 ret = t4_load_fw(adap, fw_data, size); 6709 if (ret < 0 || bootstrap) 6710 return ret; 6711 6712 /* 6713 * Older versions of the firmware don't understand the new 6714 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 6715 * restart. So for newly loaded older firmware we'll have to do the 6716 * RESET for it so it starts up on a clean slate. We can tell if 6717 * the newly loaded firmware will handle this right by checking 6718 * its header flags to see if it advertises the capability. 6719 */ 6720 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 6721 return t4_fw_restart(adap, mbox, reset); 6722 } 6723 6724 /** 6725 * t4_fw_initialize - ask FW to initialize the device 6726 * @adap: the adapter 6727 * @mbox: mailbox to use for the FW command 6728 * 6729 * Issues a command to FW to partially initialize the device. This 6730 * performs initialization that generally doesn't depend on user input. 6731 */ 6732 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 6733 { 6734 struct fw_initialize_cmd c; 6735 6736 memset(&c, 0, sizeof(c)); 6737 INIT_CMD(c, INITIALIZE, WRITE); 6738 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6739 } 6740 6741 /** 6742 * t4_query_params_rw - query FW or device parameters 6743 * @adap: the adapter 6744 * @mbox: mailbox to use for the FW command 6745 * @pf: the PF 6746 * @vf: the VF 6747 * @nparams: the number of parameters 6748 * @params: the parameter names 6749 * @val: the parameter values 6750 * @rw: Write and read flag 6751 * 6752 * Reads the value of FW or device parameters. Up to 7 parameters can be 6753 * queried at once. 6754 */ 6755 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 6756 unsigned int vf, unsigned int nparams, const u32 *params, 6757 u32 *val, int rw) 6758 { 6759 int i, ret; 6760 struct fw_params_cmd c; 6761 __be32 *p = &c.param[0].mnem; 6762 6763 if (nparams > 7) 6764 return -EINVAL; 6765 6766 memset(&c, 0, sizeof(c)); 6767 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 6768 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6769 V_FW_PARAMS_CMD_PFN(pf) | 6770 V_FW_PARAMS_CMD_VFN(vf)); 6771 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 6772 6773 for (i = 0; i < nparams; i++) { 6774 *p++ = cpu_to_be32(*params++); 6775 if (rw) 6776 *p = cpu_to_be32(*(val + i)); 6777 p++; 6778 } 6779 6780 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6781 if (ret == 0) 6782 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 6783 *val++ = be32_to_cpu(*p); 6784 return ret; 6785 } 6786 6787 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 6788 unsigned int vf, unsigned int nparams, const u32 *params, 6789 u32 *val) 6790 { 6791 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 6792 } 6793 6794 /** 6795 * t4_set_params_timeout - sets FW or device parameters 6796 * @adap: the adapter 6797 * @mbox: mailbox to use for the FW command 6798 * @pf: the PF 6799 * @vf: the VF 6800 * @nparams: the number of parameters 6801 * @params: the parameter names 6802 * @val: the parameter values 6803 * @timeout: the timeout time 6804 * 6805 * Sets the value of FW or device parameters. Up to 7 parameters can be 6806 * specified at once. 6807 */ 6808 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 6809 unsigned int pf, unsigned int vf, 6810 unsigned int nparams, const u32 *params, 6811 const u32 *val, int timeout) 6812 { 6813 struct fw_params_cmd c; 6814 __be32 *p = &c.param[0].mnem; 6815 6816 if (nparams > 7) 6817 return -EINVAL; 6818 6819 memset(&c, 0, sizeof(c)); 6820 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 6821 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 6822 V_FW_PARAMS_CMD_PFN(pf) | 6823 V_FW_PARAMS_CMD_VFN(vf)); 6824 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 6825 6826 while (nparams--) { 6827 *p++ = cpu_to_be32(*params++); 6828 *p++ = cpu_to_be32(*val++); 6829 } 6830 6831 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 6832 } 6833 6834 /** 6835 * t4_set_params - sets FW or device parameters 6836 * @adap: the adapter 6837 * @mbox: mailbox to use for the FW command 6838 * @pf: the PF 6839 * @vf: the VF 6840 * @nparams: the number of parameters 6841 * @params: the parameter names 6842 * @val: the parameter values 6843 * 6844 * Sets the value of FW or device parameters. Up to 7 parameters can be 6845 * specified at once. 6846 */ 6847 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 6848 unsigned int vf, unsigned int nparams, const u32 *params, 6849 const u32 *val) 6850 { 6851 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 6852 FW_CMD_MAX_TIMEOUT); 6853 } 6854 6855 /** 6856 * t4_cfg_pfvf - configure PF/VF resource limits 6857 * @adap: the adapter 6858 * @mbox: mailbox to use for the FW command 6859 * @pf: the PF being configured 6860 * @vf: the VF being configured 6861 * @txq: the max number of egress queues 6862 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 6863 * @rxqi: the max number of interrupt-capable ingress queues 6864 * @rxq: the max number of interruptless ingress queues 6865 * @tc: the PCI traffic class 6866 * @vi: the max number of virtual interfaces 6867 * @cmask: the channel access rights mask for the PF/VF 6868 * @pmask: the port access rights mask for the PF/VF 6869 * @nexact: the maximum number of exact MPS filters 6870 * @rcaps: read capabilities 6871 * @wxcaps: write/execute capabilities 6872 * 6873 * Configures resource limits and capabilities for a physical or virtual 6874 * function. 6875 */ 6876 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 6877 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 6878 unsigned int rxqi, unsigned int rxq, unsigned int tc, 6879 unsigned int vi, unsigned int cmask, unsigned int pmask, 6880 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 6881 { 6882 struct fw_pfvf_cmd c; 6883 6884 memset(&c, 0, sizeof(c)); 6885 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 6886 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 6887 V_FW_PFVF_CMD_VFN(vf)); 6888 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 6889 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 6890 V_FW_PFVF_CMD_NIQ(rxq)); 6891 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 6892 V_FW_PFVF_CMD_PMASK(pmask) | 6893 V_FW_PFVF_CMD_NEQ(txq)); 6894 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 6895 V_FW_PFVF_CMD_NVI(vi) | 6896 V_FW_PFVF_CMD_NEXACTF(nexact)); 6897 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 6898 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 6899 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 6900 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6901 } 6902 6903 /** 6904 * t4_alloc_vi_func - allocate a virtual interface 6905 * @adap: the adapter 6906 * @mbox: mailbox to use for the FW command 6907 * @port: physical port associated with the VI 6908 * @pf: the PF owning the VI 6909 * @vf: the VF owning the VI 6910 * @nmac: number of MAC addresses needed (1 to 5) 6911 * @mac: the MAC addresses of the VI 6912 * @rss_size: size of RSS table slice associated with this VI 6913 * @portfunc: which Port Application Function MAC Address is desired 6914 * @idstype: Intrusion Detection Type 6915 * 6916 * Allocates a virtual interface for the given physical port. If @mac is 6917 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 6918 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 6919 * @mac should be large enough to hold @nmac Ethernet addresses, they are 6920 * stored consecutively so the space needed is @nmac * 6 bytes. 6921 * Returns a negative error number or the non-negative VI id. 6922 */ 6923 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 6924 unsigned int port, unsigned int pf, unsigned int vf, 6925 unsigned int nmac, u8 *mac, u16 *rss_size, 6926 unsigned int portfunc, unsigned int idstype) 6927 { 6928 int ret; 6929 struct fw_vi_cmd c; 6930 6931 memset(&c, 0, sizeof(c)); 6932 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 6933 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 6934 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 6935 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 6936 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 6937 V_FW_VI_CMD_FUNC(portfunc)); 6938 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 6939 c.nmac = nmac - 1; 6940 if(!rss_size) 6941 c.norss_rsssize = F_FW_VI_CMD_NORSS; 6942 6943 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6944 if (ret) 6945 return ret; 6946 6947 if (mac) { 6948 memcpy(mac, c.mac, sizeof(c.mac)); 6949 switch (nmac) { 6950 case 5: 6951 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 6952 case 4: 6953 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 6954 case 3: 6955 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 6956 case 2: 6957 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 6958 } 6959 } 6960 if (rss_size) 6961 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 6962 return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 6963 } 6964 6965 /** 6966 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 6967 * @adap: the adapter 6968 * @mbox: mailbox to use for the FW command 6969 * @port: physical port associated with the VI 6970 * @pf: the PF owning the VI 6971 * @vf: the VF owning the VI 6972 * @nmac: number of MAC addresses needed (1 to 5) 6973 * @mac: the MAC addresses of the VI 6974 * @rss_size: size of RSS table slice associated with this VI 6975 * 6976 * backwards compatible and convieniance routine to allocate a Virtual 6977 * Interface with a Ethernet Port Application Function and Intrustion 6978 * Detection System disabled. 6979 */ 6980 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 6981 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 6982 u16 *rss_size) 6983 { 6984 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 6985 FW_VI_FUNC_ETH, 0); 6986 } 6987 6988 /** 6989 * t4_free_vi - free a virtual interface 6990 * @adap: the adapter 6991 * @mbox: mailbox to use for the FW command 6992 * @pf: the PF owning the VI 6993 * @vf: the VF owning the VI 6994 * @viid: virtual interface identifiler 6995 * 6996 * Free a previously allocated virtual interface. 6997 */ 6998 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 6999 unsigned int vf, unsigned int viid) 7000 { 7001 struct fw_vi_cmd c; 7002 7003 memset(&c, 0, sizeof(c)); 7004 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 7005 F_FW_CMD_REQUEST | 7006 F_FW_CMD_EXEC | 7007 V_FW_VI_CMD_PFN(pf) | 7008 V_FW_VI_CMD_VFN(vf)); 7009 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 7010 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 7011 7012 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7013 } 7014 7015 /** 7016 * t4_set_rxmode - set Rx properties of a virtual interface 7017 * @adap: the adapter 7018 * @mbox: mailbox to use for the FW command 7019 * @viid: the VI id 7020 * @mtu: the new MTU or -1 7021 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 7022 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 7023 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 7024 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 7025 * @sleep_ok: if true we may sleep while awaiting command completion 7026 * 7027 * Sets Rx properties of a virtual interface. 7028 */ 7029 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 7030 int mtu, int promisc, int all_multi, int bcast, int vlanex, 7031 bool sleep_ok) 7032 { 7033 struct fw_vi_rxmode_cmd c; 7034 7035 /* convert to FW values */ 7036 if (mtu < 0) 7037 mtu = M_FW_VI_RXMODE_CMD_MTU; 7038 if (promisc < 0) 7039 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 7040 if (all_multi < 0) 7041 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 7042 if (bcast < 0) 7043 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 7044 if (vlanex < 0) 7045 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 7046 7047 memset(&c, 0, sizeof(c)); 7048 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 7049 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7050 V_FW_VI_RXMODE_CMD_VIID(viid)); 7051 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7052 c.mtu_to_vlanexen = 7053 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 7054 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 7055 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 7056 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 7057 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 7058 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7059 } 7060 7061 /** 7062 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 7063 * @adap: the adapter 7064 * @mbox: mailbox to use for the FW command 7065 * @viid: the VI id 7066 * @free: if true any existing filters for this VI id are first removed 7067 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 7068 * @addr: the MAC address(es) 7069 * @idx: where to store the index of each allocated filter 7070 * @hash: pointer to hash address filter bitmap 7071 * @sleep_ok: call is allowed to sleep 7072 * 7073 * Allocates an exact-match filter for each of the supplied addresses and 7074 * sets it to the corresponding address. If @idx is not %NULL it should 7075 * have at least @naddr entries, each of which will be set to the index of 7076 * the filter allocated for the corresponding MAC address. If a filter 7077 * could not be allocated for an address its index is set to 0xffff. 7078 * If @hash is not %NULL addresses that fail to allocate an exact filter 7079 * are hashed and update the hash filter bitmap pointed at by @hash. 7080 * 7081 * Returns a negative error number or the number of filters allocated. 7082 */ 7083 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 7084 unsigned int viid, bool free, unsigned int naddr, 7085 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 7086 { 7087 int offset, ret = 0; 7088 struct fw_vi_mac_cmd c; 7089 unsigned int nfilters = 0; 7090 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 7091 unsigned int rem = naddr; 7092 7093 if (naddr > max_naddr) 7094 return -EINVAL; 7095 7096 for (offset = 0; offset < naddr ; /**/) { 7097 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 7098 ? rem 7099 : ARRAY_SIZE(c.u.exact)); 7100 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 7101 u.exact[fw_naddr]), 16); 7102 struct fw_vi_mac_exact *p; 7103 int i; 7104 7105 memset(&c, 0, sizeof(c)); 7106 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7107 F_FW_CMD_REQUEST | 7108 F_FW_CMD_WRITE | 7109 V_FW_CMD_EXEC(free) | 7110 V_FW_VI_MAC_CMD_VIID(viid)); 7111 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 7112 V_FW_CMD_LEN16(len16)); 7113 7114 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7115 p->valid_to_idx = 7116 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7117 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 7118 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 7119 } 7120 7121 /* 7122 * It's okay if we run out of space in our MAC address arena. 7123 * Some of the addresses we submit may get stored so we need 7124 * to run through the reply to see what the results were ... 7125 */ 7126 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 7127 if (ret && ret != -FW_ENOMEM) 7128 break; 7129 7130 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7131 u16 index = G_FW_VI_MAC_CMD_IDX( 7132 be16_to_cpu(p->valid_to_idx)); 7133 7134 if (idx) 7135 idx[offset+i] = (index >= max_naddr 7136 ? 0xffff 7137 : index); 7138 if (index < max_naddr) 7139 nfilters++; 7140 else if (hash) 7141 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 7142 } 7143 7144 free = false; 7145 offset += fw_naddr; 7146 rem -= fw_naddr; 7147 } 7148 7149 if (ret == 0 || ret == -FW_ENOMEM) 7150 ret = nfilters; 7151 return ret; 7152 } 7153 7154 /** 7155 * t4_change_mac - modifies the exact-match filter for a MAC address 7156 * @adap: the adapter 7157 * @mbox: mailbox to use for the FW command 7158 * @viid: the VI id 7159 * @idx: index of existing filter for old value of MAC address, or -1 7160 * @addr: the new MAC address value 7161 * @persist: whether a new MAC allocation should be persistent 7162 * @add_smt: if true also add the address to the HW SMT 7163 * 7164 * Modifies an exact-match filter and sets it to the new MAC address if 7165 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 7166 * latter case the address is added persistently if @persist is %true. 7167 * 7168 * Note that in general it is not possible to modify the value of a given 7169 * filter so the generic way to modify an address filter is to free the one 7170 * being used by the old address value and allocate a new filter for the 7171 * new address value. 7172 * 7173 * Returns a negative error number or the index of the filter with the new 7174 * MAC value. Note that this index may differ from @idx. 7175 */ 7176 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 7177 int idx, const u8 *addr, bool persist, bool add_smt) 7178 { 7179 int ret, mode; 7180 struct fw_vi_mac_cmd c; 7181 struct fw_vi_mac_exact *p = c.u.exact; 7182 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 7183 7184 if (idx < 0) /* new allocation */ 7185 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 7186 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 7187 7188 memset(&c, 0, sizeof(c)); 7189 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7190 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7191 V_FW_VI_MAC_CMD_VIID(viid)); 7192 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 7193 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7194 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 7195 V_FW_VI_MAC_CMD_IDX(idx)); 7196 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 7197 7198 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7199 if (ret == 0) { 7200 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 7201 if (ret >= max_mac_addr) 7202 ret = -ENOMEM; 7203 } 7204 return ret; 7205 } 7206 7207 /** 7208 * t4_set_addr_hash - program the MAC inexact-match hash filter 7209 * @adap: the adapter 7210 * @mbox: mailbox to use for the FW command 7211 * @viid: the VI id 7212 * @ucast: whether the hash filter should also match unicast addresses 7213 * @vec: the value to be written to the hash filter 7214 * @sleep_ok: call is allowed to sleep 7215 * 7216 * Sets the 64-bit inexact-match hash filter for a virtual interface. 7217 */ 7218 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 7219 bool ucast, u64 vec, bool sleep_ok) 7220 { 7221 struct fw_vi_mac_cmd c; 7222 u32 val; 7223 7224 memset(&c, 0, sizeof(c)); 7225 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7226 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7227 V_FW_VI_ENABLE_CMD_VIID(viid)); 7228 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 7229 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 7230 c.freemacs_to_len16 = cpu_to_be32(val); 7231 c.u.hash.hashvec = cpu_to_be64(vec); 7232 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7233 } 7234 7235 /** 7236 * t4_enable_vi_params - enable/disable a virtual interface 7237 * @adap: the adapter 7238 * @mbox: mailbox to use for the FW command 7239 * @viid: the VI id 7240 * @rx_en: 1=enable Rx, 0=disable Rx 7241 * @tx_en: 1=enable Tx, 0=disable Tx 7242 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 7243 * 7244 * Enables/disables a virtual interface. Note that setting DCB Enable 7245 * only makes sense when enabling a Virtual Interface ... 7246 */ 7247 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 7248 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 7249 { 7250 struct fw_vi_enable_cmd c; 7251 7252 memset(&c, 0, sizeof(c)); 7253 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7254 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7255 V_FW_VI_ENABLE_CMD_VIID(viid)); 7256 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 7257 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 7258 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 7259 FW_LEN16(c)); 7260 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 7261 } 7262 7263 /** 7264 * t4_enable_vi - enable/disable a virtual interface 7265 * @adap: the adapter 7266 * @mbox: mailbox to use for the FW command 7267 * @viid: the VI id 7268 * @rx_en: 1=enable Rx, 0=disable Rx 7269 * @tx_en: 1=enable Tx, 0=disable Tx 7270 * 7271 * Enables/disables a virtual interface. Note that setting DCB Enable 7272 * only makes sense when enabling a Virtual Interface ... 7273 */ 7274 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 7275 bool rx_en, bool tx_en) 7276 { 7277 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 7278 } 7279 7280 /** 7281 * t4_identify_port - identify a VI's port by blinking its LED 7282 * @adap: the adapter 7283 * @mbox: mailbox to use for the FW command 7284 * @viid: the VI id 7285 * @nblinks: how many times to blink LED at 2.5 Hz 7286 * 7287 * Identifies a VI's port by blinking its LED. 7288 */ 7289 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 7290 unsigned int nblinks) 7291 { 7292 struct fw_vi_enable_cmd c; 7293 7294 memset(&c, 0, sizeof(c)); 7295 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7296 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7297 V_FW_VI_ENABLE_CMD_VIID(viid)); 7298 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 7299 c.blinkdur = cpu_to_be16(nblinks); 7300 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7301 } 7302 7303 /** 7304 * t4_iq_stop - stop an ingress queue and its FLs 7305 * @adap: the adapter 7306 * @mbox: mailbox to use for the FW command 7307 * @pf: the PF owning the queues 7308 * @vf: the VF owning the queues 7309 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7310 * @iqid: ingress queue id 7311 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7312 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7313 * 7314 * Stops an ingress queue and its associated FLs, if any. This causes 7315 * any current or future data/messages destined for these queues to be 7316 * tossed. 7317 */ 7318 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 7319 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7320 unsigned int fl0id, unsigned int fl1id) 7321 { 7322 struct fw_iq_cmd c; 7323 7324 memset(&c, 0, sizeof(c)); 7325 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7326 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7327 V_FW_IQ_CMD_VFN(vf)); 7328 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 7329 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7330 c.iqid = cpu_to_be16(iqid); 7331 c.fl0id = cpu_to_be16(fl0id); 7332 c.fl1id = cpu_to_be16(fl1id); 7333 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7334 } 7335 7336 /** 7337 * t4_iq_free - free an ingress queue and its FLs 7338 * @adap: the adapter 7339 * @mbox: mailbox to use for the FW command 7340 * @pf: the PF owning the queues 7341 * @vf: the VF owning the queues 7342 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7343 * @iqid: ingress queue id 7344 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7345 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7346 * 7347 * Frees an ingress queue and its associated FLs, if any. 7348 */ 7349 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7350 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7351 unsigned int fl0id, unsigned int fl1id) 7352 { 7353 struct fw_iq_cmd c; 7354 7355 memset(&c, 0, sizeof(c)); 7356 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7357 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7358 V_FW_IQ_CMD_VFN(vf)); 7359 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 7360 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7361 c.iqid = cpu_to_be16(iqid); 7362 c.fl0id = cpu_to_be16(fl0id); 7363 c.fl1id = cpu_to_be16(fl1id); 7364 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7365 } 7366 7367 /** 7368 * t4_eth_eq_free - free an Ethernet egress queue 7369 * @adap: the adapter 7370 * @mbox: mailbox to use for the FW command 7371 * @pf: the PF owning the queue 7372 * @vf: the VF owning the queue 7373 * @eqid: egress queue id 7374 * 7375 * Frees an Ethernet egress queue. 7376 */ 7377 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7378 unsigned int vf, unsigned int eqid) 7379 { 7380 struct fw_eq_eth_cmd c; 7381 7382 memset(&c, 0, sizeof(c)); 7383 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 7384 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7385 V_FW_EQ_ETH_CMD_PFN(pf) | 7386 V_FW_EQ_ETH_CMD_VFN(vf)); 7387 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 7388 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 7389 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7390 } 7391 7392 /** 7393 * t4_ctrl_eq_free - free a control egress queue 7394 * @adap: the adapter 7395 * @mbox: mailbox to use for the FW command 7396 * @pf: the PF owning the queue 7397 * @vf: the VF owning the queue 7398 * @eqid: egress queue id 7399 * 7400 * Frees a control egress queue. 7401 */ 7402 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7403 unsigned int vf, unsigned int eqid) 7404 { 7405 struct fw_eq_ctrl_cmd c; 7406 7407 memset(&c, 0, sizeof(c)); 7408 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 7409 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7410 V_FW_EQ_CTRL_CMD_PFN(pf) | 7411 V_FW_EQ_CTRL_CMD_VFN(vf)); 7412 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 7413 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 7414 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7415 } 7416 7417 /** 7418 * t4_ofld_eq_free - free an offload egress queue 7419 * @adap: the adapter 7420 * @mbox: mailbox to use for the FW command 7421 * @pf: the PF owning the queue 7422 * @vf: the VF owning the queue 7423 * @eqid: egress queue id 7424 * 7425 * Frees a control egress queue. 7426 */ 7427 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7428 unsigned int vf, unsigned int eqid) 7429 { 7430 struct fw_eq_ofld_cmd c; 7431 7432 memset(&c, 0, sizeof(c)); 7433 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 7434 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7435 V_FW_EQ_OFLD_CMD_PFN(pf) | 7436 V_FW_EQ_OFLD_CMD_VFN(vf)); 7437 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 7438 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 7439 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7440 } 7441 7442 /** 7443 * t4_link_down_rc_str - return a string for a Link Down Reason Code 7444 * @link_down_rc: Link Down Reason Code 7445 * 7446 * Returns a string representation of the Link Down Reason Code. 7447 */ 7448 const char *t4_link_down_rc_str(unsigned char link_down_rc) 7449 { 7450 static const char *reason[] = { 7451 "Link Down", 7452 "Remote Fault", 7453 "Auto-negotiation Failure", 7454 "Reserved3", 7455 "Insufficient Airflow", 7456 "Unable To Determine Reason", 7457 "No RX Signal Detected", 7458 "Reserved7", 7459 }; 7460 7461 if (link_down_rc >= ARRAY_SIZE(reason)) 7462 return "Bad Reason Code"; 7463 7464 return reason[link_down_rc]; 7465 } 7466 7467 /** 7468 * t4_handle_fw_rpl - process a FW reply message 7469 * @adap: the adapter 7470 * @rpl: start of the FW message 7471 * 7472 * Processes a FW message, such as link state change messages. 7473 */ 7474 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 7475 { 7476 u8 opcode = *(const u8 *)rpl; 7477 const struct fw_port_cmd *p = (const void *)rpl; 7478 unsigned int action = 7479 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 7480 7481 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) { 7482 /* link/module state change message */ 7483 int speed = 0, fc = 0, i; 7484 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 7485 struct port_info *pi = NULL; 7486 struct link_config *lc; 7487 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 7488 int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 7489 u32 mod = G_FW_PORT_CMD_MODTYPE(stat); 7490 7491 if (stat & F_FW_PORT_CMD_RXPAUSE) 7492 fc |= PAUSE_RX; 7493 if (stat & F_FW_PORT_CMD_TXPAUSE) 7494 fc |= PAUSE_TX; 7495 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 7496 speed = 100; 7497 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 7498 speed = 1000; 7499 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 7500 speed = 10000; 7501 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 7502 speed = 25000; 7503 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 7504 speed = 40000; 7505 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 7506 speed = 100000; 7507 7508 for_each_port(adap, i) { 7509 pi = adap2pinfo(adap, i); 7510 if (pi->tx_chan == chan) 7511 break; 7512 } 7513 lc = &pi->link_cfg; 7514 7515 if (mod != pi->mod_type) { 7516 pi->mod_type = mod; 7517 t4_os_portmod_changed(adap, i); 7518 } 7519 if (link_ok != lc->link_ok || speed != lc->speed || 7520 fc != lc->fc) { /* something changed */ 7521 int reason; 7522 7523 if (!link_ok && lc->link_ok) 7524 reason = G_FW_PORT_CMD_LINKDNRC(stat); 7525 else 7526 reason = -1; 7527 7528 lc->link_ok = link_ok; 7529 lc->speed = speed; 7530 lc->fc = fc; 7531 lc->supported = be16_to_cpu(p->u.info.pcap); 7532 t4_os_link_changed(adap, i, link_ok, reason); 7533 } 7534 } else { 7535 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 7536 return -EINVAL; 7537 } 7538 return 0; 7539 } 7540 7541 /** 7542 * get_pci_mode - determine a card's PCI mode 7543 * @adapter: the adapter 7544 * @p: where to store the PCI settings 7545 * 7546 * Determines a card's PCI mode and associated parameters, such as speed 7547 * and width. 7548 */ 7549 static void get_pci_mode(struct adapter *adapter, 7550 struct pci_params *p) 7551 { 7552 u16 val; 7553 u32 pcie_cap; 7554 7555 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 7556 if (pcie_cap) { 7557 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 7558 p->speed = val & PCI_EXP_LNKSTA_CLS; 7559 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 7560 } 7561 } 7562 7563 /** 7564 * init_link_config - initialize a link's SW state 7565 * @lc: structure holding the link state 7566 * @caps: link capabilities 7567 * 7568 * Initializes the SW state maintained for each link, including the link's 7569 * capabilities and default speed/flow-control/autonegotiation settings. 7570 */ 7571 static void init_link_config(struct link_config *lc, unsigned int caps) 7572 { 7573 lc->supported = caps; 7574 lc->requested_speed = 0; 7575 lc->speed = 0; 7576 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX; 7577 if (lc->supported & FW_PORT_CAP_ANEG) { 7578 lc->advertising = lc->supported & ADVERT_MASK; 7579 lc->autoneg = AUTONEG_ENABLE; 7580 lc->requested_fc |= PAUSE_AUTONEG; 7581 } else { 7582 lc->advertising = 0; 7583 lc->autoneg = AUTONEG_DISABLE; 7584 } 7585 } 7586 7587 struct flash_desc { 7588 u32 vendor_and_model_id; 7589 u32 size_mb; 7590 }; 7591 7592 int t4_get_flash_params(struct adapter *adapter) 7593 { 7594 /* 7595 * Table for non-Numonix supported flash parts. Numonix parts are left 7596 * to the preexisting well-tested code. All flash parts have 64KB 7597 * sectors. 7598 */ 7599 static struct flash_desc supported_flash[] = { 7600 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 7601 }; 7602 7603 int ret; 7604 u32 info = 0; 7605 7606 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 7607 if (!ret) 7608 ret = sf1_read(adapter, 3, 0, 1, &info); 7609 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 7610 if (ret < 0) 7611 return ret; 7612 7613 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret) 7614 if (supported_flash[ret].vendor_and_model_id == info) { 7615 adapter->params.sf_size = supported_flash[ret].size_mb; 7616 adapter->params.sf_nsec = 7617 adapter->params.sf_size / SF_SEC_SIZE; 7618 return 0; 7619 } 7620 7621 if ((info & 0xff) != 0x20) /* not a Numonix flash */ 7622 return -EINVAL; 7623 info >>= 16; /* log2 of size */ 7624 if (info >= 0x14 && info < 0x18) 7625 adapter->params.sf_nsec = 1 << (info - 16); 7626 else if (info == 0x18) 7627 adapter->params.sf_nsec = 64; 7628 else 7629 return -EINVAL; 7630 adapter->params.sf_size = 1 << info; 7631 7632 /* 7633 * We should ~probably~ reject adapters with FLASHes which are too 7634 * small but we have some legacy FPGAs with small FLASHes that we'd 7635 * still like to use. So instead we emit a scary message ... 7636 */ 7637 if (adapter->params.sf_size < FLASH_MIN_SIZE) 7638 CH_WARN(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n", 7639 adapter->params.sf_size, FLASH_MIN_SIZE); 7640 7641 return 0; 7642 } 7643 7644 static void set_pcie_completion_timeout(struct adapter *adapter, 7645 u8 range) 7646 { 7647 u16 val; 7648 u32 pcie_cap; 7649 7650 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 7651 if (pcie_cap) { 7652 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 7653 val &= 0xfff0; 7654 val |= range ; 7655 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 7656 } 7657 } 7658 7659 const struct chip_params *t4_get_chip_params(int chipid) 7660 { 7661 static const struct chip_params chip_params[] = { 7662 { 7663 /* T4 */ 7664 .nchan = NCHAN, 7665 .pm_stats_cnt = PM_NSTATS, 7666 .cng_ch_bits_log = 2, 7667 .nsched_cls = 15, 7668 .cim_num_obq = CIM_NUM_OBQ, 7669 .mps_rplc_size = 128, 7670 .vfcount = 128, 7671 .sge_fl_db = F_DBPRIO, 7672 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 7673 }, 7674 { 7675 /* T5 */ 7676 .nchan = NCHAN, 7677 .pm_stats_cnt = PM_NSTATS, 7678 .cng_ch_bits_log = 2, 7679 .nsched_cls = 16, 7680 .cim_num_obq = CIM_NUM_OBQ_T5, 7681 .mps_rplc_size = 128, 7682 .vfcount = 128, 7683 .sge_fl_db = F_DBPRIO | F_DBTYPE, 7684 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 7685 }, 7686 { 7687 /* T6 */ 7688 .nchan = T6_NCHAN, 7689 .pm_stats_cnt = T6_PM_NSTATS, 7690 .cng_ch_bits_log = 3, 7691 .nsched_cls = 16, 7692 .cim_num_obq = CIM_NUM_OBQ_T5, 7693 .mps_rplc_size = 256, 7694 .vfcount = 256, 7695 .sge_fl_db = 0, 7696 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 7697 }, 7698 }; 7699 7700 chipid -= CHELSIO_T4; 7701 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 7702 return NULL; 7703 7704 return &chip_params[chipid]; 7705 } 7706 7707 /** 7708 * t4_prep_adapter - prepare SW and HW for operation 7709 * @adapter: the adapter 7710 * @buf: temporary space of at least VPD_LEN size provided by the caller. 7711 * 7712 * Initialize adapter SW state for the various HW modules, set initial 7713 * values for some adapter tunables, take PHYs out of reset, and 7714 * initialize the MDIO interface. 7715 */ 7716 int t4_prep_adapter(struct adapter *adapter, u8 *buf) 7717 { 7718 int ret; 7719 uint16_t device_id; 7720 uint32_t pl_rev; 7721 7722 get_pci_mode(adapter, &adapter->params.pci); 7723 7724 pl_rev = t4_read_reg(adapter, A_PL_REV); 7725 adapter->params.chipid = G_CHIPID(pl_rev); 7726 adapter->params.rev = G_REV(pl_rev); 7727 if (adapter->params.chipid == 0) { 7728 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 7729 adapter->params.chipid = CHELSIO_T4; 7730 7731 /* T4A1 chip is not supported */ 7732 if (adapter->params.rev == 1) { 7733 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 7734 return -EINVAL; 7735 } 7736 } 7737 7738 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 7739 if (adapter->chip_params == NULL) 7740 return -EINVAL; 7741 7742 adapter->params.pci.vpd_cap_addr = 7743 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 7744 7745 ret = t4_get_flash_params(adapter); 7746 if (ret < 0) 7747 return ret; 7748 7749 ret = get_vpd_params(adapter, &adapter->params.vpd, buf); 7750 if (ret < 0) 7751 return ret; 7752 7753 /* Cards with real ASICs have the chipid in the PCIe device id */ 7754 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 7755 if (device_id >> 12 == chip_id(adapter)) 7756 adapter->params.cim_la_size = CIMLA_SIZE; 7757 else { 7758 /* FPGA */ 7759 adapter->params.fpga = 1; 7760 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 7761 } 7762 7763 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 7764 7765 /* 7766 * Default port and clock for debugging in case we can't reach FW. 7767 */ 7768 adapter->params.nports = 1; 7769 adapter->params.portvec = 1; 7770 adapter->params.vpd.cclk = 50000; 7771 7772 /* Set pci completion timeout value to 4 seconds. */ 7773 set_pcie_completion_timeout(adapter, 0xd); 7774 return 0; 7775 } 7776 7777 /** 7778 * t4_shutdown_adapter - shut down adapter, host & wire 7779 * @adapter: the adapter 7780 * 7781 * Perform an emergency shutdown of the adapter and stop it from 7782 * continuing any further communication on the ports or DMA to the 7783 * host. This is typically used when the adapter and/or firmware 7784 * have crashed and we want to prevent any further accidental 7785 * communication with the rest of the world. This will also force 7786 * the port Link Status to go down -- if register writes work -- 7787 * which should help our peers figure out that we're down. 7788 */ 7789 int t4_shutdown_adapter(struct adapter *adapter) 7790 { 7791 int port; 7792 7793 t4_intr_disable(adapter); 7794 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 7795 for_each_port(adapter, port) { 7796 u32 a_port_cfg = PORT_REG(port, 7797 is_t4(adapter) 7798 ? A_XGMAC_PORT_CFG 7799 : A_MAC_PORT_CFG); 7800 7801 t4_write_reg(adapter, a_port_cfg, 7802 t4_read_reg(adapter, a_port_cfg) 7803 & ~V_SIGNAL_DET(1)); 7804 } 7805 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 7806 7807 return 0; 7808 } 7809 7810 /** 7811 * t4_init_devlog_params - initialize adapter->params.devlog 7812 * @adap: the adapter 7813 * @fw_attach: whether we can talk to the firmware 7814 * 7815 * Initialize various fields of the adapter's Firmware Device Log 7816 * Parameters structure. 7817 */ 7818 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 7819 { 7820 struct devlog_params *dparams = &adap->params.devlog; 7821 u32 pf_dparams; 7822 unsigned int devlog_meminfo; 7823 struct fw_devlog_cmd devlog_cmd; 7824 int ret; 7825 7826 /* If we're dealing with newer firmware, the Device Log Paramerters 7827 * are stored in a designated register which allows us to access the 7828 * Device Log even if we can't talk to the firmware. 7829 */ 7830 pf_dparams = 7831 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 7832 if (pf_dparams) { 7833 unsigned int nentries, nentries128; 7834 7835 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 7836 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 7837 7838 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 7839 nentries = (nentries128 + 1) * 128; 7840 dparams->size = nentries * sizeof(struct fw_devlog_e); 7841 7842 return 0; 7843 } 7844 7845 /* 7846 * For any failing returns ... 7847 */ 7848 memset(dparams, 0, sizeof *dparams); 7849 7850 /* 7851 * If we can't talk to the firmware, there's really nothing we can do 7852 * at this point. 7853 */ 7854 if (!fw_attach) 7855 return -ENXIO; 7856 7857 /* Otherwise, ask the firmware for it's Device Log Parameters. 7858 */ 7859 memset(&devlog_cmd, 0, sizeof devlog_cmd); 7860 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 7861 F_FW_CMD_REQUEST | F_FW_CMD_READ); 7862 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 7863 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 7864 &devlog_cmd); 7865 if (ret) 7866 return ret; 7867 7868 devlog_meminfo = 7869 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 7870 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 7871 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 7872 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 7873 7874 return 0; 7875 } 7876 7877 /** 7878 * t4_init_sge_params - initialize adap->params.sge 7879 * @adapter: the adapter 7880 * 7881 * Initialize various fields of the adapter's SGE Parameters structure. 7882 */ 7883 int t4_init_sge_params(struct adapter *adapter) 7884 { 7885 u32 r; 7886 struct sge_params *sp = &adapter->params.sge; 7887 unsigned i; 7888 7889 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 7890 sp->counter_val[0] = G_THRESHOLD_0(r); 7891 sp->counter_val[1] = G_THRESHOLD_1(r); 7892 sp->counter_val[2] = G_THRESHOLD_2(r); 7893 sp->counter_val[3] = G_THRESHOLD_3(r); 7894 7895 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 7896 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)); 7897 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)); 7898 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 7899 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)); 7900 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)); 7901 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 7902 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)); 7903 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)); 7904 7905 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 7906 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 7907 if (is_t4(adapter)) 7908 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 7909 else if (is_t5(adapter)) 7910 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 7911 else 7912 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 7913 7914 /* egress queues: log2 of # of doorbells per BAR2 page */ 7915 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 7916 r >>= S_QUEUESPERPAGEPF0 + 7917 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 7918 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 7919 7920 /* ingress queues: log2 of # of doorbells per BAR2 page */ 7921 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 7922 r >>= S_QUEUESPERPAGEPF0 + 7923 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 7924 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 7925 7926 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 7927 r >>= S_HOSTPAGESIZEPF0 + 7928 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 7929 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 7930 7931 r = t4_read_reg(adapter, A_SGE_CONTROL); 7932 sp->sge_control = r; 7933 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 7934 sp->fl_pktshift = G_PKTSHIFT(r); 7935 if (chip_id(adapter) <= CHELSIO_T5) { 7936 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 7937 X_INGPADBOUNDARY_SHIFT); 7938 } else { 7939 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 7940 X_T6_INGPADBOUNDARY_SHIFT); 7941 } 7942 if (is_t4(adapter)) 7943 sp->pack_boundary = sp->pad_boundary; 7944 else { 7945 r = t4_read_reg(adapter, A_SGE_CONTROL2); 7946 if (G_INGPACKBOUNDARY(r) == 0) 7947 sp->pack_boundary = 16; 7948 else 7949 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 7950 } 7951 for (i = 0; i < SGE_FLBUF_SIZES; i++) 7952 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 7953 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 7954 7955 return 0; 7956 } 7957 7958 /* 7959 * Read and cache the adapter's compressed filter mode and ingress config. 7960 */ 7961 static void read_filter_mode_and_ingress_config(struct adapter *adap) 7962 { 7963 struct tp_params *tpp = &adap->params.tp; 7964 7965 if (t4_use_ldst(adap)) { 7966 t4_fw_tp_pio_rw(adap, &tpp->vlan_pri_map, 1, 7967 A_TP_VLAN_PRI_MAP, 1); 7968 t4_fw_tp_pio_rw(adap, &tpp->ingress_config, 1, 7969 A_TP_INGRESS_CONFIG, 1); 7970 } else { 7971 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 7972 &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP); 7973 t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 7974 &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG); 7975 } 7976 7977 /* 7978 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 7979 * shift positions of several elements of the Compressed Filter Tuple 7980 * for this adapter which we need frequently ... 7981 */ 7982 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 7983 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 7984 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 7985 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 7986 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 7987 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 7988 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 7989 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 7990 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 7991 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 7992 7993 /* 7994 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID 7995 * represents the presence of an Outer VLAN instead of a VNIC ID. 7996 */ 7997 if ((tpp->ingress_config & F_VNIC) == 0) 7998 tpp->vnic_shift = -1; 7999 } 8000 8001 /** 8002 * t4_init_tp_params - initialize adap->params.tp 8003 * @adap: the adapter 8004 * 8005 * Initialize various fields of the adapter's TP Parameters structure. 8006 */ 8007 int t4_init_tp_params(struct adapter *adap) 8008 { 8009 int chan; 8010 u32 v; 8011 struct tp_params *tpp = &adap->params.tp; 8012 8013 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 8014 tpp->tre = G_TIMERRESOLUTION(v); 8015 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 8016 8017 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 8018 for (chan = 0; chan < MAX_NCHAN; chan++) 8019 tpp->tx_modq[chan] = chan; 8020 8021 read_filter_mode_and_ingress_config(adap); 8022 8023 /* 8024 * For T6, cache the adapter's compressed error vector 8025 * and passing outer header info for encapsulated packets. 8026 */ 8027 if (chip_id(adap) > CHELSIO_T5) { 8028 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 8029 tpp->rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0; 8030 } 8031 8032 return 0; 8033 } 8034 8035 /** 8036 * t4_filter_field_shift - calculate filter field shift 8037 * @adap: the adapter 8038 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 8039 * 8040 * Return the shift position of a filter field within the Compressed 8041 * Filter Tuple. The filter field is specified via its selection bit 8042 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 8043 */ 8044 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 8045 { 8046 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 8047 unsigned int sel; 8048 int field_shift; 8049 8050 if ((filter_mode & filter_sel) == 0) 8051 return -1; 8052 8053 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 8054 switch (filter_mode & sel) { 8055 case F_FCOE: 8056 field_shift += W_FT_FCOE; 8057 break; 8058 case F_PORT: 8059 field_shift += W_FT_PORT; 8060 break; 8061 case F_VNIC_ID: 8062 field_shift += W_FT_VNIC_ID; 8063 break; 8064 case F_VLAN: 8065 field_shift += W_FT_VLAN; 8066 break; 8067 case F_TOS: 8068 field_shift += W_FT_TOS; 8069 break; 8070 case F_PROTOCOL: 8071 field_shift += W_FT_PROTOCOL; 8072 break; 8073 case F_ETHERTYPE: 8074 field_shift += W_FT_ETHERTYPE; 8075 break; 8076 case F_MACMATCH: 8077 field_shift += W_FT_MACMATCH; 8078 break; 8079 case F_MPSHITTYPE: 8080 field_shift += W_FT_MPSHITTYPE; 8081 break; 8082 case F_FRAGMENTATION: 8083 field_shift += W_FT_FRAGMENTATION; 8084 break; 8085 } 8086 } 8087 return field_shift; 8088 } 8089 8090 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 8091 { 8092 u8 addr[6]; 8093 int ret, i, j; 8094 struct fw_port_cmd c; 8095 u16 rss_size; 8096 struct port_info *p = adap2pinfo(adap, port_id); 8097 u32 param, val; 8098 8099 memset(&c, 0, sizeof(c)); 8100 8101 for (i = 0, j = -1; i <= p->port_id; i++) { 8102 do { 8103 j++; 8104 } while ((adap->params.portvec & (1 << j)) == 0); 8105 } 8106 8107 if (!(adap->flags & IS_VF) || 8108 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 8109 c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) | 8110 F_FW_CMD_REQUEST | F_FW_CMD_READ | 8111 V_FW_PORT_CMD_PORTID(j)); 8112 c.action_to_len16 = htonl( 8113 V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) | 8114 FW_LEN16(c)); 8115 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8116 if (ret) 8117 return ret; 8118 8119 ret = be32_to_cpu(c.u.info.lstatus_to_modtype); 8120 p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ? 8121 G_FW_PORT_CMD_MDIOADDR(ret) : -1; 8122 p->port_type = G_FW_PORT_CMD_PTYPE(ret); 8123 p->mod_type = G_FW_PORT_CMD_MODTYPE(ret); 8124 8125 init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap)); 8126 } 8127 8128 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 8129 if (ret < 0) 8130 return ret; 8131 8132 p->vi[0].viid = ret; 8133 if (chip_id(adap) <= CHELSIO_T5) 8134 p->vi[0].smt_idx = (ret & 0x7f) << 1; 8135 else 8136 p->vi[0].smt_idx = (ret & 0x7f); 8137 p->tx_chan = j; 8138 p->rx_chan_map = t4_get_mps_bg_map(adap, j); 8139 p->lport = j; 8140 p->vi[0].rss_size = rss_size; 8141 t4_os_set_hw_addr(adap, p->port_id, addr); 8142 8143 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8144 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 8145 V_FW_PARAMS_PARAM_YZ(p->vi[0].viid); 8146 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 8147 if (ret) 8148 p->vi[0].rss_base = 0xffff; 8149 else { 8150 /* MPASS((val >> 16) == rss_size); */ 8151 p->vi[0].rss_base = val & 0xffff; 8152 } 8153 8154 return 0; 8155 } 8156 8157 /** 8158 * t4_read_cimq_cfg - read CIM queue configuration 8159 * @adap: the adapter 8160 * @base: holds the queue base addresses in bytes 8161 * @size: holds the queue sizes in bytes 8162 * @thres: holds the queue full thresholds in bytes 8163 * 8164 * Returns the current configuration of the CIM queues, starting with 8165 * the IBQs, then the OBQs. 8166 */ 8167 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 8168 { 8169 unsigned int i, v; 8170 int cim_num_obq = adap->chip_params->cim_num_obq; 8171 8172 for (i = 0; i < CIM_NUM_IBQ; i++) { 8173 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 8174 V_QUENUMSELECT(i)); 8175 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8176 /* value is in 256-byte units */ 8177 *base++ = G_CIMQBASE(v) * 256; 8178 *size++ = G_CIMQSIZE(v) * 256; 8179 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 8180 } 8181 for (i = 0; i < cim_num_obq; i++) { 8182 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8183 V_QUENUMSELECT(i)); 8184 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8185 /* value is in 256-byte units */ 8186 *base++ = G_CIMQBASE(v) * 256; 8187 *size++ = G_CIMQSIZE(v) * 256; 8188 } 8189 } 8190 8191 /** 8192 * t4_read_cim_ibq - read the contents of a CIM inbound queue 8193 * @adap: the adapter 8194 * @qid: the queue index 8195 * @data: where to store the queue contents 8196 * @n: capacity of @data in 32-bit words 8197 * 8198 * Reads the contents of the selected CIM queue starting at address 0 up 8199 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8200 * error and the number of 32-bit words actually read on success. 8201 */ 8202 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8203 { 8204 int i, err, attempts; 8205 unsigned int addr; 8206 const unsigned int nwords = CIM_IBQ_SIZE * 4; 8207 8208 if (qid > 5 || (n & 3)) 8209 return -EINVAL; 8210 8211 addr = qid * nwords; 8212 if (n > nwords) 8213 n = nwords; 8214 8215 /* It might take 3-10ms before the IBQ debug read access is allowed. 8216 * Wait for 1 Sec with a delay of 1 usec. 8217 */ 8218 attempts = 1000000; 8219 8220 for (i = 0; i < n; i++, addr++) { 8221 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 8222 F_IBQDBGEN); 8223 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 8224 attempts, 1); 8225 if (err) 8226 return err; 8227 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 8228 } 8229 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 8230 return i; 8231 } 8232 8233 /** 8234 * t4_read_cim_obq - read the contents of a CIM outbound queue 8235 * @adap: the adapter 8236 * @qid: the queue index 8237 * @data: where to store the queue contents 8238 * @n: capacity of @data in 32-bit words 8239 * 8240 * Reads the contents of the selected CIM queue starting at address 0 up 8241 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8242 * error and the number of 32-bit words actually read on success. 8243 */ 8244 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8245 { 8246 int i, err; 8247 unsigned int addr, v, nwords; 8248 int cim_num_obq = adap->chip_params->cim_num_obq; 8249 8250 if ((qid > (cim_num_obq - 1)) || (n & 3)) 8251 return -EINVAL; 8252 8253 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8254 V_QUENUMSELECT(qid)); 8255 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8256 8257 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 8258 nwords = G_CIMQSIZE(v) * 64; /* same */ 8259 if (n > nwords) 8260 n = nwords; 8261 8262 for (i = 0; i < n; i++, addr++) { 8263 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 8264 F_OBQDBGEN); 8265 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 8266 2, 1); 8267 if (err) 8268 return err; 8269 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 8270 } 8271 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 8272 return i; 8273 } 8274 8275 enum { 8276 CIM_QCTL_BASE = 0, 8277 CIM_CTL_BASE = 0x2000, 8278 CIM_PBT_ADDR_BASE = 0x2800, 8279 CIM_PBT_LRF_BASE = 0x3000, 8280 CIM_PBT_DATA_BASE = 0x3800 8281 }; 8282 8283 /** 8284 * t4_cim_read - read a block from CIM internal address space 8285 * @adap: the adapter 8286 * @addr: the start address within the CIM address space 8287 * @n: number of words to read 8288 * @valp: where to store the result 8289 * 8290 * Reads a block of 4-byte words from the CIM intenal address space. 8291 */ 8292 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 8293 unsigned int *valp) 8294 { 8295 int ret = 0; 8296 8297 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8298 return -EBUSY; 8299 8300 for ( ; !ret && n--; addr += 4) { 8301 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 8302 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8303 0, 5, 2); 8304 if (!ret) 8305 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 8306 } 8307 return ret; 8308 } 8309 8310 /** 8311 * t4_cim_write - write a block into CIM internal address space 8312 * @adap: the adapter 8313 * @addr: the start address within the CIM address space 8314 * @n: number of words to write 8315 * @valp: set of values to write 8316 * 8317 * Writes a block of 4-byte words into the CIM intenal address space. 8318 */ 8319 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 8320 const unsigned int *valp) 8321 { 8322 int ret = 0; 8323 8324 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8325 return -EBUSY; 8326 8327 for ( ; !ret && n--; addr += 4) { 8328 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 8329 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 8330 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8331 0, 5, 2); 8332 } 8333 return ret; 8334 } 8335 8336 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 8337 unsigned int val) 8338 { 8339 return t4_cim_write(adap, addr, 1, &val); 8340 } 8341 8342 /** 8343 * t4_cim_ctl_read - read a block from CIM control region 8344 * @adap: the adapter 8345 * @addr: the start address within the CIM control region 8346 * @n: number of words to read 8347 * @valp: where to store the result 8348 * 8349 * Reads a block of 4-byte words from the CIM control region. 8350 */ 8351 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 8352 unsigned int *valp) 8353 { 8354 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 8355 } 8356 8357 /** 8358 * t4_cim_read_la - read CIM LA capture buffer 8359 * @adap: the adapter 8360 * @la_buf: where to store the LA data 8361 * @wrptr: the HW write pointer within the capture buffer 8362 * 8363 * Reads the contents of the CIM LA buffer with the most recent entry at 8364 * the end of the returned data and with the entry at @wrptr first. 8365 * We try to leave the LA in the running state we find it in. 8366 */ 8367 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 8368 { 8369 int i, ret; 8370 unsigned int cfg, val, idx; 8371 8372 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 8373 if (ret) 8374 return ret; 8375 8376 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 8377 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 8378 if (ret) 8379 return ret; 8380 } 8381 8382 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 8383 if (ret) 8384 goto restart; 8385 8386 idx = G_UPDBGLAWRPTR(val); 8387 if (wrptr) 8388 *wrptr = idx; 8389 8390 for (i = 0; i < adap->params.cim_la_size; i++) { 8391 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 8392 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 8393 if (ret) 8394 break; 8395 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 8396 if (ret) 8397 break; 8398 if (val & F_UPDBGLARDEN) { 8399 ret = -ETIMEDOUT; 8400 break; 8401 } 8402 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 8403 if (ret) 8404 break; 8405 8406 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */ 8407 idx = (idx + 1) & M_UPDBGLARDPTR; 8408 /* 8409 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 8410 * identify the 32-bit portion of the full 312-bit data 8411 */ 8412 if (is_t6(adap)) 8413 while ((idx & 0xf) > 9) 8414 idx = (idx + 1) % M_UPDBGLARDPTR; 8415 } 8416 restart: 8417 if (cfg & F_UPDBGLAEN) { 8418 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 8419 cfg & ~F_UPDBGLARDEN); 8420 if (!ret) 8421 ret = r; 8422 } 8423 return ret; 8424 } 8425 8426 /** 8427 * t4_tp_read_la - read TP LA capture buffer 8428 * @adap: the adapter 8429 * @la_buf: where to store the LA data 8430 * @wrptr: the HW write pointer within the capture buffer 8431 * 8432 * Reads the contents of the TP LA buffer with the most recent entry at 8433 * the end of the returned data and with the entry at @wrptr first. 8434 * We leave the LA in the running state we find it in. 8435 */ 8436 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 8437 { 8438 bool last_incomplete; 8439 unsigned int i, cfg, val, idx; 8440 8441 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 8442 if (cfg & F_DBGLAENABLE) /* freeze LA */ 8443 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 8444 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 8445 8446 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 8447 idx = G_DBGLAWPTR(val); 8448 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 8449 if (last_incomplete) 8450 idx = (idx + 1) & M_DBGLARPTR; 8451 if (wrptr) 8452 *wrptr = idx; 8453 8454 val &= 0xffff; 8455 val &= ~V_DBGLARPTR(M_DBGLARPTR); 8456 val |= adap->params.tp.la_mask; 8457 8458 for (i = 0; i < TPLA_SIZE; i++) { 8459 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 8460 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 8461 idx = (idx + 1) & M_DBGLARPTR; 8462 } 8463 8464 /* Wipe out last entry if it isn't valid */ 8465 if (last_incomplete) 8466 la_buf[TPLA_SIZE - 1] = ~0ULL; 8467 8468 if (cfg & F_DBGLAENABLE) /* restore running state */ 8469 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 8470 cfg | adap->params.tp.la_mask); 8471 } 8472 8473 /* 8474 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 8475 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 8476 * state for more than the Warning Threshold then we'll issue a warning about 8477 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 8478 * appears to be hung every Warning Repeat second till the situation clears. 8479 * If the situation clears, we'll note that as well. 8480 */ 8481 #define SGE_IDMA_WARN_THRESH 1 8482 #define SGE_IDMA_WARN_REPEAT 300 8483 8484 /** 8485 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 8486 * @adapter: the adapter 8487 * @idma: the adapter IDMA Monitor state 8488 * 8489 * Initialize the state of an SGE Ingress DMA Monitor. 8490 */ 8491 void t4_idma_monitor_init(struct adapter *adapter, 8492 struct sge_idma_monitor_state *idma) 8493 { 8494 /* Initialize the state variables for detecting an SGE Ingress DMA 8495 * hang. The SGE has internal counters which count up on each clock 8496 * tick whenever the SGE finds its Ingress DMA State Engines in the 8497 * same state they were on the previous clock tick. The clock used is 8498 * the Core Clock so we have a limit on the maximum "time" they can 8499 * record; typically a very small number of seconds. For instance, 8500 * with a 600MHz Core Clock, we can only count up to a bit more than 8501 * 7s. So we'll synthesize a larger counter in order to not run the 8502 * risk of having the "timers" overflow and give us the flexibility to 8503 * maintain a Hung SGE State Machine of our own which operates across 8504 * a longer time frame. 8505 */ 8506 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 8507 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 8508 } 8509 8510 /** 8511 * t4_idma_monitor - monitor SGE Ingress DMA state 8512 * @adapter: the adapter 8513 * @idma: the adapter IDMA Monitor state 8514 * @hz: number of ticks/second 8515 * @ticks: number of ticks since the last IDMA Monitor call 8516 */ 8517 void t4_idma_monitor(struct adapter *adapter, 8518 struct sge_idma_monitor_state *idma, 8519 int hz, int ticks) 8520 { 8521 int i, idma_same_state_cnt[2]; 8522 8523 /* Read the SGE Debug Ingress DMA Same State Count registers. These 8524 * are counters inside the SGE which count up on each clock when the 8525 * SGE finds its Ingress DMA State Engines in the same states they 8526 * were in the previous clock. The counters will peg out at 8527 * 0xffffffff without wrapping around so once they pass the 1s 8528 * threshold they'll stay above that till the IDMA state changes. 8529 */ 8530 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 8531 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 8532 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8533 8534 for (i = 0; i < 2; i++) { 8535 u32 debug0, debug11; 8536 8537 /* If the Ingress DMA Same State Counter ("timer") is less 8538 * than 1s, then we can reset our synthesized Stall Timer and 8539 * continue. If we have previously emitted warnings about a 8540 * potential stalled Ingress Queue, issue a note indicating 8541 * that the Ingress Queue has resumed forward progress. 8542 */ 8543 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 8544 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 8545 CH_WARN(adapter, "SGE idma%d, queue %u, " 8546 "resumed after %d seconds\n", 8547 i, idma->idma_qid[i], 8548 idma->idma_stalled[i]/hz); 8549 idma->idma_stalled[i] = 0; 8550 continue; 8551 } 8552 8553 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 8554 * domain. The first time we get here it'll be because we 8555 * passed the 1s Threshold; each additional time it'll be 8556 * because the RX Timer Callback is being fired on its regular 8557 * schedule. 8558 * 8559 * If the stall is below our Potential Hung Ingress Queue 8560 * Warning Threshold, continue. 8561 */ 8562 if (idma->idma_stalled[i] == 0) { 8563 idma->idma_stalled[i] = hz; 8564 idma->idma_warn[i] = 0; 8565 } else { 8566 idma->idma_stalled[i] += ticks; 8567 idma->idma_warn[i] -= ticks; 8568 } 8569 8570 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 8571 continue; 8572 8573 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 8574 */ 8575 if (idma->idma_warn[i] > 0) 8576 continue; 8577 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 8578 8579 /* Read and save the SGE IDMA State and Queue ID information. 8580 * We do this every time in case it changes across time ... 8581 * can't be too careful ... 8582 */ 8583 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 8584 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8585 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 8586 8587 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 8588 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8589 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 8590 8591 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 8592 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 8593 i, idma->idma_qid[i], idma->idma_state[i], 8594 idma->idma_stalled[i]/hz, 8595 debug0, debug11); 8596 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 8597 } 8598 } 8599 8600 /** 8601 * t4_read_pace_tbl - read the pace table 8602 * @adap: the adapter 8603 * @pace_vals: holds the returned values 8604 * 8605 * Returns the values of TP's pace table in microseconds. 8606 */ 8607 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 8608 { 8609 unsigned int i, v; 8610 8611 for (i = 0; i < NTX_SCHED; i++) { 8612 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 8613 v = t4_read_reg(adap, A_TP_PACE_TABLE); 8614 pace_vals[i] = dack_ticks_to_usec(adap, v); 8615 } 8616 } 8617 8618 /** 8619 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 8620 * @adap: the adapter 8621 * @sched: the scheduler index 8622 * @kbps: the byte rate in Kbps 8623 * @ipg: the interpacket delay in tenths of nanoseconds 8624 * 8625 * Return the current configuration of a HW Tx scheduler. 8626 */ 8627 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 8628 unsigned int *ipg) 8629 { 8630 unsigned int v, addr, bpt, cpt; 8631 8632 if (kbps) { 8633 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 8634 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 8635 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 8636 if (sched & 1) 8637 v >>= 16; 8638 bpt = (v >> 8) & 0xff; 8639 cpt = v & 0xff; 8640 if (!cpt) 8641 *kbps = 0; /* scheduler disabled */ 8642 else { 8643 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 8644 *kbps = (v * bpt) / 125; 8645 } 8646 } 8647 if (ipg) { 8648 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 8649 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 8650 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 8651 if (sched & 1) 8652 v >>= 16; 8653 v &= 0xffff; 8654 *ipg = (10000 * v) / core_ticks_per_usec(adap); 8655 } 8656 } 8657 8658 /** 8659 * t4_load_cfg - download config file 8660 * @adap: the adapter 8661 * @cfg_data: the cfg text file to write 8662 * @size: text file size 8663 * 8664 * Write the supplied config text file to the card's serial flash. 8665 */ 8666 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 8667 { 8668 int ret, i, n, cfg_addr; 8669 unsigned int addr; 8670 unsigned int flash_cfg_start_sec; 8671 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 8672 8673 cfg_addr = t4_flash_cfg_addr(adap); 8674 if (cfg_addr < 0) 8675 return cfg_addr; 8676 8677 addr = cfg_addr; 8678 flash_cfg_start_sec = addr / SF_SEC_SIZE; 8679 8680 if (size > FLASH_CFG_MAX_SIZE) { 8681 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 8682 FLASH_CFG_MAX_SIZE); 8683 return -EFBIG; 8684 } 8685 8686 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 8687 sf_sec_size); 8688 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 8689 flash_cfg_start_sec + i - 1); 8690 /* 8691 * If size == 0 then we're simply erasing the FLASH sectors associated 8692 * with the on-adapter Firmware Configuration File. 8693 */ 8694 if (ret || size == 0) 8695 goto out; 8696 8697 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 8698 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 8699 if ( (size - i) < SF_PAGE_SIZE) 8700 n = size - i; 8701 else 8702 n = SF_PAGE_SIZE; 8703 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 8704 if (ret) 8705 goto out; 8706 8707 addr += SF_PAGE_SIZE; 8708 cfg_data += SF_PAGE_SIZE; 8709 } 8710 8711 out: 8712 if (ret) 8713 CH_ERR(adap, "config file %s failed %d\n", 8714 (size == 0 ? "clear" : "download"), ret); 8715 return ret; 8716 } 8717 8718 /** 8719 * t5_fw_init_extern_mem - initialize the external memory 8720 * @adap: the adapter 8721 * 8722 * Initializes the external memory on T5. 8723 */ 8724 int t5_fw_init_extern_mem(struct adapter *adap) 8725 { 8726 u32 params[1], val[1]; 8727 int ret; 8728 8729 if (!is_t5(adap)) 8730 return 0; 8731 8732 val[0] = 0xff; /* Initialize all MCs */ 8733 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8734 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 8735 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 8736 FW_CMD_MAX_TIMEOUT); 8737 8738 return ret; 8739 } 8740 8741 /* BIOS boot headers */ 8742 typedef struct pci_expansion_rom_header { 8743 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 8744 u8 reserved[22]; /* Reserved per processor Architecture data */ 8745 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 8746 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 8747 8748 /* Legacy PCI Expansion ROM Header */ 8749 typedef struct legacy_pci_expansion_rom_header { 8750 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 8751 u8 size512; /* Current Image Size in units of 512 bytes */ 8752 u8 initentry_point[4]; 8753 u8 cksum; /* Checksum computed on the entire Image */ 8754 u8 reserved[16]; /* Reserved */ 8755 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 8756 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 8757 8758 /* EFI PCI Expansion ROM Header */ 8759 typedef struct efi_pci_expansion_rom_header { 8760 u8 signature[2]; // ROM signature. The value 0xaa55 8761 u8 initialization_size[2]; /* Units 512. Includes this header */ 8762 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 8763 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 8764 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 8765 u8 compression_type[2]; /* Compression type. */ 8766 /* 8767 * Compression type definition 8768 * 0x0: uncompressed 8769 * 0x1: Compressed 8770 * 0x2-0xFFFF: Reserved 8771 */ 8772 u8 reserved[8]; /* Reserved */ 8773 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 8774 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 8775 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 8776 8777 /* PCI Data Structure Format */ 8778 typedef struct pcir_data_structure { /* PCI Data Structure */ 8779 u8 signature[4]; /* Signature. The string "PCIR" */ 8780 u8 vendor_id[2]; /* Vendor Identification */ 8781 u8 device_id[2]; /* Device Identification */ 8782 u8 vital_product[2]; /* Pointer to Vital Product Data */ 8783 u8 length[2]; /* PCIR Data Structure Length */ 8784 u8 revision; /* PCIR Data Structure Revision */ 8785 u8 class_code[3]; /* Class Code */ 8786 u8 image_length[2]; /* Image Length. Multiple of 512B */ 8787 u8 code_revision[2]; /* Revision Level of Code/Data */ 8788 u8 code_type; /* Code Type. */ 8789 /* 8790 * PCI Expansion ROM Code Types 8791 * 0x00: Intel IA-32, PC-AT compatible. Legacy 8792 * 0x01: Open Firmware standard for PCI. FCODE 8793 * 0x02: Hewlett-Packard PA RISC. HP reserved 8794 * 0x03: EFI Image. EFI 8795 * 0x04-0xFF: Reserved. 8796 */ 8797 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 8798 u8 reserved[2]; /* Reserved */ 8799 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 8800 8801 /* BOOT constants */ 8802 enum { 8803 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 8804 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 8805 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 8806 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 8807 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 8808 VENDOR_ID = 0x1425, /* Vendor ID */ 8809 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 8810 }; 8811 8812 /* 8813 * modify_device_id - Modifies the device ID of the Boot BIOS image 8814 * @adatper: the device ID to write. 8815 * @boot_data: the boot image to modify. 8816 * 8817 * Write the supplied device ID to the boot BIOS image. 8818 */ 8819 static void modify_device_id(int device_id, u8 *boot_data) 8820 { 8821 legacy_pci_exp_rom_header_t *header; 8822 pcir_data_t *pcir_header; 8823 u32 cur_header = 0; 8824 8825 /* 8826 * Loop through all chained images and change the device ID's 8827 */ 8828 while (1) { 8829 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 8830 pcir_header = (pcir_data_t *) &boot_data[cur_header + 8831 le16_to_cpu(*(u16*)header->pcir_offset)]; 8832 8833 /* 8834 * Only modify the Device ID if code type is Legacy or HP. 8835 * 0x00: Okay to modify 8836 * 0x01: FCODE. Do not be modify 8837 * 0x03: Okay to modify 8838 * 0x04-0xFF: Do not modify 8839 */ 8840 if (pcir_header->code_type == 0x00) { 8841 u8 csum = 0; 8842 int i; 8843 8844 /* 8845 * Modify Device ID to match current adatper 8846 */ 8847 *(u16*) pcir_header->device_id = device_id; 8848 8849 /* 8850 * Set checksum temporarily to 0. 8851 * We will recalculate it later. 8852 */ 8853 header->cksum = 0x0; 8854 8855 /* 8856 * Calculate and update checksum 8857 */ 8858 for (i = 0; i < (header->size512 * 512); i++) 8859 csum += (u8)boot_data[cur_header + i]; 8860 8861 /* 8862 * Invert summed value to create the checksum 8863 * Writing new checksum value directly to the boot data 8864 */ 8865 boot_data[cur_header + 7] = -csum; 8866 8867 } else if (pcir_header->code_type == 0x03) { 8868 8869 /* 8870 * Modify Device ID to match current adatper 8871 */ 8872 *(u16*) pcir_header->device_id = device_id; 8873 8874 } 8875 8876 8877 /* 8878 * Check indicator element to identify if this is the last 8879 * image in the ROM. 8880 */ 8881 if (pcir_header->indicator & 0x80) 8882 break; 8883 8884 /* 8885 * Move header pointer up to the next image in the ROM. 8886 */ 8887 cur_header += header->size512 * 512; 8888 } 8889 } 8890 8891 /* 8892 * t4_load_boot - download boot flash 8893 * @adapter: the adapter 8894 * @boot_data: the boot image to write 8895 * @boot_addr: offset in flash to write boot_data 8896 * @size: image size 8897 * 8898 * Write the supplied boot image to the card's serial flash. 8899 * The boot image has the following sections: a 28-byte header and the 8900 * boot image. 8901 */ 8902 int t4_load_boot(struct adapter *adap, u8 *boot_data, 8903 unsigned int boot_addr, unsigned int size) 8904 { 8905 pci_exp_rom_header_t *header; 8906 int pcir_offset ; 8907 pcir_data_t *pcir_header; 8908 int ret, addr; 8909 uint16_t device_id; 8910 unsigned int i; 8911 unsigned int boot_sector = (boot_addr * 1024 ); 8912 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 8913 8914 /* 8915 * Make sure the boot image does not encroach on the firmware region 8916 */ 8917 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 8918 CH_ERR(adap, "boot image encroaching on firmware region\n"); 8919 return -EFBIG; 8920 } 8921 8922 /* 8923 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 8924 * and Boot configuration data sections. These 3 boot sections span 8925 * sectors 0 to 7 in flash and live right before the FW image location. 8926 */ 8927 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 8928 sf_sec_size); 8929 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 8930 (boot_sector >> 16) + i - 1); 8931 8932 /* 8933 * If size == 0 then we're simply erasing the FLASH sectors associated 8934 * with the on-adapter option ROM file 8935 */ 8936 if (ret || (size == 0)) 8937 goto out; 8938 8939 /* Get boot header */ 8940 header = (pci_exp_rom_header_t *)boot_data; 8941 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 8942 /* PCIR Data Structure */ 8943 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 8944 8945 /* 8946 * Perform some primitive sanity testing to avoid accidentally 8947 * writing garbage over the boot sectors. We ought to check for 8948 * more but it's not worth it for now ... 8949 */ 8950 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 8951 CH_ERR(adap, "boot image too small/large\n"); 8952 return -EFBIG; 8953 } 8954 8955 #ifndef CHELSIO_T4_DIAGS 8956 /* 8957 * Check BOOT ROM header signature 8958 */ 8959 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 8960 CH_ERR(adap, "Boot image missing signature\n"); 8961 return -EINVAL; 8962 } 8963 8964 /* 8965 * Check PCI header signature 8966 */ 8967 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 8968 CH_ERR(adap, "PCI header missing signature\n"); 8969 return -EINVAL; 8970 } 8971 8972 /* 8973 * Check Vendor ID matches Chelsio ID 8974 */ 8975 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 8976 CH_ERR(adap, "Vendor ID missing signature\n"); 8977 return -EINVAL; 8978 } 8979 #endif 8980 8981 /* 8982 * Retrieve adapter's device ID 8983 */ 8984 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 8985 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 8986 device_id = device_id & 0xf0ff; 8987 8988 /* 8989 * Check PCIE Device ID 8990 */ 8991 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 8992 /* 8993 * Change the device ID in the Boot BIOS image to match 8994 * the Device ID of the current adapter. 8995 */ 8996 modify_device_id(device_id, boot_data); 8997 } 8998 8999 /* 9000 * Skip over the first SF_PAGE_SIZE worth of data and write it after 9001 * we finish copying the rest of the boot image. This will ensure 9002 * that the BIOS boot header will only be written if the boot image 9003 * was written in full. 9004 */ 9005 addr = boot_sector; 9006 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 9007 addr += SF_PAGE_SIZE; 9008 boot_data += SF_PAGE_SIZE; 9009 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 9010 if (ret) 9011 goto out; 9012 } 9013 9014 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 9015 (const u8 *)header, 0); 9016 9017 out: 9018 if (ret) 9019 CH_ERR(adap, "boot image download failed, error %d\n", ret); 9020 return ret; 9021 } 9022 9023 /* 9024 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 9025 * @adapter: the adapter 9026 * 9027 * Return the address within the flash where the OptionROM Configuration 9028 * is stored, or an error if the device FLASH is too small to contain 9029 * a OptionROM Configuration. 9030 */ 9031 static int t4_flash_bootcfg_addr(struct adapter *adapter) 9032 { 9033 /* 9034 * If the device FLASH isn't large enough to hold a Firmware 9035 * Configuration File, return an error. 9036 */ 9037 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 9038 return -ENOSPC; 9039 9040 return FLASH_BOOTCFG_START; 9041 } 9042 9043 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 9044 { 9045 int ret, i, n, cfg_addr; 9046 unsigned int addr; 9047 unsigned int flash_cfg_start_sec; 9048 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9049 9050 cfg_addr = t4_flash_bootcfg_addr(adap); 9051 if (cfg_addr < 0) 9052 return cfg_addr; 9053 9054 addr = cfg_addr; 9055 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9056 9057 if (size > FLASH_BOOTCFG_MAX_SIZE) { 9058 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 9059 FLASH_BOOTCFG_MAX_SIZE); 9060 return -EFBIG; 9061 } 9062 9063 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 9064 sf_sec_size); 9065 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9066 flash_cfg_start_sec + i - 1); 9067 9068 /* 9069 * If size == 0 then we're simply erasing the FLASH sectors associated 9070 * with the on-adapter OptionROM Configuration File. 9071 */ 9072 if (ret || size == 0) 9073 goto out; 9074 9075 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9076 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9077 if ( (size - i) < SF_PAGE_SIZE) 9078 n = size - i; 9079 else 9080 n = SF_PAGE_SIZE; 9081 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 9082 if (ret) 9083 goto out; 9084 9085 addr += SF_PAGE_SIZE; 9086 cfg_data += SF_PAGE_SIZE; 9087 } 9088 9089 out: 9090 if (ret) 9091 CH_ERR(adap, "boot config data %s failed %d\n", 9092 (size == 0 ? "clear" : "download"), ret); 9093 return ret; 9094 } 9095 9096 /** 9097 * t4_set_filter_mode - configure the optional components of filter tuples 9098 * @adap: the adapter 9099 * @mode_map: a bitmap selcting which optional filter components to enable 9100 * 9101 * Sets the filter mode by selecting the optional components to enable 9102 * in filter tuples. Returns 0 on success and a negative error if the 9103 * requested mode needs more bits than are available for optional 9104 * components. 9105 */ 9106 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map) 9107 { 9108 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 9109 9110 int i, nbits = 0; 9111 9112 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 9113 if (mode_map & (1 << i)) 9114 nbits += width[i]; 9115 if (nbits > FILTER_OPT_LEN) 9116 return -EINVAL; 9117 if (t4_use_ldst(adap)) 9118 t4_fw_tp_pio_rw(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, 0); 9119 else 9120 t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, &mode_map, 9121 1, A_TP_VLAN_PRI_MAP); 9122 read_filter_mode_and_ingress_config(adap); 9123 9124 return 0; 9125 } 9126 9127 /** 9128 * t4_clr_port_stats - clear port statistics 9129 * @adap: the adapter 9130 * @idx: the port index 9131 * 9132 * Clear HW statistics for the given port. 9133 */ 9134 void t4_clr_port_stats(struct adapter *adap, int idx) 9135 { 9136 unsigned int i; 9137 u32 bgmap = t4_get_mps_bg_map(adap, idx); 9138 u32 port_base_addr; 9139 9140 if (is_t4(adap)) 9141 port_base_addr = PORT_BASE(idx); 9142 else 9143 port_base_addr = T5_PORT_BASE(idx); 9144 9145 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 9146 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 9147 t4_write_reg(adap, port_base_addr + i, 0); 9148 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 9149 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 9150 t4_write_reg(adap, port_base_addr + i, 0); 9151 for (i = 0; i < 4; i++) 9152 if (bgmap & (1 << i)) { 9153 t4_write_reg(adap, 9154 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 9155 t4_write_reg(adap, 9156 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 9157 } 9158 } 9159 9160 /** 9161 * t4_i2c_rd - read I2C data from adapter 9162 * @adap: the adapter 9163 * @port: Port number if per-port device; <0 if not 9164 * @devid: per-port device ID or absolute device ID 9165 * @offset: byte offset into device I2C space 9166 * @len: byte length of I2C space data 9167 * @buf: buffer in which to return I2C data 9168 * 9169 * Reads the I2C data from the indicated device and location. 9170 */ 9171 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 9172 int port, unsigned int devid, 9173 unsigned int offset, unsigned int len, 9174 u8 *buf) 9175 { 9176 u32 ldst_addrspace; 9177 struct fw_ldst_cmd ldst; 9178 int ret; 9179 9180 if (port >= 4 || 9181 devid >= 256 || 9182 offset >= 256 || 9183 len > sizeof ldst.u.i2c.data) 9184 return -EINVAL; 9185 9186 memset(&ldst, 0, sizeof ldst); 9187 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9188 ldst.op_to_addrspace = 9189 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9190 F_FW_CMD_REQUEST | 9191 F_FW_CMD_READ | 9192 ldst_addrspace); 9193 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9194 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9195 ldst.u.i2c.did = devid; 9196 ldst.u.i2c.boffset = offset; 9197 ldst.u.i2c.blen = len; 9198 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9199 if (!ret) 9200 memcpy(buf, ldst.u.i2c.data, len); 9201 return ret; 9202 } 9203 9204 /** 9205 * t4_i2c_wr - write I2C data to adapter 9206 * @adap: the adapter 9207 * @port: Port number if per-port device; <0 if not 9208 * @devid: per-port device ID or absolute device ID 9209 * @offset: byte offset into device I2C space 9210 * @len: byte length of I2C space data 9211 * @buf: buffer containing new I2C data 9212 * 9213 * Write the I2C data to the indicated device and location. 9214 */ 9215 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 9216 int port, unsigned int devid, 9217 unsigned int offset, unsigned int len, 9218 u8 *buf) 9219 { 9220 u32 ldst_addrspace; 9221 struct fw_ldst_cmd ldst; 9222 9223 if (port >= 4 || 9224 devid >= 256 || 9225 offset >= 256 || 9226 len > sizeof ldst.u.i2c.data) 9227 return -EINVAL; 9228 9229 memset(&ldst, 0, sizeof ldst); 9230 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9231 ldst.op_to_addrspace = 9232 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9233 F_FW_CMD_REQUEST | 9234 F_FW_CMD_WRITE | 9235 ldst_addrspace); 9236 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9237 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9238 ldst.u.i2c.did = devid; 9239 ldst.u.i2c.boffset = offset; 9240 ldst.u.i2c.blen = len; 9241 memcpy(ldst.u.i2c.data, buf, len); 9242 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9243 } 9244 9245 /** 9246 * t4_sge_ctxt_rd - read an SGE context through FW 9247 * @adap: the adapter 9248 * @mbox: mailbox to use for the FW command 9249 * @cid: the context id 9250 * @ctype: the context type 9251 * @data: where to store the context data 9252 * 9253 * Issues a FW command through the given mailbox to read an SGE context. 9254 */ 9255 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 9256 enum ctxt_type ctype, u32 *data) 9257 { 9258 int ret; 9259 struct fw_ldst_cmd c; 9260 9261 if (ctype == CTXT_EGRESS) 9262 ret = FW_LDST_ADDRSPC_SGE_EGRC; 9263 else if (ctype == CTXT_INGRESS) 9264 ret = FW_LDST_ADDRSPC_SGE_INGC; 9265 else if (ctype == CTXT_FLM) 9266 ret = FW_LDST_ADDRSPC_SGE_FLMC; 9267 else 9268 ret = FW_LDST_ADDRSPC_SGE_CONMC; 9269 9270 memset(&c, 0, sizeof(c)); 9271 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9272 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9273 V_FW_LDST_CMD_ADDRSPACE(ret)); 9274 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 9275 c.u.idctxt.physid = cpu_to_be32(cid); 9276 9277 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 9278 if (ret == 0) { 9279 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 9280 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 9281 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 9282 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 9283 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 9284 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 9285 } 9286 return ret; 9287 } 9288 9289 /** 9290 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 9291 * @adap: the adapter 9292 * @cid: the context id 9293 * @ctype: the context type 9294 * @data: where to store the context data 9295 * 9296 * Reads an SGE context directly, bypassing FW. This is only for 9297 * debugging when FW is unavailable. 9298 */ 9299 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 9300 u32 *data) 9301 { 9302 int i, ret; 9303 9304 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 9305 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 9306 if (!ret) 9307 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 9308 *data++ = t4_read_reg(adap, i); 9309 return ret; 9310 } 9311 9312 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 9313 int sleep_ok) 9314 { 9315 struct fw_sched_cmd cmd; 9316 9317 memset(&cmd, 0, sizeof(cmd)); 9318 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9319 F_FW_CMD_REQUEST | 9320 F_FW_CMD_WRITE); 9321 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9322 9323 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 9324 cmd.u.config.type = type; 9325 cmd.u.config.minmaxen = minmaxen; 9326 9327 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9328 NULL, sleep_ok); 9329 } 9330 9331 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 9332 int rateunit, int ratemode, int channel, int cl, 9333 int minrate, int maxrate, int weight, int pktsize, 9334 int sleep_ok) 9335 { 9336 struct fw_sched_cmd cmd; 9337 9338 memset(&cmd, 0, sizeof(cmd)); 9339 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9340 F_FW_CMD_REQUEST | 9341 F_FW_CMD_WRITE); 9342 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9343 9344 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9345 cmd.u.params.type = type; 9346 cmd.u.params.level = level; 9347 cmd.u.params.mode = mode; 9348 cmd.u.params.ch = channel; 9349 cmd.u.params.cl = cl; 9350 cmd.u.params.unit = rateunit; 9351 cmd.u.params.rate = ratemode; 9352 cmd.u.params.min = cpu_to_be32(minrate); 9353 cmd.u.params.max = cpu_to_be32(maxrate); 9354 cmd.u.params.weight = cpu_to_be16(weight); 9355 cmd.u.params.pktsize = cpu_to_be16(pktsize); 9356 9357 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9358 NULL, sleep_ok); 9359 } 9360 9361 /* 9362 * t4_config_watchdog - configure (enable/disable) a watchdog timer 9363 * @adapter: the adapter 9364 * @mbox: mailbox to use for the FW command 9365 * @pf: the PF owning the queue 9366 * @vf: the VF owning the queue 9367 * @timeout: watchdog timeout in ms 9368 * @action: watchdog timer / action 9369 * 9370 * There are separate watchdog timers for each possible watchdog 9371 * action. Configure one of the watchdog timers by setting a non-zero 9372 * timeout. Disable a watchdog timer by using a timeout of zero. 9373 */ 9374 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 9375 unsigned int pf, unsigned int vf, 9376 unsigned int timeout, unsigned int action) 9377 { 9378 struct fw_watchdog_cmd wdog; 9379 unsigned int ticks; 9380 9381 /* 9382 * The watchdog command expects a timeout in units of 10ms so we need 9383 * to convert it here (via rounding) and force a minimum of one 10ms 9384 * "tick" if the timeout is non-zero but the conversion results in 0 9385 * ticks. 9386 */ 9387 ticks = (timeout + 5)/10; 9388 if (timeout && !ticks) 9389 ticks = 1; 9390 9391 memset(&wdog, 0, sizeof wdog); 9392 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 9393 F_FW_CMD_REQUEST | 9394 F_FW_CMD_WRITE | 9395 V_FW_PARAMS_CMD_PFN(pf) | 9396 V_FW_PARAMS_CMD_VFN(vf)); 9397 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 9398 wdog.timeout = cpu_to_be32(ticks); 9399 wdog.action = cpu_to_be32(action); 9400 9401 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 9402 } 9403 9404 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 9405 { 9406 struct fw_devlog_cmd devlog_cmd; 9407 int ret; 9408 9409 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 9410 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9411 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9412 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9413 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 9414 sizeof(devlog_cmd), &devlog_cmd); 9415 if (ret) 9416 return ret; 9417 9418 *level = devlog_cmd.level; 9419 return 0; 9420 } 9421 9422 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 9423 { 9424 struct fw_devlog_cmd devlog_cmd; 9425 9426 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 9427 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9428 F_FW_CMD_REQUEST | 9429 F_FW_CMD_WRITE); 9430 devlog_cmd.level = level; 9431 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9432 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 9433 sizeof(devlog_cmd), &devlog_cmd); 9434 } 9435