1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) 215 CH_ERR(adap, "Firmware reports adapter error: %s\n", 216 reason[G_PCIE_FW_EVAL(pcie_fw)]); 217 } 218 219 /* 220 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 221 */ 222 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 223 u32 mbox_addr) 224 { 225 for ( ; nflit; nflit--, mbox_addr += 8) 226 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 227 } 228 229 /* 230 * Handle a FW assertion reported in a mailbox. 231 */ 232 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 233 { 234 CH_ALERT(adap, 235 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 236 asrt->u.assert.filename_0_7, 237 be32_to_cpu(asrt->u.assert.line), 238 be32_to_cpu(asrt->u.assert.x), 239 be32_to_cpu(asrt->u.assert.y)); 240 } 241 242 #define X_CIM_PF_NOACCESS 0xeeeeeeee 243 /** 244 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 245 * @adap: the adapter 246 * @mbox: index of the mailbox to use 247 * @cmd: the command to write 248 * @size: command length in bytes 249 * @rpl: where to optionally store the reply 250 * @sleep_ok: if true we may sleep while awaiting command completion 251 * @timeout: time to wait for command to finish before timing out 252 * (negative implies @sleep_ok=false) 253 * 254 * Sends the given command to FW through the selected mailbox and waits 255 * for the FW to execute the command. If @rpl is not %NULL it is used to 256 * store the FW's reply to the command. The command and its optional 257 * reply are of the same length. Some FW commands like RESET and 258 * INITIALIZE can take a considerable amount of time to execute. 259 * @sleep_ok determines whether we may sleep while awaiting the response. 260 * If sleeping is allowed we use progressive backoff otherwise we spin. 261 * Note that passing in a negative @timeout is an alternate mechanism 262 * for specifying @sleep_ok=false. This is useful when a higher level 263 * interface allows for specification of @timeout but not @sleep_ok ... 264 * 265 * The return value is 0 on success or a negative errno on failure. A 266 * failure can happen either because we are not able to execute the 267 * command or FW executes it but signals an error. In the latter case 268 * the return value is the error code indicated by FW (negated). 269 */ 270 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 271 int size, void *rpl, bool sleep_ok, int timeout) 272 { 273 /* 274 * We delay in small increments at first in an effort to maintain 275 * responsiveness for simple, fast executing commands but then back 276 * off to larger delays to a maximum retry delay. 277 */ 278 static const int delay[] = { 279 1, 1, 3, 5, 10, 10, 20, 50, 100 280 }; 281 u32 v; 282 u64 res; 283 int i, ms, delay_idx, ret; 284 const __be64 *p = cmd; 285 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 286 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 287 u32 ctl; 288 __be64 cmd_rpl[MBOX_LEN/8]; 289 u32 pcie_fw; 290 291 if (adap->flags & CHK_MBOX_ACCESS) 292 ASSERT_SYNCHRONIZED_OP(adap); 293 294 if ((size & 15) || size > MBOX_LEN) 295 return -EINVAL; 296 297 if (adap->flags & IS_VF) { 298 if (is_t6(adap)) 299 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 300 else 301 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 302 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 303 } 304 305 /* 306 * If we have a negative timeout, that implies that we can't sleep. 307 */ 308 if (timeout < 0) { 309 sleep_ok = false; 310 timeout = -timeout; 311 } 312 313 /* 314 * Attempt to gain access to the mailbox. 315 */ 316 for (i = 0; i < 4; i++) { 317 ctl = t4_read_reg(adap, ctl_reg); 318 v = G_MBOWNER(ctl); 319 if (v != X_MBOWNER_NONE) 320 break; 321 } 322 323 /* 324 * If we were unable to gain access, dequeue ourselves from the 325 * mailbox atomic access list and report the error to our caller. 326 */ 327 if (v != X_MBOWNER_PL) { 328 t4_report_fw_error(adap); 329 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 330 return ret; 331 } 332 333 /* 334 * If we gain ownership of the mailbox and there's a "valid" message 335 * in it, this is likely an asynchronous error message from the 336 * firmware. So we'll report that and then proceed on with attempting 337 * to issue our own command ... which may well fail if the error 338 * presaged the firmware crashing ... 339 */ 340 if (ctl & F_MBMSGVALID) { 341 CH_ERR(adap, "found VALID command in mbox %u: %016llx %016llx " 342 "%016llx %016llx %016llx %016llx %016llx %016llx\n", 343 mbox, (unsigned long long)t4_read_reg64(adap, data_reg), 344 (unsigned long long)t4_read_reg64(adap, data_reg + 8), 345 (unsigned long long)t4_read_reg64(adap, data_reg + 16), 346 (unsigned long long)t4_read_reg64(adap, data_reg + 24), 347 (unsigned long long)t4_read_reg64(adap, data_reg + 32), 348 (unsigned long long)t4_read_reg64(adap, data_reg + 40), 349 (unsigned long long)t4_read_reg64(adap, data_reg + 48), 350 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); 351 } 352 353 /* 354 * Copy in the new mailbox command and send it on its way ... 355 */ 356 for (i = 0; i < size; i += 8, p++) 357 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); 358 359 if (adap->flags & IS_VF) { 360 /* 361 * For the VFs, the Mailbox Data "registers" are 362 * actually backed by T4's "MA" interface rather than 363 * PL Registers (as is the case for the PFs). Because 364 * these are in different coherency domains, the write 365 * to the VF's PL-register-backed Mailbox Control can 366 * race in front of the writes to the MA-backed VF 367 * Mailbox Data "registers". So we need to do a 368 * read-back on at least one byte of the VF Mailbox 369 * Data registers before doing the write to the VF 370 * Mailbox Control register. 371 */ 372 t4_read_reg(adap, data_reg); 373 } 374 375 CH_DUMP_MBOX(adap, mbox, data_reg); 376 377 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 378 t4_read_reg(adap, ctl_reg); /* flush write */ 379 380 delay_idx = 0; 381 ms = delay[0]; 382 383 /* 384 * Loop waiting for the reply; bail out if we time out or the firmware 385 * reports an error. 386 */ 387 pcie_fw = 0; 388 for (i = 0; i < timeout; i += ms) { 389 if (!(adap->flags & IS_VF)) { 390 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 391 if (pcie_fw & F_PCIE_FW_ERR) 392 break; 393 } 394 if (sleep_ok) { 395 ms = delay[delay_idx]; /* last element may repeat */ 396 if (delay_idx < ARRAY_SIZE(delay) - 1) 397 delay_idx++; 398 msleep(ms); 399 } else { 400 mdelay(ms); 401 } 402 403 v = t4_read_reg(adap, ctl_reg); 404 if (v == X_CIM_PF_NOACCESS) 405 continue; 406 if (G_MBOWNER(v) == X_MBOWNER_PL) { 407 if (!(v & F_MBMSGVALID)) { 408 t4_write_reg(adap, ctl_reg, 409 V_MBOWNER(X_MBOWNER_NONE)); 410 continue; 411 } 412 413 /* 414 * Retrieve the command reply and release the mailbox. 415 */ 416 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 417 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 418 419 CH_DUMP_MBOX(adap, mbox, data_reg); 420 421 res = be64_to_cpu(cmd_rpl[0]); 422 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 423 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 424 res = V_FW_CMD_RETVAL(EIO); 425 } else if (rpl) 426 memcpy(rpl, cmd_rpl, size); 427 return -G_FW_CMD_RETVAL((int)res); 428 } 429 } 430 431 /* 432 * We timed out waiting for a reply to our mailbox command. Report 433 * the error and also check to see if the firmware reported any 434 * errors ... 435 */ 436 ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; 437 CH_ERR(adap, "command %#x in mailbox %d timed out\n", 438 *(const u8 *)cmd, mbox); 439 440 /* If DUMP_MBOX is set the mbox has already been dumped */ 441 if ((adap->debug_flags & DF_DUMP_MBOX) == 0) { 442 p = cmd; 443 CH_ERR(adap, "mbox: %016llx %016llx %016llx %016llx " 444 "%016llx %016llx %016llx %016llx\n", 445 (unsigned long long)be64_to_cpu(p[0]), 446 (unsigned long long)be64_to_cpu(p[1]), 447 (unsigned long long)be64_to_cpu(p[2]), 448 (unsigned long long)be64_to_cpu(p[3]), 449 (unsigned long long)be64_to_cpu(p[4]), 450 (unsigned long long)be64_to_cpu(p[5]), 451 (unsigned long long)be64_to_cpu(p[6]), 452 (unsigned long long)be64_to_cpu(p[7])); 453 } 454 455 t4_report_fw_error(adap); 456 t4_fatal_err(adap); 457 return ret; 458 } 459 460 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 461 void *rpl, bool sleep_ok) 462 { 463 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 464 sleep_ok, FW_CMD_MAX_TIMEOUT); 465 466 } 467 468 static int t4_edc_err_read(struct adapter *adap, int idx) 469 { 470 u32 edc_ecc_err_addr_reg; 471 u32 edc_bist_status_rdata_reg; 472 473 if (is_t4(adap)) { 474 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 475 return 0; 476 } 477 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 478 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 479 return 0; 480 } 481 482 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 483 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 484 485 CH_WARN(adap, 486 "edc%d err addr 0x%x: 0x%x.\n", 487 idx, edc_ecc_err_addr_reg, 488 t4_read_reg(adap, edc_ecc_err_addr_reg)); 489 CH_WARN(adap, 490 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 491 edc_bist_status_rdata_reg, 492 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 493 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 494 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 495 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 496 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 497 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 498 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 499 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 500 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 501 502 return 0; 503 } 504 505 /** 506 * t4_mc_read - read from MC through backdoor accesses 507 * @adap: the adapter 508 * @idx: which MC to access 509 * @addr: address of first byte requested 510 * @data: 64 bytes of data containing the requested address 511 * @ecc: where to store the corresponding 64-bit ECC word 512 * 513 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 514 * that covers the requested address @addr. If @parity is not %NULL it 515 * is assigned the 64-bit ECC word for the read data. 516 */ 517 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 518 { 519 int i; 520 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 521 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 522 523 if (is_t4(adap)) { 524 mc_bist_cmd_reg = A_MC_BIST_CMD; 525 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 526 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 527 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 528 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 529 } else { 530 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 531 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 532 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 533 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 534 idx); 535 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 536 idx); 537 } 538 539 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 540 return -EBUSY; 541 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 542 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 543 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 544 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 545 F_START_BIST | V_BIST_CMD_GAP(1)); 546 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 547 if (i) 548 return i; 549 550 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 551 552 for (i = 15; i >= 0; i--) 553 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 554 if (ecc) 555 *ecc = t4_read_reg64(adap, MC_DATA(16)); 556 #undef MC_DATA 557 return 0; 558 } 559 560 /** 561 * t4_edc_read - read from EDC through backdoor accesses 562 * @adap: the adapter 563 * @idx: which EDC to access 564 * @addr: address of first byte requested 565 * @data: 64 bytes of data containing the requested address 566 * @ecc: where to store the corresponding 64-bit ECC word 567 * 568 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 569 * that covers the requested address @addr. If @parity is not %NULL it 570 * is assigned the 64-bit ECC word for the read data. 571 */ 572 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 573 { 574 int i; 575 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 576 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 577 578 if (is_t4(adap)) { 579 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 580 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 581 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 582 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 583 idx); 584 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 585 idx); 586 } else { 587 /* 588 * These macro are missing in t4_regs.h file. 589 * Added temporarily for testing. 590 */ 591 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 592 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 593 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 594 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 595 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 596 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 597 idx); 598 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 599 idx); 600 #undef EDC_REG_T5 601 #undef EDC_STRIDE_T5 602 } 603 604 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 605 return -EBUSY; 606 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 607 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 608 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 609 t4_write_reg(adap, edc_bist_cmd_reg, 610 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 611 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 612 if (i) 613 return i; 614 615 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 616 617 for (i = 15; i >= 0; i--) 618 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 619 if (ecc) 620 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 621 #undef EDC_DATA 622 return 0; 623 } 624 625 /** 626 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 627 * @adap: the adapter 628 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 629 * @addr: address within indicated memory type 630 * @len: amount of memory to read 631 * @buf: host memory buffer 632 * 633 * Reads an [almost] arbitrary memory region in the firmware: the 634 * firmware memory address, length and host buffer must be aligned on 635 * 32-bit boudaries. The memory is returned as a raw byte sequence from 636 * the firmware's memory. If this memory contains data structures which 637 * contain multi-byte integers, it's the callers responsibility to 638 * perform appropriate byte order conversions. 639 */ 640 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 641 __be32 *buf) 642 { 643 u32 pos, start, end, offset; 644 int ret; 645 646 /* 647 * Argument sanity checks ... 648 */ 649 if ((addr & 0x3) || (len & 0x3)) 650 return -EINVAL; 651 652 /* 653 * The underlaying EDC/MC read routines read 64 bytes at a time so we 654 * need to round down the start and round up the end. We'll start 655 * copying out of the first line at (addr - start) a word at a time. 656 */ 657 start = rounddown2(addr, 64); 658 end = roundup2(addr + len, 64); 659 offset = (addr - start)/sizeof(__be32); 660 661 for (pos = start; pos < end; pos += 64, offset = 0) { 662 __be32 data[16]; 663 664 /* 665 * Read the chip's memory block and bail if there's an error. 666 */ 667 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 668 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 669 else 670 ret = t4_edc_read(adap, mtype, pos, data, NULL); 671 if (ret) 672 return ret; 673 674 /* 675 * Copy the data into the caller's memory buffer. 676 */ 677 while (offset < 16 && len > 0) { 678 *buf++ = data[offset++]; 679 len -= sizeof(__be32); 680 } 681 } 682 683 return 0; 684 } 685 686 /* 687 * Return the specified PCI-E Configuration Space register from our Physical 688 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 689 * since we prefer to let the firmware own all of these registers, but if that 690 * fails we go for it directly ourselves. 691 */ 692 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 693 { 694 695 /* 696 * If fw_attach != 0, construct and send the Firmware LDST Command to 697 * retrieve the specified PCI-E Configuration Space register. 698 */ 699 if (drv_fw_attach != 0) { 700 struct fw_ldst_cmd ldst_cmd; 701 int ret; 702 703 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 704 ldst_cmd.op_to_addrspace = 705 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 706 F_FW_CMD_REQUEST | 707 F_FW_CMD_READ | 708 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 709 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 710 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 711 ldst_cmd.u.pcie.ctrl_to_fn = 712 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 713 ldst_cmd.u.pcie.r = reg; 714 715 /* 716 * If the LDST Command succeeds, return the result, otherwise 717 * fall through to reading it directly ourselves ... 718 */ 719 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 720 &ldst_cmd); 721 if (ret == 0) 722 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 723 724 CH_WARN(adap, "Firmware failed to return " 725 "Configuration Space register %d, err = %d\n", 726 reg, -ret); 727 } 728 729 /* 730 * Read the desired Configuration Space register via the PCI-E 731 * Backdoor mechanism. 732 */ 733 return t4_hw_pci_read_cfg4(adap, reg); 734 } 735 736 /** 737 * t4_get_regs_len - return the size of the chips register set 738 * @adapter: the adapter 739 * 740 * Returns the size of the chip's BAR0 register space. 741 */ 742 unsigned int t4_get_regs_len(struct adapter *adapter) 743 { 744 unsigned int chip_version = chip_id(adapter); 745 746 switch (chip_version) { 747 case CHELSIO_T4: 748 if (adapter->flags & IS_VF) 749 return FW_T4VF_REGMAP_SIZE; 750 return T4_REGMAP_SIZE; 751 752 case CHELSIO_T5: 753 case CHELSIO_T6: 754 if (adapter->flags & IS_VF) 755 return FW_T4VF_REGMAP_SIZE; 756 return T5_REGMAP_SIZE; 757 } 758 759 CH_ERR(adapter, 760 "Unsupported chip version %d\n", chip_version); 761 return 0; 762 } 763 764 /** 765 * t4_get_regs - read chip registers into provided buffer 766 * @adap: the adapter 767 * @buf: register buffer 768 * @buf_size: size (in bytes) of register buffer 769 * 770 * If the provided register buffer isn't large enough for the chip's 771 * full register range, the register dump will be truncated to the 772 * register buffer's size. 773 */ 774 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 775 { 776 static const unsigned int t4_reg_ranges[] = { 777 0x1008, 0x1108, 778 0x1180, 0x1184, 779 0x1190, 0x1194, 780 0x11a0, 0x11a4, 781 0x11b0, 0x11b4, 782 0x11fc, 0x123c, 783 0x1300, 0x173c, 784 0x1800, 0x18fc, 785 0x3000, 0x30d8, 786 0x30e0, 0x30e4, 787 0x30ec, 0x5910, 788 0x5920, 0x5924, 789 0x5960, 0x5960, 790 0x5968, 0x5968, 791 0x5970, 0x5970, 792 0x5978, 0x5978, 793 0x5980, 0x5980, 794 0x5988, 0x5988, 795 0x5990, 0x5990, 796 0x5998, 0x5998, 797 0x59a0, 0x59d4, 798 0x5a00, 0x5ae0, 799 0x5ae8, 0x5ae8, 800 0x5af0, 0x5af0, 801 0x5af8, 0x5af8, 802 0x6000, 0x6098, 803 0x6100, 0x6150, 804 0x6200, 0x6208, 805 0x6240, 0x6248, 806 0x6280, 0x62b0, 807 0x62c0, 0x6338, 808 0x6370, 0x638c, 809 0x6400, 0x643c, 810 0x6500, 0x6524, 811 0x6a00, 0x6a04, 812 0x6a14, 0x6a38, 813 0x6a60, 0x6a70, 814 0x6a78, 0x6a78, 815 0x6b00, 0x6b0c, 816 0x6b1c, 0x6b84, 817 0x6bf0, 0x6bf8, 818 0x6c00, 0x6c0c, 819 0x6c1c, 0x6c84, 820 0x6cf0, 0x6cf8, 821 0x6d00, 0x6d0c, 822 0x6d1c, 0x6d84, 823 0x6df0, 0x6df8, 824 0x6e00, 0x6e0c, 825 0x6e1c, 0x6e84, 826 0x6ef0, 0x6ef8, 827 0x6f00, 0x6f0c, 828 0x6f1c, 0x6f84, 829 0x6ff0, 0x6ff8, 830 0x7000, 0x700c, 831 0x701c, 0x7084, 832 0x70f0, 0x70f8, 833 0x7100, 0x710c, 834 0x711c, 0x7184, 835 0x71f0, 0x71f8, 836 0x7200, 0x720c, 837 0x721c, 0x7284, 838 0x72f0, 0x72f8, 839 0x7300, 0x730c, 840 0x731c, 0x7384, 841 0x73f0, 0x73f8, 842 0x7400, 0x7450, 843 0x7500, 0x7530, 844 0x7600, 0x760c, 845 0x7614, 0x761c, 846 0x7680, 0x76cc, 847 0x7700, 0x7798, 848 0x77c0, 0x77fc, 849 0x7900, 0x79fc, 850 0x7b00, 0x7b58, 851 0x7b60, 0x7b84, 852 0x7b8c, 0x7c38, 853 0x7d00, 0x7d38, 854 0x7d40, 0x7d80, 855 0x7d8c, 0x7ddc, 856 0x7de4, 0x7e04, 857 0x7e10, 0x7e1c, 858 0x7e24, 0x7e38, 859 0x7e40, 0x7e44, 860 0x7e4c, 0x7e78, 861 0x7e80, 0x7ea4, 862 0x7eac, 0x7edc, 863 0x7ee8, 0x7efc, 864 0x8dc0, 0x8e04, 865 0x8e10, 0x8e1c, 866 0x8e30, 0x8e78, 867 0x8ea0, 0x8eb8, 868 0x8ec0, 0x8f6c, 869 0x8fc0, 0x9008, 870 0x9010, 0x9058, 871 0x9060, 0x9060, 872 0x9068, 0x9074, 873 0x90fc, 0x90fc, 874 0x9400, 0x9408, 875 0x9410, 0x9458, 876 0x9600, 0x9600, 877 0x9608, 0x9638, 878 0x9640, 0x96bc, 879 0x9800, 0x9808, 880 0x9820, 0x983c, 881 0x9850, 0x9864, 882 0x9c00, 0x9c6c, 883 0x9c80, 0x9cec, 884 0x9d00, 0x9d6c, 885 0x9d80, 0x9dec, 886 0x9e00, 0x9e6c, 887 0x9e80, 0x9eec, 888 0x9f00, 0x9f6c, 889 0x9f80, 0x9fec, 890 0xd004, 0xd004, 891 0xd010, 0xd03c, 892 0xdfc0, 0xdfe0, 893 0xe000, 0xea7c, 894 0xf000, 0x11110, 895 0x11118, 0x11190, 896 0x19040, 0x1906c, 897 0x19078, 0x19080, 898 0x1908c, 0x190e4, 899 0x190f0, 0x190f8, 900 0x19100, 0x19110, 901 0x19120, 0x19124, 902 0x19150, 0x19194, 903 0x1919c, 0x191b0, 904 0x191d0, 0x191e8, 905 0x19238, 0x1924c, 906 0x193f8, 0x1943c, 907 0x1944c, 0x19474, 908 0x19490, 0x194e0, 909 0x194f0, 0x194f8, 910 0x19800, 0x19c08, 911 0x19c10, 0x19c90, 912 0x19ca0, 0x19ce4, 913 0x19cf0, 0x19d40, 914 0x19d50, 0x19d94, 915 0x19da0, 0x19de8, 916 0x19df0, 0x19e40, 917 0x19e50, 0x19e90, 918 0x19ea0, 0x19f4c, 919 0x1a000, 0x1a004, 920 0x1a010, 0x1a06c, 921 0x1a0b0, 0x1a0e4, 922 0x1a0ec, 0x1a0f4, 923 0x1a100, 0x1a108, 924 0x1a114, 0x1a120, 925 0x1a128, 0x1a130, 926 0x1a138, 0x1a138, 927 0x1a190, 0x1a1c4, 928 0x1a1fc, 0x1a1fc, 929 0x1e040, 0x1e04c, 930 0x1e284, 0x1e28c, 931 0x1e2c0, 0x1e2c0, 932 0x1e2e0, 0x1e2e0, 933 0x1e300, 0x1e384, 934 0x1e3c0, 0x1e3c8, 935 0x1e440, 0x1e44c, 936 0x1e684, 0x1e68c, 937 0x1e6c0, 0x1e6c0, 938 0x1e6e0, 0x1e6e0, 939 0x1e700, 0x1e784, 940 0x1e7c0, 0x1e7c8, 941 0x1e840, 0x1e84c, 942 0x1ea84, 0x1ea8c, 943 0x1eac0, 0x1eac0, 944 0x1eae0, 0x1eae0, 945 0x1eb00, 0x1eb84, 946 0x1ebc0, 0x1ebc8, 947 0x1ec40, 0x1ec4c, 948 0x1ee84, 0x1ee8c, 949 0x1eec0, 0x1eec0, 950 0x1eee0, 0x1eee0, 951 0x1ef00, 0x1ef84, 952 0x1efc0, 0x1efc8, 953 0x1f040, 0x1f04c, 954 0x1f284, 0x1f28c, 955 0x1f2c0, 0x1f2c0, 956 0x1f2e0, 0x1f2e0, 957 0x1f300, 0x1f384, 958 0x1f3c0, 0x1f3c8, 959 0x1f440, 0x1f44c, 960 0x1f684, 0x1f68c, 961 0x1f6c0, 0x1f6c0, 962 0x1f6e0, 0x1f6e0, 963 0x1f700, 0x1f784, 964 0x1f7c0, 0x1f7c8, 965 0x1f840, 0x1f84c, 966 0x1fa84, 0x1fa8c, 967 0x1fac0, 0x1fac0, 968 0x1fae0, 0x1fae0, 969 0x1fb00, 0x1fb84, 970 0x1fbc0, 0x1fbc8, 971 0x1fc40, 0x1fc4c, 972 0x1fe84, 0x1fe8c, 973 0x1fec0, 0x1fec0, 974 0x1fee0, 0x1fee0, 975 0x1ff00, 0x1ff84, 976 0x1ffc0, 0x1ffc8, 977 0x20000, 0x2002c, 978 0x20100, 0x2013c, 979 0x20190, 0x201a0, 980 0x201a8, 0x201b8, 981 0x201c4, 0x201c8, 982 0x20200, 0x20318, 983 0x20400, 0x204b4, 984 0x204c0, 0x20528, 985 0x20540, 0x20614, 986 0x21000, 0x21040, 987 0x2104c, 0x21060, 988 0x210c0, 0x210ec, 989 0x21200, 0x21268, 990 0x21270, 0x21284, 991 0x212fc, 0x21388, 992 0x21400, 0x21404, 993 0x21500, 0x21500, 994 0x21510, 0x21518, 995 0x2152c, 0x21530, 996 0x2153c, 0x2153c, 997 0x21550, 0x21554, 998 0x21600, 0x21600, 999 0x21608, 0x2161c, 1000 0x21624, 0x21628, 1001 0x21630, 0x21634, 1002 0x2163c, 0x2163c, 1003 0x21700, 0x2171c, 1004 0x21780, 0x2178c, 1005 0x21800, 0x21818, 1006 0x21820, 0x21828, 1007 0x21830, 0x21848, 1008 0x21850, 0x21854, 1009 0x21860, 0x21868, 1010 0x21870, 0x21870, 1011 0x21878, 0x21898, 1012 0x218a0, 0x218a8, 1013 0x218b0, 0x218c8, 1014 0x218d0, 0x218d4, 1015 0x218e0, 0x218e8, 1016 0x218f0, 0x218f0, 1017 0x218f8, 0x21a18, 1018 0x21a20, 0x21a28, 1019 0x21a30, 0x21a48, 1020 0x21a50, 0x21a54, 1021 0x21a60, 0x21a68, 1022 0x21a70, 0x21a70, 1023 0x21a78, 0x21a98, 1024 0x21aa0, 0x21aa8, 1025 0x21ab0, 0x21ac8, 1026 0x21ad0, 0x21ad4, 1027 0x21ae0, 0x21ae8, 1028 0x21af0, 0x21af0, 1029 0x21af8, 0x21c18, 1030 0x21c20, 0x21c20, 1031 0x21c28, 0x21c30, 1032 0x21c38, 0x21c38, 1033 0x21c80, 0x21c98, 1034 0x21ca0, 0x21ca8, 1035 0x21cb0, 0x21cc8, 1036 0x21cd0, 0x21cd4, 1037 0x21ce0, 0x21ce8, 1038 0x21cf0, 0x21cf0, 1039 0x21cf8, 0x21d7c, 1040 0x21e00, 0x21e04, 1041 0x22000, 0x2202c, 1042 0x22100, 0x2213c, 1043 0x22190, 0x221a0, 1044 0x221a8, 0x221b8, 1045 0x221c4, 0x221c8, 1046 0x22200, 0x22318, 1047 0x22400, 0x224b4, 1048 0x224c0, 0x22528, 1049 0x22540, 0x22614, 1050 0x23000, 0x23040, 1051 0x2304c, 0x23060, 1052 0x230c0, 0x230ec, 1053 0x23200, 0x23268, 1054 0x23270, 0x23284, 1055 0x232fc, 0x23388, 1056 0x23400, 0x23404, 1057 0x23500, 0x23500, 1058 0x23510, 0x23518, 1059 0x2352c, 0x23530, 1060 0x2353c, 0x2353c, 1061 0x23550, 0x23554, 1062 0x23600, 0x23600, 1063 0x23608, 0x2361c, 1064 0x23624, 0x23628, 1065 0x23630, 0x23634, 1066 0x2363c, 0x2363c, 1067 0x23700, 0x2371c, 1068 0x23780, 0x2378c, 1069 0x23800, 0x23818, 1070 0x23820, 0x23828, 1071 0x23830, 0x23848, 1072 0x23850, 0x23854, 1073 0x23860, 0x23868, 1074 0x23870, 0x23870, 1075 0x23878, 0x23898, 1076 0x238a0, 0x238a8, 1077 0x238b0, 0x238c8, 1078 0x238d0, 0x238d4, 1079 0x238e0, 0x238e8, 1080 0x238f0, 0x238f0, 1081 0x238f8, 0x23a18, 1082 0x23a20, 0x23a28, 1083 0x23a30, 0x23a48, 1084 0x23a50, 0x23a54, 1085 0x23a60, 0x23a68, 1086 0x23a70, 0x23a70, 1087 0x23a78, 0x23a98, 1088 0x23aa0, 0x23aa8, 1089 0x23ab0, 0x23ac8, 1090 0x23ad0, 0x23ad4, 1091 0x23ae0, 0x23ae8, 1092 0x23af0, 0x23af0, 1093 0x23af8, 0x23c18, 1094 0x23c20, 0x23c20, 1095 0x23c28, 0x23c30, 1096 0x23c38, 0x23c38, 1097 0x23c80, 0x23c98, 1098 0x23ca0, 0x23ca8, 1099 0x23cb0, 0x23cc8, 1100 0x23cd0, 0x23cd4, 1101 0x23ce0, 0x23ce8, 1102 0x23cf0, 0x23cf0, 1103 0x23cf8, 0x23d7c, 1104 0x23e00, 0x23e04, 1105 0x24000, 0x2402c, 1106 0x24100, 0x2413c, 1107 0x24190, 0x241a0, 1108 0x241a8, 0x241b8, 1109 0x241c4, 0x241c8, 1110 0x24200, 0x24318, 1111 0x24400, 0x244b4, 1112 0x244c0, 0x24528, 1113 0x24540, 0x24614, 1114 0x25000, 0x25040, 1115 0x2504c, 0x25060, 1116 0x250c0, 0x250ec, 1117 0x25200, 0x25268, 1118 0x25270, 0x25284, 1119 0x252fc, 0x25388, 1120 0x25400, 0x25404, 1121 0x25500, 0x25500, 1122 0x25510, 0x25518, 1123 0x2552c, 0x25530, 1124 0x2553c, 0x2553c, 1125 0x25550, 0x25554, 1126 0x25600, 0x25600, 1127 0x25608, 0x2561c, 1128 0x25624, 0x25628, 1129 0x25630, 0x25634, 1130 0x2563c, 0x2563c, 1131 0x25700, 0x2571c, 1132 0x25780, 0x2578c, 1133 0x25800, 0x25818, 1134 0x25820, 0x25828, 1135 0x25830, 0x25848, 1136 0x25850, 0x25854, 1137 0x25860, 0x25868, 1138 0x25870, 0x25870, 1139 0x25878, 0x25898, 1140 0x258a0, 0x258a8, 1141 0x258b0, 0x258c8, 1142 0x258d0, 0x258d4, 1143 0x258e0, 0x258e8, 1144 0x258f0, 0x258f0, 1145 0x258f8, 0x25a18, 1146 0x25a20, 0x25a28, 1147 0x25a30, 0x25a48, 1148 0x25a50, 0x25a54, 1149 0x25a60, 0x25a68, 1150 0x25a70, 0x25a70, 1151 0x25a78, 0x25a98, 1152 0x25aa0, 0x25aa8, 1153 0x25ab0, 0x25ac8, 1154 0x25ad0, 0x25ad4, 1155 0x25ae0, 0x25ae8, 1156 0x25af0, 0x25af0, 1157 0x25af8, 0x25c18, 1158 0x25c20, 0x25c20, 1159 0x25c28, 0x25c30, 1160 0x25c38, 0x25c38, 1161 0x25c80, 0x25c98, 1162 0x25ca0, 0x25ca8, 1163 0x25cb0, 0x25cc8, 1164 0x25cd0, 0x25cd4, 1165 0x25ce0, 0x25ce8, 1166 0x25cf0, 0x25cf0, 1167 0x25cf8, 0x25d7c, 1168 0x25e00, 0x25e04, 1169 0x26000, 0x2602c, 1170 0x26100, 0x2613c, 1171 0x26190, 0x261a0, 1172 0x261a8, 0x261b8, 1173 0x261c4, 0x261c8, 1174 0x26200, 0x26318, 1175 0x26400, 0x264b4, 1176 0x264c0, 0x26528, 1177 0x26540, 0x26614, 1178 0x27000, 0x27040, 1179 0x2704c, 0x27060, 1180 0x270c0, 0x270ec, 1181 0x27200, 0x27268, 1182 0x27270, 0x27284, 1183 0x272fc, 0x27388, 1184 0x27400, 0x27404, 1185 0x27500, 0x27500, 1186 0x27510, 0x27518, 1187 0x2752c, 0x27530, 1188 0x2753c, 0x2753c, 1189 0x27550, 0x27554, 1190 0x27600, 0x27600, 1191 0x27608, 0x2761c, 1192 0x27624, 0x27628, 1193 0x27630, 0x27634, 1194 0x2763c, 0x2763c, 1195 0x27700, 0x2771c, 1196 0x27780, 0x2778c, 1197 0x27800, 0x27818, 1198 0x27820, 0x27828, 1199 0x27830, 0x27848, 1200 0x27850, 0x27854, 1201 0x27860, 0x27868, 1202 0x27870, 0x27870, 1203 0x27878, 0x27898, 1204 0x278a0, 0x278a8, 1205 0x278b0, 0x278c8, 1206 0x278d0, 0x278d4, 1207 0x278e0, 0x278e8, 1208 0x278f0, 0x278f0, 1209 0x278f8, 0x27a18, 1210 0x27a20, 0x27a28, 1211 0x27a30, 0x27a48, 1212 0x27a50, 0x27a54, 1213 0x27a60, 0x27a68, 1214 0x27a70, 0x27a70, 1215 0x27a78, 0x27a98, 1216 0x27aa0, 0x27aa8, 1217 0x27ab0, 0x27ac8, 1218 0x27ad0, 0x27ad4, 1219 0x27ae0, 0x27ae8, 1220 0x27af0, 0x27af0, 1221 0x27af8, 0x27c18, 1222 0x27c20, 0x27c20, 1223 0x27c28, 0x27c30, 1224 0x27c38, 0x27c38, 1225 0x27c80, 0x27c98, 1226 0x27ca0, 0x27ca8, 1227 0x27cb0, 0x27cc8, 1228 0x27cd0, 0x27cd4, 1229 0x27ce0, 0x27ce8, 1230 0x27cf0, 0x27cf0, 1231 0x27cf8, 0x27d7c, 1232 0x27e00, 0x27e04, 1233 }; 1234 1235 static const unsigned int t4vf_reg_ranges[] = { 1236 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1237 VF_MPS_REG(A_MPS_VF_CTL), 1238 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1239 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1240 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1241 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1242 FW_T4VF_MBDATA_BASE_ADDR, 1243 FW_T4VF_MBDATA_BASE_ADDR + 1244 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1245 }; 1246 1247 static const unsigned int t5_reg_ranges[] = { 1248 0x1008, 0x10c0, 1249 0x10cc, 0x10f8, 1250 0x1100, 0x1100, 1251 0x110c, 0x1148, 1252 0x1180, 0x1184, 1253 0x1190, 0x1194, 1254 0x11a0, 0x11a4, 1255 0x11b0, 0x11b4, 1256 0x11fc, 0x123c, 1257 0x1280, 0x173c, 1258 0x1800, 0x18fc, 1259 0x3000, 0x3028, 1260 0x3060, 0x30b0, 1261 0x30b8, 0x30d8, 1262 0x30e0, 0x30fc, 1263 0x3140, 0x357c, 1264 0x35a8, 0x35cc, 1265 0x35ec, 0x35ec, 1266 0x3600, 0x5624, 1267 0x56cc, 0x56ec, 1268 0x56f4, 0x5720, 1269 0x5728, 0x575c, 1270 0x580c, 0x5814, 1271 0x5890, 0x589c, 1272 0x58a4, 0x58ac, 1273 0x58b8, 0x58bc, 1274 0x5940, 0x59c8, 1275 0x59d0, 0x59dc, 1276 0x59fc, 0x5a18, 1277 0x5a60, 0x5a70, 1278 0x5a80, 0x5a9c, 1279 0x5b94, 0x5bfc, 1280 0x6000, 0x6020, 1281 0x6028, 0x6040, 1282 0x6058, 0x609c, 1283 0x60a8, 0x614c, 1284 0x7700, 0x7798, 1285 0x77c0, 0x78fc, 1286 0x7b00, 0x7b58, 1287 0x7b60, 0x7b84, 1288 0x7b8c, 0x7c54, 1289 0x7d00, 0x7d38, 1290 0x7d40, 0x7d80, 1291 0x7d8c, 0x7ddc, 1292 0x7de4, 0x7e04, 1293 0x7e10, 0x7e1c, 1294 0x7e24, 0x7e38, 1295 0x7e40, 0x7e44, 1296 0x7e4c, 0x7e78, 1297 0x7e80, 0x7edc, 1298 0x7ee8, 0x7efc, 1299 0x8dc0, 0x8de0, 1300 0x8df8, 0x8e04, 1301 0x8e10, 0x8e84, 1302 0x8ea0, 0x8f84, 1303 0x8fc0, 0x9058, 1304 0x9060, 0x9060, 1305 0x9068, 0x90f8, 1306 0x9400, 0x9408, 1307 0x9410, 0x9470, 1308 0x9600, 0x9600, 1309 0x9608, 0x9638, 1310 0x9640, 0x96f4, 1311 0x9800, 0x9808, 1312 0x9820, 0x983c, 1313 0x9850, 0x9864, 1314 0x9c00, 0x9c6c, 1315 0x9c80, 0x9cec, 1316 0x9d00, 0x9d6c, 1317 0x9d80, 0x9dec, 1318 0x9e00, 0x9e6c, 1319 0x9e80, 0x9eec, 1320 0x9f00, 0x9f6c, 1321 0x9f80, 0xa020, 1322 0xd004, 0xd004, 1323 0xd010, 0xd03c, 1324 0xdfc0, 0xdfe0, 1325 0xe000, 0x1106c, 1326 0x11074, 0x11088, 1327 0x1109c, 0x1117c, 1328 0x11190, 0x11204, 1329 0x19040, 0x1906c, 1330 0x19078, 0x19080, 1331 0x1908c, 0x190e8, 1332 0x190f0, 0x190f8, 1333 0x19100, 0x19110, 1334 0x19120, 0x19124, 1335 0x19150, 0x19194, 1336 0x1919c, 0x191b0, 1337 0x191d0, 0x191e8, 1338 0x19238, 0x19290, 1339 0x193f8, 0x19428, 1340 0x19430, 0x19444, 1341 0x1944c, 0x1946c, 1342 0x19474, 0x19474, 1343 0x19490, 0x194cc, 1344 0x194f0, 0x194f8, 1345 0x19c00, 0x19c08, 1346 0x19c10, 0x19c60, 1347 0x19c94, 0x19ce4, 1348 0x19cf0, 0x19d40, 1349 0x19d50, 0x19d94, 1350 0x19da0, 0x19de8, 1351 0x19df0, 0x19e10, 1352 0x19e50, 0x19e90, 1353 0x19ea0, 0x19f24, 1354 0x19f34, 0x19f34, 1355 0x19f40, 0x19f50, 1356 0x19f90, 0x19fb4, 1357 0x19fc4, 0x19fe4, 1358 0x1a000, 0x1a004, 1359 0x1a010, 0x1a06c, 1360 0x1a0b0, 0x1a0e4, 1361 0x1a0ec, 0x1a0f8, 1362 0x1a100, 0x1a108, 1363 0x1a114, 0x1a120, 1364 0x1a128, 0x1a130, 1365 0x1a138, 0x1a138, 1366 0x1a190, 0x1a1c4, 1367 0x1a1fc, 0x1a1fc, 1368 0x1e008, 0x1e00c, 1369 0x1e040, 0x1e044, 1370 0x1e04c, 0x1e04c, 1371 0x1e284, 0x1e290, 1372 0x1e2c0, 0x1e2c0, 1373 0x1e2e0, 0x1e2e0, 1374 0x1e300, 0x1e384, 1375 0x1e3c0, 0x1e3c8, 1376 0x1e408, 0x1e40c, 1377 0x1e440, 0x1e444, 1378 0x1e44c, 0x1e44c, 1379 0x1e684, 0x1e690, 1380 0x1e6c0, 0x1e6c0, 1381 0x1e6e0, 0x1e6e0, 1382 0x1e700, 0x1e784, 1383 0x1e7c0, 0x1e7c8, 1384 0x1e808, 0x1e80c, 1385 0x1e840, 0x1e844, 1386 0x1e84c, 0x1e84c, 1387 0x1ea84, 0x1ea90, 1388 0x1eac0, 0x1eac0, 1389 0x1eae0, 0x1eae0, 1390 0x1eb00, 0x1eb84, 1391 0x1ebc0, 0x1ebc8, 1392 0x1ec08, 0x1ec0c, 1393 0x1ec40, 0x1ec44, 1394 0x1ec4c, 0x1ec4c, 1395 0x1ee84, 0x1ee90, 1396 0x1eec0, 0x1eec0, 1397 0x1eee0, 0x1eee0, 1398 0x1ef00, 0x1ef84, 1399 0x1efc0, 0x1efc8, 1400 0x1f008, 0x1f00c, 1401 0x1f040, 0x1f044, 1402 0x1f04c, 0x1f04c, 1403 0x1f284, 0x1f290, 1404 0x1f2c0, 0x1f2c0, 1405 0x1f2e0, 0x1f2e0, 1406 0x1f300, 0x1f384, 1407 0x1f3c0, 0x1f3c8, 1408 0x1f408, 0x1f40c, 1409 0x1f440, 0x1f444, 1410 0x1f44c, 0x1f44c, 1411 0x1f684, 0x1f690, 1412 0x1f6c0, 0x1f6c0, 1413 0x1f6e0, 0x1f6e0, 1414 0x1f700, 0x1f784, 1415 0x1f7c0, 0x1f7c8, 1416 0x1f808, 0x1f80c, 1417 0x1f840, 0x1f844, 1418 0x1f84c, 0x1f84c, 1419 0x1fa84, 0x1fa90, 1420 0x1fac0, 0x1fac0, 1421 0x1fae0, 0x1fae0, 1422 0x1fb00, 0x1fb84, 1423 0x1fbc0, 0x1fbc8, 1424 0x1fc08, 0x1fc0c, 1425 0x1fc40, 0x1fc44, 1426 0x1fc4c, 0x1fc4c, 1427 0x1fe84, 0x1fe90, 1428 0x1fec0, 0x1fec0, 1429 0x1fee0, 0x1fee0, 1430 0x1ff00, 0x1ff84, 1431 0x1ffc0, 0x1ffc8, 1432 0x30000, 0x30030, 1433 0x30100, 0x30144, 1434 0x30190, 0x301a0, 1435 0x301a8, 0x301b8, 1436 0x301c4, 0x301c8, 1437 0x301d0, 0x301d0, 1438 0x30200, 0x30318, 1439 0x30400, 0x304b4, 1440 0x304c0, 0x3052c, 1441 0x30540, 0x3061c, 1442 0x30800, 0x30828, 1443 0x30834, 0x30834, 1444 0x308c0, 0x30908, 1445 0x30910, 0x309ac, 1446 0x30a00, 0x30a14, 1447 0x30a1c, 0x30a2c, 1448 0x30a44, 0x30a50, 1449 0x30a74, 0x30a74, 1450 0x30a7c, 0x30afc, 1451 0x30b08, 0x30c24, 1452 0x30d00, 0x30d00, 1453 0x30d08, 0x30d14, 1454 0x30d1c, 0x30d20, 1455 0x30d3c, 0x30d3c, 1456 0x30d48, 0x30d50, 1457 0x31200, 0x3120c, 1458 0x31220, 0x31220, 1459 0x31240, 0x31240, 1460 0x31600, 0x3160c, 1461 0x31a00, 0x31a1c, 1462 0x31e00, 0x31e20, 1463 0x31e38, 0x31e3c, 1464 0x31e80, 0x31e80, 1465 0x31e88, 0x31ea8, 1466 0x31eb0, 0x31eb4, 1467 0x31ec8, 0x31ed4, 1468 0x31fb8, 0x32004, 1469 0x32200, 0x32200, 1470 0x32208, 0x32240, 1471 0x32248, 0x32280, 1472 0x32288, 0x322c0, 1473 0x322c8, 0x322fc, 1474 0x32600, 0x32630, 1475 0x32a00, 0x32abc, 1476 0x32b00, 0x32b10, 1477 0x32b20, 0x32b30, 1478 0x32b40, 0x32b50, 1479 0x32b60, 0x32b70, 1480 0x33000, 0x33028, 1481 0x33030, 0x33048, 1482 0x33060, 0x33068, 1483 0x33070, 0x3309c, 1484 0x330f0, 0x33128, 1485 0x33130, 0x33148, 1486 0x33160, 0x33168, 1487 0x33170, 0x3319c, 1488 0x331f0, 0x33238, 1489 0x33240, 0x33240, 1490 0x33248, 0x33250, 1491 0x3325c, 0x33264, 1492 0x33270, 0x332b8, 1493 0x332c0, 0x332e4, 1494 0x332f8, 0x33338, 1495 0x33340, 0x33340, 1496 0x33348, 0x33350, 1497 0x3335c, 0x33364, 1498 0x33370, 0x333b8, 1499 0x333c0, 0x333e4, 1500 0x333f8, 0x33428, 1501 0x33430, 0x33448, 1502 0x33460, 0x33468, 1503 0x33470, 0x3349c, 1504 0x334f0, 0x33528, 1505 0x33530, 0x33548, 1506 0x33560, 0x33568, 1507 0x33570, 0x3359c, 1508 0x335f0, 0x33638, 1509 0x33640, 0x33640, 1510 0x33648, 0x33650, 1511 0x3365c, 0x33664, 1512 0x33670, 0x336b8, 1513 0x336c0, 0x336e4, 1514 0x336f8, 0x33738, 1515 0x33740, 0x33740, 1516 0x33748, 0x33750, 1517 0x3375c, 0x33764, 1518 0x33770, 0x337b8, 1519 0x337c0, 0x337e4, 1520 0x337f8, 0x337fc, 1521 0x33814, 0x33814, 1522 0x3382c, 0x3382c, 1523 0x33880, 0x3388c, 1524 0x338e8, 0x338ec, 1525 0x33900, 0x33928, 1526 0x33930, 0x33948, 1527 0x33960, 0x33968, 1528 0x33970, 0x3399c, 1529 0x339f0, 0x33a38, 1530 0x33a40, 0x33a40, 1531 0x33a48, 0x33a50, 1532 0x33a5c, 0x33a64, 1533 0x33a70, 0x33ab8, 1534 0x33ac0, 0x33ae4, 1535 0x33af8, 0x33b10, 1536 0x33b28, 0x33b28, 1537 0x33b3c, 0x33b50, 1538 0x33bf0, 0x33c10, 1539 0x33c28, 0x33c28, 1540 0x33c3c, 0x33c50, 1541 0x33cf0, 0x33cfc, 1542 0x34000, 0x34030, 1543 0x34100, 0x34144, 1544 0x34190, 0x341a0, 1545 0x341a8, 0x341b8, 1546 0x341c4, 0x341c8, 1547 0x341d0, 0x341d0, 1548 0x34200, 0x34318, 1549 0x34400, 0x344b4, 1550 0x344c0, 0x3452c, 1551 0x34540, 0x3461c, 1552 0x34800, 0x34828, 1553 0x34834, 0x34834, 1554 0x348c0, 0x34908, 1555 0x34910, 0x349ac, 1556 0x34a00, 0x34a14, 1557 0x34a1c, 0x34a2c, 1558 0x34a44, 0x34a50, 1559 0x34a74, 0x34a74, 1560 0x34a7c, 0x34afc, 1561 0x34b08, 0x34c24, 1562 0x34d00, 0x34d00, 1563 0x34d08, 0x34d14, 1564 0x34d1c, 0x34d20, 1565 0x34d3c, 0x34d3c, 1566 0x34d48, 0x34d50, 1567 0x35200, 0x3520c, 1568 0x35220, 0x35220, 1569 0x35240, 0x35240, 1570 0x35600, 0x3560c, 1571 0x35a00, 0x35a1c, 1572 0x35e00, 0x35e20, 1573 0x35e38, 0x35e3c, 1574 0x35e80, 0x35e80, 1575 0x35e88, 0x35ea8, 1576 0x35eb0, 0x35eb4, 1577 0x35ec8, 0x35ed4, 1578 0x35fb8, 0x36004, 1579 0x36200, 0x36200, 1580 0x36208, 0x36240, 1581 0x36248, 0x36280, 1582 0x36288, 0x362c0, 1583 0x362c8, 0x362fc, 1584 0x36600, 0x36630, 1585 0x36a00, 0x36abc, 1586 0x36b00, 0x36b10, 1587 0x36b20, 0x36b30, 1588 0x36b40, 0x36b50, 1589 0x36b60, 0x36b70, 1590 0x37000, 0x37028, 1591 0x37030, 0x37048, 1592 0x37060, 0x37068, 1593 0x37070, 0x3709c, 1594 0x370f0, 0x37128, 1595 0x37130, 0x37148, 1596 0x37160, 0x37168, 1597 0x37170, 0x3719c, 1598 0x371f0, 0x37238, 1599 0x37240, 0x37240, 1600 0x37248, 0x37250, 1601 0x3725c, 0x37264, 1602 0x37270, 0x372b8, 1603 0x372c0, 0x372e4, 1604 0x372f8, 0x37338, 1605 0x37340, 0x37340, 1606 0x37348, 0x37350, 1607 0x3735c, 0x37364, 1608 0x37370, 0x373b8, 1609 0x373c0, 0x373e4, 1610 0x373f8, 0x37428, 1611 0x37430, 0x37448, 1612 0x37460, 0x37468, 1613 0x37470, 0x3749c, 1614 0x374f0, 0x37528, 1615 0x37530, 0x37548, 1616 0x37560, 0x37568, 1617 0x37570, 0x3759c, 1618 0x375f0, 0x37638, 1619 0x37640, 0x37640, 1620 0x37648, 0x37650, 1621 0x3765c, 0x37664, 1622 0x37670, 0x376b8, 1623 0x376c0, 0x376e4, 1624 0x376f8, 0x37738, 1625 0x37740, 0x37740, 1626 0x37748, 0x37750, 1627 0x3775c, 0x37764, 1628 0x37770, 0x377b8, 1629 0x377c0, 0x377e4, 1630 0x377f8, 0x377fc, 1631 0x37814, 0x37814, 1632 0x3782c, 0x3782c, 1633 0x37880, 0x3788c, 1634 0x378e8, 0x378ec, 1635 0x37900, 0x37928, 1636 0x37930, 0x37948, 1637 0x37960, 0x37968, 1638 0x37970, 0x3799c, 1639 0x379f0, 0x37a38, 1640 0x37a40, 0x37a40, 1641 0x37a48, 0x37a50, 1642 0x37a5c, 0x37a64, 1643 0x37a70, 0x37ab8, 1644 0x37ac0, 0x37ae4, 1645 0x37af8, 0x37b10, 1646 0x37b28, 0x37b28, 1647 0x37b3c, 0x37b50, 1648 0x37bf0, 0x37c10, 1649 0x37c28, 0x37c28, 1650 0x37c3c, 0x37c50, 1651 0x37cf0, 0x37cfc, 1652 0x38000, 0x38030, 1653 0x38100, 0x38144, 1654 0x38190, 0x381a0, 1655 0x381a8, 0x381b8, 1656 0x381c4, 0x381c8, 1657 0x381d0, 0x381d0, 1658 0x38200, 0x38318, 1659 0x38400, 0x384b4, 1660 0x384c0, 0x3852c, 1661 0x38540, 0x3861c, 1662 0x38800, 0x38828, 1663 0x38834, 0x38834, 1664 0x388c0, 0x38908, 1665 0x38910, 0x389ac, 1666 0x38a00, 0x38a14, 1667 0x38a1c, 0x38a2c, 1668 0x38a44, 0x38a50, 1669 0x38a74, 0x38a74, 1670 0x38a7c, 0x38afc, 1671 0x38b08, 0x38c24, 1672 0x38d00, 0x38d00, 1673 0x38d08, 0x38d14, 1674 0x38d1c, 0x38d20, 1675 0x38d3c, 0x38d3c, 1676 0x38d48, 0x38d50, 1677 0x39200, 0x3920c, 1678 0x39220, 0x39220, 1679 0x39240, 0x39240, 1680 0x39600, 0x3960c, 1681 0x39a00, 0x39a1c, 1682 0x39e00, 0x39e20, 1683 0x39e38, 0x39e3c, 1684 0x39e80, 0x39e80, 1685 0x39e88, 0x39ea8, 1686 0x39eb0, 0x39eb4, 1687 0x39ec8, 0x39ed4, 1688 0x39fb8, 0x3a004, 1689 0x3a200, 0x3a200, 1690 0x3a208, 0x3a240, 1691 0x3a248, 0x3a280, 1692 0x3a288, 0x3a2c0, 1693 0x3a2c8, 0x3a2fc, 1694 0x3a600, 0x3a630, 1695 0x3aa00, 0x3aabc, 1696 0x3ab00, 0x3ab10, 1697 0x3ab20, 0x3ab30, 1698 0x3ab40, 0x3ab50, 1699 0x3ab60, 0x3ab70, 1700 0x3b000, 0x3b028, 1701 0x3b030, 0x3b048, 1702 0x3b060, 0x3b068, 1703 0x3b070, 0x3b09c, 1704 0x3b0f0, 0x3b128, 1705 0x3b130, 0x3b148, 1706 0x3b160, 0x3b168, 1707 0x3b170, 0x3b19c, 1708 0x3b1f0, 0x3b238, 1709 0x3b240, 0x3b240, 1710 0x3b248, 0x3b250, 1711 0x3b25c, 0x3b264, 1712 0x3b270, 0x3b2b8, 1713 0x3b2c0, 0x3b2e4, 1714 0x3b2f8, 0x3b338, 1715 0x3b340, 0x3b340, 1716 0x3b348, 0x3b350, 1717 0x3b35c, 0x3b364, 1718 0x3b370, 0x3b3b8, 1719 0x3b3c0, 0x3b3e4, 1720 0x3b3f8, 0x3b428, 1721 0x3b430, 0x3b448, 1722 0x3b460, 0x3b468, 1723 0x3b470, 0x3b49c, 1724 0x3b4f0, 0x3b528, 1725 0x3b530, 0x3b548, 1726 0x3b560, 0x3b568, 1727 0x3b570, 0x3b59c, 1728 0x3b5f0, 0x3b638, 1729 0x3b640, 0x3b640, 1730 0x3b648, 0x3b650, 1731 0x3b65c, 0x3b664, 1732 0x3b670, 0x3b6b8, 1733 0x3b6c0, 0x3b6e4, 1734 0x3b6f8, 0x3b738, 1735 0x3b740, 0x3b740, 1736 0x3b748, 0x3b750, 1737 0x3b75c, 0x3b764, 1738 0x3b770, 0x3b7b8, 1739 0x3b7c0, 0x3b7e4, 1740 0x3b7f8, 0x3b7fc, 1741 0x3b814, 0x3b814, 1742 0x3b82c, 0x3b82c, 1743 0x3b880, 0x3b88c, 1744 0x3b8e8, 0x3b8ec, 1745 0x3b900, 0x3b928, 1746 0x3b930, 0x3b948, 1747 0x3b960, 0x3b968, 1748 0x3b970, 0x3b99c, 1749 0x3b9f0, 0x3ba38, 1750 0x3ba40, 0x3ba40, 1751 0x3ba48, 0x3ba50, 1752 0x3ba5c, 0x3ba64, 1753 0x3ba70, 0x3bab8, 1754 0x3bac0, 0x3bae4, 1755 0x3baf8, 0x3bb10, 1756 0x3bb28, 0x3bb28, 1757 0x3bb3c, 0x3bb50, 1758 0x3bbf0, 0x3bc10, 1759 0x3bc28, 0x3bc28, 1760 0x3bc3c, 0x3bc50, 1761 0x3bcf0, 0x3bcfc, 1762 0x3c000, 0x3c030, 1763 0x3c100, 0x3c144, 1764 0x3c190, 0x3c1a0, 1765 0x3c1a8, 0x3c1b8, 1766 0x3c1c4, 0x3c1c8, 1767 0x3c1d0, 0x3c1d0, 1768 0x3c200, 0x3c318, 1769 0x3c400, 0x3c4b4, 1770 0x3c4c0, 0x3c52c, 1771 0x3c540, 0x3c61c, 1772 0x3c800, 0x3c828, 1773 0x3c834, 0x3c834, 1774 0x3c8c0, 0x3c908, 1775 0x3c910, 0x3c9ac, 1776 0x3ca00, 0x3ca14, 1777 0x3ca1c, 0x3ca2c, 1778 0x3ca44, 0x3ca50, 1779 0x3ca74, 0x3ca74, 1780 0x3ca7c, 0x3cafc, 1781 0x3cb08, 0x3cc24, 1782 0x3cd00, 0x3cd00, 1783 0x3cd08, 0x3cd14, 1784 0x3cd1c, 0x3cd20, 1785 0x3cd3c, 0x3cd3c, 1786 0x3cd48, 0x3cd50, 1787 0x3d200, 0x3d20c, 1788 0x3d220, 0x3d220, 1789 0x3d240, 0x3d240, 1790 0x3d600, 0x3d60c, 1791 0x3da00, 0x3da1c, 1792 0x3de00, 0x3de20, 1793 0x3de38, 0x3de3c, 1794 0x3de80, 0x3de80, 1795 0x3de88, 0x3dea8, 1796 0x3deb0, 0x3deb4, 1797 0x3dec8, 0x3ded4, 1798 0x3dfb8, 0x3e004, 1799 0x3e200, 0x3e200, 1800 0x3e208, 0x3e240, 1801 0x3e248, 0x3e280, 1802 0x3e288, 0x3e2c0, 1803 0x3e2c8, 0x3e2fc, 1804 0x3e600, 0x3e630, 1805 0x3ea00, 0x3eabc, 1806 0x3eb00, 0x3eb10, 1807 0x3eb20, 0x3eb30, 1808 0x3eb40, 0x3eb50, 1809 0x3eb60, 0x3eb70, 1810 0x3f000, 0x3f028, 1811 0x3f030, 0x3f048, 1812 0x3f060, 0x3f068, 1813 0x3f070, 0x3f09c, 1814 0x3f0f0, 0x3f128, 1815 0x3f130, 0x3f148, 1816 0x3f160, 0x3f168, 1817 0x3f170, 0x3f19c, 1818 0x3f1f0, 0x3f238, 1819 0x3f240, 0x3f240, 1820 0x3f248, 0x3f250, 1821 0x3f25c, 0x3f264, 1822 0x3f270, 0x3f2b8, 1823 0x3f2c0, 0x3f2e4, 1824 0x3f2f8, 0x3f338, 1825 0x3f340, 0x3f340, 1826 0x3f348, 0x3f350, 1827 0x3f35c, 0x3f364, 1828 0x3f370, 0x3f3b8, 1829 0x3f3c0, 0x3f3e4, 1830 0x3f3f8, 0x3f428, 1831 0x3f430, 0x3f448, 1832 0x3f460, 0x3f468, 1833 0x3f470, 0x3f49c, 1834 0x3f4f0, 0x3f528, 1835 0x3f530, 0x3f548, 1836 0x3f560, 0x3f568, 1837 0x3f570, 0x3f59c, 1838 0x3f5f0, 0x3f638, 1839 0x3f640, 0x3f640, 1840 0x3f648, 0x3f650, 1841 0x3f65c, 0x3f664, 1842 0x3f670, 0x3f6b8, 1843 0x3f6c0, 0x3f6e4, 1844 0x3f6f8, 0x3f738, 1845 0x3f740, 0x3f740, 1846 0x3f748, 0x3f750, 1847 0x3f75c, 0x3f764, 1848 0x3f770, 0x3f7b8, 1849 0x3f7c0, 0x3f7e4, 1850 0x3f7f8, 0x3f7fc, 1851 0x3f814, 0x3f814, 1852 0x3f82c, 0x3f82c, 1853 0x3f880, 0x3f88c, 1854 0x3f8e8, 0x3f8ec, 1855 0x3f900, 0x3f928, 1856 0x3f930, 0x3f948, 1857 0x3f960, 0x3f968, 1858 0x3f970, 0x3f99c, 1859 0x3f9f0, 0x3fa38, 1860 0x3fa40, 0x3fa40, 1861 0x3fa48, 0x3fa50, 1862 0x3fa5c, 0x3fa64, 1863 0x3fa70, 0x3fab8, 1864 0x3fac0, 0x3fae4, 1865 0x3faf8, 0x3fb10, 1866 0x3fb28, 0x3fb28, 1867 0x3fb3c, 0x3fb50, 1868 0x3fbf0, 0x3fc10, 1869 0x3fc28, 0x3fc28, 1870 0x3fc3c, 0x3fc50, 1871 0x3fcf0, 0x3fcfc, 1872 0x40000, 0x4000c, 1873 0x40040, 0x40050, 1874 0x40060, 0x40068, 1875 0x4007c, 0x4008c, 1876 0x40094, 0x400b0, 1877 0x400c0, 0x40144, 1878 0x40180, 0x4018c, 1879 0x40200, 0x40254, 1880 0x40260, 0x40264, 1881 0x40270, 0x40288, 1882 0x40290, 0x40298, 1883 0x402ac, 0x402c8, 1884 0x402d0, 0x402e0, 1885 0x402f0, 0x402f0, 1886 0x40300, 0x4033c, 1887 0x403f8, 0x403fc, 1888 0x41304, 0x413c4, 1889 0x41400, 0x4140c, 1890 0x41414, 0x4141c, 1891 0x41480, 0x414d0, 1892 0x44000, 0x44054, 1893 0x4405c, 0x44078, 1894 0x440c0, 0x44174, 1895 0x44180, 0x441ac, 1896 0x441b4, 0x441b8, 1897 0x441c0, 0x44254, 1898 0x4425c, 0x44278, 1899 0x442c0, 0x44374, 1900 0x44380, 0x443ac, 1901 0x443b4, 0x443b8, 1902 0x443c0, 0x44454, 1903 0x4445c, 0x44478, 1904 0x444c0, 0x44574, 1905 0x44580, 0x445ac, 1906 0x445b4, 0x445b8, 1907 0x445c0, 0x44654, 1908 0x4465c, 0x44678, 1909 0x446c0, 0x44774, 1910 0x44780, 0x447ac, 1911 0x447b4, 0x447b8, 1912 0x447c0, 0x44854, 1913 0x4485c, 0x44878, 1914 0x448c0, 0x44974, 1915 0x44980, 0x449ac, 1916 0x449b4, 0x449b8, 1917 0x449c0, 0x449fc, 1918 0x45000, 0x45004, 1919 0x45010, 0x45030, 1920 0x45040, 0x45060, 1921 0x45068, 0x45068, 1922 0x45080, 0x45084, 1923 0x450a0, 0x450b0, 1924 0x45200, 0x45204, 1925 0x45210, 0x45230, 1926 0x45240, 0x45260, 1927 0x45268, 0x45268, 1928 0x45280, 0x45284, 1929 0x452a0, 0x452b0, 1930 0x460c0, 0x460e4, 1931 0x47000, 0x4703c, 1932 0x47044, 0x4708c, 1933 0x47200, 0x47250, 1934 0x47400, 0x47408, 1935 0x47414, 0x47420, 1936 0x47600, 0x47618, 1937 0x47800, 0x47814, 1938 0x48000, 0x4800c, 1939 0x48040, 0x48050, 1940 0x48060, 0x48068, 1941 0x4807c, 0x4808c, 1942 0x48094, 0x480b0, 1943 0x480c0, 0x48144, 1944 0x48180, 0x4818c, 1945 0x48200, 0x48254, 1946 0x48260, 0x48264, 1947 0x48270, 0x48288, 1948 0x48290, 0x48298, 1949 0x482ac, 0x482c8, 1950 0x482d0, 0x482e0, 1951 0x482f0, 0x482f0, 1952 0x48300, 0x4833c, 1953 0x483f8, 0x483fc, 1954 0x49304, 0x493c4, 1955 0x49400, 0x4940c, 1956 0x49414, 0x4941c, 1957 0x49480, 0x494d0, 1958 0x4c000, 0x4c054, 1959 0x4c05c, 0x4c078, 1960 0x4c0c0, 0x4c174, 1961 0x4c180, 0x4c1ac, 1962 0x4c1b4, 0x4c1b8, 1963 0x4c1c0, 0x4c254, 1964 0x4c25c, 0x4c278, 1965 0x4c2c0, 0x4c374, 1966 0x4c380, 0x4c3ac, 1967 0x4c3b4, 0x4c3b8, 1968 0x4c3c0, 0x4c454, 1969 0x4c45c, 0x4c478, 1970 0x4c4c0, 0x4c574, 1971 0x4c580, 0x4c5ac, 1972 0x4c5b4, 0x4c5b8, 1973 0x4c5c0, 0x4c654, 1974 0x4c65c, 0x4c678, 1975 0x4c6c0, 0x4c774, 1976 0x4c780, 0x4c7ac, 1977 0x4c7b4, 0x4c7b8, 1978 0x4c7c0, 0x4c854, 1979 0x4c85c, 0x4c878, 1980 0x4c8c0, 0x4c974, 1981 0x4c980, 0x4c9ac, 1982 0x4c9b4, 0x4c9b8, 1983 0x4c9c0, 0x4c9fc, 1984 0x4d000, 0x4d004, 1985 0x4d010, 0x4d030, 1986 0x4d040, 0x4d060, 1987 0x4d068, 0x4d068, 1988 0x4d080, 0x4d084, 1989 0x4d0a0, 0x4d0b0, 1990 0x4d200, 0x4d204, 1991 0x4d210, 0x4d230, 1992 0x4d240, 0x4d260, 1993 0x4d268, 0x4d268, 1994 0x4d280, 0x4d284, 1995 0x4d2a0, 0x4d2b0, 1996 0x4e0c0, 0x4e0e4, 1997 0x4f000, 0x4f03c, 1998 0x4f044, 0x4f08c, 1999 0x4f200, 0x4f250, 2000 0x4f400, 0x4f408, 2001 0x4f414, 0x4f420, 2002 0x4f600, 0x4f618, 2003 0x4f800, 0x4f814, 2004 0x50000, 0x50084, 2005 0x50090, 0x500cc, 2006 0x50400, 0x50400, 2007 0x50800, 0x50884, 2008 0x50890, 0x508cc, 2009 0x50c00, 0x50c00, 2010 0x51000, 0x5101c, 2011 0x51300, 0x51308, 2012 }; 2013 2014 static const unsigned int t5vf_reg_ranges[] = { 2015 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2016 VF_MPS_REG(A_MPS_VF_CTL), 2017 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2018 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2019 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2020 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2021 FW_T4VF_MBDATA_BASE_ADDR, 2022 FW_T4VF_MBDATA_BASE_ADDR + 2023 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2024 }; 2025 2026 static const unsigned int t6_reg_ranges[] = { 2027 0x1008, 0x101c, 2028 0x1024, 0x10a8, 2029 0x10b4, 0x10f8, 2030 0x1100, 0x1114, 2031 0x111c, 0x112c, 2032 0x1138, 0x113c, 2033 0x1144, 0x114c, 2034 0x1180, 0x1184, 2035 0x1190, 0x1194, 2036 0x11a0, 0x11a4, 2037 0x11b0, 0x11b4, 2038 0x11fc, 0x1274, 2039 0x1280, 0x133c, 2040 0x1800, 0x18fc, 2041 0x3000, 0x302c, 2042 0x3060, 0x30b0, 2043 0x30b8, 0x30d8, 2044 0x30e0, 0x30fc, 2045 0x3140, 0x357c, 2046 0x35a8, 0x35cc, 2047 0x35ec, 0x35ec, 2048 0x3600, 0x5624, 2049 0x56cc, 0x56ec, 2050 0x56f4, 0x5720, 2051 0x5728, 0x575c, 2052 0x580c, 0x5814, 2053 0x5890, 0x589c, 2054 0x58a4, 0x58ac, 2055 0x58b8, 0x58bc, 2056 0x5940, 0x595c, 2057 0x5980, 0x598c, 2058 0x59b0, 0x59c8, 2059 0x59d0, 0x59dc, 2060 0x59fc, 0x5a18, 2061 0x5a60, 0x5a6c, 2062 0x5a80, 0x5a8c, 2063 0x5a94, 0x5a9c, 2064 0x5b94, 0x5bfc, 2065 0x5c10, 0x5e48, 2066 0x5e50, 0x5e94, 2067 0x5ea0, 0x5eb0, 2068 0x5ec0, 0x5ec0, 2069 0x5ec8, 0x5ed0, 2070 0x5ee0, 0x5ee0, 2071 0x5ef0, 0x5ef0, 2072 0x5f00, 0x5f00, 2073 0x6000, 0x6020, 2074 0x6028, 0x6040, 2075 0x6058, 0x609c, 2076 0x60a8, 0x619c, 2077 0x7700, 0x7798, 2078 0x77c0, 0x7880, 2079 0x78cc, 0x78fc, 2080 0x7b00, 0x7b58, 2081 0x7b60, 0x7b84, 2082 0x7b8c, 0x7c54, 2083 0x7d00, 0x7d38, 2084 0x7d40, 0x7d84, 2085 0x7d8c, 0x7ddc, 2086 0x7de4, 0x7e04, 2087 0x7e10, 0x7e1c, 2088 0x7e24, 0x7e38, 2089 0x7e40, 0x7e44, 2090 0x7e4c, 0x7e78, 2091 0x7e80, 0x7edc, 2092 0x7ee8, 0x7efc, 2093 0x8dc0, 0x8de4, 2094 0x8df8, 0x8e04, 2095 0x8e10, 0x8e84, 2096 0x8ea0, 0x8f88, 2097 0x8fb8, 0x9058, 2098 0x9060, 0x9060, 2099 0x9068, 0x90f8, 2100 0x9100, 0x9124, 2101 0x9400, 0x9470, 2102 0x9600, 0x9600, 2103 0x9608, 0x9638, 2104 0x9640, 0x9704, 2105 0x9710, 0x971c, 2106 0x9800, 0x9808, 2107 0x9820, 0x983c, 2108 0x9850, 0x9864, 2109 0x9c00, 0x9c6c, 2110 0x9c80, 0x9cec, 2111 0x9d00, 0x9d6c, 2112 0x9d80, 0x9dec, 2113 0x9e00, 0x9e6c, 2114 0x9e80, 0x9eec, 2115 0x9f00, 0x9f6c, 2116 0x9f80, 0xa020, 2117 0xd004, 0xd03c, 2118 0xd100, 0xd118, 2119 0xd200, 0xd214, 2120 0xd220, 0xd234, 2121 0xd240, 0xd254, 2122 0xd260, 0xd274, 2123 0xd280, 0xd294, 2124 0xd2a0, 0xd2b4, 2125 0xd2c0, 0xd2d4, 2126 0xd2e0, 0xd2f4, 2127 0xd300, 0xd31c, 2128 0xdfc0, 0xdfe0, 2129 0xe000, 0xf008, 2130 0xf010, 0xf018, 2131 0xf020, 0xf028, 2132 0x11000, 0x11014, 2133 0x11048, 0x1106c, 2134 0x11074, 0x11088, 2135 0x11098, 0x11120, 2136 0x1112c, 0x1117c, 2137 0x11190, 0x112e0, 2138 0x11300, 0x1130c, 2139 0x12000, 0x1206c, 2140 0x19040, 0x1906c, 2141 0x19078, 0x19080, 2142 0x1908c, 0x190e8, 2143 0x190f0, 0x190f8, 2144 0x19100, 0x19110, 2145 0x19120, 0x19124, 2146 0x19150, 0x19194, 2147 0x1919c, 0x191b0, 2148 0x191d0, 0x191e8, 2149 0x19238, 0x19290, 2150 0x192a4, 0x192b0, 2151 0x192bc, 0x192bc, 2152 0x19348, 0x1934c, 2153 0x193f8, 0x19418, 2154 0x19420, 0x19428, 2155 0x19430, 0x19444, 2156 0x1944c, 0x1946c, 2157 0x19474, 0x19474, 2158 0x19490, 0x194cc, 2159 0x194f0, 0x194f8, 2160 0x19c00, 0x19c48, 2161 0x19c50, 0x19c80, 2162 0x19c94, 0x19c98, 2163 0x19ca0, 0x19cbc, 2164 0x19ce4, 0x19ce4, 2165 0x19cf0, 0x19cf8, 2166 0x19d00, 0x19d28, 2167 0x19d50, 0x19d78, 2168 0x19d94, 0x19d98, 2169 0x19da0, 0x19dc8, 2170 0x19df0, 0x19e10, 2171 0x19e50, 0x19e6c, 2172 0x19ea0, 0x19ebc, 2173 0x19ec4, 0x19ef4, 2174 0x19f04, 0x19f2c, 2175 0x19f34, 0x19f34, 2176 0x19f40, 0x19f50, 2177 0x19f90, 0x19fac, 2178 0x19fc4, 0x19fc8, 2179 0x19fd0, 0x19fe4, 2180 0x1a000, 0x1a004, 2181 0x1a010, 0x1a06c, 2182 0x1a0b0, 0x1a0e4, 2183 0x1a0ec, 0x1a0f8, 2184 0x1a100, 0x1a108, 2185 0x1a114, 0x1a120, 2186 0x1a128, 0x1a130, 2187 0x1a138, 0x1a138, 2188 0x1a190, 0x1a1c4, 2189 0x1a1fc, 0x1a1fc, 2190 0x1e008, 0x1e00c, 2191 0x1e040, 0x1e044, 2192 0x1e04c, 0x1e04c, 2193 0x1e284, 0x1e290, 2194 0x1e2c0, 0x1e2c0, 2195 0x1e2e0, 0x1e2e0, 2196 0x1e300, 0x1e384, 2197 0x1e3c0, 0x1e3c8, 2198 0x1e408, 0x1e40c, 2199 0x1e440, 0x1e444, 2200 0x1e44c, 0x1e44c, 2201 0x1e684, 0x1e690, 2202 0x1e6c0, 0x1e6c0, 2203 0x1e6e0, 0x1e6e0, 2204 0x1e700, 0x1e784, 2205 0x1e7c0, 0x1e7c8, 2206 0x1e808, 0x1e80c, 2207 0x1e840, 0x1e844, 2208 0x1e84c, 0x1e84c, 2209 0x1ea84, 0x1ea90, 2210 0x1eac0, 0x1eac0, 2211 0x1eae0, 0x1eae0, 2212 0x1eb00, 0x1eb84, 2213 0x1ebc0, 0x1ebc8, 2214 0x1ec08, 0x1ec0c, 2215 0x1ec40, 0x1ec44, 2216 0x1ec4c, 0x1ec4c, 2217 0x1ee84, 0x1ee90, 2218 0x1eec0, 0x1eec0, 2219 0x1eee0, 0x1eee0, 2220 0x1ef00, 0x1ef84, 2221 0x1efc0, 0x1efc8, 2222 0x1f008, 0x1f00c, 2223 0x1f040, 0x1f044, 2224 0x1f04c, 0x1f04c, 2225 0x1f284, 0x1f290, 2226 0x1f2c0, 0x1f2c0, 2227 0x1f2e0, 0x1f2e0, 2228 0x1f300, 0x1f384, 2229 0x1f3c0, 0x1f3c8, 2230 0x1f408, 0x1f40c, 2231 0x1f440, 0x1f444, 2232 0x1f44c, 0x1f44c, 2233 0x1f684, 0x1f690, 2234 0x1f6c0, 0x1f6c0, 2235 0x1f6e0, 0x1f6e0, 2236 0x1f700, 0x1f784, 2237 0x1f7c0, 0x1f7c8, 2238 0x1f808, 0x1f80c, 2239 0x1f840, 0x1f844, 2240 0x1f84c, 0x1f84c, 2241 0x1fa84, 0x1fa90, 2242 0x1fac0, 0x1fac0, 2243 0x1fae0, 0x1fae0, 2244 0x1fb00, 0x1fb84, 2245 0x1fbc0, 0x1fbc8, 2246 0x1fc08, 0x1fc0c, 2247 0x1fc40, 0x1fc44, 2248 0x1fc4c, 0x1fc4c, 2249 0x1fe84, 0x1fe90, 2250 0x1fec0, 0x1fec0, 2251 0x1fee0, 0x1fee0, 2252 0x1ff00, 0x1ff84, 2253 0x1ffc0, 0x1ffc8, 2254 0x30000, 0x30030, 2255 0x30100, 0x30168, 2256 0x30190, 0x301a0, 2257 0x301a8, 0x301b8, 2258 0x301c4, 0x301c8, 2259 0x301d0, 0x301d0, 2260 0x30200, 0x30320, 2261 0x30400, 0x304b4, 2262 0x304c0, 0x3052c, 2263 0x30540, 0x3061c, 2264 0x30800, 0x308a0, 2265 0x308c0, 0x30908, 2266 0x30910, 0x309b8, 2267 0x30a00, 0x30a04, 2268 0x30a0c, 0x30a14, 2269 0x30a1c, 0x30a2c, 2270 0x30a44, 0x30a50, 2271 0x30a74, 0x30a74, 2272 0x30a7c, 0x30afc, 2273 0x30b08, 0x30c24, 2274 0x30d00, 0x30d14, 2275 0x30d1c, 0x30d3c, 2276 0x30d44, 0x30d4c, 2277 0x30d54, 0x30d74, 2278 0x30d7c, 0x30d7c, 2279 0x30de0, 0x30de0, 2280 0x30e00, 0x30ed4, 2281 0x30f00, 0x30fa4, 2282 0x30fc0, 0x30fc4, 2283 0x31000, 0x31004, 2284 0x31080, 0x310fc, 2285 0x31208, 0x31220, 2286 0x3123c, 0x31254, 2287 0x31300, 0x31300, 2288 0x31308, 0x3131c, 2289 0x31338, 0x3133c, 2290 0x31380, 0x31380, 2291 0x31388, 0x313a8, 2292 0x313b4, 0x313b4, 2293 0x31400, 0x31420, 2294 0x31438, 0x3143c, 2295 0x31480, 0x31480, 2296 0x314a8, 0x314a8, 2297 0x314b0, 0x314b4, 2298 0x314c8, 0x314d4, 2299 0x31a40, 0x31a4c, 2300 0x31af0, 0x31b20, 2301 0x31b38, 0x31b3c, 2302 0x31b80, 0x31b80, 2303 0x31ba8, 0x31ba8, 2304 0x31bb0, 0x31bb4, 2305 0x31bc8, 0x31bd4, 2306 0x32140, 0x3218c, 2307 0x321f0, 0x321f4, 2308 0x32200, 0x32200, 2309 0x32218, 0x32218, 2310 0x32400, 0x32400, 2311 0x32408, 0x3241c, 2312 0x32618, 0x32620, 2313 0x32664, 0x32664, 2314 0x326a8, 0x326a8, 2315 0x326ec, 0x326ec, 2316 0x32a00, 0x32abc, 2317 0x32b00, 0x32b18, 2318 0x32b20, 0x32b38, 2319 0x32b40, 0x32b58, 2320 0x32b60, 0x32b78, 2321 0x32c00, 0x32c00, 2322 0x32c08, 0x32c3c, 2323 0x33000, 0x3302c, 2324 0x33034, 0x33050, 2325 0x33058, 0x33058, 2326 0x33060, 0x3308c, 2327 0x3309c, 0x330ac, 2328 0x330c0, 0x330c0, 2329 0x330c8, 0x330d0, 2330 0x330d8, 0x330e0, 2331 0x330ec, 0x3312c, 2332 0x33134, 0x33150, 2333 0x33158, 0x33158, 2334 0x33160, 0x3318c, 2335 0x3319c, 0x331ac, 2336 0x331c0, 0x331c0, 2337 0x331c8, 0x331d0, 2338 0x331d8, 0x331e0, 2339 0x331ec, 0x33290, 2340 0x33298, 0x332c4, 2341 0x332e4, 0x33390, 2342 0x33398, 0x333c4, 2343 0x333e4, 0x3342c, 2344 0x33434, 0x33450, 2345 0x33458, 0x33458, 2346 0x33460, 0x3348c, 2347 0x3349c, 0x334ac, 2348 0x334c0, 0x334c0, 2349 0x334c8, 0x334d0, 2350 0x334d8, 0x334e0, 2351 0x334ec, 0x3352c, 2352 0x33534, 0x33550, 2353 0x33558, 0x33558, 2354 0x33560, 0x3358c, 2355 0x3359c, 0x335ac, 2356 0x335c0, 0x335c0, 2357 0x335c8, 0x335d0, 2358 0x335d8, 0x335e0, 2359 0x335ec, 0x33690, 2360 0x33698, 0x336c4, 2361 0x336e4, 0x33790, 2362 0x33798, 0x337c4, 2363 0x337e4, 0x337fc, 2364 0x33814, 0x33814, 2365 0x33854, 0x33868, 2366 0x33880, 0x3388c, 2367 0x338c0, 0x338d0, 2368 0x338e8, 0x338ec, 2369 0x33900, 0x3392c, 2370 0x33934, 0x33950, 2371 0x33958, 0x33958, 2372 0x33960, 0x3398c, 2373 0x3399c, 0x339ac, 2374 0x339c0, 0x339c0, 2375 0x339c8, 0x339d0, 2376 0x339d8, 0x339e0, 2377 0x339ec, 0x33a90, 2378 0x33a98, 0x33ac4, 2379 0x33ae4, 0x33b10, 2380 0x33b24, 0x33b28, 2381 0x33b38, 0x33b50, 2382 0x33bf0, 0x33c10, 2383 0x33c24, 0x33c28, 2384 0x33c38, 0x33c50, 2385 0x33cf0, 0x33cfc, 2386 0x34000, 0x34030, 2387 0x34100, 0x34168, 2388 0x34190, 0x341a0, 2389 0x341a8, 0x341b8, 2390 0x341c4, 0x341c8, 2391 0x341d0, 0x341d0, 2392 0x34200, 0x34320, 2393 0x34400, 0x344b4, 2394 0x344c0, 0x3452c, 2395 0x34540, 0x3461c, 2396 0x34800, 0x348a0, 2397 0x348c0, 0x34908, 2398 0x34910, 0x349b8, 2399 0x34a00, 0x34a04, 2400 0x34a0c, 0x34a14, 2401 0x34a1c, 0x34a2c, 2402 0x34a44, 0x34a50, 2403 0x34a74, 0x34a74, 2404 0x34a7c, 0x34afc, 2405 0x34b08, 0x34c24, 2406 0x34d00, 0x34d14, 2407 0x34d1c, 0x34d3c, 2408 0x34d44, 0x34d4c, 2409 0x34d54, 0x34d74, 2410 0x34d7c, 0x34d7c, 2411 0x34de0, 0x34de0, 2412 0x34e00, 0x34ed4, 2413 0x34f00, 0x34fa4, 2414 0x34fc0, 0x34fc4, 2415 0x35000, 0x35004, 2416 0x35080, 0x350fc, 2417 0x35208, 0x35220, 2418 0x3523c, 0x35254, 2419 0x35300, 0x35300, 2420 0x35308, 0x3531c, 2421 0x35338, 0x3533c, 2422 0x35380, 0x35380, 2423 0x35388, 0x353a8, 2424 0x353b4, 0x353b4, 2425 0x35400, 0x35420, 2426 0x35438, 0x3543c, 2427 0x35480, 0x35480, 2428 0x354a8, 0x354a8, 2429 0x354b0, 0x354b4, 2430 0x354c8, 0x354d4, 2431 0x35a40, 0x35a4c, 2432 0x35af0, 0x35b20, 2433 0x35b38, 0x35b3c, 2434 0x35b80, 0x35b80, 2435 0x35ba8, 0x35ba8, 2436 0x35bb0, 0x35bb4, 2437 0x35bc8, 0x35bd4, 2438 0x36140, 0x3618c, 2439 0x361f0, 0x361f4, 2440 0x36200, 0x36200, 2441 0x36218, 0x36218, 2442 0x36400, 0x36400, 2443 0x36408, 0x3641c, 2444 0x36618, 0x36620, 2445 0x36664, 0x36664, 2446 0x366a8, 0x366a8, 2447 0x366ec, 0x366ec, 2448 0x36a00, 0x36abc, 2449 0x36b00, 0x36b18, 2450 0x36b20, 0x36b38, 2451 0x36b40, 0x36b58, 2452 0x36b60, 0x36b78, 2453 0x36c00, 0x36c00, 2454 0x36c08, 0x36c3c, 2455 0x37000, 0x3702c, 2456 0x37034, 0x37050, 2457 0x37058, 0x37058, 2458 0x37060, 0x3708c, 2459 0x3709c, 0x370ac, 2460 0x370c0, 0x370c0, 2461 0x370c8, 0x370d0, 2462 0x370d8, 0x370e0, 2463 0x370ec, 0x3712c, 2464 0x37134, 0x37150, 2465 0x37158, 0x37158, 2466 0x37160, 0x3718c, 2467 0x3719c, 0x371ac, 2468 0x371c0, 0x371c0, 2469 0x371c8, 0x371d0, 2470 0x371d8, 0x371e0, 2471 0x371ec, 0x37290, 2472 0x37298, 0x372c4, 2473 0x372e4, 0x37390, 2474 0x37398, 0x373c4, 2475 0x373e4, 0x3742c, 2476 0x37434, 0x37450, 2477 0x37458, 0x37458, 2478 0x37460, 0x3748c, 2479 0x3749c, 0x374ac, 2480 0x374c0, 0x374c0, 2481 0x374c8, 0x374d0, 2482 0x374d8, 0x374e0, 2483 0x374ec, 0x3752c, 2484 0x37534, 0x37550, 2485 0x37558, 0x37558, 2486 0x37560, 0x3758c, 2487 0x3759c, 0x375ac, 2488 0x375c0, 0x375c0, 2489 0x375c8, 0x375d0, 2490 0x375d8, 0x375e0, 2491 0x375ec, 0x37690, 2492 0x37698, 0x376c4, 2493 0x376e4, 0x37790, 2494 0x37798, 0x377c4, 2495 0x377e4, 0x377fc, 2496 0x37814, 0x37814, 2497 0x37854, 0x37868, 2498 0x37880, 0x3788c, 2499 0x378c0, 0x378d0, 2500 0x378e8, 0x378ec, 2501 0x37900, 0x3792c, 2502 0x37934, 0x37950, 2503 0x37958, 0x37958, 2504 0x37960, 0x3798c, 2505 0x3799c, 0x379ac, 2506 0x379c0, 0x379c0, 2507 0x379c8, 0x379d0, 2508 0x379d8, 0x379e0, 2509 0x379ec, 0x37a90, 2510 0x37a98, 0x37ac4, 2511 0x37ae4, 0x37b10, 2512 0x37b24, 0x37b28, 2513 0x37b38, 0x37b50, 2514 0x37bf0, 0x37c10, 2515 0x37c24, 0x37c28, 2516 0x37c38, 0x37c50, 2517 0x37cf0, 0x37cfc, 2518 0x40040, 0x40040, 2519 0x40080, 0x40084, 2520 0x40100, 0x40100, 2521 0x40140, 0x401bc, 2522 0x40200, 0x40214, 2523 0x40228, 0x40228, 2524 0x40240, 0x40258, 2525 0x40280, 0x40280, 2526 0x40304, 0x40304, 2527 0x40330, 0x4033c, 2528 0x41304, 0x413c8, 2529 0x413d0, 0x413dc, 2530 0x413f0, 0x413f0, 2531 0x41400, 0x4140c, 2532 0x41414, 0x4141c, 2533 0x41480, 0x414d0, 2534 0x44000, 0x4407c, 2535 0x440c0, 0x441ac, 2536 0x441b4, 0x4427c, 2537 0x442c0, 0x443ac, 2538 0x443b4, 0x4447c, 2539 0x444c0, 0x445ac, 2540 0x445b4, 0x4467c, 2541 0x446c0, 0x447ac, 2542 0x447b4, 0x4487c, 2543 0x448c0, 0x449ac, 2544 0x449b4, 0x44a7c, 2545 0x44ac0, 0x44bac, 2546 0x44bb4, 0x44c7c, 2547 0x44cc0, 0x44dac, 2548 0x44db4, 0x44e7c, 2549 0x44ec0, 0x44fac, 2550 0x44fb4, 0x4507c, 2551 0x450c0, 0x451ac, 2552 0x451b4, 0x451fc, 2553 0x45800, 0x45804, 2554 0x45810, 0x45830, 2555 0x45840, 0x45860, 2556 0x45868, 0x45868, 2557 0x45880, 0x45884, 2558 0x458a0, 0x458b0, 2559 0x45a00, 0x45a04, 2560 0x45a10, 0x45a30, 2561 0x45a40, 0x45a60, 2562 0x45a68, 0x45a68, 2563 0x45a80, 0x45a84, 2564 0x45aa0, 0x45ab0, 2565 0x460c0, 0x460e4, 2566 0x47000, 0x4703c, 2567 0x47044, 0x4708c, 2568 0x47200, 0x47250, 2569 0x47400, 0x47408, 2570 0x47414, 0x47420, 2571 0x47600, 0x47618, 2572 0x47800, 0x47814, 2573 0x47820, 0x4782c, 2574 0x50000, 0x50084, 2575 0x50090, 0x500cc, 2576 0x50300, 0x50384, 2577 0x50400, 0x50400, 2578 0x50800, 0x50884, 2579 0x50890, 0x508cc, 2580 0x50b00, 0x50b84, 2581 0x50c00, 0x50c00, 2582 0x51000, 0x51020, 2583 0x51028, 0x510b0, 2584 0x51300, 0x51324, 2585 }; 2586 2587 static const unsigned int t6vf_reg_ranges[] = { 2588 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2589 VF_MPS_REG(A_MPS_VF_CTL), 2590 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2591 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2592 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2593 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2594 FW_T6VF_MBDATA_BASE_ADDR, 2595 FW_T6VF_MBDATA_BASE_ADDR + 2596 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2597 }; 2598 2599 u32 *buf_end = (u32 *)(buf + buf_size); 2600 const unsigned int *reg_ranges; 2601 int reg_ranges_size, range; 2602 unsigned int chip_version = chip_id(adap); 2603 2604 /* 2605 * Select the right set of register ranges to dump depending on the 2606 * adapter chip type. 2607 */ 2608 switch (chip_version) { 2609 case CHELSIO_T4: 2610 if (adap->flags & IS_VF) { 2611 reg_ranges = t4vf_reg_ranges; 2612 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2613 } else { 2614 reg_ranges = t4_reg_ranges; 2615 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2616 } 2617 break; 2618 2619 case CHELSIO_T5: 2620 if (adap->flags & IS_VF) { 2621 reg_ranges = t5vf_reg_ranges; 2622 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2623 } else { 2624 reg_ranges = t5_reg_ranges; 2625 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2626 } 2627 break; 2628 2629 case CHELSIO_T6: 2630 if (adap->flags & IS_VF) { 2631 reg_ranges = t6vf_reg_ranges; 2632 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2633 } else { 2634 reg_ranges = t6_reg_ranges; 2635 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2636 } 2637 break; 2638 2639 default: 2640 CH_ERR(adap, 2641 "Unsupported chip version %d\n", chip_version); 2642 return; 2643 } 2644 2645 /* 2646 * Clear the register buffer and insert the appropriate register 2647 * values selected by the above register ranges. 2648 */ 2649 memset(buf, 0, buf_size); 2650 for (range = 0; range < reg_ranges_size; range += 2) { 2651 unsigned int reg = reg_ranges[range]; 2652 unsigned int last_reg = reg_ranges[range + 1]; 2653 u32 *bufp = (u32 *)(buf + reg); 2654 2655 /* 2656 * Iterate across the register range filling in the register 2657 * buffer but don't write past the end of the register buffer. 2658 */ 2659 while (reg <= last_reg && bufp < buf_end) { 2660 *bufp++ = t4_read_reg(adap, reg); 2661 reg += sizeof(u32); 2662 } 2663 } 2664 } 2665 2666 /* 2667 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2668 * header followed by one or more VPD-R sections, each with its own header. 2669 */ 2670 struct t4_vpd_hdr { 2671 u8 id_tag; 2672 u8 id_len[2]; 2673 u8 id_data[ID_LEN]; 2674 }; 2675 2676 struct t4_vpdr_hdr { 2677 u8 vpdr_tag; 2678 u8 vpdr_len[2]; 2679 }; 2680 2681 /* 2682 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2683 */ 2684 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2685 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2686 2687 #define EEPROM_STAT_ADDR 0x7bfc 2688 #define VPD_SIZE 0x800 2689 #define VPD_BASE 0x400 2690 #define VPD_BASE_OLD 0 2691 #define VPD_LEN 1024 2692 #define VPD_INFO_FLD_HDR_SIZE 3 2693 #define CHELSIO_VPD_UNIQUE_ID 0x82 2694 2695 /* 2696 * Small utility function to wait till any outstanding VPD Access is complete. 2697 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2698 * VPD Access in flight. This allows us to handle the problem of having a 2699 * previous VPD Access time out and prevent an attempt to inject a new VPD 2700 * Request before any in-flight VPD reguest has completed. 2701 */ 2702 static int t4_seeprom_wait(struct adapter *adapter) 2703 { 2704 unsigned int base = adapter->params.pci.vpd_cap_addr; 2705 int max_poll; 2706 2707 /* 2708 * If no VPD Access is in flight, we can just return success right 2709 * away. 2710 */ 2711 if (!adapter->vpd_busy) 2712 return 0; 2713 2714 /* 2715 * Poll the VPD Capability Address/Flag register waiting for it 2716 * to indicate that the operation is complete. 2717 */ 2718 max_poll = EEPROM_MAX_POLL; 2719 do { 2720 u16 val; 2721 2722 udelay(EEPROM_DELAY); 2723 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2724 2725 /* 2726 * If the operation is complete, mark the VPD as no longer 2727 * busy and return success. 2728 */ 2729 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2730 adapter->vpd_busy = 0; 2731 return 0; 2732 } 2733 } while (--max_poll); 2734 2735 /* 2736 * Failure! Note that we leave the VPD Busy status set in order to 2737 * avoid pushing a new VPD Access request into the VPD Capability till 2738 * the current operation eventually succeeds. It's a bug to issue a 2739 * new request when an existing request is in flight and will result 2740 * in corrupt hardware state. 2741 */ 2742 return -ETIMEDOUT; 2743 } 2744 2745 /** 2746 * t4_seeprom_read - read a serial EEPROM location 2747 * @adapter: adapter to read 2748 * @addr: EEPROM virtual address 2749 * @data: where to store the read data 2750 * 2751 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2752 * VPD capability. Note that this function must be called with a virtual 2753 * address. 2754 */ 2755 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2756 { 2757 unsigned int base = adapter->params.pci.vpd_cap_addr; 2758 int ret; 2759 2760 /* 2761 * VPD Accesses must alway be 4-byte aligned! 2762 */ 2763 if (addr >= EEPROMVSIZE || (addr & 3)) 2764 return -EINVAL; 2765 2766 /* 2767 * Wait for any previous operation which may still be in flight to 2768 * complete. 2769 */ 2770 ret = t4_seeprom_wait(adapter); 2771 if (ret) { 2772 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2773 return ret; 2774 } 2775 2776 /* 2777 * Issue our new VPD Read request, mark the VPD as being busy and wait 2778 * for our request to complete. If it doesn't complete, note the 2779 * error and return it to our caller. Note that we do not reset the 2780 * VPD Busy status! 2781 */ 2782 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2783 adapter->vpd_busy = 1; 2784 adapter->vpd_flag = PCI_VPD_ADDR_F; 2785 ret = t4_seeprom_wait(adapter); 2786 if (ret) { 2787 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2788 return ret; 2789 } 2790 2791 /* 2792 * Grab the returned data, swizzle it into our endianness and 2793 * return success. 2794 */ 2795 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2796 *data = le32_to_cpu(*data); 2797 return 0; 2798 } 2799 2800 /** 2801 * t4_seeprom_write - write a serial EEPROM location 2802 * @adapter: adapter to write 2803 * @addr: virtual EEPROM address 2804 * @data: value to write 2805 * 2806 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2807 * VPD capability. Note that this function must be called with a virtual 2808 * address. 2809 */ 2810 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2811 { 2812 unsigned int base = adapter->params.pci.vpd_cap_addr; 2813 int ret; 2814 u32 stats_reg; 2815 int max_poll; 2816 2817 /* 2818 * VPD Accesses must alway be 4-byte aligned! 2819 */ 2820 if (addr >= EEPROMVSIZE || (addr & 3)) 2821 return -EINVAL; 2822 2823 /* 2824 * Wait for any previous operation which may still be in flight to 2825 * complete. 2826 */ 2827 ret = t4_seeprom_wait(adapter); 2828 if (ret) { 2829 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2830 return ret; 2831 } 2832 2833 /* 2834 * Issue our new VPD Read request, mark the VPD as being busy and wait 2835 * for our request to complete. If it doesn't complete, note the 2836 * error and return it to our caller. Note that we do not reset the 2837 * VPD Busy status! 2838 */ 2839 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2840 cpu_to_le32(data)); 2841 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2842 (u16)addr | PCI_VPD_ADDR_F); 2843 adapter->vpd_busy = 1; 2844 adapter->vpd_flag = 0; 2845 ret = t4_seeprom_wait(adapter); 2846 if (ret) { 2847 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2848 return ret; 2849 } 2850 2851 /* 2852 * Reset PCI_VPD_DATA register after a transaction and wait for our 2853 * request to complete. If it doesn't complete, return error. 2854 */ 2855 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2856 max_poll = EEPROM_MAX_POLL; 2857 do { 2858 udelay(EEPROM_DELAY); 2859 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2860 } while ((stats_reg & 0x1) && --max_poll); 2861 if (!max_poll) 2862 return -ETIMEDOUT; 2863 2864 /* Return success! */ 2865 return 0; 2866 } 2867 2868 /** 2869 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2870 * @phys_addr: the physical EEPROM address 2871 * @fn: the PCI function number 2872 * @sz: size of function-specific area 2873 * 2874 * Translate a physical EEPROM address to virtual. The first 1K is 2875 * accessed through virtual addresses starting at 31K, the rest is 2876 * accessed through virtual addresses starting at 0. 2877 * 2878 * The mapping is as follows: 2879 * [0..1K) -> [31K..32K) 2880 * [1K..1K+A) -> [ES-A..ES) 2881 * [1K+A..ES) -> [0..ES-A-1K) 2882 * 2883 * where A = @fn * @sz, and ES = EEPROM size. 2884 */ 2885 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2886 { 2887 fn *= sz; 2888 if (phys_addr < 1024) 2889 return phys_addr + (31 << 10); 2890 if (phys_addr < 1024 + fn) 2891 return EEPROMSIZE - fn + phys_addr - 1024; 2892 if (phys_addr < EEPROMSIZE) 2893 return phys_addr - 1024 - fn; 2894 return -EINVAL; 2895 } 2896 2897 /** 2898 * t4_seeprom_wp - enable/disable EEPROM write protection 2899 * @adapter: the adapter 2900 * @enable: whether to enable or disable write protection 2901 * 2902 * Enables or disables write protection on the serial EEPROM. 2903 */ 2904 int t4_seeprom_wp(struct adapter *adapter, int enable) 2905 { 2906 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2907 } 2908 2909 /** 2910 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2911 * @vpd: Pointer to buffered vpd data structure 2912 * @kw: The keyword to search for 2913 * @region: VPD region to search (starting from 0) 2914 * 2915 * Returns the value of the information field keyword or 2916 * -ENOENT otherwise. 2917 */ 2918 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2919 { 2920 int i, tag; 2921 unsigned int offset, len; 2922 const struct t4_vpdr_hdr *vpdr; 2923 2924 offset = sizeof(struct t4_vpd_hdr); 2925 vpdr = (const void *)(vpd + offset); 2926 tag = vpdr->vpdr_tag; 2927 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2928 while (region--) { 2929 offset += sizeof(struct t4_vpdr_hdr) + len; 2930 vpdr = (const void *)(vpd + offset); 2931 if (++tag != vpdr->vpdr_tag) 2932 return -ENOENT; 2933 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2934 } 2935 offset += sizeof(struct t4_vpdr_hdr); 2936 2937 if (offset + len > VPD_LEN) { 2938 return -ENOENT; 2939 } 2940 2941 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2942 if (memcmp(vpd + i , kw , 2) == 0){ 2943 i += VPD_INFO_FLD_HDR_SIZE; 2944 return i; 2945 } 2946 2947 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2948 } 2949 2950 return -ENOENT; 2951 } 2952 2953 2954 /** 2955 * get_vpd_params - read VPD parameters from VPD EEPROM 2956 * @adapter: adapter to read 2957 * @p: where to store the parameters 2958 * @vpd: caller provided temporary space to read the VPD into 2959 * 2960 * Reads card parameters stored in VPD EEPROM. 2961 */ 2962 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 2963 u32 *buf) 2964 { 2965 int i, ret, addr; 2966 int ec, sn, pn, na, md; 2967 u8 csum; 2968 const u8 *vpd = (const u8 *)buf; 2969 2970 /* 2971 * Card information normally starts at VPD_BASE but early cards had 2972 * it at 0. 2973 */ 2974 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 2975 if (ret) 2976 return (ret); 2977 2978 /* 2979 * The VPD shall have a unique identifier specified by the PCI SIG. 2980 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 2981 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 2982 * is expected to automatically put this entry at the 2983 * beginning of the VPD. 2984 */ 2985 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 2986 2987 for (i = 0; i < VPD_LEN; i += 4) { 2988 ret = t4_seeprom_read(adapter, addr + i, buf++); 2989 if (ret) 2990 return ret; 2991 } 2992 2993 #define FIND_VPD_KW(var,name) do { \ 2994 var = get_vpd_keyword_val(vpd, name, 0); \ 2995 if (var < 0) { \ 2996 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 2997 return -EINVAL; \ 2998 } \ 2999 } while (0) 3000 3001 FIND_VPD_KW(i, "RV"); 3002 for (csum = 0; i >= 0; i--) 3003 csum += vpd[i]; 3004 3005 if (csum) { 3006 CH_ERR(adapter, 3007 "corrupted VPD EEPROM, actual csum %u\n", csum); 3008 return -EINVAL; 3009 } 3010 3011 FIND_VPD_KW(ec, "EC"); 3012 FIND_VPD_KW(sn, "SN"); 3013 FIND_VPD_KW(pn, "PN"); 3014 FIND_VPD_KW(na, "NA"); 3015 #undef FIND_VPD_KW 3016 3017 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3018 strstrip(p->id); 3019 memcpy(p->ec, vpd + ec, EC_LEN); 3020 strstrip(p->ec); 3021 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3022 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3023 strstrip(p->sn); 3024 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3025 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3026 strstrip((char *)p->pn); 3027 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3028 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3029 strstrip((char *)p->na); 3030 3031 md = get_vpd_keyword_val(vpd, "VF", 1); 3032 if (md < 0) { 3033 snprintf(p->md, sizeof(p->md), "unknown"); 3034 } else { 3035 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3036 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3037 } 3038 3039 return 0; 3040 } 3041 3042 /* serial flash and firmware constants and flash config file constants */ 3043 enum { 3044 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3045 3046 /* flash command opcodes */ 3047 SF_PROG_PAGE = 2, /* program 256B page */ 3048 SF_WR_DISABLE = 4, /* disable writes */ 3049 SF_RD_STATUS = 5, /* read status register */ 3050 SF_WR_ENABLE = 6, /* enable writes */ 3051 SF_RD_DATA_FAST = 0xb, /* read flash */ 3052 SF_RD_ID = 0x9f, /* read ID */ 3053 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3054 }; 3055 3056 /** 3057 * sf1_read - read data from the serial flash 3058 * @adapter: the adapter 3059 * @byte_cnt: number of bytes to read 3060 * @cont: whether another operation will be chained 3061 * @lock: whether to lock SF for PL access only 3062 * @valp: where to store the read data 3063 * 3064 * Reads up to 4 bytes of data from the serial flash. The location of 3065 * the read needs to be specified prior to calling this by issuing the 3066 * appropriate commands to the serial flash. 3067 */ 3068 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3069 int lock, u32 *valp) 3070 { 3071 int ret; 3072 3073 if (!byte_cnt || byte_cnt > 4) 3074 return -EINVAL; 3075 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3076 return -EBUSY; 3077 t4_write_reg(adapter, A_SF_OP, 3078 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3079 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3080 if (!ret) 3081 *valp = t4_read_reg(adapter, A_SF_DATA); 3082 return ret; 3083 } 3084 3085 /** 3086 * sf1_write - write data to the serial flash 3087 * @adapter: the adapter 3088 * @byte_cnt: number of bytes to write 3089 * @cont: whether another operation will be chained 3090 * @lock: whether to lock SF for PL access only 3091 * @val: value to write 3092 * 3093 * Writes up to 4 bytes of data to the serial flash. The location of 3094 * the write needs to be specified prior to calling this by issuing the 3095 * appropriate commands to the serial flash. 3096 */ 3097 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3098 int lock, u32 val) 3099 { 3100 if (!byte_cnt || byte_cnt > 4) 3101 return -EINVAL; 3102 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3103 return -EBUSY; 3104 t4_write_reg(adapter, A_SF_DATA, val); 3105 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3106 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3107 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3108 } 3109 3110 /** 3111 * flash_wait_op - wait for a flash operation to complete 3112 * @adapter: the adapter 3113 * @attempts: max number of polls of the status register 3114 * @delay: delay between polls in ms 3115 * 3116 * Wait for a flash operation to complete by polling the status register. 3117 */ 3118 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3119 { 3120 int ret; 3121 u32 status; 3122 3123 while (1) { 3124 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3125 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3126 return ret; 3127 if (!(status & 1)) 3128 return 0; 3129 if (--attempts == 0) 3130 return -EAGAIN; 3131 if (delay) 3132 msleep(delay); 3133 } 3134 } 3135 3136 /** 3137 * t4_read_flash - read words from serial flash 3138 * @adapter: the adapter 3139 * @addr: the start address for the read 3140 * @nwords: how many 32-bit words to read 3141 * @data: where to store the read data 3142 * @byte_oriented: whether to store data as bytes or as words 3143 * 3144 * Read the specified number of 32-bit words from the serial flash. 3145 * If @byte_oriented is set the read data is stored as a byte array 3146 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3147 * natural endianness. 3148 */ 3149 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3150 unsigned int nwords, u32 *data, int byte_oriented) 3151 { 3152 int ret; 3153 3154 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3155 return -EINVAL; 3156 3157 addr = swab32(addr) | SF_RD_DATA_FAST; 3158 3159 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3160 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3161 return ret; 3162 3163 for ( ; nwords; nwords--, data++) { 3164 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3165 if (nwords == 1) 3166 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3167 if (ret) 3168 return ret; 3169 if (byte_oriented) 3170 *data = (__force __u32)(cpu_to_be32(*data)); 3171 } 3172 return 0; 3173 } 3174 3175 /** 3176 * t4_write_flash - write up to a page of data to the serial flash 3177 * @adapter: the adapter 3178 * @addr: the start address to write 3179 * @n: length of data to write in bytes 3180 * @data: the data to write 3181 * @byte_oriented: whether to store data as bytes or as words 3182 * 3183 * Writes up to a page of data (256 bytes) to the serial flash starting 3184 * at the given address. All the data must be written to the same page. 3185 * If @byte_oriented is set the write data is stored as byte stream 3186 * (i.e. matches what on disk), otherwise in big-endian. 3187 */ 3188 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3189 unsigned int n, const u8 *data, int byte_oriented) 3190 { 3191 int ret; 3192 u32 buf[SF_PAGE_SIZE / 4]; 3193 unsigned int i, c, left, val, offset = addr & 0xff; 3194 3195 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3196 return -EINVAL; 3197 3198 val = swab32(addr) | SF_PROG_PAGE; 3199 3200 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3201 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3202 goto unlock; 3203 3204 for (left = n; left; left -= c) { 3205 c = min(left, 4U); 3206 for (val = 0, i = 0; i < c; ++i) 3207 val = (val << 8) + *data++; 3208 3209 if (!byte_oriented) 3210 val = cpu_to_be32(val); 3211 3212 ret = sf1_write(adapter, c, c != left, 1, val); 3213 if (ret) 3214 goto unlock; 3215 } 3216 ret = flash_wait_op(adapter, 8, 1); 3217 if (ret) 3218 goto unlock; 3219 3220 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3221 3222 /* Read the page to verify the write succeeded */ 3223 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3224 byte_oriented); 3225 if (ret) 3226 return ret; 3227 3228 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3229 CH_ERR(adapter, 3230 "failed to correctly write the flash page at %#x\n", 3231 addr); 3232 return -EIO; 3233 } 3234 return 0; 3235 3236 unlock: 3237 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3238 return ret; 3239 } 3240 3241 /** 3242 * t4_get_fw_version - read the firmware version 3243 * @adapter: the adapter 3244 * @vers: where to place the version 3245 * 3246 * Reads the FW version from flash. 3247 */ 3248 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3249 { 3250 return t4_read_flash(adapter, FLASH_FW_START + 3251 offsetof(struct fw_hdr, fw_ver), 1, 3252 vers, 0); 3253 } 3254 3255 /** 3256 * t4_get_bs_version - read the firmware bootstrap version 3257 * @adapter: the adapter 3258 * @vers: where to place the version 3259 * 3260 * Reads the FW Bootstrap version from flash. 3261 */ 3262 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3263 { 3264 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3265 offsetof(struct fw_hdr, fw_ver), 1, 3266 vers, 0); 3267 } 3268 3269 /** 3270 * t4_get_tp_version - read the TP microcode version 3271 * @adapter: the adapter 3272 * @vers: where to place the version 3273 * 3274 * Reads the TP microcode version from flash. 3275 */ 3276 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3277 { 3278 return t4_read_flash(adapter, FLASH_FW_START + 3279 offsetof(struct fw_hdr, tp_microcode_ver), 3280 1, vers, 0); 3281 } 3282 3283 /** 3284 * t4_get_exprom_version - return the Expansion ROM version (if any) 3285 * @adapter: the adapter 3286 * @vers: where to place the version 3287 * 3288 * Reads the Expansion ROM header from FLASH and returns the version 3289 * number (if present) through the @vers return value pointer. We return 3290 * this in the Firmware Version Format since it's convenient. Return 3291 * 0 on success, -ENOENT if no Expansion ROM is present. 3292 */ 3293 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 3294 { 3295 struct exprom_header { 3296 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3297 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3298 } *hdr; 3299 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3300 sizeof(u32))]; 3301 int ret; 3302 3303 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 3304 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3305 0); 3306 if (ret) 3307 return ret; 3308 3309 hdr = (struct exprom_header *)exprom_header_buf; 3310 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3311 return -ENOENT; 3312 3313 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3314 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3315 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3316 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3317 return 0; 3318 } 3319 3320 /** 3321 * t4_get_scfg_version - return the Serial Configuration version 3322 * @adapter: the adapter 3323 * @vers: where to place the version 3324 * 3325 * Reads the Serial Configuration Version via the Firmware interface 3326 * (thus this can only be called once we're ready to issue Firmware 3327 * commands). The format of the Serial Configuration version is 3328 * adapter specific. Returns 0 on success, an error on failure. 3329 * 3330 * Note that early versions of the Firmware didn't include the ability 3331 * to retrieve the Serial Configuration version, so we zero-out the 3332 * return-value parameter in that case to avoid leaving it with 3333 * garbage in it. 3334 * 3335 * Also note that the Firmware will return its cached copy of the Serial 3336 * Initialization Revision ID, not the actual Revision ID as written in 3337 * the Serial EEPROM. This is only an issue if a new VPD has been written 3338 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3339 * it's best to defer calling this routine till after a FW_RESET_CMD has 3340 * been issued if the Host Driver will be performing a full adapter 3341 * initialization. 3342 */ 3343 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3344 { 3345 u32 scfgrev_param; 3346 int ret; 3347 3348 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3349 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3350 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3351 1, &scfgrev_param, vers); 3352 if (ret) 3353 *vers = 0; 3354 return ret; 3355 } 3356 3357 /** 3358 * t4_get_vpd_version - return the VPD version 3359 * @adapter: the adapter 3360 * @vers: where to place the version 3361 * 3362 * Reads the VPD via the Firmware interface (thus this can only be called 3363 * once we're ready to issue Firmware commands). The format of the 3364 * VPD version is adapter specific. Returns 0 on success, an error on 3365 * failure. 3366 * 3367 * Note that early versions of the Firmware didn't include the ability 3368 * to retrieve the VPD version, so we zero-out the return-value parameter 3369 * in that case to avoid leaving it with garbage in it. 3370 * 3371 * Also note that the Firmware will return its cached copy of the VPD 3372 * Revision ID, not the actual Revision ID as written in the Serial 3373 * EEPROM. This is only an issue if a new VPD has been written and the 3374 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3375 * to defer calling this routine till after a FW_RESET_CMD has been issued 3376 * if the Host Driver will be performing a full adapter initialization. 3377 */ 3378 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3379 { 3380 u32 vpdrev_param; 3381 int ret; 3382 3383 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3384 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3385 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3386 1, &vpdrev_param, vers); 3387 if (ret) 3388 *vers = 0; 3389 return ret; 3390 } 3391 3392 /** 3393 * t4_get_version_info - extract various chip/firmware version information 3394 * @adapter: the adapter 3395 * 3396 * Reads various chip/firmware version numbers and stores them into the 3397 * adapter Adapter Parameters structure. If any of the efforts fails 3398 * the first failure will be returned, but all of the version numbers 3399 * will be read. 3400 */ 3401 int t4_get_version_info(struct adapter *adapter) 3402 { 3403 int ret = 0; 3404 3405 #define FIRST_RET(__getvinfo) \ 3406 do { \ 3407 int __ret = __getvinfo; \ 3408 if (__ret && !ret) \ 3409 ret = __ret; \ 3410 } while (0) 3411 3412 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3413 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3414 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3415 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3416 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3417 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3418 3419 #undef FIRST_RET 3420 3421 return ret; 3422 } 3423 3424 /** 3425 * t4_flash_erase_sectors - erase a range of flash sectors 3426 * @adapter: the adapter 3427 * @start: the first sector to erase 3428 * @end: the last sector to erase 3429 * 3430 * Erases the sectors in the given inclusive range. 3431 */ 3432 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3433 { 3434 int ret = 0; 3435 3436 if (end >= adapter->params.sf_nsec) 3437 return -EINVAL; 3438 3439 while (start <= end) { 3440 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3441 (ret = sf1_write(adapter, 4, 0, 1, 3442 SF_ERASE_SECTOR | (start << 8))) != 0 || 3443 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3444 CH_ERR(adapter, 3445 "erase of flash sector %d failed, error %d\n", 3446 start, ret); 3447 break; 3448 } 3449 start++; 3450 } 3451 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3452 return ret; 3453 } 3454 3455 /** 3456 * t4_flash_cfg_addr - return the address of the flash configuration file 3457 * @adapter: the adapter 3458 * 3459 * Return the address within the flash where the Firmware Configuration 3460 * File is stored, or an error if the device FLASH is too small to contain 3461 * a Firmware Configuration File. 3462 */ 3463 int t4_flash_cfg_addr(struct adapter *adapter) 3464 { 3465 /* 3466 * If the device FLASH isn't large enough to hold a Firmware 3467 * Configuration File, return an error. 3468 */ 3469 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3470 return -ENOSPC; 3471 3472 return FLASH_CFG_START; 3473 } 3474 3475 /* 3476 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3477 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3478 * and emit an error message for mismatched firmware to save our caller the 3479 * effort ... 3480 */ 3481 static int t4_fw_matches_chip(struct adapter *adap, 3482 const struct fw_hdr *hdr) 3483 { 3484 /* 3485 * The expression below will return FALSE for any unsupported adapter 3486 * which will keep us "honest" in the future ... 3487 */ 3488 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3489 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3490 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3491 return 1; 3492 3493 CH_ERR(adap, 3494 "FW image (%d) is not suitable for this adapter (%d)\n", 3495 hdr->chip, chip_id(adap)); 3496 return 0; 3497 } 3498 3499 /** 3500 * t4_load_fw - download firmware 3501 * @adap: the adapter 3502 * @fw_data: the firmware image to write 3503 * @size: image size 3504 * 3505 * Write the supplied firmware image to the card's serial flash. 3506 */ 3507 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3508 { 3509 u32 csum; 3510 int ret, addr; 3511 unsigned int i; 3512 u8 first_page[SF_PAGE_SIZE]; 3513 const u32 *p = (const u32 *)fw_data; 3514 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3515 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3516 unsigned int fw_start_sec; 3517 unsigned int fw_start; 3518 unsigned int fw_size; 3519 3520 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3521 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3522 fw_start = FLASH_FWBOOTSTRAP_START; 3523 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3524 } else { 3525 fw_start_sec = FLASH_FW_START_SEC; 3526 fw_start = FLASH_FW_START; 3527 fw_size = FLASH_FW_MAX_SIZE; 3528 } 3529 3530 if (!size) { 3531 CH_ERR(adap, "FW image has no data\n"); 3532 return -EINVAL; 3533 } 3534 if (size & 511) { 3535 CH_ERR(adap, 3536 "FW image size not multiple of 512 bytes\n"); 3537 return -EINVAL; 3538 } 3539 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3540 CH_ERR(adap, 3541 "FW image size differs from size in FW header\n"); 3542 return -EINVAL; 3543 } 3544 if (size > fw_size) { 3545 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3546 fw_size); 3547 return -EFBIG; 3548 } 3549 if (!t4_fw_matches_chip(adap, hdr)) 3550 return -EINVAL; 3551 3552 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3553 csum += be32_to_cpu(p[i]); 3554 3555 if (csum != 0xffffffff) { 3556 CH_ERR(adap, 3557 "corrupted firmware image, checksum %#x\n", csum); 3558 return -EINVAL; 3559 } 3560 3561 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3562 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3563 if (ret) 3564 goto out; 3565 3566 /* 3567 * We write the correct version at the end so the driver can see a bad 3568 * version if the FW write fails. Start by writing a copy of the 3569 * first page with a bad version. 3570 */ 3571 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3572 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3573 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3574 if (ret) 3575 goto out; 3576 3577 addr = fw_start; 3578 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3579 addr += SF_PAGE_SIZE; 3580 fw_data += SF_PAGE_SIZE; 3581 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3582 if (ret) 3583 goto out; 3584 } 3585 3586 ret = t4_write_flash(adap, 3587 fw_start + offsetof(struct fw_hdr, fw_ver), 3588 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3589 out: 3590 if (ret) 3591 CH_ERR(adap, "firmware download failed, error %d\n", 3592 ret); 3593 return ret; 3594 } 3595 3596 /** 3597 * t4_fwcache - firmware cache operation 3598 * @adap: the adapter 3599 * @op : the operation (flush or flush and invalidate) 3600 */ 3601 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3602 { 3603 struct fw_params_cmd c; 3604 3605 memset(&c, 0, sizeof(c)); 3606 c.op_to_vfn = 3607 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3608 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3609 V_FW_PARAMS_CMD_PFN(adap->pf) | 3610 V_FW_PARAMS_CMD_VFN(0)); 3611 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3612 c.param[0].mnem = 3613 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3614 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3615 c.param[0].val = (__force __be32)op; 3616 3617 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3618 } 3619 3620 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3621 unsigned int *pif_req_wrptr, 3622 unsigned int *pif_rsp_wrptr) 3623 { 3624 int i, j; 3625 u32 cfg, val, req, rsp; 3626 3627 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3628 if (cfg & F_LADBGEN) 3629 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3630 3631 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3632 req = G_POLADBGWRPTR(val); 3633 rsp = G_PILADBGWRPTR(val); 3634 if (pif_req_wrptr) 3635 *pif_req_wrptr = req; 3636 if (pif_rsp_wrptr) 3637 *pif_rsp_wrptr = rsp; 3638 3639 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3640 for (j = 0; j < 6; j++) { 3641 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3642 V_PILADBGRDPTR(rsp)); 3643 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3644 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3645 req++; 3646 rsp++; 3647 } 3648 req = (req + 2) & M_POLADBGRDPTR; 3649 rsp = (rsp + 2) & M_PILADBGRDPTR; 3650 } 3651 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3652 } 3653 3654 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3655 { 3656 u32 cfg; 3657 int i, j, idx; 3658 3659 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3660 if (cfg & F_LADBGEN) 3661 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3662 3663 for (i = 0; i < CIM_MALA_SIZE; i++) { 3664 for (j = 0; j < 5; j++) { 3665 idx = 8 * i + j; 3666 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3667 V_PILADBGRDPTR(idx)); 3668 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3669 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3670 } 3671 } 3672 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3673 } 3674 3675 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3676 { 3677 unsigned int i, j; 3678 3679 for (i = 0; i < 8; i++) { 3680 u32 *p = la_buf + i; 3681 3682 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3683 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3684 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3685 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3686 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3687 } 3688 } 3689 3690 /** 3691 * t4_link_l1cfg - apply link configuration to MAC/PHY 3692 * @phy: the PHY to setup 3693 * @mac: the MAC to setup 3694 * @lc: the requested link configuration 3695 * 3696 * Set up a port's MAC and PHY according to a desired link configuration. 3697 * - If the PHY can auto-negotiate first decide what to advertise, then 3698 * enable/disable auto-negotiation as desired, and reset. 3699 * - If the PHY does not auto-negotiate just reset it. 3700 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3701 * otherwise do it later based on the outcome of auto-negotiation. 3702 */ 3703 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3704 struct link_config *lc) 3705 { 3706 struct fw_port_cmd c; 3707 unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO); 3708 unsigned int aneg, fc, fec, speed, rcap; 3709 3710 fc = 0; 3711 if (lc->requested_fc & PAUSE_RX) 3712 fc |= FW_PORT_CAP_FC_RX; 3713 if (lc->requested_fc & PAUSE_TX) 3714 fc |= FW_PORT_CAP_FC_TX; 3715 3716 fec = 0; 3717 if (lc->requested_fec & FEC_RS) 3718 fec = FW_PORT_CAP_FEC_RS; 3719 else if (lc->requested_fec & FEC_BASER_RS) 3720 fec = FW_PORT_CAP_FEC_BASER_RS; 3721 else if (lc->requested_fec & FEC_RESERVED) 3722 fec = FW_PORT_CAP_FEC_RESERVED; 3723 3724 if (!(lc->supported & FW_PORT_CAP_ANEG) || 3725 lc->requested_aneg == AUTONEG_DISABLE) { 3726 aneg = 0; 3727 switch (lc->requested_speed) { 3728 case 100: 3729 speed = FW_PORT_CAP_SPEED_100G; 3730 break; 3731 case 40: 3732 speed = FW_PORT_CAP_SPEED_40G; 3733 break; 3734 case 25: 3735 speed = FW_PORT_CAP_SPEED_25G; 3736 break; 3737 case 10: 3738 speed = FW_PORT_CAP_SPEED_10G; 3739 break; 3740 case 1: 3741 speed = FW_PORT_CAP_SPEED_1G; 3742 break; 3743 default: 3744 return -EINVAL; 3745 break; 3746 } 3747 } else { 3748 aneg = FW_PORT_CAP_ANEG; 3749 speed = lc->supported & 3750 V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED); 3751 } 3752 3753 rcap = aneg | speed | fc | fec; 3754 if ((rcap | lc->supported) != lc->supported) { 3755 #ifdef INVARIANTS 3756 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x\n", rcap, 3757 lc->supported); 3758 #endif 3759 rcap &= lc->supported; 3760 } 3761 rcap |= mdi; 3762 3763 memset(&c, 0, sizeof(c)); 3764 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3765 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3766 V_FW_PORT_CMD_PORTID(port)); 3767 c.action_to_len16 = 3768 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3769 FW_LEN16(c)); 3770 c.u.l1cfg.rcap = cpu_to_be32(rcap); 3771 3772 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3773 } 3774 3775 /** 3776 * t4_restart_aneg - restart autonegotiation 3777 * @adap: the adapter 3778 * @mbox: mbox to use for the FW command 3779 * @port: the port id 3780 * 3781 * Restarts autonegotiation for the selected port. 3782 */ 3783 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3784 { 3785 struct fw_port_cmd c; 3786 3787 memset(&c, 0, sizeof(c)); 3788 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3789 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3790 V_FW_PORT_CMD_PORTID(port)); 3791 c.action_to_len16 = 3792 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3793 FW_LEN16(c)); 3794 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3795 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3796 } 3797 3798 typedef void (*int_handler_t)(struct adapter *adap); 3799 3800 struct intr_info { 3801 unsigned int mask; /* bits to check in interrupt status */ 3802 const char *msg; /* message to print or NULL */ 3803 short stat_idx; /* stat counter to increment or -1 */ 3804 unsigned short fatal; /* whether the condition reported is fatal */ 3805 int_handler_t int_handler; /* platform-specific int handler */ 3806 }; 3807 3808 /** 3809 * t4_handle_intr_status - table driven interrupt handler 3810 * @adapter: the adapter that generated the interrupt 3811 * @reg: the interrupt status register to process 3812 * @acts: table of interrupt actions 3813 * 3814 * A table driven interrupt handler that applies a set of masks to an 3815 * interrupt status word and performs the corresponding actions if the 3816 * interrupts described by the mask have occurred. The actions include 3817 * optionally emitting a warning or alert message. The table is terminated 3818 * by an entry specifying mask 0. Returns the number of fatal interrupt 3819 * conditions. 3820 */ 3821 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 3822 const struct intr_info *acts) 3823 { 3824 int fatal = 0; 3825 unsigned int mask = 0; 3826 unsigned int status = t4_read_reg(adapter, reg); 3827 3828 for ( ; acts->mask; ++acts) { 3829 if (!(status & acts->mask)) 3830 continue; 3831 if (acts->fatal) { 3832 fatal++; 3833 CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, 3834 status & acts->mask); 3835 } else if (acts->msg) 3836 CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg, 3837 status & acts->mask); 3838 if (acts->int_handler) 3839 acts->int_handler(adapter); 3840 mask |= acts->mask; 3841 } 3842 status &= mask; 3843 if (status) /* clear processed interrupts */ 3844 t4_write_reg(adapter, reg, status); 3845 return fatal; 3846 } 3847 3848 /* 3849 * Interrupt handler for the PCIE module. 3850 */ 3851 static void pcie_intr_handler(struct adapter *adapter) 3852 { 3853 static const struct intr_info sysbus_intr_info[] = { 3854 { F_RNPP, "RXNP array parity error", -1, 1 }, 3855 { F_RPCP, "RXPC array parity error", -1, 1 }, 3856 { F_RCIP, "RXCIF array parity error", -1, 1 }, 3857 { F_RCCP, "Rx completions control array parity error", -1, 1 }, 3858 { F_RFTP, "RXFT array parity error", -1, 1 }, 3859 { 0 } 3860 }; 3861 static const struct intr_info pcie_port_intr_info[] = { 3862 { F_TPCP, "TXPC array parity error", -1, 1 }, 3863 { F_TNPP, "TXNP array parity error", -1, 1 }, 3864 { F_TFTP, "TXFT array parity error", -1, 1 }, 3865 { F_TCAP, "TXCA array parity error", -1, 1 }, 3866 { F_TCIP, "TXCIF array parity error", -1, 1 }, 3867 { F_RCAP, "RXCA array parity error", -1, 1 }, 3868 { F_OTDD, "outbound request TLP discarded", -1, 1 }, 3869 { F_RDPE, "Rx data parity error", -1, 1 }, 3870 { F_TDUE, "Tx uncorrectable data error", -1, 1 }, 3871 { 0 } 3872 }; 3873 static const struct intr_info pcie_intr_info[] = { 3874 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 3875 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 3876 { F_MSIDATAPERR, "MSI data parity error", -1, 1 }, 3877 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 3878 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 3879 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 3880 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 3881 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 3882 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 3883 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 3884 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 3885 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 3886 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 3887 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 3888 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 3889 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 3890 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 3891 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 3892 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 3893 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 3894 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 3895 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 3896 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 }, 3897 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 3898 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 3899 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 }, 3900 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 }, 3901 { F_PCIESINT, "PCI core secondary fault", -1, 1 }, 3902 { F_PCIEPINT, "PCI core primary fault", -1, 1 }, 3903 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1, 3904 0 }, 3905 { 0 } 3906 }; 3907 3908 static const struct intr_info t5_pcie_intr_info[] = { 3909 { F_MSTGRPPERR, "Master Response Read Queue parity error", 3910 -1, 1 }, 3911 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 3912 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 3913 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 3914 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 3915 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 3916 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 3917 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 3918 -1, 1 }, 3919 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 3920 -1, 1 }, 3921 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 3922 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 3923 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 3924 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 3925 { F_DREQWRPERR, "PCI DMA channel write request parity error", 3926 -1, 1 }, 3927 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 3928 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 3929 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 3930 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 3931 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 3932 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 3933 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 3934 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 3935 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 3936 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 3937 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 3938 -1, 1 }, 3939 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 3940 -1, 1 }, 3941 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 3942 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 3943 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 3944 { F_READRSPERR, "Outbound read error", -1, 3945 0 }, 3946 { 0 } 3947 }; 3948 3949 int fat; 3950 3951 if (is_t4(adapter)) 3952 fat = t4_handle_intr_status(adapter, 3953 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 3954 sysbus_intr_info) + 3955 t4_handle_intr_status(adapter, 3956 A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 3957 pcie_port_intr_info) + 3958 t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 3959 pcie_intr_info); 3960 else 3961 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 3962 t5_pcie_intr_info); 3963 if (fat) 3964 t4_fatal_err(adapter); 3965 } 3966 3967 /* 3968 * TP interrupt handler. 3969 */ 3970 static void tp_intr_handler(struct adapter *adapter) 3971 { 3972 static const struct intr_info tp_intr_info[] = { 3973 { 0x3fffffff, "TP parity error", -1, 1 }, 3974 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 3975 { 0 } 3976 }; 3977 3978 if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info)) 3979 t4_fatal_err(adapter); 3980 } 3981 3982 /* 3983 * SGE interrupt handler. 3984 */ 3985 static void sge_intr_handler(struct adapter *adapter) 3986 { 3987 u64 v; 3988 u32 err; 3989 3990 static const struct intr_info sge_intr_info[] = { 3991 { F_ERR_CPL_EXCEED_IQE_SIZE, 3992 "SGE received CPL exceeding IQE size", -1, 1 }, 3993 { F_ERR_INVALID_CIDX_INC, 3994 "SGE GTS CIDX increment too large", -1, 0 }, 3995 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 3996 { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, 3997 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 3998 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 3999 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 4000 0 }, 4001 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 4002 0 }, 4003 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 4004 0 }, 4005 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 4006 0 }, 4007 { F_ERR_ING_CTXT_PRIO, 4008 "SGE too many priority ingress contexts", -1, 0 }, 4009 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 4010 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 4011 { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | 4012 F_ERR_PCIE_ERROR2 | F_ERR_PCIE_ERROR3, 4013 "SGE PCIe error for a DBP thread", -1, 0 }, 4014 { 0 } 4015 }; 4016 4017 static const struct intr_info t4t5_sge_intr_info[] = { 4018 { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, 4019 { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, 4020 { F_ERR_EGR_CTXT_PRIO, 4021 "SGE too many priority egress contexts", -1, 0 }, 4022 { 0 } 4023 }; 4024 4025 /* 4026 * For now, treat below interrupts as fatal so that we disable SGE and 4027 * get better debug */ 4028 static const struct intr_info t6_sge_intr_info[] = { 4029 { F_FATAL_WRE_LEN, 4030 "SGE Actual WRE packet is less than advertized length", 4031 -1, 1 }, 4032 { 0 } 4033 }; 4034 4035 v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | 4036 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); 4037 if (v) { 4038 CH_ALERT(adapter, "SGE parity error (%#llx)\n", 4039 (unsigned long long)v); 4040 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); 4041 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); 4042 } 4043 4044 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info); 4045 if (chip_id(adapter) <= CHELSIO_T5) 4046 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4047 t4t5_sge_intr_info); 4048 else 4049 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4050 t6_sge_intr_info); 4051 4052 err = t4_read_reg(adapter, A_SGE_ERROR_STATS); 4053 if (err & F_ERROR_QID_VALID) { 4054 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err)); 4055 if (err & F_UNCAPTURED_ERROR) 4056 CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4057 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID | 4058 F_UNCAPTURED_ERROR); 4059 } 4060 4061 if (v != 0) 4062 t4_fatal_err(adapter); 4063 } 4064 4065 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\ 4066 F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR) 4067 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\ 4068 F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR) 4069 4070 /* 4071 * CIM interrupt handler. 4072 */ 4073 static void cim_intr_handler(struct adapter *adapter) 4074 { 4075 static const struct intr_info cim_intr_info[] = { 4076 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 4077 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 4078 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 4079 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 4080 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 4081 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 4082 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 4083 { F_TIMER0INT, "CIM TIMER0 interrupt", -1, 1 }, 4084 { 0 } 4085 }; 4086 static const struct intr_info cim_upintr_info[] = { 4087 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 4088 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 4089 { F_ILLWRINT, "CIM illegal write", -1, 1 }, 4090 { F_ILLRDINT, "CIM illegal read", -1, 1 }, 4091 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 4092 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 4093 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 4094 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 4095 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 4096 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 4097 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 4098 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 4099 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 4100 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 4101 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 4102 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 4103 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 4104 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 4105 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 4106 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 4107 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 4108 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 4109 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 4110 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 4111 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 4112 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 4113 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 4114 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 4115 { 0 } 4116 }; 4117 u32 val, fw_err; 4118 int fat; 4119 4120 fw_err = t4_read_reg(adapter, A_PCIE_FW); 4121 if (fw_err & F_PCIE_FW_ERR) 4122 t4_report_fw_error(adapter); 4123 4124 /* When the Firmware detects an internal error which normally wouldn't 4125 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4126 * to make sure the Host sees the Firmware Crash. So if we have a 4127 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4128 * interrupt. 4129 */ 4130 val = t4_read_reg(adapter, A_CIM_HOST_INT_CAUSE); 4131 if (val & F_TIMER0INT) 4132 if (!(fw_err & F_PCIE_FW_ERR) || 4133 (G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) 4134 t4_write_reg(adapter, A_CIM_HOST_INT_CAUSE, 4135 F_TIMER0INT); 4136 4137 fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 4138 cim_intr_info) + 4139 t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE, 4140 cim_upintr_info); 4141 if (fat) 4142 t4_fatal_err(adapter); 4143 } 4144 4145 /* 4146 * ULP RX interrupt handler. 4147 */ 4148 static void ulprx_intr_handler(struct adapter *adapter) 4149 { 4150 static const struct intr_info ulprx_intr_info[] = { 4151 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 }, 4152 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 }, 4153 { 0x7fffff, "ULPRX parity error", -1, 1 }, 4154 { 0 } 4155 }; 4156 4157 if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info)) 4158 t4_fatal_err(adapter); 4159 } 4160 4161 /* 4162 * ULP TX interrupt handler. 4163 */ 4164 static void ulptx_intr_handler(struct adapter *adapter) 4165 { 4166 static const struct intr_info ulptx_intr_info[] = { 4167 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 4168 0 }, 4169 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 4170 0 }, 4171 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 4172 0 }, 4173 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 4174 0 }, 4175 { 0xfffffff, "ULPTX parity error", -1, 1 }, 4176 { 0 } 4177 }; 4178 4179 if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info)) 4180 t4_fatal_err(adapter); 4181 } 4182 4183 /* 4184 * PM TX interrupt handler. 4185 */ 4186 static void pmtx_intr_handler(struct adapter *adapter) 4187 { 4188 static const struct intr_info pmtx_intr_info[] = { 4189 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 4190 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 4191 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 4192 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 4193 { 0xffffff0, "PMTX framing error", -1, 1 }, 4194 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 4195 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 4196 1 }, 4197 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 4198 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 4199 { 0 } 4200 }; 4201 4202 if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info)) 4203 t4_fatal_err(adapter); 4204 } 4205 4206 /* 4207 * PM RX interrupt handler. 4208 */ 4209 static void pmrx_intr_handler(struct adapter *adapter) 4210 { 4211 static const struct intr_info pmrx_intr_info[] = { 4212 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 4213 { 0x3ffff0, "PMRX framing error", -1, 1 }, 4214 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 4215 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 4216 1 }, 4217 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 4218 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 4219 { 0 } 4220 }; 4221 4222 if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info)) 4223 t4_fatal_err(adapter); 4224 } 4225 4226 /* 4227 * CPL switch interrupt handler. 4228 */ 4229 static void cplsw_intr_handler(struct adapter *adapter) 4230 { 4231 static const struct intr_info cplsw_intr_info[] = { 4232 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 4233 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 4234 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 4235 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 4236 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 4237 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 4238 { 0 } 4239 }; 4240 4241 if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info)) 4242 t4_fatal_err(adapter); 4243 } 4244 4245 /* 4246 * LE interrupt handler. 4247 */ 4248 static void le_intr_handler(struct adapter *adap) 4249 { 4250 unsigned int chip_ver = chip_id(adap); 4251 static const struct intr_info le_intr_info[] = { 4252 { F_LIPMISS, "LE LIP miss", -1, 0 }, 4253 { F_LIP0, "LE 0 LIP error", -1, 0 }, 4254 { F_PARITYERR, "LE parity error", -1, 1 }, 4255 { F_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4256 { F_REQQPARERR, "LE request queue parity error", -1, 1 }, 4257 { 0 } 4258 }; 4259 4260 static const struct intr_info t6_le_intr_info[] = { 4261 { F_T6_LIPMISS, "LE LIP miss", -1, 0 }, 4262 { F_T6_LIP0, "LE 0 LIP error", -1, 0 }, 4263 { F_TCAMINTPERR, "LE parity error", -1, 1 }, 4264 { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4265 { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 }, 4266 { 0 } 4267 }; 4268 4269 if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, 4270 (chip_ver <= CHELSIO_T5) ? 4271 le_intr_info : t6_le_intr_info)) 4272 t4_fatal_err(adap); 4273 } 4274 4275 /* 4276 * MPS interrupt handler. 4277 */ 4278 static void mps_intr_handler(struct adapter *adapter) 4279 { 4280 static const struct intr_info mps_rx_intr_info[] = { 4281 { 0xffffff, "MPS Rx parity error", -1, 1 }, 4282 { 0 } 4283 }; 4284 static const struct intr_info mps_tx_intr_info[] = { 4285 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 }, 4286 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 4287 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error", 4288 -1, 1 }, 4289 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error", 4290 -1, 1 }, 4291 { F_BUBBLE, "MPS Tx underflow", -1, 1 }, 4292 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 4293 { F_FRMERR, "MPS Tx framing error", -1, 1 }, 4294 { 0 } 4295 }; 4296 static const struct intr_info mps_trc_intr_info[] = { 4297 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 }, 4298 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1, 4299 1 }, 4300 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 }, 4301 { 0 } 4302 }; 4303 static const struct intr_info mps_stat_sram_intr_info[] = { 4304 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 4305 { 0 } 4306 }; 4307 static const struct intr_info mps_stat_tx_intr_info[] = { 4308 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 4309 { 0 } 4310 }; 4311 static const struct intr_info mps_stat_rx_intr_info[] = { 4312 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 4313 { 0 } 4314 }; 4315 static const struct intr_info mps_cls_intr_info[] = { 4316 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 4317 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 4318 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 4319 { 0 } 4320 }; 4321 4322 int fat; 4323 4324 fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE, 4325 mps_rx_intr_info) + 4326 t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE, 4327 mps_tx_intr_info) + 4328 t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE, 4329 mps_trc_intr_info) + 4330 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4331 mps_stat_sram_intr_info) + 4332 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4333 mps_stat_tx_intr_info) + 4334 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4335 mps_stat_rx_intr_info) + 4336 t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE, 4337 mps_cls_intr_info); 4338 4339 t4_write_reg(adapter, A_MPS_INT_CAUSE, 0); 4340 t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ 4341 if (fat) 4342 t4_fatal_err(adapter); 4343 } 4344 4345 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \ 4346 F_ECC_UE_INT_CAUSE) 4347 4348 /* 4349 * EDC/MC interrupt handler. 4350 */ 4351 static void mem_intr_handler(struct adapter *adapter, int idx) 4352 { 4353 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; 4354 4355 unsigned int addr, cnt_addr, v; 4356 4357 if (idx <= MEM_EDC1) { 4358 addr = EDC_REG(A_EDC_INT_CAUSE, idx); 4359 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); 4360 } else if (idx == MEM_MC) { 4361 if (is_t4(adapter)) { 4362 addr = A_MC_INT_CAUSE; 4363 cnt_addr = A_MC_ECC_STATUS; 4364 } else { 4365 addr = A_MC_P_INT_CAUSE; 4366 cnt_addr = A_MC_P_ECC_STATUS; 4367 } 4368 } else { 4369 addr = MC_REG(A_MC_P_INT_CAUSE, 1); 4370 cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1); 4371 } 4372 4373 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 4374 if (v & F_PERR_INT_CAUSE) 4375 CH_ALERT(adapter, "%s FIFO parity error\n", 4376 name[idx]); 4377 if (v & F_ECC_CE_INT_CAUSE) { 4378 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); 4379 4380 if (idx <= MEM_EDC1) 4381 t4_edc_err_read(adapter, idx); 4382 4383 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); 4384 CH_WARN_RATELIMIT(adapter, 4385 "%u %s correctable ECC data error%s\n", 4386 cnt, name[idx], cnt > 1 ? "s" : ""); 4387 } 4388 if (v & F_ECC_UE_INT_CAUSE) 4389 CH_ALERT(adapter, 4390 "%s uncorrectable ECC data error\n", name[idx]); 4391 4392 t4_write_reg(adapter, addr, v); 4393 if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE)) 4394 t4_fatal_err(adapter); 4395 } 4396 4397 /* 4398 * MA interrupt handler. 4399 */ 4400 static void ma_intr_handler(struct adapter *adapter) 4401 { 4402 u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); 4403 4404 if (status & F_MEM_PERR_INT_CAUSE) { 4405 CH_ALERT(adapter, 4406 "MA parity error, parity status %#x\n", 4407 t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); 4408 if (is_t5(adapter)) 4409 CH_ALERT(adapter, 4410 "MA parity error, parity status %#x\n", 4411 t4_read_reg(adapter, 4412 A_MA_PARITY_ERROR_STATUS2)); 4413 } 4414 if (status & F_MEM_WRAP_INT_CAUSE) { 4415 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); 4416 CH_ALERT(adapter, "MA address wrap-around error by " 4417 "client %u to address %#x\n", 4418 G_MEM_WRAP_CLIENT_NUM(v), 4419 G_MEM_WRAP_ADDRESS(v) << 4); 4420 } 4421 t4_write_reg(adapter, A_MA_INT_CAUSE, status); 4422 t4_fatal_err(adapter); 4423 } 4424 4425 /* 4426 * SMB interrupt handler. 4427 */ 4428 static void smb_intr_handler(struct adapter *adap) 4429 { 4430 static const struct intr_info smb_intr_info[] = { 4431 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 4432 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 4433 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 4434 { 0 } 4435 }; 4436 4437 if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info)) 4438 t4_fatal_err(adap); 4439 } 4440 4441 /* 4442 * NC-SI interrupt handler. 4443 */ 4444 static void ncsi_intr_handler(struct adapter *adap) 4445 { 4446 static const struct intr_info ncsi_intr_info[] = { 4447 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 4448 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 4449 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 4450 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 4451 { 0 } 4452 }; 4453 4454 if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info)) 4455 t4_fatal_err(adap); 4456 } 4457 4458 /* 4459 * XGMAC interrupt handler. 4460 */ 4461 static void xgmac_intr_handler(struct adapter *adap, int port) 4462 { 4463 u32 v, int_cause_reg; 4464 4465 if (is_t4(adap)) 4466 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 4467 else 4468 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 4469 4470 v = t4_read_reg(adap, int_cause_reg); 4471 4472 v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); 4473 if (!v) 4474 return; 4475 4476 if (v & F_TXFIFO_PRTY_ERR) 4477 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", 4478 port); 4479 if (v & F_RXFIFO_PRTY_ERR) 4480 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", 4481 port); 4482 t4_write_reg(adap, int_cause_reg, v); 4483 t4_fatal_err(adap); 4484 } 4485 4486 /* 4487 * PL interrupt handler. 4488 */ 4489 static void pl_intr_handler(struct adapter *adap) 4490 { 4491 static const struct intr_info pl_intr_info[] = { 4492 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4493 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 4494 { 0 } 4495 }; 4496 4497 static const struct intr_info t5_pl_intr_info[] = { 4498 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4499 { 0 } 4500 }; 4501 4502 if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, 4503 is_t4(adap) ? 4504 pl_intr_info : t5_pl_intr_info)) 4505 t4_fatal_err(adap); 4506 } 4507 4508 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 4509 4510 /** 4511 * t4_slow_intr_handler - control path interrupt handler 4512 * @adapter: the adapter 4513 * 4514 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 4515 * The designation 'slow' is because it involves register reads, while 4516 * data interrupts typically don't involve any MMIOs. 4517 */ 4518 int t4_slow_intr_handler(struct adapter *adapter) 4519 { 4520 u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE); 4521 4522 if (!(cause & GLBL_INTR_MASK)) 4523 return 0; 4524 if (cause & F_CIM) 4525 cim_intr_handler(adapter); 4526 if (cause & F_MPS) 4527 mps_intr_handler(adapter); 4528 if (cause & F_NCSI) 4529 ncsi_intr_handler(adapter); 4530 if (cause & F_PL) 4531 pl_intr_handler(adapter); 4532 if (cause & F_SMB) 4533 smb_intr_handler(adapter); 4534 if (cause & F_MAC0) 4535 xgmac_intr_handler(adapter, 0); 4536 if (cause & F_MAC1) 4537 xgmac_intr_handler(adapter, 1); 4538 if (cause & F_MAC2) 4539 xgmac_intr_handler(adapter, 2); 4540 if (cause & F_MAC3) 4541 xgmac_intr_handler(adapter, 3); 4542 if (cause & F_PCIE) 4543 pcie_intr_handler(adapter); 4544 if (cause & F_MC0) 4545 mem_intr_handler(adapter, MEM_MC); 4546 if (is_t5(adapter) && (cause & F_MC1)) 4547 mem_intr_handler(adapter, MEM_MC1); 4548 if (cause & F_EDC0) 4549 mem_intr_handler(adapter, MEM_EDC0); 4550 if (cause & F_EDC1) 4551 mem_intr_handler(adapter, MEM_EDC1); 4552 if (cause & F_LE) 4553 le_intr_handler(adapter); 4554 if (cause & F_TP) 4555 tp_intr_handler(adapter); 4556 if (cause & F_MA) 4557 ma_intr_handler(adapter); 4558 if (cause & F_PM_TX) 4559 pmtx_intr_handler(adapter); 4560 if (cause & F_PM_RX) 4561 pmrx_intr_handler(adapter); 4562 if (cause & F_ULP_RX) 4563 ulprx_intr_handler(adapter); 4564 if (cause & F_CPL_SWITCH) 4565 cplsw_intr_handler(adapter); 4566 if (cause & F_SGE) 4567 sge_intr_handler(adapter); 4568 if (cause & F_ULP_TX) 4569 ulptx_intr_handler(adapter); 4570 4571 /* Clear the interrupts just processed for which we are the master. */ 4572 t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK); 4573 (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4574 return 1; 4575 } 4576 4577 /** 4578 * t4_intr_enable - enable interrupts 4579 * @adapter: the adapter whose interrupts should be enabled 4580 * 4581 * Enable PF-specific interrupts for the calling function and the top-level 4582 * interrupt concentrator for global interrupts. Interrupts are already 4583 * enabled at each module, here we just enable the roots of the interrupt 4584 * hierarchies. 4585 * 4586 * Note: this function should be called only when the driver manages 4587 * non PF-specific interrupts from the various HW modules. Only one PCI 4588 * function at a time should be doing this. 4589 */ 4590 void t4_intr_enable(struct adapter *adapter) 4591 { 4592 u32 val = 0; 4593 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4594 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4595 ? G_SOURCEPF(whoami) 4596 : G_T6_SOURCEPF(whoami)); 4597 4598 if (chip_id(adapter) <= CHELSIO_T5) 4599 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 4600 else 4601 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 4602 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE | 4603 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 | 4604 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR | 4605 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 | 4606 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4607 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | 4608 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val); 4609 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 4610 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf); 4611 } 4612 4613 /** 4614 * t4_intr_disable - disable interrupts 4615 * @adapter: the adapter whose interrupts should be disabled 4616 * 4617 * Disable interrupts. We only disable the top-level interrupt 4618 * concentrators. The caller must be a PCI function managing global 4619 * interrupts. 4620 */ 4621 void t4_intr_disable(struct adapter *adapter) 4622 { 4623 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4624 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4625 ? G_SOURCEPF(whoami) 4626 : G_T6_SOURCEPF(whoami)); 4627 4628 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 4629 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0); 4630 } 4631 4632 /** 4633 * t4_intr_clear - clear all interrupts 4634 * @adapter: the adapter whose interrupts should be cleared 4635 * 4636 * Clears all interrupts. The caller must be a PCI function managing 4637 * global interrupts. 4638 */ 4639 void t4_intr_clear(struct adapter *adapter) 4640 { 4641 static const unsigned int cause_reg[] = { 4642 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3, 4643 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, 4644 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE, 4645 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), 4646 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, 4647 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4648 A_TP_INT_CAUSE, 4649 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE, 4650 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE, 4651 A_MPS_RX_PERR_INT_CAUSE, 4652 A_CPL_INTR_CAUSE, 4653 MYPF_REG(A_PL_PF_INT_CAUSE), 4654 A_PL_PL_INT_CAUSE, 4655 A_LE_DB_INT_CAUSE, 4656 }; 4657 4658 unsigned int i; 4659 4660 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) 4661 t4_write_reg(adapter, cause_reg[i], 0xffffffff); 4662 4663 t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : 4664 A_MC_P_INT_CAUSE, 0xffffffff); 4665 4666 if (is_t4(adapter)) { 4667 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4668 0xffffffff); 4669 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4670 0xffffffff); 4671 } else 4672 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 4673 4674 t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); 4675 (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4676 } 4677 4678 /** 4679 * hash_mac_addr - return the hash value of a MAC address 4680 * @addr: the 48-bit Ethernet MAC address 4681 * 4682 * Hashes a MAC address according to the hash function used by HW inexact 4683 * (hash) address matching. 4684 */ 4685 static int hash_mac_addr(const u8 *addr) 4686 { 4687 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 4688 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 4689 a ^= b; 4690 a ^= (a >> 12); 4691 a ^= (a >> 6); 4692 return a & 0x3f; 4693 } 4694 4695 /** 4696 * t4_config_rss_range - configure a portion of the RSS mapping table 4697 * @adapter: the adapter 4698 * @mbox: mbox to use for the FW command 4699 * @viid: virtual interface whose RSS subtable is to be written 4700 * @start: start entry in the table to write 4701 * @n: how many table entries to write 4702 * @rspq: values for the "response queue" (Ingress Queue) lookup table 4703 * @nrspq: number of values in @rspq 4704 * 4705 * Programs the selected part of the VI's RSS mapping table with the 4706 * provided values. If @nrspq < @n the supplied values are used repeatedly 4707 * until the full table range is populated. 4708 * 4709 * The caller must ensure the values in @rspq are in the range allowed for 4710 * @viid. 4711 */ 4712 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 4713 int start, int n, const u16 *rspq, unsigned int nrspq) 4714 { 4715 int ret; 4716 const u16 *rsp = rspq; 4717 const u16 *rsp_end = rspq + nrspq; 4718 struct fw_rss_ind_tbl_cmd cmd; 4719 4720 memset(&cmd, 0, sizeof(cmd)); 4721 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 4722 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4723 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 4724 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 4725 4726 /* 4727 * Each firmware RSS command can accommodate up to 32 RSS Ingress 4728 * Queue Identifiers. These Ingress Queue IDs are packed three to 4729 * a 32-bit word as 10-bit values with the upper remaining 2 bits 4730 * reserved. 4731 */ 4732 while (n > 0) { 4733 int nq = min(n, 32); 4734 int nq_packed = 0; 4735 __be32 *qp = &cmd.iq0_to_iq2; 4736 4737 /* 4738 * Set up the firmware RSS command header to send the next 4739 * "nq" Ingress Queue IDs to the firmware. 4740 */ 4741 cmd.niqid = cpu_to_be16(nq); 4742 cmd.startidx = cpu_to_be16(start); 4743 4744 /* 4745 * "nq" more done for the start of the next loop. 4746 */ 4747 start += nq; 4748 n -= nq; 4749 4750 /* 4751 * While there are still Ingress Queue IDs to stuff into the 4752 * current firmware RSS command, retrieve them from the 4753 * Ingress Queue ID array and insert them into the command. 4754 */ 4755 while (nq > 0) { 4756 /* 4757 * Grab up to the next 3 Ingress Queue IDs (wrapping 4758 * around the Ingress Queue ID array if necessary) and 4759 * insert them into the firmware RSS command at the 4760 * current 3-tuple position within the commad. 4761 */ 4762 u16 qbuf[3]; 4763 u16 *qbp = qbuf; 4764 int nqbuf = min(3, nq); 4765 4766 nq -= nqbuf; 4767 qbuf[0] = qbuf[1] = qbuf[2] = 0; 4768 while (nqbuf && nq_packed < 32) { 4769 nqbuf--; 4770 nq_packed++; 4771 *qbp++ = *rsp++; 4772 if (rsp >= rsp_end) 4773 rsp = rspq; 4774 } 4775 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 4776 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 4777 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 4778 } 4779 4780 /* 4781 * Send this portion of the RRS table update to the firmware; 4782 * bail out on any errors. 4783 */ 4784 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 4785 if (ret) 4786 return ret; 4787 } 4788 return 0; 4789 } 4790 4791 /** 4792 * t4_config_glbl_rss - configure the global RSS mode 4793 * @adapter: the adapter 4794 * @mbox: mbox to use for the FW command 4795 * @mode: global RSS mode 4796 * @flags: mode-specific flags 4797 * 4798 * Sets the global RSS mode. 4799 */ 4800 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 4801 unsigned int flags) 4802 { 4803 struct fw_rss_glb_config_cmd c; 4804 4805 memset(&c, 0, sizeof(c)); 4806 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 4807 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 4808 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4809 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 4810 c.u.manual.mode_pkd = 4811 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4812 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 4813 c.u.basicvirtual.mode_keymode = 4814 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4815 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 4816 } else 4817 return -EINVAL; 4818 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4819 } 4820 4821 /** 4822 * t4_config_vi_rss - configure per VI RSS settings 4823 * @adapter: the adapter 4824 * @mbox: mbox to use for the FW command 4825 * @viid: the VI id 4826 * @flags: RSS flags 4827 * @defq: id of the default RSS queue for the VI. 4828 * @skeyidx: RSS secret key table index for non-global mode 4829 * @skey: RSS vf_scramble key for VI. 4830 * 4831 * Configures VI-specific RSS properties. 4832 */ 4833 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 4834 unsigned int flags, unsigned int defq, unsigned int skeyidx, 4835 unsigned int skey) 4836 { 4837 struct fw_rss_vi_config_cmd c; 4838 4839 memset(&c, 0, sizeof(c)); 4840 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 4841 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4842 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 4843 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4844 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 4845 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 4846 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 4847 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 4848 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 4849 4850 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4851 } 4852 4853 /* Read an RSS table row */ 4854 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 4855 { 4856 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 4857 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 4858 5, 0, val); 4859 } 4860 4861 /** 4862 * t4_read_rss - read the contents of the RSS mapping table 4863 * @adapter: the adapter 4864 * @map: holds the contents of the RSS mapping table 4865 * 4866 * Reads the contents of the RSS hash->queue mapping table. 4867 */ 4868 int t4_read_rss(struct adapter *adapter, u16 *map) 4869 { 4870 u32 val; 4871 int i, ret; 4872 4873 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 4874 ret = rd_rss_row(adapter, i, &val); 4875 if (ret) 4876 return ret; 4877 *map++ = G_LKPTBLQUEUE0(val); 4878 *map++ = G_LKPTBLQUEUE1(val); 4879 } 4880 return 0; 4881 } 4882 4883 /** 4884 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 4885 * @adap: the adapter 4886 * @cmd: TP fw ldst address space type 4887 * @vals: where the indirect register values are stored/written 4888 * @nregs: how many indirect registers to read/write 4889 * @start_idx: index of first indirect register to read/write 4890 * @rw: Read (1) or Write (0) 4891 * @sleep_ok: if true we may sleep while awaiting command completion 4892 * 4893 * Access TP indirect registers through LDST 4894 **/ 4895 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 4896 unsigned int nregs, unsigned int start_index, 4897 unsigned int rw, bool sleep_ok) 4898 { 4899 int ret = 0; 4900 unsigned int i; 4901 struct fw_ldst_cmd c; 4902 4903 for (i = 0; i < nregs; i++) { 4904 memset(&c, 0, sizeof(c)); 4905 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 4906 F_FW_CMD_REQUEST | 4907 (rw ? F_FW_CMD_READ : 4908 F_FW_CMD_WRITE) | 4909 V_FW_LDST_CMD_ADDRSPACE(cmd)); 4910 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4911 4912 c.u.addrval.addr = cpu_to_be32(start_index + i); 4913 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 4914 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 4915 sleep_ok); 4916 if (ret) 4917 return ret; 4918 4919 if (rw) 4920 vals[i] = be32_to_cpu(c.u.addrval.val); 4921 } 4922 return 0; 4923 } 4924 4925 /** 4926 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 4927 * @adap: the adapter 4928 * @reg_addr: Address Register 4929 * @reg_data: Data register 4930 * @buff: where the indirect register values are stored/written 4931 * @nregs: how many indirect registers to read/write 4932 * @start_index: index of first indirect register to read/write 4933 * @rw: READ(1) or WRITE(0) 4934 * @sleep_ok: if true we may sleep while awaiting command completion 4935 * 4936 * Read/Write TP indirect registers through LDST if possible. 4937 * Else, use backdoor access 4938 **/ 4939 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 4940 u32 *buff, u32 nregs, u32 start_index, int rw, 4941 bool sleep_ok) 4942 { 4943 int rc = -EINVAL; 4944 int cmd; 4945 4946 switch (reg_addr) { 4947 case A_TP_PIO_ADDR: 4948 cmd = FW_LDST_ADDRSPC_TP_PIO; 4949 break; 4950 case A_TP_TM_PIO_ADDR: 4951 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 4952 break; 4953 case A_TP_MIB_INDEX: 4954 cmd = FW_LDST_ADDRSPC_TP_MIB; 4955 break; 4956 default: 4957 goto indirect_access; 4958 } 4959 4960 if (t4_use_ldst(adap)) 4961 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 4962 sleep_ok); 4963 4964 indirect_access: 4965 4966 if (rc) { 4967 if (rw) 4968 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 4969 start_index); 4970 else 4971 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 4972 start_index); 4973 } 4974 } 4975 4976 /** 4977 * t4_tp_pio_read - Read TP PIO registers 4978 * @adap: the adapter 4979 * @buff: where the indirect register values are written 4980 * @nregs: how many indirect registers to read 4981 * @start_index: index of first indirect register to read 4982 * @sleep_ok: if true we may sleep while awaiting command completion 4983 * 4984 * Read TP PIO Registers 4985 **/ 4986 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 4987 u32 start_index, bool sleep_ok) 4988 { 4989 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 4990 start_index, 1, sleep_ok); 4991 } 4992 4993 /** 4994 * t4_tp_pio_write - Write TP PIO registers 4995 * @adap: the adapter 4996 * @buff: where the indirect register values are stored 4997 * @nregs: how many indirect registers to write 4998 * @start_index: index of first indirect register to write 4999 * @sleep_ok: if true we may sleep while awaiting command completion 5000 * 5001 * Write TP PIO Registers 5002 **/ 5003 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5004 u32 start_index, bool sleep_ok) 5005 { 5006 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5007 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5008 } 5009 5010 /** 5011 * t4_tp_tm_pio_read - Read TP TM PIO registers 5012 * @adap: the adapter 5013 * @buff: where the indirect register values are written 5014 * @nregs: how many indirect registers to read 5015 * @start_index: index of first indirect register to read 5016 * @sleep_ok: if true we may sleep while awaiting command completion 5017 * 5018 * Read TP TM PIO Registers 5019 **/ 5020 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5021 u32 start_index, bool sleep_ok) 5022 { 5023 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5024 nregs, start_index, 1, sleep_ok); 5025 } 5026 5027 /** 5028 * t4_tp_mib_read - Read TP MIB registers 5029 * @adap: the adapter 5030 * @buff: where the indirect register values are written 5031 * @nregs: how many indirect registers to read 5032 * @start_index: index of first indirect register to read 5033 * @sleep_ok: if true we may sleep while awaiting command completion 5034 * 5035 * Read TP MIB Registers 5036 **/ 5037 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5038 bool sleep_ok) 5039 { 5040 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5041 start_index, 1, sleep_ok); 5042 } 5043 5044 /** 5045 * t4_read_rss_key - read the global RSS key 5046 * @adap: the adapter 5047 * @key: 10-entry array holding the 320-bit RSS key 5048 * @sleep_ok: if true we may sleep while awaiting command completion 5049 * 5050 * Reads the global 320-bit RSS key. 5051 */ 5052 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5053 { 5054 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5055 } 5056 5057 /** 5058 * t4_write_rss_key - program one of the RSS keys 5059 * @adap: the adapter 5060 * @key: 10-entry array holding the 320-bit RSS key 5061 * @idx: which RSS key to write 5062 * @sleep_ok: if true we may sleep while awaiting command completion 5063 * 5064 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5065 * 0..15 the corresponding entry in the RSS key table is written, 5066 * otherwise the global RSS key is written. 5067 */ 5068 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5069 bool sleep_ok) 5070 { 5071 u8 rss_key_addr_cnt = 16; 5072 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5073 5074 /* 5075 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5076 * allows access to key addresses 16-63 by using KeyWrAddrX 5077 * as index[5:4](upper 2) into key table 5078 */ 5079 if ((chip_id(adap) > CHELSIO_T5) && 5080 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5081 rss_key_addr_cnt = 32; 5082 5083 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5084 5085 if (idx >= 0 && idx < rss_key_addr_cnt) { 5086 if (rss_key_addr_cnt > 16) 5087 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5088 vrt | V_KEYWRADDRX(idx >> 4) | 5089 V_T6_VFWRADDR(idx) | F_KEYWREN); 5090 else 5091 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5092 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5093 } 5094 } 5095 5096 /** 5097 * t4_read_rss_pf_config - read PF RSS Configuration Table 5098 * @adapter: the adapter 5099 * @index: the entry in the PF RSS table to read 5100 * @valp: where to store the returned value 5101 * @sleep_ok: if true we may sleep while awaiting command completion 5102 * 5103 * Reads the PF RSS Configuration Table at the specified index and returns 5104 * the value found there. 5105 */ 5106 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5107 u32 *valp, bool sleep_ok) 5108 { 5109 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5110 } 5111 5112 /** 5113 * t4_write_rss_pf_config - write PF RSS Configuration Table 5114 * @adapter: the adapter 5115 * @index: the entry in the VF RSS table to read 5116 * @val: the value to store 5117 * @sleep_ok: if true we may sleep while awaiting command completion 5118 * 5119 * Writes the PF RSS Configuration Table at the specified index with the 5120 * specified value. 5121 */ 5122 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5123 u32 val, bool sleep_ok) 5124 { 5125 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5126 sleep_ok); 5127 } 5128 5129 /** 5130 * t4_read_rss_vf_config - read VF RSS Configuration Table 5131 * @adapter: the adapter 5132 * @index: the entry in the VF RSS table to read 5133 * @vfl: where to store the returned VFL 5134 * @vfh: where to store the returned VFH 5135 * @sleep_ok: if true we may sleep while awaiting command completion 5136 * 5137 * Reads the VF RSS Configuration Table at the specified index and returns 5138 * the (VFL, VFH) values found there. 5139 */ 5140 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5141 u32 *vfl, u32 *vfh, bool sleep_ok) 5142 { 5143 u32 vrt, mask, data; 5144 5145 if (chip_id(adapter) <= CHELSIO_T5) { 5146 mask = V_VFWRADDR(M_VFWRADDR); 5147 data = V_VFWRADDR(index); 5148 } else { 5149 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5150 data = V_T6_VFWRADDR(index); 5151 } 5152 /* 5153 * Request that the index'th VF Table values be read into VFL/VFH. 5154 */ 5155 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5156 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5157 vrt |= data | F_VFRDEN; 5158 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5159 5160 /* 5161 * Grab the VFL/VFH values ... 5162 */ 5163 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5164 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5165 } 5166 5167 /** 5168 * t4_write_rss_vf_config - write VF RSS Configuration Table 5169 * 5170 * @adapter: the adapter 5171 * @index: the entry in the VF RSS table to write 5172 * @vfl: the VFL to store 5173 * @vfh: the VFH to store 5174 * 5175 * Writes the VF RSS Configuration Table at the specified index with the 5176 * specified (VFL, VFH) values. 5177 */ 5178 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 5179 u32 vfl, u32 vfh, bool sleep_ok) 5180 { 5181 u32 vrt, mask, data; 5182 5183 if (chip_id(adapter) <= CHELSIO_T5) { 5184 mask = V_VFWRADDR(M_VFWRADDR); 5185 data = V_VFWRADDR(index); 5186 } else { 5187 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5188 data = V_T6_VFWRADDR(index); 5189 } 5190 5191 /* 5192 * Load up VFL/VFH with the values to be written ... 5193 */ 5194 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5195 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5196 5197 /* 5198 * Write the VFL/VFH into the VF Table at index'th location. 5199 */ 5200 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5201 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5202 vrt |= data | F_VFRDEN; 5203 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5204 } 5205 5206 /** 5207 * t4_read_rss_pf_map - read PF RSS Map 5208 * @adapter: the adapter 5209 * @sleep_ok: if true we may sleep while awaiting command completion 5210 * 5211 * Reads the PF RSS Map register and returns its value. 5212 */ 5213 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 5214 { 5215 u32 pfmap; 5216 5217 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5218 5219 return pfmap; 5220 } 5221 5222 /** 5223 * t4_write_rss_pf_map - write PF RSS Map 5224 * @adapter: the adapter 5225 * @pfmap: PF RSS Map value 5226 * 5227 * Writes the specified value to the PF RSS Map register. 5228 */ 5229 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 5230 { 5231 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5232 } 5233 5234 /** 5235 * t4_read_rss_pf_mask - read PF RSS Mask 5236 * @adapter: the adapter 5237 * @sleep_ok: if true we may sleep while awaiting command completion 5238 * 5239 * Reads the PF RSS Mask register and returns its value. 5240 */ 5241 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 5242 { 5243 u32 pfmask; 5244 5245 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5246 5247 return pfmask; 5248 } 5249 5250 /** 5251 * t4_write_rss_pf_mask - write PF RSS Mask 5252 * @adapter: the adapter 5253 * @pfmask: PF RSS Mask value 5254 * 5255 * Writes the specified value to the PF RSS Mask register. 5256 */ 5257 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 5258 { 5259 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5260 } 5261 5262 /** 5263 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 5264 * @adap: the adapter 5265 * @v4: holds the TCP/IP counter values 5266 * @v6: holds the TCP/IPv6 counter values 5267 * @sleep_ok: if true we may sleep while awaiting command completion 5268 * 5269 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 5270 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 5271 */ 5272 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 5273 struct tp_tcp_stats *v6, bool sleep_ok) 5274 { 5275 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 5276 5277 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 5278 #define STAT(x) val[STAT_IDX(x)] 5279 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 5280 5281 if (v4) { 5282 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5283 A_TP_MIB_TCP_OUT_RST, sleep_ok); 5284 v4->tcp_out_rsts = STAT(OUT_RST); 5285 v4->tcp_in_segs = STAT64(IN_SEG); 5286 v4->tcp_out_segs = STAT64(OUT_SEG); 5287 v4->tcp_retrans_segs = STAT64(RXT_SEG); 5288 } 5289 if (v6) { 5290 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5291 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 5292 v6->tcp_out_rsts = STAT(OUT_RST); 5293 v6->tcp_in_segs = STAT64(IN_SEG); 5294 v6->tcp_out_segs = STAT64(OUT_SEG); 5295 v6->tcp_retrans_segs = STAT64(RXT_SEG); 5296 } 5297 #undef STAT64 5298 #undef STAT 5299 #undef STAT_IDX 5300 } 5301 5302 /** 5303 * t4_tp_get_err_stats - read TP's error MIB counters 5304 * @adap: the adapter 5305 * @st: holds the counter values 5306 * @sleep_ok: if true we may sleep while awaiting command completion 5307 * 5308 * Returns the values of TP's error counters. 5309 */ 5310 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 5311 bool sleep_ok) 5312 { 5313 int nchan = adap->chip_params->nchan; 5314 5315 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 5316 sleep_ok); 5317 5318 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 5319 sleep_ok); 5320 5321 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 5322 sleep_ok); 5323 5324 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 5325 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 5326 5327 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 5328 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 5329 5330 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 5331 sleep_ok); 5332 5333 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 5334 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 5335 5336 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 5337 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 5338 5339 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 5340 sleep_ok); 5341 } 5342 5343 /** 5344 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 5345 * @adap: the adapter 5346 * @st: holds the counter values 5347 * 5348 * Returns the values of TP's proxy counters. 5349 */ 5350 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 5351 bool sleep_ok) 5352 { 5353 int nchan = adap->chip_params->nchan; 5354 5355 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 5356 } 5357 5358 /** 5359 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 5360 * @adap: the adapter 5361 * @st: holds the counter values 5362 * @sleep_ok: if true we may sleep while awaiting command completion 5363 * 5364 * Returns the values of TP's CPL counters. 5365 */ 5366 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 5367 bool sleep_ok) 5368 { 5369 int nchan = adap->chip_params->nchan; 5370 5371 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 5372 5373 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 5374 } 5375 5376 /** 5377 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 5378 * @adap: the adapter 5379 * @st: holds the counter values 5380 * 5381 * Returns the values of TP's RDMA counters. 5382 */ 5383 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 5384 bool sleep_ok) 5385 { 5386 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 5387 sleep_ok); 5388 } 5389 5390 /** 5391 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 5392 * @adap: the adapter 5393 * @idx: the port index 5394 * @st: holds the counter values 5395 * @sleep_ok: if true we may sleep while awaiting command completion 5396 * 5397 * Returns the values of TP's FCoE counters for the selected port. 5398 */ 5399 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 5400 struct tp_fcoe_stats *st, bool sleep_ok) 5401 { 5402 u32 val[2]; 5403 5404 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 5405 sleep_ok); 5406 5407 t4_tp_mib_read(adap, &st->frames_drop, 1, 5408 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 5409 5410 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 5411 sleep_ok); 5412 5413 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 5414 } 5415 5416 /** 5417 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 5418 * @adap: the adapter 5419 * @st: holds the counter values 5420 * @sleep_ok: if true we may sleep while awaiting command completion 5421 * 5422 * Returns the values of TP's counters for non-TCP directly-placed packets. 5423 */ 5424 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 5425 bool sleep_ok) 5426 { 5427 u32 val[4]; 5428 5429 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 5430 5431 st->frames = val[0]; 5432 st->drops = val[1]; 5433 st->octets = ((u64)val[2] << 32) | val[3]; 5434 } 5435 5436 /** 5437 * t4_read_mtu_tbl - returns the values in the HW path MTU table 5438 * @adap: the adapter 5439 * @mtus: where to store the MTU values 5440 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 5441 * 5442 * Reads the HW path MTU table. 5443 */ 5444 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 5445 { 5446 u32 v; 5447 int i; 5448 5449 for (i = 0; i < NMTUS; ++i) { 5450 t4_write_reg(adap, A_TP_MTU_TABLE, 5451 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 5452 v = t4_read_reg(adap, A_TP_MTU_TABLE); 5453 mtus[i] = G_MTUVALUE(v); 5454 if (mtu_log) 5455 mtu_log[i] = G_MTUWIDTH(v); 5456 } 5457 } 5458 5459 /** 5460 * t4_read_cong_tbl - reads the congestion control table 5461 * @adap: the adapter 5462 * @incr: where to store the alpha values 5463 * 5464 * Reads the additive increments programmed into the HW congestion 5465 * control table. 5466 */ 5467 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 5468 { 5469 unsigned int mtu, w; 5470 5471 for (mtu = 0; mtu < NMTUS; ++mtu) 5472 for (w = 0; w < NCCTRL_WIN; ++w) { 5473 t4_write_reg(adap, A_TP_CCTRL_TABLE, 5474 V_ROWINDEX(0xffff) | (mtu << 5) | w); 5475 incr[mtu][w] = (u16)t4_read_reg(adap, 5476 A_TP_CCTRL_TABLE) & 0x1fff; 5477 } 5478 } 5479 5480 /** 5481 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 5482 * @adap: the adapter 5483 * @addr: the indirect TP register address 5484 * @mask: specifies the field within the register to modify 5485 * @val: new value for the field 5486 * 5487 * Sets a field of an indirect TP register to the given value. 5488 */ 5489 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 5490 unsigned int mask, unsigned int val) 5491 { 5492 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 5493 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 5494 t4_write_reg(adap, A_TP_PIO_DATA, val); 5495 } 5496 5497 /** 5498 * init_cong_ctrl - initialize congestion control parameters 5499 * @a: the alpha values for congestion control 5500 * @b: the beta values for congestion control 5501 * 5502 * Initialize the congestion control parameters. 5503 */ 5504 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 5505 { 5506 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 5507 a[9] = 2; 5508 a[10] = 3; 5509 a[11] = 4; 5510 a[12] = 5; 5511 a[13] = 6; 5512 a[14] = 7; 5513 a[15] = 8; 5514 a[16] = 9; 5515 a[17] = 10; 5516 a[18] = 14; 5517 a[19] = 17; 5518 a[20] = 21; 5519 a[21] = 25; 5520 a[22] = 30; 5521 a[23] = 35; 5522 a[24] = 45; 5523 a[25] = 60; 5524 a[26] = 80; 5525 a[27] = 100; 5526 a[28] = 200; 5527 a[29] = 300; 5528 a[30] = 400; 5529 a[31] = 500; 5530 5531 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 5532 b[9] = b[10] = 1; 5533 b[11] = b[12] = 2; 5534 b[13] = b[14] = b[15] = b[16] = 3; 5535 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 5536 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 5537 b[28] = b[29] = 6; 5538 b[30] = b[31] = 7; 5539 } 5540 5541 /* The minimum additive increment value for the congestion control table */ 5542 #define CC_MIN_INCR 2U 5543 5544 /** 5545 * t4_load_mtus - write the MTU and congestion control HW tables 5546 * @adap: the adapter 5547 * @mtus: the values for the MTU table 5548 * @alpha: the values for the congestion control alpha parameter 5549 * @beta: the values for the congestion control beta parameter 5550 * 5551 * Write the HW MTU table with the supplied MTUs and the high-speed 5552 * congestion control table with the supplied alpha, beta, and MTUs. 5553 * We write the two tables together because the additive increments 5554 * depend on the MTUs. 5555 */ 5556 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 5557 const unsigned short *alpha, const unsigned short *beta) 5558 { 5559 static const unsigned int avg_pkts[NCCTRL_WIN] = { 5560 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 5561 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 5562 28672, 40960, 57344, 81920, 114688, 163840, 229376 5563 }; 5564 5565 unsigned int i, w; 5566 5567 for (i = 0; i < NMTUS; ++i) { 5568 unsigned int mtu = mtus[i]; 5569 unsigned int log2 = fls(mtu); 5570 5571 if (!(mtu & ((1 << log2) >> 2))) /* round */ 5572 log2--; 5573 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 5574 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 5575 5576 for (w = 0; w < NCCTRL_WIN; ++w) { 5577 unsigned int inc; 5578 5579 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 5580 CC_MIN_INCR); 5581 5582 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 5583 (w << 16) | (beta[w] << 13) | inc); 5584 } 5585 } 5586 } 5587 5588 /** 5589 * t4_set_pace_tbl - set the pace table 5590 * @adap: the adapter 5591 * @pace_vals: the pace values in microseconds 5592 * @start: index of the first entry in the HW pace table to set 5593 * @n: how many entries to set 5594 * 5595 * Sets (a subset of the) HW pace table. 5596 */ 5597 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 5598 unsigned int start, unsigned int n) 5599 { 5600 unsigned int vals[NTX_SCHED], i; 5601 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 5602 5603 if (n > NTX_SCHED) 5604 return -ERANGE; 5605 5606 /* convert values from us to dack ticks, rounding to closest value */ 5607 for (i = 0; i < n; i++, pace_vals++) { 5608 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 5609 if (vals[i] > 0x7ff) 5610 return -ERANGE; 5611 if (*pace_vals && vals[i] == 0) 5612 return -ERANGE; 5613 } 5614 for (i = 0; i < n; i++, start++) 5615 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 5616 return 0; 5617 } 5618 5619 /** 5620 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 5621 * @adap: the adapter 5622 * @kbps: target rate in Kbps 5623 * @sched: the scheduler index 5624 * 5625 * Configure a Tx HW scheduler for the target rate. 5626 */ 5627 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 5628 { 5629 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 5630 unsigned int clk = adap->params.vpd.cclk * 1000; 5631 unsigned int selected_cpt = 0, selected_bpt = 0; 5632 5633 if (kbps > 0) { 5634 kbps *= 125; /* -> bytes */ 5635 for (cpt = 1; cpt <= 255; cpt++) { 5636 tps = clk / cpt; 5637 bpt = (kbps + tps / 2) / tps; 5638 if (bpt > 0 && bpt <= 255) { 5639 v = bpt * tps; 5640 delta = v >= kbps ? v - kbps : kbps - v; 5641 if (delta < mindelta) { 5642 mindelta = delta; 5643 selected_cpt = cpt; 5644 selected_bpt = bpt; 5645 } 5646 } else if (selected_cpt) 5647 break; 5648 } 5649 if (!selected_cpt) 5650 return -EINVAL; 5651 } 5652 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 5653 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 5654 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5655 if (sched & 1) 5656 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 5657 else 5658 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 5659 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5660 return 0; 5661 } 5662 5663 /** 5664 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 5665 * @adap: the adapter 5666 * @sched: the scheduler index 5667 * @ipg: the interpacket delay in tenths of nanoseconds 5668 * 5669 * Set the interpacket delay for a HW packet rate scheduler. 5670 */ 5671 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 5672 { 5673 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 5674 5675 /* convert ipg to nearest number of core clocks */ 5676 ipg *= core_ticks_per_usec(adap); 5677 ipg = (ipg + 5000) / 10000; 5678 if (ipg > M_TXTIMERSEPQ0) 5679 return -EINVAL; 5680 5681 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 5682 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5683 if (sched & 1) 5684 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 5685 else 5686 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 5687 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5688 t4_read_reg(adap, A_TP_TM_PIO_DATA); 5689 return 0; 5690 } 5691 5692 /* 5693 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 5694 * clocks. The formula is 5695 * 5696 * bytes/s = bytes256 * 256 * ClkFreq / 4096 5697 * 5698 * which is equivalent to 5699 * 5700 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 5701 */ 5702 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 5703 { 5704 u64 v = bytes256 * adap->params.vpd.cclk; 5705 5706 return v * 62 + v / 2; 5707 } 5708 5709 /** 5710 * t4_get_chan_txrate - get the current per channel Tx rates 5711 * @adap: the adapter 5712 * @nic_rate: rates for NIC traffic 5713 * @ofld_rate: rates for offloaded traffic 5714 * 5715 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 5716 * for each channel. 5717 */ 5718 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 5719 { 5720 u32 v; 5721 5722 v = t4_read_reg(adap, A_TP_TX_TRATE); 5723 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 5724 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 5725 if (adap->chip_params->nchan > 2) { 5726 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 5727 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 5728 } 5729 5730 v = t4_read_reg(adap, A_TP_TX_ORATE); 5731 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 5732 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 5733 if (adap->chip_params->nchan > 2) { 5734 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 5735 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 5736 } 5737 } 5738 5739 /** 5740 * t4_set_trace_filter - configure one of the tracing filters 5741 * @adap: the adapter 5742 * @tp: the desired trace filter parameters 5743 * @idx: which filter to configure 5744 * @enable: whether to enable or disable the filter 5745 * 5746 * Configures one of the tracing filters available in HW. If @tp is %NULL 5747 * it indicates that the filter is already written in the register and it 5748 * just needs to be enabled or disabled. 5749 */ 5750 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 5751 int idx, int enable) 5752 { 5753 int i, ofst = idx * 4; 5754 u32 data_reg, mask_reg, cfg; 5755 u32 multitrc = F_TRCMULTIFILTER; 5756 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 5757 5758 if (idx < 0 || idx >= NTRACE) 5759 return -EINVAL; 5760 5761 if (tp == NULL || !enable) { 5762 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 5763 enable ? en : 0); 5764 return 0; 5765 } 5766 5767 /* 5768 * TODO - After T4 data book is updated, specify the exact 5769 * section below. 5770 * 5771 * See T4 data book - MPS section for a complete description 5772 * of the below if..else handling of A_MPS_TRC_CFG register 5773 * value. 5774 */ 5775 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 5776 if (cfg & F_TRCMULTIFILTER) { 5777 /* 5778 * If multiple tracers are enabled, then maximum 5779 * capture size is 2.5KB (FIFO size of a single channel) 5780 * minus 2 flits for CPL_TRACE_PKT header. 5781 */ 5782 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 5783 return -EINVAL; 5784 } else { 5785 /* 5786 * If multiple tracers are disabled, to avoid deadlocks 5787 * maximum packet capture size of 9600 bytes is recommended. 5788 * Also in this mode, only trace0 can be enabled and running. 5789 */ 5790 multitrc = 0; 5791 if (tp->snap_len > 9600 || idx) 5792 return -EINVAL; 5793 } 5794 5795 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 5796 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 5797 tp->min_len > M_TFMINPKTSIZE) 5798 return -EINVAL; 5799 5800 /* stop the tracer we'll be changing */ 5801 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 5802 5803 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 5804 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 5805 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 5806 5807 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5808 t4_write_reg(adap, data_reg, tp->data[i]); 5809 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 5810 } 5811 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 5812 V_TFCAPTUREMAX(tp->snap_len) | 5813 V_TFMINPKTSIZE(tp->min_len)); 5814 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 5815 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 5816 (is_t4(adap) ? 5817 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 5818 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 5819 5820 return 0; 5821 } 5822 5823 /** 5824 * t4_get_trace_filter - query one of the tracing filters 5825 * @adap: the adapter 5826 * @tp: the current trace filter parameters 5827 * @idx: which trace filter to query 5828 * @enabled: non-zero if the filter is enabled 5829 * 5830 * Returns the current settings of one of the HW tracing filters. 5831 */ 5832 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 5833 int *enabled) 5834 { 5835 u32 ctla, ctlb; 5836 int i, ofst = idx * 4; 5837 u32 data_reg, mask_reg; 5838 5839 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 5840 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 5841 5842 if (is_t4(adap)) { 5843 *enabled = !!(ctla & F_TFEN); 5844 tp->port = G_TFPORT(ctla); 5845 tp->invert = !!(ctla & F_TFINVERTMATCH); 5846 } else { 5847 *enabled = !!(ctla & F_T5_TFEN); 5848 tp->port = G_T5_TFPORT(ctla); 5849 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 5850 } 5851 tp->snap_len = G_TFCAPTUREMAX(ctlb); 5852 tp->min_len = G_TFMINPKTSIZE(ctlb); 5853 tp->skip_ofst = G_TFOFFSET(ctla); 5854 tp->skip_len = G_TFLENGTH(ctla); 5855 5856 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 5857 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 5858 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 5859 5860 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5861 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 5862 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 5863 } 5864 } 5865 5866 /** 5867 * t4_pmtx_get_stats - returns the HW stats from PMTX 5868 * @adap: the adapter 5869 * @cnt: where to store the count statistics 5870 * @cycles: where to store the cycle statistics 5871 * 5872 * Returns performance statistics from PMTX. 5873 */ 5874 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 5875 { 5876 int i; 5877 u32 data[2]; 5878 5879 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 5880 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 5881 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 5882 if (is_t4(adap)) 5883 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 5884 else { 5885 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 5886 A_PM_TX_DBG_DATA, data, 2, 5887 A_PM_TX_DBG_STAT_MSB); 5888 cycles[i] = (((u64)data[0] << 32) | data[1]); 5889 } 5890 } 5891 } 5892 5893 /** 5894 * t4_pmrx_get_stats - returns the HW stats from PMRX 5895 * @adap: the adapter 5896 * @cnt: where to store the count statistics 5897 * @cycles: where to store the cycle statistics 5898 * 5899 * Returns performance statistics from PMRX. 5900 */ 5901 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 5902 { 5903 int i; 5904 u32 data[2]; 5905 5906 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 5907 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 5908 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 5909 if (is_t4(adap)) { 5910 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 5911 } else { 5912 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 5913 A_PM_RX_DBG_DATA, data, 2, 5914 A_PM_RX_DBG_STAT_MSB); 5915 cycles[i] = (((u64)data[0] << 32) | data[1]); 5916 } 5917 } 5918 } 5919 5920 /** 5921 * t4_get_mps_bg_map - return the buffer groups associated with a port 5922 * @adap: the adapter 5923 * @idx: the port index 5924 * 5925 * Returns a bitmap indicating which MPS buffer groups are associated 5926 * with the given port. Bit i is set if buffer group i is used by the 5927 * port. 5928 */ 5929 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 5930 { 5931 u32 n; 5932 5933 if (adap->params.mps_bg_map) 5934 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 5935 5936 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 5937 if (n == 0) 5938 return idx == 0 ? 0xf : 0; 5939 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 5940 return idx < 2 ? (3 << (2 * idx)) : 0; 5941 return 1 << idx; 5942 } 5943 5944 /* 5945 * TP RX e-channels associated with the port. 5946 */ 5947 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 5948 { 5949 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 5950 5951 if (n == 0) 5952 return idx == 0 ? 0xf : 0; 5953 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 5954 return idx < 2 ? (3 << (2 * idx)) : 0; 5955 return 1 << idx; 5956 } 5957 5958 /** 5959 * t4_get_port_type_description - return Port Type string description 5960 * @port_type: firmware Port Type enumeration 5961 */ 5962 const char *t4_get_port_type_description(enum fw_port_type port_type) 5963 { 5964 static const char *const port_type_description[] = { 5965 "Fiber_XFI", 5966 "Fiber_XAUI", 5967 "BT_SGMII", 5968 "BT_XFI", 5969 "BT_XAUI", 5970 "KX4", 5971 "CX4", 5972 "KX", 5973 "KR", 5974 "SFP", 5975 "BP_AP", 5976 "BP4_AP", 5977 "QSFP_10G", 5978 "QSA", 5979 "QSFP", 5980 "BP40_BA", 5981 "KR4_100G", 5982 "CR4_QSFP", 5983 "CR_QSFP", 5984 "CR2_QSFP", 5985 "SFP28", 5986 "KR_SFP28", 5987 }; 5988 5989 if (port_type < ARRAY_SIZE(port_type_description)) 5990 return port_type_description[port_type]; 5991 return "UNKNOWN"; 5992 } 5993 5994 /** 5995 * t4_get_port_stats_offset - collect port stats relative to a previous 5996 * snapshot 5997 * @adap: The adapter 5998 * @idx: The port 5999 * @stats: Current stats to fill 6000 * @offset: Previous stats snapshot 6001 */ 6002 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6003 struct port_stats *stats, 6004 struct port_stats *offset) 6005 { 6006 u64 *s, *o; 6007 int i; 6008 6009 t4_get_port_stats(adap, idx, stats); 6010 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6011 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6012 i++, s++, o++) 6013 *s -= *o; 6014 } 6015 6016 /** 6017 * t4_get_port_stats - collect port statistics 6018 * @adap: the adapter 6019 * @idx: the port index 6020 * @p: the stats structure to fill 6021 * 6022 * Collect statistics related to the given port from HW. 6023 */ 6024 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6025 { 6026 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6027 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6028 6029 #define GET_STAT(name) \ 6030 t4_read_reg64(adap, \ 6031 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6032 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6033 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6034 6035 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6036 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6037 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6038 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6039 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6040 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6041 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6042 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6043 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6044 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6045 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6046 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6047 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6048 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6049 p->tx_drop = GET_STAT(TX_PORT_DROP); 6050 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6051 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6052 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6053 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6054 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6055 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6056 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6057 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6058 6059 if (chip_id(adap) >= CHELSIO_T5) { 6060 if (stat_ctl & F_COUNTPAUSESTATTX) { 6061 p->tx_frames -= p->tx_pause; 6062 p->tx_octets -= p->tx_pause * 64; 6063 } 6064 if (stat_ctl & F_COUNTPAUSEMCTX) 6065 p->tx_mcast_frames -= p->tx_pause; 6066 } 6067 6068 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6069 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6070 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6071 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6072 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6073 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6074 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6075 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6076 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 6077 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6078 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6079 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6080 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6081 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6082 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6083 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6084 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6085 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6086 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6087 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6088 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6089 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6090 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6091 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6092 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6093 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6094 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6095 6096 if (chip_id(adap) >= CHELSIO_T5) { 6097 if (stat_ctl & F_COUNTPAUSESTATRX) { 6098 p->rx_frames -= p->rx_pause; 6099 p->rx_octets -= p->rx_pause * 64; 6100 } 6101 if (stat_ctl & F_COUNTPAUSEMCRX) 6102 p->rx_mcast_frames -= p->rx_pause; 6103 } 6104 6105 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6106 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6107 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6108 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6109 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6110 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6111 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6112 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6113 6114 #undef GET_STAT 6115 #undef GET_STAT_COM 6116 } 6117 6118 /** 6119 * t4_get_lb_stats - collect loopback port statistics 6120 * @adap: the adapter 6121 * @idx: the loopback port index 6122 * @p: the stats structure to fill 6123 * 6124 * Return HW statistics for the given loopback port. 6125 */ 6126 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 6127 { 6128 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6129 6130 #define GET_STAT(name) \ 6131 t4_read_reg64(adap, \ 6132 (is_t4(adap) ? \ 6133 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 6134 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 6135 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6136 6137 p->octets = GET_STAT(BYTES); 6138 p->frames = GET_STAT(FRAMES); 6139 p->bcast_frames = GET_STAT(BCAST); 6140 p->mcast_frames = GET_STAT(MCAST); 6141 p->ucast_frames = GET_STAT(UCAST); 6142 p->error_frames = GET_STAT(ERROR); 6143 6144 p->frames_64 = GET_STAT(64B); 6145 p->frames_65_127 = GET_STAT(65B_127B); 6146 p->frames_128_255 = GET_STAT(128B_255B); 6147 p->frames_256_511 = GET_STAT(256B_511B); 6148 p->frames_512_1023 = GET_STAT(512B_1023B); 6149 p->frames_1024_1518 = GET_STAT(1024B_1518B); 6150 p->frames_1519_max = GET_STAT(1519B_MAX); 6151 p->drop = GET_STAT(DROP_FRAMES); 6152 6153 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 6154 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 6155 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 6156 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 6157 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 6158 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 6159 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 6160 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 6161 6162 #undef GET_STAT 6163 #undef GET_STAT_COM 6164 } 6165 6166 /** 6167 * t4_wol_magic_enable - enable/disable magic packet WoL 6168 * @adap: the adapter 6169 * @port: the physical port index 6170 * @addr: MAC address expected in magic packets, %NULL to disable 6171 * 6172 * Enables/disables magic packet wake-on-LAN for the selected port. 6173 */ 6174 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 6175 const u8 *addr) 6176 { 6177 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 6178 6179 if (is_t4(adap)) { 6180 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 6181 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 6182 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6183 } else { 6184 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 6185 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 6186 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6187 } 6188 6189 if (addr) { 6190 t4_write_reg(adap, mag_id_reg_l, 6191 (addr[2] << 24) | (addr[3] << 16) | 6192 (addr[4] << 8) | addr[5]); 6193 t4_write_reg(adap, mag_id_reg_h, 6194 (addr[0] << 8) | addr[1]); 6195 } 6196 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 6197 V_MAGICEN(addr != NULL)); 6198 } 6199 6200 /** 6201 * t4_wol_pat_enable - enable/disable pattern-based WoL 6202 * @adap: the adapter 6203 * @port: the physical port index 6204 * @map: bitmap of which HW pattern filters to set 6205 * @mask0: byte mask for bytes 0-63 of a packet 6206 * @mask1: byte mask for bytes 64-127 of a packet 6207 * @crc: Ethernet CRC for selected bytes 6208 * @enable: enable/disable switch 6209 * 6210 * Sets the pattern filters indicated in @map to mask out the bytes 6211 * specified in @mask0/@mask1 in received packets and compare the CRC of 6212 * the resulting packet against @crc. If @enable is %true pattern-based 6213 * WoL is enabled, otherwise disabled. 6214 */ 6215 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 6216 u64 mask0, u64 mask1, unsigned int crc, bool enable) 6217 { 6218 int i; 6219 u32 port_cfg_reg; 6220 6221 if (is_t4(adap)) 6222 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6223 else 6224 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6225 6226 if (!enable) { 6227 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 6228 return 0; 6229 } 6230 if (map > 0xff) 6231 return -EINVAL; 6232 6233 #define EPIO_REG(name) \ 6234 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 6235 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 6236 6237 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 6238 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 6239 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 6240 6241 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 6242 if (!(map & 1)) 6243 continue; 6244 6245 /* write byte masks */ 6246 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 6247 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 6248 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6249 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6250 return -ETIMEDOUT; 6251 6252 /* write CRC */ 6253 t4_write_reg(adap, EPIO_REG(DATA0), crc); 6254 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 6255 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6256 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6257 return -ETIMEDOUT; 6258 } 6259 #undef EPIO_REG 6260 6261 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 6262 return 0; 6263 } 6264 6265 /* t4_mk_filtdelwr - create a delete filter WR 6266 * @ftid: the filter ID 6267 * @wr: the filter work request to populate 6268 * @qid: ingress queue to receive the delete notification 6269 * 6270 * Creates a filter work request to delete the supplied filter. If @qid is 6271 * negative the delete notification is suppressed. 6272 */ 6273 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 6274 { 6275 memset(wr, 0, sizeof(*wr)); 6276 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 6277 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 6278 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 6279 V_FW_FILTER_WR_NOREPLY(qid < 0)); 6280 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 6281 if (qid >= 0) 6282 wr->rx_chan_rx_rpl_iq = 6283 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 6284 } 6285 6286 #define INIT_CMD(var, cmd, rd_wr) do { \ 6287 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 6288 F_FW_CMD_REQUEST | \ 6289 F_FW_CMD_##rd_wr); \ 6290 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 6291 } while (0) 6292 6293 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 6294 u32 addr, u32 val) 6295 { 6296 u32 ldst_addrspace; 6297 struct fw_ldst_cmd c; 6298 6299 memset(&c, 0, sizeof(c)); 6300 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 6301 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6302 F_FW_CMD_REQUEST | 6303 F_FW_CMD_WRITE | 6304 ldst_addrspace); 6305 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6306 c.u.addrval.addr = cpu_to_be32(addr); 6307 c.u.addrval.val = cpu_to_be32(val); 6308 6309 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6310 } 6311 6312 /** 6313 * t4_mdio_rd - read a PHY register through MDIO 6314 * @adap: the adapter 6315 * @mbox: mailbox to use for the FW command 6316 * @phy_addr: the PHY address 6317 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6318 * @reg: the register to read 6319 * @valp: where to store the value 6320 * 6321 * Issues a FW command through the given mailbox to read a PHY register. 6322 */ 6323 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6324 unsigned int mmd, unsigned int reg, unsigned int *valp) 6325 { 6326 int ret; 6327 u32 ldst_addrspace; 6328 struct fw_ldst_cmd c; 6329 6330 memset(&c, 0, sizeof(c)); 6331 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6332 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6333 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6334 ldst_addrspace); 6335 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6336 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6337 V_FW_LDST_CMD_MMD(mmd)); 6338 c.u.mdio.raddr = cpu_to_be16(reg); 6339 6340 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6341 if (ret == 0) 6342 *valp = be16_to_cpu(c.u.mdio.rval); 6343 return ret; 6344 } 6345 6346 /** 6347 * t4_mdio_wr - write a PHY register through MDIO 6348 * @adap: the adapter 6349 * @mbox: mailbox to use for the FW command 6350 * @phy_addr: the PHY address 6351 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6352 * @reg: the register to write 6353 * @valp: value to write 6354 * 6355 * Issues a FW command through the given mailbox to write a PHY register. 6356 */ 6357 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6358 unsigned int mmd, unsigned int reg, unsigned int val) 6359 { 6360 u32 ldst_addrspace; 6361 struct fw_ldst_cmd c; 6362 6363 memset(&c, 0, sizeof(c)); 6364 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6365 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6366 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 6367 ldst_addrspace); 6368 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6369 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6370 V_FW_LDST_CMD_MMD(mmd)); 6371 c.u.mdio.raddr = cpu_to_be16(reg); 6372 c.u.mdio.rval = cpu_to_be16(val); 6373 6374 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6375 } 6376 6377 /** 6378 * 6379 * t4_sge_decode_idma_state - decode the idma state 6380 * @adap: the adapter 6381 * @state: the state idma is stuck in 6382 */ 6383 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 6384 { 6385 static const char * const t4_decode[] = { 6386 "IDMA_IDLE", 6387 "IDMA_PUSH_MORE_CPL_FIFO", 6388 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6389 "Not used", 6390 "IDMA_PHYSADDR_SEND_PCIEHDR", 6391 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6392 "IDMA_PHYSADDR_SEND_PAYLOAD", 6393 "IDMA_SEND_FIFO_TO_IMSG", 6394 "IDMA_FL_REQ_DATA_FL_PREP", 6395 "IDMA_FL_REQ_DATA_FL", 6396 "IDMA_FL_DROP", 6397 "IDMA_FL_H_REQ_HEADER_FL", 6398 "IDMA_FL_H_SEND_PCIEHDR", 6399 "IDMA_FL_H_PUSH_CPL_FIFO", 6400 "IDMA_FL_H_SEND_CPL", 6401 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6402 "IDMA_FL_H_SEND_IP_HDR", 6403 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6404 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6405 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6406 "IDMA_FL_D_SEND_PCIEHDR", 6407 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6408 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6409 "IDMA_FL_SEND_PCIEHDR", 6410 "IDMA_FL_PUSH_CPL_FIFO", 6411 "IDMA_FL_SEND_CPL", 6412 "IDMA_FL_SEND_PAYLOAD_FIRST", 6413 "IDMA_FL_SEND_PAYLOAD", 6414 "IDMA_FL_REQ_NEXT_DATA_FL", 6415 "IDMA_FL_SEND_NEXT_PCIEHDR", 6416 "IDMA_FL_SEND_PADDING", 6417 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6418 "IDMA_FL_SEND_FIFO_TO_IMSG", 6419 "IDMA_FL_REQ_DATAFL_DONE", 6420 "IDMA_FL_REQ_HEADERFL_DONE", 6421 }; 6422 static const char * const t5_decode[] = { 6423 "IDMA_IDLE", 6424 "IDMA_ALMOST_IDLE", 6425 "IDMA_PUSH_MORE_CPL_FIFO", 6426 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6427 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6428 "IDMA_PHYSADDR_SEND_PCIEHDR", 6429 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6430 "IDMA_PHYSADDR_SEND_PAYLOAD", 6431 "IDMA_SEND_FIFO_TO_IMSG", 6432 "IDMA_FL_REQ_DATA_FL", 6433 "IDMA_FL_DROP", 6434 "IDMA_FL_DROP_SEND_INC", 6435 "IDMA_FL_H_REQ_HEADER_FL", 6436 "IDMA_FL_H_SEND_PCIEHDR", 6437 "IDMA_FL_H_PUSH_CPL_FIFO", 6438 "IDMA_FL_H_SEND_CPL", 6439 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6440 "IDMA_FL_H_SEND_IP_HDR", 6441 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6442 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6443 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6444 "IDMA_FL_D_SEND_PCIEHDR", 6445 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6446 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6447 "IDMA_FL_SEND_PCIEHDR", 6448 "IDMA_FL_PUSH_CPL_FIFO", 6449 "IDMA_FL_SEND_CPL", 6450 "IDMA_FL_SEND_PAYLOAD_FIRST", 6451 "IDMA_FL_SEND_PAYLOAD", 6452 "IDMA_FL_REQ_NEXT_DATA_FL", 6453 "IDMA_FL_SEND_NEXT_PCIEHDR", 6454 "IDMA_FL_SEND_PADDING", 6455 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6456 }; 6457 static const char * const t6_decode[] = { 6458 "IDMA_IDLE", 6459 "IDMA_PUSH_MORE_CPL_FIFO", 6460 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6461 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6462 "IDMA_PHYSADDR_SEND_PCIEHDR", 6463 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6464 "IDMA_PHYSADDR_SEND_PAYLOAD", 6465 "IDMA_FL_REQ_DATA_FL", 6466 "IDMA_FL_DROP", 6467 "IDMA_FL_DROP_SEND_INC", 6468 "IDMA_FL_H_REQ_HEADER_FL", 6469 "IDMA_FL_H_SEND_PCIEHDR", 6470 "IDMA_FL_H_PUSH_CPL_FIFO", 6471 "IDMA_FL_H_SEND_CPL", 6472 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6473 "IDMA_FL_H_SEND_IP_HDR", 6474 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6475 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6476 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6477 "IDMA_FL_D_SEND_PCIEHDR", 6478 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6479 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6480 "IDMA_FL_SEND_PCIEHDR", 6481 "IDMA_FL_PUSH_CPL_FIFO", 6482 "IDMA_FL_SEND_CPL", 6483 "IDMA_FL_SEND_PAYLOAD_FIRST", 6484 "IDMA_FL_SEND_PAYLOAD", 6485 "IDMA_FL_REQ_NEXT_DATA_FL", 6486 "IDMA_FL_SEND_NEXT_PCIEHDR", 6487 "IDMA_FL_SEND_PADDING", 6488 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6489 }; 6490 static const u32 sge_regs[] = { 6491 A_SGE_DEBUG_DATA_LOW_INDEX_2, 6492 A_SGE_DEBUG_DATA_LOW_INDEX_3, 6493 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 6494 }; 6495 const char * const *sge_idma_decode; 6496 int sge_idma_decode_nstates; 6497 int i; 6498 unsigned int chip_version = chip_id(adapter); 6499 6500 /* Select the right set of decode strings to dump depending on the 6501 * adapter chip type. 6502 */ 6503 switch (chip_version) { 6504 case CHELSIO_T4: 6505 sge_idma_decode = (const char * const *)t4_decode; 6506 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 6507 break; 6508 6509 case CHELSIO_T5: 6510 sge_idma_decode = (const char * const *)t5_decode; 6511 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 6512 break; 6513 6514 case CHELSIO_T6: 6515 sge_idma_decode = (const char * const *)t6_decode; 6516 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 6517 break; 6518 6519 default: 6520 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 6521 return; 6522 } 6523 6524 if (state < sge_idma_decode_nstates) 6525 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 6526 else 6527 CH_WARN(adapter, "idma state %d unknown\n", state); 6528 6529 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 6530 CH_WARN(adapter, "SGE register %#x value %#x\n", 6531 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 6532 } 6533 6534 /** 6535 * t4_sge_ctxt_flush - flush the SGE context cache 6536 * @adap: the adapter 6537 * @mbox: mailbox to use for the FW command 6538 * 6539 * Issues a FW command through the given mailbox to flush the 6540 * SGE context cache. 6541 */ 6542 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 6543 { 6544 int ret; 6545 u32 ldst_addrspace; 6546 struct fw_ldst_cmd c; 6547 6548 memset(&c, 0, sizeof(c)); 6549 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC); 6550 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6551 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6552 ldst_addrspace); 6553 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6554 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 6555 6556 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6557 return ret; 6558 } 6559 6560 /** 6561 * t4_fw_hello - establish communication with FW 6562 * @adap: the adapter 6563 * @mbox: mailbox to use for the FW command 6564 * @evt_mbox: mailbox to receive async FW events 6565 * @master: specifies the caller's willingness to be the device master 6566 * @state: returns the current device state (if non-NULL) 6567 * 6568 * Issues a command to establish communication with FW. Returns either 6569 * an error (negative integer) or the mailbox of the Master PF. 6570 */ 6571 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 6572 enum dev_master master, enum dev_state *state) 6573 { 6574 int ret; 6575 struct fw_hello_cmd c; 6576 u32 v; 6577 unsigned int master_mbox; 6578 int retries = FW_CMD_HELLO_RETRIES; 6579 6580 retry: 6581 memset(&c, 0, sizeof(c)); 6582 INIT_CMD(c, HELLO, WRITE); 6583 c.err_to_clearinit = cpu_to_be32( 6584 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 6585 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 6586 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 6587 mbox : M_FW_HELLO_CMD_MBMASTER) | 6588 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 6589 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 6590 F_FW_HELLO_CMD_CLEARINIT); 6591 6592 /* 6593 * Issue the HELLO command to the firmware. If it's not successful 6594 * but indicates that we got a "busy" or "timeout" condition, retry 6595 * the HELLO until we exhaust our retry limit. If we do exceed our 6596 * retry limit, check to see if the firmware left us any error 6597 * information and report that if so ... 6598 */ 6599 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6600 if (ret != FW_SUCCESS) { 6601 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 6602 goto retry; 6603 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 6604 t4_report_fw_error(adap); 6605 return ret; 6606 } 6607 6608 v = be32_to_cpu(c.err_to_clearinit); 6609 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 6610 if (state) { 6611 if (v & F_FW_HELLO_CMD_ERR) 6612 *state = DEV_STATE_ERR; 6613 else if (v & F_FW_HELLO_CMD_INIT) 6614 *state = DEV_STATE_INIT; 6615 else 6616 *state = DEV_STATE_UNINIT; 6617 } 6618 6619 /* 6620 * If we're not the Master PF then we need to wait around for the 6621 * Master PF Driver to finish setting up the adapter. 6622 * 6623 * Note that we also do this wait if we're a non-Master-capable PF and 6624 * there is no current Master PF; a Master PF may show up momentarily 6625 * and we wouldn't want to fail pointlessly. (This can happen when an 6626 * OS loads lots of different drivers rapidly at the same time). In 6627 * this case, the Master PF returned by the firmware will be 6628 * M_PCIE_FW_MASTER so the test below will work ... 6629 */ 6630 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 6631 master_mbox != mbox) { 6632 int waiting = FW_CMD_HELLO_TIMEOUT; 6633 6634 /* 6635 * Wait for the firmware to either indicate an error or 6636 * initialized state. If we see either of these we bail out 6637 * and report the issue to the caller. If we exhaust the 6638 * "hello timeout" and we haven't exhausted our retries, try 6639 * again. Otherwise bail with a timeout error. 6640 */ 6641 for (;;) { 6642 u32 pcie_fw; 6643 6644 msleep(50); 6645 waiting -= 50; 6646 6647 /* 6648 * If neither Error nor Initialialized are indicated 6649 * by the firmware keep waiting till we exhaust our 6650 * timeout ... and then retry if we haven't exhausted 6651 * our retries ... 6652 */ 6653 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 6654 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 6655 if (waiting <= 0) { 6656 if (retries-- > 0) 6657 goto retry; 6658 6659 return -ETIMEDOUT; 6660 } 6661 continue; 6662 } 6663 6664 /* 6665 * We either have an Error or Initialized condition 6666 * report errors preferentially. 6667 */ 6668 if (state) { 6669 if (pcie_fw & F_PCIE_FW_ERR) 6670 *state = DEV_STATE_ERR; 6671 else if (pcie_fw & F_PCIE_FW_INIT) 6672 *state = DEV_STATE_INIT; 6673 } 6674 6675 /* 6676 * If we arrived before a Master PF was selected and 6677 * there's not a valid Master PF, grab its identity 6678 * for our caller. 6679 */ 6680 if (master_mbox == M_PCIE_FW_MASTER && 6681 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 6682 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 6683 break; 6684 } 6685 } 6686 6687 return master_mbox; 6688 } 6689 6690 /** 6691 * t4_fw_bye - end communication with FW 6692 * @adap: the adapter 6693 * @mbox: mailbox to use for the FW command 6694 * 6695 * Issues a command to terminate communication with FW. 6696 */ 6697 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 6698 { 6699 struct fw_bye_cmd c; 6700 6701 memset(&c, 0, sizeof(c)); 6702 INIT_CMD(c, BYE, WRITE); 6703 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6704 } 6705 6706 /** 6707 * t4_fw_reset - issue a reset to FW 6708 * @adap: the adapter 6709 * @mbox: mailbox to use for the FW command 6710 * @reset: specifies the type of reset to perform 6711 * 6712 * Issues a reset command of the specified type to FW. 6713 */ 6714 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 6715 { 6716 struct fw_reset_cmd c; 6717 6718 memset(&c, 0, sizeof(c)); 6719 INIT_CMD(c, RESET, WRITE); 6720 c.val = cpu_to_be32(reset); 6721 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6722 } 6723 6724 /** 6725 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 6726 * @adap: the adapter 6727 * @mbox: mailbox to use for the FW RESET command (if desired) 6728 * @force: force uP into RESET even if FW RESET command fails 6729 * 6730 * Issues a RESET command to firmware (if desired) with a HALT indication 6731 * and then puts the microprocessor into RESET state. The RESET command 6732 * will only be issued if a legitimate mailbox is provided (mbox <= 6733 * M_PCIE_FW_MASTER). 6734 * 6735 * This is generally used in order for the host to safely manipulate the 6736 * adapter without fear of conflicting with whatever the firmware might 6737 * be doing. The only way out of this state is to RESTART the firmware 6738 * ... 6739 */ 6740 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 6741 { 6742 int ret = 0; 6743 6744 /* 6745 * If a legitimate mailbox is provided, issue a RESET command 6746 * with a HALT indication. 6747 */ 6748 if (mbox <= M_PCIE_FW_MASTER) { 6749 struct fw_reset_cmd c; 6750 6751 memset(&c, 0, sizeof(c)); 6752 INIT_CMD(c, RESET, WRITE); 6753 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 6754 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 6755 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6756 } 6757 6758 /* 6759 * Normally we won't complete the operation if the firmware RESET 6760 * command fails but if our caller insists we'll go ahead and put the 6761 * uP into RESET. This can be useful if the firmware is hung or even 6762 * missing ... We'll have to take the risk of putting the uP into 6763 * RESET without the cooperation of firmware in that case. 6764 * 6765 * We also force the firmware's HALT flag to be on in case we bypassed 6766 * the firmware RESET command above or we're dealing with old firmware 6767 * which doesn't have the HALT capability. This will serve as a flag 6768 * for the incoming firmware to know that it's coming out of a HALT 6769 * rather than a RESET ... if it's new enough to understand that ... 6770 */ 6771 if (ret == 0 || force) { 6772 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 6773 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 6774 F_PCIE_FW_HALT); 6775 } 6776 6777 /* 6778 * And we always return the result of the firmware RESET command 6779 * even when we force the uP into RESET ... 6780 */ 6781 return ret; 6782 } 6783 6784 /** 6785 * t4_fw_restart - restart the firmware by taking the uP out of RESET 6786 * @adap: the adapter 6787 * @reset: if we want to do a RESET to restart things 6788 * 6789 * Restart firmware previously halted by t4_fw_halt(). On successful 6790 * return the previous PF Master remains as the new PF Master and there 6791 * is no need to issue a new HELLO command, etc. 6792 * 6793 * We do this in two ways: 6794 * 6795 * 1. If we're dealing with newer firmware we'll simply want to take 6796 * the chip's microprocessor out of RESET. This will cause the 6797 * firmware to start up from its start vector. And then we'll loop 6798 * until the firmware indicates it's started again (PCIE_FW.HALT 6799 * reset to 0) or we timeout. 6800 * 6801 * 2. If we're dealing with older firmware then we'll need to RESET 6802 * the chip since older firmware won't recognize the PCIE_FW.HALT 6803 * flag and automatically RESET itself on startup. 6804 */ 6805 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 6806 { 6807 if (reset) { 6808 /* 6809 * Since we're directing the RESET instead of the firmware 6810 * doing it automatically, we need to clear the PCIE_FW.HALT 6811 * bit. 6812 */ 6813 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0); 6814 6815 /* 6816 * If we've been given a valid mailbox, first try to get the 6817 * firmware to do the RESET. If that works, great and we can 6818 * return success. Otherwise, if we haven't been given a 6819 * valid mailbox or the RESET command failed, fall back to 6820 * hitting the chip with a hammer. 6821 */ 6822 if (mbox <= M_PCIE_FW_MASTER) { 6823 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6824 msleep(100); 6825 if (t4_fw_reset(adap, mbox, 6826 F_PIORST | F_PIORSTMODE) == 0) 6827 return 0; 6828 } 6829 6830 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 6831 msleep(2000); 6832 } else { 6833 int ms; 6834 6835 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6836 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 6837 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 6838 return FW_SUCCESS; 6839 msleep(100); 6840 ms += 100; 6841 } 6842 return -ETIMEDOUT; 6843 } 6844 return 0; 6845 } 6846 6847 /** 6848 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 6849 * @adap: the adapter 6850 * @mbox: mailbox to use for the FW RESET command (if desired) 6851 * @fw_data: the firmware image to write 6852 * @size: image size 6853 * @force: force upgrade even if firmware doesn't cooperate 6854 * 6855 * Perform all of the steps necessary for upgrading an adapter's 6856 * firmware image. Normally this requires the cooperation of the 6857 * existing firmware in order to halt all existing activities 6858 * but if an invalid mailbox token is passed in we skip that step 6859 * (though we'll still put the adapter microprocessor into RESET in 6860 * that case). 6861 * 6862 * On successful return the new firmware will have been loaded and 6863 * the adapter will have been fully RESET losing all previous setup 6864 * state. On unsuccessful return the adapter may be completely hosed ... 6865 * positive errno indicates that the adapter is ~probably~ intact, a 6866 * negative errno indicates that things are looking bad ... 6867 */ 6868 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 6869 const u8 *fw_data, unsigned int size, int force) 6870 { 6871 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 6872 unsigned int bootstrap = 6873 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 6874 int reset, ret; 6875 6876 if (!t4_fw_matches_chip(adap, fw_hdr)) 6877 return -EINVAL; 6878 6879 if (!bootstrap) { 6880 ret = t4_fw_halt(adap, mbox, force); 6881 if (ret < 0 && !force) 6882 return ret; 6883 } 6884 6885 ret = t4_load_fw(adap, fw_data, size); 6886 if (ret < 0 || bootstrap) 6887 return ret; 6888 6889 /* 6890 * Older versions of the firmware don't understand the new 6891 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 6892 * restart. So for newly loaded older firmware we'll have to do the 6893 * RESET for it so it starts up on a clean slate. We can tell if 6894 * the newly loaded firmware will handle this right by checking 6895 * its header flags to see if it advertises the capability. 6896 */ 6897 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 6898 return t4_fw_restart(adap, mbox, reset); 6899 } 6900 6901 /* 6902 * Card doesn't have a firmware, install one. 6903 */ 6904 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data, 6905 unsigned int size) 6906 { 6907 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 6908 unsigned int bootstrap = 6909 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 6910 int ret; 6911 6912 if (!t4_fw_matches_chip(adap, fw_hdr) || bootstrap) 6913 return -EINVAL; 6914 6915 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 6916 t4_write_reg(adap, A_PCIE_FW, 0); /* Clobber internal state */ 6917 ret = t4_load_fw(adap, fw_data, size); 6918 if (ret < 0) 6919 return ret; 6920 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 6921 msleep(1000); 6922 6923 return (0); 6924 } 6925 6926 /** 6927 * t4_fw_initialize - ask FW to initialize the device 6928 * @adap: the adapter 6929 * @mbox: mailbox to use for the FW command 6930 * 6931 * Issues a command to FW to partially initialize the device. This 6932 * performs initialization that generally doesn't depend on user input. 6933 */ 6934 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 6935 { 6936 struct fw_initialize_cmd c; 6937 6938 memset(&c, 0, sizeof(c)); 6939 INIT_CMD(c, INITIALIZE, WRITE); 6940 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6941 } 6942 6943 /** 6944 * t4_query_params_rw - query FW or device parameters 6945 * @adap: the adapter 6946 * @mbox: mailbox to use for the FW command 6947 * @pf: the PF 6948 * @vf: the VF 6949 * @nparams: the number of parameters 6950 * @params: the parameter names 6951 * @val: the parameter values 6952 * @rw: Write and read flag 6953 * 6954 * Reads the value of FW or device parameters. Up to 7 parameters can be 6955 * queried at once. 6956 */ 6957 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 6958 unsigned int vf, unsigned int nparams, const u32 *params, 6959 u32 *val, int rw) 6960 { 6961 int i, ret; 6962 struct fw_params_cmd c; 6963 __be32 *p = &c.param[0].mnem; 6964 6965 if (nparams > 7) 6966 return -EINVAL; 6967 6968 memset(&c, 0, sizeof(c)); 6969 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 6970 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6971 V_FW_PARAMS_CMD_PFN(pf) | 6972 V_FW_PARAMS_CMD_VFN(vf)); 6973 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 6974 6975 for (i = 0; i < nparams; i++) { 6976 *p++ = cpu_to_be32(*params++); 6977 if (rw) 6978 *p = cpu_to_be32(*(val + i)); 6979 p++; 6980 } 6981 6982 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6983 if (ret == 0) 6984 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 6985 *val++ = be32_to_cpu(*p); 6986 return ret; 6987 } 6988 6989 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 6990 unsigned int vf, unsigned int nparams, const u32 *params, 6991 u32 *val) 6992 { 6993 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 6994 } 6995 6996 /** 6997 * t4_set_params_timeout - sets FW or device parameters 6998 * @adap: the adapter 6999 * @mbox: mailbox to use for the FW command 7000 * @pf: the PF 7001 * @vf: the VF 7002 * @nparams: the number of parameters 7003 * @params: the parameter names 7004 * @val: the parameter values 7005 * @timeout: the timeout time 7006 * 7007 * Sets the value of FW or device parameters. Up to 7 parameters can be 7008 * specified at once. 7009 */ 7010 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7011 unsigned int pf, unsigned int vf, 7012 unsigned int nparams, const u32 *params, 7013 const u32 *val, int timeout) 7014 { 7015 struct fw_params_cmd c; 7016 __be32 *p = &c.param[0].mnem; 7017 7018 if (nparams > 7) 7019 return -EINVAL; 7020 7021 memset(&c, 0, sizeof(c)); 7022 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7023 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7024 V_FW_PARAMS_CMD_PFN(pf) | 7025 V_FW_PARAMS_CMD_VFN(vf)); 7026 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7027 7028 while (nparams--) { 7029 *p++ = cpu_to_be32(*params++); 7030 *p++ = cpu_to_be32(*val++); 7031 } 7032 7033 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7034 } 7035 7036 /** 7037 * t4_set_params - sets FW or device parameters 7038 * @adap: the adapter 7039 * @mbox: mailbox to use for the FW command 7040 * @pf: the PF 7041 * @vf: the VF 7042 * @nparams: the number of parameters 7043 * @params: the parameter names 7044 * @val: the parameter values 7045 * 7046 * Sets the value of FW or device parameters. Up to 7 parameters can be 7047 * specified at once. 7048 */ 7049 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7050 unsigned int vf, unsigned int nparams, const u32 *params, 7051 const u32 *val) 7052 { 7053 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7054 FW_CMD_MAX_TIMEOUT); 7055 } 7056 7057 /** 7058 * t4_cfg_pfvf - configure PF/VF resource limits 7059 * @adap: the adapter 7060 * @mbox: mailbox to use for the FW command 7061 * @pf: the PF being configured 7062 * @vf: the VF being configured 7063 * @txq: the max number of egress queues 7064 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7065 * @rxqi: the max number of interrupt-capable ingress queues 7066 * @rxq: the max number of interruptless ingress queues 7067 * @tc: the PCI traffic class 7068 * @vi: the max number of virtual interfaces 7069 * @cmask: the channel access rights mask for the PF/VF 7070 * @pmask: the port access rights mask for the PF/VF 7071 * @nexact: the maximum number of exact MPS filters 7072 * @rcaps: read capabilities 7073 * @wxcaps: write/execute capabilities 7074 * 7075 * Configures resource limits and capabilities for a physical or virtual 7076 * function. 7077 */ 7078 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7079 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7080 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7081 unsigned int vi, unsigned int cmask, unsigned int pmask, 7082 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7083 { 7084 struct fw_pfvf_cmd c; 7085 7086 memset(&c, 0, sizeof(c)); 7087 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7088 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7089 V_FW_PFVF_CMD_VFN(vf)); 7090 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7091 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7092 V_FW_PFVF_CMD_NIQ(rxq)); 7093 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7094 V_FW_PFVF_CMD_PMASK(pmask) | 7095 V_FW_PFVF_CMD_NEQ(txq)); 7096 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7097 V_FW_PFVF_CMD_NVI(vi) | 7098 V_FW_PFVF_CMD_NEXACTF(nexact)); 7099 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7100 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7101 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7102 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7103 } 7104 7105 /** 7106 * t4_alloc_vi_func - allocate a virtual interface 7107 * @adap: the adapter 7108 * @mbox: mailbox to use for the FW command 7109 * @port: physical port associated with the VI 7110 * @pf: the PF owning the VI 7111 * @vf: the VF owning the VI 7112 * @nmac: number of MAC addresses needed (1 to 5) 7113 * @mac: the MAC addresses of the VI 7114 * @rss_size: size of RSS table slice associated with this VI 7115 * @portfunc: which Port Application Function MAC Address is desired 7116 * @idstype: Intrusion Detection Type 7117 * 7118 * Allocates a virtual interface for the given physical port. If @mac is 7119 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7120 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7121 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7122 * stored consecutively so the space needed is @nmac * 6 bytes. 7123 * Returns a negative error number or the non-negative VI id. 7124 */ 7125 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7126 unsigned int port, unsigned int pf, unsigned int vf, 7127 unsigned int nmac, u8 *mac, u16 *rss_size, 7128 unsigned int portfunc, unsigned int idstype) 7129 { 7130 int ret; 7131 struct fw_vi_cmd c; 7132 7133 memset(&c, 0, sizeof(c)); 7134 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7135 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7136 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7137 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7138 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7139 V_FW_VI_CMD_FUNC(portfunc)); 7140 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7141 c.nmac = nmac - 1; 7142 if(!rss_size) 7143 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7144 7145 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7146 if (ret) 7147 return ret; 7148 7149 if (mac) { 7150 memcpy(mac, c.mac, sizeof(c.mac)); 7151 switch (nmac) { 7152 case 5: 7153 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7154 case 4: 7155 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7156 case 3: 7157 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7158 case 2: 7159 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7160 } 7161 } 7162 if (rss_size) 7163 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7164 return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7165 } 7166 7167 /** 7168 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7169 * @adap: the adapter 7170 * @mbox: mailbox to use for the FW command 7171 * @port: physical port associated with the VI 7172 * @pf: the PF owning the VI 7173 * @vf: the VF owning the VI 7174 * @nmac: number of MAC addresses needed (1 to 5) 7175 * @mac: the MAC addresses of the VI 7176 * @rss_size: size of RSS table slice associated with this VI 7177 * 7178 * backwards compatible and convieniance routine to allocate a Virtual 7179 * Interface with a Ethernet Port Application Function and Intrustion 7180 * Detection System disabled. 7181 */ 7182 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 7183 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 7184 u16 *rss_size) 7185 { 7186 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 7187 FW_VI_FUNC_ETH, 0); 7188 } 7189 7190 /** 7191 * t4_free_vi - free a virtual interface 7192 * @adap: the adapter 7193 * @mbox: mailbox to use for the FW command 7194 * @pf: the PF owning the VI 7195 * @vf: the VF owning the VI 7196 * @viid: virtual interface identifiler 7197 * 7198 * Free a previously allocated virtual interface. 7199 */ 7200 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 7201 unsigned int vf, unsigned int viid) 7202 { 7203 struct fw_vi_cmd c; 7204 7205 memset(&c, 0, sizeof(c)); 7206 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 7207 F_FW_CMD_REQUEST | 7208 F_FW_CMD_EXEC | 7209 V_FW_VI_CMD_PFN(pf) | 7210 V_FW_VI_CMD_VFN(vf)); 7211 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 7212 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 7213 7214 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7215 } 7216 7217 /** 7218 * t4_set_rxmode - set Rx properties of a virtual interface 7219 * @adap: the adapter 7220 * @mbox: mailbox to use for the FW command 7221 * @viid: the VI id 7222 * @mtu: the new MTU or -1 7223 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 7224 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 7225 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 7226 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 7227 * @sleep_ok: if true we may sleep while awaiting command completion 7228 * 7229 * Sets Rx properties of a virtual interface. 7230 */ 7231 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 7232 int mtu, int promisc, int all_multi, int bcast, int vlanex, 7233 bool sleep_ok) 7234 { 7235 struct fw_vi_rxmode_cmd c; 7236 7237 /* convert to FW values */ 7238 if (mtu < 0) 7239 mtu = M_FW_VI_RXMODE_CMD_MTU; 7240 if (promisc < 0) 7241 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 7242 if (all_multi < 0) 7243 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 7244 if (bcast < 0) 7245 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 7246 if (vlanex < 0) 7247 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 7248 7249 memset(&c, 0, sizeof(c)); 7250 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 7251 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7252 V_FW_VI_RXMODE_CMD_VIID(viid)); 7253 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7254 c.mtu_to_vlanexen = 7255 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 7256 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 7257 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 7258 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 7259 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 7260 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7261 } 7262 7263 /** 7264 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 7265 * @adap: the adapter 7266 * @mbox: mailbox to use for the FW command 7267 * @viid: the VI id 7268 * @free: if true any existing filters for this VI id are first removed 7269 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 7270 * @addr: the MAC address(es) 7271 * @idx: where to store the index of each allocated filter 7272 * @hash: pointer to hash address filter bitmap 7273 * @sleep_ok: call is allowed to sleep 7274 * 7275 * Allocates an exact-match filter for each of the supplied addresses and 7276 * sets it to the corresponding address. If @idx is not %NULL it should 7277 * have at least @naddr entries, each of which will be set to the index of 7278 * the filter allocated for the corresponding MAC address. If a filter 7279 * could not be allocated for an address its index is set to 0xffff. 7280 * If @hash is not %NULL addresses that fail to allocate an exact filter 7281 * are hashed and update the hash filter bitmap pointed at by @hash. 7282 * 7283 * Returns a negative error number or the number of filters allocated. 7284 */ 7285 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 7286 unsigned int viid, bool free, unsigned int naddr, 7287 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 7288 { 7289 int offset, ret = 0; 7290 struct fw_vi_mac_cmd c; 7291 unsigned int nfilters = 0; 7292 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 7293 unsigned int rem = naddr; 7294 7295 if (naddr > max_naddr) 7296 return -EINVAL; 7297 7298 for (offset = 0; offset < naddr ; /**/) { 7299 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 7300 ? rem 7301 : ARRAY_SIZE(c.u.exact)); 7302 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 7303 u.exact[fw_naddr]), 16); 7304 struct fw_vi_mac_exact *p; 7305 int i; 7306 7307 memset(&c, 0, sizeof(c)); 7308 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7309 F_FW_CMD_REQUEST | 7310 F_FW_CMD_WRITE | 7311 V_FW_CMD_EXEC(free) | 7312 V_FW_VI_MAC_CMD_VIID(viid)); 7313 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 7314 V_FW_CMD_LEN16(len16)); 7315 7316 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7317 p->valid_to_idx = 7318 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7319 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 7320 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 7321 } 7322 7323 /* 7324 * It's okay if we run out of space in our MAC address arena. 7325 * Some of the addresses we submit may get stored so we need 7326 * to run through the reply to see what the results were ... 7327 */ 7328 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 7329 if (ret && ret != -FW_ENOMEM) 7330 break; 7331 7332 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7333 u16 index = G_FW_VI_MAC_CMD_IDX( 7334 be16_to_cpu(p->valid_to_idx)); 7335 7336 if (idx) 7337 idx[offset+i] = (index >= max_naddr 7338 ? 0xffff 7339 : index); 7340 if (index < max_naddr) 7341 nfilters++; 7342 else if (hash) 7343 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 7344 } 7345 7346 free = false; 7347 offset += fw_naddr; 7348 rem -= fw_naddr; 7349 } 7350 7351 if (ret == 0 || ret == -FW_ENOMEM) 7352 ret = nfilters; 7353 return ret; 7354 } 7355 7356 /** 7357 * t4_change_mac - modifies the exact-match filter for a MAC address 7358 * @adap: the adapter 7359 * @mbox: mailbox to use for the FW command 7360 * @viid: the VI id 7361 * @idx: index of existing filter for old value of MAC address, or -1 7362 * @addr: the new MAC address value 7363 * @persist: whether a new MAC allocation should be persistent 7364 * @add_smt: if true also add the address to the HW SMT 7365 * 7366 * Modifies an exact-match filter and sets it to the new MAC address if 7367 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 7368 * latter case the address is added persistently if @persist is %true. 7369 * 7370 * Note that in general it is not possible to modify the value of a given 7371 * filter so the generic way to modify an address filter is to free the one 7372 * being used by the old address value and allocate a new filter for the 7373 * new address value. 7374 * 7375 * Returns a negative error number or the index of the filter with the new 7376 * MAC value. Note that this index may differ from @idx. 7377 */ 7378 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 7379 int idx, const u8 *addr, bool persist, bool add_smt) 7380 { 7381 int ret, mode; 7382 struct fw_vi_mac_cmd c; 7383 struct fw_vi_mac_exact *p = c.u.exact; 7384 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 7385 7386 if (idx < 0) /* new allocation */ 7387 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 7388 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 7389 7390 memset(&c, 0, sizeof(c)); 7391 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7392 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7393 V_FW_VI_MAC_CMD_VIID(viid)); 7394 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 7395 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7396 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 7397 V_FW_VI_MAC_CMD_IDX(idx)); 7398 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 7399 7400 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7401 if (ret == 0) { 7402 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 7403 if (ret >= max_mac_addr) 7404 ret = -ENOMEM; 7405 } 7406 return ret; 7407 } 7408 7409 /** 7410 * t4_set_addr_hash - program the MAC inexact-match hash filter 7411 * @adap: the adapter 7412 * @mbox: mailbox to use for the FW command 7413 * @viid: the VI id 7414 * @ucast: whether the hash filter should also match unicast addresses 7415 * @vec: the value to be written to the hash filter 7416 * @sleep_ok: call is allowed to sleep 7417 * 7418 * Sets the 64-bit inexact-match hash filter for a virtual interface. 7419 */ 7420 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 7421 bool ucast, u64 vec, bool sleep_ok) 7422 { 7423 struct fw_vi_mac_cmd c; 7424 u32 val; 7425 7426 memset(&c, 0, sizeof(c)); 7427 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7428 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7429 V_FW_VI_ENABLE_CMD_VIID(viid)); 7430 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 7431 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 7432 c.freemacs_to_len16 = cpu_to_be32(val); 7433 c.u.hash.hashvec = cpu_to_be64(vec); 7434 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7435 } 7436 7437 /** 7438 * t4_enable_vi_params - enable/disable a virtual interface 7439 * @adap: the adapter 7440 * @mbox: mailbox to use for the FW command 7441 * @viid: the VI id 7442 * @rx_en: 1=enable Rx, 0=disable Rx 7443 * @tx_en: 1=enable Tx, 0=disable Tx 7444 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 7445 * 7446 * Enables/disables a virtual interface. Note that setting DCB Enable 7447 * only makes sense when enabling a Virtual Interface ... 7448 */ 7449 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 7450 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 7451 { 7452 struct fw_vi_enable_cmd c; 7453 7454 memset(&c, 0, sizeof(c)); 7455 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7456 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7457 V_FW_VI_ENABLE_CMD_VIID(viid)); 7458 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 7459 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 7460 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 7461 FW_LEN16(c)); 7462 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 7463 } 7464 7465 /** 7466 * t4_enable_vi - enable/disable a virtual interface 7467 * @adap: the adapter 7468 * @mbox: mailbox to use for the FW command 7469 * @viid: the VI id 7470 * @rx_en: 1=enable Rx, 0=disable Rx 7471 * @tx_en: 1=enable Tx, 0=disable Tx 7472 * 7473 * Enables/disables a virtual interface. Note that setting DCB Enable 7474 * only makes sense when enabling a Virtual Interface ... 7475 */ 7476 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 7477 bool rx_en, bool tx_en) 7478 { 7479 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 7480 } 7481 7482 /** 7483 * t4_identify_port - identify a VI's port by blinking its LED 7484 * @adap: the adapter 7485 * @mbox: mailbox to use for the FW command 7486 * @viid: the VI id 7487 * @nblinks: how many times to blink LED at 2.5 Hz 7488 * 7489 * Identifies a VI's port by blinking its LED. 7490 */ 7491 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 7492 unsigned int nblinks) 7493 { 7494 struct fw_vi_enable_cmd c; 7495 7496 memset(&c, 0, sizeof(c)); 7497 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7498 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7499 V_FW_VI_ENABLE_CMD_VIID(viid)); 7500 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 7501 c.blinkdur = cpu_to_be16(nblinks); 7502 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7503 } 7504 7505 /** 7506 * t4_iq_stop - stop an ingress queue and its FLs 7507 * @adap: the adapter 7508 * @mbox: mailbox to use for the FW command 7509 * @pf: the PF owning the queues 7510 * @vf: the VF owning the queues 7511 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7512 * @iqid: ingress queue id 7513 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7514 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7515 * 7516 * Stops an ingress queue and its associated FLs, if any. This causes 7517 * any current or future data/messages destined for these queues to be 7518 * tossed. 7519 */ 7520 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 7521 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7522 unsigned int fl0id, unsigned int fl1id) 7523 { 7524 struct fw_iq_cmd c; 7525 7526 memset(&c, 0, sizeof(c)); 7527 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7528 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7529 V_FW_IQ_CMD_VFN(vf)); 7530 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 7531 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7532 c.iqid = cpu_to_be16(iqid); 7533 c.fl0id = cpu_to_be16(fl0id); 7534 c.fl1id = cpu_to_be16(fl1id); 7535 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7536 } 7537 7538 /** 7539 * t4_iq_free - free an ingress queue and its FLs 7540 * @adap: the adapter 7541 * @mbox: mailbox to use for the FW command 7542 * @pf: the PF owning the queues 7543 * @vf: the VF owning the queues 7544 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7545 * @iqid: ingress queue id 7546 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7547 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7548 * 7549 * Frees an ingress queue and its associated FLs, if any. 7550 */ 7551 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7552 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7553 unsigned int fl0id, unsigned int fl1id) 7554 { 7555 struct fw_iq_cmd c; 7556 7557 memset(&c, 0, sizeof(c)); 7558 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7559 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7560 V_FW_IQ_CMD_VFN(vf)); 7561 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 7562 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7563 c.iqid = cpu_to_be16(iqid); 7564 c.fl0id = cpu_to_be16(fl0id); 7565 c.fl1id = cpu_to_be16(fl1id); 7566 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7567 } 7568 7569 /** 7570 * t4_eth_eq_free - free an Ethernet egress queue 7571 * @adap: the adapter 7572 * @mbox: mailbox to use for the FW command 7573 * @pf: the PF owning the queue 7574 * @vf: the VF owning the queue 7575 * @eqid: egress queue id 7576 * 7577 * Frees an Ethernet egress queue. 7578 */ 7579 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7580 unsigned int vf, unsigned int eqid) 7581 { 7582 struct fw_eq_eth_cmd c; 7583 7584 memset(&c, 0, sizeof(c)); 7585 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 7586 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7587 V_FW_EQ_ETH_CMD_PFN(pf) | 7588 V_FW_EQ_ETH_CMD_VFN(vf)); 7589 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 7590 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 7591 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7592 } 7593 7594 /** 7595 * t4_ctrl_eq_free - free a control egress queue 7596 * @adap: the adapter 7597 * @mbox: mailbox to use for the FW command 7598 * @pf: the PF owning the queue 7599 * @vf: the VF owning the queue 7600 * @eqid: egress queue id 7601 * 7602 * Frees a control egress queue. 7603 */ 7604 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7605 unsigned int vf, unsigned int eqid) 7606 { 7607 struct fw_eq_ctrl_cmd c; 7608 7609 memset(&c, 0, sizeof(c)); 7610 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 7611 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7612 V_FW_EQ_CTRL_CMD_PFN(pf) | 7613 V_FW_EQ_CTRL_CMD_VFN(vf)); 7614 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 7615 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 7616 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7617 } 7618 7619 /** 7620 * t4_ofld_eq_free - free an offload egress queue 7621 * @adap: the adapter 7622 * @mbox: mailbox to use for the FW command 7623 * @pf: the PF owning the queue 7624 * @vf: the VF owning the queue 7625 * @eqid: egress queue id 7626 * 7627 * Frees a control egress queue. 7628 */ 7629 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7630 unsigned int vf, unsigned int eqid) 7631 { 7632 struct fw_eq_ofld_cmd c; 7633 7634 memset(&c, 0, sizeof(c)); 7635 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 7636 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7637 V_FW_EQ_OFLD_CMD_PFN(pf) | 7638 V_FW_EQ_OFLD_CMD_VFN(vf)); 7639 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 7640 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 7641 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7642 } 7643 7644 /** 7645 * t4_link_down_rc_str - return a string for a Link Down Reason Code 7646 * @link_down_rc: Link Down Reason Code 7647 * 7648 * Returns a string representation of the Link Down Reason Code. 7649 */ 7650 const char *t4_link_down_rc_str(unsigned char link_down_rc) 7651 { 7652 static const char *reason[] = { 7653 "Link Down", 7654 "Remote Fault", 7655 "Auto-negotiation Failure", 7656 "Reserved3", 7657 "Insufficient Airflow", 7658 "Unable To Determine Reason", 7659 "No RX Signal Detected", 7660 "Reserved7", 7661 }; 7662 7663 if (link_down_rc >= ARRAY_SIZE(reason)) 7664 return "Bad Reason Code"; 7665 7666 return reason[link_down_rc]; 7667 } 7668 7669 /* 7670 * Updates all fields owned by the common code in port_info and link_config 7671 * based on information provided by the firmware. Does not touch any 7672 * requested_* field. 7673 */ 7674 static void handle_port_info(struct port_info *pi, const struct fw_port_info *p) 7675 { 7676 struct link_config *lc = &pi->link_cfg; 7677 int speed; 7678 unsigned char fc, fec; 7679 u32 stat = be32_to_cpu(p->lstatus_to_modtype); 7680 7681 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 7682 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 7683 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 7684 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 7685 7686 lc->supported = be16_to_cpu(p->pcap); 7687 lc->advertising = be16_to_cpu(p->acap); 7688 lc->lp_advertising = be16_to_cpu(p->lpacap); 7689 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 7690 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 7691 7692 speed = 0; 7693 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 7694 speed = 100; 7695 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 7696 speed = 1000; 7697 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 7698 speed = 10000; 7699 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 7700 speed = 25000; 7701 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 7702 speed = 40000; 7703 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 7704 speed = 100000; 7705 lc->speed = speed; 7706 7707 fc = 0; 7708 if (stat & F_FW_PORT_CMD_RXPAUSE) 7709 fc |= PAUSE_RX; 7710 if (stat & F_FW_PORT_CMD_TXPAUSE) 7711 fc |= PAUSE_TX; 7712 lc->fc = fc; 7713 7714 fec = 0; 7715 if (lc->advertising & FW_PORT_CAP_FEC_RS) 7716 fec |= FEC_RS; 7717 if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS) 7718 fec |= FEC_BASER_RS; 7719 if (lc->advertising & FW_PORT_CAP_FEC_RESERVED) 7720 fec |= FEC_RESERVED; 7721 lc->fec = fec; 7722 } 7723 7724 /** 7725 * t4_update_port_info - retrieve and update port information if changed 7726 * @pi: the port_info 7727 * 7728 * We issue a Get Port Information Command to the Firmware and, if 7729 * successful, we check to see if anything is different from what we 7730 * last recorded and update things accordingly. 7731 */ 7732 int t4_update_port_info(struct port_info *pi) 7733 { 7734 struct fw_port_cmd port_cmd; 7735 int ret; 7736 7737 memset(&port_cmd, 0, sizeof port_cmd); 7738 port_cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 7739 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7740 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 7741 port_cmd.action_to_len16 = cpu_to_be32( 7742 V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) | 7743 FW_LEN16(port_cmd)); 7744 ret = t4_wr_mbox_ns(pi->adapter, pi->adapter->mbox, 7745 &port_cmd, sizeof(port_cmd), &port_cmd); 7746 if (ret) 7747 return ret; 7748 7749 handle_port_info(pi, &port_cmd.u.info); 7750 return 0; 7751 } 7752 7753 /** 7754 * t4_handle_fw_rpl - process a FW reply message 7755 * @adap: the adapter 7756 * @rpl: start of the FW message 7757 * 7758 * Processes a FW message, such as link state change messages. 7759 */ 7760 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 7761 { 7762 u8 opcode = *(const u8 *)rpl; 7763 const struct fw_port_cmd *p = (const void *)rpl; 7764 unsigned int action = 7765 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 7766 7767 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) { 7768 /* link/module state change message */ 7769 int i, old_ptype, old_mtype; 7770 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 7771 struct port_info *pi = NULL; 7772 struct link_config *lc, *old_lc; 7773 7774 for_each_port(adap, i) { 7775 pi = adap2pinfo(adap, i); 7776 if (pi->tx_chan == chan) 7777 break; 7778 } 7779 7780 lc = &pi->link_cfg; 7781 old_lc = &pi->old_link_cfg; 7782 old_ptype = pi->port_type; 7783 old_mtype = pi->mod_type; 7784 7785 handle_port_info(pi, &p->u.info); 7786 if (old_ptype != pi->port_type || old_mtype != pi->mod_type) { 7787 t4_os_portmod_changed(pi); 7788 } 7789 if (old_lc->link_ok != lc->link_ok || 7790 old_lc->speed != lc->speed || 7791 old_lc->fec != lc->fec || 7792 old_lc->fc != lc->fc) { 7793 t4_os_link_changed(pi); 7794 *old_lc = *lc; 7795 } 7796 } else { 7797 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 7798 return -EINVAL; 7799 } 7800 return 0; 7801 } 7802 7803 /** 7804 * get_pci_mode - determine a card's PCI mode 7805 * @adapter: the adapter 7806 * @p: where to store the PCI settings 7807 * 7808 * Determines a card's PCI mode and associated parameters, such as speed 7809 * and width. 7810 */ 7811 static void get_pci_mode(struct adapter *adapter, 7812 struct pci_params *p) 7813 { 7814 u16 val; 7815 u32 pcie_cap; 7816 7817 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 7818 if (pcie_cap) { 7819 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 7820 p->speed = val & PCI_EXP_LNKSTA_CLS; 7821 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 7822 } 7823 } 7824 7825 struct flash_desc { 7826 u32 vendor_and_model_id; 7827 u32 size_mb; 7828 }; 7829 7830 int t4_get_flash_params(struct adapter *adapter) 7831 { 7832 /* 7833 * Table for non-standard supported Flash parts. Note, all Flash 7834 * parts must have 64KB sectors. 7835 */ 7836 static struct flash_desc supported_flash[] = { 7837 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 7838 }; 7839 7840 int ret; 7841 u32 flashid = 0; 7842 unsigned int part, manufacturer; 7843 unsigned int density, size; 7844 7845 7846 /* 7847 * Issue a Read ID Command to the Flash part. We decode supported 7848 * Flash parts and their sizes from this. There's a newer Query 7849 * Command which can retrieve detailed geometry information but many 7850 * Flash parts don't support it. 7851 */ 7852 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 7853 if (!ret) 7854 ret = sf1_read(adapter, 3, 0, 1, &flashid); 7855 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 7856 if (ret < 0) 7857 return ret; 7858 7859 /* 7860 * Check to see if it's one of our non-standard supported Flash parts. 7861 */ 7862 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 7863 if (supported_flash[part].vendor_and_model_id == flashid) { 7864 adapter->params.sf_size = 7865 supported_flash[part].size_mb; 7866 adapter->params.sf_nsec = 7867 adapter->params.sf_size / SF_SEC_SIZE; 7868 goto found; 7869 } 7870 7871 /* 7872 * Decode Flash part size. The code below looks repetative with 7873 * common encodings, but that's not guaranteed in the JEDEC 7874 * specification for the Read JADEC ID command. The only thing that 7875 * we're guaranteed by the JADEC specification is where the 7876 * Manufacturer ID is in the returned result. After that each 7877 * Manufacturer ~could~ encode things completely differently. 7878 * Note, all Flash parts must have 64KB sectors. 7879 */ 7880 manufacturer = flashid & 0xff; 7881 switch (manufacturer) { 7882 case 0x20: { /* Micron/Numonix */ 7883 /* 7884 * This Density -> Size decoding table is taken from Micron 7885 * Data Sheets. 7886 */ 7887 density = (flashid >> 16) & 0xff; 7888 switch (density) { 7889 case 0x14: size = 1 << 20; break; /* 1MB */ 7890 case 0x15: size = 1 << 21; break; /* 2MB */ 7891 case 0x16: size = 1 << 22; break; /* 4MB */ 7892 case 0x17: size = 1 << 23; break; /* 8MB */ 7893 case 0x18: size = 1 << 24; break; /* 16MB */ 7894 case 0x19: size = 1 << 25; break; /* 32MB */ 7895 case 0x20: size = 1 << 26; break; /* 64MB */ 7896 case 0x21: size = 1 << 27; break; /* 128MB */ 7897 case 0x22: size = 1 << 28; break; /* 256MB */ 7898 7899 default: 7900 CH_ERR(adapter, "Micron Flash Part has bad size, " 7901 "ID = %#x, Density code = %#x\n", 7902 flashid, density); 7903 return -EINVAL; 7904 } 7905 break; 7906 } 7907 7908 case 0xef: { /* Winbond */ 7909 /* 7910 * This Density -> Size decoding table is taken from Winbond 7911 * Data Sheets. 7912 */ 7913 density = (flashid >> 16) & 0xff; 7914 switch (density) { 7915 case 0x17: size = 1 << 23; break; /* 8MB */ 7916 case 0x18: size = 1 << 24; break; /* 16MB */ 7917 7918 default: 7919 CH_ERR(adapter, "Winbond Flash Part has bad size, " 7920 "ID = %#x, Density code = %#x\n", 7921 flashid, density); 7922 return -EINVAL; 7923 } 7924 break; 7925 } 7926 7927 default: 7928 CH_ERR(adapter, "Unsupported Flash Part, ID = %#x\n", flashid); 7929 return -EINVAL; 7930 } 7931 7932 /* 7933 * Store decoded Flash size and fall through into vetting code. 7934 */ 7935 adapter->params.sf_size = size; 7936 adapter->params.sf_nsec = size / SF_SEC_SIZE; 7937 7938 found: 7939 /* 7940 * We should ~probably~ reject adapters with FLASHes which are too 7941 * small but we have some legacy FPGAs with small FLASHes that we'd 7942 * still like to use. So instead we emit a scary message ... 7943 */ 7944 if (adapter->params.sf_size < FLASH_MIN_SIZE) 7945 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 7946 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 7947 7948 return 0; 7949 } 7950 7951 static void set_pcie_completion_timeout(struct adapter *adapter, 7952 u8 range) 7953 { 7954 u16 val; 7955 u32 pcie_cap; 7956 7957 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 7958 if (pcie_cap) { 7959 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 7960 val &= 0xfff0; 7961 val |= range ; 7962 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 7963 } 7964 } 7965 7966 const struct chip_params *t4_get_chip_params(int chipid) 7967 { 7968 static const struct chip_params chip_params[] = { 7969 { 7970 /* T4 */ 7971 .nchan = NCHAN, 7972 .pm_stats_cnt = PM_NSTATS, 7973 .cng_ch_bits_log = 2, 7974 .nsched_cls = 15, 7975 .cim_num_obq = CIM_NUM_OBQ, 7976 .mps_rplc_size = 128, 7977 .vfcount = 128, 7978 .sge_fl_db = F_DBPRIO, 7979 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 7980 }, 7981 { 7982 /* T5 */ 7983 .nchan = NCHAN, 7984 .pm_stats_cnt = PM_NSTATS, 7985 .cng_ch_bits_log = 2, 7986 .nsched_cls = 16, 7987 .cim_num_obq = CIM_NUM_OBQ_T5, 7988 .mps_rplc_size = 128, 7989 .vfcount = 128, 7990 .sge_fl_db = F_DBPRIO | F_DBTYPE, 7991 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 7992 }, 7993 { 7994 /* T6 */ 7995 .nchan = T6_NCHAN, 7996 .pm_stats_cnt = T6_PM_NSTATS, 7997 .cng_ch_bits_log = 3, 7998 .nsched_cls = 16, 7999 .cim_num_obq = CIM_NUM_OBQ_T5, 8000 .mps_rplc_size = 256, 8001 .vfcount = 256, 8002 .sge_fl_db = 0, 8003 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8004 }, 8005 }; 8006 8007 chipid -= CHELSIO_T4; 8008 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 8009 return NULL; 8010 8011 return &chip_params[chipid]; 8012 } 8013 8014 /** 8015 * t4_prep_adapter - prepare SW and HW for operation 8016 * @adapter: the adapter 8017 * @buf: temporary space of at least VPD_LEN size provided by the caller. 8018 * 8019 * Initialize adapter SW state for the various HW modules, set initial 8020 * values for some adapter tunables, take PHYs out of reset, and 8021 * initialize the MDIO interface. 8022 */ 8023 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 8024 { 8025 int ret; 8026 uint16_t device_id; 8027 uint32_t pl_rev; 8028 8029 get_pci_mode(adapter, &adapter->params.pci); 8030 8031 pl_rev = t4_read_reg(adapter, A_PL_REV); 8032 adapter->params.chipid = G_CHIPID(pl_rev); 8033 adapter->params.rev = G_REV(pl_rev); 8034 if (adapter->params.chipid == 0) { 8035 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 8036 adapter->params.chipid = CHELSIO_T4; 8037 8038 /* T4A1 chip is not supported */ 8039 if (adapter->params.rev == 1) { 8040 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 8041 return -EINVAL; 8042 } 8043 } 8044 8045 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 8046 if (adapter->chip_params == NULL) 8047 return -EINVAL; 8048 8049 adapter->params.pci.vpd_cap_addr = 8050 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 8051 8052 ret = t4_get_flash_params(adapter); 8053 if (ret < 0) 8054 return ret; 8055 8056 ret = get_vpd_params(adapter, &adapter->params.vpd, buf); 8057 if (ret < 0) 8058 return ret; 8059 8060 /* Cards with real ASICs have the chipid in the PCIe device id */ 8061 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 8062 if (device_id >> 12 == chip_id(adapter)) 8063 adapter->params.cim_la_size = CIMLA_SIZE; 8064 else { 8065 /* FPGA */ 8066 adapter->params.fpga = 1; 8067 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 8068 } 8069 8070 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 8071 8072 /* 8073 * Default port and clock for debugging in case we can't reach FW. 8074 */ 8075 adapter->params.nports = 1; 8076 adapter->params.portvec = 1; 8077 adapter->params.vpd.cclk = 50000; 8078 8079 /* Set pci completion timeout value to 4 seconds. */ 8080 set_pcie_completion_timeout(adapter, 0xd); 8081 return 0; 8082 } 8083 8084 /** 8085 * t4_shutdown_adapter - shut down adapter, host & wire 8086 * @adapter: the adapter 8087 * 8088 * Perform an emergency shutdown of the adapter and stop it from 8089 * continuing any further communication on the ports or DMA to the 8090 * host. This is typically used when the adapter and/or firmware 8091 * have crashed and we want to prevent any further accidental 8092 * communication with the rest of the world. This will also force 8093 * the port Link Status to go down -- if register writes work -- 8094 * which should help our peers figure out that we're down. 8095 */ 8096 int t4_shutdown_adapter(struct adapter *adapter) 8097 { 8098 int port; 8099 8100 t4_intr_disable(adapter); 8101 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 8102 for_each_port(adapter, port) { 8103 u32 a_port_cfg = is_t4(adapter) ? 8104 PORT_REG(port, A_XGMAC_PORT_CFG) : 8105 T5_PORT_REG(port, A_MAC_PORT_CFG); 8106 8107 t4_write_reg(adapter, a_port_cfg, 8108 t4_read_reg(adapter, a_port_cfg) 8109 & ~V_SIGNAL_DET(1)); 8110 } 8111 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 8112 8113 return 0; 8114 } 8115 8116 /** 8117 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 8118 * @adapter: the adapter 8119 * @qid: the Queue ID 8120 * @qtype: the Ingress or Egress type for @qid 8121 * @user: true if this request is for a user mode queue 8122 * @pbar2_qoffset: BAR2 Queue Offset 8123 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 8124 * 8125 * Returns the BAR2 SGE Queue Registers information associated with the 8126 * indicated Absolute Queue ID. These are passed back in return value 8127 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 8128 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 8129 * 8130 * This may return an error which indicates that BAR2 SGE Queue 8131 * registers aren't available. If an error is not returned, then the 8132 * following values are returned: 8133 * 8134 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 8135 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 8136 * 8137 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 8138 * require the "Inferred Queue ID" ability may be used. E.g. the 8139 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 8140 * then these "Inferred Queue ID" register may not be used. 8141 */ 8142 int t4_bar2_sge_qregs(struct adapter *adapter, 8143 unsigned int qid, 8144 enum t4_bar2_qtype qtype, 8145 int user, 8146 u64 *pbar2_qoffset, 8147 unsigned int *pbar2_qid) 8148 { 8149 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 8150 u64 bar2_page_offset, bar2_qoffset; 8151 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 8152 8153 /* T4 doesn't support BAR2 SGE Queue registers for kernel 8154 * mode queues. 8155 */ 8156 if (!user && is_t4(adapter)) 8157 return -EINVAL; 8158 8159 /* Get our SGE Page Size parameters. 8160 */ 8161 page_shift = adapter->params.sge.page_shift; 8162 page_size = 1 << page_shift; 8163 8164 /* Get the right Queues per Page parameters for our Queue. 8165 */ 8166 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 8167 ? adapter->params.sge.eq_s_qpp 8168 : adapter->params.sge.iq_s_qpp); 8169 qpp_mask = (1 << qpp_shift) - 1; 8170 8171 /* Calculate the basics of the BAR2 SGE Queue register area: 8172 * o The BAR2 page the Queue registers will be in. 8173 * o The BAR2 Queue ID. 8174 * o The BAR2 Queue ID Offset into the BAR2 page. 8175 */ 8176 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 8177 bar2_qid = qid & qpp_mask; 8178 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 8179 8180 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 8181 * hardware will infer the Absolute Queue ID simply from the writes to 8182 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 8183 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 8184 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 8185 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 8186 * from the BAR2 Page and BAR2 Queue ID. 8187 * 8188 * One important censequence of this is that some BAR2 SGE registers 8189 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 8190 * there. But other registers synthesize the SGE Queue ID purely 8191 * from the writes to the registers -- the Write Combined Doorbell 8192 * Buffer is a good example. These BAR2 SGE Registers are only 8193 * available for those BAR2 SGE Register areas where the SGE Absolute 8194 * Queue ID can be inferred from simple writes. 8195 */ 8196 bar2_qoffset = bar2_page_offset; 8197 bar2_qinferred = (bar2_qid_offset < page_size); 8198 if (bar2_qinferred) { 8199 bar2_qoffset += bar2_qid_offset; 8200 bar2_qid = 0; 8201 } 8202 8203 *pbar2_qoffset = bar2_qoffset; 8204 *pbar2_qid = bar2_qid; 8205 return 0; 8206 } 8207 8208 /** 8209 * t4_init_devlog_params - initialize adapter->params.devlog 8210 * @adap: the adapter 8211 * @fw_attach: whether we can talk to the firmware 8212 * 8213 * Initialize various fields of the adapter's Firmware Device Log 8214 * Parameters structure. 8215 */ 8216 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 8217 { 8218 struct devlog_params *dparams = &adap->params.devlog; 8219 u32 pf_dparams; 8220 unsigned int devlog_meminfo; 8221 struct fw_devlog_cmd devlog_cmd; 8222 int ret; 8223 8224 /* If we're dealing with newer firmware, the Device Log Paramerters 8225 * are stored in a designated register which allows us to access the 8226 * Device Log even if we can't talk to the firmware. 8227 */ 8228 pf_dparams = 8229 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 8230 if (pf_dparams) { 8231 unsigned int nentries, nentries128; 8232 8233 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 8234 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 8235 8236 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 8237 nentries = (nentries128 + 1) * 128; 8238 dparams->size = nentries * sizeof(struct fw_devlog_e); 8239 8240 return 0; 8241 } 8242 8243 /* 8244 * For any failing returns ... 8245 */ 8246 memset(dparams, 0, sizeof *dparams); 8247 8248 /* 8249 * If we can't talk to the firmware, there's really nothing we can do 8250 * at this point. 8251 */ 8252 if (!fw_attach) 8253 return -ENXIO; 8254 8255 /* Otherwise, ask the firmware for it's Device Log Parameters. 8256 */ 8257 memset(&devlog_cmd, 0, sizeof devlog_cmd); 8258 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 8259 F_FW_CMD_REQUEST | F_FW_CMD_READ); 8260 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 8261 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 8262 &devlog_cmd); 8263 if (ret) 8264 return ret; 8265 8266 devlog_meminfo = 8267 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 8268 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 8269 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 8270 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 8271 8272 return 0; 8273 } 8274 8275 /** 8276 * t4_init_sge_params - initialize adap->params.sge 8277 * @adapter: the adapter 8278 * 8279 * Initialize various fields of the adapter's SGE Parameters structure. 8280 */ 8281 int t4_init_sge_params(struct adapter *adapter) 8282 { 8283 u32 r; 8284 struct sge_params *sp = &adapter->params.sge; 8285 unsigned i, tscale = 1; 8286 8287 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 8288 sp->counter_val[0] = G_THRESHOLD_0(r); 8289 sp->counter_val[1] = G_THRESHOLD_1(r); 8290 sp->counter_val[2] = G_THRESHOLD_2(r); 8291 sp->counter_val[3] = G_THRESHOLD_3(r); 8292 8293 if (chip_id(adapter) >= CHELSIO_T6) { 8294 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 8295 tscale = G_TSCALE(r); 8296 if (tscale == 0) 8297 tscale = 1; 8298 else 8299 tscale += 2; 8300 } 8301 8302 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 8303 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 8304 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 8305 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 8306 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 8307 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 8308 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 8309 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 8310 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 8311 8312 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 8313 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 8314 if (is_t4(adapter)) 8315 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 8316 else if (is_t5(adapter)) 8317 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 8318 else 8319 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 8320 8321 /* egress queues: log2 of # of doorbells per BAR2 page */ 8322 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 8323 r >>= S_QUEUESPERPAGEPF0 + 8324 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8325 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 8326 8327 /* ingress queues: log2 of # of doorbells per BAR2 page */ 8328 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 8329 r >>= S_QUEUESPERPAGEPF0 + 8330 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8331 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 8332 8333 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 8334 r >>= S_HOSTPAGESIZEPF0 + 8335 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 8336 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 8337 8338 r = t4_read_reg(adapter, A_SGE_CONTROL); 8339 sp->sge_control = r; 8340 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 8341 sp->fl_pktshift = G_PKTSHIFT(r); 8342 if (chip_id(adapter) <= CHELSIO_T5) { 8343 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8344 X_INGPADBOUNDARY_SHIFT); 8345 } else { 8346 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8347 X_T6_INGPADBOUNDARY_SHIFT); 8348 } 8349 if (is_t4(adapter)) 8350 sp->pack_boundary = sp->pad_boundary; 8351 else { 8352 r = t4_read_reg(adapter, A_SGE_CONTROL2); 8353 if (G_INGPACKBOUNDARY(r) == 0) 8354 sp->pack_boundary = 16; 8355 else 8356 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 8357 } 8358 for (i = 0; i < SGE_FLBUF_SIZES; i++) 8359 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 8360 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 8361 8362 return 0; 8363 } 8364 8365 /* 8366 * Read and cache the adapter's compressed filter mode and ingress config. 8367 */ 8368 static void read_filter_mode_and_ingress_config(struct adapter *adap, 8369 bool sleep_ok) 8370 { 8371 struct tp_params *tpp = &adap->params.tp; 8372 8373 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP, 8374 sleep_ok); 8375 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG, 8376 sleep_ok); 8377 8378 /* 8379 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 8380 * shift positions of several elements of the Compressed Filter Tuple 8381 * for this adapter which we need frequently ... 8382 */ 8383 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 8384 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 8385 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 8386 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 8387 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 8388 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 8389 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 8390 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 8391 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 8392 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 8393 8394 /* 8395 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID 8396 * represents the presence of an Outer VLAN instead of a VNIC ID. 8397 */ 8398 if ((tpp->ingress_config & F_VNIC) == 0) 8399 tpp->vnic_shift = -1; 8400 } 8401 8402 /** 8403 * t4_init_tp_params - initialize adap->params.tp 8404 * @adap: the adapter 8405 * 8406 * Initialize various fields of the adapter's TP Parameters structure. 8407 */ 8408 int t4_init_tp_params(struct adapter *adap, bool sleep_ok) 8409 { 8410 int chan; 8411 u32 v; 8412 struct tp_params *tpp = &adap->params.tp; 8413 8414 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 8415 tpp->tre = G_TIMERRESOLUTION(v); 8416 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 8417 8418 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 8419 for (chan = 0; chan < MAX_NCHAN; chan++) 8420 tpp->tx_modq[chan] = chan; 8421 8422 read_filter_mode_and_ingress_config(adap, sleep_ok); 8423 8424 /* 8425 * Cache a mask of the bits that represent the error vector portion of 8426 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room 8427 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE). 8428 */ 8429 tpp->err_vec_mask = htobe16(0xffff); 8430 if (chip_id(adap) > CHELSIO_T5) { 8431 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 8432 if (v & F_CRXPKTENC) { 8433 tpp->err_vec_mask = 8434 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC)); 8435 } 8436 } 8437 8438 return 0; 8439 } 8440 8441 /** 8442 * t4_filter_field_shift - calculate filter field shift 8443 * @adap: the adapter 8444 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 8445 * 8446 * Return the shift position of a filter field within the Compressed 8447 * Filter Tuple. The filter field is specified via its selection bit 8448 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 8449 */ 8450 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 8451 { 8452 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 8453 unsigned int sel; 8454 int field_shift; 8455 8456 if ((filter_mode & filter_sel) == 0) 8457 return -1; 8458 8459 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 8460 switch (filter_mode & sel) { 8461 case F_FCOE: 8462 field_shift += W_FT_FCOE; 8463 break; 8464 case F_PORT: 8465 field_shift += W_FT_PORT; 8466 break; 8467 case F_VNIC_ID: 8468 field_shift += W_FT_VNIC_ID; 8469 break; 8470 case F_VLAN: 8471 field_shift += W_FT_VLAN; 8472 break; 8473 case F_TOS: 8474 field_shift += W_FT_TOS; 8475 break; 8476 case F_PROTOCOL: 8477 field_shift += W_FT_PROTOCOL; 8478 break; 8479 case F_ETHERTYPE: 8480 field_shift += W_FT_ETHERTYPE; 8481 break; 8482 case F_MACMATCH: 8483 field_shift += W_FT_MACMATCH; 8484 break; 8485 case F_MPSHITTYPE: 8486 field_shift += W_FT_MPSHITTYPE; 8487 break; 8488 case F_FRAGMENTATION: 8489 field_shift += W_FT_FRAGMENTATION; 8490 break; 8491 } 8492 } 8493 return field_shift; 8494 } 8495 8496 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 8497 { 8498 u8 addr[6]; 8499 int ret, i, j; 8500 u16 rss_size; 8501 struct port_info *p = adap2pinfo(adap, port_id); 8502 u32 param, val; 8503 8504 for (i = 0, j = -1; i <= p->port_id; i++) { 8505 do { 8506 j++; 8507 } while ((adap->params.portvec & (1 << j)) == 0); 8508 } 8509 8510 if (!(adap->flags & IS_VF) || 8511 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 8512 t4_update_port_info(p); 8513 } 8514 8515 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 8516 if (ret < 0) 8517 return ret; 8518 8519 p->vi[0].viid = ret; 8520 if (chip_id(adap) <= CHELSIO_T5) 8521 p->vi[0].smt_idx = (ret & 0x7f) << 1; 8522 else 8523 p->vi[0].smt_idx = (ret & 0x7f); 8524 p->tx_chan = j; 8525 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 8526 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 8527 p->lport = j; 8528 p->vi[0].rss_size = rss_size; 8529 t4_os_set_hw_addr(p, addr); 8530 8531 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8532 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 8533 V_FW_PARAMS_PARAM_YZ(p->vi[0].viid); 8534 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 8535 if (ret) 8536 p->vi[0].rss_base = 0xffff; 8537 else { 8538 /* MPASS((val >> 16) == rss_size); */ 8539 p->vi[0].rss_base = val & 0xffff; 8540 } 8541 8542 return 0; 8543 } 8544 8545 /** 8546 * t4_read_cimq_cfg - read CIM queue configuration 8547 * @adap: the adapter 8548 * @base: holds the queue base addresses in bytes 8549 * @size: holds the queue sizes in bytes 8550 * @thres: holds the queue full thresholds in bytes 8551 * 8552 * Returns the current configuration of the CIM queues, starting with 8553 * the IBQs, then the OBQs. 8554 */ 8555 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 8556 { 8557 unsigned int i, v; 8558 int cim_num_obq = adap->chip_params->cim_num_obq; 8559 8560 for (i = 0; i < CIM_NUM_IBQ; i++) { 8561 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 8562 V_QUENUMSELECT(i)); 8563 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8564 /* value is in 256-byte units */ 8565 *base++ = G_CIMQBASE(v) * 256; 8566 *size++ = G_CIMQSIZE(v) * 256; 8567 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 8568 } 8569 for (i = 0; i < cim_num_obq; i++) { 8570 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8571 V_QUENUMSELECT(i)); 8572 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8573 /* value is in 256-byte units */ 8574 *base++ = G_CIMQBASE(v) * 256; 8575 *size++ = G_CIMQSIZE(v) * 256; 8576 } 8577 } 8578 8579 /** 8580 * t4_read_cim_ibq - read the contents of a CIM inbound queue 8581 * @adap: the adapter 8582 * @qid: the queue index 8583 * @data: where to store the queue contents 8584 * @n: capacity of @data in 32-bit words 8585 * 8586 * Reads the contents of the selected CIM queue starting at address 0 up 8587 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8588 * error and the number of 32-bit words actually read on success. 8589 */ 8590 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8591 { 8592 int i, err, attempts; 8593 unsigned int addr; 8594 const unsigned int nwords = CIM_IBQ_SIZE * 4; 8595 8596 if (qid > 5 || (n & 3)) 8597 return -EINVAL; 8598 8599 addr = qid * nwords; 8600 if (n > nwords) 8601 n = nwords; 8602 8603 /* It might take 3-10ms before the IBQ debug read access is allowed. 8604 * Wait for 1 Sec with a delay of 1 usec. 8605 */ 8606 attempts = 1000000; 8607 8608 for (i = 0; i < n; i++, addr++) { 8609 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 8610 F_IBQDBGEN); 8611 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 8612 attempts, 1); 8613 if (err) 8614 return err; 8615 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 8616 } 8617 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 8618 return i; 8619 } 8620 8621 /** 8622 * t4_read_cim_obq - read the contents of a CIM outbound queue 8623 * @adap: the adapter 8624 * @qid: the queue index 8625 * @data: where to store the queue contents 8626 * @n: capacity of @data in 32-bit words 8627 * 8628 * Reads the contents of the selected CIM queue starting at address 0 up 8629 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8630 * error and the number of 32-bit words actually read on success. 8631 */ 8632 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8633 { 8634 int i, err; 8635 unsigned int addr, v, nwords; 8636 int cim_num_obq = adap->chip_params->cim_num_obq; 8637 8638 if ((qid > (cim_num_obq - 1)) || (n & 3)) 8639 return -EINVAL; 8640 8641 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8642 V_QUENUMSELECT(qid)); 8643 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8644 8645 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 8646 nwords = G_CIMQSIZE(v) * 64; /* same */ 8647 if (n > nwords) 8648 n = nwords; 8649 8650 for (i = 0; i < n; i++, addr++) { 8651 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 8652 F_OBQDBGEN); 8653 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 8654 2, 1); 8655 if (err) 8656 return err; 8657 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 8658 } 8659 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 8660 return i; 8661 } 8662 8663 enum { 8664 CIM_QCTL_BASE = 0, 8665 CIM_CTL_BASE = 0x2000, 8666 CIM_PBT_ADDR_BASE = 0x2800, 8667 CIM_PBT_LRF_BASE = 0x3000, 8668 CIM_PBT_DATA_BASE = 0x3800 8669 }; 8670 8671 /** 8672 * t4_cim_read - read a block from CIM internal address space 8673 * @adap: the adapter 8674 * @addr: the start address within the CIM address space 8675 * @n: number of words to read 8676 * @valp: where to store the result 8677 * 8678 * Reads a block of 4-byte words from the CIM intenal address space. 8679 */ 8680 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 8681 unsigned int *valp) 8682 { 8683 int ret = 0; 8684 8685 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8686 return -EBUSY; 8687 8688 for ( ; !ret && n--; addr += 4) { 8689 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 8690 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8691 0, 5, 2); 8692 if (!ret) 8693 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 8694 } 8695 return ret; 8696 } 8697 8698 /** 8699 * t4_cim_write - write a block into CIM internal address space 8700 * @adap: the adapter 8701 * @addr: the start address within the CIM address space 8702 * @n: number of words to write 8703 * @valp: set of values to write 8704 * 8705 * Writes a block of 4-byte words into the CIM intenal address space. 8706 */ 8707 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 8708 const unsigned int *valp) 8709 { 8710 int ret = 0; 8711 8712 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8713 return -EBUSY; 8714 8715 for ( ; !ret && n--; addr += 4) { 8716 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 8717 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 8718 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8719 0, 5, 2); 8720 } 8721 return ret; 8722 } 8723 8724 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 8725 unsigned int val) 8726 { 8727 return t4_cim_write(adap, addr, 1, &val); 8728 } 8729 8730 /** 8731 * t4_cim_ctl_read - read a block from CIM control region 8732 * @adap: the adapter 8733 * @addr: the start address within the CIM control region 8734 * @n: number of words to read 8735 * @valp: where to store the result 8736 * 8737 * Reads a block of 4-byte words from the CIM control region. 8738 */ 8739 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 8740 unsigned int *valp) 8741 { 8742 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 8743 } 8744 8745 /** 8746 * t4_cim_read_la - read CIM LA capture buffer 8747 * @adap: the adapter 8748 * @la_buf: where to store the LA data 8749 * @wrptr: the HW write pointer within the capture buffer 8750 * 8751 * Reads the contents of the CIM LA buffer with the most recent entry at 8752 * the end of the returned data and with the entry at @wrptr first. 8753 * We try to leave the LA in the running state we find it in. 8754 */ 8755 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 8756 { 8757 int i, ret; 8758 unsigned int cfg, val, idx; 8759 8760 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 8761 if (ret) 8762 return ret; 8763 8764 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 8765 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 8766 if (ret) 8767 return ret; 8768 } 8769 8770 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 8771 if (ret) 8772 goto restart; 8773 8774 idx = G_UPDBGLAWRPTR(val); 8775 if (wrptr) 8776 *wrptr = idx; 8777 8778 for (i = 0; i < adap->params.cim_la_size; i++) { 8779 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 8780 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 8781 if (ret) 8782 break; 8783 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 8784 if (ret) 8785 break; 8786 if (val & F_UPDBGLARDEN) { 8787 ret = -ETIMEDOUT; 8788 break; 8789 } 8790 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 8791 if (ret) 8792 break; 8793 8794 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */ 8795 idx = (idx + 1) & M_UPDBGLARDPTR; 8796 /* 8797 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 8798 * identify the 32-bit portion of the full 312-bit data 8799 */ 8800 if (is_t6(adap)) 8801 while ((idx & 0xf) > 9) 8802 idx = (idx + 1) % M_UPDBGLARDPTR; 8803 } 8804 restart: 8805 if (cfg & F_UPDBGLAEN) { 8806 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 8807 cfg & ~F_UPDBGLARDEN); 8808 if (!ret) 8809 ret = r; 8810 } 8811 return ret; 8812 } 8813 8814 /** 8815 * t4_tp_read_la - read TP LA capture buffer 8816 * @adap: the adapter 8817 * @la_buf: where to store the LA data 8818 * @wrptr: the HW write pointer within the capture buffer 8819 * 8820 * Reads the contents of the TP LA buffer with the most recent entry at 8821 * the end of the returned data and with the entry at @wrptr first. 8822 * We leave the LA in the running state we find it in. 8823 */ 8824 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 8825 { 8826 bool last_incomplete; 8827 unsigned int i, cfg, val, idx; 8828 8829 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 8830 if (cfg & F_DBGLAENABLE) /* freeze LA */ 8831 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 8832 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 8833 8834 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 8835 idx = G_DBGLAWPTR(val); 8836 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 8837 if (last_incomplete) 8838 idx = (idx + 1) & M_DBGLARPTR; 8839 if (wrptr) 8840 *wrptr = idx; 8841 8842 val &= 0xffff; 8843 val &= ~V_DBGLARPTR(M_DBGLARPTR); 8844 val |= adap->params.tp.la_mask; 8845 8846 for (i = 0; i < TPLA_SIZE; i++) { 8847 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 8848 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 8849 idx = (idx + 1) & M_DBGLARPTR; 8850 } 8851 8852 /* Wipe out last entry if it isn't valid */ 8853 if (last_incomplete) 8854 la_buf[TPLA_SIZE - 1] = ~0ULL; 8855 8856 if (cfg & F_DBGLAENABLE) /* restore running state */ 8857 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 8858 cfg | adap->params.tp.la_mask); 8859 } 8860 8861 /* 8862 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 8863 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 8864 * state for more than the Warning Threshold then we'll issue a warning about 8865 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 8866 * appears to be hung every Warning Repeat second till the situation clears. 8867 * If the situation clears, we'll note that as well. 8868 */ 8869 #define SGE_IDMA_WARN_THRESH 1 8870 #define SGE_IDMA_WARN_REPEAT 300 8871 8872 /** 8873 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 8874 * @adapter: the adapter 8875 * @idma: the adapter IDMA Monitor state 8876 * 8877 * Initialize the state of an SGE Ingress DMA Monitor. 8878 */ 8879 void t4_idma_monitor_init(struct adapter *adapter, 8880 struct sge_idma_monitor_state *idma) 8881 { 8882 /* Initialize the state variables for detecting an SGE Ingress DMA 8883 * hang. The SGE has internal counters which count up on each clock 8884 * tick whenever the SGE finds its Ingress DMA State Engines in the 8885 * same state they were on the previous clock tick. The clock used is 8886 * the Core Clock so we have a limit on the maximum "time" they can 8887 * record; typically a very small number of seconds. For instance, 8888 * with a 600MHz Core Clock, we can only count up to a bit more than 8889 * 7s. So we'll synthesize a larger counter in order to not run the 8890 * risk of having the "timers" overflow and give us the flexibility to 8891 * maintain a Hung SGE State Machine of our own which operates across 8892 * a longer time frame. 8893 */ 8894 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 8895 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 8896 } 8897 8898 /** 8899 * t4_idma_monitor - monitor SGE Ingress DMA state 8900 * @adapter: the adapter 8901 * @idma: the adapter IDMA Monitor state 8902 * @hz: number of ticks/second 8903 * @ticks: number of ticks since the last IDMA Monitor call 8904 */ 8905 void t4_idma_monitor(struct adapter *adapter, 8906 struct sge_idma_monitor_state *idma, 8907 int hz, int ticks) 8908 { 8909 int i, idma_same_state_cnt[2]; 8910 8911 /* Read the SGE Debug Ingress DMA Same State Count registers. These 8912 * are counters inside the SGE which count up on each clock when the 8913 * SGE finds its Ingress DMA State Engines in the same states they 8914 * were in the previous clock. The counters will peg out at 8915 * 0xffffffff without wrapping around so once they pass the 1s 8916 * threshold they'll stay above that till the IDMA state changes. 8917 */ 8918 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 8919 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 8920 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8921 8922 for (i = 0; i < 2; i++) { 8923 u32 debug0, debug11; 8924 8925 /* If the Ingress DMA Same State Counter ("timer") is less 8926 * than 1s, then we can reset our synthesized Stall Timer and 8927 * continue. If we have previously emitted warnings about a 8928 * potential stalled Ingress Queue, issue a note indicating 8929 * that the Ingress Queue has resumed forward progress. 8930 */ 8931 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 8932 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 8933 CH_WARN(adapter, "SGE idma%d, queue %u, " 8934 "resumed after %d seconds\n", 8935 i, idma->idma_qid[i], 8936 idma->idma_stalled[i]/hz); 8937 idma->idma_stalled[i] = 0; 8938 continue; 8939 } 8940 8941 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 8942 * domain. The first time we get here it'll be because we 8943 * passed the 1s Threshold; each additional time it'll be 8944 * because the RX Timer Callback is being fired on its regular 8945 * schedule. 8946 * 8947 * If the stall is below our Potential Hung Ingress Queue 8948 * Warning Threshold, continue. 8949 */ 8950 if (idma->idma_stalled[i] == 0) { 8951 idma->idma_stalled[i] = hz; 8952 idma->idma_warn[i] = 0; 8953 } else { 8954 idma->idma_stalled[i] += ticks; 8955 idma->idma_warn[i] -= ticks; 8956 } 8957 8958 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 8959 continue; 8960 8961 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 8962 */ 8963 if (idma->idma_warn[i] > 0) 8964 continue; 8965 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 8966 8967 /* Read and save the SGE IDMA State and Queue ID information. 8968 * We do this every time in case it changes across time ... 8969 * can't be too careful ... 8970 */ 8971 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 8972 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8973 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 8974 8975 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 8976 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8977 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 8978 8979 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 8980 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 8981 i, idma->idma_qid[i], idma->idma_state[i], 8982 idma->idma_stalled[i]/hz, 8983 debug0, debug11); 8984 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 8985 } 8986 } 8987 8988 /** 8989 * t4_read_pace_tbl - read the pace table 8990 * @adap: the adapter 8991 * @pace_vals: holds the returned values 8992 * 8993 * Returns the values of TP's pace table in microseconds. 8994 */ 8995 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 8996 { 8997 unsigned int i, v; 8998 8999 for (i = 0; i < NTX_SCHED; i++) { 9000 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 9001 v = t4_read_reg(adap, A_TP_PACE_TABLE); 9002 pace_vals[i] = dack_ticks_to_usec(adap, v); 9003 } 9004 } 9005 9006 /** 9007 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 9008 * @adap: the adapter 9009 * @sched: the scheduler index 9010 * @kbps: the byte rate in Kbps 9011 * @ipg: the interpacket delay in tenths of nanoseconds 9012 * 9013 * Return the current configuration of a HW Tx scheduler. 9014 */ 9015 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 9016 unsigned int *ipg, bool sleep_ok) 9017 { 9018 unsigned int v, addr, bpt, cpt; 9019 9020 if (kbps) { 9021 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 9022 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9023 if (sched & 1) 9024 v >>= 16; 9025 bpt = (v >> 8) & 0xff; 9026 cpt = v & 0xff; 9027 if (!cpt) 9028 *kbps = 0; /* scheduler disabled */ 9029 else { 9030 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 9031 *kbps = (v * bpt) / 125; 9032 } 9033 } 9034 if (ipg) { 9035 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 9036 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9037 if (sched & 1) 9038 v >>= 16; 9039 v &= 0xffff; 9040 *ipg = (10000 * v) / core_ticks_per_usec(adap); 9041 } 9042 } 9043 9044 /** 9045 * t4_load_cfg - download config file 9046 * @adap: the adapter 9047 * @cfg_data: the cfg text file to write 9048 * @size: text file size 9049 * 9050 * Write the supplied config text file to the card's serial flash. 9051 */ 9052 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 9053 { 9054 int ret, i, n, cfg_addr; 9055 unsigned int addr; 9056 unsigned int flash_cfg_start_sec; 9057 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9058 9059 cfg_addr = t4_flash_cfg_addr(adap); 9060 if (cfg_addr < 0) 9061 return cfg_addr; 9062 9063 addr = cfg_addr; 9064 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9065 9066 if (size > FLASH_CFG_MAX_SIZE) { 9067 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 9068 FLASH_CFG_MAX_SIZE); 9069 return -EFBIG; 9070 } 9071 9072 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 9073 sf_sec_size); 9074 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9075 flash_cfg_start_sec + i - 1); 9076 /* 9077 * If size == 0 then we're simply erasing the FLASH sectors associated 9078 * with the on-adapter Firmware Configuration File. 9079 */ 9080 if (ret || size == 0) 9081 goto out; 9082 9083 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9084 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9085 if ( (size - i) < SF_PAGE_SIZE) 9086 n = size - i; 9087 else 9088 n = SF_PAGE_SIZE; 9089 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 9090 if (ret) 9091 goto out; 9092 9093 addr += SF_PAGE_SIZE; 9094 cfg_data += SF_PAGE_SIZE; 9095 } 9096 9097 out: 9098 if (ret) 9099 CH_ERR(adap, "config file %s failed %d\n", 9100 (size == 0 ? "clear" : "download"), ret); 9101 return ret; 9102 } 9103 9104 /** 9105 * t5_fw_init_extern_mem - initialize the external memory 9106 * @adap: the adapter 9107 * 9108 * Initializes the external memory on T5. 9109 */ 9110 int t5_fw_init_extern_mem(struct adapter *adap) 9111 { 9112 u32 params[1], val[1]; 9113 int ret; 9114 9115 if (!is_t5(adap)) 9116 return 0; 9117 9118 val[0] = 0xff; /* Initialize all MCs */ 9119 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9120 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 9121 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 9122 FW_CMD_MAX_TIMEOUT); 9123 9124 return ret; 9125 } 9126 9127 /* BIOS boot headers */ 9128 typedef struct pci_expansion_rom_header { 9129 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9130 u8 reserved[22]; /* Reserved per processor Architecture data */ 9131 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9132 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 9133 9134 /* Legacy PCI Expansion ROM Header */ 9135 typedef struct legacy_pci_expansion_rom_header { 9136 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9137 u8 size512; /* Current Image Size in units of 512 bytes */ 9138 u8 initentry_point[4]; 9139 u8 cksum; /* Checksum computed on the entire Image */ 9140 u8 reserved[16]; /* Reserved */ 9141 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 9142 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 9143 9144 /* EFI PCI Expansion ROM Header */ 9145 typedef struct efi_pci_expansion_rom_header { 9146 u8 signature[2]; // ROM signature. The value 0xaa55 9147 u8 initialization_size[2]; /* Units 512. Includes this header */ 9148 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 9149 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 9150 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 9151 u8 compression_type[2]; /* Compression type. */ 9152 /* 9153 * Compression type definition 9154 * 0x0: uncompressed 9155 * 0x1: Compressed 9156 * 0x2-0xFFFF: Reserved 9157 */ 9158 u8 reserved[8]; /* Reserved */ 9159 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 9160 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9161 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 9162 9163 /* PCI Data Structure Format */ 9164 typedef struct pcir_data_structure { /* PCI Data Structure */ 9165 u8 signature[4]; /* Signature. The string "PCIR" */ 9166 u8 vendor_id[2]; /* Vendor Identification */ 9167 u8 device_id[2]; /* Device Identification */ 9168 u8 vital_product[2]; /* Pointer to Vital Product Data */ 9169 u8 length[2]; /* PCIR Data Structure Length */ 9170 u8 revision; /* PCIR Data Structure Revision */ 9171 u8 class_code[3]; /* Class Code */ 9172 u8 image_length[2]; /* Image Length. Multiple of 512B */ 9173 u8 code_revision[2]; /* Revision Level of Code/Data */ 9174 u8 code_type; /* Code Type. */ 9175 /* 9176 * PCI Expansion ROM Code Types 9177 * 0x00: Intel IA-32, PC-AT compatible. Legacy 9178 * 0x01: Open Firmware standard for PCI. FCODE 9179 * 0x02: Hewlett-Packard PA RISC. HP reserved 9180 * 0x03: EFI Image. EFI 9181 * 0x04-0xFF: Reserved. 9182 */ 9183 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 9184 u8 reserved[2]; /* Reserved */ 9185 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 9186 9187 /* BOOT constants */ 9188 enum { 9189 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 9190 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 9191 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 9192 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 9193 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 9194 VENDOR_ID = 0x1425, /* Vendor ID */ 9195 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 9196 }; 9197 9198 /* 9199 * modify_device_id - Modifies the device ID of the Boot BIOS image 9200 * @adatper: the device ID to write. 9201 * @boot_data: the boot image to modify. 9202 * 9203 * Write the supplied device ID to the boot BIOS image. 9204 */ 9205 static void modify_device_id(int device_id, u8 *boot_data) 9206 { 9207 legacy_pci_exp_rom_header_t *header; 9208 pcir_data_t *pcir_header; 9209 u32 cur_header = 0; 9210 9211 /* 9212 * Loop through all chained images and change the device ID's 9213 */ 9214 while (1) { 9215 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 9216 pcir_header = (pcir_data_t *) &boot_data[cur_header + 9217 le16_to_cpu(*(u16*)header->pcir_offset)]; 9218 9219 /* 9220 * Only modify the Device ID if code type is Legacy or HP. 9221 * 0x00: Okay to modify 9222 * 0x01: FCODE. Do not be modify 9223 * 0x03: Okay to modify 9224 * 0x04-0xFF: Do not modify 9225 */ 9226 if (pcir_header->code_type == 0x00) { 9227 u8 csum = 0; 9228 int i; 9229 9230 /* 9231 * Modify Device ID to match current adatper 9232 */ 9233 *(u16*) pcir_header->device_id = device_id; 9234 9235 /* 9236 * Set checksum temporarily to 0. 9237 * We will recalculate it later. 9238 */ 9239 header->cksum = 0x0; 9240 9241 /* 9242 * Calculate and update checksum 9243 */ 9244 for (i = 0; i < (header->size512 * 512); i++) 9245 csum += (u8)boot_data[cur_header + i]; 9246 9247 /* 9248 * Invert summed value to create the checksum 9249 * Writing new checksum value directly to the boot data 9250 */ 9251 boot_data[cur_header + 7] = -csum; 9252 9253 } else if (pcir_header->code_type == 0x03) { 9254 9255 /* 9256 * Modify Device ID to match current adatper 9257 */ 9258 *(u16*) pcir_header->device_id = device_id; 9259 9260 } 9261 9262 9263 /* 9264 * Check indicator element to identify if this is the last 9265 * image in the ROM. 9266 */ 9267 if (pcir_header->indicator & 0x80) 9268 break; 9269 9270 /* 9271 * Move header pointer up to the next image in the ROM. 9272 */ 9273 cur_header += header->size512 * 512; 9274 } 9275 } 9276 9277 /* 9278 * t4_load_boot - download boot flash 9279 * @adapter: the adapter 9280 * @boot_data: the boot image to write 9281 * @boot_addr: offset in flash to write boot_data 9282 * @size: image size 9283 * 9284 * Write the supplied boot image to the card's serial flash. 9285 * The boot image has the following sections: a 28-byte header and the 9286 * boot image. 9287 */ 9288 int t4_load_boot(struct adapter *adap, u8 *boot_data, 9289 unsigned int boot_addr, unsigned int size) 9290 { 9291 pci_exp_rom_header_t *header; 9292 int pcir_offset ; 9293 pcir_data_t *pcir_header; 9294 int ret, addr; 9295 uint16_t device_id; 9296 unsigned int i; 9297 unsigned int boot_sector = (boot_addr * 1024 ); 9298 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9299 9300 /* 9301 * Make sure the boot image does not encroach on the firmware region 9302 */ 9303 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 9304 CH_ERR(adap, "boot image encroaching on firmware region\n"); 9305 return -EFBIG; 9306 } 9307 9308 /* 9309 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 9310 * and Boot configuration data sections. These 3 boot sections span 9311 * sectors 0 to 7 in flash and live right before the FW image location. 9312 */ 9313 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 9314 sf_sec_size); 9315 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 9316 (boot_sector >> 16) + i - 1); 9317 9318 /* 9319 * If size == 0 then we're simply erasing the FLASH sectors associated 9320 * with the on-adapter option ROM file 9321 */ 9322 if (ret || (size == 0)) 9323 goto out; 9324 9325 /* Get boot header */ 9326 header = (pci_exp_rom_header_t *)boot_data; 9327 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 9328 /* PCIR Data Structure */ 9329 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 9330 9331 /* 9332 * Perform some primitive sanity testing to avoid accidentally 9333 * writing garbage over the boot sectors. We ought to check for 9334 * more but it's not worth it for now ... 9335 */ 9336 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 9337 CH_ERR(adap, "boot image too small/large\n"); 9338 return -EFBIG; 9339 } 9340 9341 #ifndef CHELSIO_T4_DIAGS 9342 /* 9343 * Check BOOT ROM header signature 9344 */ 9345 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 9346 CH_ERR(adap, "Boot image missing signature\n"); 9347 return -EINVAL; 9348 } 9349 9350 /* 9351 * Check PCI header signature 9352 */ 9353 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 9354 CH_ERR(adap, "PCI header missing signature\n"); 9355 return -EINVAL; 9356 } 9357 9358 /* 9359 * Check Vendor ID matches Chelsio ID 9360 */ 9361 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 9362 CH_ERR(adap, "Vendor ID missing signature\n"); 9363 return -EINVAL; 9364 } 9365 #endif 9366 9367 /* 9368 * Retrieve adapter's device ID 9369 */ 9370 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 9371 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 9372 device_id = device_id & 0xf0ff; 9373 9374 /* 9375 * Check PCIE Device ID 9376 */ 9377 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 9378 /* 9379 * Change the device ID in the Boot BIOS image to match 9380 * the Device ID of the current adapter. 9381 */ 9382 modify_device_id(device_id, boot_data); 9383 } 9384 9385 /* 9386 * Skip over the first SF_PAGE_SIZE worth of data and write it after 9387 * we finish copying the rest of the boot image. This will ensure 9388 * that the BIOS boot header will only be written if the boot image 9389 * was written in full. 9390 */ 9391 addr = boot_sector; 9392 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 9393 addr += SF_PAGE_SIZE; 9394 boot_data += SF_PAGE_SIZE; 9395 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 9396 if (ret) 9397 goto out; 9398 } 9399 9400 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 9401 (const u8 *)header, 0); 9402 9403 out: 9404 if (ret) 9405 CH_ERR(adap, "boot image download failed, error %d\n", ret); 9406 return ret; 9407 } 9408 9409 /* 9410 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 9411 * @adapter: the adapter 9412 * 9413 * Return the address within the flash where the OptionROM Configuration 9414 * is stored, or an error if the device FLASH is too small to contain 9415 * a OptionROM Configuration. 9416 */ 9417 static int t4_flash_bootcfg_addr(struct adapter *adapter) 9418 { 9419 /* 9420 * If the device FLASH isn't large enough to hold a Firmware 9421 * Configuration File, return an error. 9422 */ 9423 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 9424 return -ENOSPC; 9425 9426 return FLASH_BOOTCFG_START; 9427 } 9428 9429 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 9430 { 9431 int ret, i, n, cfg_addr; 9432 unsigned int addr; 9433 unsigned int flash_cfg_start_sec; 9434 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9435 9436 cfg_addr = t4_flash_bootcfg_addr(adap); 9437 if (cfg_addr < 0) 9438 return cfg_addr; 9439 9440 addr = cfg_addr; 9441 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9442 9443 if (size > FLASH_BOOTCFG_MAX_SIZE) { 9444 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 9445 FLASH_BOOTCFG_MAX_SIZE); 9446 return -EFBIG; 9447 } 9448 9449 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 9450 sf_sec_size); 9451 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9452 flash_cfg_start_sec + i - 1); 9453 9454 /* 9455 * If size == 0 then we're simply erasing the FLASH sectors associated 9456 * with the on-adapter OptionROM Configuration File. 9457 */ 9458 if (ret || size == 0) 9459 goto out; 9460 9461 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9462 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9463 if ( (size - i) < SF_PAGE_SIZE) 9464 n = size - i; 9465 else 9466 n = SF_PAGE_SIZE; 9467 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 9468 if (ret) 9469 goto out; 9470 9471 addr += SF_PAGE_SIZE; 9472 cfg_data += SF_PAGE_SIZE; 9473 } 9474 9475 out: 9476 if (ret) 9477 CH_ERR(adap, "boot config data %s failed %d\n", 9478 (size == 0 ? "clear" : "download"), ret); 9479 return ret; 9480 } 9481 9482 /** 9483 * t4_set_filter_mode - configure the optional components of filter tuples 9484 * @adap: the adapter 9485 * @mode_map: a bitmap selcting which optional filter components to enable 9486 * @sleep_ok: if true we may sleep while awaiting command completion 9487 * 9488 * Sets the filter mode by selecting the optional components to enable 9489 * in filter tuples. Returns 0 on success and a negative error if the 9490 * requested mode needs more bits than are available for optional 9491 * components. 9492 */ 9493 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 9494 bool sleep_ok) 9495 { 9496 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 9497 9498 int i, nbits = 0; 9499 9500 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 9501 if (mode_map & (1 << i)) 9502 nbits += width[i]; 9503 if (nbits > FILTER_OPT_LEN) 9504 return -EINVAL; 9505 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok); 9506 read_filter_mode_and_ingress_config(adap, sleep_ok); 9507 9508 return 0; 9509 } 9510 9511 /** 9512 * t4_clr_port_stats - clear port statistics 9513 * @adap: the adapter 9514 * @idx: the port index 9515 * 9516 * Clear HW statistics for the given port. 9517 */ 9518 void t4_clr_port_stats(struct adapter *adap, int idx) 9519 { 9520 unsigned int i; 9521 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 9522 u32 port_base_addr; 9523 9524 if (is_t4(adap)) 9525 port_base_addr = PORT_BASE(idx); 9526 else 9527 port_base_addr = T5_PORT_BASE(idx); 9528 9529 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 9530 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 9531 t4_write_reg(adap, port_base_addr + i, 0); 9532 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 9533 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 9534 t4_write_reg(adap, port_base_addr + i, 0); 9535 for (i = 0; i < 4; i++) 9536 if (bgmap & (1 << i)) { 9537 t4_write_reg(adap, 9538 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 9539 t4_write_reg(adap, 9540 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 9541 } 9542 } 9543 9544 /** 9545 * t4_i2c_rd - read I2C data from adapter 9546 * @adap: the adapter 9547 * @port: Port number if per-port device; <0 if not 9548 * @devid: per-port device ID or absolute device ID 9549 * @offset: byte offset into device I2C space 9550 * @len: byte length of I2C space data 9551 * @buf: buffer in which to return I2C data 9552 * 9553 * Reads the I2C data from the indicated device and location. 9554 */ 9555 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 9556 int port, unsigned int devid, 9557 unsigned int offset, unsigned int len, 9558 u8 *buf) 9559 { 9560 u32 ldst_addrspace; 9561 struct fw_ldst_cmd ldst; 9562 int ret; 9563 9564 if (port >= 4 || 9565 devid >= 256 || 9566 offset >= 256 || 9567 len > sizeof ldst.u.i2c.data) 9568 return -EINVAL; 9569 9570 memset(&ldst, 0, sizeof ldst); 9571 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9572 ldst.op_to_addrspace = 9573 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9574 F_FW_CMD_REQUEST | 9575 F_FW_CMD_READ | 9576 ldst_addrspace); 9577 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9578 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9579 ldst.u.i2c.did = devid; 9580 ldst.u.i2c.boffset = offset; 9581 ldst.u.i2c.blen = len; 9582 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9583 if (!ret) 9584 memcpy(buf, ldst.u.i2c.data, len); 9585 return ret; 9586 } 9587 9588 /** 9589 * t4_i2c_wr - write I2C data to adapter 9590 * @adap: the adapter 9591 * @port: Port number if per-port device; <0 if not 9592 * @devid: per-port device ID or absolute device ID 9593 * @offset: byte offset into device I2C space 9594 * @len: byte length of I2C space data 9595 * @buf: buffer containing new I2C data 9596 * 9597 * Write the I2C data to the indicated device and location. 9598 */ 9599 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 9600 int port, unsigned int devid, 9601 unsigned int offset, unsigned int len, 9602 u8 *buf) 9603 { 9604 u32 ldst_addrspace; 9605 struct fw_ldst_cmd ldst; 9606 9607 if (port >= 4 || 9608 devid >= 256 || 9609 offset >= 256 || 9610 len > sizeof ldst.u.i2c.data) 9611 return -EINVAL; 9612 9613 memset(&ldst, 0, sizeof ldst); 9614 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9615 ldst.op_to_addrspace = 9616 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9617 F_FW_CMD_REQUEST | 9618 F_FW_CMD_WRITE | 9619 ldst_addrspace); 9620 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9621 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9622 ldst.u.i2c.did = devid; 9623 ldst.u.i2c.boffset = offset; 9624 ldst.u.i2c.blen = len; 9625 memcpy(ldst.u.i2c.data, buf, len); 9626 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9627 } 9628 9629 /** 9630 * t4_sge_ctxt_rd - read an SGE context through FW 9631 * @adap: the adapter 9632 * @mbox: mailbox to use for the FW command 9633 * @cid: the context id 9634 * @ctype: the context type 9635 * @data: where to store the context data 9636 * 9637 * Issues a FW command through the given mailbox to read an SGE context. 9638 */ 9639 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 9640 enum ctxt_type ctype, u32 *data) 9641 { 9642 int ret; 9643 struct fw_ldst_cmd c; 9644 9645 if (ctype == CTXT_EGRESS) 9646 ret = FW_LDST_ADDRSPC_SGE_EGRC; 9647 else if (ctype == CTXT_INGRESS) 9648 ret = FW_LDST_ADDRSPC_SGE_INGC; 9649 else if (ctype == CTXT_FLM) 9650 ret = FW_LDST_ADDRSPC_SGE_FLMC; 9651 else 9652 ret = FW_LDST_ADDRSPC_SGE_CONMC; 9653 9654 memset(&c, 0, sizeof(c)); 9655 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9656 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9657 V_FW_LDST_CMD_ADDRSPACE(ret)); 9658 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 9659 c.u.idctxt.physid = cpu_to_be32(cid); 9660 9661 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 9662 if (ret == 0) { 9663 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 9664 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 9665 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 9666 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 9667 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 9668 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 9669 } 9670 return ret; 9671 } 9672 9673 /** 9674 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 9675 * @adap: the adapter 9676 * @cid: the context id 9677 * @ctype: the context type 9678 * @data: where to store the context data 9679 * 9680 * Reads an SGE context directly, bypassing FW. This is only for 9681 * debugging when FW is unavailable. 9682 */ 9683 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 9684 u32 *data) 9685 { 9686 int i, ret; 9687 9688 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 9689 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 9690 if (!ret) 9691 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 9692 *data++ = t4_read_reg(adap, i); 9693 return ret; 9694 } 9695 9696 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 9697 int sleep_ok) 9698 { 9699 struct fw_sched_cmd cmd; 9700 9701 memset(&cmd, 0, sizeof(cmd)); 9702 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9703 F_FW_CMD_REQUEST | 9704 F_FW_CMD_WRITE); 9705 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9706 9707 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 9708 cmd.u.config.type = type; 9709 cmd.u.config.minmaxen = minmaxen; 9710 9711 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9712 NULL, sleep_ok); 9713 } 9714 9715 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 9716 int rateunit, int ratemode, int channel, int cl, 9717 int minrate, int maxrate, int weight, int pktsize, 9718 int sleep_ok) 9719 { 9720 struct fw_sched_cmd cmd; 9721 9722 memset(&cmd, 0, sizeof(cmd)); 9723 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9724 F_FW_CMD_REQUEST | 9725 F_FW_CMD_WRITE); 9726 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9727 9728 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9729 cmd.u.params.type = type; 9730 cmd.u.params.level = level; 9731 cmd.u.params.mode = mode; 9732 cmd.u.params.ch = channel; 9733 cmd.u.params.cl = cl; 9734 cmd.u.params.unit = rateunit; 9735 cmd.u.params.rate = ratemode; 9736 cmd.u.params.min = cpu_to_be32(minrate); 9737 cmd.u.params.max = cpu_to_be32(maxrate); 9738 cmd.u.params.weight = cpu_to_be16(weight); 9739 cmd.u.params.pktsize = cpu_to_be16(pktsize); 9740 9741 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9742 NULL, sleep_ok); 9743 } 9744 9745 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 9746 unsigned int maxrate, int sleep_ok) 9747 { 9748 struct fw_sched_cmd cmd; 9749 9750 memset(&cmd, 0, sizeof(cmd)); 9751 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9752 F_FW_CMD_REQUEST | 9753 F_FW_CMD_WRITE); 9754 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9755 9756 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9757 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 9758 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 9759 cmd.u.params.ch = channel; 9760 cmd.u.params.rate = ratemode; /* REL or ABS */ 9761 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 9762 9763 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9764 NULL, sleep_ok); 9765 } 9766 9767 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 9768 int weight, int sleep_ok) 9769 { 9770 struct fw_sched_cmd cmd; 9771 9772 if (weight < 0 || weight > 100) 9773 return -EINVAL; 9774 9775 memset(&cmd, 0, sizeof(cmd)); 9776 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9777 F_FW_CMD_REQUEST | 9778 F_FW_CMD_WRITE); 9779 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9780 9781 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9782 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 9783 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 9784 cmd.u.params.ch = channel; 9785 cmd.u.params.cl = cl; 9786 cmd.u.params.weight = cpu_to_be16(weight); 9787 9788 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9789 NULL, sleep_ok); 9790 } 9791 9792 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 9793 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 9794 { 9795 struct fw_sched_cmd cmd; 9796 9797 memset(&cmd, 0, sizeof(cmd)); 9798 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9799 F_FW_CMD_REQUEST | 9800 F_FW_CMD_WRITE); 9801 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9802 9803 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9804 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 9805 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 9806 cmd.u.params.mode = mode; 9807 cmd.u.params.ch = channel; 9808 cmd.u.params.cl = cl; 9809 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 9810 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 9811 cmd.u.params.max = cpu_to_be32(maxrate); 9812 cmd.u.params.pktsize = cpu_to_be16(pktsize); 9813 9814 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9815 NULL, sleep_ok); 9816 } 9817 9818 /* 9819 * t4_config_watchdog - configure (enable/disable) a watchdog timer 9820 * @adapter: the adapter 9821 * @mbox: mailbox to use for the FW command 9822 * @pf: the PF owning the queue 9823 * @vf: the VF owning the queue 9824 * @timeout: watchdog timeout in ms 9825 * @action: watchdog timer / action 9826 * 9827 * There are separate watchdog timers for each possible watchdog 9828 * action. Configure one of the watchdog timers by setting a non-zero 9829 * timeout. Disable a watchdog timer by using a timeout of zero. 9830 */ 9831 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 9832 unsigned int pf, unsigned int vf, 9833 unsigned int timeout, unsigned int action) 9834 { 9835 struct fw_watchdog_cmd wdog; 9836 unsigned int ticks; 9837 9838 /* 9839 * The watchdog command expects a timeout in units of 10ms so we need 9840 * to convert it here (via rounding) and force a minimum of one 10ms 9841 * "tick" if the timeout is non-zero but the conversion results in 0 9842 * ticks. 9843 */ 9844 ticks = (timeout + 5)/10; 9845 if (timeout && !ticks) 9846 ticks = 1; 9847 9848 memset(&wdog, 0, sizeof wdog); 9849 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 9850 F_FW_CMD_REQUEST | 9851 F_FW_CMD_WRITE | 9852 V_FW_PARAMS_CMD_PFN(pf) | 9853 V_FW_PARAMS_CMD_VFN(vf)); 9854 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 9855 wdog.timeout = cpu_to_be32(ticks); 9856 wdog.action = cpu_to_be32(action); 9857 9858 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 9859 } 9860 9861 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 9862 { 9863 struct fw_devlog_cmd devlog_cmd; 9864 int ret; 9865 9866 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 9867 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9868 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9869 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9870 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 9871 sizeof(devlog_cmd), &devlog_cmd); 9872 if (ret) 9873 return ret; 9874 9875 *level = devlog_cmd.level; 9876 return 0; 9877 } 9878 9879 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 9880 { 9881 struct fw_devlog_cmd devlog_cmd; 9882 9883 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 9884 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9885 F_FW_CMD_REQUEST | 9886 F_FW_CMD_WRITE); 9887 devlog_cmd.level = level; 9888 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9889 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 9890 sizeof(devlog_cmd), &devlog_cmd); 9891 } 9892