1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 adap->flags &= ~FW_OK; 216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 218 if (pcie_fw != 0xffffffff) 219 t4_os_dump_devlog(adap); 220 } 221 } 222 223 /* 224 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 225 */ 226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 227 u32 mbox_addr) 228 { 229 for ( ; nflit; nflit--, mbox_addr += 8) 230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 231 } 232 233 /* 234 * Handle a FW assertion reported in a mailbox. 235 */ 236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 237 { 238 CH_ALERT(adap, 239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 240 asrt->u.assert.filename_0_7, 241 be32_to_cpu(asrt->u.assert.line), 242 be32_to_cpu(asrt->u.assert.x), 243 be32_to_cpu(asrt->u.assert.y)); 244 } 245 246 struct port_tx_state { 247 uint64_t rx_pause; 248 uint64_t tx_frames; 249 }; 250 251 static void 252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 253 { 254 uint32_t rx_pause_reg, tx_frames_reg; 255 256 if (is_t4(sc)) { 257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 259 } else { 260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 262 } 263 264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 266 } 267 268 static void 269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 270 { 271 int i; 272 273 for_each_port(sc, i) 274 read_tx_state_one(sc, i, &tx_state[i]); 275 } 276 277 static void 278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 279 { 280 uint32_t port_ctl_reg; 281 uint64_t tx_frames, rx_pause; 282 int i; 283 284 for_each_port(sc, i) { 285 rx_pause = tx_state[i].rx_pause; 286 tx_frames = tx_state[i].tx_frames; 287 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 288 289 if (is_t4(sc)) 290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 291 else 292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 294 rx_pause != tx_state[i].rx_pause && 295 tx_frames == tx_state[i].tx_frames) { 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 297 mdelay(1); 298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 299 } 300 } 301 } 302 303 #define X_CIM_PF_NOACCESS 0xeeeeeeee 304 /** 305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 306 * @adap: the adapter 307 * @mbox: index of the mailbox to use 308 * @cmd: the command to write 309 * @size: command length in bytes 310 * @rpl: where to optionally store the reply 311 * @sleep_ok: if true we may sleep while awaiting command completion 312 * @timeout: time to wait for command to finish before timing out 313 * (negative implies @sleep_ok=false) 314 * 315 * Sends the given command to FW through the selected mailbox and waits 316 * for the FW to execute the command. If @rpl is not %NULL it is used to 317 * store the FW's reply to the command. The command and its optional 318 * reply are of the same length. Some FW commands like RESET and 319 * INITIALIZE can take a considerable amount of time to execute. 320 * @sleep_ok determines whether we may sleep while awaiting the response. 321 * If sleeping is allowed we use progressive backoff otherwise we spin. 322 * Note that passing in a negative @timeout is an alternate mechanism 323 * for specifying @sleep_ok=false. This is useful when a higher level 324 * interface allows for specification of @timeout but not @sleep_ok ... 325 * 326 * The return value is 0 on success or a negative errno on failure. A 327 * failure can happen either because we are not able to execute the 328 * command or FW executes it but signals an error. In the latter case 329 * the return value is the error code indicated by FW (negated). 330 */ 331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 332 int size, void *rpl, bool sleep_ok, int timeout) 333 { 334 /* 335 * We delay in small increments at first in an effort to maintain 336 * responsiveness for simple, fast executing commands but then back 337 * off to larger delays to a maximum retry delay. 338 */ 339 static const int delay[] = { 340 1, 1, 3, 5, 10, 10, 20, 50, 100 341 }; 342 u32 v; 343 u64 res; 344 int i, ms, delay_idx, ret, next_tx_check; 345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 347 u32 ctl; 348 __be64 cmd_rpl[MBOX_LEN/8]; 349 u32 pcie_fw; 350 struct port_tx_state tx_state[MAX_NPORTS]; 351 352 if (adap->flags & CHK_MBOX_ACCESS) 353 ASSERT_SYNCHRONIZED_OP(adap); 354 355 if (size <= 0 || (size & 15) || size > MBOX_LEN) 356 return -EINVAL; 357 358 if (adap->flags & IS_VF) { 359 if (is_t6(adap)) 360 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 361 else 362 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 364 } 365 366 /* 367 * If we have a negative timeout, that implies that we can't sleep. 368 */ 369 if (timeout < 0) { 370 sleep_ok = false; 371 timeout = -timeout; 372 } 373 374 /* 375 * Attempt to gain access to the mailbox. 376 */ 377 for (i = 0; i < 4; i++) { 378 ctl = t4_read_reg(adap, ctl_reg); 379 v = G_MBOWNER(ctl); 380 if (v != X_MBOWNER_NONE) 381 break; 382 } 383 384 /* 385 * If we were unable to gain access, report the error to our caller. 386 */ 387 if (v != X_MBOWNER_PL) { 388 t4_report_fw_error(adap); 389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 390 return ret; 391 } 392 393 /* 394 * If we gain ownership of the mailbox and there's a "valid" message 395 * in it, this is likely an asynchronous error message from the 396 * firmware. So we'll report that and then proceed on with attempting 397 * to issue our own command ... which may well fail if the error 398 * presaged the firmware crashing ... 399 */ 400 if (ctl & F_MBMSGVALID) { 401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 402 } 403 404 /* 405 * Copy in the new mailbox command and send it on its way ... 406 */ 407 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 408 memcpy(cmd_rpl, cmd, size); 409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 412 413 if (adap->flags & IS_VF) { 414 /* 415 * For the VFs, the Mailbox Data "registers" are 416 * actually backed by T4's "MA" interface rather than 417 * PL Registers (as is the case for the PFs). Because 418 * these are in different coherency domains, the write 419 * to the VF's PL-register-backed Mailbox Control can 420 * race in front of the writes to the MA-backed VF 421 * Mailbox Data "registers". So we need to do a 422 * read-back on at least one byte of the VF Mailbox 423 * Data registers before doing the write to the VF 424 * Mailbox Control register. 425 */ 426 t4_read_reg(adap, data_reg); 427 } 428 429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 431 next_tx_check = 1000; 432 delay_idx = 0; 433 ms = delay[0]; 434 435 /* 436 * Loop waiting for the reply; bail out if we time out or the firmware 437 * reports an error. 438 */ 439 pcie_fw = 0; 440 for (i = 0; i < timeout; i += ms) { 441 if (!(adap->flags & IS_VF)) { 442 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 443 if (pcie_fw & F_PCIE_FW_ERR) 444 break; 445 } 446 447 if (i >= next_tx_check) { 448 check_tx_state(adap, &tx_state[0]); 449 next_tx_check = i + 1000; 450 } 451 452 if (sleep_ok) { 453 ms = delay[delay_idx]; /* last element may repeat */ 454 if (delay_idx < ARRAY_SIZE(delay) - 1) 455 delay_idx++; 456 msleep(ms); 457 } else { 458 mdelay(ms); 459 } 460 461 v = t4_read_reg(adap, ctl_reg); 462 if (v == X_CIM_PF_NOACCESS) 463 continue; 464 if (G_MBOWNER(v) == X_MBOWNER_PL) { 465 if (!(v & F_MBMSGVALID)) { 466 t4_write_reg(adap, ctl_reg, 467 V_MBOWNER(X_MBOWNER_NONE)); 468 continue; 469 } 470 471 /* 472 * Retrieve the command reply and release the mailbox. 473 */ 474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 477 478 res = be64_to_cpu(cmd_rpl[0]); 479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 481 res = V_FW_CMD_RETVAL(EIO); 482 } else if (rpl) 483 memcpy(rpl, cmd_rpl, size); 484 return -G_FW_CMD_RETVAL((int)res); 485 } 486 } 487 488 /* 489 * We timed out waiting for a reply to our mailbox command. Report 490 * the error and also check to see if the firmware reported any 491 * errors ... 492 */ 493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 494 *(const u8 *)cmd, mbox, pcie_fw); 495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 497 498 if (pcie_fw & F_PCIE_FW_ERR) { 499 ret = -ENXIO; 500 t4_report_fw_error(adap); 501 } else { 502 ret = -ETIMEDOUT; 503 t4_os_dump_devlog(adap); 504 } 505 506 t4_fatal_err(adap, true); 507 return ret; 508 } 509 510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 511 void *rpl, bool sleep_ok) 512 { 513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 514 sleep_ok, FW_CMD_MAX_TIMEOUT); 515 516 } 517 518 static int t4_edc_err_read(struct adapter *adap, int idx) 519 { 520 u32 edc_ecc_err_addr_reg; 521 u32 edc_bist_status_rdata_reg; 522 523 if (is_t4(adap)) { 524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 525 return 0; 526 } 527 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 529 return 0; 530 } 531 532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 534 535 CH_WARN(adap, 536 "edc%d err addr 0x%x: 0x%x.\n", 537 idx, edc_ecc_err_addr_reg, 538 t4_read_reg(adap, edc_ecc_err_addr_reg)); 539 CH_WARN(adap, 540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 541 edc_bist_status_rdata_reg, 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 551 552 return 0; 553 } 554 555 /** 556 * t4_mc_read - read from MC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which MC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568 { 569 int i; 570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 572 573 if (is_t4(adap)) { 574 mc_bist_cmd_reg = A_MC_BIST_CMD; 575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 579 } else { 580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 584 idx); 585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 586 idx); 587 } 588 589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 590 return -EBUSY; 591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 595 F_START_BIST | V_BIST_CMD_GAP(1)); 596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 597 if (i) 598 return i; 599 600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 601 602 for (i = 15; i >= 0; i--) 603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 604 if (ecc) 605 *ecc = t4_read_reg64(adap, MC_DATA(16)); 606 #undef MC_DATA 607 return 0; 608 } 609 610 /** 611 * t4_edc_read - read from EDC through backdoor accesses 612 * @adap: the adapter 613 * @idx: which EDC to access 614 * @addr: address of first byte requested 615 * @data: 64 bytes of data containing the requested address 616 * @ecc: where to store the corresponding 64-bit ECC word 617 * 618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 619 * that covers the requested address @addr. If @parity is not %NULL it 620 * is assigned the 64-bit ECC word for the read data. 621 */ 622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 623 { 624 int i; 625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 627 628 if (is_t4(adap)) { 629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 633 idx); 634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 635 idx); 636 } else { 637 /* 638 * These macro are missing in t4_regs.h file. 639 * Added temporarily for testing. 640 */ 641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 649 idx); 650 #undef EDC_REG_T5 651 #undef EDC_STRIDE_T5 652 } 653 654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 655 return -EBUSY; 656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 659 t4_write_reg(adap, edc_bist_cmd_reg, 660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 662 if (i) 663 return i; 664 665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 666 667 for (i = 15; i >= 0; i--) 668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 669 if (ecc) 670 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 671 #undef EDC_DATA 672 return 0; 673 } 674 675 /** 676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 677 * @adap: the adapter 678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 679 * @addr: address within indicated memory type 680 * @len: amount of memory to read 681 * @buf: host memory buffer 682 * 683 * Reads an [almost] arbitrary memory region in the firmware: the 684 * firmware memory address, length and host buffer must be aligned on 685 * 32-bit boudaries. The memory is returned as a raw byte sequence from 686 * the firmware's memory. If this memory contains data structures which 687 * contain multi-byte integers, it's the callers responsibility to 688 * perform appropriate byte order conversions. 689 */ 690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 691 __be32 *buf) 692 { 693 u32 pos, start, end, offset; 694 int ret; 695 696 /* 697 * Argument sanity checks ... 698 */ 699 if ((addr & 0x3) || (len & 0x3)) 700 return -EINVAL; 701 702 /* 703 * The underlaying EDC/MC read routines read 64 bytes at a time so we 704 * need to round down the start and round up the end. We'll start 705 * copying out of the first line at (addr - start) a word at a time. 706 */ 707 start = rounddown2(addr, 64); 708 end = roundup2(addr + len, 64); 709 offset = (addr - start)/sizeof(__be32); 710 711 for (pos = start; pos < end; pos += 64, offset = 0) { 712 __be32 data[16]; 713 714 /* 715 * Read the chip's memory block and bail if there's an error. 716 */ 717 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 719 else 720 ret = t4_edc_read(adap, mtype, pos, data, NULL); 721 if (ret) 722 return ret; 723 724 /* 725 * Copy the data into the caller's memory buffer. 726 */ 727 while (offset < 16 && len > 0) { 728 *buf++ = data[offset++]; 729 len -= sizeof(__be32); 730 } 731 } 732 733 return 0; 734 } 735 736 /* 737 * Return the specified PCI-E Configuration Space register from our Physical 738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 739 * since we prefer to let the firmware own all of these registers, but if that 740 * fails we go for it directly ourselves. 741 */ 742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 743 { 744 745 /* 746 * If fw_attach != 0, construct and send the Firmware LDST Command to 747 * retrieve the specified PCI-E Configuration Space register. 748 */ 749 if (drv_fw_attach != 0) { 750 struct fw_ldst_cmd ldst_cmd; 751 int ret; 752 753 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 754 ldst_cmd.op_to_addrspace = 755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 756 F_FW_CMD_REQUEST | 757 F_FW_CMD_READ | 758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 761 ldst_cmd.u.pcie.ctrl_to_fn = 762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 763 ldst_cmd.u.pcie.r = reg; 764 765 /* 766 * If the LDST Command succeeds, return the result, otherwise 767 * fall through to reading it directly ourselves ... 768 */ 769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 770 &ldst_cmd); 771 if (ret == 0) 772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 773 774 CH_WARN(adap, "Firmware failed to return " 775 "Configuration Space register %d, err = %d\n", 776 reg, -ret); 777 } 778 779 /* 780 * Read the desired Configuration Space register via the PCI-E 781 * Backdoor mechanism. 782 */ 783 return t4_hw_pci_read_cfg4(adap, reg); 784 } 785 786 /** 787 * t4_get_regs_len - return the size of the chips register set 788 * @adapter: the adapter 789 * 790 * Returns the size of the chip's BAR0 register space. 791 */ 792 unsigned int t4_get_regs_len(struct adapter *adapter) 793 { 794 unsigned int chip_version = chip_id(adapter); 795 796 switch (chip_version) { 797 case CHELSIO_T4: 798 if (adapter->flags & IS_VF) 799 return FW_T4VF_REGMAP_SIZE; 800 return T4_REGMAP_SIZE; 801 802 case CHELSIO_T5: 803 case CHELSIO_T6: 804 if (adapter->flags & IS_VF) 805 return FW_T4VF_REGMAP_SIZE; 806 return T5_REGMAP_SIZE; 807 } 808 809 CH_ERR(adapter, 810 "Unsupported chip version %d\n", chip_version); 811 return 0; 812 } 813 814 /** 815 * t4_get_regs - read chip registers into provided buffer 816 * @adap: the adapter 817 * @buf: register buffer 818 * @buf_size: size (in bytes) of register buffer 819 * 820 * If the provided register buffer isn't large enough for the chip's 821 * full register range, the register dump will be truncated to the 822 * register buffer's size. 823 */ 824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 825 { 826 static const unsigned int t4_reg_ranges[] = { 827 0x1008, 0x1108, 828 0x1180, 0x1184, 829 0x1190, 0x1194, 830 0x11a0, 0x11a4, 831 0x11b0, 0x11b4, 832 0x11fc, 0x123c, 833 0x1300, 0x173c, 834 0x1800, 0x18fc, 835 0x3000, 0x30d8, 836 0x30e0, 0x30e4, 837 0x30ec, 0x5910, 838 0x5920, 0x5924, 839 0x5960, 0x5960, 840 0x5968, 0x5968, 841 0x5970, 0x5970, 842 0x5978, 0x5978, 843 0x5980, 0x5980, 844 0x5988, 0x5988, 845 0x5990, 0x5990, 846 0x5998, 0x5998, 847 0x59a0, 0x59d4, 848 0x5a00, 0x5ae0, 849 0x5ae8, 0x5ae8, 850 0x5af0, 0x5af0, 851 0x5af8, 0x5af8, 852 0x6000, 0x6098, 853 0x6100, 0x6150, 854 0x6200, 0x6208, 855 0x6240, 0x6248, 856 0x6280, 0x62b0, 857 0x62c0, 0x6338, 858 0x6370, 0x638c, 859 0x6400, 0x643c, 860 0x6500, 0x6524, 861 0x6a00, 0x6a04, 862 0x6a14, 0x6a38, 863 0x6a60, 0x6a70, 864 0x6a78, 0x6a78, 865 0x6b00, 0x6b0c, 866 0x6b1c, 0x6b84, 867 0x6bf0, 0x6bf8, 868 0x6c00, 0x6c0c, 869 0x6c1c, 0x6c84, 870 0x6cf0, 0x6cf8, 871 0x6d00, 0x6d0c, 872 0x6d1c, 0x6d84, 873 0x6df0, 0x6df8, 874 0x6e00, 0x6e0c, 875 0x6e1c, 0x6e84, 876 0x6ef0, 0x6ef8, 877 0x6f00, 0x6f0c, 878 0x6f1c, 0x6f84, 879 0x6ff0, 0x6ff8, 880 0x7000, 0x700c, 881 0x701c, 0x7084, 882 0x70f0, 0x70f8, 883 0x7100, 0x710c, 884 0x711c, 0x7184, 885 0x71f0, 0x71f8, 886 0x7200, 0x720c, 887 0x721c, 0x7284, 888 0x72f0, 0x72f8, 889 0x7300, 0x730c, 890 0x731c, 0x7384, 891 0x73f0, 0x73f8, 892 0x7400, 0x7450, 893 0x7500, 0x7530, 894 0x7600, 0x760c, 895 0x7614, 0x761c, 896 0x7680, 0x76cc, 897 0x7700, 0x7798, 898 0x77c0, 0x77fc, 899 0x7900, 0x79fc, 900 0x7b00, 0x7b58, 901 0x7b60, 0x7b84, 902 0x7b8c, 0x7c38, 903 0x7d00, 0x7d38, 904 0x7d40, 0x7d80, 905 0x7d8c, 0x7ddc, 906 0x7de4, 0x7e04, 907 0x7e10, 0x7e1c, 908 0x7e24, 0x7e38, 909 0x7e40, 0x7e44, 910 0x7e4c, 0x7e78, 911 0x7e80, 0x7ea4, 912 0x7eac, 0x7edc, 913 0x7ee8, 0x7efc, 914 0x8dc0, 0x8e04, 915 0x8e10, 0x8e1c, 916 0x8e30, 0x8e78, 917 0x8ea0, 0x8eb8, 918 0x8ec0, 0x8f6c, 919 0x8fc0, 0x9008, 920 0x9010, 0x9058, 921 0x9060, 0x9060, 922 0x9068, 0x9074, 923 0x90fc, 0x90fc, 924 0x9400, 0x9408, 925 0x9410, 0x9458, 926 0x9600, 0x9600, 927 0x9608, 0x9638, 928 0x9640, 0x96bc, 929 0x9800, 0x9808, 930 0x9820, 0x983c, 931 0x9850, 0x9864, 932 0x9c00, 0x9c6c, 933 0x9c80, 0x9cec, 934 0x9d00, 0x9d6c, 935 0x9d80, 0x9dec, 936 0x9e00, 0x9e6c, 937 0x9e80, 0x9eec, 938 0x9f00, 0x9f6c, 939 0x9f80, 0x9fec, 940 0xd004, 0xd004, 941 0xd010, 0xd03c, 942 0xdfc0, 0xdfe0, 943 0xe000, 0xea7c, 944 0xf000, 0x11110, 945 0x11118, 0x11190, 946 0x19040, 0x1906c, 947 0x19078, 0x19080, 948 0x1908c, 0x190e4, 949 0x190f0, 0x190f8, 950 0x19100, 0x19110, 951 0x19120, 0x19124, 952 0x19150, 0x19194, 953 0x1919c, 0x191b0, 954 0x191d0, 0x191e8, 955 0x19238, 0x1924c, 956 0x193f8, 0x1943c, 957 0x1944c, 0x19474, 958 0x19490, 0x194e0, 959 0x194f0, 0x194f8, 960 0x19800, 0x19c08, 961 0x19c10, 0x19c90, 962 0x19ca0, 0x19ce4, 963 0x19cf0, 0x19d40, 964 0x19d50, 0x19d94, 965 0x19da0, 0x19de8, 966 0x19df0, 0x19e40, 967 0x19e50, 0x19e90, 968 0x19ea0, 0x19f4c, 969 0x1a000, 0x1a004, 970 0x1a010, 0x1a06c, 971 0x1a0b0, 0x1a0e4, 972 0x1a0ec, 0x1a0f4, 973 0x1a100, 0x1a108, 974 0x1a114, 0x1a120, 975 0x1a128, 0x1a130, 976 0x1a138, 0x1a138, 977 0x1a190, 0x1a1c4, 978 0x1a1fc, 0x1a1fc, 979 0x1e040, 0x1e04c, 980 0x1e284, 0x1e28c, 981 0x1e2c0, 0x1e2c0, 982 0x1e2e0, 0x1e2e0, 983 0x1e300, 0x1e384, 984 0x1e3c0, 0x1e3c8, 985 0x1e440, 0x1e44c, 986 0x1e684, 0x1e68c, 987 0x1e6c0, 0x1e6c0, 988 0x1e6e0, 0x1e6e0, 989 0x1e700, 0x1e784, 990 0x1e7c0, 0x1e7c8, 991 0x1e840, 0x1e84c, 992 0x1ea84, 0x1ea8c, 993 0x1eac0, 0x1eac0, 994 0x1eae0, 0x1eae0, 995 0x1eb00, 0x1eb84, 996 0x1ebc0, 0x1ebc8, 997 0x1ec40, 0x1ec4c, 998 0x1ee84, 0x1ee8c, 999 0x1eec0, 0x1eec0, 1000 0x1eee0, 0x1eee0, 1001 0x1ef00, 0x1ef84, 1002 0x1efc0, 0x1efc8, 1003 0x1f040, 0x1f04c, 1004 0x1f284, 0x1f28c, 1005 0x1f2c0, 0x1f2c0, 1006 0x1f2e0, 0x1f2e0, 1007 0x1f300, 0x1f384, 1008 0x1f3c0, 0x1f3c8, 1009 0x1f440, 0x1f44c, 1010 0x1f684, 0x1f68c, 1011 0x1f6c0, 0x1f6c0, 1012 0x1f6e0, 0x1f6e0, 1013 0x1f700, 0x1f784, 1014 0x1f7c0, 0x1f7c8, 1015 0x1f840, 0x1f84c, 1016 0x1fa84, 0x1fa8c, 1017 0x1fac0, 0x1fac0, 1018 0x1fae0, 0x1fae0, 1019 0x1fb00, 0x1fb84, 1020 0x1fbc0, 0x1fbc8, 1021 0x1fc40, 0x1fc4c, 1022 0x1fe84, 0x1fe8c, 1023 0x1fec0, 0x1fec0, 1024 0x1fee0, 0x1fee0, 1025 0x1ff00, 0x1ff84, 1026 0x1ffc0, 0x1ffc8, 1027 0x20000, 0x2002c, 1028 0x20100, 0x2013c, 1029 0x20190, 0x201a0, 1030 0x201a8, 0x201b8, 1031 0x201c4, 0x201c8, 1032 0x20200, 0x20318, 1033 0x20400, 0x204b4, 1034 0x204c0, 0x20528, 1035 0x20540, 0x20614, 1036 0x21000, 0x21040, 1037 0x2104c, 0x21060, 1038 0x210c0, 0x210ec, 1039 0x21200, 0x21268, 1040 0x21270, 0x21284, 1041 0x212fc, 0x21388, 1042 0x21400, 0x21404, 1043 0x21500, 0x21500, 1044 0x21510, 0x21518, 1045 0x2152c, 0x21530, 1046 0x2153c, 0x2153c, 1047 0x21550, 0x21554, 1048 0x21600, 0x21600, 1049 0x21608, 0x2161c, 1050 0x21624, 0x21628, 1051 0x21630, 0x21634, 1052 0x2163c, 0x2163c, 1053 0x21700, 0x2171c, 1054 0x21780, 0x2178c, 1055 0x21800, 0x21818, 1056 0x21820, 0x21828, 1057 0x21830, 0x21848, 1058 0x21850, 0x21854, 1059 0x21860, 0x21868, 1060 0x21870, 0x21870, 1061 0x21878, 0x21898, 1062 0x218a0, 0x218a8, 1063 0x218b0, 0x218c8, 1064 0x218d0, 0x218d4, 1065 0x218e0, 0x218e8, 1066 0x218f0, 0x218f0, 1067 0x218f8, 0x21a18, 1068 0x21a20, 0x21a28, 1069 0x21a30, 0x21a48, 1070 0x21a50, 0x21a54, 1071 0x21a60, 0x21a68, 1072 0x21a70, 0x21a70, 1073 0x21a78, 0x21a98, 1074 0x21aa0, 0x21aa8, 1075 0x21ab0, 0x21ac8, 1076 0x21ad0, 0x21ad4, 1077 0x21ae0, 0x21ae8, 1078 0x21af0, 0x21af0, 1079 0x21af8, 0x21c18, 1080 0x21c20, 0x21c20, 1081 0x21c28, 0x21c30, 1082 0x21c38, 0x21c38, 1083 0x21c80, 0x21c98, 1084 0x21ca0, 0x21ca8, 1085 0x21cb0, 0x21cc8, 1086 0x21cd0, 0x21cd4, 1087 0x21ce0, 0x21ce8, 1088 0x21cf0, 0x21cf0, 1089 0x21cf8, 0x21d7c, 1090 0x21e00, 0x21e04, 1091 0x22000, 0x2202c, 1092 0x22100, 0x2213c, 1093 0x22190, 0x221a0, 1094 0x221a8, 0x221b8, 1095 0x221c4, 0x221c8, 1096 0x22200, 0x22318, 1097 0x22400, 0x224b4, 1098 0x224c0, 0x22528, 1099 0x22540, 0x22614, 1100 0x23000, 0x23040, 1101 0x2304c, 0x23060, 1102 0x230c0, 0x230ec, 1103 0x23200, 0x23268, 1104 0x23270, 0x23284, 1105 0x232fc, 0x23388, 1106 0x23400, 0x23404, 1107 0x23500, 0x23500, 1108 0x23510, 0x23518, 1109 0x2352c, 0x23530, 1110 0x2353c, 0x2353c, 1111 0x23550, 0x23554, 1112 0x23600, 0x23600, 1113 0x23608, 0x2361c, 1114 0x23624, 0x23628, 1115 0x23630, 0x23634, 1116 0x2363c, 0x2363c, 1117 0x23700, 0x2371c, 1118 0x23780, 0x2378c, 1119 0x23800, 0x23818, 1120 0x23820, 0x23828, 1121 0x23830, 0x23848, 1122 0x23850, 0x23854, 1123 0x23860, 0x23868, 1124 0x23870, 0x23870, 1125 0x23878, 0x23898, 1126 0x238a0, 0x238a8, 1127 0x238b0, 0x238c8, 1128 0x238d0, 0x238d4, 1129 0x238e0, 0x238e8, 1130 0x238f0, 0x238f0, 1131 0x238f8, 0x23a18, 1132 0x23a20, 0x23a28, 1133 0x23a30, 0x23a48, 1134 0x23a50, 0x23a54, 1135 0x23a60, 0x23a68, 1136 0x23a70, 0x23a70, 1137 0x23a78, 0x23a98, 1138 0x23aa0, 0x23aa8, 1139 0x23ab0, 0x23ac8, 1140 0x23ad0, 0x23ad4, 1141 0x23ae0, 0x23ae8, 1142 0x23af0, 0x23af0, 1143 0x23af8, 0x23c18, 1144 0x23c20, 0x23c20, 1145 0x23c28, 0x23c30, 1146 0x23c38, 0x23c38, 1147 0x23c80, 0x23c98, 1148 0x23ca0, 0x23ca8, 1149 0x23cb0, 0x23cc8, 1150 0x23cd0, 0x23cd4, 1151 0x23ce0, 0x23ce8, 1152 0x23cf0, 0x23cf0, 1153 0x23cf8, 0x23d7c, 1154 0x23e00, 0x23e04, 1155 0x24000, 0x2402c, 1156 0x24100, 0x2413c, 1157 0x24190, 0x241a0, 1158 0x241a8, 0x241b8, 1159 0x241c4, 0x241c8, 1160 0x24200, 0x24318, 1161 0x24400, 0x244b4, 1162 0x244c0, 0x24528, 1163 0x24540, 0x24614, 1164 0x25000, 0x25040, 1165 0x2504c, 0x25060, 1166 0x250c0, 0x250ec, 1167 0x25200, 0x25268, 1168 0x25270, 0x25284, 1169 0x252fc, 0x25388, 1170 0x25400, 0x25404, 1171 0x25500, 0x25500, 1172 0x25510, 0x25518, 1173 0x2552c, 0x25530, 1174 0x2553c, 0x2553c, 1175 0x25550, 0x25554, 1176 0x25600, 0x25600, 1177 0x25608, 0x2561c, 1178 0x25624, 0x25628, 1179 0x25630, 0x25634, 1180 0x2563c, 0x2563c, 1181 0x25700, 0x2571c, 1182 0x25780, 0x2578c, 1183 0x25800, 0x25818, 1184 0x25820, 0x25828, 1185 0x25830, 0x25848, 1186 0x25850, 0x25854, 1187 0x25860, 0x25868, 1188 0x25870, 0x25870, 1189 0x25878, 0x25898, 1190 0x258a0, 0x258a8, 1191 0x258b0, 0x258c8, 1192 0x258d0, 0x258d4, 1193 0x258e0, 0x258e8, 1194 0x258f0, 0x258f0, 1195 0x258f8, 0x25a18, 1196 0x25a20, 0x25a28, 1197 0x25a30, 0x25a48, 1198 0x25a50, 0x25a54, 1199 0x25a60, 0x25a68, 1200 0x25a70, 0x25a70, 1201 0x25a78, 0x25a98, 1202 0x25aa0, 0x25aa8, 1203 0x25ab0, 0x25ac8, 1204 0x25ad0, 0x25ad4, 1205 0x25ae0, 0x25ae8, 1206 0x25af0, 0x25af0, 1207 0x25af8, 0x25c18, 1208 0x25c20, 0x25c20, 1209 0x25c28, 0x25c30, 1210 0x25c38, 0x25c38, 1211 0x25c80, 0x25c98, 1212 0x25ca0, 0x25ca8, 1213 0x25cb0, 0x25cc8, 1214 0x25cd0, 0x25cd4, 1215 0x25ce0, 0x25ce8, 1216 0x25cf0, 0x25cf0, 1217 0x25cf8, 0x25d7c, 1218 0x25e00, 0x25e04, 1219 0x26000, 0x2602c, 1220 0x26100, 0x2613c, 1221 0x26190, 0x261a0, 1222 0x261a8, 0x261b8, 1223 0x261c4, 0x261c8, 1224 0x26200, 0x26318, 1225 0x26400, 0x264b4, 1226 0x264c0, 0x26528, 1227 0x26540, 0x26614, 1228 0x27000, 0x27040, 1229 0x2704c, 0x27060, 1230 0x270c0, 0x270ec, 1231 0x27200, 0x27268, 1232 0x27270, 0x27284, 1233 0x272fc, 0x27388, 1234 0x27400, 0x27404, 1235 0x27500, 0x27500, 1236 0x27510, 0x27518, 1237 0x2752c, 0x27530, 1238 0x2753c, 0x2753c, 1239 0x27550, 0x27554, 1240 0x27600, 0x27600, 1241 0x27608, 0x2761c, 1242 0x27624, 0x27628, 1243 0x27630, 0x27634, 1244 0x2763c, 0x2763c, 1245 0x27700, 0x2771c, 1246 0x27780, 0x2778c, 1247 0x27800, 0x27818, 1248 0x27820, 0x27828, 1249 0x27830, 0x27848, 1250 0x27850, 0x27854, 1251 0x27860, 0x27868, 1252 0x27870, 0x27870, 1253 0x27878, 0x27898, 1254 0x278a0, 0x278a8, 1255 0x278b0, 0x278c8, 1256 0x278d0, 0x278d4, 1257 0x278e0, 0x278e8, 1258 0x278f0, 0x278f0, 1259 0x278f8, 0x27a18, 1260 0x27a20, 0x27a28, 1261 0x27a30, 0x27a48, 1262 0x27a50, 0x27a54, 1263 0x27a60, 0x27a68, 1264 0x27a70, 0x27a70, 1265 0x27a78, 0x27a98, 1266 0x27aa0, 0x27aa8, 1267 0x27ab0, 0x27ac8, 1268 0x27ad0, 0x27ad4, 1269 0x27ae0, 0x27ae8, 1270 0x27af0, 0x27af0, 1271 0x27af8, 0x27c18, 1272 0x27c20, 0x27c20, 1273 0x27c28, 0x27c30, 1274 0x27c38, 0x27c38, 1275 0x27c80, 0x27c98, 1276 0x27ca0, 0x27ca8, 1277 0x27cb0, 0x27cc8, 1278 0x27cd0, 0x27cd4, 1279 0x27ce0, 0x27ce8, 1280 0x27cf0, 0x27cf0, 1281 0x27cf8, 0x27d7c, 1282 0x27e00, 0x27e04, 1283 }; 1284 1285 static const unsigned int t4vf_reg_ranges[] = { 1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1287 VF_MPS_REG(A_MPS_VF_CTL), 1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1292 FW_T4VF_MBDATA_BASE_ADDR, 1293 FW_T4VF_MBDATA_BASE_ADDR + 1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1295 }; 1296 1297 static const unsigned int t5_reg_ranges[] = { 1298 0x1008, 0x10c0, 1299 0x10cc, 0x10f8, 1300 0x1100, 0x1100, 1301 0x110c, 0x1148, 1302 0x1180, 0x1184, 1303 0x1190, 0x1194, 1304 0x11a0, 0x11a4, 1305 0x11b0, 0x11b4, 1306 0x11fc, 0x123c, 1307 0x1280, 0x173c, 1308 0x1800, 0x18fc, 1309 0x3000, 0x3028, 1310 0x3060, 0x30b0, 1311 0x30b8, 0x30d8, 1312 0x30e0, 0x30fc, 1313 0x3140, 0x357c, 1314 0x35a8, 0x35cc, 1315 0x35ec, 0x35ec, 1316 0x3600, 0x5624, 1317 0x56cc, 0x56ec, 1318 0x56f4, 0x5720, 1319 0x5728, 0x575c, 1320 0x580c, 0x5814, 1321 0x5890, 0x589c, 1322 0x58a4, 0x58ac, 1323 0x58b8, 0x58bc, 1324 0x5940, 0x59c8, 1325 0x59d0, 0x59dc, 1326 0x59fc, 0x5a18, 1327 0x5a60, 0x5a70, 1328 0x5a80, 0x5a9c, 1329 0x5b94, 0x5bfc, 1330 0x6000, 0x6020, 1331 0x6028, 0x6040, 1332 0x6058, 0x609c, 1333 0x60a8, 0x614c, 1334 0x7700, 0x7798, 1335 0x77c0, 0x78fc, 1336 0x7b00, 0x7b58, 1337 0x7b60, 0x7b84, 1338 0x7b8c, 0x7c54, 1339 0x7d00, 0x7d38, 1340 0x7d40, 0x7d80, 1341 0x7d8c, 0x7ddc, 1342 0x7de4, 0x7e04, 1343 0x7e10, 0x7e1c, 1344 0x7e24, 0x7e38, 1345 0x7e40, 0x7e44, 1346 0x7e4c, 0x7e78, 1347 0x7e80, 0x7edc, 1348 0x7ee8, 0x7efc, 1349 0x8dc0, 0x8de0, 1350 0x8df8, 0x8e04, 1351 0x8e10, 0x8e84, 1352 0x8ea0, 0x8f84, 1353 0x8fc0, 0x9058, 1354 0x9060, 0x9060, 1355 0x9068, 0x90f8, 1356 0x9400, 0x9408, 1357 0x9410, 0x9470, 1358 0x9600, 0x9600, 1359 0x9608, 0x9638, 1360 0x9640, 0x96f4, 1361 0x9800, 0x9808, 1362 0x9810, 0x9864, 1363 0x9c00, 0x9c6c, 1364 0x9c80, 0x9cec, 1365 0x9d00, 0x9d6c, 1366 0x9d80, 0x9dec, 1367 0x9e00, 0x9e6c, 1368 0x9e80, 0x9eec, 1369 0x9f00, 0x9f6c, 1370 0x9f80, 0xa020, 1371 0xd000, 0xd004, 1372 0xd010, 0xd03c, 1373 0xdfc0, 0xdfe0, 1374 0xe000, 0x1106c, 1375 0x11074, 0x11088, 1376 0x1109c, 0x11110, 1377 0x11118, 0x1117c, 1378 0x11190, 0x11204, 1379 0x19040, 0x1906c, 1380 0x19078, 0x19080, 1381 0x1908c, 0x190e8, 1382 0x190f0, 0x190f8, 1383 0x19100, 0x19110, 1384 0x19120, 0x19124, 1385 0x19150, 0x19194, 1386 0x1919c, 0x191b0, 1387 0x191d0, 0x191e8, 1388 0x19238, 0x19290, 1389 0x193f8, 0x19428, 1390 0x19430, 0x19444, 1391 0x1944c, 0x1946c, 1392 0x19474, 0x19474, 1393 0x19490, 0x194cc, 1394 0x194f0, 0x194f8, 1395 0x19c00, 0x19c08, 1396 0x19c10, 0x19c60, 1397 0x19c94, 0x19ce4, 1398 0x19cf0, 0x19d40, 1399 0x19d50, 0x19d94, 1400 0x19da0, 0x19de8, 1401 0x19df0, 0x19e10, 1402 0x19e50, 0x19e90, 1403 0x19ea0, 0x19f24, 1404 0x19f34, 0x19f34, 1405 0x19f40, 0x19f50, 1406 0x19f90, 0x19fb4, 1407 0x19fc4, 0x19fe4, 1408 0x1a000, 0x1a004, 1409 0x1a010, 0x1a06c, 1410 0x1a0b0, 0x1a0e4, 1411 0x1a0ec, 0x1a0f8, 1412 0x1a100, 0x1a108, 1413 0x1a114, 0x1a130, 1414 0x1a138, 0x1a1c4, 1415 0x1a1fc, 0x1a1fc, 1416 0x1e008, 0x1e00c, 1417 0x1e040, 0x1e044, 1418 0x1e04c, 0x1e04c, 1419 0x1e284, 0x1e290, 1420 0x1e2c0, 0x1e2c0, 1421 0x1e2e0, 0x1e2e0, 1422 0x1e300, 0x1e384, 1423 0x1e3c0, 0x1e3c8, 1424 0x1e408, 0x1e40c, 1425 0x1e440, 0x1e444, 1426 0x1e44c, 0x1e44c, 1427 0x1e684, 0x1e690, 1428 0x1e6c0, 0x1e6c0, 1429 0x1e6e0, 0x1e6e0, 1430 0x1e700, 0x1e784, 1431 0x1e7c0, 0x1e7c8, 1432 0x1e808, 0x1e80c, 1433 0x1e840, 0x1e844, 1434 0x1e84c, 0x1e84c, 1435 0x1ea84, 0x1ea90, 1436 0x1eac0, 0x1eac0, 1437 0x1eae0, 0x1eae0, 1438 0x1eb00, 0x1eb84, 1439 0x1ebc0, 0x1ebc8, 1440 0x1ec08, 0x1ec0c, 1441 0x1ec40, 0x1ec44, 1442 0x1ec4c, 0x1ec4c, 1443 0x1ee84, 0x1ee90, 1444 0x1eec0, 0x1eec0, 1445 0x1eee0, 0x1eee0, 1446 0x1ef00, 0x1ef84, 1447 0x1efc0, 0x1efc8, 1448 0x1f008, 0x1f00c, 1449 0x1f040, 0x1f044, 1450 0x1f04c, 0x1f04c, 1451 0x1f284, 0x1f290, 1452 0x1f2c0, 0x1f2c0, 1453 0x1f2e0, 0x1f2e0, 1454 0x1f300, 0x1f384, 1455 0x1f3c0, 0x1f3c8, 1456 0x1f408, 0x1f40c, 1457 0x1f440, 0x1f444, 1458 0x1f44c, 0x1f44c, 1459 0x1f684, 0x1f690, 1460 0x1f6c0, 0x1f6c0, 1461 0x1f6e0, 0x1f6e0, 1462 0x1f700, 0x1f784, 1463 0x1f7c0, 0x1f7c8, 1464 0x1f808, 0x1f80c, 1465 0x1f840, 0x1f844, 1466 0x1f84c, 0x1f84c, 1467 0x1fa84, 0x1fa90, 1468 0x1fac0, 0x1fac0, 1469 0x1fae0, 0x1fae0, 1470 0x1fb00, 0x1fb84, 1471 0x1fbc0, 0x1fbc8, 1472 0x1fc08, 0x1fc0c, 1473 0x1fc40, 0x1fc44, 1474 0x1fc4c, 0x1fc4c, 1475 0x1fe84, 0x1fe90, 1476 0x1fec0, 0x1fec0, 1477 0x1fee0, 0x1fee0, 1478 0x1ff00, 0x1ff84, 1479 0x1ffc0, 0x1ffc8, 1480 0x30000, 0x30030, 1481 0x30100, 0x30144, 1482 0x30190, 0x301a0, 1483 0x301a8, 0x301b8, 1484 0x301c4, 0x301c8, 1485 0x301d0, 0x301d0, 1486 0x30200, 0x30318, 1487 0x30400, 0x304b4, 1488 0x304c0, 0x3052c, 1489 0x30540, 0x3061c, 1490 0x30800, 0x30828, 1491 0x30834, 0x30834, 1492 0x308c0, 0x30908, 1493 0x30910, 0x309ac, 1494 0x30a00, 0x30a14, 1495 0x30a1c, 0x30a2c, 1496 0x30a44, 0x30a50, 1497 0x30a74, 0x30a74, 1498 0x30a7c, 0x30afc, 1499 0x30b08, 0x30c24, 1500 0x30d00, 0x30d00, 1501 0x30d08, 0x30d14, 1502 0x30d1c, 0x30d20, 1503 0x30d3c, 0x30d3c, 1504 0x30d48, 0x30d50, 1505 0x31200, 0x3120c, 1506 0x31220, 0x31220, 1507 0x31240, 0x31240, 1508 0x31600, 0x3160c, 1509 0x31a00, 0x31a1c, 1510 0x31e00, 0x31e20, 1511 0x31e38, 0x31e3c, 1512 0x31e80, 0x31e80, 1513 0x31e88, 0x31ea8, 1514 0x31eb0, 0x31eb4, 1515 0x31ec8, 0x31ed4, 1516 0x31fb8, 0x32004, 1517 0x32200, 0x32200, 1518 0x32208, 0x32240, 1519 0x32248, 0x32280, 1520 0x32288, 0x322c0, 1521 0x322c8, 0x322fc, 1522 0x32600, 0x32630, 1523 0x32a00, 0x32abc, 1524 0x32b00, 0x32b10, 1525 0x32b20, 0x32b30, 1526 0x32b40, 0x32b50, 1527 0x32b60, 0x32b70, 1528 0x33000, 0x33028, 1529 0x33030, 0x33048, 1530 0x33060, 0x33068, 1531 0x33070, 0x3309c, 1532 0x330f0, 0x33128, 1533 0x33130, 0x33148, 1534 0x33160, 0x33168, 1535 0x33170, 0x3319c, 1536 0x331f0, 0x33238, 1537 0x33240, 0x33240, 1538 0x33248, 0x33250, 1539 0x3325c, 0x33264, 1540 0x33270, 0x332b8, 1541 0x332c0, 0x332e4, 1542 0x332f8, 0x33338, 1543 0x33340, 0x33340, 1544 0x33348, 0x33350, 1545 0x3335c, 0x33364, 1546 0x33370, 0x333b8, 1547 0x333c0, 0x333e4, 1548 0x333f8, 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1722 0x38d1c, 0x38d20, 1723 0x38d3c, 0x38d3c, 1724 0x38d48, 0x38d50, 1725 0x39200, 0x3920c, 1726 0x39220, 0x39220, 1727 0x39240, 0x39240, 1728 0x39600, 0x3960c, 1729 0x39a00, 0x39a1c, 1730 0x39e00, 0x39e20, 1731 0x39e38, 0x39e3c, 1732 0x39e80, 0x39e80, 1733 0x39e88, 0x39ea8, 1734 0x39eb0, 0x39eb4, 1735 0x39ec8, 0x39ed4, 1736 0x39fb8, 0x3a004, 1737 0x3a200, 0x3a200, 1738 0x3a208, 0x3a240, 1739 0x3a248, 0x3a280, 1740 0x3a288, 0x3a2c0, 1741 0x3a2c8, 0x3a2fc, 1742 0x3a600, 0x3a630, 1743 0x3aa00, 0x3aabc, 1744 0x3ab00, 0x3ab10, 1745 0x3ab20, 0x3ab30, 1746 0x3ab40, 0x3ab50, 1747 0x3ab60, 0x3ab70, 1748 0x3b000, 0x3b028, 1749 0x3b030, 0x3b048, 1750 0x3b060, 0x3b068, 1751 0x3b070, 0x3b09c, 1752 0x3b0f0, 0x3b128, 1753 0x3b130, 0x3b148, 1754 0x3b160, 0x3b168, 1755 0x3b170, 0x3b19c, 1756 0x3b1f0, 0x3b238, 1757 0x3b240, 0x3b240, 1758 0x3b248, 0x3b250, 1759 0x3b25c, 0x3b264, 1760 0x3b270, 0x3b2b8, 1761 0x3b2c0, 0x3b2e4, 1762 0x3b2f8, 0x3b338, 1763 0x3b340, 0x3b340, 1764 0x3b348, 0x3b350, 1765 0x3b35c, 0x3b364, 1766 0x3b370, 0x3b3b8, 1767 0x3b3c0, 0x3b3e4, 1768 0x3b3f8, 0x3b428, 1769 0x3b430, 0x3b448, 1770 0x3b460, 0x3b468, 1771 0x3b470, 0x3b49c, 1772 0x3b4f0, 0x3b528, 1773 0x3b530, 0x3b548, 1774 0x3b560, 0x3b568, 1775 0x3b570, 0x3b59c, 1776 0x3b5f0, 0x3b638, 1777 0x3b640, 0x3b640, 1778 0x3b648, 0x3b650, 1779 0x3b65c, 0x3b664, 1780 0x3b670, 0x3b6b8, 1781 0x3b6c0, 0x3b6e4, 1782 0x3b6f8, 0x3b738, 1783 0x3b740, 0x3b740, 1784 0x3b748, 0x3b750, 1785 0x3b75c, 0x3b764, 1786 0x3b770, 0x3b7b8, 1787 0x3b7c0, 0x3b7e4, 1788 0x3b7f8, 0x3b7fc, 1789 0x3b814, 0x3b814, 1790 0x3b82c, 0x3b82c, 1791 0x3b880, 0x3b88c, 1792 0x3b8e8, 0x3b8ec, 1793 0x3b900, 0x3b928, 1794 0x3b930, 0x3b948, 1795 0x3b960, 0x3b968, 1796 0x3b970, 0x3b99c, 1797 0x3b9f0, 0x3ba38, 1798 0x3ba40, 0x3ba40, 1799 0x3ba48, 0x3ba50, 1800 0x3ba5c, 0x3ba64, 1801 0x3ba70, 0x3bab8, 1802 0x3bac0, 0x3bae4, 1803 0x3baf8, 0x3bb10, 1804 0x3bb28, 0x3bb28, 1805 0x3bb3c, 0x3bb50, 1806 0x3bbf0, 0x3bc10, 1807 0x3bc28, 0x3bc28, 1808 0x3bc3c, 0x3bc50, 1809 0x3bcf0, 0x3bcfc, 1810 0x3c000, 0x3c030, 1811 0x3c100, 0x3c144, 1812 0x3c190, 0x3c1a0, 1813 0x3c1a8, 0x3c1b8, 1814 0x3c1c4, 0x3c1c8, 1815 0x3c1d0, 0x3c1d0, 1816 0x3c200, 0x3c318, 1817 0x3c400, 0x3c4b4, 1818 0x3c4c0, 0x3c52c, 1819 0x3c540, 0x3c61c, 1820 0x3c800, 0x3c828, 1821 0x3c834, 0x3c834, 1822 0x3c8c0, 0x3c908, 1823 0x3c910, 0x3c9ac, 1824 0x3ca00, 0x3ca14, 1825 0x3ca1c, 0x3ca2c, 1826 0x3ca44, 0x3ca50, 1827 0x3ca74, 0x3ca74, 1828 0x3ca7c, 0x3cafc, 1829 0x3cb08, 0x3cc24, 1830 0x3cd00, 0x3cd00, 1831 0x3cd08, 0x3cd14, 1832 0x3cd1c, 0x3cd20, 1833 0x3cd3c, 0x3cd3c, 1834 0x3cd48, 0x3cd50, 1835 0x3d200, 0x3d20c, 1836 0x3d220, 0x3d220, 1837 0x3d240, 0x3d240, 1838 0x3d600, 0x3d60c, 1839 0x3da00, 0x3da1c, 1840 0x3de00, 0x3de20, 1841 0x3de38, 0x3de3c, 1842 0x3de80, 0x3de80, 1843 0x3de88, 0x3dea8, 1844 0x3deb0, 0x3deb4, 1845 0x3dec8, 0x3ded4, 1846 0x3dfb8, 0x3e004, 1847 0x3e200, 0x3e200, 1848 0x3e208, 0x3e240, 1849 0x3e248, 0x3e280, 1850 0x3e288, 0x3e2c0, 1851 0x3e2c8, 0x3e2fc, 1852 0x3e600, 0x3e630, 1853 0x3ea00, 0x3eabc, 1854 0x3eb00, 0x3eb10, 1855 0x3eb20, 0x3eb30, 1856 0x3eb40, 0x3eb50, 1857 0x3eb60, 0x3eb70, 1858 0x3f000, 0x3f028, 1859 0x3f030, 0x3f048, 1860 0x3f060, 0x3f068, 1861 0x3f070, 0x3f09c, 1862 0x3f0f0, 0x3f128, 1863 0x3f130, 0x3f148, 1864 0x3f160, 0x3f168, 1865 0x3f170, 0x3f19c, 1866 0x3f1f0, 0x3f238, 1867 0x3f240, 0x3f240, 1868 0x3f248, 0x3f250, 1869 0x3f25c, 0x3f264, 1870 0x3f270, 0x3f2b8, 1871 0x3f2c0, 0x3f2e4, 1872 0x3f2f8, 0x3f338, 1873 0x3f340, 0x3f340, 1874 0x3f348, 0x3f350, 1875 0x3f35c, 0x3f364, 1876 0x3f370, 0x3f3b8, 1877 0x3f3c0, 0x3f3e4, 1878 0x3f3f8, 0x3f428, 1879 0x3f430, 0x3f448, 1880 0x3f460, 0x3f468, 1881 0x3f470, 0x3f49c, 1882 0x3f4f0, 0x3f528, 1883 0x3f530, 0x3f548, 1884 0x3f560, 0x3f568, 1885 0x3f570, 0x3f59c, 1886 0x3f5f0, 0x3f638, 1887 0x3f640, 0x3f640, 1888 0x3f648, 0x3f650, 1889 0x3f65c, 0x3f664, 1890 0x3f670, 0x3f6b8, 1891 0x3f6c0, 0x3f6e4, 1892 0x3f6f8, 0x3f738, 1893 0x3f740, 0x3f740, 1894 0x3f748, 0x3f750, 1895 0x3f75c, 0x3f764, 1896 0x3f770, 0x3f7b8, 1897 0x3f7c0, 0x3f7e4, 1898 0x3f7f8, 0x3f7fc, 1899 0x3f814, 0x3f814, 1900 0x3f82c, 0x3f82c, 1901 0x3f880, 0x3f88c, 1902 0x3f8e8, 0x3f8ec, 1903 0x3f900, 0x3f928, 1904 0x3f930, 0x3f948, 1905 0x3f960, 0x3f968, 1906 0x3f970, 0x3f99c, 1907 0x3f9f0, 0x3fa38, 1908 0x3fa40, 0x3fa40, 1909 0x3fa48, 0x3fa50, 1910 0x3fa5c, 0x3fa64, 1911 0x3fa70, 0x3fab8, 1912 0x3fac0, 0x3fae4, 1913 0x3faf8, 0x3fb10, 1914 0x3fb28, 0x3fb28, 1915 0x3fb3c, 0x3fb50, 1916 0x3fbf0, 0x3fc10, 1917 0x3fc28, 0x3fc28, 1918 0x3fc3c, 0x3fc50, 1919 0x3fcf0, 0x3fcfc, 1920 0x40000, 0x4000c, 1921 0x40040, 0x40050, 1922 0x40060, 0x40068, 1923 0x4007c, 0x4008c, 1924 0x40094, 0x400b0, 1925 0x400c0, 0x40144, 1926 0x40180, 0x4018c, 1927 0x40200, 0x40254, 1928 0x40260, 0x40264, 1929 0x40270, 0x40288, 1930 0x40290, 0x40298, 1931 0x402ac, 0x402c8, 1932 0x402d0, 0x402e0, 1933 0x402f0, 0x402f0, 1934 0x40300, 0x4033c, 1935 0x403f8, 0x403fc, 1936 0x41304, 0x413c4, 1937 0x41400, 0x4140c, 1938 0x41414, 0x4141c, 1939 0x41480, 0x414d0, 1940 0x44000, 0x44054, 1941 0x4405c, 0x44078, 1942 0x440c0, 0x44174, 1943 0x44180, 0x441ac, 1944 0x441b4, 0x441b8, 1945 0x441c0, 0x44254, 1946 0x4425c, 0x44278, 1947 0x442c0, 0x44374, 1948 0x44380, 0x443ac, 1949 0x443b4, 0x443b8, 1950 0x443c0, 0x44454, 1951 0x4445c, 0x44478, 1952 0x444c0, 0x44574, 1953 0x44580, 0x445ac, 1954 0x445b4, 0x445b8, 1955 0x445c0, 0x44654, 1956 0x4465c, 0x44678, 1957 0x446c0, 0x44774, 1958 0x44780, 0x447ac, 1959 0x447b4, 0x447b8, 1960 0x447c0, 0x44854, 1961 0x4485c, 0x44878, 1962 0x448c0, 0x44974, 1963 0x44980, 0x449ac, 1964 0x449b4, 0x449b8, 1965 0x449c0, 0x449fc, 1966 0x45000, 0x45004, 1967 0x45010, 0x45030, 1968 0x45040, 0x45060, 1969 0x45068, 0x45068, 1970 0x45080, 0x45084, 1971 0x450a0, 0x450b0, 1972 0x45200, 0x45204, 1973 0x45210, 0x45230, 1974 0x45240, 0x45260, 1975 0x45268, 0x45268, 1976 0x45280, 0x45284, 1977 0x452a0, 0x452b0, 1978 0x460c0, 0x460e4, 1979 0x47000, 0x4703c, 1980 0x47044, 0x4708c, 1981 0x47200, 0x47250, 1982 0x47400, 0x47408, 1983 0x47414, 0x47420, 1984 0x47600, 0x47618, 1985 0x47800, 0x47814, 1986 0x48000, 0x4800c, 1987 0x48040, 0x48050, 1988 0x48060, 0x48068, 1989 0x4807c, 0x4808c, 1990 0x48094, 0x480b0, 1991 0x480c0, 0x48144, 1992 0x48180, 0x4818c, 1993 0x48200, 0x48254, 1994 0x48260, 0x48264, 1995 0x48270, 0x48288, 1996 0x48290, 0x48298, 1997 0x482ac, 0x482c8, 1998 0x482d0, 0x482e0, 1999 0x482f0, 0x482f0, 2000 0x48300, 0x4833c, 2001 0x483f8, 0x483fc, 2002 0x49304, 0x493c4, 2003 0x49400, 0x4940c, 2004 0x49414, 0x4941c, 2005 0x49480, 0x494d0, 2006 0x4c000, 0x4c054, 2007 0x4c05c, 0x4c078, 2008 0x4c0c0, 0x4c174, 2009 0x4c180, 0x4c1ac, 2010 0x4c1b4, 0x4c1b8, 2011 0x4c1c0, 0x4c254, 2012 0x4c25c, 0x4c278, 2013 0x4c2c0, 0x4c374, 2014 0x4c380, 0x4c3ac, 2015 0x4c3b4, 0x4c3b8, 2016 0x4c3c0, 0x4c454, 2017 0x4c45c, 0x4c478, 2018 0x4c4c0, 0x4c574, 2019 0x4c580, 0x4c5ac, 2020 0x4c5b4, 0x4c5b8, 2021 0x4c5c0, 0x4c654, 2022 0x4c65c, 0x4c678, 2023 0x4c6c0, 0x4c774, 2024 0x4c780, 0x4c7ac, 2025 0x4c7b4, 0x4c7b8, 2026 0x4c7c0, 0x4c854, 2027 0x4c85c, 0x4c878, 2028 0x4c8c0, 0x4c974, 2029 0x4c980, 0x4c9ac, 2030 0x4c9b4, 0x4c9b8, 2031 0x4c9c0, 0x4c9fc, 2032 0x4d000, 0x4d004, 2033 0x4d010, 0x4d030, 2034 0x4d040, 0x4d060, 2035 0x4d068, 0x4d068, 2036 0x4d080, 0x4d084, 2037 0x4d0a0, 0x4d0b0, 2038 0x4d200, 0x4d204, 2039 0x4d210, 0x4d230, 2040 0x4d240, 0x4d260, 2041 0x4d268, 0x4d268, 2042 0x4d280, 0x4d284, 2043 0x4d2a0, 0x4d2b0, 2044 0x4e0c0, 0x4e0e4, 2045 0x4f000, 0x4f03c, 2046 0x4f044, 0x4f08c, 2047 0x4f200, 0x4f250, 2048 0x4f400, 0x4f408, 2049 0x4f414, 0x4f420, 2050 0x4f600, 0x4f618, 2051 0x4f800, 0x4f814, 2052 0x50000, 0x50084, 2053 0x50090, 0x500cc, 2054 0x50400, 0x50400, 2055 0x50800, 0x50884, 2056 0x50890, 0x508cc, 2057 0x50c00, 0x50c00, 2058 0x51000, 0x5101c, 2059 0x51300, 0x51308, 2060 }; 2061 2062 static const unsigned int t5vf_reg_ranges[] = { 2063 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2064 VF_MPS_REG(A_MPS_VF_CTL), 2065 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2066 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2068 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2069 FW_T4VF_MBDATA_BASE_ADDR, 2070 FW_T4VF_MBDATA_BASE_ADDR + 2071 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2072 }; 2073 2074 static const unsigned int t6_reg_ranges[] = { 2075 0x1008, 0x101c, 2076 0x1024, 0x10a8, 2077 0x10b4, 0x10f8, 2078 0x1100, 0x1114, 2079 0x111c, 0x112c, 2080 0x1138, 0x113c, 2081 0x1144, 0x114c, 2082 0x1180, 0x1184, 2083 0x1190, 0x1194, 2084 0x11a0, 0x11a4, 2085 0x11b0, 0x11c4, 2086 0x11fc, 0x123c, 2087 0x1254, 0x1274, 2088 0x1280, 0x133c, 2089 0x1800, 0x18fc, 2090 0x3000, 0x302c, 2091 0x3060, 0x30b0, 2092 0x30b8, 0x30d8, 2093 0x30e0, 0x30fc, 2094 0x3140, 0x357c, 2095 0x35a8, 0x35cc, 2096 0x35ec, 0x35ec, 2097 0x3600, 0x5624, 2098 0x56cc, 0x56ec, 2099 0x56f4, 0x5720, 2100 0x5728, 0x575c, 2101 0x580c, 0x5814, 2102 0x5890, 0x589c, 2103 0x58a4, 0x58ac, 2104 0x58b8, 0x58bc, 2105 0x5940, 0x595c, 2106 0x5980, 0x598c, 2107 0x59b0, 0x59c8, 2108 0x59d0, 0x59dc, 2109 0x59fc, 0x5a18, 2110 0x5a60, 0x5a6c, 2111 0x5a80, 0x5a8c, 2112 0x5a94, 0x5a9c, 2113 0x5b94, 0x5bfc, 2114 0x5c10, 0x5e48, 2115 0x5e50, 0x5e94, 2116 0x5ea0, 0x5eb0, 2117 0x5ec0, 0x5ec0, 2118 0x5ec8, 0x5ed0, 2119 0x5ee0, 0x5ee0, 2120 0x5ef0, 0x5ef0, 2121 0x5f00, 0x5f00, 2122 0x6000, 0x6020, 2123 0x6028, 0x6040, 2124 0x6058, 0x609c, 2125 0x60a8, 0x619c, 2126 0x7700, 0x7798, 2127 0x77c0, 0x7880, 2128 0x78cc, 0x78fc, 2129 0x7b00, 0x7b58, 2130 0x7b60, 0x7b84, 2131 0x7b8c, 0x7c54, 2132 0x7d00, 0x7d38, 2133 0x7d40, 0x7d84, 2134 0x7d8c, 0x7ddc, 2135 0x7de4, 0x7e04, 2136 0x7e10, 0x7e1c, 2137 0x7e24, 0x7e38, 2138 0x7e40, 0x7e44, 2139 0x7e4c, 0x7e78, 2140 0x7e80, 0x7edc, 2141 0x7ee8, 0x7efc, 2142 0x8dc0, 0x8de0, 2143 0x8df8, 0x8e04, 2144 0x8e10, 0x8e84, 2145 0x8ea0, 0x8f88, 2146 0x8fb8, 0x9058, 2147 0x9060, 0x9060, 2148 0x9068, 0x90f8, 2149 0x9100, 0x9124, 2150 0x9400, 0x9470, 2151 0x9600, 0x9600, 2152 0x9608, 0x9638, 2153 0x9640, 0x9704, 2154 0x9710, 0x971c, 2155 0x9800, 0x9808, 2156 0x9810, 0x9864, 2157 0x9c00, 0x9c6c, 2158 0x9c80, 0x9cec, 2159 0x9d00, 0x9d6c, 2160 0x9d80, 0x9dec, 2161 0x9e00, 0x9e6c, 2162 0x9e80, 0x9eec, 2163 0x9f00, 0x9f6c, 2164 0x9f80, 0xa020, 2165 0xd000, 0xd03c, 2166 0xd100, 0xd118, 2167 0xd200, 0xd214, 2168 0xd220, 0xd234, 2169 0xd240, 0xd254, 2170 0xd260, 0xd274, 2171 0xd280, 0xd294, 2172 0xd2a0, 0xd2b4, 2173 0xd2c0, 0xd2d4, 2174 0xd2e0, 0xd2f4, 2175 0xd300, 0xd31c, 2176 0xdfc0, 0xdfe0, 2177 0xe000, 0xf008, 2178 0xf010, 0xf018, 2179 0xf020, 0xf028, 2180 0x11000, 0x11014, 2181 0x11048, 0x1106c, 2182 0x11074, 0x11088, 2183 0x11098, 0x11120, 2184 0x1112c, 0x1117c, 2185 0x11190, 0x112e0, 2186 0x11300, 0x1130c, 2187 0x12000, 0x1206c, 2188 0x19040, 0x1906c, 2189 0x19078, 0x19080, 2190 0x1908c, 0x190e8, 2191 0x190f0, 0x190f8, 2192 0x19100, 0x19110, 2193 0x19120, 0x19124, 2194 0x19150, 0x19194, 2195 0x1919c, 0x191b0, 2196 0x191d0, 0x191e8, 2197 0x19238, 0x19290, 2198 0x192a4, 0x192b0, 2199 0x19348, 0x1934c, 2200 0x193f8, 0x19418, 2201 0x19420, 0x19428, 2202 0x19430, 0x19444, 2203 0x1944c, 0x1946c, 2204 0x19474, 0x19474, 2205 0x19490, 0x194cc, 2206 0x194f0, 0x194f8, 2207 0x19c00, 0x19c48, 2208 0x19c50, 0x19c80, 2209 0x19c94, 0x19c98, 2210 0x19ca0, 0x19cbc, 2211 0x19ce4, 0x19ce4, 2212 0x19cf0, 0x19cf8, 2213 0x19d00, 0x19d28, 2214 0x19d50, 0x19d78, 2215 0x19d94, 0x19d98, 2216 0x19da0, 0x19de0, 2217 0x19df0, 0x19e10, 2218 0x19e50, 0x19e6c, 2219 0x19ea0, 0x19ebc, 2220 0x19ec4, 0x19ef4, 2221 0x19f04, 0x19f2c, 2222 0x19f34, 0x19f34, 2223 0x19f40, 0x19f50, 2224 0x19f90, 0x19fac, 2225 0x19fc4, 0x19fc8, 2226 0x19fd0, 0x19fe4, 2227 0x1a000, 0x1a004, 2228 0x1a010, 0x1a06c, 2229 0x1a0b0, 0x1a0e4, 2230 0x1a0ec, 0x1a0f8, 2231 0x1a100, 0x1a108, 2232 0x1a114, 0x1a130, 2233 0x1a138, 0x1a1c4, 2234 0x1a1fc, 0x1a1fc, 2235 0x1e008, 0x1e00c, 2236 0x1e040, 0x1e044, 2237 0x1e04c, 0x1e04c, 2238 0x1e284, 0x1e290, 2239 0x1e2c0, 0x1e2c0, 2240 0x1e2e0, 0x1e2e0, 2241 0x1e300, 0x1e384, 2242 0x1e3c0, 0x1e3c8, 2243 0x1e408, 0x1e40c, 2244 0x1e440, 0x1e444, 2245 0x1e44c, 0x1e44c, 2246 0x1e684, 0x1e690, 2247 0x1e6c0, 0x1e6c0, 2248 0x1e6e0, 0x1e6e0, 2249 0x1e700, 0x1e784, 2250 0x1e7c0, 0x1e7c8, 2251 0x1e808, 0x1e80c, 2252 0x1e840, 0x1e844, 2253 0x1e84c, 0x1e84c, 2254 0x1ea84, 0x1ea90, 2255 0x1eac0, 0x1eac0, 2256 0x1eae0, 0x1eae0, 2257 0x1eb00, 0x1eb84, 2258 0x1ebc0, 0x1ebc8, 2259 0x1ec08, 0x1ec0c, 2260 0x1ec40, 0x1ec44, 2261 0x1ec4c, 0x1ec4c, 2262 0x1ee84, 0x1ee90, 2263 0x1eec0, 0x1eec0, 2264 0x1eee0, 0x1eee0, 2265 0x1ef00, 0x1ef84, 2266 0x1efc0, 0x1efc8, 2267 0x1f008, 0x1f00c, 2268 0x1f040, 0x1f044, 2269 0x1f04c, 0x1f04c, 2270 0x1f284, 0x1f290, 2271 0x1f2c0, 0x1f2c0, 2272 0x1f2e0, 0x1f2e0, 2273 0x1f300, 0x1f384, 2274 0x1f3c0, 0x1f3c8, 2275 0x1f408, 0x1f40c, 2276 0x1f440, 0x1f444, 2277 0x1f44c, 0x1f44c, 2278 0x1f684, 0x1f690, 2279 0x1f6c0, 0x1f6c0, 2280 0x1f6e0, 0x1f6e0, 2281 0x1f700, 0x1f784, 2282 0x1f7c0, 0x1f7c8, 2283 0x1f808, 0x1f80c, 2284 0x1f840, 0x1f844, 2285 0x1f84c, 0x1f84c, 2286 0x1fa84, 0x1fa90, 2287 0x1fac0, 0x1fac0, 2288 0x1fae0, 0x1fae0, 2289 0x1fb00, 0x1fb84, 2290 0x1fbc0, 0x1fbc8, 2291 0x1fc08, 0x1fc0c, 2292 0x1fc40, 0x1fc44, 2293 0x1fc4c, 0x1fc4c, 2294 0x1fe84, 0x1fe90, 2295 0x1fec0, 0x1fec0, 2296 0x1fee0, 0x1fee0, 2297 0x1ff00, 0x1ff84, 2298 0x1ffc0, 0x1ffc8, 2299 0x30000, 0x30030, 2300 0x30100, 0x30168, 2301 0x30190, 0x301a0, 2302 0x301a8, 0x301b8, 2303 0x301c4, 0x301c8, 2304 0x301d0, 0x301d0, 2305 0x30200, 0x30320, 2306 0x30400, 0x304b4, 2307 0x304c0, 0x3052c, 2308 0x30540, 0x3061c, 2309 0x30800, 0x308a0, 2310 0x308c0, 0x30908, 2311 0x30910, 0x309b8, 2312 0x30a00, 0x30a04, 2313 0x30a0c, 0x30a14, 2314 0x30a1c, 0x30a2c, 2315 0x30a44, 0x30a50, 2316 0x30a74, 0x30a74, 2317 0x30a7c, 0x30afc, 2318 0x30b08, 0x30c24, 2319 0x30d00, 0x30d14, 2320 0x30d1c, 0x30d3c, 2321 0x30d44, 0x30d4c, 2322 0x30d54, 0x30d74, 2323 0x30d7c, 0x30d7c, 2324 0x30de0, 0x30de0, 2325 0x30e00, 0x30ed4, 2326 0x30f00, 0x30fa4, 2327 0x30fc0, 0x30fc4, 2328 0x31000, 0x31004, 2329 0x31080, 0x310fc, 2330 0x31208, 0x31220, 2331 0x3123c, 0x31254, 2332 0x31300, 0x31300, 2333 0x31308, 0x3131c, 2334 0x31338, 0x3133c, 2335 0x31380, 0x31380, 2336 0x31388, 0x313a8, 2337 0x313b4, 0x313b4, 2338 0x31400, 0x31420, 2339 0x31438, 0x3143c, 2340 0x31480, 0x31480, 2341 0x314a8, 0x314a8, 2342 0x314b0, 0x314b4, 2343 0x314c8, 0x314d4, 2344 0x31a40, 0x31a4c, 2345 0x31af0, 0x31b20, 2346 0x31b38, 0x31b3c, 2347 0x31b80, 0x31b80, 2348 0x31ba8, 0x31ba8, 2349 0x31bb0, 0x31bb4, 2350 0x31bc8, 0x31bd4, 2351 0x32140, 0x3218c, 2352 0x321f0, 0x321f4, 2353 0x32200, 0x32200, 2354 0x32218, 0x32218, 2355 0x32400, 0x32400, 2356 0x32408, 0x3241c, 2357 0x32618, 0x32620, 2358 0x32664, 0x32664, 2359 0x326a8, 0x326a8, 2360 0x326ec, 0x326ec, 2361 0x32a00, 0x32abc, 2362 0x32b00, 0x32b18, 2363 0x32b20, 0x32b38, 2364 0x32b40, 0x32b58, 2365 0x32b60, 0x32b78, 2366 0x32c00, 0x32c00, 2367 0x32c08, 0x32c3c, 2368 0x33000, 0x3302c, 2369 0x33034, 0x33050, 2370 0x33058, 0x33058, 2371 0x33060, 0x3308c, 2372 0x3309c, 0x330ac, 2373 0x330c0, 0x330c0, 2374 0x330c8, 0x330d0, 2375 0x330d8, 0x330e0, 2376 0x330ec, 0x3312c, 2377 0x33134, 0x33150, 2378 0x33158, 0x33158, 2379 0x33160, 0x3318c, 2380 0x3319c, 0x331ac, 2381 0x331c0, 0x331c0, 2382 0x331c8, 0x331d0, 2383 0x331d8, 0x331e0, 2384 0x331ec, 0x33290, 2385 0x33298, 0x332c4, 2386 0x332e4, 0x33390, 2387 0x33398, 0x333c4, 2388 0x333e4, 0x3342c, 2389 0x33434, 0x33450, 2390 0x33458, 0x33458, 2391 0x33460, 0x3348c, 2392 0x3349c, 0x334ac, 2393 0x334c0, 0x334c0, 2394 0x334c8, 0x334d0, 2395 0x334d8, 0x334e0, 2396 0x334ec, 0x3352c, 2397 0x33534, 0x33550, 2398 0x33558, 0x33558, 2399 0x33560, 0x3358c, 2400 0x3359c, 0x335ac, 2401 0x335c0, 0x335c0, 2402 0x335c8, 0x335d0, 2403 0x335d8, 0x335e0, 2404 0x335ec, 0x33690, 2405 0x33698, 0x336c4, 2406 0x336e4, 0x33790, 2407 0x33798, 0x337c4, 2408 0x337e4, 0x337fc, 2409 0x33814, 0x33814, 2410 0x33854, 0x33868, 2411 0x33880, 0x3388c, 2412 0x338c0, 0x338d0, 2413 0x338e8, 0x338ec, 2414 0x33900, 0x3392c, 2415 0x33934, 0x33950, 2416 0x33958, 0x33958, 2417 0x33960, 0x3398c, 2418 0x3399c, 0x339ac, 2419 0x339c0, 0x339c0, 2420 0x339c8, 0x339d0, 2421 0x339d8, 0x339e0, 2422 0x339ec, 0x33a90, 2423 0x33a98, 0x33ac4, 2424 0x33ae4, 0x33b10, 2425 0x33b24, 0x33b28, 2426 0x33b38, 0x33b50, 2427 0x33bf0, 0x33c10, 2428 0x33c24, 0x33c28, 2429 0x33c38, 0x33c50, 2430 0x33cf0, 0x33cfc, 2431 0x34000, 0x34030, 2432 0x34100, 0x34168, 2433 0x34190, 0x341a0, 2434 0x341a8, 0x341b8, 2435 0x341c4, 0x341c8, 2436 0x341d0, 0x341d0, 2437 0x34200, 0x34320, 2438 0x34400, 0x344b4, 2439 0x344c0, 0x3452c, 2440 0x34540, 0x3461c, 2441 0x34800, 0x348a0, 2442 0x348c0, 0x34908, 2443 0x34910, 0x349b8, 2444 0x34a00, 0x34a04, 2445 0x34a0c, 0x34a14, 2446 0x34a1c, 0x34a2c, 2447 0x34a44, 0x34a50, 2448 0x34a74, 0x34a74, 2449 0x34a7c, 0x34afc, 2450 0x34b08, 0x34c24, 2451 0x34d00, 0x34d14, 2452 0x34d1c, 0x34d3c, 2453 0x34d44, 0x34d4c, 2454 0x34d54, 0x34d74, 2455 0x34d7c, 0x34d7c, 2456 0x34de0, 0x34de0, 2457 0x34e00, 0x34ed4, 2458 0x34f00, 0x34fa4, 2459 0x34fc0, 0x34fc4, 2460 0x35000, 0x35004, 2461 0x35080, 0x350fc, 2462 0x35208, 0x35220, 2463 0x3523c, 0x35254, 2464 0x35300, 0x35300, 2465 0x35308, 0x3531c, 2466 0x35338, 0x3533c, 2467 0x35380, 0x35380, 2468 0x35388, 0x353a8, 2469 0x353b4, 0x353b4, 2470 0x35400, 0x35420, 2471 0x35438, 0x3543c, 2472 0x35480, 0x35480, 2473 0x354a8, 0x354a8, 2474 0x354b0, 0x354b4, 2475 0x354c8, 0x354d4, 2476 0x35a40, 0x35a4c, 2477 0x35af0, 0x35b20, 2478 0x35b38, 0x35b3c, 2479 0x35b80, 0x35b80, 2480 0x35ba8, 0x35ba8, 2481 0x35bb0, 0x35bb4, 2482 0x35bc8, 0x35bd4, 2483 0x36140, 0x3618c, 2484 0x361f0, 0x361f4, 2485 0x36200, 0x36200, 2486 0x36218, 0x36218, 2487 0x36400, 0x36400, 2488 0x36408, 0x3641c, 2489 0x36618, 0x36620, 2490 0x36664, 0x36664, 2491 0x366a8, 0x366a8, 2492 0x366ec, 0x366ec, 2493 0x36a00, 0x36abc, 2494 0x36b00, 0x36b18, 2495 0x36b20, 0x36b38, 2496 0x36b40, 0x36b58, 2497 0x36b60, 0x36b78, 2498 0x36c00, 0x36c00, 2499 0x36c08, 0x36c3c, 2500 0x37000, 0x3702c, 2501 0x37034, 0x37050, 2502 0x37058, 0x37058, 2503 0x37060, 0x3708c, 2504 0x3709c, 0x370ac, 2505 0x370c0, 0x370c0, 2506 0x370c8, 0x370d0, 2507 0x370d8, 0x370e0, 2508 0x370ec, 0x3712c, 2509 0x37134, 0x37150, 2510 0x37158, 0x37158, 2511 0x37160, 0x3718c, 2512 0x3719c, 0x371ac, 2513 0x371c0, 0x371c0, 2514 0x371c8, 0x371d0, 2515 0x371d8, 0x371e0, 2516 0x371ec, 0x37290, 2517 0x37298, 0x372c4, 2518 0x372e4, 0x37390, 2519 0x37398, 0x373c4, 2520 0x373e4, 0x3742c, 2521 0x37434, 0x37450, 2522 0x37458, 0x37458, 2523 0x37460, 0x3748c, 2524 0x3749c, 0x374ac, 2525 0x374c0, 0x374c0, 2526 0x374c8, 0x374d0, 2527 0x374d8, 0x374e0, 2528 0x374ec, 0x3752c, 2529 0x37534, 0x37550, 2530 0x37558, 0x37558, 2531 0x37560, 0x3758c, 2532 0x3759c, 0x375ac, 2533 0x375c0, 0x375c0, 2534 0x375c8, 0x375d0, 2535 0x375d8, 0x375e0, 2536 0x375ec, 0x37690, 2537 0x37698, 0x376c4, 2538 0x376e4, 0x37790, 2539 0x37798, 0x377c4, 2540 0x377e4, 0x377fc, 2541 0x37814, 0x37814, 2542 0x37854, 0x37868, 2543 0x37880, 0x3788c, 2544 0x378c0, 0x378d0, 2545 0x378e8, 0x378ec, 2546 0x37900, 0x3792c, 2547 0x37934, 0x37950, 2548 0x37958, 0x37958, 2549 0x37960, 0x3798c, 2550 0x3799c, 0x379ac, 2551 0x379c0, 0x379c0, 2552 0x379c8, 0x379d0, 2553 0x379d8, 0x379e0, 2554 0x379ec, 0x37a90, 2555 0x37a98, 0x37ac4, 2556 0x37ae4, 0x37b10, 2557 0x37b24, 0x37b28, 2558 0x37b38, 0x37b50, 2559 0x37bf0, 0x37c10, 2560 0x37c24, 0x37c28, 2561 0x37c38, 0x37c50, 2562 0x37cf0, 0x37cfc, 2563 0x40040, 0x40040, 2564 0x40080, 0x40084, 2565 0x40100, 0x40100, 2566 0x40140, 0x401bc, 2567 0x40200, 0x40214, 2568 0x40228, 0x40228, 2569 0x40240, 0x40258, 2570 0x40280, 0x40280, 2571 0x40304, 0x40304, 2572 0x40330, 0x4033c, 2573 0x41304, 0x413c8, 2574 0x413d0, 0x413dc, 2575 0x413f0, 0x413f0, 2576 0x41400, 0x4140c, 2577 0x41414, 0x4141c, 2578 0x41480, 0x414d0, 2579 0x44000, 0x4407c, 2580 0x440c0, 0x441ac, 2581 0x441b4, 0x4427c, 2582 0x442c0, 0x443ac, 2583 0x443b4, 0x4447c, 2584 0x444c0, 0x445ac, 2585 0x445b4, 0x4467c, 2586 0x446c0, 0x447ac, 2587 0x447b4, 0x4487c, 2588 0x448c0, 0x449ac, 2589 0x449b4, 0x44a7c, 2590 0x44ac0, 0x44bac, 2591 0x44bb4, 0x44c7c, 2592 0x44cc0, 0x44dac, 2593 0x44db4, 0x44e7c, 2594 0x44ec0, 0x44fac, 2595 0x44fb4, 0x4507c, 2596 0x450c0, 0x451ac, 2597 0x451b4, 0x451fc, 2598 0x45800, 0x45804, 2599 0x45810, 0x45830, 2600 0x45840, 0x45860, 2601 0x45868, 0x45868, 2602 0x45880, 0x45884, 2603 0x458a0, 0x458b0, 2604 0x45a00, 0x45a04, 2605 0x45a10, 0x45a30, 2606 0x45a40, 0x45a60, 2607 0x45a68, 0x45a68, 2608 0x45a80, 0x45a84, 2609 0x45aa0, 0x45ab0, 2610 0x460c0, 0x460e4, 2611 0x47000, 0x4703c, 2612 0x47044, 0x4708c, 2613 0x47200, 0x47250, 2614 0x47400, 0x47408, 2615 0x47414, 0x47420, 2616 0x47600, 0x47618, 2617 0x47800, 0x47814, 2618 0x47820, 0x4782c, 2619 0x50000, 0x50084, 2620 0x50090, 0x500cc, 2621 0x50300, 0x50384, 2622 0x50400, 0x50400, 2623 0x50800, 0x50884, 2624 0x50890, 0x508cc, 2625 0x50b00, 0x50b84, 2626 0x50c00, 0x50c00, 2627 0x51000, 0x51020, 2628 0x51028, 0x510b0, 2629 0x51300, 0x51324, 2630 }; 2631 2632 static const unsigned int t6vf_reg_ranges[] = { 2633 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2634 VF_MPS_REG(A_MPS_VF_CTL), 2635 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2636 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2637 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2638 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2639 FW_T6VF_MBDATA_BASE_ADDR, 2640 FW_T6VF_MBDATA_BASE_ADDR + 2641 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2642 }; 2643 2644 u32 *buf_end = (u32 *)(buf + buf_size); 2645 const unsigned int *reg_ranges; 2646 int reg_ranges_size, range; 2647 unsigned int chip_version = chip_id(adap); 2648 2649 /* 2650 * Select the right set of register ranges to dump depending on the 2651 * adapter chip type. 2652 */ 2653 switch (chip_version) { 2654 case CHELSIO_T4: 2655 if (adap->flags & IS_VF) { 2656 reg_ranges = t4vf_reg_ranges; 2657 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2658 } else { 2659 reg_ranges = t4_reg_ranges; 2660 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2661 } 2662 break; 2663 2664 case CHELSIO_T5: 2665 if (adap->flags & IS_VF) { 2666 reg_ranges = t5vf_reg_ranges; 2667 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2668 } else { 2669 reg_ranges = t5_reg_ranges; 2670 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2671 } 2672 break; 2673 2674 case CHELSIO_T6: 2675 if (adap->flags & IS_VF) { 2676 reg_ranges = t6vf_reg_ranges; 2677 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2678 } else { 2679 reg_ranges = t6_reg_ranges; 2680 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2681 } 2682 break; 2683 2684 default: 2685 CH_ERR(adap, 2686 "Unsupported chip version %d\n", chip_version); 2687 return; 2688 } 2689 2690 /* 2691 * Clear the register buffer and insert the appropriate register 2692 * values selected by the above register ranges. 2693 */ 2694 memset(buf, 0, buf_size); 2695 for (range = 0; range < reg_ranges_size; range += 2) { 2696 unsigned int reg = reg_ranges[range]; 2697 unsigned int last_reg = reg_ranges[range + 1]; 2698 u32 *bufp = (u32 *)(buf + reg); 2699 2700 /* 2701 * Iterate across the register range filling in the register 2702 * buffer but don't write past the end of the register buffer. 2703 */ 2704 while (reg <= last_reg && bufp < buf_end) { 2705 *bufp++ = t4_read_reg(adap, reg); 2706 reg += sizeof(u32); 2707 } 2708 } 2709 } 2710 2711 /* 2712 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2713 * header followed by one or more VPD-R sections, each with its own header. 2714 */ 2715 struct t4_vpd_hdr { 2716 u8 id_tag; 2717 u8 id_len[2]; 2718 u8 id_data[ID_LEN]; 2719 }; 2720 2721 struct t4_vpdr_hdr { 2722 u8 vpdr_tag; 2723 u8 vpdr_len[2]; 2724 }; 2725 2726 /* 2727 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2728 */ 2729 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2730 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2731 2732 #define EEPROM_STAT_ADDR 0x7bfc 2733 #define VPD_SIZE 0x800 2734 #define VPD_BASE 0x400 2735 #define VPD_BASE_OLD 0 2736 #define VPD_LEN 1024 2737 #define VPD_INFO_FLD_HDR_SIZE 3 2738 #define CHELSIO_VPD_UNIQUE_ID 0x82 2739 2740 /* 2741 * Small utility function to wait till any outstanding VPD Access is complete. 2742 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2743 * VPD Access in flight. This allows us to handle the problem of having a 2744 * previous VPD Access time out and prevent an attempt to inject a new VPD 2745 * Request before any in-flight VPD reguest has completed. 2746 */ 2747 static int t4_seeprom_wait(struct adapter *adapter) 2748 { 2749 unsigned int base = adapter->params.pci.vpd_cap_addr; 2750 int max_poll; 2751 2752 /* 2753 * If no VPD Access is in flight, we can just return success right 2754 * away. 2755 */ 2756 if (!adapter->vpd_busy) 2757 return 0; 2758 2759 /* 2760 * Poll the VPD Capability Address/Flag register waiting for it 2761 * to indicate that the operation is complete. 2762 */ 2763 max_poll = EEPROM_MAX_POLL; 2764 do { 2765 u16 val; 2766 2767 udelay(EEPROM_DELAY); 2768 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2769 2770 /* 2771 * If the operation is complete, mark the VPD as no longer 2772 * busy and return success. 2773 */ 2774 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2775 adapter->vpd_busy = 0; 2776 return 0; 2777 } 2778 } while (--max_poll); 2779 2780 /* 2781 * Failure! Note that we leave the VPD Busy status set in order to 2782 * avoid pushing a new VPD Access request into the VPD Capability till 2783 * the current operation eventually succeeds. It's a bug to issue a 2784 * new request when an existing request is in flight and will result 2785 * in corrupt hardware state. 2786 */ 2787 return -ETIMEDOUT; 2788 } 2789 2790 /** 2791 * t4_seeprom_read - read a serial EEPROM location 2792 * @adapter: adapter to read 2793 * @addr: EEPROM virtual address 2794 * @data: where to store the read data 2795 * 2796 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2797 * VPD capability. Note that this function must be called with a virtual 2798 * address. 2799 */ 2800 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2801 { 2802 unsigned int base = adapter->params.pci.vpd_cap_addr; 2803 int ret; 2804 2805 /* 2806 * VPD Accesses must alway be 4-byte aligned! 2807 */ 2808 if (addr >= EEPROMVSIZE || (addr & 3)) 2809 return -EINVAL; 2810 2811 /* 2812 * Wait for any previous operation which may still be in flight to 2813 * complete. 2814 */ 2815 ret = t4_seeprom_wait(adapter); 2816 if (ret) { 2817 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2818 return ret; 2819 } 2820 2821 /* 2822 * Issue our new VPD Read request, mark the VPD as being busy and wait 2823 * for our request to complete. If it doesn't complete, note the 2824 * error and return it to our caller. Note that we do not reset the 2825 * VPD Busy status! 2826 */ 2827 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2828 adapter->vpd_busy = 1; 2829 adapter->vpd_flag = PCI_VPD_ADDR_F; 2830 ret = t4_seeprom_wait(adapter); 2831 if (ret) { 2832 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2833 return ret; 2834 } 2835 2836 /* 2837 * Grab the returned data, swizzle it into our endianness and 2838 * return success. 2839 */ 2840 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2841 *data = le32_to_cpu(*data); 2842 return 0; 2843 } 2844 2845 /** 2846 * t4_seeprom_write - write a serial EEPROM location 2847 * @adapter: adapter to write 2848 * @addr: virtual EEPROM address 2849 * @data: value to write 2850 * 2851 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2852 * VPD capability. Note that this function must be called with a virtual 2853 * address. 2854 */ 2855 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2856 { 2857 unsigned int base = adapter->params.pci.vpd_cap_addr; 2858 int ret; 2859 u32 stats_reg; 2860 int max_poll; 2861 2862 /* 2863 * VPD Accesses must alway be 4-byte aligned! 2864 */ 2865 if (addr >= EEPROMVSIZE || (addr & 3)) 2866 return -EINVAL; 2867 2868 /* 2869 * Wait for any previous operation which may still be in flight to 2870 * complete. 2871 */ 2872 ret = t4_seeprom_wait(adapter); 2873 if (ret) { 2874 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2875 return ret; 2876 } 2877 2878 /* 2879 * Issue our new VPD Read request, mark the VPD as being busy and wait 2880 * for our request to complete. If it doesn't complete, note the 2881 * error and return it to our caller. Note that we do not reset the 2882 * VPD Busy status! 2883 */ 2884 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2885 cpu_to_le32(data)); 2886 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2887 (u16)addr | PCI_VPD_ADDR_F); 2888 adapter->vpd_busy = 1; 2889 adapter->vpd_flag = 0; 2890 ret = t4_seeprom_wait(adapter); 2891 if (ret) { 2892 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2893 return ret; 2894 } 2895 2896 /* 2897 * Reset PCI_VPD_DATA register after a transaction and wait for our 2898 * request to complete. If it doesn't complete, return error. 2899 */ 2900 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2901 max_poll = EEPROM_MAX_POLL; 2902 do { 2903 udelay(EEPROM_DELAY); 2904 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2905 } while ((stats_reg & 0x1) && --max_poll); 2906 if (!max_poll) 2907 return -ETIMEDOUT; 2908 2909 /* Return success! */ 2910 return 0; 2911 } 2912 2913 /** 2914 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2915 * @phys_addr: the physical EEPROM address 2916 * @fn: the PCI function number 2917 * @sz: size of function-specific area 2918 * 2919 * Translate a physical EEPROM address to virtual. The first 1K is 2920 * accessed through virtual addresses starting at 31K, the rest is 2921 * accessed through virtual addresses starting at 0. 2922 * 2923 * The mapping is as follows: 2924 * [0..1K) -> [31K..32K) 2925 * [1K..1K+A) -> [ES-A..ES) 2926 * [1K+A..ES) -> [0..ES-A-1K) 2927 * 2928 * where A = @fn * @sz, and ES = EEPROM size. 2929 */ 2930 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2931 { 2932 fn *= sz; 2933 if (phys_addr < 1024) 2934 return phys_addr + (31 << 10); 2935 if (phys_addr < 1024 + fn) 2936 return EEPROMSIZE - fn + phys_addr - 1024; 2937 if (phys_addr < EEPROMSIZE) 2938 return phys_addr - 1024 - fn; 2939 return -EINVAL; 2940 } 2941 2942 /** 2943 * t4_seeprom_wp - enable/disable EEPROM write protection 2944 * @adapter: the adapter 2945 * @enable: whether to enable or disable write protection 2946 * 2947 * Enables or disables write protection on the serial EEPROM. 2948 */ 2949 int t4_seeprom_wp(struct adapter *adapter, int enable) 2950 { 2951 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2952 } 2953 2954 /** 2955 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2956 * @vpd: Pointer to buffered vpd data structure 2957 * @kw: The keyword to search for 2958 * @region: VPD region to search (starting from 0) 2959 * 2960 * Returns the value of the information field keyword or 2961 * -ENOENT otherwise. 2962 */ 2963 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2964 { 2965 int i, tag; 2966 unsigned int offset, len; 2967 const struct t4_vpdr_hdr *vpdr; 2968 2969 offset = sizeof(struct t4_vpd_hdr); 2970 vpdr = (const void *)(vpd + offset); 2971 tag = vpdr->vpdr_tag; 2972 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2973 while (region--) { 2974 offset += sizeof(struct t4_vpdr_hdr) + len; 2975 vpdr = (const void *)(vpd + offset); 2976 if (++tag != vpdr->vpdr_tag) 2977 return -ENOENT; 2978 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2979 } 2980 offset += sizeof(struct t4_vpdr_hdr); 2981 2982 if (offset + len > VPD_LEN) { 2983 return -ENOENT; 2984 } 2985 2986 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2987 if (memcmp(vpd + i , kw , 2) == 0){ 2988 i += VPD_INFO_FLD_HDR_SIZE; 2989 return i; 2990 } 2991 2992 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2993 } 2994 2995 return -ENOENT; 2996 } 2997 2998 2999 /** 3000 * get_vpd_params - read VPD parameters from VPD EEPROM 3001 * @adapter: adapter to read 3002 * @p: where to store the parameters 3003 * @vpd: caller provided temporary space to read the VPD into 3004 * 3005 * Reads card parameters stored in VPD EEPROM. 3006 */ 3007 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3008 uint16_t device_id, u32 *buf) 3009 { 3010 int i, ret, addr; 3011 int ec, sn, pn, na, md; 3012 u8 csum; 3013 const u8 *vpd = (const u8 *)buf; 3014 3015 /* 3016 * Card information normally starts at VPD_BASE but early cards had 3017 * it at 0. 3018 */ 3019 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3020 if (ret) 3021 return (ret); 3022 3023 /* 3024 * The VPD shall have a unique identifier specified by the PCI SIG. 3025 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3026 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3027 * is expected to automatically put this entry at the 3028 * beginning of the VPD. 3029 */ 3030 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3031 3032 for (i = 0; i < VPD_LEN; i += 4) { 3033 ret = t4_seeprom_read(adapter, addr + i, buf++); 3034 if (ret) 3035 return ret; 3036 } 3037 3038 #define FIND_VPD_KW(var,name) do { \ 3039 var = get_vpd_keyword_val(vpd, name, 0); \ 3040 if (var < 0) { \ 3041 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3042 return -EINVAL; \ 3043 } \ 3044 } while (0) 3045 3046 FIND_VPD_KW(i, "RV"); 3047 for (csum = 0; i >= 0; i--) 3048 csum += vpd[i]; 3049 3050 if (csum) { 3051 CH_ERR(adapter, 3052 "corrupted VPD EEPROM, actual csum %u\n", csum); 3053 return -EINVAL; 3054 } 3055 3056 FIND_VPD_KW(ec, "EC"); 3057 FIND_VPD_KW(sn, "SN"); 3058 FIND_VPD_KW(pn, "PN"); 3059 FIND_VPD_KW(na, "NA"); 3060 #undef FIND_VPD_KW 3061 3062 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3063 strstrip(p->id); 3064 memcpy(p->ec, vpd + ec, EC_LEN); 3065 strstrip(p->ec); 3066 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3067 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3068 strstrip(p->sn); 3069 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3070 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3071 strstrip((char *)p->pn); 3072 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3073 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3074 strstrip((char *)p->na); 3075 3076 if (device_id & 0x80) 3077 return 0; /* Custom card */ 3078 3079 md = get_vpd_keyword_val(vpd, "VF", 1); 3080 if (md < 0) { 3081 snprintf(p->md, sizeof(p->md), "unknown"); 3082 } else { 3083 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3084 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3085 strstrip((char *)p->md); 3086 } 3087 3088 return 0; 3089 } 3090 3091 /* serial flash and firmware constants and flash config file constants */ 3092 enum { 3093 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3094 3095 /* flash command opcodes */ 3096 SF_PROG_PAGE = 2, /* program 256B page */ 3097 SF_WR_DISABLE = 4, /* disable writes */ 3098 SF_RD_STATUS = 5, /* read status register */ 3099 SF_WR_ENABLE = 6, /* enable writes */ 3100 SF_RD_DATA_FAST = 0xb, /* read flash */ 3101 SF_RD_ID = 0x9f, /* read ID */ 3102 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3103 }; 3104 3105 /** 3106 * sf1_read - read data from the serial flash 3107 * @adapter: the adapter 3108 * @byte_cnt: number of bytes to read 3109 * @cont: whether another operation will be chained 3110 * @lock: whether to lock SF for PL access only 3111 * @valp: where to store the read data 3112 * 3113 * Reads up to 4 bytes of data from the serial flash. The location of 3114 * the read needs to be specified prior to calling this by issuing the 3115 * appropriate commands to the serial flash. 3116 */ 3117 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3118 int lock, u32 *valp) 3119 { 3120 int ret; 3121 3122 if (!byte_cnt || byte_cnt > 4) 3123 return -EINVAL; 3124 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3125 return -EBUSY; 3126 t4_write_reg(adapter, A_SF_OP, 3127 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3128 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3129 if (!ret) 3130 *valp = t4_read_reg(adapter, A_SF_DATA); 3131 return ret; 3132 } 3133 3134 /** 3135 * sf1_write - write data to the serial flash 3136 * @adapter: the adapter 3137 * @byte_cnt: number of bytes to write 3138 * @cont: whether another operation will be chained 3139 * @lock: whether to lock SF for PL access only 3140 * @val: value to write 3141 * 3142 * Writes up to 4 bytes of data to the serial flash. The location of 3143 * the write needs to be specified prior to calling this by issuing the 3144 * appropriate commands to the serial flash. 3145 */ 3146 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3147 int lock, u32 val) 3148 { 3149 if (!byte_cnt || byte_cnt > 4) 3150 return -EINVAL; 3151 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3152 return -EBUSY; 3153 t4_write_reg(adapter, A_SF_DATA, val); 3154 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3155 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3156 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3157 } 3158 3159 /** 3160 * flash_wait_op - wait for a flash operation to complete 3161 * @adapter: the adapter 3162 * @attempts: max number of polls of the status register 3163 * @delay: delay between polls in ms 3164 * 3165 * Wait for a flash operation to complete by polling the status register. 3166 */ 3167 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3168 { 3169 int ret; 3170 u32 status; 3171 3172 while (1) { 3173 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3174 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3175 return ret; 3176 if (!(status & 1)) 3177 return 0; 3178 if (--attempts == 0) 3179 return -EAGAIN; 3180 if (delay) 3181 msleep(delay); 3182 } 3183 } 3184 3185 /** 3186 * t4_read_flash - read words from serial flash 3187 * @adapter: the adapter 3188 * @addr: the start address for the read 3189 * @nwords: how many 32-bit words to read 3190 * @data: where to store the read data 3191 * @byte_oriented: whether to store data as bytes or as words 3192 * 3193 * Read the specified number of 32-bit words from the serial flash. 3194 * If @byte_oriented is set the read data is stored as a byte array 3195 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3196 * natural endianness. 3197 */ 3198 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3199 unsigned int nwords, u32 *data, int byte_oriented) 3200 { 3201 int ret; 3202 3203 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3204 return -EINVAL; 3205 3206 addr = swab32(addr) | SF_RD_DATA_FAST; 3207 3208 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3209 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3210 return ret; 3211 3212 for ( ; nwords; nwords--, data++) { 3213 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3214 if (nwords == 1) 3215 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3216 if (ret) 3217 return ret; 3218 if (byte_oriented) 3219 *data = (__force __u32)(cpu_to_be32(*data)); 3220 } 3221 return 0; 3222 } 3223 3224 /** 3225 * t4_write_flash - write up to a page of data to the serial flash 3226 * @adapter: the adapter 3227 * @addr: the start address to write 3228 * @n: length of data to write in bytes 3229 * @data: the data to write 3230 * @byte_oriented: whether to store data as bytes or as words 3231 * 3232 * Writes up to a page of data (256 bytes) to the serial flash starting 3233 * at the given address. All the data must be written to the same page. 3234 * If @byte_oriented is set the write data is stored as byte stream 3235 * (i.e. matches what on disk), otherwise in big-endian. 3236 */ 3237 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3238 unsigned int n, const u8 *data, int byte_oriented) 3239 { 3240 int ret; 3241 u32 buf[SF_PAGE_SIZE / 4]; 3242 unsigned int i, c, left, val, offset = addr & 0xff; 3243 3244 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3245 return -EINVAL; 3246 3247 val = swab32(addr) | SF_PROG_PAGE; 3248 3249 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3250 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3251 goto unlock; 3252 3253 for (left = n; left; left -= c) { 3254 c = min(left, 4U); 3255 for (val = 0, i = 0; i < c; ++i) 3256 val = (val << 8) + *data++; 3257 3258 if (!byte_oriented) 3259 val = cpu_to_be32(val); 3260 3261 ret = sf1_write(adapter, c, c != left, 1, val); 3262 if (ret) 3263 goto unlock; 3264 } 3265 ret = flash_wait_op(adapter, 8, 1); 3266 if (ret) 3267 goto unlock; 3268 3269 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3270 3271 /* Read the page to verify the write succeeded */ 3272 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3273 byte_oriented); 3274 if (ret) 3275 return ret; 3276 3277 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3278 CH_ERR(adapter, 3279 "failed to correctly write the flash page at %#x\n", 3280 addr); 3281 return -EIO; 3282 } 3283 return 0; 3284 3285 unlock: 3286 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3287 return ret; 3288 } 3289 3290 /** 3291 * t4_get_fw_version - read the firmware version 3292 * @adapter: the adapter 3293 * @vers: where to place the version 3294 * 3295 * Reads the FW version from flash. 3296 */ 3297 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3298 { 3299 return t4_read_flash(adapter, FLASH_FW_START + 3300 offsetof(struct fw_hdr, fw_ver), 1, 3301 vers, 0); 3302 } 3303 3304 /** 3305 * t4_get_fw_hdr - read the firmware header 3306 * @adapter: the adapter 3307 * @hdr: where to place the version 3308 * 3309 * Reads the FW header from flash into caller provided buffer. 3310 */ 3311 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3312 { 3313 return t4_read_flash(adapter, FLASH_FW_START, 3314 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3315 } 3316 3317 /** 3318 * t4_get_bs_version - read the firmware bootstrap version 3319 * @adapter: the adapter 3320 * @vers: where to place the version 3321 * 3322 * Reads the FW Bootstrap version from flash. 3323 */ 3324 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3325 { 3326 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3327 offsetof(struct fw_hdr, fw_ver), 1, 3328 vers, 0); 3329 } 3330 3331 /** 3332 * t4_get_tp_version - read the TP microcode version 3333 * @adapter: the adapter 3334 * @vers: where to place the version 3335 * 3336 * Reads the TP microcode version from flash. 3337 */ 3338 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3339 { 3340 return t4_read_flash(adapter, FLASH_FW_START + 3341 offsetof(struct fw_hdr, tp_microcode_ver), 3342 1, vers, 0); 3343 } 3344 3345 /** 3346 * t4_get_exprom_version - return the Expansion ROM version (if any) 3347 * @adapter: the adapter 3348 * @vers: where to place the version 3349 * 3350 * Reads the Expansion ROM header from FLASH and returns the version 3351 * number (if present) through the @vers return value pointer. We return 3352 * this in the Firmware Version Format since it's convenient. Return 3353 * 0 on success, -ENOENT if no Expansion ROM is present. 3354 */ 3355 int t4_get_exprom_version(struct adapter *adapter, u32 *vers) 3356 { 3357 struct exprom_header { 3358 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3359 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3360 } *hdr; 3361 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3362 sizeof(u32))]; 3363 int ret; 3364 3365 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START, 3366 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3367 0); 3368 if (ret) 3369 return ret; 3370 3371 hdr = (struct exprom_header *)exprom_header_buf; 3372 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3373 return -ENOENT; 3374 3375 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3376 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3377 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3378 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3379 return 0; 3380 } 3381 3382 /** 3383 * t4_get_scfg_version - return the Serial Configuration version 3384 * @adapter: the adapter 3385 * @vers: where to place the version 3386 * 3387 * Reads the Serial Configuration Version via the Firmware interface 3388 * (thus this can only be called once we're ready to issue Firmware 3389 * commands). The format of the Serial Configuration version is 3390 * adapter specific. Returns 0 on success, an error on failure. 3391 * 3392 * Note that early versions of the Firmware didn't include the ability 3393 * to retrieve the Serial Configuration version, so we zero-out the 3394 * return-value parameter in that case to avoid leaving it with 3395 * garbage in it. 3396 * 3397 * Also note that the Firmware will return its cached copy of the Serial 3398 * Initialization Revision ID, not the actual Revision ID as written in 3399 * the Serial EEPROM. This is only an issue if a new VPD has been written 3400 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3401 * it's best to defer calling this routine till after a FW_RESET_CMD has 3402 * been issued if the Host Driver will be performing a full adapter 3403 * initialization. 3404 */ 3405 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3406 { 3407 u32 scfgrev_param; 3408 int ret; 3409 3410 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3411 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3412 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3413 1, &scfgrev_param, vers); 3414 if (ret) 3415 *vers = 0; 3416 return ret; 3417 } 3418 3419 /** 3420 * t4_get_vpd_version - return the VPD version 3421 * @adapter: the adapter 3422 * @vers: where to place the version 3423 * 3424 * Reads the VPD via the Firmware interface (thus this can only be called 3425 * once we're ready to issue Firmware commands). The format of the 3426 * VPD version is adapter specific. Returns 0 on success, an error on 3427 * failure. 3428 * 3429 * Note that early versions of the Firmware didn't include the ability 3430 * to retrieve the VPD version, so we zero-out the return-value parameter 3431 * in that case to avoid leaving it with garbage in it. 3432 * 3433 * Also note that the Firmware will return its cached copy of the VPD 3434 * Revision ID, not the actual Revision ID as written in the Serial 3435 * EEPROM. This is only an issue if a new VPD has been written and the 3436 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3437 * to defer calling this routine till after a FW_RESET_CMD has been issued 3438 * if the Host Driver will be performing a full adapter initialization. 3439 */ 3440 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3441 { 3442 u32 vpdrev_param; 3443 int ret; 3444 3445 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3446 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3447 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3448 1, &vpdrev_param, vers); 3449 if (ret) 3450 *vers = 0; 3451 return ret; 3452 } 3453 3454 /** 3455 * t4_get_version_info - extract various chip/firmware version information 3456 * @adapter: the adapter 3457 * 3458 * Reads various chip/firmware version numbers and stores them into the 3459 * adapter Adapter Parameters structure. If any of the efforts fails 3460 * the first failure will be returned, but all of the version numbers 3461 * will be read. 3462 */ 3463 int t4_get_version_info(struct adapter *adapter) 3464 { 3465 int ret = 0; 3466 3467 #define FIRST_RET(__getvinfo) \ 3468 do { \ 3469 int __ret = __getvinfo; \ 3470 if (__ret && !ret) \ 3471 ret = __ret; \ 3472 } while (0) 3473 3474 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3475 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3476 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3477 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3478 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3479 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3480 3481 #undef FIRST_RET 3482 3483 return ret; 3484 } 3485 3486 /** 3487 * t4_flash_erase_sectors - erase a range of flash sectors 3488 * @adapter: the adapter 3489 * @start: the first sector to erase 3490 * @end: the last sector to erase 3491 * 3492 * Erases the sectors in the given inclusive range. 3493 */ 3494 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3495 { 3496 int ret = 0; 3497 3498 if (end >= adapter->params.sf_nsec) 3499 return -EINVAL; 3500 3501 while (start <= end) { 3502 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3503 (ret = sf1_write(adapter, 4, 0, 1, 3504 SF_ERASE_SECTOR | (start << 8))) != 0 || 3505 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3506 CH_ERR(adapter, 3507 "erase of flash sector %d failed, error %d\n", 3508 start, ret); 3509 break; 3510 } 3511 start++; 3512 } 3513 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3514 return ret; 3515 } 3516 3517 /** 3518 * t4_flash_cfg_addr - return the address of the flash configuration file 3519 * @adapter: the adapter 3520 * 3521 * Return the address within the flash where the Firmware Configuration 3522 * File is stored, or an error if the device FLASH is too small to contain 3523 * a Firmware Configuration File. 3524 */ 3525 int t4_flash_cfg_addr(struct adapter *adapter) 3526 { 3527 /* 3528 * If the device FLASH isn't large enough to hold a Firmware 3529 * Configuration File, return an error. 3530 */ 3531 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3532 return -ENOSPC; 3533 3534 return FLASH_CFG_START; 3535 } 3536 3537 /* 3538 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3539 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3540 * and emit an error message for mismatched firmware to save our caller the 3541 * effort ... 3542 */ 3543 static int t4_fw_matches_chip(struct adapter *adap, 3544 const struct fw_hdr *hdr) 3545 { 3546 /* 3547 * The expression below will return FALSE for any unsupported adapter 3548 * which will keep us "honest" in the future ... 3549 */ 3550 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3551 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3552 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3553 return 1; 3554 3555 CH_ERR(adap, 3556 "FW image (%d) is not suitable for this adapter (%d)\n", 3557 hdr->chip, chip_id(adap)); 3558 return 0; 3559 } 3560 3561 /** 3562 * t4_load_fw - download firmware 3563 * @adap: the adapter 3564 * @fw_data: the firmware image to write 3565 * @size: image size 3566 * 3567 * Write the supplied firmware image to the card's serial flash. 3568 */ 3569 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3570 { 3571 u32 csum; 3572 int ret, addr; 3573 unsigned int i; 3574 u8 first_page[SF_PAGE_SIZE]; 3575 const u32 *p = (const u32 *)fw_data; 3576 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3577 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3578 unsigned int fw_start_sec; 3579 unsigned int fw_start; 3580 unsigned int fw_size; 3581 3582 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3583 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3584 fw_start = FLASH_FWBOOTSTRAP_START; 3585 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3586 } else { 3587 fw_start_sec = FLASH_FW_START_SEC; 3588 fw_start = FLASH_FW_START; 3589 fw_size = FLASH_FW_MAX_SIZE; 3590 } 3591 3592 if (!size) { 3593 CH_ERR(adap, "FW image has no data\n"); 3594 return -EINVAL; 3595 } 3596 if (size & 511) { 3597 CH_ERR(adap, 3598 "FW image size not multiple of 512 bytes\n"); 3599 return -EINVAL; 3600 } 3601 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3602 CH_ERR(adap, 3603 "FW image size differs from size in FW header\n"); 3604 return -EINVAL; 3605 } 3606 if (size > fw_size) { 3607 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3608 fw_size); 3609 return -EFBIG; 3610 } 3611 if (!t4_fw_matches_chip(adap, hdr)) 3612 return -EINVAL; 3613 3614 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3615 csum += be32_to_cpu(p[i]); 3616 3617 if (csum != 0xffffffff) { 3618 CH_ERR(adap, 3619 "corrupted firmware image, checksum %#x\n", csum); 3620 return -EINVAL; 3621 } 3622 3623 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3624 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3625 if (ret) 3626 goto out; 3627 3628 /* 3629 * We write the correct version at the end so the driver can see a bad 3630 * version if the FW write fails. Start by writing a copy of the 3631 * first page with a bad version. 3632 */ 3633 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3634 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3635 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3636 if (ret) 3637 goto out; 3638 3639 addr = fw_start; 3640 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3641 addr += SF_PAGE_SIZE; 3642 fw_data += SF_PAGE_SIZE; 3643 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3644 if (ret) 3645 goto out; 3646 } 3647 3648 ret = t4_write_flash(adap, 3649 fw_start + offsetof(struct fw_hdr, fw_ver), 3650 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3651 out: 3652 if (ret) 3653 CH_ERR(adap, "firmware download failed, error %d\n", 3654 ret); 3655 return ret; 3656 } 3657 3658 /** 3659 * t4_fwcache - firmware cache operation 3660 * @adap: the adapter 3661 * @op : the operation (flush or flush and invalidate) 3662 */ 3663 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3664 { 3665 struct fw_params_cmd c; 3666 3667 memset(&c, 0, sizeof(c)); 3668 c.op_to_vfn = 3669 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3670 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3671 V_FW_PARAMS_CMD_PFN(adap->pf) | 3672 V_FW_PARAMS_CMD_VFN(0)); 3673 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3674 c.param[0].mnem = 3675 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3676 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3677 c.param[0].val = (__force __be32)op; 3678 3679 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3680 } 3681 3682 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3683 unsigned int *pif_req_wrptr, 3684 unsigned int *pif_rsp_wrptr) 3685 { 3686 int i, j; 3687 u32 cfg, val, req, rsp; 3688 3689 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3690 if (cfg & F_LADBGEN) 3691 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3692 3693 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3694 req = G_POLADBGWRPTR(val); 3695 rsp = G_PILADBGWRPTR(val); 3696 if (pif_req_wrptr) 3697 *pif_req_wrptr = req; 3698 if (pif_rsp_wrptr) 3699 *pif_rsp_wrptr = rsp; 3700 3701 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3702 for (j = 0; j < 6; j++) { 3703 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3704 V_PILADBGRDPTR(rsp)); 3705 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3706 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3707 req++; 3708 rsp++; 3709 } 3710 req = (req + 2) & M_POLADBGRDPTR; 3711 rsp = (rsp + 2) & M_PILADBGRDPTR; 3712 } 3713 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3714 } 3715 3716 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3717 { 3718 u32 cfg; 3719 int i, j, idx; 3720 3721 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3722 if (cfg & F_LADBGEN) 3723 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3724 3725 for (i = 0; i < CIM_MALA_SIZE; i++) { 3726 for (j = 0; j < 5; j++) { 3727 idx = 8 * i + j; 3728 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3729 V_PILADBGRDPTR(idx)); 3730 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3731 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3732 } 3733 } 3734 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3735 } 3736 3737 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3738 { 3739 unsigned int i, j; 3740 3741 for (i = 0; i < 8; i++) { 3742 u32 *p = la_buf + i; 3743 3744 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3745 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3746 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3747 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3748 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3749 } 3750 } 3751 3752 /** 3753 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3754 * @caps16: a 16-bit Port Capabilities value 3755 * 3756 * Returns the equivalent 32-bit Port Capabilities value. 3757 */ 3758 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3759 { 3760 uint32_t caps32 = 0; 3761 3762 #define CAP16_TO_CAP32(__cap) \ 3763 do { \ 3764 if (caps16 & FW_PORT_CAP_##__cap) \ 3765 caps32 |= FW_PORT_CAP32_##__cap; \ 3766 } while (0) 3767 3768 CAP16_TO_CAP32(SPEED_100M); 3769 CAP16_TO_CAP32(SPEED_1G); 3770 CAP16_TO_CAP32(SPEED_25G); 3771 CAP16_TO_CAP32(SPEED_10G); 3772 CAP16_TO_CAP32(SPEED_40G); 3773 CAP16_TO_CAP32(SPEED_100G); 3774 CAP16_TO_CAP32(FC_RX); 3775 CAP16_TO_CAP32(FC_TX); 3776 CAP16_TO_CAP32(ANEG); 3777 CAP16_TO_CAP32(FORCE_PAUSE); 3778 CAP16_TO_CAP32(MDIAUTO); 3779 CAP16_TO_CAP32(MDISTRAIGHT); 3780 CAP16_TO_CAP32(FEC_RS); 3781 CAP16_TO_CAP32(FEC_BASER_RS); 3782 CAP16_TO_CAP32(802_3_PAUSE); 3783 CAP16_TO_CAP32(802_3_ASM_DIR); 3784 3785 #undef CAP16_TO_CAP32 3786 3787 return caps32; 3788 } 3789 3790 /** 3791 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3792 * @caps32: a 32-bit Port Capabilities value 3793 * 3794 * Returns the equivalent 16-bit Port Capabilities value. Note that 3795 * not all 32-bit Port Capabilities can be represented in the 16-bit 3796 * Port Capabilities and some fields/values may not make it. 3797 */ 3798 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3799 { 3800 uint16_t caps16 = 0; 3801 3802 #define CAP32_TO_CAP16(__cap) \ 3803 do { \ 3804 if (caps32 & FW_PORT_CAP32_##__cap) \ 3805 caps16 |= FW_PORT_CAP_##__cap; \ 3806 } while (0) 3807 3808 CAP32_TO_CAP16(SPEED_100M); 3809 CAP32_TO_CAP16(SPEED_1G); 3810 CAP32_TO_CAP16(SPEED_10G); 3811 CAP32_TO_CAP16(SPEED_25G); 3812 CAP32_TO_CAP16(SPEED_40G); 3813 CAP32_TO_CAP16(SPEED_100G); 3814 CAP32_TO_CAP16(FC_RX); 3815 CAP32_TO_CAP16(FC_TX); 3816 CAP32_TO_CAP16(802_3_PAUSE); 3817 CAP32_TO_CAP16(802_3_ASM_DIR); 3818 CAP32_TO_CAP16(ANEG); 3819 CAP32_TO_CAP16(FORCE_PAUSE); 3820 CAP32_TO_CAP16(MDIAUTO); 3821 CAP32_TO_CAP16(MDISTRAIGHT); 3822 CAP32_TO_CAP16(FEC_RS); 3823 CAP32_TO_CAP16(FEC_BASER_RS); 3824 3825 #undef CAP32_TO_CAP16 3826 3827 return caps16; 3828 } 3829 3830 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none) 3831 { 3832 int8_t fec = 0; 3833 3834 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) 3835 return (unset_means_none ? FEC_NONE : 0); 3836 3837 if (caps & FW_PORT_CAP32_FEC_RS) 3838 fec |= FEC_RS; 3839 if (caps & FW_PORT_CAP32_FEC_BASER_RS) 3840 fec |= FEC_BASER_RS; 3841 if (caps & FW_PORT_CAP32_FEC_NO_FEC) 3842 fec |= FEC_NONE; 3843 3844 return (fec); 3845 } 3846 3847 /* 3848 * Note that 0 is not translated to NO_FEC. 3849 */ 3850 static uint32_t fec_to_fwcap(int8_t fec) 3851 { 3852 uint32_t caps = 0; 3853 3854 /* Only real FECs allowed. */ 3855 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); 3856 3857 if (fec & FEC_RS) 3858 caps |= FW_PORT_CAP32_FEC_RS; 3859 if (fec & FEC_BASER_RS) 3860 caps |= FW_PORT_CAP32_FEC_BASER_RS; 3861 if (fec & FEC_NONE) 3862 caps |= FW_PORT_CAP32_FEC_NO_FEC; 3863 3864 return (caps); 3865 } 3866 3867 /** 3868 * t4_link_l1cfg - apply link configuration to MAC/PHY 3869 * @phy: the PHY to setup 3870 * @mac: the MAC to setup 3871 * @lc: the requested link configuration 3872 * 3873 * Set up a port's MAC and PHY according to a desired link configuration. 3874 * - If the PHY can auto-negotiate first decide what to advertise, then 3875 * enable/disable auto-negotiation as desired, and reset. 3876 * - If the PHY does not auto-negotiate just reset it. 3877 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3878 * otherwise do it later based on the outcome of auto-negotiation. 3879 */ 3880 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3881 struct link_config *lc) 3882 { 3883 struct fw_port_cmd c; 3884 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3885 unsigned int aneg, fc, fec, speed, rcap; 3886 3887 fc = 0; 3888 if (lc->requested_fc & PAUSE_RX) 3889 fc |= FW_PORT_CAP32_FC_RX; 3890 if (lc->requested_fc & PAUSE_TX) 3891 fc |= FW_PORT_CAP32_FC_TX; 3892 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3893 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3894 3895 if (lc->requested_aneg == AUTONEG_DISABLE) 3896 aneg = 0; 3897 else if (lc->requested_aneg == AUTONEG_ENABLE) 3898 aneg = FW_PORT_CAP32_ANEG; 3899 else 3900 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3901 3902 if (aneg) { 3903 speed = lc->pcaps & 3904 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3905 } else if (lc->requested_speed != 0) 3906 speed = speed_to_fwcap(lc->requested_speed); 3907 else 3908 speed = fwcap_top_speed(lc->pcaps); 3909 3910 fec = 0; 3911 #ifdef INVARIANTS 3912 if (lc->force_fec != 0) 3913 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_FEC); 3914 #endif 3915 if (fec_supported(speed)) { 3916 if (lc->requested_fec == FEC_AUTO) { 3917 if (lc->force_fec > 0) { 3918 /* 3919 * Must use FORCE_FEC even though requested FEC 3920 * is AUTO. Set all the FEC bits valid for the 3921 * speed and let the firmware pick one. 3922 */ 3923 fec |= FW_PORT_CAP32_FORCE_FEC; 3924 if (speed & FW_PORT_CAP32_SPEED_100G) { 3925 fec |= FW_PORT_CAP32_FEC_RS; 3926 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3927 } else { 3928 fec |= FW_PORT_CAP32_FEC_RS; 3929 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3930 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3931 } 3932 } else { 3933 /* 3934 * Set only 1b. Old firmwares can't deal with 3935 * multiple bits and new firmwares are free to 3936 * ignore this and try whatever FECs they want 3937 * because we aren't setting FORCE_FEC here. 3938 */ 3939 fec |= fec_to_fwcap(lc->fec_hint); 3940 } 3941 } else { 3942 /* 3943 * User has explicitly requested some FEC(s). Set 3944 * FORCE_FEC unless prohibited from using it. 3945 */ 3946 if (lc->force_fec != 0) 3947 fec |= FW_PORT_CAP32_FORCE_FEC; 3948 fec |= fec_to_fwcap(lc->requested_fec & 3949 M_FW_PORT_CAP32_FEC); 3950 if (lc->requested_fec & FEC_MODULE) 3951 fec |= fec_to_fwcap(lc->fec_hint); 3952 } 3953 3954 /* 3955 * This is for compatibility with old firmwares. The original 3956 * way to request NO_FEC was to not set any of the FEC bits. New 3957 * firmwares understand this too. 3958 */ 3959 if (fec == FW_PORT_CAP32_FEC_NO_FEC) 3960 fec = 0; 3961 } 3962 3963 /* Force AN on for BT cards. */ 3964 if (isset(&adap->bt_map, port)) 3965 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3966 3967 rcap = aneg | speed | fc | fec; 3968 if ((rcap | lc->pcaps) != lc->pcaps) { 3969 #ifdef INVARIANTS 3970 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, 3971 lc->pcaps, rcap & (rcap ^ lc->pcaps)); 3972 #endif 3973 rcap &= lc->pcaps; 3974 } 3975 rcap |= mdi; 3976 3977 memset(&c, 0, sizeof(c)); 3978 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3979 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3980 V_FW_PORT_CMD_PORTID(port)); 3981 if (adap->params.port_caps32) { 3982 c.action_to_len16 = 3983 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3984 FW_LEN16(c)); 3985 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3986 } else { 3987 c.action_to_len16 = 3988 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3989 FW_LEN16(c)); 3990 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3991 } 3992 3993 lc->requested_caps = rcap; 3994 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3995 } 3996 3997 /** 3998 * t4_restart_aneg - restart autonegotiation 3999 * @adap: the adapter 4000 * @mbox: mbox to use for the FW command 4001 * @port: the port id 4002 * 4003 * Restarts autonegotiation for the selected port. 4004 */ 4005 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 4006 { 4007 struct fw_port_cmd c; 4008 4009 memset(&c, 0, sizeof(c)); 4010 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 4011 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 4012 V_FW_PORT_CMD_PORTID(port)); 4013 c.action_to_len16 = 4014 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4015 FW_LEN16(c)); 4016 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 4017 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4018 } 4019 4020 struct intr_details { 4021 u32 mask; 4022 const char *msg; 4023 }; 4024 4025 struct intr_action { 4026 u32 mask; 4027 int arg; 4028 bool (*action)(struct adapter *, int, bool); 4029 }; 4030 4031 #define NONFATAL_IF_DISABLED 1 4032 struct intr_info { 4033 const char *name; /* name of the INT_CAUSE register */ 4034 int cause_reg; /* INT_CAUSE register */ 4035 int enable_reg; /* INT_ENABLE register */ 4036 u32 fatal; /* bits that are fatal */ 4037 int flags; /* hints */ 4038 const struct intr_details *details; 4039 const struct intr_action *actions; 4040 }; 4041 4042 static inline char 4043 intr_alert_char(u32 cause, u32 enable, u32 fatal) 4044 { 4045 4046 if (cause & fatal) 4047 return ('!'); 4048 if (cause & enable) 4049 return ('*'); 4050 return ('-'); 4051 } 4052 4053 static void 4054 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 4055 { 4056 u32 enable, fatal, leftover; 4057 const struct intr_details *details; 4058 char alert; 4059 4060 enable = t4_read_reg(adap, ii->enable_reg); 4061 if (ii->flags & NONFATAL_IF_DISABLED) 4062 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 4063 else 4064 fatal = ii->fatal; 4065 alert = intr_alert_char(cause, enable, fatal); 4066 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 4067 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4068 4069 leftover = cause; 4070 for (details = ii->details; details && details->mask != 0; details++) { 4071 u32 msgbits = details->mask & cause; 4072 if (msgbits == 0) 4073 continue; 4074 alert = intr_alert_char(msgbits, enable, ii->fatal); 4075 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4076 details->msg); 4077 leftover &= ~msgbits; 4078 } 4079 if (leftover != 0 && leftover != cause) 4080 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4081 } 4082 4083 /* 4084 * Returns true for fatal error. 4085 */ 4086 static bool 4087 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4088 u32 additional_cause, bool verbose) 4089 { 4090 u32 cause, fatal; 4091 bool rc; 4092 const struct intr_action *action; 4093 4094 /* 4095 * Read and display cause. Note that the top level PL_INT_CAUSE is a 4096 * bit special and we need to completely ignore the bits that are not in 4097 * PL_INT_ENABLE. 4098 */ 4099 cause = t4_read_reg(adap, ii->cause_reg); 4100 if (ii->cause_reg == A_PL_INT_CAUSE) 4101 cause &= t4_read_reg(adap, ii->enable_reg); 4102 if (verbose || cause != 0) 4103 t4_show_intr_info(adap, ii, cause); 4104 fatal = cause & ii->fatal; 4105 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4106 fatal &= t4_read_reg(adap, ii->enable_reg); 4107 cause |= additional_cause; 4108 if (cause == 0) 4109 return (false); 4110 4111 rc = fatal != 0; 4112 for (action = ii->actions; action && action->mask != 0; action++) { 4113 if (!(action->mask & cause)) 4114 continue; 4115 rc |= (action->action)(adap, action->arg, verbose); 4116 } 4117 4118 /* clear */ 4119 t4_write_reg(adap, ii->cause_reg, cause); 4120 (void)t4_read_reg(adap, ii->cause_reg); 4121 4122 return (rc); 4123 } 4124 4125 /* 4126 * Interrupt handler for the PCIE module. 4127 */ 4128 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4129 { 4130 static const struct intr_details sysbus_intr_details[] = { 4131 { F_RNPP, "RXNP array parity error" }, 4132 { F_RPCP, "RXPC array parity error" }, 4133 { F_RCIP, "RXCIF array parity error" }, 4134 { F_RCCP, "Rx completions control array parity error" }, 4135 { F_RFTP, "RXFT array parity error" }, 4136 { 0 } 4137 }; 4138 static const struct intr_info sysbus_intr_info = { 4139 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4140 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4141 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4142 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4143 .flags = 0, 4144 .details = sysbus_intr_details, 4145 .actions = NULL, 4146 }; 4147 static const struct intr_details pcie_port_intr_details[] = { 4148 { F_TPCP, "TXPC array parity error" }, 4149 { F_TNPP, "TXNP array parity error" }, 4150 { F_TFTP, "TXFT array parity error" }, 4151 { F_TCAP, "TXCA array parity error" }, 4152 { F_TCIP, "TXCIF array parity error" }, 4153 { F_RCAP, "RXCA array parity error" }, 4154 { F_OTDD, "outbound request TLP discarded" }, 4155 { F_RDPE, "Rx data parity error" }, 4156 { F_TDUE, "Tx uncorrectable data error" }, 4157 { 0 } 4158 }; 4159 static const struct intr_info pcie_port_intr_info = { 4160 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4161 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4162 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4163 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4164 F_OTDD | F_RDPE | F_TDUE, 4165 .flags = 0, 4166 .details = pcie_port_intr_details, 4167 .actions = NULL, 4168 }; 4169 static const struct intr_details pcie_intr_details[] = { 4170 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4171 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4172 { F_MSIDATAPERR, "MSI data parity error" }, 4173 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4174 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4175 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4176 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4177 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4178 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4179 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4180 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4181 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4182 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4183 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4184 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4185 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4186 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4187 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4188 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4189 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4190 { F_FIDPERR, "PCIe FID parity error" }, 4191 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4192 { F_MATAGPERR, "PCIe MA tag parity error" }, 4193 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4194 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4195 { F_RXWRPERR, "PCIe Rx write parity error" }, 4196 { F_RPLPERR, "PCIe replay buffer parity error" }, 4197 { F_PCIESINT, "PCIe core secondary fault" }, 4198 { F_PCIEPINT, "PCIe core primary fault" }, 4199 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4200 { 0 } 4201 }; 4202 static const struct intr_details t5_pcie_intr_details[] = { 4203 { F_IPGRPPERR, "Parity errors observed by IP" }, 4204 { F_NONFATALERR, "PCIe non-fatal error" }, 4205 { F_READRSPERR, "Outbound read error" }, 4206 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4207 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4208 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4209 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4210 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4211 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4212 { F_MAGRPPERR, "MA group FIFO parity error" }, 4213 { F_VFIDPERR, "VFID SRAM parity error" }, 4214 { F_FIDPERR, "FID SRAM parity error" }, 4215 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4216 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4217 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4218 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4219 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4220 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4221 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4222 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4223 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4224 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4225 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4226 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4227 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4228 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4229 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4230 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4231 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4232 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4233 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4234 { 0 } 4235 }; 4236 struct intr_info pcie_intr_info = { 4237 .name = "PCIE_INT_CAUSE", 4238 .cause_reg = A_PCIE_INT_CAUSE, 4239 .enable_reg = A_PCIE_INT_ENABLE, 4240 .fatal = 0xffffffff, 4241 .flags = NONFATAL_IF_DISABLED, 4242 .details = NULL, 4243 .actions = NULL, 4244 }; 4245 bool fatal = false; 4246 4247 if (is_t4(adap)) { 4248 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4249 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4250 4251 pcie_intr_info.details = pcie_intr_details; 4252 } else { 4253 pcie_intr_info.details = t5_pcie_intr_details; 4254 } 4255 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4256 4257 return (fatal); 4258 } 4259 4260 /* 4261 * TP interrupt handler. 4262 */ 4263 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4264 { 4265 static const struct intr_details tp_intr_details[] = { 4266 { 0x3fffffff, "TP parity error" }, 4267 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4268 { 0 } 4269 }; 4270 static const struct intr_info tp_intr_info = { 4271 .name = "TP_INT_CAUSE", 4272 .cause_reg = A_TP_INT_CAUSE, 4273 .enable_reg = A_TP_INT_ENABLE, 4274 .fatal = 0x7fffffff, 4275 .flags = NONFATAL_IF_DISABLED, 4276 .details = tp_intr_details, 4277 .actions = NULL, 4278 }; 4279 4280 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4281 } 4282 4283 /* 4284 * SGE interrupt handler. 4285 */ 4286 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4287 { 4288 static const struct intr_info sge_int1_info = { 4289 .name = "SGE_INT_CAUSE1", 4290 .cause_reg = A_SGE_INT_CAUSE1, 4291 .enable_reg = A_SGE_INT_ENABLE1, 4292 .fatal = 0xffffffff, 4293 .flags = NONFATAL_IF_DISABLED, 4294 .details = NULL, 4295 .actions = NULL, 4296 }; 4297 static const struct intr_info sge_int2_info = { 4298 .name = "SGE_INT_CAUSE2", 4299 .cause_reg = A_SGE_INT_CAUSE2, 4300 .enable_reg = A_SGE_INT_ENABLE2, 4301 .fatal = 0xffffffff, 4302 .flags = NONFATAL_IF_DISABLED, 4303 .details = NULL, 4304 .actions = NULL, 4305 }; 4306 static const struct intr_details sge_int3_details[] = { 4307 { F_ERR_FLM_DBP, 4308 "DBP pointer delivery for invalid context or QID" }, 4309 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4310 "Invalid QID or header request by IDMA" }, 4311 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4312 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4313 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4314 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4315 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4316 { F_ERR_TIMER_ABOVE_MAX_QID, 4317 "SGE GTS with timer 0-5 for IQID > 1023" }, 4318 { F_ERR_CPL_EXCEED_IQE_SIZE, 4319 "SGE received CPL exceeding IQE size" }, 4320 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4321 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4322 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4323 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4324 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4325 "SGE IQID > 1023 received CPL for FL" }, 4326 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4327 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4328 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4329 { F_ERR_ING_CTXT_PRIO, 4330 "Ingress context manager priority user error" }, 4331 { F_ERR_EGR_CTXT_PRIO, 4332 "Egress context manager priority user error" }, 4333 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4334 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4335 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4336 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4337 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4338 { 0x0000000f, "SGE context access for invalid queue" }, 4339 { 0 } 4340 }; 4341 static const struct intr_details t6_sge_int3_details[] = { 4342 { F_ERR_FLM_DBP, 4343 "DBP pointer delivery for invalid context or QID" }, 4344 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4345 "Invalid QID or header request by IDMA" }, 4346 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4347 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4348 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4349 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4350 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4351 { F_ERR_TIMER_ABOVE_MAX_QID, 4352 "SGE GTS with timer 0-5 for IQID > 1023" }, 4353 { F_ERR_CPL_EXCEED_IQE_SIZE, 4354 "SGE received CPL exceeding IQE size" }, 4355 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4356 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4357 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4358 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4359 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4360 "SGE IQID > 1023 received CPL for FL" }, 4361 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4362 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4363 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4364 { F_ERR_ING_CTXT_PRIO, 4365 "Ingress context manager priority user error" }, 4366 { F_ERR_EGR_CTXT_PRIO, 4367 "Egress context manager priority user error" }, 4368 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4369 { F_FATAL_WRE_LEN, 4370 "SGE WRE packet less than advertized length" }, 4371 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4372 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4373 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4374 { 0x0000000f, "SGE context access for invalid queue" }, 4375 { 0 } 4376 }; 4377 struct intr_info sge_int3_info = { 4378 .name = "SGE_INT_CAUSE3", 4379 .cause_reg = A_SGE_INT_CAUSE3, 4380 .enable_reg = A_SGE_INT_ENABLE3, 4381 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4382 .flags = 0, 4383 .details = NULL, 4384 .actions = NULL, 4385 }; 4386 static const struct intr_info sge_int4_info = { 4387 .name = "SGE_INT_CAUSE4", 4388 .cause_reg = A_SGE_INT_CAUSE4, 4389 .enable_reg = A_SGE_INT_ENABLE4, 4390 .fatal = 0, 4391 .flags = 0, 4392 .details = NULL, 4393 .actions = NULL, 4394 }; 4395 static const struct intr_info sge_int5_info = { 4396 .name = "SGE_INT_CAUSE5", 4397 .cause_reg = A_SGE_INT_CAUSE5, 4398 .enable_reg = A_SGE_INT_ENABLE5, 4399 .fatal = 0xffffffff, 4400 .flags = NONFATAL_IF_DISABLED, 4401 .details = NULL, 4402 .actions = NULL, 4403 }; 4404 static const struct intr_info sge_int6_info = { 4405 .name = "SGE_INT_CAUSE6", 4406 .cause_reg = A_SGE_INT_CAUSE6, 4407 .enable_reg = A_SGE_INT_ENABLE6, 4408 .fatal = 0, 4409 .flags = 0, 4410 .details = NULL, 4411 .actions = NULL, 4412 }; 4413 4414 bool fatal; 4415 u32 v; 4416 4417 if (chip_id(adap) <= CHELSIO_T5) { 4418 sge_int3_info.details = sge_int3_details; 4419 } else { 4420 sge_int3_info.details = t6_sge_int3_details; 4421 } 4422 4423 fatal = false; 4424 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4425 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4426 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4427 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4428 if (chip_id(adap) >= CHELSIO_T5) 4429 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4430 if (chip_id(adap) >= CHELSIO_T6) 4431 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4432 4433 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4434 if (v & F_ERROR_QID_VALID) { 4435 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4436 if (v & F_UNCAPTURED_ERROR) 4437 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4438 t4_write_reg(adap, A_SGE_ERROR_STATS, 4439 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4440 } 4441 4442 return (fatal); 4443 } 4444 4445 /* 4446 * CIM interrupt handler. 4447 */ 4448 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4449 { 4450 static const struct intr_action cim_host_intr_actions[] = { 4451 { F_TIMER0INT, 0, t4_os_dump_cimla }, 4452 { 0 }, 4453 }; 4454 static const struct intr_details cim_host_intr_details[] = { 4455 /* T6+ */ 4456 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4457 4458 /* T5+ */ 4459 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4460 { F_PLCIM_MSTRSPDATAPARERR, 4461 "PL2CIM master response data parity error" }, 4462 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4463 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4464 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4465 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4466 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4467 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4468 4469 /* T4+ */ 4470 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4471 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4472 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4473 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4474 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4475 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4476 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4477 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4478 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4479 "CIM IBQ PCIe/SGE_HI parity error" }, 4480 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4481 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4482 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4483 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4484 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4485 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4486 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4487 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4488 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4489 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4490 { 0} 4491 }; 4492 static const struct intr_info cim_host_intr_info = { 4493 .name = "CIM_HOST_INT_CAUSE", 4494 .cause_reg = A_CIM_HOST_INT_CAUSE, 4495 .enable_reg = A_CIM_HOST_INT_ENABLE, 4496 .fatal = 0x007fffe6, 4497 .flags = NONFATAL_IF_DISABLED, 4498 .details = cim_host_intr_details, 4499 .actions = cim_host_intr_actions, 4500 }; 4501 static const struct intr_details cim_host_upacc_intr_details[] = { 4502 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4503 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4504 { F_TIMEOUTINT, "CIM PIF timeout" }, 4505 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4506 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4507 { F_BLKWRPLINT, "CIM block write to PL space" }, 4508 { F_BLKRDPLINT, "CIM block read from PL space" }, 4509 { F_SGLWRPLINT, 4510 "CIM single write to PL space with illegal BEs" }, 4511 { F_SGLRDPLINT, 4512 "CIM single read from PL space with illegal BEs" }, 4513 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4514 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4515 { F_SGLWRCTLINT, 4516 "CIM single write to CTL space with illegal BEs" }, 4517 { F_SGLRDCTLINT, 4518 "CIM single read from CTL space with illegal BEs" }, 4519 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4520 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4521 { F_SGLWREEPROMINT, 4522 "CIM single write to EEPROM space with illegal BEs" }, 4523 { F_SGLRDEEPROMINT, 4524 "CIM single read from EEPROM space with illegal BEs" }, 4525 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4526 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4527 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4528 { F_SGLRDFLASHINT, 4529 "CIM single read from flash space with illegal BEs" }, 4530 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4531 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4532 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4533 { F_SGLRDBOOTINT, 4534 "CIM single read from boot space with illegal BEs" }, 4535 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4536 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4537 { F_ILLRDINT, "CIM illegal read" }, 4538 { F_ILLWRINT, "CIM illegal write" }, 4539 { F_ILLTRANSINT, "CIM illegal transaction" }, 4540 { F_RSVDSPACEINT, "CIM reserved space access" }, 4541 {0} 4542 }; 4543 static const struct intr_info cim_host_upacc_intr_info = { 4544 .name = "CIM_HOST_UPACC_INT_CAUSE", 4545 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4546 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4547 .fatal = 0x3fffeeff, 4548 .flags = NONFATAL_IF_DISABLED, 4549 .details = cim_host_upacc_intr_details, 4550 .actions = NULL, 4551 }; 4552 static const struct intr_info cim_pf_host_intr_info = { 4553 .name = "CIM_PF_HOST_INT_CAUSE", 4554 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4555 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4556 .fatal = 0, 4557 .flags = 0, 4558 .details = NULL, 4559 .actions = NULL, 4560 }; 4561 u32 val, fw_err; 4562 bool fatal; 4563 4564 fw_err = t4_read_reg(adap, A_PCIE_FW); 4565 if (fw_err & F_PCIE_FW_ERR) 4566 t4_report_fw_error(adap); 4567 4568 /* 4569 * When the Firmware detects an internal error which normally wouldn't 4570 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4571 * to make sure the Host sees the Firmware Crash. So if we have a 4572 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4573 * interrupt. 4574 */ 4575 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4576 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4577 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4578 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4579 } 4580 4581 fatal = false; 4582 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4583 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4584 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4585 4586 return (fatal); 4587 } 4588 4589 /* 4590 * ULP RX interrupt handler. 4591 */ 4592 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4593 { 4594 static const struct intr_details ulprx_intr_details[] = { 4595 /* T5+ */ 4596 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4597 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4598 4599 /* T4+ */ 4600 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4601 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4602 { 0x007fffff, "ULPRX parity error" }, 4603 { 0 } 4604 }; 4605 static const struct intr_info ulprx_intr_info = { 4606 .name = "ULP_RX_INT_CAUSE", 4607 .cause_reg = A_ULP_RX_INT_CAUSE, 4608 .enable_reg = A_ULP_RX_INT_ENABLE, 4609 .fatal = 0x07ffffff, 4610 .flags = NONFATAL_IF_DISABLED, 4611 .details = ulprx_intr_details, 4612 .actions = NULL, 4613 }; 4614 static const struct intr_info ulprx_intr2_info = { 4615 .name = "ULP_RX_INT_CAUSE_2", 4616 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4617 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4618 .fatal = 0, 4619 .flags = 0, 4620 .details = NULL, 4621 .actions = NULL, 4622 }; 4623 bool fatal = false; 4624 4625 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4626 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4627 4628 return (fatal); 4629 } 4630 4631 /* 4632 * ULP TX interrupt handler. 4633 */ 4634 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4635 { 4636 static const struct intr_details ulptx_intr_details[] = { 4637 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4638 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4639 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4640 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4641 { 0x0fffffff, "ULPTX parity error" }, 4642 { 0 } 4643 }; 4644 static const struct intr_info ulptx_intr_info = { 4645 .name = "ULP_TX_INT_CAUSE", 4646 .cause_reg = A_ULP_TX_INT_CAUSE, 4647 .enable_reg = A_ULP_TX_INT_ENABLE, 4648 .fatal = 0x0fffffff, 4649 .flags = NONFATAL_IF_DISABLED, 4650 .details = ulptx_intr_details, 4651 .actions = NULL, 4652 }; 4653 static const struct intr_info ulptx_intr2_info = { 4654 .name = "ULP_TX_INT_CAUSE_2", 4655 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4656 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4657 .fatal = 0xf0, 4658 .flags = NONFATAL_IF_DISABLED, 4659 .details = NULL, 4660 .actions = NULL, 4661 }; 4662 bool fatal = false; 4663 4664 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4665 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4666 4667 return (fatal); 4668 } 4669 4670 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4671 { 4672 int i; 4673 u32 data[17]; 4674 4675 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4676 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4677 for (i = 0; i < ARRAY_SIZE(data); i++) { 4678 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4679 A_PM_TX_DBG_STAT0 + i, data[i]); 4680 } 4681 4682 return (false); 4683 } 4684 4685 /* 4686 * PM TX interrupt handler. 4687 */ 4688 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4689 { 4690 static const struct intr_action pmtx_intr_actions[] = { 4691 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4692 { 0 }, 4693 }; 4694 static const struct intr_details pmtx_intr_details[] = { 4695 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4696 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4697 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4698 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4699 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4700 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4701 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4702 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4703 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4704 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4705 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4706 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4707 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4708 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4709 { 0 } 4710 }; 4711 static const struct intr_info pmtx_intr_info = { 4712 .name = "PM_TX_INT_CAUSE", 4713 .cause_reg = A_PM_TX_INT_CAUSE, 4714 .enable_reg = A_PM_TX_INT_ENABLE, 4715 .fatal = 0xffffffff, 4716 .flags = 0, 4717 .details = pmtx_intr_details, 4718 .actions = pmtx_intr_actions, 4719 }; 4720 4721 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4722 } 4723 4724 /* 4725 * PM RX interrupt handler. 4726 */ 4727 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4728 { 4729 static const struct intr_details pmrx_intr_details[] = { 4730 /* T6+ */ 4731 { 0x18000000, "PMRX ospi overflow" }, 4732 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4733 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4734 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4735 { F_SDC_ERR, "PMRX SDC error" }, 4736 4737 /* T4+ */ 4738 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4739 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4740 { 0x0003c000, "PMRX iespi Rx framing error" }, 4741 { 0x00003c00, "PMRX iespi Tx framing error" }, 4742 { 0x00000300, "PMRX ocspi Rx framing error" }, 4743 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4744 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4745 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4746 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4747 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4748 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4749 { 0 } 4750 }; 4751 static const struct intr_info pmrx_intr_info = { 4752 .name = "PM_RX_INT_CAUSE", 4753 .cause_reg = A_PM_RX_INT_CAUSE, 4754 .enable_reg = A_PM_RX_INT_ENABLE, 4755 .fatal = 0x1fffffff, 4756 .flags = NONFATAL_IF_DISABLED, 4757 .details = pmrx_intr_details, 4758 .actions = NULL, 4759 }; 4760 4761 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4762 } 4763 4764 /* 4765 * CPL switch interrupt handler. 4766 */ 4767 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4768 { 4769 static const struct intr_details cplsw_intr_details[] = { 4770 /* T5+ */ 4771 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4772 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4773 4774 /* T4+ */ 4775 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4776 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4777 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4778 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4779 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4780 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4781 { 0 } 4782 }; 4783 static const struct intr_info cplsw_intr_info = { 4784 .name = "CPL_INTR_CAUSE", 4785 .cause_reg = A_CPL_INTR_CAUSE, 4786 .enable_reg = A_CPL_INTR_ENABLE, 4787 .fatal = 0xff, 4788 .flags = NONFATAL_IF_DISABLED, 4789 .details = cplsw_intr_details, 4790 .actions = NULL, 4791 }; 4792 4793 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4794 } 4795 4796 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4797 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4798 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4799 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4800 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4801 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4802 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4803 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4804 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4805 4806 /* 4807 * LE interrupt handler. 4808 */ 4809 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4810 { 4811 static const struct intr_details le_intr_details[] = { 4812 { F_REQQPARERR, "LE request queue parity error" }, 4813 { F_UNKNOWNCMD, "LE unknown command" }, 4814 { F_ACTRGNFULL, "LE active region full" }, 4815 { F_PARITYERR, "LE parity error" }, 4816 { F_LIPMISS, "LE LIP miss" }, 4817 { F_LIP0, "LE 0 LIP error" }, 4818 { 0 } 4819 }; 4820 static const struct intr_details t6_le_intr_details[] = { 4821 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4822 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4823 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4824 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4825 { F_TOTCNTERR, "LE total active < TCAM count" }, 4826 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4827 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4828 { F_T6_ACTRGNFULL, "LE active region full" }, 4829 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4830 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4831 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4832 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4833 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4834 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4835 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4836 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4837 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4838 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4839 { 0 } 4840 }; 4841 struct intr_info le_intr_info = { 4842 .name = "LE_DB_INT_CAUSE", 4843 .cause_reg = A_LE_DB_INT_CAUSE, 4844 .enable_reg = A_LE_DB_INT_ENABLE, 4845 .fatal = 0, 4846 .flags = NONFATAL_IF_DISABLED, 4847 .details = NULL, 4848 .actions = NULL, 4849 }; 4850 4851 if (chip_id(adap) <= CHELSIO_T5) { 4852 le_intr_info.details = le_intr_details; 4853 le_intr_info.fatal = T5_LE_FATAL_MASK; 4854 } else { 4855 le_intr_info.details = t6_le_intr_details; 4856 le_intr_info.fatal = T6_LE_FATAL_MASK; 4857 } 4858 4859 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4860 } 4861 4862 /* 4863 * MPS interrupt handler. 4864 */ 4865 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4866 { 4867 static const struct intr_details mps_rx_perr_intr_details[] = { 4868 { 0xffffffff, "MPS Rx parity error" }, 4869 { 0 } 4870 }; 4871 static const struct intr_info mps_rx_perr_intr_info = { 4872 .name = "MPS_RX_PERR_INT_CAUSE", 4873 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4874 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4875 .fatal = 0xffffffff, 4876 .flags = NONFATAL_IF_DISABLED, 4877 .details = mps_rx_perr_intr_details, 4878 .actions = NULL, 4879 }; 4880 static const struct intr_details mps_tx_intr_details[] = { 4881 { F_PORTERR, "MPS Tx destination port is disabled" }, 4882 { F_FRMERR, "MPS Tx framing error" }, 4883 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4884 { F_BUBBLE, "MPS Tx underflow" }, 4885 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4886 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4887 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4888 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4889 { 0 } 4890 }; 4891 static const struct intr_info mps_tx_intr_info = { 4892 .name = "MPS_TX_INT_CAUSE", 4893 .cause_reg = A_MPS_TX_INT_CAUSE, 4894 .enable_reg = A_MPS_TX_INT_ENABLE, 4895 .fatal = 0x1ffff, 4896 .flags = NONFATAL_IF_DISABLED, 4897 .details = mps_tx_intr_details, 4898 .actions = NULL, 4899 }; 4900 static const struct intr_details mps_trc_intr_details[] = { 4901 { F_MISCPERR, "MPS TRC misc parity error" }, 4902 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4903 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4904 { 0 } 4905 }; 4906 static const struct intr_info mps_trc_intr_info = { 4907 .name = "MPS_TRC_INT_CAUSE", 4908 .cause_reg = A_MPS_TRC_INT_CAUSE, 4909 .enable_reg = A_MPS_TRC_INT_ENABLE, 4910 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4911 .flags = 0, 4912 .details = mps_trc_intr_details, 4913 .actions = NULL, 4914 }; 4915 static const struct intr_details mps_stat_sram_intr_details[] = { 4916 { 0xffffffff, "MPS statistics SRAM parity error" }, 4917 { 0 } 4918 }; 4919 static const struct intr_info mps_stat_sram_intr_info = { 4920 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4921 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4922 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4923 .fatal = 0x1fffffff, 4924 .flags = NONFATAL_IF_DISABLED, 4925 .details = mps_stat_sram_intr_details, 4926 .actions = NULL, 4927 }; 4928 static const struct intr_details mps_stat_tx_intr_details[] = { 4929 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4930 { 0 } 4931 }; 4932 static const struct intr_info mps_stat_tx_intr_info = { 4933 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4934 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4935 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4936 .fatal = 0xffffff, 4937 .flags = NONFATAL_IF_DISABLED, 4938 .details = mps_stat_tx_intr_details, 4939 .actions = NULL, 4940 }; 4941 static const struct intr_details mps_stat_rx_intr_details[] = { 4942 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4943 { 0 } 4944 }; 4945 static const struct intr_info mps_stat_rx_intr_info = { 4946 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4947 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4948 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4949 .fatal = 0xffffff, 4950 .flags = 0, 4951 .details = mps_stat_rx_intr_details, 4952 .actions = NULL, 4953 }; 4954 static const struct intr_details mps_cls_intr_details[] = { 4955 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4956 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4957 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4958 { 0 } 4959 }; 4960 static const struct intr_info mps_cls_intr_info = { 4961 .name = "MPS_CLS_INT_CAUSE", 4962 .cause_reg = A_MPS_CLS_INT_CAUSE, 4963 .enable_reg = A_MPS_CLS_INT_ENABLE, 4964 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4965 .flags = 0, 4966 .details = mps_cls_intr_details, 4967 .actions = NULL, 4968 }; 4969 static const struct intr_details mps_stat_sram1_intr_details[] = { 4970 { 0xff, "MPS statistics SRAM1 parity error" }, 4971 { 0 } 4972 }; 4973 static const struct intr_info mps_stat_sram1_intr_info = { 4974 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4975 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4976 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4977 .fatal = 0xff, 4978 .flags = 0, 4979 .details = mps_stat_sram1_intr_details, 4980 .actions = NULL, 4981 }; 4982 4983 bool fatal; 4984 4985 fatal = false; 4986 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 4987 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 4988 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 4989 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 4990 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 4991 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 4992 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 4993 if (chip_id(adap) > CHELSIO_T4) { 4994 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 4995 verbose); 4996 } 4997 4998 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 4999 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 5000 5001 return (fatal); 5002 5003 } 5004 5005 /* 5006 * EDC/MC interrupt handler. 5007 */ 5008 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 5009 { 5010 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 5011 unsigned int count_reg, v; 5012 static const struct intr_details mem_intr_details[] = { 5013 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 5014 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 5015 { F_PERR_INT_CAUSE, "FIFO parity error" }, 5016 { 0 } 5017 }; 5018 struct intr_info ii = { 5019 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 5020 .details = mem_intr_details, 5021 .flags = 0, 5022 .actions = NULL, 5023 }; 5024 bool fatal; 5025 5026 switch (idx) { 5027 case MEM_EDC0: 5028 ii.name = "EDC0_INT_CAUSE"; 5029 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 5030 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 5031 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 5032 break; 5033 case MEM_EDC1: 5034 ii.name = "EDC1_INT_CAUSE"; 5035 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 5036 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 5037 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 5038 break; 5039 case MEM_MC0: 5040 ii.name = "MC0_INT_CAUSE"; 5041 if (is_t4(adap)) { 5042 ii.cause_reg = A_MC_INT_CAUSE; 5043 ii.enable_reg = A_MC_INT_ENABLE; 5044 count_reg = A_MC_ECC_STATUS; 5045 } else { 5046 ii.cause_reg = A_MC_P_INT_CAUSE; 5047 ii.enable_reg = A_MC_P_INT_ENABLE; 5048 count_reg = A_MC_P_ECC_STATUS; 5049 } 5050 break; 5051 case MEM_MC1: 5052 ii.name = "MC1_INT_CAUSE"; 5053 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 5054 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 5055 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 5056 break; 5057 } 5058 5059 fatal = t4_handle_intr(adap, &ii, 0, verbose); 5060 5061 v = t4_read_reg(adap, count_reg); 5062 if (v != 0) { 5063 if (G_ECC_UECNT(v) != 0) { 5064 CH_ALERT(adap, 5065 "%s: %u uncorrectable ECC data error(s)\n", 5066 name[idx], G_ECC_UECNT(v)); 5067 } 5068 if (G_ECC_CECNT(v) != 0) { 5069 if (idx <= MEM_EDC1) 5070 t4_edc_err_read(adap, idx); 5071 CH_WARN_RATELIMIT(adap, 5072 "%s: %u correctable ECC data error(s)\n", 5073 name[idx], G_ECC_CECNT(v)); 5074 } 5075 t4_write_reg(adap, count_reg, 0xffffffff); 5076 } 5077 5078 return (fatal); 5079 } 5080 5081 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5082 { 5083 u32 v; 5084 5085 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5086 CH_ALERT(adap, 5087 "MA address wrap-around error by client %u to address %#x\n", 5088 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5089 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5090 5091 return (false); 5092 } 5093 5094 5095 /* 5096 * MA interrupt handler. 5097 */ 5098 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5099 { 5100 static const struct intr_action ma_intr_actions[] = { 5101 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5102 { 0 }, 5103 }; 5104 static const struct intr_info ma_intr_info = { 5105 .name = "MA_INT_CAUSE", 5106 .cause_reg = A_MA_INT_CAUSE, 5107 .enable_reg = A_MA_INT_ENABLE, 5108 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5109 .flags = NONFATAL_IF_DISABLED, 5110 .details = NULL, 5111 .actions = ma_intr_actions, 5112 }; 5113 static const struct intr_info ma_perr_status1 = { 5114 .name = "MA_PARITY_ERROR_STATUS1", 5115 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5116 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5117 .fatal = 0xffffffff, 5118 .flags = 0, 5119 .details = NULL, 5120 .actions = NULL, 5121 }; 5122 static const struct intr_info ma_perr_status2 = { 5123 .name = "MA_PARITY_ERROR_STATUS2", 5124 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5125 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5126 .fatal = 0xffffffff, 5127 .flags = 0, 5128 .details = NULL, 5129 .actions = NULL, 5130 }; 5131 bool fatal; 5132 5133 fatal = false; 5134 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5135 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5136 if (chip_id(adap) > CHELSIO_T4) 5137 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5138 5139 return (fatal); 5140 } 5141 5142 /* 5143 * SMB interrupt handler. 5144 */ 5145 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5146 { 5147 static const struct intr_details smb_intr_details[] = { 5148 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5149 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5150 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5151 { 0 } 5152 }; 5153 static const struct intr_info smb_intr_info = { 5154 .name = "SMB_INT_CAUSE", 5155 .cause_reg = A_SMB_INT_CAUSE, 5156 .enable_reg = A_SMB_INT_ENABLE, 5157 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5158 .flags = 0, 5159 .details = smb_intr_details, 5160 .actions = NULL, 5161 }; 5162 5163 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5164 } 5165 5166 /* 5167 * NC-SI interrupt handler. 5168 */ 5169 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5170 { 5171 static const struct intr_details ncsi_intr_details[] = { 5172 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5173 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5174 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5175 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5176 { 0 } 5177 }; 5178 static const struct intr_info ncsi_intr_info = { 5179 .name = "NCSI_INT_CAUSE", 5180 .cause_reg = A_NCSI_INT_CAUSE, 5181 .enable_reg = A_NCSI_INT_ENABLE, 5182 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5183 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5184 .flags = 0, 5185 .details = ncsi_intr_details, 5186 .actions = NULL, 5187 }; 5188 5189 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5190 } 5191 5192 /* 5193 * MAC interrupt handler. 5194 */ 5195 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5196 { 5197 static const struct intr_details mac_intr_details[] = { 5198 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5199 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5200 { 0 } 5201 }; 5202 char name[32]; 5203 struct intr_info ii; 5204 bool fatal = false; 5205 5206 if (is_t4(adap)) { 5207 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5208 ii.name = &name[0]; 5209 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5210 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5211 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5212 ii.flags = 0; 5213 ii.details = mac_intr_details; 5214 ii.actions = NULL; 5215 } else { 5216 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5217 ii.name = &name[0]; 5218 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5219 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5220 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5221 ii.flags = 0; 5222 ii.details = mac_intr_details; 5223 ii.actions = NULL; 5224 } 5225 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5226 5227 if (chip_id(adap) >= CHELSIO_T5) { 5228 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5229 ii.name = &name[0]; 5230 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5231 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5232 ii.fatal = 0; 5233 ii.flags = 0; 5234 ii.details = NULL; 5235 ii.actions = NULL; 5236 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5237 } 5238 5239 if (chip_id(adap) >= CHELSIO_T6) { 5240 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5241 ii.name = &name[0]; 5242 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5243 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5244 ii.fatal = 0; 5245 ii.flags = 0; 5246 ii.details = NULL; 5247 ii.actions = NULL; 5248 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5249 } 5250 5251 return (fatal); 5252 } 5253 5254 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5255 { 5256 static const struct intr_details plpl_intr_details[] = { 5257 { F_FATALPERR, "Fatal parity error" }, 5258 { F_PERRVFID, "VFID_MAP parity error" }, 5259 { 0 } 5260 }; 5261 static const struct intr_info plpl_intr_info = { 5262 .name = "PL_PL_INT_CAUSE", 5263 .cause_reg = A_PL_PL_INT_CAUSE, 5264 .enable_reg = A_PL_PL_INT_ENABLE, 5265 .fatal = F_FATALPERR | F_PERRVFID, 5266 .flags = NONFATAL_IF_DISABLED, 5267 .details = plpl_intr_details, 5268 .actions = NULL, 5269 }; 5270 5271 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5272 } 5273 5274 /** 5275 * t4_slow_intr_handler - control path interrupt handler 5276 * @adap: the adapter 5277 * @verbose: increased verbosity, for debug 5278 * 5279 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5280 * The designation 'slow' is because it involves register reads, while 5281 * data interrupts typically don't involve any MMIOs. 5282 */ 5283 int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5284 { 5285 static const struct intr_details pl_intr_details[] = { 5286 { F_MC1, "MC1" }, 5287 { F_UART, "UART" }, 5288 { F_ULP_TX, "ULP TX" }, 5289 { F_SGE, "SGE" }, 5290 { F_HMA, "HMA" }, 5291 { F_CPL_SWITCH, "CPL Switch" }, 5292 { F_ULP_RX, "ULP RX" }, 5293 { F_PM_RX, "PM RX" }, 5294 { F_PM_TX, "PM TX" }, 5295 { F_MA, "MA" }, 5296 { F_TP, "TP" }, 5297 { F_LE, "LE" }, 5298 { F_EDC1, "EDC1" }, 5299 { F_EDC0, "EDC0" }, 5300 { F_MC, "MC0" }, 5301 { F_PCIE, "PCIE" }, 5302 { F_PMU, "PMU" }, 5303 { F_MAC3, "MAC3" }, 5304 { F_MAC2, "MAC2" }, 5305 { F_MAC1, "MAC1" }, 5306 { F_MAC0, "MAC0" }, 5307 { F_SMB, "SMB" }, 5308 { F_SF, "SF" }, 5309 { F_PL, "PL" }, 5310 { F_NCSI, "NC-SI" }, 5311 { F_MPS, "MPS" }, 5312 { F_MI, "MI" }, 5313 { F_DBG, "DBG" }, 5314 { F_I2CM, "I2CM" }, 5315 { F_CIM, "CIM" }, 5316 { 0 } 5317 }; 5318 static const struct intr_info pl_perr_cause = { 5319 .name = "PL_PERR_CAUSE", 5320 .cause_reg = A_PL_PERR_CAUSE, 5321 .enable_reg = A_PL_PERR_ENABLE, 5322 .fatal = 0xffffffff, 5323 .flags = 0, 5324 .details = pl_intr_details, 5325 .actions = NULL, 5326 }; 5327 static const struct intr_action pl_intr_action[] = { 5328 { F_MC1, MEM_MC1, mem_intr_handler }, 5329 { F_ULP_TX, -1, ulptx_intr_handler }, 5330 { F_SGE, -1, sge_intr_handler }, 5331 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5332 { F_ULP_RX, -1, ulprx_intr_handler }, 5333 { F_PM_RX, -1, pmrx_intr_handler}, 5334 { F_PM_TX, -1, pmtx_intr_handler}, 5335 { F_MA, -1, ma_intr_handler }, 5336 { F_TP, -1, tp_intr_handler }, 5337 { F_LE, -1, le_intr_handler }, 5338 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5339 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5340 { F_MC0, MEM_MC0, mem_intr_handler }, 5341 { F_PCIE, -1, pcie_intr_handler }, 5342 { F_MAC3, 3, mac_intr_handler}, 5343 { F_MAC2, 2, mac_intr_handler}, 5344 { F_MAC1, 1, mac_intr_handler}, 5345 { F_MAC0, 0, mac_intr_handler}, 5346 { F_SMB, -1, smb_intr_handler}, 5347 { F_PL, -1, plpl_intr_handler }, 5348 { F_NCSI, -1, ncsi_intr_handler}, 5349 { F_MPS, -1, mps_intr_handler }, 5350 { F_CIM, -1, cim_intr_handler }, 5351 { 0 } 5352 }; 5353 static const struct intr_info pl_intr_info = { 5354 .name = "PL_INT_CAUSE", 5355 .cause_reg = A_PL_INT_CAUSE, 5356 .enable_reg = A_PL_INT_ENABLE, 5357 .fatal = 0, 5358 .flags = 0, 5359 .details = pl_intr_details, 5360 .actions = pl_intr_action, 5361 }; 5362 bool fatal; 5363 u32 perr; 5364 5365 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5366 if (verbose || perr != 0) { 5367 t4_show_intr_info(adap, &pl_perr_cause, perr); 5368 if (perr != 0) 5369 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5370 if (verbose) 5371 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5372 } 5373 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5374 if (fatal) 5375 t4_fatal_err(adap, false); 5376 5377 return (0); 5378 } 5379 5380 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5381 5382 /** 5383 * t4_intr_enable - enable interrupts 5384 * @adapter: the adapter whose interrupts should be enabled 5385 * 5386 * Enable PF-specific interrupts for the calling function and the top-level 5387 * interrupt concentrator for global interrupts. Interrupts are already 5388 * enabled at each module, here we just enable the roots of the interrupt 5389 * hierarchies. 5390 * 5391 * Note: this function should be called only when the driver manages 5392 * non PF-specific interrupts from the various HW modules. Only one PCI 5393 * function at a time should be doing this. 5394 */ 5395 void t4_intr_enable(struct adapter *adap) 5396 { 5397 u32 val = 0; 5398 5399 if (chip_id(adap) <= CHELSIO_T5) 5400 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5401 else 5402 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5403 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5404 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5405 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5406 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5407 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5408 F_EGRESS_SIZE_ERR; 5409 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5410 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5411 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5412 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5413 } 5414 5415 /** 5416 * t4_intr_disable - disable interrupts 5417 * @adap: the adapter whose interrupts should be disabled 5418 * 5419 * Disable interrupts. We only disable the top-level interrupt 5420 * concentrators. The caller must be a PCI function managing global 5421 * interrupts. 5422 */ 5423 void t4_intr_disable(struct adapter *adap) 5424 { 5425 5426 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5427 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5428 } 5429 5430 /** 5431 * t4_intr_clear - clear all interrupts 5432 * @adap: the adapter whose interrupts should be cleared 5433 * 5434 * Clears all interrupts. The caller must be a PCI function managing 5435 * global interrupts. 5436 */ 5437 void t4_intr_clear(struct adapter *adap) 5438 { 5439 static const u32 cause_reg[] = { 5440 A_CIM_HOST_INT_CAUSE, 5441 A_CIM_HOST_UPACC_INT_CAUSE, 5442 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5443 A_CPL_INTR_CAUSE, 5444 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5445 A_LE_DB_INT_CAUSE, 5446 A_MA_INT_WRAP_STATUS, 5447 A_MA_PARITY_ERROR_STATUS1, 5448 A_MA_INT_CAUSE, 5449 A_MPS_CLS_INT_CAUSE, 5450 A_MPS_RX_PERR_INT_CAUSE, 5451 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5452 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5453 A_MPS_TRC_INT_CAUSE, 5454 A_MPS_TX_INT_CAUSE, 5455 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5456 A_NCSI_INT_CAUSE, 5457 A_PCIE_INT_CAUSE, 5458 A_PCIE_NONFAT_ERR, 5459 A_PL_PL_INT_CAUSE, 5460 A_PM_RX_INT_CAUSE, 5461 A_PM_TX_INT_CAUSE, 5462 A_SGE_INT_CAUSE1, 5463 A_SGE_INT_CAUSE2, 5464 A_SGE_INT_CAUSE3, 5465 A_SGE_INT_CAUSE4, 5466 A_SMB_INT_CAUSE, 5467 A_TP_INT_CAUSE, 5468 A_ULP_RX_INT_CAUSE, 5469 A_ULP_RX_INT_CAUSE_2, 5470 A_ULP_TX_INT_CAUSE, 5471 A_ULP_TX_INT_CAUSE_2, 5472 5473 MYPF_REG(A_PL_PF_INT_CAUSE), 5474 }; 5475 int i; 5476 const int nchan = adap->chip_params->nchan; 5477 5478 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5479 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5480 5481 if (is_t4(adap)) { 5482 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5483 0xffffffff); 5484 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5485 0xffffffff); 5486 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5487 for (i = 0; i < nchan; i++) { 5488 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5489 0xffffffff); 5490 } 5491 } 5492 if (chip_id(adap) >= CHELSIO_T5) { 5493 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5494 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5495 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5496 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5497 if (is_t5(adap)) { 5498 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5499 0xffffffff); 5500 } 5501 for (i = 0; i < nchan; i++) { 5502 t4_write_reg(adap, T5_PORT_REG(i, 5503 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5504 if (chip_id(adap) > CHELSIO_T5) { 5505 t4_write_reg(adap, T5_PORT_REG(i, 5506 A_MAC_PORT_PERR_INT_CAUSE_100G), 5507 0xffffffff); 5508 } 5509 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5510 0xffffffff); 5511 } 5512 } 5513 if (chip_id(adap) >= CHELSIO_T6) { 5514 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5515 } 5516 5517 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5518 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5519 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5520 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5521 } 5522 5523 /** 5524 * hash_mac_addr - return the hash value of a MAC address 5525 * @addr: the 48-bit Ethernet MAC address 5526 * 5527 * Hashes a MAC address according to the hash function used by HW inexact 5528 * (hash) address matching. 5529 */ 5530 static int hash_mac_addr(const u8 *addr) 5531 { 5532 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5533 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5534 a ^= b; 5535 a ^= (a >> 12); 5536 a ^= (a >> 6); 5537 return a & 0x3f; 5538 } 5539 5540 /** 5541 * t4_config_rss_range - configure a portion of the RSS mapping table 5542 * @adapter: the adapter 5543 * @mbox: mbox to use for the FW command 5544 * @viid: virtual interface whose RSS subtable is to be written 5545 * @start: start entry in the table to write 5546 * @n: how many table entries to write 5547 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5548 * @nrspq: number of values in @rspq 5549 * 5550 * Programs the selected part of the VI's RSS mapping table with the 5551 * provided values. If @nrspq < @n the supplied values are used repeatedly 5552 * until the full table range is populated. 5553 * 5554 * The caller must ensure the values in @rspq are in the range allowed for 5555 * @viid. 5556 */ 5557 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5558 int start, int n, const u16 *rspq, unsigned int nrspq) 5559 { 5560 int ret; 5561 const u16 *rsp = rspq; 5562 const u16 *rsp_end = rspq + nrspq; 5563 struct fw_rss_ind_tbl_cmd cmd; 5564 5565 memset(&cmd, 0, sizeof(cmd)); 5566 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5567 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5568 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5569 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5570 5571 /* 5572 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5573 * Queue Identifiers. These Ingress Queue IDs are packed three to 5574 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5575 * reserved. 5576 */ 5577 while (n > 0) { 5578 int nq = min(n, 32); 5579 int nq_packed = 0; 5580 __be32 *qp = &cmd.iq0_to_iq2; 5581 5582 /* 5583 * Set up the firmware RSS command header to send the next 5584 * "nq" Ingress Queue IDs to the firmware. 5585 */ 5586 cmd.niqid = cpu_to_be16(nq); 5587 cmd.startidx = cpu_to_be16(start); 5588 5589 /* 5590 * "nq" more done for the start of the next loop. 5591 */ 5592 start += nq; 5593 n -= nq; 5594 5595 /* 5596 * While there are still Ingress Queue IDs to stuff into the 5597 * current firmware RSS command, retrieve them from the 5598 * Ingress Queue ID array and insert them into the command. 5599 */ 5600 while (nq > 0) { 5601 /* 5602 * Grab up to the next 3 Ingress Queue IDs (wrapping 5603 * around the Ingress Queue ID array if necessary) and 5604 * insert them into the firmware RSS command at the 5605 * current 3-tuple position within the commad. 5606 */ 5607 u16 qbuf[3]; 5608 u16 *qbp = qbuf; 5609 int nqbuf = min(3, nq); 5610 5611 nq -= nqbuf; 5612 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5613 while (nqbuf && nq_packed < 32) { 5614 nqbuf--; 5615 nq_packed++; 5616 *qbp++ = *rsp++; 5617 if (rsp >= rsp_end) 5618 rsp = rspq; 5619 } 5620 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5621 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5622 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5623 } 5624 5625 /* 5626 * Send this portion of the RRS table update to the firmware; 5627 * bail out on any errors. 5628 */ 5629 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5630 if (ret) 5631 return ret; 5632 } 5633 return 0; 5634 } 5635 5636 /** 5637 * t4_config_glbl_rss - configure the global RSS mode 5638 * @adapter: the adapter 5639 * @mbox: mbox to use for the FW command 5640 * @mode: global RSS mode 5641 * @flags: mode-specific flags 5642 * 5643 * Sets the global RSS mode. 5644 */ 5645 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5646 unsigned int flags) 5647 { 5648 struct fw_rss_glb_config_cmd c; 5649 5650 memset(&c, 0, sizeof(c)); 5651 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5652 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5653 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5654 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5655 c.u.manual.mode_pkd = 5656 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5657 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5658 c.u.basicvirtual.mode_keymode = 5659 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5660 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5661 } else 5662 return -EINVAL; 5663 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5664 } 5665 5666 /** 5667 * t4_config_vi_rss - configure per VI RSS settings 5668 * @adapter: the adapter 5669 * @mbox: mbox to use for the FW command 5670 * @viid: the VI id 5671 * @flags: RSS flags 5672 * @defq: id of the default RSS queue for the VI. 5673 * @skeyidx: RSS secret key table index for non-global mode 5674 * @skey: RSS vf_scramble key for VI. 5675 * 5676 * Configures VI-specific RSS properties. 5677 */ 5678 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5679 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5680 unsigned int skey) 5681 { 5682 struct fw_rss_vi_config_cmd c; 5683 5684 memset(&c, 0, sizeof(c)); 5685 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5686 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5687 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5688 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5689 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5690 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5691 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5692 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5693 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5694 5695 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5696 } 5697 5698 /* Read an RSS table row */ 5699 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5700 { 5701 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5702 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5703 5, 0, val); 5704 } 5705 5706 /** 5707 * t4_read_rss - read the contents of the RSS mapping table 5708 * @adapter: the adapter 5709 * @map: holds the contents of the RSS mapping table 5710 * 5711 * Reads the contents of the RSS hash->queue mapping table. 5712 */ 5713 int t4_read_rss(struct adapter *adapter, u16 *map) 5714 { 5715 u32 val; 5716 int i, ret; 5717 int rss_nentries = adapter->chip_params->rss_nentries; 5718 5719 for (i = 0; i < rss_nentries / 2; ++i) { 5720 ret = rd_rss_row(adapter, i, &val); 5721 if (ret) 5722 return ret; 5723 *map++ = G_LKPTBLQUEUE0(val); 5724 *map++ = G_LKPTBLQUEUE1(val); 5725 } 5726 return 0; 5727 } 5728 5729 /** 5730 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5731 * @adap: the adapter 5732 * @cmd: TP fw ldst address space type 5733 * @vals: where the indirect register values are stored/written 5734 * @nregs: how many indirect registers to read/write 5735 * @start_idx: index of first indirect register to read/write 5736 * @rw: Read (1) or Write (0) 5737 * @sleep_ok: if true we may sleep while awaiting command completion 5738 * 5739 * Access TP indirect registers through LDST 5740 **/ 5741 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5742 unsigned int nregs, unsigned int start_index, 5743 unsigned int rw, bool sleep_ok) 5744 { 5745 int ret = 0; 5746 unsigned int i; 5747 struct fw_ldst_cmd c; 5748 5749 for (i = 0; i < nregs; i++) { 5750 memset(&c, 0, sizeof(c)); 5751 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5752 F_FW_CMD_REQUEST | 5753 (rw ? F_FW_CMD_READ : 5754 F_FW_CMD_WRITE) | 5755 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5756 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5757 5758 c.u.addrval.addr = cpu_to_be32(start_index + i); 5759 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5760 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5761 sleep_ok); 5762 if (ret) 5763 return ret; 5764 5765 if (rw) 5766 vals[i] = be32_to_cpu(c.u.addrval.val); 5767 } 5768 return 0; 5769 } 5770 5771 /** 5772 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5773 * @adap: the adapter 5774 * @reg_addr: Address Register 5775 * @reg_data: Data register 5776 * @buff: where the indirect register values are stored/written 5777 * @nregs: how many indirect registers to read/write 5778 * @start_index: index of first indirect register to read/write 5779 * @rw: READ(1) or WRITE(0) 5780 * @sleep_ok: if true we may sleep while awaiting command completion 5781 * 5782 * Read/Write TP indirect registers through LDST if possible. 5783 * Else, use backdoor access 5784 **/ 5785 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5786 u32 *buff, u32 nregs, u32 start_index, int rw, 5787 bool sleep_ok) 5788 { 5789 int rc = -EINVAL; 5790 int cmd; 5791 5792 switch (reg_addr) { 5793 case A_TP_PIO_ADDR: 5794 cmd = FW_LDST_ADDRSPC_TP_PIO; 5795 break; 5796 case A_TP_TM_PIO_ADDR: 5797 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5798 break; 5799 case A_TP_MIB_INDEX: 5800 cmd = FW_LDST_ADDRSPC_TP_MIB; 5801 break; 5802 default: 5803 goto indirect_access; 5804 } 5805 5806 if (t4_use_ldst(adap)) 5807 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5808 sleep_ok); 5809 5810 indirect_access: 5811 5812 if (rc) { 5813 if (rw) 5814 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5815 start_index); 5816 else 5817 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5818 start_index); 5819 } 5820 } 5821 5822 /** 5823 * t4_tp_pio_read - Read TP PIO registers 5824 * @adap: the adapter 5825 * @buff: where the indirect register values are written 5826 * @nregs: how many indirect registers to read 5827 * @start_index: index of first indirect register to read 5828 * @sleep_ok: if true we may sleep while awaiting command completion 5829 * 5830 * Read TP PIO Registers 5831 **/ 5832 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5833 u32 start_index, bool sleep_ok) 5834 { 5835 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5836 start_index, 1, sleep_ok); 5837 } 5838 5839 /** 5840 * t4_tp_pio_write - Write TP PIO registers 5841 * @adap: the adapter 5842 * @buff: where the indirect register values are stored 5843 * @nregs: how many indirect registers to write 5844 * @start_index: index of first indirect register to write 5845 * @sleep_ok: if true we may sleep while awaiting command completion 5846 * 5847 * Write TP PIO Registers 5848 **/ 5849 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5850 u32 start_index, bool sleep_ok) 5851 { 5852 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5853 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5854 } 5855 5856 /** 5857 * t4_tp_tm_pio_read - Read TP TM PIO registers 5858 * @adap: the adapter 5859 * @buff: where the indirect register values are written 5860 * @nregs: how many indirect registers to read 5861 * @start_index: index of first indirect register to read 5862 * @sleep_ok: if true we may sleep while awaiting command completion 5863 * 5864 * Read TP TM PIO Registers 5865 **/ 5866 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5867 u32 start_index, bool sleep_ok) 5868 { 5869 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5870 nregs, start_index, 1, sleep_ok); 5871 } 5872 5873 /** 5874 * t4_tp_mib_read - Read TP MIB registers 5875 * @adap: the adapter 5876 * @buff: where the indirect register values are written 5877 * @nregs: how many indirect registers to read 5878 * @start_index: index of first indirect register to read 5879 * @sleep_ok: if true we may sleep while awaiting command completion 5880 * 5881 * Read TP MIB Registers 5882 **/ 5883 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5884 bool sleep_ok) 5885 { 5886 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5887 start_index, 1, sleep_ok); 5888 } 5889 5890 /** 5891 * t4_read_rss_key - read the global RSS key 5892 * @adap: the adapter 5893 * @key: 10-entry array holding the 320-bit RSS key 5894 * @sleep_ok: if true we may sleep while awaiting command completion 5895 * 5896 * Reads the global 320-bit RSS key. 5897 */ 5898 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5899 { 5900 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5901 } 5902 5903 /** 5904 * t4_write_rss_key - program one of the RSS keys 5905 * @adap: the adapter 5906 * @key: 10-entry array holding the 320-bit RSS key 5907 * @idx: which RSS key to write 5908 * @sleep_ok: if true we may sleep while awaiting command completion 5909 * 5910 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5911 * 0..15 the corresponding entry in the RSS key table is written, 5912 * otherwise the global RSS key is written. 5913 */ 5914 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5915 bool sleep_ok) 5916 { 5917 u8 rss_key_addr_cnt = 16; 5918 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5919 5920 /* 5921 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5922 * allows access to key addresses 16-63 by using KeyWrAddrX 5923 * as index[5:4](upper 2) into key table 5924 */ 5925 if ((chip_id(adap) > CHELSIO_T5) && 5926 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5927 rss_key_addr_cnt = 32; 5928 5929 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5930 5931 if (idx >= 0 && idx < rss_key_addr_cnt) { 5932 if (rss_key_addr_cnt > 16) 5933 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5934 vrt | V_KEYWRADDRX(idx >> 4) | 5935 V_T6_VFWRADDR(idx) | F_KEYWREN); 5936 else 5937 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5938 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5939 } 5940 } 5941 5942 /** 5943 * t4_read_rss_pf_config - read PF RSS Configuration Table 5944 * @adapter: the adapter 5945 * @index: the entry in the PF RSS table to read 5946 * @valp: where to store the returned value 5947 * @sleep_ok: if true we may sleep while awaiting command completion 5948 * 5949 * Reads the PF RSS Configuration Table at the specified index and returns 5950 * the value found there. 5951 */ 5952 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5953 u32 *valp, bool sleep_ok) 5954 { 5955 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5956 } 5957 5958 /** 5959 * t4_write_rss_pf_config - write PF RSS Configuration Table 5960 * @adapter: the adapter 5961 * @index: the entry in the VF RSS table to read 5962 * @val: the value to store 5963 * @sleep_ok: if true we may sleep while awaiting command completion 5964 * 5965 * Writes the PF RSS Configuration Table at the specified index with the 5966 * specified value. 5967 */ 5968 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5969 u32 val, bool sleep_ok) 5970 { 5971 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5972 sleep_ok); 5973 } 5974 5975 /** 5976 * t4_read_rss_vf_config - read VF RSS Configuration Table 5977 * @adapter: the adapter 5978 * @index: the entry in the VF RSS table to read 5979 * @vfl: where to store the returned VFL 5980 * @vfh: where to store the returned VFH 5981 * @sleep_ok: if true we may sleep while awaiting command completion 5982 * 5983 * Reads the VF RSS Configuration Table at the specified index and returns 5984 * the (VFL, VFH) values found there. 5985 */ 5986 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5987 u32 *vfl, u32 *vfh, bool sleep_ok) 5988 { 5989 u32 vrt, mask, data; 5990 5991 if (chip_id(adapter) <= CHELSIO_T5) { 5992 mask = V_VFWRADDR(M_VFWRADDR); 5993 data = V_VFWRADDR(index); 5994 } else { 5995 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5996 data = V_T6_VFWRADDR(index); 5997 } 5998 /* 5999 * Request that the index'th VF Table values be read into VFL/VFH. 6000 */ 6001 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6002 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6003 vrt |= data | F_VFRDEN; 6004 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6005 6006 /* 6007 * Grab the VFL/VFH values ... 6008 */ 6009 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6010 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6011 } 6012 6013 /** 6014 * t4_write_rss_vf_config - write VF RSS Configuration Table 6015 * 6016 * @adapter: the adapter 6017 * @index: the entry in the VF RSS table to write 6018 * @vfl: the VFL to store 6019 * @vfh: the VFH to store 6020 * 6021 * Writes the VF RSS Configuration Table at the specified index with the 6022 * specified (VFL, VFH) values. 6023 */ 6024 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 6025 u32 vfl, u32 vfh, bool sleep_ok) 6026 { 6027 u32 vrt, mask, data; 6028 6029 if (chip_id(adapter) <= CHELSIO_T5) { 6030 mask = V_VFWRADDR(M_VFWRADDR); 6031 data = V_VFWRADDR(index); 6032 } else { 6033 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6034 data = V_T6_VFWRADDR(index); 6035 } 6036 6037 /* 6038 * Load up VFL/VFH with the values to be written ... 6039 */ 6040 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6041 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6042 6043 /* 6044 * Write the VFL/VFH into the VF Table at index'th location. 6045 */ 6046 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6047 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6048 vrt |= data | F_VFRDEN; 6049 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6050 } 6051 6052 /** 6053 * t4_read_rss_pf_map - read PF RSS Map 6054 * @adapter: the adapter 6055 * @sleep_ok: if true we may sleep while awaiting command completion 6056 * 6057 * Reads the PF RSS Map register and returns its value. 6058 */ 6059 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 6060 { 6061 u32 pfmap; 6062 6063 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6064 6065 return pfmap; 6066 } 6067 6068 /** 6069 * t4_write_rss_pf_map - write PF RSS Map 6070 * @adapter: the adapter 6071 * @pfmap: PF RSS Map value 6072 * 6073 * Writes the specified value to the PF RSS Map register. 6074 */ 6075 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6076 { 6077 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6078 } 6079 6080 /** 6081 * t4_read_rss_pf_mask - read PF RSS Mask 6082 * @adapter: the adapter 6083 * @sleep_ok: if true we may sleep while awaiting command completion 6084 * 6085 * Reads the PF RSS Mask register and returns its value. 6086 */ 6087 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6088 { 6089 u32 pfmask; 6090 6091 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6092 6093 return pfmask; 6094 } 6095 6096 /** 6097 * t4_write_rss_pf_mask - write PF RSS Mask 6098 * @adapter: the adapter 6099 * @pfmask: PF RSS Mask value 6100 * 6101 * Writes the specified value to the PF RSS Mask register. 6102 */ 6103 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6104 { 6105 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6106 } 6107 6108 /** 6109 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6110 * @adap: the adapter 6111 * @v4: holds the TCP/IP counter values 6112 * @v6: holds the TCP/IPv6 counter values 6113 * @sleep_ok: if true we may sleep while awaiting command completion 6114 * 6115 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6116 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6117 */ 6118 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6119 struct tp_tcp_stats *v6, bool sleep_ok) 6120 { 6121 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6122 6123 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6124 #define STAT(x) val[STAT_IDX(x)] 6125 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6126 6127 if (v4) { 6128 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6129 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6130 v4->tcp_out_rsts = STAT(OUT_RST); 6131 v4->tcp_in_segs = STAT64(IN_SEG); 6132 v4->tcp_out_segs = STAT64(OUT_SEG); 6133 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6134 } 6135 if (v6) { 6136 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6137 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6138 v6->tcp_out_rsts = STAT(OUT_RST); 6139 v6->tcp_in_segs = STAT64(IN_SEG); 6140 v6->tcp_out_segs = STAT64(OUT_SEG); 6141 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6142 } 6143 #undef STAT64 6144 #undef STAT 6145 #undef STAT_IDX 6146 } 6147 6148 /** 6149 * t4_tp_get_err_stats - read TP's error MIB counters 6150 * @adap: the adapter 6151 * @st: holds the counter values 6152 * @sleep_ok: if true we may sleep while awaiting command completion 6153 * 6154 * Returns the values of TP's error counters. 6155 */ 6156 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6157 bool sleep_ok) 6158 { 6159 int nchan = adap->chip_params->nchan; 6160 6161 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6162 sleep_ok); 6163 6164 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6165 sleep_ok); 6166 6167 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6168 sleep_ok); 6169 6170 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6171 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6172 6173 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6174 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6175 6176 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6177 sleep_ok); 6178 6179 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6180 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6181 6182 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6183 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6184 6185 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6186 sleep_ok); 6187 } 6188 6189 /** 6190 * t4_tp_get_err_stats - read TP's error MIB counters 6191 * @adap: the adapter 6192 * @st: holds the counter values 6193 * @sleep_ok: if true we may sleep while awaiting command completion 6194 * 6195 * Returns the values of TP's error counters. 6196 */ 6197 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, 6198 bool sleep_ok) 6199 { 6200 int nchan = adap->chip_params->nchan; 6201 6202 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, 6203 sleep_ok); 6204 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, 6205 sleep_ok); 6206 } 6207 6208 /** 6209 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6210 * @adap: the adapter 6211 * @st: holds the counter values 6212 * 6213 * Returns the values of TP's proxy counters. 6214 */ 6215 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6216 bool sleep_ok) 6217 { 6218 int nchan = adap->chip_params->nchan; 6219 6220 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6221 } 6222 6223 /** 6224 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6225 * @adap: the adapter 6226 * @st: holds the counter values 6227 * @sleep_ok: if true we may sleep while awaiting command completion 6228 * 6229 * Returns the values of TP's CPL counters. 6230 */ 6231 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6232 bool sleep_ok) 6233 { 6234 int nchan = adap->chip_params->nchan; 6235 6236 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6237 6238 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6239 } 6240 6241 /** 6242 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6243 * @adap: the adapter 6244 * @st: holds the counter values 6245 * 6246 * Returns the values of TP's RDMA counters. 6247 */ 6248 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6249 bool sleep_ok) 6250 { 6251 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6252 sleep_ok); 6253 } 6254 6255 /** 6256 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6257 * @adap: the adapter 6258 * @idx: the port index 6259 * @st: holds the counter values 6260 * @sleep_ok: if true we may sleep while awaiting command completion 6261 * 6262 * Returns the values of TP's FCoE counters for the selected port. 6263 */ 6264 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6265 struct tp_fcoe_stats *st, bool sleep_ok) 6266 { 6267 u32 val[2]; 6268 6269 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6270 sleep_ok); 6271 6272 t4_tp_mib_read(adap, &st->frames_drop, 1, 6273 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6274 6275 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6276 sleep_ok); 6277 6278 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6279 } 6280 6281 /** 6282 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6283 * @adap: the adapter 6284 * @st: holds the counter values 6285 * @sleep_ok: if true we may sleep while awaiting command completion 6286 * 6287 * Returns the values of TP's counters for non-TCP directly-placed packets. 6288 */ 6289 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6290 bool sleep_ok) 6291 { 6292 u32 val[4]; 6293 6294 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6295 6296 st->frames = val[0]; 6297 st->drops = val[1]; 6298 st->octets = ((u64)val[2] << 32) | val[3]; 6299 } 6300 6301 /** 6302 * t4_tp_get_tid_stats - read TP's tid MIB counters. 6303 * @adap: the adapter 6304 * @st: holds the counter values 6305 * @sleep_ok: if true we may sleep while awaiting command completion 6306 * 6307 * Returns the values of TP's counters for tids. 6308 */ 6309 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, 6310 bool sleep_ok) 6311 { 6312 6313 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); 6314 } 6315 6316 /** 6317 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6318 * @adap: the adapter 6319 * @mtus: where to store the MTU values 6320 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6321 * 6322 * Reads the HW path MTU table. 6323 */ 6324 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6325 { 6326 u32 v; 6327 int i; 6328 6329 for (i = 0; i < NMTUS; ++i) { 6330 t4_write_reg(adap, A_TP_MTU_TABLE, 6331 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6332 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6333 mtus[i] = G_MTUVALUE(v); 6334 if (mtu_log) 6335 mtu_log[i] = G_MTUWIDTH(v); 6336 } 6337 } 6338 6339 /** 6340 * t4_read_cong_tbl - reads the congestion control table 6341 * @adap: the adapter 6342 * @incr: where to store the alpha values 6343 * 6344 * Reads the additive increments programmed into the HW congestion 6345 * control table. 6346 */ 6347 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6348 { 6349 unsigned int mtu, w; 6350 6351 for (mtu = 0; mtu < NMTUS; ++mtu) 6352 for (w = 0; w < NCCTRL_WIN; ++w) { 6353 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6354 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6355 incr[mtu][w] = (u16)t4_read_reg(adap, 6356 A_TP_CCTRL_TABLE) & 0x1fff; 6357 } 6358 } 6359 6360 /** 6361 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6362 * @adap: the adapter 6363 * @addr: the indirect TP register address 6364 * @mask: specifies the field within the register to modify 6365 * @val: new value for the field 6366 * 6367 * Sets a field of an indirect TP register to the given value. 6368 */ 6369 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6370 unsigned int mask, unsigned int val) 6371 { 6372 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6373 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6374 t4_write_reg(adap, A_TP_PIO_DATA, val); 6375 } 6376 6377 /** 6378 * init_cong_ctrl - initialize congestion control parameters 6379 * @a: the alpha values for congestion control 6380 * @b: the beta values for congestion control 6381 * 6382 * Initialize the congestion control parameters. 6383 */ 6384 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6385 { 6386 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6387 a[9] = 2; 6388 a[10] = 3; 6389 a[11] = 4; 6390 a[12] = 5; 6391 a[13] = 6; 6392 a[14] = 7; 6393 a[15] = 8; 6394 a[16] = 9; 6395 a[17] = 10; 6396 a[18] = 14; 6397 a[19] = 17; 6398 a[20] = 21; 6399 a[21] = 25; 6400 a[22] = 30; 6401 a[23] = 35; 6402 a[24] = 45; 6403 a[25] = 60; 6404 a[26] = 80; 6405 a[27] = 100; 6406 a[28] = 200; 6407 a[29] = 300; 6408 a[30] = 400; 6409 a[31] = 500; 6410 6411 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6412 b[9] = b[10] = 1; 6413 b[11] = b[12] = 2; 6414 b[13] = b[14] = b[15] = b[16] = 3; 6415 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6416 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6417 b[28] = b[29] = 6; 6418 b[30] = b[31] = 7; 6419 } 6420 6421 /* The minimum additive increment value for the congestion control table */ 6422 #define CC_MIN_INCR 2U 6423 6424 /** 6425 * t4_load_mtus - write the MTU and congestion control HW tables 6426 * @adap: the adapter 6427 * @mtus: the values for the MTU table 6428 * @alpha: the values for the congestion control alpha parameter 6429 * @beta: the values for the congestion control beta parameter 6430 * 6431 * Write the HW MTU table with the supplied MTUs and the high-speed 6432 * congestion control table with the supplied alpha, beta, and MTUs. 6433 * We write the two tables together because the additive increments 6434 * depend on the MTUs. 6435 */ 6436 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6437 const unsigned short *alpha, const unsigned short *beta) 6438 { 6439 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6440 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6441 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6442 28672, 40960, 57344, 81920, 114688, 163840, 229376 6443 }; 6444 6445 unsigned int i, w; 6446 6447 for (i = 0; i < NMTUS; ++i) { 6448 unsigned int mtu = mtus[i]; 6449 unsigned int log2 = fls(mtu); 6450 6451 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6452 log2--; 6453 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6454 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6455 6456 for (w = 0; w < NCCTRL_WIN; ++w) { 6457 unsigned int inc; 6458 6459 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6460 CC_MIN_INCR); 6461 6462 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6463 (w << 16) | (beta[w] << 13) | inc); 6464 } 6465 } 6466 } 6467 6468 /** 6469 * t4_set_pace_tbl - set the pace table 6470 * @adap: the adapter 6471 * @pace_vals: the pace values in microseconds 6472 * @start: index of the first entry in the HW pace table to set 6473 * @n: how many entries to set 6474 * 6475 * Sets (a subset of the) HW pace table. 6476 */ 6477 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6478 unsigned int start, unsigned int n) 6479 { 6480 unsigned int vals[NTX_SCHED], i; 6481 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6482 6483 if (n > NTX_SCHED) 6484 return -ERANGE; 6485 6486 /* convert values from us to dack ticks, rounding to closest value */ 6487 for (i = 0; i < n; i++, pace_vals++) { 6488 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6489 if (vals[i] > 0x7ff) 6490 return -ERANGE; 6491 if (*pace_vals && vals[i] == 0) 6492 return -ERANGE; 6493 } 6494 for (i = 0; i < n; i++, start++) 6495 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6496 return 0; 6497 } 6498 6499 /** 6500 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6501 * @adap: the adapter 6502 * @kbps: target rate in Kbps 6503 * @sched: the scheduler index 6504 * 6505 * Configure a Tx HW scheduler for the target rate. 6506 */ 6507 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6508 { 6509 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6510 unsigned int clk = adap->params.vpd.cclk * 1000; 6511 unsigned int selected_cpt = 0, selected_bpt = 0; 6512 6513 if (kbps > 0) { 6514 kbps *= 125; /* -> bytes */ 6515 for (cpt = 1; cpt <= 255; cpt++) { 6516 tps = clk / cpt; 6517 bpt = (kbps + tps / 2) / tps; 6518 if (bpt > 0 && bpt <= 255) { 6519 v = bpt * tps; 6520 delta = v >= kbps ? v - kbps : kbps - v; 6521 if (delta < mindelta) { 6522 mindelta = delta; 6523 selected_cpt = cpt; 6524 selected_bpt = bpt; 6525 } 6526 } else if (selected_cpt) 6527 break; 6528 } 6529 if (!selected_cpt) 6530 return -EINVAL; 6531 } 6532 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6533 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6534 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6535 if (sched & 1) 6536 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6537 else 6538 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6539 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6540 return 0; 6541 } 6542 6543 /** 6544 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6545 * @adap: the adapter 6546 * @sched: the scheduler index 6547 * @ipg: the interpacket delay in tenths of nanoseconds 6548 * 6549 * Set the interpacket delay for a HW packet rate scheduler. 6550 */ 6551 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6552 { 6553 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6554 6555 /* convert ipg to nearest number of core clocks */ 6556 ipg *= core_ticks_per_usec(adap); 6557 ipg = (ipg + 5000) / 10000; 6558 if (ipg > M_TXTIMERSEPQ0) 6559 return -EINVAL; 6560 6561 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6562 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6563 if (sched & 1) 6564 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6565 else 6566 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6567 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6568 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6569 return 0; 6570 } 6571 6572 /* 6573 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6574 * clocks. The formula is 6575 * 6576 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6577 * 6578 * which is equivalent to 6579 * 6580 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6581 */ 6582 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6583 { 6584 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6585 6586 return v * 62 + v / 2; 6587 } 6588 6589 /** 6590 * t4_get_chan_txrate - get the current per channel Tx rates 6591 * @adap: the adapter 6592 * @nic_rate: rates for NIC traffic 6593 * @ofld_rate: rates for offloaded traffic 6594 * 6595 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6596 * for each channel. 6597 */ 6598 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6599 { 6600 u32 v; 6601 6602 v = t4_read_reg(adap, A_TP_TX_TRATE); 6603 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6604 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6605 if (adap->chip_params->nchan > 2) { 6606 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6607 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6608 } 6609 6610 v = t4_read_reg(adap, A_TP_TX_ORATE); 6611 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6612 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6613 if (adap->chip_params->nchan > 2) { 6614 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6615 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6616 } 6617 } 6618 6619 /** 6620 * t4_set_trace_filter - configure one of the tracing filters 6621 * @adap: the adapter 6622 * @tp: the desired trace filter parameters 6623 * @idx: which filter to configure 6624 * @enable: whether to enable or disable the filter 6625 * 6626 * Configures one of the tracing filters available in HW. If @tp is %NULL 6627 * it indicates that the filter is already written in the register and it 6628 * just needs to be enabled or disabled. 6629 */ 6630 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6631 int idx, int enable) 6632 { 6633 int i, ofst = idx * 4; 6634 u32 data_reg, mask_reg, cfg; 6635 u32 multitrc = F_TRCMULTIFILTER; 6636 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6637 6638 if (idx < 0 || idx >= NTRACE) 6639 return -EINVAL; 6640 6641 if (tp == NULL || !enable) { 6642 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6643 enable ? en : 0); 6644 return 0; 6645 } 6646 6647 /* 6648 * TODO - After T4 data book is updated, specify the exact 6649 * section below. 6650 * 6651 * See T4 data book - MPS section for a complete description 6652 * of the below if..else handling of A_MPS_TRC_CFG register 6653 * value. 6654 */ 6655 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6656 if (cfg & F_TRCMULTIFILTER) { 6657 /* 6658 * If multiple tracers are enabled, then maximum 6659 * capture size is 2.5KB (FIFO size of a single channel) 6660 * minus 2 flits for CPL_TRACE_PKT header. 6661 */ 6662 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6663 return -EINVAL; 6664 } else { 6665 /* 6666 * If multiple tracers are disabled, to avoid deadlocks 6667 * maximum packet capture size of 9600 bytes is recommended. 6668 * Also in this mode, only trace0 can be enabled and running. 6669 */ 6670 multitrc = 0; 6671 if (tp->snap_len > 9600 || idx) 6672 return -EINVAL; 6673 } 6674 6675 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6676 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6677 tp->min_len > M_TFMINPKTSIZE) 6678 return -EINVAL; 6679 6680 /* stop the tracer we'll be changing */ 6681 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6682 6683 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6684 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6685 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6686 6687 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6688 t4_write_reg(adap, data_reg, tp->data[i]); 6689 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6690 } 6691 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6692 V_TFCAPTUREMAX(tp->snap_len) | 6693 V_TFMINPKTSIZE(tp->min_len)); 6694 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6695 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6696 (is_t4(adap) ? 6697 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6698 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6699 6700 return 0; 6701 } 6702 6703 /** 6704 * t4_get_trace_filter - query one of the tracing filters 6705 * @adap: the adapter 6706 * @tp: the current trace filter parameters 6707 * @idx: which trace filter to query 6708 * @enabled: non-zero if the filter is enabled 6709 * 6710 * Returns the current settings of one of the HW tracing filters. 6711 */ 6712 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6713 int *enabled) 6714 { 6715 u32 ctla, ctlb; 6716 int i, ofst = idx * 4; 6717 u32 data_reg, mask_reg; 6718 6719 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6720 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6721 6722 if (is_t4(adap)) { 6723 *enabled = !!(ctla & F_TFEN); 6724 tp->port = G_TFPORT(ctla); 6725 tp->invert = !!(ctla & F_TFINVERTMATCH); 6726 } else { 6727 *enabled = !!(ctla & F_T5_TFEN); 6728 tp->port = G_T5_TFPORT(ctla); 6729 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6730 } 6731 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6732 tp->min_len = G_TFMINPKTSIZE(ctlb); 6733 tp->skip_ofst = G_TFOFFSET(ctla); 6734 tp->skip_len = G_TFLENGTH(ctla); 6735 6736 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6737 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6738 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6739 6740 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6741 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6742 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6743 } 6744 } 6745 6746 /** 6747 * t4_pmtx_get_stats - returns the HW stats from PMTX 6748 * @adap: the adapter 6749 * @cnt: where to store the count statistics 6750 * @cycles: where to store the cycle statistics 6751 * 6752 * Returns performance statistics from PMTX. 6753 */ 6754 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6755 { 6756 int i; 6757 u32 data[2]; 6758 6759 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6760 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6761 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6762 if (is_t4(adap)) 6763 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6764 else { 6765 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6766 A_PM_TX_DBG_DATA, data, 2, 6767 A_PM_TX_DBG_STAT_MSB); 6768 cycles[i] = (((u64)data[0] << 32) | data[1]); 6769 } 6770 } 6771 } 6772 6773 /** 6774 * t4_pmrx_get_stats - returns the HW stats from PMRX 6775 * @adap: the adapter 6776 * @cnt: where to store the count statistics 6777 * @cycles: where to store the cycle statistics 6778 * 6779 * Returns performance statistics from PMRX. 6780 */ 6781 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6782 { 6783 int i; 6784 u32 data[2]; 6785 6786 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6787 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6788 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6789 if (is_t4(adap)) { 6790 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6791 } else { 6792 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6793 A_PM_RX_DBG_DATA, data, 2, 6794 A_PM_RX_DBG_STAT_MSB); 6795 cycles[i] = (((u64)data[0] << 32) | data[1]); 6796 } 6797 } 6798 } 6799 6800 /** 6801 * t4_get_mps_bg_map - return the buffer groups associated with a port 6802 * @adap: the adapter 6803 * @idx: the port index 6804 * 6805 * Returns a bitmap indicating which MPS buffer groups are associated 6806 * with the given port. Bit i is set if buffer group i is used by the 6807 * port. 6808 */ 6809 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6810 { 6811 u32 n; 6812 6813 if (adap->params.mps_bg_map) 6814 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6815 6816 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6817 if (n == 0) 6818 return idx == 0 ? 0xf : 0; 6819 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6820 return idx < 2 ? (3 << (2 * idx)) : 0; 6821 return 1 << idx; 6822 } 6823 6824 /* 6825 * TP RX e-channels associated with the port. 6826 */ 6827 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6828 { 6829 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6830 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; 6831 6832 if (n == 0) 6833 return idx == 0 ? all_chan : 0; 6834 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6835 return idx < 2 ? (3 << (2 * idx)) : 0; 6836 return 1 << idx; 6837 } 6838 6839 /* 6840 * TP RX c-channel associated with the port. 6841 */ 6842 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx) 6843 { 6844 u32 param, val; 6845 int ret; 6846 6847 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6848 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP)); 6849 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 6850 if (!ret) 6851 return (val >> (8 * idx)) & 0xff; 6852 6853 return 0; 6854 } 6855 6856 /** 6857 * t4_get_port_type_description - return Port Type string description 6858 * @port_type: firmware Port Type enumeration 6859 */ 6860 const char *t4_get_port_type_description(enum fw_port_type port_type) 6861 { 6862 static const char *const port_type_description[] = { 6863 "Fiber_XFI", 6864 "Fiber_XAUI", 6865 "BT_SGMII", 6866 "BT_XFI", 6867 "BT_XAUI", 6868 "KX4", 6869 "CX4", 6870 "KX", 6871 "KR", 6872 "SFP", 6873 "BP_AP", 6874 "BP4_AP", 6875 "QSFP_10G", 6876 "QSA", 6877 "QSFP", 6878 "BP40_BA", 6879 "KR4_100G", 6880 "CR4_QSFP", 6881 "CR_QSFP", 6882 "CR2_QSFP", 6883 "SFP28", 6884 "KR_SFP28", 6885 }; 6886 6887 if (port_type < ARRAY_SIZE(port_type_description)) 6888 return port_type_description[port_type]; 6889 return "UNKNOWN"; 6890 } 6891 6892 /** 6893 * t4_get_port_stats_offset - collect port stats relative to a previous 6894 * snapshot 6895 * @adap: The adapter 6896 * @idx: The port 6897 * @stats: Current stats to fill 6898 * @offset: Previous stats snapshot 6899 */ 6900 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6901 struct port_stats *stats, 6902 struct port_stats *offset) 6903 { 6904 u64 *s, *o; 6905 int i; 6906 6907 t4_get_port_stats(adap, idx, stats); 6908 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6909 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6910 i++, s++, o++) 6911 *s -= *o; 6912 } 6913 6914 /** 6915 * t4_get_port_stats - collect port statistics 6916 * @adap: the adapter 6917 * @idx: the port index 6918 * @p: the stats structure to fill 6919 * 6920 * Collect statistics related to the given port from HW. 6921 */ 6922 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6923 { 6924 struct port_info *pi = adap->port[idx]; 6925 u32 bgmap = pi->mps_bg_map; 6926 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6927 6928 #define GET_STAT(name) \ 6929 t4_read_reg64(adap, \ 6930 (is_t4(adap) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L) : \ 6931 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L))) 6932 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6933 6934 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6935 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6936 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6937 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6938 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6939 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6940 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6941 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6942 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6943 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6944 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6945 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6946 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6947 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6948 p->tx_drop = GET_STAT(TX_PORT_DROP); 6949 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6950 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6951 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6952 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6953 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6954 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6955 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6956 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6957 6958 if (chip_id(adap) >= CHELSIO_T5) { 6959 if (stat_ctl & F_COUNTPAUSESTATTX) { 6960 p->tx_frames -= p->tx_pause; 6961 p->tx_octets -= p->tx_pause * 64; 6962 } 6963 if (stat_ctl & F_COUNTPAUSEMCTX) 6964 p->tx_mcast_frames -= p->tx_pause; 6965 } 6966 6967 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6968 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6969 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6970 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6971 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6972 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6973 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6974 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6975 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6976 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6977 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6978 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6979 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6980 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6981 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6982 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6983 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6984 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6985 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6986 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6987 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6988 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6989 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6990 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6991 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6992 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6993 6994 if (pi->fcs_reg != -1) 6995 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; 6996 6997 if (chip_id(adap) >= CHELSIO_T5) { 6998 if (stat_ctl & F_COUNTPAUSESTATRX) { 6999 p->rx_frames -= p->rx_pause; 7000 p->rx_octets -= p->rx_pause * 64; 7001 } 7002 if (stat_ctl & F_COUNTPAUSEMCRX) 7003 p->rx_mcast_frames -= p->rx_pause; 7004 } 7005 7006 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 7007 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 7008 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 7009 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 7010 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 7011 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 7012 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 7013 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 7014 7015 #undef GET_STAT 7016 #undef GET_STAT_COM 7017 } 7018 7019 /** 7020 * t4_get_lb_stats - collect loopback port statistics 7021 * @adap: the adapter 7022 * @idx: the loopback port index 7023 * @p: the stats structure to fill 7024 * 7025 * Return HW statistics for the given loopback port. 7026 */ 7027 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 7028 { 7029 7030 #define GET_STAT(name) \ 7031 t4_read_reg64(adap, \ 7032 (is_t4(adap) ? \ 7033 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 7034 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 7035 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 7036 7037 p->octets = GET_STAT(BYTES); 7038 p->frames = GET_STAT(FRAMES); 7039 p->bcast_frames = GET_STAT(BCAST); 7040 p->mcast_frames = GET_STAT(MCAST); 7041 p->ucast_frames = GET_STAT(UCAST); 7042 p->error_frames = GET_STAT(ERROR); 7043 7044 p->frames_64 = GET_STAT(64B); 7045 p->frames_65_127 = GET_STAT(65B_127B); 7046 p->frames_128_255 = GET_STAT(128B_255B); 7047 p->frames_256_511 = GET_STAT(256B_511B); 7048 p->frames_512_1023 = GET_STAT(512B_1023B); 7049 p->frames_1024_1518 = GET_STAT(1024B_1518B); 7050 p->frames_1519_max = GET_STAT(1519B_MAX); 7051 p->drop = GET_STAT(DROP_FRAMES); 7052 7053 if (idx < adap->params.nports) { 7054 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; 7055 7056 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 7057 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 7058 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 7059 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 7060 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 7061 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 7062 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 7063 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 7064 } 7065 7066 #undef GET_STAT 7067 #undef GET_STAT_COM 7068 } 7069 7070 /** 7071 * t4_wol_magic_enable - enable/disable magic packet WoL 7072 * @adap: the adapter 7073 * @port: the physical port index 7074 * @addr: MAC address expected in magic packets, %NULL to disable 7075 * 7076 * Enables/disables magic packet wake-on-LAN for the selected port. 7077 */ 7078 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 7079 const u8 *addr) 7080 { 7081 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 7082 7083 if (is_t4(adap)) { 7084 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 7085 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 7086 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7087 } else { 7088 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 7089 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 7090 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7091 } 7092 7093 if (addr) { 7094 t4_write_reg(adap, mag_id_reg_l, 7095 (addr[2] << 24) | (addr[3] << 16) | 7096 (addr[4] << 8) | addr[5]); 7097 t4_write_reg(adap, mag_id_reg_h, 7098 (addr[0] << 8) | addr[1]); 7099 } 7100 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 7101 V_MAGICEN(addr != NULL)); 7102 } 7103 7104 /** 7105 * t4_wol_pat_enable - enable/disable pattern-based WoL 7106 * @adap: the adapter 7107 * @port: the physical port index 7108 * @map: bitmap of which HW pattern filters to set 7109 * @mask0: byte mask for bytes 0-63 of a packet 7110 * @mask1: byte mask for bytes 64-127 of a packet 7111 * @crc: Ethernet CRC for selected bytes 7112 * @enable: enable/disable switch 7113 * 7114 * Sets the pattern filters indicated in @map to mask out the bytes 7115 * specified in @mask0/@mask1 in received packets and compare the CRC of 7116 * the resulting packet against @crc. If @enable is %true pattern-based 7117 * WoL is enabled, otherwise disabled. 7118 */ 7119 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 7120 u64 mask0, u64 mask1, unsigned int crc, bool enable) 7121 { 7122 int i; 7123 u32 port_cfg_reg; 7124 7125 if (is_t4(adap)) 7126 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7127 else 7128 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7129 7130 if (!enable) { 7131 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7132 return 0; 7133 } 7134 if (map > 0xff) 7135 return -EINVAL; 7136 7137 #define EPIO_REG(name) \ 7138 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7139 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7140 7141 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7142 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7143 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7144 7145 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7146 if (!(map & 1)) 7147 continue; 7148 7149 /* write byte masks */ 7150 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7151 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7152 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7153 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7154 return -ETIMEDOUT; 7155 7156 /* write CRC */ 7157 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7158 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7159 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7160 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7161 return -ETIMEDOUT; 7162 } 7163 #undef EPIO_REG 7164 7165 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7166 return 0; 7167 } 7168 7169 /* t4_mk_filtdelwr - create a delete filter WR 7170 * @ftid: the filter ID 7171 * @wr: the filter work request to populate 7172 * @qid: ingress queue to receive the delete notification 7173 * 7174 * Creates a filter work request to delete the supplied filter. If @qid is 7175 * negative the delete notification is suppressed. 7176 */ 7177 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7178 { 7179 memset(wr, 0, sizeof(*wr)); 7180 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7181 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7182 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7183 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7184 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7185 if (qid >= 0) 7186 wr->rx_chan_rx_rpl_iq = 7187 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7188 } 7189 7190 #define INIT_CMD(var, cmd, rd_wr) do { \ 7191 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7192 F_FW_CMD_REQUEST | \ 7193 F_FW_CMD_##rd_wr); \ 7194 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7195 } while (0) 7196 7197 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7198 u32 addr, u32 val) 7199 { 7200 u32 ldst_addrspace; 7201 struct fw_ldst_cmd c; 7202 7203 memset(&c, 0, sizeof(c)); 7204 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7205 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7206 F_FW_CMD_REQUEST | 7207 F_FW_CMD_WRITE | 7208 ldst_addrspace); 7209 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7210 c.u.addrval.addr = cpu_to_be32(addr); 7211 c.u.addrval.val = cpu_to_be32(val); 7212 7213 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7214 } 7215 7216 /** 7217 * t4_mdio_rd - read a PHY register through MDIO 7218 * @adap: the adapter 7219 * @mbox: mailbox to use for the FW command 7220 * @phy_addr: the PHY address 7221 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7222 * @reg: the register to read 7223 * @valp: where to store the value 7224 * 7225 * Issues a FW command through the given mailbox to read a PHY register. 7226 */ 7227 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7228 unsigned int mmd, unsigned int reg, unsigned int *valp) 7229 { 7230 int ret; 7231 u32 ldst_addrspace; 7232 struct fw_ldst_cmd c; 7233 7234 memset(&c, 0, sizeof(c)); 7235 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7236 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7237 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7238 ldst_addrspace); 7239 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7240 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7241 V_FW_LDST_CMD_MMD(mmd)); 7242 c.u.mdio.raddr = cpu_to_be16(reg); 7243 7244 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7245 if (ret == 0) 7246 *valp = be16_to_cpu(c.u.mdio.rval); 7247 return ret; 7248 } 7249 7250 /** 7251 * t4_mdio_wr - write a PHY register through MDIO 7252 * @adap: the adapter 7253 * @mbox: mailbox to use for the FW command 7254 * @phy_addr: the PHY address 7255 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7256 * @reg: the register to write 7257 * @valp: value to write 7258 * 7259 * Issues a FW command through the given mailbox to write a PHY register. 7260 */ 7261 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7262 unsigned int mmd, unsigned int reg, unsigned int val) 7263 { 7264 u32 ldst_addrspace; 7265 struct fw_ldst_cmd c; 7266 7267 memset(&c, 0, sizeof(c)); 7268 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7269 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7270 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7271 ldst_addrspace); 7272 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7273 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7274 V_FW_LDST_CMD_MMD(mmd)); 7275 c.u.mdio.raddr = cpu_to_be16(reg); 7276 c.u.mdio.rval = cpu_to_be16(val); 7277 7278 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7279 } 7280 7281 /** 7282 * 7283 * t4_sge_decode_idma_state - decode the idma state 7284 * @adap: the adapter 7285 * @state: the state idma is stuck in 7286 */ 7287 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7288 { 7289 static const char * const t4_decode[] = { 7290 "IDMA_IDLE", 7291 "IDMA_PUSH_MORE_CPL_FIFO", 7292 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7293 "Not used", 7294 "IDMA_PHYSADDR_SEND_PCIEHDR", 7295 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7296 "IDMA_PHYSADDR_SEND_PAYLOAD", 7297 "IDMA_SEND_FIFO_TO_IMSG", 7298 "IDMA_FL_REQ_DATA_FL_PREP", 7299 "IDMA_FL_REQ_DATA_FL", 7300 "IDMA_FL_DROP", 7301 "IDMA_FL_H_REQ_HEADER_FL", 7302 "IDMA_FL_H_SEND_PCIEHDR", 7303 "IDMA_FL_H_PUSH_CPL_FIFO", 7304 "IDMA_FL_H_SEND_CPL", 7305 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7306 "IDMA_FL_H_SEND_IP_HDR", 7307 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7308 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7309 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7310 "IDMA_FL_D_SEND_PCIEHDR", 7311 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7312 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7313 "IDMA_FL_SEND_PCIEHDR", 7314 "IDMA_FL_PUSH_CPL_FIFO", 7315 "IDMA_FL_SEND_CPL", 7316 "IDMA_FL_SEND_PAYLOAD_FIRST", 7317 "IDMA_FL_SEND_PAYLOAD", 7318 "IDMA_FL_REQ_NEXT_DATA_FL", 7319 "IDMA_FL_SEND_NEXT_PCIEHDR", 7320 "IDMA_FL_SEND_PADDING", 7321 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7322 "IDMA_FL_SEND_FIFO_TO_IMSG", 7323 "IDMA_FL_REQ_DATAFL_DONE", 7324 "IDMA_FL_REQ_HEADERFL_DONE", 7325 }; 7326 static const char * const t5_decode[] = { 7327 "IDMA_IDLE", 7328 "IDMA_ALMOST_IDLE", 7329 "IDMA_PUSH_MORE_CPL_FIFO", 7330 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7331 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7332 "IDMA_PHYSADDR_SEND_PCIEHDR", 7333 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7334 "IDMA_PHYSADDR_SEND_PAYLOAD", 7335 "IDMA_SEND_FIFO_TO_IMSG", 7336 "IDMA_FL_REQ_DATA_FL", 7337 "IDMA_FL_DROP", 7338 "IDMA_FL_DROP_SEND_INC", 7339 "IDMA_FL_H_REQ_HEADER_FL", 7340 "IDMA_FL_H_SEND_PCIEHDR", 7341 "IDMA_FL_H_PUSH_CPL_FIFO", 7342 "IDMA_FL_H_SEND_CPL", 7343 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7344 "IDMA_FL_H_SEND_IP_HDR", 7345 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7346 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7347 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7348 "IDMA_FL_D_SEND_PCIEHDR", 7349 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7350 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7351 "IDMA_FL_SEND_PCIEHDR", 7352 "IDMA_FL_PUSH_CPL_FIFO", 7353 "IDMA_FL_SEND_CPL", 7354 "IDMA_FL_SEND_PAYLOAD_FIRST", 7355 "IDMA_FL_SEND_PAYLOAD", 7356 "IDMA_FL_REQ_NEXT_DATA_FL", 7357 "IDMA_FL_SEND_NEXT_PCIEHDR", 7358 "IDMA_FL_SEND_PADDING", 7359 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7360 }; 7361 static const char * const t6_decode[] = { 7362 "IDMA_IDLE", 7363 "IDMA_PUSH_MORE_CPL_FIFO", 7364 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7365 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7366 "IDMA_PHYSADDR_SEND_PCIEHDR", 7367 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7368 "IDMA_PHYSADDR_SEND_PAYLOAD", 7369 "IDMA_FL_REQ_DATA_FL", 7370 "IDMA_FL_DROP", 7371 "IDMA_FL_DROP_SEND_INC", 7372 "IDMA_FL_H_REQ_HEADER_FL", 7373 "IDMA_FL_H_SEND_PCIEHDR", 7374 "IDMA_FL_H_PUSH_CPL_FIFO", 7375 "IDMA_FL_H_SEND_CPL", 7376 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7377 "IDMA_FL_H_SEND_IP_HDR", 7378 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7379 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7380 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7381 "IDMA_FL_D_SEND_PCIEHDR", 7382 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7383 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7384 "IDMA_FL_SEND_PCIEHDR", 7385 "IDMA_FL_PUSH_CPL_FIFO", 7386 "IDMA_FL_SEND_CPL", 7387 "IDMA_FL_SEND_PAYLOAD_FIRST", 7388 "IDMA_FL_SEND_PAYLOAD", 7389 "IDMA_FL_REQ_NEXT_DATA_FL", 7390 "IDMA_FL_SEND_NEXT_PCIEHDR", 7391 "IDMA_FL_SEND_PADDING", 7392 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7393 }; 7394 static const u32 sge_regs[] = { 7395 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7396 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7397 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7398 }; 7399 const char * const *sge_idma_decode; 7400 int sge_idma_decode_nstates; 7401 int i; 7402 unsigned int chip_version = chip_id(adapter); 7403 7404 /* Select the right set of decode strings to dump depending on the 7405 * adapter chip type. 7406 */ 7407 switch (chip_version) { 7408 case CHELSIO_T4: 7409 sge_idma_decode = (const char * const *)t4_decode; 7410 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7411 break; 7412 7413 case CHELSIO_T5: 7414 sge_idma_decode = (const char * const *)t5_decode; 7415 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7416 break; 7417 7418 case CHELSIO_T6: 7419 sge_idma_decode = (const char * const *)t6_decode; 7420 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7421 break; 7422 7423 default: 7424 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7425 return; 7426 } 7427 7428 if (state < sge_idma_decode_nstates) 7429 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7430 else 7431 CH_WARN(adapter, "idma state %d unknown\n", state); 7432 7433 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7434 CH_WARN(adapter, "SGE register %#x value %#x\n", 7435 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7436 } 7437 7438 /** 7439 * t4_sge_ctxt_flush - flush the SGE context cache 7440 * @adap: the adapter 7441 * @mbox: mailbox to use for the FW command 7442 * 7443 * Issues a FW command through the given mailbox to flush the 7444 * SGE context cache. 7445 */ 7446 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type) 7447 { 7448 int ret; 7449 u32 ldst_addrspace; 7450 struct fw_ldst_cmd c; 7451 7452 memset(&c, 0, sizeof(c)); 7453 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ? 7454 FW_LDST_ADDRSPC_SGE_EGRC : 7455 FW_LDST_ADDRSPC_SGE_INGC); 7456 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7457 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7458 ldst_addrspace); 7459 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7460 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7461 7462 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7463 return ret; 7464 } 7465 7466 /** 7467 * t4_fw_hello - establish communication with FW 7468 * @adap: the adapter 7469 * @mbox: mailbox to use for the FW command 7470 * @evt_mbox: mailbox to receive async FW events 7471 * @master: specifies the caller's willingness to be the device master 7472 * @state: returns the current device state (if non-NULL) 7473 * 7474 * Issues a command to establish communication with FW. Returns either 7475 * an error (negative integer) or the mailbox of the Master PF. 7476 */ 7477 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7478 enum dev_master master, enum dev_state *state) 7479 { 7480 int ret; 7481 struct fw_hello_cmd c; 7482 u32 v; 7483 unsigned int master_mbox; 7484 int retries = FW_CMD_HELLO_RETRIES; 7485 7486 retry: 7487 memset(&c, 0, sizeof(c)); 7488 INIT_CMD(c, HELLO, WRITE); 7489 c.err_to_clearinit = cpu_to_be32( 7490 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7491 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7492 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7493 mbox : M_FW_HELLO_CMD_MBMASTER) | 7494 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7495 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7496 F_FW_HELLO_CMD_CLEARINIT); 7497 7498 /* 7499 * Issue the HELLO command to the firmware. If it's not successful 7500 * but indicates that we got a "busy" or "timeout" condition, retry 7501 * the HELLO until we exhaust our retry limit. If we do exceed our 7502 * retry limit, check to see if the firmware left us any error 7503 * information and report that if so ... 7504 */ 7505 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7506 if (ret != FW_SUCCESS) { 7507 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7508 goto retry; 7509 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7510 t4_report_fw_error(adap); 7511 return ret; 7512 } 7513 7514 v = be32_to_cpu(c.err_to_clearinit); 7515 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7516 if (state) { 7517 if (v & F_FW_HELLO_CMD_ERR) 7518 *state = DEV_STATE_ERR; 7519 else if (v & F_FW_HELLO_CMD_INIT) 7520 *state = DEV_STATE_INIT; 7521 else 7522 *state = DEV_STATE_UNINIT; 7523 } 7524 7525 /* 7526 * If we're not the Master PF then we need to wait around for the 7527 * Master PF Driver to finish setting up the adapter. 7528 * 7529 * Note that we also do this wait if we're a non-Master-capable PF and 7530 * there is no current Master PF; a Master PF may show up momentarily 7531 * and we wouldn't want to fail pointlessly. (This can happen when an 7532 * OS loads lots of different drivers rapidly at the same time). In 7533 * this case, the Master PF returned by the firmware will be 7534 * M_PCIE_FW_MASTER so the test below will work ... 7535 */ 7536 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7537 master_mbox != mbox) { 7538 int waiting = FW_CMD_HELLO_TIMEOUT; 7539 7540 /* 7541 * Wait for the firmware to either indicate an error or 7542 * initialized state. If we see either of these we bail out 7543 * and report the issue to the caller. If we exhaust the 7544 * "hello timeout" and we haven't exhausted our retries, try 7545 * again. Otherwise bail with a timeout error. 7546 */ 7547 for (;;) { 7548 u32 pcie_fw; 7549 7550 msleep(50); 7551 waiting -= 50; 7552 7553 /* 7554 * If neither Error nor Initialialized are indicated 7555 * by the firmware keep waiting till we exhaust our 7556 * timeout ... and then retry if we haven't exhausted 7557 * our retries ... 7558 */ 7559 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7560 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7561 if (waiting <= 0) { 7562 if (retries-- > 0) 7563 goto retry; 7564 7565 return -ETIMEDOUT; 7566 } 7567 continue; 7568 } 7569 7570 /* 7571 * We either have an Error or Initialized condition 7572 * report errors preferentially. 7573 */ 7574 if (state) { 7575 if (pcie_fw & F_PCIE_FW_ERR) 7576 *state = DEV_STATE_ERR; 7577 else if (pcie_fw & F_PCIE_FW_INIT) 7578 *state = DEV_STATE_INIT; 7579 } 7580 7581 /* 7582 * If we arrived before a Master PF was selected and 7583 * there's not a valid Master PF, grab its identity 7584 * for our caller. 7585 */ 7586 if (master_mbox == M_PCIE_FW_MASTER && 7587 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7588 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7589 break; 7590 } 7591 } 7592 7593 return master_mbox; 7594 } 7595 7596 /** 7597 * t4_fw_bye - end communication with FW 7598 * @adap: the adapter 7599 * @mbox: mailbox to use for the FW command 7600 * 7601 * Issues a command to terminate communication with FW. 7602 */ 7603 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7604 { 7605 struct fw_bye_cmd c; 7606 7607 memset(&c, 0, sizeof(c)); 7608 INIT_CMD(c, BYE, WRITE); 7609 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7610 } 7611 7612 /** 7613 * t4_fw_reset - issue a reset to FW 7614 * @adap: the adapter 7615 * @mbox: mailbox to use for the FW command 7616 * @reset: specifies the type of reset to perform 7617 * 7618 * Issues a reset command of the specified type to FW. 7619 */ 7620 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7621 { 7622 struct fw_reset_cmd c; 7623 7624 memset(&c, 0, sizeof(c)); 7625 INIT_CMD(c, RESET, WRITE); 7626 c.val = cpu_to_be32(reset); 7627 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7628 } 7629 7630 /** 7631 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7632 * @adap: the adapter 7633 * @mbox: mailbox to use for the FW RESET command (if desired) 7634 * @force: force uP into RESET even if FW RESET command fails 7635 * 7636 * Issues a RESET command to firmware (if desired) with a HALT indication 7637 * and then puts the microprocessor into RESET state. The RESET command 7638 * will only be issued if a legitimate mailbox is provided (mbox <= 7639 * M_PCIE_FW_MASTER). 7640 * 7641 * This is generally used in order for the host to safely manipulate the 7642 * adapter without fear of conflicting with whatever the firmware might 7643 * be doing. The only way out of this state is to RESTART the firmware 7644 * ... 7645 */ 7646 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7647 { 7648 int ret = 0; 7649 7650 /* 7651 * If a legitimate mailbox is provided, issue a RESET command 7652 * with a HALT indication. 7653 */ 7654 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7655 struct fw_reset_cmd c; 7656 7657 memset(&c, 0, sizeof(c)); 7658 INIT_CMD(c, RESET, WRITE); 7659 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7660 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7661 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7662 } 7663 7664 /* 7665 * Normally we won't complete the operation if the firmware RESET 7666 * command fails but if our caller insists we'll go ahead and put the 7667 * uP into RESET. This can be useful if the firmware is hung or even 7668 * missing ... We'll have to take the risk of putting the uP into 7669 * RESET without the cooperation of firmware in that case. 7670 * 7671 * We also force the firmware's HALT flag to be on in case we bypassed 7672 * the firmware RESET command above or we're dealing with old firmware 7673 * which doesn't have the HALT capability. This will serve as a flag 7674 * for the incoming firmware to know that it's coming out of a HALT 7675 * rather than a RESET ... if it's new enough to understand that ... 7676 */ 7677 if (ret == 0 || force) { 7678 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7679 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7680 F_PCIE_FW_HALT); 7681 } 7682 7683 /* 7684 * And we always return the result of the firmware RESET command 7685 * even when we force the uP into RESET ... 7686 */ 7687 return ret; 7688 } 7689 7690 /** 7691 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7692 * @adap: the adapter 7693 * 7694 * Restart firmware previously halted by t4_fw_halt(). On successful 7695 * return the previous PF Master remains as the new PF Master and there 7696 * is no need to issue a new HELLO command, etc. 7697 */ 7698 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7699 { 7700 int ms; 7701 7702 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7703 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7704 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7705 return FW_SUCCESS; 7706 msleep(100); 7707 ms += 100; 7708 } 7709 7710 return -ETIMEDOUT; 7711 } 7712 7713 /** 7714 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7715 * @adap: the adapter 7716 * @mbox: mailbox to use for the FW RESET command (if desired) 7717 * @fw_data: the firmware image to write 7718 * @size: image size 7719 * @force: force upgrade even if firmware doesn't cooperate 7720 * 7721 * Perform all of the steps necessary for upgrading an adapter's 7722 * firmware image. Normally this requires the cooperation of the 7723 * existing firmware in order to halt all existing activities 7724 * but if an invalid mailbox token is passed in we skip that step 7725 * (though we'll still put the adapter microprocessor into RESET in 7726 * that case). 7727 * 7728 * On successful return the new firmware will have been loaded and 7729 * the adapter will have been fully RESET losing all previous setup 7730 * state. On unsuccessful return the adapter may be completely hosed ... 7731 * positive errno indicates that the adapter is ~probably~ intact, a 7732 * negative errno indicates that things are looking bad ... 7733 */ 7734 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7735 const u8 *fw_data, unsigned int size, int force) 7736 { 7737 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7738 unsigned int bootstrap = 7739 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7740 int ret; 7741 7742 if (!t4_fw_matches_chip(adap, fw_hdr)) 7743 return -EINVAL; 7744 7745 if (!bootstrap) { 7746 ret = t4_fw_halt(adap, mbox, force); 7747 if (ret < 0 && !force) 7748 return ret; 7749 } 7750 7751 ret = t4_load_fw(adap, fw_data, size); 7752 if (ret < 0 || bootstrap) 7753 return ret; 7754 7755 return t4_fw_restart(adap, mbox); 7756 } 7757 7758 /** 7759 * t4_fw_initialize - ask FW to initialize the device 7760 * @adap: the adapter 7761 * @mbox: mailbox to use for the FW command 7762 * 7763 * Issues a command to FW to partially initialize the device. This 7764 * performs initialization that generally doesn't depend on user input. 7765 */ 7766 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7767 { 7768 struct fw_initialize_cmd c; 7769 7770 memset(&c, 0, sizeof(c)); 7771 INIT_CMD(c, INITIALIZE, WRITE); 7772 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7773 } 7774 7775 /** 7776 * t4_query_params_rw - query FW or device parameters 7777 * @adap: the adapter 7778 * @mbox: mailbox to use for the FW command 7779 * @pf: the PF 7780 * @vf: the VF 7781 * @nparams: the number of parameters 7782 * @params: the parameter names 7783 * @val: the parameter values 7784 * @rw: Write and read flag 7785 * 7786 * Reads the value of FW or device parameters. Up to 7 parameters can be 7787 * queried at once. 7788 */ 7789 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7790 unsigned int vf, unsigned int nparams, const u32 *params, 7791 u32 *val, int rw) 7792 { 7793 int i, ret; 7794 struct fw_params_cmd c; 7795 __be32 *p = &c.param[0].mnem; 7796 7797 if (nparams > 7) 7798 return -EINVAL; 7799 7800 memset(&c, 0, sizeof(c)); 7801 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7802 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7803 V_FW_PARAMS_CMD_PFN(pf) | 7804 V_FW_PARAMS_CMD_VFN(vf)); 7805 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7806 7807 for (i = 0; i < nparams; i++) { 7808 *p++ = cpu_to_be32(*params++); 7809 if (rw) 7810 *p = cpu_to_be32(*(val + i)); 7811 p++; 7812 } 7813 7814 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7815 if (ret == 0) 7816 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7817 *val++ = be32_to_cpu(*p); 7818 return ret; 7819 } 7820 7821 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7822 unsigned int vf, unsigned int nparams, const u32 *params, 7823 u32 *val) 7824 { 7825 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7826 } 7827 7828 /** 7829 * t4_set_params_timeout - sets FW or device parameters 7830 * @adap: the adapter 7831 * @mbox: mailbox to use for the FW command 7832 * @pf: the PF 7833 * @vf: the VF 7834 * @nparams: the number of parameters 7835 * @params: the parameter names 7836 * @val: the parameter values 7837 * @timeout: the timeout time 7838 * 7839 * Sets the value of FW or device parameters. Up to 7 parameters can be 7840 * specified at once. 7841 */ 7842 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7843 unsigned int pf, unsigned int vf, 7844 unsigned int nparams, const u32 *params, 7845 const u32 *val, int timeout) 7846 { 7847 struct fw_params_cmd c; 7848 __be32 *p = &c.param[0].mnem; 7849 7850 if (nparams > 7) 7851 return -EINVAL; 7852 7853 memset(&c, 0, sizeof(c)); 7854 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7855 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7856 V_FW_PARAMS_CMD_PFN(pf) | 7857 V_FW_PARAMS_CMD_VFN(vf)); 7858 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7859 7860 while (nparams--) { 7861 *p++ = cpu_to_be32(*params++); 7862 *p++ = cpu_to_be32(*val++); 7863 } 7864 7865 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7866 } 7867 7868 /** 7869 * t4_set_params - sets FW or device parameters 7870 * @adap: the adapter 7871 * @mbox: mailbox to use for the FW command 7872 * @pf: the PF 7873 * @vf: the VF 7874 * @nparams: the number of parameters 7875 * @params: the parameter names 7876 * @val: the parameter values 7877 * 7878 * Sets the value of FW or device parameters. Up to 7 parameters can be 7879 * specified at once. 7880 */ 7881 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7882 unsigned int vf, unsigned int nparams, const u32 *params, 7883 const u32 *val) 7884 { 7885 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7886 FW_CMD_MAX_TIMEOUT); 7887 } 7888 7889 /** 7890 * t4_cfg_pfvf - configure PF/VF resource limits 7891 * @adap: the adapter 7892 * @mbox: mailbox to use for the FW command 7893 * @pf: the PF being configured 7894 * @vf: the VF being configured 7895 * @txq: the max number of egress queues 7896 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7897 * @rxqi: the max number of interrupt-capable ingress queues 7898 * @rxq: the max number of interruptless ingress queues 7899 * @tc: the PCI traffic class 7900 * @vi: the max number of virtual interfaces 7901 * @cmask: the channel access rights mask for the PF/VF 7902 * @pmask: the port access rights mask for the PF/VF 7903 * @nexact: the maximum number of exact MPS filters 7904 * @rcaps: read capabilities 7905 * @wxcaps: write/execute capabilities 7906 * 7907 * Configures resource limits and capabilities for a physical or virtual 7908 * function. 7909 */ 7910 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7911 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7912 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7913 unsigned int vi, unsigned int cmask, unsigned int pmask, 7914 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7915 { 7916 struct fw_pfvf_cmd c; 7917 7918 memset(&c, 0, sizeof(c)); 7919 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7920 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7921 V_FW_PFVF_CMD_VFN(vf)); 7922 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7923 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7924 V_FW_PFVF_CMD_NIQ(rxq)); 7925 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7926 V_FW_PFVF_CMD_PMASK(pmask) | 7927 V_FW_PFVF_CMD_NEQ(txq)); 7928 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7929 V_FW_PFVF_CMD_NVI(vi) | 7930 V_FW_PFVF_CMD_NEXACTF(nexact)); 7931 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7932 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7933 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7934 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7935 } 7936 7937 /** 7938 * t4_alloc_vi_func - allocate a virtual interface 7939 * @adap: the adapter 7940 * @mbox: mailbox to use for the FW command 7941 * @port: physical port associated with the VI 7942 * @pf: the PF owning the VI 7943 * @vf: the VF owning the VI 7944 * @nmac: number of MAC addresses needed (1 to 5) 7945 * @mac: the MAC addresses of the VI 7946 * @rss_size: size of RSS table slice associated with this VI 7947 * @portfunc: which Port Application Function MAC Address is desired 7948 * @idstype: Intrusion Detection Type 7949 * 7950 * Allocates a virtual interface for the given physical port. If @mac is 7951 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7952 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7953 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7954 * stored consecutively so the space needed is @nmac * 6 bytes. 7955 * Returns a negative error number or the non-negative VI id. 7956 */ 7957 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7958 unsigned int port, unsigned int pf, unsigned int vf, 7959 unsigned int nmac, u8 *mac, u16 *rss_size, 7960 uint8_t *vfvld, uint16_t *vin, 7961 unsigned int portfunc, unsigned int idstype) 7962 { 7963 int ret; 7964 struct fw_vi_cmd c; 7965 7966 memset(&c, 0, sizeof(c)); 7967 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7968 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7969 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7970 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7971 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7972 V_FW_VI_CMD_FUNC(portfunc)); 7973 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7974 c.nmac = nmac - 1; 7975 if(!rss_size) 7976 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7977 7978 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7979 if (ret) 7980 return ret; 7981 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7982 7983 if (mac) { 7984 memcpy(mac, c.mac, sizeof(c.mac)); 7985 switch (nmac) { 7986 case 5: 7987 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7988 case 4: 7989 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7990 case 3: 7991 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7992 case 2: 7993 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7994 } 7995 } 7996 if (rss_size) 7997 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7998 if (vfvld) { 7999 *vfvld = adap->params.viid_smt_extn_support ? 8000 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 8001 G_FW_VIID_VIVLD(ret); 8002 } 8003 if (vin) { 8004 *vin = adap->params.viid_smt_extn_support ? 8005 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 8006 G_FW_VIID_VIN(ret); 8007 } 8008 8009 return ret; 8010 } 8011 8012 /** 8013 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 8014 * @adap: the adapter 8015 * @mbox: mailbox to use for the FW command 8016 * @port: physical port associated with the VI 8017 * @pf: the PF owning the VI 8018 * @vf: the VF owning the VI 8019 * @nmac: number of MAC addresses needed (1 to 5) 8020 * @mac: the MAC addresses of the VI 8021 * @rss_size: size of RSS table slice associated with this VI 8022 * 8023 * backwards compatible and convieniance routine to allocate a Virtual 8024 * Interface with a Ethernet Port Application Function and Intrustion 8025 * Detection System disabled. 8026 */ 8027 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 8028 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 8029 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 8030 { 8031 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 8032 vfvld, vin, FW_VI_FUNC_ETH, 0); 8033 } 8034 8035 /** 8036 * t4_free_vi - free a virtual interface 8037 * @adap: the adapter 8038 * @mbox: mailbox to use for the FW command 8039 * @pf: the PF owning the VI 8040 * @vf: the VF owning the VI 8041 * @viid: virtual interface identifiler 8042 * 8043 * Free a previously allocated virtual interface. 8044 */ 8045 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 8046 unsigned int vf, unsigned int viid) 8047 { 8048 struct fw_vi_cmd c; 8049 8050 memset(&c, 0, sizeof(c)); 8051 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 8052 F_FW_CMD_REQUEST | 8053 F_FW_CMD_EXEC | 8054 V_FW_VI_CMD_PFN(pf) | 8055 V_FW_VI_CMD_VFN(vf)); 8056 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 8057 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 8058 8059 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8060 } 8061 8062 /** 8063 * t4_set_rxmode - set Rx properties of a virtual interface 8064 * @adap: the adapter 8065 * @mbox: mailbox to use for the FW command 8066 * @viid: the VI id 8067 * @mtu: the new MTU or -1 8068 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 8069 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 8070 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 8071 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 8072 * @sleep_ok: if true we may sleep while awaiting command completion 8073 * 8074 * Sets Rx properties of a virtual interface. 8075 */ 8076 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 8077 int mtu, int promisc, int all_multi, int bcast, int vlanex, 8078 bool sleep_ok) 8079 { 8080 struct fw_vi_rxmode_cmd c; 8081 8082 /* convert to FW values */ 8083 if (mtu < 0) 8084 mtu = M_FW_VI_RXMODE_CMD_MTU; 8085 if (promisc < 0) 8086 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 8087 if (all_multi < 0) 8088 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 8089 if (bcast < 0) 8090 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 8091 if (vlanex < 0) 8092 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 8093 8094 memset(&c, 0, sizeof(c)); 8095 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 8096 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8097 V_FW_VI_RXMODE_CMD_VIID(viid)); 8098 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 8099 c.mtu_to_vlanexen = 8100 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 8101 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 8102 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 8103 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 8104 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 8105 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8106 } 8107 8108 /** 8109 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support 8110 * @adap: the adapter 8111 * @viid: the VI id 8112 * @mac: the MAC address 8113 * @mask: the mask 8114 * @vni: the VNI id for the tunnel protocol 8115 * @vni_mask: mask for the VNI id 8116 * @dip_hit: to enable DIP match for the MPS entry 8117 * @lookup_type: MAC address for inner (1) or outer (0) header 8118 * @sleep_ok: call is allowed to sleep 8119 * 8120 * Allocates an MPS entry with specified MAC address and VNI value. 8121 * 8122 * Returns a negative error number or the allocated index for this mac. 8123 */ 8124 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 8125 const u8 *addr, const u8 *mask, unsigned int vni, 8126 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 8127 bool sleep_ok) 8128 { 8129 struct fw_vi_mac_cmd c; 8130 struct fw_vi_mac_vni *p = c.u.exact_vni; 8131 int ret = 0; 8132 u32 val; 8133 8134 memset(&c, 0, sizeof(c)); 8135 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8136 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8137 V_FW_VI_MAC_CMD_VIID(viid)); 8138 val = V_FW_CMD_LEN16(1) | 8139 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI); 8140 c.freemacs_to_len16 = cpu_to_be32(val); 8141 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8142 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8143 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8144 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); 8145 8146 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | 8147 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) | 8148 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type)); 8149 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); 8150 8151 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8152 if (ret == 0) 8153 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8154 return ret; 8155 } 8156 8157 /** 8158 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam 8159 * @adap: the adapter 8160 * @viid: the VI id 8161 * @mac: the MAC address 8162 * @mask: the mask 8163 * @idx: index at which to add this entry 8164 * @port_id: the port index 8165 * @lookup_type: MAC address for inner (1) or outer (0) header 8166 * @sleep_ok: call is allowed to sleep 8167 * 8168 * Adds the mac entry at the specified index using raw mac interface. 8169 * 8170 * Returns a negative error number or the allocated index for this mac. 8171 */ 8172 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 8173 const u8 *addr, const u8 *mask, unsigned int idx, 8174 u8 lookup_type, u8 port_id, bool sleep_ok) 8175 { 8176 int ret = 0; 8177 struct fw_vi_mac_cmd c; 8178 struct fw_vi_mac_raw *p = &c.u.raw; 8179 u32 val; 8180 8181 memset(&c, 0, sizeof(c)); 8182 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8183 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8184 V_FW_VI_MAC_CMD_VIID(viid)); 8185 val = V_FW_CMD_LEN16(1) | 8186 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8187 c.freemacs_to_len16 = cpu_to_be32(val); 8188 8189 /* Specify that this is an inner mac address */ 8190 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); 8191 8192 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8193 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8194 V_DATAPORTNUM(port_id)); 8195 /* Lookup mask and port mask */ 8196 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8197 V_DATAPORTNUM(M_DATAPORTNUM)); 8198 8199 /* Copy the address and the mask */ 8200 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8201 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8202 8203 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8204 if (ret == 0) { 8205 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); 8206 if (ret != idx) 8207 ret = -ENOMEM; 8208 } 8209 8210 return ret; 8211 } 8212 8213 /** 8214 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 8215 * @adap: the adapter 8216 * @mbox: mailbox to use for the FW command 8217 * @viid: the VI id 8218 * @free: if true any existing filters for this VI id are first removed 8219 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8220 * @addr: the MAC address(es) 8221 * @idx: where to store the index of each allocated filter 8222 * @hash: pointer to hash address filter bitmap 8223 * @sleep_ok: call is allowed to sleep 8224 * 8225 * Allocates an exact-match filter for each of the supplied addresses and 8226 * sets it to the corresponding address. If @idx is not %NULL it should 8227 * have at least @naddr entries, each of which will be set to the index of 8228 * the filter allocated for the corresponding MAC address. If a filter 8229 * could not be allocated for an address its index is set to 0xffff. 8230 * If @hash is not %NULL addresses that fail to allocate an exact filter 8231 * are hashed and update the hash filter bitmap pointed at by @hash. 8232 * 8233 * Returns a negative error number or the number of filters allocated. 8234 */ 8235 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8236 unsigned int viid, bool free, unsigned int naddr, 8237 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8238 { 8239 int offset, ret = 0; 8240 struct fw_vi_mac_cmd c; 8241 unsigned int nfilters = 0; 8242 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8243 unsigned int rem = naddr; 8244 8245 if (naddr > max_naddr) 8246 return -EINVAL; 8247 8248 for (offset = 0; offset < naddr ; /**/) { 8249 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8250 ? rem 8251 : ARRAY_SIZE(c.u.exact)); 8252 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8253 u.exact[fw_naddr]), 16); 8254 struct fw_vi_mac_exact *p; 8255 int i; 8256 8257 memset(&c, 0, sizeof(c)); 8258 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8259 F_FW_CMD_REQUEST | 8260 F_FW_CMD_WRITE | 8261 V_FW_CMD_EXEC(free) | 8262 V_FW_VI_MAC_CMD_VIID(viid)); 8263 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8264 V_FW_CMD_LEN16(len16)); 8265 8266 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8267 p->valid_to_idx = 8268 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8269 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8270 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8271 } 8272 8273 /* 8274 * It's okay if we run out of space in our MAC address arena. 8275 * Some of the addresses we submit may get stored so we need 8276 * to run through the reply to see what the results were ... 8277 */ 8278 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8279 if (ret && ret != -FW_ENOMEM) 8280 break; 8281 8282 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8283 u16 index = G_FW_VI_MAC_CMD_IDX( 8284 be16_to_cpu(p->valid_to_idx)); 8285 8286 if (idx) 8287 idx[offset+i] = (index >= max_naddr 8288 ? 0xffff 8289 : index); 8290 if (index < max_naddr) 8291 nfilters++; 8292 else if (hash) 8293 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8294 } 8295 8296 free = false; 8297 offset += fw_naddr; 8298 rem -= fw_naddr; 8299 } 8300 8301 if (ret == 0 || ret == -FW_ENOMEM) 8302 ret = nfilters; 8303 return ret; 8304 } 8305 8306 /** 8307 * t4_free_encap_mac_filt - frees MPS entry at given index 8308 * @adap: the adapter 8309 * @viid: the VI id 8310 * @idx: index of MPS entry to be freed 8311 * @sleep_ok: call is allowed to sleep 8312 * 8313 * Frees the MPS entry at supplied index 8314 * 8315 * Returns a negative error number or zero on success 8316 */ 8317 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 8318 int idx, bool sleep_ok) 8319 { 8320 struct fw_vi_mac_exact *p; 8321 struct fw_vi_mac_cmd c; 8322 u8 addr[] = {0,0,0,0,0,0}; 8323 int ret = 0; 8324 u32 exact; 8325 8326 memset(&c, 0, sizeof(c)); 8327 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8328 F_FW_CMD_REQUEST | 8329 F_FW_CMD_WRITE | 8330 V_FW_CMD_EXEC(0) | 8331 V_FW_VI_MAC_CMD_VIID(viid)); 8332 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC); 8333 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8334 exact | 8335 V_FW_CMD_LEN16(1)); 8336 p = c.u.exact; 8337 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8338 V_FW_VI_MAC_CMD_IDX(idx)); 8339 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8340 8341 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8342 return ret; 8343 } 8344 8345 /** 8346 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam 8347 * @adap: the adapter 8348 * @viid: the VI id 8349 * @addr: the MAC address 8350 * @mask: the mask 8351 * @idx: index of the entry in mps tcam 8352 * @lookup_type: MAC address for inner (1) or outer (0) header 8353 * @port_id: the port index 8354 * @sleep_ok: call is allowed to sleep 8355 * 8356 * Removes the mac entry at the specified index using raw mac interface. 8357 * 8358 * Returns a negative error number on failure. 8359 */ 8360 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 8361 const u8 *addr, const u8 *mask, unsigned int idx, 8362 u8 lookup_type, u8 port_id, bool sleep_ok) 8363 { 8364 struct fw_vi_mac_cmd c; 8365 struct fw_vi_mac_raw *p = &c.u.raw; 8366 u32 raw; 8367 8368 memset(&c, 0, sizeof(c)); 8369 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8370 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8371 V_FW_CMD_EXEC(0) | 8372 V_FW_VI_MAC_CMD_VIID(viid)); 8373 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8374 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8375 raw | 8376 V_FW_CMD_LEN16(1)); 8377 8378 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | 8379 FW_VI_MAC_ID_BASED_FREE); 8380 8381 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8382 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8383 V_DATAPORTNUM(port_id)); 8384 /* Lookup mask and port mask */ 8385 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8386 V_DATAPORTNUM(M_DATAPORTNUM)); 8387 8388 /* Copy the address and the mask */ 8389 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8390 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8391 8392 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8393 } 8394 8395 /** 8396 * t4_free_mac_filt - frees exact-match filters of given MAC addresses 8397 * @adap: the adapter 8398 * @mbox: mailbox to use for the FW command 8399 * @viid: the VI id 8400 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8401 * @addr: the MAC address(es) 8402 * @sleep_ok: call is allowed to sleep 8403 * 8404 * Frees the exact-match filter for each of the supplied addresses 8405 * 8406 * Returns a negative error number or the number of filters freed. 8407 */ 8408 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 8409 unsigned int viid, unsigned int naddr, 8410 const u8 **addr, bool sleep_ok) 8411 { 8412 int offset, ret = 0; 8413 struct fw_vi_mac_cmd c; 8414 unsigned int nfilters = 0; 8415 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8416 unsigned int rem = naddr; 8417 8418 if (naddr > max_naddr) 8419 return -EINVAL; 8420 8421 for (offset = 0; offset < (int)naddr ; /**/) { 8422 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8423 ? rem 8424 : ARRAY_SIZE(c.u.exact)); 8425 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8426 u.exact[fw_naddr]), 16); 8427 struct fw_vi_mac_exact *p; 8428 int i; 8429 8430 memset(&c, 0, sizeof(c)); 8431 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8432 F_FW_CMD_REQUEST | 8433 F_FW_CMD_WRITE | 8434 V_FW_CMD_EXEC(0) | 8435 V_FW_VI_MAC_CMD_VIID(viid)); 8436 c.freemacs_to_len16 = 8437 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8438 V_FW_CMD_LEN16(len16)); 8439 8440 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { 8441 p->valid_to_idx = cpu_to_be16( 8442 F_FW_VI_MAC_CMD_VALID | 8443 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 8444 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8445 } 8446 8447 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8448 if (ret) 8449 break; 8450 8451 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8452 u16 index = G_FW_VI_MAC_CMD_IDX( 8453 be16_to_cpu(p->valid_to_idx)); 8454 8455 if (index < max_naddr) 8456 nfilters++; 8457 } 8458 8459 offset += fw_naddr; 8460 rem -= fw_naddr; 8461 } 8462 8463 if (ret == 0) 8464 ret = nfilters; 8465 return ret; 8466 } 8467 8468 /** 8469 * t4_change_mac - modifies the exact-match filter for a MAC address 8470 * @adap: the adapter 8471 * @mbox: mailbox to use for the FW command 8472 * @viid: the VI id 8473 * @idx: index of existing filter for old value of MAC address, or -1 8474 * @addr: the new MAC address value 8475 * @persist: whether a new MAC allocation should be persistent 8476 * @smt_idx: add MAC to SMT and return its index, or NULL 8477 * 8478 * Modifies an exact-match filter and sets it to the new MAC address if 8479 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8480 * latter case the address is added persistently if @persist is %true. 8481 * 8482 * Note that in general it is not possible to modify the value of a given 8483 * filter so the generic way to modify an address filter is to free the one 8484 * being used by the old address value and allocate a new filter for the 8485 * new address value. 8486 * 8487 * Returns a negative error number or the index of the filter with the new 8488 * MAC value. Note that this index may differ from @idx. 8489 */ 8490 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8491 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8492 { 8493 int ret, mode; 8494 struct fw_vi_mac_cmd c; 8495 struct fw_vi_mac_exact *p = c.u.exact; 8496 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8497 8498 if (idx < 0) /* new allocation */ 8499 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8500 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8501 8502 memset(&c, 0, sizeof(c)); 8503 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8504 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8505 V_FW_VI_MAC_CMD_VIID(viid)); 8506 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8507 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8508 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8509 V_FW_VI_MAC_CMD_IDX(idx)); 8510 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8511 8512 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8513 if (ret == 0) { 8514 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8515 if (ret >= max_mac_addr) 8516 ret = -ENOMEM; 8517 if (smt_idx) { 8518 if (adap->params.viid_smt_extn_support) 8519 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8520 else { 8521 if (chip_id(adap) <= CHELSIO_T5) 8522 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8523 else 8524 *smt_idx = viid & M_FW_VIID_VIN; 8525 } 8526 } 8527 } 8528 return ret; 8529 } 8530 8531 /** 8532 * t4_set_addr_hash - program the MAC inexact-match hash filter 8533 * @adap: the adapter 8534 * @mbox: mailbox to use for the FW command 8535 * @viid: the VI id 8536 * @ucast: whether the hash filter should also match unicast addresses 8537 * @vec: the value to be written to the hash filter 8538 * @sleep_ok: call is allowed to sleep 8539 * 8540 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8541 */ 8542 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8543 bool ucast, u64 vec, bool sleep_ok) 8544 { 8545 struct fw_vi_mac_cmd c; 8546 u32 val; 8547 8548 memset(&c, 0, sizeof(c)); 8549 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8550 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8551 V_FW_VI_ENABLE_CMD_VIID(viid)); 8552 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8553 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8554 c.freemacs_to_len16 = cpu_to_be32(val); 8555 c.u.hash.hashvec = cpu_to_be64(vec); 8556 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8557 } 8558 8559 /** 8560 * t4_enable_vi_params - enable/disable a virtual interface 8561 * @adap: the adapter 8562 * @mbox: mailbox to use for the FW command 8563 * @viid: the VI id 8564 * @rx_en: 1=enable Rx, 0=disable Rx 8565 * @tx_en: 1=enable Tx, 0=disable Tx 8566 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8567 * 8568 * Enables/disables a virtual interface. Note that setting DCB Enable 8569 * only makes sense when enabling a Virtual Interface ... 8570 */ 8571 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8572 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8573 { 8574 struct fw_vi_enable_cmd c; 8575 8576 memset(&c, 0, sizeof(c)); 8577 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8578 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8579 V_FW_VI_ENABLE_CMD_VIID(viid)); 8580 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8581 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8582 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8583 FW_LEN16(c)); 8584 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8585 } 8586 8587 /** 8588 * t4_enable_vi - enable/disable a virtual interface 8589 * @adap: the adapter 8590 * @mbox: mailbox to use for the FW command 8591 * @viid: the VI id 8592 * @rx_en: 1=enable Rx, 0=disable Rx 8593 * @tx_en: 1=enable Tx, 0=disable Tx 8594 * 8595 * Enables/disables a virtual interface. Note that setting DCB Enable 8596 * only makes sense when enabling a Virtual Interface ... 8597 */ 8598 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8599 bool rx_en, bool tx_en) 8600 { 8601 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8602 } 8603 8604 /** 8605 * t4_identify_port - identify a VI's port by blinking its LED 8606 * @adap: the adapter 8607 * @mbox: mailbox to use for the FW command 8608 * @viid: the VI id 8609 * @nblinks: how many times to blink LED at 2.5 Hz 8610 * 8611 * Identifies a VI's port by blinking its LED. 8612 */ 8613 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8614 unsigned int nblinks) 8615 { 8616 struct fw_vi_enable_cmd c; 8617 8618 memset(&c, 0, sizeof(c)); 8619 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8620 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8621 V_FW_VI_ENABLE_CMD_VIID(viid)); 8622 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8623 c.blinkdur = cpu_to_be16(nblinks); 8624 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8625 } 8626 8627 /** 8628 * t4_iq_stop - stop an ingress queue and its FLs 8629 * @adap: the adapter 8630 * @mbox: mailbox to use for the FW command 8631 * @pf: the PF owning the queues 8632 * @vf: the VF owning the queues 8633 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8634 * @iqid: ingress queue id 8635 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8636 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8637 * 8638 * Stops an ingress queue and its associated FLs, if any. This causes 8639 * any current or future data/messages destined for these queues to be 8640 * tossed. 8641 */ 8642 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8643 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8644 unsigned int fl0id, unsigned int fl1id) 8645 { 8646 struct fw_iq_cmd c; 8647 8648 memset(&c, 0, sizeof(c)); 8649 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8650 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8651 V_FW_IQ_CMD_VFN(vf)); 8652 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8653 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8654 c.iqid = cpu_to_be16(iqid); 8655 c.fl0id = cpu_to_be16(fl0id); 8656 c.fl1id = cpu_to_be16(fl1id); 8657 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8658 } 8659 8660 /** 8661 * t4_iq_free - free an ingress queue and its FLs 8662 * @adap: the adapter 8663 * @mbox: mailbox to use for the FW command 8664 * @pf: the PF owning the queues 8665 * @vf: the VF owning the queues 8666 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8667 * @iqid: ingress queue id 8668 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8669 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8670 * 8671 * Frees an ingress queue and its associated FLs, if any. 8672 */ 8673 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8674 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8675 unsigned int fl0id, unsigned int fl1id) 8676 { 8677 struct fw_iq_cmd c; 8678 8679 memset(&c, 0, sizeof(c)); 8680 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8681 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8682 V_FW_IQ_CMD_VFN(vf)); 8683 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8684 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8685 c.iqid = cpu_to_be16(iqid); 8686 c.fl0id = cpu_to_be16(fl0id); 8687 c.fl1id = cpu_to_be16(fl1id); 8688 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8689 } 8690 8691 /** 8692 * t4_eth_eq_stop - stop an Ethernet egress queue 8693 * @adap: the adapter 8694 * @mbox: mailbox to use for the FW command 8695 * @pf: the PF owning the queues 8696 * @vf: the VF owning the queues 8697 * @eqid: egress queue id 8698 * 8699 * Stops an Ethernet egress queue. The queue can be reinitialized or 8700 * freed but is not otherwise functional after this call. 8701 */ 8702 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8703 unsigned int vf, unsigned int eqid) 8704 { 8705 struct fw_eq_eth_cmd c; 8706 8707 memset(&c, 0, sizeof(c)); 8708 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8709 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8710 V_FW_EQ_ETH_CMD_PFN(pf) | 8711 V_FW_EQ_ETH_CMD_VFN(vf)); 8712 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c)); 8713 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8714 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8715 } 8716 8717 /** 8718 * t4_eth_eq_free - free an Ethernet egress queue 8719 * @adap: the adapter 8720 * @mbox: mailbox to use for the FW command 8721 * @pf: the PF owning the queue 8722 * @vf: the VF owning the queue 8723 * @eqid: egress queue id 8724 * 8725 * Frees an Ethernet egress queue. 8726 */ 8727 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8728 unsigned int vf, unsigned int eqid) 8729 { 8730 struct fw_eq_eth_cmd c; 8731 8732 memset(&c, 0, sizeof(c)); 8733 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8734 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8735 V_FW_EQ_ETH_CMD_PFN(pf) | 8736 V_FW_EQ_ETH_CMD_VFN(vf)); 8737 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8738 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8739 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8740 } 8741 8742 /** 8743 * t4_ctrl_eq_free - free a control egress queue 8744 * @adap: the adapter 8745 * @mbox: mailbox to use for the FW command 8746 * @pf: the PF owning the queue 8747 * @vf: the VF owning the queue 8748 * @eqid: egress queue id 8749 * 8750 * Frees a control egress queue. 8751 */ 8752 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8753 unsigned int vf, unsigned int eqid) 8754 { 8755 struct fw_eq_ctrl_cmd c; 8756 8757 memset(&c, 0, sizeof(c)); 8758 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8759 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8760 V_FW_EQ_CTRL_CMD_PFN(pf) | 8761 V_FW_EQ_CTRL_CMD_VFN(vf)); 8762 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8763 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8764 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8765 } 8766 8767 /** 8768 * t4_ofld_eq_free - free an offload egress queue 8769 * @adap: the adapter 8770 * @mbox: mailbox to use for the FW command 8771 * @pf: the PF owning the queue 8772 * @vf: the VF owning the queue 8773 * @eqid: egress queue id 8774 * 8775 * Frees a control egress queue. 8776 */ 8777 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8778 unsigned int vf, unsigned int eqid) 8779 { 8780 struct fw_eq_ofld_cmd c; 8781 8782 memset(&c, 0, sizeof(c)); 8783 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8784 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8785 V_FW_EQ_OFLD_CMD_PFN(pf) | 8786 V_FW_EQ_OFLD_CMD_VFN(vf)); 8787 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8788 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8789 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8790 } 8791 8792 /** 8793 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8794 * @link_down_rc: Link Down Reason Code 8795 * 8796 * Returns a string representation of the Link Down Reason Code. 8797 */ 8798 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8799 { 8800 static const char *reason[] = { 8801 "Link Down", 8802 "Remote Fault", 8803 "Auto-negotiation Failure", 8804 "Reserved3", 8805 "Insufficient Airflow", 8806 "Unable To Determine Reason", 8807 "No RX Signal Detected", 8808 "Reserved7", 8809 }; 8810 8811 if (link_down_rc >= ARRAY_SIZE(reason)) 8812 return "Bad Reason Code"; 8813 8814 return reason[link_down_rc]; 8815 } 8816 8817 /* 8818 * Return the highest speed set in the port capabilities, in Mb/s. 8819 */ 8820 unsigned int fwcap_to_speed(uint32_t caps) 8821 { 8822 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8823 do { \ 8824 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8825 return __speed; \ 8826 } while (0) 8827 8828 TEST_SPEED_RETURN(400G, 400000); 8829 TEST_SPEED_RETURN(200G, 200000); 8830 TEST_SPEED_RETURN(100G, 100000); 8831 TEST_SPEED_RETURN(50G, 50000); 8832 TEST_SPEED_RETURN(40G, 40000); 8833 TEST_SPEED_RETURN(25G, 25000); 8834 TEST_SPEED_RETURN(10G, 10000); 8835 TEST_SPEED_RETURN(1G, 1000); 8836 TEST_SPEED_RETURN(100M, 100); 8837 8838 #undef TEST_SPEED_RETURN 8839 8840 return 0; 8841 } 8842 8843 /* 8844 * Return the port capabilities bit for the given speed, which is in Mb/s. 8845 */ 8846 uint32_t speed_to_fwcap(unsigned int speed) 8847 { 8848 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8849 do { \ 8850 if (speed == __speed) \ 8851 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8852 } while (0) 8853 8854 TEST_SPEED_RETURN(400G, 400000); 8855 TEST_SPEED_RETURN(200G, 200000); 8856 TEST_SPEED_RETURN(100G, 100000); 8857 TEST_SPEED_RETURN(50G, 50000); 8858 TEST_SPEED_RETURN(40G, 40000); 8859 TEST_SPEED_RETURN(25G, 25000); 8860 TEST_SPEED_RETURN(10G, 10000); 8861 TEST_SPEED_RETURN(1G, 1000); 8862 TEST_SPEED_RETURN(100M, 100); 8863 8864 #undef TEST_SPEED_RETURN 8865 8866 return 0; 8867 } 8868 8869 /* 8870 * Return the port capabilities bit for the highest speed in the capabilities. 8871 */ 8872 uint32_t fwcap_top_speed(uint32_t caps) 8873 { 8874 #define TEST_SPEED_RETURN(__caps_speed) \ 8875 do { \ 8876 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8877 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8878 } while (0) 8879 8880 TEST_SPEED_RETURN(400G); 8881 TEST_SPEED_RETURN(200G); 8882 TEST_SPEED_RETURN(100G); 8883 TEST_SPEED_RETURN(50G); 8884 TEST_SPEED_RETURN(40G); 8885 TEST_SPEED_RETURN(25G); 8886 TEST_SPEED_RETURN(10G); 8887 TEST_SPEED_RETURN(1G); 8888 TEST_SPEED_RETURN(100M); 8889 8890 #undef TEST_SPEED_RETURN 8891 8892 return 0; 8893 } 8894 8895 /** 8896 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8897 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8898 * 8899 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8900 * 32-bit Port Capabilities value. 8901 */ 8902 static uint32_t lstatus_to_fwcap(u32 lstatus) 8903 { 8904 uint32_t linkattr = 0; 8905 8906 /* 8907 * Unfortunately the format of the Link Status in the old 8908 * 16-bit Port Information message isn't the same as the 8909 * 16-bit Port Capabilities bitfield used everywhere else ... 8910 */ 8911 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8912 linkattr |= FW_PORT_CAP32_FC_RX; 8913 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8914 linkattr |= FW_PORT_CAP32_FC_TX; 8915 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8916 linkattr |= FW_PORT_CAP32_SPEED_100M; 8917 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8918 linkattr |= FW_PORT_CAP32_SPEED_1G; 8919 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8920 linkattr |= FW_PORT_CAP32_SPEED_10G; 8921 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8922 linkattr |= FW_PORT_CAP32_SPEED_25G; 8923 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8924 linkattr |= FW_PORT_CAP32_SPEED_40G; 8925 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8926 linkattr |= FW_PORT_CAP32_SPEED_100G; 8927 8928 return linkattr; 8929 } 8930 8931 /* 8932 * Updates all fields owned by the common code in port_info and link_config 8933 * based on information provided by the firmware. Does not touch any 8934 * requested_* field. 8935 */ 8936 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8937 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8938 { 8939 struct link_config old_lc, *lc = &pi->link_cfg; 8940 unsigned char fc; 8941 u32 stat, linkattr; 8942 int old_ptype, old_mtype; 8943 8944 old_ptype = pi->port_type; 8945 old_mtype = pi->mod_type; 8946 old_lc = *lc; 8947 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8948 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8949 8950 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8951 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8952 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8953 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8954 8955 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8956 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8957 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8958 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8959 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8960 8961 linkattr = lstatus_to_fwcap(stat); 8962 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8963 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8964 8965 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8966 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8967 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8968 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8969 8970 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); 8971 lc->acaps = be32_to_cpu(p->u.info32.acaps32); 8972 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); 8973 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8974 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8975 8976 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8977 } else { 8978 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8979 return; 8980 } 8981 8982 lc->speed = fwcap_to_speed(linkattr); 8983 lc->fec = fwcap_to_fec(linkattr, true); 8984 8985 fc = 0; 8986 if (linkattr & FW_PORT_CAP32_FC_RX) 8987 fc |= PAUSE_RX; 8988 if (linkattr & FW_PORT_CAP32_FC_TX) 8989 fc |= PAUSE_TX; 8990 lc->fc = fc; 8991 8992 if (mod_changed != NULL) 8993 *mod_changed = false; 8994 if (link_changed != NULL) 8995 *link_changed = false; 8996 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 8997 old_lc.pcaps != lc->pcaps) { 8998 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) 8999 lc->fec_hint = fwcap_to_fec(lc->acaps, true); 9000 if (mod_changed != NULL) 9001 *mod_changed = true; 9002 } 9003 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 9004 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 9005 if (link_changed != NULL) 9006 *link_changed = true; 9007 } 9008 } 9009 9010 /** 9011 * t4_update_port_info - retrieve and update port information if changed 9012 * @pi: the port_info 9013 * 9014 * We issue a Get Port Information Command to the Firmware and, if 9015 * successful, we check to see if anything is different from what we 9016 * last recorded and update things accordingly. 9017 */ 9018 int t4_update_port_info(struct port_info *pi) 9019 { 9020 struct adapter *sc = pi->adapter; 9021 struct fw_port_cmd cmd; 9022 enum fw_port_action action; 9023 int ret; 9024 9025 memset(&cmd, 0, sizeof(cmd)); 9026 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 9027 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9028 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 9029 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 9030 FW_PORT_ACTION_GET_PORT_INFO; 9031 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 9032 FW_LEN16(cmd)); 9033 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 9034 if (ret) 9035 return ret; 9036 9037 handle_port_info(pi, &cmd, action, NULL, NULL); 9038 return 0; 9039 } 9040 9041 /** 9042 * t4_handle_fw_rpl - process a FW reply message 9043 * @adap: the adapter 9044 * @rpl: start of the FW message 9045 * 9046 * Processes a FW message, such as link state change messages. 9047 */ 9048 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 9049 { 9050 u8 opcode = *(const u8 *)rpl; 9051 const struct fw_port_cmd *p = (const void *)rpl; 9052 enum fw_port_action action = 9053 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 9054 bool mod_changed, link_changed; 9055 9056 if (opcode == FW_PORT_CMD && 9057 (action == FW_PORT_ACTION_GET_PORT_INFO || 9058 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 9059 /* link/module state change message */ 9060 int i; 9061 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 9062 struct port_info *pi = NULL; 9063 struct link_config *lc; 9064 9065 for_each_port(adap, i) { 9066 pi = adap2pinfo(adap, i); 9067 if (pi->tx_chan == chan) 9068 break; 9069 } 9070 9071 lc = &pi->link_cfg; 9072 PORT_LOCK(pi); 9073 handle_port_info(pi, p, action, &mod_changed, &link_changed); 9074 PORT_UNLOCK(pi); 9075 if (mod_changed) 9076 t4_os_portmod_changed(pi); 9077 if (link_changed) { 9078 PORT_LOCK(pi); 9079 t4_os_link_changed(pi); 9080 PORT_UNLOCK(pi); 9081 } 9082 } else { 9083 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 9084 return -EINVAL; 9085 } 9086 return 0; 9087 } 9088 9089 /** 9090 * get_pci_mode - determine a card's PCI mode 9091 * @adapter: the adapter 9092 * @p: where to store the PCI settings 9093 * 9094 * Determines a card's PCI mode and associated parameters, such as speed 9095 * and width. 9096 */ 9097 static void get_pci_mode(struct adapter *adapter, 9098 struct pci_params *p) 9099 { 9100 u16 val; 9101 u32 pcie_cap; 9102 9103 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9104 if (pcie_cap) { 9105 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 9106 p->speed = val & PCI_EXP_LNKSTA_CLS; 9107 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 9108 } 9109 } 9110 9111 struct flash_desc { 9112 u32 vendor_and_model_id; 9113 u32 size_mb; 9114 }; 9115 9116 int t4_get_flash_params(struct adapter *adapter) 9117 { 9118 /* 9119 * Table for non-standard supported Flash parts. Note, all Flash 9120 * parts must have 64KB sectors. 9121 */ 9122 static struct flash_desc supported_flash[] = { 9123 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 9124 }; 9125 9126 int ret; 9127 u32 flashid = 0; 9128 unsigned int part, manufacturer; 9129 unsigned int density, size = 0; 9130 9131 9132 /* 9133 * Issue a Read ID Command to the Flash part. We decode supported 9134 * Flash parts and their sizes from this. There's a newer Query 9135 * Command which can retrieve detailed geometry information but many 9136 * Flash parts don't support it. 9137 */ 9138 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 9139 if (!ret) 9140 ret = sf1_read(adapter, 3, 0, 1, &flashid); 9141 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 9142 if (ret < 0) 9143 return ret; 9144 9145 /* 9146 * Check to see if it's one of our non-standard supported Flash parts. 9147 */ 9148 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 9149 if (supported_flash[part].vendor_and_model_id == flashid) { 9150 adapter->params.sf_size = 9151 supported_flash[part].size_mb; 9152 adapter->params.sf_nsec = 9153 adapter->params.sf_size / SF_SEC_SIZE; 9154 goto found; 9155 } 9156 9157 /* 9158 * Decode Flash part size. The code below looks repetative with 9159 * common encodings, but that's not guaranteed in the JEDEC 9160 * specification for the Read JADEC ID command. The only thing that 9161 * we're guaranteed by the JADEC specification is where the 9162 * Manufacturer ID is in the returned result. After that each 9163 * Manufacturer ~could~ encode things completely differently. 9164 * Note, all Flash parts must have 64KB sectors. 9165 */ 9166 manufacturer = flashid & 0xff; 9167 switch (manufacturer) { 9168 case 0x20: /* Micron/Numonix */ 9169 /* 9170 * This Density -> Size decoding table is taken from Micron 9171 * Data Sheets. 9172 */ 9173 density = (flashid >> 16) & 0xff; 9174 switch (density) { 9175 case 0x14: size = 1 << 20; break; /* 1MB */ 9176 case 0x15: size = 1 << 21; break; /* 2MB */ 9177 case 0x16: size = 1 << 22; break; /* 4MB */ 9178 case 0x17: size = 1 << 23; break; /* 8MB */ 9179 case 0x18: size = 1 << 24; break; /* 16MB */ 9180 case 0x19: size = 1 << 25; break; /* 32MB */ 9181 case 0x20: size = 1 << 26; break; /* 64MB */ 9182 case 0x21: size = 1 << 27; break; /* 128MB */ 9183 case 0x22: size = 1 << 28; break; /* 256MB */ 9184 } 9185 break; 9186 9187 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 9188 /* 9189 * This Density -> Size decoding table is taken from ISSI 9190 * Data Sheets. 9191 */ 9192 density = (flashid >> 16) & 0xff; 9193 switch (density) { 9194 case 0x16: size = 1 << 25; break; /* 32MB */ 9195 case 0x17: size = 1 << 26; break; /* 64MB */ 9196 } 9197 break; 9198 9199 case 0xc2: /* Macronix */ 9200 /* 9201 * This Density -> Size decoding table is taken from Macronix 9202 * Data Sheets. 9203 */ 9204 density = (flashid >> 16) & 0xff; 9205 switch (density) { 9206 case 0x17: size = 1 << 23; break; /* 8MB */ 9207 case 0x18: size = 1 << 24; break; /* 16MB */ 9208 } 9209 break; 9210 9211 case 0xef: /* Winbond */ 9212 /* 9213 * This Density -> Size decoding table is taken from Winbond 9214 * Data Sheets. 9215 */ 9216 density = (flashid >> 16) & 0xff; 9217 switch (density) { 9218 case 0x17: size = 1 << 23; break; /* 8MB */ 9219 case 0x18: size = 1 << 24; break; /* 16MB */ 9220 } 9221 break; 9222 } 9223 9224 /* If we didn't recognize the FLASH part, that's no real issue: the 9225 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 9226 * use a FLASH part which is at least 4MB in size and has 64KB 9227 * sectors. The unrecognized FLASH part is likely to be much larger 9228 * than 4MB, but that's all we really need. 9229 */ 9230 if (size == 0) { 9231 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 9232 size = 1 << 22; 9233 } 9234 9235 /* 9236 * Store decoded Flash size and fall through into vetting code. 9237 */ 9238 adapter->params.sf_size = size; 9239 adapter->params.sf_nsec = size / SF_SEC_SIZE; 9240 9241 found: 9242 /* 9243 * We should ~probably~ reject adapters with FLASHes which are too 9244 * small but we have some legacy FPGAs with small FLASHes that we'd 9245 * still like to use. So instead we emit a scary message ... 9246 */ 9247 if (adapter->params.sf_size < FLASH_MIN_SIZE) 9248 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 9249 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 9250 9251 return 0; 9252 } 9253 9254 static void set_pcie_completion_timeout(struct adapter *adapter, 9255 u8 range) 9256 { 9257 u16 val; 9258 u32 pcie_cap; 9259 9260 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9261 if (pcie_cap) { 9262 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 9263 val &= 0xfff0; 9264 val |= range ; 9265 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 9266 } 9267 } 9268 9269 const struct chip_params *t4_get_chip_params(int chipid) 9270 { 9271 static const struct chip_params chip_params[] = { 9272 { 9273 /* T4 */ 9274 .nchan = NCHAN, 9275 .pm_stats_cnt = PM_NSTATS, 9276 .cng_ch_bits_log = 2, 9277 .nsched_cls = 15, 9278 .cim_num_obq = CIM_NUM_OBQ, 9279 .filter_opt_len = FILTER_OPT_LEN, 9280 .mps_rplc_size = 128, 9281 .vfcount = 128, 9282 .sge_fl_db = F_DBPRIO, 9283 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 9284 .rss_nentries = RSS_NENTRIES, 9285 }, 9286 { 9287 /* T5 */ 9288 .nchan = NCHAN, 9289 .pm_stats_cnt = PM_NSTATS, 9290 .cng_ch_bits_log = 2, 9291 .nsched_cls = 16, 9292 .cim_num_obq = CIM_NUM_OBQ_T5, 9293 .filter_opt_len = T5_FILTER_OPT_LEN, 9294 .mps_rplc_size = 128, 9295 .vfcount = 128, 9296 .sge_fl_db = F_DBPRIO | F_DBTYPE, 9297 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9298 .rss_nentries = RSS_NENTRIES, 9299 }, 9300 { 9301 /* T6 */ 9302 .nchan = T6_NCHAN, 9303 .pm_stats_cnt = T6_PM_NSTATS, 9304 .cng_ch_bits_log = 3, 9305 .nsched_cls = 16, 9306 .cim_num_obq = CIM_NUM_OBQ_T5, 9307 .filter_opt_len = T5_FILTER_OPT_LEN, 9308 .mps_rplc_size = 256, 9309 .vfcount = 256, 9310 .sge_fl_db = 0, 9311 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9312 .rss_nentries = T6_RSS_NENTRIES, 9313 }, 9314 }; 9315 9316 chipid -= CHELSIO_T4; 9317 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 9318 return NULL; 9319 9320 return &chip_params[chipid]; 9321 } 9322 9323 /** 9324 * t4_prep_adapter - prepare SW and HW for operation 9325 * @adapter: the adapter 9326 * @buf: temporary space of at least VPD_LEN size provided by the caller. 9327 * 9328 * Initialize adapter SW state for the various HW modules, set initial 9329 * values for some adapter tunables, take PHYs out of reset, and 9330 * initialize the MDIO interface. 9331 */ 9332 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 9333 { 9334 int ret; 9335 uint16_t device_id; 9336 uint32_t pl_rev; 9337 9338 get_pci_mode(adapter, &adapter->params.pci); 9339 9340 pl_rev = t4_read_reg(adapter, A_PL_REV); 9341 adapter->params.chipid = G_CHIPID(pl_rev); 9342 adapter->params.rev = G_REV(pl_rev); 9343 if (adapter->params.chipid == 0) { 9344 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 9345 adapter->params.chipid = CHELSIO_T4; 9346 9347 /* T4A1 chip is not supported */ 9348 if (adapter->params.rev == 1) { 9349 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 9350 return -EINVAL; 9351 } 9352 } 9353 9354 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 9355 if (adapter->chip_params == NULL) 9356 return -EINVAL; 9357 9358 adapter->params.pci.vpd_cap_addr = 9359 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 9360 9361 ret = t4_get_flash_params(adapter); 9362 if (ret < 0) 9363 return ret; 9364 9365 /* Cards with real ASICs have the chipid in the PCIe device id */ 9366 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 9367 if (device_id >> 12 == chip_id(adapter)) 9368 adapter->params.cim_la_size = CIMLA_SIZE; 9369 else { 9370 /* FPGA */ 9371 adapter->params.fpga = 1; 9372 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 9373 } 9374 9375 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 9376 if (ret < 0) 9377 return ret; 9378 9379 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 9380 9381 /* 9382 * Default port and clock for debugging in case we can't reach FW. 9383 */ 9384 adapter->params.nports = 1; 9385 adapter->params.portvec = 1; 9386 adapter->params.vpd.cclk = 50000; 9387 9388 /* Set pci completion timeout value to 4 seconds. */ 9389 set_pcie_completion_timeout(adapter, 0xd); 9390 return 0; 9391 } 9392 9393 /** 9394 * t4_shutdown_adapter - shut down adapter, host & wire 9395 * @adapter: the adapter 9396 * 9397 * Perform an emergency shutdown of the adapter and stop it from 9398 * continuing any further communication on the ports or DMA to the 9399 * host. This is typically used when the adapter and/or firmware 9400 * have crashed and we want to prevent any further accidental 9401 * communication with the rest of the world. This will also force 9402 * the port Link Status to go down -- if register writes work -- 9403 * which should help our peers figure out that we're down. 9404 */ 9405 int t4_shutdown_adapter(struct adapter *adapter) 9406 { 9407 int port; 9408 const bool bt = adapter->bt_map != 0; 9409 9410 t4_intr_disable(adapter); 9411 if (bt) 9412 t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000); 9413 for_each_port(adapter, port) { 9414 u32 a_port_cfg = is_t4(adapter) ? 9415 PORT_REG(port, A_XGMAC_PORT_CFG) : 9416 T5_PORT_REG(port, A_MAC_PORT_CFG); 9417 9418 t4_write_reg(adapter, a_port_cfg, 9419 t4_read_reg(adapter, a_port_cfg) 9420 & ~V_SIGNAL_DET(1)); 9421 if (!bt) { 9422 u32 hss_cfg0 = is_t4(adapter) ? 9423 PORT_REG(port, A_XGMAC_PORT_HSS_CFG0) : 9424 T5_PORT_REG(port, A_MAC_PORT_HSS_CFG0); 9425 t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB | 9426 F_HSSPDWNPLLA | F_HSSPLLBYPB | F_HSSPLLBYPA, 9427 F_HSSPDWNPLLB | F_HSSPDWNPLLA | F_HSSPLLBYPB | 9428 F_HSSPLLBYPA); 9429 } 9430 } 9431 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9432 9433 return 0; 9434 } 9435 9436 /** 9437 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9438 * @adapter: the adapter 9439 * @qid: the Queue ID 9440 * @qtype: the Ingress or Egress type for @qid 9441 * @user: true if this request is for a user mode queue 9442 * @pbar2_qoffset: BAR2 Queue Offset 9443 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9444 * 9445 * Returns the BAR2 SGE Queue Registers information associated with the 9446 * indicated Absolute Queue ID. These are passed back in return value 9447 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9448 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9449 * 9450 * This may return an error which indicates that BAR2 SGE Queue 9451 * registers aren't available. If an error is not returned, then the 9452 * following values are returned: 9453 * 9454 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9455 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9456 * 9457 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9458 * require the "Inferred Queue ID" ability may be used. E.g. the 9459 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9460 * then these "Inferred Queue ID" register may not be used. 9461 */ 9462 int t4_bar2_sge_qregs(struct adapter *adapter, 9463 unsigned int qid, 9464 enum t4_bar2_qtype qtype, 9465 int user, 9466 u64 *pbar2_qoffset, 9467 unsigned int *pbar2_qid) 9468 { 9469 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9470 u64 bar2_page_offset, bar2_qoffset; 9471 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9472 9473 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9474 * mode queues. 9475 */ 9476 if (!user && is_t4(adapter)) 9477 return -EINVAL; 9478 9479 /* Get our SGE Page Size parameters. 9480 */ 9481 page_shift = adapter->params.sge.page_shift; 9482 page_size = 1 << page_shift; 9483 9484 /* Get the right Queues per Page parameters for our Queue. 9485 */ 9486 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9487 ? adapter->params.sge.eq_s_qpp 9488 : adapter->params.sge.iq_s_qpp); 9489 qpp_mask = (1 << qpp_shift) - 1; 9490 9491 /* Calculate the basics of the BAR2 SGE Queue register area: 9492 * o The BAR2 page the Queue registers will be in. 9493 * o The BAR2 Queue ID. 9494 * o The BAR2 Queue ID Offset into the BAR2 page. 9495 */ 9496 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9497 bar2_qid = qid & qpp_mask; 9498 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9499 9500 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9501 * hardware will infer the Absolute Queue ID simply from the writes to 9502 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9503 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9504 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9505 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9506 * from the BAR2 Page and BAR2 Queue ID. 9507 * 9508 * One important censequence of this is that some BAR2 SGE registers 9509 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9510 * there. But other registers synthesize the SGE Queue ID purely 9511 * from the writes to the registers -- the Write Combined Doorbell 9512 * Buffer is a good example. These BAR2 SGE Registers are only 9513 * available for those BAR2 SGE Register areas where the SGE Absolute 9514 * Queue ID can be inferred from simple writes. 9515 */ 9516 bar2_qoffset = bar2_page_offset; 9517 bar2_qinferred = (bar2_qid_offset < page_size); 9518 if (bar2_qinferred) { 9519 bar2_qoffset += bar2_qid_offset; 9520 bar2_qid = 0; 9521 } 9522 9523 *pbar2_qoffset = bar2_qoffset; 9524 *pbar2_qid = bar2_qid; 9525 return 0; 9526 } 9527 9528 /** 9529 * t4_init_devlog_params - initialize adapter->params.devlog 9530 * @adap: the adapter 9531 * @fw_attach: whether we can talk to the firmware 9532 * 9533 * Initialize various fields of the adapter's Firmware Device Log 9534 * Parameters structure. 9535 */ 9536 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9537 { 9538 struct devlog_params *dparams = &adap->params.devlog; 9539 u32 pf_dparams; 9540 unsigned int devlog_meminfo; 9541 struct fw_devlog_cmd devlog_cmd; 9542 int ret; 9543 9544 /* If we're dealing with newer firmware, the Device Log Paramerters 9545 * are stored in a designated register which allows us to access the 9546 * Device Log even if we can't talk to the firmware. 9547 */ 9548 pf_dparams = 9549 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9550 if (pf_dparams) { 9551 unsigned int nentries, nentries128; 9552 9553 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9554 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9555 9556 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9557 nentries = (nentries128 + 1) * 128; 9558 dparams->size = nentries * sizeof(struct fw_devlog_e); 9559 9560 return 0; 9561 } 9562 9563 /* 9564 * For any failing returns ... 9565 */ 9566 memset(dparams, 0, sizeof *dparams); 9567 9568 /* 9569 * If we can't talk to the firmware, there's really nothing we can do 9570 * at this point. 9571 */ 9572 if (!fw_attach) 9573 return -ENXIO; 9574 9575 /* Otherwise, ask the firmware for it's Device Log Parameters. 9576 */ 9577 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9578 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9579 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9580 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9581 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9582 &devlog_cmd); 9583 if (ret) 9584 return ret; 9585 9586 devlog_meminfo = 9587 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9588 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9589 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9590 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9591 9592 return 0; 9593 } 9594 9595 /** 9596 * t4_init_sge_params - initialize adap->params.sge 9597 * @adapter: the adapter 9598 * 9599 * Initialize various fields of the adapter's SGE Parameters structure. 9600 */ 9601 int t4_init_sge_params(struct adapter *adapter) 9602 { 9603 u32 r; 9604 struct sge_params *sp = &adapter->params.sge; 9605 unsigned i, tscale = 1; 9606 9607 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9608 sp->counter_val[0] = G_THRESHOLD_0(r); 9609 sp->counter_val[1] = G_THRESHOLD_1(r); 9610 sp->counter_val[2] = G_THRESHOLD_2(r); 9611 sp->counter_val[3] = G_THRESHOLD_3(r); 9612 9613 if (chip_id(adapter) >= CHELSIO_T6) { 9614 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9615 tscale = G_TSCALE(r); 9616 if (tscale == 0) 9617 tscale = 1; 9618 else 9619 tscale += 2; 9620 } 9621 9622 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9623 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9624 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9625 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9626 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9627 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9628 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9629 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9630 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9631 9632 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9633 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9634 if (is_t4(adapter)) 9635 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9636 else if (is_t5(adapter)) 9637 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9638 else 9639 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9640 9641 /* egress queues: log2 of # of doorbells per BAR2 page */ 9642 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9643 r >>= S_QUEUESPERPAGEPF0 + 9644 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9645 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9646 9647 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9648 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9649 r >>= S_QUEUESPERPAGEPF0 + 9650 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9651 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9652 9653 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9654 r >>= S_HOSTPAGESIZEPF0 + 9655 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9656 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9657 9658 r = t4_read_reg(adapter, A_SGE_CONTROL); 9659 sp->sge_control = r; 9660 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9661 sp->fl_pktshift = G_PKTSHIFT(r); 9662 if (chip_id(adapter) <= CHELSIO_T5) { 9663 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9664 X_INGPADBOUNDARY_SHIFT); 9665 } else { 9666 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9667 X_T6_INGPADBOUNDARY_SHIFT); 9668 } 9669 if (is_t4(adapter)) 9670 sp->pack_boundary = sp->pad_boundary; 9671 else { 9672 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9673 if (G_INGPACKBOUNDARY(r) == 0) 9674 sp->pack_boundary = 16; 9675 else 9676 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9677 } 9678 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9679 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9680 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9681 9682 return 0; 9683 } 9684 9685 /* Convert the LE's hardware hash mask to a shorter filter mask. */ 9686 static inline uint16_t 9687 hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode) 9688 { 9689 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 9690 int i; 9691 uint16_t filter_mask; 9692 uint64_t mask; /* field mask */ 9693 9694 filter_mask = 0; 9695 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 9696 if ((filter_mode & (1 << i)) == 0) 9697 continue; 9698 mask = (1 << width[i]) - 1; 9699 if ((hashmask & mask) == mask) 9700 filter_mask |= 1 << i; 9701 hashmask >>= width[i]; 9702 } 9703 9704 return (filter_mask); 9705 } 9706 9707 /* 9708 * Read and cache the adapter's compressed filter mode and ingress config. 9709 */ 9710 static void 9711 read_filter_mode_and_ingress_config(struct adapter *adap) 9712 { 9713 int rc; 9714 uint32_t v, param[2], val[2]; 9715 struct tp_params *tpp = &adap->params.tp; 9716 uint64_t hash_mask; 9717 9718 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9719 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9720 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 9721 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9722 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9723 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 9724 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); 9725 if (rc == 0) { 9726 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); 9727 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); 9728 tpp->vnic_mode = val[1]; 9729 } else { 9730 /* 9731 * Old firmware. Read filter mode/mask and ingress config 9732 * straight from the hardware. 9733 */ 9734 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true); 9735 tpp->filter_mode = v & 0xffff; 9736 9737 hash_mask = 0; 9738 if (chip_id(adap) > CHELSIO_T4) { 9739 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9740 hash_mask = v; 9741 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9742 hash_mask |= (u64)v << 32; 9743 } 9744 tpp->filter_mask = hashmask_to_filtermask(hash_mask, 9745 tpp->filter_mode); 9746 9747 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true); 9748 if (v & F_VNIC) 9749 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; 9750 else 9751 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; 9752 } 9753 9754 /* 9755 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9756 * shift positions of several elements of the Compressed Filter Tuple 9757 * for this adapter which we need frequently ... 9758 */ 9759 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9760 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9761 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9762 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9763 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9764 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9765 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9766 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9767 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9768 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9769 } 9770 9771 /** 9772 * t4_init_tp_params - initialize adap->params.tp 9773 * @adap: the adapter 9774 * 9775 * Initialize various fields of the adapter's TP Parameters structure. 9776 */ 9777 int t4_init_tp_params(struct adapter *adap) 9778 { 9779 int chan; 9780 u32 tx_len, rx_len, r, v; 9781 struct tp_params *tpp = &adap->params.tp; 9782 9783 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9784 tpp->tre = G_TIMERRESOLUTION(v); 9785 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9786 9787 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9788 for (chan = 0; chan < MAX_NCHAN; chan++) 9789 tpp->tx_modq[chan] = chan; 9790 9791 read_filter_mode_and_ingress_config(adap); 9792 9793 if (chip_id(adap) > CHELSIO_T5) { 9794 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9795 tpp->rx_pkt_encap = v & F_CRXPKTENC; 9796 } else 9797 tpp->rx_pkt_encap = false; 9798 9799 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE); 9800 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE); 9801 9802 r = t4_read_reg(adap, A_TP_PARA_REG2); 9803 rx_len = min(rx_len, G_MAXRXDATA(r)); 9804 tx_len = min(tx_len, G_MAXRXDATA(r)); 9805 9806 r = t4_read_reg(adap, A_TP_PARA_REG7); 9807 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 9808 rx_len = min(rx_len, v); 9809 tx_len = min(tx_len, v); 9810 9811 tpp->max_tx_pdu = tx_len; 9812 tpp->max_rx_pdu = rx_len; 9813 9814 return 0; 9815 } 9816 9817 /** 9818 * t4_filter_field_shift - calculate filter field shift 9819 * @adap: the adapter 9820 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9821 * 9822 * Return the shift position of a filter field within the Compressed 9823 * Filter Tuple. The filter field is specified via its selection bit 9824 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9825 */ 9826 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9827 { 9828 const unsigned int filter_mode = adap->params.tp.filter_mode; 9829 unsigned int sel; 9830 int field_shift; 9831 9832 if ((filter_mode & filter_sel) == 0) 9833 return -1; 9834 9835 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9836 switch (filter_mode & sel) { 9837 case F_FCOE: 9838 field_shift += W_FT_FCOE; 9839 break; 9840 case F_PORT: 9841 field_shift += W_FT_PORT; 9842 break; 9843 case F_VNIC_ID: 9844 field_shift += W_FT_VNIC_ID; 9845 break; 9846 case F_VLAN: 9847 field_shift += W_FT_VLAN; 9848 break; 9849 case F_TOS: 9850 field_shift += W_FT_TOS; 9851 break; 9852 case F_PROTOCOL: 9853 field_shift += W_FT_PROTOCOL; 9854 break; 9855 case F_ETHERTYPE: 9856 field_shift += W_FT_ETHERTYPE; 9857 break; 9858 case F_MACMATCH: 9859 field_shift += W_FT_MACMATCH; 9860 break; 9861 case F_MPSHITTYPE: 9862 field_shift += W_FT_MPSHITTYPE; 9863 break; 9864 case F_FRAGMENTATION: 9865 field_shift += W_FT_FRAGMENTATION; 9866 break; 9867 } 9868 } 9869 return field_shift; 9870 } 9871 9872 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9873 { 9874 u8 addr[6]; 9875 int ret, i, j; 9876 struct port_info *p = adap2pinfo(adap, port_id); 9877 u32 param, val; 9878 struct vi_info *vi = &p->vi[0]; 9879 9880 for (i = 0, j = -1; i <= p->port_id; i++) { 9881 do { 9882 j++; 9883 } while ((adap->params.portvec & (1 << j)) == 0); 9884 } 9885 9886 p->tx_chan = j; 9887 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9888 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9889 p->rx_c_chan = t4_get_rx_c_chan(adap, j); 9890 p->lport = j; 9891 9892 if (!(adap->flags & IS_VF) || 9893 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9894 t4_update_port_info(p); 9895 } 9896 9897 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9898 &vi->vfvld, &vi->vin); 9899 if (ret < 0) 9900 return ret; 9901 9902 vi->viid = ret; 9903 t4_os_set_hw_addr(p, addr); 9904 9905 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9906 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9907 V_FW_PARAMS_PARAM_YZ(vi->viid); 9908 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9909 if (ret) 9910 vi->rss_base = 0xffff; 9911 else { 9912 /* MPASS((val >> 16) == rss_size); */ 9913 vi->rss_base = val & 0xffff; 9914 } 9915 9916 return 0; 9917 } 9918 9919 /** 9920 * t4_read_cimq_cfg - read CIM queue configuration 9921 * @adap: the adapter 9922 * @base: holds the queue base addresses in bytes 9923 * @size: holds the queue sizes in bytes 9924 * @thres: holds the queue full thresholds in bytes 9925 * 9926 * Returns the current configuration of the CIM queues, starting with 9927 * the IBQs, then the OBQs. 9928 */ 9929 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9930 { 9931 unsigned int i, v; 9932 int cim_num_obq = adap->chip_params->cim_num_obq; 9933 9934 for (i = 0; i < CIM_NUM_IBQ; i++) { 9935 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9936 V_QUENUMSELECT(i)); 9937 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9938 /* value is in 256-byte units */ 9939 *base++ = G_CIMQBASE(v) * 256; 9940 *size++ = G_CIMQSIZE(v) * 256; 9941 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9942 } 9943 for (i = 0; i < cim_num_obq; i++) { 9944 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9945 V_QUENUMSELECT(i)); 9946 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9947 /* value is in 256-byte units */ 9948 *base++ = G_CIMQBASE(v) * 256; 9949 *size++ = G_CIMQSIZE(v) * 256; 9950 } 9951 } 9952 9953 /** 9954 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9955 * @adap: the adapter 9956 * @qid: the queue index 9957 * @data: where to store the queue contents 9958 * @n: capacity of @data in 32-bit words 9959 * 9960 * Reads the contents of the selected CIM queue starting at address 0 up 9961 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9962 * error and the number of 32-bit words actually read on success. 9963 */ 9964 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9965 { 9966 int i, err, attempts; 9967 unsigned int addr; 9968 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9969 9970 if (qid > 5 || (n & 3)) 9971 return -EINVAL; 9972 9973 addr = qid * nwords; 9974 if (n > nwords) 9975 n = nwords; 9976 9977 /* It might take 3-10ms before the IBQ debug read access is allowed. 9978 * Wait for 1 Sec with a delay of 1 usec. 9979 */ 9980 attempts = 1000000; 9981 9982 for (i = 0; i < n; i++, addr++) { 9983 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 9984 F_IBQDBGEN); 9985 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 9986 attempts, 1); 9987 if (err) 9988 return err; 9989 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 9990 } 9991 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 9992 return i; 9993 } 9994 9995 /** 9996 * t4_read_cim_obq - read the contents of a CIM outbound queue 9997 * @adap: the adapter 9998 * @qid: the queue index 9999 * @data: where to store the queue contents 10000 * @n: capacity of @data in 32-bit words 10001 * 10002 * Reads the contents of the selected CIM queue starting at address 0 up 10003 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 10004 * error and the number of 32-bit words actually read on success. 10005 */ 10006 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 10007 { 10008 int i, err; 10009 unsigned int addr, v, nwords; 10010 int cim_num_obq = adap->chip_params->cim_num_obq; 10011 10012 if ((qid > (cim_num_obq - 1)) || (n & 3)) 10013 return -EINVAL; 10014 10015 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 10016 V_QUENUMSELECT(qid)); 10017 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 10018 10019 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 10020 nwords = G_CIMQSIZE(v) * 64; /* same */ 10021 if (n > nwords) 10022 n = nwords; 10023 10024 for (i = 0; i < n; i++, addr++) { 10025 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 10026 F_OBQDBGEN); 10027 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 10028 2, 1); 10029 if (err) 10030 return err; 10031 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 10032 } 10033 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 10034 return i; 10035 } 10036 10037 enum { 10038 CIM_QCTL_BASE = 0, 10039 CIM_CTL_BASE = 0x2000, 10040 CIM_PBT_ADDR_BASE = 0x2800, 10041 CIM_PBT_LRF_BASE = 0x3000, 10042 CIM_PBT_DATA_BASE = 0x3800 10043 }; 10044 10045 /** 10046 * t4_cim_read - read a block from CIM internal address space 10047 * @adap: the adapter 10048 * @addr: the start address within the CIM address space 10049 * @n: number of words to read 10050 * @valp: where to store the result 10051 * 10052 * Reads a block of 4-byte words from the CIM intenal address space. 10053 */ 10054 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 10055 unsigned int *valp) 10056 { 10057 int ret = 0; 10058 10059 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10060 return -EBUSY; 10061 10062 for ( ; !ret && n--; addr += 4) { 10063 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 10064 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10065 0, 5, 2); 10066 if (!ret) 10067 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 10068 } 10069 return ret; 10070 } 10071 10072 /** 10073 * t4_cim_write - write a block into CIM internal address space 10074 * @adap: the adapter 10075 * @addr: the start address within the CIM address space 10076 * @n: number of words to write 10077 * @valp: set of values to write 10078 * 10079 * Writes a block of 4-byte words into the CIM intenal address space. 10080 */ 10081 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 10082 const unsigned int *valp) 10083 { 10084 int ret = 0; 10085 10086 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10087 return -EBUSY; 10088 10089 for ( ; !ret && n--; addr += 4) { 10090 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 10091 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 10092 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10093 0, 5, 2); 10094 } 10095 return ret; 10096 } 10097 10098 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 10099 unsigned int val) 10100 { 10101 return t4_cim_write(adap, addr, 1, &val); 10102 } 10103 10104 /** 10105 * t4_cim_ctl_read - read a block from CIM control region 10106 * @adap: the adapter 10107 * @addr: the start address within the CIM control region 10108 * @n: number of words to read 10109 * @valp: where to store the result 10110 * 10111 * Reads a block of 4-byte words from the CIM control region. 10112 */ 10113 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 10114 unsigned int *valp) 10115 { 10116 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 10117 } 10118 10119 /** 10120 * t4_cim_read_la - read CIM LA capture buffer 10121 * @adap: the adapter 10122 * @la_buf: where to store the LA data 10123 * @wrptr: the HW write pointer within the capture buffer 10124 * 10125 * Reads the contents of the CIM LA buffer with the most recent entry at 10126 * the end of the returned data and with the entry at @wrptr first. 10127 * We try to leave the LA in the running state we find it in. 10128 */ 10129 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 10130 { 10131 int i, ret; 10132 unsigned int cfg, val, idx; 10133 10134 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 10135 if (ret) 10136 return ret; 10137 10138 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 10139 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 10140 if (ret) 10141 return ret; 10142 } 10143 10144 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10145 if (ret) 10146 goto restart; 10147 10148 idx = G_UPDBGLAWRPTR(val); 10149 if (wrptr) 10150 *wrptr = idx; 10151 10152 for (i = 0; i < adap->params.cim_la_size; i++) { 10153 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10154 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 10155 if (ret) 10156 break; 10157 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10158 if (ret) 10159 break; 10160 if (val & F_UPDBGLARDEN) { 10161 ret = -ETIMEDOUT; 10162 break; 10163 } 10164 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 10165 if (ret) 10166 break; 10167 10168 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 10169 * identify the 32-bit portion of the full 312-bit data 10170 */ 10171 if (is_t6(adap) && (idx & 0xf) >= 9) 10172 idx = (idx & 0xff0) + 0x10; 10173 else 10174 idx++; 10175 /* address can't exceed 0xfff */ 10176 idx &= M_UPDBGLARDPTR; 10177 } 10178 restart: 10179 if (cfg & F_UPDBGLAEN) { 10180 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10181 cfg & ~F_UPDBGLARDEN); 10182 if (!ret) 10183 ret = r; 10184 } 10185 return ret; 10186 } 10187 10188 /** 10189 * t4_tp_read_la - read TP LA capture buffer 10190 * @adap: the adapter 10191 * @la_buf: where to store the LA data 10192 * @wrptr: the HW write pointer within the capture buffer 10193 * 10194 * Reads the contents of the TP LA buffer with the most recent entry at 10195 * the end of the returned data and with the entry at @wrptr first. 10196 * We leave the LA in the running state we find it in. 10197 */ 10198 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 10199 { 10200 bool last_incomplete; 10201 unsigned int i, cfg, val, idx; 10202 10203 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 10204 if (cfg & F_DBGLAENABLE) /* freeze LA */ 10205 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10206 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 10207 10208 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 10209 idx = G_DBGLAWPTR(val); 10210 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 10211 if (last_incomplete) 10212 idx = (idx + 1) & M_DBGLARPTR; 10213 if (wrptr) 10214 *wrptr = idx; 10215 10216 val &= 0xffff; 10217 val &= ~V_DBGLARPTR(M_DBGLARPTR); 10218 val |= adap->params.tp.la_mask; 10219 10220 for (i = 0; i < TPLA_SIZE; i++) { 10221 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 10222 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 10223 idx = (idx + 1) & M_DBGLARPTR; 10224 } 10225 10226 /* Wipe out last entry if it isn't valid */ 10227 if (last_incomplete) 10228 la_buf[TPLA_SIZE - 1] = ~0ULL; 10229 10230 if (cfg & F_DBGLAENABLE) /* restore running state */ 10231 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10232 cfg | adap->params.tp.la_mask); 10233 } 10234 10235 /* 10236 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 10237 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 10238 * state for more than the Warning Threshold then we'll issue a warning about 10239 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 10240 * appears to be hung every Warning Repeat second till the situation clears. 10241 * If the situation clears, we'll note that as well. 10242 */ 10243 #define SGE_IDMA_WARN_THRESH 1 10244 #define SGE_IDMA_WARN_REPEAT 300 10245 10246 /** 10247 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 10248 * @adapter: the adapter 10249 * @idma: the adapter IDMA Monitor state 10250 * 10251 * Initialize the state of an SGE Ingress DMA Monitor. 10252 */ 10253 void t4_idma_monitor_init(struct adapter *adapter, 10254 struct sge_idma_monitor_state *idma) 10255 { 10256 /* Initialize the state variables for detecting an SGE Ingress DMA 10257 * hang. The SGE has internal counters which count up on each clock 10258 * tick whenever the SGE finds its Ingress DMA State Engines in the 10259 * same state they were on the previous clock tick. The clock used is 10260 * the Core Clock so we have a limit on the maximum "time" they can 10261 * record; typically a very small number of seconds. For instance, 10262 * with a 600MHz Core Clock, we can only count up to a bit more than 10263 * 7s. So we'll synthesize a larger counter in order to not run the 10264 * risk of having the "timers" overflow and give us the flexibility to 10265 * maintain a Hung SGE State Machine of our own which operates across 10266 * a longer time frame. 10267 */ 10268 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 10269 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 10270 } 10271 10272 /** 10273 * t4_idma_monitor - monitor SGE Ingress DMA state 10274 * @adapter: the adapter 10275 * @idma: the adapter IDMA Monitor state 10276 * @hz: number of ticks/second 10277 * @ticks: number of ticks since the last IDMA Monitor call 10278 */ 10279 void t4_idma_monitor(struct adapter *adapter, 10280 struct sge_idma_monitor_state *idma, 10281 int hz, int ticks) 10282 { 10283 int i, idma_same_state_cnt[2]; 10284 10285 /* Read the SGE Debug Ingress DMA Same State Count registers. These 10286 * are counters inside the SGE which count up on each clock when the 10287 * SGE finds its Ingress DMA State Engines in the same states they 10288 * were in the previous clock. The counters will peg out at 10289 * 0xffffffff without wrapping around so once they pass the 1s 10290 * threshold they'll stay above that till the IDMA state changes. 10291 */ 10292 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 10293 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 10294 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10295 10296 for (i = 0; i < 2; i++) { 10297 u32 debug0, debug11; 10298 10299 /* If the Ingress DMA Same State Counter ("timer") is less 10300 * than 1s, then we can reset our synthesized Stall Timer and 10301 * continue. If we have previously emitted warnings about a 10302 * potential stalled Ingress Queue, issue a note indicating 10303 * that the Ingress Queue has resumed forward progress. 10304 */ 10305 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 10306 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 10307 CH_WARN(adapter, "SGE idma%d, queue %u, " 10308 "resumed after %d seconds\n", 10309 i, idma->idma_qid[i], 10310 idma->idma_stalled[i]/hz); 10311 idma->idma_stalled[i] = 0; 10312 continue; 10313 } 10314 10315 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 10316 * domain. The first time we get here it'll be because we 10317 * passed the 1s Threshold; each additional time it'll be 10318 * because the RX Timer Callback is being fired on its regular 10319 * schedule. 10320 * 10321 * If the stall is below our Potential Hung Ingress Queue 10322 * Warning Threshold, continue. 10323 */ 10324 if (idma->idma_stalled[i] == 0) { 10325 idma->idma_stalled[i] = hz; 10326 idma->idma_warn[i] = 0; 10327 } else { 10328 idma->idma_stalled[i] += ticks; 10329 idma->idma_warn[i] -= ticks; 10330 } 10331 10332 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 10333 continue; 10334 10335 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 10336 */ 10337 if (idma->idma_warn[i] > 0) 10338 continue; 10339 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 10340 10341 /* Read and save the SGE IDMA State and Queue ID information. 10342 * We do this every time in case it changes across time ... 10343 * can't be too careful ... 10344 */ 10345 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 10346 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10347 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 10348 10349 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 10350 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10351 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 10352 10353 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 10354 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 10355 i, idma->idma_qid[i], idma->idma_state[i], 10356 idma->idma_stalled[i]/hz, 10357 debug0, debug11); 10358 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 10359 } 10360 } 10361 10362 /** 10363 * t4_set_vf_mac - Set MAC address for the specified VF 10364 * @adapter: The adapter 10365 * @pf: the PF used to instantiate the VFs 10366 * @vf: one of the VFs instantiated by the specified PF 10367 * @naddr: the number of MAC addresses 10368 * @addr: the MAC address(es) to be set to the specified VF 10369 */ 10370 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, 10371 unsigned int naddr, u8 *addr) 10372 { 10373 struct fw_acl_mac_cmd cmd; 10374 10375 memset(&cmd, 0, sizeof(cmd)); 10376 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | 10377 F_FW_CMD_REQUEST | 10378 F_FW_CMD_WRITE | 10379 V_FW_ACL_MAC_CMD_PFN(pf) | 10380 V_FW_ACL_MAC_CMD_VFN(vf)); 10381 10382 /* Note: Do not enable the ACL */ 10383 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); 10384 cmd.nmac = naddr; 10385 10386 switch (pf) { 10387 case 3: 10388 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); 10389 break; 10390 case 2: 10391 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); 10392 break; 10393 case 1: 10394 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); 10395 break; 10396 case 0: 10397 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); 10398 break; 10399 } 10400 10401 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); 10402 } 10403 10404 /** 10405 * t4_read_pace_tbl - read the pace table 10406 * @adap: the adapter 10407 * @pace_vals: holds the returned values 10408 * 10409 * Returns the values of TP's pace table in microseconds. 10410 */ 10411 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 10412 { 10413 unsigned int i, v; 10414 10415 for (i = 0; i < NTX_SCHED; i++) { 10416 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 10417 v = t4_read_reg(adap, A_TP_PACE_TABLE); 10418 pace_vals[i] = dack_ticks_to_usec(adap, v); 10419 } 10420 } 10421 10422 /** 10423 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 10424 * @adap: the adapter 10425 * @sched: the scheduler index 10426 * @kbps: the byte rate in Kbps 10427 * @ipg: the interpacket delay in tenths of nanoseconds 10428 * 10429 * Return the current configuration of a HW Tx scheduler. 10430 */ 10431 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 10432 unsigned int *ipg, bool sleep_ok) 10433 { 10434 unsigned int v, addr, bpt, cpt; 10435 10436 if (kbps) { 10437 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 10438 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10439 if (sched & 1) 10440 v >>= 16; 10441 bpt = (v >> 8) & 0xff; 10442 cpt = v & 0xff; 10443 if (!cpt) 10444 *kbps = 0; /* scheduler disabled */ 10445 else { 10446 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 10447 *kbps = (v * bpt) / 125; 10448 } 10449 } 10450 if (ipg) { 10451 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 10452 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10453 if (sched & 1) 10454 v >>= 16; 10455 v &= 0xffff; 10456 *ipg = (10000 * v) / core_ticks_per_usec(adap); 10457 } 10458 } 10459 10460 /** 10461 * t4_load_cfg - download config file 10462 * @adap: the adapter 10463 * @cfg_data: the cfg text file to write 10464 * @size: text file size 10465 * 10466 * Write the supplied config text file to the card's serial flash. 10467 */ 10468 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 10469 { 10470 int ret, i, n, cfg_addr; 10471 unsigned int addr; 10472 unsigned int flash_cfg_start_sec; 10473 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10474 10475 cfg_addr = t4_flash_cfg_addr(adap); 10476 if (cfg_addr < 0) 10477 return cfg_addr; 10478 10479 addr = cfg_addr; 10480 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10481 10482 if (size > FLASH_CFG_MAX_SIZE) { 10483 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 10484 FLASH_CFG_MAX_SIZE); 10485 return -EFBIG; 10486 } 10487 10488 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 10489 sf_sec_size); 10490 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10491 flash_cfg_start_sec + i - 1); 10492 /* 10493 * If size == 0 then we're simply erasing the FLASH sectors associated 10494 * with the on-adapter Firmware Configuration File. 10495 */ 10496 if (ret || size == 0) 10497 goto out; 10498 10499 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10500 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10501 if ( (size - i) < SF_PAGE_SIZE) 10502 n = size - i; 10503 else 10504 n = SF_PAGE_SIZE; 10505 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 10506 if (ret) 10507 goto out; 10508 10509 addr += SF_PAGE_SIZE; 10510 cfg_data += SF_PAGE_SIZE; 10511 } 10512 10513 out: 10514 if (ret) 10515 CH_ERR(adap, "config file %s failed %d\n", 10516 (size == 0 ? "clear" : "download"), ret); 10517 return ret; 10518 } 10519 10520 /** 10521 * t5_fw_init_extern_mem - initialize the external memory 10522 * @adap: the adapter 10523 * 10524 * Initializes the external memory on T5. 10525 */ 10526 int t5_fw_init_extern_mem(struct adapter *adap) 10527 { 10528 u32 params[1], val[1]; 10529 int ret; 10530 10531 if (!is_t5(adap)) 10532 return 0; 10533 10534 val[0] = 0xff; /* Initialize all MCs */ 10535 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10536 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10537 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10538 FW_CMD_MAX_TIMEOUT); 10539 10540 return ret; 10541 } 10542 10543 /* BIOS boot headers */ 10544 typedef struct pci_expansion_rom_header { 10545 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10546 u8 reserved[22]; /* Reserved per processor Architecture data */ 10547 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10548 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10549 10550 /* Legacy PCI Expansion ROM Header */ 10551 typedef struct legacy_pci_expansion_rom_header { 10552 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10553 u8 size512; /* Current Image Size in units of 512 bytes */ 10554 u8 initentry_point[4]; 10555 u8 cksum; /* Checksum computed on the entire Image */ 10556 u8 reserved[16]; /* Reserved */ 10557 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10558 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10559 10560 /* EFI PCI Expansion ROM Header */ 10561 typedef struct efi_pci_expansion_rom_header { 10562 u8 signature[2]; // ROM signature. The value 0xaa55 10563 u8 initialization_size[2]; /* Units 512. Includes this header */ 10564 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10565 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10566 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10567 u8 compression_type[2]; /* Compression type. */ 10568 /* 10569 * Compression type definition 10570 * 0x0: uncompressed 10571 * 0x1: Compressed 10572 * 0x2-0xFFFF: Reserved 10573 */ 10574 u8 reserved[8]; /* Reserved */ 10575 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10576 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10577 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10578 10579 /* PCI Data Structure Format */ 10580 typedef struct pcir_data_structure { /* PCI Data Structure */ 10581 u8 signature[4]; /* Signature. The string "PCIR" */ 10582 u8 vendor_id[2]; /* Vendor Identification */ 10583 u8 device_id[2]; /* Device Identification */ 10584 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10585 u8 length[2]; /* PCIR Data Structure Length */ 10586 u8 revision; /* PCIR Data Structure Revision */ 10587 u8 class_code[3]; /* Class Code */ 10588 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10589 u8 code_revision[2]; /* Revision Level of Code/Data */ 10590 u8 code_type; /* Code Type. */ 10591 /* 10592 * PCI Expansion ROM Code Types 10593 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10594 * 0x01: Open Firmware standard for PCI. FCODE 10595 * 0x02: Hewlett-Packard PA RISC. HP reserved 10596 * 0x03: EFI Image. EFI 10597 * 0x04-0xFF: Reserved. 10598 */ 10599 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10600 u8 reserved[2]; /* Reserved */ 10601 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10602 10603 /* BOOT constants */ 10604 enum { 10605 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10606 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10607 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10608 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10609 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10610 VENDOR_ID = 0x1425, /* Vendor ID */ 10611 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10612 }; 10613 10614 /* 10615 * modify_device_id - Modifies the device ID of the Boot BIOS image 10616 * @adatper: the device ID to write. 10617 * @boot_data: the boot image to modify. 10618 * 10619 * Write the supplied device ID to the boot BIOS image. 10620 */ 10621 static void modify_device_id(int device_id, u8 *boot_data) 10622 { 10623 legacy_pci_exp_rom_header_t *header; 10624 pcir_data_t *pcir_header; 10625 u32 cur_header = 0; 10626 10627 /* 10628 * Loop through all chained images and change the device ID's 10629 */ 10630 while (1) { 10631 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10632 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10633 le16_to_cpu(*(u16*)header->pcir_offset)]; 10634 10635 /* 10636 * Only modify the Device ID if code type is Legacy or HP. 10637 * 0x00: Okay to modify 10638 * 0x01: FCODE. Do not be modify 10639 * 0x03: Okay to modify 10640 * 0x04-0xFF: Do not modify 10641 */ 10642 if (pcir_header->code_type == 0x00) { 10643 u8 csum = 0; 10644 int i; 10645 10646 /* 10647 * Modify Device ID to match current adatper 10648 */ 10649 *(u16*) pcir_header->device_id = device_id; 10650 10651 /* 10652 * Set checksum temporarily to 0. 10653 * We will recalculate it later. 10654 */ 10655 header->cksum = 0x0; 10656 10657 /* 10658 * Calculate and update checksum 10659 */ 10660 for (i = 0; i < (header->size512 * 512); i++) 10661 csum += (u8)boot_data[cur_header + i]; 10662 10663 /* 10664 * Invert summed value to create the checksum 10665 * Writing new checksum value directly to the boot data 10666 */ 10667 boot_data[cur_header + 7] = -csum; 10668 10669 } else if (pcir_header->code_type == 0x03) { 10670 10671 /* 10672 * Modify Device ID to match current adatper 10673 */ 10674 *(u16*) pcir_header->device_id = device_id; 10675 10676 } 10677 10678 10679 /* 10680 * Check indicator element to identify if this is the last 10681 * image in the ROM. 10682 */ 10683 if (pcir_header->indicator & 0x80) 10684 break; 10685 10686 /* 10687 * Move header pointer up to the next image in the ROM. 10688 */ 10689 cur_header += header->size512 * 512; 10690 } 10691 } 10692 10693 /* 10694 * t4_load_boot - download boot flash 10695 * @adapter: the adapter 10696 * @boot_data: the boot image to write 10697 * @boot_addr: offset in flash to write boot_data 10698 * @size: image size 10699 * 10700 * Write the supplied boot image to the card's serial flash. 10701 * The boot image has the following sections: a 28-byte header and the 10702 * boot image. 10703 */ 10704 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10705 unsigned int boot_addr, unsigned int size) 10706 { 10707 pci_exp_rom_header_t *header; 10708 int pcir_offset ; 10709 pcir_data_t *pcir_header; 10710 int ret, addr; 10711 uint16_t device_id; 10712 unsigned int i; 10713 unsigned int boot_sector = (boot_addr * 1024 ); 10714 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10715 10716 /* 10717 * Make sure the boot image does not encroach on the firmware region 10718 */ 10719 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10720 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10721 return -EFBIG; 10722 } 10723 10724 /* 10725 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10726 * and Boot configuration data sections. These 3 boot sections span 10727 * sectors 0 to 7 in flash and live right before the FW image location. 10728 */ 10729 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10730 sf_sec_size); 10731 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10732 (boot_sector >> 16) + i - 1); 10733 10734 /* 10735 * If size == 0 then we're simply erasing the FLASH sectors associated 10736 * with the on-adapter option ROM file 10737 */ 10738 if (ret || (size == 0)) 10739 goto out; 10740 10741 /* Get boot header */ 10742 header = (pci_exp_rom_header_t *)boot_data; 10743 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10744 /* PCIR Data Structure */ 10745 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10746 10747 /* 10748 * Perform some primitive sanity testing to avoid accidentally 10749 * writing garbage over the boot sectors. We ought to check for 10750 * more but it's not worth it for now ... 10751 */ 10752 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10753 CH_ERR(adap, "boot image too small/large\n"); 10754 return -EFBIG; 10755 } 10756 10757 #ifndef CHELSIO_T4_DIAGS 10758 /* 10759 * Check BOOT ROM header signature 10760 */ 10761 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10762 CH_ERR(adap, "Boot image missing signature\n"); 10763 return -EINVAL; 10764 } 10765 10766 /* 10767 * Check PCI header signature 10768 */ 10769 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10770 CH_ERR(adap, "PCI header missing signature\n"); 10771 return -EINVAL; 10772 } 10773 10774 /* 10775 * Check Vendor ID matches Chelsio ID 10776 */ 10777 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10778 CH_ERR(adap, "Vendor ID missing signature\n"); 10779 return -EINVAL; 10780 } 10781 #endif 10782 10783 /* 10784 * Retrieve adapter's device ID 10785 */ 10786 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10787 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10788 device_id = device_id & 0xf0ff; 10789 10790 /* 10791 * Check PCIE Device ID 10792 */ 10793 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10794 /* 10795 * Change the device ID in the Boot BIOS image to match 10796 * the Device ID of the current adapter. 10797 */ 10798 modify_device_id(device_id, boot_data); 10799 } 10800 10801 /* 10802 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10803 * we finish copying the rest of the boot image. This will ensure 10804 * that the BIOS boot header will only be written if the boot image 10805 * was written in full. 10806 */ 10807 addr = boot_sector; 10808 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10809 addr += SF_PAGE_SIZE; 10810 boot_data += SF_PAGE_SIZE; 10811 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10812 if (ret) 10813 goto out; 10814 } 10815 10816 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10817 (const u8 *)header, 0); 10818 10819 out: 10820 if (ret) 10821 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10822 return ret; 10823 } 10824 10825 /* 10826 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10827 * @adapter: the adapter 10828 * 10829 * Return the address within the flash where the OptionROM Configuration 10830 * is stored, or an error if the device FLASH is too small to contain 10831 * a OptionROM Configuration. 10832 */ 10833 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10834 { 10835 /* 10836 * If the device FLASH isn't large enough to hold a Firmware 10837 * Configuration File, return an error. 10838 */ 10839 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10840 return -ENOSPC; 10841 10842 return FLASH_BOOTCFG_START; 10843 } 10844 10845 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10846 { 10847 int ret, i, n, cfg_addr; 10848 unsigned int addr; 10849 unsigned int flash_cfg_start_sec; 10850 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10851 10852 cfg_addr = t4_flash_bootcfg_addr(adap); 10853 if (cfg_addr < 0) 10854 return cfg_addr; 10855 10856 addr = cfg_addr; 10857 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10858 10859 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10860 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10861 FLASH_BOOTCFG_MAX_SIZE); 10862 return -EFBIG; 10863 } 10864 10865 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10866 sf_sec_size); 10867 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10868 flash_cfg_start_sec + i - 1); 10869 10870 /* 10871 * If size == 0 then we're simply erasing the FLASH sectors associated 10872 * with the on-adapter OptionROM Configuration File. 10873 */ 10874 if (ret || size == 0) 10875 goto out; 10876 10877 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10878 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10879 if ( (size - i) < SF_PAGE_SIZE) 10880 n = size - i; 10881 else 10882 n = SF_PAGE_SIZE; 10883 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10884 if (ret) 10885 goto out; 10886 10887 addr += SF_PAGE_SIZE; 10888 cfg_data += SF_PAGE_SIZE; 10889 } 10890 10891 out: 10892 if (ret) 10893 CH_ERR(adap, "boot config data %s failed %d\n", 10894 (size == 0 ? "clear" : "download"), ret); 10895 return ret; 10896 } 10897 10898 /** 10899 * t4_set_filter_cfg - set up filter mode/mask and ingress config. 10900 * @adap: the adapter 10901 * @mode: a bitmap selecting which optional filter components to enable 10902 * @mask: a bitmap selecting which components to enable in filter mask 10903 * @vnic_mode: the ingress config/vnic mode setting 10904 * 10905 * Sets the filter mode and mask by selecting the optional components to 10906 * enable in filter tuples. Returns 0 on success and a negative error if 10907 * the requested mode needs more bits than are available for optional 10908 * components. The filter mask must be a subset of the filter mode. 10909 */ 10910 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) 10911 { 10912 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 10913 int i, nbits, rc; 10914 uint32_t param, val; 10915 uint16_t fmode, fmask; 10916 const int maxbits = adap->chip_params->filter_opt_len; 10917 10918 if (mode != -1 || mask != -1) { 10919 if (mode != -1) { 10920 fmode = mode; 10921 nbits = 0; 10922 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10923 if (fmode & (1 << i)) 10924 nbits += width[i]; 10925 } 10926 if (nbits > maxbits) { 10927 CH_ERR(adap, "optional fields in the filter " 10928 "mode (0x%x) add up to %d bits " 10929 "(must be <= %db). Remove some fields and " 10930 "try again.\n", fmode, nbits, maxbits); 10931 return -E2BIG; 10932 } 10933 10934 /* 10935 * Hardware wants the bits to be maxed out. Keep 10936 * setting them until there's no room for more. 10937 */ 10938 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10939 if (fmode & (1 << i)) 10940 continue; 10941 if (nbits + width[i] <= maxbits) { 10942 fmode |= 1 << i; 10943 nbits += width[i]; 10944 if (nbits == maxbits) 10945 break; 10946 } 10947 } 10948 10949 fmask = fmode & adap->params.tp.filter_mask; 10950 if (fmask != adap->params.tp.filter_mask) { 10951 CH_WARN(adap, 10952 "filter mask will be changed from 0x%x to " 10953 "0x%x to comply with the filter mode (0x%x).\n", 10954 adap->params.tp.filter_mask, fmask, fmode); 10955 } 10956 } else { 10957 fmode = adap->params.tp.filter_mode; 10958 fmask = mask; 10959 if ((fmode | fmask) != fmode) { 10960 CH_ERR(adap, 10961 "filter mask (0x%x) must be a subset of " 10962 "the filter mode (0x%x).\n", fmask, fmode); 10963 return -EINVAL; 10964 } 10965 } 10966 10967 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10968 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10969 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 10970 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) | 10971 V_FW_PARAMS_PARAM_FILTER_MASK(fmask); 10972 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10973 &val); 10974 if (rc < 0) 10975 return rc; 10976 } 10977 10978 if (vnic_mode != -1) { 10979 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10980 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10981 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 10982 val = vnic_mode; 10983 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10984 &val); 10985 if (rc < 0) 10986 return rc; 10987 } 10988 10989 /* Refresh. */ 10990 read_filter_mode_and_ingress_config(adap); 10991 10992 return 0; 10993 } 10994 10995 /** 10996 * t4_clr_port_stats - clear port statistics 10997 * @adap: the adapter 10998 * @idx: the port index 10999 * 11000 * Clear HW statistics for the given port. 11001 */ 11002 void t4_clr_port_stats(struct adapter *adap, int idx) 11003 { 11004 unsigned int i; 11005 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 11006 u32 port_base_addr; 11007 11008 if (is_t4(adap)) 11009 port_base_addr = PORT_BASE(idx); 11010 else 11011 port_base_addr = T5_PORT_BASE(idx); 11012 11013 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 11014 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 11015 t4_write_reg(adap, port_base_addr + i, 0); 11016 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 11017 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 11018 t4_write_reg(adap, port_base_addr + i, 0); 11019 for (i = 0; i < 4; i++) 11020 if (bgmap & (1 << i)) { 11021 t4_write_reg(adap, 11022 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 11023 t4_write_reg(adap, 11024 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 11025 } 11026 } 11027 11028 /** 11029 * t4_i2c_io - read/write I2C data from adapter 11030 * @adap: the adapter 11031 * @port: Port number if per-port device; <0 if not 11032 * @devid: per-port device ID or absolute device ID 11033 * @offset: byte offset into device I2C space 11034 * @len: byte length of I2C space data 11035 * @buf: buffer in which to return I2C data for read 11036 * buffer which holds the I2C data for write 11037 * @write: if true, do a write; else do a read 11038 * Reads/Writes the I2C data from/to the indicated device and location. 11039 */ 11040 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 11041 int port, unsigned int devid, 11042 unsigned int offset, unsigned int len, 11043 u8 *buf, bool write) 11044 { 11045 struct fw_ldst_cmd ldst_cmd, ldst_rpl; 11046 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data); 11047 int ret = 0; 11048 11049 if (len > I2C_PAGE_SIZE) 11050 return -EINVAL; 11051 11052 /* Dont allow reads that spans multiple pages */ 11053 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) 11054 return -EINVAL; 11055 11056 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 11057 ldst_cmd.op_to_addrspace = 11058 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11059 F_FW_CMD_REQUEST | 11060 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) | 11061 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 11062 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 11063 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); 11064 ldst_cmd.u.i2c.did = devid; 11065 11066 while (len > 0) { 11067 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max; 11068 11069 ldst_cmd.u.i2c.boffset = offset; 11070 ldst_cmd.u.i2c.blen = i2c_len; 11071 11072 if (write) 11073 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len); 11074 11075 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd), 11076 write ? NULL : &ldst_rpl); 11077 if (ret) 11078 break; 11079 11080 if (!write) 11081 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len); 11082 offset += i2c_len; 11083 buf += i2c_len; 11084 len -= i2c_len; 11085 } 11086 11087 return ret; 11088 } 11089 11090 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 11091 int port, unsigned int devid, 11092 unsigned int offset, unsigned int len, 11093 u8 *buf) 11094 { 11095 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false); 11096 } 11097 11098 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 11099 int port, unsigned int devid, 11100 unsigned int offset, unsigned int len, 11101 u8 *buf) 11102 { 11103 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true); 11104 } 11105 11106 /** 11107 * t4_sge_ctxt_rd - read an SGE context through FW 11108 * @adap: the adapter 11109 * @mbox: mailbox to use for the FW command 11110 * @cid: the context id 11111 * @ctype: the context type 11112 * @data: where to store the context data 11113 * 11114 * Issues a FW command through the given mailbox to read an SGE context. 11115 */ 11116 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 11117 enum ctxt_type ctype, u32 *data) 11118 { 11119 int ret; 11120 struct fw_ldst_cmd c; 11121 11122 if (ctype == CTXT_EGRESS) 11123 ret = FW_LDST_ADDRSPC_SGE_EGRC; 11124 else if (ctype == CTXT_INGRESS) 11125 ret = FW_LDST_ADDRSPC_SGE_INGC; 11126 else if (ctype == CTXT_FLM) 11127 ret = FW_LDST_ADDRSPC_SGE_FLMC; 11128 else 11129 ret = FW_LDST_ADDRSPC_SGE_CONMC; 11130 11131 memset(&c, 0, sizeof(c)); 11132 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11133 F_FW_CMD_REQUEST | F_FW_CMD_READ | 11134 V_FW_LDST_CMD_ADDRSPACE(ret)); 11135 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 11136 c.u.idctxt.physid = cpu_to_be32(cid); 11137 11138 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11139 if (ret == 0) { 11140 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 11141 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 11142 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 11143 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 11144 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 11145 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 11146 } 11147 return ret; 11148 } 11149 11150 /** 11151 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 11152 * @adap: the adapter 11153 * @cid: the context id 11154 * @ctype: the context type 11155 * @data: where to store the context data 11156 * 11157 * Reads an SGE context directly, bypassing FW. This is only for 11158 * debugging when FW is unavailable. 11159 */ 11160 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 11161 u32 *data) 11162 { 11163 int i, ret; 11164 11165 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 11166 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 11167 if (!ret) 11168 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 11169 *data++ = t4_read_reg(adap, i); 11170 return ret; 11171 } 11172 11173 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 11174 int sleep_ok) 11175 { 11176 struct fw_sched_cmd cmd; 11177 11178 memset(&cmd, 0, sizeof(cmd)); 11179 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11180 F_FW_CMD_REQUEST | 11181 F_FW_CMD_WRITE); 11182 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11183 11184 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 11185 cmd.u.config.type = type; 11186 cmd.u.config.minmaxen = minmaxen; 11187 11188 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11189 NULL, sleep_ok); 11190 } 11191 11192 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 11193 int rateunit, int ratemode, int channel, int cl, 11194 int minrate, int maxrate, int weight, int pktsize, 11195 int burstsize, int sleep_ok) 11196 { 11197 struct fw_sched_cmd cmd; 11198 11199 memset(&cmd, 0, sizeof(cmd)); 11200 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11201 F_FW_CMD_REQUEST | 11202 F_FW_CMD_WRITE); 11203 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11204 11205 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11206 cmd.u.params.type = type; 11207 cmd.u.params.level = level; 11208 cmd.u.params.mode = mode; 11209 cmd.u.params.ch = channel; 11210 cmd.u.params.cl = cl; 11211 cmd.u.params.unit = rateunit; 11212 cmd.u.params.rate = ratemode; 11213 cmd.u.params.min = cpu_to_be32(minrate); 11214 cmd.u.params.max = cpu_to_be32(maxrate); 11215 cmd.u.params.weight = cpu_to_be16(weight); 11216 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11217 cmd.u.params.burstsize = cpu_to_be16(burstsize); 11218 11219 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11220 NULL, sleep_ok); 11221 } 11222 11223 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 11224 unsigned int maxrate, int sleep_ok) 11225 { 11226 struct fw_sched_cmd cmd; 11227 11228 memset(&cmd, 0, sizeof(cmd)); 11229 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11230 F_FW_CMD_REQUEST | 11231 F_FW_CMD_WRITE); 11232 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11233 11234 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11235 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11236 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 11237 cmd.u.params.ch = channel; 11238 cmd.u.params.rate = ratemode; /* REL or ABS */ 11239 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 11240 11241 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11242 NULL, sleep_ok); 11243 } 11244 11245 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 11246 int weight, int sleep_ok) 11247 { 11248 struct fw_sched_cmd cmd; 11249 11250 if (weight < 0 || weight > 100) 11251 return -EINVAL; 11252 11253 memset(&cmd, 0, sizeof(cmd)); 11254 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11255 F_FW_CMD_REQUEST | 11256 F_FW_CMD_WRITE); 11257 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11258 11259 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11260 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11261 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 11262 cmd.u.params.ch = channel; 11263 cmd.u.params.cl = cl; 11264 cmd.u.params.weight = cpu_to_be16(weight); 11265 11266 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11267 NULL, sleep_ok); 11268 } 11269 11270 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 11271 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 11272 { 11273 struct fw_sched_cmd cmd; 11274 11275 memset(&cmd, 0, sizeof(cmd)); 11276 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11277 F_FW_CMD_REQUEST | 11278 F_FW_CMD_WRITE); 11279 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11280 11281 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11282 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11283 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 11284 cmd.u.params.mode = mode; 11285 cmd.u.params.ch = channel; 11286 cmd.u.params.cl = cl; 11287 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 11288 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 11289 cmd.u.params.max = cpu_to_be32(maxrate); 11290 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11291 11292 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11293 NULL, sleep_ok); 11294 } 11295 11296 /* 11297 * t4_config_watchdog - configure (enable/disable) a watchdog timer 11298 * @adapter: the adapter 11299 * @mbox: mailbox to use for the FW command 11300 * @pf: the PF owning the queue 11301 * @vf: the VF owning the queue 11302 * @timeout: watchdog timeout in ms 11303 * @action: watchdog timer / action 11304 * 11305 * There are separate watchdog timers for each possible watchdog 11306 * action. Configure one of the watchdog timers by setting a non-zero 11307 * timeout. Disable a watchdog timer by using a timeout of zero. 11308 */ 11309 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 11310 unsigned int pf, unsigned int vf, 11311 unsigned int timeout, unsigned int action) 11312 { 11313 struct fw_watchdog_cmd wdog; 11314 unsigned int ticks; 11315 11316 /* 11317 * The watchdog command expects a timeout in units of 10ms so we need 11318 * to convert it here (via rounding) and force a minimum of one 10ms 11319 * "tick" if the timeout is non-zero but the conversion results in 0 11320 * ticks. 11321 */ 11322 ticks = (timeout + 5)/10; 11323 if (timeout && !ticks) 11324 ticks = 1; 11325 11326 memset(&wdog, 0, sizeof wdog); 11327 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 11328 F_FW_CMD_REQUEST | 11329 F_FW_CMD_WRITE | 11330 V_FW_PARAMS_CMD_PFN(pf) | 11331 V_FW_PARAMS_CMD_VFN(vf)); 11332 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 11333 wdog.timeout = cpu_to_be32(ticks); 11334 wdog.action = cpu_to_be32(action); 11335 11336 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 11337 } 11338 11339 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 11340 { 11341 struct fw_devlog_cmd devlog_cmd; 11342 int ret; 11343 11344 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11345 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11346 F_FW_CMD_REQUEST | F_FW_CMD_READ); 11347 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11348 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11349 sizeof(devlog_cmd), &devlog_cmd); 11350 if (ret) 11351 return ret; 11352 11353 *level = devlog_cmd.level; 11354 return 0; 11355 } 11356 11357 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 11358 { 11359 struct fw_devlog_cmd devlog_cmd; 11360 11361 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11362 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11363 F_FW_CMD_REQUEST | 11364 F_FW_CMD_WRITE); 11365 devlog_cmd.level = level; 11366 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11367 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11368 sizeof(devlog_cmd), &devlog_cmd); 11369 } 11370 11371 int t4_configure_add_smac(struct adapter *adap) 11372 { 11373 unsigned int param, val; 11374 int ret = 0; 11375 11376 adap->params.smac_add_support = 0; 11377 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11378 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC)); 11379 /* Query FW to check if FW supports adding source mac address 11380 * to TCAM feature or not. 11381 * If FW returns 1, driver can use this feature and driver need to send 11382 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to 11383 * enable adding smac to TCAM. 11384 */ 11385 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11386 if (ret) 11387 return ret; 11388 11389 if (val == 1) { 11390 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 11391 ¶m, &val); 11392 if (!ret) 11393 /* Firmware allows adding explicit TCAM entries. 11394 * Save this internally. 11395 */ 11396 adap->params.smac_add_support = 1; 11397 } 11398 11399 return ret; 11400 } 11401 11402 int t4_configure_ringbb(struct adapter *adap) 11403 { 11404 unsigned int param, val; 11405 int ret = 0; 11406 11407 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11408 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE)); 11409 /* Query FW to check if FW supports ring switch feature or not. 11410 * If FW returns 1, driver can use this feature and driver need to send 11411 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to 11412 * enable the ring backbone configuration. 11413 */ 11414 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11415 if (ret < 0) { 11416 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n", 11417 ret); 11418 goto out; 11419 } 11420 11421 if (val != 1) { 11422 CH_ERR(adap, "FW doesnot support ringbackbone features\n"); 11423 goto out; 11424 } 11425 11426 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11427 if (ret < 0) { 11428 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n", 11429 ret); 11430 goto out; 11431 } 11432 11433 out: 11434 return ret; 11435 } 11436 11437 /* 11438 * t4_set_vlan_acl - Set a VLAN id for the specified VF 11439 * @adapter: the adapter 11440 * @mbox: mailbox to use for the FW command 11441 * @vf: one of the VFs instantiated by the specified PF 11442 * @vlan: The vlanid to be set 11443 * 11444 */ 11445 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 11446 u16 vlan) 11447 { 11448 struct fw_acl_vlan_cmd vlan_cmd; 11449 unsigned int enable; 11450 11451 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); 11452 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); 11453 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) | 11454 F_FW_CMD_REQUEST | 11455 F_FW_CMD_WRITE | 11456 F_FW_CMD_EXEC | 11457 V_FW_ACL_VLAN_CMD_PFN(adap->pf) | 11458 V_FW_ACL_VLAN_CMD_VFN(vf)); 11459 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd)); 11460 /* Drop all packets that donot match vlan id */ 11461 vlan_cmd.dropnovlan_fm = (enable 11462 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN | 11463 F_FW_ACL_VLAN_CMD_FM) 11464 : 0); 11465 if (enable != 0) { 11466 vlan_cmd.nvlan = 1; 11467 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); 11468 } 11469 11470 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); 11471 } 11472 11473 /** 11474 * t4_del_mac - Removes the exact-match filter for a MAC address 11475 * @adap: the adapter 11476 * @mbox: mailbox to use for the FW command 11477 * @viid: the VI id 11478 * @addr: the MAC address value 11479 * @smac: if true, delete from only the smac region of MPS 11480 * 11481 * Modifies an exact-match filter and sets it to the new MAC address if 11482 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11483 * latter case the address is added persistently if @persist is %true. 11484 * 11485 * Returns a negative error number or the index of the filter with the new 11486 * MAC value. Note that this index may differ from @idx. 11487 */ 11488 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11489 const u8 *addr, bool smac) 11490 { 11491 int ret; 11492 struct fw_vi_mac_cmd c; 11493 struct fw_vi_mac_exact *p = c.u.exact; 11494 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11495 11496 memset(&c, 0, sizeof(c)); 11497 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11498 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11499 V_FW_VI_MAC_CMD_VIID(viid)); 11500 c.freemacs_to_len16 = cpu_to_be32( 11501 V_FW_CMD_LEN16(1) | 11502 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11503 11504 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11505 p->valid_to_idx = cpu_to_be16( 11506 F_FW_VI_MAC_CMD_VALID | 11507 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 11508 11509 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11510 if (ret == 0) { 11511 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11512 if (ret < max_mac_addr) 11513 return -ENOMEM; 11514 } 11515 11516 return ret; 11517 } 11518 11519 /** 11520 * t4_add_mac - Adds an exact-match filter for a MAC address 11521 * @adap: the adapter 11522 * @mbox: mailbox to use for the FW command 11523 * @viid: the VI id 11524 * @idx: index of existing filter for old value of MAC address, or -1 11525 * @addr: the new MAC address value 11526 * @persist: whether a new MAC allocation should be persistent 11527 * @add_smt: if true also add the address to the HW SMT 11528 * @smac: if true, update only the smac region of MPS 11529 * 11530 * Modifies an exact-match filter and sets it to the new MAC address if 11531 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11532 * latter case the address is added persistently if @persist is %true. 11533 * 11534 * Returns a negative error number or the index of the filter with the new 11535 * MAC value. Note that this index may differ from @idx. 11536 */ 11537 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11538 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac) 11539 { 11540 int ret, mode; 11541 struct fw_vi_mac_cmd c; 11542 struct fw_vi_mac_exact *p = c.u.exact; 11543 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11544 11545 if (idx < 0) /* new allocation */ 11546 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 11547 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 11548 11549 memset(&c, 0, sizeof(c)); 11550 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11551 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11552 V_FW_VI_MAC_CMD_VIID(viid)); 11553 c.freemacs_to_len16 = cpu_to_be32( 11554 V_FW_CMD_LEN16(1) | 11555 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11556 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 11557 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 11558 V_FW_VI_MAC_CMD_IDX(idx)); 11559 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11560 11561 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11562 if (ret == 0) { 11563 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11564 if (ret >= max_mac_addr) 11565 return -ENOMEM; 11566 if (smt_idx) { 11567 /* Does fw supports returning smt_idx? */ 11568 if (adap->params.viid_smt_extn_support) 11569 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 11570 else { 11571 /* In T4/T5, SMT contains 256 SMAC entries 11572 * organized in 128 rows of 2 entries each. 11573 * In T6, SMT contains 256 SMAC entries in 11574 * 256 rows. 11575 */ 11576 if (chip_id(adap) <= CHELSIO_T5) 11577 *smt_idx = ((viid & M_FW_VIID_VIN) << 1); 11578 else 11579 *smt_idx = (viid & M_FW_VIID_VIN); 11580 } 11581 } 11582 } 11583 11584 return ret; 11585 } 11586