1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) { 215 adap->flags &= ~FW_OK; 216 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", 217 reason[G_PCIE_FW_EVAL(pcie_fw)], pcie_fw); 218 if (pcie_fw != 0xffffffff) 219 t4_os_dump_devlog(adap); 220 } 221 } 222 223 /* 224 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 225 */ 226 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 227 u32 mbox_addr) 228 { 229 for ( ; nflit; nflit--, mbox_addr += 8) 230 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 231 } 232 233 /* 234 * Handle a FW assertion reported in a mailbox. 235 */ 236 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 237 { 238 CH_ALERT(adap, 239 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 240 asrt->u.assert.filename_0_7, 241 be32_to_cpu(asrt->u.assert.line), 242 be32_to_cpu(asrt->u.assert.x), 243 be32_to_cpu(asrt->u.assert.y)); 244 } 245 246 struct port_tx_state { 247 uint64_t rx_pause; 248 uint64_t tx_frames; 249 }; 250 251 static void 252 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 253 { 254 uint32_t rx_pause_reg, tx_frames_reg; 255 256 if (is_t4(sc)) { 257 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 258 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 259 } else { 260 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 261 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 262 } 263 264 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 265 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 266 } 267 268 static void 269 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 270 { 271 int i; 272 273 for_each_port(sc, i) 274 read_tx_state_one(sc, i, &tx_state[i]); 275 } 276 277 static void 278 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 279 { 280 uint32_t port_ctl_reg; 281 uint64_t tx_frames, rx_pause; 282 int i; 283 284 for_each_port(sc, i) { 285 rx_pause = tx_state[i].rx_pause; 286 tx_frames = tx_state[i].tx_frames; 287 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 288 289 if (is_t4(sc)) 290 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 291 else 292 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 293 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 294 rx_pause != tx_state[i].rx_pause && 295 tx_frames == tx_state[i].tx_frames) { 296 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 297 mdelay(1); 298 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 299 } 300 } 301 } 302 303 #define X_CIM_PF_NOACCESS 0xeeeeeeee 304 /** 305 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 306 * @adap: the adapter 307 * @mbox: index of the mailbox to use 308 * @cmd: the command to write 309 * @size: command length in bytes 310 * @rpl: where to optionally store the reply 311 * @sleep_ok: if true we may sleep while awaiting command completion 312 * @timeout: time to wait for command to finish before timing out 313 * (negative implies @sleep_ok=false) 314 * 315 * Sends the given command to FW through the selected mailbox and waits 316 * for the FW to execute the command. If @rpl is not %NULL it is used to 317 * store the FW's reply to the command. The command and its optional 318 * reply are of the same length. Some FW commands like RESET and 319 * INITIALIZE can take a considerable amount of time to execute. 320 * @sleep_ok determines whether we may sleep while awaiting the response. 321 * If sleeping is allowed we use progressive backoff otherwise we spin. 322 * Note that passing in a negative @timeout is an alternate mechanism 323 * for specifying @sleep_ok=false. This is useful when a higher level 324 * interface allows for specification of @timeout but not @sleep_ok ... 325 * 326 * The return value is 0 on success or a negative errno on failure. A 327 * failure can happen either because we are not able to execute the 328 * command or FW executes it but signals an error. In the latter case 329 * the return value is the error code indicated by FW (negated). 330 */ 331 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 332 int size, void *rpl, bool sleep_ok, int timeout) 333 { 334 /* 335 * We delay in small increments at first in an effort to maintain 336 * responsiveness for simple, fast executing commands but then back 337 * off to larger delays to a maximum retry delay. 338 */ 339 static const int delay[] = { 340 1, 1, 3, 5, 10, 10, 20, 50, 100 341 }; 342 u32 v; 343 u64 res; 344 int i, ms, delay_idx, ret, next_tx_check; 345 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 346 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 347 u32 ctl; 348 __be64 cmd_rpl[MBOX_LEN/8]; 349 u32 pcie_fw; 350 struct port_tx_state tx_state[MAX_NPORTS]; 351 352 if (adap->flags & CHK_MBOX_ACCESS) 353 ASSERT_SYNCHRONIZED_OP(adap); 354 355 if (size <= 0 || (size & 15) || size > MBOX_LEN) 356 return -EINVAL; 357 358 if (adap->flags & IS_VF) { 359 if (is_t6(adap)) 360 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 361 else 362 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 363 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 364 } 365 366 /* 367 * If we have a negative timeout, that implies that we can't sleep. 368 */ 369 if (timeout < 0) { 370 sleep_ok = false; 371 timeout = -timeout; 372 } 373 374 /* 375 * Attempt to gain access to the mailbox. 376 */ 377 for (i = 0; i < 4; i++) { 378 ctl = t4_read_reg(adap, ctl_reg); 379 v = G_MBOWNER(ctl); 380 if (v != X_MBOWNER_NONE) 381 break; 382 } 383 384 /* 385 * If we were unable to gain access, report the error to our caller. 386 */ 387 if (v != X_MBOWNER_PL) { 388 t4_report_fw_error(adap); 389 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 390 return ret; 391 } 392 393 /* 394 * If we gain ownership of the mailbox and there's a "valid" message 395 * in it, this is likely an asynchronous error message from the 396 * firmware. So we'll report that and then proceed on with attempting 397 * to issue our own command ... which may well fail if the error 398 * presaged the firmware crashing ... 399 */ 400 if (ctl & F_MBMSGVALID) { 401 CH_DUMP_MBOX(adap, mbox, data_reg, "VLD", NULL, true); 402 } 403 404 /* 405 * Copy in the new mailbox command and send it on its way ... 406 */ 407 memset(cmd_rpl, 0, sizeof(cmd_rpl)); 408 memcpy(cmd_rpl, cmd, size); 409 CH_DUMP_MBOX(adap, mbox, 0, "cmd", cmd_rpl, false); 410 for (i = 0; i < ARRAY_SIZE(cmd_rpl); i++) 411 t4_write_reg64(adap, data_reg + i * 8, be64_to_cpu(cmd_rpl[i])); 412 413 if (adap->flags & IS_VF) { 414 /* 415 * For the VFs, the Mailbox Data "registers" are 416 * actually backed by T4's "MA" interface rather than 417 * PL Registers (as is the case for the PFs). Because 418 * these are in different coherency domains, the write 419 * to the VF's PL-register-backed Mailbox Control can 420 * race in front of the writes to the MA-backed VF 421 * Mailbox Data "registers". So we need to do a 422 * read-back on at least one byte of the VF Mailbox 423 * Data registers before doing the write to the VF 424 * Mailbox Control register. 425 */ 426 t4_read_reg(adap, data_reg); 427 } 428 429 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 430 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 431 next_tx_check = 1000; 432 delay_idx = 0; 433 ms = delay[0]; 434 435 /* 436 * Loop waiting for the reply; bail out if we time out or the firmware 437 * reports an error. 438 */ 439 pcie_fw = 0; 440 for (i = 0; i < timeout; i += ms) { 441 if (!(adap->flags & IS_VF)) { 442 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 443 if (pcie_fw & F_PCIE_FW_ERR) 444 break; 445 } 446 447 if (i >= next_tx_check) { 448 check_tx_state(adap, &tx_state[0]); 449 next_tx_check = i + 1000; 450 } 451 452 if (sleep_ok) { 453 ms = delay[delay_idx]; /* last element may repeat */ 454 if (delay_idx < ARRAY_SIZE(delay) - 1) 455 delay_idx++; 456 msleep(ms); 457 } else { 458 mdelay(ms); 459 } 460 461 v = t4_read_reg(adap, ctl_reg); 462 if (v == X_CIM_PF_NOACCESS) 463 continue; 464 if (G_MBOWNER(v) == X_MBOWNER_PL) { 465 if (!(v & F_MBMSGVALID)) { 466 t4_write_reg(adap, ctl_reg, 467 V_MBOWNER(X_MBOWNER_NONE)); 468 continue; 469 } 470 471 /* 472 * Retrieve the command reply and release the mailbox. 473 */ 474 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 475 CH_DUMP_MBOX(adap, mbox, 0, "rpl", cmd_rpl, false); 476 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 477 478 res = be64_to_cpu(cmd_rpl[0]); 479 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 480 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 481 res = V_FW_CMD_RETVAL(EIO); 482 } else if (rpl) 483 memcpy(rpl, cmd_rpl, size); 484 return -G_FW_CMD_RETVAL((int)res); 485 } 486 } 487 488 /* 489 * We timed out waiting for a reply to our mailbox command. Report 490 * the error and also check to see if the firmware reported any 491 * errors ... 492 */ 493 CH_ERR(adap, "command %#x in mbox %d timed out (0x%08x).\n", 494 *(const u8 *)cmd, mbox, pcie_fw); 495 CH_DUMP_MBOX(adap, mbox, 0, "cmdsent", cmd_rpl, true); 496 CH_DUMP_MBOX(adap, mbox, data_reg, "current", NULL, true); 497 498 if (pcie_fw & F_PCIE_FW_ERR) { 499 ret = -ENXIO; 500 t4_report_fw_error(adap); 501 } else { 502 ret = -ETIMEDOUT; 503 t4_os_dump_devlog(adap); 504 } 505 506 t4_fatal_err(adap, true); 507 return ret; 508 } 509 510 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 511 void *rpl, bool sleep_ok) 512 { 513 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 514 sleep_ok, FW_CMD_MAX_TIMEOUT); 515 516 } 517 518 static int t4_edc_err_read(struct adapter *adap, int idx) 519 { 520 u32 edc_ecc_err_addr_reg; 521 u32 edc_bist_status_rdata_reg; 522 523 if (is_t4(adap)) { 524 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 525 return 0; 526 } 527 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 528 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 529 return 0; 530 } 531 532 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 533 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 534 535 CH_WARN(adap, 536 "edc%d err addr 0x%x: 0x%x.\n", 537 idx, edc_ecc_err_addr_reg, 538 t4_read_reg(adap, edc_ecc_err_addr_reg)); 539 CH_WARN(adap, 540 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 541 edc_bist_status_rdata_reg, 542 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 543 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 544 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 545 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 546 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 547 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 548 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 549 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 550 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 551 552 return 0; 553 } 554 555 /** 556 * t4_mc_read - read from MC through backdoor accesses 557 * @adap: the adapter 558 * @idx: which MC to access 559 * @addr: address of first byte requested 560 * @data: 64 bytes of data containing the requested address 561 * @ecc: where to store the corresponding 64-bit ECC word 562 * 563 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 564 * that covers the requested address @addr. If @parity is not %NULL it 565 * is assigned the 64-bit ECC word for the read data. 566 */ 567 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 568 { 569 int i; 570 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 571 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 572 573 if (is_t4(adap)) { 574 mc_bist_cmd_reg = A_MC_BIST_CMD; 575 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 576 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 577 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 578 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 579 } else { 580 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 581 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 582 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 583 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 584 idx); 585 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 586 idx); 587 } 588 589 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 590 return -EBUSY; 591 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 592 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 593 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 594 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 595 F_START_BIST | V_BIST_CMD_GAP(1)); 596 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 597 if (i) 598 return i; 599 600 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 601 602 for (i = 15; i >= 0; i--) 603 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 604 if (ecc) 605 *ecc = t4_read_reg64(adap, MC_DATA(16)); 606 #undef MC_DATA 607 return 0; 608 } 609 610 /** 611 * t4_edc_read - read from EDC through backdoor accesses 612 * @adap: the adapter 613 * @idx: which EDC to access 614 * @addr: address of first byte requested 615 * @data: 64 bytes of data containing the requested address 616 * @ecc: where to store the corresponding 64-bit ECC word 617 * 618 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 619 * that covers the requested address @addr. If @parity is not %NULL it 620 * is assigned the 64-bit ECC word for the read data. 621 */ 622 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 623 { 624 int i; 625 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 626 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 627 628 if (is_t4(adap)) { 629 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 630 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 631 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 632 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 633 idx); 634 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 635 idx); 636 } else { 637 /* 638 * These macro are missing in t4_regs.h file. 639 * Added temporarily for testing. 640 */ 641 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 642 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 643 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 649 idx); 650 #undef EDC_REG_T5 651 #undef EDC_STRIDE_T5 652 } 653 654 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 655 return -EBUSY; 656 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 657 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 658 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 659 t4_write_reg(adap, edc_bist_cmd_reg, 660 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 661 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 662 if (i) 663 return i; 664 665 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 666 667 for (i = 15; i >= 0; i--) 668 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 669 if (ecc) 670 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 671 #undef EDC_DATA 672 return 0; 673 } 674 675 /** 676 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 677 * @adap: the adapter 678 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 679 * @addr: address within indicated memory type 680 * @len: amount of memory to read 681 * @buf: host memory buffer 682 * 683 * Reads an [almost] arbitrary memory region in the firmware: the 684 * firmware memory address, length and host buffer must be aligned on 685 * 32-bit boudaries. The memory is returned as a raw byte sequence from 686 * the firmware's memory. If this memory contains data structures which 687 * contain multi-byte integers, it's the callers responsibility to 688 * perform appropriate byte order conversions. 689 */ 690 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 691 __be32 *buf) 692 { 693 u32 pos, start, end, offset; 694 int ret; 695 696 /* 697 * Argument sanity checks ... 698 */ 699 if ((addr & 0x3) || (len & 0x3)) 700 return -EINVAL; 701 702 /* 703 * The underlaying EDC/MC read routines read 64 bytes at a time so we 704 * need to round down the start and round up the end. We'll start 705 * copying out of the first line at (addr - start) a word at a time. 706 */ 707 start = rounddown2(addr, 64); 708 end = roundup2(addr + len, 64); 709 offset = (addr - start)/sizeof(__be32); 710 711 for (pos = start; pos < end; pos += 64, offset = 0) { 712 __be32 data[16]; 713 714 /* 715 * Read the chip's memory block and bail if there's an error. 716 */ 717 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 718 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 719 else 720 ret = t4_edc_read(adap, mtype, pos, data, NULL); 721 if (ret) 722 return ret; 723 724 /* 725 * Copy the data into the caller's memory buffer. 726 */ 727 while (offset < 16 && len > 0) { 728 *buf++ = data[offset++]; 729 len -= sizeof(__be32); 730 } 731 } 732 733 return 0; 734 } 735 736 /* 737 * Return the specified PCI-E Configuration Space register from our Physical 738 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 739 * since we prefer to let the firmware own all of these registers, but if that 740 * fails we go for it directly ourselves. 741 */ 742 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 743 { 744 745 /* 746 * If fw_attach != 0, construct and send the Firmware LDST Command to 747 * retrieve the specified PCI-E Configuration Space register. 748 */ 749 if (drv_fw_attach != 0) { 750 struct fw_ldst_cmd ldst_cmd; 751 int ret; 752 753 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 754 ldst_cmd.op_to_addrspace = 755 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 756 F_FW_CMD_REQUEST | 757 F_FW_CMD_READ | 758 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 759 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 760 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 761 ldst_cmd.u.pcie.ctrl_to_fn = 762 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 763 ldst_cmd.u.pcie.r = reg; 764 765 /* 766 * If the LDST Command succeeds, return the result, otherwise 767 * fall through to reading it directly ourselves ... 768 */ 769 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 770 &ldst_cmd); 771 if (ret == 0) 772 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 773 774 CH_WARN(adap, "Firmware failed to return " 775 "Configuration Space register %d, err = %d\n", 776 reg, -ret); 777 } 778 779 /* 780 * Read the desired Configuration Space register via the PCI-E 781 * Backdoor mechanism. 782 */ 783 return t4_hw_pci_read_cfg4(adap, reg); 784 } 785 786 /** 787 * t4_get_regs_len - return the size of the chips register set 788 * @adapter: the adapter 789 * 790 * Returns the size of the chip's BAR0 register space. 791 */ 792 unsigned int t4_get_regs_len(struct adapter *adapter) 793 { 794 unsigned int chip_version = chip_id(adapter); 795 796 switch (chip_version) { 797 case CHELSIO_T4: 798 if (adapter->flags & IS_VF) 799 return FW_T4VF_REGMAP_SIZE; 800 return T4_REGMAP_SIZE; 801 802 case CHELSIO_T5: 803 case CHELSIO_T6: 804 if (adapter->flags & IS_VF) 805 return FW_T4VF_REGMAP_SIZE; 806 return T5_REGMAP_SIZE; 807 } 808 809 CH_ERR(adapter, 810 "Unsupported chip version %d\n", chip_version); 811 return 0; 812 } 813 814 /** 815 * t4_get_regs - read chip registers into provided buffer 816 * @adap: the adapter 817 * @buf: register buffer 818 * @buf_size: size (in bytes) of register buffer 819 * 820 * If the provided register buffer isn't large enough for the chip's 821 * full register range, the register dump will be truncated to the 822 * register buffer's size. 823 */ 824 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 825 { 826 static const unsigned int t4_reg_ranges[] = { 827 0x1008, 0x1108, 828 0x1180, 0x1184, 829 0x1190, 0x1194, 830 0x11a0, 0x11a4, 831 0x11b0, 0x11b4, 832 0x11fc, 0x123c, 833 0x1300, 0x173c, 834 0x1800, 0x18fc, 835 0x3000, 0x30d8, 836 0x30e0, 0x30e4, 837 0x30ec, 0x5910, 838 0x5920, 0x5924, 839 0x5960, 0x5960, 840 0x5968, 0x5968, 841 0x5970, 0x5970, 842 0x5978, 0x5978, 843 0x5980, 0x5980, 844 0x5988, 0x5988, 845 0x5990, 0x5990, 846 0x5998, 0x5998, 847 0x59a0, 0x59d4, 848 0x5a00, 0x5ae0, 849 0x5ae8, 0x5ae8, 850 0x5af0, 0x5af0, 851 0x5af8, 0x5af8, 852 0x6000, 0x6098, 853 0x6100, 0x6150, 854 0x6200, 0x6208, 855 0x6240, 0x6248, 856 0x6280, 0x62b0, 857 0x62c0, 0x6338, 858 0x6370, 0x638c, 859 0x6400, 0x643c, 860 0x6500, 0x6524, 861 0x6a00, 0x6a04, 862 0x6a14, 0x6a38, 863 0x6a60, 0x6a70, 864 0x6a78, 0x6a78, 865 0x6b00, 0x6b0c, 866 0x6b1c, 0x6b84, 867 0x6bf0, 0x6bf8, 868 0x6c00, 0x6c0c, 869 0x6c1c, 0x6c84, 870 0x6cf0, 0x6cf8, 871 0x6d00, 0x6d0c, 872 0x6d1c, 0x6d84, 873 0x6df0, 0x6df8, 874 0x6e00, 0x6e0c, 875 0x6e1c, 0x6e84, 876 0x6ef0, 0x6ef8, 877 0x6f00, 0x6f0c, 878 0x6f1c, 0x6f84, 879 0x6ff0, 0x6ff8, 880 0x7000, 0x700c, 881 0x701c, 0x7084, 882 0x70f0, 0x70f8, 883 0x7100, 0x710c, 884 0x711c, 0x7184, 885 0x71f0, 0x71f8, 886 0x7200, 0x720c, 887 0x721c, 0x7284, 888 0x72f0, 0x72f8, 889 0x7300, 0x730c, 890 0x731c, 0x7384, 891 0x73f0, 0x73f8, 892 0x7400, 0x7450, 893 0x7500, 0x7530, 894 0x7600, 0x760c, 895 0x7614, 0x761c, 896 0x7680, 0x76cc, 897 0x7700, 0x7798, 898 0x77c0, 0x77fc, 899 0x7900, 0x79fc, 900 0x7b00, 0x7b58, 901 0x7b60, 0x7b84, 902 0x7b8c, 0x7c38, 903 0x7d00, 0x7d38, 904 0x7d40, 0x7d80, 905 0x7d8c, 0x7ddc, 906 0x7de4, 0x7e04, 907 0x7e10, 0x7e1c, 908 0x7e24, 0x7e38, 909 0x7e40, 0x7e44, 910 0x7e4c, 0x7e78, 911 0x7e80, 0x7ea4, 912 0x7eac, 0x7edc, 913 0x7ee8, 0x7efc, 914 0x8dc0, 0x8e04, 915 0x8e10, 0x8e1c, 916 0x8e30, 0x8e78, 917 0x8ea0, 0x8eb8, 918 0x8ec0, 0x8f6c, 919 0x8fc0, 0x9008, 920 0x9010, 0x9058, 921 0x9060, 0x9060, 922 0x9068, 0x9074, 923 0x90fc, 0x90fc, 924 0x9400, 0x9408, 925 0x9410, 0x9458, 926 0x9600, 0x9600, 927 0x9608, 0x9638, 928 0x9640, 0x96bc, 929 0x9800, 0x9808, 930 0x9820, 0x983c, 931 0x9850, 0x9864, 932 0x9c00, 0x9c6c, 933 0x9c80, 0x9cec, 934 0x9d00, 0x9d6c, 935 0x9d80, 0x9dec, 936 0x9e00, 0x9e6c, 937 0x9e80, 0x9eec, 938 0x9f00, 0x9f6c, 939 0x9f80, 0x9fec, 940 0xd004, 0xd004, 941 0xd010, 0xd03c, 942 0xdfc0, 0xdfe0, 943 0xe000, 0xea7c, 944 0xf000, 0x11110, 945 0x11118, 0x11190, 946 0x19040, 0x1906c, 947 0x19078, 0x19080, 948 0x1908c, 0x190e4, 949 0x190f0, 0x190f8, 950 0x19100, 0x19110, 951 0x19120, 0x19124, 952 0x19150, 0x19194, 953 0x1919c, 0x191b0, 954 0x191d0, 0x191e8, 955 0x19238, 0x1924c, 956 0x193f8, 0x1943c, 957 0x1944c, 0x19474, 958 0x19490, 0x194e0, 959 0x194f0, 0x194f8, 960 0x19800, 0x19c08, 961 0x19c10, 0x19c90, 962 0x19ca0, 0x19ce4, 963 0x19cf0, 0x19d40, 964 0x19d50, 0x19d94, 965 0x19da0, 0x19de8, 966 0x19df0, 0x19e40, 967 0x19e50, 0x19e90, 968 0x19ea0, 0x19f4c, 969 0x1a000, 0x1a004, 970 0x1a010, 0x1a06c, 971 0x1a0b0, 0x1a0e4, 972 0x1a0ec, 0x1a0f4, 973 0x1a100, 0x1a108, 974 0x1a114, 0x1a120, 975 0x1a128, 0x1a130, 976 0x1a138, 0x1a138, 977 0x1a190, 0x1a1c4, 978 0x1a1fc, 0x1a1fc, 979 0x1e040, 0x1e04c, 980 0x1e284, 0x1e28c, 981 0x1e2c0, 0x1e2c0, 982 0x1e2e0, 0x1e2e0, 983 0x1e300, 0x1e384, 984 0x1e3c0, 0x1e3c8, 985 0x1e440, 0x1e44c, 986 0x1e684, 0x1e68c, 987 0x1e6c0, 0x1e6c0, 988 0x1e6e0, 0x1e6e0, 989 0x1e700, 0x1e784, 990 0x1e7c0, 0x1e7c8, 991 0x1e840, 0x1e84c, 992 0x1ea84, 0x1ea8c, 993 0x1eac0, 0x1eac0, 994 0x1eae0, 0x1eae0, 995 0x1eb00, 0x1eb84, 996 0x1ebc0, 0x1ebc8, 997 0x1ec40, 0x1ec4c, 998 0x1ee84, 0x1ee8c, 999 0x1eec0, 0x1eec0, 1000 0x1eee0, 0x1eee0, 1001 0x1ef00, 0x1ef84, 1002 0x1efc0, 0x1efc8, 1003 0x1f040, 0x1f04c, 1004 0x1f284, 0x1f28c, 1005 0x1f2c0, 0x1f2c0, 1006 0x1f2e0, 0x1f2e0, 1007 0x1f300, 0x1f384, 1008 0x1f3c0, 0x1f3c8, 1009 0x1f440, 0x1f44c, 1010 0x1f684, 0x1f68c, 1011 0x1f6c0, 0x1f6c0, 1012 0x1f6e0, 0x1f6e0, 1013 0x1f700, 0x1f784, 1014 0x1f7c0, 0x1f7c8, 1015 0x1f840, 0x1f84c, 1016 0x1fa84, 0x1fa8c, 1017 0x1fac0, 0x1fac0, 1018 0x1fae0, 0x1fae0, 1019 0x1fb00, 0x1fb84, 1020 0x1fbc0, 0x1fbc8, 1021 0x1fc40, 0x1fc4c, 1022 0x1fe84, 0x1fe8c, 1023 0x1fec0, 0x1fec0, 1024 0x1fee0, 0x1fee0, 1025 0x1ff00, 0x1ff84, 1026 0x1ffc0, 0x1ffc8, 1027 0x20000, 0x2002c, 1028 0x20100, 0x2013c, 1029 0x20190, 0x201a0, 1030 0x201a8, 0x201b8, 1031 0x201c4, 0x201c8, 1032 0x20200, 0x20318, 1033 0x20400, 0x204b4, 1034 0x204c0, 0x20528, 1035 0x20540, 0x20614, 1036 0x21000, 0x21040, 1037 0x2104c, 0x21060, 1038 0x210c0, 0x210ec, 1039 0x21200, 0x21268, 1040 0x21270, 0x21284, 1041 0x212fc, 0x21388, 1042 0x21400, 0x21404, 1043 0x21500, 0x21500, 1044 0x21510, 0x21518, 1045 0x2152c, 0x21530, 1046 0x2153c, 0x2153c, 1047 0x21550, 0x21554, 1048 0x21600, 0x21600, 1049 0x21608, 0x2161c, 1050 0x21624, 0x21628, 1051 0x21630, 0x21634, 1052 0x2163c, 0x2163c, 1053 0x21700, 0x2171c, 1054 0x21780, 0x2178c, 1055 0x21800, 0x21818, 1056 0x21820, 0x21828, 1057 0x21830, 0x21848, 1058 0x21850, 0x21854, 1059 0x21860, 0x21868, 1060 0x21870, 0x21870, 1061 0x21878, 0x21898, 1062 0x218a0, 0x218a8, 1063 0x218b0, 0x218c8, 1064 0x218d0, 0x218d4, 1065 0x218e0, 0x218e8, 1066 0x218f0, 0x218f0, 1067 0x218f8, 0x21a18, 1068 0x21a20, 0x21a28, 1069 0x21a30, 0x21a48, 1070 0x21a50, 0x21a54, 1071 0x21a60, 0x21a68, 1072 0x21a70, 0x21a70, 1073 0x21a78, 0x21a98, 1074 0x21aa0, 0x21aa8, 1075 0x21ab0, 0x21ac8, 1076 0x21ad0, 0x21ad4, 1077 0x21ae0, 0x21ae8, 1078 0x21af0, 0x21af0, 1079 0x21af8, 0x21c18, 1080 0x21c20, 0x21c20, 1081 0x21c28, 0x21c30, 1082 0x21c38, 0x21c38, 1083 0x21c80, 0x21c98, 1084 0x21ca0, 0x21ca8, 1085 0x21cb0, 0x21cc8, 1086 0x21cd0, 0x21cd4, 1087 0x21ce0, 0x21ce8, 1088 0x21cf0, 0x21cf0, 1089 0x21cf8, 0x21d7c, 1090 0x21e00, 0x21e04, 1091 0x22000, 0x2202c, 1092 0x22100, 0x2213c, 1093 0x22190, 0x221a0, 1094 0x221a8, 0x221b8, 1095 0x221c4, 0x221c8, 1096 0x22200, 0x22318, 1097 0x22400, 0x224b4, 1098 0x224c0, 0x22528, 1099 0x22540, 0x22614, 1100 0x23000, 0x23040, 1101 0x2304c, 0x23060, 1102 0x230c0, 0x230ec, 1103 0x23200, 0x23268, 1104 0x23270, 0x23284, 1105 0x232fc, 0x23388, 1106 0x23400, 0x23404, 1107 0x23500, 0x23500, 1108 0x23510, 0x23518, 1109 0x2352c, 0x23530, 1110 0x2353c, 0x2353c, 1111 0x23550, 0x23554, 1112 0x23600, 0x23600, 1113 0x23608, 0x2361c, 1114 0x23624, 0x23628, 1115 0x23630, 0x23634, 1116 0x2363c, 0x2363c, 1117 0x23700, 0x2371c, 1118 0x23780, 0x2378c, 1119 0x23800, 0x23818, 1120 0x23820, 0x23828, 1121 0x23830, 0x23848, 1122 0x23850, 0x23854, 1123 0x23860, 0x23868, 1124 0x23870, 0x23870, 1125 0x23878, 0x23898, 1126 0x238a0, 0x238a8, 1127 0x238b0, 0x238c8, 1128 0x238d0, 0x238d4, 1129 0x238e0, 0x238e8, 1130 0x238f0, 0x238f0, 1131 0x238f8, 0x23a18, 1132 0x23a20, 0x23a28, 1133 0x23a30, 0x23a48, 1134 0x23a50, 0x23a54, 1135 0x23a60, 0x23a68, 1136 0x23a70, 0x23a70, 1137 0x23a78, 0x23a98, 1138 0x23aa0, 0x23aa8, 1139 0x23ab0, 0x23ac8, 1140 0x23ad0, 0x23ad4, 1141 0x23ae0, 0x23ae8, 1142 0x23af0, 0x23af0, 1143 0x23af8, 0x23c18, 1144 0x23c20, 0x23c20, 1145 0x23c28, 0x23c30, 1146 0x23c38, 0x23c38, 1147 0x23c80, 0x23c98, 1148 0x23ca0, 0x23ca8, 1149 0x23cb0, 0x23cc8, 1150 0x23cd0, 0x23cd4, 1151 0x23ce0, 0x23ce8, 1152 0x23cf0, 0x23cf0, 1153 0x23cf8, 0x23d7c, 1154 0x23e00, 0x23e04, 1155 0x24000, 0x2402c, 1156 0x24100, 0x2413c, 1157 0x24190, 0x241a0, 1158 0x241a8, 0x241b8, 1159 0x241c4, 0x241c8, 1160 0x24200, 0x24318, 1161 0x24400, 0x244b4, 1162 0x244c0, 0x24528, 1163 0x24540, 0x24614, 1164 0x25000, 0x25040, 1165 0x2504c, 0x25060, 1166 0x250c0, 0x250ec, 1167 0x25200, 0x25268, 1168 0x25270, 0x25284, 1169 0x252fc, 0x25388, 1170 0x25400, 0x25404, 1171 0x25500, 0x25500, 1172 0x25510, 0x25518, 1173 0x2552c, 0x25530, 1174 0x2553c, 0x2553c, 1175 0x25550, 0x25554, 1176 0x25600, 0x25600, 1177 0x25608, 0x2561c, 1178 0x25624, 0x25628, 1179 0x25630, 0x25634, 1180 0x2563c, 0x2563c, 1181 0x25700, 0x2571c, 1182 0x25780, 0x2578c, 1183 0x25800, 0x25818, 1184 0x25820, 0x25828, 1185 0x25830, 0x25848, 1186 0x25850, 0x25854, 1187 0x25860, 0x25868, 1188 0x25870, 0x25870, 1189 0x25878, 0x25898, 1190 0x258a0, 0x258a8, 1191 0x258b0, 0x258c8, 1192 0x258d0, 0x258d4, 1193 0x258e0, 0x258e8, 1194 0x258f0, 0x258f0, 1195 0x258f8, 0x25a18, 1196 0x25a20, 0x25a28, 1197 0x25a30, 0x25a48, 1198 0x25a50, 0x25a54, 1199 0x25a60, 0x25a68, 1200 0x25a70, 0x25a70, 1201 0x25a78, 0x25a98, 1202 0x25aa0, 0x25aa8, 1203 0x25ab0, 0x25ac8, 1204 0x25ad0, 0x25ad4, 1205 0x25ae0, 0x25ae8, 1206 0x25af0, 0x25af0, 1207 0x25af8, 0x25c18, 1208 0x25c20, 0x25c20, 1209 0x25c28, 0x25c30, 1210 0x25c38, 0x25c38, 1211 0x25c80, 0x25c98, 1212 0x25ca0, 0x25ca8, 1213 0x25cb0, 0x25cc8, 1214 0x25cd0, 0x25cd4, 1215 0x25ce0, 0x25ce8, 1216 0x25cf0, 0x25cf0, 1217 0x25cf8, 0x25d7c, 1218 0x25e00, 0x25e04, 1219 0x26000, 0x2602c, 1220 0x26100, 0x2613c, 1221 0x26190, 0x261a0, 1222 0x261a8, 0x261b8, 1223 0x261c4, 0x261c8, 1224 0x26200, 0x26318, 1225 0x26400, 0x264b4, 1226 0x264c0, 0x26528, 1227 0x26540, 0x26614, 1228 0x27000, 0x27040, 1229 0x2704c, 0x27060, 1230 0x270c0, 0x270ec, 1231 0x27200, 0x27268, 1232 0x27270, 0x27284, 1233 0x272fc, 0x27388, 1234 0x27400, 0x27404, 1235 0x27500, 0x27500, 1236 0x27510, 0x27518, 1237 0x2752c, 0x27530, 1238 0x2753c, 0x2753c, 1239 0x27550, 0x27554, 1240 0x27600, 0x27600, 1241 0x27608, 0x2761c, 1242 0x27624, 0x27628, 1243 0x27630, 0x27634, 1244 0x2763c, 0x2763c, 1245 0x27700, 0x2771c, 1246 0x27780, 0x2778c, 1247 0x27800, 0x27818, 1248 0x27820, 0x27828, 1249 0x27830, 0x27848, 1250 0x27850, 0x27854, 1251 0x27860, 0x27868, 1252 0x27870, 0x27870, 1253 0x27878, 0x27898, 1254 0x278a0, 0x278a8, 1255 0x278b0, 0x278c8, 1256 0x278d0, 0x278d4, 1257 0x278e0, 0x278e8, 1258 0x278f0, 0x278f0, 1259 0x278f8, 0x27a18, 1260 0x27a20, 0x27a28, 1261 0x27a30, 0x27a48, 1262 0x27a50, 0x27a54, 1263 0x27a60, 0x27a68, 1264 0x27a70, 0x27a70, 1265 0x27a78, 0x27a98, 1266 0x27aa0, 0x27aa8, 1267 0x27ab0, 0x27ac8, 1268 0x27ad0, 0x27ad4, 1269 0x27ae0, 0x27ae8, 1270 0x27af0, 0x27af0, 1271 0x27af8, 0x27c18, 1272 0x27c20, 0x27c20, 1273 0x27c28, 0x27c30, 1274 0x27c38, 0x27c38, 1275 0x27c80, 0x27c98, 1276 0x27ca0, 0x27ca8, 1277 0x27cb0, 0x27cc8, 1278 0x27cd0, 0x27cd4, 1279 0x27ce0, 0x27ce8, 1280 0x27cf0, 0x27cf0, 1281 0x27cf8, 0x27d7c, 1282 0x27e00, 0x27e04, 1283 }; 1284 1285 static const unsigned int t4vf_reg_ranges[] = { 1286 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1287 VF_MPS_REG(A_MPS_VF_CTL), 1288 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1289 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1290 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1291 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1292 FW_T4VF_MBDATA_BASE_ADDR, 1293 FW_T4VF_MBDATA_BASE_ADDR + 1294 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1295 }; 1296 1297 static const unsigned int t5_reg_ranges[] = { 1298 0x1008, 0x10c0, 1299 0x10cc, 0x10f8, 1300 0x1100, 0x1100, 1301 0x110c, 0x1148, 1302 0x1180, 0x1184, 1303 0x1190, 0x1194, 1304 0x11a0, 0x11a4, 1305 0x11b0, 0x11b4, 1306 0x11fc, 0x123c, 1307 0x1280, 0x173c, 1308 0x1800, 0x18fc, 1309 0x3000, 0x3028, 1310 0x3060, 0x30b0, 1311 0x30b8, 0x30d8, 1312 0x30e0, 0x30fc, 1313 0x3140, 0x357c, 1314 0x35a8, 0x35cc, 1315 0x35ec, 0x35ec, 1316 0x3600, 0x5624, 1317 0x56cc, 0x56ec, 1318 0x56f4, 0x5720, 1319 0x5728, 0x575c, 1320 0x580c, 0x5814, 1321 0x5890, 0x589c, 1322 0x58a4, 0x58ac, 1323 0x58b8, 0x58bc, 1324 0x5940, 0x59c8, 1325 0x59d0, 0x59dc, 1326 0x59fc, 0x5a18, 1327 0x5a60, 0x5a70, 1328 0x5a80, 0x5a9c, 1329 0x5b94, 0x5bfc, 1330 0x6000, 0x6020, 1331 0x6028, 0x6040, 1332 0x6058, 0x609c, 1333 0x60a8, 0x614c, 1334 0x7700, 0x7798, 1335 0x77c0, 0x78fc, 1336 0x7b00, 0x7b58, 1337 0x7b60, 0x7b84, 1338 0x7b8c, 0x7c54, 1339 0x7d00, 0x7d38, 1340 0x7d40, 0x7d80, 1341 0x7d8c, 0x7ddc, 1342 0x7de4, 0x7e04, 1343 0x7e10, 0x7e1c, 1344 0x7e24, 0x7e38, 1345 0x7e40, 0x7e44, 1346 0x7e4c, 0x7e78, 1347 0x7e80, 0x7edc, 1348 0x7ee8, 0x7efc, 1349 0x8dc0, 0x8de0, 1350 0x8df8, 0x8e04, 1351 0x8e10, 0x8e84, 1352 0x8ea0, 0x8f84, 1353 0x8fc0, 0x9058, 1354 0x9060, 0x9060, 1355 0x9068, 0x90f8, 1356 0x9400, 0x9408, 1357 0x9410, 0x9470, 1358 0x9600, 0x9600, 1359 0x9608, 0x9638, 1360 0x9640, 0x96f4, 1361 0x9800, 0x9808, 1362 0x9810, 0x9864, 1363 0x9c00, 0x9c6c, 1364 0x9c80, 0x9cec, 1365 0x9d00, 0x9d6c, 1366 0x9d80, 0x9dec, 1367 0x9e00, 0x9e6c, 1368 0x9e80, 0x9eec, 1369 0x9f00, 0x9f6c, 1370 0x9f80, 0xa020, 1371 0xd000, 0xd004, 1372 0xd010, 0xd03c, 1373 0xdfc0, 0xdfe0, 1374 0xe000, 0x1106c, 1375 0x11074, 0x11088, 1376 0x1109c, 0x11110, 1377 0x11118, 0x1117c, 1378 0x11190, 0x11204, 1379 0x19040, 0x1906c, 1380 0x19078, 0x19080, 1381 0x1908c, 0x190e8, 1382 0x190f0, 0x190f8, 1383 0x19100, 0x19110, 1384 0x19120, 0x19124, 1385 0x19150, 0x19194, 1386 0x1919c, 0x191b0, 1387 0x191d0, 0x191e8, 1388 0x19238, 0x19290, 1389 0x193f8, 0x19428, 1390 0x19430, 0x19444, 1391 0x1944c, 0x1946c, 1392 0x19474, 0x19474, 1393 0x19490, 0x194cc, 1394 0x194f0, 0x194f8, 1395 0x19c00, 0x19c08, 1396 0x19c10, 0x19c60, 1397 0x19c94, 0x19ce4, 1398 0x19cf0, 0x19d40, 1399 0x19d50, 0x19d94, 1400 0x19da0, 0x19de8, 1401 0x19df0, 0x19e10, 1402 0x19e50, 0x19e90, 1403 0x19ea0, 0x19f24, 1404 0x19f34, 0x19f34, 1405 0x19f40, 0x19f50, 1406 0x19f90, 0x19fb4, 1407 0x19fc4, 0x19fe4, 1408 0x1a000, 0x1a004, 1409 0x1a010, 0x1a06c, 1410 0x1a0b0, 0x1a0e4, 1411 0x1a0ec, 0x1a0f8, 1412 0x1a100, 0x1a108, 1413 0x1a114, 0x1a130, 1414 0x1a138, 0x1a1c4, 1415 0x1a1fc, 0x1a1fc, 1416 0x1e008, 0x1e00c, 1417 0x1e040, 0x1e044, 1418 0x1e04c, 0x1e04c, 1419 0x1e284, 0x1e290, 1420 0x1e2c0, 0x1e2c0, 1421 0x1e2e0, 0x1e2e0, 1422 0x1e300, 0x1e384, 1423 0x1e3c0, 0x1e3c8, 1424 0x1e408, 0x1e40c, 1425 0x1e440, 0x1e444, 1426 0x1e44c, 0x1e44c, 1427 0x1e684, 0x1e690, 1428 0x1e6c0, 0x1e6c0, 1429 0x1e6e0, 0x1e6e0, 1430 0x1e700, 0x1e784, 1431 0x1e7c0, 0x1e7c8, 1432 0x1e808, 0x1e80c, 1433 0x1e840, 0x1e844, 1434 0x1e84c, 0x1e84c, 1435 0x1ea84, 0x1ea90, 1436 0x1eac0, 0x1eac0, 1437 0x1eae0, 0x1eae0, 1438 0x1eb00, 0x1eb84, 1439 0x1ebc0, 0x1ebc8, 1440 0x1ec08, 0x1ec0c, 1441 0x1ec40, 0x1ec44, 1442 0x1ec4c, 0x1ec4c, 1443 0x1ee84, 0x1ee90, 1444 0x1eec0, 0x1eec0, 1445 0x1eee0, 0x1eee0, 1446 0x1ef00, 0x1ef84, 1447 0x1efc0, 0x1efc8, 1448 0x1f008, 0x1f00c, 1449 0x1f040, 0x1f044, 1450 0x1f04c, 0x1f04c, 1451 0x1f284, 0x1f290, 1452 0x1f2c0, 0x1f2c0, 1453 0x1f2e0, 0x1f2e0, 1454 0x1f300, 0x1f384, 1455 0x1f3c0, 0x1f3c8, 1456 0x1f408, 0x1f40c, 1457 0x1f440, 0x1f444, 1458 0x1f44c, 0x1f44c, 1459 0x1f684, 0x1f690, 1460 0x1f6c0, 0x1f6c0, 1461 0x1f6e0, 0x1f6e0, 1462 0x1f700, 0x1f784, 1463 0x1f7c0, 0x1f7c8, 1464 0x1f808, 0x1f80c, 1465 0x1f840, 0x1f844, 1466 0x1f84c, 0x1f84c, 1467 0x1fa84, 0x1fa90, 1468 0x1fac0, 0x1fac0, 1469 0x1fae0, 0x1fae0, 1470 0x1fb00, 0x1fb84, 1471 0x1fbc0, 0x1fbc8, 1472 0x1fc08, 0x1fc0c, 1473 0x1fc40, 0x1fc44, 1474 0x1fc4c, 0x1fc4c, 1475 0x1fe84, 0x1fe90, 1476 0x1fec0, 0x1fec0, 1477 0x1fee0, 0x1fee0, 1478 0x1ff00, 0x1ff84, 1479 0x1ffc0, 0x1ffc8, 1480 0x30000, 0x30030, 1481 0x30100, 0x30144, 1482 0x30190, 0x301a0, 1483 0x301a8, 0x301b8, 1484 0x301c4, 0x301c8, 1485 0x301d0, 0x301d0, 1486 0x30200, 0x30318, 1487 0x30400, 0x304b4, 1488 0x304c0, 0x3052c, 1489 0x30540, 0x3061c, 1490 0x30800, 0x30828, 1491 0x30834, 0x30834, 1492 0x308c0, 0x30908, 1493 0x30910, 0x309ac, 1494 0x30a00, 0x30a14, 1495 0x30a1c, 0x30a2c, 1496 0x30a44, 0x30a50, 1497 0x30a74, 0x30a74, 1498 0x30a7c, 0x30afc, 1499 0x30b08, 0x30c24, 1500 0x30d00, 0x30d00, 1501 0x30d08, 0x30d14, 1502 0x30d1c, 0x30d20, 1503 0x30d3c, 0x30d3c, 1504 0x30d48, 0x30d50, 1505 0x31200, 0x3120c, 1506 0x31220, 0x31220, 1507 0x31240, 0x31240, 1508 0x31600, 0x3160c, 1509 0x31a00, 0x31a1c, 1510 0x31e00, 0x31e20, 1511 0x31e38, 0x31e3c, 1512 0x31e80, 0x31e80, 1513 0x31e88, 0x31ea8, 1514 0x31eb0, 0x31eb4, 1515 0x31ec8, 0x31ed4, 1516 0x31fb8, 0x32004, 1517 0x32200, 0x32200, 1518 0x32208, 0x32240, 1519 0x32248, 0x32280, 1520 0x32288, 0x322c0, 1521 0x322c8, 0x322fc, 1522 0x32600, 0x32630, 1523 0x32a00, 0x32abc, 1524 0x32b00, 0x32b10, 1525 0x32b20, 0x32b30, 1526 0x32b40, 0x32b50, 1527 0x32b60, 0x32b70, 1528 0x33000, 0x33028, 1529 0x33030, 0x33048, 1530 0x33060, 0x33068, 1531 0x33070, 0x3309c, 1532 0x330f0, 0x33128, 1533 0x33130, 0x33148, 1534 0x33160, 0x33168, 1535 0x33170, 0x3319c, 1536 0x331f0, 0x33238, 1537 0x33240, 0x33240, 1538 0x33248, 0x33250, 1539 0x3325c, 0x33264, 1540 0x33270, 0x332b8, 1541 0x332c0, 0x332e4, 1542 0x332f8, 0x33338, 1543 0x33340, 0x33340, 1544 0x33348, 0x33350, 1545 0x3335c, 0x33364, 1546 0x33370, 0x333b8, 1547 0x333c0, 0x333e4, 1548 0x333f8, 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1722 0x38d1c, 0x38d20, 1723 0x38d3c, 0x38d3c, 1724 0x38d48, 0x38d50, 1725 0x39200, 0x3920c, 1726 0x39220, 0x39220, 1727 0x39240, 0x39240, 1728 0x39600, 0x3960c, 1729 0x39a00, 0x39a1c, 1730 0x39e00, 0x39e20, 1731 0x39e38, 0x39e3c, 1732 0x39e80, 0x39e80, 1733 0x39e88, 0x39ea8, 1734 0x39eb0, 0x39eb4, 1735 0x39ec8, 0x39ed4, 1736 0x39fb8, 0x3a004, 1737 0x3a200, 0x3a200, 1738 0x3a208, 0x3a240, 1739 0x3a248, 0x3a280, 1740 0x3a288, 0x3a2c0, 1741 0x3a2c8, 0x3a2fc, 1742 0x3a600, 0x3a630, 1743 0x3aa00, 0x3aabc, 1744 0x3ab00, 0x3ab10, 1745 0x3ab20, 0x3ab30, 1746 0x3ab40, 0x3ab50, 1747 0x3ab60, 0x3ab70, 1748 0x3b000, 0x3b028, 1749 0x3b030, 0x3b048, 1750 0x3b060, 0x3b068, 1751 0x3b070, 0x3b09c, 1752 0x3b0f0, 0x3b128, 1753 0x3b130, 0x3b148, 1754 0x3b160, 0x3b168, 1755 0x3b170, 0x3b19c, 1756 0x3b1f0, 0x3b238, 1757 0x3b240, 0x3b240, 1758 0x3b248, 0x3b250, 1759 0x3b25c, 0x3b264, 1760 0x3b270, 0x3b2b8, 1761 0x3b2c0, 0x3b2e4, 1762 0x3b2f8, 0x3b338, 1763 0x3b340, 0x3b340, 1764 0x3b348, 0x3b350, 1765 0x3b35c, 0x3b364, 1766 0x3b370, 0x3b3b8, 1767 0x3b3c0, 0x3b3e4, 1768 0x3b3f8, 0x3b428, 1769 0x3b430, 0x3b448, 1770 0x3b460, 0x3b468, 1771 0x3b470, 0x3b49c, 1772 0x3b4f0, 0x3b528, 1773 0x3b530, 0x3b548, 1774 0x3b560, 0x3b568, 1775 0x3b570, 0x3b59c, 1776 0x3b5f0, 0x3b638, 1777 0x3b640, 0x3b640, 1778 0x3b648, 0x3b650, 1779 0x3b65c, 0x3b664, 1780 0x3b670, 0x3b6b8, 1781 0x3b6c0, 0x3b6e4, 1782 0x3b6f8, 0x3b738, 1783 0x3b740, 0x3b740, 1784 0x3b748, 0x3b750, 1785 0x3b75c, 0x3b764, 1786 0x3b770, 0x3b7b8, 1787 0x3b7c0, 0x3b7e4, 1788 0x3b7f8, 0x3b7fc, 1789 0x3b814, 0x3b814, 1790 0x3b82c, 0x3b82c, 1791 0x3b880, 0x3b88c, 1792 0x3b8e8, 0x3b8ec, 1793 0x3b900, 0x3b928, 1794 0x3b930, 0x3b948, 1795 0x3b960, 0x3b968, 1796 0x3b970, 0x3b99c, 1797 0x3b9f0, 0x3ba38, 1798 0x3ba40, 0x3ba40, 1799 0x3ba48, 0x3ba50, 1800 0x3ba5c, 0x3ba64, 1801 0x3ba70, 0x3bab8, 1802 0x3bac0, 0x3bae4, 1803 0x3baf8, 0x3bb10, 1804 0x3bb28, 0x3bb28, 1805 0x3bb3c, 0x3bb50, 1806 0x3bbf0, 0x3bc10, 1807 0x3bc28, 0x3bc28, 1808 0x3bc3c, 0x3bc50, 1809 0x3bcf0, 0x3bcfc, 1810 0x3c000, 0x3c030, 1811 0x3c100, 0x3c144, 1812 0x3c190, 0x3c1a0, 1813 0x3c1a8, 0x3c1b8, 1814 0x3c1c4, 0x3c1c8, 1815 0x3c1d0, 0x3c1d0, 1816 0x3c200, 0x3c318, 1817 0x3c400, 0x3c4b4, 1818 0x3c4c0, 0x3c52c, 1819 0x3c540, 0x3c61c, 1820 0x3c800, 0x3c828, 1821 0x3c834, 0x3c834, 1822 0x3c8c0, 0x3c908, 1823 0x3c910, 0x3c9ac, 1824 0x3ca00, 0x3ca14, 1825 0x3ca1c, 0x3ca2c, 1826 0x3ca44, 0x3ca50, 1827 0x3ca74, 0x3ca74, 1828 0x3ca7c, 0x3cafc, 1829 0x3cb08, 0x3cc24, 1830 0x3cd00, 0x3cd00, 1831 0x3cd08, 0x3cd14, 1832 0x3cd1c, 0x3cd20, 1833 0x3cd3c, 0x3cd3c, 1834 0x3cd48, 0x3cd50, 1835 0x3d200, 0x3d20c, 1836 0x3d220, 0x3d220, 1837 0x3d240, 0x3d240, 1838 0x3d600, 0x3d60c, 1839 0x3da00, 0x3da1c, 1840 0x3de00, 0x3de20, 1841 0x3de38, 0x3de3c, 1842 0x3de80, 0x3de80, 1843 0x3de88, 0x3dea8, 1844 0x3deb0, 0x3deb4, 1845 0x3dec8, 0x3ded4, 1846 0x3dfb8, 0x3e004, 1847 0x3e200, 0x3e200, 1848 0x3e208, 0x3e240, 1849 0x3e248, 0x3e280, 1850 0x3e288, 0x3e2c0, 1851 0x3e2c8, 0x3e2fc, 1852 0x3e600, 0x3e630, 1853 0x3ea00, 0x3eabc, 1854 0x3eb00, 0x3eb10, 1855 0x3eb20, 0x3eb30, 1856 0x3eb40, 0x3eb50, 1857 0x3eb60, 0x3eb70, 1858 0x3f000, 0x3f028, 1859 0x3f030, 0x3f048, 1860 0x3f060, 0x3f068, 1861 0x3f070, 0x3f09c, 1862 0x3f0f0, 0x3f128, 1863 0x3f130, 0x3f148, 1864 0x3f160, 0x3f168, 1865 0x3f170, 0x3f19c, 1866 0x3f1f0, 0x3f238, 1867 0x3f240, 0x3f240, 1868 0x3f248, 0x3f250, 1869 0x3f25c, 0x3f264, 1870 0x3f270, 0x3f2b8, 1871 0x3f2c0, 0x3f2e4, 1872 0x3f2f8, 0x3f338, 1873 0x3f340, 0x3f340, 1874 0x3f348, 0x3f350, 1875 0x3f35c, 0x3f364, 1876 0x3f370, 0x3f3b8, 1877 0x3f3c0, 0x3f3e4, 1878 0x3f3f8, 0x3f428, 1879 0x3f430, 0x3f448, 1880 0x3f460, 0x3f468, 1881 0x3f470, 0x3f49c, 1882 0x3f4f0, 0x3f528, 1883 0x3f530, 0x3f548, 1884 0x3f560, 0x3f568, 1885 0x3f570, 0x3f59c, 1886 0x3f5f0, 0x3f638, 1887 0x3f640, 0x3f640, 1888 0x3f648, 0x3f650, 1889 0x3f65c, 0x3f664, 1890 0x3f670, 0x3f6b8, 1891 0x3f6c0, 0x3f6e4, 1892 0x3f6f8, 0x3f738, 1893 0x3f740, 0x3f740, 1894 0x3f748, 0x3f750, 1895 0x3f75c, 0x3f764, 1896 0x3f770, 0x3f7b8, 1897 0x3f7c0, 0x3f7e4, 1898 0x3f7f8, 0x3f7fc, 1899 0x3f814, 0x3f814, 1900 0x3f82c, 0x3f82c, 1901 0x3f880, 0x3f88c, 1902 0x3f8e8, 0x3f8ec, 1903 0x3f900, 0x3f928, 1904 0x3f930, 0x3f948, 1905 0x3f960, 0x3f968, 1906 0x3f970, 0x3f99c, 1907 0x3f9f0, 0x3fa38, 1908 0x3fa40, 0x3fa40, 1909 0x3fa48, 0x3fa50, 1910 0x3fa5c, 0x3fa64, 1911 0x3fa70, 0x3fab8, 1912 0x3fac0, 0x3fae4, 1913 0x3faf8, 0x3fb10, 1914 0x3fb28, 0x3fb28, 1915 0x3fb3c, 0x3fb50, 1916 0x3fbf0, 0x3fc10, 1917 0x3fc28, 0x3fc28, 1918 0x3fc3c, 0x3fc50, 1919 0x3fcf0, 0x3fcfc, 1920 0x40000, 0x4000c, 1921 0x40040, 0x40050, 1922 0x40060, 0x40068, 1923 0x4007c, 0x4008c, 1924 0x40094, 0x400b0, 1925 0x400c0, 0x40144, 1926 0x40180, 0x4018c, 1927 0x40200, 0x40254, 1928 0x40260, 0x40264, 1929 0x40270, 0x40288, 1930 0x40290, 0x40298, 1931 0x402ac, 0x402c8, 1932 0x402d0, 0x402e0, 1933 0x402f0, 0x402f0, 1934 0x40300, 0x4033c, 1935 0x403f8, 0x403fc, 1936 0x41304, 0x413c4, 1937 0x41400, 0x4140c, 1938 0x41414, 0x4141c, 1939 0x41480, 0x414d0, 1940 0x44000, 0x44054, 1941 0x4405c, 0x44078, 1942 0x440c0, 0x44174, 1943 0x44180, 0x441ac, 1944 0x441b4, 0x441b8, 1945 0x441c0, 0x44254, 1946 0x4425c, 0x44278, 1947 0x442c0, 0x44374, 1948 0x44380, 0x443ac, 1949 0x443b4, 0x443b8, 1950 0x443c0, 0x44454, 1951 0x4445c, 0x44478, 1952 0x444c0, 0x44574, 1953 0x44580, 0x445ac, 1954 0x445b4, 0x445b8, 1955 0x445c0, 0x44654, 1956 0x4465c, 0x44678, 1957 0x446c0, 0x44774, 1958 0x44780, 0x447ac, 1959 0x447b4, 0x447b8, 1960 0x447c0, 0x44854, 1961 0x4485c, 0x44878, 1962 0x448c0, 0x44974, 1963 0x44980, 0x449ac, 1964 0x449b4, 0x449b8, 1965 0x449c0, 0x449fc, 1966 0x45000, 0x45004, 1967 0x45010, 0x45030, 1968 0x45040, 0x45060, 1969 0x45068, 0x45068, 1970 0x45080, 0x45084, 1971 0x450a0, 0x450b0, 1972 0x45200, 0x45204, 1973 0x45210, 0x45230, 1974 0x45240, 0x45260, 1975 0x45268, 0x45268, 1976 0x45280, 0x45284, 1977 0x452a0, 0x452b0, 1978 0x460c0, 0x460e4, 1979 0x47000, 0x4703c, 1980 0x47044, 0x4708c, 1981 0x47200, 0x47250, 1982 0x47400, 0x47408, 1983 0x47414, 0x47420, 1984 0x47600, 0x47618, 1985 0x47800, 0x47814, 1986 0x48000, 0x4800c, 1987 0x48040, 0x48050, 1988 0x48060, 0x48068, 1989 0x4807c, 0x4808c, 1990 0x48094, 0x480b0, 1991 0x480c0, 0x48144, 1992 0x48180, 0x4818c, 1993 0x48200, 0x48254, 1994 0x48260, 0x48264, 1995 0x48270, 0x48288, 1996 0x48290, 0x48298, 1997 0x482ac, 0x482c8, 1998 0x482d0, 0x482e0, 1999 0x482f0, 0x482f0, 2000 0x48300, 0x4833c, 2001 0x483f8, 0x483fc, 2002 0x49304, 0x493c4, 2003 0x49400, 0x4940c, 2004 0x49414, 0x4941c, 2005 0x49480, 0x494d0, 2006 0x4c000, 0x4c054, 2007 0x4c05c, 0x4c078, 2008 0x4c0c0, 0x4c174, 2009 0x4c180, 0x4c1ac, 2010 0x4c1b4, 0x4c1b8, 2011 0x4c1c0, 0x4c254, 2012 0x4c25c, 0x4c278, 2013 0x4c2c0, 0x4c374, 2014 0x4c380, 0x4c3ac, 2015 0x4c3b4, 0x4c3b8, 2016 0x4c3c0, 0x4c454, 2017 0x4c45c, 0x4c478, 2018 0x4c4c0, 0x4c574, 2019 0x4c580, 0x4c5ac, 2020 0x4c5b4, 0x4c5b8, 2021 0x4c5c0, 0x4c654, 2022 0x4c65c, 0x4c678, 2023 0x4c6c0, 0x4c774, 2024 0x4c780, 0x4c7ac, 2025 0x4c7b4, 0x4c7b8, 2026 0x4c7c0, 0x4c854, 2027 0x4c85c, 0x4c878, 2028 0x4c8c0, 0x4c974, 2029 0x4c980, 0x4c9ac, 2030 0x4c9b4, 0x4c9b8, 2031 0x4c9c0, 0x4c9fc, 2032 0x4d000, 0x4d004, 2033 0x4d010, 0x4d030, 2034 0x4d040, 0x4d060, 2035 0x4d068, 0x4d068, 2036 0x4d080, 0x4d084, 2037 0x4d0a0, 0x4d0b0, 2038 0x4d200, 0x4d204, 2039 0x4d210, 0x4d230, 2040 0x4d240, 0x4d260, 2041 0x4d268, 0x4d268, 2042 0x4d280, 0x4d284, 2043 0x4d2a0, 0x4d2b0, 2044 0x4e0c0, 0x4e0e4, 2045 0x4f000, 0x4f03c, 2046 0x4f044, 0x4f08c, 2047 0x4f200, 0x4f250, 2048 0x4f400, 0x4f408, 2049 0x4f414, 0x4f420, 2050 0x4f600, 0x4f618, 2051 0x4f800, 0x4f814, 2052 0x50000, 0x50084, 2053 0x50090, 0x500cc, 2054 0x50400, 0x50400, 2055 0x50800, 0x50884, 2056 0x50890, 0x508cc, 2057 0x50c00, 0x50c00, 2058 0x51000, 0x5101c, 2059 0x51300, 0x51308, 2060 }; 2061 2062 static const unsigned int t5vf_reg_ranges[] = { 2063 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2064 VF_MPS_REG(A_MPS_VF_CTL), 2065 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2066 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2067 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2068 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2069 FW_T4VF_MBDATA_BASE_ADDR, 2070 FW_T4VF_MBDATA_BASE_ADDR + 2071 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2072 }; 2073 2074 static const unsigned int t6_reg_ranges[] = { 2075 0x1008, 0x101c, 2076 0x1024, 0x10a8, 2077 0x10b4, 0x10f8, 2078 0x1100, 0x1114, 2079 0x111c, 0x112c, 2080 0x1138, 0x113c, 2081 0x1144, 0x114c, 2082 0x1180, 0x1184, 2083 0x1190, 0x1194, 2084 0x11a0, 0x11a4, 2085 0x11b0, 0x11c4, 2086 0x11fc, 0x123c, 2087 0x1254, 0x1274, 2088 0x1280, 0x133c, 2089 0x1800, 0x18fc, 2090 0x3000, 0x302c, 2091 0x3060, 0x30b0, 2092 0x30b8, 0x30d8, 2093 0x30e0, 0x30fc, 2094 0x3140, 0x357c, 2095 0x35a8, 0x35cc, 2096 0x35ec, 0x35ec, 2097 0x3600, 0x5624, 2098 0x56cc, 0x56ec, 2099 0x56f4, 0x5720, 2100 0x5728, 0x575c, 2101 0x580c, 0x5814, 2102 0x5890, 0x589c, 2103 0x58a4, 0x58ac, 2104 0x58b8, 0x58bc, 2105 0x5940, 0x595c, 2106 0x5980, 0x598c, 2107 0x59b0, 0x59c8, 2108 0x59d0, 0x59dc, 2109 0x59fc, 0x5a18, 2110 0x5a60, 0x5a6c, 2111 0x5a80, 0x5a8c, 2112 0x5a94, 0x5a9c, 2113 0x5b94, 0x5bfc, 2114 0x5c10, 0x5e48, 2115 0x5e50, 0x5e94, 2116 0x5ea0, 0x5eb0, 2117 0x5ec0, 0x5ec0, 2118 0x5ec8, 0x5ed0, 2119 0x5ee0, 0x5ee0, 2120 0x5ef0, 0x5ef0, 2121 0x5f00, 0x5f00, 2122 0x6000, 0x6020, 2123 0x6028, 0x6040, 2124 0x6058, 0x609c, 2125 0x60a8, 0x619c, 2126 0x7700, 0x7798, 2127 0x77c0, 0x7880, 2128 0x78cc, 0x78fc, 2129 0x7b00, 0x7b58, 2130 0x7b60, 0x7b84, 2131 0x7b8c, 0x7c54, 2132 0x7d00, 0x7d38, 2133 0x7d40, 0x7d84, 2134 0x7d8c, 0x7ddc, 2135 0x7de4, 0x7e04, 2136 0x7e10, 0x7e1c, 2137 0x7e24, 0x7e38, 2138 0x7e40, 0x7e44, 2139 0x7e4c, 0x7e78, 2140 0x7e80, 0x7edc, 2141 0x7ee8, 0x7efc, 2142 0x8dc0, 0x8de0, 2143 0x8df8, 0x8e04, 2144 0x8e10, 0x8e84, 2145 0x8ea0, 0x8f88, 2146 0x8fb8, 0x9058, 2147 0x9060, 0x9060, 2148 0x9068, 0x90f8, 2149 0x9100, 0x9124, 2150 0x9400, 0x9470, 2151 0x9600, 0x9600, 2152 0x9608, 0x9638, 2153 0x9640, 0x9704, 2154 0x9710, 0x971c, 2155 0x9800, 0x9808, 2156 0x9810, 0x9864, 2157 0x9c00, 0x9c6c, 2158 0x9c80, 0x9cec, 2159 0x9d00, 0x9d6c, 2160 0x9d80, 0x9dec, 2161 0x9e00, 0x9e6c, 2162 0x9e80, 0x9eec, 2163 0x9f00, 0x9f6c, 2164 0x9f80, 0xa020, 2165 0xd000, 0xd03c, 2166 0xd100, 0xd118, 2167 0xd200, 0xd214, 2168 0xd220, 0xd234, 2169 0xd240, 0xd254, 2170 0xd260, 0xd274, 2171 0xd280, 0xd294, 2172 0xd2a0, 0xd2b4, 2173 0xd2c0, 0xd2d4, 2174 0xd2e0, 0xd2f4, 2175 0xd300, 0xd31c, 2176 0xdfc0, 0xdfe0, 2177 0xe000, 0xf008, 2178 0xf010, 0xf018, 2179 0xf020, 0xf028, 2180 0x11000, 0x11014, 2181 0x11048, 0x1106c, 2182 0x11074, 0x11088, 2183 0x11098, 0x11120, 2184 0x1112c, 0x1117c, 2185 0x11190, 0x112e0, 2186 0x11300, 0x1130c, 2187 0x12000, 0x1206c, 2188 0x19040, 0x1906c, 2189 0x19078, 0x19080, 2190 0x1908c, 0x190e8, 2191 0x190f0, 0x190f8, 2192 0x19100, 0x19110, 2193 0x19120, 0x19124, 2194 0x19150, 0x19194, 2195 0x1919c, 0x191b0, 2196 0x191d0, 0x191e8, 2197 0x19238, 0x19290, 2198 0x192a4, 0x192b0, 2199 0x19348, 0x1934c, 2200 0x193f8, 0x19418, 2201 0x19420, 0x19428, 2202 0x19430, 0x19444, 2203 0x1944c, 0x1946c, 2204 0x19474, 0x19474, 2205 0x19490, 0x194cc, 2206 0x194f0, 0x194f8, 2207 0x19c00, 0x19c48, 2208 0x19c50, 0x19c80, 2209 0x19c94, 0x19c98, 2210 0x19ca0, 0x19cbc, 2211 0x19ce4, 0x19ce4, 2212 0x19cf0, 0x19cf8, 2213 0x19d00, 0x19d28, 2214 0x19d50, 0x19d78, 2215 0x19d94, 0x19d98, 2216 0x19da0, 0x19de0, 2217 0x19df0, 0x19e10, 2218 0x19e50, 0x19e6c, 2219 0x19ea0, 0x19ebc, 2220 0x19ec4, 0x19ef4, 2221 0x19f04, 0x19f2c, 2222 0x19f34, 0x19f34, 2223 0x19f40, 0x19f50, 2224 0x19f90, 0x19fac, 2225 0x19fc4, 0x19fc8, 2226 0x19fd0, 0x19fe4, 2227 0x1a000, 0x1a004, 2228 0x1a010, 0x1a06c, 2229 0x1a0b0, 0x1a0e4, 2230 0x1a0ec, 0x1a0f8, 2231 0x1a100, 0x1a108, 2232 0x1a114, 0x1a130, 2233 0x1a138, 0x1a1c4, 2234 0x1a1fc, 0x1a1fc, 2235 0x1e008, 0x1e00c, 2236 0x1e040, 0x1e044, 2237 0x1e04c, 0x1e04c, 2238 0x1e284, 0x1e290, 2239 0x1e2c0, 0x1e2c0, 2240 0x1e2e0, 0x1e2e0, 2241 0x1e300, 0x1e384, 2242 0x1e3c0, 0x1e3c8, 2243 0x1e408, 0x1e40c, 2244 0x1e440, 0x1e444, 2245 0x1e44c, 0x1e44c, 2246 0x1e684, 0x1e690, 2247 0x1e6c0, 0x1e6c0, 2248 0x1e6e0, 0x1e6e0, 2249 0x1e700, 0x1e784, 2250 0x1e7c0, 0x1e7c8, 2251 0x1e808, 0x1e80c, 2252 0x1e840, 0x1e844, 2253 0x1e84c, 0x1e84c, 2254 0x1ea84, 0x1ea90, 2255 0x1eac0, 0x1eac0, 2256 0x1eae0, 0x1eae0, 2257 0x1eb00, 0x1eb84, 2258 0x1ebc0, 0x1ebc8, 2259 0x1ec08, 0x1ec0c, 2260 0x1ec40, 0x1ec44, 2261 0x1ec4c, 0x1ec4c, 2262 0x1ee84, 0x1ee90, 2263 0x1eec0, 0x1eec0, 2264 0x1eee0, 0x1eee0, 2265 0x1ef00, 0x1ef84, 2266 0x1efc0, 0x1efc8, 2267 0x1f008, 0x1f00c, 2268 0x1f040, 0x1f044, 2269 0x1f04c, 0x1f04c, 2270 0x1f284, 0x1f290, 2271 0x1f2c0, 0x1f2c0, 2272 0x1f2e0, 0x1f2e0, 2273 0x1f300, 0x1f384, 2274 0x1f3c0, 0x1f3c8, 2275 0x1f408, 0x1f40c, 2276 0x1f440, 0x1f444, 2277 0x1f44c, 0x1f44c, 2278 0x1f684, 0x1f690, 2279 0x1f6c0, 0x1f6c0, 2280 0x1f6e0, 0x1f6e0, 2281 0x1f700, 0x1f784, 2282 0x1f7c0, 0x1f7c8, 2283 0x1f808, 0x1f80c, 2284 0x1f840, 0x1f844, 2285 0x1f84c, 0x1f84c, 2286 0x1fa84, 0x1fa90, 2287 0x1fac0, 0x1fac0, 2288 0x1fae0, 0x1fae0, 2289 0x1fb00, 0x1fb84, 2290 0x1fbc0, 0x1fbc8, 2291 0x1fc08, 0x1fc0c, 2292 0x1fc40, 0x1fc44, 2293 0x1fc4c, 0x1fc4c, 2294 0x1fe84, 0x1fe90, 2295 0x1fec0, 0x1fec0, 2296 0x1fee0, 0x1fee0, 2297 0x1ff00, 0x1ff84, 2298 0x1ffc0, 0x1ffc8, 2299 0x30000, 0x30030, 2300 0x30100, 0x30168, 2301 0x30190, 0x301a0, 2302 0x301a8, 0x301b8, 2303 0x301c4, 0x301c8, 2304 0x301d0, 0x301d0, 2305 0x30200, 0x30320, 2306 0x30400, 0x304b4, 2307 0x304c0, 0x3052c, 2308 0x30540, 0x3061c, 2309 0x30800, 0x308a0, 2310 0x308c0, 0x30908, 2311 0x30910, 0x309b8, 2312 0x30a00, 0x30a04, 2313 0x30a0c, 0x30a14, 2314 0x30a1c, 0x30a2c, 2315 0x30a44, 0x30a50, 2316 0x30a74, 0x30a74, 2317 0x30a7c, 0x30afc, 2318 0x30b08, 0x30c24, 2319 0x30d00, 0x30d14, 2320 0x30d1c, 0x30d3c, 2321 0x30d44, 0x30d4c, 2322 0x30d54, 0x30d74, 2323 0x30d7c, 0x30d7c, 2324 0x30de0, 0x30de0, 2325 0x30e00, 0x30ed4, 2326 0x30f00, 0x30fa4, 2327 0x30fc0, 0x30fc4, 2328 0x31000, 0x31004, 2329 0x31080, 0x310fc, 2330 0x31208, 0x31220, 2331 0x3123c, 0x31254, 2332 0x31300, 0x31300, 2333 0x31308, 0x3131c, 2334 0x31338, 0x3133c, 2335 0x31380, 0x31380, 2336 0x31388, 0x313a8, 2337 0x313b4, 0x313b4, 2338 0x31400, 0x31420, 2339 0x31438, 0x3143c, 2340 0x31480, 0x31480, 2341 0x314a8, 0x314a8, 2342 0x314b0, 0x314b4, 2343 0x314c8, 0x314d4, 2344 0x31a40, 0x31a4c, 2345 0x31af0, 0x31b20, 2346 0x31b38, 0x31b3c, 2347 0x31b80, 0x31b80, 2348 0x31ba8, 0x31ba8, 2349 0x31bb0, 0x31bb4, 2350 0x31bc8, 0x31bd4, 2351 0x32140, 0x3218c, 2352 0x321f0, 0x321f4, 2353 0x32200, 0x32200, 2354 0x32218, 0x32218, 2355 0x32400, 0x32400, 2356 0x32408, 0x3241c, 2357 0x32618, 0x32620, 2358 0x32664, 0x32664, 2359 0x326a8, 0x326a8, 2360 0x326ec, 0x326ec, 2361 0x32a00, 0x32abc, 2362 0x32b00, 0x32b18, 2363 0x32b20, 0x32b38, 2364 0x32b40, 0x32b58, 2365 0x32b60, 0x32b78, 2366 0x32c00, 0x32c00, 2367 0x32c08, 0x32c3c, 2368 0x33000, 0x3302c, 2369 0x33034, 0x33050, 2370 0x33058, 0x33058, 2371 0x33060, 0x3308c, 2372 0x3309c, 0x330ac, 2373 0x330c0, 0x330c0, 2374 0x330c8, 0x330d0, 2375 0x330d8, 0x330e0, 2376 0x330ec, 0x3312c, 2377 0x33134, 0x33150, 2378 0x33158, 0x33158, 2379 0x33160, 0x3318c, 2380 0x3319c, 0x331ac, 2381 0x331c0, 0x331c0, 2382 0x331c8, 0x331d0, 2383 0x331d8, 0x331e0, 2384 0x331ec, 0x33290, 2385 0x33298, 0x332c4, 2386 0x332e4, 0x33390, 2387 0x33398, 0x333c4, 2388 0x333e4, 0x3342c, 2389 0x33434, 0x33450, 2390 0x33458, 0x33458, 2391 0x33460, 0x3348c, 2392 0x3349c, 0x334ac, 2393 0x334c0, 0x334c0, 2394 0x334c8, 0x334d0, 2395 0x334d8, 0x334e0, 2396 0x334ec, 0x3352c, 2397 0x33534, 0x33550, 2398 0x33558, 0x33558, 2399 0x33560, 0x3358c, 2400 0x3359c, 0x335ac, 2401 0x335c0, 0x335c0, 2402 0x335c8, 0x335d0, 2403 0x335d8, 0x335e0, 2404 0x335ec, 0x33690, 2405 0x33698, 0x336c4, 2406 0x336e4, 0x33790, 2407 0x33798, 0x337c4, 2408 0x337e4, 0x337fc, 2409 0x33814, 0x33814, 2410 0x33854, 0x33868, 2411 0x33880, 0x3388c, 2412 0x338c0, 0x338d0, 2413 0x338e8, 0x338ec, 2414 0x33900, 0x3392c, 2415 0x33934, 0x33950, 2416 0x33958, 0x33958, 2417 0x33960, 0x3398c, 2418 0x3399c, 0x339ac, 2419 0x339c0, 0x339c0, 2420 0x339c8, 0x339d0, 2421 0x339d8, 0x339e0, 2422 0x339ec, 0x33a90, 2423 0x33a98, 0x33ac4, 2424 0x33ae4, 0x33b10, 2425 0x33b24, 0x33b28, 2426 0x33b38, 0x33b50, 2427 0x33bf0, 0x33c10, 2428 0x33c24, 0x33c28, 2429 0x33c38, 0x33c50, 2430 0x33cf0, 0x33cfc, 2431 0x34000, 0x34030, 2432 0x34100, 0x34168, 2433 0x34190, 0x341a0, 2434 0x341a8, 0x341b8, 2435 0x341c4, 0x341c8, 2436 0x341d0, 0x341d0, 2437 0x34200, 0x34320, 2438 0x34400, 0x344b4, 2439 0x344c0, 0x3452c, 2440 0x34540, 0x3461c, 2441 0x34800, 0x348a0, 2442 0x348c0, 0x34908, 2443 0x34910, 0x349b8, 2444 0x34a00, 0x34a04, 2445 0x34a0c, 0x34a14, 2446 0x34a1c, 0x34a2c, 2447 0x34a44, 0x34a50, 2448 0x34a74, 0x34a74, 2449 0x34a7c, 0x34afc, 2450 0x34b08, 0x34c24, 2451 0x34d00, 0x34d14, 2452 0x34d1c, 0x34d3c, 2453 0x34d44, 0x34d4c, 2454 0x34d54, 0x34d74, 2455 0x34d7c, 0x34d7c, 2456 0x34de0, 0x34de0, 2457 0x34e00, 0x34ed4, 2458 0x34f00, 0x34fa4, 2459 0x34fc0, 0x34fc4, 2460 0x35000, 0x35004, 2461 0x35080, 0x350fc, 2462 0x35208, 0x35220, 2463 0x3523c, 0x35254, 2464 0x35300, 0x35300, 2465 0x35308, 0x3531c, 2466 0x35338, 0x3533c, 2467 0x35380, 0x35380, 2468 0x35388, 0x353a8, 2469 0x353b4, 0x353b4, 2470 0x35400, 0x35420, 2471 0x35438, 0x3543c, 2472 0x35480, 0x35480, 2473 0x354a8, 0x354a8, 2474 0x354b0, 0x354b4, 2475 0x354c8, 0x354d4, 2476 0x35a40, 0x35a4c, 2477 0x35af0, 0x35b20, 2478 0x35b38, 0x35b3c, 2479 0x35b80, 0x35b80, 2480 0x35ba8, 0x35ba8, 2481 0x35bb0, 0x35bb4, 2482 0x35bc8, 0x35bd4, 2483 0x36140, 0x3618c, 2484 0x361f0, 0x361f4, 2485 0x36200, 0x36200, 2486 0x36218, 0x36218, 2487 0x36400, 0x36400, 2488 0x36408, 0x3641c, 2489 0x36618, 0x36620, 2490 0x36664, 0x36664, 2491 0x366a8, 0x366a8, 2492 0x366ec, 0x366ec, 2493 0x36a00, 0x36abc, 2494 0x36b00, 0x36b18, 2495 0x36b20, 0x36b38, 2496 0x36b40, 0x36b58, 2497 0x36b60, 0x36b78, 2498 0x36c00, 0x36c00, 2499 0x36c08, 0x36c3c, 2500 0x37000, 0x3702c, 2501 0x37034, 0x37050, 2502 0x37058, 0x37058, 2503 0x37060, 0x3708c, 2504 0x3709c, 0x370ac, 2505 0x370c0, 0x370c0, 2506 0x370c8, 0x370d0, 2507 0x370d8, 0x370e0, 2508 0x370ec, 0x3712c, 2509 0x37134, 0x37150, 2510 0x37158, 0x37158, 2511 0x37160, 0x3718c, 2512 0x3719c, 0x371ac, 2513 0x371c0, 0x371c0, 2514 0x371c8, 0x371d0, 2515 0x371d8, 0x371e0, 2516 0x371ec, 0x37290, 2517 0x37298, 0x372c4, 2518 0x372e4, 0x37390, 2519 0x37398, 0x373c4, 2520 0x373e4, 0x3742c, 2521 0x37434, 0x37450, 2522 0x37458, 0x37458, 2523 0x37460, 0x3748c, 2524 0x3749c, 0x374ac, 2525 0x374c0, 0x374c0, 2526 0x374c8, 0x374d0, 2527 0x374d8, 0x374e0, 2528 0x374ec, 0x3752c, 2529 0x37534, 0x37550, 2530 0x37558, 0x37558, 2531 0x37560, 0x3758c, 2532 0x3759c, 0x375ac, 2533 0x375c0, 0x375c0, 2534 0x375c8, 0x375d0, 2535 0x375d8, 0x375e0, 2536 0x375ec, 0x37690, 2537 0x37698, 0x376c4, 2538 0x376e4, 0x37790, 2539 0x37798, 0x377c4, 2540 0x377e4, 0x377fc, 2541 0x37814, 0x37814, 2542 0x37854, 0x37868, 2543 0x37880, 0x3788c, 2544 0x378c0, 0x378d0, 2545 0x378e8, 0x378ec, 2546 0x37900, 0x3792c, 2547 0x37934, 0x37950, 2548 0x37958, 0x37958, 2549 0x37960, 0x3798c, 2550 0x3799c, 0x379ac, 2551 0x379c0, 0x379c0, 2552 0x379c8, 0x379d0, 2553 0x379d8, 0x379e0, 2554 0x379ec, 0x37a90, 2555 0x37a98, 0x37ac4, 2556 0x37ae4, 0x37b10, 2557 0x37b24, 0x37b28, 2558 0x37b38, 0x37b50, 2559 0x37bf0, 0x37c10, 2560 0x37c24, 0x37c28, 2561 0x37c38, 0x37c50, 2562 0x37cf0, 0x37cfc, 2563 0x40040, 0x40040, 2564 0x40080, 0x40084, 2565 0x40100, 0x40100, 2566 0x40140, 0x401bc, 2567 0x40200, 0x40214, 2568 0x40228, 0x40228, 2569 0x40240, 0x40258, 2570 0x40280, 0x40280, 2571 0x40304, 0x40304, 2572 0x40330, 0x4033c, 2573 0x41304, 0x413c8, 2574 0x413d0, 0x413dc, 2575 0x413f0, 0x413f0, 2576 0x41400, 0x4140c, 2577 0x41414, 0x4141c, 2578 0x41480, 0x414d0, 2579 0x44000, 0x4407c, 2580 0x440c0, 0x441ac, 2581 0x441b4, 0x4427c, 2582 0x442c0, 0x443ac, 2583 0x443b4, 0x4447c, 2584 0x444c0, 0x445ac, 2585 0x445b4, 0x4467c, 2586 0x446c0, 0x447ac, 2587 0x447b4, 0x4487c, 2588 0x448c0, 0x449ac, 2589 0x449b4, 0x44a7c, 2590 0x44ac0, 0x44bac, 2591 0x44bb4, 0x44c7c, 2592 0x44cc0, 0x44dac, 2593 0x44db4, 0x44e7c, 2594 0x44ec0, 0x44fac, 2595 0x44fb4, 0x4507c, 2596 0x450c0, 0x451ac, 2597 0x451b4, 0x451fc, 2598 0x45800, 0x45804, 2599 0x45810, 0x45830, 2600 0x45840, 0x45860, 2601 0x45868, 0x45868, 2602 0x45880, 0x45884, 2603 0x458a0, 0x458b0, 2604 0x45a00, 0x45a04, 2605 0x45a10, 0x45a30, 2606 0x45a40, 0x45a60, 2607 0x45a68, 0x45a68, 2608 0x45a80, 0x45a84, 2609 0x45aa0, 0x45ab0, 2610 0x460c0, 0x460e4, 2611 0x47000, 0x4703c, 2612 0x47044, 0x4708c, 2613 0x47200, 0x47250, 2614 0x47400, 0x47408, 2615 0x47414, 0x47420, 2616 0x47600, 0x47618, 2617 0x47800, 0x47814, 2618 0x47820, 0x4782c, 2619 0x50000, 0x50084, 2620 0x50090, 0x500cc, 2621 0x50300, 0x50384, 2622 0x50400, 0x50400, 2623 0x50800, 0x50884, 2624 0x50890, 0x508cc, 2625 0x50b00, 0x50b84, 2626 0x50c00, 0x50c00, 2627 0x51000, 0x51020, 2628 0x51028, 0x510b0, 2629 0x51300, 0x51324, 2630 }; 2631 2632 static const unsigned int t6vf_reg_ranges[] = { 2633 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2634 VF_MPS_REG(A_MPS_VF_CTL), 2635 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2636 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2637 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2638 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2639 FW_T6VF_MBDATA_BASE_ADDR, 2640 FW_T6VF_MBDATA_BASE_ADDR + 2641 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2642 }; 2643 2644 u32 *buf_end = (u32 *)(buf + buf_size); 2645 const unsigned int *reg_ranges; 2646 int reg_ranges_size, range; 2647 unsigned int chip_version = chip_id(adap); 2648 2649 /* 2650 * Select the right set of register ranges to dump depending on the 2651 * adapter chip type. 2652 */ 2653 switch (chip_version) { 2654 case CHELSIO_T4: 2655 if (adap->flags & IS_VF) { 2656 reg_ranges = t4vf_reg_ranges; 2657 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2658 } else { 2659 reg_ranges = t4_reg_ranges; 2660 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2661 } 2662 break; 2663 2664 case CHELSIO_T5: 2665 if (adap->flags & IS_VF) { 2666 reg_ranges = t5vf_reg_ranges; 2667 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2668 } else { 2669 reg_ranges = t5_reg_ranges; 2670 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2671 } 2672 break; 2673 2674 case CHELSIO_T6: 2675 if (adap->flags & IS_VF) { 2676 reg_ranges = t6vf_reg_ranges; 2677 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2678 } else { 2679 reg_ranges = t6_reg_ranges; 2680 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2681 } 2682 break; 2683 2684 default: 2685 CH_ERR(adap, 2686 "Unsupported chip version %d\n", chip_version); 2687 return; 2688 } 2689 2690 /* 2691 * Clear the register buffer and insert the appropriate register 2692 * values selected by the above register ranges. 2693 */ 2694 memset(buf, 0, buf_size); 2695 for (range = 0; range < reg_ranges_size; range += 2) { 2696 unsigned int reg = reg_ranges[range]; 2697 unsigned int last_reg = reg_ranges[range + 1]; 2698 u32 *bufp = (u32 *)(buf + reg); 2699 2700 /* 2701 * Iterate across the register range filling in the register 2702 * buffer but don't write past the end of the register buffer. 2703 */ 2704 while (reg <= last_reg && bufp < buf_end) { 2705 *bufp++ = t4_read_reg(adap, reg); 2706 reg += sizeof(u32); 2707 } 2708 } 2709 } 2710 2711 /* 2712 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2713 * header followed by one or more VPD-R sections, each with its own header. 2714 */ 2715 struct t4_vpd_hdr { 2716 u8 id_tag; 2717 u8 id_len[2]; 2718 u8 id_data[ID_LEN]; 2719 }; 2720 2721 struct t4_vpdr_hdr { 2722 u8 vpdr_tag; 2723 u8 vpdr_len[2]; 2724 }; 2725 2726 /* 2727 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2728 */ 2729 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2730 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2731 2732 #define EEPROM_STAT_ADDR 0x7bfc 2733 #define VPD_SIZE 0x800 2734 #define VPD_BASE 0x400 2735 #define VPD_BASE_OLD 0 2736 #define VPD_LEN 1024 2737 #define VPD_INFO_FLD_HDR_SIZE 3 2738 #define CHELSIO_VPD_UNIQUE_ID 0x82 2739 2740 /* 2741 * Small utility function to wait till any outstanding VPD Access is complete. 2742 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2743 * VPD Access in flight. This allows us to handle the problem of having a 2744 * previous VPD Access time out and prevent an attempt to inject a new VPD 2745 * Request before any in-flight VPD reguest has completed. 2746 */ 2747 static int t4_seeprom_wait(struct adapter *adapter) 2748 { 2749 unsigned int base = adapter->params.pci.vpd_cap_addr; 2750 int max_poll; 2751 2752 /* 2753 * If no VPD Access is in flight, we can just return success right 2754 * away. 2755 */ 2756 if (!adapter->vpd_busy) 2757 return 0; 2758 2759 /* 2760 * Poll the VPD Capability Address/Flag register waiting for it 2761 * to indicate that the operation is complete. 2762 */ 2763 max_poll = EEPROM_MAX_POLL; 2764 do { 2765 u16 val; 2766 2767 udelay(EEPROM_DELAY); 2768 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2769 2770 /* 2771 * If the operation is complete, mark the VPD as no longer 2772 * busy and return success. 2773 */ 2774 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2775 adapter->vpd_busy = 0; 2776 return 0; 2777 } 2778 } while (--max_poll); 2779 2780 /* 2781 * Failure! Note that we leave the VPD Busy status set in order to 2782 * avoid pushing a new VPD Access request into the VPD Capability till 2783 * the current operation eventually succeeds. It's a bug to issue a 2784 * new request when an existing request is in flight and will result 2785 * in corrupt hardware state. 2786 */ 2787 return -ETIMEDOUT; 2788 } 2789 2790 /** 2791 * t4_seeprom_read - read a serial EEPROM location 2792 * @adapter: adapter to read 2793 * @addr: EEPROM virtual address 2794 * @data: where to store the read data 2795 * 2796 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2797 * VPD capability. Note that this function must be called with a virtual 2798 * address. 2799 */ 2800 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2801 { 2802 unsigned int base = adapter->params.pci.vpd_cap_addr; 2803 int ret; 2804 2805 /* 2806 * VPD Accesses must alway be 4-byte aligned! 2807 */ 2808 if (addr >= EEPROMVSIZE || (addr & 3)) 2809 return -EINVAL; 2810 2811 /* 2812 * Wait for any previous operation which may still be in flight to 2813 * complete. 2814 */ 2815 ret = t4_seeprom_wait(adapter); 2816 if (ret) { 2817 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2818 return ret; 2819 } 2820 2821 /* 2822 * Issue our new VPD Read request, mark the VPD as being busy and wait 2823 * for our request to complete. If it doesn't complete, note the 2824 * error and return it to our caller. Note that we do not reset the 2825 * VPD Busy status! 2826 */ 2827 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2828 adapter->vpd_busy = 1; 2829 adapter->vpd_flag = PCI_VPD_ADDR_F; 2830 ret = t4_seeprom_wait(adapter); 2831 if (ret) { 2832 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2833 return ret; 2834 } 2835 2836 /* 2837 * Grab the returned data, swizzle it into our endianness and 2838 * return success. 2839 */ 2840 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2841 *data = le32_to_cpu(*data); 2842 return 0; 2843 } 2844 2845 /** 2846 * t4_seeprom_write - write a serial EEPROM location 2847 * @adapter: adapter to write 2848 * @addr: virtual EEPROM address 2849 * @data: value to write 2850 * 2851 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2852 * VPD capability. Note that this function must be called with a virtual 2853 * address. 2854 */ 2855 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2856 { 2857 unsigned int base = adapter->params.pci.vpd_cap_addr; 2858 int ret; 2859 u32 stats_reg; 2860 int max_poll; 2861 2862 /* 2863 * VPD Accesses must alway be 4-byte aligned! 2864 */ 2865 if (addr >= EEPROMVSIZE || (addr & 3)) 2866 return -EINVAL; 2867 2868 /* 2869 * Wait for any previous operation which may still be in flight to 2870 * complete. 2871 */ 2872 ret = t4_seeprom_wait(adapter); 2873 if (ret) { 2874 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2875 return ret; 2876 } 2877 2878 /* 2879 * Issue our new VPD Read request, mark the VPD as being busy and wait 2880 * for our request to complete. If it doesn't complete, note the 2881 * error and return it to our caller. Note that we do not reset the 2882 * VPD Busy status! 2883 */ 2884 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2885 cpu_to_le32(data)); 2886 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2887 (u16)addr | PCI_VPD_ADDR_F); 2888 adapter->vpd_busy = 1; 2889 adapter->vpd_flag = 0; 2890 ret = t4_seeprom_wait(adapter); 2891 if (ret) { 2892 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2893 return ret; 2894 } 2895 2896 /* 2897 * Reset PCI_VPD_DATA register after a transaction and wait for our 2898 * request to complete. If it doesn't complete, return error. 2899 */ 2900 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2901 max_poll = EEPROM_MAX_POLL; 2902 do { 2903 udelay(EEPROM_DELAY); 2904 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2905 } while ((stats_reg & 0x1) && --max_poll); 2906 if (!max_poll) 2907 return -ETIMEDOUT; 2908 2909 /* Return success! */ 2910 return 0; 2911 } 2912 2913 /** 2914 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2915 * @phys_addr: the physical EEPROM address 2916 * @fn: the PCI function number 2917 * @sz: size of function-specific area 2918 * 2919 * Translate a physical EEPROM address to virtual. The first 1K is 2920 * accessed through virtual addresses starting at 31K, the rest is 2921 * accessed through virtual addresses starting at 0. 2922 * 2923 * The mapping is as follows: 2924 * [0..1K) -> [31K..32K) 2925 * [1K..1K+A) -> [ES-A..ES) 2926 * [1K+A..ES) -> [0..ES-A-1K) 2927 * 2928 * where A = @fn * @sz, and ES = EEPROM size. 2929 */ 2930 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2931 { 2932 fn *= sz; 2933 if (phys_addr < 1024) 2934 return phys_addr + (31 << 10); 2935 if (phys_addr < 1024 + fn) 2936 return EEPROMSIZE - fn + phys_addr - 1024; 2937 if (phys_addr < EEPROMSIZE) 2938 return phys_addr - 1024 - fn; 2939 return -EINVAL; 2940 } 2941 2942 /** 2943 * t4_seeprom_wp - enable/disable EEPROM write protection 2944 * @adapter: the adapter 2945 * @enable: whether to enable or disable write protection 2946 * 2947 * Enables or disables write protection on the serial EEPROM. 2948 */ 2949 int t4_seeprom_wp(struct adapter *adapter, int enable) 2950 { 2951 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2952 } 2953 2954 /** 2955 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2956 * @vpd: Pointer to buffered vpd data structure 2957 * @kw: The keyword to search for 2958 * @region: VPD region to search (starting from 0) 2959 * 2960 * Returns the value of the information field keyword or 2961 * -ENOENT otherwise. 2962 */ 2963 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2964 { 2965 int i, tag; 2966 unsigned int offset, len; 2967 const struct t4_vpdr_hdr *vpdr; 2968 2969 offset = sizeof(struct t4_vpd_hdr); 2970 vpdr = (const void *)(vpd + offset); 2971 tag = vpdr->vpdr_tag; 2972 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2973 while (region--) { 2974 offset += sizeof(struct t4_vpdr_hdr) + len; 2975 vpdr = (const void *)(vpd + offset); 2976 if (++tag != vpdr->vpdr_tag) 2977 return -ENOENT; 2978 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2979 } 2980 offset += sizeof(struct t4_vpdr_hdr); 2981 2982 if (offset + len > VPD_LEN) { 2983 return -ENOENT; 2984 } 2985 2986 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2987 if (memcmp(vpd + i , kw , 2) == 0){ 2988 i += VPD_INFO_FLD_HDR_SIZE; 2989 return i; 2990 } 2991 2992 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 2993 } 2994 2995 return -ENOENT; 2996 } 2997 2998 2999 /** 3000 * get_vpd_params - read VPD parameters from VPD EEPROM 3001 * @adapter: adapter to read 3002 * @p: where to store the parameters 3003 * @vpd: caller provided temporary space to read the VPD into 3004 * 3005 * Reads card parameters stored in VPD EEPROM. 3006 */ 3007 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3008 uint16_t device_id, u32 *buf) 3009 { 3010 int i, ret, addr; 3011 int ec, sn, pn, na, md; 3012 u8 csum; 3013 const u8 *vpd = (const u8 *)buf; 3014 3015 /* 3016 * Card information normally starts at VPD_BASE but early cards had 3017 * it at 0. 3018 */ 3019 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3020 if (ret) 3021 return (ret); 3022 3023 /* 3024 * The VPD shall have a unique identifier specified by the PCI SIG. 3025 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3026 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3027 * is expected to automatically put this entry at the 3028 * beginning of the VPD. 3029 */ 3030 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3031 3032 for (i = 0; i < VPD_LEN; i += 4) { 3033 ret = t4_seeprom_read(adapter, addr + i, buf++); 3034 if (ret) 3035 return ret; 3036 } 3037 3038 #define FIND_VPD_KW(var,name) do { \ 3039 var = get_vpd_keyword_val(vpd, name, 0); \ 3040 if (var < 0) { \ 3041 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3042 return -EINVAL; \ 3043 } \ 3044 } while (0) 3045 3046 FIND_VPD_KW(i, "RV"); 3047 for (csum = 0; i >= 0; i--) 3048 csum += vpd[i]; 3049 3050 if (csum) { 3051 CH_ERR(adapter, 3052 "corrupted VPD EEPROM, actual csum %u\n", csum); 3053 return -EINVAL; 3054 } 3055 3056 FIND_VPD_KW(ec, "EC"); 3057 FIND_VPD_KW(sn, "SN"); 3058 FIND_VPD_KW(pn, "PN"); 3059 FIND_VPD_KW(na, "NA"); 3060 #undef FIND_VPD_KW 3061 3062 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3063 strstrip(p->id); 3064 memcpy(p->ec, vpd + ec, EC_LEN); 3065 strstrip(p->ec); 3066 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3067 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3068 strstrip(p->sn); 3069 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3070 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3071 strstrip((char *)p->pn); 3072 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3073 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3074 strstrip((char *)p->na); 3075 3076 if (device_id & 0x80) 3077 return 0; /* Custom card */ 3078 3079 md = get_vpd_keyword_val(vpd, "VF", 1); 3080 if (md < 0) { 3081 snprintf(p->md, sizeof(p->md), "unknown"); 3082 } else { 3083 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3084 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3085 strstrip((char *)p->md); 3086 } 3087 3088 return 0; 3089 } 3090 3091 /* serial flash and firmware constants and flash config file constants */ 3092 enum { 3093 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3094 3095 /* flash command opcodes */ 3096 SF_PROG_PAGE = 2, /* program 256B page */ 3097 SF_WR_DISABLE = 4, /* disable writes */ 3098 SF_RD_STATUS = 5, /* read status register */ 3099 SF_WR_ENABLE = 6, /* enable writes */ 3100 SF_RD_DATA_FAST = 0xb, /* read flash */ 3101 SF_RD_ID = 0x9f, /* read ID */ 3102 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3103 }; 3104 3105 /** 3106 * sf1_read - read data from the serial flash 3107 * @adapter: the adapter 3108 * @byte_cnt: number of bytes to read 3109 * @cont: whether another operation will be chained 3110 * @lock: whether to lock SF for PL access only 3111 * @valp: where to store the read data 3112 * 3113 * Reads up to 4 bytes of data from the serial flash. The location of 3114 * the read needs to be specified prior to calling this by issuing the 3115 * appropriate commands to the serial flash. 3116 */ 3117 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3118 int lock, u32 *valp) 3119 { 3120 int ret; 3121 3122 if (!byte_cnt || byte_cnt > 4) 3123 return -EINVAL; 3124 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3125 return -EBUSY; 3126 t4_write_reg(adapter, A_SF_OP, 3127 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3128 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3129 if (!ret) 3130 *valp = t4_read_reg(adapter, A_SF_DATA); 3131 return ret; 3132 } 3133 3134 /** 3135 * sf1_write - write data to the serial flash 3136 * @adapter: the adapter 3137 * @byte_cnt: number of bytes to write 3138 * @cont: whether another operation will be chained 3139 * @lock: whether to lock SF for PL access only 3140 * @val: value to write 3141 * 3142 * Writes up to 4 bytes of data to the serial flash. The location of 3143 * the write needs to be specified prior to calling this by issuing the 3144 * appropriate commands to the serial flash. 3145 */ 3146 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3147 int lock, u32 val) 3148 { 3149 if (!byte_cnt || byte_cnt > 4) 3150 return -EINVAL; 3151 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3152 return -EBUSY; 3153 t4_write_reg(adapter, A_SF_DATA, val); 3154 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3155 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3156 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3157 } 3158 3159 /** 3160 * flash_wait_op - wait for a flash operation to complete 3161 * @adapter: the adapter 3162 * @attempts: max number of polls of the status register 3163 * @delay: delay between polls in ms 3164 * 3165 * Wait for a flash operation to complete by polling the status register. 3166 */ 3167 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3168 { 3169 int ret; 3170 u32 status; 3171 3172 while (1) { 3173 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3174 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3175 return ret; 3176 if (!(status & 1)) 3177 return 0; 3178 if (--attempts == 0) 3179 return -EAGAIN; 3180 if (delay) 3181 msleep(delay); 3182 } 3183 } 3184 3185 /** 3186 * t4_read_flash - read words from serial flash 3187 * @adapter: the adapter 3188 * @addr: the start address for the read 3189 * @nwords: how many 32-bit words to read 3190 * @data: where to store the read data 3191 * @byte_oriented: whether to store data as bytes or as words 3192 * 3193 * Read the specified number of 32-bit words from the serial flash. 3194 * If @byte_oriented is set the read data is stored as a byte array 3195 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3196 * natural endianness. 3197 */ 3198 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3199 unsigned int nwords, u32 *data, int byte_oriented) 3200 { 3201 int ret; 3202 3203 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3204 return -EINVAL; 3205 3206 addr = swab32(addr) | SF_RD_DATA_FAST; 3207 3208 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3209 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3210 return ret; 3211 3212 for ( ; nwords; nwords--, data++) { 3213 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3214 if (nwords == 1) 3215 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3216 if (ret) 3217 return ret; 3218 if (byte_oriented) 3219 *data = (__force __u32)(cpu_to_be32(*data)); 3220 } 3221 return 0; 3222 } 3223 3224 /** 3225 * t4_write_flash - write up to a page of data to the serial flash 3226 * @adapter: the adapter 3227 * @addr: the start address to write 3228 * @n: length of data to write in bytes 3229 * @data: the data to write 3230 * @byte_oriented: whether to store data as bytes or as words 3231 * 3232 * Writes up to a page of data (256 bytes) to the serial flash starting 3233 * at the given address. All the data must be written to the same page. 3234 * If @byte_oriented is set the write data is stored as byte stream 3235 * (i.e. matches what on disk), otherwise in big-endian. 3236 */ 3237 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3238 unsigned int n, const u8 *data, int byte_oriented) 3239 { 3240 int ret; 3241 u32 buf[SF_PAGE_SIZE / 4]; 3242 unsigned int i, c, left, val, offset = addr & 0xff; 3243 3244 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3245 return -EINVAL; 3246 3247 val = swab32(addr) | SF_PROG_PAGE; 3248 3249 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3250 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3251 goto unlock; 3252 3253 for (left = n; left; left -= c) { 3254 c = min(left, 4U); 3255 for (val = 0, i = 0; i < c; ++i) 3256 val = (val << 8) + *data++; 3257 3258 if (!byte_oriented) 3259 val = cpu_to_be32(val); 3260 3261 ret = sf1_write(adapter, c, c != left, 1, val); 3262 if (ret) 3263 goto unlock; 3264 } 3265 ret = flash_wait_op(adapter, 8, 1); 3266 if (ret) 3267 goto unlock; 3268 3269 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3270 3271 /* Read the page to verify the write succeeded */ 3272 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3273 byte_oriented); 3274 if (ret) 3275 return ret; 3276 3277 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3278 CH_ERR(adapter, 3279 "failed to correctly write the flash page at %#x\n", 3280 addr); 3281 return -EIO; 3282 } 3283 return 0; 3284 3285 unlock: 3286 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3287 return ret; 3288 } 3289 3290 /** 3291 * t4_get_fw_version - read the firmware version 3292 * @adapter: the adapter 3293 * @vers: where to place the version 3294 * 3295 * Reads the FW version from flash. 3296 */ 3297 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3298 { 3299 return t4_read_flash(adapter, FLASH_FW_START + 3300 offsetof(struct fw_hdr, fw_ver), 1, 3301 vers, 0); 3302 } 3303 3304 /** 3305 * t4_get_fw_hdr - read the firmware header 3306 * @adapter: the adapter 3307 * @hdr: where to place the version 3308 * 3309 * Reads the FW header from flash into caller provided buffer. 3310 */ 3311 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3312 { 3313 return t4_read_flash(adapter, FLASH_FW_START, 3314 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3315 } 3316 3317 /** 3318 * t4_get_bs_version - read the firmware bootstrap version 3319 * @adapter: the adapter 3320 * @vers: where to place the version 3321 * 3322 * Reads the FW Bootstrap version from flash. 3323 */ 3324 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3325 { 3326 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3327 offsetof(struct fw_hdr, fw_ver), 1, 3328 vers, 0); 3329 } 3330 3331 /** 3332 * t4_get_tp_version - read the TP microcode version 3333 * @adapter: the adapter 3334 * @vers: where to place the version 3335 * 3336 * Reads the TP microcode version from flash. 3337 */ 3338 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3339 { 3340 return t4_read_flash(adapter, FLASH_FW_START + 3341 offsetof(struct fw_hdr, tp_microcode_ver), 3342 1, vers, 0); 3343 } 3344 3345 /** 3346 * t4_get_exprom_version - return the Expansion ROM version (if any) 3347 * @adapter: the adapter 3348 * @vers: where to place the version 3349 * 3350 * Reads the Expansion ROM header from FLASH and returns the version 3351 * number (if present) through the @vers return value pointer. We return 3352 * this in the Firmware Version Format since it's convenient. Return 3353 * 0 on success, -ENOENT if no Expansion ROM is present. 3354 */ 3355 int t4_get_exprom_version(struct adapter *adapter, u32 *vers) 3356 { 3357 struct exprom_header { 3358 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3359 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3360 } *hdr; 3361 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3362 sizeof(u32))]; 3363 int ret; 3364 3365 ret = t4_read_flash(adapter, FLASH_EXP_ROM_START, 3366 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3367 0); 3368 if (ret) 3369 return ret; 3370 3371 hdr = (struct exprom_header *)exprom_header_buf; 3372 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3373 return -ENOENT; 3374 3375 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3376 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3377 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3378 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3379 return 0; 3380 } 3381 3382 /** 3383 * t4_get_scfg_version - return the Serial Configuration version 3384 * @adapter: the adapter 3385 * @vers: where to place the version 3386 * 3387 * Reads the Serial Configuration Version via the Firmware interface 3388 * (thus this can only be called once we're ready to issue Firmware 3389 * commands). The format of the Serial Configuration version is 3390 * adapter specific. Returns 0 on success, an error on failure. 3391 * 3392 * Note that early versions of the Firmware didn't include the ability 3393 * to retrieve the Serial Configuration version, so we zero-out the 3394 * return-value parameter in that case to avoid leaving it with 3395 * garbage in it. 3396 * 3397 * Also note that the Firmware will return its cached copy of the Serial 3398 * Initialization Revision ID, not the actual Revision ID as written in 3399 * the Serial EEPROM. This is only an issue if a new VPD has been written 3400 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3401 * it's best to defer calling this routine till after a FW_RESET_CMD has 3402 * been issued if the Host Driver will be performing a full adapter 3403 * initialization. 3404 */ 3405 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3406 { 3407 u32 scfgrev_param; 3408 int ret; 3409 3410 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3411 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3412 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3413 1, &scfgrev_param, vers); 3414 if (ret) 3415 *vers = 0; 3416 return ret; 3417 } 3418 3419 /** 3420 * t4_get_vpd_version - return the VPD version 3421 * @adapter: the adapter 3422 * @vers: where to place the version 3423 * 3424 * Reads the VPD via the Firmware interface (thus this can only be called 3425 * once we're ready to issue Firmware commands). The format of the 3426 * VPD version is adapter specific. Returns 0 on success, an error on 3427 * failure. 3428 * 3429 * Note that early versions of the Firmware didn't include the ability 3430 * to retrieve the VPD version, so we zero-out the return-value parameter 3431 * in that case to avoid leaving it with garbage in it. 3432 * 3433 * Also note that the Firmware will return its cached copy of the VPD 3434 * Revision ID, not the actual Revision ID as written in the Serial 3435 * EEPROM. This is only an issue if a new VPD has been written and the 3436 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3437 * to defer calling this routine till after a FW_RESET_CMD has been issued 3438 * if the Host Driver will be performing a full adapter initialization. 3439 */ 3440 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3441 { 3442 u32 vpdrev_param; 3443 int ret; 3444 3445 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3446 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3447 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3448 1, &vpdrev_param, vers); 3449 if (ret) 3450 *vers = 0; 3451 return ret; 3452 } 3453 3454 /** 3455 * t4_get_version_info - extract various chip/firmware version information 3456 * @adapter: the adapter 3457 * 3458 * Reads various chip/firmware version numbers and stores them into the 3459 * adapter Adapter Parameters structure. If any of the efforts fails 3460 * the first failure will be returned, but all of the version numbers 3461 * will be read. 3462 */ 3463 int t4_get_version_info(struct adapter *adapter) 3464 { 3465 int ret = 0; 3466 3467 #define FIRST_RET(__getvinfo) \ 3468 do { \ 3469 int __ret = __getvinfo; \ 3470 if (__ret && !ret) \ 3471 ret = __ret; \ 3472 } while (0) 3473 3474 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3475 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3476 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3477 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3478 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3479 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3480 3481 #undef FIRST_RET 3482 3483 return ret; 3484 } 3485 3486 /** 3487 * t4_flash_erase_sectors - erase a range of flash sectors 3488 * @adapter: the adapter 3489 * @start: the first sector to erase 3490 * @end: the last sector to erase 3491 * 3492 * Erases the sectors in the given inclusive range. 3493 */ 3494 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3495 { 3496 int ret = 0; 3497 3498 if (end >= adapter->params.sf_nsec) 3499 return -EINVAL; 3500 3501 while (start <= end) { 3502 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3503 (ret = sf1_write(adapter, 4, 0, 1, 3504 SF_ERASE_SECTOR | (start << 8))) != 0 || 3505 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3506 CH_ERR(adapter, 3507 "erase of flash sector %d failed, error %d\n", 3508 start, ret); 3509 break; 3510 } 3511 start++; 3512 } 3513 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3514 return ret; 3515 } 3516 3517 /** 3518 * t4_flash_cfg_addr - return the address of the flash configuration file 3519 * @adapter: the adapter 3520 * 3521 * Return the address within the flash where the Firmware Configuration 3522 * File is stored, or an error if the device FLASH is too small to contain 3523 * a Firmware Configuration File. 3524 */ 3525 int t4_flash_cfg_addr(struct adapter *adapter) 3526 { 3527 /* 3528 * If the device FLASH isn't large enough to hold a Firmware 3529 * Configuration File, return an error. 3530 */ 3531 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3532 return -ENOSPC; 3533 3534 return FLASH_CFG_START; 3535 } 3536 3537 /* 3538 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3539 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3540 * and emit an error message for mismatched firmware to save our caller the 3541 * effort ... 3542 */ 3543 static int t4_fw_matches_chip(struct adapter *adap, 3544 const struct fw_hdr *hdr) 3545 { 3546 /* 3547 * The expression below will return FALSE for any unsupported adapter 3548 * which will keep us "honest" in the future ... 3549 */ 3550 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3551 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3552 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3553 return 1; 3554 3555 CH_ERR(adap, 3556 "FW image (%d) is not suitable for this adapter (%d)\n", 3557 hdr->chip, chip_id(adap)); 3558 return 0; 3559 } 3560 3561 /** 3562 * t4_load_fw - download firmware 3563 * @adap: the adapter 3564 * @fw_data: the firmware image to write 3565 * @size: image size 3566 * 3567 * Write the supplied firmware image to the card's serial flash. 3568 */ 3569 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3570 { 3571 u32 csum; 3572 int ret, addr; 3573 unsigned int i; 3574 u8 first_page[SF_PAGE_SIZE]; 3575 const u32 *p = (const u32 *)fw_data; 3576 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3577 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3578 unsigned int fw_start_sec; 3579 unsigned int fw_start; 3580 unsigned int fw_size; 3581 3582 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3583 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3584 fw_start = FLASH_FWBOOTSTRAP_START; 3585 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3586 } else { 3587 fw_start_sec = FLASH_FW_START_SEC; 3588 fw_start = FLASH_FW_START; 3589 fw_size = FLASH_FW_MAX_SIZE; 3590 } 3591 3592 if (!size) { 3593 CH_ERR(adap, "FW image has no data\n"); 3594 return -EINVAL; 3595 } 3596 if (size & 511) { 3597 CH_ERR(adap, 3598 "FW image size not multiple of 512 bytes\n"); 3599 return -EINVAL; 3600 } 3601 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3602 CH_ERR(adap, 3603 "FW image size differs from size in FW header\n"); 3604 return -EINVAL; 3605 } 3606 if (size > fw_size) { 3607 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3608 fw_size); 3609 return -EFBIG; 3610 } 3611 if (!t4_fw_matches_chip(adap, hdr)) 3612 return -EINVAL; 3613 3614 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3615 csum += be32_to_cpu(p[i]); 3616 3617 if (csum != 0xffffffff) { 3618 CH_ERR(adap, 3619 "corrupted firmware image, checksum %#x\n", csum); 3620 return -EINVAL; 3621 } 3622 3623 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3624 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3625 if (ret) 3626 goto out; 3627 3628 /* 3629 * We write the correct version at the end so the driver can see a bad 3630 * version if the FW write fails. Start by writing a copy of the 3631 * first page with a bad version. 3632 */ 3633 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3634 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3635 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3636 if (ret) 3637 goto out; 3638 3639 addr = fw_start; 3640 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3641 addr += SF_PAGE_SIZE; 3642 fw_data += SF_PAGE_SIZE; 3643 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3644 if (ret) 3645 goto out; 3646 } 3647 3648 ret = t4_write_flash(adap, 3649 fw_start + offsetof(struct fw_hdr, fw_ver), 3650 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3651 out: 3652 if (ret) 3653 CH_ERR(adap, "firmware download failed, error %d\n", 3654 ret); 3655 return ret; 3656 } 3657 3658 /** 3659 * t4_fwcache - firmware cache operation 3660 * @adap: the adapter 3661 * @op : the operation (flush or flush and invalidate) 3662 */ 3663 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3664 { 3665 struct fw_params_cmd c; 3666 3667 memset(&c, 0, sizeof(c)); 3668 c.op_to_vfn = 3669 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3670 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3671 V_FW_PARAMS_CMD_PFN(adap->pf) | 3672 V_FW_PARAMS_CMD_VFN(0)); 3673 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3674 c.param[0].mnem = 3675 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3676 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3677 c.param[0].val = (__force __be32)op; 3678 3679 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3680 } 3681 3682 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3683 unsigned int *pif_req_wrptr, 3684 unsigned int *pif_rsp_wrptr) 3685 { 3686 int i, j; 3687 u32 cfg, val, req, rsp; 3688 3689 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3690 if (cfg & F_LADBGEN) 3691 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3692 3693 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3694 req = G_POLADBGWRPTR(val); 3695 rsp = G_PILADBGWRPTR(val); 3696 if (pif_req_wrptr) 3697 *pif_req_wrptr = req; 3698 if (pif_rsp_wrptr) 3699 *pif_rsp_wrptr = rsp; 3700 3701 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3702 for (j = 0; j < 6; j++) { 3703 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3704 V_PILADBGRDPTR(rsp)); 3705 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3706 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3707 req++; 3708 rsp++; 3709 } 3710 req = (req + 2) & M_POLADBGRDPTR; 3711 rsp = (rsp + 2) & M_PILADBGRDPTR; 3712 } 3713 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3714 } 3715 3716 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3717 { 3718 u32 cfg; 3719 int i, j, idx; 3720 3721 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3722 if (cfg & F_LADBGEN) 3723 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3724 3725 for (i = 0; i < CIM_MALA_SIZE; i++) { 3726 for (j = 0; j < 5; j++) { 3727 idx = 8 * i + j; 3728 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3729 V_PILADBGRDPTR(idx)); 3730 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3731 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3732 } 3733 } 3734 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3735 } 3736 3737 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3738 { 3739 unsigned int i, j; 3740 3741 for (i = 0; i < 8; i++) { 3742 u32 *p = la_buf + i; 3743 3744 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3745 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3746 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3747 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3748 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3749 } 3750 } 3751 3752 /** 3753 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3754 * @caps16: a 16-bit Port Capabilities value 3755 * 3756 * Returns the equivalent 32-bit Port Capabilities value. 3757 */ 3758 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3759 { 3760 uint32_t caps32 = 0; 3761 3762 #define CAP16_TO_CAP32(__cap) \ 3763 do { \ 3764 if (caps16 & FW_PORT_CAP_##__cap) \ 3765 caps32 |= FW_PORT_CAP32_##__cap; \ 3766 } while (0) 3767 3768 CAP16_TO_CAP32(SPEED_100M); 3769 CAP16_TO_CAP32(SPEED_1G); 3770 CAP16_TO_CAP32(SPEED_25G); 3771 CAP16_TO_CAP32(SPEED_10G); 3772 CAP16_TO_CAP32(SPEED_40G); 3773 CAP16_TO_CAP32(SPEED_100G); 3774 CAP16_TO_CAP32(FC_RX); 3775 CAP16_TO_CAP32(FC_TX); 3776 CAP16_TO_CAP32(ANEG); 3777 CAP16_TO_CAP32(FORCE_PAUSE); 3778 CAP16_TO_CAP32(MDIAUTO); 3779 CAP16_TO_CAP32(MDISTRAIGHT); 3780 CAP16_TO_CAP32(FEC_RS); 3781 CAP16_TO_CAP32(FEC_BASER_RS); 3782 CAP16_TO_CAP32(802_3_PAUSE); 3783 CAP16_TO_CAP32(802_3_ASM_DIR); 3784 3785 #undef CAP16_TO_CAP32 3786 3787 return caps32; 3788 } 3789 3790 /** 3791 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3792 * @caps32: a 32-bit Port Capabilities value 3793 * 3794 * Returns the equivalent 16-bit Port Capabilities value. Note that 3795 * not all 32-bit Port Capabilities can be represented in the 16-bit 3796 * Port Capabilities and some fields/values may not make it. 3797 */ 3798 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3799 { 3800 uint16_t caps16 = 0; 3801 3802 #define CAP32_TO_CAP16(__cap) \ 3803 do { \ 3804 if (caps32 & FW_PORT_CAP32_##__cap) \ 3805 caps16 |= FW_PORT_CAP_##__cap; \ 3806 } while (0) 3807 3808 CAP32_TO_CAP16(SPEED_100M); 3809 CAP32_TO_CAP16(SPEED_1G); 3810 CAP32_TO_CAP16(SPEED_10G); 3811 CAP32_TO_CAP16(SPEED_25G); 3812 CAP32_TO_CAP16(SPEED_40G); 3813 CAP32_TO_CAP16(SPEED_100G); 3814 CAP32_TO_CAP16(FC_RX); 3815 CAP32_TO_CAP16(FC_TX); 3816 CAP32_TO_CAP16(802_3_PAUSE); 3817 CAP32_TO_CAP16(802_3_ASM_DIR); 3818 CAP32_TO_CAP16(ANEG); 3819 CAP32_TO_CAP16(FORCE_PAUSE); 3820 CAP32_TO_CAP16(MDIAUTO); 3821 CAP32_TO_CAP16(MDISTRAIGHT); 3822 CAP32_TO_CAP16(FEC_RS); 3823 CAP32_TO_CAP16(FEC_BASER_RS); 3824 3825 #undef CAP32_TO_CAP16 3826 3827 return caps16; 3828 } 3829 3830 static int8_t fwcap_to_fec(uint32_t caps, bool unset_means_none) 3831 { 3832 int8_t fec = 0; 3833 3834 if ((caps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC)) == 0) 3835 return (unset_means_none ? FEC_NONE : 0); 3836 3837 if (caps & FW_PORT_CAP32_FEC_RS) 3838 fec |= FEC_RS; 3839 if (caps & FW_PORT_CAP32_FEC_BASER_RS) 3840 fec |= FEC_BASER_RS; 3841 if (caps & FW_PORT_CAP32_FEC_NO_FEC) 3842 fec |= FEC_NONE; 3843 3844 return (fec); 3845 } 3846 3847 /* 3848 * Note that 0 is not translated to NO_FEC. 3849 */ 3850 static uint32_t fec_to_fwcap(int8_t fec) 3851 { 3852 uint32_t caps = 0; 3853 3854 /* Only real FECs allowed. */ 3855 MPASS((fec & ~M_FW_PORT_CAP32_FEC) == 0); 3856 3857 if (fec & FEC_RS) 3858 caps |= FW_PORT_CAP32_FEC_RS; 3859 if (fec & FEC_BASER_RS) 3860 caps |= FW_PORT_CAP32_FEC_BASER_RS; 3861 if (fec & FEC_NONE) 3862 caps |= FW_PORT_CAP32_FEC_NO_FEC; 3863 3864 return (caps); 3865 } 3866 3867 /** 3868 * t4_link_l1cfg - apply link configuration to MAC/PHY 3869 * @phy: the PHY to setup 3870 * @mac: the MAC to setup 3871 * @lc: the requested link configuration 3872 * 3873 * Set up a port's MAC and PHY according to a desired link configuration. 3874 * - If the PHY can auto-negotiate first decide what to advertise, then 3875 * enable/disable auto-negotiation as desired, and reset. 3876 * - If the PHY does not auto-negotiate just reset it. 3877 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3878 * otherwise do it later based on the outcome of auto-negotiation. 3879 */ 3880 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3881 struct link_config *lc) 3882 { 3883 struct fw_port_cmd c; 3884 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3885 unsigned int aneg, fc, fec, speed, rcap; 3886 3887 fc = 0; 3888 if (lc->requested_fc & PAUSE_RX) 3889 fc |= FW_PORT_CAP32_FC_RX; 3890 if (lc->requested_fc & PAUSE_TX) 3891 fc |= FW_PORT_CAP32_FC_TX; 3892 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3893 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3894 3895 if (lc->requested_aneg == AUTONEG_DISABLE) 3896 aneg = 0; 3897 else if (lc->requested_aneg == AUTONEG_ENABLE) 3898 aneg = FW_PORT_CAP32_ANEG; 3899 else 3900 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3901 3902 if (aneg) { 3903 speed = lc->pcaps & 3904 V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3905 } else if (lc->requested_speed != 0) 3906 speed = speed_to_fwcap(lc->requested_speed); 3907 else 3908 speed = fwcap_top_speed(lc->pcaps); 3909 3910 fec = 0; 3911 #ifdef INVARIANTS 3912 if (lc->force_fec != 0) 3913 MPASS(lc->pcaps & FW_PORT_CAP32_FORCE_FEC); 3914 #endif 3915 if (fec_supported(speed)) { 3916 if (lc->requested_fec == FEC_AUTO) { 3917 if (lc->force_fec > 0) { 3918 /* 3919 * Must use FORCE_FEC even though requested FEC 3920 * is AUTO. Set all the FEC bits valid for the 3921 * speed and let the firmware pick one. 3922 */ 3923 fec |= FW_PORT_CAP32_FORCE_FEC; 3924 if (speed & FW_PORT_CAP32_SPEED_100G) { 3925 fec |= FW_PORT_CAP32_FEC_RS; 3926 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3927 } else if (speed & FW_PORT_CAP32_SPEED_50G) { 3928 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3929 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3930 } else { 3931 fec |= FW_PORT_CAP32_FEC_RS; 3932 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3933 fec |= FW_PORT_CAP32_FEC_NO_FEC; 3934 } 3935 } else { 3936 /* 3937 * Set only 1b. Old firmwares can't deal with 3938 * multiple bits and new firmwares are free to 3939 * ignore this and try whatever FECs they want 3940 * because we aren't setting FORCE_FEC here. 3941 */ 3942 fec |= fec_to_fwcap(lc->fec_hint); 3943 MPASS(powerof2(fec)); 3944 3945 /* 3946 * Override the hint if the FEC is not valid for 3947 * the potential top speed. Request the best 3948 * FEC at that speed instead. 3949 */ 3950 if (speed & FW_PORT_CAP32_SPEED_100G) { 3951 if (fec == FW_PORT_CAP32_FEC_BASER_RS) 3952 fec = FW_PORT_CAP32_FEC_RS; 3953 } else if (speed & FW_PORT_CAP32_SPEED_50G) { 3954 if (fec == FW_PORT_CAP32_FEC_RS) 3955 fec = FW_PORT_CAP32_FEC_BASER_RS; 3956 } 3957 } 3958 } else { 3959 /* 3960 * User has explicitly requested some FEC(s). Set 3961 * FORCE_FEC unless prohibited from using it. 3962 */ 3963 if (lc->force_fec != 0) 3964 fec |= FW_PORT_CAP32_FORCE_FEC; 3965 fec |= fec_to_fwcap(lc->requested_fec & 3966 M_FW_PORT_CAP32_FEC); 3967 if (lc->requested_fec & FEC_MODULE) 3968 fec |= fec_to_fwcap(lc->fec_hint); 3969 } 3970 3971 /* 3972 * This is for compatibility with old firmwares. The original 3973 * way to request NO_FEC was to not set any of the FEC bits. New 3974 * firmwares understand this too. 3975 */ 3976 if (fec == FW_PORT_CAP32_FEC_NO_FEC) 3977 fec = 0; 3978 } 3979 3980 /* Force AN on for BT cards. */ 3981 if (isset(&adap->bt_map, port)) 3982 aneg = lc->pcaps & FW_PORT_CAP32_ANEG; 3983 3984 rcap = aneg | speed | fc | fec; 3985 if ((rcap | lc->pcaps) != lc->pcaps) { 3986 #ifdef INVARIANTS 3987 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x, removed 0x%x\n", rcap, 3988 lc->pcaps, rcap & (rcap ^ lc->pcaps)); 3989 #endif 3990 rcap &= lc->pcaps; 3991 } 3992 rcap |= mdi; 3993 3994 memset(&c, 0, sizeof(c)); 3995 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3996 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3997 V_FW_PORT_CMD_PORTID(port)); 3998 if (adap->params.port_caps32) { 3999 c.action_to_len16 = 4000 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 4001 FW_LEN16(c)); 4002 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 4003 } else { 4004 c.action_to_len16 = 4005 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4006 FW_LEN16(c)); 4007 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 4008 } 4009 4010 lc->requested_caps = rcap; 4011 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 4012 } 4013 4014 /** 4015 * t4_restart_aneg - restart autonegotiation 4016 * @adap: the adapter 4017 * @mbox: mbox to use for the FW command 4018 * @port: the port id 4019 * 4020 * Restarts autonegotiation for the selected port. 4021 */ 4022 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 4023 { 4024 struct fw_port_cmd c; 4025 4026 memset(&c, 0, sizeof(c)); 4027 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 4028 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 4029 V_FW_PORT_CMD_PORTID(port)); 4030 c.action_to_len16 = 4031 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 4032 FW_LEN16(c)); 4033 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 4034 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 4035 } 4036 4037 struct intr_details { 4038 u32 mask; 4039 const char *msg; 4040 }; 4041 4042 struct intr_action { 4043 u32 mask; 4044 int arg; 4045 bool (*action)(struct adapter *, int, bool); 4046 }; 4047 4048 #define NONFATAL_IF_DISABLED 1 4049 struct intr_info { 4050 const char *name; /* name of the INT_CAUSE register */ 4051 int cause_reg; /* INT_CAUSE register */ 4052 int enable_reg; /* INT_ENABLE register */ 4053 u32 fatal; /* bits that are fatal */ 4054 int flags; /* hints */ 4055 const struct intr_details *details; 4056 const struct intr_action *actions; 4057 }; 4058 4059 static inline char 4060 intr_alert_char(u32 cause, u32 enable, u32 fatal) 4061 { 4062 4063 if (cause & fatal) 4064 return ('!'); 4065 if (cause & enable) 4066 return ('*'); 4067 return ('-'); 4068 } 4069 4070 static void 4071 t4_show_intr_info(struct adapter *adap, const struct intr_info *ii, u32 cause) 4072 { 4073 u32 enable, fatal, leftover; 4074 const struct intr_details *details; 4075 char alert; 4076 4077 enable = t4_read_reg(adap, ii->enable_reg); 4078 if (ii->flags & NONFATAL_IF_DISABLED) 4079 fatal = ii->fatal & t4_read_reg(adap, ii->enable_reg); 4080 else 4081 fatal = ii->fatal; 4082 alert = intr_alert_char(cause, enable, fatal); 4083 CH_ALERT(adap, "%c %s 0x%x = 0x%08x, E 0x%08x, F 0x%08x\n", 4084 alert, ii->name, ii->cause_reg, cause, enable, fatal); 4085 4086 leftover = cause; 4087 for (details = ii->details; details && details->mask != 0; details++) { 4088 u32 msgbits = details->mask & cause; 4089 if (msgbits == 0) 4090 continue; 4091 alert = intr_alert_char(msgbits, enable, ii->fatal); 4092 CH_ALERT(adap, " %c [0x%08x] %s\n", alert, msgbits, 4093 details->msg); 4094 leftover &= ~msgbits; 4095 } 4096 if (leftover != 0 && leftover != cause) 4097 CH_ALERT(adap, " ? [0x%08x]\n", leftover); 4098 } 4099 4100 /* 4101 * Returns true for fatal error. 4102 */ 4103 static bool 4104 t4_handle_intr(struct adapter *adap, const struct intr_info *ii, 4105 u32 additional_cause, bool verbose) 4106 { 4107 u32 cause, fatal; 4108 bool rc; 4109 const struct intr_action *action; 4110 4111 /* 4112 * Read and display cause. Note that the top level PL_INT_CAUSE is a 4113 * bit special and we need to completely ignore the bits that are not in 4114 * PL_INT_ENABLE. 4115 */ 4116 cause = t4_read_reg(adap, ii->cause_reg); 4117 if (ii->cause_reg == A_PL_INT_CAUSE) 4118 cause &= t4_read_reg(adap, ii->enable_reg); 4119 if (verbose || cause != 0) 4120 t4_show_intr_info(adap, ii, cause); 4121 fatal = cause & ii->fatal; 4122 if (fatal != 0 && ii->flags & NONFATAL_IF_DISABLED) 4123 fatal &= t4_read_reg(adap, ii->enable_reg); 4124 cause |= additional_cause; 4125 if (cause == 0) 4126 return (false); 4127 4128 rc = fatal != 0; 4129 for (action = ii->actions; action && action->mask != 0; action++) { 4130 if (!(action->mask & cause)) 4131 continue; 4132 rc |= (action->action)(adap, action->arg, verbose); 4133 } 4134 4135 /* clear */ 4136 t4_write_reg(adap, ii->cause_reg, cause); 4137 (void)t4_read_reg(adap, ii->cause_reg); 4138 4139 return (rc); 4140 } 4141 4142 /* 4143 * Interrupt handler for the PCIE module. 4144 */ 4145 static bool pcie_intr_handler(struct adapter *adap, int arg, bool verbose) 4146 { 4147 static const struct intr_details sysbus_intr_details[] = { 4148 { F_RNPP, "RXNP array parity error" }, 4149 { F_RPCP, "RXPC array parity error" }, 4150 { F_RCIP, "RXCIF array parity error" }, 4151 { F_RCCP, "Rx completions control array parity error" }, 4152 { F_RFTP, "RXFT array parity error" }, 4153 { 0 } 4154 }; 4155 static const struct intr_info sysbus_intr_info = { 4156 .name = "PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS", 4157 .cause_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4158 .enable_reg = A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE, 4159 .fatal = F_RFTP | F_RCCP | F_RCIP | F_RPCP | F_RNPP, 4160 .flags = 0, 4161 .details = sysbus_intr_details, 4162 .actions = NULL, 4163 }; 4164 static const struct intr_details pcie_port_intr_details[] = { 4165 { F_TPCP, "TXPC array parity error" }, 4166 { F_TNPP, "TXNP array parity error" }, 4167 { F_TFTP, "TXFT array parity error" }, 4168 { F_TCAP, "TXCA array parity error" }, 4169 { F_TCIP, "TXCIF array parity error" }, 4170 { F_RCAP, "RXCA array parity error" }, 4171 { F_OTDD, "outbound request TLP discarded" }, 4172 { F_RDPE, "Rx data parity error" }, 4173 { F_TDUE, "Tx uncorrectable data error" }, 4174 { 0 } 4175 }; 4176 static const struct intr_info pcie_port_intr_info = { 4177 .name = "PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS", 4178 .cause_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4179 .enable_reg = A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE, 4180 .fatal = F_TPCP | F_TNPP | F_TFTP | F_TCAP | F_TCIP | F_RCAP | 4181 F_OTDD | F_RDPE | F_TDUE, 4182 .flags = 0, 4183 .details = pcie_port_intr_details, 4184 .actions = NULL, 4185 }; 4186 static const struct intr_details pcie_intr_details[] = { 4187 { F_MSIADDRLPERR, "MSI AddrL parity error" }, 4188 { F_MSIADDRHPERR, "MSI AddrH parity error" }, 4189 { F_MSIDATAPERR, "MSI data parity error" }, 4190 { F_MSIXADDRLPERR, "MSI-X AddrL parity error" }, 4191 { F_MSIXADDRHPERR, "MSI-X AddrH parity error" }, 4192 { F_MSIXDATAPERR, "MSI-X data parity error" }, 4193 { F_MSIXDIPERR, "MSI-X DI parity error" }, 4194 { F_PIOCPLPERR, "PCIe PIO completion FIFO parity error" }, 4195 { F_PIOREQPERR, "PCIe PIO request FIFO parity error" }, 4196 { F_TARTAGPERR, "PCIe target tag FIFO parity error" }, 4197 { F_CCNTPERR, "PCIe CMD channel count parity error" }, 4198 { F_CREQPERR, "PCIe CMD channel request parity error" }, 4199 { F_CRSPPERR, "PCIe CMD channel response parity error" }, 4200 { F_DCNTPERR, "PCIe DMA channel count parity error" }, 4201 { F_DREQPERR, "PCIe DMA channel request parity error" }, 4202 { F_DRSPPERR, "PCIe DMA channel response parity error" }, 4203 { F_HCNTPERR, "PCIe HMA channel count parity error" }, 4204 { F_HREQPERR, "PCIe HMA channel request parity error" }, 4205 { F_HRSPPERR, "PCIe HMA channel response parity error" }, 4206 { F_CFGSNPPERR, "PCIe config snoop FIFO parity error" }, 4207 { F_FIDPERR, "PCIe FID parity error" }, 4208 { F_INTXCLRPERR, "PCIe INTx clear parity error" }, 4209 { F_MATAGPERR, "PCIe MA tag parity error" }, 4210 { F_PIOTAGPERR, "PCIe PIO tag parity error" }, 4211 { F_RXCPLPERR, "PCIe Rx completion parity error" }, 4212 { F_RXWRPERR, "PCIe Rx write parity error" }, 4213 { F_RPLPERR, "PCIe replay buffer parity error" }, 4214 { F_PCIESINT, "PCIe core secondary fault" }, 4215 { F_PCIEPINT, "PCIe core primary fault" }, 4216 { F_UNXSPLCPLERR, "PCIe unexpected split completion error" }, 4217 { 0 } 4218 }; 4219 static const struct intr_details t5_pcie_intr_details[] = { 4220 { F_IPGRPPERR, "Parity errors observed by IP" }, 4221 { F_NONFATALERR, "PCIe non-fatal error" }, 4222 { F_READRSPERR, "Outbound read error" }, 4223 { F_TRGT1GRPPERR, "PCIe TRGT1 group FIFOs parity error" }, 4224 { F_IPSOTPERR, "PCIe IP SOT buffer SRAM parity error" }, 4225 { F_IPRETRYPERR, "PCIe IP replay buffer parity error" }, 4226 { F_IPRXDATAGRPPERR, "PCIe IP Rx data group SRAMs parity error" }, 4227 { F_IPRXHDRGRPPERR, "PCIe IP Rx header group SRAMs parity error" }, 4228 { F_PIOTAGQPERR, "PIO tag queue FIFO parity error" }, 4229 { F_MAGRPPERR, "MA group FIFO parity error" }, 4230 { F_VFIDPERR, "VFID SRAM parity error" }, 4231 { F_FIDPERR, "FID SRAM parity error" }, 4232 { F_CFGSNPPERR, "config snoop FIFO parity error" }, 4233 { F_HRSPPERR, "HMA channel response data SRAM parity error" }, 4234 { F_HREQRDPERR, "HMA channel read request SRAM parity error" }, 4235 { F_HREQWRPERR, "HMA channel write request SRAM parity error" }, 4236 { F_DRSPPERR, "DMA channel response data SRAM parity error" }, 4237 { F_DREQRDPERR, "DMA channel write request SRAM parity error" }, 4238 { F_CRSPPERR, "CMD channel response data SRAM parity error" }, 4239 { F_CREQRDPERR, "CMD channel read request SRAM parity error" }, 4240 { F_MSTTAGQPERR, "PCIe master tag queue SRAM parity error" }, 4241 { F_TGTTAGQPERR, "PCIe target tag queue FIFO parity error" }, 4242 { F_PIOREQGRPPERR, "PIO request group FIFOs parity error" }, 4243 { F_PIOCPLGRPPERR, "PIO completion group FIFOs parity error" }, 4244 { F_MSIXDIPERR, "MSI-X DI SRAM parity error" }, 4245 { F_MSIXDATAPERR, "MSI-X data SRAM parity error" }, 4246 { F_MSIXADDRHPERR, "MSI-X AddrH SRAM parity error" }, 4247 { F_MSIXADDRLPERR, "MSI-X AddrL SRAM parity error" }, 4248 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error" }, 4249 { F_MSTTIMEOUTPERR, "Master timeout FIFO parity error" }, 4250 { F_MSTGRPPERR, "Master response read queue SRAM parity error" }, 4251 { 0 } 4252 }; 4253 struct intr_info pcie_intr_info = { 4254 .name = "PCIE_INT_CAUSE", 4255 .cause_reg = A_PCIE_INT_CAUSE, 4256 .enable_reg = A_PCIE_INT_ENABLE, 4257 .fatal = 0xffffffff, 4258 .flags = NONFATAL_IF_DISABLED, 4259 .details = NULL, 4260 .actions = NULL, 4261 }; 4262 bool fatal = false; 4263 4264 if (is_t4(adap)) { 4265 fatal |= t4_handle_intr(adap, &sysbus_intr_info, 0, verbose); 4266 fatal |= t4_handle_intr(adap, &pcie_port_intr_info, 0, verbose); 4267 4268 pcie_intr_info.details = pcie_intr_details; 4269 } else { 4270 pcie_intr_info.details = t5_pcie_intr_details; 4271 } 4272 fatal |= t4_handle_intr(adap, &pcie_intr_info, 0, verbose); 4273 4274 return (fatal); 4275 } 4276 4277 /* 4278 * TP interrupt handler. 4279 */ 4280 static bool tp_intr_handler(struct adapter *adap, int arg, bool verbose) 4281 { 4282 static const struct intr_details tp_intr_details[] = { 4283 { 0x3fffffff, "TP parity error" }, 4284 { F_FLMTXFLSTEMPTY, "TP out of Tx pages" }, 4285 { 0 } 4286 }; 4287 static const struct intr_info tp_intr_info = { 4288 .name = "TP_INT_CAUSE", 4289 .cause_reg = A_TP_INT_CAUSE, 4290 .enable_reg = A_TP_INT_ENABLE, 4291 .fatal = 0x7fffffff, 4292 .flags = NONFATAL_IF_DISABLED, 4293 .details = tp_intr_details, 4294 .actions = NULL, 4295 }; 4296 4297 return (t4_handle_intr(adap, &tp_intr_info, 0, verbose)); 4298 } 4299 4300 /* 4301 * SGE interrupt handler. 4302 */ 4303 static bool sge_intr_handler(struct adapter *adap, int arg, bool verbose) 4304 { 4305 static const struct intr_info sge_int1_info = { 4306 .name = "SGE_INT_CAUSE1", 4307 .cause_reg = A_SGE_INT_CAUSE1, 4308 .enable_reg = A_SGE_INT_ENABLE1, 4309 .fatal = 0xffffffff, 4310 .flags = NONFATAL_IF_DISABLED, 4311 .details = NULL, 4312 .actions = NULL, 4313 }; 4314 static const struct intr_info sge_int2_info = { 4315 .name = "SGE_INT_CAUSE2", 4316 .cause_reg = A_SGE_INT_CAUSE2, 4317 .enable_reg = A_SGE_INT_ENABLE2, 4318 .fatal = 0xffffffff, 4319 .flags = NONFATAL_IF_DISABLED, 4320 .details = NULL, 4321 .actions = NULL, 4322 }; 4323 static const struct intr_details sge_int3_details[] = { 4324 { F_ERR_FLM_DBP, 4325 "DBP pointer delivery for invalid context or QID" }, 4326 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4327 "Invalid QID or header request by IDMA" }, 4328 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4329 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4330 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4331 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4332 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4333 { F_ERR_TIMER_ABOVE_MAX_QID, 4334 "SGE GTS with timer 0-5 for IQID > 1023" }, 4335 { F_ERR_CPL_EXCEED_IQE_SIZE, 4336 "SGE received CPL exceeding IQE size" }, 4337 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4338 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4339 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4340 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4341 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4342 "SGE IQID > 1023 received CPL for FL" }, 4343 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4344 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4345 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4346 { F_ERR_ING_CTXT_PRIO, 4347 "Ingress context manager priority user error" }, 4348 { F_ERR_EGR_CTXT_PRIO, 4349 "Egress context manager priority user error" }, 4350 { F_DBFIFO_HP_INT, "High priority DB FIFO threshold reached" }, 4351 { F_DBFIFO_LP_INT, "Low priority DB FIFO threshold reached" }, 4352 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4353 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4354 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4355 { 0x0000000f, "SGE context access for invalid queue" }, 4356 { 0 } 4357 }; 4358 static const struct intr_details t6_sge_int3_details[] = { 4359 { F_ERR_FLM_DBP, 4360 "DBP pointer delivery for invalid context or QID" }, 4361 { F_ERR_FLM_IDMA1 | F_ERR_FLM_IDMA0, 4362 "Invalid QID or header request by IDMA" }, 4363 { F_ERR_FLM_HINT, "FLM hint is for invalid context or QID" }, 4364 { F_ERR_PCIE_ERROR3, "SGE PCIe error for DBP thread 3" }, 4365 { F_ERR_PCIE_ERROR2, "SGE PCIe error for DBP thread 2" }, 4366 { F_ERR_PCIE_ERROR1, "SGE PCIe error for DBP thread 1" }, 4367 { F_ERR_PCIE_ERROR0, "SGE PCIe error for DBP thread 0" }, 4368 { F_ERR_TIMER_ABOVE_MAX_QID, 4369 "SGE GTS with timer 0-5 for IQID > 1023" }, 4370 { F_ERR_CPL_EXCEED_IQE_SIZE, 4371 "SGE received CPL exceeding IQE size" }, 4372 { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large" }, 4373 { F_ERR_ITP_TIME_PAUSED, "SGE ITP error" }, 4374 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL" }, 4375 { F_ERR_DROPPED_DB, "SGE DB dropped" }, 4376 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4377 "SGE IQID > 1023 received CPL for FL" }, 4378 { F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4379 F_ERR_BAD_DB_PIDX0, "SGE DBP pidx increment too large" }, 4380 { F_ERR_ING_PCIE_CHAN, "SGE Ingress PCIe channel mismatch" }, 4381 { F_ERR_ING_CTXT_PRIO, 4382 "Ingress context manager priority user error" }, 4383 { F_ERR_EGR_CTXT_PRIO, 4384 "Egress context manager priority user error" }, 4385 { F_DBP_TBUF_FULL, "SGE DBP tbuf full" }, 4386 { F_FATAL_WRE_LEN, 4387 "SGE WRE packet less than advertized length" }, 4388 { F_REG_ADDRESS_ERR, "Undefined SGE register accessed" }, 4389 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID" }, 4390 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID" }, 4391 { 0x0000000f, "SGE context access for invalid queue" }, 4392 { 0 } 4393 }; 4394 struct intr_info sge_int3_info = { 4395 .name = "SGE_INT_CAUSE3", 4396 .cause_reg = A_SGE_INT_CAUSE3, 4397 .enable_reg = A_SGE_INT_ENABLE3, 4398 .fatal = F_ERR_CPL_EXCEED_IQE_SIZE, 4399 .flags = 0, 4400 .details = NULL, 4401 .actions = NULL, 4402 }; 4403 static const struct intr_info sge_int4_info = { 4404 .name = "SGE_INT_CAUSE4", 4405 .cause_reg = A_SGE_INT_CAUSE4, 4406 .enable_reg = A_SGE_INT_ENABLE4, 4407 .fatal = 0, 4408 .flags = 0, 4409 .details = NULL, 4410 .actions = NULL, 4411 }; 4412 static const struct intr_info sge_int5_info = { 4413 .name = "SGE_INT_CAUSE5", 4414 .cause_reg = A_SGE_INT_CAUSE5, 4415 .enable_reg = A_SGE_INT_ENABLE5, 4416 .fatal = 0xffffffff, 4417 .flags = NONFATAL_IF_DISABLED, 4418 .details = NULL, 4419 .actions = NULL, 4420 }; 4421 static const struct intr_info sge_int6_info = { 4422 .name = "SGE_INT_CAUSE6", 4423 .cause_reg = A_SGE_INT_CAUSE6, 4424 .enable_reg = A_SGE_INT_ENABLE6, 4425 .fatal = 0, 4426 .flags = 0, 4427 .details = NULL, 4428 .actions = NULL, 4429 }; 4430 4431 bool fatal; 4432 u32 v; 4433 4434 if (chip_id(adap) <= CHELSIO_T5) { 4435 sge_int3_info.details = sge_int3_details; 4436 } else { 4437 sge_int3_info.details = t6_sge_int3_details; 4438 } 4439 4440 fatal = false; 4441 fatal |= t4_handle_intr(adap, &sge_int1_info, 0, verbose); 4442 fatal |= t4_handle_intr(adap, &sge_int2_info, 0, verbose); 4443 fatal |= t4_handle_intr(adap, &sge_int3_info, 0, verbose); 4444 fatal |= t4_handle_intr(adap, &sge_int4_info, 0, verbose); 4445 if (chip_id(adap) >= CHELSIO_T5) 4446 fatal |= t4_handle_intr(adap, &sge_int5_info, 0, verbose); 4447 if (chip_id(adap) >= CHELSIO_T6) 4448 fatal |= t4_handle_intr(adap, &sge_int6_info, 0, verbose); 4449 4450 v = t4_read_reg(adap, A_SGE_ERROR_STATS); 4451 if (v & F_ERROR_QID_VALID) { 4452 CH_ERR(adap, "SGE error for QID %u\n", G_ERROR_QID(v)); 4453 if (v & F_UNCAPTURED_ERROR) 4454 CH_ERR(adap, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4455 t4_write_reg(adap, A_SGE_ERROR_STATS, 4456 F_ERROR_QID_VALID | F_UNCAPTURED_ERROR); 4457 } 4458 4459 return (fatal); 4460 } 4461 4462 /* 4463 * CIM interrupt handler. 4464 */ 4465 static bool cim_intr_handler(struct adapter *adap, int arg, bool verbose) 4466 { 4467 static const struct intr_action cim_host_intr_actions[] = { 4468 { F_TIMER0INT, 0, t4_os_dump_cimla }, 4469 { 0 }, 4470 }; 4471 static const struct intr_details cim_host_intr_details[] = { 4472 /* T6+ */ 4473 { F_PCIE2CIMINTFPARERR, "CIM IBQ PCIe interface parity error" }, 4474 4475 /* T5+ */ 4476 { F_MA_CIM_INTFPERR, "MA2CIM interface parity error" }, 4477 { F_PLCIM_MSTRSPDATAPARERR, 4478 "PL2CIM master response data parity error" }, 4479 { F_NCSI2CIMINTFPARERR, "CIM IBQ NC-SI interface parity error" }, 4480 { F_SGE2CIMINTFPARERR, "CIM IBQ SGE interface parity error" }, 4481 { F_ULP2CIMINTFPARERR, "CIM IBQ ULP_TX interface parity error" }, 4482 { F_TP2CIMINTFPARERR, "CIM IBQ TP interface parity error" }, 4483 { F_OBQSGERX1PARERR, "CIM OBQ SGE1_RX parity error" }, 4484 { F_OBQSGERX0PARERR, "CIM OBQ SGE0_RX parity error" }, 4485 4486 /* T4+ */ 4487 { F_TIEQOUTPARERRINT, "CIM TIEQ outgoing FIFO parity error" }, 4488 { F_TIEQINPARERRINT, "CIM TIEQ incoming FIFO parity error" }, 4489 { F_MBHOSTPARERR, "CIM mailbox host read parity error" }, 4490 { F_MBUPPARERR, "CIM mailbox uP parity error" }, 4491 { F_IBQTP0PARERR, "CIM IBQ TP0 parity error" }, 4492 { F_IBQTP1PARERR, "CIM IBQ TP1 parity error" }, 4493 { F_IBQULPPARERR, "CIM IBQ ULP parity error" }, 4494 { F_IBQSGELOPARERR, "CIM IBQ SGE_LO parity error" }, 4495 { F_IBQSGEHIPARERR | F_IBQPCIEPARERR, /* same bit */ 4496 "CIM IBQ PCIe/SGE_HI parity error" }, 4497 { F_IBQNCSIPARERR, "CIM IBQ NC-SI parity error" }, 4498 { F_OBQULP0PARERR, "CIM OBQ ULP0 parity error" }, 4499 { F_OBQULP1PARERR, "CIM OBQ ULP1 parity error" }, 4500 { F_OBQULP2PARERR, "CIM OBQ ULP2 parity error" }, 4501 { F_OBQULP3PARERR, "CIM OBQ ULP3 parity error" }, 4502 { F_OBQSGEPARERR, "CIM OBQ SGE parity error" }, 4503 { F_OBQNCSIPARERR, "CIM OBQ NC-SI parity error" }, 4504 { F_TIMER1INT, "CIM TIMER0 interrupt" }, 4505 { F_TIMER0INT, "CIM TIMER0 interrupt" }, 4506 { F_PREFDROPINT, "CIM control register prefetch drop" }, 4507 { 0} 4508 }; 4509 static const struct intr_info cim_host_intr_info = { 4510 .name = "CIM_HOST_INT_CAUSE", 4511 .cause_reg = A_CIM_HOST_INT_CAUSE, 4512 .enable_reg = A_CIM_HOST_INT_ENABLE, 4513 .fatal = 0x007fffe6, 4514 .flags = NONFATAL_IF_DISABLED, 4515 .details = cim_host_intr_details, 4516 .actions = cim_host_intr_actions, 4517 }; 4518 static const struct intr_details cim_host_upacc_intr_details[] = { 4519 { F_EEPROMWRINT, "CIM EEPROM came out of busy state" }, 4520 { F_TIMEOUTMAINT, "CIM PIF MA timeout" }, 4521 { F_TIMEOUTINT, "CIM PIF timeout" }, 4522 { F_RSPOVRLOOKUPINT, "CIM response FIFO overwrite" }, 4523 { F_REQOVRLOOKUPINT, "CIM request FIFO overwrite" }, 4524 { F_BLKWRPLINT, "CIM block write to PL space" }, 4525 { F_BLKRDPLINT, "CIM block read from PL space" }, 4526 { F_SGLWRPLINT, 4527 "CIM single write to PL space with illegal BEs" }, 4528 { F_SGLRDPLINT, 4529 "CIM single read from PL space with illegal BEs" }, 4530 { F_BLKWRCTLINT, "CIM block write to CTL space" }, 4531 { F_BLKRDCTLINT, "CIM block read from CTL space" }, 4532 { F_SGLWRCTLINT, 4533 "CIM single write to CTL space with illegal BEs" }, 4534 { F_SGLRDCTLINT, 4535 "CIM single read from CTL space with illegal BEs" }, 4536 { F_BLKWREEPROMINT, "CIM block write to EEPROM space" }, 4537 { F_BLKRDEEPROMINT, "CIM block read from EEPROM space" }, 4538 { F_SGLWREEPROMINT, 4539 "CIM single write to EEPROM space with illegal BEs" }, 4540 { F_SGLRDEEPROMINT, 4541 "CIM single read from EEPROM space with illegal BEs" }, 4542 { F_BLKWRFLASHINT, "CIM block write to flash space" }, 4543 { F_BLKRDFLASHINT, "CIM block read from flash space" }, 4544 { F_SGLWRFLASHINT, "CIM single write to flash space" }, 4545 { F_SGLRDFLASHINT, 4546 "CIM single read from flash space with illegal BEs" }, 4547 { F_BLKWRBOOTINT, "CIM block write to boot space" }, 4548 { F_BLKRDBOOTINT, "CIM block read from boot space" }, 4549 { F_SGLWRBOOTINT, "CIM single write to boot space" }, 4550 { F_SGLRDBOOTINT, 4551 "CIM single read from boot space with illegal BEs" }, 4552 { F_ILLWRBEINT, "CIM illegal write BEs" }, 4553 { F_ILLRDBEINT, "CIM illegal read BEs" }, 4554 { F_ILLRDINT, "CIM illegal read" }, 4555 { F_ILLWRINT, "CIM illegal write" }, 4556 { F_ILLTRANSINT, "CIM illegal transaction" }, 4557 { F_RSVDSPACEINT, "CIM reserved space access" }, 4558 {0} 4559 }; 4560 static const struct intr_info cim_host_upacc_intr_info = { 4561 .name = "CIM_HOST_UPACC_INT_CAUSE", 4562 .cause_reg = A_CIM_HOST_UPACC_INT_CAUSE, 4563 .enable_reg = A_CIM_HOST_UPACC_INT_ENABLE, 4564 .fatal = 0x3fffeeff, 4565 .flags = NONFATAL_IF_DISABLED, 4566 .details = cim_host_upacc_intr_details, 4567 .actions = NULL, 4568 }; 4569 static const struct intr_info cim_pf_host_intr_info = { 4570 .name = "CIM_PF_HOST_INT_CAUSE", 4571 .cause_reg = MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4572 .enable_reg = MYPF_REG(A_CIM_PF_HOST_INT_ENABLE), 4573 .fatal = 0, 4574 .flags = 0, 4575 .details = NULL, 4576 .actions = NULL, 4577 }; 4578 u32 val, fw_err; 4579 bool fatal; 4580 4581 fw_err = t4_read_reg(adap, A_PCIE_FW); 4582 if (fw_err & F_PCIE_FW_ERR) 4583 t4_report_fw_error(adap); 4584 4585 /* 4586 * When the Firmware detects an internal error which normally wouldn't 4587 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4588 * to make sure the Host sees the Firmware Crash. So if we have a 4589 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4590 * interrupt. 4591 */ 4592 val = t4_read_reg(adap, A_CIM_HOST_INT_CAUSE); 4593 if (val & F_TIMER0INT && (!(fw_err & F_PCIE_FW_ERR) || 4594 G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) { 4595 t4_write_reg(adap, A_CIM_HOST_INT_CAUSE, F_TIMER0INT); 4596 } 4597 4598 fatal = false; 4599 fatal |= t4_handle_intr(adap, &cim_host_intr_info, 0, verbose); 4600 fatal |= t4_handle_intr(adap, &cim_host_upacc_intr_info, 0, verbose); 4601 fatal |= t4_handle_intr(adap, &cim_pf_host_intr_info, 0, verbose); 4602 4603 return (fatal); 4604 } 4605 4606 /* 4607 * ULP RX interrupt handler. 4608 */ 4609 static bool ulprx_intr_handler(struct adapter *adap, int arg, bool verbose) 4610 { 4611 static const struct intr_details ulprx_intr_details[] = { 4612 /* T5+ */ 4613 { F_SE_CNT_MISMATCH_1, "ULPRX SE count mismatch in channel 1" }, 4614 { F_SE_CNT_MISMATCH_0, "ULPRX SE count mismatch in channel 0" }, 4615 4616 /* T4+ */ 4617 { F_CAUSE_CTX_1, "ULPRX channel 1 context error" }, 4618 { F_CAUSE_CTX_0, "ULPRX channel 0 context error" }, 4619 { 0x007fffff, "ULPRX parity error" }, 4620 { 0 } 4621 }; 4622 static const struct intr_info ulprx_intr_info = { 4623 .name = "ULP_RX_INT_CAUSE", 4624 .cause_reg = A_ULP_RX_INT_CAUSE, 4625 .enable_reg = A_ULP_RX_INT_ENABLE, 4626 .fatal = 0x07ffffff, 4627 .flags = NONFATAL_IF_DISABLED, 4628 .details = ulprx_intr_details, 4629 .actions = NULL, 4630 }; 4631 static const struct intr_info ulprx_intr2_info = { 4632 .name = "ULP_RX_INT_CAUSE_2", 4633 .cause_reg = A_ULP_RX_INT_CAUSE_2, 4634 .enable_reg = A_ULP_RX_INT_ENABLE_2, 4635 .fatal = 0, 4636 .flags = 0, 4637 .details = NULL, 4638 .actions = NULL, 4639 }; 4640 bool fatal = false; 4641 4642 fatal |= t4_handle_intr(adap, &ulprx_intr_info, 0, verbose); 4643 fatal |= t4_handle_intr(adap, &ulprx_intr2_info, 0, verbose); 4644 4645 return (fatal); 4646 } 4647 4648 /* 4649 * ULP TX interrupt handler. 4650 */ 4651 static bool ulptx_intr_handler(struct adapter *adap, int arg, bool verbose) 4652 { 4653 static const struct intr_details ulptx_intr_details[] = { 4654 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds" }, 4655 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds" }, 4656 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds" }, 4657 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds" }, 4658 { 0x0fffffff, "ULPTX parity error" }, 4659 { 0 } 4660 }; 4661 static const struct intr_info ulptx_intr_info = { 4662 .name = "ULP_TX_INT_CAUSE", 4663 .cause_reg = A_ULP_TX_INT_CAUSE, 4664 .enable_reg = A_ULP_TX_INT_ENABLE, 4665 .fatal = 0x0fffffff, 4666 .flags = NONFATAL_IF_DISABLED, 4667 .details = ulptx_intr_details, 4668 .actions = NULL, 4669 }; 4670 static const struct intr_info ulptx_intr2_info = { 4671 .name = "ULP_TX_INT_CAUSE_2", 4672 .cause_reg = A_ULP_TX_INT_CAUSE_2, 4673 .enable_reg = A_ULP_TX_INT_ENABLE_2, 4674 .fatal = 0xf0, 4675 .flags = NONFATAL_IF_DISABLED, 4676 .details = NULL, 4677 .actions = NULL, 4678 }; 4679 bool fatal = false; 4680 4681 fatal |= t4_handle_intr(adap, &ulptx_intr_info, 0, verbose); 4682 fatal |= t4_handle_intr(adap, &ulptx_intr2_info, 0, verbose); 4683 4684 return (fatal); 4685 } 4686 4687 static bool pmtx_dump_dbg_stats(struct adapter *adap, int arg, bool verbose) 4688 { 4689 int i; 4690 u32 data[17]; 4691 4692 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, A_PM_TX_DBG_DATA, &data[0], 4693 ARRAY_SIZE(data), A_PM_TX_DBG_STAT0); 4694 for (i = 0; i < ARRAY_SIZE(data); i++) { 4695 CH_ALERT(adap, " - PM_TX_DBG_STAT%u (0x%x) = 0x%08x\n", i, 4696 A_PM_TX_DBG_STAT0 + i, data[i]); 4697 } 4698 4699 return (false); 4700 } 4701 4702 /* 4703 * PM TX interrupt handler. 4704 */ 4705 static bool pmtx_intr_handler(struct adapter *adap, int arg, bool verbose) 4706 { 4707 static const struct intr_action pmtx_intr_actions[] = { 4708 { 0xffffffff, 0, pmtx_dump_dbg_stats }, 4709 { 0 }, 4710 }; 4711 static const struct intr_details pmtx_intr_details[] = { 4712 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large" }, 4713 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large" }, 4714 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large" }, 4715 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd" }, 4716 { 0x0f000000, "PMTX icspi FIFO2X Rx framing error" }, 4717 { 0x00f00000, "PMTX icspi FIFO Rx framing error" }, 4718 { 0x000f0000, "PMTX icspi FIFO Tx framing error" }, 4719 { 0x0000f000, "PMTX oespi FIFO Rx framing error" }, 4720 { 0x00000f00, "PMTX oespi FIFO Tx framing error" }, 4721 { 0x000000f0, "PMTX oespi FIFO2X Tx framing error" }, 4722 { F_OESPI_PAR_ERROR, "PMTX oespi parity error" }, 4723 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error" }, 4724 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error" }, 4725 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error" }, 4726 { 0 } 4727 }; 4728 static const struct intr_info pmtx_intr_info = { 4729 .name = "PM_TX_INT_CAUSE", 4730 .cause_reg = A_PM_TX_INT_CAUSE, 4731 .enable_reg = A_PM_TX_INT_ENABLE, 4732 .fatal = 0xffffffff, 4733 .flags = 0, 4734 .details = pmtx_intr_details, 4735 .actions = pmtx_intr_actions, 4736 }; 4737 4738 return (t4_handle_intr(adap, &pmtx_intr_info, 0, verbose)); 4739 } 4740 4741 /* 4742 * PM RX interrupt handler. 4743 */ 4744 static bool pmrx_intr_handler(struct adapter *adap, int arg, bool verbose) 4745 { 4746 static const struct intr_details pmrx_intr_details[] = { 4747 /* T6+ */ 4748 { 0x18000000, "PMRX ospi overflow" }, 4749 { F_MA_INTF_SDC_ERR, "PMRX MA interface SDC parity error" }, 4750 { F_BUNDLE_LEN_PARERR, "PMRX bundle len FIFO parity error" }, 4751 { F_BUNDLE_LEN_OVFL, "PMRX bundle len FIFO overflow" }, 4752 { F_SDC_ERR, "PMRX SDC error" }, 4753 4754 /* T4+ */ 4755 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd" }, 4756 { 0x003c0000, "PMRX iespi FIFO2X Rx framing error" }, 4757 { 0x0003c000, "PMRX iespi Rx framing error" }, 4758 { 0x00003c00, "PMRX iespi Tx framing error" }, 4759 { 0x00000300, "PMRX ocspi Rx framing error" }, 4760 { 0x000000c0, "PMRX ocspi Tx framing error" }, 4761 { 0x00000030, "PMRX ocspi FIFO2X Tx framing error" }, 4762 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error" }, 4763 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error" }, 4764 { F_IESPI_PAR_ERROR, "PMRX iespi parity error" }, 4765 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error"}, 4766 { 0 } 4767 }; 4768 static const struct intr_info pmrx_intr_info = { 4769 .name = "PM_RX_INT_CAUSE", 4770 .cause_reg = A_PM_RX_INT_CAUSE, 4771 .enable_reg = A_PM_RX_INT_ENABLE, 4772 .fatal = 0x1fffffff, 4773 .flags = NONFATAL_IF_DISABLED, 4774 .details = pmrx_intr_details, 4775 .actions = NULL, 4776 }; 4777 4778 return (t4_handle_intr(adap, &pmrx_intr_info, 0, verbose)); 4779 } 4780 4781 /* 4782 * CPL switch interrupt handler. 4783 */ 4784 static bool cplsw_intr_handler(struct adapter *adap, int arg, bool verbose) 4785 { 4786 static const struct intr_details cplsw_intr_details[] = { 4787 /* T5+ */ 4788 { F_PERR_CPL_128TO128_1, "CPLSW 128TO128 FIFO1 parity error" }, 4789 { F_PERR_CPL_128TO128_0, "CPLSW 128TO128 FIFO0 parity error" }, 4790 4791 /* T4+ */ 4792 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error" }, 4793 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow" }, 4794 { F_TP_FRAMING_ERROR, "CPLSW TP framing error" }, 4795 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error" }, 4796 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error" }, 4797 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error" }, 4798 { 0 } 4799 }; 4800 static const struct intr_info cplsw_intr_info = { 4801 .name = "CPL_INTR_CAUSE", 4802 .cause_reg = A_CPL_INTR_CAUSE, 4803 .enable_reg = A_CPL_INTR_ENABLE, 4804 .fatal = 0xff, 4805 .flags = NONFATAL_IF_DISABLED, 4806 .details = cplsw_intr_details, 4807 .actions = NULL, 4808 }; 4809 4810 return (t4_handle_intr(adap, &cplsw_intr_info, 0, verbose)); 4811 } 4812 4813 #define T4_LE_FATAL_MASK (F_PARITYERR | F_UNKNOWNCMD | F_REQQPARERR) 4814 #define T5_LE_FATAL_MASK (T4_LE_FATAL_MASK | F_VFPARERR) 4815 #define T6_LE_PERRCRC_MASK (F_PIPELINEERR | F_CLIPTCAMACCFAIL | \ 4816 F_SRVSRAMACCFAIL | F_CLCAMCRCPARERR | F_CLCAMINTPERR | F_SSRAMINTPERR | \ 4817 F_SRVSRAMPERR | F_VFSRAMPERR | F_TCAMINTPERR | F_TCAMCRCERR | \ 4818 F_HASHTBLMEMACCERR | F_MAIFWRINTPERR | F_HASHTBLMEMCRCERR) 4819 #define T6_LE_FATAL_MASK (T6_LE_PERRCRC_MASK | F_T6_UNKNOWNCMD | \ 4820 F_TCAMACCFAIL | F_HASHTBLACCFAIL | F_CMDTIDERR | F_CMDPRSRINTERR | \ 4821 F_TOTCNTERR | F_CLCAMFIFOERR | F_CLIPSUBERR) 4822 4823 /* 4824 * LE interrupt handler. 4825 */ 4826 static bool le_intr_handler(struct adapter *adap, int arg, bool verbose) 4827 { 4828 static const struct intr_details le_intr_details[] = { 4829 { F_REQQPARERR, "LE request queue parity error" }, 4830 { F_UNKNOWNCMD, "LE unknown command" }, 4831 { F_ACTRGNFULL, "LE active region full" }, 4832 { F_PARITYERR, "LE parity error" }, 4833 { F_LIPMISS, "LE LIP miss" }, 4834 { F_LIP0, "LE 0 LIP error" }, 4835 { 0 } 4836 }; 4837 static const struct intr_details t6_le_intr_details[] = { 4838 { F_CLIPSUBERR, "LE CLIP CAM reverse substitution error" }, 4839 { F_CLCAMFIFOERR, "LE CLIP CAM internal FIFO error" }, 4840 { F_CTCAMINVLDENT, "Invalid IPv6 CLIP TCAM entry" }, 4841 { F_TCAMINVLDENT, "Invalid IPv6 TCAM entry" }, 4842 { F_TOTCNTERR, "LE total active < TCAM count" }, 4843 { F_CMDPRSRINTERR, "LE internal error in parser" }, 4844 { F_CMDTIDERR, "Incorrect tid in LE command" }, 4845 { F_T6_ACTRGNFULL, "LE active region full" }, 4846 { F_T6_ACTCNTIPV6TZERO, "LE IPv6 active open TCAM counter -ve" }, 4847 { F_T6_ACTCNTIPV4TZERO, "LE IPv4 active open TCAM counter -ve" }, 4848 { F_T6_ACTCNTIPV6ZERO, "LE IPv6 active open counter -ve" }, 4849 { F_T6_ACTCNTIPV4ZERO, "LE IPv4 active open counter -ve" }, 4850 { F_HASHTBLACCFAIL, "Hash table read error (proto conflict)" }, 4851 { F_TCAMACCFAIL, "LE TCAM access failure" }, 4852 { F_T6_UNKNOWNCMD, "LE unknown command" }, 4853 { F_T6_LIP0, "LE found 0 LIP during CLIP substitution" }, 4854 { F_T6_LIPMISS, "LE CLIP lookup miss" }, 4855 { T6_LE_PERRCRC_MASK, "LE parity/CRC error" }, 4856 { 0 } 4857 }; 4858 struct intr_info le_intr_info = { 4859 .name = "LE_DB_INT_CAUSE", 4860 .cause_reg = A_LE_DB_INT_CAUSE, 4861 .enable_reg = A_LE_DB_INT_ENABLE, 4862 .fatal = 0, 4863 .flags = NONFATAL_IF_DISABLED, 4864 .details = NULL, 4865 .actions = NULL, 4866 }; 4867 4868 if (chip_id(adap) <= CHELSIO_T5) { 4869 le_intr_info.details = le_intr_details; 4870 le_intr_info.fatal = T5_LE_FATAL_MASK; 4871 } else { 4872 le_intr_info.details = t6_le_intr_details; 4873 le_intr_info.fatal = T6_LE_FATAL_MASK; 4874 } 4875 4876 return (t4_handle_intr(adap, &le_intr_info, 0, verbose)); 4877 } 4878 4879 /* 4880 * MPS interrupt handler. 4881 */ 4882 static bool mps_intr_handler(struct adapter *adap, int arg, bool verbose) 4883 { 4884 static const struct intr_details mps_rx_perr_intr_details[] = { 4885 { 0xffffffff, "MPS Rx parity error" }, 4886 { 0 } 4887 }; 4888 static const struct intr_info mps_rx_perr_intr_info = { 4889 .name = "MPS_RX_PERR_INT_CAUSE", 4890 .cause_reg = A_MPS_RX_PERR_INT_CAUSE, 4891 .enable_reg = A_MPS_RX_PERR_INT_ENABLE, 4892 .fatal = 0xffffffff, 4893 .flags = NONFATAL_IF_DISABLED, 4894 .details = mps_rx_perr_intr_details, 4895 .actions = NULL, 4896 }; 4897 static const struct intr_details mps_tx_intr_details[] = { 4898 { F_PORTERR, "MPS Tx destination port is disabled" }, 4899 { F_FRMERR, "MPS Tx framing error" }, 4900 { F_SECNTERR, "MPS Tx SOP/EOP error" }, 4901 { F_BUBBLE, "MPS Tx underflow" }, 4902 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error" }, 4903 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error" }, 4904 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error" }, 4905 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error" }, 4906 { 0 } 4907 }; 4908 static const struct intr_info mps_tx_intr_info = { 4909 .name = "MPS_TX_INT_CAUSE", 4910 .cause_reg = A_MPS_TX_INT_CAUSE, 4911 .enable_reg = A_MPS_TX_INT_ENABLE, 4912 .fatal = 0x1ffff, 4913 .flags = NONFATAL_IF_DISABLED, 4914 .details = mps_tx_intr_details, 4915 .actions = NULL, 4916 }; 4917 static const struct intr_details mps_trc_intr_details[] = { 4918 { F_MISCPERR, "MPS TRC misc parity error" }, 4919 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error" }, 4920 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error" }, 4921 { 0 } 4922 }; 4923 static const struct intr_info mps_trc_intr_info = { 4924 .name = "MPS_TRC_INT_CAUSE", 4925 .cause_reg = A_MPS_TRC_INT_CAUSE, 4926 .enable_reg = A_MPS_TRC_INT_ENABLE, 4927 .fatal = F_MISCPERR | V_PKTFIFO(M_PKTFIFO) | V_FILTMEM(M_FILTMEM), 4928 .flags = 0, 4929 .details = mps_trc_intr_details, 4930 .actions = NULL, 4931 }; 4932 static const struct intr_details mps_stat_sram_intr_details[] = { 4933 { 0xffffffff, "MPS statistics SRAM parity error" }, 4934 { 0 } 4935 }; 4936 static const struct intr_info mps_stat_sram_intr_info = { 4937 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM", 4938 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4939 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM, 4940 .fatal = 0x1fffffff, 4941 .flags = NONFATAL_IF_DISABLED, 4942 .details = mps_stat_sram_intr_details, 4943 .actions = NULL, 4944 }; 4945 static const struct intr_details mps_stat_tx_intr_details[] = { 4946 { 0xffffff, "MPS statistics Tx FIFO parity error" }, 4947 { 0 } 4948 }; 4949 static const struct intr_info mps_stat_tx_intr_info = { 4950 .name = "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 4951 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4952 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO, 4953 .fatal = 0xffffff, 4954 .flags = NONFATAL_IF_DISABLED, 4955 .details = mps_stat_tx_intr_details, 4956 .actions = NULL, 4957 }; 4958 static const struct intr_details mps_stat_rx_intr_details[] = { 4959 { 0xffffff, "MPS statistics Rx FIFO parity error" }, 4960 { 0 } 4961 }; 4962 static const struct intr_info mps_stat_rx_intr_info = { 4963 .name = "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 4964 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4965 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO, 4966 .fatal = 0xffffff, 4967 .flags = 0, 4968 .details = mps_stat_rx_intr_details, 4969 .actions = NULL, 4970 }; 4971 static const struct intr_details mps_cls_intr_details[] = { 4972 { F_HASHSRAM, "MPS hash SRAM parity error" }, 4973 { F_MATCHTCAM, "MPS match TCAM parity error" }, 4974 { F_MATCHSRAM, "MPS match SRAM parity error" }, 4975 { 0 } 4976 }; 4977 static const struct intr_info mps_cls_intr_info = { 4978 .name = "MPS_CLS_INT_CAUSE", 4979 .cause_reg = A_MPS_CLS_INT_CAUSE, 4980 .enable_reg = A_MPS_CLS_INT_ENABLE, 4981 .fatal = F_MATCHSRAM | F_MATCHTCAM | F_HASHSRAM, 4982 .flags = 0, 4983 .details = mps_cls_intr_details, 4984 .actions = NULL, 4985 }; 4986 static const struct intr_details mps_stat_sram1_intr_details[] = { 4987 { 0xff, "MPS statistics SRAM1 parity error" }, 4988 { 0 } 4989 }; 4990 static const struct intr_info mps_stat_sram1_intr_info = { 4991 .name = "MPS_STAT_PERR_INT_CAUSE_SRAM1", 4992 .cause_reg = A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 4993 .enable_reg = A_MPS_STAT_PERR_INT_ENABLE_SRAM1, 4994 .fatal = 0xff, 4995 .flags = 0, 4996 .details = mps_stat_sram1_intr_details, 4997 .actions = NULL, 4998 }; 4999 5000 bool fatal; 5001 5002 fatal = false; 5003 fatal |= t4_handle_intr(adap, &mps_rx_perr_intr_info, 0, verbose); 5004 fatal |= t4_handle_intr(adap, &mps_tx_intr_info, 0, verbose); 5005 fatal |= t4_handle_intr(adap, &mps_trc_intr_info, 0, verbose); 5006 fatal |= t4_handle_intr(adap, &mps_stat_sram_intr_info, 0, verbose); 5007 fatal |= t4_handle_intr(adap, &mps_stat_tx_intr_info, 0, verbose); 5008 fatal |= t4_handle_intr(adap, &mps_stat_rx_intr_info, 0, verbose); 5009 fatal |= t4_handle_intr(adap, &mps_cls_intr_info, 0, verbose); 5010 if (chip_id(adap) > CHELSIO_T4) { 5011 fatal |= t4_handle_intr(adap, &mps_stat_sram1_intr_info, 0, 5012 verbose); 5013 } 5014 5015 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5016 t4_read_reg(adap, A_MPS_INT_CAUSE); /* flush */ 5017 5018 return (fatal); 5019 5020 } 5021 5022 /* 5023 * EDC/MC interrupt handler. 5024 */ 5025 static bool mem_intr_handler(struct adapter *adap, int idx, bool verbose) 5026 { 5027 static const char name[4][5] = { "EDC0", "EDC1", "MC0", "MC1" }; 5028 unsigned int count_reg, v; 5029 static const struct intr_details mem_intr_details[] = { 5030 { F_ECC_UE_INT_CAUSE, "Uncorrectable ECC data error(s)" }, 5031 { F_ECC_CE_INT_CAUSE, "Correctable ECC data error(s)" }, 5032 { F_PERR_INT_CAUSE, "FIFO parity error" }, 5033 { 0 } 5034 }; 5035 struct intr_info ii = { 5036 .fatal = F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE, 5037 .details = mem_intr_details, 5038 .flags = 0, 5039 .actions = NULL, 5040 }; 5041 bool fatal; 5042 5043 switch (idx) { 5044 case MEM_EDC0: 5045 ii.name = "EDC0_INT_CAUSE"; 5046 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 0); 5047 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 0); 5048 count_reg = EDC_REG(A_EDC_ECC_STATUS, 0); 5049 break; 5050 case MEM_EDC1: 5051 ii.name = "EDC1_INT_CAUSE"; 5052 ii.cause_reg = EDC_REG(A_EDC_INT_CAUSE, 1); 5053 ii.enable_reg = EDC_REG(A_EDC_INT_ENABLE, 1); 5054 count_reg = EDC_REG(A_EDC_ECC_STATUS, 1); 5055 break; 5056 case MEM_MC0: 5057 ii.name = "MC0_INT_CAUSE"; 5058 if (is_t4(adap)) { 5059 ii.cause_reg = A_MC_INT_CAUSE; 5060 ii.enable_reg = A_MC_INT_ENABLE; 5061 count_reg = A_MC_ECC_STATUS; 5062 } else { 5063 ii.cause_reg = A_MC_P_INT_CAUSE; 5064 ii.enable_reg = A_MC_P_INT_ENABLE; 5065 count_reg = A_MC_P_ECC_STATUS; 5066 } 5067 break; 5068 case MEM_MC1: 5069 ii.name = "MC1_INT_CAUSE"; 5070 ii.cause_reg = MC_REG(A_MC_P_INT_CAUSE, 1); 5071 ii.enable_reg = MC_REG(A_MC_P_INT_ENABLE, 1); 5072 count_reg = MC_REG(A_MC_P_ECC_STATUS, 1); 5073 break; 5074 } 5075 5076 fatal = t4_handle_intr(adap, &ii, 0, verbose); 5077 5078 v = t4_read_reg(adap, count_reg); 5079 if (v != 0) { 5080 if (G_ECC_UECNT(v) != 0) { 5081 CH_ALERT(adap, 5082 "%s: %u uncorrectable ECC data error(s)\n", 5083 name[idx], G_ECC_UECNT(v)); 5084 } 5085 if (G_ECC_CECNT(v) != 0) { 5086 if (idx <= MEM_EDC1) 5087 t4_edc_err_read(adap, idx); 5088 CH_WARN_RATELIMIT(adap, 5089 "%s: %u correctable ECC data error(s)\n", 5090 name[idx], G_ECC_CECNT(v)); 5091 } 5092 t4_write_reg(adap, count_reg, 0xffffffff); 5093 } 5094 5095 return (fatal); 5096 } 5097 5098 static bool ma_wrap_status(struct adapter *adap, int arg, bool verbose) 5099 { 5100 u32 v; 5101 5102 v = t4_read_reg(adap, A_MA_INT_WRAP_STATUS); 5103 CH_ALERT(adap, 5104 "MA address wrap-around error by client %u to address %#x\n", 5105 G_MEM_WRAP_CLIENT_NUM(v), G_MEM_WRAP_ADDRESS(v) << 4); 5106 t4_write_reg(adap, A_MA_INT_WRAP_STATUS, v); 5107 5108 return (false); 5109 } 5110 5111 5112 /* 5113 * MA interrupt handler. 5114 */ 5115 static bool ma_intr_handler(struct adapter *adap, int arg, bool verbose) 5116 { 5117 static const struct intr_action ma_intr_actions[] = { 5118 { F_MEM_WRAP_INT_CAUSE, 0, ma_wrap_status }, 5119 { 0 }, 5120 }; 5121 static const struct intr_info ma_intr_info = { 5122 .name = "MA_INT_CAUSE", 5123 .cause_reg = A_MA_INT_CAUSE, 5124 .enable_reg = A_MA_INT_ENABLE, 5125 .fatal = F_MEM_PERR_INT_CAUSE | F_MEM_TO_INT_CAUSE, 5126 .flags = NONFATAL_IF_DISABLED, 5127 .details = NULL, 5128 .actions = ma_intr_actions, 5129 }; 5130 static const struct intr_info ma_perr_status1 = { 5131 .name = "MA_PARITY_ERROR_STATUS1", 5132 .cause_reg = A_MA_PARITY_ERROR_STATUS1, 5133 .enable_reg = A_MA_PARITY_ERROR_ENABLE1, 5134 .fatal = 0xffffffff, 5135 .flags = 0, 5136 .details = NULL, 5137 .actions = NULL, 5138 }; 5139 static const struct intr_info ma_perr_status2 = { 5140 .name = "MA_PARITY_ERROR_STATUS2", 5141 .cause_reg = A_MA_PARITY_ERROR_STATUS2, 5142 .enable_reg = A_MA_PARITY_ERROR_ENABLE2, 5143 .fatal = 0xffffffff, 5144 .flags = 0, 5145 .details = NULL, 5146 .actions = NULL, 5147 }; 5148 bool fatal; 5149 5150 fatal = false; 5151 fatal |= t4_handle_intr(adap, &ma_intr_info, 0, verbose); 5152 fatal |= t4_handle_intr(adap, &ma_perr_status1, 0, verbose); 5153 if (chip_id(adap) > CHELSIO_T4) 5154 fatal |= t4_handle_intr(adap, &ma_perr_status2, 0, verbose); 5155 5156 return (fatal); 5157 } 5158 5159 /* 5160 * SMB interrupt handler. 5161 */ 5162 static bool smb_intr_handler(struct adapter *adap, int arg, bool verbose) 5163 { 5164 static const struct intr_details smb_intr_details[] = { 5165 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error" }, 5166 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error" }, 5167 { F_SLVFIFOPARINT, "SMB slave FIFO parity error" }, 5168 { 0 } 5169 }; 5170 static const struct intr_info smb_intr_info = { 5171 .name = "SMB_INT_CAUSE", 5172 .cause_reg = A_SMB_INT_CAUSE, 5173 .enable_reg = A_SMB_INT_ENABLE, 5174 .fatal = F_SLVFIFOPARINT | F_MSTRXFIFOPARINT | F_MSTTXFIFOPARINT, 5175 .flags = 0, 5176 .details = smb_intr_details, 5177 .actions = NULL, 5178 }; 5179 5180 return (t4_handle_intr(adap, &smb_intr_info, 0, verbose)); 5181 } 5182 5183 /* 5184 * NC-SI interrupt handler. 5185 */ 5186 static bool ncsi_intr_handler(struct adapter *adap, int arg, bool verbose) 5187 { 5188 static const struct intr_details ncsi_intr_details[] = { 5189 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error" }, 5190 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error" }, 5191 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error" }, 5192 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error" }, 5193 { 0 } 5194 }; 5195 static const struct intr_info ncsi_intr_info = { 5196 .name = "NCSI_INT_CAUSE", 5197 .cause_reg = A_NCSI_INT_CAUSE, 5198 .enable_reg = A_NCSI_INT_ENABLE, 5199 .fatal = F_RXFIFO_PRTY_ERR | F_TXFIFO_PRTY_ERR | 5200 F_MPS_DM_PRTY_ERR | F_CIM_DM_PRTY_ERR, 5201 .flags = 0, 5202 .details = ncsi_intr_details, 5203 .actions = NULL, 5204 }; 5205 5206 return (t4_handle_intr(adap, &ncsi_intr_info, 0, verbose)); 5207 } 5208 5209 /* 5210 * MAC interrupt handler. 5211 */ 5212 static bool mac_intr_handler(struct adapter *adap, int port, bool verbose) 5213 { 5214 static const struct intr_details mac_intr_details[] = { 5215 { F_TXFIFO_PRTY_ERR, "MAC Tx FIFO parity error" }, 5216 { F_RXFIFO_PRTY_ERR, "MAC Rx FIFO parity error" }, 5217 { 0 } 5218 }; 5219 char name[32]; 5220 struct intr_info ii; 5221 bool fatal = false; 5222 5223 if (is_t4(adap)) { 5224 snprintf(name, sizeof(name), "XGMAC_PORT%u_INT_CAUSE", port); 5225 ii.name = &name[0]; 5226 ii.cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 5227 ii.enable_reg = PORT_REG(port, A_XGMAC_PORT_INT_EN); 5228 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5229 ii.flags = 0; 5230 ii.details = mac_intr_details; 5231 ii.actions = NULL; 5232 } else { 5233 snprintf(name, sizeof(name), "MAC_PORT%u_INT_CAUSE", port); 5234 ii.name = &name[0]; 5235 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 5236 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_INT_EN); 5237 ii.fatal = F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR; 5238 ii.flags = 0; 5239 ii.details = mac_intr_details; 5240 ii.actions = NULL; 5241 } 5242 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5243 5244 if (chip_id(adap) >= CHELSIO_T5) { 5245 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE", port); 5246 ii.name = &name[0]; 5247 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE); 5248 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN); 5249 ii.fatal = 0; 5250 ii.flags = 0; 5251 ii.details = NULL; 5252 ii.actions = NULL; 5253 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5254 } 5255 5256 if (chip_id(adap) >= CHELSIO_T6) { 5257 snprintf(name, sizeof(name), "MAC_PORT%u_PERR_INT_CAUSE_100G", port); 5258 ii.name = &name[0]; 5259 ii.cause_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_CAUSE_100G); 5260 ii.enable_reg = T5_PORT_REG(port, A_MAC_PORT_PERR_INT_EN_100G); 5261 ii.fatal = 0; 5262 ii.flags = 0; 5263 ii.details = NULL; 5264 ii.actions = NULL; 5265 fatal |= t4_handle_intr(adap, &ii, 0, verbose); 5266 } 5267 5268 return (fatal); 5269 } 5270 5271 static bool plpl_intr_handler(struct adapter *adap, int arg, bool verbose) 5272 { 5273 static const struct intr_details plpl_intr_details[] = { 5274 { F_FATALPERR, "Fatal parity error" }, 5275 { F_PERRVFID, "VFID_MAP parity error" }, 5276 { 0 } 5277 }; 5278 static const struct intr_info plpl_intr_info = { 5279 .name = "PL_PL_INT_CAUSE", 5280 .cause_reg = A_PL_PL_INT_CAUSE, 5281 .enable_reg = A_PL_PL_INT_ENABLE, 5282 .fatal = F_FATALPERR | F_PERRVFID, 5283 .flags = NONFATAL_IF_DISABLED, 5284 .details = plpl_intr_details, 5285 .actions = NULL, 5286 }; 5287 5288 return (t4_handle_intr(adap, &plpl_intr_info, 0, verbose)); 5289 } 5290 5291 /** 5292 * t4_slow_intr_handler - control path interrupt handler 5293 * @adap: the adapter 5294 * @verbose: increased verbosity, for debug 5295 * 5296 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 5297 * The designation 'slow' is because it involves register reads, while 5298 * data interrupts typically don't involve any MMIOs. 5299 */ 5300 int t4_slow_intr_handler(struct adapter *adap, bool verbose) 5301 { 5302 static const struct intr_details pl_intr_details[] = { 5303 { F_MC1, "MC1" }, 5304 { F_UART, "UART" }, 5305 { F_ULP_TX, "ULP TX" }, 5306 { F_SGE, "SGE" }, 5307 { F_HMA, "HMA" }, 5308 { F_CPL_SWITCH, "CPL Switch" }, 5309 { F_ULP_RX, "ULP RX" }, 5310 { F_PM_RX, "PM RX" }, 5311 { F_PM_TX, "PM TX" }, 5312 { F_MA, "MA" }, 5313 { F_TP, "TP" }, 5314 { F_LE, "LE" }, 5315 { F_EDC1, "EDC1" }, 5316 { F_EDC0, "EDC0" }, 5317 { F_MC, "MC0" }, 5318 { F_PCIE, "PCIE" }, 5319 { F_PMU, "PMU" }, 5320 { F_MAC3, "MAC3" }, 5321 { F_MAC2, "MAC2" }, 5322 { F_MAC1, "MAC1" }, 5323 { F_MAC0, "MAC0" }, 5324 { F_SMB, "SMB" }, 5325 { F_SF, "SF" }, 5326 { F_PL, "PL" }, 5327 { F_NCSI, "NC-SI" }, 5328 { F_MPS, "MPS" }, 5329 { F_MI, "MI" }, 5330 { F_DBG, "DBG" }, 5331 { F_I2CM, "I2CM" }, 5332 { F_CIM, "CIM" }, 5333 { 0 } 5334 }; 5335 static const struct intr_info pl_perr_cause = { 5336 .name = "PL_PERR_CAUSE", 5337 .cause_reg = A_PL_PERR_CAUSE, 5338 .enable_reg = A_PL_PERR_ENABLE, 5339 .fatal = 0xffffffff, 5340 .flags = 0, 5341 .details = pl_intr_details, 5342 .actions = NULL, 5343 }; 5344 static const struct intr_action pl_intr_action[] = { 5345 { F_MC1, MEM_MC1, mem_intr_handler }, 5346 { F_ULP_TX, -1, ulptx_intr_handler }, 5347 { F_SGE, -1, sge_intr_handler }, 5348 { F_CPL_SWITCH, -1, cplsw_intr_handler }, 5349 { F_ULP_RX, -1, ulprx_intr_handler }, 5350 { F_PM_RX, -1, pmrx_intr_handler}, 5351 { F_PM_TX, -1, pmtx_intr_handler}, 5352 { F_MA, -1, ma_intr_handler }, 5353 { F_TP, -1, tp_intr_handler }, 5354 { F_LE, -1, le_intr_handler }, 5355 { F_EDC1, MEM_EDC1, mem_intr_handler }, 5356 { F_EDC0, MEM_EDC0, mem_intr_handler }, 5357 { F_MC0, MEM_MC0, mem_intr_handler }, 5358 { F_PCIE, -1, pcie_intr_handler }, 5359 { F_MAC3, 3, mac_intr_handler}, 5360 { F_MAC2, 2, mac_intr_handler}, 5361 { F_MAC1, 1, mac_intr_handler}, 5362 { F_MAC0, 0, mac_intr_handler}, 5363 { F_SMB, -1, smb_intr_handler}, 5364 { F_PL, -1, plpl_intr_handler }, 5365 { F_NCSI, -1, ncsi_intr_handler}, 5366 { F_MPS, -1, mps_intr_handler }, 5367 { F_CIM, -1, cim_intr_handler }, 5368 { 0 } 5369 }; 5370 static const struct intr_info pl_intr_info = { 5371 .name = "PL_INT_CAUSE", 5372 .cause_reg = A_PL_INT_CAUSE, 5373 .enable_reg = A_PL_INT_ENABLE, 5374 .fatal = 0, 5375 .flags = 0, 5376 .details = pl_intr_details, 5377 .actions = pl_intr_action, 5378 }; 5379 bool fatal; 5380 u32 perr; 5381 5382 perr = t4_read_reg(adap, pl_perr_cause.cause_reg); 5383 if (verbose || perr != 0) { 5384 t4_show_intr_info(adap, &pl_perr_cause, perr); 5385 if (perr != 0) 5386 t4_write_reg(adap, pl_perr_cause.cause_reg, perr); 5387 if (verbose) 5388 perr |= t4_read_reg(adap, pl_intr_info.enable_reg); 5389 } 5390 fatal = t4_handle_intr(adap, &pl_intr_info, perr, verbose); 5391 if (fatal) 5392 t4_fatal_err(adap, false); 5393 5394 return (0); 5395 } 5396 5397 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 5398 5399 /** 5400 * t4_intr_enable - enable interrupts 5401 * @adapter: the adapter whose interrupts should be enabled 5402 * 5403 * Enable PF-specific interrupts for the calling function and the top-level 5404 * interrupt concentrator for global interrupts. Interrupts are already 5405 * enabled at each module, here we just enable the roots of the interrupt 5406 * hierarchies. 5407 * 5408 * Note: this function should be called only when the driver manages 5409 * non PF-specific interrupts from the various HW modules. Only one PCI 5410 * function at a time should be doing this. 5411 */ 5412 void t4_intr_enable(struct adapter *adap) 5413 { 5414 u32 val = 0; 5415 5416 if (chip_id(adap) <= CHELSIO_T5) 5417 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 5418 else 5419 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 5420 val |= F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | 5421 F_ERR_CPL_OPCODE_0 | F_ERR_DATA_CPL_ON_HIGH_QID1 | 5422 F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | 5423 F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 5424 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | F_DBFIFO_LP_INT | 5425 F_EGRESS_SIZE_ERR; 5426 t4_set_reg_field(adap, A_SGE_INT_ENABLE3, val, val); 5427 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 5428 t4_set_reg_field(adap, A_PL_INT_ENABLE, F_SF | F_I2CM, 0); 5429 t4_set_reg_field(adap, A_PL_INT_MAP0, 0, 1 << adap->pf); 5430 } 5431 5432 /** 5433 * t4_intr_disable - disable interrupts 5434 * @adap: the adapter whose interrupts should be disabled 5435 * 5436 * Disable interrupts. We only disable the top-level interrupt 5437 * concentrators. The caller must be a PCI function managing global 5438 * interrupts. 5439 */ 5440 void t4_intr_disable(struct adapter *adap) 5441 { 5442 5443 t4_write_reg(adap, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 5444 t4_set_reg_field(adap, A_PL_INT_MAP0, 1 << adap->pf, 0); 5445 } 5446 5447 /** 5448 * t4_intr_clear - clear all interrupts 5449 * @adap: the adapter whose interrupts should be cleared 5450 * 5451 * Clears all interrupts. The caller must be a PCI function managing 5452 * global interrupts. 5453 */ 5454 void t4_intr_clear(struct adapter *adap) 5455 { 5456 static const u32 cause_reg[] = { 5457 A_CIM_HOST_INT_CAUSE, 5458 A_CIM_HOST_UPACC_INT_CAUSE, 5459 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 5460 A_CPL_INTR_CAUSE, 5461 EDC_REG(A_EDC_INT_CAUSE, 0), EDC_REG(A_EDC_INT_CAUSE, 1), 5462 A_LE_DB_INT_CAUSE, 5463 A_MA_INT_WRAP_STATUS, 5464 A_MA_PARITY_ERROR_STATUS1, 5465 A_MA_INT_CAUSE, 5466 A_MPS_CLS_INT_CAUSE, 5467 A_MPS_RX_PERR_INT_CAUSE, 5468 A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 5469 A_MPS_STAT_PERR_INT_CAUSE_SRAM, 5470 A_MPS_TRC_INT_CAUSE, 5471 A_MPS_TX_INT_CAUSE, 5472 A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 5473 A_NCSI_INT_CAUSE, 5474 A_PCIE_INT_CAUSE, 5475 A_PCIE_NONFAT_ERR, 5476 A_PL_PL_INT_CAUSE, 5477 A_PM_RX_INT_CAUSE, 5478 A_PM_TX_INT_CAUSE, 5479 A_SGE_INT_CAUSE1, 5480 A_SGE_INT_CAUSE2, 5481 A_SGE_INT_CAUSE3, 5482 A_SGE_INT_CAUSE4, 5483 A_SMB_INT_CAUSE, 5484 A_TP_INT_CAUSE, 5485 A_ULP_RX_INT_CAUSE, 5486 A_ULP_RX_INT_CAUSE_2, 5487 A_ULP_TX_INT_CAUSE, 5488 A_ULP_TX_INT_CAUSE_2, 5489 5490 MYPF_REG(A_PL_PF_INT_CAUSE), 5491 }; 5492 int i; 5493 const int nchan = adap->chip_params->nchan; 5494 5495 for (i = 0; i < ARRAY_SIZE(cause_reg); i++) 5496 t4_write_reg(adap, cause_reg[i], 0xffffffff); 5497 5498 if (is_t4(adap)) { 5499 t4_write_reg(adap, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 5500 0xffffffff); 5501 t4_write_reg(adap, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 5502 0xffffffff); 5503 t4_write_reg(adap, A_MC_INT_CAUSE, 0xffffffff); 5504 for (i = 0; i < nchan; i++) { 5505 t4_write_reg(adap, PORT_REG(i, A_XGMAC_PORT_INT_CAUSE), 5506 0xffffffff); 5507 } 5508 } 5509 if (chip_id(adap) >= CHELSIO_T5) { 5510 t4_write_reg(adap, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 5511 t4_write_reg(adap, A_MPS_STAT_PERR_INT_CAUSE_SRAM1, 0xffffffff); 5512 t4_write_reg(adap, A_SGE_INT_CAUSE5, 0xffffffff); 5513 t4_write_reg(adap, A_MC_P_INT_CAUSE, 0xffffffff); 5514 if (is_t5(adap)) { 5515 t4_write_reg(adap, MC_REG(A_MC_P_INT_CAUSE, 1), 5516 0xffffffff); 5517 } 5518 for (i = 0; i < nchan; i++) { 5519 t4_write_reg(adap, T5_PORT_REG(i, 5520 A_MAC_PORT_PERR_INT_CAUSE), 0xffffffff); 5521 if (chip_id(adap) > CHELSIO_T5) { 5522 t4_write_reg(adap, T5_PORT_REG(i, 5523 A_MAC_PORT_PERR_INT_CAUSE_100G), 5524 0xffffffff); 5525 } 5526 t4_write_reg(adap, T5_PORT_REG(i, A_MAC_PORT_INT_CAUSE), 5527 0xffffffff); 5528 } 5529 } 5530 if (chip_id(adap) >= CHELSIO_T6) { 5531 t4_write_reg(adap, A_SGE_INT_CAUSE6, 0xffffffff); 5532 } 5533 5534 t4_write_reg(adap, A_MPS_INT_CAUSE, is_t4(adap) ? 0 : 0xffffffff); 5535 t4_write_reg(adap, A_PL_PERR_CAUSE, 0xffffffff); 5536 t4_write_reg(adap, A_PL_INT_CAUSE, 0xffffffff); 5537 (void) t4_read_reg(adap, A_PL_INT_CAUSE); /* flush */ 5538 } 5539 5540 /** 5541 * hash_mac_addr - return the hash value of a MAC address 5542 * @addr: the 48-bit Ethernet MAC address 5543 * 5544 * Hashes a MAC address according to the hash function used by HW inexact 5545 * (hash) address matching. 5546 */ 5547 static int hash_mac_addr(const u8 *addr) 5548 { 5549 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 5550 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 5551 a ^= b; 5552 a ^= (a >> 12); 5553 a ^= (a >> 6); 5554 return a & 0x3f; 5555 } 5556 5557 /** 5558 * t4_config_rss_range - configure a portion of the RSS mapping table 5559 * @adapter: the adapter 5560 * @mbox: mbox to use for the FW command 5561 * @viid: virtual interface whose RSS subtable is to be written 5562 * @start: start entry in the table to write 5563 * @n: how many table entries to write 5564 * @rspq: values for the "response queue" (Ingress Queue) lookup table 5565 * @nrspq: number of values in @rspq 5566 * 5567 * Programs the selected part of the VI's RSS mapping table with the 5568 * provided values. If @nrspq < @n the supplied values are used repeatedly 5569 * until the full table range is populated. 5570 * 5571 * The caller must ensure the values in @rspq are in the range allowed for 5572 * @viid. 5573 */ 5574 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 5575 int start, int n, const u16 *rspq, unsigned int nrspq) 5576 { 5577 int ret; 5578 const u16 *rsp = rspq; 5579 const u16 *rsp_end = rspq + nrspq; 5580 struct fw_rss_ind_tbl_cmd cmd; 5581 5582 memset(&cmd, 0, sizeof(cmd)); 5583 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 5584 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5585 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 5586 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 5587 5588 /* 5589 * Each firmware RSS command can accommodate up to 32 RSS Ingress 5590 * Queue Identifiers. These Ingress Queue IDs are packed three to 5591 * a 32-bit word as 10-bit values with the upper remaining 2 bits 5592 * reserved. 5593 */ 5594 while (n > 0) { 5595 int nq = min(n, 32); 5596 int nq_packed = 0; 5597 __be32 *qp = &cmd.iq0_to_iq2; 5598 5599 /* 5600 * Set up the firmware RSS command header to send the next 5601 * "nq" Ingress Queue IDs to the firmware. 5602 */ 5603 cmd.niqid = cpu_to_be16(nq); 5604 cmd.startidx = cpu_to_be16(start); 5605 5606 /* 5607 * "nq" more done for the start of the next loop. 5608 */ 5609 start += nq; 5610 n -= nq; 5611 5612 /* 5613 * While there are still Ingress Queue IDs to stuff into the 5614 * current firmware RSS command, retrieve them from the 5615 * Ingress Queue ID array and insert them into the command. 5616 */ 5617 while (nq > 0) { 5618 /* 5619 * Grab up to the next 3 Ingress Queue IDs (wrapping 5620 * around the Ingress Queue ID array if necessary) and 5621 * insert them into the firmware RSS command at the 5622 * current 3-tuple position within the commad. 5623 */ 5624 u16 qbuf[3]; 5625 u16 *qbp = qbuf; 5626 int nqbuf = min(3, nq); 5627 5628 nq -= nqbuf; 5629 qbuf[0] = qbuf[1] = qbuf[2] = 0; 5630 while (nqbuf && nq_packed < 32) { 5631 nqbuf--; 5632 nq_packed++; 5633 *qbp++ = *rsp++; 5634 if (rsp >= rsp_end) 5635 rsp = rspq; 5636 } 5637 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 5638 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 5639 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 5640 } 5641 5642 /* 5643 * Send this portion of the RRS table update to the firmware; 5644 * bail out on any errors. 5645 */ 5646 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 5647 if (ret) 5648 return ret; 5649 } 5650 return 0; 5651 } 5652 5653 /** 5654 * t4_config_glbl_rss - configure the global RSS mode 5655 * @adapter: the adapter 5656 * @mbox: mbox to use for the FW command 5657 * @mode: global RSS mode 5658 * @flags: mode-specific flags 5659 * 5660 * Sets the global RSS mode. 5661 */ 5662 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 5663 unsigned int flags) 5664 { 5665 struct fw_rss_glb_config_cmd c; 5666 5667 memset(&c, 0, sizeof(c)); 5668 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 5669 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 5670 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5671 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 5672 c.u.manual.mode_pkd = 5673 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5674 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 5675 c.u.basicvirtual.mode_keymode = 5676 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 5677 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 5678 } else 5679 return -EINVAL; 5680 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5681 } 5682 5683 /** 5684 * t4_config_vi_rss - configure per VI RSS settings 5685 * @adapter: the adapter 5686 * @mbox: mbox to use for the FW command 5687 * @viid: the VI id 5688 * @flags: RSS flags 5689 * @defq: id of the default RSS queue for the VI. 5690 * @skeyidx: RSS secret key table index for non-global mode 5691 * @skey: RSS vf_scramble key for VI. 5692 * 5693 * Configures VI-specific RSS properties. 5694 */ 5695 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5696 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5697 unsigned int skey) 5698 { 5699 struct fw_rss_vi_config_cmd c; 5700 5701 memset(&c, 0, sizeof(c)); 5702 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5703 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5704 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5705 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5706 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5707 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5708 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5709 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5710 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5711 5712 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5713 } 5714 5715 /* Read an RSS table row */ 5716 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5717 { 5718 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5719 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5720 5, 0, val); 5721 } 5722 5723 /** 5724 * t4_read_rss - read the contents of the RSS mapping table 5725 * @adapter: the adapter 5726 * @map: holds the contents of the RSS mapping table 5727 * 5728 * Reads the contents of the RSS hash->queue mapping table. 5729 */ 5730 int t4_read_rss(struct adapter *adapter, u16 *map) 5731 { 5732 u32 val; 5733 int i, ret; 5734 int rss_nentries = adapter->chip_params->rss_nentries; 5735 5736 for (i = 0; i < rss_nentries / 2; ++i) { 5737 ret = rd_rss_row(adapter, i, &val); 5738 if (ret) 5739 return ret; 5740 *map++ = G_LKPTBLQUEUE0(val); 5741 *map++ = G_LKPTBLQUEUE1(val); 5742 } 5743 return 0; 5744 } 5745 5746 /** 5747 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5748 * @adap: the adapter 5749 * @cmd: TP fw ldst address space type 5750 * @vals: where the indirect register values are stored/written 5751 * @nregs: how many indirect registers to read/write 5752 * @start_idx: index of first indirect register to read/write 5753 * @rw: Read (1) or Write (0) 5754 * @sleep_ok: if true we may sleep while awaiting command completion 5755 * 5756 * Access TP indirect registers through LDST 5757 **/ 5758 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5759 unsigned int nregs, unsigned int start_index, 5760 unsigned int rw, bool sleep_ok) 5761 { 5762 int ret = 0; 5763 unsigned int i; 5764 struct fw_ldst_cmd c; 5765 5766 for (i = 0; i < nregs; i++) { 5767 memset(&c, 0, sizeof(c)); 5768 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5769 F_FW_CMD_REQUEST | 5770 (rw ? F_FW_CMD_READ : 5771 F_FW_CMD_WRITE) | 5772 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5773 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5774 5775 c.u.addrval.addr = cpu_to_be32(start_index + i); 5776 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5777 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5778 sleep_ok); 5779 if (ret) 5780 return ret; 5781 5782 if (rw) 5783 vals[i] = be32_to_cpu(c.u.addrval.val); 5784 } 5785 return 0; 5786 } 5787 5788 /** 5789 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5790 * @adap: the adapter 5791 * @reg_addr: Address Register 5792 * @reg_data: Data register 5793 * @buff: where the indirect register values are stored/written 5794 * @nregs: how many indirect registers to read/write 5795 * @start_index: index of first indirect register to read/write 5796 * @rw: READ(1) or WRITE(0) 5797 * @sleep_ok: if true we may sleep while awaiting command completion 5798 * 5799 * Read/Write TP indirect registers through LDST if possible. 5800 * Else, use backdoor access 5801 **/ 5802 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5803 u32 *buff, u32 nregs, u32 start_index, int rw, 5804 bool sleep_ok) 5805 { 5806 int rc = -EINVAL; 5807 int cmd; 5808 5809 switch (reg_addr) { 5810 case A_TP_PIO_ADDR: 5811 cmd = FW_LDST_ADDRSPC_TP_PIO; 5812 break; 5813 case A_TP_TM_PIO_ADDR: 5814 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5815 break; 5816 case A_TP_MIB_INDEX: 5817 cmd = FW_LDST_ADDRSPC_TP_MIB; 5818 break; 5819 default: 5820 goto indirect_access; 5821 } 5822 5823 if (t4_use_ldst(adap)) 5824 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5825 sleep_ok); 5826 5827 indirect_access: 5828 5829 if (rc) { 5830 if (rw) 5831 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5832 start_index); 5833 else 5834 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5835 start_index); 5836 } 5837 } 5838 5839 /** 5840 * t4_tp_pio_read - Read TP PIO registers 5841 * @adap: the adapter 5842 * @buff: where the indirect register values are written 5843 * @nregs: how many indirect registers to read 5844 * @start_index: index of first indirect register to read 5845 * @sleep_ok: if true we may sleep while awaiting command completion 5846 * 5847 * Read TP PIO Registers 5848 **/ 5849 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5850 u32 start_index, bool sleep_ok) 5851 { 5852 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5853 start_index, 1, sleep_ok); 5854 } 5855 5856 /** 5857 * t4_tp_pio_write - Write TP PIO registers 5858 * @adap: the adapter 5859 * @buff: where the indirect register values are stored 5860 * @nregs: how many indirect registers to write 5861 * @start_index: index of first indirect register to write 5862 * @sleep_ok: if true we may sleep while awaiting command completion 5863 * 5864 * Write TP PIO Registers 5865 **/ 5866 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5867 u32 start_index, bool sleep_ok) 5868 { 5869 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5870 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5871 } 5872 5873 /** 5874 * t4_tp_tm_pio_read - Read TP TM PIO registers 5875 * @adap: the adapter 5876 * @buff: where the indirect register values are written 5877 * @nregs: how many indirect registers to read 5878 * @start_index: index of first indirect register to read 5879 * @sleep_ok: if true we may sleep while awaiting command completion 5880 * 5881 * Read TP TM PIO Registers 5882 **/ 5883 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5884 u32 start_index, bool sleep_ok) 5885 { 5886 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5887 nregs, start_index, 1, sleep_ok); 5888 } 5889 5890 /** 5891 * t4_tp_mib_read - Read TP MIB registers 5892 * @adap: the adapter 5893 * @buff: where the indirect register values are written 5894 * @nregs: how many indirect registers to read 5895 * @start_index: index of first indirect register to read 5896 * @sleep_ok: if true we may sleep while awaiting command completion 5897 * 5898 * Read TP MIB Registers 5899 **/ 5900 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5901 bool sleep_ok) 5902 { 5903 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5904 start_index, 1, sleep_ok); 5905 } 5906 5907 /** 5908 * t4_read_rss_key - read the global RSS key 5909 * @adap: the adapter 5910 * @key: 10-entry array holding the 320-bit RSS key 5911 * @sleep_ok: if true we may sleep while awaiting command completion 5912 * 5913 * Reads the global 320-bit RSS key. 5914 */ 5915 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5916 { 5917 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5918 } 5919 5920 /** 5921 * t4_write_rss_key - program one of the RSS keys 5922 * @adap: the adapter 5923 * @key: 10-entry array holding the 320-bit RSS key 5924 * @idx: which RSS key to write 5925 * @sleep_ok: if true we may sleep while awaiting command completion 5926 * 5927 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5928 * 0..15 the corresponding entry in the RSS key table is written, 5929 * otherwise the global RSS key is written. 5930 */ 5931 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5932 bool sleep_ok) 5933 { 5934 u8 rss_key_addr_cnt = 16; 5935 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5936 5937 /* 5938 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5939 * allows access to key addresses 16-63 by using KeyWrAddrX 5940 * as index[5:4](upper 2) into key table 5941 */ 5942 if ((chip_id(adap) > CHELSIO_T5) && 5943 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5944 rss_key_addr_cnt = 32; 5945 5946 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5947 5948 if (idx >= 0 && idx < rss_key_addr_cnt) { 5949 if (rss_key_addr_cnt > 16) 5950 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5951 vrt | V_KEYWRADDRX(idx >> 4) | 5952 V_T6_VFWRADDR(idx) | F_KEYWREN); 5953 else 5954 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5955 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5956 } 5957 } 5958 5959 /** 5960 * t4_read_rss_pf_config - read PF RSS Configuration Table 5961 * @adapter: the adapter 5962 * @index: the entry in the PF RSS table to read 5963 * @valp: where to store the returned value 5964 * @sleep_ok: if true we may sleep while awaiting command completion 5965 * 5966 * Reads the PF RSS Configuration Table at the specified index and returns 5967 * the value found there. 5968 */ 5969 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5970 u32 *valp, bool sleep_ok) 5971 { 5972 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5973 } 5974 5975 /** 5976 * t4_write_rss_pf_config - write PF RSS Configuration Table 5977 * @adapter: the adapter 5978 * @index: the entry in the VF RSS table to read 5979 * @val: the value to store 5980 * @sleep_ok: if true we may sleep while awaiting command completion 5981 * 5982 * Writes the PF RSS Configuration Table at the specified index with the 5983 * specified value. 5984 */ 5985 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5986 u32 val, bool sleep_ok) 5987 { 5988 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5989 sleep_ok); 5990 } 5991 5992 /** 5993 * t4_read_rss_vf_config - read VF RSS Configuration Table 5994 * @adapter: the adapter 5995 * @index: the entry in the VF RSS table to read 5996 * @vfl: where to store the returned VFL 5997 * @vfh: where to store the returned VFH 5998 * @sleep_ok: if true we may sleep while awaiting command completion 5999 * 6000 * Reads the VF RSS Configuration Table at the specified index and returns 6001 * the (VFL, VFH) values found there. 6002 */ 6003 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 6004 u32 *vfl, u32 *vfh, bool sleep_ok) 6005 { 6006 u32 vrt, mask, data; 6007 6008 if (chip_id(adapter) <= CHELSIO_T5) { 6009 mask = V_VFWRADDR(M_VFWRADDR); 6010 data = V_VFWRADDR(index); 6011 } else { 6012 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6013 data = V_T6_VFWRADDR(index); 6014 } 6015 /* 6016 * Request that the index'th VF Table values be read into VFL/VFH. 6017 */ 6018 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6019 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6020 vrt |= data | F_VFRDEN; 6021 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6022 6023 /* 6024 * Grab the VFL/VFH values ... 6025 */ 6026 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6027 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6028 } 6029 6030 /** 6031 * t4_write_rss_vf_config - write VF RSS Configuration Table 6032 * 6033 * @adapter: the adapter 6034 * @index: the entry in the VF RSS table to write 6035 * @vfl: the VFL to store 6036 * @vfh: the VFH to store 6037 * 6038 * Writes the VF RSS Configuration Table at the specified index with the 6039 * specified (VFL, VFH) values. 6040 */ 6041 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 6042 u32 vfl, u32 vfh, bool sleep_ok) 6043 { 6044 u32 vrt, mask, data; 6045 6046 if (chip_id(adapter) <= CHELSIO_T5) { 6047 mask = V_VFWRADDR(M_VFWRADDR); 6048 data = V_VFWRADDR(index); 6049 } else { 6050 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 6051 data = V_T6_VFWRADDR(index); 6052 } 6053 6054 /* 6055 * Load up VFL/VFH with the values to be written ... 6056 */ 6057 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 6058 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 6059 6060 /* 6061 * Write the VFL/VFH into the VF Table at index'th location. 6062 */ 6063 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 6064 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 6065 vrt |= data | F_VFRDEN; 6066 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 6067 } 6068 6069 /** 6070 * t4_read_rss_pf_map - read PF RSS Map 6071 * @adapter: the adapter 6072 * @sleep_ok: if true we may sleep while awaiting command completion 6073 * 6074 * Reads the PF RSS Map register and returns its value. 6075 */ 6076 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 6077 { 6078 u32 pfmap; 6079 6080 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6081 6082 return pfmap; 6083 } 6084 6085 /** 6086 * t4_write_rss_pf_map - write PF RSS Map 6087 * @adapter: the adapter 6088 * @pfmap: PF RSS Map value 6089 * 6090 * Writes the specified value to the PF RSS Map register. 6091 */ 6092 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 6093 { 6094 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 6095 } 6096 6097 /** 6098 * t4_read_rss_pf_mask - read PF RSS Mask 6099 * @adapter: the adapter 6100 * @sleep_ok: if true we may sleep while awaiting command completion 6101 * 6102 * Reads the PF RSS Mask register and returns its value. 6103 */ 6104 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 6105 { 6106 u32 pfmask; 6107 6108 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6109 6110 return pfmask; 6111 } 6112 6113 /** 6114 * t4_write_rss_pf_mask - write PF RSS Mask 6115 * @adapter: the adapter 6116 * @pfmask: PF RSS Mask value 6117 * 6118 * Writes the specified value to the PF RSS Mask register. 6119 */ 6120 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 6121 { 6122 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 6123 } 6124 6125 /** 6126 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 6127 * @adap: the adapter 6128 * @v4: holds the TCP/IP counter values 6129 * @v6: holds the TCP/IPv6 counter values 6130 * @sleep_ok: if true we may sleep while awaiting command completion 6131 * 6132 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 6133 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 6134 */ 6135 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 6136 struct tp_tcp_stats *v6, bool sleep_ok) 6137 { 6138 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 6139 6140 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 6141 #define STAT(x) val[STAT_IDX(x)] 6142 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 6143 6144 if (v4) { 6145 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6146 A_TP_MIB_TCP_OUT_RST, sleep_ok); 6147 v4->tcp_out_rsts = STAT(OUT_RST); 6148 v4->tcp_in_segs = STAT64(IN_SEG); 6149 v4->tcp_out_segs = STAT64(OUT_SEG); 6150 v4->tcp_retrans_segs = STAT64(RXT_SEG); 6151 } 6152 if (v6) { 6153 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 6154 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 6155 v6->tcp_out_rsts = STAT(OUT_RST); 6156 v6->tcp_in_segs = STAT64(IN_SEG); 6157 v6->tcp_out_segs = STAT64(OUT_SEG); 6158 v6->tcp_retrans_segs = STAT64(RXT_SEG); 6159 } 6160 #undef STAT64 6161 #undef STAT 6162 #undef STAT_IDX 6163 } 6164 6165 /** 6166 * t4_tp_get_err_stats - read TP's error MIB counters 6167 * @adap: the adapter 6168 * @st: holds the counter values 6169 * @sleep_ok: if true we may sleep while awaiting command completion 6170 * 6171 * Returns the values of TP's error counters. 6172 */ 6173 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 6174 bool sleep_ok) 6175 { 6176 int nchan = adap->chip_params->nchan; 6177 6178 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 6179 sleep_ok); 6180 6181 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 6182 sleep_ok); 6183 6184 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 6185 sleep_ok); 6186 6187 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 6188 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 6189 6190 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 6191 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 6192 6193 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 6194 sleep_ok); 6195 6196 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 6197 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 6198 6199 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 6200 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 6201 6202 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 6203 sleep_ok); 6204 } 6205 6206 /** 6207 * t4_tp_get_err_stats - read TP's error MIB counters 6208 * @adap: the adapter 6209 * @st: holds the counter values 6210 * @sleep_ok: if true we may sleep while awaiting command completion 6211 * 6212 * Returns the values of TP's error counters. 6213 */ 6214 void t4_tp_get_tnl_stats(struct adapter *adap, struct tp_tnl_stats *st, 6215 bool sleep_ok) 6216 { 6217 int nchan = adap->chip_params->nchan; 6218 6219 t4_tp_mib_read(adap, st->out_pkt, nchan, A_TP_MIB_TNL_OUT_PKT_0, 6220 sleep_ok); 6221 t4_tp_mib_read(adap, st->in_pkt, nchan, A_TP_MIB_TNL_IN_PKT_0, 6222 sleep_ok); 6223 } 6224 6225 /** 6226 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 6227 * @adap: the adapter 6228 * @st: holds the counter values 6229 * 6230 * Returns the values of TP's proxy counters. 6231 */ 6232 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 6233 bool sleep_ok) 6234 { 6235 int nchan = adap->chip_params->nchan; 6236 6237 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 6238 } 6239 6240 /** 6241 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 6242 * @adap: the adapter 6243 * @st: holds the counter values 6244 * @sleep_ok: if true we may sleep while awaiting command completion 6245 * 6246 * Returns the values of TP's CPL counters. 6247 */ 6248 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 6249 bool sleep_ok) 6250 { 6251 int nchan = adap->chip_params->nchan; 6252 6253 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 6254 6255 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 6256 } 6257 6258 /** 6259 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 6260 * @adap: the adapter 6261 * @st: holds the counter values 6262 * 6263 * Returns the values of TP's RDMA counters. 6264 */ 6265 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 6266 bool sleep_ok) 6267 { 6268 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 6269 sleep_ok); 6270 } 6271 6272 /** 6273 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 6274 * @adap: the adapter 6275 * @idx: the port index 6276 * @st: holds the counter values 6277 * @sleep_ok: if true we may sleep while awaiting command completion 6278 * 6279 * Returns the values of TP's FCoE counters for the selected port. 6280 */ 6281 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 6282 struct tp_fcoe_stats *st, bool sleep_ok) 6283 { 6284 u32 val[2]; 6285 6286 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 6287 sleep_ok); 6288 6289 t4_tp_mib_read(adap, &st->frames_drop, 1, 6290 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 6291 6292 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 6293 sleep_ok); 6294 6295 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 6296 } 6297 6298 /** 6299 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 6300 * @adap: the adapter 6301 * @st: holds the counter values 6302 * @sleep_ok: if true we may sleep while awaiting command completion 6303 * 6304 * Returns the values of TP's counters for non-TCP directly-placed packets. 6305 */ 6306 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 6307 bool sleep_ok) 6308 { 6309 u32 val[4]; 6310 6311 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 6312 6313 st->frames = val[0]; 6314 st->drops = val[1]; 6315 st->octets = ((u64)val[2] << 32) | val[3]; 6316 } 6317 6318 /** 6319 * t4_tp_get_tid_stats - read TP's tid MIB counters. 6320 * @adap: the adapter 6321 * @st: holds the counter values 6322 * @sleep_ok: if true we may sleep while awaiting command completion 6323 * 6324 * Returns the values of TP's counters for tids. 6325 */ 6326 void t4_tp_get_tid_stats(struct adapter *adap, struct tp_tid_stats *st, 6327 bool sleep_ok) 6328 { 6329 6330 t4_tp_mib_read(adap, &st->del, 4, A_TP_MIB_TID_DEL, sleep_ok); 6331 } 6332 6333 /** 6334 * t4_read_mtu_tbl - returns the values in the HW path MTU table 6335 * @adap: the adapter 6336 * @mtus: where to store the MTU values 6337 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 6338 * 6339 * Reads the HW path MTU table. 6340 */ 6341 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 6342 { 6343 u32 v; 6344 int i; 6345 6346 for (i = 0; i < NMTUS; ++i) { 6347 t4_write_reg(adap, A_TP_MTU_TABLE, 6348 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 6349 v = t4_read_reg(adap, A_TP_MTU_TABLE); 6350 mtus[i] = G_MTUVALUE(v); 6351 if (mtu_log) 6352 mtu_log[i] = G_MTUWIDTH(v); 6353 } 6354 } 6355 6356 /** 6357 * t4_read_cong_tbl - reads the congestion control table 6358 * @adap: the adapter 6359 * @incr: where to store the alpha values 6360 * 6361 * Reads the additive increments programmed into the HW congestion 6362 * control table. 6363 */ 6364 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 6365 { 6366 unsigned int mtu, w; 6367 6368 for (mtu = 0; mtu < NMTUS; ++mtu) 6369 for (w = 0; w < NCCTRL_WIN; ++w) { 6370 t4_write_reg(adap, A_TP_CCTRL_TABLE, 6371 V_ROWINDEX(0xffff) | (mtu << 5) | w); 6372 incr[mtu][w] = (u16)t4_read_reg(adap, 6373 A_TP_CCTRL_TABLE) & 0x1fff; 6374 } 6375 } 6376 6377 /** 6378 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 6379 * @adap: the adapter 6380 * @addr: the indirect TP register address 6381 * @mask: specifies the field within the register to modify 6382 * @val: new value for the field 6383 * 6384 * Sets a field of an indirect TP register to the given value. 6385 */ 6386 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 6387 unsigned int mask, unsigned int val) 6388 { 6389 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 6390 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 6391 t4_write_reg(adap, A_TP_PIO_DATA, val); 6392 } 6393 6394 /** 6395 * init_cong_ctrl - initialize congestion control parameters 6396 * @a: the alpha values for congestion control 6397 * @b: the beta values for congestion control 6398 * 6399 * Initialize the congestion control parameters. 6400 */ 6401 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 6402 { 6403 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 6404 a[9] = 2; 6405 a[10] = 3; 6406 a[11] = 4; 6407 a[12] = 5; 6408 a[13] = 6; 6409 a[14] = 7; 6410 a[15] = 8; 6411 a[16] = 9; 6412 a[17] = 10; 6413 a[18] = 14; 6414 a[19] = 17; 6415 a[20] = 21; 6416 a[21] = 25; 6417 a[22] = 30; 6418 a[23] = 35; 6419 a[24] = 45; 6420 a[25] = 60; 6421 a[26] = 80; 6422 a[27] = 100; 6423 a[28] = 200; 6424 a[29] = 300; 6425 a[30] = 400; 6426 a[31] = 500; 6427 6428 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 6429 b[9] = b[10] = 1; 6430 b[11] = b[12] = 2; 6431 b[13] = b[14] = b[15] = b[16] = 3; 6432 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 6433 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 6434 b[28] = b[29] = 6; 6435 b[30] = b[31] = 7; 6436 } 6437 6438 /* The minimum additive increment value for the congestion control table */ 6439 #define CC_MIN_INCR 2U 6440 6441 /** 6442 * t4_load_mtus - write the MTU and congestion control HW tables 6443 * @adap: the adapter 6444 * @mtus: the values for the MTU table 6445 * @alpha: the values for the congestion control alpha parameter 6446 * @beta: the values for the congestion control beta parameter 6447 * 6448 * Write the HW MTU table with the supplied MTUs and the high-speed 6449 * congestion control table with the supplied alpha, beta, and MTUs. 6450 * We write the two tables together because the additive increments 6451 * depend on the MTUs. 6452 */ 6453 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 6454 const unsigned short *alpha, const unsigned short *beta) 6455 { 6456 static const unsigned int avg_pkts[NCCTRL_WIN] = { 6457 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 6458 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 6459 28672, 40960, 57344, 81920, 114688, 163840, 229376 6460 }; 6461 6462 unsigned int i, w; 6463 6464 for (i = 0; i < NMTUS; ++i) { 6465 unsigned int mtu = mtus[i]; 6466 unsigned int log2 = fls(mtu); 6467 6468 if (!(mtu & ((1 << log2) >> 2))) /* round */ 6469 log2--; 6470 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 6471 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 6472 6473 for (w = 0; w < NCCTRL_WIN; ++w) { 6474 unsigned int inc; 6475 6476 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 6477 CC_MIN_INCR); 6478 6479 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 6480 (w << 16) | (beta[w] << 13) | inc); 6481 } 6482 } 6483 } 6484 6485 /** 6486 * t4_set_pace_tbl - set the pace table 6487 * @adap: the adapter 6488 * @pace_vals: the pace values in microseconds 6489 * @start: index of the first entry in the HW pace table to set 6490 * @n: how many entries to set 6491 * 6492 * Sets (a subset of the) HW pace table. 6493 */ 6494 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 6495 unsigned int start, unsigned int n) 6496 { 6497 unsigned int vals[NTX_SCHED], i; 6498 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 6499 6500 if (n > NTX_SCHED) 6501 return -ERANGE; 6502 6503 /* convert values from us to dack ticks, rounding to closest value */ 6504 for (i = 0; i < n; i++, pace_vals++) { 6505 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 6506 if (vals[i] > 0x7ff) 6507 return -ERANGE; 6508 if (*pace_vals && vals[i] == 0) 6509 return -ERANGE; 6510 } 6511 for (i = 0; i < n; i++, start++) 6512 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 6513 return 0; 6514 } 6515 6516 /** 6517 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 6518 * @adap: the adapter 6519 * @kbps: target rate in Kbps 6520 * @sched: the scheduler index 6521 * 6522 * Configure a Tx HW scheduler for the target rate. 6523 */ 6524 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 6525 { 6526 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 6527 unsigned int clk = adap->params.vpd.cclk * 1000; 6528 unsigned int selected_cpt = 0, selected_bpt = 0; 6529 6530 if (kbps > 0) { 6531 kbps *= 125; /* -> bytes */ 6532 for (cpt = 1; cpt <= 255; cpt++) { 6533 tps = clk / cpt; 6534 bpt = (kbps + tps / 2) / tps; 6535 if (bpt > 0 && bpt <= 255) { 6536 v = bpt * tps; 6537 delta = v >= kbps ? v - kbps : kbps - v; 6538 if (delta < mindelta) { 6539 mindelta = delta; 6540 selected_cpt = cpt; 6541 selected_bpt = bpt; 6542 } 6543 } else if (selected_cpt) 6544 break; 6545 } 6546 if (!selected_cpt) 6547 return -EINVAL; 6548 } 6549 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 6550 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 6551 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6552 if (sched & 1) 6553 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 6554 else 6555 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 6556 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6557 return 0; 6558 } 6559 6560 /** 6561 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 6562 * @adap: the adapter 6563 * @sched: the scheduler index 6564 * @ipg: the interpacket delay in tenths of nanoseconds 6565 * 6566 * Set the interpacket delay for a HW packet rate scheduler. 6567 */ 6568 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 6569 { 6570 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 6571 6572 /* convert ipg to nearest number of core clocks */ 6573 ipg *= core_ticks_per_usec(adap); 6574 ipg = (ipg + 5000) / 10000; 6575 if (ipg > M_TXTIMERSEPQ0) 6576 return -EINVAL; 6577 6578 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 6579 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 6580 if (sched & 1) 6581 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 6582 else 6583 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 6584 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 6585 t4_read_reg(adap, A_TP_TM_PIO_DATA); 6586 return 0; 6587 } 6588 6589 /* 6590 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 6591 * clocks. The formula is 6592 * 6593 * bytes/s = bytes256 * 256 * ClkFreq / 4096 6594 * 6595 * which is equivalent to 6596 * 6597 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 6598 */ 6599 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 6600 { 6601 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 6602 6603 return v * 62 + v / 2; 6604 } 6605 6606 /** 6607 * t4_get_chan_txrate - get the current per channel Tx rates 6608 * @adap: the adapter 6609 * @nic_rate: rates for NIC traffic 6610 * @ofld_rate: rates for offloaded traffic 6611 * 6612 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 6613 * for each channel. 6614 */ 6615 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 6616 { 6617 u32 v; 6618 6619 v = t4_read_reg(adap, A_TP_TX_TRATE); 6620 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 6621 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 6622 if (adap->chip_params->nchan > 2) { 6623 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 6624 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 6625 } 6626 6627 v = t4_read_reg(adap, A_TP_TX_ORATE); 6628 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 6629 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 6630 if (adap->chip_params->nchan > 2) { 6631 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 6632 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 6633 } 6634 } 6635 6636 /** 6637 * t4_set_trace_filter - configure one of the tracing filters 6638 * @adap: the adapter 6639 * @tp: the desired trace filter parameters 6640 * @idx: which filter to configure 6641 * @enable: whether to enable or disable the filter 6642 * 6643 * Configures one of the tracing filters available in HW. If @tp is %NULL 6644 * it indicates that the filter is already written in the register and it 6645 * just needs to be enabled or disabled. 6646 */ 6647 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 6648 int idx, int enable) 6649 { 6650 int i, ofst = idx * 4; 6651 u32 data_reg, mask_reg, cfg; 6652 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 6653 6654 if (idx < 0 || idx >= NTRACE) 6655 return -EINVAL; 6656 6657 if (tp == NULL || !enable) { 6658 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 6659 enable ? en : 0); 6660 return 0; 6661 } 6662 6663 /* 6664 * TODO - After T4 data book is updated, specify the exact 6665 * section below. 6666 * 6667 * See T4 data book - MPS section for a complete description 6668 * of the below if..else handling of A_MPS_TRC_CFG register 6669 * value. 6670 */ 6671 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 6672 if (cfg & F_TRCMULTIFILTER) { 6673 /* 6674 * If multiple tracers are enabled, then maximum 6675 * capture size is 2.5KB (FIFO size of a single channel) 6676 * minus 2 flits for CPL_TRACE_PKT header. 6677 */ 6678 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 6679 return -EINVAL; 6680 } else { 6681 /* 6682 * If multiple tracers are disabled, to avoid deadlocks 6683 * maximum packet capture size of 9600 bytes is recommended. 6684 * Also in this mode, only trace0 can be enabled and running. 6685 */ 6686 if (tp->snap_len > 9600 || idx) 6687 return -EINVAL; 6688 } 6689 6690 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 6691 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 6692 tp->min_len > M_TFMINPKTSIZE) 6693 return -EINVAL; 6694 6695 /* stop the tracer we'll be changing */ 6696 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 6697 6698 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 6699 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 6700 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 6701 6702 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6703 t4_write_reg(adap, data_reg, tp->data[i]); 6704 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 6705 } 6706 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 6707 V_TFCAPTUREMAX(tp->snap_len) | 6708 V_TFMINPKTSIZE(tp->min_len)); 6709 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 6710 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 6711 (is_t4(adap) ? 6712 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 6713 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 6714 6715 return 0; 6716 } 6717 6718 /** 6719 * t4_get_trace_filter - query one of the tracing filters 6720 * @adap: the adapter 6721 * @tp: the current trace filter parameters 6722 * @idx: which trace filter to query 6723 * @enabled: non-zero if the filter is enabled 6724 * 6725 * Returns the current settings of one of the HW tracing filters. 6726 */ 6727 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6728 int *enabled) 6729 { 6730 u32 ctla, ctlb; 6731 int i, ofst = idx * 4; 6732 u32 data_reg, mask_reg; 6733 6734 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6735 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6736 6737 if (is_t4(adap)) { 6738 *enabled = !!(ctla & F_TFEN); 6739 tp->port = G_TFPORT(ctla); 6740 tp->invert = !!(ctla & F_TFINVERTMATCH); 6741 } else { 6742 *enabled = !!(ctla & F_T5_TFEN); 6743 tp->port = G_T5_TFPORT(ctla); 6744 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6745 } 6746 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6747 tp->min_len = G_TFMINPKTSIZE(ctlb); 6748 tp->skip_ofst = G_TFOFFSET(ctla); 6749 tp->skip_len = G_TFLENGTH(ctla); 6750 6751 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6752 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6753 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6754 6755 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6756 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6757 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6758 } 6759 } 6760 6761 /** 6762 * t4_pmtx_get_stats - returns the HW stats from PMTX 6763 * @adap: the adapter 6764 * @cnt: where to store the count statistics 6765 * @cycles: where to store the cycle statistics 6766 * 6767 * Returns performance statistics from PMTX. 6768 */ 6769 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6770 { 6771 int i; 6772 u32 data[2]; 6773 6774 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6775 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6776 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6777 if (is_t4(adap)) 6778 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6779 else { 6780 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6781 A_PM_TX_DBG_DATA, data, 2, 6782 A_PM_TX_DBG_STAT_MSB); 6783 cycles[i] = (((u64)data[0] << 32) | data[1]); 6784 } 6785 } 6786 } 6787 6788 /** 6789 * t4_pmrx_get_stats - returns the HW stats from PMRX 6790 * @adap: the adapter 6791 * @cnt: where to store the count statistics 6792 * @cycles: where to store the cycle statistics 6793 * 6794 * Returns performance statistics from PMRX. 6795 */ 6796 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6797 { 6798 int i; 6799 u32 data[2]; 6800 6801 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6802 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6803 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6804 if (is_t4(adap)) { 6805 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6806 } else { 6807 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6808 A_PM_RX_DBG_DATA, data, 2, 6809 A_PM_RX_DBG_STAT_MSB); 6810 cycles[i] = (((u64)data[0] << 32) | data[1]); 6811 } 6812 } 6813 } 6814 6815 /** 6816 * t4_get_mps_bg_map - return the buffer groups associated with a port 6817 * @adap: the adapter 6818 * @idx: the port index 6819 * 6820 * Returns a bitmap indicating which MPS buffer groups are associated 6821 * with the given port. Bit i is set if buffer group i is used by the 6822 * port. 6823 */ 6824 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6825 { 6826 u32 n; 6827 6828 if (adap->params.mps_bg_map) 6829 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6830 6831 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6832 if (n == 0) 6833 return idx == 0 ? 0xf : 0; 6834 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6835 return idx < 2 ? (3 << (2 * idx)) : 0; 6836 return 1 << idx; 6837 } 6838 6839 /* 6840 * TP RX e-channels associated with the port. 6841 */ 6842 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6843 { 6844 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6845 const u32 all_chan = (1 << adap->chip_params->nchan) - 1; 6846 6847 if (n == 0) 6848 return idx == 0 ? all_chan : 0; 6849 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6850 return idx < 2 ? (3 << (2 * idx)) : 0; 6851 return 1 << idx; 6852 } 6853 6854 /* 6855 * TP RX c-channel associated with the port. 6856 */ 6857 static unsigned int t4_get_rx_c_chan(struct adapter *adap, int idx) 6858 { 6859 u32 param, val; 6860 int ret; 6861 6862 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 6863 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_TPCHMAP)); 6864 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 6865 if (!ret) 6866 return (val >> (8 * idx)) & 0xff; 6867 6868 return 0; 6869 } 6870 6871 /** 6872 * t4_get_port_type_description - return Port Type string description 6873 * @port_type: firmware Port Type enumeration 6874 */ 6875 const char *t4_get_port_type_description(enum fw_port_type port_type) 6876 { 6877 static const char *const port_type_description[] = { 6878 "Fiber_XFI", 6879 "Fiber_XAUI", 6880 "BT_SGMII", 6881 "BT_XFI", 6882 "BT_XAUI", 6883 "KX4", 6884 "CX4", 6885 "KX", 6886 "KR", 6887 "SFP", 6888 "BP_AP", 6889 "BP4_AP", 6890 "QSFP_10G", 6891 "QSA", 6892 "QSFP", 6893 "BP40_BA", 6894 "KR4_100G", 6895 "CR4_QSFP", 6896 "CR_QSFP", 6897 "CR2_QSFP", 6898 "SFP28", 6899 "KR_SFP28", 6900 }; 6901 6902 if (port_type < ARRAY_SIZE(port_type_description)) 6903 return port_type_description[port_type]; 6904 return "UNKNOWN"; 6905 } 6906 6907 /** 6908 * t4_get_port_stats_offset - collect port stats relative to a previous 6909 * snapshot 6910 * @adap: The adapter 6911 * @idx: The port 6912 * @stats: Current stats to fill 6913 * @offset: Previous stats snapshot 6914 */ 6915 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6916 struct port_stats *stats, 6917 struct port_stats *offset) 6918 { 6919 u64 *s, *o; 6920 int i; 6921 6922 t4_get_port_stats(adap, idx, stats); 6923 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6924 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6925 i++, s++, o++) 6926 *s -= *o; 6927 } 6928 6929 /** 6930 * t4_get_port_stats - collect port statistics 6931 * @adap: the adapter 6932 * @idx: the port index 6933 * @p: the stats structure to fill 6934 * 6935 * Collect statistics related to the given port from HW. 6936 */ 6937 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6938 { 6939 struct port_info *pi = adap->port[idx]; 6940 u32 bgmap = pi->mps_bg_map; 6941 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6942 6943 #define GET_STAT(name) \ 6944 t4_read_reg64(adap, \ 6945 (is_t4(adap) ? PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L) : \ 6946 T5_PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_##name##_L))) 6947 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6948 6949 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6950 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6951 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6952 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6953 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6954 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6955 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6956 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6957 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6958 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6959 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6960 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6961 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6962 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6963 p->tx_drop = GET_STAT(TX_PORT_DROP); 6964 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6965 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6966 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6967 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6968 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6969 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6970 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6971 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6972 6973 if (chip_id(adap) >= CHELSIO_T5) { 6974 if (stat_ctl & F_COUNTPAUSESTATTX) { 6975 p->tx_frames -= p->tx_pause; 6976 p->tx_octets -= p->tx_pause * 64; 6977 } 6978 if (stat_ctl & F_COUNTPAUSEMCTX) 6979 p->tx_mcast_frames -= p->tx_pause; 6980 } 6981 6982 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6983 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6984 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6985 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6986 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6987 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6988 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6989 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6990 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6991 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6992 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6993 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6994 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6995 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6996 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6997 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6998 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6999 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 7000 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 7001 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 7002 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 7003 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 7004 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 7005 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 7006 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 7007 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 7008 7009 if (pi->fcs_reg != -1) 7010 p->rx_fcs_err = t4_read_reg64(adap, pi->fcs_reg) - pi->fcs_base; 7011 7012 if (chip_id(adap) >= CHELSIO_T5) { 7013 if (stat_ctl & F_COUNTPAUSESTATRX) { 7014 p->rx_frames -= p->rx_pause; 7015 p->rx_octets -= p->rx_pause * 64; 7016 } 7017 if (stat_ctl & F_COUNTPAUSEMCRX) 7018 p->rx_mcast_frames -= p->rx_pause; 7019 } 7020 7021 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 7022 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 7023 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 7024 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 7025 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 7026 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 7027 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 7028 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 7029 7030 #undef GET_STAT 7031 #undef GET_STAT_COM 7032 } 7033 7034 /** 7035 * t4_get_lb_stats - collect loopback port statistics 7036 * @adap: the adapter 7037 * @idx: the loopback port index 7038 * @p: the stats structure to fill 7039 * 7040 * Return HW statistics for the given loopback port. 7041 */ 7042 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 7043 { 7044 7045 #define GET_STAT(name) \ 7046 t4_read_reg64(adap, \ 7047 (is_t4(adap) ? \ 7048 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 7049 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 7050 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 7051 7052 p->octets = GET_STAT(BYTES); 7053 p->frames = GET_STAT(FRAMES); 7054 p->bcast_frames = GET_STAT(BCAST); 7055 p->mcast_frames = GET_STAT(MCAST); 7056 p->ucast_frames = GET_STAT(UCAST); 7057 p->error_frames = GET_STAT(ERROR); 7058 7059 p->frames_64 = GET_STAT(64B); 7060 p->frames_65_127 = GET_STAT(65B_127B); 7061 p->frames_128_255 = GET_STAT(128B_255B); 7062 p->frames_256_511 = GET_STAT(256B_511B); 7063 p->frames_512_1023 = GET_STAT(512B_1023B); 7064 p->frames_1024_1518 = GET_STAT(1024B_1518B); 7065 p->frames_1519_max = GET_STAT(1519B_MAX); 7066 p->drop = GET_STAT(DROP_FRAMES); 7067 7068 if (idx < adap->params.nports) { 7069 u32 bg = adap2pinfo(adap, idx)->mps_bg_map; 7070 7071 p->ovflow0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 7072 p->ovflow1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 7073 p->ovflow2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 7074 p->ovflow3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 7075 p->trunc0 = (bg & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 7076 p->trunc1 = (bg & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 7077 p->trunc2 = (bg & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 7078 p->trunc3 = (bg & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 7079 } 7080 7081 #undef GET_STAT 7082 #undef GET_STAT_COM 7083 } 7084 7085 /** 7086 * t4_wol_magic_enable - enable/disable magic packet WoL 7087 * @adap: the adapter 7088 * @port: the physical port index 7089 * @addr: MAC address expected in magic packets, %NULL to disable 7090 * 7091 * Enables/disables magic packet wake-on-LAN for the selected port. 7092 */ 7093 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 7094 const u8 *addr) 7095 { 7096 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 7097 7098 if (is_t4(adap)) { 7099 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 7100 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 7101 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7102 } else { 7103 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 7104 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 7105 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7106 } 7107 7108 if (addr) { 7109 t4_write_reg(adap, mag_id_reg_l, 7110 (addr[2] << 24) | (addr[3] << 16) | 7111 (addr[4] << 8) | addr[5]); 7112 t4_write_reg(adap, mag_id_reg_h, 7113 (addr[0] << 8) | addr[1]); 7114 } 7115 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 7116 V_MAGICEN(addr != NULL)); 7117 } 7118 7119 /** 7120 * t4_wol_pat_enable - enable/disable pattern-based WoL 7121 * @adap: the adapter 7122 * @port: the physical port index 7123 * @map: bitmap of which HW pattern filters to set 7124 * @mask0: byte mask for bytes 0-63 of a packet 7125 * @mask1: byte mask for bytes 64-127 of a packet 7126 * @crc: Ethernet CRC for selected bytes 7127 * @enable: enable/disable switch 7128 * 7129 * Sets the pattern filters indicated in @map to mask out the bytes 7130 * specified in @mask0/@mask1 in received packets and compare the CRC of 7131 * the resulting packet against @crc. If @enable is %true pattern-based 7132 * WoL is enabled, otherwise disabled. 7133 */ 7134 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 7135 u64 mask0, u64 mask1, unsigned int crc, bool enable) 7136 { 7137 int i; 7138 u32 port_cfg_reg; 7139 7140 if (is_t4(adap)) 7141 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 7142 else 7143 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 7144 7145 if (!enable) { 7146 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 7147 return 0; 7148 } 7149 if (map > 0xff) 7150 return -EINVAL; 7151 7152 #define EPIO_REG(name) \ 7153 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 7154 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 7155 7156 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 7157 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 7158 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 7159 7160 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 7161 if (!(map & 1)) 7162 continue; 7163 7164 /* write byte masks */ 7165 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 7166 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 7167 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7168 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7169 return -ETIMEDOUT; 7170 7171 /* write CRC */ 7172 t4_write_reg(adap, EPIO_REG(DATA0), crc); 7173 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 7174 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 7175 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 7176 return -ETIMEDOUT; 7177 } 7178 #undef EPIO_REG 7179 7180 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 7181 return 0; 7182 } 7183 7184 /* t4_mk_filtdelwr - create a delete filter WR 7185 * @ftid: the filter ID 7186 * @wr: the filter work request to populate 7187 * @qid: ingress queue to receive the delete notification 7188 * 7189 * Creates a filter work request to delete the supplied filter. If @qid is 7190 * negative the delete notification is suppressed. 7191 */ 7192 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 7193 { 7194 memset(wr, 0, sizeof(*wr)); 7195 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 7196 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 7197 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 7198 V_FW_FILTER_WR_NOREPLY(qid < 0)); 7199 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 7200 if (qid >= 0) 7201 wr->rx_chan_rx_rpl_iq = 7202 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 7203 } 7204 7205 #define INIT_CMD(var, cmd, rd_wr) do { \ 7206 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 7207 F_FW_CMD_REQUEST | \ 7208 F_FW_CMD_##rd_wr); \ 7209 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 7210 } while (0) 7211 7212 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 7213 u32 addr, u32 val) 7214 { 7215 u32 ldst_addrspace; 7216 struct fw_ldst_cmd c; 7217 7218 memset(&c, 0, sizeof(c)); 7219 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 7220 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7221 F_FW_CMD_REQUEST | 7222 F_FW_CMD_WRITE | 7223 ldst_addrspace); 7224 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7225 c.u.addrval.addr = cpu_to_be32(addr); 7226 c.u.addrval.val = cpu_to_be32(val); 7227 7228 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7229 } 7230 7231 /** 7232 * t4_mdio_rd - read a PHY register through MDIO 7233 * @adap: the adapter 7234 * @mbox: mailbox to use for the FW command 7235 * @phy_addr: the PHY address 7236 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7237 * @reg: the register to read 7238 * @valp: where to store the value 7239 * 7240 * Issues a FW command through the given mailbox to read a PHY register. 7241 */ 7242 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7243 unsigned int mmd, unsigned int reg, unsigned int *valp) 7244 { 7245 int ret; 7246 u32 ldst_addrspace; 7247 struct fw_ldst_cmd c; 7248 7249 memset(&c, 0, sizeof(c)); 7250 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7251 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7252 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7253 ldst_addrspace); 7254 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7255 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7256 V_FW_LDST_CMD_MMD(mmd)); 7257 c.u.mdio.raddr = cpu_to_be16(reg); 7258 7259 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7260 if (ret == 0) 7261 *valp = be16_to_cpu(c.u.mdio.rval); 7262 return ret; 7263 } 7264 7265 /** 7266 * t4_mdio_wr - write a PHY register through MDIO 7267 * @adap: the adapter 7268 * @mbox: mailbox to use for the FW command 7269 * @phy_addr: the PHY address 7270 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 7271 * @reg: the register to write 7272 * @valp: value to write 7273 * 7274 * Issues a FW command through the given mailbox to write a PHY register. 7275 */ 7276 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 7277 unsigned int mmd, unsigned int reg, unsigned int val) 7278 { 7279 u32 ldst_addrspace; 7280 struct fw_ldst_cmd c; 7281 7282 memset(&c, 0, sizeof(c)); 7283 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 7284 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7285 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7286 ldst_addrspace); 7287 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7288 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 7289 V_FW_LDST_CMD_MMD(mmd)); 7290 c.u.mdio.raddr = cpu_to_be16(reg); 7291 c.u.mdio.rval = cpu_to_be16(val); 7292 7293 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7294 } 7295 7296 /** 7297 * 7298 * t4_sge_decode_idma_state - decode the idma state 7299 * @adap: the adapter 7300 * @state: the state idma is stuck in 7301 */ 7302 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 7303 { 7304 static const char * const t4_decode[] = { 7305 "IDMA_IDLE", 7306 "IDMA_PUSH_MORE_CPL_FIFO", 7307 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7308 "Not used", 7309 "IDMA_PHYSADDR_SEND_PCIEHDR", 7310 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7311 "IDMA_PHYSADDR_SEND_PAYLOAD", 7312 "IDMA_SEND_FIFO_TO_IMSG", 7313 "IDMA_FL_REQ_DATA_FL_PREP", 7314 "IDMA_FL_REQ_DATA_FL", 7315 "IDMA_FL_DROP", 7316 "IDMA_FL_H_REQ_HEADER_FL", 7317 "IDMA_FL_H_SEND_PCIEHDR", 7318 "IDMA_FL_H_PUSH_CPL_FIFO", 7319 "IDMA_FL_H_SEND_CPL", 7320 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7321 "IDMA_FL_H_SEND_IP_HDR", 7322 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7323 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7324 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7325 "IDMA_FL_D_SEND_PCIEHDR", 7326 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7327 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7328 "IDMA_FL_SEND_PCIEHDR", 7329 "IDMA_FL_PUSH_CPL_FIFO", 7330 "IDMA_FL_SEND_CPL", 7331 "IDMA_FL_SEND_PAYLOAD_FIRST", 7332 "IDMA_FL_SEND_PAYLOAD", 7333 "IDMA_FL_REQ_NEXT_DATA_FL", 7334 "IDMA_FL_SEND_NEXT_PCIEHDR", 7335 "IDMA_FL_SEND_PADDING", 7336 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7337 "IDMA_FL_SEND_FIFO_TO_IMSG", 7338 "IDMA_FL_REQ_DATAFL_DONE", 7339 "IDMA_FL_REQ_HEADERFL_DONE", 7340 }; 7341 static const char * const t5_decode[] = { 7342 "IDMA_IDLE", 7343 "IDMA_ALMOST_IDLE", 7344 "IDMA_PUSH_MORE_CPL_FIFO", 7345 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7346 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7347 "IDMA_PHYSADDR_SEND_PCIEHDR", 7348 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7349 "IDMA_PHYSADDR_SEND_PAYLOAD", 7350 "IDMA_SEND_FIFO_TO_IMSG", 7351 "IDMA_FL_REQ_DATA_FL", 7352 "IDMA_FL_DROP", 7353 "IDMA_FL_DROP_SEND_INC", 7354 "IDMA_FL_H_REQ_HEADER_FL", 7355 "IDMA_FL_H_SEND_PCIEHDR", 7356 "IDMA_FL_H_PUSH_CPL_FIFO", 7357 "IDMA_FL_H_SEND_CPL", 7358 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7359 "IDMA_FL_H_SEND_IP_HDR", 7360 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7361 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7362 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7363 "IDMA_FL_D_SEND_PCIEHDR", 7364 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7365 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7366 "IDMA_FL_SEND_PCIEHDR", 7367 "IDMA_FL_PUSH_CPL_FIFO", 7368 "IDMA_FL_SEND_CPL", 7369 "IDMA_FL_SEND_PAYLOAD_FIRST", 7370 "IDMA_FL_SEND_PAYLOAD", 7371 "IDMA_FL_REQ_NEXT_DATA_FL", 7372 "IDMA_FL_SEND_NEXT_PCIEHDR", 7373 "IDMA_FL_SEND_PADDING", 7374 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7375 }; 7376 static const char * const t6_decode[] = { 7377 "IDMA_IDLE", 7378 "IDMA_PUSH_MORE_CPL_FIFO", 7379 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 7380 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 7381 "IDMA_PHYSADDR_SEND_PCIEHDR", 7382 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 7383 "IDMA_PHYSADDR_SEND_PAYLOAD", 7384 "IDMA_FL_REQ_DATA_FL", 7385 "IDMA_FL_DROP", 7386 "IDMA_FL_DROP_SEND_INC", 7387 "IDMA_FL_H_REQ_HEADER_FL", 7388 "IDMA_FL_H_SEND_PCIEHDR", 7389 "IDMA_FL_H_PUSH_CPL_FIFO", 7390 "IDMA_FL_H_SEND_CPL", 7391 "IDMA_FL_H_SEND_IP_HDR_FIRST", 7392 "IDMA_FL_H_SEND_IP_HDR", 7393 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 7394 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 7395 "IDMA_FL_H_SEND_IP_HDR_PADDING", 7396 "IDMA_FL_D_SEND_PCIEHDR", 7397 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 7398 "IDMA_FL_D_REQ_NEXT_DATA_FL", 7399 "IDMA_FL_SEND_PCIEHDR", 7400 "IDMA_FL_PUSH_CPL_FIFO", 7401 "IDMA_FL_SEND_CPL", 7402 "IDMA_FL_SEND_PAYLOAD_FIRST", 7403 "IDMA_FL_SEND_PAYLOAD", 7404 "IDMA_FL_REQ_NEXT_DATA_FL", 7405 "IDMA_FL_SEND_NEXT_PCIEHDR", 7406 "IDMA_FL_SEND_PADDING", 7407 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 7408 }; 7409 static const u32 sge_regs[] = { 7410 A_SGE_DEBUG_DATA_LOW_INDEX_2, 7411 A_SGE_DEBUG_DATA_LOW_INDEX_3, 7412 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 7413 }; 7414 const char * const *sge_idma_decode; 7415 int sge_idma_decode_nstates; 7416 int i; 7417 unsigned int chip_version = chip_id(adapter); 7418 7419 /* Select the right set of decode strings to dump depending on the 7420 * adapter chip type. 7421 */ 7422 switch (chip_version) { 7423 case CHELSIO_T4: 7424 sge_idma_decode = (const char * const *)t4_decode; 7425 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 7426 break; 7427 7428 case CHELSIO_T5: 7429 sge_idma_decode = (const char * const *)t5_decode; 7430 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 7431 break; 7432 7433 case CHELSIO_T6: 7434 sge_idma_decode = (const char * const *)t6_decode; 7435 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 7436 break; 7437 7438 default: 7439 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 7440 return; 7441 } 7442 7443 if (state < sge_idma_decode_nstates) 7444 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 7445 else 7446 CH_WARN(adapter, "idma state %d unknown\n", state); 7447 7448 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 7449 CH_WARN(adapter, "SGE register %#x value %#x\n", 7450 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 7451 } 7452 7453 /** 7454 * t4_sge_ctxt_flush - flush the SGE context cache 7455 * @adap: the adapter 7456 * @mbox: mailbox to use for the FW command 7457 * 7458 * Issues a FW command through the given mailbox to flush the 7459 * SGE context cache. 7460 */ 7461 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type) 7462 { 7463 int ret; 7464 u32 ldst_addrspace; 7465 struct fw_ldst_cmd c; 7466 7467 memset(&c, 0, sizeof(c)); 7468 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(ctxt_type == CTXT_EGRESS ? 7469 FW_LDST_ADDRSPC_SGE_EGRC : 7470 FW_LDST_ADDRSPC_SGE_INGC); 7471 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 7472 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7473 ldst_addrspace); 7474 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 7475 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 7476 7477 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7478 return ret; 7479 } 7480 7481 /** 7482 * t4_fw_hello - establish communication with FW 7483 * @adap: the adapter 7484 * @mbox: mailbox to use for the FW command 7485 * @evt_mbox: mailbox to receive async FW events 7486 * @master: specifies the caller's willingness to be the device master 7487 * @state: returns the current device state (if non-NULL) 7488 * 7489 * Issues a command to establish communication with FW. Returns either 7490 * an error (negative integer) or the mailbox of the Master PF. 7491 */ 7492 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 7493 enum dev_master master, enum dev_state *state) 7494 { 7495 int ret; 7496 struct fw_hello_cmd c; 7497 u32 v; 7498 unsigned int master_mbox; 7499 int retries = FW_CMD_HELLO_RETRIES; 7500 7501 retry: 7502 memset(&c, 0, sizeof(c)); 7503 INIT_CMD(c, HELLO, WRITE); 7504 c.err_to_clearinit = cpu_to_be32( 7505 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 7506 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 7507 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 7508 mbox : M_FW_HELLO_CMD_MBMASTER) | 7509 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 7510 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 7511 F_FW_HELLO_CMD_CLEARINIT); 7512 7513 /* 7514 * Issue the HELLO command to the firmware. If it's not successful 7515 * but indicates that we got a "busy" or "timeout" condition, retry 7516 * the HELLO until we exhaust our retry limit. If we do exceed our 7517 * retry limit, check to see if the firmware left us any error 7518 * information and report that if so ... 7519 */ 7520 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7521 if (ret != FW_SUCCESS) { 7522 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 7523 goto retry; 7524 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 7525 t4_report_fw_error(adap); 7526 return ret; 7527 } 7528 7529 v = be32_to_cpu(c.err_to_clearinit); 7530 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 7531 if (state) { 7532 if (v & F_FW_HELLO_CMD_ERR) 7533 *state = DEV_STATE_ERR; 7534 else if (v & F_FW_HELLO_CMD_INIT) 7535 *state = DEV_STATE_INIT; 7536 else 7537 *state = DEV_STATE_UNINIT; 7538 } 7539 7540 /* 7541 * If we're not the Master PF then we need to wait around for the 7542 * Master PF Driver to finish setting up the adapter. 7543 * 7544 * Note that we also do this wait if we're a non-Master-capable PF and 7545 * there is no current Master PF; a Master PF may show up momentarily 7546 * and we wouldn't want to fail pointlessly. (This can happen when an 7547 * OS loads lots of different drivers rapidly at the same time). In 7548 * this case, the Master PF returned by the firmware will be 7549 * M_PCIE_FW_MASTER so the test below will work ... 7550 */ 7551 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 7552 master_mbox != mbox) { 7553 int waiting = FW_CMD_HELLO_TIMEOUT; 7554 7555 /* 7556 * Wait for the firmware to either indicate an error or 7557 * initialized state. If we see either of these we bail out 7558 * and report the issue to the caller. If we exhaust the 7559 * "hello timeout" and we haven't exhausted our retries, try 7560 * again. Otherwise bail with a timeout error. 7561 */ 7562 for (;;) { 7563 u32 pcie_fw; 7564 7565 msleep(50); 7566 waiting -= 50; 7567 7568 /* 7569 * If neither Error nor Initialialized are indicated 7570 * by the firmware keep waiting till we exhaust our 7571 * timeout ... and then retry if we haven't exhausted 7572 * our retries ... 7573 */ 7574 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 7575 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 7576 if (waiting <= 0) { 7577 if (retries-- > 0) 7578 goto retry; 7579 7580 return -ETIMEDOUT; 7581 } 7582 continue; 7583 } 7584 7585 /* 7586 * We either have an Error or Initialized condition 7587 * report errors preferentially. 7588 */ 7589 if (state) { 7590 if (pcie_fw & F_PCIE_FW_ERR) 7591 *state = DEV_STATE_ERR; 7592 else if (pcie_fw & F_PCIE_FW_INIT) 7593 *state = DEV_STATE_INIT; 7594 } 7595 7596 /* 7597 * If we arrived before a Master PF was selected and 7598 * there's not a valid Master PF, grab its identity 7599 * for our caller. 7600 */ 7601 if (master_mbox == M_PCIE_FW_MASTER && 7602 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 7603 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 7604 break; 7605 } 7606 } 7607 7608 return master_mbox; 7609 } 7610 7611 /** 7612 * t4_fw_bye - end communication with FW 7613 * @adap: the adapter 7614 * @mbox: mailbox to use for the FW command 7615 * 7616 * Issues a command to terminate communication with FW. 7617 */ 7618 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 7619 { 7620 struct fw_bye_cmd c; 7621 7622 memset(&c, 0, sizeof(c)); 7623 INIT_CMD(c, BYE, WRITE); 7624 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7625 } 7626 7627 /** 7628 * t4_fw_reset - issue a reset to FW 7629 * @adap: the adapter 7630 * @mbox: mailbox to use for the FW command 7631 * @reset: specifies the type of reset to perform 7632 * 7633 * Issues a reset command of the specified type to FW. 7634 */ 7635 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 7636 { 7637 struct fw_reset_cmd c; 7638 7639 memset(&c, 0, sizeof(c)); 7640 INIT_CMD(c, RESET, WRITE); 7641 c.val = cpu_to_be32(reset); 7642 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7643 } 7644 7645 /** 7646 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 7647 * @adap: the adapter 7648 * @mbox: mailbox to use for the FW RESET command (if desired) 7649 * @force: force uP into RESET even if FW RESET command fails 7650 * 7651 * Issues a RESET command to firmware (if desired) with a HALT indication 7652 * and then puts the microprocessor into RESET state. The RESET command 7653 * will only be issued if a legitimate mailbox is provided (mbox <= 7654 * M_PCIE_FW_MASTER). 7655 * 7656 * This is generally used in order for the host to safely manipulate the 7657 * adapter without fear of conflicting with whatever the firmware might 7658 * be doing. The only way out of this state is to RESTART the firmware 7659 * ... 7660 */ 7661 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 7662 { 7663 int ret = 0; 7664 7665 /* 7666 * If a legitimate mailbox is provided, issue a RESET command 7667 * with a HALT indication. 7668 */ 7669 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 7670 struct fw_reset_cmd c; 7671 7672 memset(&c, 0, sizeof(c)); 7673 INIT_CMD(c, RESET, WRITE); 7674 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 7675 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 7676 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7677 } 7678 7679 /* 7680 * Normally we won't complete the operation if the firmware RESET 7681 * command fails but if our caller insists we'll go ahead and put the 7682 * uP into RESET. This can be useful if the firmware is hung or even 7683 * missing ... We'll have to take the risk of putting the uP into 7684 * RESET without the cooperation of firmware in that case. 7685 * 7686 * We also force the firmware's HALT flag to be on in case we bypassed 7687 * the firmware RESET command above or we're dealing with old firmware 7688 * which doesn't have the HALT capability. This will serve as a flag 7689 * for the incoming firmware to know that it's coming out of a HALT 7690 * rather than a RESET ... if it's new enough to understand that ... 7691 */ 7692 if (ret == 0 || force) { 7693 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 7694 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 7695 F_PCIE_FW_HALT); 7696 } 7697 7698 /* 7699 * And we always return the result of the firmware RESET command 7700 * even when we force the uP into RESET ... 7701 */ 7702 return ret; 7703 } 7704 7705 /** 7706 * t4_fw_restart - restart the firmware by taking the uP out of RESET 7707 * @adap: the adapter 7708 * 7709 * Restart firmware previously halted by t4_fw_halt(). On successful 7710 * return the previous PF Master remains as the new PF Master and there 7711 * is no need to issue a new HELLO command, etc. 7712 */ 7713 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 7714 { 7715 int ms; 7716 7717 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 7718 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 7719 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 7720 return FW_SUCCESS; 7721 msleep(100); 7722 ms += 100; 7723 } 7724 7725 return -ETIMEDOUT; 7726 } 7727 7728 /** 7729 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 7730 * @adap: the adapter 7731 * @mbox: mailbox to use for the FW RESET command (if desired) 7732 * @fw_data: the firmware image to write 7733 * @size: image size 7734 * @force: force upgrade even if firmware doesn't cooperate 7735 * 7736 * Perform all of the steps necessary for upgrading an adapter's 7737 * firmware image. Normally this requires the cooperation of the 7738 * existing firmware in order to halt all existing activities 7739 * but if an invalid mailbox token is passed in we skip that step 7740 * (though we'll still put the adapter microprocessor into RESET in 7741 * that case). 7742 * 7743 * On successful return the new firmware will have been loaded and 7744 * the adapter will have been fully RESET losing all previous setup 7745 * state. On unsuccessful return the adapter may be completely hosed ... 7746 * positive errno indicates that the adapter is ~probably~ intact, a 7747 * negative errno indicates that things are looking bad ... 7748 */ 7749 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 7750 const u8 *fw_data, unsigned int size, int force) 7751 { 7752 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7753 unsigned int bootstrap = 7754 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7755 int ret; 7756 7757 if (!t4_fw_matches_chip(adap, fw_hdr)) 7758 return -EINVAL; 7759 7760 if (!bootstrap) { 7761 ret = t4_fw_halt(adap, mbox, force); 7762 if (ret < 0 && !force) 7763 return ret; 7764 } 7765 7766 ret = t4_load_fw(adap, fw_data, size); 7767 if (ret < 0 || bootstrap) 7768 return ret; 7769 7770 return t4_fw_restart(adap, mbox); 7771 } 7772 7773 /** 7774 * t4_fw_initialize - ask FW to initialize the device 7775 * @adap: the adapter 7776 * @mbox: mailbox to use for the FW command 7777 * 7778 * Issues a command to FW to partially initialize the device. This 7779 * performs initialization that generally doesn't depend on user input. 7780 */ 7781 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7782 { 7783 struct fw_initialize_cmd c; 7784 7785 memset(&c, 0, sizeof(c)); 7786 INIT_CMD(c, INITIALIZE, WRITE); 7787 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7788 } 7789 7790 /** 7791 * t4_query_params_rw - query FW or device parameters 7792 * @adap: the adapter 7793 * @mbox: mailbox to use for the FW command 7794 * @pf: the PF 7795 * @vf: the VF 7796 * @nparams: the number of parameters 7797 * @params: the parameter names 7798 * @val: the parameter values 7799 * @rw: Write and read flag 7800 * 7801 * Reads the value of FW or device parameters. Up to 7 parameters can be 7802 * queried at once. 7803 */ 7804 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7805 unsigned int vf, unsigned int nparams, const u32 *params, 7806 u32 *val, int rw) 7807 { 7808 int i, ret; 7809 struct fw_params_cmd c; 7810 __be32 *p = &c.param[0].mnem; 7811 7812 if (nparams > 7) 7813 return -EINVAL; 7814 7815 memset(&c, 0, sizeof(c)); 7816 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7817 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7818 V_FW_PARAMS_CMD_PFN(pf) | 7819 V_FW_PARAMS_CMD_VFN(vf)); 7820 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7821 7822 for (i = 0; i < nparams; i++) { 7823 *p++ = cpu_to_be32(*params++); 7824 if (rw) 7825 *p = cpu_to_be32(*(val + i)); 7826 p++; 7827 } 7828 7829 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7830 if (ret == 0) 7831 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7832 *val++ = be32_to_cpu(*p); 7833 return ret; 7834 } 7835 7836 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7837 unsigned int vf, unsigned int nparams, const u32 *params, 7838 u32 *val) 7839 { 7840 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7841 } 7842 7843 /** 7844 * t4_set_params_timeout - sets FW or device parameters 7845 * @adap: the adapter 7846 * @mbox: mailbox to use for the FW command 7847 * @pf: the PF 7848 * @vf: the VF 7849 * @nparams: the number of parameters 7850 * @params: the parameter names 7851 * @val: the parameter values 7852 * @timeout: the timeout time 7853 * 7854 * Sets the value of FW or device parameters. Up to 7 parameters can be 7855 * specified at once. 7856 */ 7857 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7858 unsigned int pf, unsigned int vf, 7859 unsigned int nparams, const u32 *params, 7860 const u32 *val, int timeout) 7861 { 7862 struct fw_params_cmd c; 7863 __be32 *p = &c.param[0].mnem; 7864 7865 if (nparams > 7) 7866 return -EINVAL; 7867 7868 memset(&c, 0, sizeof(c)); 7869 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7870 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7871 V_FW_PARAMS_CMD_PFN(pf) | 7872 V_FW_PARAMS_CMD_VFN(vf)); 7873 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7874 7875 while (nparams--) { 7876 *p++ = cpu_to_be32(*params++); 7877 *p++ = cpu_to_be32(*val++); 7878 } 7879 7880 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7881 } 7882 7883 /** 7884 * t4_set_params - sets FW or device parameters 7885 * @adap: the adapter 7886 * @mbox: mailbox to use for the FW command 7887 * @pf: the PF 7888 * @vf: the VF 7889 * @nparams: the number of parameters 7890 * @params: the parameter names 7891 * @val: the parameter values 7892 * 7893 * Sets the value of FW or device parameters. Up to 7 parameters can be 7894 * specified at once. 7895 */ 7896 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7897 unsigned int vf, unsigned int nparams, const u32 *params, 7898 const u32 *val) 7899 { 7900 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7901 FW_CMD_MAX_TIMEOUT); 7902 } 7903 7904 /** 7905 * t4_cfg_pfvf - configure PF/VF resource limits 7906 * @adap: the adapter 7907 * @mbox: mailbox to use for the FW command 7908 * @pf: the PF being configured 7909 * @vf: the VF being configured 7910 * @txq: the max number of egress queues 7911 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7912 * @rxqi: the max number of interrupt-capable ingress queues 7913 * @rxq: the max number of interruptless ingress queues 7914 * @tc: the PCI traffic class 7915 * @vi: the max number of virtual interfaces 7916 * @cmask: the channel access rights mask for the PF/VF 7917 * @pmask: the port access rights mask for the PF/VF 7918 * @nexact: the maximum number of exact MPS filters 7919 * @rcaps: read capabilities 7920 * @wxcaps: write/execute capabilities 7921 * 7922 * Configures resource limits and capabilities for a physical or virtual 7923 * function. 7924 */ 7925 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7926 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7927 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7928 unsigned int vi, unsigned int cmask, unsigned int pmask, 7929 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7930 { 7931 struct fw_pfvf_cmd c; 7932 7933 memset(&c, 0, sizeof(c)); 7934 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7935 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7936 V_FW_PFVF_CMD_VFN(vf)); 7937 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7938 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7939 V_FW_PFVF_CMD_NIQ(rxq)); 7940 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7941 V_FW_PFVF_CMD_PMASK(pmask) | 7942 V_FW_PFVF_CMD_NEQ(txq)); 7943 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7944 V_FW_PFVF_CMD_NVI(vi) | 7945 V_FW_PFVF_CMD_NEXACTF(nexact)); 7946 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7947 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7948 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7949 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7950 } 7951 7952 /** 7953 * t4_alloc_vi_func - allocate a virtual interface 7954 * @adap: the adapter 7955 * @mbox: mailbox to use for the FW command 7956 * @port: physical port associated with the VI 7957 * @pf: the PF owning the VI 7958 * @vf: the VF owning the VI 7959 * @nmac: number of MAC addresses needed (1 to 5) 7960 * @mac: the MAC addresses of the VI 7961 * @rss_size: size of RSS table slice associated with this VI 7962 * @portfunc: which Port Application Function MAC Address is desired 7963 * @idstype: Intrusion Detection Type 7964 * 7965 * Allocates a virtual interface for the given physical port. If @mac is 7966 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7967 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7968 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7969 * stored consecutively so the space needed is @nmac * 6 bytes. 7970 * Returns a negative error number or the non-negative VI id. 7971 */ 7972 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7973 unsigned int port, unsigned int pf, unsigned int vf, 7974 unsigned int nmac, u8 *mac, u16 *rss_size, 7975 uint8_t *vfvld, uint16_t *vin, 7976 unsigned int portfunc, unsigned int idstype) 7977 { 7978 int ret; 7979 struct fw_vi_cmd c; 7980 7981 memset(&c, 0, sizeof(c)); 7982 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7983 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7984 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7985 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7986 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7987 V_FW_VI_CMD_FUNC(portfunc)); 7988 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7989 c.nmac = nmac - 1; 7990 if(!rss_size) 7991 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7992 7993 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7994 if (ret) 7995 return ret; 7996 ret = G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7997 7998 if (mac) { 7999 memcpy(mac, c.mac, sizeof(c.mac)); 8000 switch (nmac) { 8001 case 5: 8002 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 8003 case 4: 8004 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 8005 case 3: 8006 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 8007 case 2: 8008 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 8009 } 8010 } 8011 if (rss_size) 8012 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 8013 if (vfvld) { 8014 *vfvld = adap->params.viid_smt_extn_support ? 8015 G_FW_VI_CMD_VFVLD(be32_to_cpu(c.alloc_to_len16)) : 8016 G_FW_VIID_VIVLD(ret); 8017 } 8018 if (vin) { 8019 *vin = adap->params.viid_smt_extn_support ? 8020 G_FW_VI_CMD_VIN(be32_to_cpu(c.alloc_to_len16)) : 8021 G_FW_VIID_VIN(ret); 8022 } 8023 8024 return ret; 8025 } 8026 8027 /** 8028 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 8029 * @adap: the adapter 8030 * @mbox: mailbox to use for the FW command 8031 * @port: physical port associated with the VI 8032 * @pf: the PF owning the VI 8033 * @vf: the VF owning the VI 8034 * @nmac: number of MAC addresses needed (1 to 5) 8035 * @mac: the MAC addresses of the VI 8036 * @rss_size: size of RSS table slice associated with this VI 8037 * 8038 * backwards compatible and convieniance routine to allocate a Virtual 8039 * Interface with a Ethernet Port Application Function and Intrustion 8040 * Detection System disabled. 8041 */ 8042 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 8043 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 8044 u16 *rss_size, uint8_t *vfvld, uint16_t *vin) 8045 { 8046 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 8047 vfvld, vin, FW_VI_FUNC_ETH, 0); 8048 } 8049 8050 /** 8051 * t4_free_vi - free a virtual interface 8052 * @adap: the adapter 8053 * @mbox: mailbox to use for the FW command 8054 * @pf: the PF owning the VI 8055 * @vf: the VF owning the VI 8056 * @viid: virtual interface identifiler 8057 * 8058 * Free a previously allocated virtual interface. 8059 */ 8060 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 8061 unsigned int vf, unsigned int viid) 8062 { 8063 struct fw_vi_cmd c; 8064 8065 memset(&c, 0, sizeof(c)); 8066 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 8067 F_FW_CMD_REQUEST | 8068 F_FW_CMD_EXEC | 8069 V_FW_VI_CMD_PFN(pf) | 8070 V_FW_VI_CMD_VFN(vf)); 8071 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 8072 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 8073 8074 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8075 } 8076 8077 /** 8078 * t4_set_rxmode - set Rx properties of a virtual interface 8079 * @adap: the adapter 8080 * @mbox: mailbox to use for the FW command 8081 * @viid: the VI id 8082 * @mtu: the new MTU or -1 8083 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 8084 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 8085 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 8086 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 8087 * @sleep_ok: if true we may sleep while awaiting command completion 8088 * 8089 * Sets Rx properties of a virtual interface. 8090 */ 8091 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 8092 int mtu, int promisc, int all_multi, int bcast, int vlanex, 8093 bool sleep_ok) 8094 { 8095 struct fw_vi_rxmode_cmd c; 8096 8097 /* convert to FW values */ 8098 if (mtu < 0) 8099 mtu = M_FW_VI_RXMODE_CMD_MTU; 8100 if (promisc < 0) 8101 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 8102 if (all_multi < 0) 8103 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 8104 if (bcast < 0) 8105 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 8106 if (vlanex < 0) 8107 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 8108 8109 memset(&c, 0, sizeof(c)); 8110 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 8111 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8112 V_FW_VI_RXMODE_CMD_VIID(viid)); 8113 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 8114 c.mtu_to_vlanexen = 8115 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 8116 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 8117 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 8118 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 8119 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 8120 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8121 } 8122 8123 /** 8124 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support 8125 * @adap: the adapter 8126 * @viid: the VI id 8127 * @mac: the MAC address 8128 * @mask: the mask 8129 * @vni: the VNI id for the tunnel protocol 8130 * @vni_mask: mask for the VNI id 8131 * @dip_hit: to enable DIP match for the MPS entry 8132 * @lookup_type: MAC address for inner (1) or outer (0) header 8133 * @sleep_ok: call is allowed to sleep 8134 * 8135 * Allocates an MPS entry with specified MAC address and VNI value. 8136 * 8137 * Returns a negative error number or the allocated index for this mac. 8138 */ 8139 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid, 8140 const u8 *addr, const u8 *mask, unsigned int vni, 8141 unsigned int vni_mask, u8 dip_hit, u8 lookup_type, 8142 bool sleep_ok) 8143 { 8144 struct fw_vi_mac_cmd c; 8145 struct fw_vi_mac_vni *p = c.u.exact_vni; 8146 int ret = 0; 8147 u32 val; 8148 8149 memset(&c, 0, sizeof(c)); 8150 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8151 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8152 V_FW_VI_MAC_CMD_VIID(viid)); 8153 val = V_FW_CMD_LEN16(1) | 8154 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC_VNI); 8155 c.freemacs_to_len16 = cpu_to_be32(val); 8156 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8157 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8158 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8159 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask)); 8160 8161 p->lookup_type_to_vni = cpu_to_be32(V_FW_VI_MAC_CMD_VNI(vni) | 8162 V_FW_VI_MAC_CMD_DIP_HIT(dip_hit) | 8163 V_FW_VI_MAC_CMD_LOOKUP_TYPE(lookup_type)); 8164 p->vni_mask_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_VNI_MASK(vni_mask)); 8165 8166 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8167 if (ret == 0) 8168 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8169 return ret; 8170 } 8171 8172 /** 8173 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam 8174 * @adap: the adapter 8175 * @viid: the VI id 8176 * @mac: the MAC address 8177 * @mask: the mask 8178 * @idx: index at which to add this entry 8179 * @port_id: the port index 8180 * @lookup_type: MAC address for inner (1) or outer (0) header 8181 * @sleep_ok: call is allowed to sleep 8182 * 8183 * Adds the mac entry at the specified index using raw mac interface. 8184 * 8185 * Returns a negative error number or the allocated index for this mac. 8186 */ 8187 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid, 8188 const u8 *addr, const u8 *mask, unsigned int idx, 8189 u8 lookup_type, u8 port_id, bool sleep_ok) 8190 { 8191 int ret = 0; 8192 struct fw_vi_mac_cmd c; 8193 struct fw_vi_mac_raw *p = &c.u.raw; 8194 u32 val; 8195 8196 memset(&c, 0, sizeof(c)); 8197 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8198 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8199 V_FW_VI_MAC_CMD_VIID(viid)); 8200 val = V_FW_CMD_LEN16(1) | 8201 V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8202 c.freemacs_to_len16 = cpu_to_be32(val); 8203 8204 /* Specify that this is an inner mac address */ 8205 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx)); 8206 8207 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8208 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8209 V_DATAPORTNUM(port_id)); 8210 /* Lookup mask and port mask */ 8211 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8212 V_DATAPORTNUM(M_DATAPORTNUM)); 8213 8214 /* Copy the address and the mask */ 8215 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8216 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8217 8218 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8219 if (ret == 0) { 8220 ret = G_FW_VI_MAC_CMD_RAW_IDX(be32_to_cpu(p->raw_idx_pkd)); 8221 if (ret != idx) 8222 ret = -ENOMEM; 8223 } 8224 8225 return ret; 8226 } 8227 8228 /** 8229 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 8230 * @adap: the adapter 8231 * @mbox: mailbox to use for the FW command 8232 * @viid: the VI id 8233 * @free: if true any existing filters for this VI id are first removed 8234 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8235 * @addr: the MAC address(es) 8236 * @idx: where to store the index of each allocated filter 8237 * @hash: pointer to hash address filter bitmap 8238 * @sleep_ok: call is allowed to sleep 8239 * 8240 * Allocates an exact-match filter for each of the supplied addresses and 8241 * sets it to the corresponding address. If @idx is not %NULL it should 8242 * have at least @naddr entries, each of which will be set to the index of 8243 * the filter allocated for the corresponding MAC address. If a filter 8244 * could not be allocated for an address its index is set to 0xffff. 8245 * If @hash is not %NULL addresses that fail to allocate an exact filter 8246 * are hashed and update the hash filter bitmap pointed at by @hash. 8247 * 8248 * Returns a negative error number or the number of filters allocated. 8249 */ 8250 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 8251 unsigned int viid, bool free, unsigned int naddr, 8252 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 8253 { 8254 int offset, ret = 0; 8255 struct fw_vi_mac_cmd c; 8256 unsigned int nfilters = 0; 8257 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8258 unsigned int rem = naddr; 8259 8260 if (naddr > max_naddr) 8261 return -EINVAL; 8262 8263 for (offset = 0; offset < naddr ; /**/) { 8264 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8265 ? rem 8266 : ARRAY_SIZE(c.u.exact)); 8267 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8268 u.exact[fw_naddr]), 16); 8269 struct fw_vi_mac_exact *p; 8270 int i; 8271 8272 memset(&c, 0, sizeof(c)); 8273 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8274 F_FW_CMD_REQUEST | 8275 F_FW_CMD_WRITE | 8276 V_FW_CMD_EXEC(free) | 8277 V_FW_VI_MAC_CMD_VIID(viid)); 8278 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 8279 V_FW_CMD_LEN16(len16)); 8280 8281 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8282 p->valid_to_idx = 8283 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8284 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 8285 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8286 } 8287 8288 /* 8289 * It's okay if we run out of space in our MAC address arena. 8290 * Some of the addresses we submit may get stored so we need 8291 * to run through the reply to see what the results were ... 8292 */ 8293 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8294 if (ret && ret != -FW_ENOMEM) 8295 break; 8296 8297 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8298 u16 index = G_FW_VI_MAC_CMD_IDX( 8299 be16_to_cpu(p->valid_to_idx)); 8300 8301 if (idx) 8302 idx[offset+i] = (index >= max_naddr 8303 ? 0xffff 8304 : index); 8305 if (index < max_naddr) 8306 nfilters++; 8307 else if (hash) 8308 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 8309 } 8310 8311 free = false; 8312 offset += fw_naddr; 8313 rem -= fw_naddr; 8314 } 8315 8316 if (ret == 0 || ret == -FW_ENOMEM) 8317 ret = nfilters; 8318 return ret; 8319 } 8320 8321 /** 8322 * t4_free_encap_mac_filt - frees MPS entry at given index 8323 * @adap: the adapter 8324 * @viid: the VI id 8325 * @idx: index of MPS entry to be freed 8326 * @sleep_ok: call is allowed to sleep 8327 * 8328 * Frees the MPS entry at supplied index 8329 * 8330 * Returns a negative error number or zero on success 8331 */ 8332 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid, 8333 int idx, bool sleep_ok) 8334 { 8335 struct fw_vi_mac_exact *p; 8336 struct fw_vi_mac_cmd c; 8337 u8 addr[] = {0,0,0,0,0,0}; 8338 int ret = 0; 8339 u32 exact; 8340 8341 memset(&c, 0, sizeof(c)); 8342 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8343 F_FW_CMD_REQUEST | 8344 F_FW_CMD_WRITE | 8345 V_FW_CMD_EXEC(0) | 8346 V_FW_VI_MAC_CMD_VIID(viid)); 8347 exact = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_EXACTMAC); 8348 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8349 exact | 8350 V_FW_CMD_LEN16(1)); 8351 p = c.u.exact; 8352 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8353 V_FW_VI_MAC_CMD_IDX(idx)); 8354 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8355 8356 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8357 return ret; 8358 } 8359 8360 /** 8361 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam 8362 * @adap: the adapter 8363 * @viid: the VI id 8364 * @addr: the MAC address 8365 * @mask: the mask 8366 * @idx: index of the entry in mps tcam 8367 * @lookup_type: MAC address for inner (1) or outer (0) header 8368 * @port_id: the port index 8369 * @sleep_ok: call is allowed to sleep 8370 * 8371 * Removes the mac entry at the specified index using raw mac interface. 8372 * 8373 * Returns a negative error number on failure. 8374 */ 8375 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid, 8376 const u8 *addr, const u8 *mask, unsigned int idx, 8377 u8 lookup_type, u8 port_id, bool sleep_ok) 8378 { 8379 struct fw_vi_mac_cmd c; 8380 struct fw_vi_mac_raw *p = &c.u.raw; 8381 u32 raw; 8382 8383 memset(&c, 0, sizeof(c)); 8384 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8385 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8386 V_FW_CMD_EXEC(0) | 8387 V_FW_VI_MAC_CMD_VIID(viid)); 8388 raw = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_RAW); 8389 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8390 raw | 8391 V_FW_CMD_LEN16(1)); 8392 8393 p->raw_idx_pkd = cpu_to_be32(V_FW_VI_MAC_CMD_RAW_IDX(idx) | 8394 FW_VI_MAC_ID_BASED_FREE); 8395 8396 /* Lookup Type. Outer header: 0, Inner header: 1 */ 8397 p->data0_pkd = cpu_to_be32(V_DATALKPTYPE(lookup_type) | 8398 V_DATAPORTNUM(port_id)); 8399 /* Lookup mask and port mask */ 8400 p->data0m_pkd = cpu_to_be64(V_DATALKPTYPE(M_DATALKPTYPE) | 8401 V_DATAPORTNUM(M_DATAPORTNUM)); 8402 8403 /* Copy the address and the mask */ 8404 memcpy((u8 *)&p->data1[0] + 2, addr, ETHER_ADDR_LEN); 8405 memcpy((u8 *)&p->data1m[0] + 2, mask, ETHER_ADDR_LEN); 8406 8407 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok); 8408 } 8409 8410 /** 8411 * t4_free_mac_filt - frees exact-match filters of given MAC addresses 8412 * @adap: the adapter 8413 * @mbox: mailbox to use for the FW command 8414 * @viid: the VI id 8415 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 8416 * @addr: the MAC address(es) 8417 * @sleep_ok: call is allowed to sleep 8418 * 8419 * Frees the exact-match filter for each of the supplied addresses 8420 * 8421 * Returns a negative error number or the number of filters freed. 8422 */ 8423 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, 8424 unsigned int viid, unsigned int naddr, 8425 const u8 **addr, bool sleep_ok) 8426 { 8427 int offset, ret = 0; 8428 struct fw_vi_mac_cmd c; 8429 unsigned int nfilters = 0; 8430 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 8431 unsigned int rem = naddr; 8432 8433 if (naddr > max_naddr) 8434 return -EINVAL; 8435 8436 for (offset = 0; offset < (int)naddr ; /**/) { 8437 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 8438 ? rem 8439 : ARRAY_SIZE(c.u.exact)); 8440 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 8441 u.exact[fw_naddr]), 16); 8442 struct fw_vi_mac_exact *p; 8443 int i; 8444 8445 memset(&c, 0, sizeof(c)); 8446 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8447 F_FW_CMD_REQUEST | 8448 F_FW_CMD_WRITE | 8449 V_FW_CMD_EXEC(0) | 8450 V_FW_VI_MAC_CMD_VIID(viid)); 8451 c.freemacs_to_len16 = 8452 cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(0) | 8453 V_FW_CMD_LEN16(len16)); 8454 8455 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) { 8456 p->valid_to_idx = cpu_to_be16( 8457 F_FW_VI_MAC_CMD_VALID | 8458 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 8459 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 8460 } 8461 8462 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 8463 if (ret) 8464 break; 8465 8466 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 8467 u16 index = G_FW_VI_MAC_CMD_IDX( 8468 be16_to_cpu(p->valid_to_idx)); 8469 8470 if (index < max_naddr) 8471 nfilters++; 8472 } 8473 8474 offset += fw_naddr; 8475 rem -= fw_naddr; 8476 } 8477 8478 if (ret == 0) 8479 ret = nfilters; 8480 return ret; 8481 } 8482 8483 /** 8484 * t4_change_mac - modifies the exact-match filter for a MAC address 8485 * @adap: the adapter 8486 * @mbox: mailbox to use for the FW command 8487 * @viid: the VI id 8488 * @idx: index of existing filter for old value of MAC address, or -1 8489 * @addr: the new MAC address value 8490 * @persist: whether a new MAC allocation should be persistent 8491 * @smt_idx: add MAC to SMT and return its index, or NULL 8492 * 8493 * Modifies an exact-match filter and sets it to the new MAC address if 8494 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 8495 * latter case the address is added persistently if @persist is %true. 8496 * 8497 * Note that in general it is not possible to modify the value of a given 8498 * filter so the generic way to modify an address filter is to free the one 8499 * being used by the old address value and allocate a new filter for the 8500 * new address value. 8501 * 8502 * Returns a negative error number or the index of the filter with the new 8503 * MAC value. Note that this index may differ from @idx. 8504 */ 8505 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 8506 int idx, const u8 *addr, bool persist, uint16_t *smt_idx) 8507 { 8508 int ret, mode; 8509 struct fw_vi_mac_cmd c; 8510 struct fw_vi_mac_exact *p = c.u.exact; 8511 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 8512 8513 if (idx < 0) /* new allocation */ 8514 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 8515 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 8516 8517 memset(&c, 0, sizeof(c)); 8518 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8519 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8520 V_FW_VI_MAC_CMD_VIID(viid)); 8521 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 8522 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 8523 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 8524 V_FW_VI_MAC_CMD_IDX(idx)); 8525 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 8526 8527 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 8528 if (ret == 0) { 8529 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 8530 if (ret >= max_mac_addr) 8531 ret = -ENOMEM; 8532 if (smt_idx) { 8533 if (adap->params.viid_smt_extn_support) 8534 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 8535 else { 8536 if (chip_id(adap) <= CHELSIO_T5) 8537 *smt_idx = (viid & M_FW_VIID_VIN) << 1; 8538 else 8539 *smt_idx = viid & M_FW_VIID_VIN; 8540 } 8541 } 8542 } 8543 return ret; 8544 } 8545 8546 /** 8547 * t4_set_addr_hash - program the MAC inexact-match hash filter 8548 * @adap: the adapter 8549 * @mbox: mailbox to use for the FW command 8550 * @viid: the VI id 8551 * @ucast: whether the hash filter should also match unicast addresses 8552 * @vec: the value to be written to the hash filter 8553 * @sleep_ok: call is allowed to sleep 8554 * 8555 * Sets the 64-bit inexact-match hash filter for a virtual interface. 8556 */ 8557 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 8558 bool ucast, u64 vec, bool sleep_ok) 8559 { 8560 struct fw_vi_mac_cmd c; 8561 u32 val; 8562 8563 memset(&c, 0, sizeof(c)); 8564 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 8565 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 8566 V_FW_VI_ENABLE_CMD_VIID(viid)); 8567 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 8568 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 8569 c.freemacs_to_len16 = cpu_to_be32(val); 8570 c.u.hash.hashvec = cpu_to_be64(vec); 8571 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 8572 } 8573 8574 /** 8575 * t4_enable_vi_params - enable/disable a virtual interface 8576 * @adap: the adapter 8577 * @mbox: mailbox to use for the FW command 8578 * @viid: the VI id 8579 * @rx_en: 1=enable Rx, 0=disable Rx 8580 * @tx_en: 1=enable Tx, 0=disable Tx 8581 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 8582 * 8583 * Enables/disables a virtual interface. Note that setting DCB Enable 8584 * only makes sense when enabling a Virtual Interface ... 8585 */ 8586 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 8587 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 8588 { 8589 struct fw_vi_enable_cmd c; 8590 8591 memset(&c, 0, sizeof(c)); 8592 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8593 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8594 V_FW_VI_ENABLE_CMD_VIID(viid)); 8595 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 8596 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 8597 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 8598 FW_LEN16(c)); 8599 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 8600 } 8601 8602 /** 8603 * t4_enable_vi - enable/disable a virtual interface 8604 * @adap: the adapter 8605 * @mbox: mailbox to use for the FW command 8606 * @viid: the VI id 8607 * @rx_en: 1=enable Rx, 0=disable Rx 8608 * @tx_en: 1=enable Tx, 0=disable Tx 8609 * 8610 * Enables/disables a virtual interface. Note that setting DCB Enable 8611 * only makes sense when enabling a Virtual Interface ... 8612 */ 8613 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 8614 bool rx_en, bool tx_en) 8615 { 8616 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 8617 } 8618 8619 /** 8620 * t4_identify_port - identify a VI's port by blinking its LED 8621 * @adap: the adapter 8622 * @mbox: mailbox to use for the FW command 8623 * @viid: the VI id 8624 * @nblinks: how many times to blink LED at 2.5 Hz 8625 * 8626 * Identifies a VI's port by blinking its LED. 8627 */ 8628 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 8629 unsigned int nblinks) 8630 { 8631 struct fw_vi_enable_cmd c; 8632 8633 memset(&c, 0, sizeof(c)); 8634 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 8635 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8636 V_FW_VI_ENABLE_CMD_VIID(viid)); 8637 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 8638 c.blinkdur = cpu_to_be16(nblinks); 8639 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8640 } 8641 8642 /** 8643 * t4_iq_stop - stop an ingress queue and its FLs 8644 * @adap: the adapter 8645 * @mbox: mailbox to use for the FW command 8646 * @pf: the PF owning the queues 8647 * @vf: the VF owning the queues 8648 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8649 * @iqid: ingress queue id 8650 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8651 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8652 * 8653 * Stops an ingress queue and its associated FLs, if any. This causes 8654 * any current or future data/messages destined for these queues to be 8655 * tossed. 8656 */ 8657 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8658 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8659 unsigned int fl0id, unsigned int fl1id) 8660 { 8661 struct fw_iq_cmd c; 8662 8663 memset(&c, 0, sizeof(c)); 8664 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8665 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8666 V_FW_IQ_CMD_VFN(vf)); 8667 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 8668 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8669 c.iqid = cpu_to_be16(iqid); 8670 c.fl0id = cpu_to_be16(fl0id); 8671 c.fl1id = cpu_to_be16(fl1id); 8672 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8673 } 8674 8675 /** 8676 * t4_iq_free - free an ingress queue and its FLs 8677 * @adap: the adapter 8678 * @mbox: mailbox to use for the FW command 8679 * @pf: the PF owning the queues 8680 * @vf: the VF owning the queues 8681 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 8682 * @iqid: ingress queue id 8683 * @fl0id: FL0 queue id or 0xffff if no attached FL0 8684 * @fl1id: FL1 queue id or 0xffff if no attached FL1 8685 * 8686 * Frees an ingress queue and its associated FLs, if any. 8687 */ 8688 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8689 unsigned int vf, unsigned int iqtype, unsigned int iqid, 8690 unsigned int fl0id, unsigned int fl1id) 8691 { 8692 struct fw_iq_cmd c; 8693 8694 memset(&c, 0, sizeof(c)); 8695 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 8696 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 8697 V_FW_IQ_CMD_VFN(vf)); 8698 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 8699 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 8700 c.iqid = cpu_to_be16(iqid); 8701 c.fl0id = cpu_to_be16(fl0id); 8702 c.fl1id = cpu_to_be16(fl1id); 8703 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8704 } 8705 8706 /** 8707 * t4_eth_eq_stop - stop an Ethernet egress queue 8708 * @adap: the adapter 8709 * @mbox: mailbox to use for the FW command 8710 * @pf: the PF owning the queues 8711 * @vf: the VF owning the queues 8712 * @eqid: egress queue id 8713 * 8714 * Stops an Ethernet egress queue. The queue can be reinitialized or 8715 * freed but is not otherwise functional after this call. 8716 */ 8717 int t4_eth_eq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 8718 unsigned int vf, unsigned int eqid) 8719 { 8720 struct fw_eq_eth_cmd c; 8721 8722 memset(&c, 0, sizeof(c)); 8723 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8724 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8725 V_FW_EQ_ETH_CMD_PFN(pf) | 8726 V_FW_EQ_ETH_CMD_VFN(vf)); 8727 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_EQSTOP | FW_LEN16(c)); 8728 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8729 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8730 } 8731 8732 /** 8733 * t4_eth_eq_free - free an Ethernet egress queue 8734 * @adap: the adapter 8735 * @mbox: mailbox to use for the FW command 8736 * @pf: the PF owning the queue 8737 * @vf: the VF owning the queue 8738 * @eqid: egress queue id 8739 * 8740 * Frees an Ethernet egress queue. 8741 */ 8742 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8743 unsigned int vf, unsigned int eqid) 8744 { 8745 struct fw_eq_eth_cmd c; 8746 8747 memset(&c, 0, sizeof(c)); 8748 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 8749 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8750 V_FW_EQ_ETH_CMD_PFN(pf) | 8751 V_FW_EQ_ETH_CMD_VFN(vf)); 8752 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 8753 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 8754 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8755 } 8756 8757 /** 8758 * t4_ctrl_eq_free - free a control egress queue 8759 * @adap: the adapter 8760 * @mbox: mailbox to use for the FW command 8761 * @pf: the PF owning the queue 8762 * @vf: the VF owning the queue 8763 * @eqid: egress queue id 8764 * 8765 * Frees a control egress queue. 8766 */ 8767 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8768 unsigned int vf, unsigned int eqid) 8769 { 8770 struct fw_eq_ctrl_cmd c; 8771 8772 memset(&c, 0, sizeof(c)); 8773 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 8774 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8775 V_FW_EQ_CTRL_CMD_PFN(pf) | 8776 V_FW_EQ_CTRL_CMD_VFN(vf)); 8777 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 8778 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 8779 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8780 } 8781 8782 /** 8783 * t4_ofld_eq_free - free an offload egress queue 8784 * @adap: the adapter 8785 * @mbox: mailbox to use for the FW command 8786 * @pf: the PF owning the queue 8787 * @vf: the VF owning the queue 8788 * @eqid: egress queue id 8789 * 8790 * Frees a control egress queue. 8791 */ 8792 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 8793 unsigned int vf, unsigned int eqid) 8794 { 8795 struct fw_eq_ofld_cmd c; 8796 8797 memset(&c, 0, sizeof(c)); 8798 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 8799 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 8800 V_FW_EQ_OFLD_CMD_PFN(pf) | 8801 V_FW_EQ_OFLD_CMD_VFN(vf)); 8802 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 8803 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 8804 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 8805 } 8806 8807 /** 8808 * t4_link_down_rc_str - return a string for a Link Down Reason Code 8809 * @link_down_rc: Link Down Reason Code 8810 * 8811 * Returns a string representation of the Link Down Reason Code. 8812 */ 8813 const char *t4_link_down_rc_str(unsigned char link_down_rc) 8814 { 8815 static const char *reason[] = { 8816 "Link Down", 8817 "Remote Fault", 8818 "Auto-negotiation Failure", 8819 "Reserved3", 8820 "Insufficient Airflow", 8821 "Unable To Determine Reason", 8822 "No RX Signal Detected", 8823 "Reserved7", 8824 }; 8825 8826 if (link_down_rc >= ARRAY_SIZE(reason)) 8827 return "Bad Reason Code"; 8828 8829 return reason[link_down_rc]; 8830 } 8831 8832 /* 8833 * Return the highest speed set in the port capabilities, in Mb/s. 8834 */ 8835 unsigned int fwcap_to_speed(uint32_t caps) 8836 { 8837 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8838 do { \ 8839 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8840 return __speed; \ 8841 } while (0) 8842 8843 TEST_SPEED_RETURN(400G, 400000); 8844 TEST_SPEED_RETURN(200G, 200000); 8845 TEST_SPEED_RETURN(100G, 100000); 8846 TEST_SPEED_RETURN(50G, 50000); 8847 TEST_SPEED_RETURN(40G, 40000); 8848 TEST_SPEED_RETURN(25G, 25000); 8849 TEST_SPEED_RETURN(10G, 10000); 8850 TEST_SPEED_RETURN(1G, 1000); 8851 TEST_SPEED_RETURN(100M, 100); 8852 8853 #undef TEST_SPEED_RETURN 8854 8855 return 0; 8856 } 8857 8858 /* 8859 * Return the port capabilities bit for the given speed, which is in Mb/s. 8860 */ 8861 uint32_t speed_to_fwcap(unsigned int speed) 8862 { 8863 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 8864 do { \ 8865 if (speed == __speed) \ 8866 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8867 } while (0) 8868 8869 TEST_SPEED_RETURN(400G, 400000); 8870 TEST_SPEED_RETURN(200G, 200000); 8871 TEST_SPEED_RETURN(100G, 100000); 8872 TEST_SPEED_RETURN(50G, 50000); 8873 TEST_SPEED_RETURN(40G, 40000); 8874 TEST_SPEED_RETURN(25G, 25000); 8875 TEST_SPEED_RETURN(10G, 10000); 8876 TEST_SPEED_RETURN(1G, 1000); 8877 TEST_SPEED_RETURN(100M, 100); 8878 8879 #undef TEST_SPEED_RETURN 8880 8881 return 0; 8882 } 8883 8884 /* 8885 * Return the port capabilities bit for the highest speed in the capabilities. 8886 */ 8887 uint32_t fwcap_top_speed(uint32_t caps) 8888 { 8889 #define TEST_SPEED_RETURN(__caps_speed) \ 8890 do { \ 8891 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 8892 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 8893 } while (0) 8894 8895 TEST_SPEED_RETURN(400G); 8896 TEST_SPEED_RETURN(200G); 8897 TEST_SPEED_RETURN(100G); 8898 TEST_SPEED_RETURN(50G); 8899 TEST_SPEED_RETURN(40G); 8900 TEST_SPEED_RETURN(25G); 8901 TEST_SPEED_RETURN(10G); 8902 TEST_SPEED_RETURN(1G); 8903 TEST_SPEED_RETURN(100M); 8904 8905 #undef TEST_SPEED_RETURN 8906 8907 return 0; 8908 } 8909 8910 /** 8911 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 8912 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 8913 * 8914 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 8915 * 32-bit Port Capabilities value. 8916 */ 8917 static uint32_t lstatus_to_fwcap(u32 lstatus) 8918 { 8919 uint32_t linkattr = 0; 8920 8921 /* 8922 * Unfortunately the format of the Link Status in the old 8923 * 16-bit Port Information message isn't the same as the 8924 * 16-bit Port Capabilities bitfield used everywhere else ... 8925 */ 8926 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 8927 linkattr |= FW_PORT_CAP32_FC_RX; 8928 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 8929 linkattr |= FW_PORT_CAP32_FC_TX; 8930 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 8931 linkattr |= FW_PORT_CAP32_SPEED_100M; 8932 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 8933 linkattr |= FW_PORT_CAP32_SPEED_1G; 8934 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 8935 linkattr |= FW_PORT_CAP32_SPEED_10G; 8936 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 8937 linkattr |= FW_PORT_CAP32_SPEED_25G; 8938 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 8939 linkattr |= FW_PORT_CAP32_SPEED_40G; 8940 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 8941 linkattr |= FW_PORT_CAP32_SPEED_100G; 8942 8943 return linkattr; 8944 } 8945 8946 /* 8947 * Updates all fields owned by the common code in port_info and link_config 8948 * based on information provided by the firmware. Does not touch any 8949 * requested_* field. 8950 */ 8951 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 8952 enum fw_port_action action, bool *mod_changed, bool *link_changed) 8953 { 8954 struct link_config old_lc, *lc = &pi->link_cfg; 8955 unsigned char fc; 8956 u32 stat, linkattr; 8957 int old_ptype, old_mtype; 8958 8959 old_ptype = pi->port_type; 8960 old_mtype = pi->mod_type; 8961 old_lc = *lc; 8962 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 8963 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 8964 8965 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 8966 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 8967 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 8968 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 8969 8970 lc->pcaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 8971 lc->acaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 8972 lc->lpacaps = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 8973 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 8974 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 8975 8976 linkattr = lstatus_to_fwcap(stat); 8977 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 8978 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 8979 8980 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 8981 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 8982 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 8983 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 8984 8985 lc->pcaps = be32_to_cpu(p->u.info32.pcaps32); 8986 lc->acaps = be32_to_cpu(p->u.info32.acaps32); 8987 lc->lpacaps = be32_to_cpu(p->u.info32.lpacaps32); 8988 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 8989 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 8990 8991 linkattr = be32_to_cpu(p->u.info32.linkattr32); 8992 } else { 8993 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 8994 return; 8995 } 8996 8997 lc->speed = fwcap_to_speed(linkattr); 8998 lc->fec = fwcap_to_fec(linkattr, true); 8999 9000 fc = 0; 9001 if (linkattr & FW_PORT_CAP32_FC_RX) 9002 fc |= PAUSE_RX; 9003 if (linkattr & FW_PORT_CAP32_FC_TX) 9004 fc |= PAUSE_TX; 9005 lc->fc = fc; 9006 9007 if (mod_changed != NULL) 9008 *mod_changed = false; 9009 if (link_changed != NULL) 9010 *link_changed = false; 9011 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 9012 old_lc.pcaps != lc->pcaps) { 9013 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) 9014 lc->fec_hint = fwcap_to_fec(lc->acaps, true); 9015 if (mod_changed != NULL) 9016 *mod_changed = true; 9017 } 9018 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 9019 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 9020 if (link_changed != NULL) 9021 *link_changed = true; 9022 } 9023 } 9024 9025 /** 9026 * t4_update_port_info - retrieve and update port information if changed 9027 * @pi: the port_info 9028 * 9029 * We issue a Get Port Information Command to the Firmware and, if 9030 * successful, we check to see if anything is different from what we 9031 * last recorded and update things accordingly. 9032 */ 9033 int t4_update_port_info(struct port_info *pi) 9034 { 9035 struct adapter *sc = pi->adapter; 9036 struct fw_port_cmd cmd; 9037 enum fw_port_action action; 9038 int ret; 9039 9040 memset(&cmd, 0, sizeof(cmd)); 9041 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 9042 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9043 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 9044 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 9045 FW_PORT_ACTION_GET_PORT_INFO; 9046 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 9047 FW_LEN16(cmd)); 9048 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 9049 if (ret) 9050 return ret; 9051 9052 handle_port_info(pi, &cmd, action, NULL, NULL); 9053 return 0; 9054 } 9055 9056 /** 9057 * t4_handle_fw_rpl - process a FW reply message 9058 * @adap: the adapter 9059 * @rpl: start of the FW message 9060 * 9061 * Processes a FW message, such as link state change messages. 9062 */ 9063 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 9064 { 9065 u8 opcode = *(const u8 *)rpl; 9066 const struct fw_port_cmd *p = (const void *)rpl; 9067 enum fw_port_action action = 9068 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 9069 bool mod_changed, link_changed; 9070 9071 if (opcode == FW_PORT_CMD && 9072 (action == FW_PORT_ACTION_GET_PORT_INFO || 9073 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 9074 /* link/module state change message */ 9075 int i; 9076 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 9077 struct port_info *pi = NULL; 9078 9079 for_each_port(adap, i) { 9080 pi = adap2pinfo(adap, i); 9081 if (pi->tx_chan == chan) 9082 break; 9083 } 9084 9085 PORT_LOCK(pi); 9086 handle_port_info(pi, p, action, &mod_changed, &link_changed); 9087 PORT_UNLOCK(pi); 9088 if (mod_changed) 9089 t4_os_portmod_changed(pi); 9090 if (link_changed) { 9091 PORT_LOCK(pi); 9092 t4_os_link_changed(pi); 9093 PORT_UNLOCK(pi); 9094 } 9095 } else { 9096 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 9097 return -EINVAL; 9098 } 9099 return 0; 9100 } 9101 9102 /** 9103 * get_pci_mode - determine a card's PCI mode 9104 * @adapter: the adapter 9105 * @p: where to store the PCI settings 9106 * 9107 * Determines a card's PCI mode and associated parameters, such as speed 9108 * and width. 9109 */ 9110 static void get_pci_mode(struct adapter *adapter, 9111 struct pci_params *p) 9112 { 9113 u16 val; 9114 u32 pcie_cap; 9115 9116 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9117 if (pcie_cap) { 9118 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 9119 p->speed = val & PCI_EXP_LNKSTA_CLS; 9120 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 9121 } 9122 } 9123 9124 struct flash_desc { 9125 u32 vendor_and_model_id; 9126 u32 size_mb; 9127 }; 9128 9129 int t4_get_flash_params(struct adapter *adapter) 9130 { 9131 /* 9132 * Table for non-standard supported Flash parts. Note, all Flash 9133 * parts must have 64KB sectors. 9134 */ 9135 static struct flash_desc supported_flash[] = { 9136 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 9137 }; 9138 9139 int ret; 9140 u32 flashid = 0; 9141 unsigned int part, manufacturer; 9142 unsigned int density, size = 0; 9143 9144 9145 /* 9146 * Issue a Read ID Command to the Flash part. We decode supported 9147 * Flash parts and their sizes from this. There's a newer Query 9148 * Command which can retrieve detailed geometry information but many 9149 * Flash parts don't support it. 9150 */ 9151 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 9152 if (!ret) 9153 ret = sf1_read(adapter, 3, 0, 1, &flashid); 9154 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 9155 if (ret < 0) 9156 return ret; 9157 9158 /* 9159 * Check to see if it's one of our non-standard supported Flash parts. 9160 */ 9161 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 9162 if (supported_flash[part].vendor_and_model_id == flashid) { 9163 adapter->params.sf_size = 9164 supported_flash[part].size_mb; 9165 adapter->params.sf_nsec = 9166 adapter->params.sf_size / SF_SEC_SIZE; 9167 goto found; 9168 } 9169 9170 /* 9171 * Decode Flash part size. The code below looks repetative with 9172 * common encodings, but that's not guaranteed in the JEDEC 9173 * specification for the Read JADEC ID command. The only thing that 9174 * we're guaranteed by the JADEC specification is where the 9175 * Manufacturer ID is in the returned result. After that each 9176 * Manufacturer ~could~ encode things completely differently. 9177 * Note, all Flash parts must have 64KB sectors. 9178 */ 9179 manufacturer = flashid & 0xff; 9180 switch (manufacturer) { 9181 case 0x20: /* Micron/Numonix */ 9182 /* 9183 * This Density -> Size decoding table is taken from Micron 9184 * Data Sheets. 9185 */ 9186 density = (flashid >> 16) & 0xff; 9187 switch (density) { 9188 case 0x14: size = 1 << 20; break; /* 1MB */ 9189 case 0x15: size = 1 << 21; break; /* 2MB */ 9190 case 0x16: size = 1 << 22; break; /* 4MB */ 9191 case 0x17: size = 1 << 23; break; /* 8MB */ 9192 case 0x18: size = 1 << 24; break; /* 16MB */ 9193 case 0x19: size = 1 << 25; break; /* 32MB */ 9194 case 0x20: size = 1 << 26; break; /* 64MB */ 9195 case 0x21: size = 1 << 27; break; /* 128MB */ 9196 case 0x22: size = 1 << 28; break; /* 256MB */ 9197 } 9198 break; 9199 9200 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 9201 /* 9202 * This Density -> Size decoding table is taken from ISSI 9203 * Data Sheets. 9204 */ 9205 density = (flashid >> 16) & 0xff; 9206 switch (density) { 9207 case 0x16: size = 1 << 25; break; /* 32MB */ 9208 case 0x17: size = 1 << 26; break; /* 64MB */ 9209 } 9210 break; 9211 9212 case 0xc2: /* Macronix */ 9213 /* 9214 * This Density -> Size decoding table is taken from Macronix 9215 * Data Sheets. 9216 */ 9217 density = (flashid >> 16) & 0xff; 9218 switch (density) { 9219 case 0x17: size = 1 << 23; break; /* 8MB */ 9220 case 0x18: size = 1 << 24; break; /* 16MB */ 9221 } 9222 break; 9223 9224 case 0xef: /* Winbond */ 9225 /* 9226 * This Density -> Size decoding table is taken from Winbond 9227 * Data Sheets. 9228 */ 9229 density = (flashid >> 16) & 0xff; 9230 switch (density) { 9231 case 0x17: size = 1 << 23; break; /* 8MB */ 9232 case 0x18: size = 1 << 24; break; /* 16MB */ 9233 } 9234 break; 9235 } 9236 9237 /* If we didn't recognize the FLASH part, that's no real issue: the 9238 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 9239 * use a FLASH part which is at least 4MB in size and has 64KB 9240 * sectors. The unrecognized FLASH part is likely to be much larger 9241 * than 4MB, but that's all we really need. 9242 */ 9243 if (size == 0) { 9244 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 9245 size = 1 << 22; 9246 } 9247 9248 /* 9249 * Store decoded Flash size and fall through into vetting code. 9250 */ 9251 adapter->params.sf_size = size; 9252 adapter->params.sf_nsec = size / SF_SEC_SIZE; 9253 9254 found: 9255 /* 9256 * We should ~probably~ reject adapters with FLASHes which are too 9257 * small but we have some legacy FPGAs with small FLASHes that we'd 9258 * still like to use. So instead we emit a scary message ... 9259 */ 9260 if (adapter->params.sf_size < FLASH_MIN_SIZE) 9261 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 9262 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 9263 9264 return 0; 9265 } 9266 9267 static void set_pcie_completion_timeout(struct adapter *adapter, 9268 u8 range) 9269 { 9270 u16 val; 9271 u32 pcie_cap; 9272 9273 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 9274 if (pcie_cap) { 9275 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 9276 val &= 0xfff0; 9277 val |= range ; 9278 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 9279 } 9280 } 9281 9282 const struct chip_params *t4_get_chip_params(int chipid) 9283 { 9284 static const struct chip_params chip_params[] = { 9285 { 9286 /* T4 */ 9287 .nchan = NCHAN, 9288 .pm_stats_cnt = PM_NSTATS, 9289 .cng_ch_bits_log = 2, 9290 .nsched_cls = 15, 9291 .cim_num_obq = CIM_NUM_OBQ, 9292 .filter_opt_len = FILTER_OPT_LEN, 9293 .mps_rplc_size = 128, 9294 .vfcount = 128, 9295 .sge_fl_db = F_DBPRIO, 9296 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 9297 .rss_nentries = RSS_NENTRIES, 9298 }, 9299 { 9300 /* T5 */ 9301 .nchan = NCHAN, 9302 .pm_stats_cnt = PM_NSTATS, 9303 .cng_ch_bits_log = 2, 9304 .nsched_cls = 16, 9305 .cim_num_obq = CIM_NUM_OBQ_T5, 9306 .filter_opt_len = T5_FILTER_OPT_LEN, 9307 .mps_rplc_size = 128, 9308 .vfcount = 128, 9309 .sge_fl_db = F_DBPRIO | F_DBTYPE, 9310 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9311 .rss_nentries = RSS_NENTRIES, 9312 }, 9313 { 9314 /* T6 */ 9315 .nchan = T6_NCHAN, 9316 .pm_stats_cnt = T6_PM_NSTATS, 9317 .cng_ch_bits_log = 3, 9318 .nsched_cls = 16, 9319 .cim_num_obq = CIM_NUM_OBQ_T5, 9320 .filter_opt_len = T5_FILTER_OPT_LEN, 9321 .mps_rplc_size = 256, 9322 .vfcount = 256, 9323 .sge_fl_db = 0, 9324 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 9325 .rss_nentries = T6_RSS_NENTRIES, 9326 }, 9327 }; 9328 9329 chipid -= CHELSIO_T4; 9330 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 9331 return NULL; 9332 9333 return &chip_params[chipid]; 9334 } 9335 9336 /** 9337 * t4_prep_adapter - prepare SW and HW for operation 9338 * @adapter: the adapter 9339 * @buf: temporary space of at least VPD_LEN size provided by the caller. 9340 * 9341 * Initialize adapter SW state for the various HW modules, set initial 9342 * values for some adapter tunables, take PHYs out of reset, and 9343 * initialize the MDIO interface. 9344 */ 9345 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 9346 { 9347 int ret; 9348 uint16_t device_id; 9349 uint32_t pl_rev; 9350 9351 get_pci_mode(adapter, &adapter->params.pci); 9352 9353 pl_rev = t4_read_reg(adapter, A_PL_REV); 9354 adapter->params.chipid = G_CHIPID(pl_rev); 9355 adapter->params.rev = G_REV(pl_rev); 9356 if (adapter->params.chipid == 0) { 9357 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 9358 adapter->params.chipid = CHELSIO_T4; 9359 9360 /* T4A1 chip is not supported */ 9361 if (adapter->params.rev == 1) { 9362 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 9363 return -EINVAL; 9364 } 9365 } 9366 9367 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 9368 if (adapter->chip_params == NULL) 9369 return -EINVAL; 9370 9371 adapter->params.pci.vpd_cap_addr = 9372 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 9373 9374 ret = t4_get_flash_params(adapter); 9375 if (ret < 0) 9376 return ret; 9377 9378 /* Cards with real ASICs have the chipid in the PCIe device id */ 9379 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 9380 if (device_id >> 12 == chip_id(adapter)) 9381 adapter->params.cim_la_size = CIMLA_SIZE; 9382 else { 9383 /* FPGA */ 9384 adapter->params.fpga = 1; 9385 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 9386 } 9387 9388 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 9389 if (ret < 0) 9390 return ret; 9391 9392 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 9393 9394 /* 9395 * Default port and clock for debugging in case we can't reach FW. 9396 */ 9397 adapter->params.nports = 1; 9398 adapter->params.portvec = 1; 9399 adapter->params.vpd.cclk = 50000; 9400 9401 /* Set pci completion timeout value to 4 seconds. */ 9402 set_pcie_completion_timeout(adapter, 0xd); 9403 return 0; 9404 } 9405 9406 /** 9407 * t4_shutdown_adapter - shut down adapter, host & wire 9408 * @adapter: the adapter 9409 * 9410 * Perform an emergency shutdown of the adapter and stop it from 9411 * continuing any further communication on the ports or DMA to the 9412 * host. This is typically used when the adapter and/or firmware 9413 * have crashed and we want to prevent any further accidental 9414 * communication with the rest of the world. This will also force 9415 * the port Link Status to go down -- if register writes work -- 9416 * which should help our peers figure out that we're down. 9417 */ 9418 int t4_shutdown_adapter(struct adapter *adapter) 9419 { 9420 int port; 9421 const bool bt = adapter->bt_map != 0; 9422 9423 t4_intr_disable(adapter); 9424 if (bt) 9425 t4_write_reg(adapter, A_DBG_GPIO_EN, 0xffff0000); 9426 for_each_port(adapter, port) { 9427 u32 a_port_cfg = is_t4(adapter) ? 9428 PORT_REG(port, A_XGMAC_PORT_CFG) : 9429 T5_PORT_REG(port, A_MAC_PORT_CFG); 9430 9431 t4_write_reg(adapter, a_port_cfg, 9432 t4_read_reg(adapter, a_port_cfg) 9433 & ~V_SIGNAL_DET(1)); 9434 if (!bt) { 9435 u32 hss_cfg0 = is_t4(adapter) ? 9436 PORT_REG(port, A_XGMAC_PORT_HSS_CFG0) : 9437 T5_PORT_REG(port, A_MAC_PORT_HSS_CFG0); 9438 t4_set_reg_field(adapter, hss_cfg0, F_HSSPDWNPLLB | 9439 F_HSSPDWNPLLA | F_HSSPLLBYPB | F_HSSPLLBYPA, 9440 F_HSSPDWNPLLB | F_HSSPDWNPLLA | F_HSSPLLBYPB | 9441 F_HSSPLLBYPA); 9442 } 9443 } 9444 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 9445 9446 return 0; 9447 } 9448 9449 /** 9450 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 9451 * @adapter: the adapter 9452 * @qid: the Queue ID 9453 * @qtype: the Ingress or Egress type for @qid 9454 * @user: true if this request is for a user mode queue 9455 * @pbar2_qoffset: BAR2 Queue Offset 9456 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 9457 * 9458 * Returns the BAR2 SGE Queue Registers information associated with the 9459 * indicated Absolute Queue ID. These are passed back in return value 9460 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 9461 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 9462 * 9463 * This may return an error which indicates that BAR2 SGE Queue 9464 * registers aren't available. If an error is not returned, then the 9465 * following values are returned: 9466 * 9467 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 9468 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 9469 * 9470 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 9471 * require the "Inferred Queue ID" ability may be used. E.g. the 9472 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 9473 * then these "Inferred Queue ID" register may not be used. 9474 */ 9475 int t4_bar2_sge_qregs(struct adapter *adapter, 9476 unsigned int qid, 9477 enum t4_bar2_qtype qtype, 9478 int user, 9479 u64 *pbar2_qoffset, 9480 unsigned int *pbar2_qid) 9481 { 9482 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 9483 u64 bar2_page_offset, bar2_qoffset; 9484 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 9485 9486 /* T4 doesn't support BAR2 SGE Queue registers for kernel 9487 * mode queues. 9488 */ 9489 if (!user && is_t4(adapter)) 9490 return -EINVAL; 9491 9492 /* Get our SGE Page Size parameters. 9493 */ 9494 page_shift = adapter->params.sge.page_shift; 9495 page_size = 1 << page_shift; 9496 9497 /* Get the right Queues per Page parameters for our Queue. 9498 */ 9499 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 9500 ? adapter->params.sge.eq_s_qpp 9501 : adapter->params.sge.iq_s_qpp); 9502 qpp_mask = (1 << qpp_shift) - 1; 9503 9504 /* Calculate the basics of the BAR2 SGE Queue register area: 9505 * o The BAR2 page the Queue registers will be in. 9506 * o The BAR2 Queue ID. 9507 * o The BAR2 Queue ID Offset into the BAR2 page. 9508 */ 9509 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 9510 bar2_qid = qid & qpp_mask; 9511 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 9512 9513 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 9514 * hardware will infer the Absolute Queue ID simply from the writes to 9515 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 9516 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 9517 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 9518 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 9519 * from the BAR2 Page and BAR2 Queue ID. 9520 * 9521 * One important censequence of this is that some BAR2 SGE registers 9522 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 9523 * there. But other registers synthesize the SGE Queue ID purely 9524 * from the writes to the registers -- the Write Combined Doorbell 9525 * Buffer is a good example. These BAR2 SGE Registers are only 9526 * available for those BAR2 SGE Register areas where the SGE Absolute 9527 * Queue ID can be inferred from simple writes. 9528 */ 9529 bar2_qoffset = bar2_page_offset; 9530 bar2_qinferred = (bar2_qid_offset < page_size); 9531 if (bar2_qinferred) { 9532 bar2_qoffset += bar2_qid_offset; 9533 bar2_qid = 0; 9534 } 9535 9536 *pbar2_qoffset = bar2_qoffset; 9537 *pbar2_qid = bar2_qid; 9538 return 0; 9539 } 9540 9541 /** 9542 * t4_init_devlog_params - initialize adapter->params.devlog 9543 * @adap: the adapter 9544 * @fw_attach: whether we can talk to the firmware 9545 * 9546 * Initialize various fields of the adapter's Firmware Device Log 9547 * Parameters structure. 9548 */ 9549 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 9550 { 9551 struct devlog_params *dparams = &adap->params.devlog; 9552 u32 pf_dparams; 9553 unsigned int devlog_meminfo; 9554 struct fw_devlog_cmd devlog_cmd; 9555 int ret; 9556 9557 /* If we're dealing with newer firmware, the Device Log Paramerters 9558 * are stored in a designated register which allows us to access the 9559 * Device Log even if we can't talk to the firmware. 9560 */ 9561 pf_dparams = 9562 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 9563 if (pf_dparams) { 9564 unsigned int nentries, nentries128; 9565 9566 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 9567 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 9568 9569 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 9570 nentries = (nentries128 + 1) * 128; 9571 dparams->size = nentries * sizeof(struct fw_devlog_e); 9572 9573 return 0; 9574 } 9575 9576 /* 9577 * For any failing returns ... 9578 */ 9579 memset(dparams, 0, sizeof *dparams); 9580 9581 /* 9582 * If we can't talk to the firmware, there's really nothing we can do 9583 * at this point. 9584 */ 9585 if (!fw_attach) 9586 return -ENXIO; 9587 9588 /* Otherwise, ask the firmware for it's Device Log Parameters. 9589 */ 9590 memset(&devlog_cmd, 0, sizeof devlog_cmd); 9591 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9592 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9593 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9594 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 9595 &devlog_cmd); 9596 if (ret) 9597 return ret; 9598 9599 devlog_meminfo = 9600 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 9601 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 9602 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 9603 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 9604 9605 return 0; 9606 } 9607 9608 /** 9609 * t4_init_sge_params - initialize adap->params.sge 9610 * @adapter: the adapter 9611 * 9612 * Initialize various fields of the adapter's SGE Parameters structure. 9613 */ 9614 int t4_init_sge_params(struct adapter *adapter) 9615 { 9616 u32 r; 9617 struct sge_params *sp = &adapter->params.sge; 9618 unsigned i, tscale = 1; 9619 9620 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 9621 sp->counter_val[0] = G_THRESHOLD_0(r); 9622 sp->counter_val[1] = G_THRESHOLD_1(r); 9623 sp->counter_val[2] = G_THRESHOLD_2(r); 9624 sp->counter_val[3] = G_THRESHOLD_3(r); 9625 9626 if (chip_id(adapter) >= CHELSIO_T6) { 9627 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 9628 tscale = G_TSCALE(r); 9629 if (tscale == 0) 9630 tscale = 1; 9631 else 9632 tscale += 2; 9633 } 9634 9635 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 9636 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 9637 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 9638 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 9639 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 9640 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 9641 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 9642 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 9643 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 9644 9645 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 9646 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 9647 if (is_t4(adapter)) 9648 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 9649 else if (is_t5(adapter)) 9650 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 9651 else 9652 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 9653 9654 /* egress queues: log2 of # of doorbells per BAR2 page */ 9655 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 9656 r >>= S_QUEUESPERPAGEPF0 + 9657 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9658 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 9659 9660 /* ingress queues: log2 of # of doorbells per BAR2 page */ 9661 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 9662 r >>= S_QUEUESPERPAGEPF0 + 9663 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 9664 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 9665 9666 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 9667 r >>= S_HOSTPAGESIZEPF0 + 9668 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 9669 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 9670 9671 r = t4_read_reg(adapter, A_SGE_CONTROL); 9672 sp->sge_control = r; 9673 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 9674 sp->fl_pktshift = G_PKTSHIFT(r); 9675 if (chip_id(adapter) <= CHELSIO_T5) { 9676 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9677 X_INGPADBOUNDARY_SHIFT); 9678 } else { 9679 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 9680 X_T6_INGPADBOUNDARY_SHIFT); 9681 } 9682 if (is_t4(adapter)) 9683 sp->pack_boundary = sp->pad_boundary; 9684 else { 9685 r = t4_read_reg(adapter, A_SGE_CONTROL2); 9686 if (G_INGPACKBOUNDARY(r) == 0) 9687 sp->pack_boundary = 16; 9688 else 9689 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 9690 } 9691 for (i = 0; i < SGE_FLBUF_SIZES; i++) 9692 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 9693 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 9694 9695 return 0; 9696 } 9697 9698 /* Convert the LE's hardware hash mask to a shorter filter mask. */ 9699 static inline uint16_t 9700 hashmask_to_filtermask(uint64_t hashmask, uint16_t filter_mode) 9701 { 9702 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 9703 int i; 9704 uint16_t filter_mask; 9705 uint64_t mask; /* field mask */ 9706 9707 filter_mask = 0; 9708 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 9709 if ((filter_mode & (1 << i)) == 0) 9710 continue; 9711 mask = (1 << width[i]) - 1; 9712 if ((hashmask & mask) == mask) 9713 filter_mask |= 1 << i; 9714 hashmask >>= width[i]; 9715 } 9716 9717 return (filter_mask); 9718 } 9719 9720 /* 9721 * Read and cache the adapter's compressed filter mode and ingress config. 9722 */ 9723 static void 9724 read_filter_mode_and_ingress_config(struct adapter *adap) 9725 { 9726 int rc; 9727 uint32_t v, param[2], val[2]; 9728 struct tp_params *tpp = &adap->params.tp; 9729 uint64_t hash_mask; 9730 9731 param[0] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9732 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9733 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 9734 param[1] = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9735 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 9736 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 9737 rc = -t4_query_params(adap, adap->mbox, adap->pf, 0, 2, param, val); 9738 if (rc == 0) { 9739 tpp->filter_mode = G_FW_PARAMS_PARAM_FILTER_MODE(val[0]); 9740 tpp->filter_mask = G_FW_PARAMS_PARAM_FILTER_MASK(val[0]); 9741 tpp->vnic_mode = val[1]; 9742 } else { 9743 /* 9744 * Old firmware. Read filter mode/mask and ingress config 9745 * straight from the hardware. 9746 */ 9747 t4_tp_pio_read(adap, &v, 1, A_TP_VLAN_PRI_MAP, true); 9748 tpp->filter_mode = v & 0xffff; 9749 9750 hash_mask = 0; 9751 if (chip_id(adap) > CHELSIO_T4) { 9752 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 9753 hash_mask = v; 9754 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 9755 hash_mask |= (u64)v << 32; 9756 } 9757 tpp->filter_mask = hashmask_to_filtermask(hash_mask, 9758 tpp->filter_mode); 9759 9760 t4_tp_pio_read(adap, &v, 1, A_TP_INGRESS_CONFIG, true); 9761 if (v & F_VNIC) 9762 tpp->vnic_mode = FW_VNIC_MODE_PF_VF; 9763 else 9764 tpp->vnic_mode = FW_VNIC_MODE_OUTER_VLAN; 9765 } 9766 9767 /* 9768 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 9769 * shift positions of several elements of the Compressed Filter Tuple 9770 * for this adapter which we need frequently ... 9771 */ 9772 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 9773 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 9774 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 9775 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 9776 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 9777 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 9778 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 9779 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 9780 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 9781 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 9782 } 9783 9784 /** 9785 * t4_init_tp_params - initialize adap->params.tp 9786 * @adap: the adapter 9787 * 9788 * Initialize various fields of the adapter's TP Parameters structure. 9789 */ 9790 int t4_init_tp_params(struct adapter *adap) 9791 { 9792 int chan; 9793 u32 tx_len, rx_len, r, v; 9794 struct tp_params *tpp = &adap->params.tp; 9795 9796 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 9797 tpp->tre = G_TIMERRESOLUTION(v); 9798 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 9799 9800 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 9801 for (chan = 0; chan < MAX_NCHAN; chan++) 9802 tpp->tx_modq[chan] = chan; 9803 9804 read_filter_mode_and_ingress_config(adap); 9805 9806 if (chip_id(adap) > CHELSIO_T5) { 9807 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 9808 tpp->rx_pkt_encap = v & F_CRXPKTENC; 9809 } else 9810 tpp->rx_pkt_encap = false; 9811 9812 rx_len = t4_read_reg(adap, A_TP_PMM_RX_PAGE_SIZE); 9813 tx_len = t4_read_reg(adap, A_TP_PMM_TX_PAGE_SIZE); 9814 9815 r = t4_read_reg(adap, A_TP_PARA_REG2); 9816 rx_len = min(rx_len, G_MAXRXDATA(r)); 9817 tx_len = min(tx_len, G_MAXRXDATA(r)); 9818 9819 r = t4_read_reg(adap, A_TP_PARA_REG7); 9820 v = min(G_PMMAXXFERLEN0(r), G_PMMAXXFERLEN1(r)); 9821 rx_len = min(rx_len, v); 9822 tx_len = min(tx_len, v); 9823 9824 tpp->max_tx_pdu = tx_len; 9825 tpp->max_rx_pdu = rx_len; 9826 9827 return 0; 9828 } 9829 9830 /** 9831 * t4_filter_field_shift - calculate filter field shift 9832 * @adap: the adapter 9833 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 9834 * 9835 * Return the shift position of a filter field within the Compressed 9836 * Filter Tuple. The filter field is specified via its selection bit 9837 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 9838 */ 9839 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 9840 { 9841 const unsigned int filter_mode = adap->params.tp.filter_mode; 9842 unsigned int sel; 9843 int field_shift; 9844 9845 if ((filter_mode & filter_sel) == 0) 9846 return -1; 9847 9848 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 9849 switch (filter_mode & sel) { 9850 case F_FCOE: 9851 field_shift += W_FT_FCOE; 9852 break; 9853 case F_PORT: 9854 field_shift += W_FT_PORT; 9855 break; 9856 case F_VNIC_ID: 9857 field_shift += W_FT_VNIC_ID; 9858 break; 9859 case F_VLAN: 9860 field_shift += W_FT_VLAN; 9861 break; 9862 case F_TOS: 9863 field_shift += W_FT_TOS; 9864 break; 9865 case F_PROTOCOL: 9866 field_shift += W_FT_PROTOCOL; 9867 break; 9868 case F_ETHERTYPE: 9869 field_shift += W_FT_ETHERTYPE; 9870 break; 9871 case F_MACMATCH: 9872 field_shift += W_FT_MACMATCH; 9873 break; 9874 case F_MPSHITTYPE: 9875 field_shift += W_FT_MPSHITTYPE; 9876 break; 9877 case F_FRAGMENTATION: 9878 field_shift += W_FT_FRAGMENTATION; 9879 break; 9880 } 9881 } 9882 return field_shift; 9883 } 9884 9885 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 9886 { 9887 u8 addr[6]; 9888 int ret, i, j; 9889 struct port_info *p = adap2pinfo(adap, port_id); 9890 u32 param, val; 9891 struct vi_info *vi = &p->vi[0]; 9892 9893 for (i = 0, j = -1; i <= p->port_id; i++) { 9894 do { 9895 j++; 9896 } while ((adap->params.portvec & (1 << j)) == 0); 9897 } 9898 9899 p->tx_chan = j; 9900 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 9901 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 9902 p->rx_c_chan = t4_get_rx_c_chan(adap, j); 9903 p->lport = j; 9904 9905 if (!(adap->flags & IS_VF) || 9906 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 9907 t4_update_port_info(p); 9908 } 9909 9910 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &vi->rss_size, 9911 &vi->vfvld, &vi->vin); 9912 if (ret < 0) 9913 return ret; 9914 9915 vi->viid = ret; 9916 t4_os_set_hw_addr(p, addr); 9917 9918 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9919 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 9920 V_FW_PARAMS_PARAM_YZ(vi->viid); 9921 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 9922 if (ret) 9923 vi->rss_base = 0xffff; 9924 else { 9925 /* MPASS((val >> 16) == rss_size); */ 9926 vi->rss_base = val & 0xffff; 9927 } 9928 9929 return 0; 9930 } 9931 9932 /** 9933 * t4_read_cimq_cfg - read CIM queue configuration 9934 * @adap: the adapter 9935 * @base: holds the queue base addresses in bytes 9936 * @size: holds the queue sizes in bytes 9937 * @thres: holds the queue full thresholds in bytes 9938 * 9939 * Returns the current configuration of the CIM queues, starting with 9940 * the IBQs, then the OBQs. 9941 */ 9942 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 9943 { 9944 unsigned int i, v; 9945 int cim_num_obq = adap->chip_params->cim_num_obq; 9946 9947 for (i = 0; i < CIM_NUM_IBQ; i++) { 9948 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 9949 V_QUENUMSELECT(i)); 9950 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9951 /* value is in 256-byte units */ 9952 *base++ = G_CIMQBASE(v) * 256; 9953 *size++ = G_CIMQSIZE(v) * 256; 9954 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 9955 } 9956 for (i = 0; i < cim_num_obq; i++) { 9957 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 9958 V_QUENUMSELECT(i)); 9959 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 9960 /* value is in 256-byte units */ 9961 *base++ = G_CIMQBASE(v) * 256; 9962 *size++ = G_CIMQSIZE(v) * 256; 9963 } 9964 } 9965 9966 /** 9967 * t4_read_cim_ibq - read the contents of a CIM inbound queue 9968 * @adap: the adapter 9969 * @qid: the queue index 9970 * @data: where to store the queue contents 9971 * @n: capacity of @data in 32-bit words 9972 * 9973 * Reads the contents of the selected CIM queue starting at address 0 up 9974 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 9975 * error and the number of 32-bit words actually read on success. 9976 */ 9977 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 9978 { 9979 int i, err, attempts; 9980 unsigned int addr; 9981 const unsigned int nwords = CIM_IBQ_SIZE * 4; 9982 9983 if (qid > 5 || (n & 3)) 9984 return -EINVAL; 9985 9986 addr = qid * nwords; 9987 if (n > nwords) 9988 n = nwords; 9989 9990 /* It might take 3-10ms before the IBQ debug read access is allowed. 9991 * Wait for 1 Sec with a delay of 1 usec. 9992 */ 9993 attempts = 1000000; 9994 9995 for (i = 0; i < n; i++, addr++) { 9996 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 9997 F_IBQDBGEN); 9998 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 9999 attempts, 1); 10000 if (err) 10001 return err; 10002 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 10003 } 10004 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 10005 return i; 10006 } 10007 10008 /** 10009 * t4_read_cim_obq - read the contents of a CIM outbound queue 10010 * @adap: the adapter 10011 * @qid: the queue index 10012 * @data: where to store the queue contents 10013 * @n: capacity of @data in 32-bit words 10014 * 10015 * Reads the contents of the selected CIM queue starting at address 0 up 10016 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 10017 * error and the number of 32-bit words actually read on success. 10018 */ 10019 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 10020 { 10021 int i, err; 10022 unsigned int addr, v, nwords; 10023 int cim_num_obq = adap->chip_params->cim_num_obq; 10024 10025 if ((qid > (cim_num_obq - 1)) || (n & 3)) 10026 return -EINVAL; 10027 10028 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 10029 V_QUENUMSELECT(qid)); 10030 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 10031 10032 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 10033 nwords = G_CIMQSIZE(v) * 64; /* same */ 10034 if (n > nwords) 10035 n = nwords; 10036 10037 for (i = 0; i < n; i++, addr++) { 10038 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 10039 F_OBQDBGEN); 10040 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 10041 2, 1); 10042 if (err) 10043 return err; 10044 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 10045 } 10046 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 10047 return i; 10048 } 10049 10050 enum { 10051 CIM_QCTL_BASE = 0, 10052 CIM_CTL_BASE = 0x2000, 10053 CIM_PBT_ADDR_BASE = 0x2800, 10054 CIM_PBT_LRF_BASE = 0x3000, 10055 CIM_PBT_DATA_BASE = 0x3800 10056 }; 10057 10058 /** 10059 * t4_cim_read - read a block from CIM internal address space 10060 * @adap: the adapter 10061 * @addr: the start address within the CIM address space 10062 * @n: number of words to read 10063 * @valp: where to store the result 10064 * 10065 * Reads a block of 4-byte words from the CIM intenal address space. 10066 */ 10067 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 10068 unsigned int *valp) 10069 { 10070 int ret = 0; 10071 10072 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10073 return -EBUSY; 10074 10075 for ( ; !ret && n--; addr += 4) { 10076 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 10077 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10078 0, 5, 2); 10079 if (!ret) 10080 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 10081 } 10082 return ret; 10083 } 10084 10085 /** 10086 * t4_cim_write - write a block into CIM internal address space 10087 * @adap: the adapter 10088 * @addr: the start address within the CIM address space 10089 * @n: number of words to write 10090 * @valp: set of values to write 10091 * 10092 * Writes a block of 4-byte words into the CIM intenal address space. 10093 */ 10094 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 10095 const unsigned int *valp) 10096 { 10097 int ret = 0; 10098 10099 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 10100 return -EBUSY; 10101 10102 for ( ; !ret && n--; addr += 4) { 10103 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 10104 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 10105 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 10106 0, 5, 2); 10107 } 10108 return ret; 10109 } 10110 10111 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 10112 unsigned int val) 10113 { 10114 return t4_cim_write(adap, addr, 1, &val); 10115 } 10116 10117 /** 10118 * t4_cim_ctl_read - read a block from CIM control region 10119 * @adap: the adapter 10120 * @addr: the start address within the CIM control region 10121 * @n: number of words to read 10122 * @valp: where to store the result 10123 * 10124 * Reads a block of 4-byte words from the CIM control region. 10125 */ 10126 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 10127 unsigned int *valp) 10128 { 10129 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 10130 } 10131 10132 /** 10133 * t4_cim_read_la - read CIM LA capture buffer 10134 * @adap: the adapter 10135 * @la_buf: where to store the LA data 10136 * @wrptr: the HW write pointer within the capture buffer 10137 * 10138 * Reads the contents of the CIM LA buffer with the most recent entry at 10139 * the end of the returned data and with the entry at @wrptr first. 10140 * We try to leave the LA in the running state we find it in. 10141 */ 10142 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 10143 { 10144 int i, ret; 10145 unsigned int cfg, val, idx; 10146 10147 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 10148 if (ret) 10149 return ret; 10150 10151 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 10152 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 10153 if (ret) 10154 return ret; 10155 } 10156 10157 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10158 if (ret) 10159 goto restart; 10160 10161 idx = G_UPDBGLAWRPTR(val); 10162 if (wrptr) 10163 *wrptr = idx; 10164 10165 for (i = 0; i < adap->params.cim_la_size; i++) { 10166 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10167 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 10168 if (ret) 10169 break; 10170 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 10171 if (ret) 10172 break; 10173 if (val & F_UPDBGLARDEN) { 10174 ret = -ETIMEDOUT; 10175 break; 10176 } 10177 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 10178 if (ret) 10179 break; 10180 10181 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 10182 * identify the 32-bit portion of the full 312-bit data 10183 */ 10184 if (is_t6(adap) && (idx & 0xf) >= 9) 10185 idx = (idx & 0xff0) + 0x10; 10186 else 10187 idx++; 10188 /* address can't exceed 0xfff */ 10189 idx &= M_UPDBGLARDPTR; 10190 } 10191 restart: 10192 if (cfg & F_UPDBGLAEN) { 10193 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 10194 cfg & ~F_UPDBGLARDEN); 10195 if (!ret) 10196 ret = r; 10197 } 10198 return ret; 10199 } 10200 10201 /** 10202 * t4_tp_read_la - read TP LA capture buffer 10203 * @adap: the adapter 10204 * @la_buf: where to store the LA data 10205 * @wrptr: the HW write pointer within the capture buffer 10206 * 10207 * Reads the contents of the TP LA buffer with the most recent entry at 10208 * the end of the returned data and with the entry at @wrptr first. 10209 * We leave the LA in the running state we find it in. 10210 */ 10211 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 10212 { 10213 bool last_incomplete; 10214 unsigned int i, cfg, val, idx; 10215 10216 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 10217 if (cfg & F_DBGLAENABLE) /* freeze LA */ 10218 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10219 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 10220 10221 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 10222 idx = G_DBGLAWPTR(val); 10223 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 10224 if (last_incomplete) 10225 idx = (idx + 1) & M_DBGLARPTR; 10226 if (wrptr) 10227 *wrptr = idx; 10228 10229 val &= 0xffff; 10230 val &= ~V_DBGLARPTR(M_DBGLARPTR); 10231 val |= adap->params.tp.la_mask; 10232 10233 for (i = 0; i < TPLA_SIZE; i++) { 10234 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 10235 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 10236 idx = (idx + 1) & M_DBGLARPTR; 10237 } 10238 10239 /* Wipe out last entry if it isn't valid */ 10240 if (last_incomplete) 10241 la_buf[TPLA_SIZE - 1] = ~0ULL; 10242 10243 if (cfg & F_DBGLAENABLE) /* restore running state */ 10244 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 10245 cfg | adap->params.tp.la_mask); 10246 } 10247 10248 /* 10249 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 10250 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 10251 * state for more than the Warning Threshold then we'll issue a warning about 10252 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 10253 * appears to be hung every Warning Repeat second till the situation clears. 10254 * If the situation clears, we'll note that as well. 10255 */ 10256 #define SGE_IDMA_WARN_THRESH 1 10257 #define SGE_IDMA_WARN_REPEAT 300 10258 10259 /** 10260 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 10261 * @adapter: the adapter 10262 * @idma: the adapter IDMA Monitor state 10263 * 10264 * Initialize the state of an SGE Ingress DMA Monitor. 10265 */ 10266 void t4_idma_monitor_init(struct adapter *adapter, 10267 struct sge_idma_monitor_state *idma) 10268 { 10269 /* Initialize the state variables for detecting an SGE Ingress DMA 10270 * hang. The SGE has internal counters which count up on each clock 10271 * tick whenever the SGE finds its Ingress DMA State Engines in the 10272 * same state they were on the previous clock tick. The clock used is 10273 * the Core Clock so we have a limit on the maximum "time" they can 10274 * record; typically a very small number of seconds. For instance, 10275 * with a 600MHz Core Clock, we can only count up to a bit more than 10276 * 7s. So we'll synthesize a larger counter in order to not run the 10277 * risk of having the "timers" overflow and give us the flexibility to 10278 * maintain a Hung SGE State Machine of our own which operates across 10279 * a longer time frame. 10280 */ 10281 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 10282 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 10283 } 10284 10285 /** 10286 * t4_idma_monitor - monitor SGE Ingress DMA state 10287 * @adapter: the adapter 10288 * @idma: the adapter IDMA Monitor state 10289 * @hz: number of ticks/second 10290 * @ticks: number of ticks since the last IDMA Monitor call 10291 */ 10292 void t4_idma_monitor(struct adapter *adapter, 10293 struct sge_idma_monitor_state *idma, 10294 int hz, int ticks) 10295 { 10296 int i, idma_same_state_cnt[2]; 10297 10298 /* Read the SGE Debug Ingress DMA Same State Count registers. These 10299 * are counters inside the SGE which count up on each clock when the 10300 * SGE finds its Ingress DMA State Engines in the same states they 10301 * were in the previous clock. The counters will peg out at 10302 * 0xffffffff without wrapping around so once they pass the 1s 10303 * threshold they'll stay above that till the IDMA state changes. 10304 */ 10305 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 10306 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 10307 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10308 10309 for (i = 0; i < 2; i++) { 10310 u32 debug0, debug11; 10311 10312 /* If the Ingress DMA Same State Counter ("timer") is less 10313 * than 1s, then we can reset our synthesized Stall Timer and 10314 * continue. If we have previously emitted warnings about a 10315 * potential stalled Ingress Queue, issue a note indicating 10316 * that the Ingress Queue has resumed forward progress. 10317 */ 10318 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 10319 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 10320 CH_WARN(adapter, "SGE idma%d, queue %u, " 10321 "resumed after %d seconds\n", 10322 i, idma->idma_qid[i], 10323 idma->idma_stalled[i]/hz); 10324 idma->idma_stalled[i] = 0; 10325 continue; 10326 } 10327 10328 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 10329 * domain. The first time we get here it'll be because we 10330 * passed the 1s Threshold; each additional time it'll be 10331 * because the RX Timer Callback is being fired on its regular 10332 * schedule. 10333 * 10334 * If the stall is below our Potential Hung Ingress Queue 10335 * Warning Threshold, continue. 10336 */ 10337 if (idma->idma_stalled[i] == 0) { 10338 idma->idma_stalled[i] = hz; 10339 idma->idma_warn[i] = 0; 10340 } else { 10341 idma->idma_stalled[i] += ticks; 10342 idma->idma_warn[i] -= ticks; 10343 } 10344 10345 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 10346 continue; 10347 10348 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 10349 */ 10350 if (idma->idma_warn[i] > 0) 10351 continue; 10352 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 10353 10354 /* Read and save the SGE IDMA State and Queue ID information. 10355 * We do this every time in case it changes across time ... 10356 * can't be too careful ... 10357 */ 10358 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 10359 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10360 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 10361 10362 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 10363 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 10364 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 10365 10366 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 10367 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 10368 i, idma->idma_qid[i], idma->idma_state[i], 10369 idma->idma_stalled[i]/hz, 10370 debug0, debug11); 10371 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 10372 } 10373 } 10374 10375 /** 10376 * t4_set_vf_mac - Set MAC address for the specified VF 10377 * @adapter: The adapter 10378 * @pf: the PF used to instantiate the VFs 10379 * @vf: one of the VFs instantiated by the specified PF 10380 * @naddr: the number of MAC addresses 10381 * @addr: the MAC address(es) to be set to the specified VF 10382 */ 10383 int t4_set_vf_mac(struct adapter *adapter, unsigned int pf, unsigned int vf, 10384 unsigned int naddr, u8 *addr) 10385 { 10386 struct fw_acl_mac_cmd cmd; 10387 10388 memset(&cmd, 0, sizeof(cmd)); 10389 cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_MAC_CMD) | 10390 F_FW_CMD_REQUEST | 10391 F_FW_CMD_WRITE | 10392 V_FW_ACL_MAC_CMD_PFN(pf) | 10393 V_FW_ACL_MAC_CMD_VFN(vf)); 10394 10395 /* Note: Do not enable the ACL */ 10396 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd)); 10397 cmd.nmac = naddr; 10398 10399 switch (pf) { 10400 case 3: 10401 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3)); 10402 break; 10403 case 2: 10404 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2)); 10405 break; 10406 case 1: 10407 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1)); 10408 break; 10409 case 0: 10410 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0)); 10411 break; 10412 } 10413 10414 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd); 10415 } 10416 10417 /** 10418 * t4_read_pace_tbl - read the pace table 10419 * @adap: the adapter 10420 * @pace_vals: holds the returned values 10421 * 10422 * Returns the values of TP's pace table in microseconds. 10423 */ 10424 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 10425 { 10426 unsigned int i, v; 10427 10428 for (i = 0; i < NTX_SCHED; i++) { 10429 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 10430 v = t4_read_reg(adap, A_TP_PACE_TABLE); 10431 pace_vals[i] = dack_ticks_to_usec(adap, v); 10432 } 10433 } 10434 10435 /** 10436 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 10437 * @adap: the adapter 10438 * @sched: the scheduler index 10439 * @kbps: the byte rate in Kbps 10440 * @ipg: the interpacket delay in tenths of nanoseconds 10441 * 10442 * Return the current configuration of a HW Tx scheduler. 10443 */ 10444 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 10445 unsigned int *ipg, bool sleep_ok) 10446 { 10447 unsigned int v, addr, bpt, cpt; 10448 10449 if (kbps) { 10450 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 10451 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10452 if (sched & 1) 10453 v >>= 16; 10454 bpt = (v >> 8) & 0xff; 10455 cpt = v & 0xff; 10456 if (!cpt) 10457 *kbps = 0; /* scheduler disabled */ 10458 else { 10459 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 10460 *kbps = (v * bpt) / 125; 10461 } 10462 } 10463 if (ipg) { 10464 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 10465 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 10466 if (sched & 1) 10467 v >>= 16; 10468 v &= 0xffff; 10469 *ipg = (10000 * v) / core_ticks_per_usec(adap); 10470 } 10471 } 10472 10473 /** 10474 * t4_load_cfg - download config file 10475 * @adap: the adapter 10476 * @cfg_data: the cfg text file to write 10477 * @size: text file size 10478 * 10479 * Write the supplied config text file to the card's serial flash. 10480 */ 10481 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 10482 { 10483 int ret, i, n, cfg_addr; 10484 unsigned int addr; 10485 unsigned int flash_cfg_start_sec; 10486 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10487 10488 cfg_addr = t4_flash_cfg_addr(adap); 10489 if (cfg_addr < 0) 10490 return cfg_addr; 10491 10492 addr = cfg_addr; 10493 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10494 10495 if (size > FLASH_CFG_MAX_SIZE) { 10496 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 10497 FLASH_CFG_MAX_SIZE); 10498 return -EFBIG; 10499 } 10500 10501 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 10502 sf_sec_size); 10503 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10504 flash_cfg_start_sec + i - 1); 10505 /* 10506 * If size == 0 then we're simply erasing the FLASH sectors associated 10507 * with the on-adapter Firmware Configuration File. 10508 */ 10509 if (ret || size == 0) 10510 goto out; 10511 10512 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10513 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10514 if ( (size - i) < SF_PAGE_SIZE) 10515 n = size - i; 10516 else 10517 n = SF_PAGE_SIZE; 10518 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 10519 if (ret) 10520 goto out; 10521 10522 addr += SF_PAGE_SIZE; 10523 cfg_data += SF_PAGE_SIZE; 10524 } 10525 10526 out: 10527 if (ret) 10528 CH_ERR(adap, "config file %s failed %d\n", 10529 (size == 0 ? "clear" : "download"), ret); 10530 return ret; 10531 } 10532 10533 /** 10534 * t5_fw_init_extern_mem - initialize the external memory 10535 * @adap: the adapter 10536 * 10537 * Initializes the external memory on T5. 10538 */ 10539 int t5_fw_init_extern_mem(struct adapter *adap) 10540 { 10541 u32 params[1], val[1]; 10542 int ret; 10543 10544 if (!is_t5(adap)) 10545 return 0; 10546 10547 val[0] = 0xff; /* Initialize all MCs */ 10548 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10549 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 10550 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 10551 FW_CMD_MAX_TIMEOUT); 10552 10553 return ret; 10554 } 10555 10556 /* BIOS boot headers */ 10557 typedef struct pci_expansion_rom_header { 10558 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10559 u8 reserved[22]; /* Reserved per processor Architecture data */ 10560 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10561 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 10562 10563 /* Legacy PCI Expansion ROM Header */ 10564 typedef struct legacy_pci_expansion_rom_header { 10565 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 10566 u8 size512; /* Current Image Size in units of 512 bytes */ 10567 u8 initentry_point[4]; 10568 u8 cksum; /* Checksum computed on the entire Image */ 10569 u8 reserved[16]; /* Reserved */ 10570 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 10571 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 10572 10573 /* EFI PCI Expansion ROM Header */ 10574 typedef struct efi_pci_expansion_rom_header { 10575 u8 signature[2]; // ROM signature. The value 0xaa55 10576 u8 initialization_size[2]; /* Units 512. Includes this header */ 10577 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 10578 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 10579 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 10580 u8 compression_type[2]; /* Compression type. */ 10581 /* 10582 * Compression type definition 10583 * 0x0: uncompressed 10584 * 0x1: Compressed 10585 * 0x2-0xFFFF: Reserved 10586 */ 10587 u8 reserved[8]; /* Reserved */ 10588 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 10589 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 10590 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 10591 10592 /* PCI Data Structure Format */ 10593 typedef struct pcir_data_structure { /* PCI Data Structure */ 10594 u8 signature[4]; /* Signature. The string "PCIR" */ 10595 u8 vendor_id[2]; /* Vendor Identification */ 10596 u8 device_id[2]; /* Device Identification */ 10597 u8 vital_product[2]; /* Pointer to Vital Product Data */ 10598 u8 length[2]; /* PCIR Data Structure Length */ 10599 u8 revision; /* PCIR Data Structure Revision */ 10600 u8 class_code[3]; /* Class Code */ 10601 u8 image_length[2]; /* Image Length. Multiple of 512B */ 10602 u8 code_revision[2]; /* Revision Level of Code/Data */ 10603 u8 code_type; /* Code Type. */ 10604 /* 10605 * PCI Expansion ROM Code Types 10606 * 0x00: Intel IA-32, PC-AT compatible. Legacy 10607 * 0x01: Open Firmware standard for PCI. FCODE 10608 * 0x02: Hewlett-Packard PA RISC. HP reserved 10609 * 0x03: EFI Image. EFI 10610 * 0x04-0xFF: Reserved. 10611 */ 10612 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 10613 u8 reserved[2]; /* Reserved */ 10614 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 10615 10616 /* BOOT constants */ 10617 enum { 10618 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 10619 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 10620 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 10621 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 10622 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 10623 VENDOR_ID = 0x1425, /* Vendor ID */ 10624 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 10625 }; 10626 10627 /* 10628 * modify_device_id - Modifies the device ID of the Boot BIOS image 10629 * @adatper: the device ID to write. 10630 * @boot_data: the boot image to modify. 10631 * 10632 * Write the supplied device ID to the boot BIOS image. 10633 */ 10634 static void modify_device_id(int device_id, u8 *boot_data) 10635 { 10636 legacy_pci_exp_rom_header_t *header; 10637 pcir_data_t *pcir_header; 10638 u32 cur_header = 0; 10639 10640 /* 10641 * Loop through all chained images and change the device ID's 10642 */ 10643 while (1) { 10644 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 10645 pcir_header = (pcir_data_t *) &boot_data[cur_header + 10646 le16_to_cpu(*(u16*)header->pcir_offset)]; 10647 10648 /* 10649 * Only modify the Device ID if code type is Legacy or HP. 10650 * 0x00: Okay to modify 10651 * 0x01: FCODE. Do not be modify 10652 * 0x03: Okay to modify 10653 * 0x04-0xFF: Do not modify 10654 */ 10655 if (pcir_header->code_type == 0x00) { 10656 u8 csum = 0; 10657 int i; 10658 10659 /* 10660 * Modify Device ID to match current adatper 10661 */ 10662 *(u16*) pcir_header->device_id = device_id; 10663 10664 /* 10665 * Set checksum temporarily to 0. 10666 * We will recalculate it later. 10667 */ 10668 header->cksum = 0x0; 10669 10670 /* 10671 * Calculate and update checksum 10672 */ 10673 for (i = 0; i < (header->size512 * 512); i++) 10674 csum += (u8)boot_data[cur_header + i]; 10675 10676 /* 10677 * Invert summed value to create the checksum 10678 * Writing new checksum value directly to the boot data 10679 */ 10680 boot_data[cur_header + 7] = -csum; 10681 10682 } else if (pcir_header->code_type == 0x03) { 10683 10684 /* 10685 * Modify Device ID to match current adatper 10686 */ 10687 *(u16*) pcir_header->device_id = device_id; 10688 10689 } 10690 10691 10692 /* 10693 * Check indicator element to identify if this is the last 10694 * image in the ROM. 10695 */ 10696 if (pcir_header->indicator & 0x80) 10697 break; 10698 10699 /* 10700 * Move header pointer up to the next image in the ROM. 10701 */ 10702 cur_header += header->size512 * 512; 10703 } 10704 } 10705 10706 /* 10707 * t4_load_boot - download boot flash 10708 * @adapter: the adapter 10709 * @boot_data: the boot image to write 10710 * @boot_addr: offset in flash to write boot_data 10711 * @size: image size 10712 * 10713 * Write the supplied boot image to the card's serial flash. 10714 * The boot image has the following sections: a 28-byte header and the 10715 * boot image. 10716 */ 10717 int t4_load_boot(struct adapter *adap, u8 *boot_data, 10718 unsigned int boot_addr, unsigned int size) 10719 { 10720 pci_exp_rom_header_t *header; 10721 int pcir_offset ; 10722 pcir_data_t *pcir_header; 10723 int ret, addr; 10724 uint16_t device_id; 10725 unsigned int i; 10726 unsigned int boot_sector = (boot_addr * 1024 ); 10727 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10728 10729 /* 10730 * Make sure the boot image does not encroach on the firmware region 10731 */ 10732 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 10733 CH_ERR(adap, "boot image encroaching on firmware region\n"); 10734 return -EFBIG; 10735 } 10736 10737 /* 10738 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 10739 * and Boot configuration data sections. These 3 boot sections span 10740 * sectors 0 to 7 in flash and live right before the FW image location. 10741 */ 10742 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 10743 sf_sec_size); 10744 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 10745 (boot_sector >> 16) + i - 1); 10746 10747 /* 10748 * If size == 0 then we're simply erasing the FLASH sectors associated 10749 * with the on-adapter option ROM file 10750 */ 10751 if (ret || (size == 0)) 10752 goto out; 10753 10754 /* Get boot header */ 10755 header = (pci_exp_rom_header_t *)boot_data; 10756 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 10757 /* PCIR Data Structure */ 10758 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 10759 10760 /* 10761 * Perform some primitive sanity testing to avoid accidentally 10762 * writing garbage over the boot sectors. We ought to check for 10763 * more but it's not worth it for now ... 10764 */ 10765 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 10766 CH_ERR(adap, "boot image too small/large\n"); 10767 return -EFBIG; 10768 } 10769 10770 #ifndef CHELSIO_T4_DIAGS 10771 /* 10772 * Check BOOT ROM header signature 10773 */ 10774 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 10775 CH_ERR(adap, "Boot image missing signature\n"); 10776 return -EINVAL; 10777 } 10778 10779 /* 10780 * Check PCI header signature 10781 */ 10782 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 10783 CH_ERR(adap, "PCI header missing signature\n"); 10784 return -EINVAL; 10785 } 10786 10787 /* 10788 * Check Vendor ID matches Chelsio ID 10789 */ 10790 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 10791 CH_ERR(adap, "Vendor ID missing signature\n"); 10792 return -EINVAL; 10793 } 10794 #endif 10795 10796 /* 10797 * Retrieve adapter's device ID 10798 */ 10799 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 10800 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 10801 device_id = device_id & 0xf0ff; 10802 10803 /* 10804 * Check PCIE Device ID 10805 */ 10806 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 10807 /* 10808 * Change the device ID in the Boot BIOS image to match 10809 * the Device ID of the current adapter. 10810 */ 10811 modify_device_id(device_id, boot_data); 10812 } 10813 10814 /* 10815 * Skip over the first SF_PAGE_SIZE worth of data and write it after 10816 * we finish copying the rest of the boot image. This will ensure 10817 * that the BIOS boot header will only be written if the boot image 10818 * was written in full. 10819 */ 10820 addr = boot_sector; 10821 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 10822 addr += SF_PAGE_SIZE; 10823 boot_data += SF_PAGE_SIZE; 10824 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 10825 if (ret) 10826 goto out; 10827 } 10828 10829 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 10830 (const u8 *)header, 0); 10831 10832 out: 10833 if (ret) 10834 CH_ERR(adap, "boot image download failed, error %d\n", ret); 10835 return ret; 10836 } 10837 10838 /* 10839 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 10840 * @adapter: the adapter 10841 * 10842 * Return the address within the flash where the OptionROM Configuration 10843 * is stored, or an error if the device FLASH is too small to contain 10844 * a OptionROM Configuration. 10845 */ 10846 static int t4_flash_bootcfg_addr(struct adapter *adapter) 10847 { 10848 /* 10849 * If the device FLASH isn't large enough to hold a Firmware 10850 * Configuration File, return an error. 10851 */ 10852 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 10853 return -ENOSPC; 10854 10855 return FLASH_BOOTCFG_START; 10856 } 10857 10858 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 10859 { 10860 int ret, i, n, cfg_addr; 10861 unsigned int addr; 10862 unsigned int flash_cfg_start_sec; 10863 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 10864 10865 cfg_addr = t4_flash_bootcfg_addr(adap); 10866 if (cfg_addr < 0) 10867 return cfg_addr; 10868 10869 addr = cfg_addr; 10870 flash_cfg_start_sec = addr / SF_SEC_SIZE; 10871 10872 if (size > FLASH_BOOTCFG_MAX_SIZE) { 10873 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 10874 FLASH_BOOTCFG_MAX_SIZE); 10875 return -EFBIG; 10876 } 10877 10878 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 10879 sf_sec_size); 10880 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 10881 flash_cfg_start_sec + i - 1); 10882 10883 /* 10884 * If size == 0 then we're simply erasing the FLASH sectors associated 10885 * with the on-adapter OptionROM Configuration File. 10886 */ 10887 if (ret || size == 0) 10888 goto out; 10889 10890 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 10891 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 10892 if ( (size - i) < SF_PAGE_SIZE) 10893 n = size - i; 10894 else 10895 n = SF_PAGE_SIZE; 10896 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 10897 if (ret) 10898 goto out; 10899 10900 addr += SF_PAGE_SIZE; 10901 cfg_data += SF_PAGE_SIZE; 10902 } 10903 10904 out: 10905 if (ret) 10906 CH_ERR(adap, "boot config data %s failed %d\n", 10907 (size == 0 ? "clear" : "download"), ret); 10908 return ret; 10909 } 10910 10911 /** 10912 * t4_set_filter_cfg - set up filter mode/mask and ingress config. 10913 * @adap: the adapter 10914 * @mode: a bitmap selecting which optional filter components to enable 10915 * @mask: a bitmap selecting which components to enable in filter mask 10916 * @vnic_mode: the ingress config/vnic mode setting 10917 * 10918 * Sets the filter mode and mask by selecting the optional components to 10919 * enable in filter tuples. Returns 0 on success and a negative error if 10920 * the requested mode needs more bits than are available for optional 10921 * components. The filter mask must be a subset of the filter mode. 10922 */ 10923 int t4_set_filter_cfg(struct adapter *adap, int mode, int mask, int vnic_mode) 10924 { 10925 static const uint8_t width[] = {1, 3, 17, 17, 8, 8, 16, 9, 3, 1}; 10926 int i, nbits, rc; 10927 uint32_t param, val; 10928 uint16_t fmode, fmask; 10929 const int maxbits = adap->chip_params->filter_opt_len; 10930 10931 if (mode != -1 || mask != -1) { 10932 if (mode != -1) { 10933 fmode = mode; 10934 nbits = 0; 10935 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10936 if (fmode & (1 << i)) 10937 nbits += width[i]; 10938 } 10939 if (nbits > maxbits) { 10940 CH_ERR(adap, "optional fields in the filter " 10941 "mode (0x%x) add up to %d bits " 10942 "(must be <= %db). Remove some fields and " 10943 "try again.\n", fmode, nbits, maxbits); 10944 return -E2BIG; 10945 } 10946 10947 /* 10948 * Hardware wants the bits to be maxed out. Keep 10949 * setting them until there's no room for more. 10950 */ 10951 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) { 10952 if (fmode & (1 << i)) 10953 continue; 10954 if (nbits + width[i] <= maxbits) { 10955 fmode |= 1 << i; 10956 nbits += width[i]; 10957 if (nbits == maxbits) 10958 break; 10959 } 10960 } 10961 10962 fmask = fmode & adap->params.tp.filter_mask; 10963 if (fmask != adap->params.tp.filter_mask) { 10964 CH_WARN(adap, 10965 "filter mask will be changed from 0x%x to " 10966 "0x%x to comply with the filter mode (0x%x).\n", 10967 adap->params.tp.filter_mask, fmask, fmode); 10968 } 10969 } else { 10970 fmode = adap->params.tp.filter_mode; 10971 fmask = mask; 10972 if ((fmode | fmask) != fmode) { 10973 CH_ERR(adap, 10974 "filter mask (0x%x) must be a subset of " 10975 "the filter mode (0x%x).\n", fmask, fmode); 10976 return -EINVAL; 10977 } 10978 } 10979 10980 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10981 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10982 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_MODE_MASK); 10983 val = V_FW_PARAMS_PARAM_FILTER_MODE(fmode) | 10984 V_FW_PARAMS_PARAM_FILTER_MASK(fmask); 10985 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10986 &val); 10987 if (rc < 0) 10988 return rc; 10989 } 10990 10991 if (vnic_mode != -1) { 10992 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 10993 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FILTER) | 10994 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_FILTER_VNIC_MODE); 10995 val = vnic_mode; 10996 rc = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, 10997 &val); 10998 if (rc < 0) 10999 return rc; 11000 } 11001 11002 /* Refresh. */ 11003 read_filter_mode_and_ingress_config(adap); 11004 11005 return 0; 11006 } 11007 11008 /** 11009 * t4_clr_port_stats - clear port statistics 11010 * @adap: the adapter 11011 * @idx: the port index 11012 * 11013 * Clear HW statistics for the given port. 11014 */ 11015 void t4_clr_port_stats(struct adapter *adap, int idx) 11016 { 11017 unsigned int i; 11018 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 11019 u32 port_base_addr; 11020 11021 if (is_t4(adap)) 11022 port_base_addr = PORT_BASE(idx); 11023 else 11024 port_base_addr = T5_PORT_BASE(idx); 11025 11026 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 11027 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 11028 t4_write_reg(adap, port_base_addr + i, 0); 11029 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 11030 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 11031 t4_write_reg(adap, port_base_addr + i, 0); 11032 for (i = 0; i < 4; i++) 11033 if (bgmap & (1 << i)) { 11034 t4_write_reg(adap, 11035 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 11036 t4_write_reg(adap, 11037 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 11038 } 11039 } 11040 11041 /** 11042 * t4_i2c_io - read/write I2C data from adapter 11043 * @adap: the adapter 11044 * @port: Port number if per-port device; <0 if not 11045 * @devid: per-port device ID or absolute device ID 11046 * @offset: byte offset into device I2C space 11047 * @len: byte length of I2C space data 11048 * @buf: buffer in which to return I2C data for read 11049 * buffer which holds the I2C data for write 11050 * @write: if true, do a write; else do a read 11051 * Reads/Writes the I2C data from/to the indicated device and location. 11052 */ 11053 int t4_i2c_io(struct adapter *adap, unsigned int mbox, 11054 int port, unsigned int devid, 11055 unsigned int offset, unsigned int len, 11056 u8 *buf, bool write) 11057 { 11058 struct fw_ldst_cmd ldst_cmd, ldst_rpl; 11059 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data); 11060 int ret = 0; 11061 11062 if (len > I2C_PAGE_SIZE) 11063 return -EINVAL; 11064 11065 /* Dont allow reads that spans multiple pages */ 11066 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE) 11067 return -EINVAL; 11068 11069 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 11070 ldst_cmd.op_to_addrspace = 11071 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11072 F_FW_CMD_REQUEST | 11073 (write ? F_FW_CMD_WRITE : F_FW_CMD_READ) | 11074 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C)); 11075 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 11076 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port); 11077 ldst_cmd.u.i2c.did = devid; 11078 11079 while (len > 0) { 11080 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max; 11081 11082 ldst_cmd.u.i2c.boffset = offset; 11083 ldst_cmd.u.i2c.blen = i2c_len; 11084 11085 if (write) 11086 memcpy(ldst_cmd.u.i2c.data, buf, i2c_len); 11087 11088 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd), 11089 write ? NULL : &ldst_rpl); 11090 if (ret) 11091 break; 11092 11093 if (!write) 11094 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len); 11095 offset += i2c_len; 11096 buf += i2c_len; 11097 len -= i2c_len; 11098 } 11099 11100 return ret; 11101 } 11102 11103 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 11104 int port, unsigned int devid, 11105 unsigned int offset, unsigned int len, 11106 u8 *buf) 11107 { 11108 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, false); 11109 } 11110 11111 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 11112 int port, unsigned int devid, 11113 unsigned int offset, unsigned int len, 11114 u8 *buf) 11115 { 11116 return t4_i2c_io(adap, mbox, port, devid, offset, len, buf, true); 11117 } 11118 11119 /** 11120 * t4_sge_ctxt_rd - read an SGE context through FW 11121 * @adap: the adapter 11122 * @mbox: mailbox to use for the FW command 11123 * @cid: the context id 11124 * @ctype: the context type 11125 * @data: where to store the context data 11126 * 11127 * Issues a FW command through the given mailbox to read an SGE context. 11128 */ 11129 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 11130 enum ctxt_type ctype, u32 *data) 11131 { 11132 int ret; 11133 struct fw_ldst_cmd c; 11134 11135 if (ctype == CTXT_EGRESS) 11136 ret = FW_LDST_ADDRSPC_SGE_EGRC; 11137 else if (ctype == CTXT_INGRESS) 11138 ret = FW_LDST_ADDRSPC_SGE_INGC; 11139 else if (ctype == CTXT_FLM) 11140 ret = FW_LDST_ADDRSPC_SGE_FLMC; 11141 else 11142 ret = FW_LDST_ADDRSPC_SGE_CONMC; 11143 11144 memset(&c, 0, sizeof(c)); 11145 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 11146 F_FW_CMD_REQUEST | F_FW_CMD_READ | 11147 V_FW_LDST_CMD_ADDRSPACE(ret)); 11148 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 11149 c.u.idctxt.physid = cpu_to_be32(cid); 11150 11151 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11152 if (ret == 0) { 11153 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 11154 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 11155 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 11156 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 11157 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 11158 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 11159 } 11160 return ret; 11161 } 11162 11163 /** 11164 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 11165 * @adap: the adapter 11166 * @cid: the context id 11167 * @ctype: the context type 11168 * @data: where to store the context data 11169 * 11170 * Reads an SGE context directly, bypassing FW. This is only for 11171 * debugging when FW is unavailable. 11172 */ 11173 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 11174 u32 *data) 11175 { 11176 int i, ret; 11177 11178 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 11179 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 11180 if (!ret) 11181 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 11182 *data++ = t4_read_reg(adap, i); 11183 return ret; 11184 } 11185 11186 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 11187 int sleep_ok) 11188 { 11189 struct fw_sched_cmd cmd; 11190 11191 memset(&cmd, 0, sizeof(cmd)); 11192 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11193 F_FW_CMD_REQUEST | 11194 F_FW_CMD_WRITE); 11195 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11196 11197 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 11198 cmd.u.config.type = type; 11199 cmd.u.config.minmaxen = minmaxen; 11200 11201 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11202 NULL, sleep_ok); 11203 } 11204 11205 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 11206 int rateunit, int ratemode, int channel, int cl, 11207 int minrate, int maxrate, int weight, int pktsize, 11208 int burstsize, int sleep_ok) 11209 { 11210 struct fw_sched_cmd cmd; 11211 11212 memset(&cmd, 0, sizeof(cmd)); 11213 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11214 F_FW_CMD_REQUEST | 11215 F_FW_CMD_WRITE); 11216 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11217 11218 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11219 cmd.u.params.type = type; 11220 cmd.u.params.level = level; 11221 cmd.u.params.mode = mode; 11222 cmd.u.params.ch = channel; 11223 cmd.u.params.cl = cl; 11224 cmd.u.params.unit = rateunit; 11225 cmd.u.params.rate = ratemode; 11226 cmd.u.params.min = cpu_to_be32(minrate); 11227 cmd.u.params.max = cpu_to_be32(maxrate); 11228 cmd.u.params.weight = cpu_to_be16(weight); 11229 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11230 cmd.u.params.burstsize = cpu_to_be16(burstsize); 11231 11232 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11233 NULL, sleep_ok); 11234 } 11235 11236 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 11237 unsigned int maxrate, int sleep_ok) 11238 { 11239 struct fw_sched_cmd cmd; 11240 11241 memset(&cmd, 0, sizeof(cmd)); 11242 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11243 F_FW_CMD_REQUEST | 11244 F_FW_CMD_WRITE); 11245 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11246 11247 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11248 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11249 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 11250 cmd.u.params.ch = channel; 11251 cmd.u.params.rate = ratemode; /* REL or ABS */ 11252 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 11253 11254 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11255 NULL, sleep_ok); 11256 } 11257 11258 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 11259 int weight, int sleep_ok) 11260 { 11261 struct fw_sched_cmd cmd; 11262 11263 if (weight < 0 || weight > 100) 11264 return -EINVAL; 11265 11266 memset(&cmd, 0, sizeof(cmd)); 11267 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11268 F_FW_CMD_REQUEST | 11269 F_FW_CMD_WRITE); 11270 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11271 11272 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11273 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11274 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 11275 cmd.u.params.ch = channel; 11276 cmd.u.params.cl = cl; 11277 cmd.u.params.weight = cpu_to_be16(weight); 11278 11279 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11280 NULL, sleep_ok); 11281 } 11282 11283 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 11284 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 11285 { 11286 struct fw_sched_cmd cmd; 11287 11288 memset(&cmd, 0, sizeof(cmd)); 11289 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 11290 F_FW_CMD_REQUEST | 11291 F_FW_CMD_WRITE); 11292 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 11293 11294 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 11295 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 11296 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 11297 cmd.u.params.mode = mode; 11298 cmd.u.params.ch = channel; 11299 cmd.u.params.cl = cl; 11300 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 11301 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 11302 cmd.u.params.max = cpu_to_be32(maxrate); 11303 cmd.u.params.pktsize = cpu_to_be16(pktsize); 11304 11305 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 11306 NULL, sleep_ok); 11307 } 11308 11309 /* 11310 * t4_config_watchdog - configure (enable/disable) a watchdog timer 11311 * @adapter: the adapter 11312 * @mbox: mailbox to use for the FW command 11313 * @pf: the PF owning the queue 11314 * @vf: the VF owning the queue 11315 * @timeout: watchdog timeout in ms 11316 * @action: watchdog timer / action 11317 * 11318 * There are separate watchdog timers for each possible watchdog 11319 * action. Configure one of the watchdog timers by setting a non-zero 11320 * timeout. Disable a watchdog timer by using a timeout of zero. 11321 */ 11322 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 11323 unsigned int pf, unsigned int vf, 11324 unsigned int timeout, unsigned int action) 11325 { 11326 struct fw_watchdog_cmd wdog; 11327 unsigned int ticks; 11328 11329 /* 11330 * The watchdog command expects a timeout in units of 10ms so we need 11331 * to convert it here (via rounding) and force a minimum of one 10ms 11332 * "tick" if the timeout is non-zero but the conversion results in 0 11333 * ticks. 11334 */ 11335 ticks = (timeout + 5)/10; 11336 if (timeout && !ticks) 11337 ticks = 1; 11338 11339 memset(&wdog, 0, sizeof wdog); 11340 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 11341 F_FW_CMD_REQUEST | 11342 F_FW_CMD_WRITE | 11343 V_FW_PARAMS_CMD_PFN(pf) | 11344 V_FW_PARAMS_CMD_VFN(vf)); 11345 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 11346 wdog.timeout = cpu_to_be32(ticks); 11347 wdog.action = cpu_to_be32(action); 11348 11349 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 11350 } 11351 11352 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 11353 { 11354 struct fw_devlog_cmd devlog_cmd; 11355 int ret; 11356 11357 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11358 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11359 F_FW_CMD_REQUEST | F_FW_CMD_READ); 11360 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11361 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11362 sizeof(devlog_cmd), &devlog_cmd); 11363 if (ret) 11364 return ret; 11365 11366 *level = devlog_cmd.level; 11367 return 0; 11368 } 11369 11370 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 11371 { 11372 struct fw_devlog_cmd devlog_cmd; 11373 11374 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 11375 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 11376 F_FW_CMD_REQUEST | 11377 F_FW_CMD_WRITE); 11378 devlog_cmd.level = level; 11379 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 11380 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 11381 sizeof(devlog_cmd), &devlog_cmd); 11382 } 11383 11384 int t4_configure_add_smac(struct adapter *adap) 11385 { 11386 unsigned int param, val; 11387 int ret = 0; 11388 11389 adap->params.smac_add_support = 0; 11390 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11391 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_ADD_SMAC)); 11392 /* Query FW to check if FW supports adding source mac address 11393 * to TCAM feature or not. 11394 * If FW returns 1, driver can use this feature and driver need to send 11395 * FW_PARAMS_PARAM_DEV_ADD_SMAC write command with value 1 to 11396 * enable adding smac to TCAM. 11397 */ 11398 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11399 if (ret) 11400 return ret; 11401 11402 if (val == 1) { 11403 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 11404 ¶m, &val); 11405 if (!ret) 11406 /* Firmware allows adding explicit TCAM entries. 11407 * Save this internally. 11408 */ 11409 adap->params.smac_add_support = 1; 11410 } 11411 11412 return ret; 11413 } 11414 11415 int t4_configure_ringbb(struct adapter *adap) 11416 { 11417 unsigned int param, val; 11418 int ret = 0; 11419 11420 param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 11421 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RING_BACKBONE)); 11422 /* Query FW to check if FW supports ring switch feature or not. 11423 * If FW returns 1, driver can use this feature and driver need to send 11424 * FW_PARAMS_PARAM_DEV_RING_BACKBONE write command with value 1 to 11425 * enable the ring backbone configuration. 11426 */ 11427 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11428 if (ret < 0) { 11429 CH_ERR(adap, "Querying FW using Ring backbone params command failed, err=%d\n", 11430 ret); 11431 goto out; 11432 } 11433 11434 if (val != 1) { 11435 CH_ERR(adap, "FW doesnot support ringbackbone features\n"); 11436 goto out; 11437 } 11438 11439 ret = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, ¶m, &val); 11440 if (ret < 0) { 11441 CH_ERR(adap, "Could not set Ringbackbone, err= %d\n", 11442 ret); 11443 goto out; 11444 } 11445 11446 out: 11447 return ret; 11448 } 11449 11450 /* 11451 * t4_set_vlan_acl - Set a VLAN id for the specified VF 11452 * @adapter: the adapter 11453 * @mbox: mailbox to use for the FW command 11454 * @vf: one of the VFs instantiated by the specified PF 11455 * @vlan: The vlanid to be set 11456 * 11457 */ 11458 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf, 11459 u16 vlan) 11460 { 11461 struct fw_acl_vlan_cmd vlan_cmd; 11462 unsigned int enable; 11463 11464 enable = (vlan ? F_FW_ACL_VLAN_CMD_EN : 0); 11465 memset(&vlan_cmd, 0, sizeof(vlan_cmd)); 11466 vlan_cmd.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_ACL_VLAN_CMD) | 11467 F_FW_CMD_REQUEST | 11468 F_FW_CMD_WRITE | 11469 F_FW_CMD_EXEC | 11470 V_FW_ACL_VLAN_CMD_PFN(adap->pf) | 11471 V_FW_ACL_VLAN_CMD_VFN(vf)); 11472 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd)); 11473 /* Drop all packets that donot match vlan id */ 11474 vlan_cmd.dropnovlan_fm = (enable 11475 ? (F_FW_ACL_VLAN_CMD_DROPNOVLAN | 11476 F_FW_ACL_VLAN_CMD_FM) 11477 : 0); 11478 if (enable != 0) { 11479 vlan_cmd.nvlan = 1; 11480 vlan_cmd.vlanid[0] = cpu_to_be16(vlan); 11481 } 11482 11483 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL); 11484 } 11485 11486 /** 11487 * t4_del_mac - Removes the exact-match filter for a MAC address 11488 * @adap: the adapter 11489 * @mbox: mailbox to use for the FW command 11490 * @viid: the VI id 11491 * @addr: the MAC address value 11492 * @smac: if true, delete from only the smac region of MPS 11493 * 11494 * Modifies an exact-match filter and sets it to the new MAC address if 11495 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11496 * latter case the address is added persistently if @persist is %true. 11497 * 11498 * Returns a negative error number or the index of the filter with the new 11499 * MAC value. Note that this index may differ from @idx. 11500 */ 11501 int t4_del_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11502 const u8 *addr, bool smac) 11503 { 11504 int ret; 11505 struct fw_vi_mac_cmd c; 11506 struct fw_vi_mac_exact *p = c.u.exact; 11507 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11508 11509 memset(&c, 0, sizeof(c)); 11510 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11511 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11512 V_FW_VI_MAC_CMD_VIID(viid)); 11513 c.freemacs_to_len16 = cpu_to_be32( 11514 V_FW_CMD_LEN16(1) | 11515 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11516 11517 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11518 p->valid_to_idx = cpu_to_be16( 11519 F_FW_VI_MAC_CMD_VALID | 11520 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_MAC_BASED_FREE)); 11521 11522 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11523 if (ret == 0) { 11524 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11525 if (ret < max_mac_addr) 11526 return -ENOMEM; 11527 } 11528 11529 return ret; 11530 } 11531 11532 /** 11533 * t4_add_mac - Adds an exact-match filter for a MAC address 11534 * @adap: the adapter 11535 * @mbox: mailbox to use for the FW command 11536 * @viid: the VI id 11537 * @idx: index of existing filter for old value of MAC address, or -1 11538 * @addr: the new MAC address value 11539 * @persist: whether a new MAC allocation should be persistent 11540 * @add_smt: if true also add the address to the HW SMT 11541 * @smac: if true, update only the smac region of MPS 11542 * 11543 * Modifies an exact-match filter and sets it to the new MAC address if 11544 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 11545 * latter case the address is added persistently if @persist is %true. 11546 * 11547 * Returns a negative error number or the index of the filter with the new 11548 * MAC value. Note that this index may differ from @idx. 11549 */ 11550 int t4_add_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 11551 int idx, const u8 *addr, bool persist, u8 *smt_idx, bool smac) 11552 { 11553 int ret, mode; 11554 struct fw_vi_mac_cmd c; 11555 struct fw_vi_mac_exact *p = c.u.exact; 11556 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 11557 11558 if (idx < 0) /* new allocation */ 11559 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 11560 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 11561 11562 memset(&c, 0, sizeof(c)); 11563 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 11564 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 11565 V_FW_VI_MAC_CMD_VIID(viid)); 11566 c.freemacs_to_len16 = cpu_to_be32( 11567 V_FW_CMD_LEN16(1) | 11568 (smac ? F_FW_VI_MAC_CMD_IS_SMAC : 0)); 11569 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 11570 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 11571 V_FW_VI_MAC_CMD_IDX(idx)); 11572 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 11573 11574 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 11575 if (ret == 0) { 11576 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 11577 if (ret >= max_mac_addr) 11578 return -ENOMEM; 11579 if (smt_idx) { 11580 /* Does fw supports returning smt_idx? */ 11581 if (adap->params.viid_smt_extn_support) 11582 *smt_idx = G_FW_VI_MAC_CMD_SMTID(be32_to_cpu(c.op_to_viid)); 11583 else { 11584 /* In T4/T5, SMT contains 256 SMAC entries 11585 * organized in 128 rows of 2 entries each. 11586 * In T6, SMT contains 256 SMAC entries in 11587 * 256 rows. 11588 */ 11589 if (chip_id(adap) <= CHELSIO_T5) 11590 *smt_idx = ((viid & M_FW_VIID_VIN) << 1); 11591 else 11592 *smt_idx = (viid & M_FW_VIID_VIN); 11593 } 11594 } 11595 } 11596 11597 return ret; 11598 } 11599