xref: /freebsd/sys/dev/cxgbe/common/t4_hw.c (revision 273c26a3c3bea87a241d6879abd4f991db180bf0)
1 /*-
2  * Copyright (c) 2012, 2016 Chelsio Communications, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include "opt_inet.h"
31 
32 #include <sys/param.h>
33 #include <sys/eventhandler.h>
34 
35 #include "common.h"
36 #include "t4_regs.h"
37 #include "t4_regs_values.h"
38 #include "firmware/t4fw_interface.h"
39 
40 #undef msleep
41 #define msleep(x) do { \
42 	if (cold) \
43 		DELAY((x) * 1000); \
44 	else \
45 		pause("t4hw", (x) * hz / 1000); \
46 } while (0)
47 
48 /**
49  *	t4_wait_op_done_val - wait until an operation is completed
50  *	@adapter: the adapter performing the operation
51  *	@reg: the register to check for completion
52  *	@mask: a single-bit field within @reg that indicates completion
53  *	@polarity: the value of the field when the operation is completed
54  *	@attempts: number of check iterations
55  *	@delay: delay in usecs between iterations
56  *	@valp: where to store the value of the register at completion time
57  *
58  *	Wait until an operation is completed by checking a bit in a register
59  *	up to @attempts times.  If @valp is not NULL the value of the register
60  *	at the time it indicated completion is stored there.  Returns 0 if the
61  *	operation completes and	-EAGAIN	otherwise.
62  */
63 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
64 			       int polarity, int attempts, int delay, u32 *valp)
65 {
66 	while (1) {
67 		u32 val = t4_read_reg(adapter, reg);
68 
69 		if (!!(val & mask) == polarity) {
70 			if (valp)
71 				*valp = val;
72 			return 0;
73 		}
74 		if (--attempts == 0)
75 			return -EAGAIN;
76 		if (delay)
77 			udelay(delay);
78 	}
79 }
80 
81 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
82 				  int polarity, int attempts, int delay)
83 {
84 	return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
85 				   delay, NULL);
86 }
87 
88 /**
89  *	t4_set_reg_field - set a register field to a value
90  *	@adapter: the adapter to program
91  *	@addr: the register address
92  *	@mask: specifies the portion of the register to modify
93  *	@val: the new value for the register field
94  *
95  *	Sets a register field specified by the supplied mask to the
96  *	given value.
97  */
98 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
99 		      u32 val)
100 {
101 	u32 v = t4_read_reg(adapter, addr) & ~mask;
102 
103 	t4_write_reg(adapter, addr, v | val);
104 	(void) t4_read_reg(adapter, addr);      /* flush */
105 }
106 
107 /**
108  *	t4_read_indirect - read indirectly addressed registers
109  *	@adap: the adapter
110  *	@addr_reg: register holding the indirect address
111  *	@data_reg: register holding the value of the indirect register
112  *	@vals: where the read register values are stored
113  *	@nregs: how many indirect registers to read
114  *	@start_idx: index of first indirect register to read
115  *
116  *	Reads registers that are accessed indirectly through an address/data
117  *	register pair.
118  */
119 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
120 			     unsigned int data_reg, u32 *vals,
121 			     unsigned int nregs, unsigned int start_idx)
122 {
123 	while (nregs--) {
124 		t4_write_reg(adap, addr_reg, start_idx);
125 		*vals++ = t4_read_reg(adap, data_reg);
126 		start_idx++;
127 	}
128 }
129 
130 /**
131  *	t4_write_indirect - write indirectly addressed registers
132  *	@adap: the adapter
133  *	@addr_reg: register holding the indirect addresses
134  *	@data_reg: register holding the value for the indirect registers
135  *	@vals: values to write
136  *	@nregs: how many indirect registers to write
137  *	@start_idx: address of first indirect register to write
138  *
139  *	Writes a sequential block of registers that are accessed indirectly
140  *	through an address/data register pair.
141  */
142 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
143 		       unsigned int data_reg, const u32 *vals,
144 		       unsigned int nregs, unsigned int start_idx)
145 {
146 	while (nregs--) {
147 		t4_write_reg(adap, addr_reg, start_idx++);
148 		t4_write_reg(adap, data_reg, *vals++);
149 	}
150 }
151 
152 /*
153  * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
154  * mechanism.  This guarantees that we get the real value even if we're
155  * operating within a Virtual Machine and the Hypervisor is trapping our
156  * Configuration Space accesses.
157  *
158  * N.B. This routine should only be used as a last resort: the firmware uses
159  *      the backdoor registers on a regular basis and we can end up
160  *      conflicting with it's uses!
161  */
162 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg)
163 {
164 	u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg);
165 	u32 val;
166 
167 	if (chip_id(adap) <= CHELSIO_T5)
168 		req |= F_ENABLE;
169 	else
170 		req |= F_T6_ENABLE;
171 
172 	if (is_t4(adap))
173 		req |= F_LOCALCFG;
174 
175 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req);
176 	val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA);
177 
178 	/*
179 	 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
180 	 * Configuration Space read.  (None of the other fields matter when
181 	 * F_ENABLE is 0 so a simple register write is easier than a
182 	 * read-modify-write via t4_set_reg_field().)
183 	 */
184 	t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0);
185 
186 	return val;
187 }
188 
189 /*
190  * t4_report_fw_error - report firmware error
191  * @adap: the adapter
192  *
193  * The adapter firmware can indicate error conditions to the host.
194  * If the firmware has indicated an error, print out the reason for
195  * the firmware error.
196  */
197 static void t4_report_fw_error(struct adapter *adap)
198 {
199 	static const char *const reason[] = {
200 		"Crash",			/* PCIE_FW_EVAL_CRASH */
201 		"During Device Preparation",	/* PCIE_FW_EVAL_PREP */
202 		"During Device Configuration",	/* PCIE_FW_EVAL_CONF */
203 		"During Device Initialization",	/* PCIE_FW_EVAL_INIT */
204 		"Unexpected Event",		/* PCIE_FW_EVAL_UNEXPECTEDEVENT */
205 		"Insufficient Airflow",		/* PCIE_FW_EVAL_OVERHEAT */
206 		"Device Shutdown",		/* PCIE_FW_EVAL_DEVICESHUTDOWN */
207 		"Reserved",			/* reserved */
208 	};
209 	u32 pcie_fw;
210 
211 	pcie_fw = t4_read_reg(adap, A_PCIE_FW);
212 	if (pcie_fw & F_PCIE_FW_ERR)
213 		CH_ERR(adap, "Firmware reports adapter error: %s\n",
214 			reason[G_PCIE_FW_EVAL(pcie_fw)]);
215 }
216 
217 /*
218  * Get the reply to a mailbox command and store it in @rpl in big-endian order.
219  */
220 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
221 			 u32 mbox_addr)
222 {
223 	for ( ; nflit; nflit--, mbox_addr += 8)
224 		*rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
225 }
226 
227 /*
228  * Handle a FW assertion reported in a mailbox.
229  */
230 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt)
231 {
232 	CH_ALERT(adap,
233 		  "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
234 		  asrt->u.assert.filename_0_7,
235 		  be32_to_cpu(asrt->u.assert.line),
236 		  be32_to_cpu(asrt->u.assert.x),
237 		  be32_to_cpu(asrt->u.assert.y));
238 }
239 
240 #define X_CIM_PF_NOACCESS 0xeeeeeeee
241 /**
242  *	t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
243  *	@adap: the adapter
244  *	@mbox: index of the mailbox to use
245  *	@cmd: the command to write
246  *	@size: command length in bytes
247  *	@rpl: where to optionally store the reply
248  *	@sleep_ok: if true we may sleep while awaiting command completion
249  *	@timeout: time to wait for command to finish before timing out
250  *		(negative implies @sleep_ok=false)
251  *
252  *	Sends the given command to FW through the selected mailbox and waits
253  *	for the FW to execute the command.  If @rpl is not %NULL it is used to
254  *	store the FW's reply to the command.  The command and its optional
255  *	reply are of the same length.  Some FW commands like RESET and
256  *	INITIALIZE can take a considerable amount of time to execute.
257  *	@sleep_ok determines whether we may sleep while awaiting the response.
258  *	If sleeping is allowed we use progressive backoff otherwise we spin.
259  *	Note that passing in a negative @timeout is an alternate mechanism
260  *	for specifying @sleep_ok=false.  This is useful when a higher level
261  *	interface allows for specification of @timeout but not @sleep_ok ...
262  *
263  *	The return value is 0 on success or a negative errno on failure.  A
264  *	failure can happen either because we are not able to execute the
265  *	command or FW executes it but signals an error.  In the latter case
266  *	the return value is the error code indicated by FW (negated).
267  */
268 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
269 			    int size, void *rpl, bool sleep_ok, int timeout)
270 {
271 	/*
272 	 * We delay in small increments at first in an effort to maintain
273 	 * responsiveness for simple, fast executing commands but then back
274 	 * off to larger delays to a maximum retry delay.
275 	 */
276 	static const int delay[] = {
277 		1, 1, 3, 5, 10, 10, 20, 50, 100
278 	};
279 	u32 v;
280 	u64 res;
281 	int i, ms, delay_idx, ret;
282 	const __be64 *p = cmd;
283 	u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA);
284 	u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL);
285 	u32 ctl;
286 	__be64 cmd_rpl[MBOX_LEN/8];
287 	u32 pcie_fw;
288 
289 	if ((size & 15) || size > MBOX_LEN)
290 		return -EINVAL;
291 
292 	if (adap->flags & IS_VF) {
293 		if (is_t6(adap))
294 			data_reg = FW_T6VF_MBDATA_BASE_ADDR;
295 		else
296 			data_reg = FW_T4VF_MBDATA_BASE_ADDR;
297 		ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL);
298 	}
299 
300 	/*
301 	 * If we have a negative timeout, that implies that we can't sleep.
302 	 */
303 	if (timeout < 0) {
304 		sleep_ok = false;
305 		timeout = -timeout;
306 	}
307 
308 	/*
309 	 * Attempt to gain access to the mailbox.
310 	 */
311 	for (i = 0; i < 4; i++) {
312 		ctl = t4_read_reg(adap, ctl_reg);
313 		v = G_MBOWNER(ctl);
314 		if (v != X_MBOWNER_NONE)
315 			break;
316 	}
317 
318 	/*
319 	 * If we were unable to gain access, dequeue ourselves from the
320 	 * mailbox atomic access list and report the error to our caller.
321 	 */
322 	if (v != X_MBOWNER_PL) {
323 		t4_report_fw_error(adap);
324 		ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT;
325 		return ret;
326 	}
327 
328 	/*
329 	 * If we gain ownership of the mailbox and there's a "valid" message
330 	 * in it, this is likely an asynchronous error message from the
331 	 * firmware.  So we'll report that and then proceed on with attempting
332 	 * to issue our own command ... which may well fail if the error
333 	 * presaged the firmware crashing ...
334 	 */
335 	if (ctl & F_MBMSGVALID) {
336 		CH_ERR(adap, "found VALID command in mbox %u: "
337 		       "%llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
338 		       (unsigned long long)t4_read_reg64(adap, data_reg),
339 		       (unsigned long long)t4_read_reg64(adap, data_reg + 8),
340 		       (unsigned long long)t4_read_reg64(adap, data_reg + 16),
341 		       (unsigned long long)t4_read_reg64(adap, data_reg + 24),
342 		       (unsigned long long)t4_read_reg64(adap, data_reg + 32),
343 		       (unsigned long long)t4_read_reg64(adap, data_reg + 40),
344 		       (unsigned long long)t4_read_reg64(adap, data_reg + 48),
345 		       (unsigned long long)t4_read_reg64(adap, data_reg + 56));
346 	}
347 
348 	/*
349 	 * Copy in the new mailbox command and send it on its way ...
350 	 */
351 	for (i = 0; i < size; i += 8, p++)
352 		t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p));
353 
354 	if (adap->flags & IS_VF) {
355 		/*
356 		 * For the VFs, the Mailbox Data "registers" are
357 		 * actually backed by T4's "MA" interface rather than
358 		 * PL Registers (as is the case for the PFs).  Because
359 		 * these are in different coherency domains, the write
360 		 * to the VF's PL-register-backed Mailbox Control can
361 		 * race in front of the writes to the MA-backed VF
362 		 * Mailbox Data "registers".  So we need to do a
363 		 * read-back on at least one byte of the VF Mailbox
364 		 * Data registers before doing the write to the VF
365 		 * Mailbox Control register.
366 		 */
367 		t4_read_reg(adap, data_reg);
368 	}
369 
370 	CH_DUMP_MBOX(adap, mbox, data_reg);
371 
372 	t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW));
373 	t4_read_reg(adap, ctl_reg);	/* flush write */
374 
375 	delay_idx = 0;
376 	ms = delay[0];
377 
378 	/*
379 	 * Loop waiting for the reply; bail out if we time out or the firmware
380 	 * reports an error.
381 	 */
382 	pcie_fw = 0;
383 	for (i = 0; i < timeout; i += ms) {
384 		if (!(adap->flags & IS_VF)) {
385 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
386 			if (pcie_fw & F_PCIE_FW_ERR)
387 				break;
388 		}
389 		if (sleep_ok) {
390 			ms = delay[delay_idx];  /* last element may repeat */
391 			if (delay_idx < ARRAY_SIZE(delay) - 1)
392 				delay_idx++;
393 			msleep(ms);
394 		} else {
395 			mdelay(ms);
396 		}
397 
398 		v = t4_read_reg(adap, ctl_reg);
399 		if (v == X_CIM_PF_NOACCESS)
400 			continue;
401 		if (G_MBOWNER(v) == X_MBOWNER_PL) {
402 			if (!(v & F_MBMSGVALID)) {
403 				t4_write_reg(adap, ctl_reg,
404 					     V_MBOWNER(X_MBOWNER_NONE));
405 				continue;
406 			}
407 
408 			/*
409 			 * Retrieve the command reply and release the mailbox.
410 			 */
411 			get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg);
412 			t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE));
413 
414 			CH_DUMP_MBOX(adap, mbox, data_reg);
415 
416 			res = be64_to_cpu(cmd_rpl[0]);
417 			if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) {
418 				fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl);
419 				res = V_FW_CMD_RETVAL(EIO);
420 			} else if (rpl)
421 				memcpy(rpl, cmd_rpl, size);
422 			return -G_FW_CMD_RETVAL((int)res);
423 		}
424 	}
425 
426 	/*
427 	 * We timed out waiting for a reply to our mailbox command.  Report
428 	 * the error and also check to see if the firmware reported any
429 	 * errors ...
430 	 */
431 	ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT;
432 	CH_ERR(adap, "command %#x in mailbox %d timed out\n",
433 	       *(const u8 *)cmd, mbox);
434 
435 	t4_report_fw_error(adap);
436 	t4_fatal_err(adap);
437 	return ret;
438 }
439 
440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
441 		    void *rpl, bool sleep_ok)
442 {
443 		return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl,
444 					       sleep_ok, FW_CMD_MAX_TIMEOUT);
445 
446 }
447 
448 static int t4_edc_err_read(struct adapter *adap, int idx)
449 {
450 	u32 edc_ecc_err_addr_reg;
451 	u32 edc_bist_status_rdata_reg;
452 
453 	if (is_t4(adap)) {
454 		CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
455 		return 0;
456 	}
457 	if (idx != 0 && idx != 1) {
458 		CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
459 		return 0;
460 	}
461 
462 	edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx);
463 	edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx);
464 
465 	CH_WARN(adap,
466 		"edc%d err addr 0x%x: 0x%x.\n",
467 		idx, edc_ecc_err_addr_reg,
468 		t4_read_reg(adap, edc_ecc_err_addr_reg));
469 	CH_WARN(adap,
470 	 	"bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
471 		edc_bist_status_rdata_reg,
472 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg),
473 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8),
474 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16),
475 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24),
476 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32),
477 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40),
478 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48),
479 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56),
480 		(unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64));
481 
482 	return 0;
483 }
484 
485 /**
486  *	t4_mc_read - read from MC through backdoor accesses
487  *	@adap: the adapter
488  *	@idx: which MC to access
489  *	@addr: address of first byte requested
490  *	@data: 64 bytes of data containing the requested address
491  *	@ecc: where to store the corresponding 64-bit ECC word
492  *
493  *	Read 64 bytes of data from MC starting at a 64-byte-aligned address
494  *	that covers the requested address @addr.  If @parity is not %NULL it
495  *	is assigned the 64-bit ECC word for the read data.
496  */
497 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
498 {
499 	int i;
500 	u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
501 	u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
502 
503 	if (is_t4(adap)) {
504 		mc_bist_cmd_reg = A_MC_BIST_CMD;
505 		mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR;
506 		mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN;
507 		mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA;
508 		mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN;
509 	} else {
510 		mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx);
511 		mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx);
512 		mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx);
513 		mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA,
514 						  idx);
515 		mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN,
516 						  idx);
517 	}
518 
519 	if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST)
520 		return -EBUSY;
521 	t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU);
522 	t4_write_reg(adap, mc_bist_cmd_len_reg, 64);
523 	t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc);
524 	t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) |
525 		     F_START_BIST | V_BIST_CMD_GAP(1));
526 	i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
527 	if (i)
528 		return i;
529 
530 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i)
531 
532 	for (i = 15; i >= 0; i--)
533 		*data++ = ntohl(t4_read_reg(adap, MC_DATA(i)));
534 	if (ecc)
535 		*ecc = t4_read_reg64(adap, MC_DATA(16));
536 #undef MC_DATA
537 	return 0;
538 }
539 
540 /**
541  *	t4_edc_read - read from EDC through backdoor accesses
542  *	@adap: the adapter
543  *	@idx: which EDC to access
544  *	@addr: address of first byte requested
545  *	@data: 64 bytes of data containing the requested address
546  *	@ecc: where to store the corresponding 64-bit ECC word
547  *
548  *	Read 64 bytes of data from EDC starting at a 64-byte-aligned address
549  *	that covers the requested address @addr.  If @parity is not %NULL it
550  *	is assigned the 64-bit ECC word for the read data.
551  */
552 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
553 {
554 	int i;
555 	u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
556 	u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
557 
558 	if (is_t4(adap)) {
559 		edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
560 		edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
561 		edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
562 		edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
563 						    idx);
564 		edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
565 						    idx);
566 	} else {
567 /*
568  * These macro are missing in t4_regs.h file.
569  * Added temporarily for testing.
570  */
571 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
572 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
573 		edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
574 		edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
575 		edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
576 		edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
577 						    idx);
578 		edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
579 						    idx);
580 #undef EDC_REG_T5
581 #undef EDC_STRIDE_T5
582 	}
583 
584 	if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
585 		return -EBUSY;
586 	t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
587 	t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
588 	t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
589 	t4_write_reg(adap, edc_bist_cmd_reg,
590 		     V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
591 	i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
592 	if (i)
593 		return i;
594 
595 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
596 
597 	for (i = 15; i >= 0; i--)
598 		*data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
599 	if (ecc)
600 		*ecc = t4_read_reg64(adap, EDC_DATA(16));
601 #undef EDC_DATA
602 	return 0;
603 }
604 
605 /**
606  *	t4_mem_read - read EDC 0, EDC 1 or MC into buffer
607  *	@adap: the adapter
608  *	@mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
609  *	@addr: address within indicated memory type
610  *	@len: amount of memory to read
611  *	@buf: host memory buffer
612  *
613  *	Reads an [almost] arbitrary memory region in the firmware: the
614  *	firmware memory address, length and host buffer must be aligned on
615  *	32-bit boudaries.  The memory is returned as a raw byte sequence from
616  *	the firmware's memory.  If this memory contains data structures which
617  *	contain multi-byte integers, it's the callers responsibility to
618  *	perform appropriate byte order conversions.
619  */
620 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len,
621 		__be32 *buf)
622 {
623 	u32 pos, start, end, offset;
624 	int ret;
625 
626 	/*
627 	 * Argument sanity checks ...
628 	 */
629 	if ((addr & 0x3) || (len & 0x3))
630 		return -EINVAL;
631 
632 	/*
633 	 * The underlaying EDC/MC read routines read 64 bytes at a time so we
634 	 * need to round down the start and round up the end.  We'll start
635 	 * copying out of the first line at (addr - start) a word at a time.
636 	 */
637 	start = rounddown2(addr, 64);
638 	end = roundup2(addr + len, 64);
639 	offset = (addr - start)/sizeof(__be32);
640 
641 	for (pos = start; pos < end; pos += 64, offset = 0) {
642 		__be32 data[16];
643 
644 		/*
645 		 * Read the chip's memory block and bail if there's an error.
646 		 */
647 		if ((mtype == MEM_MC) || (mtype == MEM_MC1))
648 			ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL);
649 		else
650 			ret = t4_edc_read(adap, mtype, pos, data, NULL);
651 		if (ret)
652 			return ret;
653 
654 		/*
655 		 * Copy the data into the caller's memory buffer.
656 		 */
657 		while (offset < 16 && len > 0) {
658 			*buf++ = data[offset++];
659 			len -= sizeof(__be32);
660 		}
661 	}
662 
663 	return 0;
664 }
665 
666 /*
667  * Return the specified PCI-E Configuration Space register from our Physical
668  * Function.  We try first via a Firmware LDST Command (if fw_attach != 0)
669  * since we prefer to let the firmware own all of these registers, but if that
670  * fails we go for it directly ourselves.
671  */
672 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach)
673 {
674 
675 	/*
676 	 * If fw_attach != 0, construct and send the Firmware LDST Command to
677 	 * retrieve the specified PCI-E Configuration Space register.
678 	 */
679 	if (drv_fw_attach != 0) {
680 		struct fw_ldst_cmd ldst_cmd;
681 		int ret;
682 
683 		memset(&ldst_cmd, 0, sizeof(ldst_cmd));
684 		ldst_cmd.op_to_addrspace =
685 			cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
686 				    F_FW_CMD_REQUEST |
687 				    F_FW_CMD_READ |
688 				    V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
689 		ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
690 		ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1);
691 		ldst_cmd.u.pcie.ctrl_to_fn =
692 			(F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf));
693 		ldst_cmd.u.pcie.r = reg;
694 
695 		/*
696 		 * If the LDST Command succeeds, return the result, otherwise
697 		 * fall through to reading it directly ourselves ...
698 		 */
699 		ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
700 				 &ldst_cmd);
701 		if (ret == 0)
702 			return be32_to_cpu(ldst_cmd.u.pcie.data[0]);
703 
704 		CH_WARN(adap, "Firmware failed to return "
705 			"Configuration Space register %d, err = %d\n",
706 			reg, -ret);
707 	}
708 
709 	/*
710 	 * Read the desired Configuration Space register via the PCI-E
711 	 * Backdoor mechanism.
712 	 */
713 	return t4_hw_pci_read_cfg4(adap, reg);
714 }
715 
716 /**
717  *	t4_get_regs_len - return the size of the chips register set
718  *	@adapter: the adapter
719  *
720  *	Returns the size of the chip's BAR0 register space.
721  */
722 unsigned int t4_get_regs_len(struct adapter *adapter)
723 {
724 	unsigned int chip_version = chip_id(adapter);
725 
726 	switch (chip_version) {
727 	case CHELSIO_T4:
728 		if (adapter->flags & IS_VF)
729 			return FW_T4VF_REGMAP_SIZE;
730 		return T4_REGMAP_SIZE;
731 
732 	case CHELSIO_T5:
733 	case CHELSIO_T6:
734 		if (adapter->flags & IS_VF)
735 			return FW_T4VF_REGMAP_SIZE;
736 		return T5_REGMAP_SIZE;
737 	}
738 
739 	CH_ERR(adapter,
740 		"Unsupported chip version %d\n", chip_version);
741 	return 0;
742 }
743 
744 /**
745  *	t4_get_regs - read chip registers into provided buffer
746  *	@adap: the adapter
747  *	@buf: register buffer
748  *	@buf_size: size (in bytes) of register buffer
749  *
750  *	If the provided register buffer isn't large enough for the chip's
751  *	full register range, the register dump will be truncated to the
752  *	register buffer's size.
753  */
754 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size)
755 {
756 	static const unsigned int t4_reg_ranges[] = {
757 		0x1008, 0x1108,
758 		0x1180, 0x1184,
759 		0x1190, 0x1194,
760 		0x11a0, 0x11a4,
761 		0x11b0, 0x11b4,
762 		0x11fc, 0x123c,
763 		0x1300, 0x173c,
764 		0x1800, 0x18fc,
765 		0x3000, 0x30d8,
766 		0x30e0, 0x30e4,
767 		0x30ec, 0x5910,
768 		0x5920, 0x5924,
769 		0x5960, 0x5960,
770 		0x5968, 0x5968,
771 		0x5970, 0x5970,
772 		0x5978, 0x5978,
773 		0x5980, 0x5980,
774 		0x5988, 0x5988,
775 		0x5990, 0x5990,
776 		0x5998, 0x5998,
777 		0x59a0, 0x59d4,
778 		0x5a00, 0x5ae0,
779 		0x5ae8, 0x5ae8,
780 		0x5af0, 0x5af0,
781 		0x5af8, 0x5af8,
782 		0x6000, 0x6098,
783 		0x6100, 0x6150,
784 		0x6200, 0x6208,
785 		0x6240, 0x6248,
786 		0x6280, 0x62b0,
787 		0x62c0, 0x6338,
788 		0x6370, 0x638c,
789 		0x6400, 0x643c,
790 		0x6500, 0x6524,
791 		0x6a00, 0x6a04,
792 		0x6a14, 0x6a38,
793 		0x6a60, 0x6a70,
794 		0x6a78, 0x6a78,
795 		0x6b00, 0x6b0c,
796 		0x6b1c, 0x6b84,
797 		0x6bf0, 0x6bf8,
798 		0x6c00, 0x6c0c,
799 		0x6c1c, 0x6c84,
800 		0x6cf0, 0x6cf8,
801 		0x6d00, 0x6d0c,
802 		0x6d1c, 0x6d84,
803 		0x6df0, 0x6df8,
804 		0x6e00, 0x6e0c,
805 		0x6e1c, 0x6e84,
806 		0x6ef0, 0x6ef8,
807 		0x6f00, 0x6f0c,
808 		0x6f1c, 0x6f84,
809 		0x6ff0, 0x6ff8,
810 		0x7000, 0x700c,
811 		0x701c, 0x7084,
812 		0x70f0, 0x70f8,
813 		0x7100, 0x710c,
814 		0x711c, 0x7184,
815 		0x71f0, 0x71f8,
816 		0x7200, 0x720c,
817 		0x721c, 0x7284,
818 		0x72f0, 0x72f8,
819 		0x7300, 0x730c,
820 		0x731c, 0x7384,
821 		0x73f0, 0x73f8,
822 		0x7400, 0x7450,
823 		0x7500, 0x7530,
824 		0x7600, 0x760c,
825 		0x7614, 0x761c,
826 		0x7680, 0x76cc,
827 		0x7700, 0x7798,
828 		0x77c0, 0x77fc,
829 		0x7900, 0x79fc,
830 		0x7b00, 0x7b58,
831 		0x7b60, 0x7b84,
832 		0x7b8c, 0x7c38,
833 		0x7d00, 0x7d38,
834 		0x7d40, 0x7d80,
835 		0x7d8c, 0x7ddc,
836 		0x7de4, 0x7e04,
837 		0x7e10, 0x7e1c,
838 		0x7e24, 0x7e38,
839 		0x7e40, 0x7e44,
840 		0x7e4c, 0x7e78,
841 		0x7e80, 0x7ea4,
842 		0x7eac, 0x7edc,
843 		0x7ee8, 0x7efc,
844 		0x8dc0, 0x8e04,
845 		0x8e10, 0x8e1c,
846 		0x8e30, 0x8e78,
847 		0x8ea0, 0x8eb8,
848 		0x8ec0, 0x8f6c,
849 		0x8fc0, 0x9008,
850 		0x9010, 0x9058,
851 		0x9060, 0x9060,
852 		0x9068, 0x9074,
853 		0x90fc, 0x90fc,
854 		0x9400, 0x9408,
855 		0x9410, 0x9458,
856 		0x9600, 0x9600,
857 		0x9608, 0x9638,
858 		0x9640, 0x96bc,
859 		0x9800, 0x9808,
860 		0x9820, 0x983c,
861 		0x9850, 0x9864,
862 		0x9c00, 0x9c6c,
863 		0x9c80, 0x9cec,
864 		0x9d00, 0x9d6c,
865 		0x9d80, 0x9dec,
866 		0x9e00, 0x9e6c,
867 		0x9e80, 0x9eec,
868 		0x9f00, 0x9f6c,
869 		0x9f80, 0x9fec,
870 		0xd004, 0xd004,
871 		0xd010, 0xd03c,
872 		0xdfc0, 0xdfe0,
873 		0xe000, 0xea7c,
874 		0xf000, 0x11190,
875 		0x19040, 0x1906c,
876 		0x19078, 0x19080,
877 		0x1908c, 0x190e4,
878 		0x190f0, 0x190f8,
879 		0x19100, 0x19110,
880 		0x19120, 0x19124,
881 		0x19150, 0x19194,
882 		0x1919c, 0x191b0,
883 		0x191d0, 0x191e8,
884 		0x19238, 0x1924c,
885 		0x193f8, 0x1943c,
886 		0x1944c, 0x19474,
887 		0x19490, 0x194e0,
888 		0x194f0, 0x194f8,
889 		0x19800, 0x19c08,
890 		0x19c10, 0x19c90,
891 		0x19ca0, 0x19ce4,
892 		0x19cf0, 0x19d40,
893 		0x19d50, 0x19d94,
894 		0x19da0, 0x19de8,
895 		0x19df0, 0x19e40,
896 		0x19e50, 0x19e90,
897 		0x19ea0, 0x19f4c,
898 		0x1a000, 0x1a004,
899 		0x1a010, 0x1a06c,
900 		0x1a0b0, 0x1a0e4,
901 		0x1a0ec, 0x1a0f4,
902 		0x1a100, 0x1a108,
903 		0x1a114, 0x1a120,
904 		0x1a128, 0x1a130,
905 		0x1a138, 0x1a138,
906 		0x1a190, 0x1a1c4,
907 		0x1a1fc, 0x1a1fc,
908 		0x1e040, 0x1e04c,
909 		0x1e284, 0x1e28c,
910 		0x1e2c0, 0x1e2c0,
911 		0x1e2e0, 0x1e2e0,
912 		0x1e300, 0x1e384,
913 		0x1e3c0, 0x1e3c8,
914 		0x1e440, 0x1e44c,
915 		0x1e684, 0x1e68c,
916 		0x1e6c0, 0x1e6c0,
917 		0x1e6e0, 0x1e6e0,
918 		0x1e700, 0x1e784,
919 		0x1e7c0, 0x1e7c8,
920 		0x1e840, 0x1e84c,
921 		0x1ea84, 0x1ea8c,
922 		0x1eac0, 0x1eac0,
923 		0x1eae0, 0x1eae0,
924 		0x1eb00, 0x1eb84,
925 		0x1ebc0, 0x1ebc8,
926 		0x1ec40, 0x1ec4c,
927 		0x1ee84, 0x1ee8c,
928 		0x1eec0, 0x1eec0,
929 		0x1eee0, 0x1eee0,
930 		0x1ef00, 0x1ef84,
931 		0x1efc0, 0x1efc8,
932 		0x1f040, 0x1f04c,
933 		0x1f284, 0x1f28c,
934 		0x1f2c0, 0x1f2c0,
935 		0x1f2e0, 0x1f2e0,
936 		0x1f300, 0x1f384,
937 		0x1f3c0, 0x1f3c8,
938 		0x1f440, 0x1f44c,
939 		0x1f684, 0x1f68c,
940 		0x1f6c0, 0x1f6c0,
941 		0x1f6e0, 0x1f6e0,
942 		0x1f700, 0x1f784,
943 		0x1f7c0, 0x1f7c8,
944 		0x1f840, 0x1f84c,
945 		0x1fa84, 0x1fa8c,
946 		0x1fac0, 0x1fac0,
947 		0x1fae0, 0x1fae0,
948 		0x1fb00, 0x1fb84,
949 		0x1fbc0, 0x1fbc8,
950 		0x1fc40, 0x1fc4c,
951 		0x1fe84, 0x1fe8c,
952 		0x1fec0, 0x1fec0,
953 		0x1fee0, 0x1fee0,
954 		0x1ff00, 0x1ff84,
955 		0x1ffc0, 0x1ffc8,
956 		0x20000, 0x2002c,
957 		0x20100, 0x2013c,
958 		0x20190, 0x201a0,
959 		0x201a8, 0x201b8,
960 		0x201c4, 0x201c8,
961 		0x20200, 0x20318,
962 		0x20400, 0x204b4,
963 		0x204c0, 0x20528,
964 		0x20540, 0x20614,
965 		0x21000, 0x21040,
966 		0x2104c, 0x21060,
967 		0x210c0, 0x210ec,
968 		0x21200, 0x21268,
969 		0x21270, 0x21284,
970 		0x212fc, 0x21388,
971 		0x21400, 0x21404,
972 		0x21500, 0x21500,
973 		0x21510, 0x21518,
974 		0x2152c, 0x21530,
975 		0x2153c, 0x2153c,
976 		0x21550, 0x21554,
977 		0x21600, 0x21600,
978 		0x21608, 0x2161c,
979 		0x21624, 0x21628,
980 		0x21630, 0x21634,
981 		0x2163c, 0x2163c,
982 		0x21700, 0x2171c,
983 		0x21780, 0x2178c,
984 		0x21800, 0x21818,
985 		0x21820, 0x21828,
986 		0x21830, 0x21848,
987 		0x21850, 0x21854,
988 		0x21860, 0x21868,
989 		0x21870, 0x21870,
990 		0x21878, 0x21898,
991 		0x218a0, 0x218a8,
992 		0x218b0, 0x218c8,
993 		0x218d0, 0x218d4,
994 		0x218e0, 0x218e8,
995 		0x218f0, 0x218f0,
996 		0x218f8, 0x21a18,
997 		0x21a20, 0x21a28,
998 		0x21a30, 0x21a48,
999 		0x21a50, 0x21a54,
1000 		0x21a60, 0x21a68,
1001 		0x21a70, 0x21a70,
1002 		0x21a78, 0x21a98,
1003 		0x21aa0, 0x21aa8,
1004 		0x21ab0, 0x21ac8,
1005 		0x21ad0, 0x21ad4,
1006 		0x21ae0, 0x21ae8,
1007 		0x21af0, 0x21af0,
1008 		0x21af8, 0x21c18,
1009 		0x21c20, 0x21c20,
1010 		0x21c28, 0x21c30,
1011 		0x21c38, 0x21c38,
1012 		0x21c80, 0x21c98,
1013 		0x21ca0, 0x21ca8,
1014 		0x21cb0, 0x21cc8,
1015 		0x21cd0, 0x21cd4,
1016 		0x21ce0, 0x21ce8,
1017 		0x21cf0, 0x21cf0,
1018 		0x21cf8, 0x21d7c,
1019 		0x21e00, 0x21e04,
1020 		0x22000, 0x2202c,
1021 		0x22100, 0x2213c,
1022 		0x22190, 0x221a0,
1023 		0x221a8, 0x221b8,
1024 		0x221c4, 0x221c8,
1025 		0x22200, 0x22318,
1026 		0x22400, 0x224b4,
1027 		0x224c0, 0x22528,
1028 		0x22540, 0x22614,
1029 		0x23000, 0x23040,
1030 		0x2304c, 0x23060,
1031 		0x230c0, 0x230ec,
1032 		0x23200, 0x23268,
1033 		0x23270, 0x23284,
1034 		0x232fc, 0x23388,
1035 		0x23400, 0x23404,
1036 		0x23500, 0x23500,
1037 		0x23510, 0x23518,
1038 		0x2352c, 0x23530,
1039 		0x2353c, 0x2353c,
1040 		0x23550, 0x23554,
1041 		0x23600, 0x23600,
1042 		0x23608, 0x2361c,
1043 		0x23624, 0x23628,
1044 		0x23630, 0x23634,
1045 		0x2363c, 0x2363c,
1046 		0x23700, 0x2371c,
1047 		0x23780, 0x2378c,
1048 		0x23800, 0x23818,
1049 		0x23820, 0x23828,
1050 		0x23830, 0x23848,
1051 		0x23850, 0x23854,
1052 		0x23860, 0x23868,
1053 		0x23870, 0x23870,
1054 		0x23878, 0x23898,
1055 		0x238a0, 0x238a8,
1056 		0x238b0, 0x238c8,
1057 		0x238d0, 0x238d4,
1058 		0x238e0, 0x238e8,
1059 		0x238f0, 0x238f0,
1060 		0x238f8, 0x23a18,
1061 		0x23a20, 0x23a28,
1062 		0x23a30, 0x23a48,
1063 		0x23a50, 0x23a54,
1064 		0x23a60, 0x23a68,
1065 		0x23a70, 0x23a70,
1066 		0x23a78, 0x23a98,
1067 		0x23aa0, 0x23aa8,
1068 		0x23ab0, 0x23ac8,
1069 		0x23ad0, 0x23ad4,
1070 		0x23ae0, 0x23ae8,
1071 		0x23af0, 0x23af0,
1072 		0x23af8, 0x23c18,
1073 		0x23c20, 0x23c20,
1074 		0x23c28, 0x23c30,
1075 		0x23c38, 0x23c38,
1076 		0x23c80, 0x23c98,
1077 		0x23ca0, 0x23ca8,
1078 		0x23cb0, 0x23cc8,
1079 		0x23cd0, 0x23cd4,
1080 		0x23ce0, 0x23ce8,
1081 		0x23cf0, 0x23cf0,
1082 		0x23cf8, 0x23d7c,
1083 		0x23e00, 0x23e04,
1084 		0x24000, 0x2402c,
1085 		0x24100, 0x2413c,
1086 		0x24190, 0x241a0,
1087 		0x241a8, 0x241b8,
1088 		0x241c4, 0x241c8,
1089 		0x24200, 0x24318,
1090 		0x24400, 0x244b4,
1091 		0x244c0, 0x24528,
1092 		0x24540, 0x24614,
1093 		0x25000, 0x25040,
1094 		0x2504c, 0x25060,
1095 		0x250c0, 0x250ec,
1096 		0x25200, 0x25268,
1097 		0x25270, 0x25284,
1098 		0x252fc, 0x25388,
1099 		0x25400, 0x25404,
1100 		0x25500, 0x25500,
1101 		0x25510, 0x25518,
1102 		0x2552c, 0x25530,
1103 		0x2553c, 0x2553c,
1104 		0x25550, 0x25554,
1105 		0x25600, 0x25600,
1106 		0x25608, 0x2561c,
1107 		0x25624, 0x25628,
1108 		0x25630, 0x25634,
1109 		0x2563c, 0x2563c,
1110 		0x25700, 0x2571c,
1111 		0x25780, 0x2578c,
1112 		0x25800, 0x25818,
1113 		0x25820, 0x25828,
1114 		0x25830, 0x25848,
1115 		0x25850, 0x25854,
1116 		0x25860, 0x25868,
1117 		0x25870, 0x25870,
1118 		0x25878, 0x25898,
1119 		0x258a0, 0x258a8,
1120 		0x258b0, 0x258c8,
1121 		0x258d0, 0x258d4,
1122 		0x258e0, 0x258e8,
1123 		0x258f0, 0x258f0,
1124 		0x258f8, 0x25a18,
1125 		0x25a20, 0x25a28,
1126 		0x25a30, 0x25a48,
1127 		0x25a50, 0x25a54,
1128 		0x25a60, 0x25a68,
1129 		0x25a70, 0x25a70,
1130 		0x25a78, 0x25a98,
1131 		0x25aa0, 0x25aa8,
1132 		0x25ab0, 0x25ac8,
1133 		0x25ad0, 0x25ad4,
1134 		0x25ae0, 0x25ae8,
1135 		0x25af0, 0x25af0,
1136 		0x25af8, 0x25c18,
1137 		0x25c20, 0x25c20,
1138 		0x25c28, 0x25c30,
1139 		0x25c38, 0x25c38,
1140 		0x25c80, 0x25c98,
1141 		0x25ca0, 0x25ca8,
1142 		0x25cb0, 0x25cc8,
1143 		0x25cd0, 0x25cd4,
1144 		0x25ce0, 0x25ce8,
1145 		0x25cf0, 0x25cf0,
1146 		0x25cf8, 0x25d7c,
1147 		0x25e00, 0x25e04,
1148 		0x26000, 0x2602c,
1149 		0x26100, 0x2613c,
1150 		0x26190, 0x261a0,
1151 		0x261a8, 0x261b8,
1152 		0x261c4, 0x261c8,
1153 		0x26200, 0x26318,
1154 		0x26400, 0x264b4,
1155 		0x264c0, 0x26528,
1156 		0x26540, 0x26614,
1157 		0x27000, 0x27040,
1158 		0x2704c, 0x27060,
1159 		0x270c0, 0x270ec,
1160 		0x27200, 0x27268,
1161 		0x27270, 0x27284,
1162 		0x272fc, 0x27388,
1163 		0x27400, 0x27404,
1164 		0x27500, 0x27500,
1165 		0x27510, 0x27518,
1166 		0x2752c, 0x27530,
1167 		0x2753c, 0x2753c,
1168 		0x27550, 0x27554,
1169 		0x27600, 0x27600,
1170 		0x27608, 0x2761c,
1171 		0x27624, 0x27628,
1172 		0x27630, 0x27634,
1173 		0x2763c, 0x2763c,
1174 		0x27700, 0x2771c,
1175 		0x27780, 0x2778c,
1176 		0x27800, 0x27818,
1177 		0x27820, 0x27828,
1178 		0x27830, 0x27848,
1179 		0x27850, 0x27854,
1180 		0x27860, 0x27868,
1181 		0x27870, 0x27870,
1182 		0x27878, 0x27898,
1183 		0x278a0, 0x278a8,
1184 		0x278b0, 0x278c8,
1185 		0x278d0, 0x278d4,
1186 		0x278e0, 0x278e8,
1187 		0x278f0, 0x278f0,
1188 		0x278f8, 0x27a18,
1189 		0x27a20, 0x27a28,
1190 		0x27a30, 0x27a48,
1191 		0x27a50, 0x27a54,
1192 		0x27a60, 0x27a68,
1193 		0x27a70, 0x27a70,
1194 		0x27a78, 0x27a98,
1195 		0x27aa0, 0x27aa8,
1196 		0x27ab0, 0x27ac8,
1197 		0x27ad0, 0x27ad4,
1198 		0x27ae0, 0x27ae8,
1199 		0x27af0, 0x27af0,
1200 		0x27af8, 0x27c18,
1201 		0x27c20, 0x27c20,
1202 		0x27c28, 0x27c30,
1203 		0x27c38, 0x27c38,
1204 		0x27c80, 0x27c98,
1205 		0x27ca0, 0x27ca8,
1206 		0x27cb0, 0x27cc8,
1207 		0x27cd0, 0x27cd4,
1208 		0x27ce0, 0x27ce8,
1209 		0x27cf0, 0x27cf0,
1210 		0x27cf8, 0x27d7c,
1211 		0x27e00, 0x27e04,
1212 	};
1213 
1214 	static const unsigned int t4vf_reg_ranges[] = {
1215 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
1216 		VF_MPS_REG(A_MPS_VF_CTL),
1217 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
1218 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI),
1219 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
1220 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
1221 		FW_T4VF_MBDATA_BASE_ADDR,
1222 		FW_T4VF_MBDATA_BASE_ADDR +
1223 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
1224 	};
1225 
1226 	static const unsigned int t5_reg_ranges[] = {
1227 		0x1008, 0x10c0,
1228 		0x10cc, 0x10f8,
1229 		0x1100, 0x1100,
1230 		0x110c, 0x1148,
1231 		0x1180, 0x1184,
1232 		0x1190, 0x1194,
1233 		0x11a0, 0x11a4,
1234 		0x11b0, 0x11b4,
1235 		0x11fc, 0x123c,
1236 		0x1280, 0x173c,
1237 		0x1800, 0x18fc,
1238 		0x3000, 0x3028,
1239 		0x3060, 0x30b0,
1240 		0x30b8, 0x30d8,
1241 		0x30e0, 0x30fc,
1242 		0x3140, 0x357c,
1243 		0x35a8, 0x35cc,
1244 		0x35ec, 0x35ec,
1245 		0x3600, 0x5624,
1246 		0x56cc, 0x56ec,
1247 		0x56f4, 0x5720,
1248 		0x5728, 0x575c,
1249 		0x580c, 0x5814,
1250 		0x5890, 0x589c,
1251 		0x58a4, 0x58ac,
1252 		0x58b8, 0x58bc,
1253 		0x5940, 0x59c8,
1254 		0x59d0, 0x59dc,
1255 		0x59fc, 0x5a18,
1256 		0x5a60, 0x5a70,
1257 		0x5a80, 0x5a9c,
1258 		0x5b94, 0x5bfc,
1259 		0x6000, 0x6020,
1260 		0x6028, 0x6040,
1261 		0x6058, 0x609c,
1262 		0x60a8, 0x614c,
1263 		0x7700, 0x7798,
1264 		0x77c0, 0x78fc,
1265 		0x7b00, 0x7b58,
1266 		0x7b60, 0x7b84,
1267 		0x7b8c, 0x7c54,
1268 		0x7d00, 0x7d38,
1269 		0x7d40, 0x7d80,
1270 		0x7d8c, 0x7ddc,
1271 		0x7de4, 0x7e04,
1272 		0x7e10, 0x7e1c,
1273 		0x7e24, 0x7e38,
1274 		0x7e40, 0x7e44,
1275 		0x7e4c, 0x7e78,
1276 		0x7e80, 0x7edc,
1277 		0x7ee8, 0x7efc,
1278 		0x8dc0, 0x8de0,
1279 		0x8df8, 0x8e04,
1280 		0x8e10, 0x8e84,
1281 		0x8ea0, 0x8f84,
1282 		0x8fc0, 0x9058,
1283 		0x9060, 0x9060,
1284 		0x9068, 0x90f8,
1285 		0x9400, 0x9408,
1286 		0x9410, 0x9470,
1287 		0x9600, 0x9600,
1288 		0x9608, 0x9638,
1289 		0x9640, 0x96f4,
1290 		0x9800, 0x9808,
1291 		0x9820, 0x983c,
1292 		0x9850, 0x9864,
1293 		0x9c00, 0x9c6c,
1294 		0x9c80, 0x9cec,
1295 		0x9d00, 0x9d6c,
1296 		0x9d80, 0x9dec,
1297 		0x9e00, 0x9e6c,
1298 		0x9e80, 0x9eec,
1299 		0x9f00, 0x9f6c,
1300 		0x9f80, 0xa020,
1301 		0xd004, 0xd004,
1302 		0xd010, 0xd03c,
1303 		0xdfc0, 0xdfe0,
1304 		0xe000, 0x1106c,
1305 		0x11074, 0x11088,
1306 		0x1109c, 0x1117c,
1307 		0x11190, 0x11204,
1308 		0x19040, 0x1906c,
1309 		0x19078, 0x19080,
1310 		0x1908c, 0x190e8,
1311 		0x190f0, 0x190f8,
1312 		0x19100, 0x19110,
1313 		0x19120, 0x19124,
1314 		0x19150, 0x19194,
1315 		0x1919c, 0x191b0,
1316 		0x191d0, 0x191e8,
1317 		0x19238, 0x19290,
1318 		0x193f8, 0x19428,
1319 		0x19430, 0x19444,
1320 		0x1944c, 0x1946c,
1321 		0x19474, 0x19474,
1322 		0x19490, 0x194cc,
1323 		0x194f0, 0x194f8,
1324 		0x19c00, 0x19c08,
1325 		0x19c10, 0x19c60,
1326 		0x19c94, 0x19ce4,
1327 		0x19cf0, 0x19d40,
1328 		0x19d50, 0x19d94,
1329 		0x19da0, 0x19de8,
1330 		0x19df0, 0x19e10,
1331 		0x19e50, 0x19e90,
1332 		0x19ea0, 0x19f24,
1333 		0x19f34, 0x19f34,
1334 		0x19f40, 0x19f50,
1335 		0x19f90, 0x19fb4,
1336 		0x19fc4, 0x19fe4,
1337 		0x1a000, 0x1a004,
1338 		0x1a010, 0x1a06c,
1339 		0x1a0b0, 0x1a0e4,
1340 		0x1a0ec, 0x1a0f8,
1341 		0x1a100, 0x1a108,
1342 		0x1a114, 0x1a120,
1343 		0x1a128, 0x1a130,
1344 		0x1a138, 0x1a138,
1345 		0x1a190, 0x1a1c4,
1346 		0x1a1fc, 0x1a1fc,
1347 		0x1e008, 0x1e00c,
1348 		0x1e040, 0x1e044,
1349 		0x1e04c, 0x1e04c,
1350 		0x1e284, 0x1e290,
1351 		0x1e2c0, 0x1e2c0,
1352 		0x1e2e0, 0x1e2e0,
1353 		0x1e300, 0x1e384,
1354 		0x1e3c0, 0x1e3c8,
1355 		0x1e408, 0x1e40c,
1356 		0x1e440, 0x1e444,
1357 		0x1e44c, 0x1e44c,
1358 		0x1e684, 0x1e690,
1359 		0x1e6c0, 0x1e6c0,
1360 		0x1e6e0, 0x1e6e0,
1361 		0x1e700, 0x1e784,
1362 		0x1e7c0, 0x1e7c8,
1363 		0x1e808, 0x1e80c,
1364 		0x1e840, 0x1e844,
1365 		0x1e84c, 0x1e84c,
1366 		0x1ea84, 0x1ea90,
1367 		0x1eac0, 0x1eac0,
1368 		0x1eae0, 0x1eae0,
1369 		0x1eb00, 0x1eb84,
1370 		0x1ebc0, 0x1ebc8,
1371 		0x1ec08, 0x1ec0c,
1372 		0x1ec40, 0x1ec44,
1373 		0x1ec4c, 0x1ec4c,
1374 		0x1ee84, 0x1ee90,
1375 		0x1eec0, 0x1eec0,
1376 		0x1eee0, 0x1eee0,
1377 		0x1ef00, 0x1ef84,
1378 		0x1efc0, 0x1efc8,
1379 		0x1f008, 0x1f00c,
1380 		0x1f040, 0x1f044,
1381 		0x1f04c, 0x1f04c,
1382 		0x1f284, 0x1f290,
1383 		0x1f2c0, 0x1f2c0,
1384 		0x1f2e0, 0x1f2e0,
1385 		0x1f300, 0x1f384,
1386 		0x1f3c0, 0x1f3c8,
1387 		0x1f408, 0x1f40c,
1388 		0x1f440, 0x1f444,
1389 		0x1f44c, 0x1f44c,
1390 		0x1f684, 0x1f690,
1391 		0x1f6c0, 0x1f6c0,
1392 		0x1f6e0, 0x1f6e0,
1393 		0x1f700, 0x1f784,
1394 		0x1f7c0, 0x1f7c8,
1395 		0x1f808, 0x1f80c,
1396 		0x1f840, 0x1f844,
1397 		0x1f84c, 0x1f84c,
1398 		0x1fa84, 0x1fa90,
1399 		0x1fac0, 0x1fac0,
1400 		0x1fae0, 0x1fae0,
1401 		0x1fb00, 0x1fb84,
1402 		0x1fbc0, 0x1fbc8,
1403 		0x1fc08, 0x1fc0c,
1404 		0x1fc40, 0x1fc44,
1405 		0x1fc4c, 0x1fc4c,
1406 		0x1fe84, 0x1fe90,
1407 		0x1fec0, 0x1fec0,
1408 		0x1fee0, 0x1fee0,
1409 		0x1ff00, 0x1ff84,
1410 		0x1ffc0, 0x1ffc8,
1411 		0x30000, 0x30030,
1412 		0x30038, 0x30038,
1413 		0x30040, 0x30040,
1414 		0x30100, 0x30144,
1415 		0x30190, 0x301a0,
1416 		0x301a8, 0x301b8,
1417 		0x301c4, 0x301c8,
1418 		0x301d0, 0x301d0,
1419 		0x30200, 0x30318,
1420 		0x30400, 0x304b4,
1421 		0x304c0, 0x3052c,
1422 		0x30540, 0x3061c,
1423 		0x30800, 0x30828,
1424 		0x30834, 0x30834,
1425 		0x308c0, 0x30908,
1426 		0x30910, 0x309ac,
1427 		0x30a00, 0x30a14,
1428 		0x30a1c, 0x30a2c,
1429 		0x30a44, 0x30a50,
1430 		0x30a74, 0x30a74,
1431 		0x30a7c, 0x30afc,
1432 		0x30b08, 0x30c24,
1433 		0x30d00, 0x30d00,
1434 		0x30d08, 0x30d14,
1435 		0x30d1c, 0x30d20,
1436 		0x30d3c, 0x30d3c,
1437 		0x30d48, 0x30d50,
1438 		0x31200, 0x3120c,
1439 		0x31220, 0x31220,
1440 		0x31240, 0x31240,
1441 		0x31600, 0x3160c,
1442 		0x31a00, 0x31a1c,
1443 		0x31e00, 0x31e20,
1444 		0x31e38, 0x31e3c,
1445 		0x31e80, 0x31e80,
1446 		0x31e88, 0x31ea8,
1447 		0x31eb0, 0x31eb4,
1448 		0x31ec8, 0x31ed4,
1449 		0x31fb8, 0x32004,
1450 		0x32200, 0x32200,
1451 		0x32208, 0x32240,
1452 		0x32248, 0x32280,
1453 		0x32288, 0x322c0,
1454 		0x322c8, 0x322fc,
1455 		0x32600, 0x32630,
1456 		0x32a00, 0x32abc,
1457 		0x32b00, 0x32b10,
1458 		0x32b20, 0x32b30,
1459 		0x32b40, 0x32b50,
1460 		0x32b60, 0x32b70,
1461 		0x33000, 0x33028,
1462 		0x33030, 0x33048,
1463 		0x33060, 0x33068,
1464 		0x33070, 0x3309c,
1465 		0x330f0, 0x33128,
1466 		0x33130, 0x33148,
1467 		0x33160, 0x33168,
1468 		0x33170, 0x3319c,
1469 		0x331f0, 0x33238,
1470 		0x33240, 0x33240,
1471 		0x33248, 0x33250,
1472 		0x3325c, 0x33264,
1473 		0x33270, 0x332b8,
1474 		0x332c0, 0x332e4,
1475 		0x332f8, 0x33338,
1476 		0x33340, 0x33340,
1477 		0x33348, 0x33350,
1478 		0x3335c, 0x33364,
1479 		0x33370, 0x333b8,
1480 		0x333c0, 0x333e4,
1481 		0x333f8, 0x33428,
1482 		0x33430, 0x33448,
1483 		0x33460, 0x33468,
1484 		0x33470, 0x3349c,
1485 		0x334f0, 0x33528,
1486 		0x33530, 0x33548,
1487 		0x33560, 0x33568,
1488 		0x33570, 0x3359c,
1489 		0x335f0, 0x33638,
1490 		0x33640, 0x33640,
1491 		0x33648, 0x33650,
1492 		0x3365c, 0x33664,
1493 		0x33670, 0x336b8,
1494 		0x336c0, 0x336e4,
1495 		0x336f8, 0x33738,
1496 		0x33740, 0x33740,
1497 		0x33748, 0x33750,
1498 		0x3375c, 0x33764,
1499 		0x33770, 0x337b8,
1500 		0x337c0, 0x337e4,
1501 		0x337f8, 0x337fc,
1502 		0x33814, 0x33814,
1503 		0x3382c, 0x3382c,
1504 		0x33880, 0x3388c,
1505 		0x338e8, 0x338ec,
1506 		0x33900, 0x33928,
1507 		0x33930, 0x33948,
1508 		0x33960, 0x33968,
1509 		0x33970, 0x3399c,
1510 		0x339f0, 0x33a38,
1511 		0x33a40, 0x33a40,
1512 		0x33a48, 0x33a50,
1513 		0x33a5c, 0x33a64,
1514 		0x33a70, 0x33ab8,
1515 		0x33ac0, 0x33ae4,
1516 		0x33af8, 0x33b10,
1517 		0x33b28, 0x33b28,
1518 		0x33b3c, 0x33b50,
1519 		0x33bf0, 0x33c10,
1520 		0x33c28, 0x33c28,
1521 		0x33c3c, 0x33c50,
1522 		0x33cf0, 0x33cfc,
1523 		0x34000, 0x34030,
1524 		0x34038, 0x34038,
1525 		0x34040, 0x34040,
1526 		0x34100, 0x34144,
1527 		0x34190, 0x341a0,
1528 		0x341a8, 0x341b8,
1529 		0x341c4, 0x341c8,
1530 		0x341d0, 0x341d0,
1531 		0x34200, 0x34318,
1532 		0x34400, 0x344b4,
1533 		0x344c0, 0x3452c,
1534 		0x34540, 0x3461c,
1535 		0x34800, 0x34828,
1536 		0x34834, 0x34834,
1537 		0x348c0, 0x34908,
1538 		0x34910, 0x349ac,
1539 		0x34a00, 0x34a14,
1540 		0x34a1c, 0x34a2c,
1541 		0x34a44, 0x34a50,
1542 		0x34a74, 0x34a74,
1543 		0x34a7c, 0x34afc,
1544 		0x34b08, 0x34c24,
1545 		0x34d00, 0x34d00,
1546 		0x34d08, 0x34d14,
1547 		0x34d1c, 0x34d20,
1548 		0x34d3c, 0x34d3c,
1549 		0x34d48, 0x34d50,
1550 		0x35200, 0x3520c,
1551 		0x35220, 0x35220,
1552 		0x35240, 0x35240,
1553 		0x35600, 0x3560c,
1554 		0x35a00, 0x35a1c,
1555 		0x35e00, 0x35e20,
1556 		0x35e38, 0x35e3c,
1557 		0x35e80, 0x35e80,
1558 		0x35e88, 0x35ea8,
1559 		0x35eb0, 0x35eb4,
1560 		0x35ec8, 0x35ed4,
1561 		0x35fb8, 0x36004,
1562 		0x36200, 0x36200,
1563 		0x36208, 0x36240,
1564 		0x36248, 0x36280,
1565 		0x36288, 0x362c0,
1566 		0x362c8, 0x362fc,
1567 		0x36600, 0x36630,
1568 		0x36a00, 0x36abc,
1569 		0x36b00, 0x36b10,
1570 		0x36b20, 0x36b30,
1571 		0x36b40, 0x36b50,
1572 		0x36b60, 0x36b70,
1573 		0x37000, 0x37028,
1574 		0x37030, 0x37048,
1575 		0x37060, 0x37068,
1576 		0x37070, 0x3709c,
1577 		0x370f0, 0x37128,
1578 		0x37130, 0x37148,
1579 		0x37160, 0x37168,
1580 		0x37170, 0x3719c,
1581 		0x371f0, 0x37238,
1582 		0x37240, 0x37240,
1583 		0x37248, 0x37250,
1584 		0x3725c, 0x37264,
1585 		0x37270, 0x372b8,
1586 		0x372c0, 0x372e4,
1587 		0x372f8, 0x37338,
1588 		0x37340, 0x37340,
1589 		0x37348, 0x37350,
1590 		0x3735c, 0x37364,
1591 		0x37370, 0x373b8,
1592 		0x373c0, 0x373e4,
1593 		0x373f8, 0x37428,
1594 		0x37430, 0x37448,
1595 		0x37460, 0x37468,
1596 		0x37470, 0x3749c,
1597 		0x374f0, 0x37528,
1598 		0x37530, 0x37548,
1599 		0x37560, 0x37568,
1600 		0x37570, 0x3759c,
1601 		0x375f0, 0x37638,
1602 		0x37640, 0x37640,
1603 		0x37648, 0x37650,
1604 		0x3765c, 0x37664,
1605 		0x37670, 0x376b8,
1606 		0x376c0, 0x376e4,
1607 		0x376f8, 0x37738,
1608 		0x37740, 0x37740,
1609 		0x37748, 0x37750,
1610 		0x3775c, 0x37764,
1611 		0x37770, 0x377b8,
1612 		0x377c0, 0x377e4,
1613 		0x377f8, 0x377fc,
1614 		0x37814, 0x37814,
1615 		0x3782c, 0x3782c,
1616 		0x37880, 0x3788c,
1617 		0x378e8, 0x378ec,
1618 		0x37900, 0x37928,
1619 		0x37930, 0x37948,
1620 		0x37960, 0x37968,
1621 		0x37970, 0x3799c,
1622 		0x379f0, 0x37a38,
1623 		0x37a40, 0x37a40,
1624 		0x37a48, 0x37a50,
1625 		0x37a5c, 0x37a64,
1626 		0x37a70, 0x37ab8,
1627 		0x37ac0, 0x37ae4,
1628 		0x37af8, 0x37b10,
1629 		0x37b28, 0x37b28,
1630 		0x37b3c, 0x37b50,
1631 		0x37bf0, 0x37c10,
1632 		0x37c28, 0x37c28,
1633 		0x37c3c, 0x37c50,
1634 		0x37cf0, 0x37cfc,
1635 		0x38000, 0x38030,
1636 		0x38038, 0x38038,
1637 		0x38040, 0x38040,
1638 		0x38100, 0x38144,
1639 		0x38190, 0x381a0,
1640 		0x381a8, 0x381b8,
1641 		0x381c4, 0x381c8,
1642 		0x381d0, 0x381d0,
1643 		0x38200, 0x38318,
1644 		0x38400, 0x384b4,
1645 		0x384c0, 0x3852c,
1646 		0x38540, 0x3861c,
1647 		0x38800, 0x38828,
1648 		0x38834, 0x38834,
1649 		0x388c0, 0x38908,
1650 		0x38910, 0x389ac,
1651 		0x38a00, 0x38a14,
1652 		0x38a1c, 0x38a2c,
1653 		0x38a44, 0x38a50,
1654 		0x38a74, 0x38a74,
1655 		0x38a7c, 0x38afc,
1656 		0x38b08, 0x38c24,
1657 		0x38d00, 0x38d00,
1658 		0x38d08, 0x38d14,
1659 		0x38d1c, 0x38d20,
1660 		0x38d3c, 0x38d3c,
1661 		0x38d48, 0x38d50,
1662 		0x39200, 0x3920c,
1663 		0x39220, 0x39220,
1664 		0x39240, 0x39240,
1665 		0x39600, 0x3960c,
1666 		0x39a00, 0x39a1c,
1667 		0x39e00, 0x39e20,
1668 		0x39e38, 0x39e3c,
1669 		0x39e80, 0x39e80,
1670 		0x39e88, 0x39ea8,
1671 		0x39eb0, 0x39eb4,
1672 		0x39ec8, 0x39ed4,
1673 		0x39fb8, 0x3a004,
1674 		0x3a200, 0x3a200,
1675 		0x3a208, 0x3a240,
1676 		0x3a248, 0x3a280,
1677 		0x3a288, 0x3a2c0,
1678 		0x3a2c8, 0x3a2fc,
1679 		0x3a600, 0x3a630,
1680 		0x3aa00, 0x3aabc,
1681 		0x3ab00, 0x3ab10,
1682 		0x3ab20, 0x3ab30,
1683 		0x3ab40, 0x3ab50,
1684 		0x3ab60, 0x3ab70,
1685 		0x3b000, 0x3b028,
1686 		0x3b030, 0x3b048,
1687 		0x3b060, 0x3b068,
1688 		0x3b070, 0x3b09c,
1689 		0x3b0f0, 0x3b128,
1690 		0x3b130, 0x3b148,
1691 		0x3b160, 0x3b168,
1692 		0x3b170, 0x3b19c,
1693 		0x3b1f0, 0x3b238,
1694 		0x3b240, 0x3b240,
1695 		0x3b248, 0x3b250,
1696 		0x3b25c, 0x3b264,
1697 		0x3b270, 0x3b2b8,
1698 		0x3b2c0, 0x3b2e4,
1699 		0x3b2f8, 0x3b338,
1700 		0x3b340, 0x3b340,
1701 		0x3b348, 0x3b350,
1702 		0x3b35c, 0x3b364,
1703 		0x3b370, 0x3b3b8,
1704 		0x3b3c0, 0x3b3e4,
1705 		0x3b3f8, 0x3b428,
1706 		0x3b430, 0x3b448,
1707 		0x3b460, 0x3b468,
1708 		0x3b470, 0x3b49c,
1709 		0x3b4f0, 0x3b528,
1710 		0x3b530, 0x3b548,
1711 		0x3b560, 0x3b568,
1712 		0x3b570, 0x3b59c,
1713 		0x3b5f0, 0x3b638,
1714 		0x3b640, 0x3b640,
1715 		0x3b648, 0x3b650,
1716 		0x3b65c, 0x3b664,
1717 		0x3b670, 0x3b6b8,
1718 		0x3b6c0, 0x3b6e4,
1719 		0x3b6f8, 0x3b738,
1720 		0x3b740, 0x3b740,
1721 		0x3b748, 0x3b750,
1722 		0x3b75c, 0x3b764,
1723 		0x3b770, 0x3b7b8,
1724 		0x3b7c0, 0x3b7e4,
1725 		0x3b7f8, 0x3b7fc,
1726 		0x3b814, 0x3b814,
1727 		0x3b82c, 0x3b82c,
1728 		0x3b880, 0x3b88c,
1729 		0x3b8e8, 0x3b8ec,
1730 		0x3b900, 0x3b928,
1731 		0x3b930, 0x3b948,
1732 		0x3b960, 0x3b968,
1733 		0x3b970, 0x3b99c,
1734 		0x3b9f0, 0x3ba38,
1735 		0x3ba40, 0x3ba40,
1736 		0x3ba48, 0x3ba50,
1737 		0x3ba5c, 0x3ba64,
1738 		0x3ba70, 0x3bab8,
1739 		0x3bac0, 0x3bae4,
1740 		0x3baf8, 0x3bb10,
1741 		0x3bb28, 0x3bb28,
1742 		0x3bb3c, 0x3bb50,
1743 		0x3bbf0, 0x3bc10,
1744 		0x3bc28, 0x3bc28,
1745 		0x3bc3c, 0x3bc50,
1746 		0x3bcf0, 0x3bcfc,
1747 		0x3c000, 0x3c030,
1748 		0x3c038, 0x3c038,
1749 		0x3c040, 0x3c040,
1750 		0x3c100, 0x3c144,
1751 		0x3c190, 0x3c1a0,
1752 		0x3c1a8, 0x3c1b8,
1753 		0x3c1c4, 0x3c1c8,
1754 		0x3c1d0, 0x3c1d0,
1755 		0x3c200, 0x3c318,
1756 		0x3c400, 0x3c4b4,
1757 		0x3c4c0, 0x3c52c,
1758 		0x3c540, 0x3c61c,
1759 		0x3c800, 0x3c828,
1760 		0x3c834, 0x3c834,
1761 		0x3c8c0, 0x3c908,
1762 		0x3c910, 0x3c9ac,
1763 		0x3ca00, 0x3ca14,
1764 		0x3ca1c, 0x3ca2c,
1765 		0x3ca44, 0x3ca50,
1766 		0x3ca74, 0x3ca74,
1767 		0x3ca7c, 0x3cafc,
1768 		0x3cb08, 0x3cc24,
1769 		0x3cd00, 0x3cd00,
1770 		0x3cd08, 0x3cd14,
1771 		0x3cd1c, 0x3cd20,
1772 		0x3cd3c, 0x3cd3c,
1773 		0x3cd48, 0x3cd50,
1774 		0x3d200, 0x3d20c,
1775 		0x3d220, 0x3d220,
1776 		0x3d240, 0x3d240,
1777 		0x3d600, 0x3d60c,
1778 		0x3da00, 0x3da1c,
1779 		0x3de00, 0x3de20,
1780 		0x3de38, 0x3de3c,
1781 		0x3de80, 0x3de80,
1782 		0x3de88, 0x3dea8,
1783 		0x3deb0, 0x3deb4,
1784 		0x3dec8, 0x3ded4,
1785 		0x3dfb8, 0x3e004,
1786 		0x3e200, 0x3e200,
1787 		0x3e208, 0x3e240,
1788 		0x3e248, 0x3e280,
1789 		0x3e288, 0x3e2c0,
1790 		0x3e2c8, 0x3e2fc,
1791 		0x3e600, 0x3e630,
1792 		0x3ea00, 0x3eabc,
1793 		0x3eb00, 0x3eb10,
1794 		0x3eb20, 0x3eb30,
1795 		0x3eb40, 0x3eb50,
1796 		0x3eb60, 0x3eb70,
1797 		0x3f000, 0x3f028,
1798 		0x3f030, 0x3f048,
1799 		0x3f060, 0x3f068,
1800 		0x3f070, 0x3f09c,
1801 		0x3f0f0, 0x3f128,
1802 		0x3f130, 0x3f148,
1803 		0x3f160, 0x3f168,
1804 		0x3f170, 0x3f19c,
1805 		0x3f1f0, 0x3f238,
1806 		0x3f240, 0x3f240,
1807 		0x3f248, 0x3f250,
1808 		0x3f25c, 0x3f264,
1809 		0x3f270, 0x3f2b8,
1810 		0x3f2c0, 0x3f2e4,
1811 		0x3f2f8, 0x3f338,
1812 		0x3f340, 0x3f340,
1813 		0x3f348, 0x3f350,
1814 		0x3f35c, 0x3f364,
1815 		0x3f370, 0x3f3b8,
1816 		0x3f3c0, 0x3f3e4,
1817 		0x3f3f8, 0x3f428,
1818 		0x3f430, 0x3f448,
1819 		0x3f460, 0x3f468,
1820 		0x3f470, 0x3f49c,
1821 		0x3f4f0, 0x3f528,
1822 		0x3f530, 0x3f548,
1823 		0x3f560, 0x3f568,
1824 		0x3f570, 0x3f59c,
1825 		0x3f5f0, 0x3f638,
1826 		0x3f640, 0x3f640,
1827 		0x3f648, 0x3f650,
1828 		0x3f65c, 0x3f664,
1829 		0x3f670, 0x3f6b8,
1830 		0x3f6c0, 0x3f6e4,
1831 		0x3f6f8, 0x3f738,
1832 		0x3f740, 0x3f740,
1833 		0x3f748, 0x3f750,
1834 		0x3f75c, 0x3f764,
1835 		0x3f770, 0x3f7b8,
1836 		0x3f7c0, 0x3f7e4,
1837 		0x3f7f8, 0x3f7fc,
1838 		0x3f814, 0x3f814,
1839 		0x3f82c, 0x3f82c,
1840 		0x3f880, 0x3f88c,
1841 		0x3f8e8, 0x3f8ec,
1842 		0x3f900, 0x3f928,
1843 		0x3f930, 0x3f948,
1844 		0x3f960, 0x3f968,
1845 		0x3f970, 0x3f99c,
1846 		0x3f9f0, 0x3fa38,
1847 		0x3fa40, 0x3fa40,
1848 		0x3fa48, 0x3fa50,
1849 		0x3fa5c, 0x3fa64,
1850 		0x3fa70, 0x3fab8,
1851 		0x3fac0, 0x3fae4,
1852 		0x3faf8, 0x3fb10,
1853 		0x3fb28, 0x3fb28,
1854 		0x3fb3c, 0x3fb50,
1855 		0x3fbf0, 0x3fc10,
1856 		0x3fc28, 0x3fc28,
1857 		0x3fc3c, 0x3fc50,
1858 		0x3fcf0, 0x3fcfc,
1859 		0x40000, 0x4000c,
1860 		0x40040, 0x40050,
1861 		0x40060, 0x40068,
1862 		0x4007c, 0x4008c,
1863 		0x40094, 0x400b0,
1864 		0x400c0, 0x40144,
1865 		0x40180, 0x4018c,
1866 		0x40200, 0x40254,
1867 		0x40260, 0x40264,
1868 		0x40270, 0x40288,
1869 		0x40290, 0x40298,
1870 		0x402ac, 0x402c8,
1871 		0x402d0, 0x402e0,
1872 		0x402f0, 0x402f0,
1873 		0x40300, 0x4033c,
1874 		0x403f8, 0x403fc,
1875 		0x41304, 0x413c4,
1876 		0x41400, 0x4140c,
1877 		0x41414, 0x4141c,
1878 		0x41480, 0x414d0,
1879 		0x44000, 0x44054,
1880 		0x4405c, 0x44078,
1881 		0x440c0, 0x44174,
1882 		0x44180, 0x441ac,
1883 		0x441b4, 0x441b8,
1884 		0x441c0, 0x44254,
1885 		0x4425c, 0x44278,
1886 		0x442c0, 0x44374,
1887 		0x44380, 0x443ac,
1888 		0x443b4, 0x443b8,
1889 		0x443c0, 0x44454,
1890 		0x4445c, 0x44478,
1891 		0x444c0, 0x44574,
1892 		0x44580, 0x445ac,
1893 		0x445b4, 0x445b8,
1894 		0x445c0, 0x44654,
1895 		0x4465c, 0x44678,
1896 		0x446c0, 0x44774,
1897 		0x44780, 0x447ac,
1898 		0x447b4, 0x447b8,
1899 		0x447c0, 0x44854,
1900 		0x4485c, 0x44878,
1901 		0x448c0, 0x44974,
1902 		0x44980, 0x449ac,
1903 		0x449b4, 0x449b8,
1904 		0x449c0, 0x449fc,
1905 		0x45000, 0x45004,
1906 		0x45010, 0x45030,
1907 		0x45040, 0x45060,
1908 		0x45068, 0x45068,
1909 		0x45080, 0x45084,
1910 		0x450a0, 0x450b0,
1911 		0x45200, 0x45204,
1912 		0x45210, 0x45230,
1913 		0x45240, 0x45260,
1914 		0x45268, 0x45268,
1915 		0x45280, 0x45284,
1916 		0x452a0, 0x452b0,
1917 		0x460c0, 0x460e4,
1918 		0x47000, 0x4703c,
1919 		0x47044, 0x4708c,
1920 		0x47200, 0x47250,
1921 		0x47400, 0x47408,
1922 		0x47414, 0x47420,
1923 		0x47600, 0x47618,
1924 		0x47800, 0x47814,
1925 		0x48000, 0x4800c,
1926 		0x48040, 0x48050,
1927 		0x48060, 0x48068,
1928 		0x4807c, 0x4808c,
1929 		0x48094, 0x480b0,
1930 		0x480c0, 0x48144,
1931 		0x48180, 0x4818c,
1932 		0x48200, 0x48254,
1933 		0x48260, 0x48264,
1934 		0x48270, 0x48288,
1935 		0x48290, 0x48298,
1936 		0x482ac, 0x482c8,
1937 		0x482d0, 0x482e0,
1938 		0x482f0, 0x482f0,
1939 		0x48300, 0x4833c,
1940 		0x483f8, 0x483fc,
1941 		0x49304, 0x493c4,
1942 		0x49400, 0x4940c,
1943 		0x49414, 0x4941c,
1944 		0x49480, 0x494d0,
1945 		0x4c000, 0x4c054,
1946 		0x4c05c, 0x4c078,
1947 		0x4c0c0, 0x4c174,
1948 		0x4c180, 0x4c1ac,
1949 		0x4c1b4, 0x4c1b8,
1950 		0x4c1c0, 0x4c254,
1951 		0x4c25c, 0x4c278,
1952 		0x4c2c0, 0x4c374,
1953 		0x4c380, 0x4c3ac,
1954 		0x4c3b4, 0x4c3b8,
1955 		0x4c3c0, 0x4c454,
1956 		0x4c45c, 0x4c478,
1957 		0x4c4c0, 0x4c574,
1958 		0x4c580, 0x4c5ac,
1959 		0x4c5b4, 0x4c5b8,
1960 		0x4c5c0, 0x4c654,
1961 		0x4c65c, 0x4c678,
1962 		0x4c6c0, 0x4c774,
1963 		0x4c780, 0x4c7ac,
1964 		0x4c7b4, 0x4c7b8,
1965 		0x4c7c0, 0x4c854,
1966 		0x4c85c, 0x4c878,
1967 		0x4c8c0, 0x4c974,
1968 		0x4c980, 0x4c9ac,
1969 		0x4c9b4, 0x4c9b8,
1970 		0x4c9c0, 0x4c9fc,
1971 		0x4d000, 0x4d004,
1972 		0x4d010, 0x4d030,
1973 		0x4d040, 0x4d060,
1974 		0x4d068, 0x4d068,
1975 		0x4d080, 0x4d084,
1976 		0x4d0a0, 0x4d0b0,
1977 		0x4d200, 0x4d204,
1978 		0x4d210, 0x4d230,
1979 		0x4d240, 0x4d260,
1980 		0x4d268, 0x4d268,
1981 		0x4d280, 0x4d284,
1982 		0x4d2a0, 0x4d2b0,
1983 		0x4e0c0, 0x4e0e4,
1984 		0x4f000, 0x4f03c,
1985 		0x4f044, 0x4f08c,
1986 		0x4f200, 0x4f250,
1987 		0x4f400, 0x4f408,
1988 		0x4f414, 0x4f420,
1989 		0x4f600, 0x4f618,
1990 		0x4f800, 0x4f814,
1991 		0x50000, 0x50084,
1992 		0x50090, 0x500cc,
1993 		0x50400, 0x50400,
1994 		0x50800, 0x50884,
1995 		0x50890, 0x508cc,
1996 		0x50c00, 0x50c00,
1997 		0x51000, 0x5101c,
1998 		0x51300, 0x51308,
1999 	};
2000 
2001 	static const unsigned int t5vf_reg_ranges[] = {
2002 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2003 		VF_MPS_REG(A_MPS_VF_CTL),
2004 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2005 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2006 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2007 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2008 		FW_T4VF_MBDATA_BASE_ADDR,
2009 		FW_T4VF_MBDATA_BASE_ADDR +
2010 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2011 	};
2012 
2013 	static const unsigned int t6_reg_ranges[] = {
2014 		0x1008, 0x101c,
2015 		0x1024, 0x10a8,
2016 		0x10b4, 0x10f8,
2017 		0x1100, 0x1114,
2018 		0x111c, 0x112c,
2019 		0x1138, 0x113c,
2020 		0x1144, 0x114c,
2021 		0x1180, 0x1184,
2022 		0x1190, 0x1194,
2023 		0x11a0, 0x11a4,
2024 		0x11b0, 0x11b4,
2025 		0x11fc, 0x1274,
2026 		0x1280, 0x133c,
2027 		0x1800, 0x18fc,
2028 		0x3000, 0x302c,
2029 		0x3060, 0x30b0,
2030 		0x30b8, 0x30d8,
2031 		0x30e0, 0x30fc,
2032 		0x3140, 0x357c,
2033 		0x35a8, 0x35cc,
2034 		0x35ec, 0x35ec,
2035 		0x3600, 0x5624,
2036 		0x56cc, 0x56ec,
2037 		0x56f4, 0x5720,
2038 		0x5728, 0x575c,
2039 		0x580c, 0x5814,
2040 		0x5890, 0x589c,
2041 		0x58a4, 0x58ac,
2042 		0x58b8, 0x58bc,
2043 		0x5940, 0x595c,
2044 		0x5980, 0x598c,
2045 		0x59b0, 0x59c8,
2046 		0x59d0, 0x59dc,
2047 		0x59fc, 0x5a18,
2048 		0x5a60, 0x5a6c,
2049 		0x5a80, 0x5a8c,
2050 		0x5a94, 0x5a9c,
2051 		0x5b94, 0x5bfc,
2052 		0x5c10, 0x5e48,
2053 		0x5e50, 0x5e94,
2054 		0x5ea0, 0x5eb0,
2055 		0x5ec0, 0x5ec0,
2056 		0x5ec8, 0x5ed0,
2057 		0x5ee0, 0x5ee0,
2058 		0x5ef0, 0x5ef0,
2059 		0x5f00, 0x5f00,
2060 		0x6000, 0x6020,
2061 		0x6028, 0x6040,
2062 		0x6058, 0x609c,
2063 		0x60a8, 0x619c,
2064 		0x7700, 0x7798,
2065 		0x77c0, 0x7880,
2066 		0x78cc, 0x78fc,
2067 		0x7b00, 0x7b58,
2068 		0x7b60, 0x7b84,
2069 		0x7b8c, 0x7c54,
2070 		0x7d00, 0x7d38,
2071 		0x7d40, 0x7d84,
2072 		0x7d8c, 0x7ddc,
2073 		0x7de4, 0x7e04,
2074 		0x7e10, 0x7e1c,
2075 		0x7e24, 0x7e38,
2076 		0x7e40, 0x7e44,
2077 		0x7e4c, 0x7e78,
2078 		0x7e80, 0x7edc,
2079 		0x7ee8, 0x7efc,
2080 		0x8dc0, 0x8de4,
2081 		0x8df8, 0x8e04,
2082 		0x8e10, 0x8e84,
2083 		0x8ea0, 0x8f88,
2084 		0x8fb8, 0x9058,
2085 		0x9060, 0x9060,
2086 		0x9068, 0x90f8,
2087 		0x9100, 0x9124,
2088 		0x9400, 0x9470,
2089 		0x9600, 0x9600,
2090 		0x9608, 0x9638,
2091 		0x9640, 0x9704,
2092 		0x9710, 0x971c,
2093 		0x9800, 0x9808,
2094 		0x9820, 0x983c,
2095 		0x9850, 0x9864,
2096 		0x9c00, 0x9c6c,
2097 		0x9c80, 0x9cec,
2098 		0x9d00, 0x9d6c,
2099 		0x9d80, 0x9dec,
2100 		0x9e00, 0x9e6c,
2101 		0x9e80, 0x9eec,
2102 		0x9f00, 0x9f6c,
2103 		0x9f80, 0xa020,
2104 		0xd004, 0xd03c,
2105 		0xd100, 0xd118,
2106 		0xd200, 0xd214,
2107 		0xd220, 0xd234,
2108 		0xd240, 0xd254,
2109 		0xd260, 0xd274,
2110 		0xd280, 0xd294,
2111 		0xd2a0, 0xd2b4,
2112 		0xd2c0, 0xd2d4,
2113 		0xd2e0, 0xd2f4,
2114 		0xd300, 0xd31c,
2115 		0xdfc0, 0xdfe0,
2116 		0xe000, 0xf008,
2117 		0xf010, 0xf018,
2118 		0xf020, 0xf028,
2119 		0x11000, 0x11014,
2120 		0x11048, 0x1106c,
2121 		0x11074, 0x11088,
2122 		0x11098, 0x11120,
2123 		0x1112c, 0x1117c,
2124 		0x11190, 0x112e0,
2125 		0x11300, 0x1130c,
2126 		0x12000, 0x1206c,
2127 		0x19040, 0x1906c,
2128 		0x19078, 0x19080,
2129 		0x1908c, 0x190e8,
2130 		0x190f0, 0x190f8,
2131 		0x19100, 0x19110,
2132 		0x19120, 0x19124,
2133 		0x19150, 0x19194,
2134 		0x1919c, 0x191b0,
2135 		0x191d0, 0x191e8,
2136 		0x19238, 0x19290,
2137 		0x192a4, 0x192b0,
2138 		0x192bc, 0x192bc,
2139 		0x19348, 0x1934c,
2140 		0x193f8, 0x19418,
2141 		0x19420, 0x19428,
2142 		0x19430, 0x19444,
2143 		0x1944c, 0x1946c,
2144 		0x19474, 0x19474,
2145 		0x19490, 0x194cc,
2146 		0x194f0, 0x194f8,
2147 		0x19c00, 0x19c48,
2148 		0x19c50, 0x19c80,
2149 		0x19c94, 0x19c98,
2150 		0x19ca0, 0x19cbc,
2151 		0x19ce4, 0x19ce4,
2152 		0x19cf0, 0x19cf8,
2153 		0x19d00, 0x19d28,
2154 		0x19d50, 0x19d78,
2155 		0x19d94, 0x19d98,
2156 		0x19da0, 0x19dc8,
2157 		0x19df0, 0x19e10,
2158 		0x19e50, 0x19e6c,
2159 		0x19ea0, 0x19ebc,
2160 		0x19ec4, 0x19ef4,
2161 		0x19f04, 0x19f2c,
2162 		0x19f34, 0x19f34,
2163 		0x19f40, 0x19f50,
2164 		0x19f90, 0x19fac,
2165 		0x19fc4, 0x19fc8,
2166 		0x19fd0, 0x19fe4,
2167 		0x1a000, 0x1a004,
2168 		0x1a010, 0x1a06c,
2169 		0x1a0b0, 0x1a0e4,
2170 		0x1a0ec, 0x1a0f8,
2171 		0x1a100, 0x1a108,
2172 		0x1a114, 0x1a120,
2173 		0x1a128, 0x1a130,
2174 		0x1a138, 0x1a138,
2175 		0x1a190, 0x1a1c4,
2176 		0x1a1fc, 0x1a1fc,
2177 		0x1e008, 0x1e00c,
2178 		0x1e040, 0x1e044,
2179 		0x1e04c, 0x1e04c,
2180 		0x1e284, 0x1e290,
2181 		0x1e2c0, 0x1e2c0,
2182 		0x1e2e0, 0x1e2e0,
2183 		0x1e300, 0x1e384,
2184 		0x1e3c0, 0x1e3c8,
2185 		0x1e408, 0x1e40c,
2186 		0x1e440, 0x1e444,
2187 		0x1e44c, 0x1e44c,
2188 		0x1e684, 0x1e690,
2189 		0x1e6c0, 0x1e6c0,
2190 		0x1e6e0, 0x1e6e0,
2191 		0x1e700, 0x1e784,
2192 		0x1e7c0, 0x1e7c8,
2193 		0x1e808, 0x1e80c,
2194 		0x1e840, 0x1e844,
2195 		0x1e84c, 0x1e84c,
2196 		0x1ea84, 0x1ea90,
2197 		0x1eac0, 0x1eac0,
2198 		0x1eae0, 0x1eae0,
2199 		0x1eb00, 0x1eb84,
2200 		0x1ebc0, 0x1ebc8,
2201 		0x1ec08, 0x1ec0c,
2202 		0x1ec40, 0x1ec44,
2203 		0x1ec4c, 0x1ec4c,
2204 		0x1ee84, 0x1ee90,
2205 		0x1eec0, 0x1eec0,
2206 		0x1eee0, 0x1eee0,
2207 		0x1ef00, 0x1ef84,
2208 		0x1efc0, 0x1efc8,
2209 		0x1f008, 0x1f00c,
2210 		0x1f040, 0x1f044,
2211 		0x1f04c, 0x1f04c,
2212 		0x1f284, 0x1f290,
2213 		0x1f2c0, 0x1f2c0,
2214 		0x1f2e0, 0x1f2e0,
2215 		0x1f300, 0x1f384,
2216 		0x1f3c0, 0x1f3c8,
2217 		0x1f408, 0x1f40c,
2218 		0x1f440, 0x1f444,
2219 		0x1f44c, 0x1f44c,
2220 		0x1f684, 0x1f690,
2221 		0x1f6c0, 0x1f6c0,
2222 		0x1f6e0, 0x1f6e0,
2223 		0x1f700, 0x1f784,
2224 		0x1f7c0, 0x1f7c8,
2225 		0x1f808, 0x1f80c,
2226 		0x1f840, 0x1f844,
2227 		0x1f84c, 0x1f84c,
2228 		0x1fa84, 0x1fa90,
2229 		0x1fac0, 0x1fac0,
2230 		0x1fae0, 0x1fae0,
2231 		0x1fb00, 0x1fb84,
2232 		0x1fbc0, 0x1fbc8,
2233 		0x1fc08, 0x1fc0c,
2234 		0x1fc40, 0x1fc44,
2235 		0x1fc4c, 0x1fc4c,
2236 		0x1fe84, 0x1fe90,
2237 		0x1fec0, 0x1fec0,
2238 		0x1fee0, 0x1fee0,
2239 		0x1ff00, 0x1ff84,
2240 		0x1ffc0, 0x1ffc8,
2241 		0x30000, 0x30030,
2242 		0x30038, 0x30038,
2243 		0x30040, 0x30040,
2244 		0x30048, 0x30048,
2245 		0x30050, 0x30050,
2246 		0x3005c, 0x30060,
2247 		0x30068, 0x30068,
2248 		0x30070, 0x30070,
2249 		0x30100, 0x30168,
2250 		0x30190, 0x301a0,
2251 		0x301a8, 0x301b8,
2252 		0x301c4, 0x301c8,
2253 		0x301d0, 0x301d0,
2254 		0x30200, 0x30320,
2255 		0x30400, 0x304b4,
2256 		0x304c0, 0x3052c,
2257 		0x30540, 0x3061c,
2258 		0x30800, 0x308a0,
2259 		0x308c0, 0x30908,
2260 		0x30910, 0x309b8,
2261 		0x30a00, 0x30a04,
2262 		0x30a0c, 0x30a14,
2263 		0x30a1c, 0x30a2c,
2264 		0x30a44, 0x30a50,
2265 		0x30a74, 0x30a74,
2266 		0x30a7c, 0x30afc,
2267 		0x30b08, 0x30c24,
2268 		0x30d00, 0x30d14,
2269 		0x30d1c, 0x30d3c,
2270 		0x30d44, 0x30d4c,
2271 		0x30d54, 0x30d74,
2272 		0x30d7c, 0x30d7c,
2273 		0x30de0, 0x30de0,
2274 		0x30e00, 0x30ed4,
2275 		0x30f00, 0x30fa4,
2276 		0x30fc0, 0x30fc4,
2277 		0x31000, 0x31004,
2278 		0x31080, 0x310fc,
2279 		0x31208, 0x31220,
2280 		0x3123c, 0x31254,
2281 		0x31300, 0x31300,
2282 		0x31308, 0x3131c,
2283 		0x31338, 0x3133c,
2284 		0x31380, 0x31380,
2285 		0x31388, 0x313a8,
2286 		0x313b4, 0x313b4,
2287 		0x31400, 0x31420,
2288 		0x31438, 0x3143c,
2289 		0x31480, 0x31480,
2290 		0x314a8, 0x314a8,
2291 		0x314b0, 0x314b4,
2292 		0x314c8, 0x314d4,
2293 		0x31a40, 0x31a4c,
2294 		0x31af0, 0x31b20,
2295 		0x31b38, 0x31b3c,
2296 		0x31b80, 0x31b80,
2297 		0x31ba8, 0x31ba8,
2298 		0x31bb0, 0x31bb4,
2299 		0x31bc8, 0x31bd4,
2300 		0x32140, 0x3218c,
2301 		0x321f0, 0x321f4,
2302 		0x32200, 0x32200,
2303 		0x32218, 0x32218,
2304 		0x32400, 0x32400,
2305 		0x32408, 0x3241c,
2306 		0x32618, 0x32620,
2307 		0x32664, 0x32664,
2308 		0x326a8, 0x326a8,
2309 		0x326ec, 0x326ec,
2310 		0x32a00, 0x32abc,
2311 		0x32b00, 0x32b38,
2312 		0x32b40, 0x32b58,
2313 		0x32b60, 0x32b78,
2314 		0x32c00, 0x32c00,
2315 		0x32c08, 0x32c3c,
2316 		0x32e00, 0x32e2c,
2317 		0x32f00, 0x32f2c,
2318 		0x33000, 0x3302c,
2319 		0x33034, 0x33050,
2320 		0x33058, 0x33058,
2321 		0x33060, 0x3308c,
2322 		0x3309c, 0x330ac,
2323 		0x330c0, 0x330c0,
2324 		0x330c8, 0x330d0,
2325 		0x330d8, 0x330e0,
2326 		0x330ec, 0x3312c,
2327 		0x33134, 0x33150,
2328 		0x33158, 0x33158,
2329 		0x33160, 0x3318c,
2330 		0x3319c, 0x331ac,
2331 		0x331c0, 0x331c0,
2332 		0x331c8, 0x331d0,
2333 		0x331d8, 0x331e0,
2334 		0x331ec, 0x33290,
2335 		0x33298, 0x332c4,
2336 		0x332e4, 0x33390,
2337 		0x33398, 0x333c4,
2338 		0x333e4, 0x3342c,
2339 		0x33434, 0x33450,
2340 		0x33458, 0x33458,
2341 		0x33460, 0x3348c,
2342 		0x3349c, 0x334ac,
2343 		0x334c0, 0x334c0,
2344 		0x334c8, 0x334d0,
2345 		0x334d8, 0x334e0,
2346 		0x334ec, 0x3352c,
2347 		0x33534, 0x33550,
2348 		0x33558, 0x33558,
2349 		0x33560, 0x3358c,
2350 		0x3359c, 0x335ac,
2351 		0x335c0, 0x335c0,
2352 		0x335c8, 0x335d0,
2353 		0x335d8, 0x335e0,
2354 		0x335ec, 0x33690,
2355 		0x33698, 0x336c4,
2356 		0x336e4, 0x33790,
2357 		0x33798, 0x337c4,
2358 		0x337e4, 0x337fc,
2359 		0x33814, 0x33814,
2360 		0x33854, 0x33868,
2361 		0x33880, 0x3388c,
2362 		0x338c0, 0x338d0,
2363 		0x338e8, 0x338ec,
2364 		0x33900, 0x3392c,
2365 		0x33934, 0x33950,
2366 		0x33958, 0x33958,
2367 		0x33960, 0x3398c,
2368 		0x3399c, 0x339ac,
2369 		0x339c0, 0x339c0,
2370 		0x339c8, 0x339d0,
2371 		0x339d8, 0x339e0,
2372 		0x339ec, 0x33a90,
2373 		0x33a98, 0x33ac4,
2374 		0x33ae4, 0x33b10,
2375 		0x33b24, 0x33b28,
2376 		0x33b38, 0x33b50,
2377 		0x33bf0, 0x33c10,
2378 		0x33c24, 0x33c28,
2379 		0x33c38, 0x33c50,
2380 		0x33cf0, 0x33cfc,
2381 		0x34000, 0x34030,
2382 		0x34038, 0x34038,
2383 		0x34040, 0x34040,
2384 		0x34048, 0x34048,
2385 		0x34050, 0x34050,
2386 		0x3405c, 0x34060,
2387 		0x34068, 0x34068,
2388 		0x34070, 0x34070,
2389 		0x34100, 0x34168,
2390 		0x34190, 0x341a0,
2391 		0x341a8, 0x341b8,
2392 		0x341c4, 0x341c8,
2393 		0x341d0, 0x341d0,
2394 		0x34200, 0x34320,
2395 		0x34400, 0x344b4,
2396 		0x344c0, 0x3452c,
2397 		0x34540, 0x3461c,
2398 		0x34800, 0x348a0,
2399 		0x348c0, 0x34908,
2400 		0x34910, 0x349b8,
2401 		0x34a00, 0x34a04,
2402 		0x34a0c, 0x34a14,
2403 		0x34a1c, 0x34a2c,
2404 		0x34a44, 0x34a50,
2405 		0x34a74, 0x34a74,
2406 		0x34a7c, 0x34afc,
2407 		0x34b08, 0x34c24,
2408 		0x34d00, 0x34d14,
2409 		0x34d1c, 0x34d3c,
2410 		0x34d44, 0x34d4c,
2411 		0x34d54, 0x34d74,
2412 		0x34d7c, 0x34d7c,
2413 		0x34de0, 0x34de0,
2414 		0x34e00, 0x34ed4,
2415 		0x34f00, 0x34fa4,
2416 		0x34fc0, 0x34fc4,
2417 		0x35000, 0x35004,
2418 		0x35080, 0x350fc,
2419 		0x35208, 0x35220,
2420 		0x3523c, 0x35254,
2421 		0x35300, 0x35300,
2422 		0x35308, 0x3531c,
2423 		0x35338, 0x3533c,
2424 		0x35380, 0x35380,
2425 		0x35388, 0x353a8,
2426 		0x353b4, 0x353b4,
2427 		0x35400, 0x35420,
2428 		0x35438, 0x3543c,
2429 		0x35480, 0x35480,
2430 		0x354a8, 0x354a8,
2431 		0x354b0, 0x354b4,
2432 		0x354c8, 0x354d4,
2433 		0x35a40, 0x35a4c,
2434 		0x35af0, 0x35b20,
2435 		0x35b38, 0x35b3c,
2436 		0x35b80, 0x35b80,
2437 		0x35ba8, 0x35ba8,
2438 		0x35bb0, 0x35bb4,
2439 		0x35bc8, 0x35bd4,
2440 		0x36140, 0x3618c,
2441 		0x361f0, 0x361f4,
2442 		0x36200, 0x36200,
2443 		0x36218, 0x36218,
2444 		0x36400, 0x36400,
2445 		0x36408, 0x3641c,
2446 		0x36618, 0x36620,
2447 		0x36664, 0x36664,
2448 		0x366a8, 0x366a8,
2449 		0x366ec, 0x366ec,
2450 		0x36a00, 0x36abc,
2451 		0x36b00, 0x36b38,
2452 		0x36b40, 0x36b58,
2453 		0x36b60, 0x36b78,
2454 		0x36c00, 0x36c00,
2455 		0x36c08, 0x36c3c,
2456 		0x36e00, 0x36e2c,
2457 		0x36f00, 0x36f2c,
2458 		0x37000, 0x3702c,
2459 		0x37034, 0x37050,
2460 		0x37058, 0x37058,
2461 		0x37060, 0x3708c,
2462 		0x3709c, 0x370ac,
2463 		0x370c0, 0x370c0,
2464 		0x370c8, 0x370d0,
2465 		0x370d8, 0x370e0,
2466 		0x370ec, 0x3712c,
2467 		0x37134, 0x37150,
2468 		0x37158, 0x37158,
2469 		0x37160, 0x3718c,
2470 		0x3719c, 0x371ac,
2471 		0x371c0, 0x371c0,
2472 		0x371c8, 0x371d0,
2473 		0x371d8, 0x371e0,
2474 		0x371ec, 0x37290,
2475 		0x37298, 0x372c4,
2476 		0x372e4, 0x37390,
2477 		0x37398, 0x373c4,
2478 		0x373e4, 0x3742c,
2479 		0x37434, 0x37450,
2480 		0x37458, 0x37458,
2481 		0x37460, 0x3748c,
2482 		0x3749c, 0x374ac,
2483 		0x374c0, 0x374c0,
2484 		0x374c8, 0x374d0,
2485 		0x374d8, 0x374e0,
2486 		0x374ec, 0x3752c,
2487 		0x37534, 0x37550,
2488 		0x37558, 0x37558,
2489 		0x37560, 0x3758c,
2490 		0x3759c, 0x375ac,
2491 		0x375c0, 0x375c0,
2492 		0x375c8, 0x375d0,
2493 		0x375d8, 0x375e0,
2494 		0x375ec, 0x37690,
2495 		0x37698, 0x376c4,
2496 		0x376e4, 0x37790,
2497 		0x37798, 0x377c4,
2498 		0x377e4, 0x377fc,
2499 		0x37814, 0x37814,
2500 		0x37854, 0x37868,
2501 		0x37880, 0x3788c,
2502 		0x378c0, 0x378d0,
2503 		0x378e8, 0x378ec,
2504 		0x37900, 0x3792c,
2505 		0x37934, 0x37950,
2506 		0x37958, 0x37958,
2507 		0x37960, 0x3798c,
2508 		0x3799c, 0x379ac,
2509 		0x379c0, 0x379c0,
2510 		0x379c8, 0x379d0,
2511 		0x379d8, 0x379e0,
2512 		0x379ec, 0x37a90,
2513 		0x37a98, 0x37ac4,
2514 		0x37ae4, 0x37b10,
2515 		0x37b24, 0x37b28,
2516 		0x37b38, 0x37b50,
2517 		0x37bf0, 0x37c10,
2518 		0x37c24, 0x37c28,
2519 		0x37c38, 0x37c50,
2520 		0x37cf0, 0x37cfc,
2521 		0x40040, 0x40040,
2522 		0x40080, 0x40084,
2523 		0x40100, 0x40100,
2524 		0x40140, 0x401bc,
2525 		0x40200, 0x40214,
2526 		0x40228, 0x40228,
2527 		0x40240, 0x40258,
2528 		0x40280, 0x40280,
2529 		0x40304, 0x40304,
2530 		0x40330, 0x4033c,
2531 		0x41304, 0x413c8,
2532 		0x413d0, 0x413dc,
2533 		0x413f0, 0x413f0,
2534 		0x41400, 0x4140c,
2535 		0x41414, 0x4141c,
2536 		0x41480, 0x414d0,
2537 		0x44000, 0x4407c,
2538 		0x440c0, 0x441ac,
2539 		0x441b4, 0x4427c,
2540 		0x442c0, 0x443ac,
2541 		0x443b4, 0x4447c,
2542 		0x444c0, 0x445ac,
2543 		0x445b4, 0x4467c,
2544 		0x446c0, 0x447ac,
2545 		0x447b4, 0x4487c,
2546 		0x448c0, 0x449ac,
2547 		0x449b4, 0x44a7c,
2548 		0x44ac0, 0x44bac,
2549 		0x44bb4, 0x44c7c,
2550 		0x44cc0, 0x44dac,
2551 		0x44db4, 0x44e7c,
2552 		0x44ec0, 0x44fac,
2553 		0x44fb4, 0x4507c,
2554 		0x450c0, 0x451ac,
2555 		0x451b4, 0x451fc,
2556 		0x45800, 0x45804,
2557 		0x45810, 0x45830,
2558 		0x45840, 0x45860,
2559 		0x45868, 0x45868,
2560 		0x45880, 0x45884,
2561 		0x458a0, 0x458b0,
2562 		0x45a00, 0x45a04,
2563 		0x45a10, 0x45a30,
2564 		0x45a40, 0x45a60,
2565 		0x45a68, 0x45a68,
2566 		0x45a80, 0x45a84,
2567 		0x45aa0, 0x45ab0,
2568 		0x460c0, 0x460e4,
2569 		0x47000, 0x4703c,
2570 		0x47044, 0x4708c,
2571 		0x47200, 0x47250,
2572 		0x47400, 0x47408,
2573 		0x47414, 0x47420,
2574 		0x47600, 0x47618,
2575 		0x47800, 0x47814,
2576 		0x47820, 0x4782c,
2577 		0x50000, 0x50084,
2578 		0x50090, 0x500cc,
2579 		0x50300, 0x50384,
2580 		0x50400, 0x50400,
2581 		0x50800, 0x50884,
2582 		0x50890, 0x508cc,
2583 		0x50b00, 0x50b84,
2584 		0x50c00, 0x50c00,
2585 		0x51000, 0x51020,
2586 		0x51028, 0x510b0,
2587 		0x51300, 0x51324,
2588 	};
2589 
2590 	static const unsigned int t6vf_reg_ranges[] = {
2591 		VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS),
2592 		VF_MPS_REG(A_MPS_VF_CTL),
2593 		VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H),
2594 		VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION),
2595 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL),
2596 		VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS),
2597 		FW_T6VF_MBDATA_BASE_ADDR,
2598 		FW_T6VF_MBDATA_BASE_ADDR +
2599 		((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4),
2600 	};
2601 
2602 	u32 *buf_end = (u32 *)(buf + buf_size);
2603 	const unsigned int *reg_ranges;
2604 	int reg_ranges_size, range;
2605 	unsigned int chip_version = chip_id(adap);
2606 
2607 	/*
2608 	 * Select the right set of register ranges to dump depending on the
2609 	 * adapter chip type.
2610 	 */
2611 	switch (chip_version) {
2612 	case CHELSIO_T4:
2613 		if (adap->flags & IS_VF) {
2614 			reg_ranges = t4vf_reg_ranges;
2615 			reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges);
2616 		} else {
2617 			reg_ranges = t4_reg_ranges;
2618 			reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2619 		}
2620 		break;
2621 
2622 	case CHELSIO_T5:
2623 		if (adap->flags & IS_VF) {
2624 			reg_ranges = t5vf_reg_ranges;
2625 			reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges);
2626 		} else {
2627 			reg_ranges = t5_reg_ranges;
2628 			reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2629 		}
2630 		break;
2631 
2632 	case CHELSIO_T6:
2633 		if (adap->flags & IS_VF) {
2634 			reg_ranges = t6vf_reg_ranges;
2635 			reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges);
2636 		} else {
2637 			reg_ranges = t6_reg_ranges;
2638 			reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2639 		}
2640 		break;
2641 
2642 	default:
2643 		CH_ERR(adap,
2644 			"Unsupported chip version %d\n", chip_version);
2645 		return;
2646 	}
2647 
2648 	/*
2649 	 * Clear the register buffer and insert the appropriate register
2650 	 * values selected by the above register ranges.
2651 	 */
2652 	memset(buf, 0, buf_size);
2653 	for (range = 0; range < reg_ranges_size; range += 2) {
2654 		unsigned int reg = reg_ranges[range];
2655 		unsigned int last_reg = reg_ranges[range + 1];
2656 		u32 *bufp = (u32 *)(buf + reg);
2657 
2658 		/*
2659 		 * Iterate across the register range filling in the register
2660 		 * buffer but don't write past the end of the register buffer.
2661 		 */
2662 		while (reg <= last_reg && bufp < buf_end) {
2663 			*bufp++ = t4_read_reg(adap, reg);
2664 			reg += sizeof(u32);
2665 		}
2666 	}
2667 }
2668 
2669 /*
2670  * Partial EEPROM Vital Product Data structure.  Includes only the ID and
2671  * VPD-R sections.
2672  */
2673 struct t4_vpd_hdr {
2674 	u8  id_tag;
2675 	u8  id_len[2];
2676 	u8  id_data[ID_LEN];
2677 	u8  vpdr_tag;
2678 	u8  vpdr_len[2];
2679 };
2680 
2681 /*
2682  * EEPROM reads take a few tens of us while writes can take a bit over 5 ms.
2683  */
2684 #define EEPROM_DELAY		10		/* 10us per poll spin */
2685 #define EEPROM_MAX_POLL		5000		/* x 5000 == 50ms */
2686 
2687 #define EEPROM_STAT_ADDR	0x7bfc
2688 #define VPD_BASE		0x400
2689 #define VPD_BASE_OLD		0
2690 #define VPD_LEN			1024
2691 #define VPD_INFO_FLD_HDR_SIZE	3
2692 #define CHELSIO_VPD_UNIQUE_ID	0x82
2693 
2694 /*
2695  * Small utility function to wait till any outstanding VPD Access is complete.
2696  * We have a per-adapter state variable "VPD Busy" to indicate when we have a
2697  * VPD Access in flight.  This allows us to handle the problem of having a
2698  * previous VPD Access time out and prevent an attempt to inject a new VPD
2699  * Request before any in-flight VPD reguest has completed.
2700  */
2701 static int t4_seeprom_wait(struct adapter *adapter)
2702 {
2703 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2704 	int max_poll;
2705 
2706 	/*
2707 	 * If no VPD Access is in flight, we can just return success right
2708 	 * away.
2709 	 */
2710 	if (!adapter->vpd_busy)
2711 		return 0;
2712 
2713 	/*
2714 	 * Poll the VPD Capability Address/Flag register waiting for it
2715 	 * to indicate that the operation is complete.
2716 	 */
2717 	max_poll = EEPROM_MAX_POLL;
2718 	do {
2719 		u16 val;
2720 
2721 		udelay(EEPROM_DELAY);
2722 		t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val);
2723 
2724 		/*
2725 		 * If the operation is complete, mark the VPD as no longer
2726 		 * busy and return success.
2727 		 */
2728 		if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) {
2729 			adapter->vpd_busy = 0;
2730 			return 0;
2731 		}
2732 	} while (--max_poll);
2733 
2734 	/*
2735 	 * Failure!  Note that we leave the VPD Busy status set in order to
2736 	 * avoid pushing a new VPD Access request into the VPD Capability till
2737 	 * the current operation eventually succeeds.  It's a bug to issue a
2738 	 * new request when an existing request is in flight and will result
2739 	 * in corrupt hardware state.
2740 	 */
2741 	return -ETIMEDOUT;
2742 }
2743 
2744 /**
2745  *	t4_seeprom_read - read a serial EEPROM location
2746  *	@adapter: adapter to read
2747  *	@addr: EEPROM virtual address
2748  *	@data: where to store the read data
2749  *
2750  *	Read a 32-bit word from a location in serial EEPROM using the card's PCI
2751  *	VPD capability.  Note that this function must be called with a virtual
2752  *	address.
2753  */
2754 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data)
2755 {
2756 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2757 	int ret;
2758 
2759 	/*
2760 	 * VPD Accesses must alway be 4-byte aligned!
2761 	 */
2762 	if (addr >= EEPROMVSIZE || (addr & 3))
2763 		return -EINVAL;
2764 
2765 	/*
2766 	 * Wait for any previous operation which may still be in flight to
2767 	 * complete.
2768 	 */
2769 	ret = t4_seeprom_wait(adapter);
2770 	if (ret) {
2771 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2772 		return ret;
2773 	}
2774 
2775 	/*
2776 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2777 	 * for our request to complete.  If it doesn't complete, note the
2778 	 * error and return it to our caller.  Note that we do not reset the
2779 	 * VPD Busy status!
2780 	 */
2781 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr);
2782 	adapter->vpd_busy = 1;
2783 	adapter->vpd_flag = PCI_VPD_ADDR_F;
2784 	ret = t4_seeprom_wait(adapter);
2785 	if (ret) {
2786 		CH_ERR(adapter, "VPD read of address %#x failed\n", addr);
2787 		return ret;
2788 	}
2789 
2790 	/*
2791 	 * Grab the returned data, swizzle it into our endianness and
2792 	 * return success.
2793 	 */
2794 	t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data);
2795 	*data = le32_to_cpu(*data);
2796 	return 0;
2797 }
2798 
2799 /**
2800  *	t4_seeprom_write - write a serial EEPROM location
2801  *	@adapter: adapter to write
2802  *	@addr: virtual EEPROM address
2803  *	@data: value to write
2804  *
2805  *	Write a 32-bit word to a location in serial EEPROM using the card's PCI
2806  *	VPD capability.  Note that this function must be called with a virtual
2807  *	address.
2808  */
2809 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data)
2810 {
2811 	unsigned int base = adapter->params.pci.vpd_cap_addr;
2812 	int ret;
2813 	u32 stats_reg;
2814 	int max_poll;
2815 
2816 	/*
2817 	 * VPD Accesses must alway be 4-byte aligned!
2818 	 */
2819 	if (addr >= EEPROMVSIZE || (addr & 3))
2820 		return -EINVAL;
2821 
2822 	/*
2823 	 * Wait for any previous operation which may still be in flight to
2824 	 * complete.
2825 	 */
2826 	ret = t4_seeprom_wait(adapter);
2827 	if (ret) {
2828 		CH_ERR(adapter, "VPD still busy from previous operation\n");
2829 		return ret;
2830 	}
2831 
2832 	/*
2833 	 * Issue our new VPD Read request, mark the VPD as being busy and wait
2834 	 * for our request to complete.  If it doesn't complete, note the
2835 	 * error and return it to our caller.  Note that we do not reset the
2836 	 * VPD Busy status!
2837 	 */
2838 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA,
2839 				 cpu_to_le32(data));
2840 	t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR,
2841 				 (u16)addr | PCI_VPD_ADDR_F);
2842 	adapter->vpd_busy = 1;
2843 	adapter->vpd_flag = 0;
2844 	ret = t4_seeprom_wait(adapter);
2845 	if (ret) {
2846 		CH_ERR(adapter, "VPD write of address %#x failed\n", addr);
2847 		return ret;
2848 	}
2849 
2850 	/*
2851 	 * Reset PCI_VPD_DATA register after a transaction and wait for our
2852 	 * request to complete. If it doesn't complete, return error.
2853 	 */
2854 	t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0);
2855 	max_poll = EEPROM_MAX_POLL;
2856 	do {
2857 		udelay(EEPROM_DELAY);
2858 		t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg);
2859 	} while ((stats_reg & 0x1) && --max_poll);
2860 	if (!max_poll)
2861 		return -ETIMEDOUT;
2862 
2863 	/* Return success! */
2864 	return 0;
2865 }
2866 
2867 /**
2868  *	t4_eeprom_ptov - translate a physical EEPROM address to virtual
2869  *	@phys_addr: the physical EEPROM address
2870  *	@fn: the PCI function number
2871  *	@sz: size of function-specific area
2872  *
2873  *	Translate a physical EEPROM address to virtual.  The first 1K is
2874  *	accessed through virtual addresses starting at 31K, the rest is
2875  *	accessed through virtual addresses starting at 0.
2876  *
2877  *	The mapping is as follows:
2878  *	[0..1K) -> [31K..32K)
2879  *	[1K..1K+A) -> [ES-A..ES)
2880  *	[1K+A..ES) -> [0..ES-A-1K)
2881  *
2882  *	where A = @fn * @sz, and ES = EEPROM size.
2883  */
2884 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2885 {
2886 	fn *= sz;
2887 	if (phys_addr < 1024)
2888 		return phys_addr + (31 << 10);
2889 	if (phys_addr < 1024 + fn)
2890 		return EEPROMSIZE - fn + phys_addr - 1024;
2891 	if (phys_addr < EEPROMSIZE)
2892 		return phys_addr - 1024 - fn;
2893 	return -EINVAL;
2894 }
2895 
2896 /**
2897  *	t4_seeprom_wp - enable/disable EEPROM write protection
2898  *	@adapter: the adapter
2899  *	@enable: whether to enable or disable write protection
2900  *
2901  *	Enables or disables write protection on the serial EEPROM.
2902  */
2903 int t4_seeprom_wp(struct adapter *adapter, int enable)
2904 {
2905 	return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0);
2906 }
2907 
2908 /**
2909  *	get_vpd_keyword_val - Locates an information field keyword in the VPD
2910  *	@v: Pointer to buffered vpd data structure
2911  *	@kw: The keyword to search for
2912  *
2913  *	Returns the value of the information field keyword or
2914  *	-ENOENT otherwise.
2915  */
2916 static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw)
2917 {
2918 	int i;
2919 	unsigned int offset , len;
2920 	const u8 *buf = (const u8 *)v;
2921 	const u8 *vpdr_len = &v->vpdr_len[0];
2922 	offset = sizeof(struct t4_vpd_hdr);
2923 	len =  (u16)vpdr_len[0] + ((u16)vpdr_len[1] << 8);
2924 
2925 	if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) {
2926 		return -ENOENT;
2927 	}
2928 
2929 	for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) {
2930 		if(memcmp(buf + i , kw , 2) == 0){
2931 			i += VPD_INFO_FLD_HDR_SIZE;
2932 			return i;
2933 		}
2934 
2935 		i += VPD_INFO_FLD_HDR_SIZE + buf[i+2];
2936 	}
2937 
2938 	return -ENOENT;
2939 }
2940 
2941 
2942 /**
2943  *	get_vpd_params - read VPD parameters from VPD EEPROM
2944  *	@adapter: adapter to read
2945  *	@p: where to store the parameters
2946  *	@vpd: caller provided temporary space to read the VPD into
2947  *
2948  *	Reads card parameters stored in VPD EEPROM.
2949  */
2950 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p,
2951     u8 *vpd)
2952 {
2953 	int i, ret, addr;
2954 	int ec, sn, pn, na;
2955 	u8 csum;
2956 	const struct t4_vpd_hdr *v;
2957 
2958 	/*
2959 	 * Card information normally starts at VPD_BASE but early cards had
2960 	 * it at 0.
2961 	 */
2962 	ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd));
2963 	if (ret)
2964 		return (ret);
2965 
2966 	/*
2967 	 * The VPD shall have a unique identifier specified by the PCI SIG.
2968 	 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2969 	 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2970 	 * is expected to automatically put this entry at the
2971 	 * beginning of the VPD.
2972 	 */
2973 	addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2974 
2975 	for (i = 0; i < VPD_LEN; i += 4) {
2976 		ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i));
2977 		if (ret)
2978 			return ret;
2979 	}
2980  	v = (const struct t4_vpd_hdr *)vpd;
2981 
2982 #define FIND_VPD_KW(var,name) do { \
2983 	var = get_vpd_keyword_val(v , name); \
2984 	if (var < 0) { \
2985 		CH_ERR(adapter, "missing VPD keyword " name "\n"); \
2986 		return -EINVAL; \
2987 	} \
2988 } while (0)
2989 
2990 	FIND_VPD_KW(i, "RV");
2991 	for (csum = 0; i >= 0; i--)
2992 		csum += vpd[i];
2993 
2994 	if (csum) {
2995 		CH_ERR(adapter,
2996 			"corrupted VPD EEPROM, actual csum %u\n", csum);
2997 		return -EINVAL;
2998 	}
2999 
3000 	FIND_VPD_KW(ec, "EC");
3001 	FIND_VPD_KW(sn, "SN");
3002 	FIND_VPD_KW(pn, "PN");
3003 	FIND_VPD_KW(na, "NA");
3004 #undef FIND_VPD_KW
3005 
3006 	memcpy(p->id, v->id_data, ID_LEN);
3007 	strstrip(p->id);
3008 	memcpy(p->ec, vpd + ec, EC_LEN);
3009 	strstrip(p->ec);
3010 	i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2];
3011 	memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
3012 	strstrip(p->sn);
3013 	i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2];
3014 	memcpy(p->pn, vpd + pn, min(i, PN_LEN));
3015 	strstrip((char *)p->pn);
3016 	i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2];
3017 	memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
3018 	strstrip((char *)p->na);
3019 
3020 	return 0;
3021 }
3022 
3023 /* serial flash and firmware constants and flash config file constants */
3024 enum {
3025 	SF_ATTEMPTS = 10,	/* max retries for SF operations */
3026 
3027 	/* flash command opcodes */
3028 	SF_PROG_PAGE    = 2,	/* program page */
3029 	SF_WR_DISABLE   = 4,	/* disable writes */
3030 	SF_RD_STATUS    = 5,	/* read status register */
3031 	SF_WR_ENABLE    = 6,	/* enable writes */
3032 	SF_RD_DATA_FAST = 0xb,	/* read flash */
3033 	SF_RD_ID	= 0x9f,	/* read ID */
3034 	SF_ERASE_SECTOR = 0xd8,	/* erase sector */
3035 };
3036 
3037 /**
3038  *	sf1_read - read data from the serial flash
3039  *	@adapter: the adapter
3040  *	@byte_cnt: number of bytes to read
3041  *	@cont: whether another operation will be chained
3042  *	@lock: whether to lock SF for PL access only
3043  *	@valp: where to store the read data
3044  *
3045  *	Reads up to 4 bytes of data from the serial flash.  The location of
3046  *	the read needs to be specified prior to calling this by issuing the
3047  *	appropriate commands to the serial flash.
3048  */
3049 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
3050 		    int lock, u32 *valp)
3051 {
3052 	int ret;
3053 
3054 	if (!byte_cnt || byte_cnt > 4)
3055 		return -EINVAL;
3056 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3057 		return -EBUSY;
3058 	t4_write_reg(adapter, A_SF_OP,
3059 		     V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1));
3060 	ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3061 	if (!ret)
3062 		*valp = t4_read_reg(adapter, A_SF_DATA);
3063 	return ret;
3064 }
3065 
3066 /**
3067  *	sf1_write - write data to the serial flash
3068  *	@adapter: the adapter
3069  *	@byte_cnt: number of bytes to write
3070  *	@cont: whether another operation will be chained
3071  *	@lock: whether to lock SF for PL access only
3072  *	@val: value to write
3073  *
3074  *	Writes up to 4 bytes of data to the serial flash.  The location of
3075  *	the write needs to be specified prior to calling this by issuing the
3076  *	appropriate commands to the serial flash.
3077  */
3078 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
3079 		     int lock, u32 val)
3080 {
3081 	if (!byte_cnt || byte_cnt > 4)
3082 		return -EINVAL;
3083 	if (t4_read_reg(adapter, A_SF_OP) & F_BUSY)
3084 		return -EBUSY;
3085 	t4_write_reg(adapter, A_SF_DATA, val);
3086 	t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) |
3087 		     V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1));
3088 	return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5);
3089 }
3090 
3091 /**
3092  *	flash_wait_op - wait for a flash operation to complete
3093  *	@adapter: the adapter
3094  *	@attempts: max number of polls of the status register
3095  *	@delay: delay between polls in ms
3096  *
3097  *	Wait for a flash operation to complete by polling the status register.
3098  */
3099 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3100 {
3101 	int ret;
3102 	u32 status;
3103 
3104 	while (1) {
3105 		if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3106 		    (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3107 			return ret;
3108 		if (!(status & 1))
3109 			return 0;
3110 		if (--attempts == 0)
3111 			return -EAGAIN;
3112 		if (delay)
3113 			msleep(delay);
3114 	}
3115 }
3116 
3117 /**
3118  *	t4_read_flash - read words from serial flash
3119  *	@adapter: the adapter
3120  *	@addr: the start address for the read
3121  *	@nwords: how many 32-bit words to read
3122  *	@data: where to store the read data
3123  *	@byte_oriented: whether to store data as bytes or as words
3124  *
3125  *	Read the specified number of 32-bit words from the serial flash.
3126  *	If @byte_oriented is set the read data is stored as a byte array
3127  *	(i.e., big-endian), otherwise as 32-bit words in the platform's
3128  *	natural endianness.
3129  */
3130 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3131 		  unsigned int nwords, u32 *data, int byte_oriented)
3132 {
3133 	int ret;
3134 
3135 	if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3136 		return -EINVAL;
3137 
3138 	addr = swab32(addr) | SF_RD_DATA_FAST;
3139 
3140 	if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3141 	    (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3142 		return ret;
3143 
3144 	for ( ; nwords; nwords--, data++) {
3145 		ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3146 		if (nwords == 1)
3147 			t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3148 		if (ret)
3149 			return ret;
3150 		if (byte_oriented)
3151 			*data = (__force __u32)(cpu_to_be32(*data));
3152 	}
3153 	return 0;
3154 }
3155 
3156 /**
3157  *	t4_write_flash - write up to a page of data to the serial flash
3158  *	@adapter: the adapter
3159  *	@addr: the start address to write
3160  *	@n: length of data to write in bytes
3161  *	@data: the data to write
3162  *	@byte_oriented: whether to store data as bytes or as words
3163  *
3164  *	Writes up to a page of data (256 bytes) to the serial flash starting
3165  *	at the given address.  All the data must be written to the same page.
3166  *	If @byte_oriented is set the write data is stored as byte stream
3167  *	(i.e. matches what on disk), otherwise in big-endian.
3168  */
3169 int t4_write_flash(struct adapter *adapter, unsigned int addr,
3170 			  unsigned int n, const u8 *data, int byte_oriented)
3171 {
3172 	int ret;
3173 	u32 buf[SF_PAGE_SIZE / 4];
3174 	unsigned int i, c, left, val, offset = addr & 0xff;
3175 
3176 	if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3177 		return -EINVAL;
3178 
3179 	val = swab32(addr) | SF_PROG_PAGE;
3180 
3181 	if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3182 	    (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3183 		goto unlock;
3184 
3185 	for (left = n; left; left -= c) {
3186 		c = min(left, 4U);
3187 		for (val = 0, i = 0; i < c; ++i)
3188 			val = (val << 8) + *data++;
3189 
3190 		if (!byte_oriented)
3191 			val = cpu_to_be32(val);
3192 
3193 		ret = sf1_write(adapter, c, c != left, 1, val);
3194 		if (ret)
3195 			goto unlock;
3196 	}
3197 	ret = flash_wait_op(adapter, 8, 1);
3198 	if (ret)
3199 		goto unlock;
3200 
3201 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3202 
3203 	/* Read the page to verify the write succeeded */
3204 	ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3205 			    byte_oriented);
3206 	if (ret)
3207 		return ret;
3208 
3209 	if (memcmp(data - n, (u8 *)buf + offset, n)) {
3210 		CH_ERR(adapter,
3211 			"failed to correctly write the flash page at %#x\n",
3212 			addr);
3213 		return -EIO;
3214 	}
3215 	return 0;
3216 
3217 unlock:
3218 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3219 	return ret;
3220 }
3221 
3222 /**
3223  *	t4_get_fw_version - read the firmware version
3224  *	@adapter: the adapter
3225  *	@vers: where to place the version
3226  *
3227  *	Reads the FW version from flash.
3228  */
3229 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3230 {
3231 	return t4_read_flash(adapter, FLASH_FW_START +
3232 			     offsetof(struct fw_hdr, fw_ver), 1,
3233 			     vers, 0);
3234 }
3235 
3236 /**
3237  *	t4_get_bs_version - read the firmware bootstrap version
3238  *	@adapter: the adapter
3239  *	@vers: where to place the version
3240  *
3241  *	Reads the FW Bootstrap version from flash.
3242  */
3243 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3244 {
3245 	return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3246 			     offsetof(struct fw_hdr, fw_ver), 1,
3247 			     vers, 0);
3248 }
3249 
3250 /**
3251  *	t4_get_tp_version - read the TP microcode version
3252  *	@adapter: the adapter
3253  *	@vers: where to place the version
3254  *
3255  *	Reads the TP microcode version from flash.
3256  */
3257 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3258 {
3259 	return t4_read_flash(adapter, FLASH_FW_START +
3260 			     offsetof(struct fw_hdr, tp_microcode_ver),
3261 			     1, vers, 0);
3262 }
3263 
3264 /**
3265  *	t4_get_exprom_version - return the Expansion ROM version (if any)
3266  *	@adapter: the adapter
3267  *	@vers: where to place the version
3268  *
3269  *	Reads the Expansion ROM header from FLASH and returns the version
3270  *	number (if present) through the @vers return value pointer.  We return
3271  *	this in the Firmware Version Format since it's convenient.  Return
3272  *	0 on success, -ENOENT if no Expansion ROM is present.
3273  */
3274 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3275 {
3276 	struct exprom_header {
3277 		unsigned char hdr_arr[16];	/* must start with 0x55aa */
3278 		unsigned char hdr_ver[4];	/* Expansion ROM version */
3279 	} *hdr;
3280 	u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3281 					   sizeof(u32))];
3282 	int ret;
3283 
3284 	ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3285 			    ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3286 			    0);
3287 	if (ret)
3288 		return ret;
3289 
3290 	hdr = (struct exprom_header *)exprom_header_buf;
3291 	if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3292 		return -ENOENT;
3293 
3294 	*vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) |
3295 		 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) |
3296 		 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) |
3297 		 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3]));
3298 	return 0;
3299 }
3300 
3301 /**
3302  *	t4_get_scfg_version - return the Serial Configuration version
3303  *	@adapter: the adapter
3304  *	@vers: where to place the version
3305  *
3306  *	Reads the Serial Configuration Version via the Firmware interface
3307  *	(thus this can only be called once we're ready to issue Firmware
3308  *	commands).  The format of the Serial Configuration version is
3309  *	adapter specific.  Returns 0 on success, an error on failure.
3310  *
3311  *	Note that early versions of the Firmware didn't include the ability
3312  *	to retrieve the Serial Configuration version, so we zero-out the
3313  *	return-value parameter in that case to avoid leaving it with
3314  *	garbage in it.
3315  *
3316  *	Also note that the Firmware will return its cached copy of the Serial
3317  *	Initialization Revision ID, not the actual Revision ID as written in
3318  *	the Serial EEPROM.  This is only an issue if a new VPD has been written
3319  *	and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3320  *	it's best to defer calling this routine till after a FW_RESET_CMD has
3321  *	been issued if the Host Driver will be performing a full adapter
3322  *	initialization.
3323  */
3324 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3325 {
3326 	u32 scfgrev_param;
3327 	int ret;
3328 
3329 	scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3330 			 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV));
3331 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3332 			      1, &scfgrev_param, vers);
3333 	if (ret)
3334 		*vers = 0;
3335 	return ret;
3336 }
3337 
3338 /**
3339  *	t4_get_vpd_version - return the VPD version
3340  *	@adapter: the adapter
3341  *	@vers: where to place the version
3342  *
3343  *	Reads the VPD via the Firmware interface (thus this can only be called
3344  *	once we're ready to issue Firmware commands).  The format of the
3345  *	VPD version is adapter specific.  Returns 0 on success, an error on
3346  *	failure.
3347  *
3348  *	Note that early versions of the Firmware didn't include the ability
3349  *	to retrieve the VPD version, so we zero-out the return-value parameter
3350  *	in that case to avoid leaving it with garbage in it.
3351  *
3352  *	Also note that the Firmware will return its cached copy of the VPD
3353  *	Revision ID, not the actual Revision ID as written in the Serial
3354  *	EEPROM.  This is only an issue if a new VPD has been written and the
3355  *	Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3356  *	to defer calling this routine till after a FW_RESET_CMD has been issued
3357  *	if the Host Driver will be performing a full adapter initialization.
3358  */
3359 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3360 {
3361 	u32 vpdrev_param;
3362 	int ret;
3363 
3364 	vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3365 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV));
3366 	ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3367 			      1, &vpdrev_param, vers);
3368 	if (ret)
3369 		*vers = 0;
3370 	return ret;
3371 }
3372 
3373 /**
3374  *	t4_get_version_info - extract various chip/firmware version information
3375  *	@adapter: the adapter
3376  *
3377  *	Reads various chip/firmware version numbers and stores them into the
3378  *	adapter Adapter Parameters structure.  If any of the efforts fails
3379  *	the first failure will be returned, but all of the version numbers
3380  *	will be read.
3381  */
3382 int t4_get_version_info(struct adapter *adapter)
3383 {
3384 	int ret = 0;
3385 
3386 	#define FIRST_RET(__getvinfo) \
3387 	do { \
3388 		int __ret = __getvinfo; \
3389 		if (__ret && !ret) \
3390 			ret = __ret; \
3391 	} while (0)
3392 
3393 	FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3394 	FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3395 	FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3396 	FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3397 	FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3398 	FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3399 
3400 	#undef FIRST_RET
3401 
3402 	return ret;
3403 }
3404 
3405 /**
3406  *	t4_flash_erase_sectors - erase a range of flash sectors
3407  *	@adapter: the adapter
3408  *	@start: the first sector to erase
3409  *	@end: the last sector to erase
3410  *
3411  *	Erases the sectors in the given inclusive range.
3412  */
3413 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3414 {
3415 	int ret = 0;
3416 
3417 	if (end >= adapter->params.sf_nsec)
3418 		return -EINVAL;
3419 
3420 	while (start <= end) {
3421 		if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3422 		    (ret = sf1_write(adapter, 4, 0, 1,
3423 				     SF_ERASE_SECTOR | (start << 8))) != 0 ||
3424 		    (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3425 			CH_ERR(adapter,
3426 				"erase of flash sector %d failed, error %d\n",
3427 				start, ret);
3428 			break;
3429 		}
3430 		start++;
3431 	}
3432 	t4_write_reg(adapter, A_SF_OP, 0);    /* unlock SF */
3433 	return ret;
3434 }
3435 
3436 /**
3437  *	t4_flash_cfg_addr - return the address of the flash configuration file
3438  *	@adapter: the adapter
3439  *
3440  *	Return the address within the flash where the Firmware Configuration
3441  *	File is stored, or an error if the device FLASH is too small to contain
3442  *	a Firmware Configuration File.
3443  */
3444 int t4_flash_cfg_addr(struct adapter *adapter)
3445 {
3446 	/*
3447 	 * If the device FLASH isn't large enough to hold a Firmware
3448 	 * Configuration File, return an error.
3449 	 */
3450 	if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE)
3451 		return -ENOSPC;
3452 
3453 	return FLASH_CFG_START;
3454 }
3455 
3456 /*
3457  * Return TRUE if the specified firmware matches the adapter.  I.e. T4
3458  * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3459  * and emit an error message for mismatched firmware to save our caller the
3460  * effort ...
3461  */
3462 static int t4_fw_matches_chip(struct adapter *adap,
3463 			      const struct fw_hdr *hdr)
3464 {
3465 	/*
3466 	 * The expression below will return FALSE for any unsupported adapter
3467 	 * which will keep us "honest" in the future ...
3468 	 */
3469 	if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) ||
3470 	    (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) ||
3471 	    (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6))
3472 		return 1;
3473 
3474 	CH_ERR(adap,
3475 		"FW image (%d) is not suitable for this adapter (%d)\n",
3476 		hdr->chip, chip_id(adap));
3477 	return 0;
3478 }
3479 
3480 /**
3481  *	t4_load_fw - download firmware
3482  *	@adap: the adapter
3483  *	@fw_data: the firmware image to write
3484  *	@size: image size
3485  *
3486  *	Write the supplied firmware image to the card's serial flash.
3487  */
3488 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3489 {
3490 	u32 csum;
3491 	int ret, addr;
3492 	unsigned int i;
3493 	u8 first_page[SF_PAGE_SIZE];
3494 	const u32 *p = (const u32 *)fw_data;
3495 	const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3496 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3497 	unsigned int fw_start_sec;
3498 	unsigned int fw_start;
3499 	unsigned int fw_size;
3500 
3501 	if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) {
3502 		fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC;
3503 		fw_start = FLASH_FWBOOTSTRAP_START;
3504 		fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE;
3505 	} else {
3506 		fw_start_sec = FLASH_FW_START_SEC;
3507  		fw_start = FLASH_FW_START;
3508 		fw_size = FLASH_FW_MAX_SIZE;
3509 	}
3510 
3511 	if (!size) {
3512 		CH_ERR(adap, "FW image has no data\n");
3513 		return -EINVAL;
3514 	}
3515 	if (size & 511) {
3516 		CH_ERR(adap,
3517 			"FW image size not multiple of 512 bytes\n");
3518 		return -EINVAL;
3519 	}
3520 	if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) {
3521 		CH_ERR(adap,
3522 			"FW image size differs from size in FW header\n");
3523 		return -EINVAL;
3524 	}
3525 	if (size > fw_size) {
3526 		CH_ERR(adap, "FW image too large, max is %u bytes\n",
3527 			fw_size);
3528 		return -EFBIG;
3529 	}
3530 	if (!t4_fw_matches_chip(adap, hdr))
3531 		return -EINVAL;
3532 
3533 	for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3534 		csum += be32_to_cpu(p[i]);
3535 
3536 	if (csum != 0xffffffff) {
3537 		CH_ERR(adap,
3538 			"corrupted firmware image, checksum %#x\n", csum);
3539 		return -EINVAL;
3540 	}
3541 
3542 	i = DIV_ROUND_UP(size, sf_sec_size);	/* # of sectors spanned */
3543 	ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3544 	if (ret)
3545 		goto out;
3546 
3547 	/*
3548 	 * We write the correct version at the end so the driver can see a bad
3549 	 * version if the FW write fails.  Start by writing a copy of the
3550 	 * first page with a bad version.
3551 	 */
3552 	memcpy(first_page, fw_data, SF_PAGE_SIZE);
3553 	((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3554 	ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1);
3555 	if (ret)
3556 		goto out;
3557 
3558 	addr = fw_start;
3559 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3560 		addr += SF_PAGE_SIZE;
3561 		fw_data += SF_PAGE_SIZE;
3562 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1);
3563 		if (ret)
3564 			goto out;
3565 	}
3566 
3567 	ret = t4_write_flash(adap,
3568 			     fw_start + offsetof(struct fw_hdr, fw_ver),
3569 			     sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1);
3570 out:
3571 	if (ret)
3572 		CH_ERR(adap, "firmware download failed, error %d\n",
3573 			ret);
3574 	return ret;
3575 }
3576 
3577 /**
3578  *	t4_fwcache - firmware cache operation
3579  *	@adap: the adapter
3580  *	@op  : the operation (flush or flush and invalidate)
3581  */
3582 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3583 {
3584 	struct fw_params_cmd c;
3585 
3586 	memset(&c, 0, sizeof(c));
3587 	c.op_to_vfn =
3588 	    cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
3589 			    F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
3590 				V_FW_PARAMS_CMD_PFN(adap->pf) |
3591 				V_FW_PARAMS_CMD_VFN(0));
3592 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3593 	c.param[0].mnem =
3594 	    cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
3595 			    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE));
3596 	c.param[0].val = (__force __be32)op;
3597 
3598 	return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3599 }
3600 
3601 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3602 			unsigned int *pif_req_wrptr,
3603 			unsigned int *pif_rsp_wrptr)
3604 {
3605 	int i, j;
3606 	u32 cfg, val, req, rsp;
3607 
3608 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3609 	if (cfg & F_LADBGEN)
3610 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3611 
3612 	val = t4_read_reg(adap, A_CIM_DEBUGSTS);
3613 	req = G_POLADBGWRPTR(val);
3614 	rsp = G_PILADBGWRPTR(val);
3615 	if (pif_req_wrptr)
3616 		*pif_req_wrptr = req;
3617 	if (pif_rsp_wrptr)
3618 		*pif_rsp_wrptr = rsp;
3619 
3620 	for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3621 		for (j = 0; j < 6; j++) {
3622 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) |
3623 				     V_PILADBGRDPTR(rsp));
3624 			*pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA);
3625 			*pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA);
3626 			req++;
3627 			rsp++;
3628 		}
3629 		req = (req + 2) & M_POLADBGRDPTR;
3630 		rsp = (rsp + 2) & M_PILADBGRDPTR;
3631 	}
3632 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3633 }
3634 
3635 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3636 {
3637 	u32 cfg;
3638 	int i, j, idx;
3639 
3640 	cfg = t4_read_reg(adap, A_CIM_DEBUGCFG);
3641 	if (cfg & F_LADBGEN)
3642 		t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN);
3643 
3644 	for (i = 0; i < CIM_MALA_SIZE; i++) {
3645 		for (j = 0; j < 5; j++) {
3646 			idx = 8 * i + j;
3647 			t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) |
3648 				     V_PILADBGRDPTR(idx));
3649 			*ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA);
3650 			*ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA);
3651 		}
3652 	}
3653 	t4_write_reg(adap, A_CIM_DEBUGCFG, cfg);
3654 }
3655 
3656 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3657 {
3658 	unsigned int i, j;
3659 
3660 	for (i = 0; i < 8; i++) {
3661 		u32 *p = la_buf + i;
3662 
3663 		t4_write_reg(adap, A_ULP_RX_LA_CTL, i);
3664 		j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR);
3665 		t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j);
3666 		for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3667 			*p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA);
3668 	}
3669 }
3670 
3671 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3672 		     FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_25G | \
3673 		     FW_PORT_CAP_SPEED_40G | FW_PORT_CAP_SPEED_100G | \
3674 		     FW_PORT_CAP_ANEG)
3675 
3676 /**
3677  *	t4_link_l1cfg - apply link configuration to MAC/PHY
3678  *	@phy: the PHY to setup
3679  *	@mac: the MAC to setup
3680  *	@lc: the requested link configuration
3681  *
3682  *	Set up a port's MAC and PHY according to a desired link configuration.
3683  *	- If the PHY can auto-negotiate first decide what to advertise, then
3684  *	  enable/disable auto-negotiation as desired, and reset.
3685  *	- If the PHY does not auto-negotiate just reset it.
3686  *	- If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3687  *	  otherwise do it later based on the outcome of auto-negotiation.
3688  */
3689 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3690 		  struct link_config *lc)
3691 {
3692 	struct fw_port_cmd c;
3693 	unsigned int fc = 0, mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO);
3694 
3695 	lc->link_ok = 0;
3696 	if (lc->requested_fc & PAUSE_RX)
3697 		fc |= FW_PORT_CAP_FC_RX;
3698 	if (lc->requested_fc & PAUSE_TX)
3699 		fc |= FW_PORT_CAP_FC_TX;
3700 
3701 	memset(&c, 0, sizeof(c));
3702 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3703 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3704 				     V_FW_PORT_CMD_PORTID(port));
3705 	c.action_to_len16 =
3706 		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3707 			    FW_LEN16(c));
3708 
3709 	if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3710 		c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3711 					     fc);
3712 		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3713 	} else if (lc->autoneg == AUTONEG_DISABLE) {
3714 		c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3715 		lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3716 	} else
3717 		c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3718 
3719 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3720 }
3721 
3722 /**
3723  *	t4_restart_aneg - restart autonegotiation
3724  *	@adap: the adapter
3725  *	@mbox: mbox to use for the FW command
3726  *	@port: the port id
3727  *
3728  *	Restarts autonegotiation for the selected port.
3729  */
3730 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3731 {
3732 	struct fw_port_cmd c;
3733 
3734 	memset(&c, 0, sizeof(c));
3735 	c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) |
3736 				     F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
3737 				     V_FW_PORT_CMD_PORTID(port));
3738 	c.action_to_len16 =
3739 		cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
3740 			    FW_LEN16(c));
3741 	c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3742 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3743 }
3744 
3745 typedef void (*int_handler_t)(struct adapter *adap);
3746 
3747 struct intr_info {
3748 	unsigned int mask;	/* bits to check in interrupt status */
3749 	const char *msg;	/* message to print or NULL */
3750 	short stat_idx;		/* stat counter to increment or -1 */
3751 	unsigned short fatal;	/* whether the condition reported is fatal */
3752 	int_handler_t int_handler;	/* platform-specific int handler */
3753 };
3754 
3755 /**
3756  *	t4_handle_intr_status - table driven interrupt handler
3757  *	@adapter: the adapter that generated the interrupt
3758  *	@reg: the interrupt status register to process
3759  *	@acts: table of interrupt actions
3760  *
3761  *	A table driven interrupt handler that applies a set of masks to an
3762  *	interrupt status word and performs the corresponding actions if the
3763  *	interrupts described by the mask have occurred.  The actions include
3764  *	optionally emitting a warning or alert message.  The table is terminated
3765  *	by an entry specifying mask 0.  Returns the number of fatal interrupt
3766  *	conditions.
3767  */
3768 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3769 				 const struct intr_info *acts)
3770 {
3771 	int fatal = 0;
3772 	unsigned int mask = 0;
3773 	unsigned int status = t4_read_reg(adapter, reg);
3774 
3775 	for ( ; acts->mask; ++acts) {
3776 		if (!(status & acts->mask))
3777 			continue;
3778 		if (acts->fatal) {
3779 			fatal++;
3780 			CH_ALERT(adapter, "%s (0x%x)\n", acts->msg,
3781 				  status & acts->mask);
3782 		} else if (acts->msg)
3783 			CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg,
3784 				 status & acts->mask);
3785 		if (acts->int_handler)
3786 			acts->int_handler(adapter);
3787 		mask |= acts->mask;
3788 	}
3789 	status &= mask;
3790 	if (status)	/* clear processed interrupts */
3791 		t4_write_reg(adapter, reg, status);
3792 	return fatal;
3793 }
3794 
3795 /*
3796  * Interrupt handler for the PCIE module.
3797  */
3798 static void pcie_intr_handler(struct adapter *adapter)
3799 {
3800 	static const struct intr_info sysbus_intr_info[] = {
3801 		{ F_RNPP, "RXNP array parity error", -1, 1 },
3802 		{ F_RPCP, "RXPC array parity error", -1, 1 },
3803 		{ F_RCIP, "RXCIF array parity error", -1, 1 },
3804 		{ F_RCCP, "Rx completions control array parity error", -1, 1 },
3805 		{ F_RFTP, "RXFT array parity error", -1, 1 },
3806 		{ 0 }
3807 	};
3808 	static const struct intr_info pcie_port_intr_info[] = {
3809 		{ F_TPCP, "TXPC array parity error", -1, 1 },
3810 		{ F_TNPP, "TXNP array parity error", -1, 1 },
3811 		{ F_TFTP, "TXFT array parity error", -1, 1 },
3812 		{ F_TCAP, "TXCA array parity error", -1, 1 },
3813 		{ F_TCIP, "TXCIF array parity error", -1, 1 },
3814 		{ F_RCAP, "RXCA array parity error", -1, 1 },
3815 		{ F_OTDD, "outbound request TLP discarded", -1, 1 },
3816 		{ F_RDPE, "Rx data parity error", -1, 1 },
3817 		{ F_TDUE, "Tx uncorrectable data error", -1, 1 },
3818 		{ 0 }
3819 	};
3820 	static const struct intr_info pcie_intr_info[] = {
3821 		{ F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
3822 		{ F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
3823 		{ F_MSIDATAPERR, "MSI data parity error", -1, 1 },
3824 		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3825 		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3826 		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3827 		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3828 		{ F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
3829 		{ F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
3830 		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3831 		{ F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
3832 		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3833 		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3834 		{ F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
3835 		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3836 		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3837 		{ F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
3838 		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3839 		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3840 		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3841 		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
3842 		{ F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
3843 		{ F_MATAGPERR, "PCI MA tag parity error", -1, 1 },
3844 		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3845 		{ F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
3846 		{ F_RXWRPERR, "PCI Rx write parity error", -1, 1 },
3847 		{ F_RPLPERR, "PCI replay buffer parity error", -1, 1 },
3848 		{ F_PCIESINT, "PCI core secondary fault", -1, 1 },
3849 		{ F_PCIEPINT, "PCI core primary fault", -1, 1 },
3850 		{ F_UNXSPLCPLERR, "PCI unexpected split completion error", -1,
3851 		  0 },
3852 		{ 0 }
3853 	};
3854 
3855 	static const struct intr_info t5_pcie_intr_info[] = {
3856 		{ F_MSTGRPPERR, "Master Response Read Queue parity error",
3857 		  -1, 1 },
3858 		{ F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
3859 		{ F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
3860 		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
3861 		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
3862 		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
3863 		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
3864 		{ F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
3865 		  -1, 1 },
3866 		{ F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
3867 		  -1, 1 },
3868 		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
3869 		{ F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
3870 		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
3871 		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
3872 		{ F_DREQWRPERR, "PCI DMA channel write request parity error",
3873 		  -1, 1 },
3874 		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
3875 		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
3876 		{ F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
3877 		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
3878 		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
3879 		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
3880 		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
3881 		{ F_VFIDPERR, "PCI INTx clear parity error", -1, 1 },
3882 		{ F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
3883 		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
3884 		{ F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
3885 		  -1, 1 },
3886 		{ F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
3887 		  -1, 1 },
3888 		{ F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
3889 		{ F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
3890 		{ F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3891 		{ F_READRSPERR, "Outbound read error", -1,
3892 		  0 },
3893 		{ 0 }
3894 	};
3895 
3896 	int fat;
3897 
3898 	if (is_t4(adapter))
3899 		fat = t4_handle_intr_status(adapter,
3900 				A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
3901 				sysbus_intr_info) +
3902 			t4_handle_intr_status(adapter,
3903 					A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
3904 					pcie_port_intr_info) +
3905 			t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3906 					      pcie_intr_info);
3907 	else
3908 		fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
3909 					    t5_pcie_intr_info);
3910 	if (fat)
3911 		t4_fatal_err(adapter);
3912 }
3913 
3914 /*
3915  * TP interrupt handler.
3916  */
3917 static void tp_intr_handler(struct adapter *adapter)
3918 {
3919 	static const struct intr_info tp_intr_info[] = {
3920 		{ 0x3fffffff, "TP parity error", -1, 1 },
3921 		{ F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
3922 		{ 0 }
3923 	};
3924 
3925 	if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info))
3926 		t4_fatal_err(adapter);
3927 }
3928 
3929 /*
3930  * SGE interrupt handler.
3931  */
3932 static void sge_intr_handler(struct adapter *adapter)
3933 {
3934 	u64 v;
3935 	u32 err;
3936 
3937 	static const struct intr_info sge_intr_info[] = {
3938 		{ F_ERR_CPL_EXCEED_IQE_SIZE,
3939 		  "SGE received CPL exceeding IQE size", -1, 1 },
3940 		{ F_ERR_INVALID_CIDX_INC,
3941 		  "SGE GTS CIDX increment too large", -1, 0 },
3942 		{ F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
3943 		{ F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
3944 		{ F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0,
3945 		  "SGE IQID > 1023 received CPL for FL", -1, 0 },
3946 		{ F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
3947 		  0 },
3948 		{ F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
3949 		  0 },
3950 		{ F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
3951 		  0 },
3952 		{ F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
3953 		  0 },
3954 		{ F_ERR_ING_CTXT_PRIO,
3955 		  "SGE too many priority ingress contexts", -1, 0 },
3956 		{ F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
3957 		{ F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
3958 		{ 0 }
3959 	};
3960 
3961 	static const struct intr_info t4t5_sge_intr_info[] = {
3962 		{ F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
3963 		{ F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
3964 		{ F_ERR_EGR_CTXT_PRIO,
3965 		  "SGE too many priority egress contexts", -1, 0 },
3966 		{ 0 }
3967 	};
3968 
3969 	/*
3970  	* For now, treat below interrupts as fatal so that we disable SGE and
3971  	* get better debug */
3972 	static const struct intr_info t6_sge_intr_info[] = {
3973 		{ F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1,
3974 		  "SGE PCIe error for a DBP thread", -1, 1 },
3975 		{ F_FATAL_WRE_LEN,
3976 		  "SGE Actual WRE packet is less than advertized length",
3977 		  -1, 1 },
3978 		{ 0 }
3979 	};
3980 
3981 	v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) |
3982 		((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32);
3983 	if (v) {
3984 		CH_ALERT(adapter, "SGE parity error (%#llx)\n",
3985 				(unsigned long long)v);
3986 		t4_write_reg(adapter, A_SGE_INT_CAUSE1, v);
3987 		t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32);
3988 	}
3989 
3990 	v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info);
3991 	if (chip_id(adapter) <= CHELSIO_T5)
3992 		v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
3993 					   t4t5_sge_intr_info);
3994 	else
3995 		v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3,
3996 					   t6_sge_intr_info);
3997 
3998 	err = t4_read_reg(adapter, A_SGE_ERROR_STATS);
3999 	if (err & F_ERROR_QID_VALID) {
4000 		CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err));
4001 		if (err & F_UNCAPTURED_ERROR)
4002 			CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n");
4003 		t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID |
4004 			     F_UNCAPTURED_ERROR);
4005 	}
4006 
4007 	if (v != 0)
4008 		t4_fatal_err(adapter);
4009 }
4010 
4011 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\
4012 		      F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR)
4013 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\
4014 		      F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR)
4015 
4016 /*
4017  * CIM interrupt handler.
4018  */
4019 static void cim_intr_handler(struct adapter *adapter)
4020 {
4021 	static const struct intr_info cim_intr_info[] = {
4022 		{ F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
4023 		{ CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4024 		{ CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4025 		{ F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
4026 		{ F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
4027 		{ F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
4028 		{ F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
4029 		{ 0 }
4030 	};
4031 	static const struct intr_info cim_upintr_info[] = {
4032 		{ F_RSVDSPACEINT, "CIM reserved space access", -1, 1 },
4033 		{ F_ILLTRANSINT, "CIM illegal transaction", -1, 1 },
4034 		{ F_ILLWRINT, "CIM illegal write", -1, 1 },
4035 		{ F_ILLRDINT, "CIM illegal read", -1, 1 },
4036 		{ F_ILLRDBEINT, "CIM illegal read BE", -1, 1 },
4037 		{ F_ILLWRBEINT, "CIM illegal write BE", -1, 1 },
4038 		{ F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
4039 		{ F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
4040 		{ F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
4041 		{ F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
4042 		{ F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
4043 		{ F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
4044 		{ F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
4045 		{ F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
4046 		{ F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
4047 		{ F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
4048 		{ F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
4049 		{ F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
4050 		{ F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
4051 		{ F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
4052 		{ F_SGLRDPLINT , "CIM single read from PL space", -1, 1 },
4053 		{ F_SGLWRPLINT , "CIM single write to PL space", -1, 1 },
4054 		{ F_BLKRDPLINT , "CIM block read from PL space", -1, 1 },
4055 		{ F_BLKWRPLINT , "CIM block write to PL space", -1, 1 },
4056 		{ F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
4057 		{ F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
4058 		{ F_TIMEOUTINT , "CIM PIF timeout", -1, 1 },
4059 		{ F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
4060 		{ 0 }
4061 	};
4062 	int fat;
4063 
4064 	if (t4_read_reg(adapter, A_PCIE_FW) & F_PCIE_FW_ERR)
4065 		t4_report_fw_error(adapter);
4066 
4067 	fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE,
4068 				    cim_intr_info) +
4069 	      t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE,
4070 				    cim_upintr_info);
4071 	if (fat)
4072 		t4_fatal_err(adapter);
4073 }
4074 
4075 /*
4076  * ULP RX interrupt handler.
4077  */
4078 static void ulprx_intr_handler(struct adapter *adapter)
4079 {
4080 	static const struct intr_info ulprx_intr_info[] = {
4081 		{ F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 },
4082 		{ F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 },
4083 		{ 0x7fffff, "ULPRX parity error", -1, 1 },
4084 		{ 0 }
4085 	};
4086 
4087 	if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info))
4088 		t4_fatal_err(adapter);
4089 }
4090 
4091 /*
4092  * ULP TX interrupt handler.
4093  */
4094 static void ulptx_intr_handler(struct adapter *adapter)
4095 {
4096 	static const struct intr_info ulptx_intr_info[] = {
4097 		{ F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
4098 		  0 },
4099 		{ F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
4100 		  0 },
4101 		{ F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
4102 		  0 },
4103 		{ F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
4104 		  0 },
4105 		{ 0xfffffff, "ULPTX parity error", -1, 1 },
4106 		{ 0 }
4107 	};
4108 
4109 	if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info))
4110 		t4_fatal_err(adapter);
4111 }
4112 
4113 /*
4114  * PM TX interrupt handler.
4115  */
4116 static void pmtx_intr_handler(struct adapter *adapter)
4117 {
4118 	static const struct intr_info pmtx_intr_info[] = {
4119 		{ F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
4120 		{ F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
4121 		{ F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
4122 		{ F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
4123 		{ 0xffffff0, "PMTX framing error", -1, 1 },
4124 		{ F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
4125 		{ F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1,
4126 		  1 },
4127 		{ F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
4128 		{ F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
4129 		{ 0 }
4130 	};
4131 
4132 	if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info))
4133 		t4_fatal_err(adapter);
4134 }
4135 
4136 /*
4137  * PM RX interrupt handler.
4138  */
4139 static void pmrx_intr_handler(struct adapter *adapter)
4140 {
4141 	static const struct intr_info pmrx_intr_info[] = {
4142 		{ F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
4143 		{ 0x3ffff0, "PMRX framing error", -1, 1 },
4144 		{ F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
4145 		{ F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1,
4146 		  1 },
4147 		{ F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
4148 		{ F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
4149 		{ 0 }
4150 	};
4151 
4152 	if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info))
4153 		t4_fatal_err(adapter);
4154 }
4155 
4156 /*
4157  * CPL switch interrupt handler.
4158  */
4159 static void cplsw_intr_handler(struct adapter *adapter)
4160 {
4161 	static const struct intr_info cplsw_intr_info[] = {
4162 		{ F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
4163 		{ F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
4164 		{ F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
4165 		{ F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
4166 		{ F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
4167 		{ F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
4168 		{ 0 }
4169 	};
4170 
4171 	if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info))
4172 		t4_fatal_err(adapter);
4173 }
4174 
4175 /*
4176  * LE interrupt handler.
4177  */
4178 static void le_intr_handler(struct adapter *adap)
4179 {
4180 	unsigned int chip_ver = chip_id(adap);
4181 	static const struct intr_info le_intr_info[] = {
4182 		{ F_LIPMISS, "LE LIP miss", -1, 0 },
4183 		{ F_LIP0, "LE 0 LIP error", -1, 0 },
4184 		{ F_PARITYERR, "LE parity error", -1, 1 },
4185 		{ F_UNKNOWNCMD, "LE unknown command", -1, 1 },
4186 		{ F_REQQPARERR, "LE request queue parity error", -1, 1 },
4187 		{ 0 }
4188 	};
4189 
4190 	static const struct intr_info t6_le_intr_info[] = {
4191 		{ F_T6_LIPMISS, "LE LIP miss", -1, 0 },
4192 		{ F_T6_LIP0, "LE 0 LIP error", -1, 0 },
4193 		{ F_TCAMINTPERR, "LE parity error", -1, 1 },
4194 		{ F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 },
4195 		{ F_SSRAMINTPERR, "LE request queue parity error", -1, 1 },
4196 		{ 0 }
4197 	};
4198 
4199 	if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE,
4200 				  (chip_ver <= CHELSIO_T5) ?
4201 				  le_intr_info : t6_le_intr_info))
4202 		t4_fatal_err(adap);
4203 }
4204 
4205 /*
4206  * MPS interrupt handler.
4207  */
4208 static void mps_intr_handler(struct adapter *adapter)
4209 {
4210 	static const struct intr_info mps_rx_intr_info[] = {
4211 		{ 0xffffff, "MPS Rx parity error", -1, 1 },
4212 		{ 0 }
4213 	};
4214 	static const struct intr_info mps_tx_intr_info[] = {
4215 		{ V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 },
4216 		{ F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4217 		{ V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error",
4218 		  -1, 1 },
4219 		{ V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error",
4220 		  -1, 1 },
4221 		{ F_BUBBLE, "MPS Tx underflow", -1, 1 },
4222 		{ F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
4223 		{ F_FRMERR, "MPS Tx framing error", -1, 1 },
4224 		{ 0 }
4225 	};
4226 	static const struct intr_info mps_trc_intr_info[] = {
4227 		{ V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 },
4228 		{ V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1,
4229 		  1 },
4230 		{ F_MISCPERR, "MPS TRC misc parity error", -1, 1 },
4231 		{ 0 }
4232 	};
4233 	static const struct intr_info mps_stat_sram_intr_info[] = {
4234 		{ 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4235 		{ 0 }
4236 	};
4237 	static const struct intr_info mps_stat_tx_intr_info[] = {
4238 		{ 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4239 		{ 0 }
4240 	};
4241 	static const struct intr_info mps_stat_rx_intr_info[] = {
4242 		{ 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4243 		{ 0 }
4244 	};
4245 	static const struct intr_info mps_cls_intr_info[] = {
4246 		{ F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
4247 		{ F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
4248 		{ F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
4249 		{ 0 }
4250 	};
4251 
4252 	int fat;
4253 
4254 	fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE,
4255 				    mps_rx_intr_info) +
4256 	      t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE,
4257 				    mps_tx_intr_info) +
4258 	      t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE,
4259 				    mps_trc_intr_info) +
4260 	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM,
4261 				    mps_stat_sram_intr_info) +
4262 	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
4263 				    mps_stat_tx_intr_info) +
4264 	      t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
4265 				    mps_stat_rx_intr_info) +
4266 	      t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE,
4267 				    mps_cls_intr_info);
4268 
4269 	t4_write_reg(adapter, A_MPS_INT_CAUSE, 0);
4270 	t4_read_reg(adapter, A_MPS_INT_CAUSE);	/* flush */
4271 	if (fat)
4272 		t4_fatal_err(adapter);
4273 }
4274 
4275 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \
4276 		      F_ECC_UE_INT_CAUSE)
4277 
4278 /*
4279  * EDC/MC interrupt handler.
4280  */
4281 static void mem_intr_handler(struct adapter *adapter, int idx)
4282 {
4283 	static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4284 
4285 	unsigned int addr, cnt_addr, v;
4286 
4287 	if (idx <= MEM_EDC1) {
4288 		addr = EDC_REG(A_EDC_INT_CAUSE, idx);
4289 		cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx);
4290 	} else if (idx == MEM_MC) {
4291 		if (is_t4(adapter)) {
4292 			addr = A_MC_INT_CAUSE;
4293 			cnt_addr = A_MC_ECC_STATUS;
4294 		} else {
4295 			addr = A_MC_P_INT_CAUSE;
4296 			cnt_addr = A_MC_P_ECC_STATUS;
4297 		}
4298 	} else {
4299 		addr = MC_REG(A_MC_P_INT_CAUSE, 1);
4300 		cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1);
4301 	}
4302 
4303 	v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4304 	if (v & F_PERR_INT_CAUSE)
4305 		CH_ALERT(adapter, "%s FIFO parity error\n",
4306 			  name[idx]);
4307 	if (v & F_ECC_CE_INT_CAUSE) {
4308 		u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr));
4309 
4310 		t4_edc_err_read(adapter, idx);
4311 
4312 		t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT));
4313 		CH_WARN_RATELIMIT(adapter,
4314 				  "%u %s correctable ECC data error%s\n",
4315 				  cnt, name[idx], cnt > 1 ? "s" : "");
4316 	}
4317 	if (v & F_ECC_UE_INT_CAUSE)
4318 		CH_ALERT(adapter,
4319 			 "%s uncorrectable ECC data error\n", name[idx]);
4320 
4321 	t4_write_reg(adapter, addr, v);
4322 	if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE))
4323 		t4_fatal_err(adapter);
4324 }
4325 
4326 /*
4327  * MA interrupt handler.
4328  */
4329 static void ma_intr_handler(struct adapter *adapter)
4330 {
4331 	u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE);
4332 
4333 	if (status & F_MEM_PERR_INT_CAUSE) {
4334 		CH_ALERT(adapter,
4335 			  "MA parity error, parity status %#x\n",
4336 			  t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1));
4337 		if (is_t5(adapter))
4338 			CH_ALERT(adapter,
4339 				  "MA parity error, parity status %#x\n",
4340 				  t4_read_reg(adapter,
4341 					      A_MA_PARITY_ERROR_STATUS2));
4342 	}
4343 	if (status & F_MEM_WRAP_INT_CAUSE) {
4344 		v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS);
4345 		CH_ALERT(adapter, "MA address wrap-around error by "
4346 			  "client %u to address %#x\n",
4347 			  G_MEM_WRAP_CLIENT_NUM(v),
4348 			  G_MEM_WRAP_ADDRESS(v) << 4);
4349 	}
4350 	t4_write_reg(adapter, A_MA_INT_CAUSE, status);
4351 	t4_fatal_err(adapter);
4352 }
4353 
4354 /*
4355  * SMB interrupt handler.
4356  */
4357 static void smb_intr_handler(struct adapter *adap)
4358 {
4359 	static const struct intr_info smb_intr_info[] = {
4360 		{ F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
4361 		{ F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
4362 		{ F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
4363 		{ 0 }
4364 	};
4365 
4366 	if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info))
4367 		t4_fatal_err(adap);
4368 }
4369 
4370 /*
4371  * NC-SI interrupt handler.
4372  */
4373 static void ncsi_intr_handler(struct adapter *adap)
4374 {
4375 	static const struct intr_info ncsi_intr_info[] = {
4376 		{ F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
4377 		{ F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
4378 		{ F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
4379 		{ F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
4380 		{ 0 }
4381 	};
4382 
4383 	if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info))
4384 		t4_fatal_err(adap);
4385 }
4386 
4387 /*
4388  * XGMAC interrupt handler.
4389  */
4390 static void xgmac_intr_handler(struct adapter *adap, int port)
4391 {
4392 	u32 v, int_cause_reg;
4393 
4394 	if (is_t4(adap))
4395 		int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE);
4396 	else
4397 		int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE);
4398 
4399 	v = t4_read_reg(adap, int_cause_reg);
4400 
4401 	v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR);
4402 	if (!v)
4403 		return;
4404 
4405 	if (v & F_TXFIFO_PRTY_ERR)
4406 		CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n",
4407 			  port);
4408 	if (v & F_RXFIFO_PRTY_ERR)
4409 		CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n",
4410 			  port);
4411 	t4_write_reg(adap, int_cause_reg, v);
4412 	t4_fatal_err(adap);
4413 }
4414 
4415 /*
4416  * PL interrupt handler.
4417  */
4418 static void pl_intr_handler(struct adapter *adap)
4419 {
4420 	static const struct intr_info pl_intr_info[] = {
4421 		{ F_FATALPERR, "Fatal parity error", -1, 1 },
4422 		{ F_PERRVFID, "PL VFID_MAP parity error", -1, 1 },
4423 		{ 0 }
4424 	};
4425 
4426 	static const struct intr_info t5_pl_intr_info[] = {
4427 		{ F_FATALPERR, "Fatal parity error", -1, 1 },
4428 		{ 0 }
4429 	};
4430 
4431 	if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE,
4432 				  is_t4(adap) ?
4433 				  pl_intr_info : t5_pl_intr_info))
4434 		t4_fatal_err(adap);
4435 }
4436 
4437 #define PF_INTR_MASK (F_PFSW | F_PFCIM)
4438 
4439 /**
4440  *	t4_slow_intr_handler - control path interrupt handler
4441  *	@adapter: the adapter
4442  *
4443  *	T4 interrupt handler for non-data global interrupt events, e.g., errors.
4444  *	The designation 'slow' is because it involves register reads, while
4445  *	data interrupts typically don't involve any MMIOs.
4446  */
4447 int t4_slow_intr_handler(struct adapter *adapter)
4448 {
4449 	u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
4450 
4451 	if (!(cause & GLBL_INTR_MASK))
4452 		return 0;
4453 	if (cause & F_CIM)
4454 		cim_intr_handler(adapter);
4455 	if (cause & F_MPS)
4456 		mps_intr_handler(adapter);
4457 	if (cause & F_NCSI)
4458 		ncsi_intr_handler(adapter);
4459 	if (cause & F_PL)
4460 		pl_intr_handler(adapter);
4461 	if (cause & F_SMB)
4462 		smb_intr_handler(adapter);
4463 	if (cause & F_MAC0)
4464 		xgmac_intr_handler(adapter, 0);
4465 	if (cause & F_MAC1)
4466 		xgmac_intr_handler(adapter, 1);
4467 	if (cause & F_MAC2)
4468 		xgmac_intr_handler(adapter, 2);
4469 	if (cause & F_MAC3)
4470 		xgmac_intr_handler(adapter, 3);
4471 	if (cause & F_PCIE)
4472 		pcie_intr_handler(adapter);
4473 	if (cause & F_MC0)
4474 		mem_intr_handler(adapter, MEM_MC);
4475 	if (is_t5(adapter) && (cause & F_MC1))
4476 		mem_intr_handler(adapter, MEM_MC1);
4477 	if (cause & F_EDC0)
4478 		mem_intr_handler(adapter, MEM_EDC0);
4479 	if (cause & F_EDC1)
4480 		mem_intr_handler(adapter, MEM_EDC1);
4481 	if (cause & F_LE)
4482 		le_intr_handler(adapter);
4483 	if (cause & F_TP)
4484 		tp_intr_handler(adapter);
4485 	if (cause & F_MA)
4486 		ma_intr_handler(adapter);
4487 	if (cause & F_PM_TX)
4488 		pmtx_intr_handler(adapter);
4489 	if (cause & F_PM_RX)
4490 		pmrx_intr_handler(adapter);
4491 	if (cause & F_ULP_RX)
4492 		ulprx_intr_handler(adapter);
4493 	if (cause & F_CPL_SWITCH)
4494 		cplsw_intr_handler(adapter);
4495 	if (cause & F_SGE)
4496 		sge_intr_handler(adapter);
4497 	if (cause & F_ULP_TX)
4498 		ulptx_intr_handler(adapter);
4499 
4500 	/* Clear the interrupts just processed for which we are the master. */
4501 	t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK);
4502 	(void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */
4503 	return 1;
4504 }
4505 
4506 /**
4507  *	t4_intr_enable - enable interrupts
4508  *	@adapter: the adapter whose interrupts should be enabled
4509  *
4510  *	Enable PF-specific interrupts for the calling function and the top-level
4511  *	interrupt concentrator for global interrupts.  Interrupts are already
4512  *	enabled at each module,	here we just enable the roots of the interrupt
4513  *	hierarchies.
4514  *
4515  *	Note: this function should be called only when the driver manages
4516  *	non PF-specific interrupts from the various HW modules.  Only one PCI
4517  *	function at a time should be doing this.
4518  */
4519 void t4_intr_enable(struct adapter *adapter)
4520 {
4521 	u32 val = 0;
4522 	u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4523 	u32 pf = (chip_id(adapter) <= CHELSIO_T5
4524 		  ? G_SOURCEPF(whoami)
4525 		  : G_T6_SOURCEPF(whoami));
4526 
4527 	if (chip_id(adapter) <= CHELSIO_T5)
4528 		val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT;
4529 	else
4530 		val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN;
4531 	t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE |
4532 		     F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 |
4533 		     F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR |
4534 		     F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 |
4535 		     F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 |
4536 		     F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO |
4537 		     F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val);
4538 	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK);
4539 	t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf);
4540 }
4541 
4542 /**
4543  *	t4_intr_disable - disable interrupts
4544  *	@adapter: the adapter whose interrupts should be disabled
4545  *
4546  *	Disable interrupts.  We only disable the top-level interrupt
4547  *	concentrators.  The caller must be a PCI function managing global
4548  *	interrupts.
4549  */
4550 void t4_intr_disable(struct adapter *adapter)
4551 {
4552 	u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI);
4553 	u32 pf = (chip_id(adapter) <= CHELSIO_T5
4554 		  ? G_SOURCEPF(whoami)
4555 		  : G_T6_SOURCEPF(whoami));
4556 
4557 	t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0);
4558 	t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0);
4559 }
4560 
4561 /**
4562  *	t4_intr_clear - clear all interrupts
4563  *	@adapter: the adapter whose interrupts should be cleared
4564  *
4565  *	Clears all interrupts.  The caller must be a PCI function managing
4566  *	global interrupts.
4567  */
4568 void t4_intr_clear(struct adapter *adapter)
4569 {
4570 	static const unsigned int cause_reg[] = {
4571 		A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3,
4572 		A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE,
4573 		A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE,
4574 		A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1),
4575 		A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE,
4576 		MYPF_REG(A_CIM_PF_HOST_INT_CAUSE),
4577 		A_TP_INT_CAUSE,
4578 		A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE,
4579 		A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE,
4580 		A_MPS_RX_PERR_INT_CAUSE,
4581 		A_CPL_INTR_CAUSE,
4582 		MYPF_REG(A_PL_PF_INT_CAUSE),
4583 		A_PL_PL_INT_CAUSE,
4584 		A_LE_DB_INT_CAUSE,
4585 	};
4586 
4587 	unsigned int i;
4588 
4589 	for (i = 0; i < ARRAY_SIZE(cause_reg); ++i)
4590 		t4_write_reg(adapter, cause_reg[i], 0xffffffff);
4591 
4592 	t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE :
4593 				A_MC_P_INT_CAUSE, 0xffffffff);
4594 
4595 	if (is_t4(adapter)) {
4596 		t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
4597 				0xffffffff);
4598 		t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
4599 				0xffffffff);
4600 	} else
4601 		t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff);
4602 
4603 	t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK);
4604 	(void) t4_read_reg(adapter, A_PL_INT_CAUSE);          /* flush */
4605 }
4606 
4607 /**
4608  *	hash_mac_addr - return the hash value of a MAC address
4609  *	@addr: the 48-bit Ethernet MAC address
4610  *
4611  *	Hashes a MAC address according to the hash function used by HW inexact
4612  *	(hash) address matching.
4613  */
4614 static int hash_mac_addr(const u8 *addr)
4615 {
4616 	u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
4617 	u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
4618 	a ^= b;
4619 	a ^= (a >> 12);
4620 	a ^= (a >> 6);
4621 	return a & 0x3f;
4622 }
4623 
4624 /**
4625  *	t4_config_rss_range - configure a portion of the RSS mapping table
4626  *	@adapter: the adapter
4627  *	@mbox: mbox to use for the FW command
4628  *	@viid: virtual interface whose RSS subtable is to be written
4629  *	@start: start entry in the table to write
4630  *	@n: how many table entries to write
4631  *	@rspq: values for the "response queue" (Ingress Queue) lookup table
4632  *	@nrspq: number of values in @rspq
4633  *
4634  *	Programs the selected part of the VI's RSS mapping table with the
4635  *	provided values.  If @nrspq < @n the supplied values are used repeatedly
4636  *	until the full table range is populated.
4637  *
4638  *	The caller must ensure the values in @rspq are in the range allowed for
4639  *	@viid.
4640  */
4641 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4642 			int start, int n, const u16 *rspq, unsigned int nrspq)
4643 {
4644 	int ret;
4645 	const u16 *rsp = rspq;
4646 	const u16 *rsp_end = rspq + nrspq;
4647 	struct fw_rss_ind_tbl_cmd cmd;
4648 
4649 	memset(&cmd, 0, sizeof(cmd));
4650 	cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
4651 				     F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4652 				     V_FW_RSS_IND_TBL_CMD_VIID(viid));
4653 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4654 
4655 	/*
4656 	 * Each firmware RSS command can accommodate up to 32 RSS Ingress
4657 	 * Queue Identifiers.  These Ingress Queue IDs are packed three to
4658 	 * a 32-bit word as 10-bit values with the upper remaining 2 bits
4659 	 * reserved.
4660 	 */
4661 	while (n > 0) {
4662 		int nq = min(n, 32);
4663 		int nq_packed = 0;
4664 		__be32 *qp = &cmd.iq0_to_iq2;
4665 
4666 		/*
4667 		 * Set up the firmware RSS command header to send the next
4668 		 * "nq" Ingress Queue IDs to the firmware.
4669 		 */
4670 		cmd.niqid = cpu_to_be16(nq);
4671 		cmd.startidx = cpu_to_be16(start);
4672 
4673 		/*
4674 		 * "nq" more done for the start of the next loop.
4675 		 */
4676 		start += nq;
4677 		n -= nq;
4678 
4679 		/*
4680 		 * While there are still Ingress Queue IDs to stuff into the
4681 		 * current firmware RSS command, retrieve them from the
4682 		 * Ingress Queue ID array and insert them into the command.
4683 		 */
4684 		while (nq > 0) {
4685 			/*
4686 			 * Grab up to the next 3 Ingress Queue IDs (wrapping
4687 			 * around the Ingress Queue ID array if necessary) and
4688 			 * insert them into the firmware RSS command at the
4689 			 * current 3-tuple position within the commad.
4690 			 */
4691 			u16 qbuf[3];
4692 			u16 *qbp = qbuf;
4693 			int nqbuf = min(3, nq);
4694 
4695 			nq -= nqbuf;
4696 			qbuf[0] = qbuf[1] = qbuf[2] = 0;
4697 			while (nqbuf && nq_packed < 32) {
4698 				nqbuf--;
4699 				nq_packed++;
4700 				*qbp++ = *rsp++;
4701 				if (rsp >= rsp_end)
4702 					rsp = rspq;
4703 			}
4704 			*qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) |
4705 					    V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) |
4706 					    V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2]));
4707 		}
4708 
4709 		/*
4710 		 * Send this portion of the RRS table update to the firmware;
4711 		 * bail out on any errors.
4712 		 */
4713 		ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4714 		if (ret)
4715 			return ret;
4716 	}
4717 	return 0;
4718 }
4719 
4720 /**
4721  *	t4_config_glbl_rss - configure the global RSS mode
4722  *	@adapter: the adapter
4723  *	@mbox: mbox to use for the FW command
4724  *	@mode: global RSS mode
4725  *	@flags: mode-specific flags
4726  *
4727  *	Sets the global RSS mode.
4728  */
4729 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4730 		       unsigned int flags)
4731 {
4732 	struct fw_rss_glb_config_cmd c;
4733 
4734 	memset(&c, 0, sizeof(c));
4735 	c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
4736 				    F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
4737 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4738 	if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4739 		c.u.manual.mode_pkd =
4740 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4741 	} else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4742 		c.u.basicvirtual.mode_pkd =
4743 			cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode));
4744 		c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4745 	} else
4746 		return -EINVAL;
4747 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4748 }
4749 
4750 /**
4751  *	t4_config_vi_rss - configure per VI RSS settings
4752  *	@adapter: the adapter
4753  *	@mbox: mbox to use for the FW command
4754  *	@viid: the VI id
4755  *	@flags: RSS flags
4756  *	@defq: id of the default RSS queue for the VI.
4757  *
4758  *	Configures VI-specific RSS properties.
4759  */
4760 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4761 		     unsigned int flags, unsigned int defq)
4762 {
4763 	struct fw_rss_vi_config_cmd c;
4764 
4765 	memset(&c, 0, sizeof(c));
4766 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
4767 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
4768 				   V_FW_RSS_VI_CONFIG_CMD_VIID(viid));
4769 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4770 	c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4771 					V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq));
4772 	return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4773 }
4774 
4775 /* Read an RSS table row */
4776 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4777 {
4778 	t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row);
4779 	return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1,
4780 				   5, 0, val);
4781 }
4782 
4783 /**
4784  *	t4_read_rss - read the contents of the RSS mapping table
4785  *	@adapter: the adapter
4786  *	@map: holds the contents of the RSS mapping table
4787  *
4788  *	Reads the contents of the RSS hash->queue mapping table.
4789  */
4790 int t4_read_rss(struct adapter *adapter, u16 *map)
4791 {
4792 	u32 val;
4793 	int i, ret;
4794 
4795 	for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4796 		ret = rd_rss_row(adapter, i, &val);
4797 		if (ret)
4798 			return ret;
4799 		*map++ = G_LKPTBLQUEUE0(val);
4800 		*map++ = G_LKPTBLQUEUE1(val);
4801 	}
4802 	return 0;
4803 }
4804 
4805 /**
4806  *	t4_fw_tp_pio_rw - Access TP PIO through LDST
4807  *	@adap: the adapter
4808  *	@vals: where the indirect register values are stored/written
4809  *	@nregs: how many indirect registers to read/write
4810  *	@start_idx: index of first indirect register to read/write
4811  *	@rw: Read (1) or Write (0)
4812  *
4813  *	Access TP PIO registers through LDST
4814  */
4815 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4816 		     unsigned int start_index, unsigned int rw)
4817 {
4818 	int ret, i;
4819 	int cmd = FW_LDST_ADDRSPC_TP_PIO;
4820 	struct fw_ldst_cmd c;
4821 
4822 	for (i = 0 ; i < nregs; i++) {
4823 		memset(&c, 0, sizeof(c));
4824 		c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
4825 						F_FW_CMD_REQUEST |
4826 						(rw ? F_FW_CMD_READ :
4827 						     F_FW_CMD_WRITE) |
4828 						V_FW_LDST_CMD_ADDRSPACE(cmd));
4829 		c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4830 
4831 		c.u.addrval.addr = cpu_to_be32(start_index + i);
4832 		c.u.addrval.val  = rw ? 0 : cpu_to_be32(vals[i]);
4833 		ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4834 		if (ret == 0) {
4835 			if (rw)
4836 				vals[i] = be32_to_cpu(c.u.addrval.val);
4837 		}
4838 	}
4839 }
4840 
4841 /**
4842  *	t4_read_rss_key - read the global RSS key
4843  *	@adap: the adapter
4844  *	@key: 10-entry array holding the 320-bit RSS key
4845  *
4846  *	Reads the global 320-bit RSS key.
4847  */
4848 void t4_read_rss_key(struct adapter *adap, u32 *key)
4849 {
4850 	if (t4_use_ldst(adap))
4851 		t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 1);
4852 	else
4853 		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4854 				 A_TP_RSS_SECRET_KEY0);
4855 }
4856 
4857 /**
4858  *	t4_write_rss_key - program one of the RSS keys
4859  *	@adap: the adapter
4860  *	@key: 10-entry array holding the 320-bit RSS key
4861  *	@idx: which RSS key to write
4862  *
4863  *	Writes one of the RSS keys with the given 320-bit value.  If @idx is
4864  *	0..15 the corresponding entry in the RSS key table is written,
4865  *	otherwise the global RSS key is written.
4866  */
4867 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx)
4868 {
4869 	u8 rss_key_addr_cnt = 16;
4870 	u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT);
4871 
4872 	/*
4873 	 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4874 	 * allows access to key addresses 16-63 by using KeyWrAddrX
4875 	 * as index[5:4](upper 2) into key table
4876 	 */
4877 	if ((chip_id(adap) > CHELSIO_T5) &&
4878 	    (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3))
4879 		rss_key_addr_cnt = 32;
4880 
4881 	if (t4_use_ldst(adap))
4882 		t4_fw_tp_pio_rw(adap, key, 10, A_TP_RSS_SECRET_KEY0, 0);
4883 	else
4884 		t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, key, 10,
4885 				  A_TP_RSS_SECRET_KEY0);
4886 
4887 	if (idx >= 0 && idx < rss_key_addr_cnt) {
4888 		if (rss_key_addr_cnt > 16)
4889 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4890 				     V_KEYWRADDRX(idx >> 4) |
4891 				     V_T6_VFWRADDR(idx) | F_KEYWREN);
4892 		else
4893 			t4_write_reg(adap, A_TP_RSS_CONFIG_VRT,
4894 				     V_KEYWRADDR(idx) | F_KEYWREN);
4895 	}
4896 }
4897 
4898 /**
4899  *	t4_read_rss_pf_config - read PF RSS Configuration Table
4900  *	@adapter: the adapter
4901  *	@index: the entry in the PF RSS table to read
4902  *	@valp: where to store the returned value
4903  *
4904  *	Reads the PF RSS Configuration Table at the specified index and returns
4905  *	the value found there.
4906  */
4907 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4908 			   u32 *valp)
4909 {
4910 	if (t4_use_ldst(adapter))
4911 		t4_fw_tp_pio_rw(adapter, valp, 1,
4912 				A_TP_RSS_PF0_CONFIG + index, 1);
4913 	else
4914 		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4915 				 valp, 1, A_TP_RSS_PF0_CONFIG + index);
4916 }
4917 
4918 /**
4919  *	t4_write_rss_pf_config - write PF RSS Configuration Table
4920  *	@adapter: the adapter
4921  *	@index: the entry in the VF RSS table to read
4922  *	@val: the value to store
4923  *
4924  *	Writes the PF RSS Configuration Table at the specified index with the
4925  *	specified value.
4926  */
4927 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
4928 			    u32 val)
4929 {
4930 	if (t4_use_ldst(adapter))
4931 		t4_fw_tp_pio_rw(adapter, &val, 1,
4932 				A_TP_RSS_PF0_CONFIG + index, 0);
4933 	else
4934 		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4935 				  &val, 1, A_TP_RSS_PF0_CONFIG + index);
4936 }
4937 
4938 /**
4939  *	t4_read_rss_vf_config - read VF RSS Configuration Table
4940  *	@adapter: the adapter
4941  *	@index: the entry in the VF RSS table to read
4942  *	@vfl: where to store the returned VFL
4943  *	@vfh: where to store the returned VFH
4944  *
4945  *	Reads the VF RSS Configuration Table at the specified index and returns
4946  *	the (VFL, VFH) values found there.
4947  */
4948 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4949 			   u32 *vfl, u32 *vfh)
4950 {
4951 	u32 vrt, mask, data;
4952 
4953 	if (chip_id(adapter) <= CHELSIO_T5) {
4954 		mask = V_VFWRADDR(M_VFWRADDR);
4955 		data = V_VFWRADDR(index);
4956 	} else {
4957 		 mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
4958 		 data = V_T6_VFWRADDR(index);
4959 	}
4960 	/*
4961 	 * Request that the index'th VF Table values be read into VFL/VFH.
4962 	 */
4963 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
4964 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
4965 	vrt |= data | F_VFRDEN;
4966 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
4967 
4968 	/*
4969 	 * Grab the VFL/VFH values ...
4970 	 */
4971 	if (t4_use_ldst(adapter)) {
4972 		t4_fw_tp_pio_rw(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, 1);
4973 		t4_fw_tp_pio_rw(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, 1);
4974 	} else {
4975 		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4976 				 vfl, 1, A_TP_RSS_VFL_CONFIG);
4977 		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
4978 				 vfh, 1, A_TP_RSS_VFH_CONFIG);
4979 	}
4980 }
4981 
4982 /**
4983  *	t4_write_rss_vf_config - write VF RSS Configuration Table
4984  *
4985  *	@adapter: the adapter
4986  *	@index: the entry in the VF RSS table to write
4987  *	@vfl: the VFL to store
4988  *	@vfh: the VFH to store
4989  *
4990  *	Writes the VF RSS Configuration Table at the specified index with the
4991  *	specified (VFL, VFH) values.
4992  */
4993 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
4994 			    u32 vfl, u32 vfh)
4995 {
4996 	u32 vrt, mask, data;
4997 
4998 	if (chip_id(adapter) <= CHELSIO_T5) {
4999 		mask = V_VFWRADDR(M_VFWRADDR);
5000 		data = V_VFWRADDR(index);
5001 	} else {
5002 		mask =  V_T6_VFWRADDR(M_T6_VFWRADDR);
5003 		data = V_T6_VFWRADDR(index);
5004 	}
5005 
5006 	/*
5007 	 * Load up VFL/VFH with the values to be written ...
5008 	 */
5009 	if (t4_use_ldst(adapter)) {
5010 		t4_fw_tp_pio_rw(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, 0);
5011 		t4_fw_tp_pio_rw(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, 0);
5012 	} else {
5013 		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5014 				  &vfl, 1, A_TP_RSS_VFL_CONFIG);
5015 		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5016 				  &vfh, 1, A_TP_RSS_VFH_CONFIG);
5017 	}
5018 
5019 	/*
5020 	 * Write the VFL/VFH into the VF Table at index'th location.
5021 	 */
5022 	vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT);
5023 	vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask);
5024 	vrt |= data | F_VFRDEN;
5025 	t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt);
5026 }
5027 
5028 /**
5029  *	t4_read_rss_pf_map - read PF RSS Map
5030  *	@adapter: the adapter
5031  *
5032  *	Reads the PF RSS Map register and returns its value.
5033  */
5034 u32 t4_read_rss_pf_map(struct adapter *adapter)
5035 {
5036 	u32 pfmap;
5037 
5038 	if (t4_use_ldst(adapter))
5039 		t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 1);
5040 	else
5041 		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5042 				 &pfmap, 1, A_TP_RSS_PF_MAP);
5043 	return pfmap;
5044 }
5045 
5046 /**
5047  *	t4_write_rss_pf_map - write PF RSS Map
5048  *	@adapter: the adapter
5049  *	@pfmap: PF RSS Map value
5050  *
5051  *	Writes the specified value to the PF RSS Map register.
5052  */
5053 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap)
5054 {
5055 	if (t4_use_ldst(adapter))
5056 		t4_fw_tp_pio_rw(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, 0);
5057 	else
5058 		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5059 				  &pfmap, 1, A_TP_RSS_PF_MAP);
5060 }
5061 
5062 /**
5063  *	t4_read_rss_pf_mask - read PF RSS Mask
5064  *	@adapter: the adapter
5065  *
5066  *	Reads the PF RSS Mask register and returns its value.
5067  */
5068 u32 t4_read_rss_pf_mask(struct adapter *adapter)
5069 {
5070 	u32 pfmask;
5071 
5072 	if (t4_use_ldst(adapter))
5073 		t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 1);
5074 	else
5075 		t4_read_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5076 				 &pfmask, 1, A_TP_RSS_PF_MSK);
5077 	return pfmask;
5078 }
5079 
5080 /**
5081  *	t4_write_rss_pf_mask - write PF RSS Mask
5082  *	@adapter: the adapter
5083  *	@pfmask: PF RSS Mask value
5084  *
5085  *	Writes the specified value to the PF RSS Mask register.
5086  */
5087 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask)
5088 {
5089 	if (t4_use_ldst(adapter))
5090 		t4_fw_tp_pio_rw(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, 0);
5091 	else
5092 		t4_write_indirect(adapter, A_TP_PIO_ADDR, A_TP_PIO_DATA,
5093 				  &pfmask, 1, A_TP_RSS_PF_MSK);
5094 }
5095 
5096 /**
5097  *	t4_tp_get_tcp_stats - read TP's TCP MIB counters
5098  *	@adap: the adapter
5099  *	@v4: holds the TCP/IP counter values
5100  *	@v6: holds the TCP/IPv6 counter values
5101  *
5102  *	Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5103  *	Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5104  */
5105 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5106 			 struct tp_tcp_stats *v6)
5107 {
5108 	u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1];
5109 
5110 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST)
5111 #define STAT(x)     val[STAT_IDX(x)]
5112 #define STAT64(x)   (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5113 
5114 	if (v4) {
5115 		t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5116 				 ARRAY_SIZE(val), A_TP_MIB_TCP_OUT_RST);
5117 		v4->tcp_out_rsts = STAT(OUT_RST);
5118 		v4->tcp_in_segs  = STAT64(IN_SEG);
5119 		v4->tcp_out_segs = STAT64(OUT_SEG);
5120 		v4->tcp_retrans_segs = STAT64(RXT_SEG);
5121 	}
5122 	if (v6) {
5123 		t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5124 				 ARRAY_SIZE(val), A_TP_MIB_TCP_V6OUT_RST);
5125 		v6->tcp_out_rsts = STAT(OUT_RST);
5126 		v6->tcp_in_segs  = STAT64(IN_SEG);
5127 		v6->tcp_out_segs = STAT64(OUT_SEG);
5128 		v6->tcp_retrans_segs = STAT64(RXT_SEG);
5129 	}
5130 #undef STAT64
5131 #undef STAT
5132 #undef STAT_IDX
5133 }
5134 
5135 /**
5136  *	t4_tp_get_err_stats - read TP's error MIB counters
5137  *	@adap: the adapter
5138  *	@st: holds the counter values
5139  *
5140  *	Returns the values of TP's error counters.
5141  */
5142 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
5143 {
5144 	int nchan = adap->chip_params->nchan;
5145 
5146 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5147 			st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0);
5148 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5149 			st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0);
5150 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5151 			st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0);
5152 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5153 			st->tnl_cong_drops, nchan, A_TP_MIB_TNL_CNG_DROP_0);
5154 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5155 			st->ofld_chan_drops, nchan, A_TP_MIB_OFD_CHN_DROP_0);
5156 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5157 			st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0);
5158 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5159 			st->ofld_vlan_drops, nchan, A_TP_MIB_OFD_VLN_DROP_0);
5160 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5161 			st->tcp6_in_errs, nchan, A_TP_MIB_TCP_V6IN_ERR_0);
5162 
5163 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA,
5164 			 &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP);
5165 }
5166 
5167 /**
5168  *	t4_tp_get_proxy_stats - read TP's proxy MIB counters
5169  *	@adap: the adapter
5170  *	@st: holds the counter values
5171  *
5172  *	Returns the values of TP's proxy counters.
5173  */
5174 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st)
5175 {
5176 	int nchan = adap->chip_params->nchan;
5177 
5178 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->proxy,
5179 			 nchan, A_TP_MIB_TNL_LPBK_0);
5180 }
5181 
5182 /**
5183  *	t4_tp_get_cpl_stats - read TP's CPL MIB counters
5184  *	@adap: the adapter
5185  *	@st: holds the counter values
5186  *
5187  *	Returns the values of TP's CPL counters.
5188  */
5189 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
5190 {
5191 	int nchan = adap->chip_params->nchan;
5192 
5193 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->req,
5194 			 nchan, A_TP_MIB_CPL_IN_REQ_0);
5195 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, st->rsp,
5196 			 nchan, A_TP_MIB_CPL_OUT_RSP_0);
5197 }
5198 
5199 /**
5200  *	t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5201  *	@adap: the adapter
5202  *	@st: holds the counter values
5203  *
5204  *	Returns the values of TP's RDMA counters.
5205  */
5206 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
5207 {
5208 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->rqe_dfr_pkt,
5209 			 2, A_TP_MIB_RQE_DFR_PKT);
5210 }
5211 
5212 /**
5213  *	t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5214  *	@adap: the adapter
5215  *	@idx: the port index
5216  *	@st: holds the counter values
5217  *
5218  *	Returns the values of TP's FCoE counters for the selected port.
5219  */
5220 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5221 		       struct tp_fcoe_stats *st)
5222 {
5223 	u32 val[2];
5224 
5225 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_ddp,
5226 			 1, A_TP_MIB_FCOE_DDP_0 + idx);
5227 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, &st->frames_drop,
5228 			 1, A_TP_MIB_FCOE_DROP_0 + idx);
5229 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val,
5230 			 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx);
5231 	st->octets_ddp = ((u64)val[0] << 32) | val[1];
5232 }
5233 
5234 /**
5235  *	t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5236  *	@adap: the adapter
5237  *	@st: holds the counter values
5238  *
5239  *	Returns the values of TP's counters for non-TCP directly-placed packets.
5240  */
5241 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
5242 {
5243 	u32 val[4];
5244 
5245 	t4_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, val, 4,
5246 			 A_TP_MIB_USM_PKTS);
5247 	st->frames = val[0];
5248 	st->drops = val[1];
5249 	st->octets = ((u64)val[2] << 32) | val[3];
5250 }
5251 
5252 /**
5253  *	t4_read_mtu_tbl - returns the values in the HW path MTU table
5254  *	@adap: the adapter
5255  *	@mtus: where to store the MTU values
5256  *	@mtu_log: where to store the MTU base-2 log (may be %NULL)
5257  *
5258  *	Reads the HW path MTU table.
5259  */
5260 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5261 {
5262 	u32 v;
5263 	int i;
5264 
5265 	for (i = 0; i < NMTUS; ++i) {
5266 		t4_write_reg(adap, A_TP_MTU_TABLE,
5267 			     V_MTUINDEX(0xff) | V_MTUVALUE(i));
5268 		v = t4_read_reg(adap, A_TP_MTU_TABLE);
5269 		mtus[i] = G_MTUVALUE(v);
5270 		if (mtu_log)
5271 			mtu_log[i] = G_MTUWIDTH(v);
5272 	}
5273 }
5274 
5275 /**
5276  *	t4_read_cong_tbl - reads the congestion control table
5277  *	@adap: the adapter
5278  *	@incr: where to store the alpha values
5279  *
5280  *	Reads the additive increments programmed into the HW congestion
5281  *	control table.
5282  */
5283 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5284 {
5285 	unsigned int mtu, w;
5286 
5287 	for (mtu = 0; mtu < NMTUS; ++mtu)
5288 		for (w = 0; w < NCCTRL_WIN; ++w) {
5289 			t4_write_reg(adap, A_TP_CCTRL_TABLE,
5290 				     V_ROWINDEX(0xffff) | (mtu << 5) | w);
5291 			incr[mtu][w] = (u16)t4_read_reg(adap,
5292 						A_TP_CCTRL_TABLE) & 0x1fff;
5293 		}
5294 }
5295 
5296 /**
5297  *	t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5298  *	@adap: the adapter
5299  *	@addr: the indirect TP register address
5300  *	@mask: specifies the field within the register to modify
5301  *	@val: new value for the field
5302  *
5303  *	Sets a field of an indirect TP register to the given value.
5304  */
5305 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5306 			    unsigned int mask, unsigned int val)
5307 {
5308 	t4_write_reg(adap, A_TP_PIO_ADDR, addr);
5309 	val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask;
5310 	t4_write_reg(adap, A_TP_PIO_DATA, val);
5311 }
5312 
5313 /**
5314  *	init_cong_ctrl - initialize congestion control parameters
5315  *	@a: the alpha values for congestion control
5316  *	@b: the beta values for congestion control
5317  *
5318  *	Initialize the congestion control parameters.
5319  */
5320 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5321 {
5322 	a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5323 	a[9] = 2;
5324 	a[10] = 3;
5325 	a[11] = 4;
5326 	a[12] = 5;
5327 	a[13] = 6;
5328 	a[14] = 7;
5329 	a[15] = 8;
5330 	a[16] = 9;
5331 	a[17] = 10;
5332 	a[18] = 14;
5333 	a[19] = 17;
5334 	a[20] = 21;
5335 	a[21] = 25;
5336 	a[22] = 30;
5337 	a[23] = 35;
5338 	a[24] = 45;
5339 	a[25] = 60;
5340 	a[26] = 80;
5341 	a[27] = 100;
5342 	a[28] = 200;
5343 	a[29] = 300;
5344 	a[30] = 400;
5345 	a[31] = 500;
5346 
5347 	b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5348 	b[9] = b[10] = 1;
5349 	b[11] = b[12] = 2;
5350 	b[13] = b[14] = b[15] = b[16] = 3;
5351 	b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5352 	b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5353 	b[28] = b[29] = 6;
5354 	b[30] = b[31] = 7;
5355 }
5356 
5357 /* The minimum additive increment value for the congestion control table */
5358 #define CC_MIN_INCR 2U
5359 
5360 /**
5361  *	t4_load_mtus - write the MTU and congestion control HW tables
5362  *	@adap: the adapter
5363  *	@mtus: the values for the MTU table
5364  *	@alpha: the values for the congestion control alpha parameter
5365  *	@beta: the values for the congestion control beta parameter
5366  *
5367  *	Write the HW MTU table with the supplied MTUs and the high-speed
5368  *	congestion control table with the supplied alpha, beta, and MTUs.
5369  *	We write the two tables together because the additive increments
5370  *	depend on the MTUs.
5371  */
5372 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5373 		  const unsigned short *alpha, const unsigned short *beta)
5374 {
5375 	static const unsigned int avg_pkts[NCCTRL_WIN] = {
5376 		2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5377 		896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5378 		28672, 40960, 57344, 81920, 114688, 163840, 229376
5379 	};
5380 
5381 	unsigned int i, w;
5382 
5383 	for (i = 0; i < NMTUS; ++i) {
5384 		unsigned int mtu = mtus[i];
5385 		unsigned int log2 = fls(mtu);
5386 
5387 		if (!(mtu & ((1 << log2) >> 2)))     /* round */
5388 			log2--;
5389 		t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) |
5390 			     V_MTUWIDTH(log2) | V_MTUVALUE(mtu));
5391 
5392 		for (w = 0; w < NCCTRL_WIN; ++w) {
5393 			unsigned int inc;
5394 
5395 			inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5396 				  CC_MIN_INCR);
5397 
5398 			t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
5399 				     (w << 16) | (beta[w] << 13) | inc);
5400 		}
5401 	}
5402 }
5403 
5404 /**
5405  *	t4_set_pace_tbl - set the pace table
5406  *	@adap: the adapter
5407  *	@pace_vals: the pace values in microseconds
5408  *	@start: index of the first entry in the HW pace table to set
5409  *	@n: how many entries to set
5410  *
5411  *	Sets (a subset of the) HW pace table.
5412  */
5413 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
5414 		     unsigned int start, unsigned int n)
5415 {
5416 	unsigned int vals[NTX_SCHED], i;
5417 	unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
5418 
5419 	if (n > NTX_SCHED)
5420 	    return -ERANGE;
5421 
5422 	/* convert values from us to dack ticks, rounding to closest value */
5423 	for (i = 0; i < n; i++, pace_vals++) {
5424 		vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns;
5425 		if (vals[i] > 0x7ff)
5426 			return -ERANGE;
5427 		if (*pace_vals && vals[i] == 0)
5428 			return -ERANGE;
5429 	}
5430 	for (i = 0; i < n; i++, start++)
5431 		t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]);
5432 	return 0;
5433 }
5434 
5435 /**
5436  *	t4_set_sched_bps - set the bit rate for a HW traffic scheduler
5437  *	@adap: the adapter
5438  *	@kbps: target rate in Kbps
5439  *	@sched: the scheduler index
5440  *
5441  *	Configure a Tx HW scheduler for the target rate.
5442  */
5443 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps)
5444 {
5445 	unsigned int v, tps, cpt, bpt, delta, mindelta = ~0;
5446 	unsigned int clk = adap->params.vpd.cclk * 1000;
5447 	unsigned int selected_cpt = 0, selected_bpt = 0;
5448 
5449 	if (kbps > 0) {
5450 		kbps *= 125;     /* -> bytes */
5451 		for (cpt = 1; cpt <= 255; cpt++) {
5452 			tps = clk / cpt;
5453 			bpt = (kbps + tps / 2) / tps;
5454 			if (bpt > 0 && bpt <= 255) {
5455 				v = bpt * tps;
5456 				delta = v >= kbps ? v - kbps : kbps - v;
5457 				if (delta < mindelta) {
5458 					mindelta = delta;
5459 					selected_cpt = cpt;
5460 					selected_bpt = bpt;
5461 				}
5462 			} else if (selected_cpt)
5463 				break;
5464 		}
5465 		if (!selected_cpt)
5466 			return -EINVAL;
5467 	}
5468 	t4_write_reg(adap, A_TP_TM_PIO_ADDR,
5469 		     A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2);
5470 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5471 	if (sched & 1)
5472 		v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24);
5473 	else
5474 		v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8);
5475 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5476 	return 0;
5477 }
5478 
5479 /**
5480  *	t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler
5481  *	@adap: the adapter
5482  *	@sched: the scheduler index
5483  *	@ipg: the interpacket delay in tenths of nanoseconds
5484  *
5485  *	Set the interpacket delay for a HW packet rate scheduler.
5486  */
5487 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg)
5488 {
5489 	unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
5490 
5491 	/* convert ipg to nearest number of core clocks */
5492 	ipg *= core_ticks_per_usec(adap);
5493 	ipg = (ipg + 5000) / 10000;
5494 	if (ipg > M_TXTIMERSEPQ0)
5495 		return -EINVAL;
5496 
5497 	t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
5498 	v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
5499 	if (sched & 1)
5500 		v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg);
5501 	else
5502 		v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg);
5503 	t4_write_reg(adap, A_TP_TM_PIO_DATA, v);
5504 	t4_read_reg(adap, A_TP_TM_PIO_DATA);
5505 	return 0;
5506 }
5507 
5508 /*
5509  * Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5510  * clocks.  The formula is
5511  *
5512  * bytes/s = bytes256 * 256 * ClkFreq / 4096
5513  *
5514  * which is equivalent to
5515  *
5516  * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5517  */
5518 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5519 {
5520 	u64 v = bytes256 * adap->params.vpd.cclk;
5521 
5522 	return v * 62 + v / 2;
5523 }
5524 
5525 /**
5526  *	t4_get_chan_txrate - get the current per channel Tx rates
5527  *	@adap: the adapter
5528  *	@nic_rate: rates for NIC traffic
5529  *	@ofld_rate: rates for offloaded traffic
5530  *
5531  *	Return the current Tx rates in bytes/s for NIC and offloaded traffic
5532  *	for each channel.
5533  */
5534 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5535 {
5536 	u32 v;
5537 
5538 	v = t4_read_reg(adap, A_TP_TX_TRATE);
5539 	nic_rate[0] = chan_rate(adap, G_TNLRATE0(v));
5540 	nic_rate[1] = chan_rate(adap, G_TNLRATE1(v));
5541 	if (adap->chip_params->nchan > 2) {
5542 		nic_rate[2] = chan_rate(adap, G_TNLRATE2(v));
5543 		nic_rate[3] = chan_rate(adap, G_TNLRATE3(v));
5544 	}
5545 
5546 	v = t4_read_reg(adap, A_TP_TX_ORATE);
5547 	ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v));
5548 	ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v));
5549 	if (adap->chip_params->nchan > 2) {
5550 		ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v));
5551 		ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v));
5552 	}
5553 }
5554 
5555 /**
5556  *	t4_set_trace_filter - configure one of the tracing filters
5557  *	@adap: the adapter
5558  *	@tp: the desired trace filter parameters
5559  *	@idx: which filter to configure
5560  *	@enable: whether to enable or disable the filter
5561  *
5562  *	Configures one of the tracing filters available in HW.  If @tp is %NULL
5563  *	it indicates that the filter is already written in the register and it
5564  *	just needs to be enabled or disabled.
5565  */
5566 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5567     int idx, int enable)
5568 {
5569 	int i, ofst = idx * 4;
5570 	u32 data_reg, mask_reg, cfg;
5571 	u32 multitrc = F_TRCMULTIFILTER;
5572 	u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN;
5573 
5574 	if (idx < 0 || idx >= NTRACE)
5575 		return -EINVAL;
5576 
5577 	if (tp == NULL || !enable) {
5578 		t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en,
5579 		    enable ? en : 0);
5580 		return 0;
5581 	}
5582 
5583 	/*
5584 	 * TODO - After T4 data book is updated, specify the exact
5585 	 * section below.
5586 	 *
5587 	 * See T4 data book - MPS section for a complete description
5588 	 * of the below if..else handling of A_MPS_TRC_CFG register
5589 	 * value.
5590 	 */
5591 	cfg = t4_read_reg(adap, A_MPS_TRC_CFG);
5592 	if (cfg & F_TRCMULTIFILTER) {
5593 		/*
5594 		 * If multiple tracers are enabled, then maximum
5595 		 * capture size is 2.5KB (FIFO size of a single channel)
5596 		 * minus 2 flits for CPL_TRACE_PKT header.
5597 		 */
5598 		if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5599 			return -EINVAL;
5600 	} else {
5601 		/*
5602 		 * If multiple tracers are disabled, to avoid deadlocks
5603 		 * maximum packet capture size of 9600 bytes is recommended.
5604 		 * Also in this mode, only trace0 can be enabled and running.
5605 		 */
5606 		multitrc = 0;
5607 		if (tp->snap_len > 9600 || idx)
5608 			return -EINVAL;
5609 	}
5610 
5611 	if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 ||
5612 	    tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET ||
5613 	    tp->min_len > M_TFMINPKTSIZE)
5614 		return -EINVAL;
5615 
5616 	/* stop the tracer we'll be changing */
5617 	t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0);
5618 
5619 	idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH);
5620 	data_reg = A_MPS_TRC_FILTER0_MATCH + idx;
5621 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx;
5622 
5623 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5624 		t4_write_reg(adap, data_reg, tp->data[i]);
5625 		t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5626 	}
5627 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst,
5628 		     V_TFCAPTUREMAX(tp->snap_len) |
5629 		     V_TFMINPKTSIZE(tp->min_len));
5630 	t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst,
5631 		     V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en |
5632 		     (is_t4(adap) ?
5633 		     V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) :
5634 		     V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert)));
5635 
5636 	return 0;
5637 }
5638 
5639 /**
5640  *	t4_get_trace_filter - query one of the tracing filters
5641  *	@adap: the adapter
5642  *	@tp: the current trace filter parameters
5643  *	@idx: which trace filter to query
5644  *	@enabled: non-zero if the filter is enabled
5645  *
5646  *	Returns the current settings of one of the HW tracing filters.
5647  */
5648 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5649 			 int *enabled)
5650 {
5651 	u32 ctla, ctlb;
5652 	int i, ofst = idx * 4;
5653 	u32 data_reg, mask_reg;
5654 
5655 	ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst);
5656 	ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst);
5657 
5658 	if (is_t4(adap)) {
5659 		*enabled = !!(ctla & F_TFEN);
5660 		tp->port =  G_TFPORT(ctla);
5661 		tp->invert = !!(ctla & F_TFINVERTMATCH);
5662 	} else {
5663 		*enabled = !!(ctla & F_T5_TFEN);
5664 		tp->port = G_T5_TFPORT(ctla);
5665 		tp->invert = !!(ctla & F_T5_TFINVERTMATCH);
5666 	}
5667 	tp->snap_len = G_TFCAPTUREMAX(ctlb);
5668 	tp->min_len = G_TFMINPKTSIZE(ctlb);
5669 	tp->skip_ofst = G_TFOFFSET(ctla);
5670 	tp->skip_len = G_TFLENGTH(ctla);
5671 
5672 	ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx;
5673 	data_reg = A_MPS_TRC_FILTER0_MATCH + ofst;
5674 	mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst;
5675 
5676 	for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5677 		tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5678 		tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5679 	}
5680 }
5681 
5682 /**
5683  *	t4_pmtx_get_stats - returns the HW stats from PMTX
5684  *	@adap: the adapter
5685  *	@cnt: where to store the count statistics
5686  *	@cycles: where to store the cycle statistics
5687  *
5688  *	Returns performance statistics from PMTX.
5689  */
5690 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5691 {
5692 	int i;
5693 	u32 data[2];
5694 
5695 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5696 		t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1);
5697 		cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT);
5698 		if (is_t4(adap))
5699 			cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB);
5700 		else {
5701 			t4_read_indirect(adap, A_PM_TX_DBG_CTRL,
5702 					 A_PM_TX_DBG_DATA, data, 2,
5703 					 A_PM_TX_DBG_STAT_MSB);
5704 			cycles[i] = (((u64)data[0] << 32) | data[1]);
5705 		}
5706 	}
5707 }
5708 
5709 /**
5710  *	t4_pmrx_get_stats - returns the HW stats from PMRX
5711  *	@adap: the adapter
5712  *	@cnt: where to store the count statistics
5713  *	@cycles: where to store the cycle statistics
5714  *
5715  *	Returns performance statistics from PMRX.
5716  */
5717 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5718 {
5719 	int i;
5720 	u32 data[2];
5721 
5722 	for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) {
5723 		t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1);
5724 		cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT);
5725 		if (is_t4(adap)) {
5726 			cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB);
5727 		} else {
5728 			t4_read_indirect(adap, A_PM_RX_DBG_CTRL,
5729 					 A_PM_RX_DBG_DATA, data, 2,
5730 					 A_PM_RX_DBG_STAT_MSB);
5731 			cycles[i] = (((u64)data[0] << 32) | data[1]);
5732 		}
5733 	}
5734 }
5735 
5736 /**
5737  *	t4_get_mps_bg_map - return the buffer groups associated with a port
5738  *	@adap: the adapter
5739  *	@idx: the port index
5740  *
5741  *	Returns a bitmap indicating which MPS buffer groups are associated
5742  *	with the given port.  Bit i is set if buffer group i is used by the
5743  *	port.
5744  */
5745 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5746 {
5747 	u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL));
5748 
5749 	if (n == 0)
5750 		return idx == 0 ? 0xf : 0;
5751 	if (n == 1 && chip_id(adap) <= CHELSIO_T5)
5752 		return idx < 2 ? (3 << (2 * idx)) : 0;
5753 	return 1 << idx;
5754 }
5755 
5756 /**
5757  *      t4_get_port_type_description - return Port Type string description
5758  *      @port_type: firmware Port Type enumeration
5759  */
5760 const char *t4_get_port_type_description(enum fw_port_type port_type)
5761 {
5762 	static const char *const port_type_description[] = {
5763 		"Fiber_XFI",
5764 		"Fiber_XAUI",
5765 		"BT_SGMII",
5766 		"BT_XFI",
5767 		"BT_XAUI",
5768 		"KX4",
5769 		"CX4",
5770 		"KX",
5771 		"KR",
5772 		"SFP",
5773 		"BP_AP",
5774 		"BP4_AP",
5775 		"QSFP_10G",
5776 		"QSA",
5777 		"QSFP",
5778 		"BP40_BA",
5779 		"KR4_100G",
5780 		"CR4_QSFP",
5781 		"CR_QSFP",
5782 		"CR2_QSFP",
5783 		"SFP28",
5784 	};
5785 
5786 	if (port_type < ARRAY_SIZE(port_type_description))
5787 		return port_type_description[port_type];
5788 	return "UNKNOWN";
5789 }
5790 
5791 /**
5792  *      t4_get_port_stats_offset - collect port stats relative to a previous
5793  *				   snapshot
5794  *      @adap: The adapter
5795  *      @idx: The port
5796  *      @stats: Current stats to fill
5797  *      @offset: Previous stats snapshot
5798  */
5799 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5800 		struct port_stats *stats,
5801 		struct port_stats *offset)
5802 {
5803 	u64 *s, *o;
5804 	int i;
5805 
5806 	t4_get_port_stats(adap, idx, stats);
5807 	for (i = 0, s = (u64 *)stats, o = (u64 *)offset ;
5808 			i < (sizeof(struct port_stats)/sizeof(u64)) ;
5809 			i++, s++, o++)
5810 		*s -= *o;
5811 }
5812 
5813 /**
5814  *	t4_get_port_stats - collect port statistics
5815  *	@adap: the adapter
5816  *	@idx: the port index
5817  *	@p: the stats structure to fill
5818  *
5819  *	Collect statistics related to the given port from HW.
5820  */
5821 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5822 {
5823 	u32 bgmap = t4_get_mps_bg_map(adap, idx);
5824 	u32 stat_ctl;
5825 
5826 #define GET_STAT(name) \
5827 	t4_read_reg64(adap, \
5828 	(is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \
5829 	T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L)))
5830 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5831 
5832 	stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL);
5833 
5834 	p->tx_pause		= GET_STAT(TX_PORT_PAUSE);
5835 	p->tx_octets		= GET_STAT(TX_PORT_BYTES);
5836 	p->tx_frames		= GET_STAT(TX_PORT_FRAMES);
5837 	p->tx_bcast_frames	= GET_STAT(TX_PORT_BCAST);
5838 	p->tx_mcast_frames	= GET_STAT(TX_PORT_MCAST);
5839 	p->tx_ucast_frames	= GET_STAT(TX_PORT_UCAST);
5840 	p->tx_error_frames	= GET_STAT(TX_PORT_ERROR);
5841 	p->tx_frames_64		= GET_STAT(TX_PORT_64B);
5842 	p->tx_frames_65_127	= GET_STAT(TX_PORT_65B_127B);
5843 	p->tx_frames_128_255	= GET_STAT(TX_PORT_128B_255B);
5844 	p->tx_frames_256_511	= GET_STAT(TX_PORT_256B_511B);
5845 	p->tx_frames_512_1023	= GET_STAT(TX_PORT_512B_1023B);
5846 	p->tx_frames_1024_1518	= GET_STAT(TX_PORT_1024B_1518B);
5847 	p->tx_frames_1519_max	= GET_STAT(TX_PORT_1519B_MAX);
5848 	p->tx_drop		= GET_STAT(TX_PORT_DROP);
5849 	p->tx_ppp0		= GET_STAT(TX_PORT_PPP0);
5850 	p->tx_ppp1		= GET_STAT(TX_PORT_PPP1);
5851 	p->tx_ppp2		= GET_STAT(TX_PORT_PPP2);
5852 	p->tx_ppp3		= GET_STAT(TX_PORT_PPP3);
5853 	p->tx_ppp4		= GET_STAT(TX_PORT_PPP4);
5854 	p->tx_ppp5		= GET_STAT(TX_PORT_PPP5);
5855 	p->tx_ppp6		= GET_STAT(TX_PORT_PPP6);
5856 	p->tx_ppp7		= GET_STAT(TX_PORT_PPP7);
5857 
5858 	if (stat_ctl & F_COUNTPAUSESTATTX) {
5859 		p->tx_frames -= p->tx_pause;
5860 		p->tx_octets -= p->tx_pause * 64;
5861 		p->tx_mcast_frames -= p->tx_pause;
5862 	}
5863 
5864 	p->rx_pause		= GET_STAT(RX_PORT_PAUSE);
5865 	p->rx_octets		= GET_STAT(RX_PORT_BYTES);
5866 	p->rx_frames		= GET_STAT(RX_PORT_FRAMES);
5867 	p->rx_bcast_frames	= GET_STAT(RX_PORT_BCAST);
5868 	p->rx_mcast_frames	= GET_STAT(RX_PORT_MCAST);
5869 	p->rx_ucast_frames	= GET_STAT(RX_PORT_UCAST);
5870 	p->rx_too_long		= GET_STAT(RX_PORT_MTU_ERROR);
5871 	p->rx_jabber		= GET_STAT(RX_PORT_MTU_CRC_ERROR);
5872 	p->rx_fcs_err		= GET_STAT(RX_PORT_CRC_ERROR);
5873 	p->rx_len_err		= GET_STAT(RX_PORT_LEN_ERROR);
5874 	p->rx_symbol_err	= GET_STAT(RX_PORT_SYM_ERROR);
5875 	p->rx_runt		= GET_STAT(RX_PORT_LESS_64B);
5876 	p->rx_frames_64		= GET_STAT(RX_PORT_64B);
5877 	p->rx_frames_65_127	= GET_STAT(RX_PORT_65B_127B);
5878 	p->rx_frames_128_255	= GET_STAT(RX_PORT_128B_255B);
5879 	p->rx_frames_256_511	= GET_STAT(RX_PORT_256B_511B);
5880 	p->rx_frames_512_1023	= GET_STAT(RX_PORT_512B_1023B);
5881 	p->rx_frames_1024_1518	= GET_STAT(RX_PORT_1024B_1518B);
5882 	p->rx_frames_1519_max	= GET_STAT(RX_PORT_1519B_MAX);
5883 	p->rx_ppp0		= GET_STAT(RX_PORT_PPP0);
5884 	p->rx_ppp1		= GET_STAT(RX_PORT_PPP1);
5885 	p->rx_ppp2		= GET_STAT(RX_PORT_PPP2);
5886 	p->rx_ppp3		= GET_STAT(RX_PORT_PPP3);
5887 	p->rx_ppp4		= GET_STAT(RX_PORT_PPP4);
5888 	p->rx_ppp5		= GET_STAT(RX_PORT_PPP5);
5889 	p->rx_ppp6		= GET_STAT(RX_PORT_PPP6);
5890 	p->rx_ppp7		= GET_STAT(RX_PORT_PPP7);
5891 
5892 	if (stat_ctl & F_COUNTPAUSESTATRX) {
5893 		p->rx_frames -= p->rx_pause;
5894 		p->rx_octets -= p->rx_pause * 64;
5895 		p->rx_mcast_frames -= p->rx_pause;
5896 	}
5897 
5898 	p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5899 	p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5900 	p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5901 	p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5902 	p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5903 	p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5904 	p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5905 	p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5906 
5907 #undef GET_STAT
5908 #undef GET_STAT_COM
5909 }
5910 
5911 /**
5912  *	t4_get_lb_stats - collect loopback port statistics
5913  *	@adap: the adapter
5914  *	@idx: the loopback port index
5915  *	@p: the stats structure to fill
5916  *
5917  *	Return HW statistics for the given loopback port.
5918  */
5919 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5920 {
5921 	u32 bgmap = t4_get_mps_bg_map(adap, idx);
5922 
5923 #define GET_STAT(name) \
5924 	t4_read_reg64(adap, \
5925 	(is_t4(adap) ? \
5926 	PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \
5927 	T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L)))
5928 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L)
5929 
5930 	p->octets	= GET_STAT(BYTES);
5931 	p->frames	= GET_STAT(FRAMES);
5932 	p->bcast_frames	= GET_STAT(BCAST);
5933 	p->mcast_frames	= GET_STAT(MCAST);
5934 	p->ucast_frames	= GET_STAT(UCAST);
5935 	p->error_frames	= GET_STAT(ERROR);
5936 
5937 	p->frames_64		= GET_STAT(64B);
5938 	p->frames_65_127	= GET_STAT(65B_127B);
5939 	p->frames_128_255	= GET_STAT(128B_255B);
5940 	p->frames_256_511	= GET_STAT(256B_511B);
5941 	p->frames_512_1023	= GET_STAT(512B_1023B);
5942 	p->frames_1024_1518	= GET_STAT(1024B_1518B);
5943 	p->frames_1519_max	= GET_STAT(1519B_MAX);
5944 	p->drop			= GET_STAT(DROP_FRAMES);
5945 
5946 	p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5947 	p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5948 	p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5949 	p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5950 	p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5951 	p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5952 	p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5953 	p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5954 
5955 #undef GET_STAT
5956 #undef GET_STAT_COM
5957 }
5958 
5959 /**
5960  *	t4_wol_magic_enable - enable/disable magic packet WoL
5961  *	@adap: the adapter
5962  *	@port: the physical port index
5963  *	@addr: MAC address expected in magic packets, %NULL to disable
5964  *
5965  *	Enables/disables magic packet wake-on-LAN for the selected port.
5966  */
5967 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
5968 			 const u8 *addr)
5969 {
5970 	u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg;
5971 
5972 	if (is_t4(adap)) {
5973 		mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO);
5974 		mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI);
5975 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
5976 	} else {
5977 		mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO);
5978 		mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI);
5979 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
5980 	}
5981 
5982 	if (addr) {
5983 		t4_write_reg(adap, mag_id_reg_l,
5984 			     (addr[2] << 24) | (addr[3] << 16) |
5985 			     (addr[4] << 8) | addr[5]);
5986 		t4_write_reg(adap, mag_id_reg_h,
5987 			     (addr[0] << 8) | addr[1]);
5988 	}
5989 	t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN,
5990 			 V_MAGICEN(addr != NULL));
5991 }
5992 
5993 /**
5994  *	t4_wol_pat_enable - enable/disable pattern-based WoL
5995  *	@adap: the adapter
5996  *	@port: the physical port index
5997  *	@map: bitmap of which HW pattern filters to set
5998  *	@mask0: byte mask for bytes 0-63 of a packet
5999  *	@mask1: byte mask for bytes 64-127 of a packet
6000  *	@crc: Ethernet CRC for selected bytes
6001  *	@enable: enable/disable switch
6002  *
6003  *	Sets the pattern filters indicated in @map to mask out the bytes
6004  *	specified in @mask0/@mask1 in received packets and compare the CRC of
6005  *	the resulting packet against @crc.  If @enable is %true pattern-based
6006  *	WoL is enabled, otherwise disabled.
6007  */
6008 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
6009 		      u64 mask0, u64 mask1, unsigned int crc, bool enable)
6010 {
6011 	int i;
6012 	u32 port_cfg_reg;
6013 
6014 	if (is_t4(adap))
6015 		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
6016 	else
6017 		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
6018 
6019 	if (!enable) {
6020 		t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
6021 		return 0;
6022 	}
6023 	if (map > 0xff)
6024 		return -EINVAL;
6025 
6026 #define EPIO_REG(name) \
6027 	(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
6028 	T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
6029 
6030 	t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
6031 	t4_write_reg(adap, EPIO_REG(DATA2), mask1);
6032 	t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
6033 
6034 	for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
6035 		if (!(map & 1))
6036 			continue;
6037 
6038 		/* write byte masks */
6039 		t4_write_reg(adap, EPIO_REG(DATA0), mask0);
6040 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
6041 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
6042 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
6043 			return -ETIMEDOUT;
6044 
6045 		/* write CRC */
6046 		t4_write_reg(adap, EPIO_REG(DATA0), crc);
6047 		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
6048 		t4_read_reg(adap, EPIO_REG(OP));                /* flush */
6049 		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
6050 			return -ETIMEDOUT;
6051 	}
6052 #undef EPIO_REG
6053 
6054 	t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
6055 	return 0;
6056 }
6057 
6058 /*     t4_mk_filtdelwr - create a delete filter WR
6059  *     @ftid: the filter ID
6060  *     @wr: the filter work request to populate
6061  *     @qid: ingress queue to receive the delete notification
6062  *
6063  *     Creates a filter work request to delete the supplied filter.  If @qid is
6064  *     negative the delete notification is suppressed.
6065  */
6066 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6067 {
6068 	memset(wr, 0, sizeof(*wr));
6069 	wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR));
6070 	wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16));
6071 	wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) |
6072 				    V_FW_FILTER_WR_NOREPLY(qid < 0));
6073 	wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER);
6074 	if (qid >= 0)
6075 		wr->rx_chan_rx_rpl_iq =
6076 				cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid));
6077 }
6078 
6079 #define INIT_CMD(var, cmd, rd_wr) do { \
6080 	(var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \
6081 					F_FW_CMD_REQUEST | \
6082 					F_FW_CMD_##rd_wr); \
6083 	(var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6084 } while (0)
6085 
6086 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6087 			  u32 addr, u32 val)
6088 {
6089 	u32 ldst_addrspace;
6090 	struct fw_ldst_cmd c;
6091 
6092 	memset(&c, 0, sizeof(c));
6093 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE);
6094 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6095 					F_FW_CMD_REQUEST |
6096 					F_FW_CMD_WRITE |
6097 					ldst_addrspace);
6098 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6099 	c.u.addrval.addr = cpu_to_be32(addr);
6100 	c.u.addrval.val = cpu_to_be32(val);
6101 
6102 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6103 }
6104 
6105 /**
6106  *	t4_mdio_rd - read a PHY register through MDIO
6107  *	@adap: the adapter
6108  *	@mbox: mailbox to use for the FW command
6109  *	@phy_addr: the PHY address
6110  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
6111  *	@reg: the register to read
6112  *	@valp: where to store the value
6113  *
6114  *	Issues a FW command through the given mailbox to read a PHY register.
6115  */
6116 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6117 	       unsigned int mmd, unsigned int reg, unsigned int *valp)
6118 {
6119 	int ret;
6120 	u32 ldst_addrspace;
6121 	struct fw_ldst_cmd c;
6122 
6123 	memset(&c, 0, sizeof(c));
6124 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6125 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6126 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
6127 					ldst_addrspace);
6128 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6129 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6130 					 V_FW_LDST_CMD_MMD(mmd));
6131 	c.u.mdio.raddr = cpu_to_be16(reg);
6132 
6133 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6134 	if (ret == 0)
6135 		*valp = be16_to_cpu(c.u.mdio.rval);
6136 	return ret;
6137 }
6138 
6139 /**
6140  *	t4_mdio_wr - write a PHY register through MDIO
6141  *	@adap: the adapter
6142  *	@mbox: mailbox to use for the FW command
6143  *	@phy_addr: the PHY address
6144  *	@mmd: the PHY MMD to access (0 for clause 22 PHYs)
6145  *	@reg: the register to write
6146  *	@valp: value to write
6147  *
6148  *	Issues a FW command through the given mailbox to write a PHY register.
6149  */
6150 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6151 	       unsigned int mmd, unsigned int reg, unsigned int val)
6152 {
6153 	u32 ldst_addrspace;
6154 	struct fw_ldst_cmd c;
6155 
6156 	memset(&c, 0, sizeof(c));
6157 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO);
6158 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6159 					F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6160 					ldst_addrspace);
6161 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6162 	c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) |
6163 					 V_FW_LDST_CMD_MMD(mmd));
6164 	c.u.mdio.raddr = cpu_to_be16(reg);
6165 	c.u.mdio.rval = cpu_to_be16(val);
6166 
6167 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6168 }
6169 
6170 /**
6171  *
6172  *	t4_sge_decode_idma_state - decode the idma state
6173  *	@adap: the adapter
6174  *	@state: the state idma is stuck in
6175  */
6176 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6177 {
6178 	static const char * const t4_decode[] = {
6179 		"IDMA_IDLE",
6180 		"IDMA_PUSH_MORE_CPL_FIFO",
6181 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6182 		"Not used",
6183 		"IDMA_PHYSADDR_SEND_PCIEHDR",
6184 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6185 		"IDMA_PHYSADDR_SEND_PAYLOAD",
6186 		"IDMA_SEND_FIFO_TO_IMSG",
6187 		"IDMA_FL_REQ_DATA_FL_PREP",
6188 		"IDMA_FL_REQ_DATA_FL",
6189 		"IDMA_FL_DROP",
6190 		"IDMA_FL_H_REQ_HEADER_FL",
6191 		"IDMA_FL_H_SEND_PCIEHDR",
6192 		"IDMA_FL_H_PUSH_CPL_FIFO",
6193 		"IDMA_FL_H_SEND_CPL",
6194 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6195 		"IDMA_FL_H_SEND_IP_HDR",
6196 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6197 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6198 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6199 		"IDMA_FL_D_SEND_PCIEHDR",
6200 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6201 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6202 		"IDMA_FL_SEND_PCIEHDR",
6203 		"IDMA_FL_PUSH_CPL_FIFO",
6204 		"IDMA_FL_SEND_CPL",
6205 		"IDMA_FL_SEND_PAYLOAD_FIRST",
6206 		"IDMA_FL_SEND_PAYLOAD",
6207 		"IDMA_FL_REQ_NEXT_DATA_FL",
6208 		"IDMA_FL_SEND_NEXT_PCIEHDR",
6209 		"IDMA_FL_SEND_PADDING",
6210 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6211 		"IDMA_FL_SEND_FIFO_TO_IMSG",
6212 		"IDMA_FL_REQ_DATAFL_DONE",
6213 		"IDMA_FL_REQ_HEADERFL_DONE",
6214 	};
6215 	static const char * const t5_decode[] = {
6216 		"IDMA_IDLE",
6217 		"IDMA_ALMOST_IDLE",
6218 		"IDMA_PUSH_MORE_CPL_FIFO",
6219 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6220 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6221 		"IDMA_PHYSADDR_SEND_PCIEHDR",
6222 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6223 		"IDMA_PHYSADDR_SEND_PAYLOAD",
6224 		"IDMA_SEND_FIFO_TO_IMSG",
6225 		"IDMA_FL_REQ_DATA_FL",
6226 		"IDMA_FL_DROP",
6227 		"IDMA_FL_DROP_SEND_INC",
6228 		"IDMA_FL_H_REQ_HEADER_FL",
6229 		"IDMA_FL_H_SEND_PCIEHDR",
6230 		"IDMA_FL_H_PUSH_CPL_FIFO",
6231 		"IDMA_FL_H_SEND_CPL",
6232 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6233 		"IDMA_FL_H_SEND_IP_HDR",
6234 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6235 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6236 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6237 		"IDMA_FL_D_SEND_PCIEHDR",
6238 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6239 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6240 		"IDMA_FL_SEND_PCIEHDR",
6241 		"IDMA_FL_PUSH_CPL_FIFO",
6242 		"IDMA_FL_SEND_CPL",
6243 		"IDMA_FL_SEND_PAYLOAD_FIRST",
6244 		"IDMA_FL_SEND_PAYLOAD",
6245 		"IDMA_FL_REQ_NEXT_DATA_FL",
6246 		"IDMA_FL_SEND_NEXT_PCIEHDR",
6247 		"IDMA_FL_SEND_PADDING",
6248 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6249 	};
6250 	static const char * const t6_decode[] = {
6251 		"IDMA_IDLE",
6252 		"IDMA_PUSH_MORE_CPL_FIFO",
6253 		"IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6254 		"IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6255 		"IDMA_PHYSADDR_SEND_PCIEHDR",
6256 		"IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6257 		"IDMA_PHYSADDR_SEND_PAYLOAD",
6258 		"IDMA_FL_REQ_DATA_FL",
6259 		"IDMA_FL_DROP",
6260 		"IDMA_FL_DROP_SEND_INC",
6261 		"IDMA_FL_H_REQ_HEADER_FL",
6262 		"IDMA_FL_H_SEND_PCIEHDR",
6263 		"IDMA_FL_H_PUSH_CPL_FIFO",
6264 		"IDMA_FL_H_SEND_CPL",
6265 		"IDMA_FL_H_SEND_IP_HDR_FIRST",
6266 		"IDMA_FL_H_SEND_IP_HDR",
6267 		"IDMA_FL_H_REQ_NEXT_HEADER_FL",
6268 		"IDMA_FL_H_SEND_NEXT_PCIEHDR",
6269 		"IDMA_FL_H_SEND_IP_HDR_PADDING",
6270 		"IDMA_FL_D_SEND_PCIEHDR",
6271 		"IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6272 		"IDMA_FL_D_REQ_NEXT_DATA_FL",
6273 		"IDMA_FL_SEND_PCIEHDR",
6274 		"IDMA_FL_PUSH_CPL_FIFO",
6275 		"IDMA_FL_SEND_CPL",
6276 		"IDMA_FL_SEND_PAYLOAD_FIRST",
6277 		"IDMA_FL_SEND_PAYLOAD",
6278 		"IDMA_FL_REQ_NEXT_DATA_FL",
6279 		"IDMA_FL_SEND_NEXT_PCIEHDR",
6280 		"IDMA_FL_SEND_PADDING",
6281 		"IDMA_FL_SEND_COMPLETION_TO_IMSG",
6282 	};
6283 	static const u32 sge_regs[] = {
6284 		A_SGE_DEBUG_DATA_LOW_INDEX_2,
6285 		A_SGE_DEBUG_DATA_LOW_INDEX_3,
6286 		A_SGE_DEBUG_DATA_HIGH_INDEX_10,
6287 	};
6288 	const char * const *sge_idma_decode;
6289 	int sge_idma_decode_nstates;
6290 	int i;
6291 	unsigned int chip_version = chip_id(adapter);
6292 
6293 	/* Select the right set of decode strings to dump depending on the
6294 	 * adapter chip type.
6295 	 */
6296 	switch (chip_version) {
6297 	case CHELSIO_T4:
6298 		sge_idma_decode = (const char * const *)t4_decode;
6299 		sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6300 		break;
6301 
6302 	case CHELSIO_T5:
6303 		sge_idma_decode = (const char * const *)t5_decode;
6304 		sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6305 		break;
6306 
6307 	case CHELSIO_T6:
6308 		sge_idma_decode = (const char * const *)t6_decode;
6309 		sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6310 		break;
6311 
6312 	default:
6313 		CH_ERR(adapter,	"Unsupported chip version %d\n", chip_version);
6314 		return;
6315 	}
6316 
6317 	if (state < sge_idma_decode_nstates)
6318 		CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6319 	else
6320 		CH_WARN(adapter, "idma state %d unknown\n", state);
6321 
6322 	for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6323 		CH_WARN(adapter, "SGE register %#x value %#x\n",
6324 			sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6325 }
6326 
6327 /**
6328  *      t4_sge_ctxt_flush - flush the SGE context cache
6329  *      @adap: the adapter
6330  *      @mbox: mailbox to use for the FW command
6331  *
6332  *      Issues a FW command through the given mailbox to flush the
6333  *      SGE context cache.
6334  */
6335 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
6336 {
6337 	int ret;
6338 	u32 ldst_addrspace;
6339 	struct fw_ldst_cmd c;
6340 
6341 	memset(&c, 0, sizeof(c));
6342 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC);
6343 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
6344 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
6345 					ldst_addrspace);
6346 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6347 	c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH);
6348 
6349 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6350 	return ret;
6351 }
6352 
6353 /**
6354  *      t4_fw_hello - establish communication with FW
6355  *      @adap: the adapter
6356  *      @mbox: mailbox to use for the FW command
6357  *      @evt_mbox: mailbox to receive async FW events
6358  *      @master: specifies the caller's willingness to be the device master
6359  *	@state: returns the current device state (if non-NULL)
6360  *
6361  *	Issues a command to establish communication with FW.  Returns either
6362  *	an error (negative integer) or the mailbox of the Master PF.
6363  */
6364 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6365 		enum dev_master master, enum dev_state *state)
6366 {
6367 	int ret;
6368 	struct fw_hello_cmd c;
6369 	u32 v;
6370 	unsigned int master_mbox;
6371 	int retries = FW_CMD_HELLO_RETRIES;
6372 
6373 retry:
6374 	memset(&c, 0, sizeof(c));
6375 	INIT_CMD(c, HELLO, WRITE);
6376 	c.err_to_clearinit = cpu_to_be32(
6377 		V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
6378 		V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
6379 		V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ?
6380 					mbox : M_FW_HELLO_CMD_MBMASTER) |
6381 		V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
6382 		V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) |
6383 		F_FW_HELLO_CMD_CLEARINIT);
6384 
6385 	/*
6386 	 * Issue the HELLO command to the firmware.  If it's not successful
6387 	 * but indicates that we got a "busy" or "timeout" condition, retry
6388 	 * the HELLO until we exhaust our retry limit.  If we do exceed our
6389 	 * retry limit, check to see if the firmware left us any error
6390 	 * information and report that if so ...
6391 	 */
6392 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6393 	if (ret != FW_SUCCESS) {
6394 		if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6395 			goto retry;
6396 		if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR)
6397 			t4_report_fw_error(adap);
6398 		return ret;
6399 	}
6400 
6401 	v = be32_to_cpu(c.err_to_clearinit);
6402 	master_mbox = G_FW_HELLO_CMD_MBMASTER(v);
6403 	if (state) {
6404 		if (v & F_FW_HELLO_CMD_ERR)
6405 			*state = DEV_STATE_ERR;
6406 		else if (v & F_FW_HELLO_CMD_INIT)
6407 			*state = DEV_STATE_INIT;
6408 		else
6409 			*state = DEV_STATE_UNINIT;
6410 	}
6411 
6412 	/*
6413 	 * If we're not the Master PF then we need to wait around for the
6414 	 * Master PF Driver to finish setting up the adapter.
6415 	 *
6416 	 * Note that we also do this wait if we're a non-Master-capable PF and
6417 	 * there is no current Master PF; a Master PF may show up momentarily
6418 	 * and we wouldn't want to fail pointlessly.  (This can happen when an
6419 	 * OS loads lots of different drivers rapidly at the same time).  In
6420 	 * this case, the Master PF returned by the firmware will be
6421 	 * M_PCIE_FW_MASTER so the test below will work ...
6422 	 */
6423 	if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 &&
6424 	    master_mbox != mbox) {
6425 		int waiting = FW_CMD_HELLO_TIMEOUT;
6426 
6427 		/*
6428 		 * Wait for the firmware to either indicate an error or
6429 		 * initialized state.  If we see either of these we bail out
6430 		 * and report the issue to the caller.  If we exhaust the
6431 		 * "hello timeout" and we haven't exhausted our retries, try
6432 		 * again.  Otherwise bail with a timeout error.
6433 		 */
6434 		for (;;) {
6435 			u32 pcie_fw;
6436 
6437 			msleep(50);
6438 			waiting -= 50;
6439 
6440 			/*
6441 			 * If neither Error nor Initialialized are indicated
6442 			 * by the firmware keep waiting till we exhaust our
6443 			 * timeout ... and then retry if we haven't exhausted
6444 			 * our retries ...
6445 			 */
6446 			pcie_fw = t4_read_reg(adap, A_PCIE_FW);
6447 			if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) {
6448 				if (waiting <= 0) {
6449 					if (retries-- > 0)
6450 						goto retry;
6451 
6452 					return -ETIMEDOUT;
6453 				}
6454 				continue;
6455 			}
6456 
6457 			/*
6458 			 * We either have an Error or Initialized condition
6459 			 * report errors preferentially.
6460 			 */
6461 			if (state) {
6462 				if (pcie_fw & F_PCIE_FW_ERR)
6463 					*state = DEV_STATE_ERR;
6464 				else if (pcie_fw & F_PCIE_FW_INIT)
6465 					*state = DEV_STATE_INIT;
6466 			}
6467 
6468 			/*
6469 			 * If we arrived before a Master PF was selected and
6470 			 * there's not a valid Master PF, grab its identity
6471 			 * for our caller.
6472 			 */
6473 			if (master_mbox == M_PCIE_FW_MASTER &&
6474 			    (pcie_fw & F_PCIE_FW_MASTER_VLD))
6475 				master_mbox = G_PCIE_FW_MASTER(pcie_fw);
6476 			break;
6477 		}
6478 	}
6479 
6480 	return master_mbox;
6481 }
6482 
6483 /**
6484  *	t4_fw_bye - end communication with FW
6485  *	@adap: the adapter
6486  *	@mbox: mailbox to use for the FW command
6487  *
6488  *	Issues a command to terminate communication with FW.
6489  */
6490 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6491 {
6492 	struct fw_bye_cmd c;
6493 
6494 	memset(&c, 0, sizeof(c));
6495 	INIT_CMD(c, BYE, WRITE);
6496 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6497 }
6498 
6499 /**
6500  *	t4_fw_reset - issue a reset to FW
6501  *	@adap: the adapter
6502  *	@mbox: mailbox to use for the FW command
6503  *	@reset: specifies the type of reset to perform
6504  *
6505  *	Issues a reset command of the specified type to FW.
6506  */
6507 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6508 {
6509 	struct fw_reset_cmd c;
6510 
6511 	memset(&c, 0, sizeof(c));
6512 	INIT_CMD(c, RESET, WRITE);
6513 	c.val = cpu_to_be32(reset);
6514 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6515 }
6516 
6517 /**
6518  *	t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6519  *	@adap: the adapter
6520  *	@mbox: mailbox to use for the FW RESET command (if desired)
6521  *	@force: force uP into RESET even if FW RESET command fails
6522  *
6523  *	Issues a RESET command to firmware (if desired) with a HALT indication
6524  *	and then puts the microprocessor into RESET state.  The RESET command
6525  *	will only be issued if a legitimate mailbox is provided (mbox <=
6526  *	M_PCIE_FW_MASTER).
6527  *
6528  *	This is generally used in order for the host to safely manipulate the
6529  *	adapter without fear of conflicting with whatever the firmware might
6530  *	be doing.  The only way out of this state is to RESTART the firmware
6531  *	...
6532  */
6533 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6534 {
6535 	int ret = 0;
6536 
6537 	/*
6538 	 * If a legitimate mailbox is provided, issue a RESET command
6539 	 * with a HALT indication.
6540 	 */
6541 	if (mbox <= M_PCIE_FW_MASTER) {
6542 		struct fw_reset_cmd c;
6543 
6544 		memset(&c, 0, sizeof(c));
6545 		INIT_CMD(c, RESET, WRITE);
6546 		c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE);
6547 		c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT);
6548 		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6549 	}
6550 
6551 	/*
6552 	 * Normally we won't complete the operation if the firmware RESET
6553 	 * command fails but if our caller insists we'll go ahead and put the
6554 	 * uP into RESET.  This can be useful if the firmware is hung or even
6555 	 * missing ...  We'll have to take the risk of putting the uP into
6556 	 * RESET without the cooperation of firmware in that case.
6557 	 *
6558 	 * We also force the firmware's HALT flag to be on in case we bypassed
6559 	 * the firmware RESET command above or we're dealing with old firmware
6560 	 * which doesn't have the HALT capability.  This will serve as a flag
6561 	 * for the incoming firmware to know that it's coming out of a HALT
6562 	 * rather than a RESET ... if it's new enough to understand that ...
6563 	 */
6564 	if (ret == 0 || force) {
6565 		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST);
6566 		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT,
6567 				 F_PCIE_FW_HALT);
6568 	}
6569 
6570 	/*
6571 	 * And we always return the result of the firmware RESET command
6572 	 * even when we force the uP into RESET ...
6573 	 */
6574 	return ret;
6575 }
6576 
6577 /**
6578  *	t4_fw_restart - restart the firmware by taking the uP out of RESET
6579  *	@adap: the adapter
6580  *	@reset: if we want to do a RESET to restart things
6581  *
6582  *	Restart firmware previously halted by t4_fw_halt().  On successful
6583  *	return the previous PF Master remains as the new PF Master and there
6584  *	is no need to issue a new HELLO command, etc.
6585  *
6586  *	We do this in two ways:
6587  *
6588  *	 1. If we're dealing with newer firmware we'll simply want to take
6589  *	    the chip's microprocessor out of RESET.  This will cause the
6590  *	    firmware to start up from its start vector.  And then we'll loop
6591  *	    until the firmware indicates it's started again (PCIE_FW.HALT
6592  *	    reset to 0) or we timeout.
6593  *
6594  *	 2. If we're dealing with older firmware then we'll need to RESET
6595  *	    the chip since older firmware won't recognize the PCIE_FW.HALT
6596  *	    flag and automatically RESET itself on startup.
6597  */
6598 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6599 {
6600 	if (reset) {
6601 		/*
6602 		 * Since we're directing the RESET instead of the firmware
6603 		 * doing it automatically, we need to clear the PCIE_FW.HALT
6604 		 * bit.
6605 		 */
6606 		t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0);
6607 
6608 		/*
6609 		 * If we've been given a valid mailbox, first try to get the
6610 		 * firmware to do the RESET.  If that works, great and we can
6611 		 * return success.  Otherwise, if we haven't been given a
6612 		 * valid mailbox or the RESET command failed, fall back to
6613 		 * hitting the chip with a hammer.
6614 		 */
6615 		if (mbox <= M_PCIE_FW_MASTER) {
6616 			t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6617 			msleep(100);
6618 			if (t4_fw_reset(adap, mbox,
6619 					F_PIORST | F_PIORSTMODE) == 0)
6620 				return 0;
6621 		}
6622 
6623 		t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE);
6624 		msleep(2000);
6625 	} else {
6626 		int ms;
6627 
6628 		t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0);
6629 		for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6630 			if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT))
6631 				return FW_SUCCESS;
6632 			msleep(100);
6633 			ms += 100;
6634 		}
6635 		return -ETIMEDOUT;
6636 	}
6637 	return 0;
6638 }
6639 
6640 /**
6641  *	t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6642  *	@adap: the adapter
6643  *	@mbox: mailbox to use for the FW RESET command (if desired)
6644  *	@fw_data: the firmware image to write
6645  *	@size: image size
6646  *	@force: force upgrade even if firmware doesn't cooperate
6647  *
6648  *	Perform all of the steps necessary for upgrading an adapter's
6649  *	firmware image.  Normally this requires the cooperation of the
6650  *	existing firmware in order to halt all existing activities
6651  *	but if an invalid mailbox token is passed in we skip that step
6652  *	(though we'll still put the adapter microprocessor into RESET in
6653  *	that case).
6654  *
6655  *	On successful return the new firmware will have been loaded and
6656  *	the adapter will have been fully RESET losing all previous setup
6657  *	state.  On unsuccessful return the adapter may be completely hosed ...
6658  *	positive errno indicates that the adapter is ~probably~ intact, a
6659  *	negative errno indicates that things are looking bad ...
6660  */
6661 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6662 		  const u8 *fw_data, unsigned int size, int force)
6663 {
6664 	const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6665 	unsigned int bootstrap =
6666 	    be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP;
6667 	int reset, ret;
6668 
6669 	if (!t4_fw_matches_chip(adap, fw_hdr))
6670 		return -EINVAL;
6671 
6672 	if (!bootstrap) {
6673 		ret = t4_fw_halt(adap, mbox, force);
6674 		if (ret < 0 && !force)
6675 			return ret;
6676 	}
6677 
6678 	ret = t4_load_fw(adap, fw_data, size);
6679 	if (ret < 0 || bootstrap)
6680 		return ret;
6681 
6682 	/*
6683 	 * Older versions of the firmware don't understand the new
6684 	 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6685 	 * restart.  So for newly loaded older firmware we'll have to do the
6686 	 * RESET for it so it starts up on a clean slate.  We can tell if
6687 	 * the newly loaded firmware will handle this right by checking
6688 	 * its header flags to see if it advertises the capability.
6689 	 */
6690 	reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6691 	return t4_fw_restart(adap, mbox, reset);
6692 }
6693 
6694 /**
6695  *	t4_fw_initialize - ask FW to initialize the device
6696  *	@adap: the adapter
6697  *	@mbox: mailbox to use for the FW command
6698  *
6699  *	Issues a command to FW to partially initialize the device.  This
6700  *	performs initialization that generally doesn't depend on user input.
6701  */
6702 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6703 {
6704 	struct fw_initialize_cmd c;
6705 
6706 	memset(&c, 0, sizeof(c));
6707 	INIT_CMD(c, INITIALIZE, WRITE);
6708 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6709 }
6710 
6711 /**
6712  *	t4_query_params_rw - query FW or device parameters
6713  *	@adap: the adapter
6714  *	@mbox: mailbox to use for the FW command
6715  *	@pf: the PF
6716  *	@vf: the VF
6717  *	@nparams: the number of parameters
6718  *	@params: the parameter names
6719  *	@val: the parameter values
6720  *	@rw: Write and read flag
6721  *
6722  *	Reads the value of FW or device parameters.  Up to 7 parameters can be
6723  *	queried at once.
6724  */
6725 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6726 		       unsigned int vf, unsigned int nparams, const u32 *params,
6727 		       u32 *val, int rw)
6728 {
6729 	int i, ret;
6730 	struct fw_params_cmd c;
6731 	__be32 *p = &c.param[0].mnem;
6732 
6733 	if (nparams > 7)
6734 		return -EINVAL;
6735 
6736 	memset(&c, 0, sizeof(c));
6737 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6738 				  F_FW_CMD_REQUEST | F_FW_CMD_READ |
6739 				  V_FW_PARAMS_CMD_PFN(pf) |
6740 				  V_FW_PARAMS_CMD_VFN(vf));
6741 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6742 
6743 	for (i = 0; i < nparams; i++) {
6744 		*p++ = cpu_to_be32(*params++);
6745 		if (rw)
6746 			*p = cpu_to_be32(*(val + i));
6747 		p++;
6748 	}
6749 
6750 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6751 	if (ret == 0)
6752 		for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6753 			*val++ = be32_to_cpu(*p);
6754 	return ret;
6755 }
6756 
6757 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6758 		    unsigned int vf, unsigned int nparams, const u32 *params,
6759 		    u32 *val)
6760 {
6761 	return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6762 }
6763 
6764 /**
6765  *      t4_set_params_timeout - sets FW or device parameters
6766  *      @adap: the adapter
6767  *      @mbox: mailbox to use for the FW command
6768  *      @pf: the PF
6769  *      @vf: the VF
6770  *      @nparams: the number of parameters
6771  *      @params: the parameter names
6772  *      @val: the parameter values
6773  *      @timeout: the timeout time
6774  *
6775  *      Sets the value of FW or device parameters.  Up to 7 parameters can be
6776  *      specified at once.
6777  */
6778 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6779 			  unsigned int pf, unsigned int vf,
6780 			  unsigned int nparams, const u32 *params,
6781 			  const u32 *val, int timeout)
6782 {
6783 	struct fw_params_cmd c;
6784 	__be32 *p = &c.param[0].mnem;
6785 
6786 	if (nparams > 7)
6787 		return -EINVAL;
6788 
6789 	memset(&c, 0, sizeof(c));
6790 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) |
6791 				  F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
6792 				  V_FW_PARAMS_CMD_PFN(pf) |
6793 				  V_FW_PARAMS_CMD_VFN(vf));
6794 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6795 
6796 	while (nparams--) {
6797 		*p++ = cpu_to_be32(*params++);
6798 		*p++ = cpu_to_be32(*val++);
6799 	}
6800 
6801 	return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6802 }
6803 
6804 /**
6805  *	t4_set_params - sets FW or device parameters
6806  *	@adap: the adapter
6807  *	@mbox: mailbox to use for the FW command
6808  *	@pf: the PF
6809  *	@vf: the VF
6810  *	@nparams: the number of parameters
6811  *	@params: the parameter names
6812  *	@val: the parameter values
6813  *
6814  *	Sets the value of FW or device parameters.  Up to 7 parameters can be
6815  *	specified at once.
6816  */
6817 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6818 		  unsigned int vf, unsigned int nparams, const u32 *params,
6819 		  const u32 *val)
6820 {
6821 	return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6822 				     FW_CMD_MAX_TIMEOUT);
6823 }
6824 
6825 /**
6826  *	t4_cfg_pfvf - configure PF/VF resource limits
6827  *	@adap: the adapter
6828  *	@mbox: mailbox to use for the FW command
6829  *	@pf: the PF being configured
6830  *	@vf: the VF being configured
6831  *	@txq: the max number of egress queues
6832  *	@txq_eth_ctrl: the max number of egress Ethernet or control queues
6833  *	@rxqi: the max number of interrupt-capable ingress queues
6834  *	@rxq: the max number of interruptless ingress queues
6835  *	@tc: the PCI traffic class
6836  *	@vi: the max number of virtual interfaces
6837  *	@cmask: the channel access rights mask for the PF/VF
6838  *	@pmask: the port access rights mask for the PF/VF
6839  *	@nexact: the maximum number of exact MPS filters
6840  *	@rcaps: read capabilities
6841  *	@wxcaps: write/execute capabilities
6842  *
6843  *	Configures resource limits and capabilities for a physical or virtual
6844  *	function.
6845  */
6846 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6847 		unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6848 		unsigned int rxqi, unsigned int rxq, unsigned int tc,
6849 		unsigned int vi, unsigned int cmask, unsigned int pmask,
6850 		unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6851 {
6852 	struct fw_pfvf_cmd c;
6853 
6854 	memset(&c, 0, sizeof(c));
6855 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST |
6856 				  F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) |
6857 				  V_FW_PFVF_CMD_VFN(vf));
6858 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6859 	c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) |
6860 				     V_FW_PFVF_CMD_NIQ(rxq));
6861 	c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) |
6862 				    V_FW_PFVF_CMD_PMASK(pmask) |
6863 				    V_FW_PFVF_CMD_NEQ(txq));
6864 	c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) |
6865 				      V_FW_PFVF_CMD_NVI(vi) |
6866 				      V_FW_PFVF_CMD_NEXACTF(nexact));
6867 	c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) |
6868 				     V_FW_PFVF_CMD_WX_CAPS(wxcaps) |
6869 				     V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
6870 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6871 }
6872 
6873 /**
6874  *	t4_alloc_vi_func - allocate a virtual interface
6875  *	@adap: the adapter
6876  *	@mbox: mailbox to use for the FW command
6877  *	@port: physical port associated with the VI
6878  *	@pf: the PF owning the VI
6879  *	@vf: the VF owning the VI
6880  *	@nmac: number of MAC addresses needed (1 to 5)
6881  *	@mac: the MAC addresses of the VI
6882  *	@rss_size: size of RSS table slice associated with this VI
6883  *	@portfunc: which Port Application Function MAC Address is desired
6884  *	@idstype: Intrusion Detection Type
6885  *
6886  *	Allocates a virtual interface for the given physical port.  If @mac is
6887  *	not %NULL it contains the MAC addresses of the VI as assigned by FW.
6888  *	If @rss_size is %NULL the VI is not assigned any RSS slice by FW.
6889  *	@mac should be large enough to hold @nmac Ethernet addresses, they are
6890  *	stored consecutively so the space needed is @nmac * 6 bytes.
6891  *	Returns a negative error number or the non-negative VI id.
6892  */
6893 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
6894 		     unsigned int port, unsigned int pf, unsigned int vf,
6895 		     unsigned int nmac, u8 *mac, u16 *rss_size,
6896 		     unsigned int portfunc, unsigned int idstype)
6897 {
6898 	int ret;
6899 	struct fw_vi_cmd c;
6900 
6901 	memset(&c, 0, sizeof(c));
6902 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST |
6903 				  F_FW_CMD_WRITE | F_FW_CMD_EXEC |
6904 				  V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf));
6905 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c));
6906 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) |
6907 				     V_FW_VI_CMD_FUNC(portfunc));
6908 	c.portid_pkd = V_FW_VI_CMD_PORTID(port);
6909 	c.nmac = nmac - 1;
6910 	if(!rss_size)
6911 		c.norss_rsssize = F_FW_VI_CMD_NORSS;
6912 
6913 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6914 	if (ret)
6915 		return ret;
6916 
6917 	if (mac) {
6918 		memcpy(mac, c.mac, sizeof(c.mac));
6919 		switch (nmac) {
6920 		case 5:
6921 			memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6922 		case 4:
6923 			memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6924 		case 3:
6925 			memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6926 		case 2:
6927 			memcpy(mac + 6,  c.nmac0, sizeof(c.nmac0));
6928 		}
6929 	}
6930 	if (rss_size)
6931 		*rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize));
6932 	return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid));
6933 }
6934 
6935 /**
6936  *      t4_alloc_vi - allocate an [Ethernet Function] virtual interface
6937  *      @adap: the adapter
6938  *      @mbox: mailbox to use for the FW command
6939  *      @port: physical port associated with the VI
6940  *      @pf: the PF owning the VI
6941  *      @vf: the VF owning the VI
6942  *      @nmac: number of MAC addresses needed (1 to 5)
6943  *      @mac: the MAC addresses of the VI
6944  *      @rss_size: size of RSS table slice associated with this VI
6945  *
6946  *	backwards compatible and convieniance routine to allocate a Virtual
6947  *	Interface with a Ethernet Port Application Function and Intrustion
6948  *	Detection System disabled.
6949  */
6950 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6951 		unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6952 		u16 *rss_size)
6953 {
6954 	return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size,
6955 				FW_VI_FUNC_ETH, 0);
6956 }
6957 
6958 /**
6959  * 	t4_free_vi - free a virtual interface
6960  * 	@adap: the adapter
6961  * 	@mbox: mailbox to use for the FW command
6962  * 	@pf: the PF owning the VI
6963  * 	@vf: the VF owning the VI
6964  * 	@viid: virtual interface identifiler
6965  *
6966  * 	Free a previously allocated virtual interface.
6967  */
6968 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6969 	       unsigned int vf, unsigned int viid)
6970 {
6971 	struct fw_vi_cmd c;
6972 
6973 	memset(&c, 0, sizeof(c));
6974 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) |
6975 				  F_FW_CMD_REQUEST |
6976 				  F_FW_CMD_EXEC |
6977 				  V_FW_VI_CMD_PFN(pf) |
6978 				  V_FW_VI_CMD_VFN(vf));
6979 	c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c));
6980 	c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid));
6981 
6982 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6983 }
6984 
6985 /**
6986  *	t4_set_rxmode - set Rx properties of a virtual interface
6987  *	@adap: the adapter
6988  *	@mbox: mailbox to use for the FW command
6989  *	@viid: the VI id
6990  *	@mtu: the new MTU or -1
6991  *	@promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6992  *	@all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6993  *	@bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6994  *	@vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6995  *	@sleep_ok: if true we may sleep while awaiting command completion
6996  *
6997  *	Sets Rx properties of a virtual interface.
6998  */
6999 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7000 		  int mtu, int promisc, int all_multi, int bcast, int vlanex,
7001 		  bool sleep_ok)
7002 {
7003 	struct fw_vi_rxmode_cmd c;
7004 
7005 	/* convert to FW values */
7006 	if (mtu < 0)
7007 		mtu = M_FW_VI_RXMODE_CMD_MTU;
7008 	if (promisc < 0)
7009 		promisc = M_FW_VI_RXMODE_CMD_PROMISCEN;
7010 	if (all_multi < 0)
7011 		all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN;
7012 	if (bcast < 0)
7013 		bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN;
7014 	if (vlanex < 0)
7015 		vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN;
7016 
7017 	memset(&c, 0, sizeof(c));
7018 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) |
7019 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7020 				   V_FW_VI_RXMODE_CMD_VIID(viid));
7021 	c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7022 	c.mtu_to_vlanexen =
7023 		cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) |
7024 			    V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
7025 			    V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
7026 			    V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
7027 			    V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
7028 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7029 }
7030 
7031 /**
7032  *	t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7033  *	@adap: the adapter
7034  *	@mbox: mailbox to use for the FW command
7035  *	@viid: the VI id
7036  *	@free: if true any existing filters for this VI id are first removed
7037  *	@naddr: the number of MAC addresses to allocate filters for (up to 7)
7038  *	@addr: the MAC address(es)
7039  *	@idx: where to store the index of each allocated filter
7040  *	@hash: pointer to hash address filter bitmap
7041  *	@sleep_ok: call is allowed to sleep
7042  *
7043  *	Allocates an exact-match filter for each of the supplied addresses and
7044  *	sets it to the corresponding address.  If @idx is not %NULL it should
7045  *	have at least @naddr entries, each of which will be set to the index of
7046  *	the filter allocated for the corresponding MAC address.  If a filter
7047  *	could not be allocated for an address its index is set to 0xffff.
7048  *	If @hash is not %NULL addresses that fail to allocate an exact filter
7049  *	are hashed and update the hash filter bitmap pointed at by @hash.
7050  *
7051  *	Returns a negative error number or the number of filters allocated.
7052  */
7053 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7054 		      unsigned int viid, bool free, unsigned int naddr,
7055 		      const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7056 {
7057 	int offset, ret = 0;
7058 	struct fw_vi_mac_cmd c;
7059 	unsigned int nfilters = 0;
7060 	unsigned int max_naddr = adap->chip_params->mps_tcam_size;
7061 	unsigned int rem = naddr;
7062 
7063 	if (naddr > max_naddr)
7064 		return -EINVAL;
7065 
7066 	for (offset = 0; offset < naddr ; /**/) {
7067 		unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
7068 					 ? rem
7069 					 : ARRAY_SIZE(c.u.exact));
7070 		size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7071 						     u.exact[fw_naddr]), 16);
7072 		struct fw_vi_mac_exact *p;
7073 		int i;
7074 
7075 		memset(&c, 0, sizeof(c));
7076 		c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7077 					   F_FW_CMD_REQUEST |
7078 					   F_FW_CMD_WRITE |
7079 					   V_FW_CMD_EXEC(free) |
7080 					   V_FW_VI_MAC_CMD_VIID(viid));
7081 		c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) |
7082 						  V_FW_CMD_LEN16(len16));
7083 
7084 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7085 			p->valid_to_idx =
7086 				cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
7087 					    V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
7088 			memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
7089 		}
7090 
7091 		/*
7092 		 * It's okay if we run out of space in our MAC address arena.
7093 		 * Some of the addresses we submit may get stored so we need
7094 		 * to run through the reply to see what the results were ...
7095 		 */
7096 		ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7097 		if (ret && ret != -FW_ENOMEM)
7098 			break;
7099 
7100 		for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7101 			u16 index = G_FW_VI_MAC_CMD_IDX(
7102 						be16_to_cpu(p->valid_to_idx));
7103 
7104 			if (idx)
7105 				idx[offset+i] = (index >=  max_naddr
7106 						 ? 0xffff
7107 						 : index);
7108 			if (index < max_naddr)
7109 				nfilters++;
7110 			else if (hash)
7111 				*hash |= (1ULL << hash_mac_addr(addr[offset+i]));
7112 		}
7113 
7114 		free = false;
7115 		offset += fw_naddr;
7116 		rem -= fw_naddr;
7117 	}
7118 
7119 	if (ret == 0 || ret == -FW_ENOMEM)
7120 		ret = nfilters;
7121 	return ret;
7122 }
7123 
7124 /**
7125  *	t4_change_mac - modifies the exact-match filter for a MAC address
7126  *	@adap: the adapter
7127  *	@mbox: mailbox to use for the FW command
7128  *	@viid: the VI id
7129  *	@idx: index of existing filter for old value of MAC address, or -1
7130  *	@addr: the new MAC address value
7131  *	@persist: whether a new MAC allocation should be persistent
7132  *	@add_smt: if true also add the address to the HW SMT
7133  *
7134  *	Modifies an exact-match filter and sets it to the new MAC address if
7135  *	@idx >= 0, or adds the MAC address to a new filter if @idx < 0.  In the
7136  *	latter case the address is added persistently if @persist is %true.
7137  *
7138  *	Note that in general it is not possible to modify the value of a given
7139  *	filter so the generic way to modify an address filter is to free the one
7140  *	being used by the old address value and allocate a new filter for the
7141  *	new address value.
7142  *
7143  *	Returns a negative error number or the index of the filter with the new
7144  *	MAC value.  Note that this index may differ from @idx.
7145  */
7146 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
7147 		  int idx, const u8 *addr, bool persist, bool add_smt)
7148 {
7149 	int ret, mode;
7150 	struct fw_vi_mac_cmd c;
7151 	struct fw_vi_mac_exact *p = c.u.exact;
7152 	unsigned int max_mac_addr = adap->chip_params->mps_tcam_size;
7153 
7154 	if (idx < 0)		/* new allocation */
7155 		idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
7156 	mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
7157 
7158 	memset(&c, 0, sizeof(c));
7159 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7160 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7161 				   V_FW_VI_MAC_CMD_VIID(viid));
7162 	c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1));
7163 	p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID |
7164 				      V_FW_VI_MAC_CMD_SMAC_RESULT(mode) |
7165 				      V_FW_VI_MAC_CMD_IDX(idx));
7166 	memcpy(p->macaddr, addr, sizeof(p->macaddr));
7167 
7168 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7169 	if (ret == 0) {
7170 		ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx));
7171 		if (ret >= max_mac_addr)
7172 			ret = -ENOMEM;
7173 	}
7174 	return ret;
7175 }
7176 
7177 /**
7178  *	t4_set_addr_hash - program the MAC inexact-match hash filter
7179  *	@adap: the adapter
7180  *	@mbox: mailbox to use for the FW command
7181  *	@viid: the VI id
7182  *	@ucast: whether the hash filter should also match unicast addresses
7183  *	@vec: the value to be written to the hash filter
7184  *	@sleep_ok: call is allowed to sleep
7185  *
7186  *	Sets the 64-bit inexact-match hash filter for a virtual interface.
7187  */
7188 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
7189 		     bool ucast, u64 vec, bool sleep_ok)
7190 {
7191 	struct fw_vi_mac_cmd c;
7192 	u32 val;
7193 
7194 	memset(&c, 0, sizeof(c));
7195 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) |
7196 				   F_FW_CMD_REQUEST | F_FW_CMD_WRITE |
7197 				   V_FW_VI_ENABLE_CMD_VIID(viid));
7198 	val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) |
7199 	      V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1);
7200 	c.freemacs_to_len16 = cpu_to_be32(val);
7201 	c.u.hash.hashvec = cpu_to_be64(vec);
7202 	return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7203 }
7204 
7205 /**
7206  *      t4_enable_vi_params - enable/disable a virtual interface
7207  *      @adap: the adapter
7208  *      @mbox: mailbox to use for the FW command
7209  *      @viid: the VI id
7210  *      @rx_en: 1=enable Rx, 0=disable Rx
7211  *      @tx_en: 1=enable Tx, 0=disable Tx
7212  *      @dcb_en: 1=enable delivery of Data Center Bridging messages.
7213  *
7214  *      Enables/disables a virtual interface.  Note that setting DCB Enable
7215  *      only makes sense when enabling a Virtual Interface ...
7216  */
7217 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
7218 			unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
7219 {
7220 	struct fw_vi_enable_cmd c;
7221 
7222 	memset(&c, 0, sizeof(c));
7223 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7224 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7225 				   V_FW_VI_ENABLE_CMD_VIID(viid));
7226 	c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) |
7227 				     V_FW_VI_ENABLE_CMD_EEN(tx_en) |
7228 				     V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) |
7229 				     FW_LEN16(c));
7230 	return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
7231 }
7232 
7233 /**
7234  *	t4_enable_vi - enable/disable a virtual interface
7235  *	@adap: the adapter
7236  *	@mbox: mailbox to use for the FW command
7237  *	@viid: the VI id
7238  *	@rx_en: 1=enable Rx, 0=disable Rx
7239  *	@tx_en: 1=enable Tx, 0=disable Tx
7240  *
7241  *	Enables/disables a virtual interface.  Note that setting DCB Enable
7242  *	only makes sense when enabling a Virtual Interface ...
7243  */
7244 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
7245 		 bool rx_en, bool tx_en)
7246 {
7247 	return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
7248 }
7249 
7250 /**
7251  *	t4_identify_port - identify a VI's port by blinking its LED
7252  *	@adap: the adapter
7253  *	@mbox: mailbox to use for the FW command
7254  *	@viid: the VI id
7255  *	@nblinks: how many times to blink LED at 2.5 Hz
7256  *
7257  *	Identifies a VI's port by blinking its LED.
7258  */
7259 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
7260 		     unsigned int nblinks)
7261 {
7262 	struct fw_vi_enable_cmd c;
7263 
7264 	memset(&c, 0, sizeof(c));
7265 	c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) |
7266 				   F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7267 				   V_FW_VI_ENABLE_CMD_VIID(viid));
7268 	c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
7269 	c.blinkdur = cpu_to_be16(nblinks);
7270 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7271 }
7272 
7273 /**
7274  *	t4_iq_stop - stop an ingress queue and its FLs
7275  *	@adap: the adapter
7276  *	@mbox: mailbox to use for the FW command
7277  *	@pf: the PF owning the queues
7278  *	@vf: the VF owning the queues
7279  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7280  *	@iqid: ingress queue id
7281  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
7282  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
7283  *
7284  *	Stops an ingress queue and its associated FLs, if any.  This causes
7285  *	any current or future data/messages destined for these queues to be
7286  *	tossed.
7287  */
7288 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
7289 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
7290 	       unsigned int fl0id, unsigned int fl1id)
7291 {
7292 	struct fw_iq_cmd c;
7293 
7294 	memset(&c, 0, sizeof(c));
7295 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7296 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7297 				  V_FW_IQ_CMD_VFN(vf));
7298 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c));
7299 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7300 	c.iqid = cpu_to_be16(iqid);
7301 	c.fl0id = cpu_to_be16(fl0id);
7302 	c.fl1id = cpu_to_be16(fl1id);
7303 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7304 }
7305 
7306 /**
7307  *	t4_iq_free - free an ingress queue and its FLs
7308  *	@adap: the adapter
7309  *	@mbox: mailbox to use for the FW command
7310  *	@pf: the PF owning the queues
7311  *	@vf: the VF owning the queues
7312  *	@iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
7313  *	@iqid: ingress queue id
7314  *	@fl0id: FL0 queue id or 0xffff if no attached FL0
7315  *	@fl1id: FL1 queue id or 0xffff if no attached FL1
7316  *
7317  *	Frees an ingress queue and its associated FLs, if any.
7318  */
7319 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7320 	       unsigned int vf, unsigned int iqtype, unsigned int iqid,
7321 	       unsigned int fl0id, unsigned int fl1id)
7322 {
7323 	struct fw_iq_cmd c;
7324 
7325 	memset(&c, 0, sizeof(c));
7326 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
7327 				  F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) |
7328 				  V_FW_IQ_CMD_VFN(vf));
7329 	c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c));
7330 	c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype));
7331 	c.iqid = cpu_to_be16(iqid);
7332 	c.fl0id = cpu_to_be16(fl0id);
7333 	c.fl1id = cpu_to_be16(fl1id);
7334 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7335 }
7336 
7337 /**
7338  *	t4_eth_eq_free - free an Ethernet egress queue
7339  *	@adap: the adapter
7340  *	@mbox: mailbox to use for the FW command
7341  *	@pf: the PF owning the queue
7342  *	@vf: the VF owning the queue
7343  *	@eqid: egress queue id
7344  *
7345  *	Frees an Ethernet egress queue.
7346  */
7347 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7348 		   unsigned int vf, unsigned int eqid)
7349 {
7350 	struct fw_eq_eth_cmd c;
7351 
7352 	memset(&c, 0, sizeof(c));
7353 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) |
7354 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7355 				  V_FW_EQ_ETH_CMD_PFN(pf) |
7356 				  V_FW_EQ_ETH_CMD_VFN(vf));
7357 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
7358 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid));
7359 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7360 }
7361 
7362 /**
7363  *	t4_ctrl_eq_free - free a control egress queue
7364  *	@adap: the adapter
7365  *	@mbox: mailbox to use for the FW command
7366  *	@pf: the PF owning the queue
7367  *	@vf: the VF owning the queue
7368  *	@eqid: egress queue id
7369  *
7370  *	Frees a control egress queue.
7371  */
7372 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7373 		    unsigned int vf, unsigned int eqid)
7374 {
7375 	struct fw_eq_ctrl_cmd c;
7376 
7377 	memset(&c, 0, sizeof(c));
7378 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) |
7379 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7380 				  V_FW_EQ_CTRL_CMD_PFN(pf) |
7381 				  V_FW_EQ_CTRL_CMD_VFN(vf));
7382 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
7383 	c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid));
7384 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7385 }
7386 
7387 /**
7388  *	t4_ofld_eq_free - free an offload egress queue
7389  *	@adap: the adapter
7390  *	@mbox: mailbox to use for the FW command
7391  *	@pf: the PF owning the queue
7392  *	@vf: the VF owning the queue
7393  *	@eqid: egress queue id
7394  *
7395  *	Frees a control egress queue.
7396  */
7397 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7398 		    unsigned int vf, unsigned int eqid)
7399 {
7400 	struct fw_eq_ofld_cmd c;
7401 
7402 	memset(&c, 0, sizeof(c));
7403 	c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) |
7404 				  F_FW_CMD_REQUEST | F_FW_CMD_EXEC |
7405 				  V_FW_EQ_OFLD_CMD_PFN(pf) |
7406 				  V_FW_EQ_OFLD_CMD_VFN(vf));
7407 	c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
7408 	c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid));
7409 	return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7410 }
7411 
7412 /**
7413  *	t4_link_down_rc_str - return a string for a Link Down Reason Code
7414  *	@link_down_rc: Link Down Reason Code
7415  *
7416  *	Returns a string representation of the Link Down Reason Code.
7417  */
7418 const char *t4_link_down_rc_str(unsigned char link_down_rc)
7419 {
7420 	static const char *reason[] = {
7421 		"Link Down",
7422 		"Remote Fault",
7423 		"Auto-negotiation Failure",
7424 		"Reserved3",
7425 		"Insufficient Airflow",
7426 		"Unable To Determine Reason",
7427 		"No RX Signal Detected",
7428 		"Reserved7",
7429 	};
7430 
7431 	if (link_down_rc >= ARRAY_SIZE(reason))
7432 		return "Bad Reason Code";
7433 
7434 	return reason[link_down_rc];
7435 }
7436 
7437 /**
7438  *	t4_handle_fw_rpl - process a FW reply message
7439  *	@adap: the adapter
7440  *	@rpl: start of the FW message
7441  *
7442  *	Processes a FW message, such as link state change messages.
7443  */
7444 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7445 {
7446 	u8 opcode = *(const u8 *)rpl;
7447 	const struct fw_port_cmd *p = (const void *)rpl;
7448 	unsigned int action =
7449 			G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16));
7450 
7451 	if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) {
7452 		/* link/module state change message */
7453 		int speed = 0, fc = 0, i;
7454 		int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid));
7455 		struct port_info *pi = NULL;
7456 		struct link_config *lc;
7457 		u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7458 		int link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0;
7459 		u32 mod = G_FW_PORT_CMD_MODTYPE(stat);
7460 
7461 		if (stat & F_FW_PORT_CMD_RXPAUSE)
7462 			fc |= PAUSE_RX;
7463 		if (stat & F_FW_PORT_CMD_TXPAUSE)
7464 			fc |= PAUSE_TX;
7465 		if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
7466 			speed = 100;
7467 		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
7468 			speed = 1000;
7469 		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
7470 			speed = 10000;
7471 		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G))
7472 			speed = 25000;
7473 		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G))
7474 			speed = 40000;
7475 		else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G))
7476 			speed = 100000;
7477 
7478 		for_each_port(adap, i) {
7479 			pi = adap2pinfo(adap, i);
7480 			if (pi->tx_chan == chan)
7481 				break;
7482 		}
7483 		lc = &pi->link_cfg;
7484 
7485 		if (mod != pi->mod_type) {
7486 			pi->mod_type = mod;
7487 			t4_os_portmod_changed(adap, i);
7488 		}
7489 		if (link_ok != lc->link_ok || speed != lc->speed ||
7490 		    fc != lc->fc) {                    /* something changed */
7491 			int reason;
7492 
7493 			if (!link_ok && lc->link_ok)
7494 				reason = G_FW_PORT_CMD_LINKDNRC(stat);
7495 			else
7496 				reason = -1;
7497 
7498 			lc->link_ok = link_ok;
7499 			lc->speed = speed;
7500 			lc->fc = fc;
7501 			lc->supported = be16_to_cpu(p->u.info.pcap);
7502 			t4_os_link_changed(adap, i, link_ok, reason);
7503 		}
7504 	} else {
7505 		CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode);
7506 		return -EINVAL;
7507 	}
7508 	return 0;
7509 }
7510 
7511 /**
7512  *	get_pci_mode - determine a card's PCI mode
7513  *	@adapter: the adapter
7514  *	@p: where to store the PCI settings
7515  *
7516  *	Determines a card's PCI mode and associated parameters, such as speed
7517  *	and width.
7518  */
7519 static void get_pci_mode(struct adapter *adapter,
7520 				   struct pci_params *p)
7521 {
7522 	u16 val;
7523 	u32 pcie_cap;
7524 
7525 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7526 	if (pcie_cap) {
7527 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val);
7528 		p->speed = val & PCI_EXP_LNKSTA_CLS;
7529 		p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7530 	}
7531 }
7532 
7533 /**
7534  *	init_link_config - initialize a link's SW state
7535  *	@lc: structure holding the link state
7536  *	@caps: link capabilities
7537  *
7538  *	Initializes the SW state maintained for each link, including the link's
7539  *	capabilities and default speed/flow-control/autonegotiation settings.
7540  */
7541 static void init_link_config(struct link_config *lc, unsigned int caps)
7542 {
7543 	lc->supported = caps;
7544 	lc->requested_speed = 0;
7545 	lc->speed = 0;
7546 	lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7547 	if (lc->supported & FW_PORT_CAP_ANEG) {
7548 		lc->advertising = lc->supported & ADVERT_MASK;
7549 		lc->autoneg = AUTONEG_ENABLE;
7550 		lc->requested_fc |= PAUSE_AUTONEG;
7551 	} else {
7552 		lc->advertising = 0;
7553 		lc->autoneg = AUTONEG_DISABLE;
7554 	}
7555 }
7556 
7557 struct flash_desc {
7558 	u32 vendor_and_model_id;
7559 	u32 size_mb;
7560 };
7561 
7562 int t4_get_flash_params(struct adapter *adapter)
7563 {
7564 	/*
7565 	 * Table for non-Numonix supported flash parts.  Numonix parts are left
7566 	 * to the preexisting well-tested code.  All flash parts have 64KB
7567 	 * sectors.
7568 	 */
7569 	static struct flash_desc supported_flash[] = {
7570 		{ 0x150201, 4 << 20 },       /* Spansion 4MB S25FL032P */
7571 	};
7572 
7573 	int ret;
7574 	u32 info = 0;
7575 
7576 	ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID);
7577 	if (!ret)
7578 		ret = sf1_read(adapter, 3, 0, 1, &info);
7579 	t4_write_reg(adapter, A_SF_OP, 0);	/* unlock SF */
7580 	if (ret < 0)
7581 		return ret;
7582 
7583 	for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7584 		if (supported_flash[ret].vendor_and_model_id == info) {
7585 			adapter->params.sf_size = supported_flash[ret].size_mb;
7586 			adapter->params.sf_nsec =
7587 				adapter->params.sf_size / SF_SEC_SIZE;
7588 			return 0;
7589 		}
7590 
7591 	if ((info & 0xff) != 0x20)		/* not a Numonix flash */
7592 		return -EINVAL;
7593 	info >>= 16;				/* log2 of size */
7594 	if (info >= 0x14 && info < 0x18)
7595 		adapter->params.sf_nsec = 1 << (info - 16);
7596 	else if (info == 0x18)
7597 		adapter->params.sf_nsec = 64;
7598 	else
7599 		return -EINVAL;
7600 	adapter->params.sf_size = 1 << info;
7601 
7602 	/*
7603 	 * We should ~probably~ reject adapters with FLASHes which are too
7604 	 * small but we have some legacy FPGAs with small FLASHes that we'd
7605 	 * still like to use.  So instead we emit a scary message ...
7606 	 */
7607 	if (adapter->params.sf_size < FLASH_MIN_SIZE)
7608 		CH_WARN(adapter, "WARNING!!! FLASH size %#x < %#x!!!\n",
7609 			adapter->params.sf_size, FLASH_MIN_SIZE);
7610 
7611 	return 0;
7612 }
7613 
7614 static void set_pcie_completion_timeout(struct adapter *adapter,
7615 						  u8 range)
7616 {
7617 	u16 val;
7618 	u32 pcie_cap;
7619 
7620 	pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP);
7621 	if (pcie_cap) {
7622 		t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val);
7623 		val &= 0xfff0;
7624 		val |= range ;
7625 		t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val);
7626 	}
7627 }
7628 
7629 const struct chip_params *t4_get_chip_params(int chipid)
7630 {
7631 	static const struct chip_params chip_params[] = {
7632 		{
7633 			/* T4 */
7634 			.nchan = NCHAN,
7635 			.pm_stats_cnt = PM_NSTATS,
7636 			.cng_ch_bits_log = 2,
7637 			.nsched_cls = 15,
7638 			.cim_num_obq = CIM_NUM_OBQ,
7639 			.mps_rplc_size = 128,
7640 			.vfcount = 128,
7641 			.sge_fl_db = F_DBPRIO,
7642 			.mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES,
7643 		},
7644 		{
7645 			/* T5 */
7646 			.nchan = NCHAN,
7647 			.pm_stats_cnt = PM_NSTATS,
7648 			.cng_ch_bits_log = 2,
7649 			.nsched_cls = 16,
7650 			.cim_num_obq = CIM_NUM_OBQ_T5,
7651 			.mps_rplc_size = 128,
7652 			.vfcount = 128,
7653 			.sge_fl_db = F_DBPRIO | F_DBTYPE,
7654 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7655 		},
7656 		{
7657 			/* T6 */
7658 			.nchan = T6_NCHAN,
7659 			.pm_stats_cnt = T6_PM_NSTATS,
7660 			.cng_ch_bits_log = 3,
7661 			.nsched_cls = 16,
7662 			.cim_num_obq = CIM_NUM_OBQ_T5,
7663 			.mps_rplc_size = 256,
7664 			.vfcount = 256,
7665 			.sge_fl_db = 0,
7666 			.mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES,
7667 		},
7668 	};
7669 
7670 	chipid -= CHELSIO_T4;
7671 	if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params))
7672 		return NULL;
7673 
7674 	return &chip_params[chipid];
7675 }
7676 
7677 /**
7678  *	t4_prep_adapter - prepare SW and HW for operation
7679  *	@adapter: the adapter
7680  *	@buf: temporary space of at least VPD_LEN size provided by the caller.
7681  *
7682  *	Initialize adapter SW state for the various HW modules, set initial
7683  *	values for some adapter tunables, take PHYs out of reset, and
7684  *	initialize the MDIO interface.
7685  */
7686 int t4_prep_adapter(struct adapter *adapter, u8 *buf)
7687 {
7688 	int ret;
7689 	uint16_t device_id;
7690 	uint32_t pl_rev;
7691 
7692 	get_pci_mode(adapter, &adapter->params.pci);
7693 
7694 	pl_rev = t4_read_reg(adapter, A_PL_REV);
7695 	adapter->params.chipid = G_CHIPID(pl_rev);
7696 	adapter->params.rev = G_REV(pl_rev);
7697 	if (adapter->params.chipid == 0) {
7698 		/* T4 did not have chipid in PL_REV (T5 onwards do) */
7699 		adapter->params.chipid = CHELSIO_T4;
7700 
7701 		/* T4A1 chip is not supported */
7702 		if (adapter->params.rev == 1) {
7703 			CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n");
7704 			return -EINVAL;
7705 		}
7706 	}
7707 
7708 	adapter->chip_params = t4_get_chip_params(chip_id(adapter));
7709 	if (adapter->chip_params == NULL)
7710 		return -EINVAL;
7711 
7712 	adapter->params.pci.vpd_cap_addr =
7713 	    t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
7714 
7715 	ret = t4_get_flash_params(adapter);
7716 	if (ret < 0)
7717 		return ret;
7718 
7719 	ret = get_vpd_params(adapter, &adapter->params.vpd, buf);
7720 	if (ret < 0)
7721 		return ret;
7722 
7723 	/* Cards with real ASICs have the chipid in the PCIe device id */
7724 	t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id);
7725 	if (device_id >> 12 == chip_id(adapter))
7726 		adapter->params.cim_la_size = CIMLA_SIZE;
7727 	else {
7728 		/* FPGA */
7729 		adapter->params.fpga = 1;
7730 		adapter->params.cim_la_size = 2 * CIMLA_SIZE;
7731 	}
7732 
7733 	init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7734 
7735 	/*
7736 	 * Default port and clock for debugging in case we can't reach FW.
7737 	 */
7738 	adapter->params.nports = 1;
7739 	adapter->params.portvec = 1;
7740 	adapter->params.vpd.cclk = 50000;
7741 
7742 	/* Set pci completion timeout value to 4 seconds. */
7743 	set_pcie_completion_timeout(adapter, 0xd);
7744 	return 0;
7745 }
7746 
7747 /**
7748  *	t4_shutdown_adapter - shut down adapter, host & wire
7749  *	@adapter: the adapter
7750  *
7751  *	Perform an emergency shutdown of the adapter and stop it from
7752  *	continuing any further communication on the ports or DMA to the
7753  *	host.  This is typically used when the adapter and/or firmware
7754  *	have crashed and we want to prevent any further accidental
7755  *	communication with the rest of the world.  This will also force
7756  *	the port Link Status to go down -- if register writes work --
7757  *	which should help our peers figure out that we're down.
7758  */
7759 int t4_shutdown_adapter(struct adapter *adapter)
7760 {
7761 	int port;
7762 
7763 	t4_intr_disable(adapter);
7764 	t4_write_reg(adapter, A_DBG_GPIO_EN, 0);
7765 	for_each_port(adapter, port) {
7766 		u32 a_port_cfg = PORT_REG(port,
7767 					  is_t4(adapter)
7768 					  ? A_XGMAC_PORT_CFG
7769 					  : A_MAC_PORT_CFG);
7770 
7771 		t4_write_reg(adapter, a_port_cfg,
7772 			     t4_read_reg(adapter, a_port_cfg)
7773 			     & ~V_SIGNAL_DET(1));
7774 	}
7775 	t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0);
7776 
7777 	return 0;
7778 }
7779 
7780 /**
7781  *	t4_init_devlog_params - initialize adapter->params.devlog
7782  *	@adap: the adapter
7783  *	@fw_attach: whether we can talk to the firmware
7784  *
7785  *	Initialize various fields of the adapter's Firmware Device Log
7786  *	Parameters structure.
7787  */
7788 int t4_init_devlog_params(struct adapter *adap, int fw_attach)
7789 {
7790 	struct devlog_params *dparams = &adap->params.devlog;
7791 	u32 pf_dparams;
7792 	unsigned int devlog_meminfo;
7793 	struct fw_devlog_cmd devlog_cmd;
7794 	int ret;
7795 
7796 	/* If we're dealing with newer firmware, the Device Log Paramerters
7797 	 * are stored in a designated register which allows us to access the
7798 	 * Device Log even if we can't talk to the firmware.
7799 	 */
7800 	pf_dparams =
7801 		t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG));
7802 	if (pf_dparams) {
7803 		unsigned int nentries, nentries128;
7804 
7805 		dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams);
7806 		dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4;
7807 
7808 		nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams);
7809 		nentries = (nentries128 + 1) * 128;
7810 		dparams->size = nentries * sizeof(struct fw_devlog_e);
7811 
7812 		return 0;
7813 	}
7814 
7815 	/*
7816 	 * For any failing returns ...
7817 	 */
7818 	memset(dparams, 0, sizeof *dparams);
7819 
7820 	/*
7821 	 * If we can't talk to the firmware, there's really nothing we can do
7822 	 * at this point.
7823 	 */
7824 	if (!fw_attach)
7825 		return -ENXIO;
7826 
7827 	/* Otherwise, ask the firmware for it's Device Log Parameters.
7828 	 */
7829 	memset(&devlog_cmd, 0, sizeof devlog_cmd);
7830 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
7831 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
7832 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7833 	ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7834 			 &devlog_cmd);
7835 	if (ret)
7836 		return ret;
7837 
7838 	devlog_meminfo =
7839 		be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7840 	dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo);
7841 	dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4;
7842 	dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7843 
7844 	return 0;
7845 }
7846 
7847 /**
7848  *	t4_init_sge_params - initialize adap->params.sge
7849  *	@adapter: the adapter
7850  *
7851  *	Initialize various fields of the adapter's SGE Parameters structure.
7852  */
7853 int t4_init_sge_params(struct adapter *adapter)
7854 {
7855 	u32 r;
7856 	struct sge_params *sp = &adapter->params.sge;
7857 	unsigned i;
7858 
7859 	r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD);
7860 	sp->counter_val[0] = G_THRESHOLD_0(r);
7861 	sp->counter_val[1] = G_THRESHOLD_1(r);
7862 	sp->counter_val[2] = G_THRESHOLD_2(r);
7863 	sp->counter_val[3] = G_THRESHOLD_3(r);
7864 
7865 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1);
7866 	sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r));
7867 	sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r));
7868 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3);
7869 	sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r));
7870 	sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r));
7871 	r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5);
7872 	sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r));
7873 	sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r));
7874 
7875 	r = t4_read_reg(adapter, A_SGE_CONM_CTRL);
7876 	sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
7877 	if (is_t4(adapter))
7878 		sp->fl_starve_threshold2 = sp->fl_starve_threshold;
7879 	else if (is_t5(adapter))
7880 		sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
7881 	else
7882 		sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1;
7883 
7884 	/* egress queues: log2 of # of doorbells per BAR2 page */
7885 	r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
7886 	r >>= S_QUEUESPERPAGEPF0 +
7887 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7888 	sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
7889 
7890 	/* ingress queues: log2 of # of doorbells per BAR2 page */
7891 	r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
7892 	r >>= S_QUEUESPERPAGEPF0 +
7893 	    (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf;
7894 	sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
7895 
7896 	r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE);
7897 	r >>= S_HOSTPAGESIZEPF0 +
7898 	    (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf;
7899 	sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10;
7900 
7901 	r = t4_read_reg(adapter, A_SGE_CONTROL);
7902 	sp->sge_control = r;
7903 	sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64;
7904 	sp->fl_pktshift = G_PKTSHIFT(r);
7905 	if (chip_id(adapter) <= CHELSIO_T5) {
7906 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
7907 		    X_INGPADBOUNDARY_SHIFT);
7908 	} else {
7909 		sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) +
7910 		    X_T6_INGPADBOUNDARY_SHIFT);
7911 	}
7912 	if (is_t4(adapter))
7913 		sp->pack_boundary = sp->pad_boundary;
7914 	else {
7915 		r = t4_read_reg(adapter, A_SGE_CONTROL2);
7916 		if (G_INGPACKBOUNDARY(r) == 0)
7917 			sp->pack_boundary = 16;
7918 		else
7919 			sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
7920 	}
7921 	for (i = 0; i < SGE_FLBUF_SIZES; i++)
7922 		sp->sge_fl_buffer_size[i] = t4_read_reg(adapter,
7923 		    A_SGE_FL_BUFFER_SIZE0 + (4 * i));
7924 
7925 	return 0;
7926 }
7927 
7928 /*
7929  * Read and cache the adapter's compressed filter mode and ingress config.
7930  */
7931 static void read_filter_mode_and_ingress_config(struct adapter *adap)
7932 {
7933 	struct tp_params *tpp = &adap->params.tp;
7934 
7935 	if (t4_use_ldst(adap)) {
7936 		t4_fw_tp_pio_rw(adap, &tpp->vlan_pri_map, 1,
7937 				A_TP_VLAN_PRI_MAP, 1);
7938 		t4_fw_tp_pio_rw(adap, &tpp->ingress_config, 1,
7939 				A_TP_INGRESS_CONFIG, 1);
7940 	} else {
7941 		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7942 				 &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP);
7943 		t4_read_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA,
7944 				 &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG);
7945 	}
7946 
7947 	/*
7948 	 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7949 	 * shift positions of several elements of the Compressed Filter Tuple
7950 	 * for this adapter which we need frequently ...
7951 	 */
7952 	tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE);
7953 	tpp->port_shift = t4_filter_field_shift(adap, F_PORT);
7954 	tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID);
7955 	tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN);
7956 	tpp->tos_shift = t4_filter_field_shift(adap, F_TOS);
7957 	tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL);
7958 	tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE);
7959 	tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH);
7960 	tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE);
7961 	tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION);
7962 
7963 	/*
7964 	 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7965 	 * represents the presence of an Outer VLAN instead of a VNIC ID.
7966 	 */
7967 	if ((tpp->ingress_config & F_VNIC) == 0)
7968 		tpp->vnic_shift = -1;
7969 }
7970 
7971 /**
7972  *      t4_init_tp_params - initialize adap->params.tp
7973  *      @adap: the adapter
7974  *
7975  *      Initialize various fields of the adapter's TP Parameters structure.
7976  */
7977 int t4_init_tp_params(struct adapter *adap)
7978 {
7979 	int chan;
7980 	u32 v;
7981 	struct tp_params *tpp = &adap->params.tp;
7982 
7983 	v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION);
7984 	tpp->tre = G_TIMERRESOLUTION(v);
7985 	tpp->dack_re = G_DELAYEDACKRESOLUTION(v);
7986 
7987 	/* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7988 	for (chan = 0; chan < MAX_NCHAN; chan++)
7989 		tpp->tx_modq[chan] = chan;
7990 
7991 	read_filter_mode_and_ingress_config(adap);
7992 
7993 	/*
7994 	 * For T6, cache the adapter's compressed error vector
7995 	 * and passing outer header info for encapsulated packets.
7996 	 */
7997 	if (chip_id(adap) > CHELSIO_T5) {
7998 		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
7999 		tpp->rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
8000 	}
8001 
8002 	return 0;
8003 }
8004 
8005 /**
8006  *      t4_filter_field_shift - calculate filter field shift
8007  *      @adap: the adapter
8008  *      @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
8009  *
8010  *      Return the shift position of a filter field within the Compressed
8011  *      Filter Tuple.  The filter field is specified via its selection bit
8012  *      within TP_VLAN_PRI_MAL (filter mode).  E.g. F_VLAN.
8013  */
8014 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
8015 {
8016 	unsigned int filter_mode = adap->params.tp.vlan_pri_map;
8017 	unsigned int sel;
8018 	int field_shift;
8019 
8020 	if ((filter_mode & filter_sel) == 0)
8021 		return -1;
8022 
8023 	for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
8024 		switch (filter_mode & sel) {
8025 		case F_FCOE:
8026 			field_shift += W_FT_FCOE;
8027 			break;
8028 		case F_PORT:
8029 			field_shift += W_FT_PORT;
8030 			break;
8031 		case F_VNIC_ID:
8032 			field_shift += W_FT_VNIC_ID;
8033 			break;
8034 		case F_VLAN:
8035 			field_shift += W_FT_VLAN;
8036 			break;
8037 		case F_TOS:
8038 			field_shift += W_FT_TOS;
8039 			break;
8040 		case F_PROTOCOL:
8041 			field_shift += W_FT_PROTOCOL;
8042 			break;
8043 		case F_ETHERTYPE:
8044 			field_shift += W_FT_ETHERTYPE;
8045 			break;
8046 		case F_MACMATCH:
8047 			field_shift += W_FT_MACMATCH;
8048 			break;
8049 		case F_MPSHITTYPE:
8050 			field_shift += W_FT_MPSHITTYPE;
8051 			break;
8052 		case F_FRAGMENTATION:
8053 			field_shift += W_FT_FRAGMENTATION;
8054 			break;
8055 		}
8056 	}
8057 	return field_shift;
8058 }
8059 
8060 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id)
8061 {
8062 	u8 addr[6];
8063 	int ret, i, j;
8064 	struct fw_port_cmd c;
8065 	u16 rss_size;
8066 	struct port_info *p = adap2pinfo(adap, port_id);
8067 	u32 param, val;
8068 
8069 	memset(&c, 0, sizeof(c));
8070 
8071 	for (i = 0, j = -1; i <= p->port_id; i++) {
8072 		do {
8073 			j++;
8074 		} while ((adap->params.portvec & (1 << j)) == 0);
8075 	}
8076 
8077 	if (!(adap->flags & IS_VF) ||
8078 	    adap->params.vfres.r_caps & FW_CMD_CAP_PORT) {
8079 		c.op_to_portid = htonl(V_FW_CMD_OP(FW_PORT_CMD) |
8080 				       F_FW_CMD_REQUEST | F_FW_CMD_READ |
8081 				       V_FW_PORT_CMD_PORTID(j));
8082 		c.action_to_len16 = htonl(
8083 			V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
8084 			FW_LEN16(c));
8085 		ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8086 		if (ret)
8087 			return ret;
8088 
8089 		ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
8090 		p->mdio_addr = (ret & F_FW_PORT_CMD_MDIOCAP) ?
8091 			G_FW_PORT_CMD_MDIOADDR(ret) : -1;
8092 		p->port_type = G_FW_PORT_CMD_PTYPE(ret);
8093 		p->mod_type = G_FW_PORT_CMD_MODTYPE(ret);
8094 
8095 		init_link_config(&p->link_cfg, be16_to_cpu(c.u.info.pcap));
8096 	}
8097 
8098 	ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
8099 	if (ret < 0)
8100 		return ret;
8101 
8102 	p->vi[0].viid = ret;
8103 	if (chip_id(adap) <= CHELSIO_T5)
8104 		p->vi[0].smt_idx = (ret & 0x7f) << 1;
8105 	else
8106 		p->vi[0].smt_idx = (ret & 0x7f);
8107 	p->tx_chan = j;
8108 	p->rx_chan_map = t4_get_mps_bg_map(adap, j);
8109 	p->lport = j;
8110 	p->vi[0].rss_size = rss_size;
8111 	t4_os_set_hw_addr(adap, p->port_id, addr);
8112 
8113 	param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8114 	    V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
8115 	    V_FW_PARAMS_PARAM_YZ(p->vi[0].viid);
8116 	ret = t4_query_params(adap, mbox, pf, vf, 1, &param, &val);
8117 	if (ret)
8118 		p->vi[0].rss_base = 0xffff;
8119 	else {
8120 		/* MPASS((val >> 16) == rss_size); */
8121 		p->vi[0].rss_base = val & 0xffff;
8122 	}
8123 
8124 	return 0;
8125 }
8126 
8127 /**
8128  *	t4_read_cimq_cfg - read CIM queue configuration
8129  *	@adap: the adapter
8130  *	@base: holds the queue base addresses in bytes
8131  *	@size: holds the queue sizes in bytes
8132  *	@thres: holds the queue full thresholds in bytes
8133  *
8134  *	Returns the current configuration of the CIM queues, starting with
8135  *	the IBQs, then the OBQs.
8136  */
8137 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
8138 {
8139 	unsigned int i, v;
8140 	int cim_num_obq = adap->chip_params->cim_num_obq;
8141 
8142 	for (i = 0; i < CIM_NUM_IBQ; i++) {
8143 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT |
8144 			     V_QUENUMSELECT(i));
8145 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8146 		/* value is in 256-byte units */
8147 		*base++ = G_CIMQBASE(v) * 256;
8148 		*size++ = G_CIMQSIZE(v) * 256;
8149 		*thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */
8150 	}
8151 	for (i = 0; i < cim_num_obq; i++) {
8152 		t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8153 			     V_QUENUMSELECT(i));
8154 		v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8155 		/* value is in 256-byte units */
8156 		*base++ = G_CIMQBASE(v) * 256;
8157 		*size++ = G_CIMQSIZE(v) * 256;
8158 	}
8159 }
8160 
8161 /**
8162  *	t4_read_cim_ibq - read the contents of a CIM inbound queue
8163  *	@adap: the adapter
8164  *	@qid: the queue index
8165  *	@data: where to store the queue contents
8166  *	@n: capacity of @data in 32-bit words
8167  *
8168  *	Reads the contents of the selected CIM queue starting at address 0 up
8169  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8170  *	error and the number of 32-bit words actually read on success.
8171  */
8172 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8173 {
8174 	int i, err, attempts;
8175 	unsigned int addr;
8176 	const unsigned int nwords = CIM_IBQ_SIZE * 4;
8177 
8178 	if (qid > 5 || (n & 3))
8179 		return -EINVAL;
8180 
8181 	addr = qid * nwords;
8182 	if (n > nwords)
8183 		n = nwords;
8184 
8185 	/* It might take 3-10ms before the IBQ debug read access is allowed.
8186 	 * Wait for 1 Sec with a delay of 1 usec.
8187 	 */
8188 	attempts = 1000000;
8189 
8190 	for (i = 0; i < n; i++, addr++) {
8191 		t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) |
8192 			     F_IBQDBGEN);
8193 		err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0,
8194 				      attempts, 1);
8195 		if (err)
8196 			return err;
8197 		*data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA);
8198 	}
8199 	t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0);
8200 	return i;
8201 }
8202 
8203 /**
8204  *	t4_read_cim_obq - read the contents of a CIM outbound queue
8205  *	@adap: the adapter
8206  *	@qid: the queue index
8207  *	@data: where to store the queue contents
8208  *	@n: capacity of @data in 32-bit words
8209  *
8210  *	Reads the contents of the selected CIM queue starting at address 0 up
8211  *	to the capacity of @data.  @n must be a multiple of 4.  Returns < 0 on
8212  *	error and the number of 32-bit words actually read on success.
8213  */
8214 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
8215 {
8216 	int i, err;
8217 	unsigned int addr, v, nwords;
8218 	int cim_num_obq = adap->chip_params->cim_num_obq;
8219 
8220 	if ((qid > (cim_num_obq - 1)) || (n & 3))
8221 		return -EINVAL;
8222 
8223 	t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT |
8224 		     V_QUENUMSELECT(qid));
8225 	v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL);
8226 
8227 	addr = G_CIMQBASE(v) * 64;    /* muliple of 256 -> muliple of 4 */
8228 	nwords = G_CIMQSIZE(v) * 64;  /* same */
8229 	if (n > nwords)
8230 		n = nwords;
8231 
8232 	for (i = 0; i < n; i++, addr++) {
8233 		t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) |
8234 			     F_OBQDBGEN);
8235 		err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0,
8236 				      2, 1);
8237 		if (err)
8238 			return err;
8239 		*data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA);
8240 	}
8241 	t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0);
8242 	return i;
8243 }
8244 
8245 enum {
8246 	CIM_QCTL_BASE     = 0,
8247 	CIM_CTL_BASE      = 0x2000,
8248 	CIM_PBT_ADDR_BASE = 0x2800,
8249 	CIM_PBT_LRF_BASE  = 0x3000,
8250 	CIM_PBT_DATA_BASE = 0x3800
8251 };
8252 
8253 /**
8254  *	t4_cim_read - read a block from CIM internal address space
8255  *	@adap: the adapter
8256  *	@addr: the start address within the CIM address space
8257  *	@n: number of words to read
8258  *	@valp: where to store the result
8259  *
8260  *	Reads a block of 4-byte words from the CIM intenal address space.
8261  */
8262 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
8263 		unsigned int *valp)
8264 {
8265 	int ret = 0;
8266 
8267 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8268 		return -EBUSY;
8269 
8270 	for ( ; !ret && n--; addr += 4) {
8271 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr);
8272 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8273 				      0, 5, 2);
8274 		if (!ret)
8275 			*valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA);
8276 	}
8277 	return ret;
8278 }
8279 
8280 /**
8281  *	t4_cim_write - write a block into CIM internal address space
8282  *	@adap: the adapter
8283  *	@addr: the start address within the CIM address space
8284  *	@n: number of words to write
8285  *	@valp: set of values to write
8286  *
8287  *	Writes a block of 4-byte words into the CIM intenal address space.
8288  */
8289 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
8290 		 const unsigned int *valp)
8291 {
8292 	int ret = 0;
8293 
8294 	if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
8295 		return -EBUSY;
8296 
8297 	for ( ; !ret && n--; addr += 4) {
8298 		t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++);
8299 		t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE);
8300 		ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
8301 				      0, 5, 2);
8302 	}
8303 	return ret;
8304 }
8305 
8306 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
8307 			 unsigned int val)
8308 {
8309 	return t4_cim_write(adap, addr, 1, &val);
8310 }
8311 
8312 /**
8313  *	t4_cim_ctl_read - read a block from CIM control region
8314  *	@adap: the adapter
8315  *	@addr: the start address within the CIM control region
8316  *	@n: number of words to read
8317  *	@valp: where to store the result
8318  *
8319  *	Reads a block of 4-byte words from the CIM control region.
8320  */
8321 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
8322 		    unsigned int *valp)
8323 {
8324 	return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp);
8325 }
8326 
8327 /**
8328  *	t4_cim_read_la - read CIM LA capture buffer
8329  *	@adap: the adapter
8330  *	@la_buf: where to store the LA data
8331  *	@wrptr: the HW write pointer within the capture buffer
8332  *
8333  *	Reads the contents of the CIM LA buffer with the most recent entry at
8334  *	the end	of the returned data and with the entry at @wrptr first.
8335  *	We try to leave the LA in the running state we find it in.
8336  */
8337 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
8338 {
8339 	int i, ret;
8340 	unsigned int cfg, val, idx;
8341 
8342 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg);
8343 	if (ret)
8344 		return ret;
8345 
8346 	if (cfg & F_UPDBGLAEN) {	/* LA is running, freeze it */
8347 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0);
8348 		if (ret)
8349 			return ret;
8350 	}
8351 
8352 	ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8353 	if (ret)
8354 		goto restart;
8355 
8356 	idx = G_UPDBGLAWRPTR(val);
8357 	if (wrptr)
8358 		*wrptr = idx;
8359 
8360 	for (i = 0; i < adap->params.cim_la_size; i++) {
8361 		ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8362 				    V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN);
8363 		if (ret)
8364 			break;
8365 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val);
8366 		if (ret)
8367 			break;
8368 		if (val & F_UPDBGLARDEN) {
8369 			ret = -ETIMEDOUT;
8370 			break;
8371 		}
8372 		ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]);
8373 		if (ret)
8374 			break;
8375 
8376 		/* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */
8377 		idx = (idx + 1) & M_UPDBGLARDPTR;
8378 		/*
8379 		 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
8380 		 * identify the 32-bit portion of the full 312-bit data
8381 		 */
8382 		if (is_t6(adap))
8383 			while ((idx & 0xf) > 9)
8384 				idx = (idx + 1) % M_UPDBGLARDPTR;
8385 	}
8386 restart:
8387 	if (cfg & F_UPDBGLAEN) {
8388 		int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG,
8389 				      cfg & ~F_UPDBGLARDEN);
8390 		if (!ret)
8391 			ret = r;
8392 	}
8393 	return ret;
8394 }
8395 
8396 /**
8397  *	t4_tp_read_la - read TP LA capture buffer
8398  *	@adap: the adapter
8399  *	@la_buf: where to store the LA data
8400  *	@wrptr: the HW write pointer within the capture buffer
8401  *
8402  *	Reads the contents of the TP LA buffer with the most recent entry at
8403  *	the end	of the returned data and with the entry at @wrptr first.
8404  *	We leave the LA in the running state we find it in.
8405  */
8406 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
8407 {
8408 	bool last_incomplete;
8409 	unsigned int i, cfg, val, idx;
8410 
8411 	cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff;
8412 	if (cfg & F_DBGLAENABLE)			/* freeze LA */
8413 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8414 			     adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE));
8415 
8416 	val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG);
8417 	idx = G_DBGLAWPTR(val);
8418 	last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0;
8419 	if (last_incomplete)
8420 		idx = (idx + 1) & M_DBGLARPTR;
8421 	if (wrptr)
8422 		*wrptr = idx;
8423 
8424 	val &= 0xffff;
8425 	val &= ~V_DBGLARPTR(M_DBGLARPTR);
8426 	val |= adap->params.tp.la_mask;
8427 
8428 	for (i = 0; i < TPLA_SIZE; i++) {
8429 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val);
8430 		la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL);
8431 		idx = (idx + 1) & M_DBGLARPTR;
8432 	}
8433 
8434 	/* Wipe out last entry if it isn't valid */
8435 	if (last_incomplete)
8436 		la_buf[TPLA_SIZE - 1] = ~0ULL;
8437 
8438 	if (cfg & F_DBGLAENABLE)		/* restore running state */
8439 		t4_write_reg(adap, A_TP_DBG_LA_CONFIG,
8440 			     cfg | adap->params.tp.la_mask);
8441 }
8442 
8443 /*
8444  * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8445  * seconds).  If we find one of the SGE Ingress DMA State Machines in the same
8446  * state for more than the Warning Threshold then we'll issue a warning about
8447  * a potential hang.  We'll repeat the warning as the SGE Ingress DMA Channel
8448  * appears to be hung every Warning Repeat second till the situation clears.
8449  * If the situation clears, we'll note that as well.
8450  */
8451 #define SGE_IDMA_WARN_THRESH 1
8452 #define SGE_IDMA_WARN_REPEAT 300
8453 
8454 /**
8455  *	t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8456  *	@adapter: the adapter
8457  *	@idma: the adapter IDMA Monitor state
8458  *
8459  *	Initialize the state of an SGE Ingress DMA Monitor.
8460  */
8461 void t4_idma_monitor_init(struct adapter *adapter,
8462 			  struct sge_idma_monitor_state *idma)
8463 {
8464 	/* Initialize the state variables for detecting an SGE Ingress DMA
8465 	 * hang.  The SGE has internal counters which count up on each clock
8466 	 * tick whenever the SGE finds its Ingress DMA State Engines in the
8467 	 * same state they were on the previous clock tick.  The clock used is
8468 	 * the Core Clock so we have a limit on the maximum "time" they can
8469 	 * record; typically a very small number of seconds.  For instance,
8470 	 * with a 600MHz Core Clock, we can only count up to a bit more than
8471 	 * 7s.  So we'll synthesize a larger counter in order to not run the
8472 	 * risk of having the "timers" overflow and give us the flexibility to
8473 	 * maintain a Hung SGE State Machine of our own which operates across
8474 	 * a longer time frame.
8475 	 */
8476 	idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8477 	idma->idma_stalled[0] = idma->idma_stalled[1] = 0;
8478 }
8479 
8480 /**
8481  *	t4_idma_monitor - monitor SGE Ingress DMA state
8482  *	@adapter: the adapter
8483  *	@idma: the adapter IDMA Monitor state
8484  *	@hz: number of ticks/second
8485  *	@ticks: number of ticks since the last IDMA Monitor call
8486  */
8487 void t4_idma_monitor(struct adapter *adapter,
8488 		     struct sge_idma_monitor_state *idma,
8489 		     int hz, int ticks)
8490 {
8491 	int i, idma_same_state_cnt[2];
8492 
8493 	 /* Read the SGE Debug Ingress DMA Same State Count registers.  These
8494 	  * are counters inside the SGE which count up on each clock when the
8495 	  * SGE finds its Ingress DMA State Engines in the same states they
8496 	  * were in the previous clock.  The counters will peg out at
8497 	  * 0xffffffff without wrapping around so once they pass the 1s
8498 	  * threshold they'll stay above that till the IDMA state changes.
8499 	  */
8500 	t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13);
8501 	idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH);
8502 	idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8503 
8504 	for (i = 0; i < 2; i++) {
8505 		u32 debug0, debug11;
8506 
8507 		/* If the Ingress DMA Same State Counter ("timer") is less
8508 		 * than 1s, then we can reset our synthesized Stall Timer and
8509 		 * continue.  If we have previously emitted warnings about a
8510 		 * potential stalled Ingress Queue, issue a note indicating
8511 		 * that the Ingress Queue has resumed forward progress.
8512 		 */
8513 		if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8514 			if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz)
8515 				CH_WARN(adapter, "SGE idma%d, queue %u, "
8516 					"resumed after %d seconds\n",
8517 					i, idma->idma_qid[i],
8518 					idma->idma_stalled[i]/hz);
8519 			idma->idma_stalled[i] = 0;
8520 			continue;
8521 		}
8522 
8523 		/* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8524 		 * domain.  The first time we get here it'll be because we
8525 		 * passed the 1s Threshold; each additional time it'll be
8526 		 * because the RX Timer Callback is being fired on its regular
8527 		 * schedule.
8528 		 *
8529 		 * If the stall is below our Potential Hung Ingress Queue
8530 		 * Warning Threshold, continue.
8531 		 */
8532 		if (idma->idma_stalled[i] == 0) {
8533 			idma->idma_stalled[i] = hz;
8534 			idma->idma_warn[i] = 0;
8535 		} else {
8536 			idma->idma_stalled[i] += ticks;
8537 			idma->idma_warn[i] -= ticks;
8538 		}
8539 
8540 		if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz)
8541 			continue;
8542 
8543 		/* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8544 		 */
8545 		if (idma->idma_warn[i] > 0)
8546 			continue;
8547 		idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz;
8548 
8549 		/* Read and save the SGE IDMA State and Queue ID information.
8550 		 * We do this every time in case it changes across time ...
8551 		 * can't be too careful ...
8552 		 */
8553 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0);
8554 		debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8555 		idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8556 
8557 		t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11);
8558 		debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW);
8559 		idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8560 
8561 		CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in "
8562 			" state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8563 			i, idma->idma_qid[i], idma->idma_state[i],
8564 			idma->idma_stalled[i]/hz,
8565 			debug0, debug11);
8566 		t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
8567 	}
8568 }
8569 
8570 /**
8571  *	t4_read_pace_tbl - read the pace table
8572  *	@adap: the adapter
8573  *	@pace_vals: holds the returned values
8574  *
8575  *	Returns the values of TP's pace table in microseconds.
8576  */
8577 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
8578 {
8579 	unsigned int i, v;
8580 
8581 	for (i = 0; i < NTX_SCHED; i++) {
8582 		t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
8583 		v = t4_read_reg(adap, A_TP_PACE_TABLE);
8584 		pace_vals[i] = dack_ticks_to_usec(adap, v);
8585 	}
8586 }
8587 
8588 /**
8589  *	t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
8590  *	@adap: the adapter
8591  *	@sched: the scheduler index
8592  *	@kbps: the byte rate in Kbps
8593  *	@ipg: the interpacket delay in tenths of nanoseconds
8594  *
8595  *	Return the current configuration of a HW Tx scheduler.
8596  */
8597 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
8598 		     unsigned int *ipg)
8599 {
8600 	unsigned int v, addr, bpt, cpt;
8601 
8602 	if (kbps) {
8603 		addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2;
8604 		t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8605 		v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8606 		if (sched & 1)
8607 			v >>= 16;
8608 		bpt = (v >> 8) & 0xff;
8609 		cpt = v & 0xff;
8610 		if (!cpt)
8611 			*kbps = 0;	/* scheduler disabled */
8612 		else {
8613 			v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
8614 			*kbps = (v * bpt) / 125;
8615 		}
8616 	}
8617 	if (ipg) {
8618 		addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2;
8619 		t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
8620 		v = t4_read_reg(adap, A_TP_TM_PIO_DATA);
8621 		if (sched & 1)
8622 			v >>= 16;
8623 		v &= 0xffff;
8624 		*ipg = (10000 * v) / core_ticks_per_usec(adap);
8625 	}
8626 }
8627 
8628 /**
8629  *	t4_load_cfg - download config file
8630  *	@adap: the adapter
8631  *	@cfg_data: the cfg text file to write
8632  *	@size: text file size
8633  *
8634  *	Write the supplied config text file to the card's serial flash.
8635  */
8636 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
8637 {
8638 	int ret, i, n, cfg_addr;
8639 	unsigned int addr;
8640 	unsigned int flash_cfg_start_sec;
8641 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8642 
8643 	cfg_addr = t4_flash_cfg_addr(adap);
8644 	if (cfg_addr < 0)
8645 		return cfg_addr;
8646 
8647 	addr = cfg_addr;
8648 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
8649 
8650 	if (size > FLASH_CFG_MAX_SIZE) {
8651 		CH_ERR(adap, "cfg file too large, max is %u bytes\n",
8652 		       FLASH_CFG_MAX_SIZE);
8653 		return -EFBIG;
8654 	}
8655 
8656 	i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE,	/* # of sectors spanned */
8657 			 sf_sec_size);
8658 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
8659 				     flash_cfg_start_sec + i - 1);
8660 	/*
8661 	 * If size == 0 then we're simply erasing the FLASH sectors associated
8662 	 * with the on-adapter Firmware Configuration File.
8663 	 */
8664 	if (ret || size == 0)
8665 		goto out;
8666 
8667 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
8668 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
8669 		if ( (size - i) <  SF_PAGE_SIZE)
8670 			n = size - i;
8671 		else
8672 			n = SF_PAGE_SIZE;
8673 		ret = t4_write_flash(adap, addr, n, cfg_data, 1);
8674 		if (ret)
8675 			goto out;
8676 
8677 		addr += SF_PAGE_SIZE;
8678 		cfg_data += SF_PAGE_SIZE;
8679 	}
8680 
8681 out:
8682 	if (ret)
8683 		CH_ERR(adap, "config file %s failed %d\n",
8684 		       (size == 0 ? "clear" : "download"), ret);
8685 	return ret;
8686 }
8687 
8688 /**
8689  *	t5_fw_init_extern_mem - initialize the external memory
8690  *	@adap: the adapter
8691  *
8692  *	Initializes the external memory on T5.
8693  */
8694 int t5_fw_init_extern_mem(struct adapter *adap)
8695 {
8696 	u32 params[1], val[1];
8697 	int ret;
8698 
8699 	if (!is_t5(adap))
8700 		return 0;
8701 
8702 	val[0] = 0xff; /* Initialize all MCs */
8703 	params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
8704 			V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT));
8705 	ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val,
8706 			FW_CMD_MAX_TIMEOUT);
8707 
8708 	return ret;
8709 }
8710 
8711 /* BIOS boot headers */
8712 typedef struct pci_expansion_rom_header {
8713 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
8714 	u8	reserved[22]; /* Reserved per processor Architecture data */
8715 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
8716 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */
8717 
8718 /* Legacy PCI Expansion ROM Header */
8719 typedef struct legacy_pci_expansion_rom_header {
8720 	u8	signature[2]; /* ROM Signature. Should be 0xaa55 */
8721 	u8	size512; /* Current Image Size in units of 512 bytes */
8722 	u8	initentry_point[4];
8723 	u8	cksum; /* Checksum computed on the entire Image */
8724 	u8	reserved[16]; /* Reserved */
8725 	u8	pcir_offset[2]; /* Offset to PCI Data Struture */
8726 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */
8727 
8728 /* EFI PCI Expansion ROM Header */
8729 typedef struct efi_pci_expansion_rom_header {
8730 	u8	signature[2]; // ROM signature. The value 0xaa55
8731 	u8	initialization_size[2]; /* Units 512. Includes this header */
8732 	u8	efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */
8733 	u8	efi_subsystem[2]; /* Subsystem value for EFI image header */
8734 	u8	efi_machine_type[2]; /* Machine type from EFI image header */
8735 	u8	compression_type[2]; /* Compression type. */
8736 		/*
8737 		 * Compression type definition
8738 		 * 0x0: uncompressed
8739 		 * 0x1: Compressed
8740 		 * 0x2-0xFFFF: Reserved
8741 		 */
8742 	u8	reserved[8]; /* Reserved */
8743 	u8	efi_image_header_offset[2]; /* Offset to EFI Image */
8744 	u8	pcir_offset[2]; /* Offset to PCI Data Structure */
8745 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */
8746 
8747 /* PCI Data Structure Format */
8748 typedef struct pcir_data_structure { /* PCI Data Structure */
8749 	u8	signature[4]; /* Signature. The string "PCIR" */
8750 	u8	vendor_id[2]; /* Vendor Identification */
8751 	u8	device_id[2]; /* Device Identification */
8752 	u8	vital_product[2]; /* Pointer to Vital Product Data */
8753 	u8	length[2]; /* PCIR Data Structure Length */
8754 	u8	revision; /* PCIR Data Structure Revision */
8755 	u8	class_code[3]; /* Class Code */
8756 	u8	image_length[2]; /* Image Length. Multiple of 512B */
8757 	u8	code_revision[2]; /* Revision Level of Code/Data */
8758 	u8	code_type; /* Code Type. */
8759 		/*
8760 		 * PCI Expansion ROM Code Types
8761 		 * 0x00: Intel IA-32, PC-AT compatible. Legacy
8762 		 * 0x01: Open Firmware standard for PCI. FCODE
8763 		 * 0x02: Hewlett-Packard PA RISC. HP reserved
8764 		 * 0x03: EFI Image. EFI
8765 		 * 0x04-0xFF: Reserved.
8766 		 */
8767 	u8	indicator; /* Indicator. Identifies the last image in the ROM */
8768 	u8	reserved[2]; /* Reserved */
8769 } pcir_data_t; /* PCI__DATA_STRUCTURE */
8770 
8771 /* BOOT constants */
8772 enum {
8773 	BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */
8774 	BOOT_SIGNATURE = 0xaa55,   /* signature of BIOS boot ROM */
8775 	BOOT_SIZE_INC = 512,       /* image size measured in 512B chunks */
8776 	BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */
8777 	BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment  */
8778 	VENDOR_ID = 0x1425, /* Vendor ID */
8779 	PCIR_SIGNATURE = 0x52494350 /* PCIR signature */
8780 };
8781 
8782 /*
8783  *	modify_device_id - Modifies the device ID of the Boot BIOS image
8784  *	@adatper: the device ID to write.
8785  *	@boot_data: the boot image to modify.
8786  *
8787  *	Write the supplied device ID to the boot BIOS image.
8788  */
8789 static void modify_device_id(int device_id, u8 *boot_data)
8790 {
8791 	legacy_pci_exp_rom_header_t *header;
8792 	pcir_data_t *pcir_header;
8793 	u32 cur_header = 0;
8794 
8795 	/*
8796 	 * Loop through all chained images and change the device ID's
8797 	 */
8798 	while (1) {
8799 		header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header];
8800 		pcir_header = (pcir_data_t *) &boot_data[cur_header +
8801 			      le16_to_cpu(*(u16*)header->pcir_offset)];
8802 
8803 		/*
8804 		 * Only modify the Device ID if code type is Legacy or HP.
8805 		 * 0x00: Okay to modify
8806 		 * 0x01: FCODE. Do not be modify
8807 		 * 0x03: Okay to modify
8808 		 * 0x04-0xFF: Do not modify
8809 		 */
8810 		if (pcir_header->code_type == 0x00) {
8811 			u8 csum = 0;
8812 			int i;
8813 
8814 			/*
8815 			 * Modify Device ID to match current adatper
8816 			 */
8817 			*(u16*) pcir_header->device_id = device_id;
8818 
8819 			/*
8820 			 * Set checksum temporarily to 0.
8821 			 * We will recalculate it later.
8822 			 */
8823 			header->cksum = 0x0;
8824 
8825 			/*
8826 			 * Calculate and update checksum
8827 			 */
8828 			for (i = 0; i < (header->size512 * 512); i++)
8829 				csum += (u8)boot_data[cur_header + i];
8830 
8831 			/*
8832 			 * Invert summed value to create the checksum
8833 			 * Writing new checksum value directly to the boot data
8834 			 */
8835 			boot_data[cur_header + 7] = -csum;
8836 
8837 		} else if (pcir_header->code_type == 0x03) {
8838 
8839 			/*
8840 			 * Modify Device ID to match current adatper
8841 			 */
8842 			*(u16*) pcir_header->device_id = device_id;
8843 
8844 		}
8845 
8846 
8847 		/*
8848 		 * Check indicator element to identify if this is the last
8849 		 * image in the ROM.
8850 		 */
8851 		if (pcir_header->indicator & 0x80)
8852 			break;
8853 
8854 		/*
8855 		 * Move header pointer up to the next image in the ROM.
8856 		 */
8857 		cur_header += header->size512 * 512;
8858 	}
8859 }
8860 
8861 /*
8862  *	t4_load_boot - download boot flash
8863  *	@adapter: the adapter
8864  *	@boot_data: the boot image to write
8865  *	@boot_addr: offset in flash to write boot_data
8866  *	@size: image size
8867  *
8868  *	Write the supplied boot image to the card's serial flash.
8869  *	The boot image has the following sections: a 28-byte header and the
8870  *	boot image.
8871  */
8872 int t4_load_boot(struct adapter *adap, u8 *boot_data,
8873 		 unsigned int boot_addr, unsigned int size)
8874 {
8875 	pci_exp_rom_header_t *header;
8876 	int pcir_offset ;
8877 	pcir_data_t *pcir_header;
8878 	int ret, addr;
8879 	uint16_t device_id;
8880 	unsigned int i;
8881 	unsigned int boot_sector = (boot_addr * 1024 );
8882 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
8883 
8884 	/*
8885 	 * Make sure the boot image does not encroach on the firmware region
8886 	 */
8887 	if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
8888 		CH_ERR(adap, "boot image encroaching on firmware region\n");
8889 		return -EFBIG;
8890 	}
8891 
8892 	/*
8893 	 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
8894 	 * and Boot configuration data sections. These 3 boot sections span
8895 	 * sectors 0 to 7 in flash and live right before the FW image location.
8896 	 */
8897 	i = DIV_ROUND_UP(size ? size : FLASH_FW_START,
8898 			sf_sec_size);
8899 	ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
8900 				     (boot_sector >> 16) + i - 1);
8901 
8902 	/*
8903 	 * If size == 0 then we're simply erasing the FLASH sectors associated
8904 	 * with the on-adapter option ROM file
8905 	 */
8906 	if (ret || (size == 0))
8907 		goto out;
8908 
8909 	/* Get boot header */
8910 	header = (pci_exp_rom_header_t *)boot_data;
8911 	pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset);
8912 	/* PCIR Data Structure */
8913 	pcir_header = (pcir_data_t *) &boot_data[pcir_offset];
8914 
8915 	/*
8916 	 * Perform some primitive sanity testing to avoid accidentally
8917 	 * writing garbage over the boot sectors.  We ought to check for
8918 	 * more but it's not worth it for now ...
8919 	 */
8920 	if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
8921 		CH_ERR(adap, "boot image too small/large\n");
8922 		return -EFBIG;
8923 	}
8924 
8925 #ifndef CHELSIO_T4_DIAGS
8926 	/*
8927 	 * Check BOOT ROM header signature
8928 	 */
8929 	if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) {
8930 		CH_ERR(adap, "Boot image missing signature\n");
8931 		return -EINVAL;
8932 	}
8933 
8934 	/*
8935 	 * Check PCI header signature
8936 	 */
8937 	if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) {
8938 		CH_ERR(adap, "PCI header missing signature\n");
8939 		return -EINVAL;
8940 	}
8941 
8942 	/*
8943 	 * Check Vendor ID matches Chelsio ID
8944 	 */
8945 	if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) {
8946 		CH_ERR(adap, "Vendor ID missing signature\n");
8947 		return -EINVAL;
8948 	}
8949 #endif
8950 
8951 	/*
8952 	 * Retrieve adapter's device ID
8953 	 */
8954 	t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id);
8955 	/* Want to deal with PF 0 so I strip off PF 4 indicator */
8956 	device_id = device_id & 0xf0ff;
8957 
8958 	/*
8959 	 * Check PCIE Device ID
8960 	 */
8961 	if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) {
8962 		/*
8963 		 * Change the device ID in the Boot BIOS image to match
8964 		 * the Device ID of the current adapter.
8965 		 */
8966 		modify_device_id(device_id, boot_data);
8967 	}
8968 
8969 	/*
8970 	 * Skip over the first SF_PAGE_SIZE worth of data and write it after
8971 	 * we finish copying the rest of the boot image. This will ensure
8972 	 * that the BIOS boot header will only be written if the boot image
8973 	 * was written in full.
8974 	 */
8975 	addr = boot_sector;
8976 	for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
8977 		addr += SF_PAGE_SIZE;
8978 		boot_data += SF_PAGE_SIZE;
8979 		ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0);
8980 		if (ret)
8981 			goto out;
8982 	}
8983 
8984 	ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
8985 			     (const u8 *)header, 0);
8986 
8987 out:
8988 	if (ret)
8989 		CH_ERR(adap, "boot image download failed, error %d\n", ret);
8990 	return ret;
8991 }
8992 
8993 /*
8994  *	t4_flash_bootcfg_addr - return the address of the flash optionrom configuration
8995  *	@adapter: the adapter
8996  *
8997  *	Return the address within the flash where the OptionROM Configuration
8998  *	is stored, or an error if the device FLASH is too small to contain
8999  *	a OptionROM Configuration.
9000  */
9001 static int t4_flash_bootcfg_addr(struct adapter *adapter)
9002 {
9003 	/*
9004 	 * If the device FLASH isn't large enough to hold a Firmware
9005 	 * Configuration File, return an error.
9006 	 */
9007 	if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
9008 		return -ENOSPC;
9009 
9010 	return FLASH_BOOTCFG_START;
9011 }
9012 
9013 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size)
9014 {
9015 	int ret, i, n, cfg_addr;
9016 	unsigned int addr;
9017 	unsigned int flash_cfg_start_sec;
9018 	unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
9019 
9020 	cfg_addr = t4_flash_bootcfg_addr(adap);
9021 	if (cfg_addr < 0)
9022 		return cfg_addr;
9023 
9024 	addr = cfg_addr;
9025 	flash_cfg_start_sec = addr / SF_SEC_SIZE;
9026 
9027 	if (size > FLASH_BOOTCFG_MAX_SIZE) {
9028 		CH_ERR(adap, "bootcfg file too large, max is %u bytes\n",
9029 			FLASH_BOOTCFG_MAX_SIZE);
9030 		return -EFBIG;
9031 	}
9032 
9033 	i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */
9034 			 sf_sec_size);
9035 	ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
9036 					flash_cfg_start_sec + i - 1);
9037 
9038 	/*
9039 	 * If size == 0 then we're simply erasing the FLASH sectors associated
9040 	 * with the on-adapter OptionROM Configuration File.
9041 	 */
9042 	if (ret || size == 0)
9043 		goto out;
9044 
9045 	/* this will write to the flash up to SF_PAGE_SIZE at a time */
9046 	for (i = 0; i< size; i+= SF_PAGE_SIZE) {
9047 		if ( (size - i) <  SF_PAGE_SIZE)
9048 			n = size - i;
9049 		else
9050 			n = SF_PAGE_SIZE;
9051 		ret = t4_write_flash(adap, addr, n, cfg_data, 0);
9052 		if (ret)
9053 			goto out;
9054 
9055 		addr += SF_PAGE_SIZE;
9056 		cfg_data += SF_PAGE_SIZE;
9057 	}
9058 
9059 out:
9060 	if (ret)
9061 		CH_ERR(adap, "boot config data %s failed %d\n",
9062 				(size == 0 ? "clear" : "download"), ret);
9063 	return ret;
9064 }
9065 
9066 /**
9067  *	t4_set_filter_mode - configure the optional components of filter tuples
9068  *	@adap: the adapter
9069  *	@mode_map: a bitmap selcting which optional filter components to enable
9070  *
9071  *	Sets the filter mode by selecting the optional components to enable
9072  *	in filter tuples.  Returns 0 on success and a negative error if the
9073  *	requested mode needs more bits than are available for optional
9074  *	components.
9075  */
9076 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map)
9077 {
9078 	static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 };
9079 
9080 	int i, nbits = 0;
9081 
9082 	for (i = S_FCOE; i <= S_FRAGMENTATION; i++)
9083 		if (mode_map & (1 << i))
9084 			nbits += width[i];
9085 	if (nbits > FILTER_OPT_LEN)
9086 		return -EINVAL;
9087 	if (t4_use_ldst(adap))
9088 		t4_fw_tp_pio_rw(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, 0);
9089 	else
9090 		t4_write_indirect(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, &mode_map,
9091 				  1, A_TP_VLAN_PRI_MAP);
9092 	read_filter_mode_and_ingress_config(adap);
9093 
9094 	return 0;
9095 }
9096 
9097 /**
9098  *	t4_clr_port_stats - clear port statistics
9099  *	@adap: the adapter
9100  *	@idx: the port index
9101  *
9102  *	Clear HW statistics for the given port.
9103  */
9104 void t4_clr_port_stats(struct adapter *adap, int idx)
9105 {
9106 	unsigned int i;
9107 	u32 bgmap = t4_get_mps_bg_map(adap, idx);
9108 	u32 port_base_addr;
9109 
9110 	if (is_t4(adap))
9111 		port_base_addr = PORT_BASE(idx);
9112 	else
9113 		port_base_addr = T5_PORT_BASE(idx);
9114 
9115 	for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L;
9116 			i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8)
9117 		t4_write_reg(adap, port_base_addr + i, 0);
9118 	for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L;
9119 			i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8)
9120 		t4_write_reg(adap, port_base_addr + i, 0);
9121 	for (i = 0; i < 4; i++)
9122 		if (bgmap & (1 << i)) {
9123 			t4_write_reg(adap,
9124 			A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0);
9125 			t4_write_reg(adap,
9126 			A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0);
9127 		}
9128 }
9129 
9130 /**
9131  *	t4_i2c_rd - read I2C data from adapter
9132  *	@adap: the adapter
9133  *	@port: Port number if per-port device; <0 if not
9134  *	@devid: per-port device ID or absolute device ID
9135  *	@offset: byte offset into device I2C space
9136  *	@len: byte length of I2C space data
9137  *	@buf: buffer in which to return I2C data
9138  *
9139  *	Reads the I2C data from the indicated device and location.
9140  */
9141 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
9142 	      int port, unsigned int devid,
9143 	      unsigned int offset, unsigned int len,
9144 	      u8 *buf)
9145 {
9146 	u32 ldst_addrspace;
9147 	struct fw_ldst_cmd ldst;
9148 	int ret;
9149 
9150 	if (port >= 4 ||
9151 	    devid >= 256 ||
9152 	    offset >= 256 ||
9153 	    len > sizeof ldst.u.i2c.data)
9154 		return -EINVAL;
9155 
9156 	memset(&ldst, 0, sizeof ldst);
9157 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9158 	ldst.op_to_addrspace =
9159 		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9160 			    F_FW_CMD_REQUEST |
9161 			    F_FW_CMD_READ |
9162 			    ldst_addrspace);
9163 	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9164 	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9165 	ldst.u.i2c.did = devid;
9166 	ldst.u.i2c.boffset = offset;
9167 	ldst.u.i2c.blen = len;
9168 	ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9169 	if (!ret)
9170 		memcpy(buf, ldst.u.i2c.data, len);
9171 	return ret;
9172 }
9173 
9174 /**
9175  *	t4_i2c_wr - write I2C data to adapter
9176  *	@adap: the adapter
9177  *	@port: Port number if per-port device; <0 if not
9178  *	@devid: per-port device ID or absolute device ID
9179  *	@offset: byte offset into device I2C space
9180  *	@len: byte length of I2C space data
9181  *	@buf: buffer containing new I2C data
9182  *
9183  *	Write the I2C data to the indicated device and location.
9184  */
9185 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
9186 	      int port, unsigned int devid,
9187 	      unsigned int offset, unsigned int len,
9188 	      u8 *buf)
9189 {
9190 	u32 ldst_addrspace;
9191 	struct fw_ldst_cmd ldst;
9192 
9193 	if (port >= 4 ||
9194 	    devid >= 256 ||
9195 	    offset >= 256 ||
9196 	    len > sizeof ldst.u.i2c.data)
9197 		return -EINVAL;
9198 
9199 	memset(&ldst, 0, sizeof ldst);
9200 	ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C);
9201 	ldst.op_to_addrspace =
9202 		cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9203 			    F_FW_CMD_REQUEST |
9204 			    F_FW_CMD_WRITE |
9205 			    ldst_addrspace);
9206 	ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst));
9207 	ldst.u.i2c.pid = (port < 0 ? 0xff : port);
9208 	ldst.u.i2c.did = devid;
9209 	ldst.u.i2c.boffset = offset;
9210 	ldst.u.i2c.blen = len;
9211 	memcpy(ldst.u.i2c.data, buf, len);
9212 	return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst);
9213 }
9214 
9215 /**
9216  * 	t4_sge_ctxt_rd - read an SGE context through FW
9217  * 	@adap: the adapter
9218  * 	@mbox: mailbox to use for the FW command
9219  * 	@cid: the context id
9220  * 	@ctype: the context type
9221  * 	@data: where to store the context data
9222  *
9223  * 	Issues a FW command through the given mailbox to read an SGE context.
9224  */
9225 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
9226 		   enum ctxt_type ctype, u32 *data)
9227 {
9228 	int ret;
9229 	struct fw_ldst_cmd c;
9230 
9231 	if (ctype == CTXT_EGRESS)
9232 		ret = FW_LDST_ADDRSPC_SGE_EGRC;
9233 	else if (ctype == CTXT_INGRESS)
9234 		ret = FW_LDST_ADDRSPC_SGE_INGC;
9235 	else if (ctype == CTXT_FLM)
9236 		ret = FW_LDST_ADDRSPC_SGE_FLMC;
9237 	else
9238 		ret = FW_LDST_ADDRSPC_SGE_CONMC;
9239 
9240 	memset(&c, 0, sizeof(c));
9241 	c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) |
9242 					F_FW_CMD_REQUEST | F_FW_CMD_READ |
9243 					V_FW_LDST_CMD_ADDRSPACE(ret));
9244 	c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
9245 	c.u.idctxt.physid = cpu_to_be32(cid);
9246 
9247 	ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
9248 	if (ret == 0) {
9249 		data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
9250 		data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
9251 		data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
9252 		data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
9253 		data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
9254 		data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
9255 	}
9256 	return ret;
9257 }
9258 
9259 /**
9260  * 	t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
9261  * 	@adap: the adapter
9262  * 	@cid: the context id
9263  * 	@ctype: the context type
9264  * 	@data: where to store the context data
9265  *
9266  * 	Reads an SGE context directly, bypassing FW.  This is only for
9267  * 	debugging when FW is unavailable.
9268  */
9269 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
9270 		      u32 *data)
9271 {
9272 	int i, ret;
9273 
9274 	t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype));
9275 	ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1);
9276 	if (!ret)
9277 		for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4)
9278 			*data++ = t4_read_reg(adap, i);
9279 	return ret;
9280 }
9281 
9282 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
9283     		    int sleep_ok)
9284 {
9285 	struct fw_sched_cmd cmd;
9286 
9287 	memset(&cmd, 0, sizeof(cmd));
9288 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9289 				      F_FW_CMD_REQUEST |
9290 				      F_FW_CMD_WRITE);
9291 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9292 
9293 	cmd.u.config.sc = FW_SCHED_SC_CONFIG;
9294 	cmd.u.config.type = type;
9295 	cmd.u.config.minmaxen = minmaxen;
9296 
9297 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9298 			       NULL, sleep_ok);
9299 }
9300 
9301 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
9302 		    int rateunit, int ratemode, int channel, int cl,
9303 		    int minrate, int maxrate, int weight, int pktsize,
9304 		    int sleep_ok)
9305 {
9306 	struct fw_sched_cmd cmd;
9307 
9308 	memset(&cmd, 0, sizeof(cmd));
9309 	cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) |
9310 				      F_FW_CMD_REQUEST |
9311 				      F_FW_CMD_WRITE);
9312 	cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
9313 
9314 	cmd.u.params.sc = FW_SCHED_SC_PARAMS;
9315 	cmd.u.params.type = type;
9316 	cmd.u.params.level = level;
9317 	cmd.u.params.mode = mode;
9318 	cmd.u.params.ch = channel;
9319 	cmd.u.params.cl = cl;
9320 	cmd.u.params.unit = rateunit;
9321 	cmd.u.params.rate = ratemode;
9322 	cmd.u.params.min = cpu_to_be32(minrate);
9323 	cmd.u.params.max = cpu_to_be32(maxrate);
9324 	cmd.u.params.weight = cpu_to_be16(weight);
9325 	cmd.u.params.pktsize = cpu_to_be16(pktsize);
9326 
9327 	return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd),
9328 			       NULL, sleep_ok);
9329 }
9330 
9331 /*
9332  *	t4_config_watchdog - configure (enable/disable) a watchdog timer
9333  *	@adapter: the adapter
9334  * 	@mbox: mailbox to use for the FW command
9335  * 	@pf: the PF owning the queue
9336  * 	@vf: the VF owning the queue
9337  *	@timeout: watchdog timeout in ms
9338  *	@action: watchdog timer / action
9339  *
9340  *	There are separate watchdog timers for each possible watchdog
9341  *	action.  Configure one of the watchdog timers by setting a non-zero
9342  *	timeout.  Disable a watchdog timer by using a timeout of zero.
9343  */
9344 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
9345 		       unsigned int pf, unsigned int vf,
9346 		       unsigned int timeout, unsigned int action)
9347 {
9348 	struct fw_watchdog_cmd wdog;
9349 	unsigned int ticks;
9350 
9351 	/*
9352 	 * The watchdog command expects a timeout in units of 10ms so we need
9353 	 * to convert it here (via rounding) and force a minimum of one 10ms
9354 	 * "tick" if the timeout is non-zero but the conversion results in 0
9355 	 * ticks.
9356 	 */
9357 	ticks = (timeout + 5)/10;
9358 	if (timeout && !ticks)
9359 		ticks = 1;
9360 
9361 	memset(&wdog, 0, sizeof wdog);
9362 	wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) |
9363 				     F_FW_CMD_REQUEST |
9364 				     F_FW_CMD_WRITE |
9365 				     V_FW_PARAMS_CMD_PFN(pf) |
9366 				     V_FW_PARAMS_CMD_VFN(vf));
9367 	wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog));
9368 	wdog.timeout = cpu_to_be32(ticks);
9369 	wdog.action = cpu_to_be32(action);
9370 
9371 	return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL);
9372 }
9373 
9374 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level)
9375 {
9376 	struct fw_devlog_cmd devlog_cmd;
9377 	int ret;
9378 
9379 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9380 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9381 					     F_FW_CMD_REQUEST | F_FW_CMD_READ);
9382 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9383 	ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9384 			 sizeof(devlog_cmd), &devlog_cmd);
9385 	if (ret)
9386 		return ret;
9387 
9388 	*level = devlog_cmd.level;
9389 	return 0;
9390 }
9391 
9392 int t4_set_devlog_level(struct adapter *adapter, unsigned int level)
9393 {
9394 	struct fw_devlog_cmd devlog_cmd;
9395 
9396 	memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9397 	devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
9398 					     F_FW_CMD_REQUEST |
9399 					     F_FW_CMD_WRITE);
9400 	devlog_cmd.level = level;
9401 	devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9402 	return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd,
9403 			  sizeof(devlog_cmd), &devlog_cmd);
9404 }
9405