1 /*- 2 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_inet.h" 31 32 #include <sys/param.h> 33 #include <sys/eventhandler.h> 34 35 #include "common.h" 36 #include "t4_regs.h" 37 #include "t4_regs_values.h" 38 #include "firmware/t4fw_interface.h" 39 40 #undef msleep 41 #define msleep(x) do { \ 42 if (cold) \ 43 DELAY((x) * 1000); \ 44 else \ 45 pause("t4hw", (x) * hz / 1000); \ 46 } while (0) 47 48 /** 49 * t4_wait_op_done_val - wait until an operation is completed 50 * @adapter: the adapter performing the operation 51 * @reg: the register to check for completion 52 * @mask: a single-bit field within @reg that indicates completion 53 * @polarity: the value of the field when the operation is completed 54 * @attempts: number of check iterations 55 * @delay: delay in usecs between iterations 56 * @valp: where to store the value of the register at completion time 57 * 58 * Wait until an operation is completed by checking a bit in a register 59 * up to @attempts times. If @valp is not NULL the value of the register 60 * at the time it indicated completion is stored there. Returns 0 if the 61 * operation completes and -EAGAIN otherwise. 62 */ 63 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 64 int polarity, int attempts, int delay, u32 *valp) 65 { 66 while (1) { 67 u32 val = t4_read_reg(adapter, reg); 68 69 if (!!(val & mask) == polarity) { 70 if (valp) 71 *valp = val; 72 return 0; 73 } 74 if (--attempts == 0) 75 return -EAGAIN; 76 if (delay) 77 udelay(delay); 78 } 79 } 80 81 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 82 int polarity, int attempts, int delay) 83 { 84 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 85 delay, NULL); 86 } 87 88 /** 89 * t4_set_reg_field - set a register field to a value 90 * @adapter: the adapter to program 91 * @addr: the register address 92 * @mask: specifies the portion of the register to modify 93 * @val: the new value for the register field 94 * 95 * Sets a register field specified by the supplied mask to the 96 * given value. 97 */ 98 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 99 u32 val) 100 { 101 u32 v = t4_read_reg(adapter, addr) & ~mask; 102 103 t4_write_reg(adapter, addr, v | val); 104 (void) t4_read_reg(adapter, addr); /* flush */ 105 } 106 107 /** 108 * t4_read_indirect - read indirectly addressed registers 109 * @adap: the adapter 110 * @addr_reg: register holding the indirect address 111 * @data_reg: register holding the value of the indirect register 112 * @vals: where the read register values are stored 113 * @nregs: how many indirect registers to read 114 * @start_idx: index of first indirect register to read 115 * 116 * Reads registers that are accessed indirectly through an address/data 117 * register pair. 118 */ 119 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 120 unsigned int data_reg, u32 *vals, 121 unsigned int nregs, unsigned int start_idx) 122 { 123 while (nregs--) { 124 t4_write_reg(adap, addr_reg, start_idx); 125 *vals++ = t4_read_reg(adap, data_reg); 126 start_idx++; 127 } 128 } 129 130 /** 131 * t4_write_indirect - write indirectly addressed registers 132 * @adap: the adapter 133 * @addr_reg: register holding the indirect addresses 134 * @data_reg: register holding the value for the indirect registers 135 * @vals: values to write 136 * @nregs: how many indirect registers to write 137 * @start_idx: address of first indirect register to write 138 * 139 * Writes a sequential block of registers that are accessed indirectly 140 * through an address/data register pair. 141 */ 142 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 143 unsigned int data_reg, const u32 *vals, 144 unsigned int nregs, unsigned int start_idx) 145 { 146 while (nregs--) { 147 t4_write_reg(adap, addr_reg, start_idx++); 148 t4_write_reg(adap, data_reg, *vals++); 149 } 150 } 151 152 /* 153 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 154 * mechanism. This guarantees that we get the real value even if we're 155 * operating within a Virtual Machine and the Hypervisor is trapping our 156 * Configuration Space accesses. 157 * 158 * N.B. This routine should only be used as a last resort: the firmware uses 159 * the backdoor registers on a regular basis and we can end up 160 * conflicting with it's uses! 161 */ 162 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 163 { 164 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 165 u32 val; 166 167 if (chip_id(adap) <= CHELSIO_T5) 168 req |= F_ENABLE; 169 else 170 req |= F_T6_ENABLE; 171 172 if (is_t4(adap)) 173 req |= F_LOCALCFG; 174 175 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 176 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 177 178 /* 179 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 180 * Configuration Space read. (None of the other fields matter when 181 * F_ENABLE is 0 so a simple register write is easier than a 182 * read-modify-write via t4_set_reg_field().) 183 */ 184 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 185 186 return val; 187 } 188 189 /* 190 * t4_report_fw_error - report firmware error 191 * @adap: the adapter 192 * 193 * The adapter firmware can indicate error conditions to the host. 194 * If the firmware has indicated an error, print out the reason for 195 * the firmware error. 196 */ 197 static void t4_report_fw_error(struct adapter *adap) 198 { 199 static const char *const reason[] = { 200 "Crash", /* PCIE_FW_EVAL_CRASH */ 201 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 202 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 203 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 204 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 205 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 206 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 207 "Reserved", /* reserved */ 208 }; 209 u32 pcie_fw; 210 211 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 212 if (pcie_fw & F_PCIE_FW_ERR) 213 CH_ERR(adap, "Firmware reports adapter error: %s\n", 214 reason[G_PCIE_FW_EVAL(pcie_fw)]); 215 } 216 217 /* 218 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 219 */ 220 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 221 u32 mbox_addr) 222 { 223 for ( ; nflit; nflit--, mbox_addr += 8) 224 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 225 } 226 227 /* 228 * Handle a FW assertion reported in a mailbox. 229 */ 230 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 231 { 232 CH_ALERT(adap, 233 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 234 asrt->u.assert.filename_0_7, 235 be32_to_cpu(asrt->u.assert.line), 236 be32_to_cpu(asrt->u.assert.x), 237 be32_to_cpu(asrt->u.assert.y)); 238 } 239 240 #define X_CIM_PF_NOACCESS 0xeeeeeeee 241 /** 242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 243 * @adap: the adapter 244 * @mbox: index of the mailbox to use 245 * @cmd: the command to write 246 * @size: command length in bytes 247 * @rpl: where to optionally store the reply 248 * @sleep_ok: if true we may sleep while awaiting command completion 249 * @timeout: time to wait for command to finish before timing out 250 * (negative implies @sleep_ok=false) 251 * 252 * Sends the given command to FW through the selected mailbox and waits 253 * for the FW to execute the command. If @rpl is not %NULL it is used to 254 * store the FW's reply to the command. The command and its optional 255 * reply are of the same length. Some FW commands like RESET and 256 * INITIALIZE can take a considerable amount of time to execute. 257 * @sleep_ok determines whether we may sleep while awaiting the response. 258 * If sleeping is allowed we use progressive backoff otherwise we spin. 259 * Note that passing in a negative @timeout is an alternate mechanism 260 * for specifying @sleep_ok=false. This is useful when a higher level 261 * interface allows for specification of @timeout but not @sleep_ok ... 262 * 263 * The return value is 0 on success or a negative errno on failure. A 264 * failure can happen either because we are not able to execute the 265 * command or FW executes it but signals an error. In the latter case 266 * the return value is the error code indicated by FW (negated). 267 */ 268 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 269 int size, void *rpl, bool sleep_ok, int timeout) 270 { 271 /* 272 * We delay in small increments at first in an effort to maintain 273 * responsiveness for simple, fast executing commands but then back 274 * off to larger delays to a maximum retry delay. 275 */ 276 static const int delay[] = { 277 1, 1, 3, 5, 10, 10, 20, 50, 100 278 }; 279 u32 v; 280 u64 res; 281 int i, ms, delay_idx, ret; 282 const __be64 *p = cmd; 283 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 284 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 285 u32 ctl; 286 __be64 cmd_rpl[MBOX_LEN/8]; 287 u32 pcie_fw; 288 289 if (adap->flags & CHK_MBOX_ACCESS) 290 ASSERT_SYNCHRONIZED_OP(adap); 291 292 if ((size & 15) || size > MBOX_LEN) 293 return -EINVAL; 294 295 if (adap->flags & IS_VF) { 296 if (is_t6(adap)) 297 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 298 else 299 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 300 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 301 } 302 303 /* 304 * If we have a negative timeout, that implies that we can't sleep. 305 */ 306 if (timeout < 0) { 307 sleep_ok = false; 308 timeout = -timeout; 309 } 310 311 /* 312 * Attempt to gain access to the mailbox. 313 */ 314 for (i = 0; i < 4; i++) { 315 ctl = t4_read_reg(adap, ctl_reg); 316 v = G_MBOWNER(ctl); 317 if (v != X_MBOWNER_NONE) 318 break; 319 } 320 321 /* 322 * If we were unable to gain access, dequeue ourselves from the 323 * mailbox atomic access list and report the error to our caller. 324 */ 325 if (v != X_MBOWNER_PL) { 326 t4_report_fw_error(adap); 327 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 328 return ret; 329 } 330 331 /* 332 * If we gain ownership of the mailbox and there's a "valid" message 333 * in it, this is likely an asynchronous error message from the 334 * firmware. So we'll report that and then proceed on with attempting 335 * to issue our own command ... which may well fail if the error 336 * presaged the firmware crashing ... 337 */ 338 if (ctl & F_MBMSGVALID) { 339 CH_ERR(adap, "found VALID command in mbox %u: %016llx %016llx " 340 "%016llx %016llx %016llx %016llx %016llx %016llx\n", 341 mbox, (unsigned long long)t4_read_reg64(adap, data_reg), 342 (unsigned long long)t4_read_reg64(adap, data_reg + 8), 343 (unsigned long long)t4_read_reg64(adap, data_reg + 16), 344 (unsigned long long)t4_read_reg64(adap, data_reg + 24), 345 (unsigned long long)t4_read_reg64(adap, data_reg + 32), 346 (unsigned long long)t4_read_reg64(adap, data_reg + 40), 347 (unsigned long long)t4_read_reg64(adap, data_reg + 48), 348 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); 349 } 350 351 /* 352 * Copy in the new mailbox command and send it on its way ... 353 */ 354 for (i = 0; i < size; i += 8, p++) 355 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); 356 357 if (adap->flags & IS_VF) { 358 /* 359 * For the VFs, the Mailbox Data "registers" are 360 * actually backed by T4's "MA" interface rather than 361 * PL Registers (as is the case for the PFs). Because 362 * these are in different coherency domains, the write 363 * to the VF's PL-register-backed Mailbox Control can 364 * race in front of the writes to the MA-backed VF 365 * Mailbox Data "registers". So we need to do a 366 * read-back on at least one byte of the VF Mailbox 367 * Data registers before doing the write to the VF 368 * Mailbox Control register. 369 */ 370 t4_read_reg(adap, data_reg); 371 } 372 373 CH_DUMP_MBOX(adap, mbox, data_reg); 374 375 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 376 t4_read_reg(adap, ctl_reg); /* flush write */ 377 378 delay_idx = 0; 379 ms = delay[0]; 380 381 /* 382 * Loop waiting for the reply; bail out if we time out or the firmware 383 * reports an error. 384 */ 385 pcie_fw = 0; 386 for (i = 0; i < timeout; i += ms) { 387 if (!(adap->flags & IS_VF)) { 388 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 389 if (pcie_fw & F_PCIE_FW_ERR) 390 break; 391 } 392 if (sleep_ok) { 393 ms = delay[delay_idx]; /* last element may repeat */ 394 if (delay_idx < ARRAY_SIZE(delay) - 1) 395 delay_idx++; 396 msleep(ms); 397 } else { 398 mdelay(ms); 399 } 400 401 v = t4_read_reg(adap, ctl_reg); 402 if (v == X_CIM_PF_NOACCESS) 403 continue; 404 if (G_MBOWNER(v) == X_MBOWNER_PL) { 405 if (!(v & F_MBMSGVALID)) { 406 t4_write_reg(adap, ctl_reg, 407 V_MBOWNER(X_MBOWNER_NONE)); 408 continue; 409 } 410 411 /* 412 * Retrieve the command reply and release the mailbox. 413 */ 414 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 415 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 416 417 CH_DUMP_MBOX(adap, mbox, data_reg); 418 419 res = be64_to_cpu(cmd_rpl[0]); 420 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 421 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 422 res = V_FW_CMD_RETVAL(EIO); 423 } else if (rpl) 424 memcpy(rpl, cmd_rpl, size); 425 return -G_FW_CMD_RETVAL((int)res); 426 } 427 } 428 429 /* 430 * We timed out waiting for a reply to our mailbox command. Report 431 * the error and also check to see if the firmware reported any 432 * errors ... 433 */ 434 ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; 435 CH_ERR(adap, "command %#x in mailbox %d timed out\n", 436 *(const u8 *)cmd, mbox); 437 438 /* If DUMP_MBOX is set the mbox has already been dumped */ 439 if ((adap->debug_flags & DF_DUMP_MBOX) == 0) { 440 p = cmd; 441 CH_ERR(adap, "mbox: %016llx %016llx %016llx %016llx " 442 "%016llx %016llx %016llx %016llx\n", 443 (unsigned long long)be64_to_cpu(p[0]), 444 (unsigned long long)be64_to_cpu(p[1]), 445 (unsigned long long)be64_to_cpu(p[2]), 446 (unsigned long long)be64_to_cpu(p[3]), 447 (unsigned long long)be64_to_cpu(p[4]), 448 (unsigned long long)be64_to_cpu(p[5]), 449 (unsigned long long)be64_to_cpu(p[6]), 450 (unsigned long long)be64_to_cpu(p[7])); 451 } 452 453 t4_report_fw_error(adap); 454 t4_fatal_err(adap); 455 return ret; 456 } 457 458 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 459 void *rpl, bool sleep_ok) 460 { 461 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 462 sleep_ok, FW_CMD_MAX_TIMEOUT); 463 464 } 465 466 static int t4_edc_err_read(struct adapter *adap, int idx) 467 { 468 u32 edc_ecc_err_addr_reg; 469 u32 edc_bist_status_rdata_reg; 470 471 if (is_t4(adap)) { 472 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 473 return 0; 474 } 475 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 476 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 477 return 0; 478 } 479 480 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 481 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 482 483 CH_WARN(adap, 484 "edc%d err addr 0x%x: 0x%x.\n", 485 idx, edc_ecc_err_addr_reg, 486 t4_read_reg(adap, edc_ecc_err_addr_reg)); 487 CH_WARN(adap, 488 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 489 edc_bist_status_rdata_reg, 490 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 491 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 492 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 493 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 494 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 495 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 496 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 497 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 498 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 499 500 return 0; 501 } 502 503 /** 504 * t4_mc_read - read from MC through backdoor accesses 505 * @adap: the adapter 506 * @idx: which MC to access 507 * @addr: address of first byte requested 508 * @data: 64 bytes of data containing the requested address 509 * @ecc: where to store the corresponding 64-bit ECC word 510 * 511 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 512 * that covers the requested address @addr. If @parity is not %NULL it 513 * is assigned the 64-bit ECC word for the read data. 514 */ 515 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 516 { 517 int i; 518 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 519 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 520 521 if (is_t4(adap)) { 522 mc_bist_cmd_reg = A_MC_BIST_CMD; 523 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 524 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 525 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 526 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 527 } else { 528 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 529 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 530 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 531 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 532 idx); 533 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 534 idx); 535 } 536 537 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 538 return -EBUSY; 539 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 540 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 541 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 542 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 543 F_START_BIST | V_BIST_CMD_GAP(1)); 544 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 545 if (i) 546 return i; 547 548 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 549 550 for (i = 15; i >= 0; i--) 551 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 552 if (ecc) 553 *ecc = t4_read_reg64(adap, MC_DATA(16)); 554 #undef MC_DATA 555 return 0; 556 } 557 558 /** 559 * t4_edc_read - read from EDC through backdoor accesses 560 * @adap: the adapter 561 * @idx: which EDC to access 562 * @addr: address of first byte requested 563 * @data: 64 bytes of data containing the requested address 564 * @ecc: where to store the corresponding 64-bit ECC word 565 * 566 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 567 * that covers the requested address @addr. If @parity is not %NULL it 568 * is assigned the 64-bit ECC word for the read data. 569 */ 570 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 571 { 572 int i; 573 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 574 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 575 576 if (is_t4(adap)) { 577 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 578 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 579 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 580 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 581 idx); 582 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 583 idx); 584 } else { 585 /* 586 * These macro are missing in t4_regs.h file. 587 * Added temporarily for testing. 588 */ 589 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 590 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 591 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 592 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 593 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 594 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 595 idx); 596 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 597 idx); 598 #undef EDC_REG_T5 599 #undef EDC_STRIDE_T5 600 } 601 602 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 603 return -EBUSY; 604 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 605 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 606 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 607 t4_write_reg(adap, edc_bist_cmd_reg, 608 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 609 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 610 if (i) 611 return i; 612 613 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 614 615 for (i = 15; i >= 0; i--) 616 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 617 if (ecc) 618 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 619 #undef EDC_DATA 620 return 0; 621 } 622 623 /** 624 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 625 * @adap: the adapter 626 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 627 * @addr: address within indicated memory type 628 * @len: amount of memory to read 629 * @buf: host memory buffer 630 * 631 * Reads an [almost] arbitrary memory region in the firmware: the 632 * firmware memory address, length and host buffer must be aligned on 633 * 32-bit boudaries. The memory is returned as a raw byte sequence from 634 * the firmware's memory. If this memory contains data structures which 635 * contain multi-byte integers, it's the callers responsibility to 636 * perform appropriate byte order conversions. 637 */ 638 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 639 __be32 *buf) 640 { 641 u32 pos, start, end, offset; 642 int ret; 643 644 /* 645 * Argument sanity checks ... 646 */ 647 if ((addr & 0x3) || (len & 0x3)) 648 return -EINVAL; 649 650 /* 651 * The underlaying EDC/MC read routines read 64 bytes at a time so we 652 * need to round down the start and round up the end. We'll start 653 * copying out of the first line at (addr - start) a word at a time. 654 */ 655 start = rounddown2(addr, 64); 656 end = roundup2(addr + len, 64); 657 offset = (addr - start)/sizeof(__be32); 658 659 for (pos = start; pos < end; pos += 64, offset = 0) { 660 __be32 data[16]; 661 662 /* 663 * Read the chip's memory block and bail if there's an error. 664 */ 665 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 666 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 667 else 668 ret = t4_edc_read(adap, mtype, pos, data, NULL); 669 if (ret) 670 return ret; 671 672 /* 673 * Copy the data into the caller's memory buffer. 674 */ 675 while (offset < 16 && len > 0) { 676 *buf++ = data[offset++]; 677 len -= sizeof(__be32); 678 } 679 } 680 681 return 0; 682 } 683 684 /* 685 * Return the specified PCI-E Configuration Space register from our Physical 686 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 687 * since we prefer to let the firmware own all of these registers, but if that 688 * fails we go for it directly ourselves. 689 */ 690 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 691 { 692 693 /* 694 * If fw_attach != 0, construct and send the Firmware LDST Command to 695 * retrieve the specified PCI-E Configuration Space register. 696 */ 697 if (drv_fw_attach != 0) { 698 struct fw_ldst_cmd ldst_cmd; 699 int ret; 700 701 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 702 ldst_cmd.op_to_addrspace = 703 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 704 F_FW_CMD_REQUEST | 705 F_FW_CMD_READ | 706 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 707 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 708 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 709 ldst_cmd.u.pcie.ctrl_to_fn = 710 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 711 ldst_cmd.u.pcie.r = reg; 712 713 /* 714 * If the LDST Command succeeds, return the result, otherwise 715 * fall through to reading it directly ourselves ... 716 */ 717 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 718 &ldst_cmd); 719 if (ret == 0) 720 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 721 722 CH_WARN(adap, "Firmware failed to return " 723 "Configuration Space register %d, err = %d\n", 724 reg, -ret); 725 } 726 727 /* 728 * Read the desired Configuration Space register via the PCI-E 729 * Backdoor mechanism. 730 */ 731 return t4_hw_pci_read_cfg4(adap, reg); 732 } 733 734 /** 735 * t4_get_regs_len - return the size of the chips register set 736 * @adapter: the adapter 737 * 738 * Returns the size of the chip's BAR0 register space. 739 */ 740 unsigned int t4_get_regs_len(struct adapter *adapter) 741 { 742 unsigned int chip_version = chip_id(adapter); 743 744 switch (chip_version) { 745 case CHELSIO_T4: 746 if (adapter->flags & IS_VF) 747 return FW_T4VF_REGMAP_SIZE; 748 return T4_REGMAP_SIZE; 749 750 case CHELSIO_T5: 751 case CHELSIO_T6: 752 if (adapter->flags & IS_VF) 753 return FW_T4VF_REGMAP_SIZE; 754 return T5_REGMAP_SIZE; 755 } 756 757 CH_ERR(adapter, 758 "Unsupported chip version %d\n", chip_version); 759 return 0; 760 } 761 762 /** 763 * t4_get_regs - read chip registers into provided buffer 764 * @adap: the adapter 765 * @buf: register buffer 766 * @buf_size: size (in bytes) of register buffer 767 * 768 * If the provided register buffer isn't large enough for the chip's 769 * full register range, the register dump will be truncated to the 770 * register buffer's size. 771 */ 772 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 773 { 774 static const unsigned int t4_reg_ranges[] = { 775 0x1008, 0x1108, 776 0x1180, 0x1184, 777 0x1190, 0x1194, 778 0x11a0, 0x11a4, 779 0x11b0, 0x11b4, 780 0x11fc, 0x123c, 781 0x1300, 0x173c, 782 0x1800, 0x18fc, 783 0x3000, 0x30d8, 784 0x30e0, 0x30e4, 785 0x30ec, 0x5910, 786 0x5920, 0x5924, 787 0x5960, 0x5960, 788 0x5968, 0x5968, 789 0x5970, 0x5970, 790 0x5978, 0x5978, 791 0x5980, 0x5980, 792 0x5988, 0x5988, 793 0x5990, 0x5990, 794 0x5998, 0x5998, 795 0x59a0, 0x59d4, 796 0x5a00, 0x5ae0, 797 0x5ae8, 0x5ae8, 798 0x5af0, 0x5af0, 799 0x5af8, 0x5af8, 800 0x6000, 0x6098, 801 0x6100, 0x6150, 802 0x6200, 0x6208, 803 0x6240, 0x6248, 804 0x6280, 0x62b0, 805 0x62c0, 0x6338, 806 0x6370, 0x638c, 807 0x6400, 0x643c, 808 0x6500, 0x6524, 809 0x6a00, 0x6a04, 810 0x6a14, 0x6a38, 811 0x6a60, 0x6a70, 812 0x6a78, 0x6a78, 813 0x6b00, 0x6b0c, 814 0x6b1c, 0x6b84, 815 0x6bf0, 0x6bf8, 816 0x6c00, 0x6c0c, 817 0x6c1c, 0x6c84, 818 0x6cf0, 0x6cf8, 819 0x6d00, 0x6d0c, 820 0x6d1c, 0x6d84, 821 0x6df0, 0x6df8, 822 0x6e00, 0x6e0c, 823 0x6e1c, 0x6e84, 824 0x6ef0, 0x6ef8, 825 0x6f00, 0x6f0c, 826 0x6f1c, 0x6f84, 827 0x6ff0, 0x6ff8, 828 0x7000, 0x700c, 829 0x701c, 0x7084, 830 0x70f0, 0x70f8, 831 0x7100, 0x710c, 832 0x711c, 0x7184, 833 0x71f0, 0x71f8, 834 0x7200, 0x720c, 835 0x721c, 0x7284, 836 0x72f0, 0x72f8, 837 0x7300, 0x730c, 838 0x731c, 0x7384, 839 0x73f0, 0x73f8, 840 0x7400, 0x7450, 841 0x7500, 0x7530, 842 0x7600, 0x760c, 843 0x7614, 0x761c, 844 0x7680, 0x76cc, 845 0x7700, 0x7798, 846 0x77c0, 0x77fc, 847 0x7900, 0x79fc, 848 0x7b00, 0x7b58, 849 0x7b60, 0x7b84, 850 0x7b8c, 0x7c38, 851 0x7d00, 0x7d38, 852 0x7d40, 0x7d80, 853 0x7d8c, 0x7ddc, 854 0x7de4, 0x7e04, 855 0x7e10, 0x7e1c, 856 0x7e24, 0x7e38, 857 0x7e40, 0x7e44, 858 0x7e4c, 0x7e78, 859 0x7e80, 0x7ea4, 860 0x7eac, 0x7edc, 861 0x7ee8, 0x7efc, 862 0x8dc0, 0x8e04, 863 0x8e10, 0x8e1c, 864 0x8e30, 0x8e78, 865 0x8ea0, 0x8eb8, 866 0x8ec0, 0x8f6c, 867 0x8fc0, 0x9008, 868 0x9010, 0x9058, 869 0x9060, 0x9060, 870 0x9068, 0x9074, 871 0x90fc, 0x90fc, 872 0x9400, 0x9408, 873 0x9410, 0x9458, 874 0x9600, 0x9600, 875 0x9608, 0x9638, 876 0x9640, 0x96bc, 877 0x9800, 0x9808, 878 0x9820, 0x983c, 879 0x9850, 0x9864, 880 0x9c00, 0x9c6c, 881 0x9c80, 0x9cec, 882 0x9d00, 0x9d6c, 883 0x9d80, 0x9dec, 884 0x9e00, 0x9e6c, 885 0x9e80, 0x9eec, 886 0x9f00, 0x9f6c, 887 0x9f80, 0x9fec, 888 0xd004, 0xd004, 889 0xd010, 0xd03c, 890 0xdfc0, 0xdfe0, 891 0xe000, 0xea7c, 892 0xf000, 0x11110, 893 0x11118, 0x11190, 894 0x19040, 0x1906c, 895 0x19078, 0x19080, 896 0x1908c, 0x190e4, 897 0x190f0, 0x190f8, 898 0x19100, 0x19110, 899 0x19120, 0x19124, 900 0x19150, 0x19194, 901 0x1919c, 0x191b0, 902 0x191d0, 0x191e8, 903 0x19238, 0x1924c, 904 0x193f8, 0x1943c, 905 0x1944c, 0x19474, 906 0x19490, 0x194e0, 907 0x194f0, 0x194f8, 908 0x19800, 0x19c08, 909 0x19c10, 0x19c90, 910 0x19ca0, 0x19ce4, 911 0x19cf0, 0x19d40, 912 0x19d50, 0x19d94, 913 0x19da0, 0x19de8, 914 0x19df0, 0x19e40, 915 0x19e50, 0x19e90, 916 0x19ea0, 0x19f4c, 917 0x1a000, 0x1a004, 918 0x1a010, 0x1a06c, 919 0x1a0b0, 0x1a0e4, 920 0x1a0ec, 0x1a0f4, 921 0x1a100, 0x1a108, 922 0x1a114, 0x1a120, 923 0x1a128, 0x1a130, 924 0x1a138, 0x1a138, 925 0x1a190, 0x1a1c4, 926 0x1a1fc, 0x1a1fc, 927 0x1e040, 0x1e04c, 928 0x1e284, 0x1e28c, 929 0x1e2c0, 0x1e2c0, 930 0x1e2e0, 0x1e2e0, 931 0x1e300, 0x1e384, 932 0x1e3c0, 0x1e3c8, 933 0x1e440, 0x1e44c, 934 0x1e684, 0x1e68c, 935 0x1e6c0, 0x1e6c0, 936 0x1e6e0, 0x1e6e0, 937 0x1e700, 0x1e784, 938 0x1e7c0, 0x1e7c8, 939 0x1e840, 0x1e84c, 940 0x1ea84, 0x1ea8c, 941 0x1eac0, 0x1eac0, 942 0x1eae0, 0x1eae0, 943 0x1eb00, 0x1eb84, 944 0x1ebc0, 0x1ebc8, 945 0x1ec40, 0x1ec4c, 946 0x1ee84, 0x1ee8c, 947 0x1eec0, 0x1eec0, 948 0x1eee0, 0x1eee0, 949 0x1ef00, 0x1ef84, 950 0x1efc0, 0x1efc8, 951 0x1f040, 0x1f04c, 952 0x1f284, 0x1f28c, 953 0x1f2c0, 0x1f2c0, 954 0x1f2e0, 0x1f2e0, 955 0x1f300, 0x1f384, 956 0x1f3c0, 0x1f3c8, 957 0x1f440, 0x1f44c, 958 0x1f684, 0x1f68c, 959 0x1f6c0, 0x1f6c0, 960 0x1f6e0, 0x1f6e0, 961 0x1f700, 0x1f784, 962 0x1f7c0, 0x1f7c8, 963 0x1f840, 0x1f84c, 964 0x1fa84, 0x1fa8c, 965 0x1fac0, 0x1fac0, 966 0x1fae0, 0x1fae0, 967 0x1fb00, 0x1fb84, 968 0x1fbc0, 0x1fbc8, 969 0x1fc40, 0x1fc4c, 970 0x1fe84, 0x1fe8c, 971 0x1fec0, 0x1fec0, 972 0x1fee0, 0x1fee0, 973 0x1ff00, 0x1ff84, 974 0x1ffc0, 0x1ffc8, 975 0x20000, 0x2002c, 976 0x20100, 0x2013c, 977 0x20190, 0x201a0, 978 0x201a8, 0x201b8, 979 0x201c4, 0x201c8, 980 0x20200, 0x20318, 981 0x20400, 0x204b4, 982 0x204c0, 0x20528, 983 0x20540, 0x20614, 984 0x21000, 0x21040, 985 0x2104c, 0x21060, 986 0x210c0, 0x210ec, 987 0x21200, 0x21268, 988 0x21270, 0x21284, 989 0x212fc, 0x21388, 990 0x21400, 0x21404, 991 0x21500, 0x21500, 992 0x21510, 0x21518, 993 0x2152c, 0x21530, 994 0x2153c, 0x2153c, 995 0x21550, 0x21554, 996 0x21600, 0x21600, 997 0x21608, 0x2161c, 998 0x21624, 0x21628, 999 0x21630, 0x21634, 1000 0x2163c, 0x2163c, 1001 0x21700, 0x2171c, 1002 0x21780, 0x2178c, 1003 0x21800, 0x21818, 1004 0x21820, 0x21828, 1005 0x21830, 0x21848, 1006 0x21850, 0x21854, 1007 0x21860, 0x21868, 1008 0x21870, 0x21870, 1009 0x21878, 0x21898, 1010 0x218a0, 0x218a8, 1011 0x218b0, 0x218c8, 1012 0x218d0, 0x218d4, 1013 0x218e0, 0x218e8, 1014 0x218f0, 0x218f0, 1015 0x218f8, 0x21a18, 1016 0x21a20, 0x21a28, 1017 0x21a30, 0x21a48, 1018 0x21a50, 0x21a54, 1019 0x21a60, 0x21a68, 1020 0x21a70, 0x21a70, 1021 0x21a78, 0x21a98, 1022 0x21aa0, 0x21aa8, 1023 0x21ab0, 0x21ac8, 1024 0x21ad0, 0x21ad4, 1025 0x21ae0, 0x21ae8, 1026 0x21af0, 0x21af0, 1027 0x21af8, 0x21c18, 1028 0x21c20, 0x21c20, 1029 0x21c28, 0x21c30, 1030 0x21c38, 0x21c38, 1031 0x21c80, 0x21c98, 1032 0x21ca0, 0x21ca8, 1033 0x21cb0, 0x21cc8, 1034 0x21cd0, 0x21cd4, 1035 0x21ce0, 0x21ce8, 1036 0x21cf0, 0x21cf0, 1037 0x21cf8, 0x21d7c, 1038 0x21e00, 0x21e04, 1039 0x22000, 0x2202c, 1040 0x22100, 0x2213c, 1041 0x22190, 0x221a0, 1042 0x221a8, 0x221b8, 1043 0x221c4, 0x221c8, 1044 0x22200, 0x22318, 1045 0x22400, 0x224b4, 1046 0x224c0, 0x22528, 1047 0x22540, 0x22614, 1048 0x23000, 0x23040, 1049 0x2304c, 0x23060, 1050 0x230c0, 0x230ec, 1051 0x23200, 0x23268, 1052 0x23270, 0x23284, 1053 0x232fc, 0x23388, 1054 0x23400, 0x23404, 1055 0x23500, 0x23500, 1056 0x23510, 0x23518, 1057 0x2352c, 0x23530, 1058 0x2353c, 0x2353c, 1059 0x23550, 0x23554, 1060 0x23600, 0x23600, 1061 0x23608, 0x2361c, 1062 0x23624, 0x23628, 1063 0x23630, 0x23634, 1064 0x2363c, 0x2363c, 1065 0x23700, 0x2371c, 1066 0x23780, 0x2378c, 1067 0x23800, 0x23818, 1068 0x23820, 0x23828, 1069 0x23830, 0x23848, 1070 0x23850, 0x23854, 1071 0x23860, 0x23868, 1072 0x23870, 0x23870, 1073 0x23878, 0x23898, 1074 0x238a0, 0x238a8, 1075 0x238b0, 0x238c8, 1076 0x238d0, 0x238d4, 1077 0x238e0, 0x238e8, 1078 0x238f0, 0x238f0, 1079 0x238f8, 0x23a18, 1080 0x23a20, 0x23a28, 1081 0x23a30, 0x23a48, 1082 0x23a50, 0x23a54, 1083 0x23a60, 0x23a68, 1084 0x23a70, 0x23a70, 1085 0x23a78, 0x23a98, 1086 0x23aa0, 0x23aa8, 1087 0x23ab0, 0x23ac8, 1088 0x23ad0, 0x23ad4, 1089 0x23ae0, 0x23ae8, 1090 0x23af0, 0x23af0, 1091 0x23af8, 0x23c18, 1092 0x23c20, 0x23c20, 1093 0x23c28, 0x23c30, 1094 0x23c38, 0x23c38, 1095 0x23c80, 0x23c98, 1096 0x23ca0, 0x23ca8, 1097 0x23cb0, 0x23cc8, 1098 0x23cd0, 0x23cd4, 1099 0x23ce0, 0x23ce8, 1100 0x23cf0, 0x23cf0, 1101 0x23cf8, 0x23d7c, 1102 0x23e00, 0x23e04, 1103 0x24000, 0x2402c, 1104 0x24100, 0x2413c, 1105 0x24190, 0x241a0, 1106 0x241a8, 0x241b8, 1107 0x241c4, 0x241c8, 1108 0x24200, 0x24318, 1109 0x24400, 0x244b4, 1110 0x244c0, 0x24528, 1111 0x24540, 0x24614, 1112 0x25000, 0x25040, 1113 0x2504c, 0x25060, 1114 0x250c0, 0x250ec, 1115 0x25200, 0x25268, 1116 0x25270, 0x25284, 1117 0x252fc, 0x25388, 1118 0x25400, 0x25404, 1119 0x25500, 0x25500, 1120 0x25510, 0x25518, 1121 0x2552c, 0x25530, 1122 0x2553c, 0x2553c, 1123 0x25550, 0x25554, 1124 0x25600, 0x25600, 1125 0x25608, 0x2561c, 1126 0x25624, 0x25628, 1127 0x25630, 0x25634, 1128 0x2563c, 0x2563c, 1129 0x25700, 0x2571c, 1130 0x25780, 0x2578c, 1131 0x25800, 0x25818, 1132 0x25820, 0x25828, 1133 0x25830, 0x25848, 1134 0x25850, 0x25854, 1135 0x25860, 0x25868, 1136 0x25870, 0x25870, 1137 0x25878, 0x25898, 1138 0x258a0, 0x258a8, 1139 0x258b0, 0x258c8, 1140 0x258d0, 0x258d4, 1141 0x258e0, 0x258e8, 1142 0x258f0, 0x258f0, 1143 0x258f8, 0x25a18, 1144 0x25a20, 0x25a28, 1145 0x25a30, 0x25a48, 1146 0x25a50, 0x25a54, 1147 0x25a60, 0x25a68, 1148 0x25a70, 0x25a70, 1149 0x25a78, 0x25a98, 1150 0x25aa0, 0x25aa8, 1151 0x25ab0, 0x25ac8, 1152 0x25ad0, 0x25ad4, 1153 0x25ae0, 0x25ae8, 1154 0x25af0, 0x25af0, 1155 0x25af8, 0x25c18, 1156 0x25c20, 0x25c20, 1157 0x25c28, 0x25c30, 1158 0x25c38, 0x25c38, 1159 0x25c80, 0x25c98, 1160 0x25ca0, 0x25ca8, 1161 0x25cb0, 0x25cc8, 1162 0x25cd0, 0x25cd4, 1163 0x25ce0, 0x25ce8, 1164 0x25cf0, 0x25cf0, 1165 0x25cf8, 0x25d7c, 1166 0x25e00, 0x25e04, 1167 0x26000, 0x2602c, 1168 0x26100, 0x2613c, 1169 0x26190, 0x261a0, 1170 0x261a8, 0x261b8, 1171 0x261c4, 0x261c8, 1172 0x26200, 0x26318, 1173 0x26400, 0x264b4, 1174 0x264c0, 0x26528, 1175 0x26540, 0x26614, 1176 0x27000, 0x27040, 1177 0x2704c, 0x27060, 1178 0x270c0, 0x270ec, 1179 0x27200, 0x27268, 1180 0x27270, 0x27284, 1181 0x272fc, 0x27388, 1182 0x27400, 0x27404, 1183 0x27500, 0x27500, 1184 0x27510, 0x27518, 1185 0x2752c, 0x27530, 1186 0x2753c, 0x2753c, 1187 0x27550, 0x27554, 1188 0x27600, 0x27600, 1189 0x27608, 0x2761c, 1190 0x27624, 0x27628, 1191 0x27630, 0x27634, 1192 0x2763c, 0x2763c, 1193 0x27700, 0x2771c, 1194 0x27780, 0x2778c, 1195 0x27800, 0x27818, 1196 0x27820, 0x27828, 1197 0x27830, 0x27848, 1198 0x27850, 0x27854, 1199 0x27860, 0x27868, 1200 0x27870, 0x27870, 1201 0x27878, 0x27898, 1202 0x278a0, 0x278a8, 1203 0x278b0, 0x278c8, 1204 0x278d0, 0x278d4, 1205 0x278e0, 0x278e8, 1206 0x278f0, 0x278f0, 1207 0x278f8, 0x27a18, 1208 0x27a20, 0x27a28, 1209 0x27a30, 0x27a48, 1210 0x27a50, 0x27a54, 1211 0x27a60, 0x27a68, 1212 0x27a70, 0x27a70, 1213 0x27a78, 0x27a98, 1214 0x27aa0, 0x27aa8, 1215 0x27ab0, 0x27ac8, 1216 0x27ad0, 0x27ad4, 1217 0x27ae0, 0x27ae8, 1218 0x27af0, 0x27af0, 1219 0x27af8, 0x27c18, 1220 0x27c20, 0x27c20, 1221 0x27c28, 0x27c30, 1222 0x27c38, 0x27c38, 1223 0x27c80, 0x27c98, 1224 0x27ca0, 0x27ca8, 1225 0x27cb0, 0x27cc8, 1226 0x27cd0, 0x27cd4, 1227 0x27ce0, 0x27ce8, 1228 0x27cf0, 0x27cf0, 1229 0x27cf8, 0x27d7c, 1230 0x27e00, 0x27e04, 1231 }; 1232 1233 static const unsigned int t4vf_reg_ranges[] = { 1234 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1235 VF_MPS_REG(A_MPS_VF_CTL), 1236 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1237 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1238 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1239 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1240 FW_T4VF_MBDATA_BASE_ADDR, 1241 FW_T4VF_MBDATA_BASE_ADDR + 1242 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1243 }; 1244 1245 static const unsigned int t5_reg_ranges[] = { 1246 0x1008, 0x10c0, 1247 0x10cc, 0x10f8, 1248 0x1100, 0x1100, 1249 0x110c, 0x1148, 1250 0x1180, 0x1184, 1251 0x1190, 0x1194, 1252 0x11a0, 0x11a4, 1253 0x11b0, 0x11b4, 1254 0x11fc, 0x123c, 1255 0x1280, 0x173c, 1256 0x1800, 0x18fc, 1257 0x3000, 0x3028, 1258 0x3060, 0x30b0, 1259 0x30b8, 0x30d8, 1260 0x30e0, 0x30fc, 1261 0x3140, 0x357c, 1262 0x35a8, 0x35cc, 1263 0x35ec, 0x35ec, 1264 0x3600, 0x5624, 1265 0x56cc, 0x56ec, 1266 0x56f4, 0x5720, 1267 0x5728, 0x575c, 1268 0x580c, 0x5814, 1269 0x5890, 0x589c, 1270 0x58a4, 0x58ac, 1271 0x58b8, 0x58bc, 1272 0x5940, 0x59c8, 1273 0x59d0, 0x59dc, 1274 0x59fc, 0x5a18, 1275 0x5a60, 0x5a70, 1276 0x5a80, 0x5a9c, 1277 0x5b94, 0x5bfc, 1278 0x6000, 0x6020, 1279 0x6028, 0x6040, 1280 0x6058, 0x609c, 1281 0x60a8, 0x614c, 1282 0x7700, 0x7798, 1283 0x77c0, 0x78fc, 1284 0x7b00, 0x7b58, 1285 0x7b60, 0x7b84, 1286 0x7b8c, 0x7c54, 1287 0x7d00, 0x7d38, 1288 0x7d40, 0x7d80, 1289 0x7d8c, 0x7ddc, 1290 0x7de4, 0x7e04, 1291 0x7e10, 0x7e1c, 1292 0x7e24, 0x7e38, 1293 0x7e40, 0x7e44, 1294 0x7e4c, 0x7e78, 1295 0x7e80, 0x7edc, 1296 0x7ee8, 0x7efc, 1297 0x8dc0, 0x8de0, 1298 0x8df8, 0x8e04, 1299 0x8e10, 0x8e84, 1300 0x8ea0, 0x8f84, 1301 0x8fc0, 0x9058, 1302 0x9060, 0x9060, 1303 0x9068, 0x90f8, 1304 0x9400, 0x9408, 1305 0x9410, 0x9470, 1306 0x9600, 0x9600, 1307 0x9608, 0x9638, 1308 0x9640, 0x96f4, 1309 0x9800, 0x9808, 1310 0x9820, 0x983c, 1311 0x9850, 0x9864, 1312 0x9c00, 0x9c6c, 1313 0x9c80, 0x9cec, 1314 0x9d00, 0x9d6c, 1315 0x9d80, 0x9dec, 1316 0x9e00, 0x9e6c, 1317 0x9e80, 0x9eec, 1318 0x9f00, 0x9f6c, 1319 0x9f80, 0xa020, 1320 0xd004, 0xd004, 1321 0xd010, 0xd03c, 1322 0xdfc0, 0xdfe0, 1323 0xe000, 0x1106c, 1324 0x11074, 0x11088, 1325 0x1109c, 0x1117c, 1326 0x11190, 0x11204, 1327 0x19040, 0x1906c, 1328 0x19078, 0x19080, 1329 0x1908c, 0x190e8, 1330 0x190f0, 0x190f8, 1331 0x19100, 0x19110, 1332 0x19120, 0x19124, 1333 0x19150, 0x19194, 1334 0x1919c, 0x191b0, 1335 0x191d0, 0x191e8, 1336 0x19238, 0x19290, 1337 0x193f8, 0x19428, 1338 0x19430, 0x19444, 1339 0x1944c, 0x1946c, 1340 0x19474, 0x19474, 1341 0x19490, 0x194cc, 1342 0x194f0, 0x194f8, 1343 0x19c00, 0x19c08, 1344 0x19c10, 0x19c60, 1345 0x19c94, 0x19ce4, 1346 0x19cf0, 0x19d40, 1347 0x19d50, 0x19d94, 1348 0x19da0, 0x19de8, 1349 0x19df0, 0x19e10, 1350 0x19e50, 0x19e90, 1351 0x19ea0, 0x19f24, 1352 0x19f34, 0x19f34, 1353 0x19f40, 0x19f50, 1354 0x19f90, 0x19fb4, 1355 0x19fc4, 0x19fe4, 1356 0x1a000, 0x1a004, 1357 0x1a010, 0x1a06c, 1358 0x1a0b0, 0x1a0e4, 1359 0x1a0ec, 0x1a0f8, 1360 0x1a100, 0x1a108, 1361 0x1a114, 0x1a120, 1362 0x1a128, 0x1a130, 1363 0x1a138, 0x1a138, 1364 0x1a190, 0x1a1c4, 1365 0x1a1fc, 0x1a1fc, 1366 0x1e008, 0x1e00c, 1367 0x1e040, 0x1e044, 1368 0x1e04c, 0x1e04c, 1369 0x1e284, 0x1e290, 1370 0x1e2c0, 0x1e2c0, 1371 0x1e2e0, 0x1e2e0, 1372 0x1e300, 0x1e384, 1373 0x1e3c0, 0x1e3c8, 1374 0x1e408, 0x1e40c, 1375 0x1e440, 0x1e444, 1376 0x1e44c, 0x1e44c, 1377 0x1e684, 0x1e690, 1378 0x1e6c0, 0x1e6c0, 1379 0x1e6e0, 0x1e6e0, 1380 0x1e700, 0x1e784, 1381 0x1e7c0, 0x1e7c8, 1382 0x1e808, 0x1e80c, 1383 0x1e840, 0x1e844, 1384 0x1e84c, 0x1e84c, 1385 0x1ea84, 0x1ea90, 1386 0x1eac0, 0x1eac0, 1387 0x1eae0, 0x1eae0, 1388 0x1eb00, 0x1eb84, 1389 0x1ebc0, 0x1ebc8, 1390 0x1ec08, 0x1ec0c, 1391 0x1ec40, 0x1ec44, 1392 0x1ec4c, 0x1ec4c, 1393 0x1ee84, 0x1ee90, 1394 0x1eec0, 0x1eec0, 1395 0x1eee0, 0x1eee0, 1396 0x1ef00, 0x1ef84, 1397 0x1efc0, 0x1efc8, 1398 0x1f008, 0x1f00c, 1399 0x1f040, 0x1f044, 1400 0x1f04c, 0x1f04c, 1401 0x1f284, 0x1f290, 1402 0x1f2c0, 0x1f2c0, 1403 0x1f2e0, 0x1f2e0, 1404 0x1f300, 0x1f384, 1405 0x1f3c0, 0x1f3c8, 1406 0x1f408, 0x1f40c, 1407 0x1f440, 0x1f444, 1408 0x1f44c, 0x1f44c, 1409 0x1f684, 0x1f690, 1410 0x1f6c0, 0x1f6c0, 1411 0x1f6e0, 0x1f6e0, 1412 0x1f700, 0x1f784, 1413 0x1f7c0, 0x1f7c8, 1414 0x1f808, 0x1f80c, 1415 0x1f840, 0x1f844, 1416 0x1f84c, 0x1f84c, 1417 0x1fa84, 0x1fa90, 1418 0x1fac0, 0x1fac0, 1419 0x1fae0, 0x1fae0, 1420 0x1fb00, 0x1fb84, 1421 0x1fbc0, 0x1fbc8, 1422 0x1fc08, 0x1fc0c, 1423 0x1fc40, 0x1fc44, 1424 0x1fc4c, 0x1fc4c, 1425 0x1fe84, 0x1fe90, 1426 0x1fec0, 0x1fec0, 1427 0x1fee0, 0x1fee0, 1428 0x1ff00, 0x1ff84, 1429 0x1ffc0, 0x1ffc8, 1430 0x30000, 0x30030, 1431 0x30100, 0x30144, 1432 0x30190, 0x301a0, 1433 0x301a8, 0x301b8, 1434 0x301c4, 0x301c8, 1435 0x301d0, 0x301d0, 1436 0x30200, 0x30318, 1437 0x30400, 0x304b4, 1438 0x304c0, 0x3052c, 1439 0x30540, 0x3061c, 1440 0x30800, 0x30828, 1441 0x30834, 0x30834, 1442 0x308c0, 0x30908, 1443 0x30910, 0x309ac, 1444 0x30a00, 0x30a14, 1445 0x30a1c, 0x30a2c, 1446 0x30a44, 0x30a50, 1447 0x30a74, 0x30a74, 1448 0x30a7c, 0x30afc, 1449 0x30b08, 0x30c24, 1450 0x30d00, 0x30d00, 1451 0x30d08, 0x30d14, 1452 0x30d1c, 0x30d20, 1453 0x30d3c, 0x30d3c, 1454 0x30d48, 0x30d50, 1455 0x31200, 0x3120c, 1456 0x31220, 0x31220, 1457 0x31240, 0x31240, 1458 0x31600, 0x3160c, 1459 0x31a00, 0x31a1c, 1460 0x31e00, 0x31e20, 1461 0x31e38, 0x31e3c, 1462 0x31e80, 0x31e80, 1463 0x31e88, 0x31ea8, 1464 0x31eb0, 0x31eb4, 1465 0x31ec8, 0x31ed4, 1466 0x31fb8, 0x32004, 1467 0x32200, 0x32200, 1468 0x32208, 0x32240, 1469 0x32248, 0x32280, 1470 0x32288, 0x322c0, 1471 0x322c8, 0x322fc, 1472 0x32600, 0x32630, 1473 0x32a00, 0x32abc, 1474 0x32b00, 0x32b10, 1475 0x32b20, 0x32b30, 1476 0x32b40, 0x32b50, 1477 0x32b60, 0x32b70, 1478 0x33000, 0x33028, 1479 0x33030, 0x33048, 1480 0x33060, 0x33068, 1481 0x33070, 0x3309c, 1482 0x330f0, 0x33128, 1483 0x33130, 0x33148, 1484 0x33160, 0x33168, 1485 0x33170, 0x3319c, 1486 0x331f0, 0x33238, 1487 0x33240, 0x33240, 1488 0x33248, 0x33250, 1489 0x3325c, 0x33264, 1490 0x33270, 0x332b8, 1491 0x332c0, 0x332e4, 1492 0x332f8, 0x33338, 1493 0x33340, 0x33340, 1494 0x33348, 0x33350, 1495 0x3335c, 0x33364, 1496 0x33370, 0x333b8, 1497 0x333c0, 0x333e4, 1498 0x333f8, 0x33428, 1499 0x33430, 0x33448, 1500 0x33460, 0x33468, 1501 0x33470, 0x3349c, 1502 0x334f0, 0x33528, 1503 0x33530, 0x33548, 1504 0x33560, 0x33568, 1505 0x33570, 0x3359c, 1506 0x335f0, 0x33638, 1507 0x33640, 0x33640, 1508 0x33648, 0x33650, 1509 0x3365c, 0x33664, 1510 0x33670, 0x336b8, 1511 0x336c0, 0x336e4, 1512 0x336f8, 0x33738, 1513 0x33740, 0x33740, 1514 0x33748, 0x33750, 1515 0x3375c, 0x33764, 1516 0x33770, 0x337b8, 1517 0x337c0, 0x337e4, 1518 0x337f8, 0x337fc, 1519 0x33814, 0x33814, 1520 0x3382c, 0x3382c, 1521 0x33880, 0x3388c, 1522 0x338e8, 0x338ec, 1523 0x33900, 0x33928, 1524 0x33930, 0x33948, 1525 0x33960, 0x33968, 1526 0x33970, 0x3399c, 1527 0x339f0, 0x33a38, 1528 0x33a40, 0x33a40, 1529 0x33a48, 0x33a50, 1530 0x33a5c, 0x33a64, 1531 0x33a70, 0x33ab8, 1532 0x33ac0, 0x33ae4, 1533 0x33af8, 0x33b10, 1534 0x33b28, 0x33b28, 1535 0x33b3c, 0x33b50, 1536 0x33bf0, 0x33c10, 1537 0x33c28, 0x33c28, 1538 0x33c3c, 0x33c50, 1539 0x33cf0, 0x33cfc, 1540 0x34000, 0x34030, 1541 0x34100, 0x34144, 1542 0x34190, 0x341a0, 1543 0x341a8, 0x341b8, 1544 0x341c4, 0x341c8, 1545 0x341d0, 0x341d0, 1546 0x34200, 0x34318, 1547 0x34400, 0x344b4, 1548 0x344c0, 0x3452c, 1549 0x34540, 0x3461c, 1550 0x34800, 0x34828, 1551 0x34834, 0x34834, 1552 0x348c0, 0x34908, 1553 0x34910, 0x349ac, 1554 0x34a00, 0x34a14, 1555 0x34a1c, 0x34a2c, 1556 0x34a44, 0x34a50, 1557 0x34a74, 0x34a74, 1558 0x34a7c, 0x34afc, 1559 0x34b08, 0x34c24, 1560 0x34d00, 0x34d00, 1561 0x34d08, 0x34d14, 1562 0x34d1c, 0x34d20, 1563 0x34d3c, 0x34d3c, 1564 0x34d48, 0x34d50, 1565 0x35200, 0x3520c, 1566 0x35220, 0x35220, 1567 0x35240, 0x35240, 1568 0x35600, 0x3560c, 1569 0x35a00, 0x35a1c, 1570 0x35e00, 0x35e20, 1571 0x35e38, 0x35e3c, 1572 0x35e80, 0x35e80, 1573 0x35e88, 0x35ea8, 1574 0x35eb0, 0x35eb4, 1575 0x35ec8, 0x35ed4, 1576 0x35fb8, 0x36004, 1577 0x36200, 0x36200, 1578 0x36208, 0x36240, 1579 0x36248, 0x36280, 1580 0x36288, 0x362c0, 1581 0x362c8, 0x362fc, 1582 0x36600, 0x36630, 1583 0x36a00, 0x36abc, 1584 0x36b00, 0x36b10, 1585 0x36b20, 0x36b30, 1586 0x36b40, 0x36b50, 1587 0x36b60, 0x36b70, 1588 0x37000, 0x37028, 1589 0x37030, 0x37048, 1590 0x37060, 0x37068, 1591 0x37070, 0x3709c, 1592 0x370f0, 0x37128, 1593 0x37130, 0x37148, 1594 0x37160, 0x37168, 1595 0x37170, 0x3719c, 1596 0x371f0, 0x37238, 1597 0x37240, 0x37240, 1598 0x37248, 0x37250, 1599 0x3725c, 0x37264, 1600 0x37270, 0x372b8, 1601 0x372c0, 0x372e4, 1602 0x372f8, 0x37338, 1603 0x37340, 0x37340, 1604 0x37348, 0x37350, 1605 0x3735c, 0x37364, 1606 0x37370, 0x373b8, 1607 0x373c0, 0x373e4, 1608 0x373f8, 0x37428, 1609 0x37430, 0x37448, 1610 0x37460, 0x37468, 1611 0x37470, 0x3749c, 1612 0x374f0, 0x37528, 1613 0x37530, 0x37548, 1614 0x37560, 0x37568, 1615 0x37570, 0x3759c, 1616 0x375f0, 0x37638, 1617 0x37640, 0x37640, 1618 0x37648, 0x37650, 1619 0x3765c, 0x37664, 1620 0x37670, 0x376b8, 1621 0x376c0, 0x376e4, 1622 0x376f8, 0x37738, 1623 0x37740, 0x37740, 1624 0x37748, 0x37750, 1625 0x3775c, 0x37764, 1626 0x37770, 0x377b8, 1627 0x377c0, 0x377e4, 1628 0x377f8, 0x377fc, 1629 0x37814, 0x37814, 1630 0x3782c, 0x3782c, 1631 0x37880, 0x3788c, 1632 0x378e8, 0x378ec, 1633 0x37900, 0x37928, 1634 0x37930, 0x37948, 1635 0x37960, 0x37968, 1636 0x37970, 0x3799c, 1637 0x379f0, 0x37a38, 1638 0x37a40, 0x37a40, 1639 0x37a48, 0x37a50, 1640 0x37a5c, 0x37a64, 1641 0x37a70, 0x37ab8, 1642 0x37ac0, 0x37ae4, 1643 0x37af8, 0x37b10, 1644 0x37b28, 0x37b28, 1645 0x37b3c, 0x37b50, 1646 0x37bf0, 0x37c10, 1647 0x37c28, 0x37c28, 1648 0x37c3c, 0x37c50, 1649 0x37cf0, 0x37cfc, 1650 0x38000, 0x38030, 1651 0x38100, 0x38144, 1652 0x38190, 0x381a0, 1653 0x381a8, 0x381b8, 1654 0x381c4, 0x381c8, 1655 0x381d0, 0x381d0, 1656 0x38200, 0x38318, 1657 0x38400, 0x384b4, 1658 0x384c0, 0x3852c, 1659 0x38540, 0x3861c, 1660 0x38800, 0x38828, 1661 0x38834, 0x38834, 1662 0x388c0, 0x38908, 1663 0x38910, 0x389ac, 1664 0x38a00, 0x38a14, 1665 0x38a1c, 0x38a2c, 1666 0x38a44, 0x38a50, 1667 0x38a74, 0x38a74, 1668 0x38a7c, 0x38afc, 1669 0x38b08, 0x38c24, 1670 0x38d00, 0x38d00, 1671 0x38d08, 0x38d14, 1672 0x38d1c, 0x38d20, 1673 0x38d3c, 0x38d3c, 1674 0x38d48, 0x38d50, 1675 0x39200, 0x3920c, 1676 0x39220, 0x39220, 1677 0x39240, 0x39240, 1678 0x39600, 0x3960c, 1679 0x39a00, 0x39a1c, 1680 0x39e00, 0x39e20, 1681 0x39e38, 0x39e3c, 1682 0x39e80, 0x39e80, 1683 0x39e88, 0x39ea8, 1684 0x39eb0, 0x39eb4, 1685 0x39ec8, 0x39ed4, 1686 0x39fb8, 0x3a004, 1687 0x3a200, 0x3a200, 1688 0x3a208, 0x3a240, 1689 0x3a248, 0x3a280, 1690 0x3a288, 0x3a2c0, 1691 0x3a2c8, 0x3a2fc, 1692 0x3a600, 0x3a630, 1693 0x3aa00, 0x3aabc, 1694 0x3ab00, 0x3ab10, 1695 0x3ab20, 0x3ab30, 1696 0x3ab40, 0x3ab50, 1697 0x3ab60, 0x3ab70, 1698 0x3b000, 0x3b028, 1699 0x3b030, 0x3b048, 1700 0x3b060, 0x3b068, 1701 0x3b070, 0x3b09c, 1702 0x3b0f0, 0x3b128, 1703 0x3b130, 0x3b148, 1704 0x3b160, 0x3b168, 1705 0x3b170, 0x3b19c, 1706 0x3b1f0, 0x3b238, 1707 0x3b240, 0x3b240, 1708 0x3b248, 0x3b250, 1709 0x3b25c, 0x3b264, 1710 0x3b270, 0x3b2b8, 1711 0x3b2c0, 0x3b2e4, 1712 0x3b2f8, 0x3b338, 1713 0x3b340, 0x3b340, 1714 0x3b348, 0x3b350, 1715 0x3b35c, 0x3b364, 1716 0x3b370, 0x3b3b8, 1717 0x3b3c0, 0x3b3e4, 1718 0x3b3f8, 0x3b428, 1719 0x3b430, 0x3b448, 1720 0x3b460, 0x3b468, 1721 0x3b470, 0x3b49c, 1722 0x3b4f0, 0x3b528, 1723 0x3b530, 0x3b548, 1724 0x3b560, 0x3b568, 1725 0x3b570, 0x3b59c, 1726 0x3b5f0, 0x3b638, 1727 0x3b640, 0x3b640, 1728 0x3b648, 0x3b650, 1729 0x3b65c, 0x3b664, 1730 0x3b670, 0x3b6b8, 1731 0x3b6c0, 0x3b6e4, 1732 0x3b6f8, 0x3b738, 1733 0x3b740, 0x3b740, 1734 0x3b748, 0x3b750, 1735 0x3b75c, 0x3b764, 1736 0x3b770, 0x3b7b8, 1737 0x3b7c0, 0x3b7e4, 1738 0x3b7f8, 0x3b7fc, 1739 0x3b814, 0x3b814, 1740 0x3b82c, 0x3b82c, 1741 0x3b880, 0x3b88c, 1742 0x3b8e8, 0x3b8ec, 1743 0x3b900, 0x3b928, 1744 0x3b930, 0x3b948, 1745 0x3b960, 0x3b968, 1746 0x3b970, 0x3b99c, 1747 0x3b9f0, 0x3ba38, 1748 0x3ba40, 0x3ba40, 1749 0x3ba48, 0x3ba50, 1750 0x3ba5c, 0x3ba64, 1751 0x3ba70, 0x3bab8, 1752 0x3bac0, 0x3bae4, 1753 0x3baf8, 0x3bb10, 1754 0x3bb28, 0x3bb28, 1755 0x3bb3c, 0x3bb50, 1756 0x3bbf0, 0x3bc10, 1757 0x3bc28, 0x3bc28, 1758 0x3bc3c, 0x3bc50, 1759 0x3bcf0, 0x3bcfc, 1760 0x3c000, 0x3c030, 1761 0x3c100, 0x3c144, 1762 0x3c190, 0x3c1a0, 1763 0x3c1a8, 0x3c1b8, 1764 0x3c1c4, 0x3c1c8, 1765 0x3c1d0, 0x3c1d0, 1766 0x3c200, 0x3c318, 1767 0x3c400, 0x3c4b4, 1768 0x3c4c0, 0x3c52c, 1769 0x3c540, 0x3c61c, 1770 0x3c800, 0x3c828, 1771 0x3c834, 0x3c834, 1772 0x3c8c0, 0x3c908, 1773 0x3c910, 0x3c9ac, 1774 0x3ca00, 0x3ca14, 1775 0x3ca1c, 0x3ca2c, 1776 0x3ca44, 0x3ca50, 1777 0x3ca74, 0x3ca74, 1778 0x3ca7c, 0x3cafc, 1779 0x3cb08, 0x3cc24, 1780 0x3cd00, 0x3cd00, 1781 0x3cd08, 0x3cd14, 1782 0x3cd1c, 0x3cd20, 1783 0x3cd3c, 0x3cd3c, 1784 0x3cd48, 0x3cd50, 1785 0x3d200, 0x3d20c, 1786 0x3d220, 0x3d220, 1787 0x3d240, 0x3d240, 1788 0x3d600, 0x3d60c, 1789 0x3da00, 0x3da1c, 1790 0x3de00, 0x3de20, 1791 0x3de38, 0x3de3c, 1792 0x3de80, 0x3de80, 1793 0x3de88, 0x3dea8, 1794 0x3deb0, 0x3deb4, 1795 0x3dec8, 0x3ded4, 1796 0x3dfb8, 0x3e004, 1797 0x3e200, 0x3e200, 1798 0x3e208, 0x3e240, 1799 0x3e248, 0x3e280, 1800 0x3e288, 0x3e2c0, 1801 0x3e2c8, 0x3e2fc, 1802 0x3e600, 0x3e630, 1803 0x3ea00, 0x3eabc, 1804 0x3eb00, 0x3eb10, 1805 0x3eb20, 0x3eb30, 1806 0x3eb40, 0x3eb50, 1807 0x3eb60, 0x3eb70, 1808 0x3f000, 0x3f028, 1809 0x3f030, 0x3f048, 1810 0x3f060, 0x3f068, 1811 0x3f070, 0x3f09c, 1812 0x3f0f0, 0x3f128, 1813 0x3f130, 0x3f148, 1814 0x3f160, 0x3f168, 1815 0x3f170, 0x3f19c, 1816 0x3f1f0, 0x3f238, 1817 0x3f240, 0x3f240, 1818 0x3f248, 0x3f250, 1819 0x3f25c, 0x3f264, 1820 0x3f270, 0x3f2b8, 1821 0x3f2c0, 0x3f2e4, 1822 0x3f2f8, 0x3f338, 1823 0x3f340, 0x3f340, 1824 0x3f348, 0x3f350, 1825 0x3f35c, 0x3f364, 1826 0x3f370, 0x3f3b8, 1827 0x3f3c0, 0x3f3e4, 1828 0x3f3f8, 0x3f428, 1829 0x3f430, 0x3f448, 1830 0x3f460, 0x3f468, 1831 0x3f470, 0x3f49c, 1832 0x3f4f0, 0x3f528, 1833 0x3f530, 0x3f548, 1834 0x3f560, 0x3f568, 1835 0x3f570, 0x3f59c, 1836 0x3f5f0, 0x3f638, 1837 0x3f640, 0x3f640, 1838 0x3f648, 0x3f650, 1839 0x3f65c, 0x3f664, 1840 0x3f670, 0x3f6b8, 1841 0x3f6c0, 0x3f6e4, 1842 0x3f6f8, 0x3f738, 1843 0x3f740, 0x3f740, 1844 0x3f748, 0x3f750, 1845 0x3f75c, 0x3f764, 1846 0x3f770, 0x3f7b8, 1847 0x3f7c0, 0x3f7e4, 1848 0x3f7f8, 0x3f7fc, 1849 0x3f814, 0x3f814, 1850 0x3f82c, 0x3f82c, 1851 0x3f880, 0x3f88c, 1852 0x3f8e8, 0x3f8ec, 1853 0x3f900, 0x3f928, 1854 0x3f930, 0x3f948, 1855 0x3f960, 0x3f968, 1856 0x3f970, 0x3f99c, 1857 0x3f9f0, 0x3fa38, 1858 0x3fa40, 0x3fa40, 1859 0x3fa48, 0x3fa50, 1860 0x3fa5c, 0x3fa64, 1861 0x3fa70, 0x3fab8, 1862 0x3fac0, 0x3fae4, 1863 0x3faf8, 0x3fb10, 1864 0x3fb28, 0x3fb28, 1865 0x3fb3c, 0x3fb50, 1866 0x3fbf0, 0x3fc10, 1867 0x3fc28, 0x3fc28, 1868 0x3fc3c, 0x3fc50, 1869 0x3fcf0, 0x3fcfc, 1870 0x40000, 0x4000c, 1871 0x40040, 0x40050, 1872 0x40060, 0x40068, 1873 0x4007c, 0x4008c, 1874 0x40094, 0x400b0, 1875 0x400c0, 0x40144, 1876 0x40180, 0x4018c, 1877 0x40200, 0x40254, 1878 0x40260, 0x40264, 1879 0x40270, 0x40288, 1880 0x40290, 0x40298, 1881 0x402ac, 0x402c8, 1882 0x402d0, 0x402e0, 1883 0x402f0, 0x402f0, 1884 0x40300, 0x4033c, 1885 0x403f8, 0x403fc, 1886 0x41304, 0x413c4, 1887 0x41400, 0x4140c, 1888 0x41414, 0x4141c, 1889 0x41480, 0x414d0, 1890 0x44000, 0x44054, 1891 0x4405c, 0x44078, 1892 0x440c0, 0x44174, 1893 0x44180, 0x441ac, 1894 0x441b4, 0x441b8, 1895 0x441c0, 0x44254, 1896 0x4425c, 0x44278, 1897 0x442c0, 0x44374, 1898 0x44380, 0x443ac, 1899 0x443b4, 0x443b8, 1900 0x443c0, 0x44454, 1901 0x4445c, 0x44478, 1902 0x444c0, 0x44574, 1903 0x44580, 0x445ac, 1904 0x445b4, 0x445b8, 1905 0x445c0, 0x44654, 1906 0x4465c, 0x44678, 1907 0x446c0, 0x44774, 1908 0x44780, 0x447ac, 1909 0x447b4, 0x447b8, 1910 0x447c0, 0x44854, 1911 0x4485c, 0x44878, 1912 0x448c0, 0x44974, 1913 0x44980, 0x449ac, 1914 0x449b4, 0x449b8, 1915 0x449c0, 0x449fc, 1916 0x45000, 0x45004, 1917 0x45010, 0x45030, 1918 0x45040, 0x45060, 1919 0x45068, 0x45068, 1920 0x45080, 0x45084, 1921 0x450a0, 0x450b0, 1922 0x45200, 0x45204, 1923 0x45210, 0x45230, 1924 0x45240, 0x45260, 1925 0x45268, 0x45268, 1926 0x45280, 0x45284, 1927 0x452a0, 0x452b0, 1928 0x460c0, 0x460e4, 1929 0x47000, 0x4703c, 1930 0x47044, 0x4708c, 1931 0x47200, 0x47250, 1932 0x47400, 0x47408, 1933 0x47414, 0x47420, 1934 0x47600, 0x47618, 1935 0x47800, 0x47814, 1936 0x48000, 0x4800c, 1937 0x48040, 0x48050, 1938 0x48060, 0x48068, 1939 0x4807c, 0x4808c, 1940 0x48094, 0x480b0, 1941 0x480c0, 0x48144, 1942 0x48180, 0x4818c, 1943 0x48200, 0x48254, 1944 0x48260, 0x48264, 1945 0x48270, 0x48288, 1946 0x48290, 0x48298, 1947 0x482ac, 0x482c8, 1948 0x482d0, 0x482e0, 1949 0x482f0, 0x482f0, 1950 0x48300, 0x4833c, 1951 0x483f8, 0x483fc, 1952 0x49304, 0x493c4, 1953 0x49400, 0x4940c, 1954 0x49414, 0x4941c, 1955 0x49480, 0x494d0, 1956 0x4c000, 0x4c054, 1957 0x4c05c, 0x4c078, 1958 0x4c0c0, 0x4c174, 1959 0x4c180, 0x4c1ac, 1960 0x4c1b4, 0x4c1b8, 1961 0x4c1c0, 0x4c254, 1962 0x4c25c, 0x4c278, 1963 0x4c2c0, 0x4c374, 1964 0x4c380, 0x4c3ac, 1965 0x4c3b4, 0x4c3b8, 1966 0x4c3c0, 0x4c454, 1967 0x4c45c, 0x4c478, 1968 0x4c4c0, 0x4c574, 1969 0x4c580, 0x4c5ac, 1970 0x4c5b4, 0x4c5b8, 1971 0x4c5c0, 0x4c654, 1972 0x4c65c, 0x4c678, 1973 0x4c6c0, 0x4c774, 1974 0x4c780, 0x4c7ac, 1975 0x4c7b4, 0x4c7b8, 1976 0x4c7c0, 0x4c854, 1977 0x4c85c, 0x4c878, 1978 0x4c8c0, 0x4c974, 1979 0x4c980, 0x4c9ac, 1980 0x4c9b4, 0x4c9b8, 1981 0x4c9c0, 0x4c9fc, 1982 0x4d000, 0x4d004, 1983 0x4d010, 0x4d030, 1984 0x4d040, 0x4d060, 1985 0x4d068, 0x4d068, 1986 0x4d080, 0x4d084, 1987 0x4d0a0, 0x4d0b0, 1988 0x4d200, 0x4d204, 1989 0x4d210, 0x4d230, 1990 0x4d240, 0x4d260, 1991 0x4d268, 0x4d268, 1992 0x4d280, 0x4d284, 1993 0x4d2a0, 0x4d2b0, 1994 0x4e0c0, 0x4e0e4, 1995 0x4f000, 0x4f03c, 1996 0x4f044, 0x4f08c, 1997 0x4f200, 0x4f250, 1998 0x4f400, 0x4f408, 1999 0x4f414, 0x4f420, 2000 0x4f600, 0x4f618, 2001 0x4f800, 0x4f814, 2002 0x50000, 0x50084, 2003 0x50090, 0x500cc, 2004 0x50400, 0x50400, 2005 0x50800, 0x50884, 2006 0x50890, 0x508cc, 2007 0x50c00, 0x50c00, 2008 0x51000, 0x5101c, 2009 0x51300, 0x51308, 2010 }; 2011 2012 static const unsigned int t5vf_reg_ranges[] = { 2013 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2014 VF_MPS_REG(A_MPS_VF_CTL), 2015 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2016 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2017 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2018 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2019 FW_T4VF_MBDATA_BASE_ADDR, 2020 FW_T4VF_MBDATA_BASE_ADDR + 2021 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2022 }; 2023 2024 static const unsigned int t6_reg_ranges[] = { 2025 0x1008, 0x101c, 2026 0x1024, 0x10a8, 2027 0x10b4, 0x10f8, 2028 0x1100, 0x1114, 2029 0x111c, 0x112c, 2030 0x1138, 0x113c, 2031 0x1144, 0x114c, 2032 0x1180, 0x1184, 2033 0x1190, 0x1194, 2034 0x11a0, 0x11a4, 2035 0x11b0, 0x11b4, 2036 0x11fc, 0x1274, 2037 0x1280, 0x133c, 2038 0x1800, 0x18fc, 2039 0x3000, 0x302c, 2040 0x3060, 0x30b0, 2041 0x30b8, 0x30d8, 2042 0x30e0, 0x30fc, 2043 0x3140, 0x357c, 2044 0x35a8, 0x35cc, 2045 0x35ec, 0x35ec, 2046 0x3600, 0x5624, 2047 0x56cc, 0x56ec, 2048 0x56f4, 0x5720, 2049 0x5728, 0x575c, 2050 0x580c, 0x5814, 2051 0x5890, 0x589c, 2052 0x58a4, 0x58ac, 2053 0x58b8, 0x58bc, 2054 0x5940, 0x595c, 2055 0x5980, 0x598c, 2056 0x59b0, 0x59c8, 2057 0x59d0, 0x59dc, 2058 0x59fc, 0x5a18, 2059 0x5a60, 0x5a6c, 2060 0x5a80, 0x5a8c, 2061 0x5a94, 0x5a9c, 2062 0x5b94, 0x5bfc, 2063 0x5c10, 0x5e48, 2064 0x5e50, 0x5e94, 2065 0x5ea0, 0x5eb0, 2066 0x5ec0, 0x5ec0, 2067 0x5ec8, 0x5ed0, 2068 0x5ee0, 0x5ee0, 2069 0x5ef0, 0x5ef0, 2070 0x5f00, 0x5f00, 2071 0x6000, 0x6020, 2072 0x6028, 0x6040, 2073 0x6058, 0x609c, 2074 0x60a8, 0x619c, 2075 0x7700, 0x7798, 2076 0x77c0, 0x7880, 2077 0x78cc, 0x78fc, 2078 0x7b00, 0x7b58, 2079 0x7b60, 0x7b84, 2080 0x7b8c, 0x7c54, 2081 0x7d00, 0x7d38, 2082 0x7d40, 0x7d84, 2083 0x7d8c, 0x7ddc, 2084 0x7de4, 0x7e04, 2085 0x7e10, 0x7e1c, 2086 0x7e24, 0x7e38, 2087 0x7e40, 0x7e44, 2088 0x7e4c, 0x7e78, 2089 0x7e80, 0x7edc, 2090 0x7ee8, 0x7efc, 2091 0x8dc0, 0x8de4, 2092 0x8df8, 0x8e04, 2093 0x8e10, 0x8e84, 2094 0x8ea0, 0x8f88, 2095 0x8fb8, 0x9058, 2096 0x9060, 0x9060, 2097 0x9068, 0x90f8, 2098 0x9100, 0x9124, 2099 0x9400, 0x9470, 2100 0x9600, 0x9600, 2101 0x9608, 0x9638, 2102 0x9640, 0x9704, 2103 0x9710, 0x971c, 2104 0x9800, 0x9808, 2105 0x9820, 0x983c, 2106 0x9850, 0x9864, 2107 0x9c00, 0x9c6c, 2108 0x9c80, 0x9cec, 2109 0x9d00, 0x9d6c, 2110 0x9d80, 0x9dec, 2111 0x9e00, 0x9e6c, 2112 0x9e80, 0x9eec, 2113 0x9f00, 0x9f6c, 2114 0x9f80, 0xa020, 2115 0xd004, 0xd03c, 2116 0xd100, 0xd118, 2117 0xd200, 0xd214, 2118 0xd220, 0xd234, 2119 0xd240, 0xd254, 2120 0xd260, 0xd274, 2121 0xd280, 0xd294, 2122 0xd2a0, 0xd2b4, 2123 0xd2c0, 0xd2d4, 2124 0xd2e0, 0xd2f4, 2125 0xd300, 0xd31c, 2126 0xdfc0, 0xdfe0, 2127 0xe000, 0xf008, 2128 0xf010, 0xf018, 2129 0xf020, 0xf028, 2130 0x11000, 0x11014, 2131 0x11048, 0x1106c, 2132 0x11074, 0x11088, 2133 0x11098, 0x11120, 2134 0x1112c, 0x1117c, 2135 0x11190, 0x112e0, 2136 0x11300, 0x1130c, 2137 0x12000, 0x1206c, 2138 0x19040, 0x1906c, 2139 0x19078, 0x19080, 2140 0x1908c, 0x190e8, 2141 0x190f0, 0x190f8, 2142 0x19100, 0x19110, 2143 0x19120, 0x19124, 2144 0x19150, 0x19194, 2145 0x1919c, 0x191b0, 2146 0x191d0, 0x191e8, 2147 0x19238, 0x19290, 2148 0x192a4, 0x192b0, 2149 0x192bc, 0x192bc, 2150 0x19348, 0x1934c, 2151 0x193f8, 0x19418, 2152 0x19420, 0x19428, 2153 0x19430, 0x19444, 2154 0x1944c, 0x1946c, 2155 0x19474, 0x19474, 2156 0x19490, 0x194cc, 2157 0x194f0, 0x194f8, 2158 0x19c00, 0x19c48, 2159 0x19c50, 0x19c80, 2160 0x19c94, 0x19c98, 2161 0x19ca0, 0x19cbc, 2162 0x19ce4, 0x19ce4, 2163 0x19cf0, 0x19cf8, 2164 0x19d00, 0x19d28, 2165 0x19d50, 0x19d78, 2166 0x19d94, 0x19d98, 2167 0x19da0, 0x19dc8, 2168 0x19df0, 0x19e10, 2169 0x19e50, 0x19e6c, 2170 0x19ea0, 0x19ebc, 2171 0x19ec4, 0x19ef4, 2172 0x19f04, 0x19f2c, 2173 0x19f34, 0x19f34, 2174 0x19f40, 0x19f50, 2175 0x19f90, 0x19fac, 2176 0x19fc4, 0x19fc8, 2177 0x19fd0, 0x19fe4, 2178 0x1a000, 0x1a004, 2179 0x1a010, 0x1a06c, 2180 0x1a0b0, 0x1a0e4, 2181 0x1a0ec, 0x1a0f8, 2182 0x1a100, 0x1a108, 2183 0x1a114, 0x1a120, 2184 0x1a128, 0x1a130, 2185 0x1a138, 0x1a138, 2186 0x1a190, 0x1a1c4, 2187 0x1a1fc, 0x1a1fc, 2188 0x1e008, 0x1e00c, 2189 0x1e040, 0x1e044, 2190 0x1e04c, 0x1e04c, 2191 0x1e284, 0x1e290, 2192 0x1e2c0, 0x1e2c0, 2193 0x1e2e0, 0x1e2e0, 2194 0x1e300, 0x1e384, 2195 0x1e3c0, 0x1e3c8, 2196 0x1e408, 0x1e40c, 2197 0x1e440, 0x1e444, 2198 0x1e44c, 0x1e44c, 2199 0x1e684, 0x1e690, 2200 0x1e6c0, 0x1e6c0, 2201 0x1e6e0, 0x1e6e0, 2202 0x1e700, 0x1e784, 2203 0x1e7c0, 0x1e7c8, 2204 0x1e808, 0x1e80c, 2205 0x1e840, 0x1e844, 2206 0x1e84c, 0x1e84c, 2207 0x1ea84, 0x1ea90, 2208 0x1eac0, 0x1eac0, 2209 0x1eae0, 0x1eae0, 2210 0x1eb00, 0x1eb84, 2211 0x1ebc0, 0x1ebc8, 2212 0x1ec08, 0x1ec0c, 2213 0x1ec40, 0x1ec44, 2214 0x1ec4c, 0x1ec4c, 2215 0x1ee84, 0x1ee90, 2216 0x1eec0, 0x1eec0, 2217 0x1eee0, 0x1eee0, 2218 0x1ef00, 0x1ef84, 2219 0x1efc0, 0x1efc8, 2220 0x1f008, 0x1f00c, 2221 0x1f040, 0x1f044, 2222 0x1f04c, 0x1f04c, 2223 0x1f284, 0x1f290, 2224 0x1f2c0, 0x1f2c0, 2225 0x1f2e0, 0x1f2e0, 2226 0x1f300, 0x1f384, 2227 0x1f3c0, 0x1f3c8, 2228 0x1f408, 0x1f40c, 2229 0x1f440, 0x1f444, 2230 0x1f44c, 0x1f44c, 2231 0x1f684, 0x1f690, 2232 0x1f6c0, 0x1f6c0, 2233 0x1f6e0, 0x1f6e0, 2234 0x1f700, 0x1f784, 2235 0x1f7c0, 0x1f7c8, 2236 0x1f808, 0x1f80c, 2237 0x1f840, 0x1f844, 2238 0x1f84c, 0x1f84c, 2239 0x1fa84, 0x1fa90, 2240 0x1fac0, 0x1fac0, 2241 0x1fae0, 0x1fae0, 2242 0x1fb00, 0x1fb84, 2243 0x1fbc0, 0x1fbc8, 2244 0x1fc08, 0x1fc0c, 2245 0x1fc40, 0x1fc44, 2246 0x1fc4c, 0x1fc4c, 2247 0x1fe84, 0x1fe90, 2248 0x1fec0, 0x1fec0, 2249 0x1fee0, 0x1fee0, 2250 0x1ff00, 0x1ff84, 2251 0x1ffc0, 0x1ffc8, 2252 0x30000, 0x30030, 2253 0x30100, 0x30168, 2254 0x30190, 0x301a0, 2255 0x301a8, 0x301b8, 2256 0x301c4, 0x301c8, 2257 0x301d0, 0x301d0, 2258 0x30200, 0x30320, 2259 0x30400, 0x304b4, 2260 0x304c0, 0x3052c, 2261 0x30540, 0x3061c, 2262 0x30800, 0x308a0, 2263 0x308c0, 0x30908, 2264 0x30910, 0x309b8, 2265 0x30a00, 0x30a04, 2266 0x30a0c, 0x30a14, 2267 0x30a1c, 0x30a2c, 2268 0x30a44, 0x30a50, 2269 0x30a74, 0x30a74, 2270 0x30a7c, 0x30afc, 2271 0x30b08, 0x30c24, 2272 0x30d00, 0x30d14, 2273 0x30d1c, 0x30d3c, 2274 0x30d44, 0x30d4c, 2275 0x30d54, 0x30d74, 2276 0x30d7c, 0x30d7c, 2277 0x30de0, 0x30de0, 2278 0x30e00, 0x30ed4, 2279 0x30f00, 0x30fa4, 2280 0x30fc0, 0x30fc4, 2281 0x31000, 0x31004, 2282 0x31080, 0x310fc, 2283 0x31208, 0x31220, 2284 0x3123c, 0x31254, 2285 0x31300, 0x31300, 2286 0x31308, 0x3131c, 2287 0x31338, 0x3133c, 2288 0x31380, 0x31380, 2289 0x31388, 0x313a8, 2290 0x313b4, 0x313b4, 2291 0x31400, 0x31420, 2292 0x31438, 0x3143c, 2293 0x31480, 0x31480, 2294 0x314a8, 0x314a8, 2295 0x314b0, 0x314b4, 2296 0x314c8, 0x314d4, 2297 0x31a40, 0x31a4c, 2298 0x31af0, 0x31b20, 2299 0x31b38, 0x31b3c, 2300 0x31b80, 0x31b80, 2301 0x31ba8, 0x31ba8, 2302 0x31bb0, 0x31bb4, 2303 0x31bc8, 0x31bd4, 2304 0x32140, 0x3218c, 2305 0x321f0, 0x321f4, 2306 0x32200, 0x32200, 2307 0x32218, 0x32218, 2308 0x32400, 0x32400, 2309 0x32408, 0x3241c, 2310 0x32618, 0x32620, 2311 0x32664, 0x32664, 2312 0x326a8, 0x326a8, 2313 0x326ec, 0x326ec, 2314 0x32a00, 0x32abc, 2315 0x32b00, 0x32b18, 2316 0x32b20, 0x32b38, 2317 0x32b40, 0x32b58, 2318 0x32b60, 0x32b78, 2319 0x32c00, 0x32c00, 2320 0x32c08, 0x32c3c, 2321 0x33000, 0x3302c, 2322 0x33034, 0x33050, 2323 0x33058, 0x33058, 2324 0x33060, 0x3308c, 2325 0x3309c, 0x330ac, 2326 0x330c0, 0x330c0, 2327 0x330c8, 0x330d0, 2328 0x330d8, 0x330e0, 2329 0x330ec, 0x3312c, 2330 0x33134, 0x33150, 2331 0x33158, 0x33158, 2332 0x33160, 0x3318c, 2333 0x3319c, 0x331ac, 2334 0x331c0, 0x331c0, 2335 0x331c8, 0x331d0, 2336 0x331d8, 0x331e0, 2337 0x331ec, 0x33290, 2338 0x33298, 0x332c4, 2339 0x332e4, 0x33390, 2340 0x33398, 0x333c4, 2341 0x333e4, 0x3342c, 2342 0x33434, 0x33450, 2343 0x33458, 0x33458, 2344 0x33460, 0x3348c, 2345 0x3349c, 0x334ac, 2346 0x334c0, 0x334c0, 2347 0x334c8, 0x334d0, 2348 0x334d8, 0x334e0, 2349 0x334ec, 0x3352c, 2350 0x33534, 0x33550, 2351 0x33558, 0x33558, 2352 0x33560, 0x3358c, 2353 0x3359c, 0x335ac, 2354 0x335c0, 0x335c0, 2355 0x335c8, 0x335d0, 2356 0x335d8, 0x335e0, 2357 0x335ec, 0x33690, 2358 0x33698, 0x336c4, 2359 0x336e4, 0x33790, 2360 0x33798, 0x337c4, 2361 0x337e4, 0x337fc, 2362 0x33814, 0x33814, 2363 0x33854, 0x33868, 2364 0x33880, 0x3388c, 2365 0x338c0, 0x338d0, 2366 0x338e8, 0x338ec, 2367 0x33900, 0x3392c, 2368 0x33934, 0x33950, 2369 0x33958, 0x33958, 2370 0x33960, 0x3398c, 2371 0x3399c, 0x339ac, 2372 0x339c0, 0x339c0, 2373 0x339c8, 0x339d0, 2374 0x339d8, 0x339e0, 2375 0x339ec, 0x33a90, 2376 0x33a98, 0x33ac4, 2377 0x33ae4, 0x33b10, 2378 0x33b24, 0x33b28, 2379 0x33b38, 0x33b50, 2380 0x33bf0, 0x33c10, 2381 0x33c24, 0x33c28, 2382 0x33c38, 0x33c50, 2383 0x33cf0, 0x33cfc, 2384 0x34000, 0x34030, 2385 0x34100, 0x34168, 2386 0x34190, 0x341a0, 2387 0x341a8, 0x341b8, 2388 0x341c4, 0x341c8, 2389 0x341d0, 0x341d0, 2390 0x34200, 0x34320, 2391 0x34400, 0x344b4, 2392 0x344c0, 0x3452c, 2393 0x34540, 0x3461c, 2394 0x34800, 0x348a0, 2395 0x348c0, 0x34908, 2396 0x34910, 0x349b8, 2397 0x34a00, 0x34a04, 2398 0x34a0c, 0x34a14, 2399 0x34a1c, 0x34a2c, 2400 0x34a44, 0x34a50, 2401 0x34a74, 0x34a74, 2402 0x34a7c, 0x34afc, 2403 0x34b08, 0x34c24, 2404 0x34d00, 0x34d14, 2405 0x34d1c, 0x34d3c, 2406 0x34d44, 0x34d4c, 2407 0x34d54, 0x34d74, 2408 0x34d7c, 0x34d7c, 2409 0x34de0, 0x34de0, 2410 0x34e00, 0x34ed4, 2411 0x34f00, 0x34fa4, 2412 0x34fc0, 0x34fc4, 2413 0x35000, 0x35004, 2414 0x35080, 0x350fc, 2415 0x35208, 0x35220, 2416 0x3523c, 0x35254, 2417 0x35300, 0x35300, 2418 0x35308, 0x3531c, 2419 0x35338, 0x3533c, 2420 0x35380, 0x35380, 2421 0x35388, 0x353a8, 2422 0x353b4, 0x353b4, 2423 0x35400, 0x35420, 2424 0x35438, 0x3543c, 2425 0x35480, 0x35480, 2426 0x354a8, 0x354a8, 2427 0x354b0, 0x354b4, 2428 0x354c8, 0x354d4, 2429 0x35a40, 0x35a4c, 2430 0x35af0, 0x35b20, 2431 0x35b38, 0x35b3c, 2432 0x35b80, 0x35b80, 2433 0x35ba8, 0x35ba8, 2434 0x35bb0, 0x35bb4, 2435 0x35bc8, 0x35bd4, 2436 0x36140, 0x3618c, 2437 0x361f0, 0x361f4, 2438 0x36200, 0x36200, 2439 0x36218, 0x36218, 2440 0x36400, 0x36400, 2441 0x36408, 0x3641c, 2442 0x36618, 0x36620, 2443 0x36664, 0x36664, 2444 0x366a8, 0x366a8, 2445 0x366ec, 0x366ec, 2446 0x36a00, 0x36abc, 2447 0x36b00, 0x36b18, 2448 0x36b20, 0x36b38, 2449 0x36b40, 0x36b58, 2450 0x36b60, 0x36b78, 2451 0x36c00, 0x36c00, 2452 0x36c08, 0x36c3c, 2453 0x37000, 0x3702c, 2454 0x37034, 0x37050, 2455 0x37058, 0x37058, 2456 0x37060, 0x3708c, 2457 0x3709c, 0x370ac, 2458 0x370c0, 0x370c0, 2459 0x370c8, 0x370d0, 2460 0x370d8, 0x370e0, 2461 0x370ec, 0x3712c, 2462 0x37134, 0x37150, 2463 0x37158, 0x37158, 2464 0x37160, 0x3718c, 2465 0x3719c, 0x371ac, 2466 0x371c0, 0x371c0, 2467 0x371c8, 0x371d0, 2468 0x371d8, 0x371e0, 2469 0x371ec, 0x37290, 2470 0x37298, 0x372c4, 2471 0x372e4, 0x37390, 2472 0x37398, 0x373c4, 2473 0x373e4, 0x3742c, 2474 0x37434, 0x37450, 2475 0x37458, 0x37458, 2476 0x37460, 0x3748c, 2477 0x3749c, 0x374ac, 2478 0x374c0, 0x374c0, 2479 0x374c8, 0x374d0, 2480 0x374d8, 0x374e0, 2481 0x374ec, 0x3752c, 2482 0x37534, 0x37550, 2483 0x37558, 0x37558, 2484 0x37560, 0x3758c, 2485 0x3759c, 0x375ac, 2486 0x375c0, 0x375c0, 2487 0x375c8, 0x375d0, 2488 0x375d8, 0x375e0, 2489 0x375ec, 0x37690, 2490 0x37698, 0x376c4, 2491 0x376e4, 0x37790, 2492 0x37798, 0x377c4, 2493 0x377e4, 0x377fc, 2494 0x37814, 0x37814, 2495 0x37854, 0x37868, 2496 0x37880, 0x3788c, 2497 0x378c0, 0x378d0, 2498 0x378e8, 0x378ec, 2499 0x37900, 0x3792c, 2500 0x37934, 0x37950, 2501 0x37958, 0x37958, 2502 0x37960, 0x3798c, 2503 0x3799c, 0x379ac, 2504 0x379c0, 0x379c0, 2505 0x379c8, 0x379d0, 2506 0x379d8, 0x379e0, 2507 0x379ec, 0x37a90, 2508 0x37a98, 0x37ac4, 2509 0x37ae4, 0x37b10, 2510 0x37b24, 0x37b28, 2511 0x37b38, 0x37b50, 2512 0x37bf0, 0x37c10, 2513 0x37c24, 0x37c28, 2514 0x37c38, 0x37c50, 2515 0x37cf0, 0x37cfc, 2516 0x40040, 0x40040, 2517 0x40080, 0x40084, 2518 0x40100, 0x40100, 2519 0x40140, 0x401bc, 2520 0x40200, 0x40214, 2521 0x40228, 0x40228, 2522 0x40240, 0x40258, 2523 0x40280, 0x40280, 2524 0x40304, 0x40304, 2525 0x40330, 0x4033c, 2526 0x41304, 0x413c8, 2527 0x413d0, 0x413dc, 2528 0x413f0, 0x413f0, 2529 0x41400, 0x4140c, 2530 0x41414, 0x4141c, 2531 0x41480, 0x414d0, 2532 0x44000, 0x4407c, 2533 0x440c0, 0x441ac, 2534 0x441b4, 0x4427c, 2535 0x442c0, 0x443ac, 2536 0x443b4, 0x4447c, 2537 0x444c0, 0x445ac, 2538 0x445b4, 0x4467c, 2539 0x446c0, 0x447ac, 2540 0x447b4, 0x4487c, 2541 0x448c0, 0x449ac, 2542 0x449b4, 0x44a7c, 2543 0x44ac0, 0x44bac, 2544 0x44bb4, 0x44c7c, 2545 0x44cc0, 0x44dac, 2546 0x44db4, 0x44e7c, 2547 0x44ec0, 0x44fac, 2548 0x44fb4, 0x4507c, 2549 0x450c0, 0x451ac, 2550 0x451b4, 0x451fc, 2551 0x45800, 0x45804, 2552 0x45810, 0x45830, 2553 0x45840, 0x45860, 2554 0x45868, 0x45868, 2555 0x45880, 0x45884, 2556 0x458a0, 0x458b0, 2557 0x45a00, 0x45a04, 2558 0x45a10, 0x45a30, 2559 0x45a40, 0x45a60, 2560 0x45a68, 0x45a68, 2561 0x45a80, 0x45a84, 2562 0x45aa0, 0x45ab0, 2563 0x460c0, 0x460e4, 2564 0x47000, 0x4703c, 2565 0x47044, 0x4708c, 2566 0x47200, 0x47250, 2567 0x47400, 0x47408, 2568 0x47414, 0x47420, 2569 0x47600, 0x47618, 2570 0x47800, 0x47814, 2571 0x47820, 0x4782c, 2572 0x50000, 0x50084, 2573 0x50090, 0x500cc, 2574 0x50300, 0x50384, 2575 0x50400, 0x50400, 2576 0x50800, 0x50884, 2577 0x50890, 0x508cc, 2578 0x50b00, 0x50b84, 2579 0x50c00, 0x50c00, 2580 0x51000, 0x51020, 2581 0x51028, 0x510b0, 2582 0x51300, 0x51324, 2583 }; 2584 2585 static const unsigned int t6vf_reg_ranges[] = { 2586 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2587 VF_MPS_REG(A_MPS_VF_CTL), 2588 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2589 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2590 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2591 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2592 FW_T6VF_MBDATA_BASE_ADDR, 2593 FW_T6VF_MBDATA_BASE_ADDR + 2594 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2595 }; 2596 2597 u32 *buf_end = (u32 *)(buf + buf_size); 2598 const unsigned int *reg_ranges; 2599 int reg_ranges_size, range; 2600 unsigned int chip_version = chip_id(adap); 2601 2602 /* 2603 * Select the right set of register ranges to dump depending on the 2604 * adapter chip type. 2605 */ 2606 switch (chip_version) { 2607 case CHELSIO_T4: 2608 if (adap->flags & IS_VF) { 2609 reg_ranges = t4vf_reg_ranges; 2610 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2611 } else { 2612 reg_ranges = t4_reg_ranges; 2613 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2614 } 2615 break; 2616 2617 case CHELSIO_T5: 2618 if (adap->flags & IS_VF) { 2619 reg_ranges = t5vf_reg_ranges; 2620 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2621 } else { 2622 reg_ranges = t5_reg_ranges; 2623 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2624 } 2625 break; 2626 2627 case CHELSIO_T6: 2628 if (adap->flags & IS_VF) { 2629 reg_ranges = t6vf_reg_ranges; 2630 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2631 } else { 2632 reg_ranges = t6_reg_ranges; 2633 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2634 } 2635 break; 2636 2637 default: 2638 CH_ERR(adap, 2639 "Unsupported chip version %d\n", chip_version); 2640 return; 2641 } 2642 2643 /* 2644 * Clear the register buffer and insert the appropriate register 2645 * values selected by the above register ranges. 2646 */ 2647 memset(buf, 0, buf_size); 2648 for (range = 0; range < reg_ranges_size; range += 2) { 2649 unsigned int reg = reg_ranges[range]; 2650 unsigned int last_reg = reg_ranges[range + 1]; 2651 u32 *bufp = (u32 *)(buf + reg); 2652 2653 /* 2654 * Iterate across the register range filling in the register 2655 * buffer but don't write past the end of the register buffer. 2656 */ 2657 while (reg <= last_reg && bufp < buf_end) { 2658 *bufp++ = t4_read_reg(adap, reg); 2659 reg += sizeof(u32); 2660 } 2661 } 2662 } 2663 2664 /* 2665 * Partial EEPROM Vital Product Data structure. Includes only the ID and 2666 * VPD-R sections. 2667 */ 2668 struct t4_vpd_hdr { 2669 u8 id_tag; 2670 u8 id_len[2]; 2671 u8 id_data[ID_LEN]; 2672 u8 vpdr_tag; 2673 u8 vpdr_len[2]; 2674 }; 2675 2676 /* 2677 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2678 */ 2679 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2680 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2681 2682 #define EEPROM_STAT_ADDR 0x7bfc 2683 #define VPD_SIZE 0x800 2684 #define VPD_BASE 0x400 2685 #define VPD_BASE_OLD 0 2686 #define VPD_LEN 1024 2687 #define VPD_INFO_FLD_HDR_SIZE 3 2688 #define CHELSIO_VPD_UNIQUE_ID 0x82 2689 2690 /* 2691 * Small utility function to wait till any outstanding VPD Access is complete. 2692 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2693 * VPD Access in flight. This allows us to handle the problem of having a 2694 * previous VPD Access time out and prevent an attempt to inject a new VPD 2695 * Request before any in-flight VPD reguest has completed. 2696 */ 2697 static int t4_seeprom_wait(struct adapter *adapter) 2698 { 2699 unsigned int base = adapter->params.pci.vpd_cap_addr; 2700 int max_poll; 2701 2702 /* 2703 * If no VPD Access is in flight, we can just return success right 2704 * away. 2705 */ 2706 if (!adapter->vpd_busy) 2707 return 0; 2708 2709 /* 2710 * Poll the VPD Capability Address/Flag register waiting for it 2711 * to indicate that the operation is complete. 2712 */ 2713 max_poll = EEPROM_MAX_POLL; 2714 do { 2715 u16 val; 2716 2717 udelay(EEPROM_DELAY); 2718 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2719 2720 /* 2721 * If the operation is complete, mark the VPD as no longer 2722 * busy and return success. 2723 */ 2724 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2725 adapter->vpd_busy = 0; 2726 return 0; 2727 } 2728 } while (--max_poll); 2729 2730 /* 2731 * Failure! Note that we leave the VPD Busy status set in order to 2732 * avoid pushing a new VPD Access request into the VPD Capability till 2733 * the current operation eventually succeeds. It's a bug to issue a 2734 * new request when an existing request is in flight and will result 2735 * in corrupt hardware state. 2736 */ 2737 return -ETIMEDOUT; 2738 } 2739 2740 /** 2741 * t4_seeprom_read - read a serial EEPROM location 2742 * @adapter: adapter to read 2743 * @addr: EEPROM virtual address 2744 * @data: where to store the read data 2745 * 2746 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2747 * VPD capability. Note that this function must be called with a virtual 2748 * address. 2749 */ 2750 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2751 { 2752 unsigned int base = adapter->params.pci.vpd_cap_addr; 2753 int ret; 2754 2755 /* 2756 * VPD Accesses must alway be 4-byte aligned! 2757 */ 2758 if (addr >= EEPROMVSIZE || (addr & 3)) 2759 return -EINVAL; 2760 2761 /* 2762 * Wait for any previous operation which may still be in flight to 2763 * complete. 2764 */ 2765 ret = t4_seeprom_wait(adapter); 2766 if (ret) { 2767 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2768 return ret; 2769 } 2770 2771 /* 2772 * Issue our new VPD Read request, mark the VPD as being busy and wait 2773 * for our request to complete. If it doesn't complete, note the 2774 * error and return it to our caller. Note that we do not reset the 2775 * VPD Busy status! 2776 */ 2777 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2778 adapter->vpd_busy = 1; 2779 adapter->vpd_flag = PCI_VPD_ADDR_F; 2780 ret = t4_seeprom_wait(adapter); 2781 if (ret) { 2782 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2783 return ret; 2784 } 2785 2786 /* 2787 * Grab the returned data, swizzle it into our endianness and 2788 * return success. 2789 */ 2790 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2791 *data = le32_to_cpu(*data); 2792 return 0; 2793 } 2794 2795 /** 2796 * t4_seeprom_write - write a serial EEPROM location 2797 * @adapter: adapter to write 2798 * @addr: virtual EEPROM address 2799 * @data: value to write 2800 * 2801 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2802 * VPD capability. Note that this function must be called with a virtual 2803 * address. 2804 */ 2805 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2806 { 2807 unsigned int base = adapter->params.pci.vpd_cap_addr; 2808 int ret; 2809 u32 stats_reg; 2810 int max_poll; 2811 2812 /* 2813 * VPD Accesses must alway be 4-byte aligned! 2814 */ 2815 if (addr >= EEPROMVSIZE || (addr & 3)) 2816 return -EINVAL; 2817 2818 /* 2819 * Wait for any previous operation which may still be in flight to 2820 * complete. 2821 */ 2822 ret = t4_seeprom_wait(adapter); 2823 if (ret) { 2824 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2825 return ret; 2826 } 2827 2828 /* 2829 * Issue our new VPD Read request, mark the VPD as being busy and wait 2830 * for our request to complete. If it doesn't complete, note the 2831 * error and return it to our caller. Note that we do not reset the 2832 * VPD Busy status! 2833 */ 2834 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2835 cpu_to_le32(data)); 2836 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2837 (u16)addr | PCI_VPD_ADDR_F); 2838 adapter->vpd_busy = 1; 2839 adapter->vpd_flag = 0; 2840 ret = t4_seeprom_wait(adapter); 2841 if (ret) { 2842 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2843 return ret; 2844 } 2845 2846 /* 2847 * Reset PCI_VPD_DATA register after a transaction and wait for our 2848 * request to complete. If it doesn't complete, return error. 2849 */ 2850 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2851 max_poll = EEPROM_MAX_POLL; 2852 do { 2853 udelay(EEPROM_DELAY); 2854 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2855 } while ((stats_reg & 0x1) && --max_poll); 2856 if (!max_poll) 2857 return -ETIMEDOUT; 2858 2859 /* Return success! */ 2860 return 0; 2861 } 2862 2863 /** 2864 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2865 * @phys_addr: the physical EEPROM address 2866 * @fn: the PCI function number 2867 * @sz: size of function-specific area 2868 * 2869 * Translate a physical EEPROM address to virtual. The first 1K is 2870 * accessed through virtual addresses starting at 31K, the rest is 2871 * accessed through virtual addresses starting at 0. 2872 * 2873 * The mapping is as follows: 2874 * [0..1K) -> [31K..32K) 2875 * [1K..1K+A) -> [ES-A..ES) 2876 * [1K+A..ES) -> [0..ES-A-1K) 2877 * 2878 * where A = @fn * @sz, and ES = EEPROM size. 2879 */ 2880 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2881 { 2882 fn *= sz; 2883 if (phys_addr < 1024) 2884 return phys_addr + (31 << 10); 2885 if (phys_addr < 1024 + fn) 2886 return EEPROMSIZE - fn + phys_addr - 1024; 2887 if (phys_addr < EEPROMSIZE) 2888 return phys_addr - 1024 - fn; 2889 return -EINVAL; 2890 } 2891 2892 /** 2893 * t4_seeprom_wp - enable/disable EEPROM write protection 2894 * @adapter: the adapter 2895 * @enable: whether to enable or disable write protection 2896 * 2897 * Enables or disables write protection on the serial EEPROM. 2898 */ 2899 int t4_seeprom_wp(struct adapter *adapter, int enable) 2900 { 2901 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2902 } 2903 2904 /** 2905 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2906 * @v: Pointer to buffered vpd data structure 2907 * @kw: The keyword to search for 2908 * 2909 * Returns the value of the information field keyword or 2910 * -ENOENT otherwise. 2911 */ 2912 static int get_vpd_keyword_val(const struct t4_vpd_hdr *v, const char *kw) 2913 { 2914 int i; 2915 unsigned int offset , len; 2916 const u8 *buf = (const u8 *)v; 2917 const u8 *vpdr_len = &v->vpdr_len[0]; 2918 offset = sizeof(struct t4_vpd_hdr); 2919 len = (u16)vpdr_len[0] + ((u16)vpdr_len[1] << 8); 2920 2921 if (len + sizeof(struct t4_vpd_hdr) > VPD_LEN) { 2922 return -ENOENT; 2923 } 2924 2925 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 2926 if(memcmp(buf + i , kw , 2) == 0){ 2927 i += VPD_INFO_FLD_HDR_SIZE; 2928 return i; 2929 } 2930 2931 i += VPD_INFO_FLD_HDR_SIZE + buf[i+2]; 2932 } 2933 2934 return -ENOENT; 2935 } 2936 2937 2938 /** 2939 * get_vpd_params - read VPD parameters from VPD EEPROM 2940 * @adapter: adapter to read 2941 * @p: where to store the parameters 2942 * @vpd: caller provided temporary space to read the VPD into 2943 * 2944 * Reads card parameters stored in VPD EEPROM. 2945 */ 2946 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 2947 u8 *vpd) 2948 { 2949 int i, ret, addr; 2950 int ec, sn, pn, na; 2951 u8 csum; 2952 const struct t4_vpd_hdr *v; 2953 2954 /* 2955 * Card information normally starts at VPD_BASE but early cards had 2956 * it at 0. 2957 */ 2958 ret = t4_seeprom_read(adapter, VPD_BASE, (u32 *)(vpd)); 2959 if (ret) 2960 return (ret); 2961 2962 /* 2963 * The VPD shall have a unique identifier specified by the PCI SIG. 2964 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 2965 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 2966 * is expected to automatically put this entry at the 2967 * beginning of the VPD. 2968 */ 2969 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 2970 2971 for (i = 0; i < VPD_LEN; i += 4) { 2972 ret = t4_seeprom_read(adapter, addr + i, (u32 *)(vpd + i)); 2973 if (ret) 2974 return ret; 2975 } 2976 v = (const struct t4_vpd_hdr *)vpd; 2977 2978 #define FIND_VPD_KW(var,name) do { \ 2979 var = get_vpd_keyword_val(v , name); \ 2980 if (var < 0) { \ 2981 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 2982 return -EINVAL; \ 2983 } \ 2984 } while (0) 2985 2986 FIND_VPD_KW(i, "RV"); 2987 for (csum = 0; i >= 0; i--) 2988 csum += vpd[i]; 2989 2990 if (csum) { 2991 CH_ERR(adapter, 2992 "corrupted VPD EEPROM, actual csum %u\n", csum); 2993 return -EINVAL; 2994 } 2995 2996 FIND_VPD_KW(ec, "EC"); 2997 FIND_VPD_KW(sn, "SN"); 2998 FIND_VPD_KW(pn, "PN"); 2999 FIND_VPD_KW(na, "NA"); 3000 #undef FIND_VPD_KW 3001 3002 memcpy(p->id, v->id_data, ID_LEN); 3003 strstrip(p->id); 3004 memcpy(p->ec, vpd + ec, EC_LEN); 3005 strstrip(p->ec); 3006 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3007 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3008 strstrip(p->sn); 3009 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3010 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3011 strstrip((char *)p->pn); 3012 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3013 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3014 strstrip((char *)p->na); 3015 3016 return 0; 3017 } 3018 3019 /* serial flash and firmware constants and flash config file constants */ 3020 enum { 3021 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3022 3023 /* flash command opcodes */ 3024 SF_PROG_PAGE = 2, /* program 256B page */ 3025 SF_WR_DISABLE = 4, /* disable writes */ 3026 SF_RD_STATUS = 5, /* read status register */ 3027 SF_WR_ENABLE = 6, /* enable writes */ 3028 SF_RD_DATA_FAST = 0xb, /* read flash */ 3029 SF_RD_ID = 0x9f, /* read ID */ 3030 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3031 }; 3032 3033 /** 3034 * sf1_read - read data from the serial flash 3035 * @adapter: the adapter 3036 * @byte_cnt: number of bytes to read 3037 * @cont: whether another operation will be chained 3038 * @lock: whether to lock SF for PL access only 3039 * @valp: where to store the read data 3040 * 3041 * Reads up to 4 bytes of data from the serial flash. The location of 3042 * the read needs to be specified prior to calling this by issuing the 3043 * appropriate commands to the serial flash. 3044 */ 3045 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3046 int lock, u32 *valp) 3047 { 3048 int ret; 3049 3050 if (!byte_cnt || byte_cnt > 4) 3051 return -EINVAL; 3052 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3053 return -EBUSY; 3054 t4_write_reg(adapter, A_SF_OP, 3055 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3056 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3057 if (!ret) 3058 *valp = t4_read_reg(adapter, A_SF_DATA); 3059 return ret; 3060 } 3061 3062 /** 3063 * sf1_write - write data to the serial flash 3064 * @adapter: the adapter 3065 * @byte_cnt: number of bytes to write 3066 * @cont: whether another operation will be chained 3067 * @lock: whether to lock SF for PL access only 3068 * @val: value to write 3069 * 3070 * Writes up to 4 bytes of data to the serial flash. The location of 3071 * the write needs to be specified prior to calling this by issuing the 3072 * appropriate commands to the serial flash. 3073 */ 3074 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3075 int lock, u32 val) 3076 { 3077 if (!byte_cnt || byte_cnt > 4) 3078 return -EINVAL; 3079 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3080 return -EBUSY; 3081 t4_write_reg(adapter, A_SF_DATA, val); 3082 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3083 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3084 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3085 } 3086 3087 /** 3088 * flash_wait_op - wait for a flash operation to complete 3089 * @adapter: the adapter 3090 * @attempts: max number of polls of the status register 3091 * @delay: delay between polls in ms 3092 * 3093 * Wait for a flash operation to complete by polling the status register. 3094 */ 3095 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3096 { 3097 int ret; 3098 u32 status; 3099 3100 while (1) { 3101 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3102 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3103 return ret; 3104 if (!(status & 1)) 3105 return 0; 3106 if (--attempts == 0) 3107 return -EAGAIN; 3108 if (delay) 3109 msleep(delay); 3110 } 3111 } 3112 3113 /** 3114 * t4_read_flash - read words from serial flash 3115 * @adapter: the adapter 3116 * @addr: the start address for the read 3117 * @nwords: how many 32-bit words to read 3118 * @data: where to store the read data 3119 * @byte_oriented: whether to store data as bytes or as words 3120 * 3121 * Read the specified number of 32-bit words from the serial flash. 3122 * If @byte_oriented is set the read data is stored as a byte array 3123 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3124 * natural endianness. 3125 */ 3126 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3127 unsigned int nwords, u32 *data, int byte_oriented) 3128 { 3129 int ret; 3130 3131 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3132 return -EINVAL; 3133 3134 addr = swab32(addr) | SF_RD_DATA_FAST; 3135 3136 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3137 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3138 return ret; 3139 3140 for ( ; nwords; nwords--, data++) { 3141 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3142 if (nwords == 1) 3143 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3144 if (ret) 3145 return ret; 3146 if (byte_oriented) 3147 *data = (__force __u32)(cpu_to_be32(*data)); 3148 } 3149 return 0; 3150 } 3151 3152 /** 3153 * t4_write_flash - write up to a page of data to the serial flash 3154 * @adapter: the adapter 3155 * @addr: the start address to write 3156 * @n: length of data to write in bytes 3157 * @data: the data to write 3158 * @byte_oriented: whether to store data as bytes or as words 3159 * 3160 * Writes up to a page of data (256 bytes) to the serial flash starting 3161 * at the given address. All the data must be written to the same page. 3162 * If @byte_oriented is set the write data is stored as byte stream 3163 * (i.e. matches what on disk), otherwise in big-endian. 3164 */ 3165 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3166 unsigned int n, const u8 *data, int byte_oriented) 3167 { 3168 int ret; 3169 u32 buf[SF_PAGE_SIZE / 4]; 3170 unsigned int i, c, left, val, offset = addr & 0xff; 3171 3172 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3173 return -EINVAL; 3174 3175 val = swab32(addr) | SF_PROG_PAGE; 3176 3177 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3178 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3179 goto unlock; 3180 3181 for (left = n; left; left -= c) { 3182 c = min(left, 4U); 3183 for (val = 0, i = 0; i < c; ++i) 3184 val = (val << 8) + *data++; 3185 3186 if (!byte_oriented) 3187 val = cpu_to_be32(val); 3188 3189 ret = sf1_write(adapter, c, c != left, 1, val); 3190 if (ret) 3191 goto unlock; 3192 } 3193 ret = flash_wait_op(adapter, 8, 1); 3194 if (ret) 3195 goto unlock; 3196 3197 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3198 3199 /* Read the page to verify the write succeeded */ 3200 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3201 byte_oriented); 3202 if (ret) 3203 return ret; 3204 3205 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3206 CH_ERR(adapter, 3207 "failed to correctly write the flash page at %#x\n", 3208 addr); 3209 return -EIO; 3210 } 3211 return 0; 3212 3213 unlock: 3214 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3215 return ret; 3216 } 3217 3218 /** 3219 * t4_get_fw_version - read the firmware version 3220 * @adapter: the adapter 3221 * @vers: where to place the version 3222 * 3223 * Reads the FW version from flash. 3224 */ 3225 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3226 { 3227 return t4_read_flash(adapter, FLASH_FW_START + 3228 offsetof(struct fw_hdr, fw_ver), 1, 3229 vers, 0); 3230 } 3231 3232 /** 3233 * t4_get_bs_version - read the firmware bootstrap version 3234 * @adapter: the adapter 3235 * @vers: where to place the version 3236 * 3237 * Reads the FW Bootstrap version from flash. 3238 */ 3239 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3240 { 3241 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3242 offsetof(struct fw_hdr, fw_ver), 1, 3243 vers, 0); 3244 } 3245 3246 /** 3247 * t4_get_tp_version - read the TP microcode version 3248 * @adapter: the adapter 3249 * @vers: where to place the version 3250 * 3251 * Reads the TP microcode version from flash. 3252 */ 3253 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3254 { 3255 return t4_read_flash(adapter, FLASH_FW_START + 3256 offsetof(struct fw_hdr, tp_microcode_ver), 3257 1, vers, 0); 3258 } 3259 3260 /** 3261 * t4_get_exprom_version - return the Expansion ROM version (if any) 3262 * @adapter: the adapter 3263 * @vers: where to place the version 3264 * 3265 * Reads the Expansion ROM header from FLASH and returns the version 3266 * number (if present) through the @vers return value pointer. We return 3267 * this in the Firmware Version Format since it's convenient. Return 3268 * 0 on success, -ENOENT if no Expansion ROM is present. 3269 */ 3270 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 3271 { 3272 struct exprom_header { 3273 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3274 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3275 } *hdr; 3276 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3277 sizeof(u32))]; 3278 int ret; 3279 3280 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 3281 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3282 0); 3283 if (ret) 3284 return ret; 3285 3286 hdr = (struct exprom_header *)exprom_header_buf; 3287 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3288 return -ENOENT; 3289 3290 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3291 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3292 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3293 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3294 return 0; 3295 } 3296 3297 /** 3298 * t4_get_scfg_version - return the Serial Configuration version 3299 * @adapter: the adapter 3300 * @vers: where to place the version 3301 * 3302 * Reads the Serial Configuration Version via the Firmware interface 3303 * (thus this can only be called once we're ready to issue Firmware 3304 * commands). The format of the Serial Configuration version is 3305 * adapter specific. Returns 0 on success, an error on failure. 3306 * 3307 * Note that early versions of the Firmware didn't include the ability 3308 * to retrieve the Serial Configuration version, so we zero-out the 3309 * return-value parameter in that case to avoid leaving it with 3310 * garbage in it. 3311 * 3312 * Also note that the Firmware will return its cached copy of the Serial 3313 * Initialization Revision ID, not the actual Revision ID as written in 3314 * the Serial EEPROM. This is only an issue if a new VPD has been written 3315 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3316 * it's best to defer calling this routine till after a FW_RESET_CMD has 3317 * been issued if the Host Driver will be performing a full adapter 3318 * initialization. 3319 */ 3320 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3321 { 3322 u32 scfgrev_param; 3323 int ret; 3324 3325 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3326 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3327 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3328 1, &scfgrev_param, vers); 3329 if (ret) 3330 *vers = 0; 3331 return ret; 3332 } 3333 3334 /** 3335 * t4_get_vpd_version - return the VPD version 3336 * @adapter: the adapter 3337 * @vers: where to place the version 3338 * 3339 * Reads the VPD via the Firmware interface (thus this can only be called 3340 * once we're ready to issue Firmware commands). The format of the 3341 * VPD version is adapter specific. Returns 0 on success, an error on 3342 * failure. 3343 * 3344 * Note that early versions of the Firmware didn't include the ability 3345 * to retrieve the VPD version, so we zero-out the return-value parameter 3346 * in that case to avoid leaving it with garbage in it. 3347 * 3348 * Also note that the Firmware will return its cached copy of the VPD 3349 * Revision ID, not the actual Revision ID as written in the Serial 3350 * EEPROM. This is only an issue if a new VPD has been written and the 3351 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3352 * to defer calling this routine till after a FW_RESET_CMD has been issued 3353 * if the Host Driver will be performing a full adapter initialization. 3354 */ 3355 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3356 { 3357 u32 vpdrev_param; 3358 int ret; 3359 3360 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3361 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3362 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3363 1, &vpdrev_param, vers); 3364 if (ret) 3365 *vers = 0; 3366 return ret; 3367 } 3368 3369 /** 3370 * t4_get_version_info - extract various chip/firmware version information 3371 * @adapter: the adapter 3372 * 3373 * Reads various chip/firmware version numbers and stores them into the 3374 * adapter Adapter Parameters structure. If any of the efforts fails 3375 * the first failure will be returned, but all of the version numbers 3376 * will be read. 3377 */ 3378 int t4_get_version_info(struct adapter *adapter) 3379 { 3380 int ret = 0; 3381 3382 #define FIRST_RET(__getvinfo) \ 3383 do { \ 3384 int __ret = __getvinfo; \ 3385 if (__ret && !ret) \ 3386 ret = __ret; \ 3387 } while (0) 3388 3389 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3390 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3391 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3392 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3393 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3394 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3395 3396 #undef FIRST_RET 3397 3398 return ret; 3399 } 3400 3401 /** 3402 * t4_flash_erase_sectors - erase a range of flash sectors 3403 * @adapter: the adapter 3404 * @start: the first sector to erase 3405 * @end: the last sector to erase 3406 * 3407 * Erases the sectors in the given inclusive range. 3408 */ 3409 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3410 { 3411 int ret = 0; 3412 3413 if (end >= adapter->params.sf_nsec) 3414 return -EINVAL; 3415 3416 while (start <= end) { 3417 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3418 (ret = sf1_write(adapter, 4, 0, 1, 3419 SF_ERASE_SECTOR | (start << 8))) != 0 || 3420 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3421 CH_ERR(adapter, 3422 "erase of flash sector %d failed, error %d\n", 3423 start, ret); 3424 break; 3425 } 3426 start++; 3427 } 3428 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3429 return ret; 3430 } 3431 3432 /** 3433 * t4_flash_cfg_addr - return the address of the flash configuration file 3434 * @adapter: the adapter 3435 * 3436 * Return the address within the flash where the Firmware Configuration 3437 * File is stored, or an error if the device FLASH is too small to contain 3438 * a Firmware Configuration File. 3439 */ 3440 int t4_flash_cfg_addr(struct adapter *adapter) 3441 { 3442 /* 3443 * If the device FLASH isn't large enough to hold a Firmware 3444 * Configuration File, return an error. 3445 */ 3446 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3447 return -ENOSPC; 3448 3449 return FLASH_CFG_START; 3450 } 3451 3452 /* 3453 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3454 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3455 * and emit an error message for mismatched firmware to save our caller the 3456 * effort ... 3457 */ 3458 static int t4_fw_matches_chip(struct adapter *adap, 3459 const struct fw_hdr *hdr) 3460 { 3461 /* 3462 * The expression below will return FALSE for any unsupported adapter 3463 * which will keep us "honest" in the future ... 3464 */ 3465 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3466 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3467 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3468 return 1; 3469 3470 CH_ERR(adap, 3471 "FW image (%d) is not suitable for this adapter (%d)\n", 3472 hdr->chip, chip_id(adap)); 3473 return 0; 3474 } 3475 3476 /** 3477 * t4_load_fw - download firmware 3478 * @adap: the adapter 3479 * @fw_data: the firmware image to write 3480 * @size: image size 3481 * 3482 * Write the supplied firmware image to the card's serial flash. 3483 */ 3484 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3485 { 3486 u32 csum; 3487 int ret, addr; 3488 unsigned int i; 3489 u8 first_page[SF_PAGE_SIZE]; 3490 const u32 *p = (const u32 *)fw_data; 3491 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3492 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3493 unsigned int fw_start_sec; 3494 unsigned int fw_start; 3495 unsigned int fw_size; 3496 3497 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3498 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3499 fw_start = FLASH_FWBOOTSTRAP_START; 3500 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3501 } else { 3502 fw_start_sec = FLASH_FW_START_SEC; 3503 fw_start = FLASH_FW_START; 3504 fw_size = FLASH_FW_MAX_SIZE; 3505 } 3506 3507 if (!size) { 3508 CH_ERR(adap, "FW image has no data\n"); 3509 return -EINVAL; 3510 } 3511 if (size & 511) { 3512 CH_ERR(adap, 3513 "FW image size not multiple of 512 bytes\n"); 3514 return -EINVAL; 3515 } 3516 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3517 CH_ERR(adap, 3518 "FW image size differs from size in FW header\n"); 3519 return -EINVAL; 3520 } 3521 if (size > fw_size) { 3522 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3523 fw_size); 3524 return -EFBIG; 3525 } 3526 if (!t4_fw_matches_chip(adap, hdr)) 3527 return -EINVAL; 3528 3529 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3530 csum += be32_to_cpu(p[i]); 3531 3532 if (csum != 0xffffffff) { 3533 CH_ERR(adap, 3534 "corrupted firmware image, checksum %#x\n", csum); 3535 return -EINVAL; 3536 } 3537 3538 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3539 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3540 if (ret) 3541 goto out; 3542 3543 /* 3544 * We write the correct version at the end so the driver can see a bad 3545 * version if the FW write fails. Start by writing a copy of the 3546 * first page with a bad version. 3547 */ 3548 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3549 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3550 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3551 if (ret) 3552 goto out; 3553 3554 addr = fw_start; 3555 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3556 addr += SF_PAGE_SIZE; 3557 fw_data += SF_PAGE_SIZE; 3558 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3559 if (ret) 3560 goto out; 3561 } 3562 3563 ret = t4_write_flash(adap, 3564 fw_start + offsetof(struct fw_hdr, fw_ver), 3565 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3566 out: 3567 if (ret) 3568 CH_ERR(adap, "firmware download failed, error %d\n", 3569 ret); 3570 return ret; 3571 } 3572 3573 /** 3574 * t4_fwcache - firmware cache operation 3575 * @adap: the adapter 3576 * @op : the operation (flush or flush and invalidate) 3577 */ 3578 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3579 { 3580 struct fw_params_cmd c; 3581 3582 memset(&c, 0, sizeof(c)); 3583 c.op_to_vfn = 3584 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3585 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3586 V_FW_PARAMS_CMD_PFN(adap->pf) | 3587 V_FW_PARAMS_CMD_VFN(0)); 3588 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3589 c.param[0].mnem = 3590 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3591 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3592 c.param[0].val = (__force __be32)op; 3593 3594 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3595 } 3596 3597 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3598 unsigned int *pif_req_wrptr, 3599 unsigned int *pif_rsp_wrptr) 3600 { 3601 int i, j; 3602 u32 cfg, val, req, rsp; 3603 3604 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3605 if (cfg & F_LADBGEN) 3606 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3607 3608 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3609 req = G_POLADBGWRPTR(val); 3610 rsp = G_PILADBGWRPTR(val); 3611 if (pif_req_wrptr) 3612 *pif_req_wrptr = req; 3613 if (pif_rsp_wrptr) 3614 *pif_rsp_wrptr = rsp; 3615 3616 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3617 for (j = 0; j < 6; j++) { 3618 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3619 V_PILADBGRDPTR(rsp)); 3620 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3621 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3622 req++; 3623 rsp++; 3624 } 3625 req = (req + 2) & M_POLADBGRDPTR; 3626 rsp = (rsp + 2) & M_PILADBGRDPTR; 3627 } 3628 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3629 } 3630 3631 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3632 { 3633 u32 cfg; 3634 int i, j, idx; 3635 3636 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3637 if (cfg & F_LADBGEN) 3638 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3639 3640 for (i = 0; i < CIM_MALA_SIZE; i++) { 3641 for (j = 0; j < 5; j++) { 3642 idx = 8 * i + j; 3643 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3644 V_PILADBGRDPTR(idx)); 3645 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3646 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3647 } 3648 } 3649 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3650 } 3651 3652 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3653 { 3654 unsigned int i, j; 3655 3656 for (i = 0; i < 8; i++) { 3657 u32 *p = la_buf + i; 3658 3659 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3660 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3661 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3662 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3663 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3664 } 3665 } 3666 3667 /** 3668 * t4_link_l1cfg - apply link configuration to MAC/PHY 3669 * @phy: the PHY to setup 3670 * @mac: the MAC to setup 3671 * @lc: the requested link configuration 3672 * 3673 * Set up a port's MAC and PHY according to a desired link configuration. 3674 * - If the PHY can auto-negotiate first decide what to advertise, then 3675 * enable/disable auto-negotiation as desired, and reset. 3676 * - If the PHY does not auto-negotiate just reset it. 3677 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3678 * otherwise do it later based on the outcome of auto-negotiation. 3679 */ 3680 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3681 struct link_config *lc) 3682 { 3683 struct fw_port_cmd c; 3684 unsigned int mdi = V_FW_PORT_CAP_MDI(FW_PORT_CAP_MDI_AUTO); 3685 unsigned int aneg, fc, fec, speed; 3686 3687 fc = 0; 3688 if (lc->requested_fc & PAUSE_RX) 3689 fc |= FW_PORT_CAP_FC_RX; 3690 if (lc->requested_fc & PAUSE_TX) 3691 fc |= FW_PORT_CAP_FC_TX; 3692 3693 fec = 0; 3694 if (lc->requested_fec & FEC_RS) 3695 fec = FW_PORT_CAP_FEC_RS; 3696 else if (lc->requested_fec & FEC_BASER_RS) 3697 fec = FW_PORT_CAP_FEC_BASER_RS; 3698 else if (lc->requested_fec & FEC_RESERVED) 3699 fec = FW_PORT_CAP_FEC_RESERVED; 3700 3701 if (!(lc->supported & FW_PORT_CAP_ANEG) || 3702 lc->requested_aneg == AUTONEG_DISABLE) { 3703 aneg = 0; 3704 switch (lc->requested_speed) { 3705 case 100: 3706 speed = FW_PORT_CAP_SPEED_100G; 3707 break; 3708 case 40: 3709 speed = FW_PORT_CAP_SPEED_40G; 3710 break; 3711 case 25: 3712 speed = FW_PORT_CAP_SPEED_25G; 3713 break; 3714 case 10: 3715 speed = FW_PORT_CAP_SPEED_10G; 3716 break; 3717 case 1: 3718 speed = FW_PORT_CAP_SPEED_1G; 3719 break; 3720 default: 3721 return -EINVAL; 3722 break; 3723 } 3724 } else { 3725 aneg = FW_PORT_CAP_ANEG; 3726 speed = lc->supported & 3727 V_FW_PORT_CAP_SPEED(M_FW_PORT_CAP_SPEED); 3728 } 3729 3730 memset(&c, 0, sizeof(c)); 3731 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3732 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3733 V_FW_PORT_CMD_PORTID(port)); 3734 c.action_to_len16 = 3735 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3736 FW_LEN16(c)); 3737 c.u.l1cfg.rcap = cpu_to_be32(aneg | speed | fc | fec | mdi); 3738 3739 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3740 } 3741 3742 /** 3743 * t4_restart_aneg - restart autonegotiation 3744 * @adap: the adapter 3745 * @mbox: mbox to use for the FW command 3746 * @port: the port id 3747 * 3748 * Restarts autonegotiation for the selected port. 3749 */ 3750 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3751 { 3752 struct fw_port_cmd c; 3753 3754 memset(&c, 0, sizeof(c)); 3755 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3756 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3757 V_FW_PORT_CMD_PORTID(port)); 3758 c.action_to_len16 = 3759 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3760 FW_LEN16(c)); 3761 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3762 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3763 } 3764 3765 typedef void (*int_handler_t)(struct adapter *adap); 3766 3767 struct intr_info { 3768 unsigned int mask; /* bits to check in interrupt status */ 3769 const char *msg; /* message to print or NULL */ 3770 short stat_idx; /* stat counter to increment or -1 */ 3771 unsigned short fatal; /* whether the condition reported is fatal */ 3772 int_handler_t int_handler; /* platform-specific int handler */ 3773 }; 3774 3775 /** 3776 * t4_handle_intr_status - table driven interrupt handler 3777 * @adapter: the adapter that generated the interrupt 3778 * @reg: the interrupt status register to process 3779 * @acts: table of interrupt actions 3780 * 3781 * A table driven interrupt handler that applies a set of masks to an 3782 * interrupt status word and performs the corresponding actions if the 3783 * interrupts described by the mask have occurred. The actions include 3784 * optionally emitting a warning or alert message. The table is terminated 3785 * by an entry specifying mask 0. Returns the number of fatal interrupt 3786 * conditions. 3787 */ 3788 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 3789 const struct intr_info *acts) 3790 { 3791 int fatal = 0; 3792 unsigned int mask = 0; 3793 unsigned int status = t4_read_reg(adapter, reg); 3794 3795 for ( ; acts->mask; ++acts) { 3796 if (!(status & acts->mask)) 3797 continue; 3798 if (acts->fatal) { 3799 fatal++; 3800 CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, 3801 status & acts->mask); 3802 } else if (acts->msg) 3803 CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg, 3804 status & acts->mask); 3805 if (acts->int_handler) 3806 acts->int_handler(adapter); 3807 mask |= acts->mask; 3808 } 3809 status &= mask; 3810 if (status) /* clear processed interrupts */ 3811 t4_write_reg(adapter, reg, status); 3812 return fatal; 3813 } 3814 3815 /* 3816 * Interrupt handler for the PCIE module. 3817 */ 3818 static void pcie_intr_handler(struct adapter *adapter) 3819 { 3820 static const struct intr_info sysbus_intr_info[] = { 3821 { F_RNPP, "RXNP array parity error", -1, 1 }, 3822 { F_RPCP, "RXPC array parity error", -1, 1 }, 3823 { F_RCIP, "RXCIF array parity error", -1, 1 }, 3824 { F_RCCP, "Rx completions control array parity error", -1, 1 }, 3825 { F_RFTP, "RXFT array parity error", -1, 1 }, 3826 { 0 } 3827 }; 3828 static const struct intr_info pcie_port_intr_info[] = { 3829 { F_TPCP, "TXPC array parity error", -1, 1 }, 3830 { F_TNPP, "TXNP array parity error", -1, 1 }, 3831 { F_TFTP, "TXFT array parity error", -1, 1 }, 3832 { F_TCAP, "TXCA array parity error", -1, 1 }, 3833 { F_TCIP, "TXCIF array parity error", -1, 1 }, 3834 { F_RCAP, "RXCA array parity error", -1, 1 }, 3835 { F_OTDD, "outbound request TLP discarded", -1, 1 }, 3836 { F_RDPE, "Rx data parity error", -1, 1 }, 3837 { F_TDUE, "Tx uncorrectable data error", -1, 1 }, 3838 { 0 } 3839 }; 3840 static const struct intr_info pcie_intr_info[] = { 3841 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 3842 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 3843 { F_MSIDATAPERR, "MSI data parity error", -1, 1 }, 3844 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 3845 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 3846 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 3847 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 3848 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 3849 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 3850 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 3851 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 3852 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 3853 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 3854 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 3855 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 3856 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 3857 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 3858 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 3859 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 3860 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 3861 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 3862 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 3863 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 }, 3864 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 3865 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 3866 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 }, 3867 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 }, 3868 { F_PCIESINT, "PCI core secondary fault", -1, 1 }, 3869 { F_PCIEPINT, "PCI core primary fault", -1, 1 }, 3870 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1, 3871 0 }, 3872 { 0 } 3873 }; 3874 3875 static const struct intr_info t5_pcie_intr_info[] = { 3876 { F_MSTGRPPERR, "Master Response Read Queue parity error", 3877 -1, 1 }, 3878 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 3879 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 3880 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 3881 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 3882 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 3883 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 3884 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 3885 -1, 1 }, 3886 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 3887 -1, 1 }, 3888 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 3889 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 3890 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 3891 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 3892 { F_DREQWRPERR, "PCI DMA channel write request parity error", 3893 -1, 1 }, 3894 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 3895 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 3896 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 3897 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 3898 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 3899 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 3900 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 3901 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 3902 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 3903 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 3904 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 3905 -1, 1 }, 3906 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 3907 -1, 1 }, 3908 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 3909 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 3910 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 3911 { F_READRSPERR, "Outbound read error", -1, 3912 0 }, 3913 { 0 } 3914 }; 3915 3916 int fat; 3917 3918 if (is_t4(adapter)) 3919 fat = t4_handle_intr_status(adapter, 3920 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 3921 sysbus_intr_info) + 3922 t4_handle_intr_status(adapter, 3923 A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 3924 pcie_port_intr_info) + 3925 t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 3926 pcie_intr_info); 3927 else 3928 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 3929 t5_pcie_intr_info); 3930 if (fat) 3931 t4_fatal_err(adapter); 3932 } 3933 3934 /* 3935 * TP interrupt handler. 3936 */ 3937 static void tp_intr_handler(struct adapter *adapter) 3938 { 3939 static const struct intr_info tp_intr_info[] = { 3940 { 0x3fffffff, "TP parity error", -1, 1 }, 3941 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 3942 { 0 } 3943 }; 3944 3945 if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info)) 3946 t4_fatal_err(adapter); 3947 } 3948 3949 /* 3950 * SGE interrupt handler. 3951 */ 3952 static void sge_intr_handler(struct adapter *adapter) 3953 { 3954 u64 v; 3955 u32 err; 3956 3957 static const struct intr_info sge_intr_info[] = { 3958 { F_ERR_CPL_EXCEED_IQE_SIZE, 3959 "SGE received CPL exceeding IQE size", -1, 1 }, 3960 { F_ERR_INVALID_CIDX_INC, 3961 "SGE GTS CIDX increment too large", -1, 0 }, 3962 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 3963 { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, 3964 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 3965 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 3966 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 3967 0 }, 3968 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 3969 0 }, 3970 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 3971 0 }, 3972 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 3973 0 }, 3974 { F_ERR_ING_CTXT_PRIO, 3975 "SGE too many priority ingress contexts", -1, 0 }, 3976 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 3977 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 3978 { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | 3979 F_ERR_PCIE_ERROR2 | F_ERR_PCIE_ERROR3, 3980 "SGE PCIe error for a DBP thread", -1, 0 }, 3981 { 0 } 3982 }; 3983 3984 static const struct intr_info t4t5_sge_intr_info[] = { 3985 { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, 3986 { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, 3987 { F_ERR_EGR_CTXT_PRIO, 3988 "SGE too many priority egress contexts", -1, 0 }, 3989 { 0 } 3990 }; 3991 3992 /* 3993 * For now, treat below interrupts as fatal so that we disable SGE and 3994 * get better debug */ 3995 static const struct intr_info t6_sge_intr_info[] = { 3996 { F_FATAL_WRE_LEN, 3997 "SGE Actual WRE packet is less than advertized length", 3998 -1, 1 }, 3999 { 0 } 4000 }; 4001 4002 v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | 4003 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); 4004 if (v) { 4005 CH_ALERT(adapter, "SGE parity error (%#llx)\n", 4006 (unsigned long long)v); 4007 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); 4008 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); 4009 } 4010 4011 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info); 4012 if (chip_id(adapter) <= CHELSIO_T5) 4013 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4014 t4t5_sge_intr_info); 4015 else 4016 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4017 t6_sge_intr_info); 4018 4019 err = t4_read_reg(adapter, A_SGE_ERROR_STATS); 4020 if (err & F_ERROR_QID_VALID) { 4021 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err)); 4022 if (err & F_UNCAPTURED_ERROR) 4023 CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4024 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID | 4025 F_UNCAPTURED_ERROR); 4026 } 4027 4028 if (v != 0) 4029 t4_fatal_err(adapter); 4030 } 4031 4032 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\ 4033 F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR) 4034 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\ 4035 F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR) 4036 4037 /* 4038 * CIM interrupt handler. 4039 */ 4040 static void cim_intr_handler(struct adapter *adapter) 4041 { 4042 static const struct intr_info cim_intr_info[] = { 4043 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 4044 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 4045 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 4046 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 4047 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 4048 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 4049 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 4050 { F_TIMER0INT, "CIM TIMER0 interrupt", -1, 1 }, 4051 { 0 } 4052 }; 4053 static const struct intr_info cim_upintr_info[] = { 4054 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 4055 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 4056 { F_ILLWRINT, "CIM illegal write", -1, 1 }, 4057 { F_ILLRDINT, "CIM illegal read", -1, 1 }, 4058 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 4059 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 4060 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 4061 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 4062 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 4063 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 4064 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 4065 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 4066 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 4067 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 4068 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 4069 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 4070 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 4071 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 4072 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 4073 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 4074 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 4075 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 4076 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 4077 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 4078 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 4079 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 4080 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 4081 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 4082 { 0 } 4083 }; 4084 u32 val, fw_err; 4085 int fat; 4086 4087 fw_err = t4_read_reg(adapter, A_PCIE_FW); 4088 if (fw_err & F_PCIE_FW_ERR) 4089 t4_report_fw_error(adapter); 4090 4091 /* When the Firmware detects an internal error which normally wouldn't 4092 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4093 * to make sure the Host sees the Firmware Crash. So if we have a 4094 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4095 * interrupt. 4096 */ 4097 val = t4_read_reg(adapter, A_CIM_HOST_INT_CAUSE); 4098 if (val & F_TIMER0INT) 4099 if (!(fw_err & F_PCIE_FW_ERR) || 4100 (G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) 4101 t4_write_reg(adapter, A_CIM_HOST_INT_CAUSE, 4102 F_TIMER0INT); 4103 4104 fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 4105 cim_intr_info) + 4106 t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE, 4107 cim_upintr_info); 4108 if (fat) 4109 t4_fatal_err(adapter); 4110 } 4111 4112 /* 4113 * ULP RX interrupt handler. 4114 */ 4115 static void ulprx_intr_handler(struct adapter *adapter) 4116 { 4117 static const struct intr_info ulprx_intr_info[] = { 4118 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 }, 4119 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 }, 4120 { 0x7fffff, "ULPRX parity error", -1, 1 }, 4121 { 0 } 4122 }; 4123 4124 if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info)) 4125 t4_fatal_err(adapter); 4126 } 4127 4128 /* 4129 * ULP TX interrupt handler. 4130 */ 4131 static void ulptx_intr_handler(struct adapter *adapter) 4132 { 4133 static const struct intr_info ulptx_intr_info[] = { 4134 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 4135 0 }, 4136 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 4137 0 }, 4138 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 4139 0 }, 4140 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 4141 0 }, 4142 { 0xfffffff, "ULPTX parity error", -1, 1 }, 4143 { 0 } 4144 }; 4145 4146 if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info)) 4147 t4_fatal_err(adapter); 4148 } 4149 4150 /* 4151 * PM TX interrupt handler. 4152 */ 4153 static void pmtx_intr_handler(struct adapter *adapter) 4154 { 4155 static const struct intr_info pmtx_intr_info[] = { 4156 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 4157 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 4158 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 4159 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 4160 { 0xffffff0, "PMTX framing error", -1, 1 }, 4161 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 4162 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 4163 1 }, 4164 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 4165 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 4166 { 0 } 4167 }; 4168 4169 if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info)) 4170 t4_fatal_err(adapter); 4171 } 4172 4173 /* 4174 * PM RX interrupt handler. 4175 */ 4176 static void pmrx_intr_handler(struct adapter *adapter) 4177 { 4178 static const struct intr_info pmrx_intr_info[] = { 4179 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 4180 { 0x3ffff0, "PMRX framing error", -1, 1 }, 4181 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 4182 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 4183 1 }, 4184 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 4185 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 4186 { 0 } 4187 }; 4188 4189 if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info)) 4190 t4_fatal_err(adapter); 4191 } 4192 4193 /* 4194 * CPL switch interrupt handler. 4195 */ 4196 static void cplsw_intr_handler(struct adapter *adapter) 4197 { 4198 static const struct intr_info cplsw_intr_info[] = { 4199 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 4200 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 4201 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 4202 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 4203 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 4204 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 4205 { 0 } 4206 }; 4207 4208 if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info)) 4209 t4_fatal_err(adapter); 4210 } 4211 4212 /* 4213 * LE interrupt handler. 4214 */ 4215 static void le_intr_handler(struct adapter *adap) 4216 { 4217 unsigned int chip_ver = chip_id(adap); 4218 static const struct intr_info le_intr_info[] = { 4219 { F_LIPMISS, "LE LIP miss", -1, 0 }, 4220 { F_LIP0, "LE 0 LIP error", -1, 0 }, 4221 { F_PARITYERR, "LE parity error", -1, 1 }, 4222 { F_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4223 { F_REQQPARERR, "LE request queue parity error", -1, 1 }, 4224 { 0 } 4225 }; 4226 4227 static const struct intr_info t6_le_intr_info[] = { 4228 { F_T6_LIPMISS, "LE LIP miss", -1, 0 }, 4229 { F_T6_LIP0, "LE 0 LIP error", -1, 0 }, 4230 { F_TCAMINTPERR, "LE parity error", -1, 1 }, 4231 { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4232 { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 }, 4233 { 0 } 4234 }; 4235 4236 if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, 4237 (chip_ver <= CHELSIO_T5) ? 4238 le_intr_info : t6_le_intr_info)) 4239 t4_fatal_err(adap); 4240 } 4241 4242 /* 4243 * MPS interrupt handler. 4244 */ 4245 static void mps_intr_handler(struct adapter *adapter) 4246 { 4247 static const struct intr_info mps_rx_intr_info[] = { 4248 { 0xffffff, "MPS Rx parity error", -1, 1 }, 4249 { 0 } 4250 }; 4251 static const struct intr_info mps_tx_intr_info[] = { 4252 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 }, 4253 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 4254 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error", 4255 -1, 1 }, 4256 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error", 4257 -1, 1 }, 4258 { F_BUBBLE, "MPS Tx underflow", -1, 1 }, 4259 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 4260 { F_FRMERR, "MPS Tx framing error", -1, 1 }, 4261 { 0 } 4262 }; 4263 static const struct intr_info mps_trc_intr_info[] = { 4264 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 }, 4265 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1, 4266 1 }, 4267 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 }, 4268 { 0 } 4269 }; 4270 static const struct intr_info mps_stat_sram_intr_info[] = { 4271 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 4272 { 0 } 4273 }; 4274 static const struct intr_info mps_stat_tx_intr_info[] = { 4275 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 4276 { 0 } 4277 }; 4278 static const struct intr_info mps_stat_rx_intr_info[] = { 4279 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 4280 { 0 } 4281 }; 4282 static const struct intr_info mps_cls_intr_info[] = { 4283 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 4284 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 4285 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 4286 { 0 } 4287 }; 4288 4289 int fat; 4290 4291 fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE, 4292 mps_rx_intr_info) + 4293 t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE, 4294 mps_tx_intr_info) + 4295 t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE, 4296 mps_trc_intr_info) + 4297 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4298 mps_stat_sram_intr_info) + 4299 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4300 mps_stat_tx_intr_info) + 4301 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4302 mps_stat_rx_intr_info) + 4303 t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE, 4304 mps_cls_intr_info); 4305 4306 t4_write_reg(adapter, A_MPS_INT_CAUSE, 0); 4307 t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ 4308 if (fat) 4309 t4_fatal_err(adapter); 4310 } 4311 4312 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \ 4313 F_ECC_UE_INT_CAUSE) 4314 4315 /* 4316 * EDC/MC interrupt handler. 4317 */ 4318 static void mem_intr_handler(struct adapter *adapter, int idx) 4319 { 4320 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; 4321 4322 unsigned int addr, cnt_addr, v; 4323 4324 if (idx <= MEM_EDC1) { 4325 addr = EDC_REG(A_EDC_INT_CAUSE, idx); 4326 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); 4327 } else if (idx == MEM_MC) { 4328 if (is_t4(adapter)) { 4329 addr = A_MC_INT_CAUSE; 4330 cnt_addr = A_MC_ECC_STATUS; 4331 } else { 4332 addr = A_MC_P_INT_CAUSE; 4333 cnt_addr = A_MC_P_ECC_STATUS; 4334 } 4335 } else { 4336 addr = MC_REG(A_MC_P_INT_CAUSE, 1); 4337 cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1); 4338 } 4339 4340 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 4341 if (v & F_PERR_INT_CAUSE) 4342 CH_ALERT(adapter, "%s FIFO parity error\n", 4343 name[idx]); 4344 if (v & F_ECC_CE_INT_CAUSE) { 4345 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); 4346 4347 if (idx <= MEM_EDC1) 4348 t4_edc_err_read(adapter, idx); 4349 4350 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); 4351 CH_WARN_RATELIMIT(adapter, 4352 "%u %s correctable ECC data error%s\n", 4353 cnt, name[idx], cnt > 1 ? "s" : ""); 4354 } 4355 if (v & F_ECC_UE_INT_CAUSE) 4356 CH_ALERT(adapter, 4357 "%s uncorrectable ECC data error\n", name[idx]); 4358 4359 t4_write_reg(adapter, addr, v); 4360 if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE)) 4361 t4_fatal_err(adapter); 4362 } 4363 4364 /* 4365 * MA interrupt handler. 4366 */ 4367 static void ma_intr_handler(struct adapter *adapter) 4368 { 4369 u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); 4370 4371 if (status & F_MEM_PERR_INT_CAUSE) { 4372 CH_ALERT(adapter, 4373 "MA parity error, parity status %#x\n", 4374 t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); 4375 if (is_t5(adapter)) 4376 CH_ALERT(adapter, 4377 "MA parity error, parity status %#x\n", 4378 t4_read_reg(adapter, 4379 A_MA_PARITY_ERROR_STATUS2)); 4380 } 4381 if (status & F_MEM_WRAP_INT_CAUSE) { 4382 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); 4383 CH_ALERT(adapter, "MA address wrap-around error by " 4384 "client %u to address %#x\n", 4385 G_MEM_WRAP_CLIENT_NUM(v), 4386 G_MEM_WRAP_ADDRESS(v) << 4); 4387 } 4388 t4_write_reg(adapter, A_MA_INT_CAUSE, status); 4389 t4_fatal_err(adapter); 4390 } 4391 4392 /* 4393 * SMB interrupt handler. 4394 */ 4395 static void smb_intr_handler(struct adapter *adap) 4396 { 4397 static const struct intr_info smb_intr_info[] = { 4398 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 4399 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 4400 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 4401 { 0 } 4402 }; 4403 4404 if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info)) 4405 t4_fatal_err(adap); 4406 } 4407 4408 /* 4409 * NC-SI interrupt handler. 4410 */ 4411 static void ncsi_intr_handler(struct adapter *adap) 4412 { 4413 static const struct intr_info ncsi_intr_info[] = { 4414 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 4415 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 4416 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 4417 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 4418 { 0 } 4419 }; 4420 4421 if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info)) 4422 t4_fatal_err(adap); 4423 } 4424 4425 /* 4426 * XGMAC interrupt handler. 4427 */ 4428 static void xgmac_intr_handler(struct adapter *adap, int port) 4429 { 4430 u32 v, int_cause_reg; 4431 4432 if (is_t4(adap)) 4433 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 4434 else 4435 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 4436 4437 v = t4_read_reg(adap, int_cause_reg); 4438 4439 v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); 4440 if (!v) 4441 return; 4442 4443 if (v & F_TXFIFO_PRTY_ERR) 4444 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", 4445 port); 4446 if (v & F_RXFIFO_PRTY_ERR) 4447 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", 4448 port); 4449 t4_write_reg(adap, int_cause_reg, v); 4450 t4_fatal_err(adap); 4451 } 4452 4453 /* 4454 * PL interrupt handler. 4455 */ 4456 static void pl_intr_handler(struct adapter *adap) 4457 { 4458 static const struct intr_info pl_intr_info[] = { 4459 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4460 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 4461 { 0 } 4462 }; 4463 4464 static const struct intr_info t5_pl_intr_info[] = { 4465 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4466 { 0 } 4467 }; 4468 4469 if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, 4470 is_t4(adap) ? 4471 pl_intr_info : t5_pl_intr_info)) 4472 t4_fatal_err(adap); 4473 } 4474 4475 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 4476 4477 /** 4478 * t4_slow_intr_handler - control path interrupt handler 4479 * @adapter: the adapter 4480 * 4481 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 4482 * The designation 'slow' is because it involves register reads, while 4483 * data interrupts typically don't involve any MMIOs. 4484 */ 4485 int t4_slow_intr_handler(struct adapter *adapter) 4486 { 4487 u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE); 4488 4489 if (!(cause & GLBL_INTR_MASK)) 4490 return 0; 4491 if (cause & F_CIM) 4492 cim_intr_handler(adapter); 4493 if (cause & F_MPS) 4494 mps_intr_handler(adapter); 4495 if (cause & F_NCSI) 4496 ncsi_intr_handler(adapter); 4497 if (cause & F_PL) 4498 pl_intr_handler(adapter); 4499 if (cause & F_SMB) 4500 smb_intr_handler(adapter); 4501 if (cause & F_MAC0) 4502 xgmac_intr_handler(adapter, 0); 4503 if (cause & F_MAC1) 4504 xgmac_intr_handler(adapter, 1); 4505 if (cause & F_MAC2) 4506 xgmac_intr_handler(adapter, 2); 4507 if (cause & F_MAC3) 4508 xgmac_intr_handler(adapter, 3); 4509 if (cause & F_PCIE) 4510 pcie_intr_handler(adapter); 4511 if (cause & F_MC0) 4512 mem_intr_handler(adapter, MEM_MC); 4513 if (is_t5(adapter) && (cause & F_MC1)) 4514 mem_intr_handler(adapter, MEM_MC1); 4515 if (cause & F_EDC0) 4516 mem_intr_handler(adapter, MEM_EDC0); 4517 if (cause & F_EDC1) 4518 mem_intr_handler(adapter, MEM_EDC1); 4519 if (cause & F_LE) 4520 le_intr_handler(adapter); 4521 if (cause & F_TP) 4522 tp_intr_handler(adapter); 4523 if (cause & F_MA) 4524 ma_intr_handler(adapter); 4525 if (cause & F_PM_TX) 4526 pmtx_intr_handler(adapter); 4527 if (cause & F_PM_RX) 4528 pmrx_intr_handler(adapter); 4529 if (cause & F_ULP_RX) 4530 ulprx_intr_handler(adapter); 4531 if (cause & F_CPL_SWITCH) 4532 cplsw_intr_handler(adapter); 4533 if (cause & F_SGE) 4534 sge_intr_handler(adapter); 4535 if (cause & F_ULP_TX) 4536 ulptx_intr_handler(adapter); 4537 4538 /* Clear the interrupts just processed for which we are the master. */ 4539 t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK); 4540 (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4541 return 1; 4542 } 4543 4544 /** 4545 * t4_intr_enable - enable interrupts 4546 * @adapter: the adapter whose interrupts should be enabled 4547 * 4548 * Enable PF-specific interrupts for the calling function and the top-level 4549 * interrupt concentrator for global interrupts. Interrupts are already 4550 * enabled at each module, here we just enable the roots of the interrupt 4551 * hierarchies. 4552 * 4553 * Note: this function should be called only when the driver manages 4554 * non PF-specific interrupts from the various HW modules. Only one PCI 4555 * function at a time should be doing this. 4556 */ 4557 void t4_intr_enable(struct adapter *adapter) 4558 { 4559 u32 val = 0; 4560 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4561 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4562 ? G_SOURCEPF(whoami) 4563 : G_T6_SOURCEPF(whoami)); 4564 4565 if (chip_id(adapter) <= CHELSIO_T5) 4566 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 4567 else 4568 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 4569 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE | 4570 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 | 4571 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR | 4572 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 | 4573 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4574 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | 4575 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val); 4576 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 4577 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf); 4578 } 4579 4580 /** 4581 * t4_intr_disable - disable interrupts 4582 * @adapter: the adapter whose interrupts should be disabled 4583 * 4584 * Disable interrupts. We only disable the top-level interrupt 4585 * concentrators. The caller must be a PCI function managing global 4586 * interrupts. 4587 */ 4588 void t4_intr_disable(struct adapter *adapter) 4589 { 4590 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4591 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4592 ? G_SOURCEPF(whoami) 4593 : G_T6_SOURCEPF(whoami)); 4594 4595 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 4596 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0); 4597 } 4598 4599 /** 4600 * t4_intr_clear - clear all interrupts 4601 * @adapter: the adapter whose interrupts should be cleared 4602 * 4603 * Clears all interrupts. The caller must be a PCI function managing 4604 * global interrupts. 4605 */ 4606 void t4_intr_clear(struct adapter *adapter) 4607 { 4608 static const unsigned int cause_reg[] = { 4609 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3, 4610 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, 4611 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE, 4612 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), 4613 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, 4614 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4615 A_TP_INT_CAUSE, 4616 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE, 4617 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE, 4618 A_MPS_RX_PERR_INT_CAUSE, 4619 A_CPL_INTR_CAUSE, 4620 MYPF_REG(A_PL_PF_INT_CAUSE), 4621 A_PL_PL_INT_CAUSE, 4622 A_LE_DB_INT_CAUSE, 4623 }; 4624 4625 unsigned int i; 4626 4627 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) 4628 t4_write_reg(adapter, cause_reg[i], 0xffffffff); 4629 4630 t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : 4631 A_MC_P_INT_CAUSE, 0xffffffff); 4632 4633 if (is_t4(adapter)) { 4634 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4635 0xffffffff); 4636 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4637 0xffffffff); 4638 } else 4639 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 4640 4641 t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); 4642 (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4643 } 4644 4645 /** 4646 * hash_mac_addr - return the hash value of a MAC address 4647 * @addr: the 48-bit Ethernet MAC address 4648 * 4649 * Hashes a MAC address according to the hash function used by HW inexact 4650 * (hash) address matching. 4651 */ 4652 static int hash_mac_addr(const u8 *addr) 4653 { 4654 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 4655 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 4656 a ^= b; 4657 a ^= (a >> 12); 4658 a ^= (a >> 6); 4659 return a & 0x3f; 4660 } 4661 4662 /** 4663 * t4_config_rss_range - configure a portion of the RSS mapping table 4664 * @adapter: the adapter 4665 * @mbox: mbox to use for the FW command 4666 * @viid: virtual interface whose RSS subtable is to be written 4667 * @start: start entry in the table to write 4668 * @n: how many table entries to write 4669 * @rspq: values for the "response queue" (Ingress Queue) lookup table 4670 * @nrspq: number of values in @rspq 4671 * 4672 * Programs the selected part of the VI's RSS mapping table with the 4673 * provided values. If @nrspq < @n the supplied values are used repeatedly 4674 * until the full table range is populated. 4675 * 4676 * The caller must ensure the values in @rspq are in the range allowed for 4677 * @viid. 4678 */ 4679 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 4680 int start, int n, const u16 *rspq, unsigned int nrspq) 4681 { 4682 int ret; 4683 const u16 *rsp = rspq; 4684 const u16 *rsp_end = rspq + nrspq; 4685 struct fw_rss_ind_tbl_cmd cmd; 4686 4687 memset(&cmd, 0, sizeof(cmd)); 4688 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 4689 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4690 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 4691 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 4692 4693 /* 4694 * Each firmware RSS command can accommodate up to 32 RSS Ingress 4695 * Queue Identifiers. These Ingress Queue IDs are packed three to 4696 * a 32-bit word as 10-bit values with the upper remaining 2 bits 4697 * reserved. 4698 */ 4699 while (n > 0) { 4700 int nq = min(n, 32); 4701 int nq_packed = 0; 4702 __be32 *qp = &cmd.iq0_to_iq2; 4703 4704 /* 4705 * Set up the firmware RSS command header to send the next 4706 * "nq" Ingress Queue IDs to the firmware. 4707 */ 4708 cmd.niqid = cpu_to_be16(nq); 4709 cmd.startidx = cpu_to_be16(start); 4710 4711 /* 4712 * "nq" more done for the start of the next loop. 4713 */ 4714 start += nq; 4715 n -= nq; 4716 4717 /* 4718 * While there are still Ingress Queue IDs to stuff into the 4719 * current firmware RSS command, retrieve them from the 4720 * Ingress Queue ID array and insert them into the command. 4721 */ 4722 while (nq > 0) { 4723 /* 4724 * Grab up to the next 3 Ingress Queue IDs (wrapping 4725 * around the Ingress Queue ID array if necessary) and 4726 * insert them into the firmware RSS command at the 4727 * current 3-tuple position within the commad. 4728 */ 4729 u16 qbuf[3]; 4730 u16 *qbp = qbuf; 4731 int nqbuf = min(3, nq); 4732 4733 nq -= nqbuf; 4734 qbuf[0] = qbuf[1] = qbuf[2] = 0; 4735 while (nqbuf && nq_packed < 32) { 4736 nqbuf--; 4737 nq_packed++; 4738 *qbp++ = *rsp++; 4739 if (rsp >= rsp_end) 4740 rsp = rspq; 4741 } 4742 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 4743 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 4744 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 4745 } 4746 4747 /* 4748 * Send this portion of the RRS table update to the firmware; 4749 * bail out on any errors. 4750 */ 4751 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 4752 if (ret) 4753 return ret; 4754 } 4755 return 0; 4756 } 4757 4758 /** 4759 * t4_config_glbl_rss - configure the global RSS mode 4760 * @adapter: the adapter 4761 * @mbox: mbox to use for the FW command 4762 * @mode: global RSS mode 4763 * @flags: mode-specific flags 4764 * 4765 * Sets the global RSS mode. 4766 */ 4767 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 4768 unsigned int flags) 4769 { 4770 struct fw_rss_glb_config_cmd c; 4771 4772 memset(&c, 0, sizeof(c)); 4773 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 4774 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 4775 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4776 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 4777 c.u.manual.mode_pkd = 4778 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4779 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 4780 c.u.basicvirtual.mode_keymode = 4781 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4782 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 4783 } else 4784 return -EINVAL; 4785 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4786 } 4787 4788 /** 4789 * t4_config_vi_rss - configure per VI RSS settings 4790 * @adapter: the adapter 4791 * @mbox: mbox to use for the FW command 4792 * @viid: the VI id 4793 * @flags: RSS flags 4794 * @defq: id of the default RSS queue for the VI. 4795 * @skeyidx: RSS secret key table index for non-global mode 4796 * @skey: RSS vf_scramble key for VI. 4797 * 4798 * Configures VI-specific RSS properties. 4799 */ 4800 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 4801 unsigned int flags, unsigned int defq, unsigned int skeyidx, 4802 unsigned int skey) 4803 { 4804 struct fw_rss_vi_config_cmd c; 4805 4806 memset(&c, 0, sizeof(c)); 4807 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 4808 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4809 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 4810 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4811 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 4812 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 4813 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 4814 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 4815 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 4816 4817 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4818 } 4819 4820 /* Read an RSS table row */ 4821 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 4822 { 4823 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 4824 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 4825 5, 0, val); 4826 } 4827 4828 /** 4829 * t4_read_rss - read the contents of the RSS mapping table 4830 * @adapter: the adapter 4831 * @map: holds the contents of the RSS mapping table 4832 * 4833 * Reads the contents of the RSS hash->queue mapping table. 4834 */ 4835 int t4_read_rss(struct adapter *adapter, u16 *map) 4836 { 4837 u32 val; 4838 int i, ret; 4839 4840 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 4841 ret = rd_rss_row(adapter, i, &val); 4842 if (ret) 4843 return ret; 4844 *map++ = G_LKPTBLQUEUE0(val); 4845 *map++ = G_LKPTBLQUEUE1(val); 4846 } 4847 return 0; 4848 } 4849 4850 /** 4851 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 4852 * @adap: the adapter 4853 * @cmd: TP fw ldst address space type 4854 * @vals: where the indirect register values are stored/written 4855 * @nregs: how many indirect registers to read/write 4856 * @start_idx: index of first indirect register to read/write 4857 * @rw: Read (1) or Write (0) 4858 * @sleep_ok: if true we may sleep while awaiting command completion 4859 * 4860 * Access TP indirect registers through LDST 4861 **/ 4862 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 4863 unsigned int nregs, unsigned int start_index, 4864 unsigned int rw, bool sleep_ok) 4865 { 4866 int ret = 0; 4867 unsigned int i; 4868 struct fw_ldst_cmd c; 4869 4870 for (i = 0; i < nregs; i++) { 4871 memset(&c, 0, sizeof(c)); 4872 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 4873 F_FW_CMD_REQUEST | 4874 (rw ? F_FW_CMD_READ : 4875 F_FW_CMD_WRITE) | 4876 V_FW_LDST_CMD_ADDRSPACE(cmd)); 4877 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 4878 4879 c.u.addrval.addr = cpu_to_be32(start_index + i); 4880 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 4881 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 4882 sleep_ok); 4883 if (ret) 4884 return ret; 4885 4886 if (rw) 4887 vals[i] = be32_to_cpu(c.u.addrval.val); 4888 } 4889 return 0; 4890 } 4891 4892 /** 4893 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 4894 * @adap: the adapter 4895 * @reg_addr: Address Register 4896 * @reg_data: Data register 4897 * @buff: where the indirect register values are stored/written 4898 * @nregs: how many indirect registers to read/write 4899 * @start_index: index of first indirect register to read/write 4900 * @rw: READ(1) or WRITE(0) 4901 * @sleep_ok: if true we may sleep while awaiting command completion 4902 * 4903 * Read/Write TP indirect registers through LDST if possible. 4904 * Else, use backdoor access 4905 **/ 4906 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 4907 u32 *buff, u32 nregs, u32 start_index, int rw, 4908 bool sleep_ok) 4909 { 4910 int rc = -EINVAL; 4911 int cmd; 4912 4913 switch (reg_addr) { 4914 case A_TP_PIO_ADDR: 4915 cmd = FW_LDST_ADDRSPC_TP_PIO; 4916 break; 4917 case A_TP_TM_PIO_ADDR: 4918 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 4919 break; 4920 case A_TP_MIB_INDEX: 4921 cmd = FW_LDST_ADDRSPC_TP_MIB; 4922 break; 4923 default: 4924 goto indirect_access; 4925 } 4926 4927 if (t4_use_ldst(adap)) 4928 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 4929 sleep_ok); 4930 4931 indirect_access: 4932 4933 if (rc) { 4934 if (rw) 4935 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 4936 start_index); 4937 else 4938 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 4939 start_index); 4940 } 4941 } 4942 4943 /** 4944 * t4_tp_pio_read - Read TP PIO registers 4945 * @adap: the adapter 4946 * @buff: where the indirect register values are written 4947 * @nregs: how many indirect registers to read 4948 * @start_index: index of first indirect register to read 4949 * @sleep_ok: if true we may sleep while awaiting command completion 4950 * 4951 * Read TP PIO Registers 4952 **/ 4953 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 4954 u32 start_index, bool sleep_ok) 4955 { 4956 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 4957 start_index, 1, sleep_ok); 4958 } 4959 4960 /** 4961 * t4_tp_pio_write - Write TP PIO registers 4962 * @adap: the adapter 4963 * @buff: where the indirect register values are stored 4964 * @nregs: how many indirect registers to write 4965 * @start_index: index of first indirect register to write 4966 * @sleep_ok: if true we may sleep while awaiting command completion 4967 * 4968 * Write TP PIO Registers 4969 **/ 4970 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 4971 u32 start_index, bool sleep_ok) 4972 { 4973 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 4974 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 4975 } 4976 4977 /** 4978 * t4_tp_tm_pio_read - Read TP TM PIO registers 4979 * @adap: the adapter 4980 * @buff: where the indirect register values are written 4981 * @nregs: how many indirect registers to read 4982 * @start_index: index of first indirect register to read 4983 * @sleep_ok: if true we may sleep while awaiting command completion 4984 * 4985 * Read TP TM PIO Registers 4986 **/ 4987 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 4988 u32 start_index, bool sleep_ok) 4989 { 4990 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 4991 nregs, start_index, 1, sleep_ok); 4992 } 4993 4994 /** 4995 * t4_tp_mib_read - Read TP MIB registers 4996 * @adap: the adapter 4997 * @buff: where the indirect register values are written 4998 * @nregs: how many indirect registers to read 4999 * @start_index: index of first indirect register to read 5000 * @sleep_ok: if true we may sleep while awaiting command completion 5001 * 5002 * Read TP MIB Registers 5003 **/ 5004 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5005 bool sleep_ok) 5006 { 5007 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5008 start_index, 1, sleep_ok); 5009 } 5010 5011 /** 5012 * t4_read_rss_key - read the global RSS key 5013 * @adap: the adapter 5014 * @key: 10-entry array holding the 320-bit RSS key 5015 * @sleep_ok: if true we may sleep while awaiting command completion 5016 * 5017 * Reads the global 320-bit RSS key. 5018 */ 5019 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5020 { 5021 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5022 } 5023 5024 /** 5025 * t4_write_rss_key - program one of the RSS keys 5026 * @adap: the adapter 5027 * @key: 10-entry array holding the 320-bit RSS key 5028 * @idx: which RSS key to write 5029 * @sleep_ok: if true we may sleep while awaiting command completion 5030 * 5031 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5032 * 0..15 the corresponding entry in the RSS key table is written, 5033 * otherwise the global RSS key is written. 5034 */ 5035 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5036 bool sleep_ok) 5037 { 5038 u8 rss_key_addr_cnt = 16; 5039 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5040 5041 /* 5042 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5043 * allows access to key addresses 16-63 by using KeyWrAddrX 5044 * as index[5:4](upper 2) into key table 5045 */ 5046 if ((chip_id(adap) > CHELSIO_T5) && 5047 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5048 rss_key_addr_cnt = 32; 5049 5050 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5051 5052 if (idx >= 0 && idx < rss_key_addr_cnt) { 5053 if (rss_key_addr_cnt > 16) 5054 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5055 vrt | V_KEYWRADDRX(idx >> 4) | 5056 V_T6_VFWRADDR(idx) | F_KEYWREN); 5057 else 5058 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5059 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5060 } 5061 } 5062 5063 /** 5064 * t4_read_rss_pf_config - read PF RSS Configuration Table 5065 * @adapter: the adapter 5066 * @index: the entry in the PF RSS table to read 5067 * @valp: where to store the returned value 5068 * @sleep_ok: if true we may sleep while awaiting command completion 5069 * 5070 * Reads the PF RSS Configuration Table at the specified index and returns 5071 * the value found there. 5072 */ 5073 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5074 u32 *valp, bool sleep_ok) 5075 { 5076 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5077 } 5078 5079 /** 5080 * t4_write_rss_pf_config - write PF RSS Configuration Table 5081 * @adapter: the adapter 5082 * @index: the entry in the VF RSS table to read 5083 * @val: the value to store 5084 * @sleep_ok: if true we may sleep while awaiting command completion 5085 * 5086 * Writes the PF RSS Configuration Table at the specified index with the 5087 * specified value. 5088 */ 5089 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5090 u32 val, bool sleep_ok) 5091 { 5092 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5093 sleep_ok); 5094 } 5095 5096 /** 5097 * t4_read_rss_vf_config - read VF RSS Configuration Table 5098 * @adapter: the adapter 5099 * @index: the entry in the VF RSS table to read 5100 * @vfl: where to store the returned VFL 5101 * @vfh: where to store the returned VFH 5102 * @sleep_ok: if true we may sleep while awaiting command completion 5103 * 5104 * Reads the VF RSS Configuration Table at the specified index and returns 5105 * the (VFL, VFH) values found there. 5106 */ 5107 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5108 u32 *vfl, u32 *vfh, bool sleep_ok) 5109 { 5110 u32 vrt, mask, data; 5111 5112 if (chip_id(adapter) <= CHELSIO_T5) { 5113 mask = V_VFWRADDR(M_VFWRADDR); 5114 data = V_VFWRADDR(index); 5115 } else { 5116 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5117 data = V_T6_VFWRADDR(index); 5118 } 5119 /* 5120 * Request that the index'th VF Table values be read into VFL/VFH. 5121 */ 5122 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5123 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5124 vrt |= data | F_VFRDEN; 5125 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5126 5127 /* 5128 * Grab the VFL/VFH values ... 5129 */ 5130 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5131 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5132 } 5133 5134 /** 5135 * t4_write_rss_vf_config - write VF RSS Configuration Table 5136 * 5137 * @adapter: the adapter 5138 * @index: the entry in the VF RSS table to write 5139 * @vfl: the VFL to store 5140 * @vfh: the VFH to store 5141 * 5142 * Writes the VF RSS Configuration Table at the specified index with the 5143 * specified (VFL, VFH) values. 5144 */ 5145 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 5146 u32 vfl, u32 vfh, bool sleep_ok) 5147 { 5148 u32 vrt, mask, data; 5149 5150 if (chip_id(adapter) <= CHELSIO_T5) { 5151 mask = V_VFWRADDR(M_VFWRADDR); 5152 data = V_VFWRADDR(index); 5153 } else { 5154 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5155 data = V_T6_VFWRADDR(index); 5156 } 5157 5158 /* 5159 * Load up VFL/VFH with the values to be written ... 5160 */ 5161 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5162 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5163 5164 /* 5165 * Write the VFL/VFH into the VF Table at index'th location. 5166 */ 5167 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5168 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5169 vrt |= data | F_VFRDEN; 5170 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5171 } 5172 5173 /** 5174 * t4_read_rss_pf_map - read PF RSS Map 5175 * @adapter: the adapter 5176 * @sleep_ok: if true we may sleep while awaiting command completion 5177 * 5178 * Reads the PF RSS Map register and returns its value. 5179 */ 5180 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 5181 { 5182 u32 pfmap; 5183 5184 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5185 5186 return pfmap; 5187 } 5188 5189 /** 5190 * t4_write_rss_pf_map - write PF RSS Map 5191 * @adapter: the adapter 5192 * @pfmap: PF RSS Map value 5193 * 5194 * Writes the specified value to the PF RSS Map register. 5195 */ 5196 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 5197 { 5198 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5199 } 5200 5201 /** 5202 * t4_read_rss_pf_mask - read PF RSS Mask 5203 * @adapter: the adapter 5204 * @sleep_ok: if true we may sleep while awaiting command completion 5205 * 5206 * Reads the PF RSS Mask register and returns its value. 5207 */ 5208 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 5209 { 5210 u32 pfmask; 5211 5212 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5213 5214 return pfmask; 5215 } 5216 5217 /** 5218 * t4_write_rss_pf_mask - write PF RSS Mask 5219 * @adapter: the adapter 5220 * @pfmask: PF RSS Mask value 5221 * 5222 * Writes the specified value to the PF RSS Mask register. 5223 */ 5224 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 5225 { 5226 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5227 } 5228 5229 /** 5230 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 5231 * @adap: the adapter 5232 * @v4: holds the TCP/IP counter values 5233 * @v6: holds the TCP/IPv6 counter values 5234 * @sleep_ok: if true we may sleep while awaiting command completion 5235 * 5236 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 5237 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 5238 */ 5239 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 5240 struct tp_tcp_stats *v6, bool sleep_ok) 5241 { 5242 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 5243 5244 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 5245 #define STAT(x) val[STAT_IDX(x)] 5246 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 5247 5248 if (v4) { 5249 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5250 A_TP_MIB_TCP_OUT_RST, sleep_ok); 5251 v4->tcp_out_rsts = STAT(OUT_RST); 5252 v4->tcp_in_segs = STAT64(IN_SEG); 5253 v4->tcp_out_segs = STAT64(OUT_SEG); 5254 v4->tcp_retrans_segs = STAT64(RXT_SEG); 5255 } 5256 if (v6) { 5257 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5258 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 5259 v6->tcp_out_rsts = STAT(OUT_RST); 5260 v6->tcp_in_segs = STAT64(IN_SEG); 5261 v6->tcp_out_segs = STAT64(OUT_SEG); 5262 v6->tcp_retrans_segs = STAT64(RXT_SEG); 5263 } 5264 #undef STAT64 5265 #undef STAT 5266 #undef STAT_IDX 5267 } 5268 5269 /** 5270 * t4_tp_get_err_stats - read TP's error MIB counters 5271 * @adap: the adapter 5272 * @st: holds the counter values 5273 * @sleep_ok: if true we may sleep while awaiting command completion 5274 * 5275 * Returns the values of TP's error counters. 5276 */ 5277 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 5278 bool sleep_ok) 5279 { 5280 int nchan = adap->chip_params->nchan; 5281 5282 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 5283 sleep_ok); 5284 5285 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 5286 sleep_ok); 5287 5288 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 5289 sleep_ok); 5290 5291 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 5292 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 5293 5294 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 5295 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 5296 5297 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 5298 sleep_ok); 5299 5300 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 5301 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 5302 5303 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 5304 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 5305 5306 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 5307 sleep_ok); 5308 } 5309 5310 /** 5311 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 5312 * @adap: the adapter 5313 * @st: holds the counter values 5314 * 5315 * Returns the values of TP's proxy counters. 5316 */ 5317 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 5318 bool sleep_ok) 5319 { 5320 int nchan = adap->chip_params->nchan; 5321 5322 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 5323 } 5324 5325 /** 5326 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 5327 * @adap: the adapter 5328 * @st: holds the counter values 5329 * @sleep_ok: if true we may sleep while awaiting command completion 5330 * 5331 * Returns the values of TP's CPL counters. 5332 */ 5333 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 5334 bool sleep_ok) 5335 { 5336 int nchan = adap->chip_params->nchan; 5337 5338 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 5339 5340 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 5341 } 5342 5343 /** 5344 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 5345 * @adap: the adapter 5346 * @st: holds the counter values 5347 * 5348 * Returns the values of TP's RDMA counters. 5349 */ 5350 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 5351 bool sleep_ok) 5352 { 5353 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 5354 sleep_ok); 5355 } 5356 5357 /** 5358 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 5359 * @adap: the adapter 5360 * @idx: the port index 5361 * @st: holds the counter values 5362 * @sleep_ok: if true we may sleep while awaiting command completion 5363 * 5364 * Returns the values of TP's FCoE counters for the selected port. 5365 */ 5366 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 5367 struct tp_fcoe_stats *st, bool sleep_ok) 5368 { 5369 u32 val[2]; 5370 5371 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 5372 sleep_ok); 5373 5374 t4_tp_mib_read(adap, &st->frames_drop, 1, 5375 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 5376 5377 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 5378 sleep_ok); 5379 5380 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 5381 } 5382 5383 /** 5384 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 5385 * @adap: the adapter 5386 * @st: holds the counter values 5387 * @sleep_ok: if true we may sleep while awaiting command completion 5388 * 5389 * Returns the values of TP's counters for non-TCP directly-placed packets. 5390 */ 5391 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 5392 bool sleep_ok) 5393 { 5394 u32 val[4]; 5395 5396 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 5397 5398 st->frames = val[0]; 5399 st->drops = val[1]; 5400 st->octets = ((u64)val[2] << 32) | val[3]; 5401 } 5402 5403 /** 5404 * t4_read_mtu_tbl - returns the values in the HW path MTU table 5405 * @adap: the adapter 5406 * @mtus: where to store the MTU values 5407 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 5408 * 5409 * Reads the HW path MTU table. 5410 */ 5411 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 5412 { 5413 u32 v; 5414 int i; 5415 5416 for (i = 0; i < NMTUS; ++i) { 5417 t4_write_reg(adap, A_TP_MTU_TABLE, 5418 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 5419 v = t4_read_reg(adap, A_TP_MTU_TABLE); 5420 mtus[i] = G_MTUVALUE(v); 5421 if (mtu_log) 5422 mtu_log[i] = G_MTUWIDTH(v); 5423 } 5424 } 5425 5426 /** 5427 * t4_read_cong_tbl - reads the congestion control table 5428 * @adap: the adapter 5429 * @incr: where to store the alpha values 5430 * 5431 * Reads the additive increments programmed into the HW congestion 5432 * control table. 5433 */ 5434 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 5435 { 5436 unsigned int mtu, w; 5437 5438 for (mtu = 0; mtu < NMTUS; ++mtu) 5439 for (w = 0; w < NCCTRL_WIN; ++w) { 5440 t4_write_reg(adap, A_TP_CCTRL_TABLE, 5441 V_ROWINDEX(0xffff) | (mtu << 5) | w); 5442 incr[mtu][w] = (u16)t4_read_reg(adap, 5443 A_TP_CCTRL_TABLE) & 0x1fff; 5444 } 5445 } 5446 5447 /** 5448 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 5449 * @adap: the adapter 5450 * @addr: the indirect TP register address 5451 * @mask: specifies the field within the register to modify 5452 * @val: new value for the field 5453 * 5454 * Sets a field of an indirect TP register to the given value. 5455 */ 5456 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 5457 unsigned int mask, unsigned int val) 5458 { 5459 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 5460 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 5461 t4_write_reg(adap, A_TP_PIO_DATA, val); 5462 } 5463 5464 /** 5465 * init_cong_ctrl - initialize congestion control parameters 5466 * @a: the alpha values for congestion control 5467 * @b: the beta values for congestion control 5468 * 5469 * Initialize the congestion control parameters. 5470 */ 5471 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 5472 { 5473 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 5474 a[9] = 2; 5475 a[10] = 3; 5476 a[11] = 4; 5477 a[12] = 5; 5478 a[13] = 6; 5479 a[14] = 7; 5480 a[15] = 8; 5481 a[16] = 9; 5482 a[17] = 10; 5483 a[18] = 14; 5484 a[19] = 17; 5485 a[20] = 21; 5486 a[21] = 25; 5487 a[22] = 30; 5488 a[23] = 35; 5489 a[24] = 45; 5490 a[25] = 60; 5491 a[26] = 80; 5492 a[27] = 100; 5493 a[28] = 200; 5494 a[29] = 300; 5495 a[30] = 400; 5496 a[31] = 500; 5497 5498 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 5499 b[9] = b[10] = 1; 5500 b[11] = b[12] = 2; 5501 b[13] = b[14] = b[15] = b[16] = 3; 5502 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 5503 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 5504 b[28] = b[29] = 6; 5505 b[30] = b[31] = 7; 5506 } 5507 5508 /* The minimum additive increment value for the congestion control table */ 5509 #define CC_MIN_INCR 2U 5510 5511 /** 5512 * t4_load_mtus - write the MTU and congestion control HW tables 5513 * @adap: the adapter 5514 * @mtus: the values for the MTU table 5515 * @alpha: the values for the congestion control alpha parameter 5516 * @beta: the values for the congestion control beta parameter 5517 * 5518 * Write the HW MTU table with the supplied MTUs and the high-speed 5519 * congestion control table with the supplied alpha, beta, and MTUs. 5520 * We write the two tables together because the additive increments 5521 * depend on the MTUs. 5522 */ 5523 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 5524 const unsigned short *alpha, const unsigned short *beta) 5525 { 5526 static const unsigned int avg_pkts[NCCTRL_WIN] = { 5527 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 5528 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 5529 28672, 40960, 57344, 81920, 114688, 163840, 229376 5530 }; 5531 5532 unsigned int i, w; 5533 5534 for (i = 0; i < NMTUS; ++i) { 5535 unsigned int mtu = mtus[i]; 5536 unsigned int log2 = fls(mtu); 5537 5538 if (!(mtu & ((1 << log2) >> 2))) /* round */ 5539 log2--; 5540 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 5541 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 5542 5543 for (w = 0; w < NCCTRL_WIN; ++w) { 5544 unsigned int inc; 5545 5546 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 5547 CC_MIN_INCR); 5548 5549 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 5550 (w << 16) | (beta[w] << 13) | inc); 5551 } 5552 } 5553 } 5554 5555 /** 5556 * t4_set_pace_tbl - set the pace table 5557 * @adap: the adapter 5558 * @pace_vals: the pace values in microseconds 5559 * @start: index of the first entry in the HW pace table to set 5560 * @n: how many entries to set 5561 * 5562 * Sets (a subset of the) HW pace table. 5563 */ 5564 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 5565 unsigned int start, unsigned int n) 5566 { 5567 unsigned int vals[NTX_SCHED], i; 5568 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 5569 5570 if (n > NTX_SCHED) 5571 return -ERANGE; 5572 5573 /* convert values from us to dack ticks, rounding to closest value */ 5574 for (i = 0; i < n; i++, pace_vals++) { 5575 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 5576 if (vals[i] > 0x7ff) 5577 return -ERANGE; 5578 if (*pace_vals && vals[i] == 0) 5579 return -ERANGE; 5580 } 5581 for (i = 0; i < n; i++, start++) 5582 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 5583 return 0; 5584 } 5585 5586 /** 5587 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 5588 * @adap: the adapter 5589 * @kbps: target rate in Kbps 5590 * @sched: the scheduler index 5591 * 5592 * Configure a Tx HW scheduler for the target rate. 5593 */ 5594 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 5595 { 5596 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 5597 unsigned int clk = adap->params.vpd.cclk * 1000; 5598 unsigned int selected_cpt = 0, selected_bpt = 0; 5599 5600 if (kbps > 0) { 5601 kbps *= 125; /* -> bytes */ 5602 for (cpt = 1; cpt <= 255; cpt++) { 5603 tps = clk / cpt; 5604 bpt = (kbps + tps / 2) / tps; 5605 if (bpt > 0 && bpt <= 255) { 5606 v = bpt * tps; 5607 delta = v >= kbps ? v - kbps : kbps - v; 5608 if (delta < mindelta) { 5609 mindelta = delta; 5610 selected_cpt = cpt; 5611 selected_bpt = bpt; 5612 } 5613 } else if (selected_cpt) 5614 break; 5615 } 5616 if (!selected_cpt) 5617 return -EINVAL; 5618 } 5619 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 5620 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 5621 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5622 if (sched & 1) 5623 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 5624 else 5625 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 5626 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5627 return 0; 5628 } 5629 5630 /** 5631 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 5632 * @adap: the adapter 5633 * @sched: the scheduler index 5634 * @ipg: the interpacket delay in tenths of nanoseconds 5635 * 5636 * Set the interpacket delay for a HW packet rate scheduler. 5637 */ 5638 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 5639 { 5640 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 5641 5642 /* convert ipg to nearest number of core clocks */ 5643 ipg *= core_ticks_per_usec(adap); 5644 ipg = (ipg + 5000) / 10000; 5645 if (ipg > M_TXTIMERSEPQ0) 5646 return -EINVAL; 5647 5648 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 5649 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5650 if (sched & 1) 5651 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 5652 else 5653 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 5654 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5655 t4_read_reg(adap, A_TP_TM_PIO_DATA); 5656 return 0; 5657 } 5658 5659 /* 5660 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 5661 * clocks. The formula is 5662 * 5663 * bytes/s = bytes256 * 256 * ClkFreq / 4096 5664 * 5665 * which is equivalent to 5666 * 5667 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 5668 */ 5669 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 5670 { 5671 u64 v = bytes256 * adap->params.vpd.cclk; 5672 5673 return v * 62 + v / 2; 5674 } 5675 5676 /** 5677 * t4_get_chan_txrate - get the current per channel Tx rates 5678 * @adap: the adapter 5679 * @nic_rate: rates for NIC traffic 5680 * @ofld_rate: rates for offloaded traffic 5681 * 5682 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 5683 * for each channel. 5684 */ 5685 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 5686 { 5687 u32 v; 5688 5689 v = t4_read_reg(adap, A_TP_TX_TRATE); 5690 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 5691 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 5692 if (adap->chip_params->nchan > 2) { 5693 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 5694 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 5695 } 5696 5697 v = t4_read_reg(adap, A_TP_TX_ORATE); 5698 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 5699 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 5700 if (adap->chip_params->nchan > 2) { 5701 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 5702 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 5703 } 5704 } 5705 5706 /** 5707 * t4_set_trace_filter - configure one of the tracing filters 5708 * @adap: the adapter 5709 * @tp: the desired trace filter parameters 5710 * @idx: which filter to configure 5711 * @enable: whether to enable or disable the filter 5712 * 5713 * Configures one of the tracing filters available in HW. If @tp is %NULL 5714 * it indicates that the filter is already written in the register and it 5715 * just needs to be enabled or disabled. 5716 */ 5717 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 5718 int idx, int enable) 5719 { 5720 int i, ofst = idx * 4; 5721 u32 data_reg, mask_reg, cfg; 5722 u32 multitrc = F_TRCMULTIFILTER; 5723 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 5724 5725 if (idx < 0 || idx >= NTRACE) 5726 return -EINVAL; 5727 5728 if (tp == NULL || !enable) { 5729 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 5730 enable ? en : 0); 5731 return 0; 5732 } 5733 5734 /* 5735 * TODO - After T4 data book is updated, specify the exact 5736 * section below. 5737 * 5738 * See T4 data book - MPS section for a complete description 5739 * of the below if..else handling of A_MPS_TRC_CFG register 5740 * value. 5741 */ 5742 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 5743 if (cfg & F_TRCMULTIFILTER) { 5744 /* 5745 * If multiple tracers are enabled, then maximum 5746 * capture size is 2.5KB (FIFO size of a single channel) 5747 * minus 2 flits for CPL_TRACE_PKT header. 5748 */ 5749 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 5750 return -EINVAL; 5751 } else { 5752 /* 5753 * If multiple tracers are disabled, to avoid deadlocks 5754 * maximum packet capture size of 9600 bytes is recommended. 5755 * Also in this mode, only trace0 can be enabled and running. 5756 */ 5757 multitrc = 0; 5758 if (tp->snap_len > 9600 || idx) 5759 return -EINVAL; 5760 } 5761 5762 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 5763 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 5764 tp->min_len > M_TFMINPKTSIZE) 5765 return -EINVAL; 5766 5767 /* stop the tracer we'll be changing */ 5768 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 5769 5770 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 5771 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 5772 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 5773 5774 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5775 t4_write_reg(adap, data_reg, tp->data[i]); 5776 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 5777 } 5778 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 5779 V_TFCAPTUREMAX(tp->snap_len) | 5780 V_TFMINPKTSIZE(tp->min_len)); 5781 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 5782 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 5783 (is_t4(adap) ? 5784 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 5785 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 5786 5787 return 0; 5788 } 5789 5790 /** 5791 * t4_get_trace_filter - query one of the tracing filters 5792 * @adap: the adapter 5793 * @tp: the current trace filter parameters 5794 * @idx: which trace filter to query 5795 * @enabled: non-zero if the filter is enabled 5796 * 5797 * Returns the current settings of one of the HW tracing filters. 5798 */ 5799 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 5800 int *enabled) 5801 { 5802 u32 ctla, ctlb; 5803 int i, ofst = idx * 4; 5804 u32 data_reg, mask_reg; 5805 5806 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 5807 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 5808 5809 if (is_t4(adap)) { 5810 *enabled = !!(ctla & F_TFEN); 5811 tp->port = G_TFPORT(ctla); 5812 tp->invert = !!(ctla & F_TFINVERTMATCH); 5813 } else { 5814 *enabled = !!(ctla & F_T5_TFEN); 5815 tp->port = G_T5_TFPORT(ctla); 5816 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 5817 } 5818 tp->snap_len = G_TFCAPTUREMAX(ctlb); 5819 tp->min_len = G_TFMINPKTSIZE(ctlb); 5820 tp->skip_ofst = G_TFOFFSET(ctla); 5821 tp->skip_len = G_TFLENGTH(ctla); 5822 5823 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 5824 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 5825 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 5826 5827 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5828 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 5829 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 5830 } 5831 } 5832 5833 /** 5834 * t4_pmtx_get_stats - returns the HW stats from PMTX 5835 * @adap: the adapter 5836 * @cnt: where to store the count statistics 5837 * @cycles: where to store the cycle statistics 5838 * 5839 * Returns performance statistics from PMTX. 5840 */ 5841 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 5842 { 5843 int i; 5844 u32 data[2]; 5845 5846 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 5847 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 5848 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 5849 if (is_t4(adap)) 5850 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 5851 else { 5852 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 5853 A_PM_TX_DBG_DATA, data, 2, 5854 A_PM_TX_DBG_STAT_MSB); 5855 cycles[i] = (((u64)data[0] << 32) | data[1]); 5856 } 5857 } 5858 } 5859 5860 /** 5861 * t4_pmrx_get_stats - returns the HW stats from PMRX 5862 * @adap: the adapter 5863 * @cnt: where to store the count statistics 5864 * @cycles: where to store the cycle statistics 5865 * 5866 * Returns performance statistics from PMRX. 5867 */ 5868 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 5869 { 5870 int i; 5871 u32 data[2]; 5872 5873 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 5874 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 5875 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 5876 if (is_t4(adap)) { 5877 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 5878 } else { 5879 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 5880 A_PM_RX_DBG_DATA, data, 2, 5881 A_PM_RX_DBG_STAT_MSB); 5882 cycles[i] = (((u64)data[0] << 32) | data[1]); 5883 } 5884 } 5885 } 5886 5887 /** 5888 * t4_get_mps_bg_map - return the buffer groups associated with a port 5889 * @adap: the adapter 5890 * @idx: the port index 5891 * 5892 * Returns a bitmap indicating which MPS buffer groups are associated 5893 * with the given port. Bit i is set if buffer group i is used by the 5894 * port. 5895 */ 5896 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 5897 { 5898 u32 n; 5899 5900 if (adap->params.mps_bg_map) 5901 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 5902 5903 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 5904 if (n == 0) 5905 return idx == 0 ? 0xf : 0; 5906 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 5907 return idx < 2 ? (3 << (2 * idx)) : 0; 5908 return 1 << idx; 5909 } 5910 5911 /* 5912 * TP RX e-channels associated with the port. 5913 */ 5914 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 5915 { 5916 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 5917 5918 if (n == 0) 5919 return idx == 0 ? 0xf : 0; 5920 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 5921 return idx < 2 ? (3 << (2 * idx)) : 0; 5922 return 1 << idx; 5923 } 5924 5925 /** 5926 * t4_get_port_type_description - return Port Type string description 5927 * @port_type: firmware Port Type enumeration 5928 */ 5929 const char *t4_get_port_type_description(enum fw_port_type port_type) 5930 { 5931 static const char *const port_type_description[] = { 5932 "Fiber_XFI", 5933 "Fiber_XAUI", 5934 "BT_SGMII", 5935 "BT_XFI", 5936 "BT_XAUI", 5937 "KX4", 5938 "CX4", 5939 "KX", 5940 "KR", 5941 "SFP", 5942 "BP_AP", 5943 "BP4_AP", 5944 "QSFP_10G", 5945 "QSA", 5946 "QSFP", 5947 "BP40_BA", 5948 "KR4_100G", 5949 "CR4_QSFP", 5950 "CR_QSFP", 5951 "CR2_QSFP", 5952 "SFP28", 5953 "KR_SFP28", 5954 }; 5955 5956 if (port_type < ARRAY_SIZE(port_type_description)) 5957 return port_type_description[port_type]; 5958 return "UNKNOWN"; 5959 } 5960 5961 /** 5962 * t4_get_port_stats_offset - collect port stats relative to a previous 5963 * snapshot 5964 * @adap: The adapter 5965 * @idx: The port 5966 * @stats: Current stats to fill 5967 * @offset: Previous stats snapshot 5968 */ 5969 void t4_get_port_stats_offset(struct adapter *adap, int idx, 5970 struct port_stats *stats, 5971 struct port_stats *offset) 5972 { 5973 u64 *s, *o; 5974 int i; 5975 5976 t4_get_port_stats(adap, idx, stats); 5977 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 5978 i < (sizeof(struct port_stats)/sizeof(u64)) ; 5979 i++, s++, o++) 5980 *s -= *o; 5981 } 5982 5983 /** 5984 * t4_get_port_stats - collect port statistics 5985 * @adap: the adapter 5986 * @idx: the port index 5987 * @p: the stats structure to fill 5988 * 5989 * Collect statistics related to the given port from HW. 5990 */ 5991 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 5992 { 5993 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 5994 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 5995 5996 #define GET_STAT(name) \ 5997 t4_read_reg64(adap, \ 5998 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 5999 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6000 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6001 6002 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6003 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6004 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6005 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6006 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6007 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6008 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6009 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6010 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6011 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6012 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6013 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6014 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6015 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6016 p->tx_drop = GET_STAT(TX_PORT_DROP); 6017 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6018 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6019 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6020 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6021 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6022 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6023 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6024 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6025 6026 if (chip_id(adap) >= CHELSIO_T5) { 6027 if (stat_ctl & F_COUNTPAUSESTATTX) { 6028 p->tx_frames -= p->tx_pause; 6029 p->tx_octets -= p->tx_pause * 64; 6030 } 6031 if (stat_ctl & F_COUNTPAUSEMCTX) 6032 p->tx_mcast_frames -= p->tx_pause; 6033 } 6034 6035 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6036 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6037 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6038 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6039 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6040 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6041 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6042 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6043 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 6044 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6045 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6046 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6047 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6048 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6049 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6050 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6051 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6052 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6053 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6054 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6055 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6056 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6057 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6058 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6059 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6060 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6061 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6062 6063 if (chip_id(adap) >= CHELSIO_T5) { 6064 if (stat_ctl & F_COUNTPAUSESTATRX) { 6065 p->rx_frames -= p->rx_pause; 6066 p->rx_octets -= p->rx_pause * 64; 6067 } 6068 if (stat_ctl & F_COUNTPAUSEMCRX) 6069 p->rx_mcast_frames -= p->rx_pause; 6070 } 6071 6072 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6073 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6074 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6075 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6076 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6077 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6078 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6079 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6080 6081 #undef GET_STAT 6082 #undef GET_STAT_COM 6083 } 6084 6085 /** 6086 * t4_get_lb_stats - collect loopback port statistics 6087 * @adap: the adapter 6088 * @idx: the loopback port index 6089 * @p: the stats structure to fill 6090 * 6091 * Return HW statistics for the given loopback port. 6092 */ 6093 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 6094 { 6095 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6096 6097 #define GET_STAT(name) \ 6098 t4_read_reg64(adap, \ 6099 (is_t4(adap) ? \ 6100 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 6101 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 6102 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6103 6104 p->octets = GET_STAT(BYTES); 6105 p->frames = GET_STAT(FRAMES); 6106 p->bcast_frames = GET_STAT(BCAST); 6107 p->mcast_frames = GET_STAT(MCAST); 6108 p->ucast_frames = GET_STAT(UCAST); 6109 p->error_frames = GET_STAT(ERROR); 6110 6111 p->frames_64 = GET_STAT(64B); 6112 p->frames_65_127 = GET_STAT(65B_127B); 6113 p->frames_128_255 = GET_STAT(128B_255B); 6114 p->frames_256_511 = GET_STAT(256B_511B); 6115 p->frames_512_1023 = GET_STAT(512B_1023B); 6116 p->frames_1024_1518 = GET_STAT(1024B_1518B); 6117 p->frames_1519_max = GET_STAT(1519B_MAX); 6118 p->drop = GET_STAT(DROP_FRAMES); 6119 6120 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 6121 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 6122 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 6123 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 6124 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 6125 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 6126 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 6127 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 6128 6129 #undef GET_STAT 6130 #undef GET_STAT_COM 6131 } 6132 6133 /** 6134 * t4_wol_magic_enable - enable/disable magic packet WoL 6135 * @adap: the adapter 6136 * @port: the physical port index 6137 * @addr: MAC address expected in magic packets, %NULL to disable 6138 * 6139 * Enables/disables magic packet wake-on-LAN for the selected port. 6140 */ 6141 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 6142 const u8 *addr) 6143 { 6144 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 6145 6146 if (is_t4(adap)) { 6147 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 6148 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 6149 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6150 } else { 6151 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 6152 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 6153 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6154 } 6155 6156 if (addr) { 6157 t4_write_reg(adap, mag_id_reg_l, 6158 (addr[2] << 24) | (addr[3] << 16) | 6159 (addr[4] << 8) | addr[5]); 6160 t4_write_reg(adap, mag_id_reg_h, 6161 (addr[0] << 8) | addr[1]); 6162 } 6163 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 6164 V_MAGICEN(addr != NULL)); 6165 } 6166 6167 /** 6168 * t4_wol_pat_enable - enable/disable pattern-based WoL 6169 * @adap: the adapter 6170 * @port: the physical port index 6171 * @map: bitmap of which HW pattern filters to set 6172 * @mask0: byte mask for bytes 0-63 of a packet 6173 * @mask1: byte mask for bytes 64-127 of a packet 6174 * @crc: Ethernet CRC for selected bytes 6175 * @enable: enable/disable switch 6176 * 6177 * Sets the pattern filters indicated in @map to mask out the bytes 6178 * specified in @mask0/@mask1 in received packets and compare the CRC of 6179 * the resulting packet against @crc. If @enable is %true pattern-based 6180 * WoL is enabled, otherwise disabled. 6181 */ 6182 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 6183 u64 mask0, u64 mask1, unsigned int crc, bool enable) 6184 { 6185 int i; 6186 u32 port_cfg_reg; 6187 6188 if (is_t4(adap)) 6189 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6190 else 6191 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6192 6193 if (!enable) { 6194 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 6195 return 0; 6196 } 6197 if (map > 0xff) 6198 return -EINVAL; 6199 6200 #define EPIO_REG(name) \ 6201 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 6202 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 6203 6204 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 6205 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 6206 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 6207 6208 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 6209 if (!(map & 1)) 6210 continue; 6211 6212 /* write byte masks */ 6213 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 6214 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 6215 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6216 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6217 return -ETIMEDOUT; 6218 6219 /* write CRC */ 6220 t4_write_reg(adap, EPIO_REG(DATA0), crc); 6221 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 6222 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6223 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6224 return -ETIMEDOUT; 6225 } 6226 #undef EPIO_REG 6227 6228 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 6229 return 0; 6230 } 6231 6232 /* t4_mk_filtdelwr - create a delete filter WR 6233 * @ftid: the filter ID 6234 * @wr: the filter work request to populate 6235 * @qid: ingress queue to receive the delete notification 6236 * 6237 * Creates a filter work request to delete the supplied filter. If @qid is 6238 * negative the delete notification is suppressed. 6239 */ 6240 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 6241 { 6242 memset(wr, 0, sizeof(*wr)); 6243 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 6244 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 6245 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 6246 V_FW_FILTER_WR_NOREPLY(qid < 0)); 6247 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 6248 if (qid >= 0) 6249 wr->rx_chan_rx_rpl_iq = 6250 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 6251 } 6252 6253 #define INIT_CMD(var, cmd, rd_wr) do { \ 6254 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 6255 F_FW_CMD_REQUEST | \ 6256 F_FW_CMD_##rd_wr); \ 6257 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 6258 } while (0) 6259 6260 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 6261 u32 addr, u32 val) 6262 { 6263 u32 ldst_addrspace; 6264 struct fw_ldst_cmd c; 6265 6266 memset(&c, 0, sizeof(c)); 6267 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 6268 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6269 F_FW_CMD_REQUEST | 6270 F_FW_CMD_WRITE | 6271 ldst_addrspace); 6272 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6273 c.u.addrval.addr = cpu_to_be32(addr); 6274 c.u.addrval.val = cpu_to_be32(val); 6275 6276 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6277 } 6278 6279 /** 6280 * t4_mdio_rd - read a PHY register through MDIO 6281 * @adap: the adapter 6282 * @mbox: mailbox to use for the FW command 6283 * @phy_addr: the PHY address 6284 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6285 * @reg: the register to read 6286 * @valp: where to store the value 6287 * 6288 * Issues a FW command through the given mailbox to read a PHY register. 6289 */ 6290 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6291 unsigned int mmd, unsigned int reg, unsigned int *valp) 6292 { 6293 int ret; 6294 u32 ldst_addrspace; 6295 struct fw_ldst_cmd c; 6296 6297 memset(&c, 0, sizeof(c)); 6298 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6299 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6300 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6301 ldst_addrspace); 6302 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6303 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6304 V_FW_LDST_CMD_MMD(mmd)); 6305 c.u.mdio.raddr = cpu_to_be16(reg); 6306 6307 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6308 if (ret == 0) 6309 *valp = be16_to_cpu(c.u.mdio.rval); 6310 return ret; 6311 } 6312 6313 /** 6314 * t4_mdio_wr - write a PHY register through MDIO 6315 * @adap: the adapter 6316 * @mbox: mailbox to use for the FW command 6317 * @phy_addr: the PHY address 6318 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6319 * @reg: the register to write 6320 * @valp: value to write 6321 * 6322 * Issues a FW command through the given mailbox to write a PHY register. 6323 */ 6324 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6325 unsigned int mmd, unsigned int reg, unsigned int val) 6326 { 6327 u32 ldst_addrspace; 6328 struct fw_ldst_cmd c; 6329 6330 memset(&c, 0, sizeof(c)); 6331 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6332 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6333 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 6334 ldst_addrspace); 6335 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6336 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6337 V_FW_LDST_CMD_MMD(mmd)); 6338 c.u.mdio.raddr = cpu_to_be16(reg); 6339 c.u.mdio.rval = cpu_to_be16(val); 6340 6341 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6342 } 6343 6344 /** 6345 * 6346 * t4_sge_decode_idma_state - decode the idma state 6347 * @adap: the adapter 6348 * @state: the state idma is stuck in 6349 */ 6350 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 6351 { 6352 static const char * const t4_decode[] = { 6353 "IDMA_IDLE", 6354 "IDMA_PUSH_MORE_CPL_FIFO", 6355 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6356 "Not used", 6357 "IDMA_PHYSADDR_SEND_PCIEHDR", 6358 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6359 "IDMA_PHYSADDR_SEND_PAYLOAD", 6360 "IDMA_SEND_FIFO_TO_IMSG", 6361 "IDMA_FL_REQ_DATA_FL_PREP", 6362 "IDMA_FL_REQ_DATA_FL", 6363 "IDMA_FL_DROP", 6364 "IDMA_FL_H_REQ_HEADER_FL", 6365 "IDMA_FL_H_SEND_PCIEHDR", 6366 "IDMA_FL_H_PUSH_CPL_FIFO", 6367 "IDMA_FL_H_SEND_CPL", 6368 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6369 "IDMA_FL_H_SEND_IP_HDR", 6370 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6371 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6372 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6373 "IDMA_FL_D_SEND_PCIEHDR", 6374 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6375 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6376 "IDMA_FL_SEND_PCIEHDR", 6377 "IDMA_FL_PUSH_CPL_FIFO", 6378 "IDMA_FL_SEND_CPL", 6379 "IDMA_FL_SEND_PAYLOAD_FIRST", 6380 "IDMA_FL_SEND_PAYLOAD", 6381 "IDMA_FL_REQ_NEXT_DATA_FL", 6382 "IDMA_FL_SEND_NEXT_PCIEHDR", 6383 "IDMA_FL_SEND_PADDING", 6384 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6385 "IDMA_FL_SEND_FIFO_TO_IMSG", 6386 "IDMA_FL_REQ_DATAFL_DONE", 6387 "IDMA_FL_REQ_HEADERFL_DONE", 6388 }; 6389 static const char * const t5_decode[] = { 6390 "IDMA_IDLE", 6391 "IDMA_ALMOST_IDLE", 6392 "IDMA_PUSH_MORE_CPL_FIFO", 6393 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6394 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6395 "IDMA_PHYSADDR_SEND_PCIEHDR", 6396 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6397 "IDMA_PHYSADDR_SEND_PAYLOAD", 6398 "IDMA_SEND_FIFO_TO_IMSG", 6399 "IDMA_FL_REQ_DATA_FL", 6400 "IDMA_FL_DROP", 6401 "IDMA_FL_DROP_SEND_INC", 6402 "IDMA_FL_H_REQ_HEADER_FL", 6403 "IDMA_FL_H_SEND_PCIEHDR", 6404 "IDMA_FL_H_PUSH_CPL_FIFO", 6405 "IDMA_FL_H_SEND_CPL", 6406 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6407 "IDMA_FL_H_SEND_IP_HDR", 6408 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6409 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6410 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6411 "IDMA_FL_D_SEND_PCIEHDR", 6412 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6413 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6414 "IDMA_FL_SEND_PCIEHDR", 6415 "IDMA_FL_PUSH_CPL_FIFO", 6416 "IDMA_FL_SEND_CPL", 6417 "IDMA_FL_SEND_PAYLOAD_FIRST", 6418 "IDMA_FL_SEND_PAYLOAD", 6419 "IDMA_FL_REQ_NEXT_DATA_FL", 6420 "IDMA_FL_SEND_NEXT_PCIEHDR", 6421 "IDMA_FL_SEND_PADDING", 6422 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6423 }; 6424 static const char * const t6_decode[] = { 6425 "IDMA_IDLE", 6426 "IDMA_PUSH_MORE_CPL_FIFO", 6427 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6428 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6429 "IDMA_PHYSADDR_SEND_PCIEHDR", 6430 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6431 "IDMA_PHYSADDR_SEND_PAYLOAD", 6432 "IDMA_FL_REQ_DATA_FL", 6433 "IDMA_FL_DROP", 6434 "IDMA_FL_DROP_SEND_INC", 6435 "IDMA_FL_H_REQ_HEADER_FL", 6436 "IDMA_FL_H_SEND_PCIEHDR", 6437 "IDMA_FL_H_PUSH_CPL_FIFO", 6438 "IDMA_FL_H_SEND_CPL", 6439 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6440 "IDMA_FL_H_SEND_IP_HDR", 6441 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6442 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6443 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6444 "IDMA_FL_D_SEND_PCIEHDR", 6445 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6446 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6447 "IDMA_FL_SEND_PCIEHDR", 6448 "IDMA_FL_PUSH_CPL_FIFO", 6449 "IDMA_FL_SEND_CPL", 6450 "IDMA_FL_SEND_PAYLOAD_FIRST", 6451 "IDMA_FL_SEND_PAYLOAD", 6452 "IDMA_FL_REQ_NEXT_DATA_FL", 6453 "IDMA_FL_SEND_NEXT_PCIEHDR", 6454 "IDMA_FL_SEND_PADDING", 6455 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6456 }; 6457 static const u32 sge_regs[] = { 6458 A_SGE_DEBUG_DATA_LOW_INDEX_2, 6459 A_SGE_DEBUG_DATA_LOW_INDEX_3, 6460 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 6461 }; 6462 const char * const *sge_idma_decode; 6463 int sge_idma_decode_nstates; 6464 int i; 6465 unsigned int chip_version = chip_id(adapter); 6466 6467 /* Select the right set of decode strings to dump depending on the 6468 * adapter chip type. 6469 */ 6470 switch (chip_version) { 6471 case CHELSIO_T4: 6472 sge_idma_decode = (const char * const *)t4_decode; 6473 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 6474 break; 6475 6476 case CHELSIO_T5: 6477 sge_idma_decode = (const char * const *)t5_decode; 6478 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 6479 break; 6480 6481 case CHELSIO_T6: 6482 sge_idma_decode = (const char * const *)t6_decode; 6483 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 6484 break; 6485 6486 default: 6487 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 6488 return; 6489 } 6490 6491 if (state < sge_idma_decode_nstates) 6492 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 6493 else 6494 CH_WARN(adapter, "idma state %d unknown\n", state); 6495 6496 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 6497 CH_WARN(adapter, "SGE register %#x value %#x\n", 6498 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 6499 } 6500 6501 /** 6502 * t4_sge_ctxt_flush - flush the SGE context cache 6503 * @adap: the adapter 6504 * @mbox: mailbox to use for the FW command 6505 * 6506 * Issues a FW command through the given mailbox to flush the 6507 * SGE context cache. 6508 */ 6509 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 6510 { 6511 int ret; 6512 u32 ldst_addrspace; 6513 struct fw_ldst_cmd c; 6514 6515 memset(&c, 0, sizeof(c)); 6516 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC); 6517 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6518 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6519 ldst_addrspace); 6520 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6521 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 6522 6523 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6524 return ret; 6525 } 6526 6527 /** 6528 * t4_fw_hello - establish communication with FW 6529 * @adap: the adapter 6530 * @mbox: mailbox to use for the FW command 6531 * @evt_mbox: mailbox to receive async FW events 6532 * @master: specifies the caller's willingness to be the device master 6533 * @state: returns the current device state (if non-NULL) 6534 * 6535 * Issues a command to establish communication with FW. Returns either 6536 * an error (negative integer) or the mailbox of the Master PF. 6537 */ 6538 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 6539 enum dev_master master, enum dev_state *state) 6540 { 6541 int ret; 6542 struct fw_hello_cmd c; 6543 u32 v; 6544 unsigned int master_mbox; 6545 int retries = FW_CMD_HELLO_RETRIES; 6546 6547 retry: 6548 memset(&c, 0, sizeof(c)); 6549 INIT_CMD(c, HELLO, WRITE); 6550 c.err_to_clearinit = cpu_to_be32( 6551 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 6552 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 6553 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 6554 mbox : M_FW_HELLO_CMD_MBMASTER) | 6555 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 6556 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 6557 F_FW_HELLO_CMD_CLEARINIT); 6558 6559 /* 6560 * Issue the HELLO command to the firmware. If it's not successful 6561 * but indicates that we got a "busy" or "timeout" condition, retry 6562 * the HELLO until we exhaust our retry limit. If we do exceed our 6563 * retry limit, check to see if the firmware left us any error 6564 * information and report that if so ... 6565 */ 6566 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6567 if (ret != FW_SUCCESS) { 6568 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 6569 goto retry; 6570 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 6571 t4_report_fw_error(adap); 6572 return ret; 6573 } 6574 6575 v = be32_to_cpu(c.err_to_clearinit); 6576 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 6577 if (state) { 6578 if (v & F_FW_HELLO_CMD_ERR) 6579 *state = DEV_STATE_ERR; 6580 else if (v & F_FW_HELLO_CMD_INIT) 6581 *state = DEV_STATE_INIT; 6582 else 6583 *state = DEV_STATE_UNINIT; 6584 } 6585 6586 /* 6587 * If we're not the Master PF then we need to wait around for the 6588 * Master PF Driver to finish setting up the adapter. 6589 * 6590 * Note that we also do this wait if we're a non-Master-capable PF and 6591 * there is no current Master PF; a Master PF may show up momentarily 6592 * and we wouldn't want to fail pointlessly. (This can happen when an 6593 * OS loads lots of different drivers rapidly at the same time). In 6594 * this case, the Master PF returned by the firmware will be 6595 * M_PCIE_FW_MASTER so the test below will work ... 6596 */ 6597 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 6598 master_mbox != mbox) { 6599 int waiting = FW_CMD_HELLO_TIMEOUT; 6600 6601 /* 6602 * Wait for the firmware to either indicate an error or 6603 * initialized state. If we see either of these we bail out 6604 * and report the issue to the caller. If we exhaust the 6605 * "hello timeout" and we haven't exhausted our retries, try 6606 * again. Otherwise bail with a timeout error. 6607 */ 6608 for (;;) { 6609 u32 pcie_fw; 6610 6611 msleep(50); 6612 waiting -= 50; 6613 6614 /* 6615 * If neither Error nor Initialialized are indicated 6616 * by the firmware keep waiting till we exhaust our 6617 * timeout ... and then retry if we haven't exhausted 6618 * our retries ... 6619 */ 6620 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 6621 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 6622 if (waiting <= 0) { 6623 if (retries-- > 0) 6624 goto retry; 6625 6626 return -ETIMEDOUT; 6627 } 6628 continue; 6629 } 6630 6631 /* 6632 * We either have an Error or Initialized condition 6633 * report errors preferentially. 6634 */ 6635 if (state) { 6636 if (pcie_fw & F_PCIE_FW_ERR) 6637 *state = DEV_STATE_ERR; 6638 else if (pcie_fw & F_PCIE_FW_INIT) 6639 *state = DEV_STATE_INIT; 6640 } 6641 6642 /* 6643 * If we arrived before a Master PF was selected and 6644 * there's not a valid Master PF, grab its identity 6645 * for our caller. 6646 */ 6647 if (master_mbox == M_PCIE_FW_MASTER && 6648 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 6649 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 6650 break; 6651 } 6652 } 6653 6654 return master_mbox; 6655 } 6656 6657 /** 6658 * t4_fw_bye - end communication with FW 6659 * @adap: the adapter 6660 * @mbox: mailbox to use for the FW command 6661 * 6662 * Issues a command to terminate communication with FW. 6663 */ 6664 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 6665 { 6666 struct fw_bye_cmd c; 6667 6668 memset(&c, 0, sizeof(c)); 6669 INIT_CMD(c, BYE, WRITE); 6670 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6671 } 6672 6673 /** 6674 * t4_fw_reset - issue a reset to FW 6675 * @adap: the adapter 6676 * @mbox: mailbox to use for the FW command 6677 * @reset: specifies the type of reset to perform 6678 * 6679 * Issues a reset command of the specified type to FW. 6680 */ 6681 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 6682 { 6683 struct fw_reset_cmd c; 6684 6685 memset(&c, 0, sizeof(c)); 6686 INIT_CMD(c, RESET, WRITE); 6687 c.val = cpu_to_be32(reset); 6688 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6689 } 6690 6691 /** 6692 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 6693 * @adap: the adapter 6694 * @mbox: mailbox to use for the FW RESET command (if desired) 6695 * @force: force uP into RESET even if FW RESET command fails 6696 * 6697 * Issues a RESET command to firmware (if desired) with a HALT indication 6698 * and then puts the microprocessor into RESET state. The RESET command 6699 * will only be issued if a legitimate mailbox is provided (mbox <= 6700 * M_PCIE_FW_MASTER). 6701 * 6702 * This is generally used in order for the host to safely manipulate the 6703 * adapter without fear of conflicting with whatever the firmware might 6704 * be doing. The only way out of this state is to RESTART the firmware 6705 * ... 6706 */ 6707 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 6708 { 6709 int ret = 0; 6710 6711 /* 6712 * If a legitimate mailbox is provided, issue a RESET command 6713 * with a HALT indication. 6714 */ 6715 if (mbox <= M_PCIE_FW_MASTER) { 6716 struct fw_reset_cmd c; 6717 6718 memset(&c, 0, sizeof(c)); 6719 INIT_CMD(c, RESET, WRITE); 6720 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 6721 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 6722 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6723 } 6724 6725 /* 6726 * Normally we won't complete the operation if the firmware RESET 6727 * command fails but if our caller insists we'll go ahead and put the 6728 * uP into RESET. This can be useful if the firmware is hung or even 6729 * missing ... We'll have to take the risk of putting the uP into 6730 * RESET without the cooperation of firmware in that case. 6731 * 6732 * We also force the firmware's HALT flag to be on in case we bypassed 6733 * the firmware RESET command above or we're dealing with old firmware 6734 * which doesn't have the HALT capability. This will serve as a flag 6735 * for the incoming firmware to know that it's coming out of a HALT 6736 * rather than a RESET ... if it's new enough to understand that ... 6737 */ 6738 if (ret == 0 || force) { 6739 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 6740 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 6741 F_PCIE_FW_HALT); 6742 } 6743 6744 /* 6745 * And we always return the result of the firmware RESET command 6746 * even when we force the uP into RESET ... 6747 */ 6748 return ret; 6749 } 6750 6751 /** 6752 * t4_fw_restart - restart the firmware by taking the uP out of RESET 6753 * @adap: the adapter 6754 * @reset: if we want to do a RESET to restart things 6755 * 6756 * Restart firmware previously halted by t4_fw_halt(). On successful 6757 * return the previous PF Master remains as the new PF Master and there 6758 * is no need to issue a new HELLO command, etc. 6759 * 6760 * We do this in two ways: 6761 * 6762 * 1. If we're dealing with newer firmware we'll simply want to take 6763 * the chip's microprocessor out of RESET. This will cause the 6764 * firmware to start up from its start vector. And then we'll loop 6765 * until the firmware indicates it's started again (PCIE_FW.HALT 6766 * reset to 0) or we timeout. 6767 * 6768 * 2. If we're dealing with older firmware then we'll need to RESET 6769 * the chip since older firmware won't recognize the PCIE_FW.HALT 6770 * flag and automatically RESET itself on startup. 6771 */ 6772 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) 6773 { 6774 if (reset) { 6775 /* 6776 * Since we're directing the RESET instead of the firmware 6777 * doing it automatically, we need to clear the PCIE_FW.HALT 6778 * bit. 6779 */ 6780 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 0); 6781 6782 /* 6783 * If we've been given a valid mailbox, first try to get the 6784 * firmware to do the RESET. If that works, great and we can 6785 * return success. Otherwise, if we haven't been given a 6786 * valid mailbox or the RESET command failed, fall back to 6787 * hitting the chip with a hammer. 6788 */ 6789 if (mbox <= M_PCIE_FW_MASTER) { 6790 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6791 msleep(100); 6792 if (t4_fw_reset(adap, mbox, 6793 F_PIORST | F_PIORSTMODE) == 0) 6794 return 0; 6795 } 6796 6797 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 6798 msleep(2000); 6799 } else { 6800 int ms; 6801 6802 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6803 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 6804 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 6805 return FW_SUCCESS; 6806 msleep(100); 6807 ms += 100; 6808 } 6809 return -ETIMEDOUT; 6810 } 6811 return 0; 6812 } 6813 6814 /** 6815 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 6816 * @adap: the adapter 6817 * @mbox: mailbox to use for the FW RESET command (if desired) 6818 * @fw_data: the firmware image to write 6819 * @size: image size 6820 * @force: force upgrade even if firmware doesn't cooperate 6821 * 6822 * Perform all of the steps necessary for upgrading an adapter's 6823 * firmware image. Normally this requires the cooperation of the 6824 * existing firmware in order to halt all existing activities 6825 * but if an invalid mailbox token is passed in we skip that step 6826 * (though we'll still put the adapter microprocessor into RESET in 6827 * that case). 6828 * 6829 * On successful return the new firmware will have been loaded and 6830 * the adapter will have been fully RESET losing all previous setup 6831 * state. On unsuccessful return the adapter may be completely hosed ... 6832 * positive errno indicates that the adapter is ~probably~ intact, a 6833 * negative errno indicates that things are looking bad ... 6834 */ 6835 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 6836 const u8 *fw_data, unsigned int size, int force) 6837 { 6838 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 6839 unsigned int bootstrap = 6840 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 6841 int reset, ret; 6842 6843 if (!t4_fw_matches_chip(adap, fw_hdr)) 6844 return -EINVAL; 6845 6846 if (!bootstrap) { 6847 ret = t4_fw_halt(adap, mbox, force); 6848 if (ret < 0 && !force) 6849 return ret; 6850 } 6851 6852 ret = t4_load_fw(adap, fw_data, size); 6853 if (ret < 0 || bootstrap) 6854 return ret; 6855 6856 /* 6857 * Older versions of the firmware don't understand the new 6858 * PCIE_FW.HALT flag and so won't know to perform a RESET when they 6859 * restart. So for newly loaded older firmware we'll have to do the 6860 * RESET for it so it starts up on a clean slate. We can tell if 6861 * the newly loaded firmware will handle this right by checking 6862 * its header flags to see if it advertises the capability. 6863 */ 6864 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0); 6865 return t4_fw_restart(adap, mbox, reset); 6866 } 6867 6868 /* 6869 * Card doesn't have a firmware, install one. 6870 */ 6871 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data, 6872 unsigned int size) 6873 { 6874 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 6875 unsigned int bootstrap = 6876 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 6877 int ret; 6878 6879 if (!t4_fw_matches_chip(adap, fw_hdr) || bootstrap) 6880 return -EINVAL; 6881 6882 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 6883 t4_write_reg(adap, A_PCIE_FW, 0); /* Clobber internal state */ 6884 ret = t4_load_fw(adap, fw_data, size); 6885 if (ret < 0) 6886 return ret; 6887 t4_write_reg(adap, A_PL_RST, F_PIORST | F_PIORSTMODE); 6888 msleep(1000); 6889 6890 return (0); 6891 } 6892 6893 /** 6894 * t4_fw_initialize - ask FW to initialize the device 6895 * @adap: the adapter 6896 * @mbox: mailbox to use for the FW command 6897 * 6898 * Issues a command to FW to partially initialize the device. This 6899 * performs initialization that generally doesn't depend on user input. 6900 */ 6901 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 6902 { 6903 struct fw_initialize_cmd c; 6904 6905 memset(&c, 0, sizeof(c)); 6906 INIT_CMD(c, INITIALIZE, WRITE); 6907 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6908 } 6909 6910 /** 6911 * t4_query_params_rw - query FW or device parameters 6912 * @adap: the adapter 6913 * @mbox: mailbox to use for the FW command 6914 * @pf: the PF 6915 * @vf: the VF 6916 * @nparams: the number of parameters 6917 * @params: the parameter names 6918 * @val: the parameter values 6919 * @rw: Write and read flag 6920 * 6921 * Reads the value of FW or device parameters. Up to 7 parameters can be 6922 * queried at once. 6923 */ 6924 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 6925 unsigned int vf, unsigned int nparams, const u32 *params, 6926 u32 *val, int rw) 6927 { 6928 int i, ret; 6929 struct fw_params_cmd c; 6930 __be32 *p = &c.param[0].mnem; 6931 6932 if (nparams > 7) 6933 return -EINVAL; 6934 6935 memset(&c, 0, sizeof(c)); 6936 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 6937 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6938 V_FW_PARAMS_CMD_PFN(pf) | 6939 V_FW_PARAMS_CMD_VFN(vf)); 6940 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 6941 6942 for (i = 0; i < nparams; i++) { 6943 *p++ = cpu_to_be32(*params++); 6944 if (rw) 6945 *p = cpu_to_be32(*(val + i)); 6946 p++; 6947 } 6948 6949 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6950 if (ret == 0) 6951 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 6952 *val++ = be32_to_cpu(*p); 6953 return ret; 6954 } 6955 6956 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 6957 unsigned int vf, unsigned int nparams, const u32 *params, 6958 u32 *val) 6959 { 6960 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 6961 } 6962 6963 /** 6964 * t4_set_params_timeout - sets FW or device parameters 6965 * @adap: the adapter 6966 * @mbox: mailbox to use for the FW command 6967 * @pf: the PF 6968 * @vf: the VF 6969 * @nparams: the number of parameters 6970 * @params: the parameter names 6971 * @val: the parameter values 6972 * @timeout: the timeout time 6973 * 6974 * Sets the value of FW or device parameters. Up to 7 parameters can be 6975 * specified at once. 6976 */ 6977 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 6978 unsigned int pf, unsigned int vf, 6979 unsigned int nparams, const u32 *params, 6980 const u32 *val, int timeout) 6981 { 6982 struct fw_params_cmd c; 6983 __be32 *p = &c.param[0].mnem; 6984 6985 if (nparams > 7) 6986 return -EINVAL; 6987 6988 memset(&c, 0, sizeof(c)); 6989 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 6990 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 6991 V_FW_PARAMS_CMD_PFN(pf) | 6992 V_FW_PARAMS_CMD_VFN(vf)); 6993 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 6994 6995 while (nparams--) { 6996 *p++ = cpu_to_be32(*params++); 6997 *p++ = cpu_to_be32(*val++); 6998 } 6999 7000 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7001 } 7002 7003 /** 7004 * t4_set_params - sets FW or device parameters 7005 * @adap: the adapter 7006 * @mbox: mailbox to use for the FW command 7007 * @pf: the PF 7008 * @vf: the VF 7009 * @nparams: the number of parameters 7010 * @params: the parameter names 7011 * @val: the parameter values 7012 * 7013 * Sets the value of FW or device parameters. Up to 7 parameters can be 7014 * specified at once. 7015 */ 7016 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7017 unsigned int vf, unsigned int nparams, const u32 *params, 7018 const u32 *val) 7019 { 7020 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7021 FW_CMD_MAX_TIMEOUT); 7022 } 7023 7024 /** 7025 * t4_cfg_pfvf - configure PF/VF resource limits 7026 * @adap: the adapter 7027 * @mbox: mailbox to use for the FW command 7028 * @pf: the PF being configured 7029 * @vf: the VF being configured 7030 * @txq: the max number of egress queues 7031 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7032 * @rxqi: the max number of interrupt-capable ingress queues 7033 * @rxq: the max number of interruptless ingress queues 7034 * @tc: the PCI traffic class 7035 * @vi: the max number of virtual interfaces 7036 * @cmask: the channel access rights mask for the PF/VF 7037 * @pmask: the port access rights mask for the PF/VF 7038 * @nexact: the maximum number of exact MPS filters 7039 * @rcaps: read capabilities 7040 * @wxcaps: write/execute capabilities 7041 * 7042 * Configures resource limits and capabilities for a physical or virtual 7043 * function. 7044 */ 7045 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7046 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7047 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7048 unsigned int vi, unsigned int cmask, unsigned int pmask, 7049 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7050 { 7051 struct fw_pfvf_cmd c; 7052 7053 memset(&c, 0, sizeof(c)); 7054 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7055 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7056 V_FW_PFVF_CMD_VFN(vf)); 7057 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7058 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7059 V_FW_PFVF_CMD_NIQ(rxq)); 7060 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7061 V_FW_PFVF_CMD_PMASK(pmask) | 7062 V_FW_PFVF_CMD_NEQ(txq)); 7063 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7064 V_FW_PFVF_CMD_NVI(vi) | 7065 V_FW_PFVF_CMD_NEXACTF(nexact)); 7066 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7067 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7068 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7069 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7070 } 7071 7072 /** 7073 * t4_alloc_vi_func - allocate a virtual interface 7074 * @adap: the adapter 7075 * @mbox: mailbox to use for the FW command 7076 * @port: physical port associated with the VI 7077 * @pf: the PF owning the VI 7078 * @vf: the VF owning the VI 7079 * @nmac: number of MAC addresses needed (1 to 5) 7080 * @mac: the MAC addresses of the VI 7081 * @rss_size: size of RSS table slice associated with this VI 7082 * @portfunc: which Port Application Function MAC Address is desired 7083 * @idstype: Intrusion Detection Type 7084 * 7085 * Allocates a virtual interface for the given physical port. If @mac is 7086 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7087 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7088 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7089 * stored consecutively so the space needed is @nmac * 6 bytes. 7090 * Returns a negative error number or the non-negative VI id. 7091 */ 7092 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7093 unsigned int port, unsigned int pf, unsigned int vf, 7094 unsigned int nmac, u8 *mac, u16 *rss_size, 7095 unsigned int portfunc, unsigned int idstype) 7096 { 7097 int ret; 7098 struct fw_vi_cmd c; 7099 7100 memset(&c, 0, sizeof(c)); 7101 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7102 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7103 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7104 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7105 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7106 V_FW_VI_CMD_FUNC(portfunc)); 7107 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7108 c.nmac = nmac - 1; 7109 if(!rss_size) 7110 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7111 7112 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7113 if (ret) 7114 return ret; 7115 7116 if (mac) { 7117 memcpy(mac, c.mac, sizeof(c.mac)); 7118 switch (nmac) { 7119 case 5: 7120 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7121 case 4: 7122 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7123 case 3: 7124 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7125 case 2: 7126 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7127 } 7128 } 7129 if (rss_size) 7130 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7131 return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7132 } 7133 7134 /** 7135 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7136 * @adap: the adapter 7137 * @mbox: mailbox to use for the FW command 7138 * @port: physical port associated with the VI 7139 * @pf: the PF owning the VI 7140 * @vf: the VF owning the VI 7141 * @nmac: number of MAC addresses needed (1 to 5) 7142 * @mac: the MAC addresses of the VI 7143 * @rss_size: size of RSS table slice associated with this VI 7144 * 7145 * backwards compatible and convieniance routine to allocate a Virtual 7146 * Interface with a Ethernet Port Application Function and Intrustion 7147 * Detection System disabled. 7148 */ 7149 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 7150 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 7151 u16 *rss_size) 7152 { 7153 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 7154 FW_VI_FUNC_ETH, 0); 7155 } 7156 7157 /** 7158 * t4_free_vi - free a virtual interface 7159 * @adap: the adapter 7160 * @mbox: mailbox to use for the FW command 7161 * @pf: the PF owning the VI 7162 * @vf: the VF owning the VI 7163 * @viid: virtual interface identifiler 7164 * 7165 * Free a previously allocated virtual interface. 7166 */ 7167 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 7168 unsigned int vf, unsigned int viid) 7169 { 7170 struct fw_vi_cmd c; 7171 7172 memset(&c, 0, sizeof(c)); 7173 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 7174 F_FW_CMD_REQUEST | 7175 F_FW_CMD_EXEC | 7176 V_FW_VI_CMD_PFN(pf) | 7177 V_FW_VI_CMD_VFN(vf)); 7178 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 7179 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 7180 7181 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7182 } 7183 7184 /** 7185 * t4_set_rxmode - set Rx properties of a virtual interface 7186 * @adap: the adapter 7187 * @mbox: mailbox to use for the FW command 7188 * @viid: the VI id 7189 * @mtu: the new MTU or -1 7190 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 7191 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 7192 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 7193 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 7194 * @sleep_ok: if true we may sleep while awaiting command completion 7195 * 7196 * Sets Rx properties of a virtual interface. 7197 */ 7198 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 7199 int mtu, int promisc, int all_multi, int bcast, int vlanex, 7200 bool sleep_ok) 7201 { 7202 struct fw_vi_rxmode_cmd c; 7203 7204 /* convert to FW values */ 7205 if (mtu < 0) 7206 mtu = M_FW_VI_RXMODE_CMD_MTU; 7207 if (promisc < 0) 7208 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 7209 if (all_multi < 0) 7210 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 7211 if (bcast < 0) 7212 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 7213 if (vlanex < 0) 7214 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 7215 7216 memset(&c, 0, sizeof(c)); 7217 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 7218 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7219 V_FW_VI_RXMODE_CMD_VIID(viid)); 7220 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7221 c.mtu_to_vlanexen = 7222 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 7223 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 7224 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 7225 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 7226 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 7227 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7228 } 7229 7230 /** 7231 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 7232 * @adap: the adapter 7233 * @mbox: mailbox to use for the FW command 7234 * @viid: the VI id 7235 * @free: if true any existing filters for this VI id are first removed 7236 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 7237 * @addr: the MAC address(es) 7238 * @idx: where to store the index of each allocated filter 7239 * @hash: pointer to hash address filter bitmap 7240 * @sleep_ok: call is allowed to sleep 7241 * 7242 * Allocates an exact-match filter for each of the supplied addresses and 7243 * sets it to the corresponding address. If @idx is not %NULL it should 7244 * have at least @naddr entries, each of which will be set to the index of 7245 * the filter allocated for the corresponding MAC address. If a filter 7246 * could not be allocated for an address its index is set to 0xffff. 7247 * If @hash is not %NULL addresses that fail to allocate an exact filter 7248 * are hashed and update the hash filter bitmap pointed at by @hash. 7249 * 7250 * Returns a negative error number or the number of filters allocated. 7251 */ 7252 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 7253 unsigned int viid, bool free, unsigned int naddr, 7254 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 7255 { 7256 int offset, ret = 0; 7257 struct fw_vi_mac_cmd c; 7258 unsigned int nfilters = 0; 7259 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 7260 unsigned int rem = naddr; 7261 7262 if (naddr > max_naddr) 7263 return -EINVAL; 7264 7265 for (offset = 0; offset < naddr ; /**/) { 7266 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 7267 ? rem 7268 : ARRAY_SIZE(c.u.exact)); 7269 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 7270 u.exact[fw_naddr]), 16); 7271 struct fw_vi_mac_exact *p; 7272 int i; 7273 7274 memset(&c, 0, sizeof(c)); 7275 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7276 F_FW_CMD_REQUEST | 7277 F_FW_CMD_WRITE | 7278 V_FW_CMD_EXEC(free) | 7279 V_FW_VI_MAC_CMD_VIID(viid)); 7280 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 7281 V_FW_CMD_LEN16(len16)); 7282 7283 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7284 p->valid_to_idx = 7285 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7286 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 7287 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 7288 } 7289 7290 /* 7291 * It's okay if we run out of space in our MAC address arena. 7292 * Some of the addresses we submit may get stored so we need 7293 * to run through the reply to see what the results were ... 7294 */ 7295 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 7296 if (ret && ret != -FW_ENOMEM) 7297 break; 7298 7299 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7300 u16 index = G_FW_VI_MAC_CMD_IDX( 7301 be16_to_cpu(p->valid_to_idx)); 7302 7303 if (idx) 7304 idx[offset+i] = (index >= max_naddr 7305 ? 0xffff 7306 : index); 7307 if (index < max_naddr) 7308 nfilters++; 7309 else if (hash) 7310 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 7311 } 7312 7313 free = false; 7314 offset += fw_naddr; 7315 rem -= fw_naddr; 7316 } 7317 7318 if (ret == 0 || ret == -FW_ENOMEM) 7319 ret = nfilters; 7320 return ret; 7321 } 7322 7323 /** 7324 * t4_change_mac - modifies the exact-match filter for a MAC address 7325 * @adap: the adapter 7326 * @mbox: mailbox to use for the FW command 7327 * @viid: the VI id 7328 * @idx: index of existing filter for old value of MAC address, or -1 7329 * @addr: the new MAC address value 7330 * @persist: whether a new MAC allocation should be persistent 7331 * @add_smt: if true also add the address to the HW SMT 7332 * 7333 * Modifies an exact-match filter and sets it to the new MAC address if 7334 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 7335 * latter case the address is added persistently if @persist is %true. 7336 * 7337 * Note that in general it is not possible to modify the value of a given 7338 * filter so the generic way to modify an address filter is to free the one 7339 * being used by the old address value and allocate a new filter for the 7340 * new address value. 7341 * 7342 * Returns a negative error number or the index of the filter with the new 7343 * MAC value. Note that this index may differ from @idx. 7344 */ 7345 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 7346 int idx, const u8 *addr, bool persist, bool add_smt) 7347 { 7348 int ret, mode; 7349 struct fw_vi_mac_cmd c; 7350 struct fw_vi_mac_exact *p = c.u.exact; 7351 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 7352 7353 if (idx < 0) /* new allocation */ 7354 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 7355 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 7356 7357 memset(&c, 0, sizeof(c)); 7358 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7359 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7360 V_FW_VI_MAC_CMD_VIID(viid)); 7361 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 7362 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7363 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 7364 V_FW_VI_MAC_CMD_IDX(idx)); 7365 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 7366 7367 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7368 if (ret == 0) { 7369 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 7370 if (ret >= max_mac_addr) 7371 ret = -ENOMEM; 7372 } 7373 return ret; 7374 } 7375 7376 /** 7377 * t4_set_addr_hash - program the MAC inexact-match hash filter 7378 * @adap: the adapter 7379 * @mbox: mailbox to use for the FW command 7380 * @viid: the VI id 7381 * @ucast: whether the hash filter should also match unicast addresses 7382 * @vec: the value to be written to the hash filter 7383 * @sleep_ok: call is allowed to sleep 7384 * 7385 * Sets the 64-bit inexact-match hash filter for a virtual interface. 7386 */ 7387 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 7388 bool ucast, u64 vec, bool sleep_ok) 7389 { 7390 struct fw_vi_mac_cmd c; 7391 u32 val; 7392 7393 memset(&c, 0, sizeof(c)); 7394 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7395 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7396 V_FW_VI_ENABLE_CMD_VIID(viid)); 7397 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 7398 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 7399 c.freemacs_to_len16 = cpu_to_be32(val); 7400 c.u.hash.hashvec = cpu_to_be64(vec); 7401 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7402 } 7403 7404 /** 7405 * t4_enable_vi_params - enable/disable a virtual interface 7406 * @adap: the adapter 7407 * @mbox: mailbox to use for the FW command 7408 * @viid: the VI id 7409 * @rx_en: 1=enable Rx, 0=disable Rx 7410 * @tx_en: 1=enable Tx, 0=disable Tx 7411 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 7412 * 7413 * Enables/disables a virtual interface. Note that setting DCB Enable 7414 * only makes sense when enabling a Virtual Interface ... 7415 */ 7416 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 7417 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 7418 { 7419 struct fw_vi_enable_cmd c; 7420 7421 memset(&c, 0, sizeof(c)); 7422 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7423 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7424 V_FW_VI_ENABLE_CMD_VIID(viid)); 7425 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 7426 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 7427 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 7428 FW_LEN16(c)); 7429 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 7430 } 7431 7432 /** 7433 * t4_enable_vi - enable/disable a virtual interface 7434 * @adap: the adapter 7435 * @mbox: mailbox to use for the FW command 7436 * @viid: the VI id 7437 * @rx_en: 1=enable Rx, 0=disable Rx 7438 * @tx_en: 1=enable Tx, 0=disable Tx 7439 * 7440 * Enables/disables a virtual interface. Note that setting DCB Enable 7441 * only makes sense when enabling a Virtual Interface ... 7442 */ 7443 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 7444 bool rx_en, bool tx_en) 7445 { 7446 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 7447 } 7448 7449 /** 7450 * t4_identify_port - identify a VI's port by blinking its LED 7451 * @adap: the adapter 7452 * @mbox: mailbox to use for the FW command 7453 * @viid: the VI id 7454 * @nblinks: how many times to blink LED at 2.5 Hz 7455 * 7456 * Identifies a VI's port by blinking its LED. 7457 */ 7458 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 7459 unsigned int nblinks) 7460 { 7461 struct fw_vi_enable_cmd c; 7462 7463 memset(&c, 0, sizeof(c)); 7464 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7465 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7466 V_FW_VI_ENABLE_CMD_VIID(viid)); 7467 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 7468 c.blinkdur = cpu_to_be16(nblinks); 7469 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7470 } 7471 7472 /** 7473 * t4_iq_stop - stop an ingress queue and its FLs 7474 * @adap: the adapter 7475 * @mbox: mailbox to use for the FW command 7476 * @pf: the PF owning the queues 7477 * @vf: the VF owning the queues 7478 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7479 * @iqid: ingress queue id 7480 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7481 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7482 * 7483 * Stops an ingress queue and its associated FLs, if any. This causes 7484 * any current or future data/messages destined for these queues to be 7485 * tossed. 7486 */ 7487 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 7488 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7489 unsigned int fl0id, unsigned int fl1id) 7490 { 7491 struct fw_iq_cmd c; 7492 7493 memset(&c, 0, sizeof(c)); 7494 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7495 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7496 V_FW_IQ_CMD_VFN(vf)); 7497 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 7498 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7499 c.iqid = cpu_to_be16(iqid); 7500 c.fl0id = cpu_to_be16(fl0id); 7501 c.fl1id = cpu_to_be16(fl1id); 7502 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7503 } 7504 7505 /** 7506 * t4_iq_free - free an ingress queue and its FLs 7507 * @adap: the adapter 7508 * @mbox: mailbox to use for the FW command 7509 * @pf: the PF owning the queues 7510 * @vf: the VF owning the queues 7511 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7512 * @iqid: ingress queue id 7513 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7514 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7515 * 7516 * Frees an ingress queue and its associated FLs, if any. 7517 */ 7518 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7519 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7520 unsigned int fl0id, unsigned int fl1id) 7521 { 7522 struct fw_iq_cmd c; 7523 7524 memset(&c, 0, sizeof(c)); 7525 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7526 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7527 V_FW_IQ_CMD_VFN(vf)); 7528 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 7529 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7530 c.iqid = cpu_to_be16(iqid); 7531 c.fl0id = cpu_to_be16(fl0id); 7532 c.fl1id = cpu_to_be16(fl1id); 7533 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7534 } 7535 7536 /** 7537 * t4_eth_eq_free - free an Ethernet egress queue 7538 * @adap: the adapter 7539 * @mbox: mailbox to use for the FW command 7540 * @pf: the PF owning the queue 7541 * @vf: the VF owning the queue 7542 * @eqid: egress queue id 7543 * 7544 * Frees an Ethernet egress queue. 7545 */ 7546 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7547 unsigned int vf, unsigned int eqid) 7548 { 7549 struct fw_eq_eth_cmd c; 7550 7551 memset(&c, 0, sizeof(c)); 7552 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 7553 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7554 V_FW_EQ_ETH_CMD_PFN(pf) | 7555 V_FW_EQ_ETH_CMD_VFN(vf)); 7556 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 7557 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 7558 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7559 } 7560 7561 /** 7562 * t4_ctrl_eq_free - free a control egress queue 7563 * @adap: the adapter 7564 * @mbox: mailbox to use for the FW command 7565 * @pf: the PF owning the queue 7566 * @vf: the VF owning the queue 7567 * @eqid: egress queue id 7568 * 7569 * Frees a control egress queue. 7570 */ 7571 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7572 unsigned int vf, unsigned int eqid) 7573 { 7574 struct fw_eq_ctrl_cmd c; 7575 7576 memset(&c, 0, sizeof(c)); 7577 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 7578 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7579 V_FW_EQ_CTRL_CMD_PFN(pf) | 7580 V_FW_EQ_CTRL_CMD_VFN(vf)); 7581 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 7582 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 7583 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7584 } 7585 7586 /** 7587 * t4_ofld_eq_free - free an offload egress queue 7588 * @adap: the adapter 7589 * @mbox: mailbox to use for the FW command 7590 * @pf: the PF owning the queue 7591 * @vf: the VF owning the queue 7592 * @eqid: egress queue id 7593 * 7594 * Frees a control egress queue. 7595 */ 7596 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7597 unsigned int vf, unsigned int eqid) 7598 { 7599 struct fw_eq_ofld_cmd c; 7600 7601 memset(&c, 0, sizeof(c)); 7602 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 7603 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7604 V_FW_EQ_OFLD_CMD_PFN(pf) | 7605 V_FW_EQ_OFLD_CMD_VFN(vf)); 7606 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 7607 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 7608 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7609 } 7610 7611 /** 7612 * t4_link_down_rc_str - return a string for a Link Down Reason Code 7613 * @link_down_rc: Link Down Reason Code 7614 * 7615 * Returns a string representation of the Link Down Reason Code. 7616 */ 7617 const char *t4_link_down_rc_str(unsigned char link_down_rc) 7618 { 7619 static const char *reason[] = { 7620 "Link Down", 7621 "Remote Fault", 7622 "Auto-negotiation Failure", 7623 "Reserved3", 7624 "Insufficient Airflow", 7625 "Unable To Determine Reason", 7626 "No RX Signal Detected", 7627 "Reserved7", 7628 }; 7629 7630 if (link_down_rc >= ARRAY_SIZE(reason)) 7631 return "Bad Reason Code"; 7632 7633 return reason[link_down_rc]; 7634 } 7635 7636 /* 7637 * Updates all fields owned by the common code in port_info and link_config 7638 * based on information provided by the firmware. Does not touch any 7639 * requested_* field. 7640 */ 7641 static void handle_port_info(struct port_info *pi, const struct fw_port_info *p) 7642 { 7643 struct link_config *lc = &pi->link_cfg; 7644 int speed; 7645 unsigned char fc, fec; 7646 u32 stat = be32_to_cpu(p->lstatus_to_modtype); 7647 7648 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 7649 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 7650 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 7651 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 7652 7653 lc->supported = be16_to_cpu(p->pcap); 7654 lc->advertising = be16_to_cpu(p->acap); 7655 lc->lp_advertising = be16_to_cpu(p->lpacap); 7656 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 7657 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 7658 7659 speed = 0; 7660 if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 7661 speed = 100; 7662 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 7663 speed = 1000; 7664 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 7665 speed = 10000; 7666 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 7667 speed = 25000; 7668 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 7669 speed = 40000; 7670 else if (stat & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 7671 speed = 100000; 7672 lc->speed = speed; 7673 7674 fc = 0; 7675 if (stat & F_FW_PORT_CMD_RXPAUSE) 7676 fc |= PAUSE_RX; 7677 if (stat & F_FW_PORT_CMD_TXPAUSE) 7678 fc |= PAUSE_TX; 7679 lc->fc = fc; 7680 7681 fec = 0; 7682 if (lc->advertising & FW_PORT_CAP_FEC_RS) 7683 fec |= FEC_RS; 7684 if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS) 7685 fec |= FEC_BASER_RS; 7686 if (lc->advertising & FW_PORT_CAP_FEC_RESERVED) 7687 fec |= FEC_RESERVED; 7688 lc->fec = fec; 7689 } 7690 7691 /** 7692 * t4_update_port_info - retrieve and update port information if changed 7693 * @pi: the port_info 7694 * 7695 * We issue a Get Port Information Command to the Firmware and, if 7696 * successful, we check to see if anything is different from what we 7697 * last recorded and update things accordingly. 7698 */ 7699 int t4_update_port_info(struct port_info *pi) 7700 { 7701 struct fw_port_cmd port_cmd; 7702 int ret; 7703 7704 memset(&port_cmd, 0, sizeof port_cmd); 7705 port_cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 7706 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7707 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 7708 port_cmd.action_to_len16 = cpu_to_be32( 7709 V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) | 7710 FW_LEN16(port_cmd)); 7711 ret = t4_wr_mbox_ns(pi->adapter, pi->adapter->mbox, 7712 &port_cmd, sizeof(port_cmd), &port_cmd); 7713 if (ret) 7714 return ret; 7715 7716 handle_port_info(pi, &port_cmd.u.info); 7717 return 0; 7718 } 7719 7720 /** 7721 * t4_handle_fw_rpl - process a FW reply message 7722 * @adap: the adapter 7723 * @rpl: start of the FW message 7724 * 7725 * Processes a FW message, such as link state change messages. 7726 */ 7727 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 7728 { 7729 u8 opcode = *(const u8 *)rpl; 7730 const struct fw_port_cmd *p = (const void *)rpl; 7731 unsigned int action = 7732 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 7733 7734 if (opcode == FW_PORT_CMD && action == FW_PORT_ACTION_GET_PORT_INFO) { 7735 /* link/module state change message */ 7736 int i, old_ptype, old_mtype; 7737 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 7738 struct port_info *pi = NULL; 7739 struct link_config *lc, *old_lc; 7740 7741 for_each_port(adap, i) { 7742 pi = adap2pinfo(adap, i); 7743 if (pi->tx_chan == chan) 7744 break; 7745 } 7746 7747 lc = &pi->link_cfg; 7748 old_lc = &pi->old_link_cfg; 7749 old_ptype = pi->port_type; 7750 old_mtype = pi->mod_type; 7751 7752 handle_port_info(pi, &p->u.info); 7753 if (old_ptype != pi->port_type || old_mtype != pi->mod_type) { 7754 t4_os_portmod_changed(pi); 7755 } 7756 if (old_lc->link_ok != lc->link_ok || 7757 old_lc->speed != lc->speed || 7758 old_lc->fec != lc->fec || 7759 old_lc->fc != lc->fc) { 7760 t4_os_link_changed(pi); 7761 *old_lc = *lc; 7762 } 7763 } else { 7764 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 7765 return -EINVAL; 7766 } 7767 return 0; 7768 } 7769 7770 /** 7771 * get_pci_mode - determine a card's PCI mode 7772 * @adapter: the adapter 7773 * @p: where to store the PCI settings 7774 * 7775 * Determines a card's PCI mode and associated parameters, such as speed 7776 * and width. 7777 */ 7778 static void get_pci_mode(struct adapter *adapter, 7779 struct pci_params *p) 7780 { 7781 u16 val; 7782 u32 pcie_cap; 7783 7784 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 7785 if (pcie_cap) { 7786 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 7787 p->speed = val & PCI_EXP_LNKSTA_CLS; 7788 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 7789 } 7790 } 7791 7792 struct flash_desc { 7793 u32 vendor_and_model_id; 7794 u32 size_mb; 7795 }; 7796 7797 int t4_get_flash_params(struct adapter *adapter) 7798 { 7799 /* 7800 * Table for non-standard supported Flash parts. Note, all Flash 7801 * parts must have 64KB sectors. 7802 */ 7803 static struct flash_desc supported_flash[] = { 7804 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 7805 }; 7806 7807 int ret; 7808 u32 flashid = 0; 7809 unsigned int part, manufacturer; 7810 unsigned int density, size; 7811 7812 7813 /* 7814 * Issue a Read ID Command to the Flash part. We decode supported 7815 * Flash parts and their sizes from this. There's a newer Query 7816 * Command which can retrieve detailed geometry information but many 7817 * Flash parts don't support it. 7818 */ 7819 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 7820 if (!ret) 7821 ret = sf1_read(adapter, 3, 0, 1, &flashid); 7822 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 7823 if (ret < 0) 7824 return ret; 7825 7826 /* 7827 * Check to see if it's one of our non-standard supported Flash parts. 7828 */ 7829 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 7830 if (supported_flash[part].vendor_and_model_id == flashid) { 7831 adapter->params.sf_size = 7832 supported_flash[part].size_mb; 7833 adapter->params.sf_nsec = 7834 adapter->params.sf_size / SF_SEC_SIZE; 7835 goto found; 7836 } 7837 7838 /* 7839 * Decode Flash part size. The code below looks repetative with 7840 * common encodings, but that's not guaranteed in the JEDEC 7841 * specification for the Read JADEC ID command. The only thing that 7842 * we're guaranteed by the JADEC specification is where the 7843 * Manufacturer ID is in the returned result. After that each 7844 * Manufacturer ~could~ encode things completely differently. 7845 * Note, all Flash parts must have 64KB sectors. 7846 */ 7847 manufacturer = flashid & 0xff; 7848 switch (manufacturer) { 7849 case 0x20: { /* Micron/Numonix */ 7850 /* 7851 * This Density -> Size decoding table is taken from Micron 7852 * Data Sheets. 7853 */ 7854 density = (flashid >> 16) & 0xff; 7855 switch (density) { 7856 case 0x14: size = 1 << 20; break; /* 1MB */ 7857 case 0x15: size = 1 << 21; break; /* 2MB */ 7858 case 0x16: size = 1 << 22; break; /* 4MB */ 7859 case 0x17: size = 1 << 23; break; /* 8MB */ 7860 case 0x18: size = 1 << 24; break; /* 16MB */ 7861 case 0x19: size = 1 << 25; break; /* 32MB */ 7862 case 0x20: size = 1 << 26; break; /* 64MB */ 7863 case 0x21: size = 1 << 27; break; /* 128MB */ 7864 case 0x22: size = 1 << 28; break; /* 256MB */ 7865 7866 default: 7867 CH_ERR(adapter, "Micron Flash Part has bad size, " 7868 "ID = %#x, Density code = %#x\n", 7869 flashid, density); 7870 return -EINVAL; 7871 } 7872 break; 7873 } 7874 7875 case 0xef: { /* Winbond */ 7876 /* 7877 * This Density -> Size decoding table is taken from Winbond 7878 * Data Sheets. 7879 */ 7880 density = (flashid >> 16) & 0xff; 7881 switch (density) { 7882 case 0x17: size = 1 << 23; break; /* 8MB */ 7883 case 0x18: size = 1 << 24; break; /* 16MB */ 7884 7885 default: 7886 CH_ERR(adapter, "Winbond Flash Part has bad size, " 7887 "ID = %#x, Density code = %#x\n", 7888 flashid, density); 7889 return -EINVAL; 7890 } 7891 break; 7892 } 7893 7894 default: 7895 CH_ERR(adapter, "Unsupported Flash Part, ID = %#x\n", flashid); 7896 return -EINVAL; 7897 } 7898 7899 /* 7900 * Store decoded Flash size and fall through into vetting code. 7901 */ 7902 adapter->params.sf_size = size; 7903 adapter->params.sf_nsec = size / SF_SEC_SIZE; 7904 7905 found: 7906 /* 7907 * We should ~probably~ reject adapters with FLASHes which are too 7908 * small but we have some legacy FPGAs with small FLASHes that we'd 7909 * still like to use. So instead we emit a scary message ... 7910 */ 7911 if (adapter->params.sf_size < FLASH_MIN_SIZE) 7912 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 7913 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 7914 7915 return 0; 7916 } 7917 7918 static void set_pcie_completion_timeout(struct adapter *adapter, 7919 u8 range) 7920 { 7921 u16 val; 7922 u32 pcie_cap; 7923 7924 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 7925 if (pcie_cap) { 7926 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 7927 val &= 0xfff0; 7928 val |= range ; 7929 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 7930 } 7931 } 7932 7933 const struct chip_params *t4_get_chip_params(int chipid) 7934 { 7935 static const struct chip_params chip_params[] = { 7936 { 7937 /* T4 */ 7938 .nchan = NCHAN, 7939 .pm_stats_cnt = PM_NSTATS, 7940 .cng_ch_bits_log = 2, 7941 .nsched_cls = 15, 7942 .cim_num_obq = CIM_NUM_OBQ, 7943 .mps_rplc_size = 128, 7944 .vfcount = 128, 7945 .sge_fl_db = F_DBPRIO, 7946 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 7947 }, 7948 { 7949 /* T5 */ 7950 .nchan = NCHAN, 7951 .pm_stats_cnt = PM_NSTATS, 7952 .cng_ch_bits_log = 2, 7953 .nsched_cls = 16, 7954 .cim_num_obq = CIM_NUM_OBQ_T5, 7955 .mps_rplc_size = 128, 7956 .vfcount = 128, 7957 .sge_fl_db = F_DBPRIO | F_DBTYPE, 7958 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 7959 }, 7960 { 7961 /* T6 */ 7962 .nchan = T6_NCHAN, 7963 .pm_stats_cnt = T6_PM_NSTATS, 7964 .cng_ch_bits_log = 3, 7965 .nsched_cls = 16, 7966 .cim_num_obq = CIM_NUM_OBQ_T5, 7967 .mps_rplc_size = 256, 7968 .vfcount = 256, 7969 .sge_fl_db = 0, 7970 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 7971 }, 7972 }; 7973 7974 chipid -= CHELSIO_T4; 7975 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 7976 return NULL; 7977 7978 return &chip_params[chipid]; 7979 } 7980 7981 /** 7982 * t4_prep_adapter - prepare SW and HW for operation 7983 * @adapter: the adapter 7984 * @buf: temporary space of at least VPD_LEN size provided by the caller. 7985 * 7986 * Initialize adapter SW state for the various HW modules, set initial 7987 * values for some adapter tunables, take PHYs out of reset, and 7988 * initialize the MDIO interface. 7989 */ 7990 int t4_prep_adapter(struct adapter *adapter, u8 *buf) 7991 { 7992 int ret; 7993 uint16_t device_id; 7994 uint32_t pl_rev; 7995 7996 get_pci_mode(adapter, &adapter->params.pci); 7997 7998 pl_rev = t4_read_reg(adapter, A_PL_REV); 7999 adapter->params.chipid = G_CHIPID(pl_rev); 8000 adapter->params.rev = G_REV(pl_rev); 8001 if (adapter->params.chipid == 0) { 8002 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 8003 adapter->params.chipid = CHELSIO_T4; 8004 8005 /* T4A1 chip is not supported */ 8006 if (adapter->params.rev == 1) { 8007 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 8008 return -EINVAL; 8009 } 8010 } 8011 8012 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 8013 if (adapter->chip_params == NULL) 8014 return -EINVAL; 8015 8016 adapter->params.pci.vpd_cap_addr = 8017 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 8018 8019 ret = t4_get_flash_params(adapter); 8020 if (ret < 0) 8021 return ret; 8022 8023 ret = get_vpd_params(adapter, &adapter->params.vpd, buf); 8024 if (ret < 0) 8025 return ret; 8026 8027 /* Cards with real ASICs have the chipid in the PCIe device id */ 8028 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 8029 if (device_id >> 12 == chip_id(adapter)) 8030 adapter->params.cim_la_size = CIMLA_SIZE; 8031 else { 8032 /* FPGA */ 8033 adapter->params.fpga = 1; 8034 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 8035 } 8036 8037 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 8038 8039 /* 8040 * Default port and clock for debugging in case we can't reach FW. 8041 */ 8042 adapter->params.nports = 1; 8043 adapter->params.portvec = 1; 8044 adapter->params.vpd.cclk = 50000; 8045 8046 /* Set pci completion timeout value to 4 seconds. */ 8047 set_pcie_completion_timeout(adapter, 0xd); 8048 return 0; 8049 } 8050 8051 /** 8052 * t4_shutdown_adapter - shut down adapter, host & wire 8053 * @adapter: the adapter 8054 * 8055 * Perform an emergency shutdown of the adapter and stop it from 8056 * continuing any further communication on the ports or DMA to the 8057 * host. This is typically used when the adapter and/or firmware 8058 * have crashed and we want to prevent any further accidental 8059 * communication with the rest of the world. This will also force 8060 * the port Link Status to go down -- if register writes work -- 8061 * which should help our peers figure out that we're down. 8062 */ 8063 int t4_shutdown_adapter(struct adapter *adapter) 8064 { 8065 int port; 8066 8067 t4_intr_disable(adapter); 8068 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 8069 for_each_port(adapter, port) { 8070 u32 a_port_cfg = is_t4(adapter) ? 8071 PORT_REG(port, A_XGMAC_PORT_CFG) : 8072 T5_PORT_REG(port, A_MAC_PORT_CFG); 8073 8074 t4_write_reg(adapter, a_port_cfg, 8075 t4_read_reg(adapter, a_port_cfg) 8076 & ~V_SIGNAL_DET(1)); 8077 } 8078 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 8079 8080 return 0; 8081 } 8082 8083 /** 8084 * t4_init_devlog_params - initialize adapter->params.devlog 8085 * @adap: the adapter 8086 * @fw_attach: whether we can talk to the firmware 8087 * 8088 * Initialize various fields of the adapter's Firmware Device Log 8089 * Parameters structure. 8090 */ 8091 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 8092 { 8093 struct devlog_params *dparams = &adap->params.devlog; 8094 u32 pf_dparams; 8095 unsigned int devlog_meminfo; 8096 struct fw_devlog_cmd devlog_cmd; 8097 int ret; 8098 8099 /* If we're dealing with newer firmware, the Device Log Paramerters 8100 * are stored in a designated register which allows us to access the 8101 * Device Log even if we can't talk to the firmware. 8102 */ 8103 pf_dparams = 8104 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 8105 if (pf_dparams) { 8106 unsigned int nentries, nentries128; 8107 8108 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 8109 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 8110 8111 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 8112 nentries = (nentries128 + 1) * 128; 8113 dparams->size = nentries * sizeof(struct fw_devlog_e); 8114 8115 return 0; 8116 } 8117 8118 /* 8119 * For any failing returns ... 8120 */ 8121 memset(dparams, 0, sizeof *dparams); 8122 8123 /* 8124 * If we can't talk to the firmware, there's really nothing we can do 8125 * at this point. 8126 */ 8127 if (!fw_attach) 8128 return -ENXIO; 8129 8130 /* Otherwise, ask the firmware for it's Device Log Parameters. 8131 */ 8132 memset(&devlog_cmd, 0, sizeof devlog_cmd); 8133 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 8134 F_FW_CMD_REQUEST | F_FW_CMD_READ); 8135 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 8136 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 8137 &devlog_cmd); 8138 if (ret) 8139 return ret; 8140 8141 devlog_meminfo = 8142 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 8143 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 8144 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 8145 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 8146 8147 return 0; 8148 } 8149 8150 /** 8151 * t4_init_sge_params - initialize adap->params.sge 8152 * @adapter: the adapter 8153 * 8154 * Initialize various fields of the adapter's SGE Parameters structure. 8155 */ 8156 int t4_init_sge_params(struct adapter *adapter) 8157 { 8158 u32 r; 8159 struct sge_params *sp = &adapter->params.sge; 8160 unsigned i, tscale = 1; 8161 8162 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 8163 sp->counter_val[0] = G_THRESHOLD_0(r); 8164 sp->counter_val[1] = G_THRESHOLD_1(r); 8165 sp->counter_val[2] = G_THRESHOLD_2(r); 8166 sp->counter_val[3] = G_THRESHOLD_3(r); 8167 8168 if (chip_id(adapter) >= CHELSIO_T6) { 8169 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 8170 tscale = G_TSCALE(r); 8171 if (tscale == 0) 8172 tscale = 1; 8173 else 8174 tscale += 2; 8175 } 8176 8177 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 8178 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 8179 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 8180 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 8181 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 8182 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 8183 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 8184 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 8185 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 8186 8187 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 8188 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 8189 if (is_t4(adapter)) 8190 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 8191 else if (is_t5(adapter)) 8192 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 8193 else 8194 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 8195 8196 /* egress queues: log2 of # of doorbells per BAR2 page */ 8197 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 8198 r >>= S_QUEUESPERPAGEPF0 + 8199 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8200 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 8201 8202 /* ingress queues: log2 of # of doorbells per BAR2 page */ 8203 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 8204 r >>= S_QUEUESPERPAGEPF0 + 8205 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8206 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 8207 8208 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 8209 r >>= S_HOSTPAGESIZEPF0 + 8210 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 8211 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 8212 8213 r = t4_read_reg(adapter, A_SGE_CONTROL); 8214 sp->sge_control = r; 8215 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 8216 sp->fl_pktshift = G_PKTSHIFT(r); 8217 if (chip_id(adapter) <= CHELSIO_T5) { 8218 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8219 X_INGPADBOUNDARY_SHIFT); 8220 } else { 8221 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8222 X_T6_INGPADBOUNDARY_SHIFT); 8223 } 8224 if (is_t4(adapter)) 8225 sp->pack_boundary = sp->pad_boundary; 8226 else { 8227 r = t4_read_reg(adapter, A_SGE_CONTROL2); 8228 if (G_INGPACKBOUNDARY(r) == 0) 8229 sp->pack_boundary = 16; 8230 else 8231 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 8232 } 8233 for (i = 0; i < SGE_FLBUF_SIZES; i++) 8234 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 8235 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 8236 8237 return 0; 8238 } 8239 8240 /* 8241 * Read and cache the adapter's compressed filter mode and ingress config. 8242 */ 8243 static void read_filter_mode_and_ingress_config(struct adapter *adap, 8244 bool sleep_ok) 8245 { 8246 struct tp_params *tpp = &adap->params.tp; 8247 8248 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP, 8249 sleep_ok); 8250 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG, 8251 sleep_ok); 8252 8253 /* 8254 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 8255 * shift positions of several elements of the Compressed Filter Tuple 8256 * for this adapter which we need frequently ... 8257 */ 8258 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 8259 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 8260 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 8261 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 8262 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 8263 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 8264 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 8265 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 8266 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 8267 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 8268 8269 /* 8270 * If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID 8271 * represents the presence of an Outer VLAN instead of a VNIC ID. 8272 */ 8273 if ((tpp->ingress_config & F_VNIC) == 0) 8274 tpp->vnic_shift = -1; 8275 } 8276 8277 /** 8278 * t4_init_tp_params - initialize adap->params.tp 8279 * @adap: the adapter 8280 * 8281 * Initialize various fields of the adapter's TP Parameters structure. 8282 */ 8283 int t4_init_tp_params(struct adapter *adap, bool sleep_ok) 8284 { 8285 int chan; 8286 u32 v; 8287 struct tp_params *tpp = &adap->params.tp; 8288 8289 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 8290 tpp->tre = G_TIMERRESOLUTION(v); 8291 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 8292 8293 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 8294 for (chan = 0; chan < MAX_NCHAN; chan++) 8295 tpp->tx_modq[chan] = chan; 8296 8297 read_filter_mode_and_ingress_config(adap, sleep_ok); 8298 8299 /* 8300 * Cache a mask of the bits that represent the error vector portion of 8301 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room 8302 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE). 8303 */ 8304 tpp->err_vec_mask = htobe16(0xffff); 8305 if (chip_id(adap) > CHELSIO_T5) { 8306 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 8307 if (v & F_CRXPKTENC) { 8308 tpp->err_vec_mask = 8309 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC)); 8310 } 8311 } 8312 8313 return 0; 8314 } 8315 8316 /** 8317 * t4_filter_field_shift - calculate filter field shift 8318 * @adap: the adapter 8319 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 8320 * 8321 * Return the shift position of a filter field within the Compressed 8322 * Filter Tuple. The filter field is specified via its selection bit 8323 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 8324 */ 8325 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 8326 { 8327 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 8328 unsigned int sel; 8329 int field_shift; 8330 8331 if ((filter_mode & filter_sel) == 0) 8332 return -1; 8333 8334 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 8335 switch (filter_mode & sel) { 8336 case F_FCOE: 8337 field_shift += W_FT_FCOE; 8338 break; 8339 case F_PORT: 8340 field_shift += W_FT_PORT; 8341 break; 8342 case F_VNIC_ID: 8343 field_shift += W_FT_VNIC_ID; 8344 break; 8345 case F_VLAN: 8346 field_shift += W_FT_VLAN; 8347 break; 8348 case F_TOS: 8349 field_shift += W_FT_TOS; 8350 break; 8351 case F_PROTOCOL: 8352 field_shift += W_FT_PROTOCOL; 8353 break; 8354 case F_ETHERTYPE: 8355 field_shift += W_FT_ETHERTYPE; 8356 break; 8357 case F_MACMATCH: 8358 field_shift += W_FT_MACMATCH; 8359 break; 8360 case F_MPSHITTYPE: 8361 field_shift += W_FT_MPSHITTYPE; 8362 break; 8363 case F_FRAGMENTATION: 8364 field_shift += W_FT_FRAGMENTATION; 8365 break; 8366 } 8367 } 8368 return field_shift; 8369 } 8370 8371 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 8372 { 8373 u8 addr[6]; 8374 int ret, i, j; 8375 u16 rss_size; 8376 struct port_info *p = adap2pinfo(adap, port_id); 8377 u32 param, val; 8378 8379 for (i = 0, j = -1; i <= p->port_id; i++) { 8380 do { 8381 j++; 8382 } while ((adap->params.portvec & (1 << j)) == 0); 8383 } 8384 8385 if (!(adap->flags & IS_VF) || 8386 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 8387 t4_update_port_info(p); 8388 } 8389 8390 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 8391 if (ret < 0) 8392 return ret; 8393 8394 p->vi[0].viid = ret; 8395 if (chip_id(adap) <= CHELSIO_T5) 8396 p->vi[0].smt_idx = (ret & 0x7f) << 1; 8397 else 8398 p->vi[0].smt_idx = (ret & 0x7f); 8399 p->tx_chan = j; 8400 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 8401 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 8402 p->lport = j; 8403 p->vi[0].rss_size = rss_size; 8404 t4_os_set_hw_addr(p, addr); 8405 8406 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8407 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 8408 V_FW_PARAMS_PARAM_YZ(p->vi[0].viid); 8409 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 8410 if (ret) 8411 p->vi[0].rss_base = 0xffff; 8412 else { 8413 /* MPASS((val >> 16) == rss_size); */ 8414 p->vi[0].rss_base = val & 0xffff; 8415 } 8416 8417 return 0; 8418 } 8419 8420 /** 8421 * t4_read_cimq_cfg - read CIM queue configuration 8422 * @adap: the adapter 8423 * @base: holds the queue base addresses in bytes 8424 * @size: holds the queue sizes in bytes 8425 * @thres: holds the queue full thresholds in bytes 8426 * 8427 * Returns the current configuration of the CIM queues, starting with 8428 * the IBQs, then the OBQs. 8429 */ 8430 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 8431 { 8432 unsigned int i, v; 8433 int cim_num_obq = adap->chip_params->cim_num_obq; 8434 8435 for (i = 0; i < CIM_NUM_IBQ; i++) { 8436 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 8437 V_QUENUMSELECT(i)); 8438 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8439 /* value is in 256-byte units */ 8440 *base++ = G_CIMQBASE(v) * 256; 8441 *size++ = G_CIMQSIZE(v) * 256; 8442 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 8443 } 8444 for (i = 0; i < cim_num_obq; i++) { 8445 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8446 V_QUENUMSELECT(i)); 8447 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8448 /* value is in 256-byte units */ 8449 *base++ = G_CIMQBASE(v) * 256; 8450 *size++ = G_CIMQSIZE(v) * 256; 8451 } 8452 } 8453 8454 /** 8455 * t4_read_cim_ibq - read the contents of a CIM inbound queue 8456 * @adap: the adapter 8457 * @qid: the queue index 8458 * @data: where to store the queue contents 8459 * @n: capacity of @data in 32-bit words 8460 * 8461 * Reads the contents of the selected CIM queue starting at address 0 up 8462 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8463 * error and the number of 32-bit words actually read on success. 8464 */ 8465 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8466 { 8467 int i, err, attempts; 8468 unsigned int addr; 8469 const unsigned int nwords = CIM_IBQ_SIZE * 4; 8470 8471 if (qid > 5 || (n & 3)) 8472 return -EINVAL; 8473 8474 addr = qid * nwords; 8475 if (n > nwords) 8476 n = nwords; 8477 8478 /* It might take 3-10ms before the IBQ debug read access is allowed. 8479 * Wait for 1 Sec with a delay of 1 usec. 8480 */ 8481 attempts = 1000000; 8482 8483 for (i = 0; i < n; i++, addr++) { 8484 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 8485 F_IBQDBGEN); 8486 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 8487 attempts, 1); 8488 if (err) 8489 return err; 8490 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 8491 } 8492 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 8493 return i; 8494 } 8495 8496 /** 8497 * t4_read_cim_obq - read the contents of a CIM outbound queue 8498 * @adap: the adapter 8499 * @qid: the queue index 8500 * @data: where to store the queue contents 8501 * @n: capacity of @data in 32-bit words 8502 * 8503 * Reads the contents of the selected CIM queue starting at address 0 up 8504 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8505 * error and the number of 32-bit words actually read on success. 8506 */ 8507 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8508 { 8509 int i, err; 8510 unsigned int addr, v, nwords; 8511 int cim_num_obq = adap->chip_params->cim_num_obq; 8512 8513 if ((qid > (cim_num_obq - 1)) || (n & 3)) 8514 return -EINVAL; 8515 8516 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8517 V_QUENUMSELECT(qid)); 8518 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8519 8520 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 8521 nwords = G_CIMQSIZE(v) * 64; /* same */ 8522 if (n > nwords) 8523 n = nwords; 8524 8525 for (i = 0; i < n; i++, addr++) { 8526 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 8527 F_OBQDBGEN); 8528 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 8529 2, 1); 8530 if (err) 8531 return err; 8532 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 8533 } 8534 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 8535 return i; 8536 } 8537 8538 enum { 8539 CIM_QCTL_BASE = 0, 8540 CIM_CTL_BASE = 0x2000, 8541 CIM_PBT_ADDR_BASE = 0x2800, 8542 CIM_PBT_LRF_BASE = 0x3000, 8543 CIM_PBT_DATA_BASE = 0x3800 8544 }; 8545 8546 /** 8547 * t4_cim_read - read a block from CIM internal address space 8548 * @adap: the adapter 8549 * @addr: the start address within the CIM address space 8550 * @n: number of words to read 8551 * @valp: where to store the result 8552 * 8553 * Reads a block of 4-byte words from the CIM intenal address space. 8554 */ 8555 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 8556 unsigned int *valp) 8557 { 8558 int ret = 0; 8559 8560 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8561 return -EBUSY; 8562 8563 for ( ; !ret && n--; addr += 4) { 8564 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 8565 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8566 0, 5, 2); 8567 if (!ret) 8568 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 8569 } 8570 return ret; 8571 } 8572 8573 /** 8574 * t4_cim_write - write a block into CIM internal address space 8575 * @adap: the adapter 8576 * @addr: the start address within the CIM address space 8577 * @n: number of words to write 8578 * @valp: set of values to write 8579 * 8580 * Writes a block of 4-byte words into the CIM intenal address space. 8581 */ 8582 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 8583 const unsigned int *valp) 8584 { 8585 int ret = 0; 8586 8587 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8588 return -EBUSY; 8589 8590 for ( ; !ret && n--; addr += 4) { 8591 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 8592 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 8593 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8594 0, 5, 2); 8595 } 8596 return ret; 8597 } 8598 8599 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 8600 unsigned int val) 8601 { 8602 return t4_cim_write(adap, addr, 1, &val); 8603 } 8604 8605 /** 8606 * t4_cim_ctl_read - read a block from CIM control region 8607 * @adap: the adapter 8608 * @addr: the start address within the CIM control region 8609 * @n: number of words to read 8610 * @valp: where to store the result 8611 * 8612 * Reads a block of 4-byte words from the CIM control region. 8613 */ 8614 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 8615 unsigned int *valp) 8616 { 8617 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 8618 } 8619 8620 /** 8621 * t4_cim_read_la - read CIM LA capture buffer 8622 * @adap: the adapter 8623 * @la_buf: where to store the LA data 8624 * @wrptr: the HW write pointer within the capture buffer 8625 * 8626 * Reads the contents of the CIM LA buffer with the most recent entry at 8627 * the end of the returned data and with the entry at @wrptr first. 8628 * We try to leave the LA in the running state we find it in. 8629 */ 8630 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 8631 { 8632 int i, ret; 8633 unsigned int cfg, val, idx; 8634 8635 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 8636 if (ret) 8637 return ret; 8638 8639 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 8640 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 8641 if (ret) 8642 return ret; 8643 } 8644 8645 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 8646 if (ret) 8647 goto restart; 8648 8649 idx = G_UPDBGLAWRPTR(val); 8650 if (wrptr) 8651 *wrptr = idx; 8652 8653 for (i = 0; i < adap->params.cim_la_size; i++) { 8654 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 8655 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 8656 if (ret) 8657 break; 8658 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 8659 if (ret) 8660 break; 8661 if (val & F_UPDBGLARDEN) { 8662 ret = -ETIMEDOUT; 8663 break; 8664 } 8665 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 8666 if (ret) 8667 break; 8668 8669 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */ 8670 idx = (idx + 1) & M_UPDBGLARDPTR; 8671 /* 8672 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 8673 * identify the 32-bit portion of the full 312-bit data 8674 */ 8675 if (is_t6(adap)) 8676 while ((idx & 0xf) > 9) 8677 idx = (idx + 1) % M_UPDBGLARDPTR; 8678 } 8679 restart: 8680 if (cfg & F_UPDBGLAEN) { 8681 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 8682 cfg & ~F_UPDBGLARDEN); 8683 if (!ret) 8684 ret = r; 8685 } 8686 return ret; 8687 } 8688 8689 /** 8690 * t4_tp_read_la - read TP LA capture buffer 8691 * @adap: the adapter 8692 * @la_buf: where to store the LA data 8693 * @wrptr: the HW write pointer within the capture buffer 8694 * 8695 * Reads the contents of the TP LA buffer with the most recent entry at 8696 * the end of the returned data and with the entry at @wrptr first. 8697 * We leave the LA in the running state we find it in. 8698 */ 8699 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 8700 { 8701 bool last_incomplete; 8702 unsigned int i, cfg, val, idx; 8703 8704 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 8705 if (cfg & F_DBGLAENABLE) /* freeze LA */ 8706 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 8707 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 8708 8709 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 8710 idx = G_DBGLAWPTR(val); 8711 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 8712 if (last_incomplete) 8713 idx = (idx + 1) & M_DBGLARPTR; 8714 if (wrptr) 8715 *wrptr = idx; 8716 8717 val &= 0xffff; 8718 val &= ~V_DBGLARPTR(M_DBGLARPTR); 8719 val |= adap->params.tp.la_mask; 8720 8721 for (i = 0; i < TPLA_SIZE; i++) { 8722 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 8723 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 8724 idx = (idx + 1) & M_DBGLARPTR; 8725 } 8726 8727 /* Wipe out last entry if it isn't valid */ 8728 if (last_incomplete) 8729 la_buf[TPLA_SIZE - 1] = ~0ULL; 8730 8731 if (cfg & F_DBGLAENABLE) /* restore running state */ 8732 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 8733 cfg | adap->params.tp.la_mask); 8734 } 8735 8736 /* 8737 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 8738 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 8739 * state for more than the Warning Threshold then we'll issue a warning about 8740 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 8741 * appears to be hung every Warning Repeat second till the situation clears. 8742 * If the situation clears, we'll note that as well. 8743 */ 8744 #define SGE_IDMA_WARN_THRESH 1 8745 #define SGE_IDMA_WARN_REPEAT 300 8746 8747 /** 8748 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 8749 * @adapter: the adapter 8750 * @idma: the adapter IDMA Monitor state 8751 * 8752 * Initialize the state of an SGE Ingress DMA Monitor. 8753 */ 8754 void t4_idma_monitor_init(struct adapter *adapter, 8755 struct sge_idma_monitor_state *idma) 8756 { 8757 /* Initialize the state variables for detecting an SGE Ingress DMA 8758 * hang. The SGE has internal counters which count up on each clock 8759 * tick whenever the SGE finds its Ingress DMA State Engines in the 8760 * same state they were on the previous clock tick. The clock used is 8761 * the Core Clock so we have a limit on the maximum "time" they can 8762 * record; typically a very small number of seconds. For instance, 8763 * with a 600MHz Core Clock, we can only count up to a bit more than 8764 * 7s. So we'll synthesize a larger counter in order to not run the 8765 * risk of having the "timers" overflow and give us the flexibility to 8766 * maintain a Hung SGE State Machine of our own which operates across 8767 * a longer time frame. 8768 */ 8769 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 8770 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 8771 } 8772 8773 /** 8774 * t4_idma_monitor - monitor SGE Ingress DMA state 8775 * @adapter: the adapter 8776 * @idma: the adapter IDMA Monitor state 8777 * @hz: number of ticks/second 8778 * @ticks: number of ticks since the last IDMA Monitor call 8779 */ 8780 void t4_idma_monitor(struct adapter *adapter, 8781 struct sge_idma_monitor_state *idma, 8782 int hz, int ticks) 8783 { 8784 int i, idma_same_state_cnt[2]; 8785 8786 /* Read the SGE Debug Ingress DMA Same State Count registers. These 8787 * are counters inside the SGE which count up on each clock when the 8788 * SGE finds its Ingress DMA State Engines in the same states they 8789 * were in the previous clock. The counters will peg out at 8790 * 0xffffffff without wrapping around so once they pass the 1s 8791 * threshold they'll stay above that till the IDMA state changes. 8792 */ 8793 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 8794 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 8795 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8796 8797 for (i = 0; i < 2; i++) { 8798 u32 debug0, debug11; 8799 8800 /* If the Ingress DMA Same State Counter ("timer") is less 8801 * than 1s, then we can reset our synthesized Stall Timer and 8802 * continue. If we have previously emitted warnings about a 8803 * potential stalled Ingress Queue, issue a note indicating 8804 * that the Ingress Queue has resumed forward progress. 8805 */ 8806 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 8807 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 8808 CH_WARN(adapter, "SGE idma%d, queue %u, " 8809 "resumed after %d seconds\n", 8810 i, idma->idma_qid[i], 8811 idma->idma_stalled[i]/hz); 8812 idma->idma_stalled[i] = 0; 8813 continue; 8814 } 8815 8816 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 8817 * domain. The first time we get here it'll be because we 8818 * passed the 1s Threshold; each additional time it'll be 8819 * because the RX Timer Callback is being fired on its regular 8820 * schedule. 8821 * 8822 * If the stall is below our Potential Hung Ingress Queue 8823 * Warning Threshold, continue. 8824 */ 8825 if (idma->idma_stalled[i] == 0) { 8826 idma->idma_stalled[i] = hz; 8827 idma->idma_warn[i] = 0; 8828 } else { 8829 idma->idma_stalled[i] += ticks; 8830 idma->idma_warn[i] -= ticks; 8831 } 8832 8833 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 8834 continue; 8835 8836 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 8837 */ 8838 if (idma->idma_warn[i] > 0) 8839 continue; 8840 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 8841 8842 /* Read and save the SGE IDMA State and Queue ID information. 8843 * We do this every time in case it changes across time ... 8844 * can't be too careful ... 8845 */ 8846 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 8847 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8848 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 8849 8850 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 8851 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 8852 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 8853 8854 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 8855 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 8856 i, idma->idma_qid[i], idma->idma_state[i], 8857 idma->idma_stalled[i]/hz, 8858 debug0, debug11); 8859 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 8860 } 8861 } 8862 8863 /** 8864 * t4_read_pace_tbl - read the pace table 8865 * @adap: the adapter 8866 * @pace_vals: holds the returned values 8867 * 8868 * Returns the values of TP's pace table in microseconds. 8869 */ 8870 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 8871 { 8872 unsigned int i, v; 8873 8874 for (i = 0; i < NTX_SCHED; i++) { 8875 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 8876 v = t4_read_reg(adap, A_TP_PACE_TABLE); 8877 pace_vals[i] = dack_ticks_to_usec(adap, v); 8878 } 8879 } 8880 8881 /** 8882 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 8883 * @adap: the adapter 8884 * @sched: the scheduler index 8885 * @kbps: the byte rate in Kbps 8886 * @ipg: the interpacket delay in tenths of nanoseconds 8887 * 8888 * Return the current configuration of a HW Tx scheduler. 8889 */ 8890 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 8891 unsigned int *ipg, bool sleep_ok) 8892 { 8893 unsigned int v, addr, bpt, cpt; 8894 8895 if (kbps) { 8896 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 8897 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 8898 if (sched & 1) 8899 v >>= 16; 8900 bpt = (v >> 8) & 0xff; 8901 cpt = v & 0xff; 8902 if (!cpt) 8903 *kbps = 0; /* scheduler disabled */ 8904 else { 8905 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 8906 *kbps = (v * bpt) / 125; 8907 } 8908 } 8909 if (ipg) { 8910 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 8911 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 8912 if (sched & 1) 8913 v >>= 16; 8914 v &= 0xffff; 8915 *ipg = (10000 * v) / core_ticks_per_usec(adap); 8916 } 8917 } 8918 8919 /** 8920 * t4_load_cfg - download config file 8921 * @adap: the adapter 8922 * @cfg_data: the cfg text file to write 8923 * @size: text file size 8924 * 8925 * Write the supplied config text file to the card's serial flash. 8926 */ 8927 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 8928 { 8929 int ret, i, n, cfg_addr; 8930 unsigned int addr; 8931 unsigned int flash_cfg_start_sec; 8932 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 8933 8934 cfg_addr = t4_flash_cfg_addr(adap); 8935 if (cfg_addr < 0) 8936 return cfg_addr; 8937 8938 addr = cfg_addr; 8939 flash_cfg_start_sec = addr / SF_SEC_SIZE; 8940 8941 if (size > FLASH_CFG_MAX_SIZE) { 8942 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 8943 FLASH_CFG_MAX_SIZE); 8944 return -EFBIG; 8945 } 8946 8947 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 8948 sf_sec_size); 8949 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 8950 flash_cfg_start_sec + i - 1); 8951 /* 8952 * If size == 0 then we're simply erasing the FLASH sectors associated 8953 * with the on-adapter Firmware Configuration File. 8954 */ 8955 if (ret || size == 0) 8956 goto out; 8957 8958 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 8959 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 8960 if ( (size - i) < SF_PAGE_SIZE) 8961 n = size - i; 8962 else 8963 n = SF_PAGE_SIZE; 8964 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 8965 if (ret) 8966 goto out; 8967 8968 addr += SF_PAGE_SIZE; 8969 cfg_data += SF_PAGE_SIZE; 8970 } 8971 8972 out: 8973 if (ret) 8974 CH_ERR(adap, "config file %s failed %d\n", 8975 (size == 0 ? "clear" : "download"), ret); 8976 return ret; 8977 } 8978 8979 /** 8980 * t5_fw_init_extern_mem - initialize the external memory 8981 * @adap: the adapter 8982 * 8983 * Initializes the external memory on T5. 8984 */ 8985 int t5_fw_init_extern_mem(struct adapter *adap) 8986 { 8987 u32 params[1], val[1]; 8988 int ret; 8989 8990 if (!is_t5(adap)) 8991 return 0; 8992 8993 val[0] = 0xff; /* Initialize all MCs */ 8994 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8995 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 8996 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 8997 FW_CMD_MAX_TIMEOUT); 8998 8999 return ret; 9000 } 9001 9002 /* BIOS boot headers */ 9003 typedef struct pci_expansion_rom_header { 9004 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9005 u8 reserved[22]; /* Reserved per processor Architecture data */ 9006 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9007 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 9008 9009 /* Legacy PCI Expansion ROM Header */ 9010 typedef struct legacy_pci_expansion_rom_header { 9011 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9012 u8 size512; /* Current Image Size in units of 512 bytes */ 9013 u8 initentry_point[4]; 9014 u8 cksum; /* Checksum computed on the entire Image */ 9015 u8 reserved[16]; /* Reserved */ 9016 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 9017 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 9018 9019 /* EFI PCI Expansion ROM Header */ 9020 typedef struct efi_pci_expansion_rom_header { 9021 u8 signature[2]; // ROM signature. The value 0xaa55 9022 u8 initialization_size[2]; /* Units 512. Includes this header */ 9023 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 9024 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 9025 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 9026 u8 compression_type[2]; /* Compression type. */ 9027 /* 9028 * Compression type definition 9029 * 0x0: uncompressed 9030 * 0x1: Compressed 9031 * 0x2-0xFFFF: Reserved 9032 */ 9033 u8 reserved[8]; /* Reserved */ 9034 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 9035 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9036 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 9037 9038 /* PCI Data Structure Format */ 9039 typedef struct pcir_data_structure { /* PCI Data Structure */ 9040 u8 signature[4]; /* Signature. The string "PCIR" */ 9041 u8 vendor_id[2]; /* Vendor Identification */ 9042 u8 device_id[2]; /* Device Identification */ 9043 u8 vital_product[2]; /* Pointer to Vital Product Data */ 9044 u8 length[2]; /* PCIR Data Structure Length */ 9045 u8 revision; /* PCIR Data Structure Revision */ 9046 u8 class_code[3]; /* Class Code */ 9047 u8 image_length[2]; /* Image Length. Multiple of 512B */ 9048 u8 code_revision[2]; /* Revision Level of Code/Data */ 9049 u8 code_type; /* Code Type. */ 9050 /* 9051 * PCI Expansion ROM Code Types 9052 * 0x00: Intel IA-32, PC-AT compatible. Legacy 9053 * 0x01: Open Firmware standard for PCI. FCODE 9054 * 0x02: Hewlett-Packard PA RISC. HP reserved 9055 * 0x03: EFI Image. EFI 9056 * 0x04-0xFF: Reserved. 9057 */ 9058 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 9059 u8 reserved[2]; /* Reserved */ 9060 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 9061 9062 /* BOOT constants */ 9063 enum { 9064 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 9065 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 9066 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 9067 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 9068 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 9069 VENDOR_ID = 0x1425, /* Vendor ID */ 9070 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 9071 }; 9072 9073 /* 9074 * modify_device_id - Modifies the device ID of the Boot BIOS image 9075 * @adatper: the device ID to write. 9076 * @boot_data: the boot image to modify. 9077 * 9078 * Write the supplied device ID to the boot BIOS image. 9079 */ 9080 static void modify_device_id(int device_id, u8 *boot_data) 9081 { 9082 legacy_pci_exp_rom_header_t *header; 9083 pcir_data_t *pcir_header; 9084 u32 cur_header = 0; 9085 9086 /* 9087 * Loop through all chained images and change the device ID's 9088 */ 9089 while (1) { 9090 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 9091 pcir_header = (pcir_data_t *) &boot_data[cur_header + 9092 le16_to_cpu(*(u16*)header->pcir_offset)]; 9093 9094 /* 9095 * Only modify the Device ID if code type is Legacy or HP. 9096 * 0x00: Okay to modify 9097 * 0x01: FCODE. Do not be modify 9098 * 0x03: Okay to modify 9099 * 0x04-0xFF: Do not modify 9100 */ 9101 if (pcir_header->code_type == 0x00) { 9102 u8 csum = 0; 9103 int i; 9104 9105 /* 9106 * Modify Device ID to match current adatper 9107 */ 9108 *(u16*) pcir_header->device_id = device_id; 9109 9110 /* 9111 * Set checksum temporarily to 0. 9112 * We will recalculate it later. 9113 */ 9114 header->cksum = 0x0; 9115 9116 /* 9117 * Calculate and update checksum 9118 */ 9119 for (i = 0; i < (header->size512 * 512); i++) 9120 csum += (u8)boot_data[cur_header + i]; 9121 9122 /* 9123 * Invert summed value to create the checksum 9124 * Writing new checksum value directly to the boot data 9125 */ 9126 boot_data[cur_header + 7] = -csum; 9127 9128 } else if (pcir_header->code_type == 0x03) { 9129 9130 /* 9131 * Modify Device ID to match current adatper 9132 */ 9133 *(u16*) pcir_header->device_id = device_id; 9134 9135 } 9136 9137 9138 /* 9139 * Check indicator element to identify if this is the last 9140 * image in the ROM. 9141 */ 9142 if (pcir_header->indicator & 0x80) 9143 break; 9144 9145 /* 9146 * Move header pointer up to the next image in the ROM. 9147 */ 9148 cur_header += header->size512 * 512; 9149 } 9150 } 9151 9152 /* 9153 * t4_load_boot - download boot flash 9154 * @adapter: the adapter 9155 * @boot_data: the boot image to write 9156 * @boot_addr: offset in flash to write boot_data 9157 * @size: image size 9158 * 9159 * Write the supplied boot image to the card's serial flash. 9160 * The boot image has the following sections: a 28-byte header and the 9161 * boot image. 9162 */ 9163 int t4_load_boot(struct adapter *adap, u8 *boot_data, 9164 unsigned int boot_addr, unsigned int size) 9165 { 9166 pci_exp_rom_header_t *header; 9167 int pcir_offset ; 9168 pcir_data_t *pcir_header; 9169 int ret, addr; 9170 uint16_t device_id; 9171 unsigned int i; 9172 unsigned int boot_sector = (boot_addr * 1024 ); 9173 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9174 9175 /* 9176 * Make sure the boot image does not encroach on the firmware region 9177 */ 9178 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 9179 CH_ERR(adap, "boot image encroaching on firmware region\n"); 9180 return -EFBIG; 9181 } 9182 9183 /* 9184 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 9185 * and Boot configuration data sections. These 3 boot sections span 9186 * sectors 0 to 7 in flash and live right before the FW image location. 9187 */ 9188 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 9189 sf_sec_size); 9190 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 9191 (boot_sector >> 16) + i - 1); 9192 9193 /* 9194 * If size == 0 then we're simply erasing the FLASH sectors associated 9195 * with the on-adapter option ROM file 9196 */ 9197 if (ret || (size == 0)) 9198 goto out; 9199 9200 /* Get boot header */ 9201 header = (pci_exp_rom_header_t *)boot_data; 9202 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 9203 /* PCIR Data Structure */ 9204 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 9205 9206 /* 9207 * Perform some primitive sanity testing to avoid accidentally 9208 * writing garbage over the boot sectors. We ought to check for 9209 * more but it's not worth it for now ... 9210 */ 9211 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 9212 CH_ERR(adap, "boot image too small/large\n"); 9213 return -EFBIG; 9214 } 9215 9216 #ifndef CHELSIO_T4_DIAGS 9217 /* 9218 * Check BOOT ROM header signature 9219 */ 9220 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 9221 CH_ERR(adap, "Boot image missing signature\n"); 9222 return -EINVAL; 9223 } 9224 9225 /* 9226 * Check PCI header signature 9227 */ 9228 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 9229 CH_ERR(adap, "PCI header missing signature\n"); 9230 return -EINVAL; 9231 } 9232 9233 /* 9234 * Check Vendor ID matches Chelsio ID 9235 */ 9236 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 9237 CH_ERR(adap, "Vendor ID missing signature\n"); 9238 return -EINVAL; 9239 } 9240 #endif 9241 9242 /* 9243 * Retrieve adapter's device ID 9244 */ 9245 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 9246 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 9247 device_id = device_id & 0xf0ff; 9248 9249 /* 9250 * Check PCIE Device ID 9251 */ 9252 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 9253 /* 9254 * Change the device ID in the Boot BIOS image to match 9255 * the Device ID of the current adapter. 9256 */ 9257 modify_device_id(device_id, boot_data); 9258 } 9259 9260 /* 9261 * Skip over the first SF_PAGE_SIZE worth of data and write it after 9262 * we finish copying the rest of the boot image. This will ensure 9263 * that the BIOS boot header will only be written if the boot image 9264 * was written in full. 9265 */ 9266 addr = boot_sector; 9267 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 9268 addr += SF_PAGE_SIZE; 9269 boot_data += SF_PAGE_SIZE; 9270 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 9271 if (ret) 9272 goto out; 9273 } 9274 9275 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 9276 (const u8 *)header, 0); 9277 9278 out: 9279 if (ret) 9280 CH_ERR(adap, "boot image download failed, error %d\n", ret); 9281 return ret; 9282 } 9283 9284 /* 9285 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 9286 * @adapter: the adapter 9287 * 9288 * Return the address within the flash where the OptionROM Configuration 9289 * is stored, or an error if the device FLASH is too small to contain 9290 * a OptionROM Configuration. 9291 */ 9292 static int t4_flash_bootcfg_addr(struct adapter *adapter) 9293 { 9294 /* 9295 * If the device FLASH isn't large enough to hold a Firmware 9296 * Configuration File, return an error. 9297 */ 9298 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 9299 return -ENOSPC; 9300 9301 return FLASH_BOOTCFG_START; 9302 } 9303 9304 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 9305 { 9306 int ret, i, n, cfg_addr; 9307 unsigned int addr; 9308 unsigned int flash_cfg_start_sec; 9309 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9310 9311 cfg_addr = t4_flash_bootcfg_addr(adap); 9312 if (cfg_addr < 0) 9313 return cfg_addr; 9314 9315 addr = cfg_addr; 9316 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9317 9318 if (size > FLASH_BOOTCFG_MAX_SIZE) { 9319 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 9320 FLASH_BOOTCFG_MAX_SIZE); 9321 return -EFBIG; 9322 } 9323 9324 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 9325 sf_sec_size); 9326 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9327 flash_cfg_start_sec + i - 1); 9328 9329 /* 9330 * If size == 0 then we're simply erasing the FLASH sectors associated 9331 * with the on-adapter OptionROM Configuration File. 9332 */ 9333 if (ret || size == 0) 9334 goto out; 9335 9336 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9337 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9338 if ( (size - i) < SF_PAGE_SIZE) 9339 n = size - i; 9340 else 9341 n = SF_PAGE_SIZE; 9342 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 9343 if (ret) 9344 goto out; 9345 9346 addr += SF_PAGE_SIZE; 9347 cfg_data += SF_PAGE_SIZE; 9348 } 9349 9350 out: 9351 if (ret) 9352 CH_ERR(adap, "boot config data %s failed %d\n", 9353 (size == 0 ? "clear" : "download"), ret); 9354 return ret; 9355 } 9356 9357 /** 9358 * t4_set_filter_mode - configure the optional components of filter tuples 9359 * @adap: the adapter 9360 * @mode_map: a bitmap selcting which optional filter components to enable 9361 * @sleep_ok: if true we may sleep while awaiting command completion 9362 * 9363 * Sets the filter mode by selecting the optional components to enable 9364 * in filter tuples. Returns 0 on success and a negative error if the 9365 * requested mode needs more bits than are available for optional 9366 * components. 9367 */ 9368 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 9369 bool sleep_ok) 9370 { 9371 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 9372 9373 int i, nbits = 0; 9374 9375 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 9376 if (mode_map & (1 << i)) 9377 nbits += width[i]; 9378 if (nbits > FILTER_OPT_LEN) 9379 return -EINVAL; 9380 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok); 9381 read_filter_mode_and_ingress_config(adap, sleep_ok); 9382 9383 return 0; 9384 } 9385 9386 /** 9387 * t4_clr_port_stats - clear port statistics 9388 * @adap: the adapter 9389 * @idx: the port index 9390 * 9391 * Clear HW statistics for the given port. 9392 */ 9393 void t4_clr_port_stats(struct adapter *adap, int idx) 9394 { 9395 unsigned int i; 9396 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 9397 u32 port_base_addr; 9398 9399 if (is_t4(adap)) 9400 port_base_addr = PORT_BASE(idx); 9401 else 9402 port_base_addr = T5_PORT_BASE(idx); 9403 9404 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 9405 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 9406 t4_write_reg(adap, port_base_addr + i, 0); 9407 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 9408 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 9409 t4_write_reg(adap, port_base_addr + i, 0); 9410 for (i = 0; i < 4; i++) 9411 if (bgmap & (1 << i)) { 9412 t4_write_reg(adap, 9413 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 9414 t4_write_reg(adap, 9415 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 9416 } 9417 } 9418 9419 /** 9420 * t4_i2c_rd - read I2C data from adapter 9421 * @adap: the adapter 9422 * @port: Port number if per-port device; <0 if not 9423 * @devid: per-port device ID or absolute device ID 9424 * @offset: byte offset into device I2C space 9425 * @len: byte length of I2C space data 9426 * @buf: buffer in which to return I2C data 9427 * 9428 * Reads the I2C data from the indicated device and location. 9429 */ 9430 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 9431 int port, unsigned int devid, 9432 unsigned int offset, unsigned int len, 9433 u8 *buf) 9434 { 9435 u32 ldst_addrspace; 9436 struct fw_ldst_cmd ldst; 9437 int ret; 9438 9439 if (port >= 4 || 9440 devid >= 256 || 9441 offset >= 256 || 9442 len > sizeof ldst.u.i2c.data) 9443 return -EINVAL; 9444 9445 memset(&ldst, 0, sizeof ldst); 9446 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9447 ldst.op_to_addrspace = 9448 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9449 F_FW_CMD_REQUEST | 9450 F_FW_CMD_READ | 9451 ldst_addrspace); 9452 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9453 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9454 ldst.u.i2c.did = devid; 9455 ldst.u.i2c.boffset = offset; 9456 ldst.u.i2c.blen = len; 9457 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9458 if (!ret) 9459 memcpy(buf, ldst.u.i2c.data, len); 9460 return ret; 9461 } 9462 9463 /** 9464 * t4_i2c_wr - write I2C data to adapter 9465 * @adap: the adapter 9466 * @port: Port number if per-port device; <0 if not 9467 * @devid: per-port device ID or absolute device ID 9468 * @offset: byte offset into device I2C space 9469 * @len: byte length of I2C space data 9470 * @buf: buffer containing new I2C data 9471 * 9472 * Write the I2C data to the indicated device and location. 9473 */ 9474 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 9475 int port, unsigned int devid, 9476 unsigned int offset, unsigned int len, 9477 u8 *buf) 9478 { 9479 u32 ldst_addrspace; 9480 struct fw_ldst_cmd ldst; 9481 9482 if (port >= 4 || 9483 devid >= 256 || 9484 offset >= 256 || 9485 len > sizeof ldst.u.i2c.data) 9486 return -EINVAL; 9487 9488 memset(&ldst, 0, sizeof ldst); 9489 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9490 ldst.op_to_addrspace = 9491 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9492 F_FW_CMD_REQUEST | 9493 F_FW_CMD_WRITE | 9494 ldst_addrspace); 9495 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9496 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9497 ldst.u.i2c.did = devid; 9498 ldst.u.i2c.boffset = offset; 9499 ldst.u.i2c.blen = len; 9500 memcpy(ldst.u.i2c.data, buf, len); 9501 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9502 } 9503 9504 /** 9505 * t4_sge_ctxt_rd - read an SGE context through FW 9506 * @adap: the adapter 9507 * @mbox: mailbox to use for the FW command 9508 * @cid: the context id 9509 * @ctype: the context type 9510 * @data: where to store the context data 9511 * 9512 * Issues a FW command through the given mailbox to read an SGE context. 9513 */ 9514 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 9515 enum ctxt_type ctype, u32 *data) 9516 { 9517 int ret; 9518 struct fw_ldst_cmd c; 9519 9520 if (ctype == CTXT_EGRESS) 9521 ret = FW_LDST_ADDRSPC_SGE_EGRC; 9522 else if (ctype == CTXT_INGRESS) 9523 ret = FW_LDST_ADDRSPC_SGE_INGC; 9524 else if (ctype == CTXT_FLM) 9525 ret = FW_LDST_ADDRSPC_SGE_FLMC; 9526 else 9527 ret = FW_LDST_ADDRSPC_SGE_CONMC; 9528 9529 memset(&c, 0, sizeof(c)); 9530 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9531 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9532 V_FW_LDST_CMD_ADDRSPACE(ret)); 9533 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 9534 c.u.idctxt.physid = cpu_to_be32(cid); 9535 9536 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 9537 if (ret == 0) { 9538 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 9539 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 9540 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 9541 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 9542 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 9543 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 9544 } 9545 return ret; 9546 } 9547 9548 /** 9549 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 9550 * @adap: the adapter 9551 * @cid: the context id 9552 * @ctype: the context type 9553 * @data: where to store the context data 9554 * 9555 * Reads an SGE context directly, bypassing FW. This is only for 9556 * debugging when FW is unavailable. 9557 */ 9558 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 9559 u32 *data) 9560 { 9561 int i, ret; 9562 9563 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 9564 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 9565 if (!ret) 9566 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 9567 *data++ = t4_read_reg(adap, i); 9568 return ret; 9569 } 9570 9571 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 9572 int sleep_ok) 9573 { 9574 struct fw_sched_cmd cmd; 9575 9576 memset(&cmd, 0, sizeof(cmd)); 9577 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9578 F_FW_CMD_REQUEST | 9579 F_FW_CMD_WRITE); 9580 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9581 9582 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 9583 cmd.u.config.type = type; 9584 cmd.u.config.minmaxen = minmaxen; 9585 9586 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9587 NULL, sleep_ok); 9588 } 9589 9590 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 9591 int rateunit, int ratemode, int channel, int cl, 9592 int minrate, int maxrate, int weight, int pktsize, 9593 int sleep_ok) 9594 { 9595 struct fw_sched_cmd cmd; 9596 9597 memset(&cmd, 0, sizeof(cmd)); 9598 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9599 F_FW_CMD_REQUEST | 9600 F_FW_CMD_WRITE); 9601 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9602 9603 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9604 cmd.u.params.type = type; 9605 cmd.u.params.level = level; 9606 cmd.u.params.mode = mode; 9607 cmd.u.params.ch = channel; 9608 cmd.u.params.cl = cl; 9609 cmd.u.params.unit = rateunit; 9610 cmd.u.params.rate = ratemode; 9611 cmd.u.params.min = cpu_to_be32(minrate); 9612 cmd.u.params.max = cpu_to_be32(maxrate); 9613 cmd.u.params.weight = cpu_to_be16(weight); 9614 cmd.u.params.pktsize = cpu_to_be16(pktsize); 9615 9616 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9617 NULL, sleep_ok); 9618 } 9619 9620 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 9621 unsigned int maxrate, int sleep_ok) 9622 { 9623 struct fw_sched_cmd cmd; 9624 9625 memset(&cmd, 0, sizeof(cmd)); 9626 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9627 F_FW_CMD_REQUEST | 9628 F_FW_CMD_WRITE); 9629 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9630 9631 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9632 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 9633 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 9634 cmd.u.params.ch = channel; 9635 cmd.u.params.rate = ratemode; /* REL or ABS */ 9636 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 9637 9638 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9639 NULL, sleep_ok); 9640 } 9641 9642 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 9643 int weight, int sleep_ok) 9644 { 9645 struct fw_sched_cmd cmd; 9646 9647 if (weight < 0 || weight > 100) 9648 return -EINVAL; 9649 9650 memset(&cmd, 0, sizeof(cmd)); 9651 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9652 F_FW_CMD_REQUEST | 9653 F_FW_CMD_WRITE); 9654 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9655 9656 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9657 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 9658 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 9659 cmd.u.params.ch = channel; 9660 cmd.u.params.cl = cl; 9661 cmd.u.params.weight = cpu_to_be16(weight); 9662 9663 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9664 NULL, sleep_ok); 9665 } 9666 9667 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 9668 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 9669 { 9670 struct fw_sched_cmd cmd; 9671 9672 memset(&cmd, 0, sizeof(cmd)); 9673 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9674 F_FW_CMD_REQUEST | 9675 F_FW_CMD_WRITE); 9676 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9677 9678 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9679 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 9680 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 9681 cmd.u.params.mode = mode; 9682 cmd.u.params.ch = channel; 9683 cmd.u.params.cl = cl; 9684 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 9685 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 9686 cmd.u.params.max = cpu_to_be32(maxrate); 9687 cmd.u.params.pktsize = cpu_to_be16(pktsize); 9688 9689 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9690 NULL, sleep_ok); 9691 } 9692 9693 /* 9694 * t4_config_watchdog - configure (enable/disable) a watchdog timer 9695 * @adapter: the adapter 9696 * @mbox: mailbox to use for the FW command 9697 * @pf: the PF owning the queue 9698 * @vf: the VF owning the queue 9699 * @timeout: watchdog timeout in ms 9700 * @action: watchdog timer / action 9701 * 9702 * There are separate watchdog timers for each possible watchdog 9703 * action. Configure one of the watchdog timers by setting a non-zero 9704 * timeout. Disable a watchdog timer by using a timeout of zero. 9705 */ 9706 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 9707 unsigned int pf, unsigned int vf, 9708 unsigned int timeout, unsigned int action) 9709 { 9710 struct fw_watchdog_cmd wdog; 9711 unsigned int ticks; 9712 9713 /* 9714 * The watchdog command expects a timeout in units of 10ms so we need 9715 * to convert it here (via rounding) and force a minimum of one 10ms 9716 * "tick" if the timeout is non-zero but the conversion results in 0 9717 * ticks. 9718 */ 9719 ticks = (timeout + 5)/10; 9720 if (timeout && !ticks) 9721 ticks = 1; 9722 9723 memset(&wdog, 0, sizeof wdog); 9724 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 9725 F_FW_CMD_REQUEST | 9726 F_FW_CMD_WRITE | 9727 V_FW_PARAMS_CMD_PFN(pf) | 9728 V_FW_PARAMS_CMD_VFN(vf)); 9729 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 9730 wdog.timeout = cpu_to_be32(ticks); 9731 wdog.action = cpu_to_be32(action); 9732 9733 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 9734 } 9735 9736 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 9737 { 9738 struct fw_devlog_cmd devlog_cmd; 9739 int ret; 9740 9741 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 9742 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9743 F_FW_CMD_REQUEST | F_FW_CMD_READ); 9744 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9745 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 9746 sizeof(devlog_cmd), &devlog_cmd); 9747 if (ret) 9748 return ret; 9749 9750 *level = devlog_cmd.level; 9751 return 0; 9752 } 9753 9754 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 9755 { 9756 struct fw_devlog_cmd devlog_cmd; 9757 9758 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 9759 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 9760 F_FW_CMD_REQUEST | 9761 F_FW_CMD_WRITE); 9762 devlog_cmd.level = level; 9763 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 9764 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 9765 sizeof(devlog_cmd), &devlog_cmd); 9766 } 9767