1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012, 2016 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include "opt_inet.h" 33 34 #include <sys/param.h> 35 #include <sys/eventhandler.h> 36 37 #include "common.h" 38 #include "t4_regs.h" 39 #include "t4_regs_values.h" 40 #include "firmware/t4fw_interface.h" 41 42 #undef msleep 43 #define msleep(x) do { \ 44 if (cold) \ 45 DELAY((x) * 1000); \ 46 else \ 47 pause("t4hw", (x) * hz / 1000); \ 48 } while (0) 49 50 /** 51 * t4_wait_op_done_val - wait until an operation is completed 52 * @adapter: the adapter performing the operation 53 * @reg: the register to check for completion 54 * @mask: a single-bit field within @reg that indicates completion 55 * @polarity: the value of the field when the operation is completed 56 * @attempts: number of check iterations 57 * @delay: delay in usecs between iterations 58 * @valp: where to store the value of the register at completion time 59 * 60 * Wait until an operation is completed by checking a bit in a register 61 * up to @attempts times. If @valp is not NULL the value of the register 62 * at the time it indicated completion is stored there. Returns 0 if the 63 * operation completes and -EAGAIN otherwise. 64 */ 65 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 66 int polarity, int attempts, int delay, u32 *valp) 67 { 68 while (1) { 69 u32 val = t4_read_reg(adapter, reg); 70 71 if (!!(val & mask) == polarity) { 72 if (valp) 73 *valp = val; 74 return 0; 75 } 76 if (--attempts == 0) 77 return -EAGAIN; 78 if (delay) 79 udelay(delay); 80 } 81 } 82 83 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask, 84 int polarity, int attempts, int delay) 85 { 86 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts, 87 delay, NULL); 88 } 89 90 /** 91 * t4_set_reg_field - set a register field to a value 92 * @adapter: the adapter to program 93 * @addr: the register address 94 * @mask: specifies the portion of the register to modify 95 * @val: the new value for the register field 96 * 97 * Sets a register field specified by the supplied mask to the 98 * given value. 99 */ 100 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask, 101 u32 val) 102 { 103 u32 v = t4_read_reg(adapter, addr) & ~mask; 104 105 t4_write_reg(adapter, addr, v | val); 106 (void) t4_read_reg(adapter, addr); /* flush */ 107 } 108 109 /** 110 * t4_read_indirect - read indirectly addressed registers 111 * @adap: the adapter 112 * @addr_reg: register holding the indirect address 113 * @data_reg: register holding the value of the indirect register 114 * @vals: where the read register values are stored 115 * @nregs: how many indirect registers to read 116 * @start_idx: index of first indirect register to read 117 * 118 * Reads registers that are accessed indirectly through an address/data 119 * register pair. 120 */ 121 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 122 unsigned int data_reg, u32 *vals, 123 unsigned int nregs, unsigned int start_idx) 124 { 125 while (nregs--) { 126 t4_write_reg(adap, addr_reg, start_idx); 127 *vals++ = t4_read_reg(adap, data_reg); 128 start_idx++; 129 } 130 } 131 132 /** 133 * t4_write_indirect - write indirectly addressed registers 134 * @adap: the adapter 135 * @addr_reg: register holding the indirect addresses 136 * @data_reg: register holding the value for the indirect registers 137 * @vals: values to write 138 * @nregs: how many indirect registers to write 139 * @start_idx: address of first indirect register to write 140 * 141 * Writes a sequential block of registers that are accessed indirectly 142 * through an address/data register pair. 143 */ 144 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 145 unsigned int data_reg, const u32 *vals, 146 unsigned int nregs, unsigned int start_idx) 147 { 148 while (nregs--) { 149 t4_write_reg(adap, addr_reg, start_idx++); 150 t4_write_reg(adap, data_reg, *vals++); 151 } 152 } 153 154 /* 155 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor 156 * mechanism. This guarantees that we get the real value even if we're 157 * operating within a Virtual Machine and the Hypervisor is trapping our 158 * Configuration Space accesses. 159 * 160 * N.B. This routine should only be used as a last resort: the firmware uses 161 * the backdoor registers on a regular basis and we can end up 162 * conflicting with it's uses! 163 */ 164 u32 t4_hw_pci_read_cfg4(adapter_t *adap, int reg) 165 { 166 u32 req = V_FUNCTION(adap->pf) | V_REGISTER(reg); 167 u32 val; 168 169 if (chip_id(adap) <= CHELSIO_T5) 170 req |= F_ENABLE; 171 else 172 req |= F_T6_ENABLE; 173 174 if (is_t4(adap)) 175 req |= F_LOCALCFG; 176 177 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, req); 178 val = t4_read_reg(adap, A_PCIE_CFG_SPACE_DATA); 179 180 /* 181 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a 182 * Configuration Space read. (None of the other fields matter when 183 * F_ENABLE is 0 so a simple register write is easier than a 184 * read-modify-write via t4_set_reg_field().) 185 */ 186 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); 187 188 return val; 189 } 190 191 /* 192 * t4_report_fw_error - report firmware error 193 * @adap: the adapter 194 * 195 * The adapter firmware can indicate error conditions to the host. 196 * If the firmware has indicated an error, print out the reason for 197 * the firmware error. 198 */ 199 static void t4_report_fw_error(struct adapter *adap) 200 { 201 static const char *const reason[] = { 202 "Crash", /* PCIE_FW_EVAL_CRASH */ 203 "During Device Preparation", /* PCIE_FW_EVAL_PREP */ 204 "During Device Configuration", /* PCIE_FW_EVAL_CONF */ 205 "During Device Initialization", /* PCIE_FW_EVAL_INIT */ 206 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */ 207 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */ 208 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */ 209 "Reserved", /* reserved */ 210 }; 211 u32 pcie_fw; 212 213 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 214 if (pcie_fw & F_PCIE_FW_ERR) 215 CH_ERR(adap, "Firmware reports adapter error: %s\n", 216 reason[G_PCIE_FW_EVAL(pcie_fw)]); 217 } 218 219 /* 220 * Get the reply to a mailbox command and store it in @rpl in big-endian order. 221 */ 222 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, 223 u32 mbox_addr) 224 { 225 for ( ; nflit; nflit--, mbox_addr += 8) 226 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); 227 } 228 229 /* 230 * Handle a FW assertion reported in a mailbox. 231 */ 232 static void fw_asrt(struct adapter *adap, struct fw_debug_cmd *asrt) 233 { 234 CH_ALERT(adap, 235 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n", 236 asrt->u.assert.filename_0_7, 237 be32_to_cpu(asrt->u.assert.line), 238 be32_to_cpu(asrt->u.assert.x), 239 be32_to_cpu(asrt->u.assert.y)); 240 } 241 242 struct port_tx_state { 243 uint64_t rx_pause; 244 uint64_t tx_frames; 245 }; 246 247 static void 248 read_tx_state_one(struct adapter *sc, int i, struct port_tx_state *tx_state) 249 { 250 uint32_t rx_pause_reg, tx_frames_reg; 251 252 if (is_t4(sc)) { 253 tx_frames_reg = PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 254 rx_pause_reg = PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 255 } else { 256 tx_frames_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_TX_PORT_FRAMES_L); 257 rx_pause_reg = T5_PORT_REG(i, A_MPS_PORT_STAT_RX_PORT_PAUSE_L); 258 } 259 260 tx_state->rx_pause = t4_read_reg64(sc, rx_pause_reg); 261 tx_state->tx_frames = t4_read_reg64(sc, tx_frames_reg); 262 } 263 264 static void 265 read_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 266 { 267 int i; 268 269 for_each_port(sc, i) 270 read_tx_state_one(sc, i, &tx_state[i]); 271 } 272 273 static void 274 check_tx_state(struct adapter *sc, struct port_tx_state *tx_state) 275 { 276 uint32_t port_ctl_reg; 277 uint64_t tx_frames, rx_pause; 278 int i; 279 280 for_each_port(sc, i) { 281 rx_pause = tx_state[i].rx_pause; 282 tx_frames = tx_state[i].tx_frames; 283 read_tx_state_one(sc, i, &tx_state[i]); /* update */ 284 285 if (is_t4(sc)) 286 port_ctl_reg = PORT_REG(i, A_MPS_PORT_CTL); 287 else 288 port_ctl_reg = T5_PORT_REG(i, A_MPS_PORT_CTL); 289 if (t4_read_reg(sc, port_ctl_reg) & F_PORTTXEN && 290 rx_pause != tx_state[i].rx_pause && 291 tx_frames == tx_state[i].tx_frames) { 292 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); 293 mdelay(1); 294 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, F_PORTTXEN); 295 } 296 } 297 } 298 299 #define X_CIM_PF_NOACCESS 0xeeeeeeee 300 /** 301 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox 302 * @adap: the adapter 303 * @mbox: index of the mailbox to use 304 * @cmd: the command to write 305 * @size: command length in bytes 306 * @rpl: where to optionally store the reply 307 * @sleep_ok: if true we may sleep while awaiting command completion 308 * @timeout: time to wait for command to finish before timing out 309 * (negative implies @sleep_ok=false) 310 * 311 * Sends the given command to FW through the selected mailbox and waits 312 * for the FW to execute the command. If @rpl is not %NULL it is used to 313 * store the FW's reply to the command. The command and its optional 314 * reply are of the same length. Some FW commands like RESET and 315 * INITIALIZE can take a considerable amount of time to execute. 316 * @sleep_ok determines whether we may sleep while awaiting the response. 317 * If sleeping is allowed we use progressive backoff otherwise we spin. 318 * Note that passing in a negative @timeout is an alternate mechanism 319 * for specifying @sleep_ok=false. This is useful when a higher level 320 * interface allows for specification of @timeout but not @sleep_ok ... 321 * 322 * The return value is 0 on success or a negative errno on failure. A 323 * failure can happen either because we are not able to execute the 324 * command or FW executes it but signals an error. In the latter case 325 * the return value is the error code indicated by FW (negated). 326 */ 327 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 328 int size, void *rpl, bool sleep_ok, int timeout) 329 { 330 /* 331 * We delay in small increments at first in an effort to maintain 332 * responsiveness for simple, fast executing commands but then back 333 * off to larger delays to a maximum retry delay. 334 */ 335 static const int delay[] = { 336 1, 1, 3, 5, 10, 10, 20, 50, 100 337 }; 338 u32 v; 339 u64 res; 340 int i, ms, delay_idx, ret, next_tx_check; 341 const __be64 *p = cmd; 342 u32 data_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_DATA); 343 u32 ctl_reg = PF_REG(mbox, A_CIM_PF_MAILBOX_CTRL); 344 u32 ctl; 345 __be64 cmd_rpl[MBOX_LEN/8]; 346 u32 pcie_fw; 347 struct port_tx_state tx_state[MAX_NPORTS]; 348 349 if (adap->flags & CHK_MBOX_ACCESS) 350 ASSERT_SYNCHRONIZED_OP(adap); 351 352 if ((size & 15) || size > MBOX_LEN) 353 return -EINVAL; 354 355 if (adap->flags & IS_VF) { 356 if (is_t6(adap)) 357 data_reg = FW_T6VF_MBDATA_BASE_ADDR; 358 else 359 data_reg = FW_T4VF_MBDATA_BASE_ADDR; 360 ctl_reg = VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL); 361 } 362 363 /* 364 * If we have a negative timeout, that implies that we can't sleep. 365 */ 366 if (timeout < 0) { 367 sleep_ok = false; 368 timeout = -timeout; 369 } 370 371 /* 372 * Attempt to gain access to the mailbox. 373 */ 374 for (i = 0; i < 4; i++) { 375 ctl = t4_read_reg(adap, ctl_reg); 376 v = G_MBOWNER(ctl); 377 if (v != X_MBOWNER_NONE) 378 break; 379 } 380 381 /* 382 * If we were unable to gain access, dequeue ourselves from the 383 * mailbox atomic access list and report the error to our caller. 384 */ 385 if (v != X_MBOWNER_PL) { 386 t4_report_fw_error(adap); 387 ret = (v == X_MBOWNER_FW) ? -EBUSY : -ETIMEDOUT; 388 return ret; 389 } 390 391 /* 392 * If we gain ownership of the mailbox and there's a "valid" message 393 * in it, this is likely an asynchronous error message from the 394 * firmware. So we'll report that and then proceed on with attempting 395 * to issue our own command ... which may well fail if the error 396 * presaged the firmware crashing ... 397 */ 398 if (ctl & F_MBMSGVALID) { 399 CH_ERR(adap, "found VALID command in mbox %u: %016llx %016llx " 400 "%016llx %016llx %016llx %016llx %016llx %016llx\n", 401 mbox, (unsigned long long)t4_read_reg64(adap, data_reg), 402 (unsigned long long)t4_read_reg64(adap, data_reg + 8), 403 (unsigned long long)t4_read_reg64(adap, data_reg + 16), 404 (unsigned long long)t4_read_reg64(adap, data_reg + 24), 405 (unsigned long long)t4_read_reg64(adap, data_reg + 32), 406 (unsigned long long)t4_read_reg64(adap, data_reg + 40), 407 (unsigned long long)t4_read_reg64(adap, data_reg + 48), 408 (unsigned long long)t4_read_reg64(adap, data_reg + 56)); 409 } 410 411 /* 412 * Copy in the new mailbox command and send it on its way ... 413 */ 414 for (i = 0; i < size; i += 8, p++) 415 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p)); 416 417 if (adap->flags & IS_VF) { 418 /* 419 * For the VFs, the Mailbox Data "registers" are 420 * actually backed by T4's "MA" interface rather than 421 * PL Registers (as is the case for the PFs). Because 422 * these are in different coherency domains, the write 423 * to the VF's PL-register-backed Mailbox Control can 424 * race in front of the writes to the MA-backed VF 425 * Mailbox Data "registers". So we need to do a 426 * read-back on at least one byte of the VF Mailbox 427 * Data registers before doing the write to the VF 428 * Mailbox Control register. 429 */ 430 t4_read_reg(adap, data_reg); 431 } 432 433 CH_DUMP_MBOX(adap, mbox, data_reg); 434 435 t4_write_reg(adap, ctl_reg, F_MBMSGVALID | V_MBOWNER(X_MBOWNER_FW)); 436 read_tx_state(adap, &tx_state[0]); /* also flushes the write_reg */ 437 next_tx_check = 1000; 438 delay_idx = 0; 439 ms = delay[0]; 440 441 /* 442 * Loop waiting for the reply; bail out if we time out or the firmware 443 * reports an error. 444 */ 445 pcie_fw = 0; 446 for (i = 0; i < timeout; i += ms) { 447 if (!(adap->flags & IS_VF)) { 448 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 449 if (pcie_fw & F_PCIE_FW_ERR) 450 break; 451 } 452 453 if (i >= next_tx_check) { 454 check_tx_state(adap, &tx_state[0]); 455 next_tx_check = i + 1000; 456 } 457 458 if (sleep_ok) { 459 ms = delay[delay_idx]; /* last element may repeat */ 460 if (delay_idx < ARRAY_SIZE(delay) - 1) 461 delay_idx++; 462 msleep(ms); 463 } else { 464 mdelay(ms); 465 } 466 467 v = t4_read_reg(adap, ctl_reg); 468 if (v == X_CIM_PF_NOACCESS) 469 continue; 470 if (G_MBOWNER(v) == X_MBOWNER_PL) { 471 if (!(v & F_MBMSGVALID)) { 472 t4_write_reg(adap, ctl_reg, 473 V_MBOWNER(X_MBOWNER_NONE)); 474 continue; 475 } 476 477 /* 478 * Retrieve the command reply and release the mailbox. 479 */ 480 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN/8, data_reg); 481 t4_write_reg(adap, ctl_reg, V_MBOWNER(X_MBOWNER_NONE)); 482 483 CH_DUMP_MBOX(adap, mbox, data_reg); 484 485 res = be64_to_cpu(cmd_rpl[0]); 486 if (G_FW_CMD_OP(res >> 32) == FW_DEBUG_CMD) { 487 fw_asrt(adap, (struct fw_debug_cmd *)cmd_rpl); 488 res = V_FW_CMD_RETVAL(EIO); 489 } else if (rpl) 490 memcpy(rpl, cmd_rpl, size); 491 return -G_FW_CMD_RETVAL((int)res); 492 } 493 } 494 495 /* 496 * We timed out waiting for a reply to our mailbox command. Report 497 * the error and also check to see if the firmware reported any 498 * errors ... 499 */ 500 ret = (pcie_fw & F_PCIE_FW_ERR) ? -ENXIO : -ETIMEDOUT; 501 CH_ERR(adap, "command %#x in mailbox %d timed out\n", 502 *(const u8 *)cmd, mbox); 503 504 /* If DUMP_MBOX is set the mbox has already been dumped */ 505 if ((adap->debug_flags & DF_DUMP_MBOX) == 0) { 506 p = cmd; 507 CH_ERR(adap, "mbox: %016llx %016llx %016llx %016llx " 508 "%016llx %016llx %016llx %016llx\n", 509 (unsigned long long)be64_to_cpu(p[0]), 510 (unsigned long long)be64_to_cpu(p[1]), 511 (unsigned long long)be64_to_cpu(p[2]), 512 (unsigned long long)be64_to_cpu(p[3]), 513 (unsigned long long)be64_to_cpu(p[4]), 514 (unsigned long long)be64_to_cpu(p[5]), 515 (unsigned long long)be64_to_cpu(p[6]), 516 (unsigned long long)be64_to_cpu(p[7])); 517 } 518 519 t4_report_fw_error(adap); 520 t4_fatal_err(adap); 521 return ret; 522 } 523 524 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 525 void *rpl, bool sleep_ok) 526 { 527 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, 528 sleep_ok, FW_CMD_MAX_TIMEOUT); 529 530 } 531 532 static int t4_edc_err_read(struct adapter *adap, int idx) 533 { 534 u32 edc_ecc_err_addr_reg; 535 u32 edc_bist_status_rdata_reg; 536 537 if (is_t4(adap)) { 538 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); 539 return 0; 540 } 541 if (idx != MEM_EDC0 && idx != MEM_EDC1) { 542 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); 543 return 0; 544 } 545 546 edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); 547 edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); 548 549 CH_WARN(adap, 550 "edc%d err addr 0x%x: 0x%x.\n", 551 idx, edc_ecc_err_addr_reg, 552 t4_read_reg(adap, edc_ecc_err_addr_reg)); 553 CH_WARN(adap, 554 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", 555 edc_bist_status_rdata_reg, 556 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), 557 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), 558 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), 559 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), 560 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), 561 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), 562 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), 563 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), 564 (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); 565 566 return 0; 567 } 568 569 /** 570 * t4_mc_read - read from MC through backdoor accesses 571 * @adap: the adapter 572 * @idx: which MC to access 573 * @addr: address of first byte requested 574 * @data: 64 bytes of data containing the requested address 575 * @ecc: where to store the corresponding 64-bit ECC word 576 * 577 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 578 * that covers the requested address @addr. If @parity is not %NULL it 579 * is assigned the 64-bit ECC word for the read data. 580 */ 581 int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 582 { 583 int i; 584 u32 mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 585 u32 mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 586 587 if (is_t4(adap)) { 588 mc_bist_cmd_reg = A_MC_BIST_CMD; 589 mc_bist_cmd_addr_reg = A_MC_BIST_CMD_ADDR; 590 mc_bist_cmd_len_reg = A_MC_BIST_CMD_LEN; 591 mc_bist_status_rdata_reg = A_MC_BIST_STATUS_RDATA; 592 mc_bist_data_pattern_reg = A_MC_BIST_DATA_PATTERN; 593 } else { 594 mc_bist_cmd_reg = MC_REG(A_MC_P_BIST_CMD, idx); 595 mc_bist_cmd_addr_reg = MC_REG(A_MC_P_BIST_CMD_ADDR, idx); 596 mc_bist_cmd_len_reg = MC_REG(A_MC_P_BIST_CMD_LEN, idx); 597 mc_bist_status_rdata_reg = MC_REG(A_MC_P_BIST_STATUS_RDATA, 598 idx); 599 mc_bist_data_pattern_reg = MC_REG(A_MC_P_BIST_DATA_PATTERN, 600 idx); 601 } 602 603 if (t4_read_reg(adap, mc_bist_cmd_reg) & F_START_BIST) 604 return -EBUSY; 605 t4_write_reg(adap, mc_bist_cmd_addr_reg, addr & ~0x3fU); 606 t4_write_reg(adap, mc_bist_cmd_len_reg, 64); 607 t4_write_reg(adap, mc_bist_data_pattern_reg, 0xc); 608 t4_write_reg(adap, mc_bist_cmd_reg, V_BIST_OPCODE(1) | 609 F_START_BIST | V_BIST_CMD_GAP(1)); 610 i = t4_wait_op_done(adap, mc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 611 if (i) 612 return i; 613 614 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata_reg, i) 615 616 for (i = 15; i >= 0; i--) 617 *data++ = ntohl(t4_read_reg(adap, MC_DATA(i))); 618 if (ecc) 619 *ecc = t4_read_reg64(adap, MC_DATA(16)); 620 #undef MC_DATA 621 return 0; 622 } 623 624 /** 625 * t4_edc_read - read from EDC through backdoor accesses 626 * @adap: the adapter 627 * @idx: which EDC to access 628 * @addr: address of first byte requested 629 * @data: 64 bytes of data containing the requested address 630 * @ecc: where to store the corresponding 64-bit ECC word 631 * 632 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 633 * that covers the requested address @addr. If @parity is not %NULL it 634 * is assigned the 64-bit ECC word for the read data. 635 */ 636 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc) 637 { 638 int i; 639 u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 640 u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 641 642 if (is_t4(adap)) { 643 edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx); 644 edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx); 645 edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx); 646 edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN, 647 idx); 648 edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA, 649 idx); 650 } else { 651 /* 652 * These macro are missing in t4_regs.h file. 653 * Added temporarily for testing. 654 */ 655 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 656 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 657 edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx); 658 edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx); 659 edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx); 660 edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN, 661 idx); 662 edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA, 663 idx); 664 #undef EDC_REG_T5 665 #undef EDC_STRIDE_T5 666 } 667 668 if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST) 669 return -EBUSY; 670 t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU); 671 t4_write_reg(adap, edc_bist_cmd_len_reg, 64); 672 t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc); 673 t4_write_reg(adap, edc_bist_cmd_reg, 674 V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST); 675 i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1); 676 if (i) 677 return i; 678 679 #define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) 680 681 for (i = 15; i >= 0; i--) 682 *data++ = ntohl(t4_read_reg(adap, EDC_DATA(i))); 683 if (ecc) 684 *ecc = t4_read_reg64(adap, EDC_DATA(16)); 685 #undef EDC_DATA 686 return 0; 687 } 688 689 /** 690 * t4_mem_read - read EDC 0, EDC 1 or MC into buffer 691 * @adap: the adapter 692 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC 693 * @addr: address within indicated memory type 694 * @len: amount of memory to read 695 * @buf: host memory buffer 696 * 697 * Reads an [almost] arbitrary memory region in the firmware: the 698 * firmware memory address, length and host buffer must be aligned on 699 * 32-bit boudaries. The memory is returned as a raw byte sequence from 700 * the firmware's memory. If this memory contains data structures which 701 * contain multi-byte integers, it's the callers responsibility to 702 * perform appropriate byte order conversions. 703 */ 704 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 len, 705 __be32 *buf) 706 { 707 u32 pos, start, end, offset; 708 int ret; 709 710 /* 711 * Argument sanity checks ... 712 */ 713 if ((addr & 0x3) || (len & 0x3)) 714 return -EINVAL; 715 716 /* 717 * The underlaying EDC/MC read routines read 64 bytes at a time so we 718 * need to round down the start and round up the end. We'll start 719 * copying out of the first line at (addr - start) a word at a time. 720 */ 721 start = rounddown2(addr, 64); 722 end = roundup2(addr + len, 64); 723 offset = (addr - start)/sizeof(__be32); 724 725 for (pos = start; pos < end; pos += 64, offset = 0) { 726 __be32 data[16]; 727 728 /* 729 * Read the chip's memory block and bail if there's an error. 730 */ 731 if ((mtype == MEM_MC) || (mtype == MEM_MC1)) 732 ret = t4_mc_read(adap, mtype - MEM_MC, pos, data, NULL); 733 else 734 ret = t4_edc_read(adap, mtype, pos, data, NULL); 735 if (ret) 736 return ret; 737 738 /* 739 * Copy the data into the caller's memory buffer. 740 */ 741 while (offset < 16 && len > 0) { 742 *buf++ = data[offset++]; 743 len -= sizeof(__be32); 744 } 745 } 746 747 return 0; 748 } 749 750 /* 751 * Return the specified PCI-E Configuration Space register from our Physical 752 * Function. We try first via a Firmware LDST Command (if fw_attach != 0) 753 * since we prefer to let the firmware own all of these registers, but if that 754 * fails we go for it directly ourselves. 755 */ 756 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach) 757 { 758 759 /* 760 * If fw_attach != 0, construct and send the Firmware LDST Command to 761 * retrieve the specified PCI-E Configuration Space register. 762 */ 763 if (drv_fw_attach != 0) { 764 struct fw_ldst_cmd ldst_cmd; 765 int ret; 766 767 memset(&ldst_cmd, 0, sizeof(ldst_cmd)); 768 ldst_cmd.op_to_addrspace = 769 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 770 F_FW_CMD_REQUEST | 771 F_FW_CMD_READ | 772 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE)); 773 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd)); 774 ldst_cmd.u.pcie.select_naccess = V_FW_LDST_CMD_NACCESS(1); 775 ldst_cmd.u.pcie.ctrl_to_fn = 776 (F_FW_LDST_CMD_LC | V_FW_LDST_CMD_FN(adap->pf)); 777 ldst_cmd.u.pcie.r = reg; 778 779 /* 780 * If the LDST Command succeeds, return the result, otherwise 781 * fall through to reading it directly ourselves ... 782 */ 783 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), 784 &ldst_cmd); 785 if (ret == 0) 786 return be32_to_cpu(ldst_cmd.u.pcie.data[0]); 787 788 CH_WARN(adap, "Firmware failed to return " 789 "Configuration Space register %d, err = %d\n", 790 reg, -ret); 791 } 792 793 /* 794 * Read the desired Configuration Space register via the PCI-E 795 * Backdoor mechanism. 796 */ 797 return t4_hw_pci_read_cfg4(adap, reg); 798 } 799 800 /** 801 * t4_get_regs_len - return the size of the chips register set 802 * @adapter: the adapter 803 * 804 * Returns the size of the chip's BAR0 register space. 805 */ 806 unsigned int t4_get_regs_len(struct adapter *adapter) 807 { 808 unsigned int chip_version = chip_id(adapter); 809 810 switch (chip_version) { 811 case CHELSIO_T4: 812 if (adapter->flags & IS_VF) 813 return FW_T4VF_REGMAP_SIZE; 814 return T4_REGMAP_SIZE; 815 816 case CHELSIO_T5: 817 case CHELSIO_T6: 818 if (adapter->flags & IS_VF) 819 return FW_T4VF_REGMAP_SIZE; 820 return T5_REGMAP_SIZE; 821 } 822 823 CH_ERR(adapter, 824 "Unsupported chip version %d\n", chip_version); 825 return 0; 826 } 827 828 /** 829 * t4_get_regs - read chip registers into provided buffer 830 * @adap: the adapter 831 * @buf: register buffer 832 * @buf_size: size (in bytes) of register buffer 833 * 834 * If the provided register buffer isn't large enough for the chip's 835 * full register range, the register dump will be truncated to the 836 * register buffer's size. 837 */ 838 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size) 839 { 840 static const unsigned int t4_reg_ranges[] = { 841 0x1008, 0x1108, 842 0x1180, 0x1184, 843 0x1190, 0x1194, 844 0x11a0, 0x11a4, 845 0x11b0, 0x11b4, 846 0x11fc, 0x123c, 847 0x1300, 0x173c, 848 0x1800, 0x18fc, 849 0x3000, 0x30d8, 850 0x30e0, 0x30e4, 851 0x30ec, 0x5910, 852 0x5920, 0x5924, 853 0x5960, 0x5960, 854 0x5968, 0x5968, 855 0x5970, 0x5970, 856 0x5978, 0x5978, 857 0x5980, 0x5980, 858 0x5988, 0x5988, 859 0x5990, 0x5990, 860 0x5998, 0x5998, 861 0x59a0, 0x59d4, 862 0x5a00, 0x5ae0, 863 0x5ae8, 0x5ae8, 864 0x5af0, 0x5af0, 865 0x5af8, 0x5af8, 866 0x6000, 0x6098, 867 0x6100, 0x6150, 868 0x6200, 0x6208, 869 0x6240, 0x6248, 870 0x6280, 0x62b0, 871 0x62c0, 0x6338, 872 0x6370, 0x638c, 873 0x6400, 0x643c, 874 0x6500, 0x6524, 875 0x6a00, 0x6a04, 876 0x6a14, 0x6a38, 877 0x6a60, 0x6a70, 878 0x6a78, 0x6a78, 879 0x6b00, 0x6b0c, 880 0x6b1c, 0x6b84, 881 0x6bf0, 0x6bf8, 882 0x6c00, 0x6c0c, 883 0x6c1c, 0x6c84, 884 0x6cf0, 0x6cf8, 885 0x6d00, 0x6d0c, 886 0x6d1c, 0x6d84, 887 0x6df0, 0x6df8, 888 0x6e00, 0x6e0c, 889 0x6e1c, 0x6e84, 890 0x6ef0, 0x6ef8, 891 0x6f00, 0x6f0c, 892 0x6f1c, 0x6f84, 893 0x6ff0, 0x6ff8, 894 0x7000, 0x700c, 895 0x701c, 0x7084, 896 0x70f0, 0x70f8, 897 0x7100, 0x710c, 898 0x711c, 0x7184, 899 0x71f0, 0x71f8, 900 0x7200, 0x720c, 901 0x721c, 0x7284, 902 0x72f0, 0x72f8, 903 0x7300, 0x730c, 904 0x731c, 0x7384, 905 0x73f0, 0x73f8, 906 0x7400, 0x7450, 907 0x7500, 0x7530, 908 0x7600, 0x760c, 909 0x7614, 0x761c, 910 0x7680, 0x76cc, 911 0x7700, 0x7798, 912 0x77c0, 0x77fc, 913 0x7900, 0x79fc, 914 0x7b00, 0x7b58, 915 0x7b60, 0x7b84, 916 0x7b8c, 0x7c38, 917 0x7d00, 0x7d38, 918 0x7d40, 0x7d80, 919 0x7d8c, 0x7ddc, 920 0x7de4, 0x7e04, 921 0x7e10, 0x7e1c, 922 0x7e24, 0x7e38, 923 0x7e40, 0x7e44, 924 0x7e4c, 0x7e78, 925 0x7e80, 0x7ea4, 926 0x7eac, 0x7edc, 927 0x7ee8, 0x7efc, 928 0x8dc0, 0x8e04, 929 0x8e10, 0x8e1c, 930 0x8e30, 0x8e78, 931 0x8ea0, 0x8eb8, 932 0x8ec0, 0x8f6c, 933 0x8fc0, 0x9008, 934 0x9010, 0x9058, 935 0x9060, 0x9060, 936 0x9068, 0x9074, 937 0x90fc, 0x90fc, 938 0x9400, 0x9408, 939 0x9410, 0x9458, 940 0x9600, 0x9600, 941 0x9608, 0x9638, 942 0x9640, 0x96bc, 943 0x9800, 0x9808, 944 0x9820, 0x983c, 945 0x9850, 0x9864, 946 0x9c00, 0x9c6c, 947 0x9c80, 0x9cec, 948 0x9d00, 0x9d6c, 949 0x9d80, 0x9dec, 950 0x9e00, 0x9e6c, 951 0x9e80, 0x9eec, 952 0x9f00, 0x9f6c, 953 0x9f80, 0x9fec, 954 0xd004, 0xd004, 955 0xd010, 0xd03c, 956 0xdfc0, 0xdfe0, 957 0xe000, 0xea7c, 958 0xf000, 0x11110, 959 0x11118, 0x11190, 960 0x19040, 0x1906c, 961 0x19078, 0x19080, 962 0x1908c, 0x190e4, 963 0x190f0, 0x190f8, 964 0x19100, 0x19110, 965 0x19120, 0x19124, 966 0x19150, 0x19194, 967 0x1919c, 0x191b0, 968 0x191d0, 0x191e8, 969 0x19238, 0x1924c, 970 0x193f8, 0x1943c, 971 0x1944c, 0x19474, 972 0x19490, 0x194e0, 973 0x194f0, 0x194f8, 974 0x19800, 0x19c08, 975 0x19c10, 0x19c90, 976 0x19ca0, 0x19ce4, 977 0x19cf0, 0x19d40, 978 0x19d50, 0x19d94, 979 0x19da0, 0x19de8, 980 0x19df0, 0x19e40, 981 0x19e50, 0x19e90, 982 0x19ea0, 0x19f4c, 983 0x1a000, 0x1a004, 984 0x1a010, 0x1a06c, 985 0x1a0b0, 0x1a0e4, 986 0x1a0ec, 0x1a0f4, 987 0x1a100, 0x1a108, 988 0x1a114, 0x1a120, 989 0x1a128, 0x1a130, 990 0x1a138, 0x1a138, 991 0x1a190, 0x1a1c4, 992 0x1a1fc, 0x1a1fc, 993 0x1e040, 0x1e04c, 994 0x1e284, 0x1e28c, 995 0x1e2c0, 0x1e2c0, 996 0x1e2e0, 0x1e2e0, 997 0x1e300, 0x1e384, 998 0x1e3c0, 0x1e3c8, 999 0x1e440, 0x1e44c, 1000 0x1e684, 0x1e68c, 1001 0x1e6c0, 0x1e6c0, 1002 0x1e6e0, 0x1e6e0, 1003 0x1e700, 0x1e784, 1004 0x1e7c0, 0x1e7c8, 1005 0x1e840, 0x1e84c, 1006 0x1ea84, 0x1ea8c, 1007 0x1eac0, 0x1eac0, 1008 0x1eae0, 0x1eae0, 1009 0x1eb00, 0x1eb84, 1010 0x1ebc0, 0x1ebc8, 1011 0x1ec40, 0x1ec4c, 1012 0x1ee84, 0x1ee8c, 1013 0x1eec0, 0x1eec0, 1014 0x1eee0, 0x1eee0, 1015 0x1ef00, 0x1ef84, 1016 0x1efc0, 0x1efc8, 1017 0x1f040, 0x1f04c, 1018 0x1f284, 0x1f28c, 1019 0x1f2c0, 0x1f2c0, 1020 0x1f2e0, 0x1f2e0, 1021 0x1f300, 0x1f384, 1022 0x1f3c0, 0x1f3c8, 1023 0x1f440, 0x1f44c, 1024 0x1f684, 0x1f68c, 1025 0x1f6c0, 0x1f6c0, 1026 0x1f6e0, 0x1f6e0, 1027 0x1f700, 0x1f784, 1028 0x1f7c0, 0x1f7c8, 1029 0x1f840, 0x1f84c, 1030 0x1fa84, 0x1fa8c, 1031 0x1fac0, 0x1fac0, 1032 0x1fae0, 0x1fae0, 1033 0x1fb00, 0x1fb84, 1034 0x1fbc0, 0x1fbc8, 1035 0x1fc40, 0x1fc4c, 1036 0x1fe84, 0x1fe8c, 1037 0x1fec0, 0x1fec0, 1038 0x1fee0, 0x1fee0, 1039 0x1ff00, 0x1ff84, 1040 0x1ffc0, 0x1ffc8, 1041 0x20000, 0x2002c, 1042 0x20100, 0x2013c, 1043 0x20190, 0x201a0, 1044 0x201a8, 0x201b8, 1045 0x201c4, 0x201c8, 1046 0x20200, 0x20318, 1047 0x20400, 0x204b4, 1048 0x204c0, 0x20528, 1049 0x20540, 0x20614, 1050 0x21000, 0x21040, 1051 0x2104c, 0x21060, 1052 0x210c0, 0x210ec, 1053 0x21200, 0x21268, 1054 0x21270, 0x21284, 1055 0x212fc, 0x21388, 1056 0x21400, 0x21404, 1057 0x21500, 0x21500, 1058 0x21510, 0x21518, 1059 0x2152c, 0x21530, 1060 0x2153c, 0x2153c, 1061 0x21550, 0x21554, 1062 0x21600, 0x21600, 1063 0x21608, 0x2161c, 1064 0x21624, 0x21628, 1065 0x21630, 0x21634, 1066 0x2163c, 0x2163c, 1067 0x21700, 0x2171c, 1068 0x21780, 0x2178c, 1069 0x21800, 0x21818, 1070 0x21820, 0x21828, 1071 0x21830, 0x21848, 1072 0x21850, 0x21854, 1073 0x21860, 0x21868, 1074 0x21870, 0x21870, 1075 0x21878, 0x21898, 1076 0x218a0, 0x218a8, 1077 0x218b0, 0x218c8, 1078 0x218d0, 0x218d4, 1079 0x218e0, 0x218e8, 1080 0x218f0, 0x218f0, 1081 0x218f8, 0x21a18, 1082 0x21a20, 0x21a28, 1083 0x21a30, 0x21a48, 1084 0x21a50, 0x21a54, 1085 0x21a60, 0x21a68, 1086 0x21a70, 0x21a70, 1087 0x21a78, 0x21a98, 1088 0x21aa0, 0x21aa8, 1089 0x21ab0, 0x21ac8, 1090 0x21ad0, 0x21ad4, 1091 0x21ae0, 0x21ae8, 1092 0x21af0, 0x21af0, 1093 0x21af8, 0x21c18, 1094 0x21c20, 0x21c20, 1095 0x21c28, 0x21c30, 1096 0x21c38, 0x21c38, 1097 0x21c80, 0x21c98, 1098 0x21ca0, 0x21ca8, 1099 0x21cb0, 0x21cc8, 1100 0x21cd0, 0x21cd4, 1101 0x21ce0, 0x21ce8, 1102 0x21cf0, 0x21cf0, 1103 0x21cf8, 0x21d7c, 1104 0x21e00, 0x21e04, 1105 0x22000, 0x2202c, 1106 0x22100, 0x2213c, 1107 0x22190, 0x221a0, 1108 0x221a8, 0x221b8, 1109 0x221c4, 0x221c8, 1110 0x22200, 0x22318, 1111 0x22400, 0x224b4, 1112 0x224c0, 0x22528, 1113 0x22540, 0x22614, 1114 0x23000, 0x23040, 1115 0x2304c, 0x23060, 1116 0x230c0, 0x230ec, 1117 0x23200, 0x23268, 1118 0x23270, 0x23284, 1119 0x232fc, 0x23388, 1120 0x23400, 0x23404, 1121 0x23500, 0x23500, 1122 0x23510, 0x23518, 1123 0x2352c, 0x23530, 1124 0x2353c, 0x2353c, 1125 0x23550, 0x23554, 1126 0x23600, 0x23600, 1127 0x23608, 0x2361c, 1128 0x23624, 0x23628, 1129 0x23630, 0x23634, 1130 0x2363c, 0x2363c, 1131 0x23700, 0x2371c, 1132 0x23780, 0x2378c, 1133 0x23800, 0x23818, 1134 0x23820, 0x23828, 1135 0x23830, 0x23848, 1136 0x23850, 0x23854, 1137 0x23860, 0x23868, 1138 0x23870, 0x23870, 1139 0x23878, 0x23898, 1140 0x238a0, 0x238a8, 1141 0x238b0, 0x238c8, 1142 0x238d0, 0x238d4, 1143 0x238e0, 0x238e8, 1144 0x238f0, 0x238f0, 1145 0x238f8, 0x23a18, 1146 0x23a20, 0x23a28, 1147 0x23a30, 0x23a48, 1148 0x23a50, 0x23a54, 1149 0x23a60, 0x23a68, 1150 0x23a70, 0x23a70, 1151 0x23a78, 0x23a98, 1152 0x23aa0, 0x23aa8, 1153 0x23ab0, 0x23ac8, 1154 0x23ad0, 0x23ad4, 1155 0x23ae0, 0x23ae8, 1156 0x23af0, 0x23af0, 1157 0x23af8, 0x23c18, 1158 0x23c20, 0x23c20, 1159 0x23c28, 0x23c30, 1160 0x23c38, 0x23c38, 1161 0x23c80, 0x23c98, 1162 0x23ca0, 0x23ca8, 1163 0x23cb0, 0x23cc8, 1164 0x23cd0, 0x23cd4, 1165 0x23ce0, 0x23ce8, 1166 0x23cf0, 0x23cf0, 1167 0x23cf8, 0x23d7c, 1168 0x23e00, 0x23e04, 1169 0x24000, 0x2402c, 1170 0x24100, 0x2413c, 1171 0x24190, 0x241a0, 1172 0x241a8, 0x241b8, 1173 0x241c4, 0x241c8, 1174 0x24200, 0x24318, 1175 0x24400, 0x244b4, 1176 0x244c0, 0x24528, 1177 0x24540, 0x24614, 1178 0x25000, 0x25040, 1179 0x2504c, 0x25060, 1180 0x250c0, 0x250ec, 1181 0x25200, 0x25268, 1182 0x25270, 0x25284, 1183 0x252fc, 0x25388, 1184 0x25400, 0x25404, 1185 0x25500, 0x25500, 1186 0x25510, 0x25518, 1187 0x2552c, 0x25530, 1188 0x2553c, 0x2553c, 1189 0x25550, 0x25554, 1190 0x25600, 0x25600, 1191 0x25608, 0x2561c, 1192 0x25624, 0x25628, 1193 0x25630, 0x25634, 1194 0x2563c, 0x2563c, 1195 0x25700, 0x2571c, 1196 0x25780, 0x2578c, 1197 0x25800, 0x25818, 1198 0x25820, 0x25828, 1199 0x25830, 0x25848, 1200 0x25850, 0x25854, 1201 0x25860, 0x25868, 1202 0x25870, 0x25870, 1203 0x25878, 0x25898, 1204 0x258a0, 0x258a8, 1205 0x258b0, 0x258c8, 1206 0x258d0, 0x258d4, 1207 0x258e0, 0x258e8, 1208 0x258f0, 0x258f0, 1209 0x258f8, 0x25a18, 1210 0x25a20, 0x25a28, 1211 0x25a30, 0x25a48, 1212 0x25a50, 0x25a54, 1213 0x25a60, 0x25a68, 1214 0x25a70, 0x25a70, 1215 0x25a78, 0x25a98, 1216 0x25aa0, 0x25aa8, 1217 0x25ab0, 0x25ac8, 1218 0x25ad0, 0x25ad4, 1219 0x25ae0, 0x25ae8, 1220 0x25af0, 0x25af0, 1221 0x25af8, 0x25c18, 1222 0x25c20, 0x25c20, 1223 0x25c28, 0x25c30, 1224 0x25c38, 0x25c38, 1225 0x25c80, 0x25c98, 1226 0x25ca0, 0x25ca8, 1227 0x25cb0, 0x25cc8, 1228 0x25cd0, 0x25cd4, 1229 0x25ce0, 0x25ce8, 1230 0x25cf0, 0x25cf0, 1231 0x25cf8, 0x25d7c, 1232 0x25e00, 0x25e04, 1233 0x26000, 0x2602c, 1234 0x26100, 0x2613c, 1235 0x26190, 0x261a0, 1236 0x261a8, 0x261b8, 1237 0x261c4, 0x261c8, 1238 0x26200, 0x26318, 1239 0x26400, 0x264b4, 1240 0x264c0, 0x26528, 1241 0x26540, 0x26614, 1242 0x27000, 0x27040, 1243 0x2704c, 0x27060, 1244 0x270c0, 0x270ec, 1245 0x27200, 0x27268, 1246 0x27270, 0x27284, 1247 0x272fc, 0x27388, 1248 0x27400, 0x27404, 1249 0x27500, 0x27500, 1250 0x27510, 0x27518, 1251 0x2752c, 0x27530, 1252 0x2753c, 0x2753c, 1253 0x27550, 0x27554, 1254 0x27600, 0x27600, 1255 0x27608, 0x2761c, 1256 0x27624, 0x27628, 1257 0x27630, 0x27634, 1258 0x2763c, 0x2763c, 1259 0x27700, 0x2771c, 1260 0x27780, 0x2778c, 1261 0x27800, 0x27818, 1262 0x27820, 0x27828, 1263 0x27830, 0x27848, 1264 0x27850, 0x27854, 1265 0x27860, 0x27868, 1266 0x27870, 0x27870, 1267 0x27878, 0x27898, 1268 0x278a0, 0x278a8, 1269 0x278b0, 0x278c8, 1270 0x278d0, 0x278d4, 1271 0x278e0, 0x278e8, 1272 0x278f0, 0x278f0, 1273 0x278f8, 0x27a18, 1274 0x27a20, 0x27a28, 1275 0x27a30, 0x27a48, 1276 0x27a50, 0x27a54, 1277 0x27a60, 0x27a68, 1278 0x27a70, 0x27a70, 1279 0x27a78, 0x27a98, 1280 0x27aa0, 0x27aa8, 1281 0x27ab0, 0x27ac8, 1282 0x27ad0, 0x27ad4, 1283 0x27ae0, 0x27ae8, 1284 0x27af0, 0x27af0, 1285 0x27af8, 0x27c18, 1286 0x27c20, 0x27c20, 1287 0x27c28, 0x27c30, 1288 0x27c38, 0x27c38, 1289 0x27c80, 0x27c98, 1290 0x27ca0, 0x27ca8, 1291 0x27cb0, 0x27cc8, 1292 0x27cd0, 0x27cd4, 1293 0x27ce0, 0x27ce8, 1294 0x27cf0, 0x27cf0, 1295 0x27cf8, 0x27d7c, 1296 0x27e00, 0x27e04, 1297 }; 1298 1299 static const unsigned int t4vf_reg_ranges[] = { 1300 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 1301 VF_MPS_REG(A_MPS_VF_CTL), 1302 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 1303 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_WHOAMI), 1304 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 1305 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 1306 FW_T4VF_MBDATA_BASE_ADDR, 1307 FW_T4VF_MBDATA_BASE_ADDR + 1308 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 1309 }; 1310 1311 static const unsigned int t5_reg_ranges[] = { 1312 0x1008, 0x10c0, 1313 0x10cc, 0x10f8, 1314 0x1100, 0x1100, 1315 0x110c, 0x1148, 1316 0x1180, 0x1184, 1317 0x1190, 0x1194, 1318 0x11a0, 0x11a4, 1319 0x11b0, 0x11b4, 1320 0x11fc, 0x123c, 1321 0x1280, 0x173c, 1322 0x1800, 0x18fc, 1323 0x3000, 0x3028, 1324 0x3060, 0x30b0, 1325 0x30b8, 0x30d8, 1326 0x30e0, 0x30fc, 1327 0x3140, 0x357c, 1328 0x35a8, 0x35cc, 1329 0x35ec, 0x35ec, 1330 0x3600, 0x5624, 1331 0x56cc, 0x56ec, 1332 0x56f4, 0x5720, 1333 0x5728, 0x575c, 1334 0x580c, 0x5814, 1335 0x5890, 0x589c, 1336 0x58a4, 0x58ac, 1337 0x58b8, 0x58bc, 1338 0x5940, 0x59c8, 1339 0x59d0, 0x59dc, 1340 0x59fc, 0x5a18, 1341 0x5a60, 0x5a70, 1342 0x5a80, 0x5a9c, 1343 0x5b94, 0x5bfc, 1344 0x6000, 0x6020, 1345 0x6028, 0x6040, 1346 0x6058, 0x609c, 1347 0x60a8, 0x614c, 1348 0x7700, 0x7798, 1349 0x77c0, 0x78fc, 1350 0x7b00, 0x7b58, 1351 0x7b60, 0x7b84, 1352 0x7b8c, 0x7c54, 1353 0x7d00, 0x7d38, 1354 0x7d40, 0x7d80, 1355 0x7d8c, 0x7ddc, 1356 0x7de4, 0x7e04, 1357 0x7e10, 0x7e1c, 1358 0x7e24, 0x7e38, 1359 0x7e40, 0x7e44, 1360 0x7e4c, 0x7e78, 1361 0x7e80, 0x7edc, 1362 0x7ee8, 0x7efc, 1363 0x8dc0, 0x8de0, 1364 0x8df8, 0x8e04, 1365 0x8e10, 0x8e84, 1366 0x8ea0, 0x8f84, 1367 0x8fc0, 0x9058, 1368 0x9060, 0x9060, 1369 0x9068, 0x90f8, 1370 0x9400, 0x9408, 1371 0x9410, 0x9470, 1372 0x9600, 0x9600, 1373 0x9608, 0x9638, 1374 0x9640, 0x96f4, 1375 0x9800, 0x9808, 1376 0x9820, 0x983c, 1377 0x9850, 0x9864, 1378 0x9c00, 0x9c6c, 1379 0x9c80, 0x9cec, 1380 0x9d00, 0x9d6c, 1381 0x9d80, 0x9dec, 1382 0x9e00, 0x9e6c, 1383 0x9e80, 0x9eec, 1384 0x9f00, 0x9f6c, 1385 0x9f80, 0xa020, 1386 0xd004, 0xd004, 1387 0xd010, 0xd03c, 1388 0xdfc0, 0xdfe0, 1389 0xe000, 0x1106c, 1390 0x11074, 0x11088, 1391 0x1109c, 0x1117c, 1392 0x11190, 0x11204, 1393 0x19040, 0x1906c, 1394 0x19078, 0x19080, 1395 0x1908c, 0x190e8, 1396 0x190f0, 0x190f8, 1397 0x19100, 0x19110, 1398 0x19120, 0x19124, 1399 0x19150, 0x19194, 1400 0x1919c, 0x191b0, 1401 0x191d0, 0x191e8, 1402 0x19238, 0x19290, 1403 0x193f8, 0x19428, 1404 0x19430, 0x19444, 1405 0x1944c, 0x1946c, 1406 0x19474, 0x19474, 1407 0x19490, 0x194cc, 1408 0x194f0, 0x194f8, 1409 0x19c00, 0x19c08, 1410 0x19c10, 0x19c60, 1411 0x19c94, 0x19ce4, 1412 0x19cf0, 0x19d40, 1413 0x19d50, 0x19d94, 1414 0x19da0, 0x19de8, 1415 0x19df0, 0x19e10, 1416 0x19e50, 0x19e90, 1417 0x19ea0, 0x19f24, 1418 0x19f34, 0x19f34, 1419 0x19f40, 0x19f50, 1420 0x19f90, 0x19fb4, 1421 0x19fc4, 0x19fe4, 1422 0x1a000, 0x1a004, 1423 0x1a010, 0x1a06c, 1424 0x1a0b0, 0x1a0e4, 1425 0x1a0ec, 0x1a0f8, 1426 0x1a100, 0x1a108, 1427 0x1a114, 0x1a120, 1428 0x1a128, 0x1a130, 1429 0x1a138, 0x1a138, 1430 0x1a190, 0x1a1c4, 1431 0x1a1fc, 0x1a1fc, 1432 0x1e008, 0x1e00c, 1433 0x1e040, 0x1e044, 1434 0x1e04c, 0x1e04c, 1435 0x1e284, 0x1e290, 1436 0x1e2c0, 0x1e2c0, 1437 0x1e2e0, 0x1e2e0, 1438 0x1e300, 0x1e384, 1439 0x1e3c0, 0x1e3c8, 1440 0x1e408, 0x1e40c, 1441 0x1e440, 0x1e444, 1442 0x1e44c, 0x1e44c, 1443 0x1e684, 0x1e690, 1444 0x1e6c0, 0x1e6c0, 1445 0x1e6e0, 0x1e6e0, 1446 0x1e700, 0x1e784, 1447 0x1e7c0, 0x1e7c8, 1448 0x1e808, 0x1e80c, 1449 0x1e840, 0x1e844, 1450 0x1e84c, 0x1e84c, 1451 0x1ea84, 0x1ea90, 1452 0x1eac0, 0x1eac0, 1453 0x1eae0, 0x1eae0, 1454 0x1eb00, 0x1eb84, 1455 0x1ebc0, 0x1ebc8, 1456 0x1ec08, 0x1ec0c, 1457 0x1ec40, 0x1ec44, 1458 0x1ec4c, 0x1ec4c, 1459 0x1ee84, 0x1ee90, 1460 0x1eec0, 0x1eec0, 1461 0x1eee0, 0x1eee0, 1462 0x1ef00, 0x1ef84, 1463 0x1efc0, 0x1efc8, 1464 0x1f008, 0x1f00c, 1465 0x1f040, 0x1f044, 1466 0x1f04c, 0x1f04c, 1467 0x1f284, 0x1f290, 1468 0x1f2c0, 0x1f2c0, 1469 0x1f2e0, 0x1f2e0, 1470 0x1f300, 0x1f384, 1471 0x1f3c0, 0x1f3c8, 1472 0x1f408, 0x1f40c, 1473 0x1f440, 0x1f444, 1474 0x1f44c, 0x1f44c, 1475 0x1f684, 0x1f690, 1476 0x1f6c0, 0x1f6c0, 1477 0x1f6e0, 0x1f6e0, 1478 0x1f700, 0x1f784, 1479 0x1f7c0, 0x1f7c8, 1480 0x1f808, 0x1f80c, 1481 0x1f840, 0x1f844, 1482 0x1f84c, 0x1f84c, 1483 0x1fa84, 0x1fa90, 1484 0x1fac0, 0x1fac0, 1485 0x1fae0, 0x1fae0, 1486 0x1fb00, 0x1fb84, 1487 0x1fbc0, 0x1fbc8, 1488 0x1fc08, 0x1fc0c, 1489 0x1fc40, 0x1fc44, 1490 0x1fc4c, 0x1fc4c, 1491 0x1fe84, 0x1fe90, 1492 0x1fec0, 0x1fec0, 1493 0x1fee0, 0x1fee0, 1494 0x1ff00, 0x1ff84, 1495 0x1ffc0, 0x1ffc8, 1496 0x30000, 0x30030, 1497 0x30100, 0x30144, 1498 0x30190, 0x301a0, 1499 0x301a8, 0x301b8, 1500 0x301c4, 0x301c8, 1501 0x301d0, 0x301d0, 1502 0x30200, 0x30318, 1503 0x30400, 0x304b4, 1504 0x304c0, 0x3052c, 1505 0x30540, 0x3061c, 1506 0x30800, 0x30828, 1507 0x30834, 0x30834, 1508 0x308c0, 0x30908, 1509 0x30910, 0x309ac, 1510 0x30a00, 0x30a14, 1511 0x30a1c, 0x30a2c, 1512 0x30a44, 0x30a50, 1513 0x30a74, 0x30a74, 1514 0x30a7c, 0x30afc, 1515 0x30b08, 0x30c24, 1516 0x30d00, 0x30d00, 1517 0x30d08, 0x30d14, 1518 0x30d1c, 0x30d20, 1519 0x30d3c, 0x30d3c, 1520 0x30d48, 0x30d50, 1521 0x31200, 0x3120c, 1522 0x31220, 0x31220, 1523 0x31240, 0x31240, 1524 0x31600, 0x3160c, 1525 0x31a00, 0x31a1c, 1526 0x31e00, 0x31e20, 1527 0x31e38, 0x31e3c, 1528 0x31e80, 0x31e80, 1529 0x31e88, 0x31ea8, 1530 0x31eb0, 0x31eb4, 1531 0x31ec8, 0x31ed4, 1532 0x31fb8, 0x32004, 1533 0x32200, 0x32200, 1534 0x32208, 0x32240, 1535 0x32248, 0x32280, 1536 0x32288, 0x322c0, 1537 0x322c8, 0x322fc, 1538 0x32600, 0x32630, 1539 0x32a00, 0x32abc, 1540 0x32b00, 0x32b10, 1541 0x32b20, 0x32b30, 1542 0x32b40, 0x32b50, 1543 0x32b60, 0x32b70, 1544 0x33000, 0x33028, 1545 0x33030, 0x33048, 1546 0x33060, 0x33068, 1547 0x33070, 0x3309c, 1548 0x330f0, 0x33128, 1549 0x33130, 0x33148, 1550 0x33160, 0x33168, 1551 0x33170, 0x3319c, 1552 0x331f0, 0x33238, 1553 0x33240, 0x33240, 1554 0x33248, 0x33250, 1555 0x3325c, 0x33264, 1556 0x33270, 0x332b8, 1557 0x332c0, 0x332e4, 1558 0x332f8, 0x33338, 1559 0x33340, 0x33340, 1560 0x33348, 0x33350, 1561 0x3335c, 0x33364, 1562 0x33370, 0x333b8, 1563 0x333c0, 0x333e4, 1564 0x333f8, 0x33428, 1565 0x33430, 0x33448, 1566 0x33460, 0x33468, 1567 0x33470, 0x3349c, 1568 0x334f0, 0x33528, 1569 0x33530, 0x33548, 1570 0x33560, 0x33568, 1571 0x33570, 0x3359c, 1572 0x335f0, 0x33638, 1573 0x33640, 0x33640, 1574 0x33648, 0x33650, 1575 0x3365c, 0x33664, 1576 0x33670, 0x336b8, 1577 0x336c0, 0x336e4, 1578 0x336f8, 0x33738, 1579 0x33740, 0x33740, 1580 0x33748, 0x33750, 1581 0x3375c, 0x33764, 1582 0x33770, 0x337b8, 1583 0x337c0, 0x337e4, 1584 0x337f8, 0x337fc, 1585 0x33814, 0x33814, 1586 0x3382c, 0x3382c, 1587 0x33880, 0x3388c, 1588 0x338e8, 0x338ec, 1589 0x33900, 0x33928, 1590 0x33930, 0x33948, 1591 0x33960, 0x33968, 1592 0x33970, 0x3399c, 1593 0x339f0, 0x33a38, 1594 0x33a40, 0x33a40, 1595 0x33a48, 0x33a50, 1596 0x33a5c, 0x33a64, 1597 0x33a70, 0x33ab8, 1598 0x33ac0, 0x33ae4, 1599 0x33af8, 0x33b10, 1600 0x33b28, 0x33b28, 1601 0x33b3c, 0x33b50, 1602 0x33bf0, 0x33c10, 1603 0x33c28, 0x33c28, 1604 0x33c3c, 0x33c50, 1605 0x33cf0, 0x33cfc, 1606 0x34000, 0x34030, 1607 0x34100, 0x34144, 1608 0x34190, 0x341a0, 1609 0x341a8, 0x341b8, 1610 0x341c4, 0x341c8, 1611 0x341d0, 0x341d0, 1612 0x34200, 0x34318, 1613 0x34400, 0x344b4, 1614 0x344c0, 0x3452c, 1615 0x34540, 0x3461c, 1616 0x34800, 0x34828, 1617 0x34834, 0x34834, 1618 0x348c0, 0x34908, 1619 0x34910, 0x349ac, 1620 0x34a00, 0x34a14, 1621 0x34a1c, 0x34a2c, 1622 0x34a44, 0x34a50, 1623 0x34a74, 0x34a74, 1624 0x34a7c, 0x34afc, 1625 0x34b08, 0x34c24, 1626 0x34d00, 0x34d00, 1627 0x34d08, 0x34d14, 1628 0x34d1c, 0x34d20, 1629 0x34d3c, 0x34d3c, 1630 0x34d48, 0x34d50, 1631 0x35200, 0x3520c, 1632 0x35220, 0x35220, 1633 0x35240, 0x35240, 1634 0x35600, 0x3560c, 1635 0x35a00, 0x35a1c, 1636 0x35e00, 0x35e20, 1637 0x35e38, 0x35e3c, 1638 0x35e80, 0x35e80, 1639 0x35e88, 0x35ea8, 1640 0x35eb0, 0x35eb4, 1641 0x35ec8, 0x35ed4, 1642 0x35fb8, 0x36004, 1643 0x36200, 0x36200, 1644 0x36208, 0x36240, 1645 0x36248, 0x36280, 1646 0x36288, 0x362c0, 1647 0x362c8, 0x362fc, 1648 0x36600, 0x36630, 1649 0x36a00, 0x36abc, 1650 0x36b00, 0x36b10, 1651 0x36b20, 0x36b30, 1652 0x36b40, 0x36b50, 1653 0x36b60, 0x36b70, 1654 0x37000, 0x37028, 1655 0x37030, 0x37048, 1656 0x37060, 0x37068, 1657 0x37070, 0x3709c, 1658 0x370f0, 0x37128, 1659 0x37130, 0x37148, 1660 0x37160, 0x37168, 1661 0x37170, 0x3719c, 1662 0x371f0, 0x37238, 1663 0x37240, 0x37240, 1664 0x37248, 0x37250, 1665 0x3725c, 0x37264, 1666 0x37270, 0x372b8, 1667 0x372c0, 0x372e4, 1668 0x372f8, 0x37338, 1669 0x37340, 0x37340, 1670 0x37348, 0x37350, 1671 0x3735c, 0x37364, 1672 0x37370, 0x373b8, 1673 0x373c0, 0x373e4, 1674 0x373f8, 0x37428, 1675 0x37430, 0x37448, 1676 0x37460, 0x37468, 1677 0x37470, 0x3749c, 1678 0x374f0, 0x37528, 1679 0x37530, 0x37548, 1680 0x37560, 0x37568, 1681 0x37570, 0x3759c, 1682 0x375f0, 0x37638, 1683 0x37640, 0x37640, 1684 0x37648, 0x37650, 1685 0x3765c, 0x37664, 1686 0x37670, 0x376b8, 1687 0x376c0, 0x376e4, 1688 0x376f8, 0x37738, 1689 0x37740, 0x37740, 1690 0x37748, 0x37750, 1691 0x3775c, 0x37764, 1692 0x37770, 0x377b8, 1693 0x377c0, 0x377e4, 1694 0x377f8, 0x377fc, 1695 0x37814, 0x37814, 1696 0x3782c, 0x3782c, 1697 0x37880, 0x3788c, 1698 0x378e8, 0x378ec, 1699 0x37900, 0x37928, 1700 0x37930, 0x37948, 1701 0x37960, 0x37968, 1702 0x37970, 0x3799c, 1703 0x379f0, 0x37a38, 1704 0x37a40, 0x37a40, 1705 0x37a48, 0x37a50, 1706 0x37a5c, 0x37a64, 1707 0x37a70, 0x37ab8, 1708 0x37ac0, 0x37ae4, 1709 0x37af8, 0x37b10, 1710 0x37b28, 0x37b28, 1711 0x37b3c, 0x37b50, 1712 0x37bf0, 0x37c10, 1713 0x37c28, 0x37c28, 1714 0x37c3c, 0x37c50, 1715 0x37cf0, 0x37cfc, 1716 0x38000, 0x38030, 1717 0x38100, 0x38144, 1718 0x38190, 0x381a0, 1719 0x381a8, 0x381b8, 1720 0x381c4, 0x381c8, 1721 0x381d0, 0x381d0, 1722 0x38200, 0x38318, 1723 0x38400, 0x384b4, 1724 0x384c0, 0x3852c, 1725 0x38540, 0x3861c, 1726 0x38800, 0x38828, 1727 0x38834, 0x38834, 1728 0x388c0, 0x38908, 1729 0x38910, 0x389ac, 1730 0x38a00, 0x38a14, 1731 0x38a1c, 0x38a2c, 1732 0x38a44, 0x38a50, 1733 0x38a74, 0x38a74, 1734 0x38a7c, 0x38afc, 1735 0x38b08, 0x38c24, 1736 0x38d00, 0x38d00, 1737 0x38d08, 0x38d14, 1738 0x38d1c, 0x38d20, 1739 0x38d3c, 0x38d3c, 1740 0x38d48, 0x38d50, 1741 0x39200, 0x3920c, 1742 0x39220, 0x39220, 1743 0x39240, 0x39240, 1744 0x39600, 0x3960c, 1745 0x39a00, 0x39a1c, 1746 0x39e00, 0x39e20, 1747 0x39e38, 0x39e3c, 1748 0x39e80, 0x39e80, 1749 0x39e88, 0x39ea8, 1750 0x39eb0, 0x39eb4, 1751 0x39ec8, 0x39ed4, 1752 0x39fb8, 0x3a004, 1753 0x3a200, 0x3a200, 1754 0x3a208, 0x3a240, 1755 0x3a248, 0x3a280, 1756 0x3a288, 0x3a2c0, 1757 0x3a2c8, 0x3a2fc, 1758 0x3a600, 0x3a630, 1759 0x3aa00, 0x3aabc, 1760 0x3ab00, 0x3ab10, 1761 0x3ab20, 0x3ab30, 1762 0x3ab40, 0x3ab50, 1763 0x3ab60, 0x3ab70, 1764 0x3b000, 0x3b028, 1765 0x3b030, 0x3b048, 1766 0x3b060, 0x3b068, 1767 0x3b070, 0x3b09c, 1768 0x3b0f0, 0x3b128, 1769 0x3b130, 0x3b148, 1770 0x3b160, 0x3b168, 1771 0x3b170, 0x3b19c, 1772 0x3b1f0, 0x3b238, 1773 0x3b240, 0x3b240, 1774 0x3b248, 0x3b250, 1775 0x3b25c, 0x3b264, 1776 0x3b270, 0x3b2b8, 1777 0x3b2c0, 0x3b2e4, 1778 0x3b2f8, 0x3b338, 1779 0x3b340, 0x3b340, 1780 0x3b348, 0x3b350, 1781 0x3b35c, 0x3b364, 1782 0x3b370, 0x3b3b8, 1783 0x3b3c0, 0x3b3e4, 1784 0x3b3f8, 0x3b428, 1785 0x3b430, 0x3b448, 1786 0x3b460, 0x3b468, 1787 0x3b470, 0x3b49c, 1788 0x3b4f0, 0x3b528, 1789 0x3b530, 0x3b548, 1790 0x3b560, 0x3b568, 1791 0x3b570, 0x3b59c, 1792 0x3b5f0, 0x3b638, 1793 0x3b640, 0x3b640, 1794 0x3b648, 0x3b650, 1795 0x3b65c, 0x3b664, 1796 0x3b670, 0x3b6b8, 1797 0x3b6c0, 0x3b6e4, 1798 0x3b6f8, 0x3b738, 1799 0x3b740, 0x3b740, 1800 0x3b748, 0x3b750, 1801 0x3b75c, 0x3b764, 1802 0x3b770, 0x3b7b8, 1803 0x3b7c0, 0x3b7e4, 1804 0x3b7f8, 0x3b7fc, 1805 0x3b814, 0x3b814, 1806 0x3b82c, 0x3b82c, 1807 0x3b880, 0x3b88c, 1808 0x3b8e8, 0x3b8ec, 1809 0x3b900, 0x3b928, 1810 0x3b930, 0x3b948, 1811 0x3b960, 0x3b968, 1812 0x3b970, 0x3b99c, 1813 0x3b9f0, 0x3ba38, 1814 0x3ba40, 0x3ba40, 1815 0x3ba48, 0x3ba50, 1816 0x3ba5c, 0x3ba64, 1817 0x3ba70, 0x3bab8, 1818 0x3bac0, 0x3bae4, 1819 0x3baf8, 0x3bb10, 1820 0x3bb28, 0x3bb28, 1821 0x3bb3c, 0x3bb50, 1822 0x3bbf0, 0x3bc10, 1823 0x3bc28, 0x3bc28, 1824 0x3bc3c, 0x3bc50, 1825 0x3bcf0, 0x3bcfc, 1826 0x3c000, 0x3c030, 1827 0x3c100, 0x3c144, 1828 0x3c190, 0x3c1a0, 1829 0x3c1a8, 0x3c1b8, 1830 0x3c1c4, 0x3c1c8, 1831 0x3c1d0, 0x3c1d0, 1832 0x3c200, 0x3c318, 1833 0x3c400, 0x3c4b4, 1834 0x3c4c0, 0x3c52c, 1835 0x3c540, 0x3c61c, 1836 0x3c800, 0x3c828, 1837 0x3c834, 0x3c834, 1838 0x3c8c0, 0x3c908, 1839 0x3c910, 0x3c9ac, 1840 0x3ca00, 0x3ca14, 1841 0x3ca1c, 0x3ca2c, 1842 0x3ca44, 0x3ca50, 1843 0x3ca74, 0x3ca74, 1844 0x3ca7c, 0x3cafc, 1845 0x3cb08, 0x3cc24, 1846 0x3cd00, 0x3cd00, 1847 0x3cd08, 0x3cd14, 1848 0x3cd1c, 0x3cd20, 1849 0x3cd3c, 0x3cd3c, 1850 0x3cd48, 0x3cd50, 1851 0x3d200, 0x3d20c, 1852 0x3d220, 0x3d220, 1853 0x3d240, 0x3d240, 1854 0x3d600, 0x3d60c, 1855 0x3da00, 0x3da1c, 1856 0x3de00, 0x3de20, 1857 0x3de38, 0x3de3c, 1858 0x3de80, 0x3de80, 1859 0x3de88, 0x3dea8, 1860 0x3deb0, 0x3deb4, 1861 0x3dec8, 0x3ded4, 1862 0x3dfb8, 0x3e004, 1863 0x3e200, 0x3e200, 1864 0x3e208, 0x3e240, 1865 0x3e248, 0x3e280, 1866 0x3e288, 0x3e2c0, 1867 0x3e2c8, 0x3e2fc, 1868 0x3e600, 0x3e630, 1869 0x3ea00, 0x3eabc, 1870 0x3eb00, 0x3eb10, 1871 0x3eb20, 0x3eb30, 1872 0x3eb40, 0x3eb50, 1873 0x3eb60, 0x3eb70, 1874 0x3f000, 0x3f028, 1875 0x3f030, 0x3f048, 1876 0x3f060, 0x3f068, 1877 0x3f070, 0x3f09c, 1878 0x3f0f0, 0x3f128, 1879 0x3f130, 0x3f148, 1880 0x3f160, 0x3f168, 1881 0x3f170, 0x3f19c, 1882 0x3f1f0, 0x3f238, 1883 0x3f240, 0x3f240, 1884 0x3f248, 0x3f250, 1885 0x3f25c, 0x3f264, 1886 0x3f270, 0x3f2b8, 1887 0x3f2c0, 0x3f2e4, 1888 0x3f2f8, 0x3f338, 1889 0x3f340, 0x3f340, 1890 0x3f348, 0x3f350, 1891 0x3f35c, 0x3f364, 1892 0x3f370, 0x3f3b8, 1893 0x3f3c0, 0x3f3e4, 1894 0x3f3f8, 0x3f428, 1895 0x3f430, 0x3f448, 1896 0x3f460, 0x3f468, 1897 0x3f470, 0x3f49c, 1898 0x3f4f0, 0x3f528, 1899 0x3f530, 0x3f548, 1900 0x3f560, 0x3f568, 1901 0x3f570, 0x3f59c, 1902 0x3f5f0, 0x3f638, 1903 0x3f640, 0x3f640, 1904 0x3f648, 0x3f650, 1905 0x3f65c, 0x3f664, 1906 0x3f670, 0x3f6b8, 1907 0x3f6c0, 0x3f6e4, 1908 0x3f6f8, 0x3f738, 1909 0x3f740, 0x3f740, 1910 0x3f748, 0x3f750, 1911 0x3f75c, 0x3f764, 1912 0x3f770, 0x3f7b8, 1913 0x3f7c0, 0x3f7e4, 1914 0x3f7f8, 0x3f7fc, 1915 0x3f814, 0x3f814, 1916 0x3f82c, 0x3f82c, 1917 0x3f880, 0x3f88c, 1918 0x3f8e8, 0x3f8ec, 1919 0x3f900, 0x3f928, 1920 0x3f930, 0x3f948, 1921 0x3f960, 0x3f968, 1922 0x3f970, 0x3f99c, 1923 0x3f9f0, 0x3fa38, 1924 0x3fa40, 0x3fa40, 1925 0x3fa48, 0x3fa50, 1926 0x3fa5c, 0x3fa64, 1927 0x3fa70, 0x3fab8, 1928 0x3fac0, 0x3fae4, 1929 0x3faf8, 0x3fb10, 1930 0x3fb28, 0x3fb28, 1931 0x3fb3c, 0x3fb50, 1932 0x3fbf0, 0x3fc10, 1933 0x3fc28, 0x3fc28, 1934 0x3fc3c, 0x3fc50, 1935 0x3fcf0, 0x3fcfc, 1936 0x40000, 0x4000c, 1937 0x40040, 0x40050, 1938 0x40060, 0x40068, 1939 0x4007c, 0x4008c, 1940 0x40094, 0x400b0, 1941 0x400c0, 0x40144, 1942 0x40180, 0x4018c, 1943 0x40200, 0x40254, 1944 0x40260, 0x40264, 1945 0x40270, 0x40288, 1946 0x40290, 0x40298, 1947 0x402ac, 0x402c8, 1948 0x402d0, 0x402e0, 1949 0x402f0, 0x402f0, 1950 0x40300, 0x4033c, 1951 0x403f8, 0x403fc, 1952 0x41304, 0x413c4, 1953 0x41400, 0x4140c, 1954 0x41414, 0x4141c, 1955 0x41480, 0x414d0, 1956 0x44000, 0x44054, 1957 0x4405c, 0x44078, 1958 0x440c0, 0x44174, 1959 0x44180, 0x441ac, 1960 0x441b4, 0x441b8, 1961 0x441c0, 0x44254, 1962 0x4425c, 0x44278, 1963 0x442c0, 0x44374, 1964 0x44380, 0x443ac, 1965 0x443b4, 0x443b8, 1966 0x443c0, 0x44454, 1967 0x4445c, 0x44478, 1968 0x444c0, 0x44574, 1969 0x44580, 0x445ac, 1970 0x445b4, 0x445b8, 1971 0x445c0, 0x44654, 1972 0x4465c, 0x44678, 1973 0x446c0, 0x44774, 1974 0x44780, 0x447ac, 1975 0x447b4, 0x447b8, 1976 0x447c0, 0x44854, 1977 0x4485c, 0x44878, 1978 0x448c0, 0x44974, 1979 0x44980, 0x449ac, 1980 0x449b4, 0x449b8, 1981 0x449c0, 0x449fc, 1982 0x45000, 0x45004, 1983 0x45010, 0x45030, 1984 0x45040, 0x45060, 1985 0x45068, 0x45068, 1986 0x45080, 0x45084, 1987 0x450a0, 0x450b0, 1988 0x45200, 0x45204, 1989 0x45210, 0x45230, 1990 0x45240, 0x45260, 1991 0x45268, 0x45268, 1992 0x45280, 0x45284, 1993 0x452a0, 0x452b0, 1994 0x460c0, 0x460e4, 1995 0x47000, 0x4703c, 1996 0x47044, 0x4708c, 1997 0x47200, 0x47250, 1998 0x47400, 0x47408, 1999 0x47414, 0x47420, 2000 0x47600, 0x47618, 2001 0x47800, 0x47814, 2002 0x48000, 0x4800c, 2003 0x48040, 0x48050, 2004 0x48060, 0x48068, 2005 0x4807c, 0x4808c, 2006 0x48094, 0x480b0, 2007 0x480c0, 0x48144, 2008 0x48180, 0x4818c, 2009 0x48200, 0x48254, 2010 0x48260, 0x48264, 2011 0x48270, 0x48288, 2012 0x48290, 0x48298, 2013 0x482ac, 0x482c8, 2014 0x482d0, 0x482e0, 2015 0x482f0, 0x482f0, 2016 0x48300, 0x4833c, 2017 0x483f8, 0x483fc, 2018 0x49304, 0x493c4, 2019 0x49400, 0x4940c, 2020 0x49414, 0x4941c, 2021 0x49480, 0x494d0, 2022 0x4c000, 0x4c054, 2023 0x4c05c, 0x4c078, 2024 0x4c0c0, 0x4c174, 2025 0x4c180, 0x4c1ac, 2026 0x4c1b4, 0x4c1b8, 2027 0x4c1c0, 0x4c254, 2028 0x4c25c, 0x4c278, 2029 0x4c2c0, 0x4c374, 2030 0x4c380, 0x4c3ac, 2031 0x4c3b4, 0x4c3b8, 2032 0x4c3c0, 0x4c454, 2033 0x4c45c, 0x4c478, 2034 0x4c4c0, 0x4c574, 2035 0x4c580, 0x4c5ac, 2036 0x4c5b4, 0x4c5b8, 2037 0x4c5c0, 0x4c654, 2038 0x4c65c, 0x4c678, 2039 0x4c6c0, 0x4c774, 2040 0x4c780, 0x4c7ac, 2041 0x4c7b4, 0x4c7b8, 2042 0x4c7c0, 0x4c854, 2043 0x4c85c, 0x4c878, 2044 0x4c8c0, 0x4c974, 2045 0x4c980, 0x4c9ac, 2046 0x4c9b4, 0x4c9b8, 2047 0x4c9c0, 0x4c9fc, 2048 0x4d000, 0x4d004, 2049 0x4d010, 0x4d030, 2050 0x4d040, 0x4d060, 2051 0x4d068, 0x4d068, 2052 0x4d080, 0x4d084, 2053 0x4d0a0, 0x4d0b0, 2054 0x4d200, 0x4d204, 2055 0x4d210, 0x4d230, 2056 0x4d240, 0x4d260, 2057 0x4d268, 0x4d268, 2058 0x4d280, 0x4d284, 2059 0x4d2a0, 0x4d2b0, 2060 0x4e0c0, 0x4e0e4, 2061 0x4f000, 0x4f03c, 2062 0x4f044, 0x4f08c, 2063 0x4f200, 0x4f250, 2064 0x4f400, 0x4f408, 2065 0x4f414, 0x4f420, 2066 0x4f600, 0x4f618, 2067 0x4f800, 0x4f814, 2068 0x50000, 0x50084, 2069 0x50090, 0x500cc, 2070 0x50400, 0x50400, 2071 0x50800, 0x50884, 2072 0x50890, 0x508cc, 2073 0x50c00, 0x50c00, 2074 0x51000, 0x5101c, 2075 0x51300, 0x51308, 2076 }; 2077 2078 static const unsigned int t5vf_reg_ranges[] = { 2079 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2080 VF_MPS_REG(A_MPS_VF_CTL), 2081 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2082 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2083 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2084 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2085 FW_T4VF_MBDATA_BASE_ADDR, 2086 FW_T4VF_MBDATA_BASE_ADDR + 2087 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2088 }; 2089 2090 static const unsigned int t6_reg_ranges[] = { 2091 0x1008, 0x101c, 2092 0x1024, 0x10a8, 2093 0x10b4, 0x10f8, 2094 0x1100, 0x1114, 2095 0x111c, 0x112c, 2096 0x1138, 0x113c, 2097 0x1144, 0x114c, 2098 0x1180, 0x1184, 2099 0x1190, 0x1194, 2100 0x11a0, 0x11a4, 2101 0x11b0, 0x11b4, 2102 0x11fc, 0x1274, 2103 0x1280, 0x133c, 2104 0x1800, 0x18fc, 2105 0x3000, 0x302c, 2106 0x3060, 0x30b0, 2107 0x30b8, 0x30d8, 2108 0x30e0, 0x30fc, 2109 0x3140, 0x357c, 2110 0x35a8, 0x35cc, 2111 0x35ec, 0x35ec, 2112 0x3600, 0x5624, 2113 0x56cc, 0x56ec, 2114 0x56f4, 0x5720, 2115 0x5728, 0x575c, 2116 0x580c, 0x5814, 2117 0x5890, 0x589c, 2118 0x58a4, 0x58ac, 2119 0x58b8, 0x58bc, 2120 0x5940, 0x595c, 2121 0x5980, 0x598c, 2122 0x59b0, 0x59c8, 2123 0x59d0, 0x59dc, 2124 0x59fc, 0x5a18, 2125 0x5a60, 0x5a6c, 2126 0x5a80, 0x5a8c, 2127 0x5a94, 0x5a9c, 2128 0x5b94, 0x5bfc, 2129 0x5c10, 0x5e48, 2130 0x5e50, 0x5e94, 2131 0x5ea0, 0x5eb0, 2132 0x5ec0, 0x5ec0, 2133 0x5ec8, 0x5ed0, 2134 0x5ee0, 0x5ee0, 2135 0x5ef0, 0x5ef0, 2136 0x5f00, 0x5f00, 2137 0x6000, 0x6020, 2138 0x6028, 0x6040, 2139 0x6058, 0x609c, 2140 0x60a8, 0x619c, 2141 0x7700, 0x7798, 2142 0x77c0, 0x7880, 2143 0x78cc, 0x78fc, 2144 0x7b00, 0x7b58, 2145 0x7b60, 0x7b84, 2146 0x7b8c, 0x7c54, 2147 0x7d00, 0x7d38, 2148 0x7d40, 0x7d84, 2149 0x7d8c, 0x7ddc, 2150 0x7de4, 0x7e04, 2151 0x7e10, 0x7e1c, 2152 0x7e24, 0x7e38, 2153 0x7e40, 0x7e44, 2154 0x7e4c, 0x7e78, 2155 0x7e80, 0x7edc, 2156 0x7ee8, 0x7efc, 2157 0x8dc0, 0x8de4, 2158 0x8df8, 0x8e04, 2159 0x8e10, 0x8e84, 2160 0x8ea0, 0x8f88, 2161 0x8fb8, 0x9058, 2162 0x9060, 0x9060, 2163 0x9068, 0x90f8, 2164 0x9100, 0x9124, 2165 0x9400, 0x9470, 2166 0x9600, 0x9600, 2167 0x9608, 0x9638, 2168 0x9640, 0x9704, 2169 0x9710, 0x971c, 2170 0x9800, 0x9808, 2171 0x9820, 0x983c, 2172 0x9850, 0x9864, 2173 0x9c00, 0x9c6c, 2174 0x9c80, 0x9cec, 2175 0x9d00, 0x9d6c, 2176 0x9d80, 0x9dec, 2177 0x9e00, 0x9e6c, 2178 0x9e80, 0x9eec, 2179 0x9f00, 0x9f6c, 2180 0x9f80, 0xa020, 2181 0xd004, 0xd03c, 2182 0xd100, 0xd118, 2183 0xd200, 0xd214, 2184 0xd220, 0xd234, 2185 0xd240, 0xd254, 2186 0xd260, 0xd274, 2187 0xd280, 0xd294, 2188 0xd2a0, 0xd2b4, 2189 0xd2c0, 0xd2d4, 2190 0xd2e0, 0xd2f4, 2191 0xd300, 0xd31c, 2192 0xdfc0, 0xdfe0, 2193 0xe000, 0xf008, 2194 0xf010, 0xf018, 2195 0xf020, 0xf028, 2196 0x11000, 0x11014, 2197 0x11048, 0x1106c, 2198 0x11074, 0x11088, 2199 0x11098, 0x11120, 2200 0x1112c, 0x1117c, 2201 0x11190, 0x112e0, 2202 0x11300, 0x1130c, 2203 0x12000, 0x1206c, 2204 0x19040, 0x1906c, 2205 0x19078, 0x19080, 2206 0x1908c, 0x190e8, 2207 0x190f0, 0x190f8, 2208 0x19100, 0x19110, 2209 0x19120, 0x19124, 2210 0x19150, 0x19194, 2211 0x1919c, 0x191b0, 2212 0x191d0, 0x191e8, 2213 0x19238, 0x19290, 2214 0x192a4, 0x192b0, 2215 0x192bc, 0x192bc, 2216 0x19348, 0x1934c, 2217 0x193f8, 0x19418, 2218 0x19420, 0x19428, 2219 0x19430, 0x19444, 2220 0x1944c, 0x1946c, 2221 0x19474, 0x19474, 2222 0x19490, 0x194cc, 2223 0x194f0, 0x194f8, 2224 0x19c00, 0x19c48, 2225 0x19c50, 0x19c80, 2226 0x19c94, 0x19c98, 2227 0x19ca0, 0x19cbc, 2228 0x19ce4, 0x19ce4, 2229 0x19cf0, 0x19cf8, 2230 0x19d00, 0x19d28, 2231 0x19d50, 0x19d78, 2232 0x19d94, 0x19d98, 2233 0x19da0, 0x19dc8, 2234 0x19df0, 0x19e10, 2235 0x19e50, 0x19e6c, 2236 0x19ea0, 0x19ebc, 2237 0x19ec4, 0x19ef4, 2238 0x19f04, 0x19f2c, 2239 0x19f34, 0x19f34, 2240 0x19f40, 0x19f50, 2241 0x19f90, 0x19fac, 2242 0x19fc4, 0x19fc8, 2243 0x19fd0, 0x19fe4, 2244 0x1a000, 0x1a004, 2245 0x1a010, 0x1a06c, 2246 0x1a0b0, 0x1a0e4, 2247 0x1a0ec, 0x1a0f8, 2248 0x1a100, 0x1a108, 2249 0x1a114, 0x1a120, 2250 0x1a128, 0x1a130, 2251 0x1a138, 0x1a138, 2252 0x1a190, 0x1a1c4, 2253 0x1a1fc, 0x1a1fc, 2254 0x1e008, 0x1e00c, 2255 0x1e040, 0x1e044, 2256 0x1e04c, 0x1e04c, 2257 0x1e284, 0x1e290, 2258 0x1e2c0, 0x1e2c0, 2259 0x1e2e0, 0x1e2e0, 2260 0x1e300, 0x1e384, 2261 0x1e3c0, 0x1e3c8, 2262 0x1e408, 0x1e40c, 2263 0x1e440, 0x1e444, 2264 0x1e44c, 0x1e44c, 2265 0x1e684, 0x1e690, 2266 0x1e6c0, 0x1e6c0, 2267 0x1e6e0, 0x1e6e0, 2268 0x1e700, 0x1e784, 2269 0x1e7c0, 0x1e7c8, 2270 0x1e808, 0x1e80c, 2271 0x1e840, 0x1e844, 2272 0x1e84c, 0x1e84c, 2273 0x1ea84, 0x1ea90, 2274 0x1eac0, 0x1eac0, 2275 0x1eae0, 0x1eae0, 2276 0x1eb00, 0x1eb84, 2277 0x1ebc0, 0x1ebc8, 2278 0x1ec08, 0x1ec0c, 2279 0x1ec40, 0x1ec44, 2280 0x1ec4c, 0x1ec4c, 2281 0x1ee84, 0x1ee90, 2282 0x1eec0, 0x1eec0, 2283 0x1eee0, 0x1eee0, 2284 0x1ef00, 0x1ef84, 2285 0x1efc0, 0x1efc8, 2286 0x1f008, 0x1f00c, 2287 0x1f040, 0x1f044, 2288 0x1f04c, 0x1f04c, 2289 0x1f284, 0x1f290, 2290 0x1f2c0, 0x1f2c0, 2291 0x1f2e0, 0x1f2e0, 2292 0x1f300, 0x1f384, 2293 0x1f3c0, 0x1f3c8, 2294 0x1f408, 0x1f40c, 2295 0x1f440, 0x1f444, 2296 0x1f44c, 0x1f44c, 2297 0x1f684, 0x1f690, 2298 0x1f6c0, 0x1f6c0, 2299 0x1f6e0, 0x1f6e0, 2300 0x1f700, 0x1f784, 2301 0x1f7c0, 0x1f7c8, 2302 0x1f808, 0x1f80c, 2303 0x1f840, 0x1f844, 2304 0x1f84c, 0x1f84c, 2305 0x1fa84, 0x1fa90, 2306 0x1fac0, 0x1fac0, 2307 0x1fae0, 0x1fae0, 2308 0x1fb00, 0x1fb84, 2309 0x1fbc0, 0x1fbc8, 2310 0x1fc08, 0x1fc0c, 2311 0x1fc40, 0x1fc44, 2312 0x1fc4c, 0x1fc4c, 2313 0x1fe84, 0x1fe90, 2314 0x1fec0, 0x1fec0, 2315 0x1fee0, 0x1fee0, 2316 0x1ff00, 0x1ff84, 2317 0x1ffc0, 0x1ffc8, 2318 0x30000, 0x30030, 2319 0x30100, 0x30168, 2320 0x30190, 0x301a0, 2321 0x301a8, 0x301b8, 2322 0x301c4, 0x301c8, 2323 0x301d0, 0x301d0, 2324 0x30200, 0x30320, 2325 0x30400, 0x304b4, 2326 0x304c0, 0x3052c, 2327 0x30540, 0x3061c, 2328 0x30800, 0x308a0, 2329 0x308c0, 0x30908, 2330 0x30910, 0x309b8, 2331 0x30a00, 0x30a04, 2332 0x30a0c, 0x30a14, 2333 0x30a1c, 0x30a2c, 2334 0x30a44, 0x30a50, 2335 0x30a74, 0x30a74, 2336 0x30a7c, 0x30afc, 2337 0x30b08, 0x30c24, 2338 0x30d00, 0x30d14, 2339 0x30d1c, 0x30d3c, 2340 0x30d44, 0x30d4c, 2341 0x30d54, 0x30d74, 2342 0x30d7c, 0x30d7c, 2343 0x30de0, 0x30de0, 2344 0x30e00, 0x30ed4, 2345 0x30f00, 0x30fa4, 2346 0x30fc0, 0x30fc4, 2347 0x31000, 0x31004, 2348 0x31080, 0x310fc, 2349 0x31208, 0x31220, 2350 0x3123c, 0x31254, 2351 0x31300, 0x31300, 2352 0x31308, 0x3131c, 2353 0x31338, 0x3133c, 2354 0x31380, 0x31380, 2355 0x31388, 0x313a8, 2356 0x313b4, 0x313b4, 2357 0x31400, 0x31420, 2358 0x31438, 0x3143c, 2359 0x31480, 0x31480, 2360 0x314a8, 0x314a8, 2361 0x314b0, 0x314b4, 2362 0x314c8, 0x314d4, 2363 0x31a40, 0x31a4c, 2364 0x31af0, 0x31b20, 2365 0x31b38, 0x31b3c, 2366 0x31b80, 0x31b80, 2367 0x31ba8, 0x31ba8, 2368 0x31bb0, 0x31bb4, 2369 0x31bc8, 0x31bd4, 2370 0x32140, 0x3218c, 2371 0x321f0, 0x321f4, 2372 0x32200, 0x32200, 2373 0x32218, 0x32218, 2374 0x32400, 0x32400, 2375 0x32408, 0x3241c, 2376 0x32618, 0x32620, 2377 0x32664, 0x32664, 2378 0x326a8, 0x326a8, 2379 0x326ec, 0x326ec, 2380 0x32a00, 0x32abc, 2381 0x32b00, 0x32b18, 2382 0x32b20, 0x32b38, 2383 0x32b40, 0x32b58, 2384 0x32b60, 0x32b78, 2385 0x32c00, 0x32c00, 2386 0x32c08, 0x32c3c, 2387 0x33000, 0x3302c, 2388 0x33034, 0x33050, 2389 0x33058, 0x33058, 2390 0x33060, 0x3308c, 2391 0x3309c, 0x330ac, 2392 0x330c0, 0x330c0, 2393 0x330c8, 0x330d0, 2394 0x330d8, 0x330e0, 2395 0x330ec, 0x3312c, 2396 0x33134, 0x33150, 2397 0x33158, 0x33158, 2398 0x33160, 0x3318c, 2399 0x3319c, 0x331ac, 2400 0x331c0, 0x331c0, 2401 0x331c8, 0x331d0, 2402 0x331d8, 0x331e0, 2403 0x331ec, 0x33290, 2404 0x33298, 0x332c4, 2405 0x332e4, 0x33390, 2406 0x33398, 0x333c4, 2407 0x333e4, 0x3342c, 2408 0x33434, 0x33450, 2409 0x33458, 0x33458, 2410 0x33460, 0x3348c, 2411 0x3349c, 0x334ac, 2412 0x334c0, 0x334c0, 2413 0x334c8, 0x334d0, 2414 0x334d8, 0x334e0, 2415 0x334ec, 0x3352c, 2416 0x33534, 0x33550, 2417 0x33558, 0x33558, 2418 0x33560, 0x3358c, 2419 0x3359c, 0x335ac, 2420 0x335c0, 0x335c0, 2421 0x335c8, 0x335d0, 2422 0x335d8, 0x335e0, 2423 0x335ec, 0x33690, 2424 0x33698, 0x336c4, 2425 0x336e4, 0x33790, 2426 0x33798, 0x337c4, 2427 0x337e4, 0x337fc, 2428 0x33814, 0x33814, 2429 0x33854, 0x33868, 2430 0x33880, 0x3388c, 2431 0x338c0, 0x338d0, 2432 0x338e8, 0x338ec, 2433 0x33900, 0x3392c, 2434 0x33934, 0x33950, 2435 0x33958, 0x33958, 2436 0x33960, 0x3398c, 2437 0x3399c, 0x339ac, 2438 0x339c0, 0x339c0, 2439 0x339c8, 0x339d0, 2440 0x339d8, 0x339e0, 2441 0x339ec, 0x33a90, 2442 0x33a98, 0x33ac4, 2443 0x33ae4, 0x33b10, 2444 0x33b24, 0x33b28, 2445 0x33b38, 0x33b50, 2446 0x33bf0, 0x33c10, 2447 0x33c24, 0x33c28, 2448 0x33c38, 0x33c50, 2449 0x33cf0, 0x33cfc, 2450 0x34000, 0x34030, 2451 0x34100, 0x34168, 2452 0x34190, 0x341a0, 2453 0x341a8, 0x341b8, 2454 0x341c4, 0x341c8, 2455 0x341d0, 0x341d0, 2456 0x34200, 0x34320, 2457 0x34400, 0x344b4, 2458 0x344c0, 0x3452c, 2459 0x34540, 0x3461c, 2460 0x34800, 0x348a0, 2461 0x348c0, 0x34908, 2462 0x34910, 0x349b8, 2463 0x34a00, 0x34a04, 2464 0x34a0c, 0x34a14, 2465 0x34a1c, 0x34a2c, 2466 0x34a44, 0x34a50, 2467 0x34a74, 0x34a74, 2468 0x34a7c, 0x34afc, 2469 0x34b08, 0x34c24, 2470 0x34d00, 0x34d14, 2471 0x34d1c, 0x34d3c, 2472 0x34d44, 0x34d4c, 2473 0x34d54, 0x34d74, 2474 0x34d7c, 0x34d7c, 2475 0x34de0, 0x34de0, 2476 0x34e00, 0x34ed4, 2477 0x34f00, 0x34fa4, 2478 0x34fc0, 0x34fc4, 2479 0x35000, 0x35004, 2480 0x35080, 0x350fc, 2481 0x35208, 0x35220, 2482 0x3523c, 0x35254, 2483 0x35300, 0x35300, 2484 0x35308, 0x3531c, 2485 0x35338, 0x3533c, 2486 0x35380, 0x35380, 2487 0x35388, 0x353a8, 2488 0x353b4, 0x353b4, 2489 0x35400, 0x35420, 2490 0x35438, 0x3543c, 2491 0x35480, 0x35480, 2492 0x354a8, 0x354a8, 2493 0x354b0, 0x354b4, 2494 0x354c8, 0x354d4, 2495 0x35a40, 0x35a4c, 2496 0x35af0, 0x35b20, 2497 0x35b38, 0x35b3c, 2498 0x35b80, 0x35b80, 2499 0x35ba8, 0x35ba8, 2500 0x35bb0, 0x35bb4, 2501 0x35bc8, 0x35bd4, 2502 0x36140, 0x3618c, 2503 0x361f0, 0x361f4, 2504 0x36200, 0x36200, 2505 0x36218, 0x36218, 2506 0x36400, 0x36400, 2507 0x36408, 0x3641c, 2508 0x36618, 0x36620, 2509 0x36664, 0x36664, 2510 0x366a8, 0x366a8, 2511 0x366ec, 0x366ec, 2512 0x36a00, 0x36abc, 2513 0x36b00, 0x36b18, 2514 0x36b20, 0x36b38, 2515 0x36b40, 0x36b58, 2516 0x36b60, 0x36b78, 2517 0x36c00, 0x36c00, 2518 0x36c08, 0x36c3c, 2519 0x37000, 0x3702c, 2520 0x37034, 0x37050, 2521 0x37058, 0x37058, 2522 0x37060, 0x3708c, 2523 0x3709c, 0x370ac, 2524 0x370c0, 0x370c0, 2525 0x370c8, 0x370d0, 2526 0x370d8, 0x370e0, 2527 0x370ec, 0x3712c, 2528 0x37134, 0x37150, 2529 0x37158, 0x37158, 2530 0x37160, 0x3718c, 2531 0x3719c, 0x371ac, 2532 0x371c0, 0x371c0, 2533 0x371c8, 0x371d0, 2534 0x371d8, 0x371e0, 2535 0x371ec, 0x37290, 2536 0x37298, 0x372c4, 2537 0x372e4, 0x37390, 2538 0x37398, 0x373c4, 2539 0x373e4, 0x3742c, 2540 0x37434, 0x37450, 2541 0x37458, 0x37458, 2542 0x37460, 0x3748c, 2543 0x3749c, 0x374ac, 2544 0x374c0, 0x374c0, 2545 0x374c8, 0x374d0, 2546 0x374d8, 0x374e0, 2547 0x374ec, 0x3752c, 2548 0x37534, 0x37550, 2549 0x37558, 0x37558, 2550 0x37560, 0x3758c, 2551 0x3759c, 0x375ac, 2552 0x375c0, 0x375c0, 2553 0x375c8, 0x375d0, 2554 0x375d8, 0x375e0, 2555 0x375ec, 0x37690, 2556 0x37698, 0x376c4, 2557 0x376e4, 0x37790, 2558 0x37798, 0x377c4, 2559 0x377e4, 0x377fc, 2560 0x37814, 0x37814, 2561 0x37854, 0x37868, 2562 0x37880, 0x3788c, 2563 0x378c0, 0x378d0, 2564 0x378e8, 0x378ec, 2565 0x37900, 0x3792c, 2566 0x37934, 0x37950, 2567 0x37958, 0x37958, 2568 0x37960, 0x3798c, 2569 0x3799c, 0x379ac, 2570 0x379c0, 0x379c0, 2571 0x379c8, 0x379d0, 2572 0x379d8, 0x379e0, 2573 0x379ec, 0x37a90, 2574 0x37a98, 0x37ac4, 2575 0x37ae4, 0x37b10, 2576 0x37b24, 0x37b28, 2577 0x37b38, 0x37b50, 2578 0x37bf0, 0x37c10, 2579 0x37c24, 0x37c28, 2580 0x37c38, 0x37c50, 2581 0x37cf0, 0x37cfc, 2582 0x40040, 0x40040, 2583 0x40080, 0x40084, 2584 0x40100, 0x40100, 2585 0x40140, 0x401bc, 2586 0x40200, 0x40214, 2587 0x40228, 0x40228, 2588 0x40240, 0x40258, 2589 0x40280, 0x40280, 2590 0x40304, 0x40304, 2591 0x40330, 0x4033c, 2592 0x41304, 0x413c8, 2593 0x413d0, 0x413dc, 2594 0x413f0, 0x413f0, 2595 0x41400, 0x4140c, 2596 0x41414, 0x4141c, 2597 0x41480, 0x414d0, 2598 0x44000, 0x4407c, 2599 0x440c0, 0x441ac, 2600 0x441b4, 0x4427c, 2601 0x442c0, 0x443ac, 2602 0x443b4, 0x4447c, 2603 0x444c0, 0x445ac, 2604 0x445b4, 0x4467c, 2605 0x446c0, 0x447ac, 2606 0x447b4, 0x4487c, 2607 0x448c0, 0x449ac, 2608 0x449b4, 0x44a7c, 2609 0x44ac0, 0x44bac, 2610 0x44bb4, 0x44c7c, 2611 0x44cc0, 0x44dac, 2612 0x44db4, 0x44e7c, 2613 0x44ec0, 0x44fac, 2614 0x44fb4, 0x4507c, 2615 0x450c0, 0x451ac, 2616 0x451b4, 0x451fc, 2617 0x45800, 0x45804, 2618 0x45810, 0x45830, 2619 0x45840, 0x45860, 2620 0x45868, 0x45868, 2621 0x45880, 0x45884, 2622 0x458a0, 0x458b0, 2623 0x45a00, 0x45a04, 2624 0x45a10, 0x45a30, 2625 0x45a40, 0x45a60, 2626 0x45a68, 0x45a68, 2627 0x45a80, 0x45a84, 2628 0x45aa0, 0x45ab0, 2629 0x460c0, 0x460e4, 2630 0x47000, 0x4703c, 2631 0x47044, 0x4708c, 2632 0x47200, 0x47250, 2633 0x47400, 0x47408, 2634 0x47414, 0x47420, 2635 0x47600, 0x47618, 2636 0x47800, 0x47814, 2637 0x47820, 0x4782c, 2638 0x50000, 0x50084, 2639 0x50090, 0x500cc, 2640 0x50300, 0x50384, 2641 0x50400, 0x50400, 2642 0x50800, 0x50884, 2643 0x50890, 0x508cc, 2644 0x50b00, 0x50b84, 2645 0x50c00, 0x50c00, 2646 0x51000, 0x51020, 2647 0x51028, 0x510b0, 2648 0x51300, 0x51324, 2649 }; 2650 2651 static const unsigned int t6vf_reg_ranges[] = { 2652 VF_SGE_REG(A_SGE_VF_KDOORBELL), VF_SGE_REG(A_SGE_VF_GTS), 2653 VF_MPS_REG(A_MPS_VF_CTL), 2654 VF_MPS_REG(A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H), 2655 VF_PL_REG(A_PL_VF_WHOAMI), VF_PL_REG(A_PL_VF_REVISION), 2656 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_CTRL), 2657 VF_CIM_REG(A_CIM_VF_EXT_MAILBOX_STATUS), 2658 FW_T6VF_MBDATA_BASE_ADDR, 2659 FW_T6VF_MBDATA_BASE_ADDR + 2660 ((NUM_CIM_PF_MAILBOX_DATA_INSTANCES - 1) * 4), 2661 }; 2662 2663 u32 *buf_end = (u32 *)(buf + buf_size); 2664 const unsigned int *reg_ranges; 2665 int reg_ranges_size, range; 2666 unsigned int chip_version = chip_id(adap); 2667 2668 /* 2669 * Select the right set of register ranges to dump depending on the 2670 * adapter chip type. 2671 */ 2672 switch (chip_version) { 2673 case CHELSIO_T4: 2674 if (adap->flags & IS_VF) { 2675 reg_ranges = t4vf_reg_ranges; 2676 reg_ranges_size = ARRAY_SIZE(t4vf_reg_ranges); 2677 } else { 2678 reg_ranges = t4_reg_ranges; 2679 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges); 2680 } 2681 break; 2682 2683 case CHELSIO_T5: 2684 if (adap->flags & IS_VF) { 2685 reg_ranges = t5vf_reg_ranges; 2686 reg_ranges_size = ARRAY_SIZE(t5vf_reg_ranges); 2687 } else { 2688 reg_ranges = t5_reg_ranges; 2689 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges); 2690 } 2691 break; 2692 2693 case CHELSIO_T6: 2694 if (adap->flags & IS_VF) { 2695 reg_ranges = t6vf_reg_ranges; 2696 reg_ranges_size = ARRAY_SIZE(t6vf_reg_ranges); 2697 } else { 2698 reg_ranges = t6_reg_ranges; 2699 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges); 2700 } 2701 break; 2702 2703 default: 2704 CH_ERR(adap, 2705 "Unsupported chip version %d\n", chip_version); 2706 return; 2707 } 2708 2709 /* 2710 * Clear the register buffer and insert the appropriate register 2711 * values selected by the above register ranges. 2712 */ 2713 memset(buf, 0, buf_size); 2714 for (range = 0; range < reg_ranges_size; range += 2) { 2715 unsigned int reg = reg_ranges[range]; 2716 unsigned int last_reg = reg_ranges[range + 1]; 2717 u32 *bufp = (u32 *)(buf + reg); 2718 2719 /* 2720 * Iterate across the register range filling in the register 2721 * buffer but don't write past the end of the register buffer. 2722 */ 2723 while (reg <= last_reg && bufp < buf_end) { 2724 *bufp++ = t4_read_reg(adap, reg); 2725 reg += sizeof(u32); 2726 } 2727 } 2728 } 2729 2730 /* 2731 * Partial EEPROM Vital Product Data structure. The VPD starts with one ID 2732 * header followed by one or more VPD-R sections, each with its own header. 2733 */ 2734 struct t4_vpd_hdr { 2735 u8 id_tag; 2736 u8 id_len[2]; 2737 u8 id_data[ID_LEN]; 2738 }; 2739 2740 struct t4_vpdr_hdr { 2741 u8 vpdr_tag; 2742 u8 vpdr_len[2]; 2743 }; 2744 2745 /* 2746 * EEPROM reads take a few tens of us while writes can take a bit over 5 ms. 2747 */ 2748 #define EEPROM_DELAY 10 /* 10us per poll spin */ 2749 #define EEPROM_MAX_POLL 5000 /* x 5000 == 50ms */ 2750 2751 #define EEPROM_STAT_ADDR 0x7bfc 2752 #define VPD_SIZE 0x800 2753 #define VPD_BASE 0x400 2754 #define VPD_BASE_OLD 0 2755 #define VPD_LEN 1024 2756 #define VPD_INFO_FLD_HDR_SIZE 3 2757 #define CHELSIO_VPD_UNIQUE_ID 0x82 2758 2759 /* 2760 * Small utility function to wait till any outstanding VPD Access is complete. 2761 * We have a per-adapter state variable "VPD Busy" to indicate when we have a 2762 * VPD Access in flight. This allows us to handle the problem of having a 2763 * previous VPD Access time out and prevent an attempt to inject a new VPD 2764 * Request before any in-flight VPD reguest has completed. 2765 */ 2766 static int t4_seeprom_wait(struct adapter *adapter) 2767 { 2768 unsigned int base = adapter->params.pci.vpd_cap_addr; 2769 int max_poll; 2770 2771 /* 2772 * If no VPD Access is in flight, we can just return success right 2773 * away. 2774 */ 2775 if (!adapter->vpd_busy) 2776 return 0; 2777 2778 /* 2779 * Poll the VPD Capability Address/Flag register waiting for it 2780 * to indicate that the operation is complete. 2781 */ 2782 max_poll = EEPROM_MAX_POLL; 2783 do { 2784 u16 val; 2785 2786 udelay(EEPROM_DELAY); 2787 t4_os_pci_read_cfg2(adapter, base + PCI_VPD_ADDR, &val); 2788 2789 /* 2790 * If the operation is complete, mark the VPD as no longer 2791 * busy and return success. 2792 */ 2793 if ((val & PCI_VPD_ADDR_F) == adapter->vpd_flag) { 2794 adapter->vpd_busy = 0; 2795 return 0; 2796 } 2797 } while (--max_poll); 2798 2799 /* 2800 * Failure! Note that we leave the VPD Busy status set in order to 2801 * avoid pushing a new VPD Access request into the VPD Capability till 2802 * the current operation eventually succeeds. It's a bug to issue a 2803 * new request when an existing request is in flight and will result 2804 * in corrupt hardware state. 2805 */ 2806 return -ETIMEDOUT; 2807 } 2808 2809 /** 2810 * t4_seeprom_read - read a serial EEPROM location 2811 * @adapter: adapter to read 2812 * @addr: EEPROM virtual address 2813 * @data: where to store the read data 2814 * 2815 * Read a 32-bit word from a location in serial EEPROM using the card's PCI 2816 * VPD capability. Note that this function must be called with a virtual 2817 * address. 2818 */ 2819 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data) 2820 { 2821 unsigned int base = adapter->params.pci.vpd_cap_addr; 2822 int ret; 2823 2824 /* 2825 * VPD Accesses must alway be 4-byte aligned! 2826 */ 2827 if (addr >= EEPROMVSIZE || (addr & 3)) 2828 return -EINVAL; 2829 2830 /* 2831 * Wait for any previous operation which may still be in flight to 2832 * complete. 2833 */ 2834 ret = t4_seeprom_wait(adapter); 2835 if (ret) { 2836 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2837 return ret; 2838 } 2839 2840 /* 2841 * Issue our new VPD Read request, mark the VPD as being busy and wait 2842 * for our request to complete. If it doesn't complete, note the 2843 * error and return it to our caller. Note that we do not reset the 2844 * VPD Busy status! 2845 */ 2846 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, (u16)addr); 2847 adapter->vpd_busy = 1; 2848 adapter->vpd_flag = PCI_VPD_ADDR_F; 2849 ret = t4_seeprom_wait(adapter); 2850 if (ret) { 2851 CH_ERR(adapter, "VPD read of address %#x failed\n", addr); 2852 return ret; 2853 } 2854 2855 /* 2856 * Grab the returned data, swizzle it into our endianness and 2857 * return success. 2858 */ 2859 t4_os_pci_read_cfg4(adapter, base + PCI_VPD_DATA, data); 2860 *data = le32_to_cpu(*data); 2861 return 0; 2862 } 2863 2864 /** 2865 * t4_seeprom_write - write a serial EEPROM location 2866 * @adapter: adapter to write 2867 * @addr: virtual EEPROM address 2868 * @data: value to write 2869 * 2870 * Write a 32-bit word to a location in serial EEPROM using the card's PCI 2871 * VPD capability. Note that this function must be called with a virtual 2872 * address. 2873 */ 2874 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data) 2875 { 2876 unsigned int base = adapter->params.pci.vpd_cap_addr; 2877 int ret; 2878 u32 stats_reg; 2879 int max_poll; 2880 2881 /* 2882 * VPD Accesses must alway be 4-byte aligned! 2883 */ 2884 if (addr >= EEPROMVSIZE || (addr & 3)) 2885 return -EINVAL; 2886 2887 /* 2888 * Wait for any previous operation which may still be in flight to 2889 * complete. 2890 */ 2891 ret = t4_seeprom_wait(adapter); 2892 if (ret) { 2893 CH_ERR(adapter, "VPD still busy from previous operation\n"); 2894 return ret; 2895 } 2896 2897 /* 2898 * Issue our new VPD Read request, mark the VPD as being busy and wait 2899 * for our request to complete. If it doesn't complete, note the 2900 * error and return it to our caller. Note that we do not reset the 2901 * VPD Busy status! 2902 */ 2903 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 2904 cpu_to_le32(data)); 2905 t4_os_pci_write_cfg2(adapter, base + PCI_VPD_ADDR, 2906 (u16)addr | PCI_VPD_ADDR_F); 2907 adapter->vpd_busy = 1; 2908 adapter->vpd_flag = 0; 2909 ret = t4_seeprom_wait(adapter); 2910 if (ret) { 2911 CH_ERR(adapter, "VPD write of address %#x failed\n", addr); 2912 return ret; 2913 } 2914 2915 /* 2916 * Reset PCI_VPD_DATA register after a transaction and wait for our 2917 * request to complete. If it doesn't complete, return error. 2918 */ 2919 t4_os_pci_write_cfg4(adapter, base + PCI_VPD_DATA, 0); 2920 max_poll = EEPROM_MAX_POLL; 2921 do { 2922 udelay(EEPROM_DELAY); 2923 t4_seeprom_read(adapter, EEPROM_STAT_ADDR, &stats_reg); 2924 } while ((stats_reg & 0x1) && --max_poll); 2925 if (!max_poll) 2926 return -ETIMEDOUT; 2927 2928 /* Return success! */ 2929 return 0; 2930 } 2931 2932 /** 2933 * t4_eeprom_ptov - translate a physical EEPROM address to virtual 2934 * @phys_addr: the physical EEPROM address 2935 * @fn: the PCI function number 2936 * @sz: size of function-specific area 2937 * 2938 * Translate a physical EEPROM address to virtual. The first 1K is 2939 * accessed through virtual addresses starting at 31K, the rest is 2940 * accessed through virtual addresses starting at 0. 2941 * 2942 * The mapping is as follows: 2943 * [0..1K) -> [31K..32K) 2944 * [1K..1K+A) -> [ES-A..ES) 2945 * [1K+A..ES) -> [0..ES-A-1K) 2946 * 2947 * where A = @fn * @sz, and ES = EEPROM size. 2948 */ 2949 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 2950 { 2951 fn *= sz; 2952 if (phys_addr < 1024) 2953 return phys_addr + (31 << 10); 2954 if (phys_addr < 1024 + fn) 2955 return EEPROMSIZE - fn + phys_addr - 1024; 2956 if (phys_addr < EEPROMSIZE) 2957 return phys_addr - 1024 - fn; 2958 return -EINVAL; 2959 } 2960 2961 /** 2962 * t4_seeprom_wp - enable/disable EEPROM write protection 2963 * @adapter: the adapter 2964 * @enable: whether to enable or disable write protection 2965 * 2966 * Enables or disables write protection on the serial EEPROM. 2967 */ 2968 int t4_seeprom_wp(struct adapter *adapter, int enable) 2969 { 2970 return t4_seeprom_write(adapter, EEPROM_STAT_ADDR, enable ? 0xc : 0); 2971 } 2972 2973 /** 2974 * get_vpd_keyword_val - Locates an information field keyword in the VPD 2975 * @vpd: Pointer to buffered vpd data structure 2976 * @kw: The keyword to search for 2977 * @region: VPD region to search (starting from 0) 2978 * 2979 * Returns the value of the information field keyword or 2980 * -ENOENT otherwise. 2981 */ 2982 static int get_vpd_keyword_val(const u8 *vpd, const char *kw, int region) 2983 { 2984 int i, tag; 2985 unsigned int offset, len; 2986 const struct t4_vpdr_hdr *vpdr; 2987 2988 offset = sizeof(struct t4_vpd_hdr); 2989 vpdr = (const void *)(vpd + offset); 2990 tag = vpdr->vpdr_tag; 2991 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2992 while (region--) { 2993 offset += sizeof(struct t4_vpdr_hdr) + len; 2994 vpdr = (const void *)(vpd + offset); 2995 if (++tag != vpdr->vpdr_tag) 2996 return -ENOENT; 2997 len = (u16)vpdr->vpdr_len[0] + ((u16)vpdr->vpdr_len[1] << 8); 2998 } 2999 offset += sizeof(struct t4_vpdr_hdr); 3000 3001 if (offset + len > VPD_LEN) { 3002 return -ENOENT; 3003 } 3004 3005 for (i = offset; i + VPD_INFO_FLD_HDR_SIZE <= offset + len;) { 3006 if (memcmp(vpd + i , kw , 2) == 0){ 3007 i += VPD_INFO_FLD_HDR_SIZE; 3008 return i; 3009 } 3010 3011 i += VPD_INFO_FLD_HDR_SIZE + vpd[i+2]; 3012 } 3013 3014 return -ENOENT; 3015 } 3016 3017 3018 /** 3019 * get_vpd_params - read VPD parameters from VPD EEPROM 3020 * @adapter: adapter to read 3021 * @p: where to store the parameters 3022 * @vpd: caller provided temporary space to read the VPD into 3023 * 3024 * Reads card parameters stored in VPD EEPROM. 3025 */ 3026 static int get_vpd_params(struct adapter *adapter, struct vpd_params *p, 3027 uint16_t device_id, u32 *buf) 3028 { 3029 int i, ret, addr; 3030 int ec, sn, pn, na, md; 3031 u8 csum; 3032 const u8 *vpd = (const u8 *)buf; 3033 3034 /* 3035 * Card information normally starts at VPD_BASE but early cards had 3036 * it at 0. 3037 */ 3038 ret = t4_seeprom_read(adapter, VPD_BASE, buf); 3039 if (ret) 3040 return (ret); 3041 3042 /* 3043 * The VPD shall have a unique identifier specified by the PCI SIG. 3044 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD 3045 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software 3046 * is expected to automatically put this entry at the 3047 * beginning of the VPD. 3048 */ 3049 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD; 3050 3051 for (i = 0; i < VPD_LEN; i += 4) { 3052 ret = t4_seeprom_read(adapter, addr + i, buf++); 3053 if (ret) 3054 return ret; 3055 } 3056 3057 #define FIND_VPD_KW(var,name) do { \ 3058 var = get_vpd_keyword_val(vpd, name, 0); \ 3059 if (var < 0) { \ 3060 CH_ERR(adapter, "missing VPD keyword " name "\n"); \ 3061 return -EINVAL; \ 3062 } \ 3063 } while (0) 3064 3065 FIND_VPD_KW(i, "RV"); 3066 for (csum = 0; i >= 0; i--) 3067 csum += vpd[i]; 3068 3069 if (csum) { 3070 CH_ERR(adapter, 3071 "corrupted VPD EEPROM, actual csum %u\n", csum); 3072 return -EINVAL; 3073 } 3074 3075 FIND_VPD_KW(ec, "EC"); 3076 FIND_VPD_KW(sn, "SN"); 3077 FIND_VPD_KW(pn, "PN"); 3078 FIND_VPD_KW(na, "NA"); 3079 #undef FIND_VPD_KW 3080 3081 memcpy(p->id, vpd + offsetof(struct t4_vpd_hdr, id_data), ID_LEN); 3082 strstrip(p->id); 3083 memcpy(p->ec, vpd + ec, EC_LEN); 3084 strstrip(p->ec); 3085 i = vpd[sn - VPD_INFO_FLD_HDR_SIZE + 2]; 3086 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN)); 3087 strstrip(p->sn); 3088 i = vpd[pn - VPD_INFO_FLD_HDR_SIZE + 2]; 3089 memcpy(p->pn, vpd + pn, min(i, PN_LEN)); 3090 strstrip((char *)p->pn); 3091 i = vpd[na - VPD_INFO_FLD_HDR_SIZE + 2]; 3092 memcpy(p->na, vpd + na, min(i, MACADDR_LEN)); 3093 strstrip((char *)p->na); 3094 3095 if (device_id & 0x80) 3096 return 0; /* Custom card */ 3097 3098 md = get_vpd_keyword_val(vpd, "VF", 1); 3099 if (md < 0) { 3100 snprintf(p->md, sizeof(p->md), "unknown"); 3101 } else { 3102 i = vpd[md - VPD_INFO_FLD_HDR_SIZE + 2]; 3103 memcpy(p->md, vpd + md, min(i, MD_LEN)); 3104 strstrip((char *)p->md); 3105 } 3106 3107 return 0; 3108 } 3109 3110 /* serial flash and firmware constants and flash config file constants */ 3111 enum { 3112 SF_ATTEMPTS = 10, /* max retries for SF operations */ 3113 3114 /* flash command opcodes */ 3115 SF_PROG_PAGE = 2, /* program 256B page */ 3116 SF_WR_DISABLE = 4, /* disable writes */ 3117 SF_RD_STATUS = 5, /* read status register */ 3118 SF_WR_ENABLE = 6, /* enable writes */ 3119 SF_RD_DATA_FAST = 0xb, /* read flash */ 3120 SF_RD_ID = 0x9f, /* read ID */ 3121 SF_ERASE_SECTOR = 0xd8, /* erase 64KB sector */ 3122 }; 3123 3124 /** 3125 * sf1_read - read data from the serial flash 3126 * @adapter: the adapter 3127 * @byte_cnt: number of bytes to read 3128 * @cont: whether another operation will be chained 3129 * @lock: whether to lock SF for PL access only 3130 * @valp: where to store the read data 3131 * 3132 * Reads up to 4 bytes of data from the serial flash. The location of 3133 * the read needs to be specified prior to calling this by issuing the 3134 * appropriate commands to the serial flash. 3135 */ 3136 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont, 3137 int lock, u32 *valp) 3138 { 3139 int ret; 3140 3141 if (!byte_cnt || byte_cnt > 4) 3142 return -EINVAL; 3143 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3144 return -EBUSY; 3145 t4_write_reg(adapter, A_SF_OP, 3146 V_SF_LOCK(lock) | V_CONT(cont) | V_BYTECNT(byte_cnt - 1)); 3147 ret = t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3148 if (!ret) 3149 *valp = t4_read_reg(adapter, A_SF_DATA); 3150 return ret; 3151 } 3152 3153 /** 3154 * sf1_write - write data to the serial flash 3155 * @adapter: the adapter 3156 * @byte_cnt: number of bytes to write 3157 * @cont: whether another operation will be chained 3158 * @lock: whether to lock SF for PL access only 3159 * @val: value to write 3160 * 3161 * Writes up to 4 bytes of data to the serial flash. The location of 3162 * the write needs to be specified prior to calling this by issuing the 3163 * appropriate commands to the serial flash. 3164 */ 3165 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont, 3166 int lock, u32 val) 3167 { 3168 if (!byte_cnt || byte_cnt > 4) 3169 return -EINVAL; 3170 if (t4_read_reg(adapter, A_SF_OP) & F_BUSY) 3171 return -EBUSY; 3172 t4_write_reg(adapter, A_SF_DATA, val); 3173 t4_write_reg(adapter, A_SF_OP, V_SF_LOCK(lock) | 3174 V_CONT(cont) | V_BYTECNT(byte_cnt - 1) | V_OP(1)); 3175 return t4_wait_op_done(adapter, A_SF_OP, F_BUSY, 0, SF_ATTEMPTS, 5); 3176 } 3177 3178 /** 3179 * flash_wait_op - wait for a flash operation to complete 3180 * @adapter: the adapter 3181 * @attempts: max number of polls of the status register 3182 * @delay: delay between polls in ms 3183 * 3184 * Wait for a flash operation to complete by polling the status register. 3185 */ 3186 static int flash_wait_op(struct adapter *adapter, int attempts, int delay) 3187 { 3188 int ret; 3189 u32 status; 3190 3191 while (1) { 3192 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 || 3193 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0) 3194 return ret; 3195 if (!(status & 1)) 3196 return 0; 3197 if (--attempts == 0) 3198 return -EAGAIN; 3199 if (delay) 3200 msleep(delay); 3201 } 3202 } 3203 3204 /** 3205 * t4_read_flash - read words from serial flash 3206 * @adapter: the adapter 3207 * @addr: the start address for the read 3208 * @nwords: how many 32-bit words to read 3209 * @data: where to store the read data 3210 * @byte_oriented: whether to store data as bytes or as words 3211 * 3212 * Read the specified number of 32-bit words from the serial flash. 3213 * If @byte_oriented is set the read data is stored as a byte array 3214 * (i.e., big-endian), otherwise as 32-bit words in the platform's 3215 * natural endianness. 3216 */ 3217 int t4_read_flash(struct adapter *adapter, unsigned int addr, 3218 unsigned int nwords, u32 *data, int byte_oriented) 3219 { 3220 int ret; 3221 3222 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3)) 3223 return -EINVAL; 3224 3225 addr = swab32(addr) | SF_RD_DATA_FAST; 3226 3227 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 || 3228 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0) 3229 return ret; 3230 3231 for ( ; nwords; nwords--, data++) { 3232 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data); 3233 if (nwords == 1) 3234 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3235 if (ret) 3236 return ret; 3237 if (byte_oriented) 3238 *data = (__force __u32)(cpu_to_be32(*data)); 3239 } 3240 return 0; 3241 } 3242 3243 /** 3244 * t4_write_flash - write up to a page of data to the serial flash 3245 * @adapter: the adapter 3246 * @addr: the start address to write 3247 * @n: length of data to write in bytes 3248 * @data: the data to write 3249 * @byte_oriented: whether to store data as bytes or as words 3250 * 3251 * Writes up to a page of data (256 bytes) to the serial flash starting 3252 * at the given address. All the data must be written to the same page. 3253 * If @byte_oriented is set the write data is stored as byte stream 3254 * (i.e. matches what on disk), otherwise in big-endian. 3255 */ 3256 int t4_write_flash(struct adapter *adapter, unsigned int addr, 3257 unsigned int n, const u8 *data, int byte_oriented) 3258 { 3259 int ret; 3260 u32 buf[SF_PAGE_SIZE / 4]; 3261 unsigned int i, c, left, val, offset = addr & 0xff; 3262 3263 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE) 3264 return -EINVAL; 3265 3266 val = swab32(addr) | SF_PROG_PAGE; 3267 3268 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3269 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0) 3270 goto unlock; 3271 3272 for (left = n; left; left -= c) { 3273 c = min(left, 4U); 3274 for (val = 0, i = 0; i < c; ++i) 3275 val = (val << 8) + *data++; 3276 3277 if (!byte_oriented) 3278 val = cpu_to_be32(val); 3279 3280 ret = sf1_write(adapter, c, c != left, 1, val); 3281 if (ret) 3282 goto unlock; 3283 } 3284 ret = flash_wait_op(adapter, 8, 1); 3285 if (ret) 3286 goto unlock; 3287 3288 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3289 3290 /* Read the page to verify the write succeeded */ 3291 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 3292 byte_oriented); 3293 if (ret) 3294 return ret; 3295 3296 if (memcmp(data - n, (u8 *)buf + offset, n)) { 3297 CH_ERR(adapter, 3298 "failed to correctly write the flash page at %#x\n", 3299 addr); 3300 return -EIO; 3301 } 3302 return 0; 3303 3304 unlock: 3305 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3306 return ret; 3307 } 3308 3309 /** 3310 * t4_get_fw_version - read the firmware version 3311 * @adapter: the adapter 3312 * @vers: where to place the version 3313 * 3314 * Reads the FW version from flash. 3315 */ 3316 int t4_get_fw_version(struct adapter *adapter, u32 *vers) 3317 { 3318 return t4_read_flash(adapter, FLASH_FW_START + 3319 offsetof(struct fw_hdr, fw_ver), 1, 3320 vers, 0); 3321 } 3322 3323 /** 3324 * t4_get_fw_hdr - read the firmware header 3325 * @adapter: the adapter 3326 * @hdr: where to place the version 3327 * 3328 * Reads the FW header from flash into caller provided buffer. 3329 */ 3330 int t4_get_fw_hdr(struct adapter *adapter, struct fw_hdr *hdr) 3331 { 3332 return t4_read_flash(adapter, FLASH_FW_START, 3333 sizeof (*hdr) / sizeof (uint32_t), (uint32_t *)hdr, 1); 3334 } 3335 3336 /** 3337 * t4_get_bs_version - read the firmware bootstrap version 3338 * @adapter: the adapter 3339 * @vers: where to place the version 3340 * 3341 * Reads the FW Bootstrap version from flash. 3342 */ 3343 int t4_get_bs_version(struct adapter *adapter, u32 *vers) 3344 { 3345 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START + 3346 offsetof(struct fw_hdr, fw_ver), 1, 3347 vers, 0); 3348 } 3349 3350 /** 3351 * t4_get_tp_version - read the TP microcode version 3352 * @adapter: the adapter 3353 * @vers: where to place the version 3354 * 3355 * Reads the TP microcode version from flash. 3356 */ 3357 int t4_get_tp_version(struct adapter *adapter, u32 *vers) 3358 { 3359 return t4_read_flash(adapter, FLASH_FW_START + 3360 offsetof(struct fw_hdr, tp_microcode_ver), 3361 1, vers, 0); 3362 } 3363 3364 /** 3365 * t4_get_exprom_version - return the Expansion ROM version (if any) 3366 * @adapter: the adapter 3367 * @vers: where to place the version 3368 * 3369 * Reads the Expansion ROM header from FLASH and returns the version 3370 * number (if present) through the @vers return value pointer. We return 3371 * this in the Firmware Version Format since it's convenient. Return 3372 * 0 on success, -ENOENT if no Expansion ROM is present. 3373 */ 3374 int t4_get_exprom_version(struct adapter *adap, u32 *vers) 3375 { 3376 struct exprom_header { 3377 unsigned char hdr_arr[16]; /* must start with 0x55aa */ 3378 unsigned char hdr_ver[4]; /* Expansion ROM version */ 3379 } *hdr; 3380 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header), 3381 sizeof(u32))]; 3382 int ret; 3383 3384 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, 3385 ARRAY_SIZE(exprom_header_buf), exprom_header_buf, 3386 0); 3387 if (ret) 3388 return ret; 3389 3390 hdr = (struct exprom_header *)exprom_header_buf; 3391 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa) 3392 return -ENOENT; 3393 3394 *vers = (V_FW_HDR_FW_VER_MAJOR(hdr->hdr_ver[0]) | 3395 V_FW_HDR_FW_VER_MINOR(hdr->hdr_ver[1]) | 3396 V_FW_HDR_FW_VER_MICRO(hdr->hdr_ver[2]) | 3397 V_FW_HDR_FW_VER_BUILD(hdr->hdr_ver[3])); 3398 return 0; 3399 } 3400 3401 /** 3402 * t4_get_scfg_version - return the Serial Configuration version 3403 * @adapter: the adapter 3404 * @vers: where to place the version 3405 * 3406 * Reads the Serial Configuration Version via the Firmware interface 3407 * (thus this can only be called once we're ready to issue Firmware 3408 * commands). The format of the Serial Configuration version is 3409 * adapter specific. Returns 0 on success, an error on failure. 3410 * 3411 * Note that early versions of the Firmware didn't include the ability 3412 * to retrieve the Serial Configuration version, so we zero-out the 3413 * return-value parameter in that case to avoid leaving it with 3414 * garbage in it. 3415 * 3416 * Also note that the Firmware will return its cached copy of the Serial 3417 * Initialization Revision ID, not the actual Revision ID as written in 3418 * the Serial EEPROM. This is only an issue if a new VPD has been written 3419 * and the Firmware/Chip haven't yet gone through a RESET sequence. So 3420 * it's best to defer calling this routine till after a FW_RESET_CMD has 3421 * been issued if the Host Driver will be performing a full adapter 3422 * initialization. 3423 */ 3424 int t4_get_scfg_version(struct adapter *adapter, u32 *vers) 3425 { 3426 u32 scfgrev_param; 3427 int ret; 3428 3429 scfgrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3430 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_SCFGREV)); 3431 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3432 1, &scfgrev_param, vers); 3433 if (ret) 3434 *vers = 0; 3435 return ret; 3436 } 3437 3438 /** 3439 * t4_get_vpd_version - return the VPD version 3440 * @adapter: the adapter 3441 * @vers: where to place the version 3442 * 3443 * Reads the VPD via the Firmware interface (thus this can only be called 3444 * once we're ready to issue Firmware commands). The format of the 3445 * VPD version is adapter specific. Returns 0 on success, an error on 3446 * failure. 3447 * 3448 * Note that early versions of the Firmware didn't include the ability 3449 * to retrieve the VPD version, so we zero-out the return-value parameter 3450 * in that case to avoid leaving it with garbage in it. 3451 * 3452 * Also note that the Firmware will return its cached copy of the VPD 3453 * Revision ID, not the actual Revision ID as written in the Serial 3454 * EEPROM. This is only an issue if a new VPD has been written and the 3455 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best 3456 * to defer calling this routine till after a FW_RESET_CMD has been issued 3457 * if the Host Driver will be performing a full adapter initialization. 3458 */ 3459 int t4_get_vpd_version(struct adapter *adapter, u32 *vers) 3460 { 3461 u32 vpdrev_param; 3462 int ret; 3463 3464 vpdrev_param = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3465 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_VPDREV)); 3466 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0, 3467 1, &vpdrev_param, vers); 3468 if (ret) 3469 *vers = 0; 3470 return ret; 3471 } 3472 3473 /** 3474 * t4_get_version_info - extract various chip/firmware version information 3475 * @adapter: the adapter 3476 * 3477 * Reads various chip/firmware version numbers and stores them into the 3478 * adapter Adapter Parameters structure. If any of the efforts fails 3479 * the first failure will be returned, but all of the version numbers 3480 * will be read. 3481 */ 3482 int t4_get_version_info(struct adapter *adapter) 3483 { 3484 int ret = 0; 3485 3486 #define FIRST_RET(__getvinfo) \ 3487 do { \ 3488 int __ret = __getvinfo; \ 3489 if (__ret && !ret) \ 3490 ret = __ret; \ 3491 } while (0) 3492 3493 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers)); 3494 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers)); 3495 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers)); 3496 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers)); 3497 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers)); 3498 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers)); 3499 3500 #undef FIRST_RET 3501 3502 return ret; 3503 } 3504 3505 /** 3506 * t4_flash_erase_sectors - erase a range of flash sectors 3507 * @adapter: the adapter 3508 * @start: the first sector to erase 3509 * @end: the last sector to erase 3510 * 3511 * Erases the sectors in the given inclusive range. 3512 */ 3513 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end) 3514 { 3515 int ret = 0; 3516 3517 if (end >= adapter->params.sf_nsec) 3518 return -EINVAL; 3519 3520 while (start <= end) { 3521 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 || 3522 (ret = sf1_write(adapter, 4, 0, 1, 3523 SF_ERASE_SECTOR | (start << 8))) != 0 || 3524 (ret = flash_wait_op(adapter, 14, 500)) != 0) { 3525 CH_ERR(adapter, 3526 "erase of flash sector %d failed, error %d\n", 3527 start, ret); 3528 break; 3529 } 3530 start++; 3531 } 3532 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 3533 return ret; 3534 } 3535 3536 /** 3537 * t4_flash_cfg_addr - return the address of the flash configuration file 3538 * @adapter: the adapter 3539 * 3540 * Return the address within the flash where the Firmware Configuration 3541 * File is stored, or an error if the device FLASH is too small to contain 3542 * a Firmware Configuration File. 3543 */ 3544 int t4_flash_cfg_addr(struct adapter *adapter) 3545 { 3546 /* 3547 * If the device FLASH isn't large enough to hold a Firmware 3548 * Configuration File, return an error. 3549 */ 3550 if (adapter->params.sf_size < FLASH_CFG_START + FLASH_CFG_MAX_SIZE) 3551 return -ENOSPC; 3552 3553 return FLASH_CFG_START; 3554 } 3555 3556 /* 3557 * Return TRUE if the specified firmware matches the adapter. I.e. T4 3558 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead 3559 * and emit an error message for mismatched firmware to save our caller the 3560 * effort ... 3561 */ 3562 static int t4_fw_matches_chip(struct adapter *adap, 3563 const struct fw_hdr *hdr) 3564 { 3565 /* 3566 * The expression below will return FALSE for any unsupported adapter 3567 * which will keep us "honest" in the future ... 3568 */ 3569 if ((is_t4(adap) && hdr->chip == FW_HDR_CHIP_T4) || 3570 (is_t5(adap) && hdr->chip == FW_HDR_CHIP_T5) || 3571 (is_t6(adap) && hdr->chip == FW_HDR_CHIP_T6)) 3572 return 1; 3573 3574 CH_ERR(adap, 3575 "FW image (%d) is not suitable for this adapter (%d)\n", 3576 hdr->chip, chip_id(adap)); 3577 return 0; 3578 } 3579 3580 /** 3581 * t4_load_fw - download firmware 3582 * @adap: the adapter 3583 * @fw_data: the firmware image to write 3584 * @size: image size 3585 * 3586 * Write the supplied firmware image to the card's serial flash. 3587 */ 3588 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) 3589 { 3590 u32 csum; 3591 int ret, addr; 3592 unsigned int i; 3593 u8 first_page[SF_PAGE_SIZE]; 3594 const u32 *p = (const u32 *)fw_data; 3595 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; 3596 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 3597 unsigned int fw_start_sec; 3598 unsigned int fw_start; 3599 unsigned int fw_size; 3600 3601 if (ntohl(hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP) { 3602 fw_start_sec = FLASH_FWBOOTSTRAP_START_SEC; 3603 fw_start = FLASH_FWBOOTSTRAP_START; 3604 fw_size = FLASH_FWBOOTSTRAP_MAX_SIZE; 3605 } else { 3606 fw_start_sec = FLASH_FW_START_SEC; 3607 fw_start = FLASH_FW_START; 3608 fw_size = FLASH_FW_MAX_SIZE; 3609 } 3610 3611 if (!size) { 3612 CH_ERR(adap, "FW image has no data\n"); 3613 return -EINVAL; 3614 } 3615 if (size & 511) { 3616 CH_ERR(adap, 3617 "FW image size not multiple of 512 bytes\n"); 3618 return -EINVAL; 3619 } 3620 if ((unsigned int) be16_to_cpu(hdr->len512) * 512 != size) { 3621 CH_ERR(adap, 3622 "FW image size differs from size in FW header\n"); 3623 return -EINVAL; 3624 } 3625 if (size > fw_size) { 3626 CH_ERR(adap, "FW image too large, max is %u bytes\n", 3627 fw_size); 3628 return -EFBIG; 3629 } 3630 if (!t4_fw_matches_chip(adap, hdr)) 3631 return -EINVAL; 3632 3633 for (csum = 0, i = 0; i < size / sizeof(csum); i++) 3634 csum += be32_to_cpu(p[i]); 3635 3636 if (csum != 0xffffffff) { 3637 CH_ERR(adap, 3638 "corrupted firmware image, checksum %#x\n", csum); 3639 return -EINVAL; 3640 } 3641 3642 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 3643 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); 3644 if (ret) 3645 goto out; 3646 3647 /* 3648 * We write the correct version at the end so the driver can see a bad 3649 * version if the FW write fails. Start by writing a copy of the 3650 * first page with a bad version. 3651 */ 3652 memcpy(first_page, fw_data, SF_PAGE_SIZE); 3653 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff); 3654 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, 1); 3655 if (ret) 3656 goto out; 3657 3658 addr = fw_start; 3659 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 3660 addr += SF_PAGE_SIZE; 3661 fw_data += SF_PAGE_SIZE; 3662 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, 1); 3663 if (ret) 3664 goto out; 3665 } 3666 3667 ret = t4_write_flash(adap, 3668 fw_start + offsetof(struct fw_hdr, fw_ver), 3669 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver, 1); 3670 out: 3671 if (ret) 3672 CH_ERR(adap, "firmware download failed, error %d\n", 3673 ret); 3674 return ret; 3675 } 3676 3677 /** 3678 * t4_fwcache - firmware cache operation 3679 * @adap: the adapter 3680 * @op : the operation (flush or flush and invalidate) 3681 */ 3682 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) 3683 { 3684 struct fw_params_cmd c; 3685 3686 memset(&c, 0, sizeof(c)); 3687 c.op_to_vfn = 3688 cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 3689 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 3690 V_FW_PARAMS_CMD_PFN(adap->pf) | 3691 V_FW_PARAMS_CMD_VFN(0)); 3692 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 3693 c.param[0].mnem = 3694 cpu_to_be32(V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 3695 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_FWCACHE)); 3696 c.param[0].val = (__force __be32)op; 3697 3698 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); 3699 } 3700 3701 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 3702 unsigned int *pif_req_wrptr, 3703 unsigned int *pif_rsp_wrptr) 3704 { 3705 int i, j; 3706 u32 cfg, val, req, rsp; 3707 3708 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3709 if (cfg & F_LADBGEN) 3710 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3711 3712 val = t4_read_reg(adap, A_CIM_DEBUGSTS); 3713 req = G_POLADBGWRPTR(val); 3714 rsp = G_PILADBGWRPTR(val); 3715 if (pif_req_wrptr) 3716 *pif_req_wrptr = req; 3717 if (pif_rsp_wrptr) 3718 *pif_rsp_wrptr = rsp; 3719 3720 for (i = 0; i < CIM_PIFLA_SIZE; i++) { 3721 for (j = 0; j < 6; j++) { 3722 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(req) | 3723 V_PILADBGRDPTR(rsp)); 3724 *pif_req++ = t4_read_reg(adap, A_CIM_PO_LA_DEBUGDATA); 3725 *pif_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_DEBUGDATA); 3726 req++; 3727 rsp++; 3728 } 3729 req = (req + 2) & M_POLADBGRDPTR; 3730 rsp = (rsp + 2) & M_PILADBGRDPTR; 3731 } 3732 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3733 } 3734 3735 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) 3736 { 3737 u32 cfg; 3738 int i, j, idx; 3739 3740 cfg = t4_read_reg(adap, A_CIM_DEBUGCFG); 3741 if (cfg & F_LADBGEN) 3742 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg ^ F_LADBGEN); 3743 3744 for (i = 0; i < CIM_MALA_SIZE; i++) { 3745 for (j = 0; j < 5; j++) { 3746 idx = 8 * i + j; 3747 t4_write_reg(adap, A_CIM_DEBUGCFG, V_POLADBGRDPTR(idx) | 3748 V_PILADBGRDPTR(idx)); 3749 *ma_req++ = t4_read_reg(adap, A_CIM_PO_LA_MADEBUGDATA); 3750 *ma_rsp++ = t4_read_reg(adap, A_CIM_PI_LA_MADEBUGDATA); 3751 } 3752 } 3753 t4_write_reg(adap, A_CIM_DEBUGCFG, cfg); 3754 } 3755 3756 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) 3757 { 3758 unsigned int i, j; 3759 3760 for (i = 0; i < 8; i++) { 3761 u32 *p = la_buf + i; 3762 3763 t4_write_reg(adap, A_ULP_RX_LA_CTL, i); 3764 j = t4_read_reg(adap, A_ULP_RX_LA_WRPTR); 3765 t4_write_reg(adap, A_ULP_RX_LA_RDPTR, j); 3766 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8) 3767 *p = t4_read_reg(adap, A_ULP_RX_LA_RDDATA); 3768 } 3769 } 3770 3771 /** 3772 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits 3773 * @caps16: a 16-bit Port Capabilities value 3774 * 3775 * Returns the equivalent 32-bit Port Capabilities value. 3776 */ 3777 static uint32_t fwcaps16_to_caps32(uint16_t caps16) 3778 { 3779 uint32_t caps32 = 0; 3780 3781 #define CAP16_TO_CAP32(__cap) \ 3782 do { \ 3783 if (caps16 & FW_PORT_CAP_##__cap) \ 3784 caps32 |= FW_PORT_CAP32_##__cap; \ 3785 } while (0) 3786 3787 CAP16_TO_CAP32(SPEED_100M); 3788 CAP16_TO_CAP32(SPEED_1G); 3789 CAP16_TO_CAP32(SPEED_25G); 3790 CAP16_TO_CAP32(SPEED_10G); 3791 CAP16_TO_CAP32(SPEED_40G); 3792 CAP16_TO_CAP32(SPEED_100G); 3793 CAP16_TO_CAP32(FC_RX); 3794 CAP16_TO_CAP32(FC_TX); 3795 CAP16_TO_CAP32(ANEG); 3796 CAP16_TO_CAP32(FORCE_PAUSE); 3797 CAP16_TO_CAP32(MDIAUTO); 3798 CAP16_TO_CAP32(MDISTRAIGHT); 3799 CAP16_TO_CAP32(FEC_RS); 3800 CAP16_TO_CAP32(FEC_BASER_RS); 3801 CAP16_TO_CAP32(802_3_PAUSE); 3802 CAP16_TO_CAP32(802_3_ASM_DIR); 3803 3804 #undef CAP16_TO_CAP32 3805 3806 return caps32; 3807 } 3808 3809 /** 3810 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits 3811 * @caps32: a 32-bit Port Capabilities value 3812 * 3813 * Returns the equivalent 16-bit Port Capabilities value. Note that 3814 * not all 32-bit Port Capabilities can be represented in the 16-bit 3815 * Port Capabilities and some fields/values may not make it. 3816 */ 3817 static uint16_t fwcaps32_to_caps16(uint32_t caps32) 3818 { 3819 uint16_t caps16 = 0; 3820 3821 #define CAP32_TO_CAP16(__cap) \ 3822 do { \ 3823 if (caps32 & FW_PORT_CAP32_##__cap) \ 3824 caps16 |= FW_PORT_CAP_##__cap; \ 3825 } while (0) 3826 3827 CAP32_TO_CAP16(SPEED_100M); 3828 CAP32_TO_CAP16(SPEED_1G); 3829 CAP32_TO_CAP16(SPEED_10G); 3830 CAP32_TO_CAP16(SPEED_25G); 3831 CAP32_TO_CAP16(SPEED_40G); 3832 CAP32_TO_CAP16(SPEED_100G); 3833 CAP32_TO_CAP16(FC_RX); 3834 CAP32_TO_CAP16(FC_TX); 3835 CAP32_TO_CAP16(802_3_PAUSE); 3836 CAP32_TO_CAP16(802_3_ASM_DIR); 3837 CAP32_TO_CAP16(ANEG); 3838 CAP32_TO_CAP16(FORCE_PAUSE); 3839 CAP32_TO_CAP16(MDIAUTO); 3840 CAP32_TO_CAP16(MDISTRAIGHT); 3841 CAP32_TO_CAP16(FEC_RS); 3842 CAP32_TO_CAP16(FEC_BASER_RS); 3843 3844 #undef CAP32_TO_CAP16 3845 3846 return caps16; 3847 } 3848 3849 static bool 3850 is_bt(struct port_info *pi) 3851 { 3852 3853 return (pi->port_type == FW_PORT_TYPE_BT_SGMII || 3854 pi->port_type == FW_PORT_TYPE_BT_XFI || 3855 pi->port_type == FW_PORT_TYPE_BT_XAUI); 3856 } 3857 3858 /** 3859 * t4_link_l1cfg - apply link configuration to MAC/PHY 3860 * @phy: the PHY to setup 3861 * @mac: the MAC to setup 3862 * @lc: the requested link configuration 3863 * 3864 * Set up a port's MAC and PHY according to a desired link configuration. 3865 * - If the PHY can auto-negotiate first decide what to advertise, then 3866 * enable/disable auto-negotiation as desired, and reset. 3867 * - If the PHY does not auto-negotiate just reset it. 3868 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC, 3869 * otherwise do it later based on the outcome of auto-negotiation. 3870 */ 3871 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 3872 struct link_config *lc) 3873 { 3874 struct fw_port_cmd c; 3875 unsigned int mdi = V_FW_PORT_CAP32_MDI(FW_PORT_CAP32_MDI_AUTO); 3876 unsigned int aneg, fc, fec, speed, rcap; 3877 3878 fc = 0; 3879 if (lc->requested_fc & PAUSE_RX) 3880 fc |= FW_PORT_CAP32_FC_RX; 3881 if (lc->requested_fc & PAUSE_TX) 3882 fc |= FW_PORT_CAP32_FC_TX; 3883 if (!(lc->requested_fc & PAUSE_AUTONEG)) 3884 fc |= FW_PORT_CAP32_FORCE_PAUSE; 3885 3886 fec = 0; 3887 if (lc->requested_fec == FEC_AUTO) 3888 fec = lc->fec_hint; 3889 else { 3890 if (lc->requested_fec & FEC_RS) 3891 fec |= FW_PORT_CAP32_FEC_RS; 3892 if (lc->requested_fec & FEC_BASER_RS) 3893 fec |= FW_PORT_CAP32_FEC_BASER_RS; 3894 } 3895 3896 if (lc->requested_aneg == AUTONEG_DISABLE) 3897 aneg = 0; 3898 else if (lc->requested_aneg == AUTONEG_ENABLE) 3899 aneg = FW_PORT_CAP32_ANEG; 3900 else 3901 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3902 3903 if (aneg) { 3904 speed = lc->supported & V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED); 3905 } else if (lc->requested_speed != 0) 3906 speed = speed_to_fwcap(lc->requested_speed); 3907 else 3908 speed = fwcap_top_speed(lc->supported); 3909 3910 /* Force AN on for BT cards. */ 3911 if (is_bt(adap->port[port])) 3912 aneg = lc->supported & FW_PORT_CAP32_ANEG; 3913 3914 rcap = aneg | speed | fc | fec; 3915 if ((rcap | lc->supported) != lc->supported) { 3916 #ifdef INVARIANTS 3917 CH_WARN(adap, "rcap 0x%08x, pcap 0x%08x\n", rcap, 3918 lc->supported); 3919 #endif 3920 rcap &= lc->supported; 3921 } 3922 rcap |= mdi; 3923 3924 memset(&c, 0, sizeof(c)); 3925 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3926 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3927 V_FW_PORT_CMD_PORTID(port)); 3928 if (adap->params.port_caps32) { 3929 c.action_to_len16 = 3930 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG32) | 3931 FW_LEN16(c)); 3932 c.u.l1cfg32.rcap32 = cpu_to_be32(rcap); 3933 } else { 3934 c.action_to_len16 = 3935 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3936 FW_LEN16(c)); 3937 c.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap)); 3938 } 3939 3940 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 3941 } 3942 3943 /** 3944 * t4_restart_aneg - restart autonegotiation 3945 * @adap: the adapter 3946 * @mbox: mbox to use for the FW command 3947 * @port: the port id 3948 * 3949 * Restarts autonegotiation for the selected port. 3950 */ 3951 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) 3952 { 3953 struct fw_port_cmd c; 3954 3955 memset(&c, 0, sizeof(c)); 3956 c.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 3957 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 3958 V_FW_PORT_CMD_PORTID(port)); 3959 c.action_to_len16 = 3960 cpu_to_be32(V_FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) | 3961 FW_LEN16(c)); 3962 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG); 3963 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 3964 } 3965 3966 typedef void (*int_handler_t)(struct adapter *adap); 3967 3968 struct intr_info { 3969 unsigned int mask; /* bits to check in interrupt status */ 3970 const char *msg; /* message to print or NULL */ 3971 short stat_idx; /* stat counter to increment or -1 */ 3972 unsigned short fatal; /* whether the condition reported is fatal */ 3973 int_handler_t int_handler; /* platform-specific int handler */ 3974 }; 3975 3976 /** 3977 * t4_handle_intr_status - table driven interrupt handler 3978 * @adapter: the adapter that generated the interrupt 3979 * @reg: the interrupt status register to process 3980 * @acts: table of interrupt actions 3981 * 3982 * A table driven interrupt handler that applies a set of masks to an 3983 * interrupt status word and performs the corresponding actions if the 3984 * interrupts described by the mask have occurred. The actions include 3985 * optionally emitting a warning or alert message. The table is terminated 3986 * by an entry specifying mask 0. Returns the number of fatal interrupt 3987 * conditions. 3988 */ 3989 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg, 3990 const struct intr_info *acts) 3991 { 3992 int fatal = 0; 3993 unsigned int mask = 0; 3994 unsigned int status = t4_read_reg(adapter, reg); 3995 3996 for ( ; acts->mask; ++acts) { 3997 if (!(status & acts->mask)) 3998 continue; 3999 if (acts->fatal) { 4000 fatal++; 4001 CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, 4002 status & acts->mask); 4003 } else if (acts->msg) 4004 CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg, 4005 status & acts->mask); 4006 if (acts->int_handler) 4007 acts->int_handler(adapter); 4008 mask |= acts->mask; 4009 } 4010 status &= mask; 4011 if (status) /* clear processed interrupts */ 4012 t4_write_reg(adapter, reg, status); 4013 return fatal; 4014 } 4015 4016 /* 4017 * Interrupt handler for the PCIE module. 4018 */ 4019 static void pcie_intr_handler(struct adapter *adapter) 4020 { 4021 static const struct intr_info sysbus_intr_info[] = { 4022 { F_RNPP, "RXNP array parity error", -1, 1 }, 4023 { F_RPCP, "RXPC array parity error", -1, 1 }, 4024 { F_RCIP, "RXCIF array parity error", -1, 1 }, 4025 { F_RCCP, "Rx completions control array parity error", -1, 1 }, 4026 { F_RFTP, "RXFT array parity error", -1, 1 }, 4027 { 0 } 4028 }; 4029 static const struct intr_info pcie_port_intr_info[] = { 4030 { F_TPCP, "TXPC array parity error", -1, 1 }, 4031 { F_TNPP, "TXNP array parity error", -1, 1 }, 4032 { F_TFTP, "TXFT array parity error", -1, 1 }, 4033 { F_TCAP, "TXCA array parity error", -1, 1 }, 4034 { F_TCIP, "TXCIF array parity error", -1, 1 }, 4035 { F_RCAP, "RXCA array parity error", -1, 1 }, 4036 { F_OTDD, "outbound request TLP discarded", -1, 1 }, 4037 { F_RDPE, "Rx data parity error", -1, 1 }, 4038 { F_TDUE, "Tx uncorrectable data error", -1, 1 }, 4039 { 0 } 4040 }; 4041 static const struct intr_info pcie_intr_info[] = { 4042 { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, 4043 { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, 4044 { F_MSIDATAPERR, "MSI data parity error", -1, 1 }, 4045 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 4046 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 4047 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 4048 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 4049 { F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 }, 4050 { F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 }, 4051 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 4052 { F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 }, 4053 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 4054 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 4055 { F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 }, 4056 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 4057 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 4058 { F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 }, 4059 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 4060 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 4061 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 4062 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 4063 { F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 }, 4064 { F_MATAGPERR, "PCI MA tag parity error", -1, 1 }, 4065 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 4066 { F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 }, 4067 { F_RXWRPERR, "PCI Rx write parity error", -1, 1 }, 4068 { F_RPLPERR, "PCI replay buffer parity error", -1, 1 }, 4069 { F_PCIESINT, "PCI core secondary fault", -1, 1 }, 4070 { F_PCIEPINT, "PCI core primary fault", -1, 1 }, 4071 { F_UNXSPLCPLERR, "PCI unexpected split completion error", -1, 4072 0 }, 4073 { 0 } 4074 }; 4075 4076 static const struct intr_info t5_pcie_intr_info[] = { 4077 { F_MSTGRPPERR, "Master Response Read Queue parity error", 4078 -1, 1 }, 4079 { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 4080 { F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 4081 { F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 4082 { F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 4083 { F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 4084 { F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 4085 { F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 4086 -1, 1 }, 4087 { F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 4088 -1, 1 }, 4089 { F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 4090 { F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 4091 { F_CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 4092 { F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 4093 { F_DREQWRPERR, "PCI DMA channel write request parity error", 4094 -1, 1 }, 4095 { F_DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 4096 { F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 4097 { F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 4098 { F_HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 4099 { F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 4100 { F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 4101 { F_FIDPERR, "PCI FID parity error", -1, 1 }, 4102 { F_VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 4103 { F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 4104 { F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 4105 { F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 4106 -1, 1 }, 4107 { F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 4108 -1, 1 }, 4109 { F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 4110 { F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 4111 { F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 4112 { F_READRSPERR, "Outbound read error", -1, 4113 0 }, 4114 { 0 } 4115 }; 4116 4117 int fat; 4118 4119 if (is_t4(adapter)) 4120 fat = t4_handle_intr_status(adapter, 4121 A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4122 sysbus_intr_info) + 4123 t4_handle_intr_status(adapter, 4124 A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4125 pcie_port_intr_info) + 4126 t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 4127 pcie_intr_info); 4128 else 4129 fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, 4130 t5_pcie_intr_info); 4131 if (fat) 4132 t4_fatal_err(adapter); 4133 } 4134 4135 /* 4136 * TP interrupt handler. 4137 */ 4138 static void tp_intr_handler(struct adapter *adapter) 4139 { 4140 static const struct intr_info tp_intr_info[] = { 4141 { 0x3fffffff, "TP parity error", -1, 1 }, 4142 { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 4143 { 0 } 4144 }; 4145 4146 if (t4_handle_intr_status(adapter, A_TP_INT_CAUSE, tp_intr_info)) 4147 t4_fatal_err(adapter); 4148 } 4149 4150 /* 4151 * SGE interrupt handler. 4152 */ 4153 static void sge_intr_handler(struct adapter *adapter) 4154 { 4155 u64 v; 4156 u32 err; 4157 4158 static const struct intr_info sge_intr_info[] = { 4159 { F_ERR_CPL_EXCEED_IQE_SIZE, 4160 "SGE received CPL exceeding IQE size", -1, 1 }, 4161 { F_ERR_INVALID_CIDX_INC, 4162 "SGE GTS CIDX increment too large", -1, 0 }, 4163 { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 4164 { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, 4165 { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, 4166 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 4167 { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 4168 0 }, 4169 { F_ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 4170 0 }, 4171 { F_ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 4172 0 }, 4173 { F_ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 4174 0 }, 4175 { F_ERR_ING_CTXT_PRIO, 4176 "SGE too many priority ingress contexts", -1, 0 }, 4177 { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 4178 { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 4179 { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | 4180 F_ERR_PCIE_ERROR2 | F_ERR_PCIE_ERROR3, 4181 "SGE PCIe error for a DBP thread", -1, 0 }, 4182 { 0 } 4183 }; 4184 4185 static const struct intr_info t4t5_sge_intr_info[] = { 4186 { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, 4187 { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, 4188 { F_ERR_EGR_CTXT_PRIO, 4189 "SGE too many priority egress contexts", -1, 0 }, 4190 { 0 } 4191 }; 4192 4193 /* 4194 * For now, treat below interrupts as fatal so that we disable SGE and 4195 * get better debug */ 4196 static const struct intr_info t6_sge_intr_info[] = { 4197 { F_FATAL_WRE_LEN, 4198 "SGE Actual WRE packet is less than advertized length", 4199 -1, 1 }, 4200 { 0 } 4201 }; 4202 4203 v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | 4204 ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); 4205 if (v) { 4206 CH_ALERT(adapter, "SGE parity error (%#llx)\n", 4207 (unsigned long long)v); 4208 t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); 4209 t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); 4210 } 4211 4212 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info); 4213 if (chip_id(adapter) <= CHELSIO_T5) 4214 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4215 t4t5_sge_intr_info); 4216 else 4217 v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, 4218 t6_sge_intr_info); 4219 4220 err = t4_read_reg(adapter, A_SGE_ERROR_STATS); 4221 if (err & F_ERROR_QID_VALID) { 4222 CH_ERR(adapter, "SGE error for queue %u\n", G_ERROR_QID(err)); 4223 if (err & F_UNCAPTURED_ERROR) 4224 CH_ERR(adapter, "SGE UNCAPTURED_ERROR set (clearing)\n"); 4225 t4_write_reg(adapter, A_SGE_ERROR_STATS, F_ERROR_QID_VALID | 4226 F_UNCAPTURED_ERROR); 4227 } 4228 4229 if (v != 0) 4230 t4_fatal_err(adapter); 4231 } 4232 4233 #define CIM_OBQ_INTR (F_OBQULP0PARERR | F_OBQULP1PARERR | F_OBQULP2PARERR |\ 4234 F_OBQULP3PARERR | F_OBQSGEPARERR | F_OBQNCSIPARERR) 4235 #define CIM_IBQ_INTR (F_IBQTP0PARERR | F_IBQTP1PARERR | F_IBQULPPARERR |\ 4236 F_IBQSGEHIPARERR | F_IBQSGELOPARERR | F_IBQNCSIPARERR) 4237 4238 /* 4239 * CIM interrupt handler. 4240 */ 4241 static void cim_intr_handler(struct adapter *adapter) 4242 { 4243 static const struct intr_info cim_intr_info[] = { 4244 { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 4245 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 4246 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 4247 { F_MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 4248 { F_MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 4249 { F_TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 4250 { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 4251 { F_TIMER0INT, "CIM TIMER0 interrupt", -1, 1 }, 4252 { 0 } 4253 }; 4254 static const struct intr_info cim_upintr_info[] = { 4255 { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 4256 { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 4257 { F_ILLWRINT, "CIM illegal write", -1, 1 }, 4258 { F_ILLRDINT, "CIM illegal read", -1, 1 }, 4259 { F_ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 4260 { F_ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 4261 { F_SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 4262 { F_SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 4263 { F_BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 4264 { F_SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 4265 { F_SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 4266 { F_BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 4267 { F_SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 4268 { F_SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 4269 { F_BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 4270 { F_BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 4271 { F_SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 4272 { F_SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 4273 { F_BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 4274 { F_BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 4275 { F_SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 4276 { F_SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 4277 { F_BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 4278 { F_BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 4279 { F_REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 4280 { F_RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 4281 { F_TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 4282 { F_TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 4283 { 0 } 4284 }; 4285 u32 val, fw_err; 4286 int fat; 4287 4288 fw_err = t4_read_reg(adapter, A_PCIE_FW); 4289 if (fw_err & F_PCIE_FW_ERR) 4290 t4_report_fw_error(adapter); 4291 4292 /* When the Firmware detects an internal error which normally wouldn't 4293 * raise a Host Interrupt, it forces a CIM Timer0 interrupt in order 4294 * to make sure the Host sees the Firmware Crash. So if we have a 4295 * Timer0 interrupt and don't see a Firmware Crash, ignore the Timer0 4296 * interrupt. 4297 */ 4298 val = t4_read_reg(adapter, A_CIM_HOST_INT_CAUSE); 4299 if (val & F_TIMER0INT) 4300 if (!(fw_err & F_PCIE_FW_ERR) || 4301 (G_PCIE_FW_EVAL(fw_err) != PCIE_FW_EVAL_CRASH)) 4302 t4_write_reg(adapter, A_CIM_HOST_INT_CAUSE, 4303 F_TIMER0INT); 4304 4305 fat = t4_handle_intr_status(adapter, A_CIM_HOST_INT_CAUSE, 4306 cim_intr_info) + 4307 t4_handle_intr_status(adapter, A_CIM_HOST_UPACC_INT_CAUSE, 4308 cim_upintr_info); 4309 if (fat) 4310 t4_fatal_err(adapter); 4311 } 4312 4313 /* 4314 * ULP RX interrupt handler. 4315 */ 4316 static void ulprx_intr_handler(struct adapter *adapter) 4317 { 4318 static const struct intr_info ulprx_intr_info[] = { 4319 { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 }, 4320 { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 }, 4321 { 0x7fffff, "ULPRX parity error", -1, 1 }, 4322 { 0 } 4323 }; 4324 4325 if (t4_handle_intr_status(adapter, A_ULP_RX_INT_CAUSE, ulprx_intr_info)) 4326 t4_fatal_err(adapter); 4327 } 4328 4329 /* 4330 * ULP TX interrupt handler. 4331 */ 4332 static void ulptx_intr_handler(struct adapter *adapter) 4333 { 4334 static const struct intr_info ulptx_intr_info[] = { 4335 { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 4336 0 }, 4337 { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 4338 0 }, 4339 { F_PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 4340 0 }, 4341 { F_PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 4342 0 }, 4343 { 0xfffffff, "ULPTX parity error", -1, 1 }, 4344 { 0 } 4345 }; 4346 4347 if (t4_handle_intr_status(adapter, A_ULP_TX_INT_CAUSE, ulptx_intr_info)) 4348 t4_fatal_err(adapter); 4349 } 4350 4351 /* 4352 * PM TX interrupt handler. 4353 */ 4354 static void pmtx_intr_handler(struct adapter *adapter) 4355 { 4356 static const struct intr_info pmtx_intr_info[] = { 4357 { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 4358 { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 4359 { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 4360 { F_ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 4361 { 0xffffff0, "PMTX framing error", -1, 1 }, 4362 { F_OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 4363 { F_DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 4364 1 }, 4365 { F_ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 4366 { F_C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 4367 { 0 } 4368 }; 4369 4370 if (t4_handle_intr_status(adapter, A_PM_TX_INT_CAUSE, pmtx_intr_info)) 4371 t4_fatal_err(adapter); 4372 } 4373 4374 /* 4375 * PM RX interrupt handler. 4376 */ 4377 static void pmrx_intr_handler(struct adapter *adapter) 4378 { 4379 static const struct intr_info pmrx_intr_info[] = { 4380 { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 4381 { 0x3ffff0, "PMRX framing error", -1, 1 }, 4382 { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 4383 { F_DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 4384 1 }, 4385 { F_IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 4386 { F_E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 4387 { 0 } 4388 }; 4389 4390 if (t4_handle_intr_status(adapter, A_PM_RX_INT_CAUSE, pmrx_intr_info)) 4391 t4_fatal_err(adapter); 4392 } 4393 4394 /* 4395 * CPL switch interrupt handler. 4396 */ 4397 static void cplsw_intr_handler(struct adapter *adapter) 4398 { 4399 static const struct intr_info cplsw_intr_info[] = { 4400 { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 4401 { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 4402 { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 4403 { F_SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 4404 { F_CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 4405 { F_ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 4406 { 0 } 4407 }; 4408 4409 if (t4_handle_intr_status(adapter, A_CPL_INTR_CAUSE, cplsw_intr_info)) 4410 t4_fatal_err(adapter); 4411 } 4412 4413 /* 4414 * LE interrupt handler. 4415 */ 4416 static void le_intr_handler(struct adapter *adap) 4417 { 4418 unsigned int chip_ver = chip_id(adap); 4419 static const struct intr_info le_intr_info[] = { 4420 { F_LIPMISS, "LE LIP miss", -1, 0 }, 4421 { F_LIP0, "LE 0 LIP error", -1, 0 }, 4422 { F_PARITYERR, "LE parity error", -1, 1 }, 4423 { F_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4424 { F_REQQPARERR, "LE request queue parity error", -1, 1 }, 4425 { 0 } 4426 }; 4427 4428 static const struct intr_info t6_le_intr_info[] = { 4429 { F_T6_LIPMISS, "LE LIP miss", -1, 0 }, 4430 { F_T6_LIP0, "LE 0 LIP error", -1, 0 }, 4431 { F_TCAMINTPERR, "LE parity error", -1, 1 }, 4432 { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 }, 4433 { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 }, 4434 { 0 } 4435 }; 4436 4437 if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, 4438 (chip_ver <= CHELSIO_T5) ? 4439 le_intr_info : t6_le_intr_info)) 4440 t4_fatal_err(adap); 4441 } 4442 4443 /* 4444 * MPS interrupt handler. 4445 */ 4446 static void mps_intr_handler(struct adapter *adapter) 4447 { 4448 static const struct intr_info mps_rx_intr_info[] = { 4449 { 0xffffff, "MPS Rx parity error", -1, 1 }, 4450 { 0 } 4451 }; 4452 static const struct intr_info mps_tx_intr_info[] = { 4453 { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 }, 4454 { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 4455 { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error", 4456 -1, 1 }, 4457 { V_TXDESCFIFO(M_TXDESCFIFO), "MPS Tx desc FIFO parity error", 4458 -1, 1 }, 4459 { F_BUBBLE, "MPS Tx underflow", -1, 1 }, 4460 { F_SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 4461 { F_FRMERR, "MPS Tx framing error", -1, 1 }, 4462 { 0 } 4463 }; 4464 static const struct intr_info mps_trc_intr_info[] = { 4465 { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 }, 4466 { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1, 4467 1 }, 4468 { F_MISCPERR, "MPS TRC misc parity error", -1, 1 }, 4469 { 0 } 4470 }; 4471 static const struct intr_info mps_stat_sram_intr_info[] = { 4472 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, 4473 { 0 } 4474 }; 4475 static const struct intr_info mps_stat_tx_intr_info[] = { 4476 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, 4477 { 0 } 4478 }; 4479 static const struct intr_info mps_stat_rx_intr_info[] = { 4480 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, 4481 { 0 } 4482 }; 4483 static const struct intr_info mps_cls_intr_info[] = { 4484 { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 4485 { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 4486 { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 4487 { 0 } 4488 }; 4489 4490 int fat; 4491 4492 fat = t4_handle_intr_status(adapter, A_MPS_RX_PERR_INT_CAUSE, 4493 mps_rx_intr_info) + 4494 t4_handle_intr_status(adapter, A_MPS_TX_INT_CAUSE, 4495 mps_tx_intr_info) + 4496 t4_handle_intr_status(adapter, A_MPS_TRC_INT_CAUSE, 4497 mps_trc_intr_info) + 4498 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_SRAM, 4499 mps_stat_sram_intr_info) + 4500 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 4501 mps_stat_tx_intr_info) + 4502 t4_handle_intr_status(adapter, A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 4503 mps_stat_rx_intr_info) + 4504 t4_handle_intr_status(adapter, A_MPS_CLS_INT_CAUSE, 4505 mps_cls_intr_info); 4506 4507 t4_write_reg(adapter, A_MPS_INT_CAUSE, 0); 4508 t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ 4509 if (fat) 4510 t4_fatal_err(adapter); 4511 } 4512 4513 #define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \ 4514 F_ECC_UE_INT_CAUSE) 4515 4516 /* 4517 * EDC/MC interrupt handler. 4518 */ 4519 static void mem_intr_handler(struct adapter *adapter, int idx) 4520 { 4521 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; 4522 4523 unsigned int addr, cnt_addr, v; 4524 4525 if (idx <= MEM_EDC1) { 4526 addr = EDC_REG(A_EDC_INT_CAUSE, idx); 4527 cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); 4528 } else if (idx == MEM_MC) { 4529 if (is_t4(adapter)) { 4530 addr = A_MC_INT_CAUSE; 4531 cnt_addr = A_MC_ECC_STATUS; 4532 } else { 4533 addr = A_MC_P_INT_CAUSE; 4534 cnt_addr = A_MC_P_ECC_STATUS; 4535 } 4536 } else { 4537 addr = MC_REG(A_MC_P_INT_CAUSE, 1); 4538 cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1); 4539 } 4540 4541 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; 4542 if (v & F_PERR_INT_CAUSE) 4543 CH_ALERT(adapter, "%s FIFO parity error\n", 4544 name[idx]); 4545 if (v & F_ECC_CE_INT_CAUSE) { 4546 u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); 4547 4548 if (idx <= MEM_EDC1) 4549 t4_edc_err_read(adapter, idx); 4550 4551 t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); 4552 CH_WARN_RATELIMIT(adapter, 4553 "%u %s correctable ECC data error%s\n", 4554 cnt, name[idx], cnt > 1 ? "s" : ""); 4555 } 4556 if (v & F_ECC_UE_INT_CAUSE) 4557 CH_ALERT(adapter, 4558 "%s uncorrectable ECC data error\n", name[idx]); 4559 4560 t4_write_reg(adapter, addr, v); 4561 if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE)) 4562 t4_fatal_err(adapter); 4563 } 4564 4565 /* 4566 * MA interrupt handler. 4567 */ 4568 static void ma_intr_handler(struct adapter *adapter) 4569 { 4570 u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); 4571 4572 if (status & F_MEM_PERR_INT_CAUSE) { 4573 CH_ALERT(adapter, 4574 "MA parity error, parity status %#x\n", 4575 t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); 4576 if (is_t5(adapter)) 4577 CH_ALERT(adapter, 4578 "MA parity error, parity status %#x\n", 4579 t4_read_reg(adapter, 4580 A_MA_PARITY_ERROR_STATUS2)); 4581 } 4582 if (status & F_MEM_WRAP_INT_CAUSE) { 4583 v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); 4584 CH_ALERT(adapter, "MA address wrap-around error by " 4585 "client %u to address %#x\n", 4586 G_MEM_WRAP_CLIENT_NUM(v), 4587 G_MEM_WRAP_ADDRESS(v) << 4); 4588 } 4589 t4_write_reg(adapter, A_MA_INT_CAUSE, status); 4590 t4_fatal_err(adapter); 4591 } 4592 4593 /* 4594 * SMB interrupt handler. 4595 */ 4596 static void smb_intr_handler(struct adapter *adap) 4597 { 4598 static const struct intr_info smb_intr_info[] = { 4599 { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 4600 { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 4601 { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 4602 { 0 } 4603 }; 4604 4605 if (t4_handle_intr_status(adap, A_SMB_INT_CAUSE, smb_intr_info)) 4606 t4_fatal_err(adap); 4607 } 4608 4609 /* 4610 * NC-SI interrupt handler. 4611 */ 4612 static void ncsi_intr_handler(struct adapter *adap) 4613 { 4614 static const struct intr_info ncsi_intr_info[] = { 4615 { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 4616 { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 4617 { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 4618 { F_RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 4619 { 0 } 4620 }; 4621 4622 if (t4_handle_intr_status(adap, A_NCSI_INT_CAUSE, ncsi_intr_info)) 4623 t4_fatal_err(adap); 4624 } 4625 4626 /* 4627 * XGMAC interrupt handler. 4628 */ 4629 static void xgmac_intr_handler(struct adapter *adap, int port) 4630 { 4631 u32 v, int_cause_reg; 4632 4633 if (is_t4(adap)) 4634 int_cause_reg = PORT_REG(port, A_XGMAC_PORT_INT_CAUSE); 4635 else 4636 int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); 4637 4638 v = t4_read_reg(adap, int_cause_reg); 4639 4640 v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); 4641 if (!v) 4642 return; 4643 4644 if (v & F_TXFIFO_PRTY_ERR) 4645 CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", 4646 port); 4647 if (v & F_RXFIFO_PRTY_ERR) 4648 CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", 4649 port); 4650 t4_write_reg(adap, int_cause_reg, v); 4651 t4_fatal_err(adap); 4652 } 4653 4654 /* 4655 * PL interrupt handler. 4656 */ 4657 static void pl_intr_handler(struct adapter *adap) 4658 { 4659 static const struct intr_info pl_intr_info[] = { 4660 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4661 { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 4662 { 0 } 4663 }; 4664 4665 static const struct intr_info t5_pl_intr_info[] = { 4666 { F_FATALPERR, "Fatal parity error", -1, 1 }, 4667 { 0 } 4668 }; 4669 4670 if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, 4671 is_t4(adap) ? 4672 pl_intr_info : t5_pl_intr_info)) 4673 t4_fatal_err(adap); 4674 } 4675 4676 #define PF_INTR_MASK (F_PFSW | F_PFCIM) 4677 4678 /** 4679 * t4_slow_intr_handler - control path interrupt handler 4680 * @adapter: the adapter 4681 * 4682 * T4 interrupt handler for non-data global interrupt events, e.g., errors. 4683 * The designation 'slow' is because it involves register reads, while 4684 * data interrupts typically don't involve any MMIOs. 4685 */ 4686 int t4_slow_intr_handler(struct adapter *adapter) 4687 { 4688 u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE); 4689 4690 if (!(cause & GLBL_INTR_MASK)) 4691 return 0; 4692 if (cause & F_CIM) 4693 cim_intr_handler(adapter); 4694 if (cause & F_MPS) 4695 mps_intr_handler(adapter); 4696 if (cause & F_NCSI) 4697 ncsi_intr_handler(adapter); 4698 if (cause & F_PL) 4699 pl_intr_handler(adapter); 4700 if (cause & F_SMB) 4701 smb_intr_handler(adapter); 4702 if (cause & F_MAC0) 4703 xgmac_intr_handler(adapter, 0); 4704 if (cause & F_MAC1) 4705 xgmac_intr_handler(adapter, 1); 4706 if (cause & F_MAC2) 4707 xgmac_intr_handler(adapter, 2); 4708 if (cause & F_MAC3) 4709 xgmac_intr_handler(adapter, 3); 4710 if (cause & F_PCIE) 4711 pcie_intr_handler(adapter); 4712 if (cause & F_MC0) 4713 mem_intr_handler(adapter, MEM_MC); 4714 if (is_t5(adapter) && (cause & F_MC1)) 4715 mem_intr_handler(adapter, MEM_MC1); 4716 if (cause & F_EDC0) 4717 mem_intr_handler(adapter, MEM_EDC0); 4718 if (cause & F_EDC1) 4719 mem_intr_handler(adapter, MEM_EDC1); 4720 if (cause & F_LE) 4721 le_intr_handler(adapter); 4722 if (cause & F_TP) 4723 tp_intr_handler(adapter); 4724 if (cause & F_MA) 4725 ma_intr_handler(adapter); 4726 if (cause & F_PM_TX) 4727 pmtx_intr_handler(adapter); 4728 if (cause & F_PM_RX) 4729 pmrx_intr_handler(adapter); 4730 if (cause & F_ULP_RX) 4731 ulprx_intr_handler(adapter); 4732 if (cause & F_CPL_SWITCH) 4733 cplsw_intr_handler(adapter); 4734 if (cause & F_SGE) 4735 sge_intr_handler(adapter); 4736 if (cause & F_ULP_TX) 4737 ulptx_intr_handler(adapter); 4738 4739 /* Clear the interrupts just processed for which we are the master. */ 4740 t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK); 4741 (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4742 return 1; 4743 } 4744 4745 /** 4746 * t4_intr_enable - enable interrupts 4747 * @adapter: the adapter whose interrupts should be enabled 4748 * 4749 * Enable PF-specific interrupts for the calling function and the top-level 4750 * interrupt concentrator for global interrupts. Interrupts are already 4751 * enabled at each module, here we just enable the roots of the interrupt 4752 * hierarchies. 4753 * 4754 * Note: this function should be called only when the driver manages 4755 * non PF-specific interrupts from the various HW modules. Only one PCI 4756 * function at a time should be doing this. 4757 */ 4758 void t4_intr_enable(struct adapter *adapter) 4759 { 4760 u32 val = 0; 4761 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4762 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4763 ? G_SOURCEPF(whoami) 4764 : G_T6_SOURCEPF(whoami)); 4765 4766 if (chip_id(adapter) <= CHELSIO_T5) 4767 val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; 4768 else 4769 val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; 4770 t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE | 4771 F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 | 4772 F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR | 4773 F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 | 4774 F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | 4775 F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | 4776 F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val); 4777 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); 4778 t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf); 4779 } 4780 4781 /** 4782 * t4_intr_disable - disable interrupts 4783 * @adapter: the adapter whose interrupts should be disabled 4784 * 4785 * Disable interrupts. We only disable the top-level interrupt 4786 * concentrators. The caller must be a PCI function managing global 4787 * interrupts. 4788 */ 4789 void t4_intr_disable(struct adapter *adapter) 4790 { 4791 u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); 4792 u32 pf = (chip_id(adapter) <= CHELSIO_T5 4793 ? G_SOURCEPF(whoami) 4794 : G_T6_SOURCEPF(whoami)); 4795 4796 t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0); 4797 t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0); 4798 } 4799 4800 /** 4801 * t4_intr_clear - clear all interrupts 4802 * @adapter: the adapter whose interrupts should be cleared 4803 * 4804 * Clears all interrupts. The caller must be a PCI function managing 4805 * global interrupts. 4806 */ 4807 void t4_intr_clear(struct adapter *adapter) 4808 { 4809 static const unsigned int cause_reg[] = { 4810 A_SGE_INT_CAUSE1, A_SGE_INT_CAUSE2, A_SGE_INT_CAUSE3, 4811 A_PCIE_NONFAT_ERR, A_PCIE_INT_CAUSE, 4812 A_MA_INT_WRAP_STATUS, A_MA_PARITY_ERROR_STATUS1, A_MA_INT_CAUSE, 4813 A_EDC_INT_CAUSE, EDC_REG(A_EDC_INT_CAUSE, 1), 4814 A_CIM_HOST_INT_CAUSE, A_CIM_HOST_UPACC_INT_CAUSE, 4815 MYPF_REG(A_CIM_PF_HOST_INT_CAUSE), 4816 A_TP_INT_CAUSE, 4817 A_ULP_RX_INT_CAUSE, A_ULP_TX_INT_CAUSE, 4818 A_PM_RX_INT_CAUSE, A_PM_TX_INT_CAUSE, 4819 A_MPS_RX_PERR_INT_CAUSE, 4820 A_CPL_INTR_CAUSE, 4821 MYPF_REG(A_PL_PF_INT_CAUSE), 4822 A_PL_PL_INT_CAUSE, 4823 A_LE_DB_INT_CAUSE, 4824 }; 4825 4826 unsigned int i; 4827 4828 for (i = 0; i < ARRAY_SIZE(cause_reg); ++i) 4829 t4_write_reg(adapter, cause_reg[i], 0xffffffff); 4830 4831 t4_write_reg(adapter, is_t4(adapter) ? A_MC_INT_CAUSE : 4832 A_MC_P_INT_CAUSE, 0xffffffff); 4833 4834 if (is_t4(adapter)) { 4835 t4_write_reg(adapter, A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 4836 0xffffffff); 4837 t4_write_reg(adapter, A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 4838 0xffffffff); 4839 } else 4840 t4_write_reg(adapter, A_MA_PARITY_ERROR_STATUS2, 0xffffffff); 4841 4842 t4_write_reg(adapter, A_PL_INT_CAUSE, GLBL_INTR_MASK); 4843 (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ 4844 } 4845 4846 /** 4847 * hash_mac_addr - return the hash value of a MAC address 4848 * @addr: the 48-bit Ethernet MAC address 4849 * 4850 * Hashes a MAC address according to the hash function used by HW inexact 4851 * (hash) address matching. 4852 */ 4853 static int hash_mac_addr(const u8 *addr) 4854 { 4855 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2]; 4856 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5]; 4857 a ^= b; 4858 a ^= (a >> 12); 4859 a ^= (a >> 6); 4860 return a & 0x3f; 4861 } 4862 4863 /** 4864 * t4_config_rss_range - configure a portion of the RSS mapping table 4865 * @adapter: the adapter 4866 * @mbox: mbox to use for the FW command 4867 * @viid: virtual interface whose RSS subtable is to be written 4868 * @start: start entry in the table to write 4869 * @n: how many table entries to write 4870 * @rspq: values for the "response queue" (Ingress Queue) lookup table 4871 * @nrspq: number of values in @rspq 4872 * 4873 * Programs the selected part of the VI's RSS mapping table with the 4874 * provided values. If @nrspq < @n the supplied values are used repeatedly 4875 * until the full table range is populated. 4876 * 4877 * The caller must ensure the values in @rspq are in the range allowed for 4878 * @viid. 4879 */ 4880 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 4881 int start, int n, const u16 *rspq, unsigned int nrspq) 4882 { 4883 int ret; 4884 const u16 *rsp = rspq; 4885 const u16 *rsp_end = rspq + nrspq; 4886 struct fw_rss_ind_tbl_cmd cmd; 4887 4888 memset(&cmd, 0, sizeof(cmd)); 4889 cmd.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_IND_TBL_CMD) | 4890 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 4891 V_FW_RSS_IND_TBL_CMD_VIID(viid)); 4892 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 4893 4894 /* 4895 * Each firmware RSS command can accommodate up to 32 RSS Ingress 4896 * Queue Identifiers. These Ingress Queue IDs are packed three to 4897 * a 32-bit word as 10-bit values with the upper remaining 2 bits 4898 * reserved. 4899 */ 4900 while (n > 0) { 4901 int nq = min(n, 32); 4902 int nq_packed = 0; 4903 __be32 *qp = &cmd.iq0_to_iq2; 4904 4905 /* 4906 * Set up the firmware RSS command header to send the next 4907 * "nq" Ingress Queue IDs to the firmware. 4908 */ 4909 cmd.niqid = cpu_to_be16(nq); 4910 cmd.startidx = cpu_to_be16(start); 4911 4912 /* 4913 * "nq" more done for the start of the next loop. 4914 */ 4915 start += nq; 4916 n -= nq; 4917 4918 /* 4919 * While there are still Ingress Queue IDs to stuff into the 4920 * current firmware RSS command, retrieve them from the 4921 * Ingress Queue ID array and insert them into the command. 4922 */ 4923 while (nq > 0) { 4924 /* 4925 * Grab up to the next 3 Ingress Queue IDs (wrapping 4926 * around the Ingress Queue ID array if necessary) and 4927 * insert them into the firmware RSS command at the 4928 * current 3-tuple position within the commad. 4929 */ 4930 u16 qbuf[3]; 4931 u16 *qbp = qbuf; 4932 int nqbuf = min(3, nq); 4933 4934 nq -= nqbuf; 4935 qbuf[0] = qbuf[1] = qbuf[2] = 0; 4936 while (nqbuf && nq_packed < 32) { 4937 nqbuf--; 4938 nq_packed++; 4939 *qbp++ = *rsp++; 4940 if (rsp >= rsp_end) 4941 rsp = rspq; 4942 } 4943 *qp++ = cpu_to_be32(V_FW_RSS_IND_TBL_CMD_IQ0(qbuf[0]) | 4944 V_FW_RSS_IND_TBL_CMD_IQ1(qbuf[1]) | 4945 V_FW_RSS_IND_TBL_CMD_IQ2(qbuf[2])); 4946 } 4947 4948 /* 4949 * Send this portion of the RRS table update to the firmware; 4950 * bail out on any errors. 4951 */ 4952 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL); 4953 if (ret) 4954 return ret; 4955 } 4956 return 0; 4957 } 4958 4959 /** 4960 * t4_config_glbl_rss - configure the global RSS mode 4961 * @adapter: the adapter 4962 * @mbox: mbox to use for the FW command 4963 * @mode: global RSS mode 4964 * @flags: mode-specific flags 4965 * 4966 * Sets the global RSS mode. 4967 */ 4968 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 4969 unsigned int flags) 4970 { 4971 struct fw_rss_glb_config_cmd c; 4972 4973 memset(&c, 0, sizeof(c)); 4974 c.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) | 4975 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 4976 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 4977 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) { 4978 c.u.manual.mode_pkd = 4979 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4980 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) { 4981 c.u.basicvirtual.mode_keymode = 4982 cpu_to_be32(V_FW_RSS_GLB_CONFIG_CMD_MODE(mode)); 4983 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags); 4984 } else 4985 return -EINVAL; 4986 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 4987 } 4988 4989 /** 4990 * t4_config_vi_rss - configure per VI RSS settings 4991 * @adapter: the adapter 4992 * @mbox: mbox to use for the FW command 4993 * @viid: the VI id 4994 * @flags: RSS flags 4995 * @defq: id of the default RSS queue for the VI. 4996 * @skeyidx: RSS secret key table index for non-global mode 4997 * @skey: RSS vf_scramble key for VI. 4998 * 4999 * Configures VI-specific RSS properties. 5000 */ 5001 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 5002 unsigned int flags, unsigned int defq, unsigned int skeyidx, 5003 unsigned int skey) 5004 { 5005 struct fw_rss_vi_config_cmd c; 5006 5007 memset(&c, 0, sizeof(c)); 5008 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) | 5009 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 5010 V_FW_RSS_VI_CONFIG_CMD_VIID(viid)); 5011 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 5012 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags | 5013 V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(defq)); 5014 c.u.basicvirtual.secretkeyidx_pkd = cpu_to_be32( 5015 V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(skeyidx)); 5016 c.u.basicvirtual.secretkeyxor = cpu_to_be32(skey); 5017 5018 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL); 5019 } 5020 5021 /* Read an RSS table row */ 5022 static int rd_rss_row(struct adapter *adap, int row, u32 *val) 5023 { 5024 t4_write_reg(adap, A_TP_RSS_LKP_TABLE, 0xfff00000 | row); 5025 return t4_wait_op_done_val(adap, A_TP_RSS_LKP_TABLE, F_LKPTBLROWVLD, 1, 5026 5, 0, val); 5027 } 5028 5029 /** 5030 * t4_read_rss - read the contents of the RSS mapping table 5031 * @adapter: the adapter 5032 * @map: holds the contents of the RSS mapping table 5033 * 5034 * Reads the contents of the RSS hash->queue mapping table. 5035 */ 5036 int t4_read_rss(struct adapter *adapter, u16 *map) 5037 { 5038 u32 val; 5039 int i, ret; 5040 5041 for (i = 0; i < RSS_NENTRIES / 2; ++i) { 5042 ret = rd_rss_row(adapter, i, &val); 5043 if (ret) 5044 return ret; 5045 *map++ = G_LKPTBLQUEUE0(val); 5046 *map++ = G_LKPTBLQUEUE1(val); 5047 } 5048 return 0; 5049 } 5050 5051 /** 5052 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST 5053 * @adap: the adapter 5054 * @cmd: TP fw ldst address space type 5055 * @vals: where the indirect register values are stored/written 5056 * @nregs: how many indirect registers to read/write 5057 * @start_idx: index of first indirect register to read/write 5058 * @rw: Read (1) or Write (0) 5059 * @sleep_ok: if true we may sleep while awaiting command completion 5060 * 5061 * Access TP indirect registers through LDST 5062 **/ 5063 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals, 5064 unsigned int nregs, unsigned int start_index, 5065 unsigned int rw, bool sleep_ok) 5066 { 5067 int ret = 0; 5068 unsigned int i; 5069 struct fw_ldst_cmd c; 5070 5071 for (i = 0; i < nregs; i++) { 5072 memset(&c, 0, sizeof(c)); 5073 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 5074 F_FW_CMD_REQUEST | 5075 (rw ? F_FW_CMD_READ : 5076 F_FW_CMD_WRITE) | 5077 V_FW_LDST_CMD_ADDRSPACE(cmd)); 5078 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 5079 5080 c.u.addrval.addr = cpu_to_be32(start_index + i); 5081 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]); 5082 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, 5083 sleep_ok); 5084 if (ret) 5085 return ret; 5086 5087 if (rw) 5088 vals[i] = be32_to_cpu(c.u.addrval.val); 5089 } 5090 return 0; 5091 } 5092 5093 /** 5094 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor 5095 * @adap: the adapter 5096 * @reg_addr: Address Register 5097 * @reg_data: Data register 5098 * @buff: where the indirect register values are stored/written 5099 * @nregs: how many indirect registers to read/write 5100 * @start_index: index of first indirect register to read/write 5101 * @rw: READ(1) or WRITE(0) 5102 * @sleep_ok: if true we may sleep while awaiting command completion 5103 * 5104 * Read/Write TP indirect registers through LDST if possible. 5105 * Else, use backdoor access 5106 **/ 5107 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data, 5108 u32 *buff, u32 nregs, u32 start_index, int rw, 5109 bool sleep_ok) 5110 { 5111 int rc = -EINVAL; 5112 int cmd; 5113 5114 switch (reg_addr) { 5115 case A_TP_PIO_ADDR: 5116 cmd = FW_LDST_ADDRSPC_TP_PIO; 5117 break; 5118 case A_TP_TM_PIO_ADDR: 5119 cmd = FW_LDST_ADDRSPC_TP_TM_PIO; 5120 break; 5121 case A_TP_MIB_INDEX: 5122 cmd = FW_LDST_ADDRSPC_TP_MIB; 5123 break; 5124 default: 5125 goto indirect_access; 5126 } 5127 5128 if (t4_use_ldst(adap)) 5129 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw, 5130 sleep_ok); 5131 5132 indirect_access: 5133 5134 if (rc) { 5135 if (rw) 5136 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs, 5137 start_index); 5138 else 5139 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs, 5140 start_index); 5141 } 5142 } 5143 5144 /** 5145 * t4_tp_pio_read - Read TP PIO registers 5146 * @adap: the adapter 5147 * @buff: where the indirect register values are written 5148 * @nregs: how many indirect registers to read 5149 * @start_index: index of first indirect register to read 5150 * @sleep_ok: if true we may sleep while awaiting command completion 5151 * 5152 * Read TP PIO Registers 5153 **/ 5154 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5155 u32 start_index, bool sleep_ok) 5156 { 5157 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, buff, nregs, 5158 start_index, 1, sleep_ok); 5159 } 5160 5161 /** 5162 * t4_tp_pio_write - Write TP PIO registers 5163 * @adap: the adapter 5164 * @buff: where the indirect register values are stored 5165 * @nregs: how many indirect registers to write 5166 * @start_index: index of first indirect register to write 5167 * @sleep_ok: if true we may sleep while awaiting command completion 5168 * 5169 * Write TP PIO Registers 5170 **/ 5171 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 5172 u32 start_index, bool sleep_ok) 5173 { 5174 t4_tp_indirect_rw(adap, A_TP_PIO_ADDR, A_TP_PIO_DATA, 5175 __DECONST(u32 *, buff), nregs, start_index, 0, sleep_ok); 5176 } 5177 5178 /** 5179 * t4_tp_tm_pio_read - Read TP TM PIO registers 5180 * @adap: the adapter 5181 * @buff: where the indirect register values are written 5182 * @nregs: how many indirect registers to read 5183 * @start_index: index of first indirect register to read 5184 * @sleep_ok: if true we may sleep while awaiting command completion 5185 * 5186 * Read TP TM PIO Registers 5187 **/ 5188 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 5189 u32 start_index, bool sleep_ok) 5190 { 5191 t4_tp_indirect_rw(adap, A_TP_TM_PIO_ADDR, A_TP_TM_PIO_DATA, buff, 5192 nregs, start_index, 1, sleep_ok); 5193 } 5194 5195 /** 5196 * t4_tp_mib_read - Read TP MIB registers 5197 * @adap: the adapter 5198 * @buff: where the indirect register values are written 5199 * @nregs: how many indirect registers to read 5200 * @start_index: index of first indirect register to read 5201 * @sleep_ok: if true we may sleep while awaiting command completion 5202 * 5203 * Read TP MIB Registers 5204 **/ 5205 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index, 5206 bool sleep_ok) 5207 { 5208 t4_tp_indirect_rw(adap, A_TP_MIB_INDEX, A_TP_MIB_DATA, buff, nregs, 5209 start_index, 1, sleep_ok); 5210 } 5211 5212 /** 5213 * t4_read_rss_key - read the global RSS key 5214 * @adap: the adapter 5215 * @key: 10-entry array holding the 320-bit RSS key 5216 * @sleep_ok: if true we may sleep while awaiting command completion 5217 * 5218 * Reads the global 320-bit RSS key. 5219 */ 5220 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok) 5221 { 5222 t4_tp_pio_read(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5223 } 5224 5225 /** 5226 * t4_write_rss_key - program one of the RSS keys 5227 * @adap: the adapter 5228 * @key: 10-entry array holding the 320-bit RSS key 5229 * @idx: which RSS key to write 5230 * @sleep_ok: if true we may sleep while awaiting command completion 5231 * 5232 * Writes one of the RSS keys with the given 320-bit value. If @idx is 5233 * 0..15 the corresponding entry in the RSS key table is written, 5234 * otherwise the global RSS key is written. 5235 */ 5236 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 5237 bool sleep_ok) 5238 { 5239 u8 rss_key_addr_cnt = 16; 5240 u32 vrt = t4_read_reg(adap, A_TP_RSS_CONFIG_VRT); 5241 5242 /* 5243 * T6 and later: for KeyMode 3 (per-vf and per-vf scramble), 5244 * allows access to key addresses 16-63 by using KeyWrAddrX 5245 * as index[5:4](upper 2) into key table 5246 */ 5247 if ((chip_id(adap) > CHELSIO_T5) && 5248 (vrt & F_KEYEXTEND) && (G_KEYMODE(vrt) == 3)) 5249 rss_key_addr_cnt = 32; 5250 5251 t4_tp_pio_write(adap, key, 10, A_TP_RSS_SECRET_KEY0, sleep_ok); 5252 5253 if (idx >= 0 && idx < rss_key_addr_cnt) { 5254 if (rss_key_addr_cnt > 16) 5255 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5256 vrt | V_KEYWRADDRX(idx >> 4) | 5257 V_T6_VFWRADDR(idx) | F_KEYWREN); 5258 else 5259 t4_write_reg(adap, A_TP_RSS_CONFIG_VRT, 5260 vrt| V_KEYWRADDR(idx) | F_KEYWREN); 5261 } 5262 } 5263 5264 /** 5265 * t4_read_rss_pf_config - read PF RSS Configuration Table 5266 * @adapter: the adapter 5267 * @index: the entry in the PF RSS table to read 5268 * @valp: where to store the returned value 5269 * @sleep_ok: if true we may sleep while awaiting command completion 5270 * 5271 * Reads the PF RSS Configuration Table at the specified index and returns 5272 * the value found there. 5273 */ 5274 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 5275 u32 *valp, bool sleep_ok) 5276 { 5277 t4_tp_pio_read(adapter, valp, 1, A_TP_RSS_PF0_CONFIG + index, sleep_ok); 5278 } 5279 5280 /** 5281 * t4_write_rss_pf_config - write PF RSS Configuration Table 5282 * @adapter: the adapter 5283 * @index: the entry in the VF RSS table to read 5284 * @val: the value to store 5285 * @sleep_ok: if true we may sleep while awaiting command completion 5286 * 5287 * Writes the PF RSS Configuration Table at the specified index with the 5288 * specified value. 5289 */ 5290 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 5291 u32 val, bool sleep_ok) 5292 { 5293 t4_tp_pio_write(adapter, &val, 1, A_TP_RSS_PF0_CONFIG + index, 5294 sleep_ok); 5295 } 5296 5297 /** 5298 * t4_read_rss_vf_config - read VF RSS Configuration Table 5299 * @adapter: the adapter 5300 * @index: the entry in the VF RSS table to read 5301 * @vfl: where to store the returned VFL 5302 * @vfh: where to store the returned VFH 5303 * @sleep_ok: if true we may sleep while awaiting command completion 5304 * 5305 * Reads the VF RSS Configuration Table at the specified index and returns 5306 * the (VFL, VFH) values found there. 5307 */ 5308 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 5309 u32 *vfl, u32 *vfh, bool sleep_ok) 5310 { 5311 u32 vrt, mask, data; 5312 5313 if (chip_id(adapter) <= CHELSIO_T5) { 5314 mask = V_VFWRADDR(M_VFWRADDR); 5315 data = V_VFWRADDR(index); 5316 } else { 5317 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5318 data = V_T6_VFWRADDR(index); 5319 } 5320 /* 5321 * Request that the index'th VF Table values be read into VFL/VFH. 5322 */ 5323 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5324 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5325 vrt |= data | F_VFRDEN; 5326 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5327 5328 /* 5329 * Grab the VFL/VFH values ... 5330 */ 5331 t4_tp_pio_read(adapter, vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5332 t4_tp_pio_read(adapter, vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5333 } 5334 5335 /** 5336 * t4_write_rss_vf_config - write VF RSS Configuration Table 5337 * 5338 * @adapter: the adapter 5339 * @index: the entry in the VF RSS table to write 5340 * @vfl: the VFL to store 5341 * @vfh: the VFH to store 5342 * 5343 * Writes the VF RSS Configuration Table at the specified index with the 5344 * specified (VFL, VFH) values. 5345 */ 5346 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 5347 u32 vfl, u32 vfh, bool sleep_ok) 5348 { 5349 u32 vrt, mask, data; 5350 5351 if (chip_id(adapter) <= CHELSIO_T5) { 5352 mask = V_VFWRADDR(M_VFWRADDR); 5353 data = V_VFWRADDR(index); 5354 } else { 5355 mask = V_T6_VFWRADDR(M_T6_VFWRADDR); 5356 data = V_T6_VFWRADDR(index); 5357 } 5358 5359 /* 5360 * Load up VFL/VFH with the values to be written ... 5361 */ 5362 t4_tp_pio_write(adapter, &vfl, 1, A_TP_RSS_VFL_CONFIG, sleep_ok); 5363 t4_tp_pio_write(adapter, &vfh, 1, A_TP_RSS_VFH_CONFIG, sleep_ok); 5364 5365 /* 5366 * Write the VFL/VFH into the VF Table at index'th location. 5367 */ 5368 vrt = t4_read_reg(adapter, A_TP_RSS_CONFIG_VRT); 5369 vrt &= ~(F_VFRDRG | F_VFWREN | F_KEYWREN | mask); 5370 vrt |= data | F_VFRDEN; 5371 t4_write_reg(adapter, A_TP_RSS_CONFIG_VRT, vrt); 5372 } 5373 5374 /** 5375 * t4_read_rss_pf_map - read PF RSS Map 5376 * @adapter: the adapter 5377 * @sleep_ok: if true we may sleep while awaiting command completion 5378 * 5379 * Reads the PF RSS Map register and returns its value. 5380 */ 5381 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok) 5382 { 5383 u32 pfmap; 5384 5385 t4_tp_pio_read(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5386 5387 return pfmap; 5388 } 5389 5390 /** 5391 * t4_write_rss_pf_map - write PF RSS Map 5392 * @adapter: the adapter 5393 * @pfmap: PF RSS Map value 5394 * 5395 * Writes the specified value to the PF RSS Map register. 5396 */ 5397 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok) 5398 { 5399 t4_tp_pio_write(adapter, &pfmap, 1, A_TP_RSS_PF_MAP, sleep_ok); 5400 } 5401 5402 /** 5403 * t4_read_rss_pf_mask - read PF RSS Mask 5404 * @adapter: the adapter 5405 * @sleep_ok: if true we may sleep while awaiting command completion 5406 * 5407 * Reads the PF RSS Mask register and returns its value. 5408 */ 5409 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok) 5410 { 5411 u32 pfmask; 5412 5413 t4_tp_pio_read(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5414 5415 return pfmask; 5416 } 5417 5418 /** 5419 * t4_write_rss_pf_mask - write PF RSS Mask 5420 * @adapter: the adapter 5421 * @pfmask: PF RSS Mask value 5422 * 5423 * Writes the specified value to the PF RSS Mask register. 5424 */ 5425 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok) 5426 { 5427 t4_tp_pio_write(adapter, &pfmask, 1, A_TP_RSS_PF_MSK, sleep_ok); 5428 } 5429 5430 /** 5431 * t4_tp_get_tcp_stats - read TP's TCP MIB counters 5432 * @adap: the adapter 5433 * @v4: holds the TCP/IP counter values 5434 * @v6: holds the TCP/IPv6 counter values 5435 * @sleep_ok: if true we may sleep while awaiting command completion 5436 * 5437 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters. 5438 * Either @v4 or @v6 may be %NULL to skip the corresponding stats. 5439 */ 5440 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 5441 struct tp_tcp_stats *v6, bool sleep_ok) 5442 { 5443 u32 val[A_TP_MIB_TCP_RXT_SEG_LO - A_TP_MIB_TCP_OUT_RST + 1]; 5444 5445 #define STAT_IDX(x) ((A_TP_MIB_TCP_##x) - A_TP_MIB_TCP_OUT_RST) 5446 #define STAT(x) val[STAT_IDX(x)] 5447 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 5448 5449 if (v4) { 5450 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5451 A_TP_MIB_TCP_OUT_RST, sleep_ok); 5452 v4->tcp_out_rsts = STAT(OUT_RST); 5453 v4->tcp_in_segs = STAT64(IN_SEG); 5454 v4->tcp_out_segs = STAT64(OUT_SEG); 5455 v4->tcp_retrans_segs = STAT64(RXT_SEG); 5456 } 5457 if (v6) { 5458 t4_tp_mib_read(adap, val, ARRAY_SIZE(val), 5459 A_TP_MIB_TCP_V6OUT_RST, sleep_ok); 5460 v6->tcp_out_rsts = STAT(OUT_RST); 5461 v6->tcp_in_segs = STAT64(IN_SEG); 5462 v6->tcp_out_segs = STAT64(OUT_SEG); 5463 v6->tcp_retrans_segs = STAT64(RXT_SEG); 5464 } 5465 #undef STAT64 5466 #undef STAT 5467 #undef STAT_IDX 5468 } 5469 5470 /** 5471 * t4_tp_get_err_stats - read TP's error MIB counters 5472 * @adap: the adapter 5473 * @st: holds the counter values 5474 * @sleep_ok: if true we may sleep while awaiting command completion 5475 * 5476 * Returns the values of TP's error counters. 5477 */ 5478 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 5479 bool sleep_ok) 5480 { 5481 int nchan = adap->chip_params->nchan; 5482 5483 t4_tp_mib_read(adap, st->mac_in_errs, nchan, A_TP_MIB_MAC_IN_ERR_0, 5484 sleep_ok); 5485 5486 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, A_TP_MIB_HDR_IN_ERR_0, 5487 sleep_ok); 5488 5489 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, A_TP_MIB_TCP_IN_ERR_0, 5490 sleep_ok); 5491 5492 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan, 5493 A_TP_MIB_TNL_CNG_DROP_0, sleep_ok); 5494 5495 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan, 5496 A_TP_MIB_OFD_CHN_DROP_0, sleep_ok); 5497 5498 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, A_TP_MIB_TNL_DROP_0, 5499 sleep_ok); 5500 5501 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan, 5502 A_TP_MIB_OFD_VLN_DROP_0, sleep_ok); 5503 5504 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan, 5505 A_TP_MIB_TCP_V6IN_ERR_0, sleep_ok); 5506 5507 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, A_TP_MIB_OFD_ARP_DROP, 5508 sleep_ok); 5509 } 5510 5511 /** 5512 * t4_tp_get_proxy_stats - read TP's proxy MIB counters 5513 * @adap: the adapter 5514 * @st: holds the counter values 5515 * 5516 * Returns the values of TP's proxy counters. 5517 */ 5518 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 5519 bool sleep_ok) 5520 { 5521 int nchan = adap->chip_params->nchan; 5522 5523 t4_tp_mib_read(adap, st->proxy, nchan, A_TP_MIB_TNL_LPBK_0, sleep_ok); 5524 } 5525 5526 /** 5527 * t4_tp_get_cpl_stats - read TP's CPL MIB counters 5528 * @adap: the adapter 5529 * @st: holds the counter values 5530 * @sleep_ok: if true we may sleep while awaiting command completion 5531 * 5532 * Returns the values of TP's CPL counters. 5533 */ 5534 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 5535 bool sleep_ok) 5536 { 5537 int nchan = adap->chip_params->nchan; 5538 5539 t4_tp_mib_read(adap, st->req, nchan, A_TP_MIB_CPL_IN_REQ_0, sleep_ok); 5540 5541 t4_tp_mib_read(adap, st->rsp, nchan, A_TP_MIB_CPL_OUT_RSP_0, sleep_ok); 5542 } 5543 5544 /** 5545 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters 5546 * @adap: the adapter 5547 * @st: holds the counter values 5548 * 5549 * Returns the values of TP's RDMA counters. 5550 */ 5551 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 5552 bool sleep_ok) 5553 { 5554 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, A_TP_MIB_RQE_DFR_PKT, 5555 sleep_ok); 5556 } 5557 5558 /** 5559 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port 5560 * @adap: the adapter 5561 * @idx: the port index 5562 * @st: holds the counter values 5563 * @sleep_ok: if true we may sleep while awaiting command completion 5564 * 5565 * Returns the values of TP's FCoE counters for the selected port. 5566 */ 5567 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 5568 struct tp_fcoe_stats *st, bool sleep_ok) 5569 { 5570 u32 val[2]; 5571 5572 t4_tp_mib_read(adap, &st->frames_ddp, 1, A_TP_MIB_FCOE_DDP_0 + idx, 5573 sleep_ok); 5574 5575 t4_tp_mib_read(adap, &st->frames_drop, 1, 5576 A_TP_MIB_FCOE_DROP_0 + idx, sleep_ok); 5577 5578 t4_tp_mib_read(adap, val, 2, A_TP_MIB_FCOE_BYTE_0_HI + 2 * idx, 5579 sleep_ok); 5580 5581 st->octets_ddp = ((u64)val[0] << 32) | val[1]; 5582 } 5583 5584 /** 5585 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters 5586 * @adap: the adapter 5587 * @st: holds the counter values 5588 * @sleep_ok: if true we may sleep while awaiting command completion 5589 * 5590 * Returns the values of TP's counters for non-TCP directly-placed packets. 5591 */ 5592 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 5593 bool sleep_ok) 5594 { 5595 u32 val[4]; 5596 5597 t4_tp_mib_read(adap, val, 4, A_TP_MIB_USM_PKTS, sleep_ok); 5598 5599 st->frames = val[0]; 5600 st->drops = val[1]; 5601 st->octets = ((u64)val[2] << 32) | val[3]; 5602 } 5603 5604 /** 5605 * t4_read_mtu_tbl - returns the values in the HW path MTU table 5606 * @adap: the adapter 5607 * @mtus: where to store the MTU values 5608 * @mtu_log: where to store the MTU base-2 log (may be %NULL) 5609 * 5610 * Reads the HW path MTU table. 5611 */ 5612 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) 5613 { 5614 u32 v; 5615 int i; 5616 5617 for (i = 0; i < NMTUS; ++i) { 5618 t4_write_reg(adap, A_TP_MTU_TABLE, 5619 V_MTUINDEX(0xff) | V_MTUVALUE(i)); 5620 v = t4_read_reg(adap, A_TP_MTU_TABLE); 5621 mtus[i] = G_MTUVALUE(v); 5622 if (mtu_log) 5623 mtu_log[i] = G_MTUWIDTH(v); 5624 } 5625 } 5626 5627 /** 5628 * t4_read_cong_tbl - reads the congestion control table 5629 * @adap: the adapter 5630 * @incr: where to store the alpha values 5631 * 5632 * Reads the additive increments programmed into the HW congestion 5633 * control table. 5634 */ 5635 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) 5636 { 5637 unsigned int mtu, w; 5638 5639 for (mtu = 0; mtu < NMTUS; ++mtu) 5640 for (w = 0; w < NCCTRL_WIN; ++w) { 5641 t4_write_reg(adap, A_TP_CCTRL_TABLE, 5642 V_ROWINDEX(0xffff) | (mtu << 5) | w); 5643 incr[mtu][w] = (u16)t4_read_reg(adap, 5644 A_TP_CCTRL_TABLE) & 0x1fff; 5645 } 5646 } 5647 5648 /** 5649 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register 5650 * @adap: the adapter 5651 * @addr: the indirect TP register address 5652 * @mask: specifies the field within the register to modify 5653 * @val: new value for the field 5654 * 5655 * Sets a field of an indirect TP register to the given value. 5656 */ 5657 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 5658 unsigned int mask, unsigned int val) 5659 { 5660 t4_write_reg(adap, A_TP_PIO_ADDR, addr); 5661 val |= t4_read_reg(adap, A_TP_PIO_DATA) & ~mask; 5662 t4_write_reg(adap, A_TP_PIO_DATA, val); 5663 } 5664 5665 /** 5666 * init_cong_ctrl - initialize congestion control parameters 5667 * @a: the alpha values for congestion control 5668 * @b: the beta values for congestion control 5669 * 5670 * Initialize the congestion control parameters. 5671 */ 5672 static void init_cong_ctrl(unsigned short *a, unsigned short *b) 5673 { 5674 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1; 5675 a[9] = 2; 5676 a[10] = 3; 5677 a[11] = 4; 5678 a[12] = 5; 5679 a[13] = 6; 5680 a[14] = 7; 5681 a[15] = 8; 5682 a[16] = 9; 5683 a[17] = 10; 5684 a[18] = 14; 5685 a[19] = 17; 5686 a[20] = 21; 5687 a[21] = 25; 5688 a[22] = 30; 5689 a[23] = 35; 5690 a[24] = 45; 5691 a[25] = 60; 5692 a[26] = 80; 5693 a[27] = 100; 5694 a[28] = 200; 5695 a[29] = 300; 5696 a[30] = 400; 5697 a[31] = 500; 5698 5699 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0; 5700 b[9] = b[10] = 1; 5701 b[11] = b[12] = 2; 5702 b[13] = b[14] = b[15] = b[16] = 3; 5703 b[17] = b[18] = b[19] = b[20] = b[21] = 4; 5704 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5; 5705 b[28] = b[29] = 6; 5706 b[30] = b[31] = 7; 5707 } 5708 5709 /* The minimum additive increment value for the congestion control table */ 5710 #define CC_MIN_INCR 2U 5711 5712 /** 5713 * t4_load_mtus - write the MTU and congestion control HW tables 5714 * @adap: the adapter 5715 * @mtus: the values for the MTU table 5716 * @alpha: the values for the congestion control alpha parameter 5717 * @beta: the values for the congestion control beta parameter 5718 * 5719 * Write the HW MTU table with the supplied MTUs and the high-speed 5720 * congestion control table with the supplied alpha, beta, and MTUs. 5721 * We write the two tables together because the additive increments 5722 * depend on the MTUs. 5723 */ 5724 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 5725 const unsigned short *alpha, const unsigned short *beta) 5726 { 5727 static const unsigned int avg_pkts[NCCTRL_WIN] = { 5728 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640, 5729 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480, 5730 28672, 40960, 57344, 81920, 114688, 163840, 229376 5731 }; 5732 5733 unsigned int i, w; 5734 5735 for (i = 0; i < NMTUS; ++i) { 5736 unsigned int mtu = mtus[i]; 5737 unsigned int log2 = fls(mtu); 5738 5739 if (!(mtu & ((1 << log2) >> 2))) /* round */ 5740 log2--; 5741 t4_write_reg(adap, A_TP_MTU_TABLE, V_MTUINDEX(i) | 5742 V_MTUWIDTH(log2) | V_MTUVALUE(mtu)); 5743 5744 for (w = 0; w < NCCTRL_WIN; ++w) { 5745 unsigned int inc; 5746 5747 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 5748 CC_MIN_INCR); 5749 5750 t4_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) | 5751 (w << 16) | (beta[w] << 13) | inc); 5752 } 5753 } 5754 } 5755 5756 /** 5757 * t4_set_pace_tbl - set the pace table 5758 * @adap: the adapter 5759 * @pace_vals: the pace values in microseconds 5760 * @start: index of the first entry in the HW pace table to set 5761 * @n: how many entries to set 5762 * 5763 * Sets (a subset of the) HW pace table. 5764 */ 5765 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 5766 unsigned int start, unsigned int n) 5767 { 5768 unsigned int vals[NTX_SCHED], i; 5769 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000); 5770 5771 if (n > NTX_SCHED) 5772 return -ERANGE; 5773 5774 /* convert values from us to dack ticks, rounding to closest value */ 5775 for (i = 0; i < n; i++, pace_vals++) { 5776 vals[i] = (1000 * *pace_vals + tick_ns / 2) / tick_ns; 5777 if (vals[i] > 0x7ff) 5778 return -ERANGE; 5779 if (*pace_vals && vals[i] == 0) 5780 return -ERANGE; 5781 } 5782 for (i = 0; i < n; i++, start++) 5783 t4_write_reg(adap, A_TP_PACE_TABLE, (start << 16) | vals[i]); 5784 return 0; 5785 } 5786 5787 /** 5788 * t4_set_sched_bps - set the bit rate for a HW traffic scheduler 5789 * @adap: the adapter 5790 * @kbps: target rate in Kbps 5791 * @sched: the scheduler index 5792 * 5793 * Configure a Tx HW scheduler for the target rate. 5794 */ 5795 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps) 5796 { 5797 unsigned int v, tps, cpt, bpt, delta, mindelta = ~0; 5798 unsigned int clk = adap->params.vpd.cclk * 1000; 5799 unsigned int selected_cpt = 0, selected_bpt = 0; 5800 5801 if (kbps > 0) { 5802 kbps *= 125; /* -> bytes */ 5803 for (cpt = 1; cpt <= 255; cpt++) { 5804 tps = clk / cpt; 5805 bpt = (kbps + tps / 2) / tps; 5806 if (bpt > 0 && bpt <= 255) { 5807 v = bpt * tps; 5808 delta = v >= kbps ? v - kbps : kbps - v; 5809 if (delta < mindelta) { 5810 mindelta = delta; 5811 selected_cpt = cpt; 5812 selected_bpt = bpt; 5813 } 5814 } else if (selected_cpt) 5815 break; 5816 } 5817 if (!selected_cpt) 5818 return -EINVAL; 5819 } 5820 t4_write_reg(adap, A_TP_TM_PIO_ADDR, 5821 A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2); 5822 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5823 if (sched & 1) 5824 v = (v & 0xffff) | (selected_cpt << 16) | (selected_bpt << 24); 5825 else 5826 v = (v & 0xffff0000) | selected_cpt | (selected_bpt << 8); 5827 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5828 return 0; 5829 } 5830 5831 /** 5832 * t4_set_sched_ipg - set the IPG for a Tx HW packet rate scheduler 5833 * @adap: the adapter 5834 * @sched: the scheduler index 5835 * @ipg: the interpacket delay in tenths of nanoseconds 5836 * 5837 * Set the interpacket delay for a HW packet rate scheduler. 5838 */ 5839 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg) 5840 { 5841 unsigned int v, addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 5842 5843 /* convert ipg to nearest number of core clocks */ 5844 ipg *= core_ticks_per_usec(adap); 5845 ipg = (ipg + 5000) / 10000; 5846 if (ipg > M_TXTIMERSEPQ0) 5847 return -EINVAL; 5848 5849 t4_write_reg(adap, A_TP_TM_PIO_ADDR, addr); 5850 v = t4_read_reg(adap, A_TP_TM_PIO_DATA); 5851 if (sched & 1) 5852 v = (v & V_TXTIMERSEPQ0(M_TXTIMERSEPQ0)) | V_TXTIMERSEPQ1(ipg); 5853 else 5854 v = (v & V_TXTIMERSEPQ1(M_TXTIMERSEPQ1)) | V_TXTIMERSEPQ0(ipg); 5855 t4_write_reg(adap, A_TP_TM_PIO_DATA, v); 5856 t4_read_reg(adap, A_TP_TM_PIO_DATA); 5857 return 0; 5858 } 5859 5860 /* 5861 * Calculates a rate in bytes/s given the number of 256-byte units per 4K core 5862 * clocks. The formula is 5863 * 5864 * bytes/s = bytes256 * 256 * ClkFreq / 4096 5865 * 5866 * which is equivalent to 5867 * 5868 * bytes/s = 62.5 * bytes256 * ClkFreq_ms 5869 */ 5870 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) 5871 { 5872 u64 v = (u64)bytes256 * adap->params.vpd.cclk; 5873 5874 return v * 62 + v / 2; 5875 } 5876 5877 /** 5878 * t4_get_chan_txrate - get the current per channel Tx rates 5879 * @adap: the adapter 5880 * @nic_rate: rates for NIC traffic 5881 * @ofld_rate: rates for offloaded traffic 5882 * 5883 * Return the current Tx rates in bytes/s for NIC and offloaded traffic 5884 * for each channel. 5885 */ 5886 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) 5887 { 5888 u32 v; 5889 5890 v = t4_read_reg(adap, A_TP_TX_TRATE); 5891 nic_rate[0] = chan_rate(adap, G_TNLRATE0(v)); 5892 nic_rate[1] = chan_rate(adap, G_TNLRATE1(v)); 5893 if (adap->chip_params->nchan > 2) { 5894 nic_rate[2] = chan_rate(adap, G_TNLRATE2(v)); 5895 nic_rate[3] = chan_rate(adap, G_TNLRATE3(v)); 5896 } 5897 5898 v = t4_read_reg(adap, A_TP_TX_ORATE); 5899 ofld_rate[0] = chan_rate(adap, G_OFDRATE0(v)); 5900 ofld_rate[1] = chan_rate(adap, G_OFDRATE1(v)); 5901 if (adap->chip_params->nchan > 2) { 5902 ofld_rate[2] = chan_rate(adap, G_OFDRATE2(v)); 5903 ofld_rate[3] = chan_rate(adap, G_OFDRATE3(v)); 5904 } 5905 } 5906 5907 /** 5908 * t4_set_trace_filter - configure one of the tracing filters 5909 * @adap: the adapter 5910 * @tp: the desired trace filter parameters 5911 * @idx: which filter to configure 5912 * @enable: whether to enable or disable the filter 5913 * 5914 * Configures one of the tracing filters available in HW. If @tp is %NULL 5915 * it indicates that the filter is already written in the register and it 5916 * just needs to be enabled or disabled. 5917 */ 5918 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, 5919 int idx, int enable) 5920 { 5921 int i, ofst = idx * 4; 5922 u32 data_reg, mask_reg, cfg; 5923 u32 multitrc = F_TRCMULTIFILTER; 5924 u32 en = is_t4(adap) ? F_TFEN : F_T5_TFEN; 5925 5926 if (idx < 0 || idx >= NTRACE) 5927 return -EINVAL; 5928 5929 if (tp == NULL || !enable) { 5930 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 5931 enable ? en : 0); 5932 return 0; 5933 } 5934 5935 /* 5936 * TODO - After T4 data book is updated, specify the exact 5937 * section below. 5938 * 5939 * See T4 data book - MPS section for a complete description 5940 * of the below if..else handling of A_MPS_TRC_CFG register 5941 * value. 5942 */ 5943 cfg = t4_read_reg(adap, A_MPS_TRC_CFG); 5944 if (cfg & F_TRCMULTIFILTER) { 5945 /* 5946 * If multiple tracers are enabled, then maximum 5947 * capture size is 2.5KB (FIFO size of a single channel) 5948 * minus 2 flits for CPL_TRACE_PKT header. 5949 */ 5950 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8))) 5951 return -EINVAL; 5952 } else { 5953 /* 5954 * If multiple tracers are disabled, to avoid deadlocks 5955 * maximum packet capture size of 9600 bytes is recommended. 5956 * Also in this mode, only trace0 can be enabled and running. 5957 */ 5958 multitrc = 0; 5959 if (tp->snap_len > 9600 || idx) 5960 return -EINVAL; 5961 } 5962 5963 if (tp->port > (is_t4(adap) ? 11 : 19) || tp->invert > 1 || 5964 tp->skip_len > M_TFLENGTH || tp->skip_ofst > M_TFOFFSET || 5965 tp->min_len > M_TFMINPKTSIZE) 5966 return -EINVAL; 5967 5968 /* stop the tracer we'll be changing */ 5969 t4_set_reg_field(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, en, 0); 5970 5971 idx *= (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH); 5972 data_reg = A_MPS_TRC_FILTER0_MATCH + idx; 5973 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + idx; 5974 5975 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 5976 t4_write_reg(adap, data_reg, tp->data[i]); 5977 t4_write_reg(adap, mask_reg, ~tp->mask[i]); 5978 } 5979 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst, 5980 V_TFCAPTUREMAX(tp->snap_len) | 5981 V_TFMINPKTSIZE(tp->min_len)); 5982 t4_write_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst, 5983 V_TFOFFSET(tp->skip_ofst) | V_TFLENGTH(tp->skip_len) | en | 5984 (is_t4(adap) ? 5985 V_TFPORT(tp->port) | V_TFINVERTMATCH(tp->invert) : 5986 V_T5_TFPORT(tp->port) | V_T5_TFINVERTMATCH(tp->invert))); 5987 5988 return 0; 5989 } 5990 5991 /** 5992 * t4_get_trace_filter - query one of the tracing filters 5993 * @adap: the adapter 5994 * @tp: the current trace filter parameters 5995 * @idx: which trace filter to query 5996 * @enabled: non-zero if the filter is enabled 5997 * 5998 * Returns the current settings of one of the HW tracing filters. 5999 */ 6000 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, 6001 int *enabled) 6002 { 6003 u32 ctla, ctlb; 6004 int i, ofst = idx * 4; 6005 u32 data_reg, mask_reg; 6006 6007 ctla = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_A + ofst); 6008 ctlb = t4_read_reg(adap, A_MPS_TRC_FILTER_MATCH_CTL_B + ofst); 6009 6010 if (is_t4(adap)) { 6011 *enabled = !!(ctla & F_TFEN); 6012 tp->port = G_TFPORT(ctla); 6013 tp->invert = !!(ctla & F_TFINVERTMATCH); 6014 } else { 6015 *enabled = !!(ctla & F_T5_TFEN); 6016 tp->port = G_T5_TFPORT(ctla); 6017 tp->invert = !!(ctla & F_T5_TFINVERTMATCH); 6018 } 6019 tp->snap_len = G_TFCAPTUREMAX(ctlb); 6020 tp->min_len = G_TFMINPKTSIZE(ctlb); 6021 tp->skip_ofst = G_TFOFFSET(ctla); 6022 tp->skip_len = G_TFLENGTH(ctla); 6023 6024 ofst = (A_MPS_TRC_FILTER1_MATCH - A_MPS_TRC_FILTER0_MATCH) * idx; 6025 data_reg = A_MPS_TRC_FILTER0_MATCH + ofst; 6026 mask_reg = A_MPS_TRC_FILTER0_DONT_CARE + ofst; 6027 6028 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) { 6029 tp->mask[i] = ~t4_read_reg(adap, mask_reg); 6030 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; 6031 } 6032 } 6033 6034 /** 6035 * t4_pmtx_get_stats - returns the HW stats from PMTX 6036 * @adap: the adapter 6037 * @cnt: where to store the count statistics 6038 * @cycles: where to store the cycle statistics 6039 * 6040 * Returns performance statistics from PMTX. 6041 */ 6042 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6043 { 6044 int i; 6045 u32 data[2]; 6046 6047 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6048 t4_write_reg(adap, A_PM_TX_STAT_CONFIG, i + 1); 6049 cnt[i] = t4_read_reg(adap, A_PM_TX_STAT_COUNT); 6050 if (is_t4(adap)) 6051 cycles[i] = t4_read_reg64(adap, A_PM_TX_STAT_LSB); 6052 else { 6053 t4_read_indirect(adap, A_PM_TX_DBG_CTRL, 6054 A_PM_TX_DBG_DATA, data, 2, 6055 A_PM_TX_DBG_STAT_MSB); 6056 cycles[i] = (((u64)data[0] << 32) | data[1]); 6057 } 6058 } 6059 } 6060 6061 /** 6062 * t4_pmrx_get_stats - returns the HW stats from PMRX 6063 * @adap: the adapter 6064 * @cnt: where to store the count statistics 6065 * @cycles: where to store the cycle statistics 6066 * 6067 * Returns performance statistics from PMRX. 6068 */ 6069 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) 6070 { 6071 int i; 6072 u32 data[2]; 6073 6074 for (i = 0; i < adap->chip_params->pm_stats_cnt; i++) { 6075 t4_write_reg(adap, A_PM_RX_STAT_CONFIG, i + 1); 6076 cnt[i] = t4_read_reg(adap, A_PM_RX_STAT_COUNT); 6077 if (is_t4(adap)) { 6078 cycles[i] = t4_read_reg64(adap, A_PM_RX_STAT_LSB); 6079 } else { 6080 t4_read_indirect(adap, A_PM_RX_DBG_CTRL, 6081 A_PM_RX_DBG_DATA, data, 2, 6082 A_PM_RX_DBG_STAT_MSB); 6083 cycles[i] = (((u64)data[0] << 32) | data[1]); 6084 } 6085 } 6086 } 6087 6088 /** 6089 * t4_get_mps_bg_map - return the buffer groups associated with a port 6090 * @adap: the adapter 6091 * @idx: the port index 6092 * 6093 * Returns a bitmap indicating which MPS buffer groups are associated 6094 * with the given port. Bit i is set if buffer group i is used by the 6095 * port. 6096 */ 6097 static unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx) 6098 { 6099 u32 n; 6100 6101 if (adap->params.mps_bg_map) 6102 return ((adap->params.mps_bg_map >> (idx << 3)) & 0xff); 6103 6104 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6105 if (n == 0) 6106 return idx == 0 ? 0xf : 0; 6107 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6108 return idx < 2 ? (3 << (2 * idx)) : 0; 6109 return 1 << idx; 6110 } 6111 6112 /* 6113 * TP RX e-channels associated with the port. 6114 */ 6115 static unsigned int t4_get_rx_e_chan_map(struct adapter *adap, int idx) 6116 { 6117 u32 n = G_NUMPORTS(t4_read_reg(adap, A_MPS_CMN_CTL)); 6118 6119 if (n == 0) 6120 return idx == 0 ? 0xf : 0; 6121 if (n == 1 && chip_id(adap) <= CHELSIO_T5) 6122 return idx < 2 ? (3 << (2 * idx)) : 0; 6123 return 1 << idx; 6124 } 6125 6126 /** 6127 * t4_get_port_type_description - return Port Type string description 6128 * @port_type: firmware Port Type enumeration 6129 */ 6130 const char *t4_get_port_type_description(enum fw_port_type port_type) 6131 { 6132 static const char *const port_type_description[] = { 6133 "Fiber_XFI", 6134 "Fiber_XAUI", 6135 "BT_SGMII", 6136 "BT_XFI", 6137 "BT_XAUI", 6138 "KX4", 6139 "CX4", 6140 "KX", 6141 "KR", 6142 "SFP", 6143 "BP_AP", 6144 "BP4_AP", 6145 "QSFP_10G", 6146 "QSA", 6147 "QSFP", 6148 "BP40_BA", 6149 "KR4_100G", 6150 "CR4_QSFP", 6151 "CR_QSFP", 6152 "CR2_QSFP", 6153 "SFP28", 6154 "KR_SFP28", 6155 }; 6156 6157 if (port_type < ARRAY_SIZE(port_type_description)) 6158 return port_type_description[port_type]; 6159 return "UNKNOWN"; 6160 } 6161 6162 /** 6163 * t4_get_port_stats_offset - collect port stats relative to a previous 6164 * snapshot 6165 * @adap: The adapter 6166 * @idx: The port 6167 * @stats: Current stats to fill 6168 * @offset: Previous stats snapshot 6169 */ 6170 void t4_get_port_stats_offset(struct adapter *adap, int idx, 6171 struct port_stats *stats, 6172 struct port_stats *offset) 6173 { 6174 u64 *s, *o; 6175 int i; 6176 6177 t4_get_port_stats(adap, idx, stats); 6178 for (i = 0, s = (u64 *)stats, o = (u64 *)offset ; 6179 i < (sizeof(struct port_stats)/sizeof(u64)) ; 6180 i++, s++, o++) 6181 *s -= *o; 6182 } 6183 6184 /** 6185 * t4_get_port_stats - collect port statistics 6186 * @adap: the adapter 6187 * @idx: the port index 6188 * @p: the stats structure to fill 6189 * 6190 * Collect statistics related to the given port from HW. 6191 */ 6192 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) 6193 { 6194 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6195 u32 stat_ctl = t4_read_reg(adap, A_MPS_STAT_CTL); 6196 6197 #define GET_STAT(name) \ 6198 t4_read_reg64(adap, \ 6199 (is_t4(adap) ? PORT_REG(idx, A_MPS_PORT_STAT_##name##_L) : \ 6200 T5_PORT_REG(idx, A_MPS_PORT_STAT_##name##_L))) 6201 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6202 6203 p->tx_pause = GET_STAT(TX_PORT_PAUSE); 6204 p->tx_octets = GET_STAT(TX_PORT_BYTES); 6205 p->tx_frames = GET_STAT(TX_PORT_FRAMES); 6206 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST); 6207 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST); 6208 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST); 6209 p->tx_error_frames = GET_STAT(TX_PORT_ERROR); 6210 p->tx_frames_64 = GET_STAT(TX_PORT_64B); 6211 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B); 6212 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B); 6213 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B); 6214 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B); 6215 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B); 6216 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX); 6217 p->tx_drop = GET_STAT(TX_PORT_DROP); 6218 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0); 6219 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1); 6220 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2); 6221 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3); 6222 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4); 6223 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5); 6224 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6); 6225 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7); 6226 6227 if (chip_id(adap) >= CHELSIO_T5) { 6228 if (stat_ctl & F_COUNTPAUSESTATTX) { 6229 p->tx_frames -= p->tx_pause; 6230 p->tx_octets -= p->tx_pause * 64; 6231 } 6232 if (stat_ctl & F_COUNTPAUSEMCTX) 6233 p->tx_mcast_frames -= p->tx_pause; 6234 } 6235 6236 p->rx_pause = GET_STAT(RX_PORT_PAUSE); 6237 p->rx_octets = GET_STAT(RX_PORT_BYTES); 6238 p->rx_frames = GET_STAT(RX_PORT_FRAMES); 6239 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST); 6240 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST); 6241 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST); 6242 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR); 6243 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR); 6244 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR); 6245 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR); 6246 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR); 6247 p->rx_runt = GET_STAT(RX_PORT_LESS_64B); 6248 p->rx_frames_64 = GET_STAT(RX_PORT_64B); 6249 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B); 6250 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B); 6251 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B); 6252 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B); 6253 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B); 6254 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX); 6255 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0); 6256 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1); 6257 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2); 6258 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3); 6259 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4); 6260 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5); 6261 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6); 6262 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7); 6263 6264 if (chip_id(adap) >= CHELSIO_T5) { 6265 if (stat_ctl & F_COUNTPAUSESTATRX) { 6266 p->rx_frames -= p->rx_pause; 6267 p->rx_octets -= p->rx_pause * 64; 6268 } 6269 if (stat_ctl & F_COUNTPAUSEMCRX) 6270 p->rx_mcast_frames -= p->rx_pause; 6271 } 6272 6273 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0; 6274 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0; 6275 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0; 6276 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0; 6277 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0; 6278 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0; 6279 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0; 6280 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0; 6281 6282 #undef GET_STAT 6283 #undef GET_STAT_COM 6284 } 6285 6286 /** 6287 * t4_get_lb_stats - collect loopback port statistics 6288 * @adap: the adapter 6289 * @idx: the loopback port index 6290 * @p: the stats structure to fill 6291 * 6292 * Return HW statistics for the given loopback port. 6293 */ 6294 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) 6295 { 6296 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 6297 6298 #define GET_STAT(name) \ 6299 t4_read_reg64(adap, \ 6300 (is_t4(adap) ? \ 6301 PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L) : \ 6302 T5_PORT_REG(idx, A_MPS_PORT_STAT_LB_PORT_##name##_L))) 6303 #define GET_STAT_COM(name) t4_read_reg64(adap, A_MPS_STAT_##name##_L) 6304 6305 p->octets = GET_STAT(BYTES); 6306 p->frames = GET_STAT(FRAMES); 6307 p->bcast_frames = GET_STAT(BCAST); 6308 p->mcast_frames = GET_STAT(MCAST); 6309 p->ucast_frames = GET_STAT(UCAST); 6310 p->error_frames = GET_STAT(ERROR); 6311 6312 p->frames_64 = GET_STAT(64B); 6313 p->frames_65_127 = GET_STAT(65B_127B); 6314 p->frames_128_255 = GET_STAT(128B_255B); 6315 p->frames_256_511 = GET_STAT(256B_511B); 6316 p->frames_512_1023 = GET_STAT(512B_1023B); 6317 p->frames_1024_1518 = GET_STAT(1024B_1518B); 6318 p->frames_1519_max = GET_STAT(1519B_MAX); 6319 p->drop = GET_STAT(DROP_FRAMES); 6320 6321 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0; 6322 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0; 6323 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0; 6324 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0; 6325 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0; 6326 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0; 6327 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0; 6328 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0; 6329 6330 #undef GET_STAT 6331 #undef GET_STAT_COM 6332 } 6333 6334 /** 6335 * t4_wol_magic_enable - enable/disable magic packet WoL 6336 * @adap: the adapter 6337 * @port: the physical port index 6338 * @addr: MAC address expected in magic packets, %NULL to disable 6339 * 6340 * Enables/disables magic packet wake-on-LAN for the selected port. 6341 */ 6342 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, 6343 const u8 *addr) 6344 { 6345 u32 mag_id_reg_l, mag_id_reg_h, port_cfg_reg; 6346 6347 if (is_t4(adap)) { 6348 mag_id_reg_l = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_LO); 6349 mag_id_reg_h = PORT_REG(port, A_XGMAC_PORT_MAGIC_MACID_HI); 6350 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6351 } else { 6352 mag_id_reg_l = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_LO); 6353 mag_id_reg_h = T5_PORT_REG(port, A_MAC_PORT_MAGIC_MACID_HI); 6354 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6355 } 6356 6357 if (addr) { 6358 t4_write_reg(adap, mag_id_reg_l, 6359 (addr[2] << 24) | (addr[3] << 16) | 6360 (addr[4] << 8) | addr[5]); 6361 t4_write_reg(adap, mag_id_reg_h, 6362 (addr[0] << 8) | addr[1]); 6363 } 6364 t4_set_reg_field(adap, port_cfg_reg, F_MAGICEN, 6365 V_MAGICEN(addr != NULL)); 6366 } 6367 6368 /** 6369 * t4_wol_pat_enable - enable/disable pattern-based WoL 6370 * @adap: the adapter 6371 * @port: the physical port index 6372 * @map: bitmap of which HW pattern filters to set 6373 * @mask0: byte mask for bytes 0-63 of a packet 6374 * @mask1: byte mask for bytes 64-127 of a packet 6375 * @crc: Ethernet CRC for selected bytes 6376 * @enable: enable/disable switch 6377 * 6378 * Sets the pattern filters indicated in @map to mask out the bytes 6379 * specified in @mask0/@mask1 in received packets and compare the CRC of 6380 * the resulting packet against @crc. If @enable is %true pattern-based 6381 * WoL is enabled, otherwise disabled. 6382 */ 6383 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 6384 u64 mask0, u64 mask1, unsigned int crc, bool enable) 6385 { 6386 int i; 6387 u32 port_cfg_reg; 6388 6389 if (is_t4(adap)) 6390 port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2); 6391 else 6392 port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2); 6393 6394 if (!enable) { 6395 t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0); 6396 return 0; 6397 } 6398 if (map > 0xff) 6399 return -EINVAL; 6400 6401 #define EPIO_REG(name) \ 6402 (is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \ 6403 T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) 6404 6405 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 6406 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 6407 t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32); 6408 6409 for (i = 0; i < NWOL_PAT; i++, map >>= 1) { 6410 if (!(map & 1)) 6411 continue; 6412 6413 /* write byte masks */ 6414 t4_write_reg(adap, EPIO_REG(DATA0), mask0); 6415 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR); 6416 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6417 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6418 return -ETIMEDOUT; 6419 6420 /* write CRC */ 6421 t4_write_reg(adap, EPIO_REG(DATA0), crc); 6422 t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR); 6423 t4_read_reg(adap, EPIO_REG(OP)); /* flush */ 6424 if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY) 6425 return -ETIMEDOUT; 6426 } 6427 #undef EPIO_REG 6428 6429 t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN); 6430 return 0; 6431 } 6432 6433 /* t4_mk_filtdelwr - create a delete filter WR 6434 * @ftid: the filter ID 6435 * @wr: the filter work request to populate 6436 * @qid: ingress queue to receive the delete notification 6437 * 6438 * Creates a filter work request to delete the supplied filter. If @qid is 6439 * negative the delete notification is suppressed. 6440 */ 6441 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid) 6442 { 6443 memset(wr, 0, sizeof(*wr)); 6444 wr->op_pkd = cpu_to_be32(V_FW_WR_OP(FW_FILTER_WR)); 6445 wr->len16_pkd = cpu_to_be32(V_FW_WR_LEN16(sizeof(*wr) / 16)); 6446 wr->tid_to_iq = cpu_to_be32(V_FW_FILTER_WR_TID(ftid) | 6447 V_FW_FILTER_WR_NOREPLY(qid < 0)); 6448 wr->del_filter_to_l2tix = cpu_to_be32(F_FW_FILTER_WR_DEL_FILTER); 6449 if (qid >= 0) 6450 wr->rx_chan_rx_rpl_iq = 6451 cpu_to_be16(V_FW_FILTER_WR_RX_RPL_IQ(qid)); 6452 } 6453 6454 #define INIT_CMD(var, cmd, rd_wr) do { \ 6455 (var).op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_##cmd##_CMD) | \ 6456 F_FW_CMD_REQUEST | \ 6457 F_FW_CMD_##rd_wr); \ 6458 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \ 6459 } while (0) 6460 6461 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, 6462 u32 addr, u32 val) 6463 { 6464 u32 ldst_addrspace; 6465 struct fw_ldst_cmd c; 6466 6467 memset(&c, 0, sizeof(c)); 6468 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE); 6469 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6470 F_FW_CMD_REQUEST | 6471 F_FW_CMD_WRITE | 6472 ldst_addrspace); 6473 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6474 c.u.addrval.addr = cpu_to_be32(addr); 6475 c.u.addrval.val = cpu_to_be32(val); 6476 6477 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6478 } 6479 6480 /** 6481 * t4_mdio_rd - read a PHY register through MDIO 6482 * @adap: the adapter 6483 * @mbox: mailbox to use for the FW command 6484 * @phy_addr: the PHY address 6485 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6486 * @reg: the register to read 6487 * @valp: where to store the value 6488 * 6489 * Issues a FW command through the given mailbox to read a PHY register. 6490 */ 6491 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6492 unsigned int mmd, unsigned int reg, unsigned int *valp) 6493 { 6494 int ret; 6495 u32 ldst_addrspace; 6496 struct fw_ldst_cmd c; 6497 6498 memset(&c, 0, sizeof(c)); 6499 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6500 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6501 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6502 ldst_addrspace); 6503 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6504 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6505 V_FW_LDST_CMD_MMD(mmd)); 6506 c.u.mdio.raddr = cpu_to_be16(reg); 6507 6508 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6509 if (ret == 0) 6510 *valp = be16_to_cpu(c.u.mdio.rval); 6511 return ret; 6512 } 6513 6514 /** 6515 * t4_mdio_wr - write a PHY register through MDIO 6516 * @adap: the adapter 6517 * @mbox: mailbox to use for the FW command 6518 * @phy_addr: the PHY address 6519 * @mmd: the PHY MMD to access (0 for clause 22 PHYs) 6520 * @reg: the register to write 6521 * @valp: value to write 6522 * 6523 * Issues a FW command through the given mailbox to write a PHY register. 6524 */ 6525 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 6526 unsigned int mmd, unsigned int reg, unsigned int val) 6527 { 6528 u32 ldst_addrspace; 6529 struct fw_ldst_cmd c; 6530 6531 memset(&c, 0, sizeof(c)); 6532 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO); 6533 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6534 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 6535 ldst_addrspace); 6536 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6537 c.u.mdio.paddr_mmd = cpu_to_be16(V_FW_LDST_CMD_PADDR(phy_addr) | 6538 V_FW_LDST_CMD_MMD(mmd)); 6539 c.u.mdio.raddr = cpu_to_be16(reg); 6540 c.u.mdio.rval = cpu_to_be16(val); 6541 6542 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6543 } 6544 6545 /** 6546 * 6547 * t4_sge_decode_idma_state - decode the idma state 6548 * @adap: the adapter 6549 * @state: the state idma is stuck in 6550 */ 6551 void t4_sge_decode_idma_state(struct adapter *adapter, int state) 6552 { 6553 static const char * const t4_decode[] = { 6554 "IDMA_IDLE", 6555 "IDMA_PUSH_MORE_CPL_FIFO", 6556 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6557 "Not used", 6558 "IDMA_PHYSADDR_SEND_PCIEHDR", 6559 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6560 "IDMA_PHYSADDR_SEND_PAYLOAD", 6561 "IDMA_SEND_FIFO_TO_IMSG", 6562 "IDMA_FL_REQ_DATA_FL_PREP", 6563 "IDMA_FL_REQ_DATA_FL", 6564 "IDMA_FL_DROP", 6565 "IDMA_FL_H_REQ_HEADER_FL", 6566 "IDMA_FL_H_SEND_PCIEHDR", 6567 "IDMA_FL_H_PUSH_CPL_FIFO", 6568 "IDMA_FL_H_SEND_CPL", 6569 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6570 "IDMA_FL_H_SEND_IP_HDR", 6571 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6572 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6573 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6574 "IDMA_FL_D_SEND_PCIEHDR", 6575 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6576 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6577 "IDMA_FL_SEND_PCIEHDR", 6578 "IDMA_FL_PUSH_CPL_FIFO", 6579 "IDMA_FL_SEND_CPL", 6580 "IDMA_FL_SEND_PAYLOAD_FIRST", 6581 "IDMA_FL_SEND_PAYLOAD", 6582 "IDMA_FL_REQ_NEXT_DATA_FL", 6583 "IDMA_FL_SEND_NEXT_PCIEHDR", 6584 "IDMA_FL_SEND_PADDING", 6585 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6586 "IDMA_FL_SEND_FIFO_TO_IMSG", 6587 "IDMA_FL_REQ_DATAFL_DONE", 6588 "IDMA_FL_REQ_HEADERFL_DONE", 6589 }; 6590 static const char * const t5_decode[] = { 6591 "IDMA_IDLE", 6592 "IDMA_ALMOST_IDLE", 6593 "IDMA_PUSH_MORE_CPL_FIFO", 6594 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6595 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6596 "IDMA_PHYSADDR_SEND_PCIEHDR", 6597 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6598 "IDMA_PHYSADDR_SEND_PAYLOAD", 6599 "IDMA_SEND_FIFO_TO_IMSG", 6600 "IDMA_FL_REQ_DATA_FL", 6601 "IDMA_FL_DROP", 6602 "IDMA_FL_DROP_SEND_INC", 6603 "IDMA_FL_H_REQ_HEADER_FL", 6604 "IDMA_FL_H_SEND_PCIEHDR", 6605 "IDMA_FL_H_PUSH_CPL_FIFO", 6606 "IDMA_FL_H_SEND_CPL", 6607 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6608 "IDMA_FL_H_SEND_IP_HDR", 6609 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6610 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6611 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6612 "IDMA_FL_D_SEND_PCIEHDR", 6613 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6614 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6615 "IDMA_FL_SEND_PCIEHDR", 6616 "IDMA_FL_PUSH_CPL_FIFO", 6617 "IDMA_FL_SEND_CPL", 6618 "IDMA_FL_SEND_PAYLOAD_FIRST", 6619 "IDMA_FL_SEND_PAYLOAD", 6620 "IDMA_FL_REQ_NEXT_DATA_FL", 6621 "IDMA_FL_SEND_NEXT_PCIEHDR", 6622 "IDMA_FL_SEND_PADDING", 6623 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6624 }; 6625 static const char * const t6_decode[] = { 6626 "IDMA_IDLE", 6627 "IDMA_PUSH_MORE_CPL_FIFO", 6628 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO", 6629 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR", 6630 "IDMA_PHYSADDR_SEND_PCIEHDR", 6631 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST", 6632 "IDMA_PHYSADDR_SEND_PAYLOAD", 6633 "IDMA_FL_REQ_DATA_FL", 6634 "IDMA_FL_DROP", 6635 "IDMA_FL_DROP_SEND_INC", 6636 "IDMA_FL_H_REQ_HEADER_FL", 6637 "IDMA_FL_H_SEND_PCIEHDR", 6638 "IDMA_FL_H_PUSH_CPL_FIFO", 6639 "IDMA_FL_H_SEND_CPL", 6640 "IDMA_FL_H_SEND_IP_HDR_FIRST", 6641 "IDMA_FL_H_SEND_IP_HDR", 6642 "IDMA_FL_H_REQ_NEXT_HEADER_FL", 6643 "IDMA_FL_H_SEND_NEXT_PCIEHDR", 6644 "IDMA_FL_H_SEND_IP_HDR_PADDING", 6645 "IDMA_FL_D_SEND_PCIEHDR", 6646 "IDMA_FL_D_SEND_CPL_AND_IP_HDR", 6647 "IDMA_FL_D_REQ_NEXT_DATA_FL", 6648 "IDMA_FL_SEND_PCIEHDR", 6649 "IDMA_FL_PUSH_CPL_FIFO", 6650 "IDMA_FL_SEND_CPL", 6651 "IDMA_FL_SEND_PAYLOAD_FIRST", 6652 "IDMA_FL_SEND_PAYLOAD", 6653 "IDMA_FL_REQ_NEXT_DATA_FL", 6654 "IDMA_FL_SEND_NEXT_PCIEHDR", 6655 "IDMA_FL_SEND_PADDING", 6656 "IDMA_FL_SEND_COMPLETION_TO_IMSG", 6657 }; 6658 static const u32 sge_regs[] = { 6659 A_SGE_DEBUG_DATA_LOW_INDEX_2, 6660 A_SGE_DEBUG_DATA_LOW_INDEX_3, 6661 A_SGE_DEBUG_DATA_HIGH_INDEX_10, 6662 }; 6663 const char * const *sge_idma_decode; 6664 int sge_idma_decode_nstates; 6665 int i; 6666 unsigned int chip_version = chip_id(adapter); 6667 6668 /* Select the right set of decode strings to dump depending on the 6669 * adapter chip type. 6670 */ 6671 switch (chip_version) { 6672 case CHELSIO_T4: 6673 sge_idma_decode = (const char * const *)t4_decode; 6674 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode); 6675 break; 6676 6677 case CHELSIO_T5: 6678 sge_idma_decode = (const char * const *)t5_decode; 6679 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode); 6680 break; 6681 6682 case CHELSIO_T6: 6683 sge_idma_decode = (const char * const *)t6_decode; 6684 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode); 6685 break; 6686 6687 default: 6688 CH_ERR(adapter, "Unsupported chip version %d\n", chip_version); 6689 return; 6690 } 6691 6692 if (state < sge_idma_decode_nstates) 6693 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]); 6694 else 6695 CH_WARN(adapter, "idma state %d unknown\n", state); 6696 6697 for (i = 0; i < ARRAY_SIZE(sge_regs); i++) 6698 CH_WARN(adapter, "SGE register %#x value %#x\n", 6699 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); 6700 } 6701 6702 /** 6703 * t4_sge_ctxt_flush - flush the SGE context cache 6704 * @adap: the adapter 6705 * @mbox: mailbox to use for the FW command 6706 * 6707 * Issues a FW command through the given mailbox to flush the 6708 * SGE context cache. 6709 */ 6710 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) 6711 { 6712 int ret; 6713 u32 ldst_addrspace; 6714 struct fw_ldst_cmd c; 6715 6716 memset(&c, 0, sizeof(c)); 6717 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_SGE_EGRC); 6718 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 6719 F_FW_CMD_REQUEST | F_FW_CMD_READ | 6720 ldst_addrspace); 6721 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 6722 c.u.idctxt.msg_ctxtflush = cpu_to_be32(F_FW_LDST_CMD_CTXTFLUSH); 6723 6724 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6725 return ret; 6726 } 6727 6728 /** 6729 * t4_fw_hello - establish communication with FW 6730 * @adap: the adapter 6731 * @mbox: mailbox to use for the FW command 6732 * @evt_mbox: mailbox to receive async FW events 6733 * @master: specifies the caller's willingness to be the device master 6734 * @state: returns the current device state (if non-NULL) 6735 * 6736 * Issues a command to establish communication with FW. Returns either 6737 * an error (negative integer) or the mailbox of the Master PF. 6738 */ 6739 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 6740 enum dev_master master, enum dev_state *state) 6741 { 6742 int ret; 6743 struct fw_hello_cmd c; 6744 u32 v; 6745 unsigned int master_mbox; 6746 int retries = FW_CMD_HELLO_RETRIES; 6747 6748 retry: 6749 memset(&c, 0, sizeof(c)); 6750 INIT_CMD(c, HELLO, WRITE); 6751 c.err_to_clearinit = cpu_to_be32( 6752 V_FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) | 6753 V_FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) | 6754 V_FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? 6755 mbox : M_FW_HELLO_CMD_MBMASTER) | 6756 V_FW_HELLO_CMD_MBASYNCNOT(evt_mbox) | 6757 V_FW_HELLO_CMD_STAGE(FW_HELLO_CMD_STAGE_OS) | 6758 F_FW_HELLO_CMD_CLEARINIT); 6759 6760 /* 6761 * Issue the HELLO command to the firmware. If it's not successful 6762 * but indicates that we got a "busy" or "timeout" condition, retry 6763 * the HELLO until we exhaust our retry limit. If we do exceed our 6764 * retry limit, check to see if the firmware left us any error 6765 * information and report that if so ... 6766 */ 6767 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 6768 if (ret != FW_SUCCESS) { 6769 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0) 6770 goto retry; 6771 if (t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_ERR) 6772 t4_report_fw_error(adap); 6773 return ret; 6774 } 6775 6776 v = be32_to_cpu(c.err_to_clearinit); 6777 master_mbox = G_FW_HELLO_CMD_MBMASTER(v); 6778 if (state) { 6779 if (v & F_FW_HELLO_CMD_ERR) 6780 *state = DEV_STATE_ERR; 6781 else if (v & F_FW_HELLO_CMD_INIT) 6782 *state = DEV_STATE_INIT; 6783 else 6784 *state = DEV_STATE_UNINIT; 6785 } 6786 6787 /* 6788 * If we're not the Master PF then we need to wait around for the 6789 * Master PF Driver to finish setting up the adapter. 6790 * 6791 * Note that we also do this wait if we're a non-Master-capable PF and 6792 * there is no current Master PF; a Master PF may show up momentarily 6793 * and we wouldn't want to fail pointlessly. (This can happen when an 6794 * OS loads lots of different drivers rapidly at the same time). In 6795 * this case, the Master PF returned by the firmware will be 6796 * M_PCIE_FW_MASTER so the test below will work ... 6797 */ 6798 if ((v & (F_FW_HELLO_CMD_ERR|F_FW_HELLO_CMD_INIT)) == 0 && 6799 master_mbox != mbox) { 6800 int waiting = FW_CMD_HELLO_TIMEOUT; 6801 6802 /* 6803 * Wait for the firmware to either indicate an error or 6804 * initialized state. If we see either of these we bail out 6805 * and report the issue to the caller. If we exhaust the 6806 * "hello timeout" and we haven't exhausted our retries, try 6807 * again. Otherwise bail with a timeout error. 6808 */ 6809 for (;;) { 6810 u32 pcie_fw; 6811 6812 msleep(50); 6813 waiting -= 50; 6814 6815 /* 6816 * If neither Error nor Initialialized are indicated 6817 * by the firmware keep waiting till we exhaust our 6818 * timeout ... and then retry if we haven't exhausted 6819 * our retries ... 6820 */ 6821 pcie_fw = t4_read_reg(adap, A_PCIE_FW); 6822 if (!(pcie_fw & (F_PCIE_FW_ERR|F_PCIE_FW_INIT))) { 6823 if (waiting <= 0) { 6824 if (retries-- > 0) 6825 goto retry; 6826 6827 return -ETIMEDOUT; 6828 } 6829 continue; 6830 } 6831 6832 /* 6833 * We either have an Error or Initialized condition 6834 * report errors preferentially. 6835 */ 6836 if (state) { 6837 if (pcie_fw & F_PCIE_FW_ERR) 6838 *state = DEV_STATE_ERR; 6839 else if (pcie_fw & F_PCIE_FW_INIT) 6840 *state = DEV_STATE_INIT; 6841 } 6842 6843 /* 6844 * If we arrived before a Master PF was selected and 6845 * there's not a valid Master PF, grab its identity 6846 * for our caller. 6847 */ 6848 if (master_mbox == M_PCIE_FW_MASTER && 6849 (pcie_fw & F_PCIE_FW_MASTER_VLD)) 6850 master_mbox = G_PCIE_FW_MASTER(pcie_fw); 6851 break; 6852 } 6853 } 6854 6855 return master_mbox; 6856 } 6857 6858 /** 6859 * t4_fw_bye - end communication with FW 6860 * @adap: the adapter 6861 * @mbox: mailbox to use for the FW command 6862 * 6863 * Issues a command to terminate communication with FW. 6864 */ 6865 int t4_fw_bye(struct adapter *adap, unsigned int mbox) 6866 { 6867 struct fw_bye_cmd c; 6868 6869 memset(&c, 0, sizeof(c)); 6870 INIT_CMD(c, BYE, WRITE); 6871 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6872 } 6873 6874 /** 6875 * t4_fw_reset - issue a reset to FW 6876 * @adap: the adapter 6877 * @mbox: mailbox to use for the FW command 6878 * @reset: specifies the type of reset to perform 6879 * 6880 * Issues a reset command of the specified type to FW. 6881 */ 6882 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) 6883 { 6884 struct fw_reset_cmd c; 6885 6886 memset(&c, 0, sizeof(c)); 6887 INIT_CMD(c, RESET, WRITE); 6888 c.val = cpu_to_be32(reset); 6889 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6890 } 6891 6892 /** 6893 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET 6894 * @adap: the adapter 6895 * @mbox: mailbox to use for the FW RESET command (if desired) 6896 * @force: force uP into RESET even if FW RESET command fails 6897 * 6898 * Issues a RESET command to firmware (if desired) with a HALT indication 6899 * and then puts the microprocessor into RESET state. The RESET command 6900 * will only be issued if a legitimate mailbox is provided (mbox <= 6901 * M_PCIE_FW_MASTER). 6902 * 6903 * This is generally used in order for the host to safely manipulate the 6904 * adapter without fear of conflicting with whatever the firmware might 6905 * be doing. The only way out of this state is to RESTART the firmware 6906 * ... 6907 */ 6908 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) 6909 { 6910 int ret = 0; 6911 6912 /* 6913 * If a legitimate mailbox is provided, issue a RESET command 6914 * with a HALT indication. 6915 */ 6916 if (adap->flags & FW_OK && mbox <= M_PCIE_FW_MASTER) { 6917 struct fw_reset_cmd c; 6918 6919 memset(&c, 0, sizeof(c)); 6920 INIT_CMD(c, RESET, WRITE); 6921 c.val = cpu_to_be32(F_PIORST | F_PIORSTMODE); 6922 c.halt_pkd = cpu_to_be32(F_FW_RESET_CMD_HALT); 6923 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 6924 } 6925 6926 /* 6927 * Normally we won't complete the operation if the firmware RESET 6928 * command fails but if our caller insists we'll go ahead and put the 6929 * uP into RESET. This can be useful if the firmware is hung or even 6930 * missing ... We'll have to take the risk of putting the uP into 6931 * RESET without the cooperation of firmware in that case. 6932 * 6933 * We also force the firmware's HALT flag to be on in case we bypassed 6934 * the firmware RESET command above or we're dealing with old firmware 6935 * which doesn't have the HALT capability. This will serve as a flag 6936 * for the incoming firmware to know that it's coming out of a HALT 6937 * rather than a RESET ... if it's new enough to understand that ... 6938 */ 6939 if (ret == 0 || force) { 6940 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, F_UPCRST); 6941 t4_set_reg_field(adap, A_PCIE_FW, F_PCIE_FW_HALT, 6942 F_PCIE_FW_HALT); 6943 } 6944 6945 /* 6946 * And we always return the result of the firmware RESET command 6947 * even when we force the uP into RESET ... 6948 */ 6949 return ret; 6950 } 6951 6952 /** 6953 * t4_fw_restart - restart the firmware by taking the uP out of RESET 6954 * @adap: the adapter 6955 * 6956 * Restart firmware previously halted by t4_fw_halt(). On successful 6957 * return the previous PF Master remains as the new PF Master and there 6958 * is no need to issue a new HELLO command, etc. 6959 */ 6960 int t4_fw_restart(struct adapter *adap, unsigned int mbox) 6961 { 6962 int ms; 6963 6964 t4_set_reg_field(adap, A_CIM_BOOT_CFG, F_UPCRST, 0); 6965 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 6966 if (!(t4_read_reg(adap, A_PCIE_FW) & F_PCIE_FW_HALT)) 6967 return FW_SUCCESS; 6968 msleep(100); 6969 ms += 100; 6970 } 6971 6972 return -ETIMEDOUT; 6973 } 6974 6975 /** 6976 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW 6977 * @adap: the adapter 6978 * @mbox: mailbox to use for the FW RESET command (if desired) 6979 * @fw_data: the firmware image to write 6980 * @size: image size 6981 * @force: force upgrade even if firmware doesn't cooperate 6982 * 6983 * Perform all of the steps necessary for upgrading an adapter's 6984 * firmware image. Normally this requires the cooperation of the 6985 * existing firmware in order to halt all existing activities 6986 * but if an invalid mailbox token is passed in we skip that step 6987 * (though we'll still put the adapter microprocessor into RESET in 6988 * that case). 6989 * 6990 * On successful return the new firmware will have been loaded and 6991 * the adapter will have been fully RESET losing all previous setup 6992 * state. On unsuccessful return the adapter may be completely hosed ... 6993 * positive errno indicates that the adapter is ~probably~ intact, a 6994 * negative errno indicates that things are looking bad ... 6995 */ 6996 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 6997 const u8 *fw_data, unsigned int size, int force) 6998 { 6999 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data; 7000 unsigned int bootstrap = 7001 be32_to_cpu(fw_hdr->magic) == FW_HDR_MAGIC_BOOTSTRAP; 7002 int ret; 7003 7004 if (!t4_fw_matches_chip(adap, fw_hdr)) 7005 return -EINVAL; 7006 7007 if (!bootstrap) { 7008 ret = t4_fw_halt(adap, mbox, force); 7009 if (ret < 0 && !force) 7010 return ret; 7011 } 7012 7013 ret = t4_load_fw(adap, fw_data, size); 7014 if (ret < 0 || bootstrap) 7015 return ret; 7016 7017 return t4_fw_restart(adap, mbox); 7018 } 7019 7020 /** 7021 * t4_fw_initialize - ask FW to initialize the device 7022 * @adap: the adapter 7023 * @mbox: mailbox to use for the FW command 7024 * 7025 * Issues a command to FW to partially initialize the device. This 7026 * performs initialization that generally doesn't depend on user input. 7027 */ 7028 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) 7029 { 7030 struct fw_initialize_cmd c; 7031 7032 memset(&c, 0, sizeof(c)); 7033 INIT_CMD(c, INITIALIZE, WRITE); 7034 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7035 } 7036 7037 /** 7038 * t4_query_params_rw - query FW or device parameters 7039 * @adap: the adapter 7040 * @mbox: mailbox to use for the FW command 7041 * @pf: the PF 7042 * @vf: the VF 7043 * @nparams: the number of parameters 7044 * @params: the parameter names 7045 * @val: the parameter values 7046 * @rw: Write and read flag 7047 * 7048 * Reads the value of FW or device parameters. Up to 7 parameters can be 7049 * queried at once. 7050 */ 7051 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 7052 unsigned int vf, unsigned int nparams, const u32 *params, 7053 u32 *val, int rw) 7054 { 7055 int i, ret; 7056 struct fw_params_cmd c; 7057 __be32 *p = &c.param[0].mnem; 7058 7059 if (nparams > 7) 7060 return -EINVAL; 7061 7062 memset(&c, 0, sizeof(c)); 7063 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7064 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7065 V_FW_PARAMS_CMD_PFN(pf) | 7066 V_FW_PARAMS_CMD_VFN(vf)); 7067 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7068 7069 for (i = 0; i < nparams; i++) { 7070 *p++ = cpu_to_be32(*params++); 7071 if (rw) 7072 *p = cpu_to_be32(*(val + i)); 7073 p++; 7074 } 7075 7076 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7077 if (ret == 0) 7078 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2) 7079 *val++ = be32_to_cpu(*p); 7080 return ret; 7081 } 7082 7083 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7084 unsigned int vf, unsigned int nparams, const u32 *params, 7085 u32 *val) 7086 { 7087 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0); 7088 } 7089 7090 /** 7091 * t4_set_params_timeout - sets FW or device parameters 7092 * @adap: the adapter 7093 * @mbox: mailbox to use for the FW command 7094 * @pf: the PF 7095 * @vf: the VF 7096 * @nparams: the number of parameters 7097 * @params: the parameter names 7098 * @val: the parameter values 7099 * @timeout: the timeout time 7100 * 7101 * Sets the value of FW or device parameters. Up to 7 parameters can be 7102 * specified at once. 7103 */ 7104 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 7105 unsigned int pf, unsigned int vf, 7106 unsigned int nparams, const u32 *params, 7107 const u32 *val, int timeout) 7108 { 7109 struct fw_params_cmd c; 7110 __be32 *p = &c.param[0].mnem; 7111 7112 if (nparams > 7) 7113 return -EINVAL; 7114 7115 memset(&c, 0, sizeof(c)); 7116 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PARAMS_CMD) | 7117 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7118 V_FW_PARAMS_CMD_PFN(pf) | 7119 V_FW_PARAMS_CMD_VFN(vf)); 7120 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7121 7122 while (nparams--) { 7123 *p++ = cpu_to_be32(*params++); 7124 *p++ = cpu_to_be32(*val++); 7125 } 7126 7127 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); 7128 } 7129 7130 /** 7131 * t4_set_params - sets FW or device parameters 7132 * @adap: the adapter 7133 * @mbox: mailbox to use for the FW command 7134 * @pf: the PF 7135 * @vf: the VF 7136 * @nparams: the number of parameters 7137 * @params: the parameter names 7138 * @val: the parameter values 7139 * 7140 * Sets the value of FW or device parameters. Up to 7 parameters can be 7141 * specified at once. 7142 */ 7143 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 7144 unsigned int vf, unsigned int nparams, const u32 *params, 7145 const u32 *val) 7146 { 7147 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, 7148 FW_CMD_MAX_TIMEOUT); 7149 } 7150 7151 /** 7152 * t4_cfg_pfvf - configure PF/VF resource limits 7153 * @adap: the adapter 7154 * @mbox: mailbox to use for the FW command 7155 * @pf: the PF being configured 7156 * @vf: the VF being configured 7157 * @txq: the max number of egress queues 7158 * @txq_eth_ctrl: the max number of egress Ethernet or control queues 7159 * @rxqi: the max number of interrupt-capable ingress queues 7160 * @rxq: the max number of interruptless ingress queues 7161 * @tc: the PCI traffic class 7162 * @vi: the max number of virtual interfaces 7163 * @cmask: the channel access rights mask for the PF/VF 7164 * @pmask: the port access rights mask for the PF/VF 7165 * @nexact: the maximum number of exact MPS filters 7166 * @rcaps: read capabilities 7167 * @wxcaps: write/execute capabilities 7168 * 7169 * Configures resource limits and capabilities for a physical or virtual 7170 * function. 7171 */ 7172 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 7173 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 7174 unsigned int rxqi, unsigned int rxq, unsigned int tc, 7175 unsigned int vi, unsigned int cmask, unsigned int pmask, 7176 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps) 7177 { 7178 struct fw_pfvf_cmd c; 7179 7180 memset(&c, 0, sizeof(c)); 7181 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_PFVF_CMD) | F_FW_CMD_REQUEST | 7182 F_FW_CMD_WRITE | V_FW_PFVF_CMD_PFN(pf) | 7183 V_FW_PFVF_CMD_VFN(vf)); 7184 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7185 c.niqflint_niq = cpu_to_be32(V_FW_PFVF_CMD_NIQFLINT(rxqi) | 7186 V_FW_PFVF_CMD_NIQ(rxq)); 7187 c.type_to_neq = cpu_to_be32(V_FW_PFVF_CMD_CMASK(cmask) | 7188 V_FW_PFVF_CMD_PMASK(pmask) | 7189 V_FW_PFVF_CMD_NEQ(txq)); 7190 c.tc_to_nexactf = cpu_to_be32(V_FW_PFVF_CMD_TC(tc) | 7191 V_FW_PFVF_CMD_NVI(vi) | 7192 V_FW_PFVF_CMD_NEXACTF(nexact)); 7193 c.r_caps_to_nethctrl = cpu_to_be32(V_FW_PFVF_CMD_R_CAPS(rcaps) | 7194 V_FW_PFVF_CMD_WX_CAPS(wxcaps) | 7195 V_FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl)); 7196 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7197 } 7198 7199 /** 7200 * t4_alloc_vi_func - allocate a virtual interface 7201 * @adap: the adapter 7202 * @mbox: mailbox to use for the FW command 7203 * @port: physical port associated with the VI 7204 * @pf: the PF owning the VI 7205 * @vf: the VF owning the VI 7206 * @nmac: number of MAC addresses needed (1 to 5) 7207 * @mac: the MAC addresses of the VI 7208 * @rss_size: size of RSS table slice associated with this VI 7209 * @portfunc: which Port Application Function MAC Address is desired 7210 * @idstype: Intrusion Detection Type 7211 * 7212 * Allocates a virtual interface for the given physical port. If @mac is 7213 * not %NULL it contains the MAC addresses of the VI as assigned by FW. 7214 * If @rss_size is %NULL the VI is not assigned any RSS slice by FW. 7215 * @mac should be large enough to hold @nmac Ethernet addresses, they are 7216 * stored consecutively so the space needed is @nmac * 6 bytes. 7217 * Returns a negative error number or the non-negative VI id. 7218 */ 7219 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 7220 unsigned int port, unsigned int pf, unsigned int vf, 7221 unsigned int nmac, u8 *mac, u16 *rss_size, 7222 unsigned int portfunc, unsigned int idstype) 7223 { 7224 int ret; 7225 struct fw_vi_cmd c; 7226 7227 memset(&c, 0, sizeof(c)); 7228 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | F_FW_CMD_REQUEST | 7229 F_FW_CMD_WRITE | F_FW_CMD_EXEC | 7230 V_FW_VI_CMD_PFN(pf) | V_FW_VI_CMD_VFN(vf)); 7231 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_ALLOC | FW_LEN16(c)); 7232 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_TYPE(idstype) | 7233 V_FW_VI_CMD_FUNC(portfunc)); 7234 c.portid_pkd = V_FW_VI_CMD_PORTID(port); 7235 c.nmac = nmac - 1; 7236 if(!rss_size) 7237 c.norss_rsssize = F_FW_VI_CMD_NORSS; 7238 7239 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7240 if (ret) 7241 return ret; 7242 7243 if (mac) { 7244 memcpy(mac, c.mac, sizeof(c.mac)); 7245 switch (nmac) { 7246 case 5: 7247 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3)); 7248 case 4: 7249 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2)); 7250 case 3: 7251 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1)); 7252 case 2: 7253 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0)); 7254 } 7255 } 7256 if (rss_size) 7257 *rss_size = G_FW_VI_CMD_RSSSIZE(be16_to_cpu(c.norss_rsssize)); 7258 return G_FW_VI_CMD_VIID(be16_to_cpu(c.type_to_viid)); 7259 } 7260 7261 /** 7262 * t4_alloc_vi - allocate an [Ethernet Function] virtual interface 7263 * @adap: the adapter 7264 * @mbox: mailbox to use for the FW command 7265 * @port: physical port associated with the VI 7266 * @pf: the PF owning the VI 7267 * @vf: the VF owning the VI 7268 * @nmac: number of MAC addresses needed (1 to 5) 7269 * @mac: the MAC addresses of the VI 7270 * @rss_size: size of RSS table slice associated with this VI 7271 * 7272 * backwards compatible and convieniance routine to allocate a Virtual 7273 * Interface with a Ethernet Port Application Function and Intrustion 7274 * Detection System disabled. 7275 */ 7276 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 7277 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 7278 u16 *rss_size) 7279 { 7280 return t4_alloc_vi_func(adap, mbox, port, pf, vf, nmac, mac, rss_size, 7281 FW_VI_FUNC_ETH, 0); 7282 } 7283 7284 /** 7285 * t4_free_vi - free a virtual interface 7286 * @adap: the adapter 7287 * @mbox: mailbox to use for the FW command 7288 * @pf: the PF owning the VI 7289 * @vf: the VF owning the VI 7290 * @viid: virtual interface identifiler 7291 * 7292 * Free a previously allocated virtual interface. 7293 */ 7294 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, 7295 unsigned int vf, unsigned int viid) 7296 { 7297 struct fw_vi_cmd c; 7298 7299 memset(&c, 0, sizeof(c)); 7300 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_VI_CMD) | 7301 F_FW_CMD_REQUEST | 7302 F_FW_CMD_EXEC | 7303 V_FW_VI_CMD_PFN(pf) | 7304 V_FW_VI_CMD_VFN(vf)); 7305 c.alloc_to_len16 = cpu_to_be32(F_FW_VI_CMD_FREE | FW_LEN16(c)); 7306 c.type_to_viid = cpu_to_be16(V_FW_VI_CMD_VIID(viid)); 7307 7308 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7309 } 7310 7311 /** 7312 * t4_set_rxmode - set Rx properties of a virtual interface 7313 * @adap: the adapter 7314 * @mbox: mailbox to use for the FW command 7315 * @viid: the VI id 7316 * @mtu: the new MTU or -1 7317 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change 7318 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change 7319 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change 7320 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change 7321 * @sleep_ok: if true we may sleep while awaiting command completion 7322 * 7323 * Sets Rx properties of a virtual interface. 7324 */ 7325 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 7326 int mtu, int promisc, int all_multi, int bcast, int vlanex, 7327 bool sleep_ok) 7328 { 7329 struct fw_vi_rxmode_cmd c; 7330 7331 /* convert to FW values */ 7332 if (mtu < 0) 7333 mtu = M_FW_VI_RXMODE_CMD_MTU; 7334 if (promisc < 0) 7335 promisc = M_FW_VI_RXMODE_CMD_PROMISCEN; 7336 if (all_multi < 0) 7337 all_multi = M_FW_VI_RXMODE_CMD_ALLMULTIEN; 7338 if (bcast < 0) 7339 bcast = M_FW_VI_RXMODE_CMD_BROADCASTEN; 7340 if (vlanex < 0) 7341 vlanex = M_FW_VI_RXMODE_CMD_VLANEXEN; 7342 7343 memset(&c, 0, sizeof(c)); 7344 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_RXMODE_CMD) | 7345 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7346 V_FW_VI_RXMODE_CMD_VIID(viid)); 7347 c.retval_len16 = cpu_to_be32(FW_LEN16(c)); 7348 c.mtu_to_vlanexen = 7349 cpu_to_be32(V_FW_VI_RXMODE_CMD_MTU(mtu) | 7350 V_FW_VI_RXMODE_CMD_PROMISCEN(promisc) | 7351 V_FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) | 7352 V_FW_VI_RXMODE_CMD_BROADCASTEN(bcast) | 7353 V_FW_VI_RXMODE_CMD_VLANEXEN(vlanex)); 7354 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7355 } 7356 7357 /** 7358 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses 7359 * @adap: the adapter 7360 * @mbox: mailbox to use for the FW command 7361 * @viid: the VI id 7362 * @free: if true any existing filters for this VI id are first removed 7363 * @naddr: the number of MAC addresses to allocate filters for (up to 7) 7364 * @addr: the MAC address(es) 7365 * @idx: where to store the index of each allocated filter 7366 * @hash: pointer to hash address filter bitmap 7367 * @sleep_ok: call is allowed to sleep 7368 * 7369 * Allocates an exact-match filter for each of the supplied addresses and 7370 * sets it to the corresponding address. If @idx is not %NULL it should 7371 * have at least @naddr entries, each of which will be set to the index of 7372 * the filter allocated for the corresponding MAC address. If a filter 7373 * could not be allocated for an address its index is set to 0xffff. 7374 * If @hash is not %NULL addresses that fail to allocate an exact filter 7375 * are hashed and update the hash filter bitmap pointed at by @hash. 7376 * 7377 * Returns a negative error number or the number of filters allocated. 7378 */ 7379 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, 7380 unsigned int viid, bool free, unsigned int naddr, 7381 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok) 7382 { 7383 int offset, ret = 0; 7384 struct fw_vi_mac_cmd c; 7385 unsigned int nfilters = 0; 7386 unsigned int max_naddr = adap->chip_params->mps_tcam_size; 7387 unsigned int rem = naddr; 7388 7389 if (naddr > max_naddr) 7390 return -EINVAL; 7391 7392 for (offset = 0; offset < naddr ; /**/) { 7393 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) 7394 ? rem 7395 : ARRAY_SIZE(c.u.exact)); 7396 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd, 7397 u.exact[fw_naddr]), 16); 7398 struct fw_vi_mac_exact *p; 7399 int i; 7400 7401 memset(&c, 0, sizeof(c)); 7402 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7403 F_FW_CMD_REQUEST | 7404 F_FW_CMD_WRITE | 7405 V_FW_CMD_EXEC(free) | 7406 V_FW_VI_MAC_CMD_VIID(viid)); 7407 c.freemacs_to_len16 = cpu_to_be32(V_FW_VI_MAC_CMD_FREEMACS(free) | 7408 V_FW_CMD_LEN16(len16)); 7409 7410 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7411 p->valid_to_idx = 7412 cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7413 V_FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC)); 7414 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr)); 7415 } 7416 7417 /* 7418 * It's okay if we run out of space in our MAC address arena. 7419 * Some of the addresses we submit may get stored so we need 7420 * to run through the reply to see what the results were ... 7421 */ 7422 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); 7423 if (ret && ret != -FW_ENOMEM) 7424 break; 7425 7426 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) { 7427 u16 index = G_FW_VI_MAC_CMD_IDX( 7428 be16_to_cpu(p->valid_to_idx)); 7429 7430 if (idx) 7431 idx[offset+i] = (index >= max_naddr 7432 ? 0xffff 7433 : index); 7434 if (index < max_naddr) 7435 nfilters++; 7436 else if (hash) 7437 *hash |= (1ULL << hash_mac_addr(addr[offset+i])); 7438 } 7439 7440 free = false; 7441 offset += fw_naddr; 7442 rem -= fw_naddr; 7443 } 7444 7445 if (ret == 0 || ret == -FW_ENOMEM) 7446 ret = nfilters; 7447 return ret; 7448 } 7449 7450 /** 7451 * t4_change_mac - modifies the exact-match filter for a MAC address 7452 * @adap: the adapter 7453 * @mbox: mailbox to use for the FW command 7454 * @viid: the VI id 7455 * @idx: index of existing filter for old value of MAC address, or -1 7456 * @addr: the new MAC address value 7457 * @persist: whether a new MAC allocation should be persistent 7458 * @add_smt: if true also add the address to the HW SMT 7459 * 7460 * Modifies an exact-match filter and sets it to the new MAC address if 7461 * @idx >= 0, or adds the MAC address to a new filter if @idx < 0. In the 7462 * latter case the address is added persistently if @persist is %true. 7463 * 7464 * Note that in general it is not possible to modify the value of a given 7465 * filter so the generic way to modify an address filter is to free the one 7466 * being used by the old address value and allocate a new filter for the 7467 * new address value. 7468 * 7469 * Returns a negative error number or the index of the filter with the new 7470 * MAC value. Note that this index may differ from @idx. 7471 */ 7472 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 7473 int idx, const u8 *addr, bool persist, bool add_smt) 7474 { 7475 int ret, mode; 7476 struct fw_vi_mac_cmd c; 7477 struct fw_vi_mac_exact *p = c.u.exact; 7478 unsigned int max_mac_addr = adap->chip_params->mps_tcam_size; 7479 7480 if (idx < 0) /* new allocation */ 7481 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC; 7482 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY; 7483 7484 memset(&c, 0, sizeof(c)); 7485 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7486 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7487 V_FW_VI_MAC_CMD_VIID(viid)); 7488 c.freemacs_to_len16 = cpu_to_be32(V_FW_CMD_LEN16(1)); 7489 p->valid_to_idx = cpu_to_be16(F_FW_VI_MAC_CMD_VALID | 7490 V_FW_VI_MAC_CMD_SMAC_RESULT(mode) | 7491 V_FW_VI_MAC_CMD_IDX(idx)); 7492 memcpy(p->macaddr, addr, sizeof(p->macaddr)); 7493 7494 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 7495 if (ret == 0) { 7496 ret = G_FW_VI_MAC_CMD_IDX(be16_to_cpu(p->valid_to_idx)); 7497 if (ret >= max_mac_addr) 7498 ret = -ENOMEM; 7499 } 7500 return ret; 7501 } 7502 7503 /** 7504 * t4_set_addr_hash - program the MAC inexact-match hash filter 7505 * @adap: the adapter 7506 * @mbox: mailbox to use for the FW command 7507 * @viid: the VI id 7508 * @ucast: whether the hash filter should also match unicast addresses 7509 * @vec: the value to be written to the hash filter 7510 * @sleep_ok: call is allowed to sleep 7511 * 7512 * Sets the 64-bit inexact-match hash filter for a virtual interface. 7513 */ 7514 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 7515 bool ucast, u64 vec, bool sleep_ok) 7516 { 7517 struct fw_vi_mac_cmd c; 7518 u32 val; 7519 7520 memset(&c, 0, sizeof(c)); 7521 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_MAC_CMD) | 7522 F_FW_CMD_REQUEST | F_FW_CMD_WRITE | 7523 V_FW_VI_ENABLE_CMD_VIID(viid)); 7524 val = V_FW_VI_MAC_CMD_ENTRY_TYPE(FW_VI_MAC_TYPE_HASHVEC) | 7525 V_FW_VI_MAC_CMD_HASHUNIEN(ucast) | V_FW_CMD_LEN16(1); 7526 c.freemacs_to_len16 = cpu_to_be32(val); 7527 c.u.hash.hashvec = cpu_to_be64(vec); 7528 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); 7529 } 7530 7531 /** 7532 * t4_enable_vi_params - enable/disable a virtual interface 7533 * @adap: the adapter 7534 * @mbox: mailbox to use for the FW command 7535 * @viid: the VI id 7536 * @rx_en: 1=enable Rx, 0=disable Rx 7537 * @tx_en: 1=enable Tx, 0=disable Tx 7538 * @dcb_en: 1=enable delivery of Data Center Bridging messages. 7539 * 7540 * Enables/disables a virtual interface. Note that setting DCB Enable 7541 * only makes sense when enabling a Virtual Interface ... 7542 */ 7543 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 7544 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en) 7545 { 7546 struct fw_vi_enable_cmd c; 7547 7548 memset(&c, 0, sizeof(c)); 7549 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7550 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7551 V_FW_VI_ENABLE_CMD_VIID(viid)); 7552 c.ien_to_len16 = cpu_to_be32(V_FW_VI_ENABLE_CMD_IEN(rx_en) | 7553 V_FW_VI_ENABLE_CMD_EEN(tx_en) | 7554 V_FW_VI_ENABLE_CMD_DCB_INFO(dcb_en) | 7555 FW_LEN16(c)); 7556 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); 7557 } 7558 7559 /** 7560 * t4_enable_vi - enable/disable a virtual interface 7561 * @adap: the adapter 7562 * @mbox: mailbox to use for the FW command 7563 * @viid: the VI id 7564 * @rx_en: 1=enable Rx, 0=disable Rx 7565 * @tx_en: 1=enable Tx, 0=disable Tx 7566 * 7567 * Enables/disables a virtual interface. Note that setting DCB Enable 7568 * only makes sense when enabling a Virtual Interface ... 7569 */ 7570 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 7571 bool rx_en, bool tx_en) 7572 { 7573 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); 7574 } 7575 7576 /** 7577 * t4_identify_port - identify a VI's port by blinking its LED 7578 * @adap: the adapter 7579 * @mbox: mailbox to use for the FW command 7580 * @viid: the VI id 7581 * @nblinks: how many times to blink LED at 2.5 Hz 7582 * 7583 * Identifies a VI's port by blinking its LED. 7584 */ 7585 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 7586 unsigned int nblinks) 7587 { 7588 struct fw_vi_enable_cmd c; 7589 7590 memset(&c, 0, sizeof(c)); 7591 c.op_to_viid = cpu_to_be32(V_FW_CMD_OP(FW_VI_ENABLE_CMD) | 7592 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7593 V_FW_VI_ENABLE_CMD_VIID(viid)); 7594 c.ien_to_len16 = cpu_to_be32(F_FW_VI_ENABLE_CMD_LED | FW_LEN16(c)); 7595 c.blinkdur = cpu_to_be16(nblinks); 7596 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7597 } 7598 7599 /** 7600 * t4_iq_stop - stop an ingress queue and its FLs 7601 * @adap: the adapter 7602 * @mbox: mailbox to use for the FW command 7603 * @pf: the PF owning the queues 7604 * @vf: the VF owning the queues 7605 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7606 * @iqid: ingress queue id 7607 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7608 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7609 * 7610 * Stops an ingress queue and its associated FLs, if any. This causes 7611 * any current or future data/messages destined for these queues to be 7612 * tossed. 7613 */ 7614 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 7615 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7616 unsigned int fl0id, unsigned int fl1id) 7617 { 7618 struct fw_iq_cmd c; 7619 7620 memset(&c, 0, sizeof(c)); 7621 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7622 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7623 V_FW_IQ_CMD_VFN(vf)); 7624 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_IQSTOP | FW_LEN16(c)); 7625 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7626 c.iqid = cpu_to_be16(iqid); 7627 c.fl0id = cpu_to_be16(fl0id); 7628 c.fl1id = cpu_to_be16(fl1id); 7629 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7630 } 7631 7632 /** 7633 * t4_iq_free - free an ingress queue and its FLs 7634 * @adap: the adapter 7635 * @mbox: mailbox to use for the FW command 7636 * @pf: the PF owning the queues 7637 * @vf: the VF owning the queues 7638 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.) 7639 * @iqid: ingress queue id 7640 * @fl0id: FL0 queue id or 0xffff if no attached FL0 7641 * @fl1id: FL1 queue id or 0xffff if no attached FL1 7642 * 7643 * Frees an ingress queue and its associated FLs, if any. 7644 */ 7645 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7646 unsigned int vf, unsigned int iqtype, unsigned int iqid, 7647 unsigned int fl0id, unsigned int fl1id) 7648 { 7649 struct fw_iq_cmd c; 7650 7651 memset(&c, 0, sizeof(c)); 7652 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST | 7653 F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(pf) | 7654 V_FW_IQ_CMD_VFN(vf)); 7655 c.alloc_to_len16 = cpu_to_be32(F_FW_IQ_CMD_FREE | FW_LEN16(c)); 7656 c.type_to_iqandstindex = cpu_to_be32(V_FW_IQ_CMD_TYPE(iqtype)); 7657 c.iqid = cpu_to_be16(iqid); 7658 c.fl0id = cpu_to_be16(fl0id); 7659 c.fl1id = cpu_to_be16(fl1id); 7660 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7661 } 7662 7663 /** 7664 * t4_eth_eq_free - free an Ethernet egress queue 7665 * @adap: the adapter 7666 * @mbox: mailbox to use for the FW command 7667 * @pf: the PF owning the queue 7668 * @vf: the VF owning the queue 7669 * @eqid: egress queue id 7670 * 7671 * Frees an Ethernet egress queue. 7672 */ 7673 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7674 unsigned int vf, unsigned int eqid) 7675 { 7676 struct fw_eq_eth_cmd c; 7677 7678 memset(&c, 0, sizeof(c)); 7679 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | 7680 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7681 V_FW_EQ_ETH_CMD_PFN(pf) | 7682 V_FW_EQ_ETH_CMD_VFN(vf)); 7683 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_ETH_CMD_FREE | FW_LEN16(c)); 7684 c.eqid_pkd = cpu_to_be32(V_FW_EQ_ETH_CMD_EQID(eqid)); 7685 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7686 } 7687 7688 /** 7689 * t4_ctrl_eq_free - free a control egress queue 7690 * @adap: the adapter 7691 * @mbox: mailbox to use for the FW command 7692 * @pf: the PF owning the queue 7693 * @vf: the VF owning the queue 7694 * @eqid: egress queue id 7695 * 7696 * Frees a control egress queue. 7697 */ 7698 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7699 unsigned int vf, unsigned int eqid) 7700 { 7701 struct fw_eq_ctrl_cmd c; 7702 7703 memset(&c, 0, sizeof(c)); 7704 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | 7705 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7706 V_FW_EQ_CTRL_CMD_PFN(pf) | 7707 V_FW_EQ_CTRL_CMD_VFN(vf)); 7708 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_CTRL_CMD_FREE | FW_LEN16(c)); 7709 c.cmpliqid_eqid = cpu_to_be32(V_FW_EQ_CTRL_CMD_EQID(eqid)); 7710 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7711 } 7712 7713 /** 7714 * t4_ofld_eq_free - free an offload egress queue 7715 * @adap: the adapter 7716 * @mbox: mailbox to use for the FW command 7717 * @pf: the PF owning the queue 7718 * @vf: the VF owning the queue 7719 * @eqid: egress queue id 7720 * 7721 * Frees a control egress queue. 7722 */ 7723 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 7724 unsigned int vf, unsigned int eqid) 7725 { 7726 struct fw_eq_ofld_cmd c; 7727 7728 memset(&c, 0, sizeof(c)); 7729 c.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | 7730 F_FW_CMD_REQUEST | F_FW_CMD_EXEC | 7731 V_FW_EQ_OFLD_CMD_PFN(pf) | 7732 V_FW_EQ_OFLD_CMD_VFN(vf)); 7733 c.alloc_to_len16 = cpu_to_be32(F_FW_EQ_OFLD_CMD_FREE | FW_LEN16(c)); 7734 c.eqid_pkd = cpu_to_be32(V_FW_EQ_OFLD_CMD_EQID(eqid)); 7735 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); 7736 } 7737 7738 /** 7739 * t4_link_down_rc_str - return a string for a Link Down Reason Code 7740 * @link_down_rc: Link Down Reason Code 7741 * 7742 * Returns a string representation of the Link Down Reason Code. 7743 */ 7744 const char *t4_link_down_rc_str(unsigned char link_down_rc) 7745 { 7746 static const char *reason[] = { 7747 "Link Down", 7748 "Remote Fault", 7749 "Auto-negotiation Failure", 7750 "Reserved3", 7751 "Insufficient Airflow", 7752 "Unable To Determine Reason", 7753 "No RX Signal Detected", 7754 "Reserved7", 7755 }; 7756 7757 if (link_down_rc >= ARRAY_SIZE(reason)) 7758 return "Bad Reason Code"; 7759 7760 return reason[link_down_rc]; 7761 } 7762 7763 /* 7764 * Return the highest speed set in the port capabilities, in Mb/s. 7765 */ 7766 unsigned int fwcap_to_speed(uint32_t caps) 7767 { 7768 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 7769 do { \ 7770 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 7771 return __speed; \ 7772 } while (0) 7773 7774 TEST_SPEED_RETURN(400G, 400000); 7775 TEST_SPEED_RETURN(200G, 200000); 7776 TEST_SPEED_RETURN(100G, 100000); 7777 TEST_SPEED_RETURN(50G, 50000); 7778 TEST_SPEED_RETURN(40G, 40000); 7779 TEST_SPEED_RETURN(25G, 25000); 7780 TEST_SPEED_RETURN(10G, 10000); 7781 TEST_SPEED_RETURN(1G, 1000); 7782 TEST_SPEED_RETURN(100M, 100); 7783 7784 #undef TEST_SPEED_RETURN 7785 7786 return 0; 7787 } 7788 7789 /* 7790 * Return the port capabilities bit for the given speed, which is in Mb/s. 7791 */ 7792 uint32_t speed_to_fwcap(unsigned int speed) 7793 { 7794 #define TEST_SPEED_RETURN(__caps_speed, __speed) \ 7795 do { \ 7796 if (speed == __speed) \ 7797 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 7798 } while (0) 7799 7800 TEST_SPEED_RETURN(400G, 400000); 7801 TEST_SPEED_RETURN(200G, 200000); 7802 TEST_SPEED_RETURN(100G, 100000); 7803 TEST_SPEED_RETURN(50G, 50000); 7804 TEST_SPEED_RETURN(40G, 40000); 7805 TEST_SPEED_RETURN(25G, 25000); 7806 TEST_SPEED_RETURN(10G, 10000); 7807 TEST_SPEED_RETURN(1G, 1000); 7808 TEST_SPEED_RETURN(100M, 100); 7809 7810 #undef TEST_SPEED_RETURN 7811 7812 return 0; 7813 } 7814 7815 /* 7816 * Return the port capabilities bit for the highest speed in the capabilities. 7817 */ 7818 uint32_t fwcap_top_speed(uint32_t caps) 7819 { 7820 #define TEST_SPEED_RETURN(__caps_speed) \ 7821 do { \ 7822 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \ 7823 return FW_PORT_CAP32_SPEED_##__caps_speed; \ 7824 } while (0) 7825 7826 TEST_SPEED_RETURN(400G); 7827 TEST_SPEED_RETURN(200G); 7828 TEST_SPEED_RETURN(100G); 7829 TEST_SPEED_RETURN(50G); 7830 TEST_SPEED_RETURN(40G); 7831 TEST_SPEED_RETURN(25G); 7832 TEST_SPEED_RETURN(10G); 7833 TEST_SPEED_RETURN(1G); 7834 TEST_SPEED_RETURN(100M); 7835 7836 #undef TEST_SPEED_RETURN 7837 7838 return 0; 7839 } 7840 7841 7842 /** 7843 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities 7844 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value 7845 * 7846 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new 7847 * 32-bit Port Capabilities value. 7848 */ 7849 static uint32_t lstatus_to_fwcap(u32 lstatus) 7850 { 7851 uint32_t linkattr = 0; 7852 7853 /* 7854 * Unfortunately the format of the Link Status in the old 7855 * 16-bit Port Information message isn't the same as the 7856 * 16-bit Port Capabilities bitfield used everywhere else ... 7857 */ 7858 if (lstatus & F_FW_PORT_CMD_RXPAUSE) 7859 linkattr |= FW_PORT_CAP32_FC_RX; 7860 if (lstatus & F_FW_PORT_CMD_TXPAUSE) 7861 linkattr |= FW_PORT_CAP32_FC_TX; 7862 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M)) 7863 linkattr |= FW_PORT_CAP32_SPEED_100M; 7864 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G)) 7865 linkattr |= FW_PORT_CAP32_SPEED_1G; 7866 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G)) 7867 linkattr |= FW_PORT_CAP32_SPEED_10G; 7868 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_25G)) 7869 linkattr |= FW_PORT_CAP32_SPEED_25G; 7870 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_40G)) 7871 linkattr |= FW_PORT_CAP32_SPEED_40G; 7872 if (lstatus & V_FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100G)) 7873 linkattr |= FW_PORT_CAP32_SPEED_100G; 7874 7875 return linkattr; 7876 } 7877 7878 /* 7879 * Updates all fields owned by the common code in port_info and link_config 7880 * based on information provided by the firmware. Does not touch any 7881 * requested_* field. 7882 */ 7883 static void handle_port_info(struct port_info *pi, const struct fw_port_cmd *p, 7884 enum fw_port_action action, bool *mod_changed, bool *link_changed) 7885 { 7886 struct link_config old_lc, *lc = &pi->link_cfg; 7887 unsigned char fc, fec; 7888 u32 stat, linkattr; 7889 int old_ptype, old_mtype; 7890 7891 old_ptype = pi->port_type; 7892 old_mtype = pi->mod_type; 7893 old_lc = *lc; 7894 if (action == FW_PORT_ACTION_GET_PORT_INFO) { 7895 stat = be32_to_cpu(p->u.info.lstatus_to_modtype); 7896 7897 pi->port_type = G_FW_PORT_CMD_PTYPE(stat); 7898 pi->mod_type = G_FW_PORT_CMD_MODTYPE(stat); 7899 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP ? 7900 G_FW_PORT_CMD_MDIOADDR(stat) : -1; 7901 7902 lc->supported = fwcaps16_to_caps32(be16_to_cpu(p->u.info.pcap)); 7903 lc->advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.acap)); 7904 lc->lp_advertising = fwcaps16_to_caps32(be16_to_cpu(p->u.info.lpacap)); 7905 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS) != 0; 7906 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC(stat); 7907 7908 linkattr = lstatus_to_fwcap(stat); 7909 } else if (action == FW_PORT_ACTION_GET_PORT_INFO32) { 7910 stat = be32_to_cpu(p->u.info32.lstatus32_to_cbllen32); 7911 7912 pi->port_type = G_FW_PORT_CMD_PORTTYPE32(stat); 7913 pi->mod_type = G_FW_PORT_CMD_MODTYPE32(stat); 7914 pi->mdio_addr = stat & F_FW_PORT_CMD_MDIOCAP32 ? 7915 G_FW_PORT_CMD_MDIOADDR32(stat) : -1; 7916 7917 lc->supported = be32_to_cpu(p->u.info32.pcaps32); 7918 lc->advertising = be32_to_cpu(p->u.info32.acaps32); 7919 lc->lp_advertising = be16_to_cpu(p->u.info32.lpacaps32); 7920 lc->link_ok = (stat & F_FW_PORT_CMD_LSTATUS32) != 0; 7921 lc->link_down_rc = G_FW_PORT_CMD_LINKDNRC32(stat); 7922 7923 linkattr = be32_to_cpu(p->u.info32.linkattr32); 7924 } else { 7925 CH_ERR(pi->adapter, "bad port_info action 0x%x\n", action); 7926 return; 7927 } 7928 7929 lc->speed = fwcap_to_speed(linkattr); 7930 7931 fc = 0; 7932 if (linkattr & FW_PORT_CAP32_FC_RX) 7933 fc |= PAUSE_RX; 7934 if (linkattr & FW_PORT_CAP32_FC_TX) 7935 fc |= PAUSE_TX; 7936 lc->fc = fc; 7937 7938 fec = FEC_NONE; 7939 if (linkattr & FW_PORT_CAP32_FEC_RS) 7940 fec |= FEC_RS; 7941 if (linkattr & FW_PORT_CAP32_FEC_BASER_RS) 7942 fec |= FEC_BASER_RS; 7943 lc->fec = fec; 7944 7945 if (mod_changed != NULL) 7946 *mod_changed = false; 7947 if (link_changed != NULL) 7948 *link_changed = false; 7949 if (old_ptype != pi->port_type || old_mtype != pi->mod_type || 7950 old_lc.supported != lc->supported) { 7951 if (pi->mod_type != FW_PORT_MOD_TYPE_NONE) { 7952 lc->fec_hint = lc->advertising & 7953 V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC); 7954 } 7955 if (mod_changed != NULL) 7956 *mod_changed = true; 7957 } 7958 if (old_lc.link_ok != lc->link_ok || old_lc.speed != lc->speed || 7959 old_lc.fec != lc->fec || old_lc.fc != lc->fc) { 7960 if (link_changed != NULL) 7961 *link_changed = true; 7962 } 7963 } 7964 7965 /** 7966 * t4_update_port_info - retrieve and update port information if changed 7967 * @pi: the port_info 7968 * 7969 * We issue a Get Port Information Command to the Firmware and, if 7970 * successful, we check to see if anything is different from what we 7971 * last recorded and update things accordingly. 7972 */ 7973 int t4_update_port_info(struct port_info *pi) 7974 { 7975 struct adapter *sc = pi->adapter; 7976 struct fw_port_cmd cmd; 7977 enum fw_port_action action; 7978 int ret; 7979 7980 memset(&cmd, 0, sizeof(cmd)); 7981 cmd.op_to_portid = cpu_to_be32(V_FW_CMD_OP(FW_PORT_CMD) | 7982 F_FW_CMD_REQUEST | F_FW_CMD_READ | 7983 V_FW_PORT_CMD_PORTID(pi->tx_chan)); 7984 action = sc->params.port_caps32 ? FW_PORT_ACTION_GET_PORT_INFO32 : 7985 FW_PORT_ACTION_GET_PORT_INFO; 7986 cmd.action_to_len16 = cpu_to_be32(V_FW_PORT_CMD_ACTION(action) | 7987 FW_LEN16(cmd)); 7988 ret = t4_wr_mbox_ns(sc, sc->mbox, &cmd, sizeof(cmd), &cmd); 7989 if (ret) 7990 return ret; 7991 7992 handle_port_info(pi, &cmd, action, NULL, NULL); 7993 return 0; 7994 } 7995 7996 /** 7997 * t4_handle_fw_rpl - process a FW reply message 7998 * @adap: the adapter 7999 * @rpl: start of the FW message 8000 * 8001 * Processes a FW message, such as link state change messages. 8002 */ 8003 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) 8004 { 8005 u8 opcode = *(const u8 *)rpl; 8006 const struct fw_port_cmd *p = (const void *)rpl; 8007 enum fw_port_action action = 8008 G_FW_PORT_CMD_ACTION(be32_to_cpu(p->action_to_len16)); 8009 bool mod_changed, link_changed; 8010 8011 if (opcode == FW_PORT_CMD && 8012 (action == FW_PORT_ACTION_GET_PORT_INFO || 8013 action == FW_PORT_ACTION_GET_PORT_INFO32)) { 8014 /* link/module state change message */ 8015 int i; 8016 int chan = G_FW_PORT_CMD_PORTID(be32_to_cpu(p->op_to_portid)); 8017 struct port_info *pi = NULL; 8018 struct link_config *lc; 8019 8020 for_each_port(adap, i) { 8021 pi = adap2pinfo(adap, i); 8022 if (pi->tx_chan == chan) 8023 break; 8024 } 8025 8026 lc = &pi->link_cfg; 8027 PORT_LOCK(pi); 8028 handle_port_info(pi, p, action, &mod_changed, &link_changed); 8029 PORT_UNLOCK(pi); 8030 if (mod_changed) 8031 t4_os_portmod_changed(pi); 8032 if (link_changed) { 8033 PORT_LOCK(pi); 8034 t4_os_link_changed(pi); 8035 PORT_UNLOCK(pi); 8036 } 8037 } else { 8038 CH_WARN_RATELIMIT(adap, "Unknown firmware reply %d\n", opcode); 8039 return -EINVAL; 8040 } 8041 return 0; 8042 } 8043 8044 /** 8045 * get_pci_mode - determine a card's PCI mode 8046 * @adapter: the adapter 8047 * @p: where to store the PCI settings 8048 * 8049 * Determines a card's PCI mode and associated parameters, such as speed 8050 * and width. 8051 */ 8052 static void get_pci_mode(struct adapter *adapter, 8053 struct pci_params *p) 8054 { 8055 u16 val; 8056 u32 pcie_cap; 8057 8058 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8059 if (pcie_cap) { 8060 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_LNKSTA, &val); 8061 p->speed = val & PCI_EXP_LNKSTA_CLS; 8062 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 8063 } 8064 } 8065 8066 struct flash_desc { 8067 u32 vendor_and_model_id; 8068 u32 size_mb; 8069 }; 8070 8071 int t4_get_flash_params(struct adapter *adapter) 8072 { 8073 /* 8074 * Table for non-standard supported Flash parts. Note, all Flash 8075 * parts must have 64KB sectors. 8076 */ 8077 static struct flash_desc supported_flash[] = { 8078 { 0x00150201, 4 << 20 }, /* Spansion 4MB S25FL032P */ 8079 }; 8080 8081 int ret; 8082 u32 flashid = 0; 8083 unsigned int part, manufacturer; 8084 unsigned int density, size = 0; 8085 8086 8087 /* 8088 * Issue a Read ID Command to the Flash part. We decode supported 8089 * Flash parts and their sizes from this. There's a newer Query 8090 * Command which can retrieve detailed geometry information but many 8091 * Flash parts don't support it. 8092 */ 8093 ret = sf1_write(adapter, 1, 1, 0, SF_RD_ID); 8094 if (!ret) 8095 ret = sf1_read(adapter, 3, 0, 1, &flashid); 8096 t4_write_reg(adapter, A_SF_OP, 0); /* unlock SF */ 8097 if (ret < 0) 8098 return ret; 8099 8100 /* 8101 * Check to see if it's one of our non-standard supported Flash parts. 8102 */ 8103 for (part = 0; part < ARRAY_SIZE(supported_flash); part++) 8104 if (supported_flash[part].vendor_and_model_id == flashid) { 8105 adapter->params.sf_size = 8106 supported_flash[part].size_mb; 8107 adapter->params.sf_nsec = 8108 adapter->params.sf_size / SF_SEC_SIZE; 8109 goto found; 8110 } 8111 8112 /* 8113 * Decode Flash part size. The code below looks repetative with 8114 * common encodings, but that's not guaranteed in the JEDEC 8115 * specification for the Read JADEC ID command. The only thing that 8116 * we're guaranteed by the JADEC specification is where the 8117 * Manufacturer ID is in the returned result. After that each 8118 * Manufacturer ~could~ encode things completely differently. 8119 * Note, all Flash parts must have 64KB sectors. 8120 */ 8121 manufacturer = flashid & 0xff; 8122 switch (manufacturer) { 8123 case 0x20: /* Micron/Numonix */ 8124 /* 8125 * This Density -> Size decoding table is taken from Micron 8126 * Data Sheets. 8127 */ 8128 density = (flashid >> 16) & 0xff; 8129 switch (density) { 8130 case 0x14: size = 1 << 20; break; /* 1MB */ 8131 case 0x15: size = 1 << 21; break; /* 2MB */ 8132 case 0x16: size = 1 << 22; break; /* 4MB */ 8133 case 0x17: size = 1 << 23; break; /* 8MB */ 8134 case 0x18: size = 1 << 24; break; /* 16MB */ 8135 case 0x19: size = 1 << 25; break; /* 32MB */ 8136 case 0x20: size = 1 << 26; break; /* 64MB */ 8137 case 0x21: size = 1 << 27; break; /* 128MB */ 8138 case 0x22: size = 1 << 28; break; /* 256MB */ 8139 } 8140 break; 8141 8142 case 0x9d: /* ISSI -- Integrated Silicon Solution, Inc. */ 8143 /* 8144 * This Density -> Size decoding table is taken from ISSI 8145 * Data Sheets. 8146 */ 8147 density = (flashid >> 16) & 0xff; 8148 switch (density) { 8149 case 0x16: size = 1 << 25; break; /* 32MB */ 8150 case 0x17: size = 1 << 26; break; /* 64MB */ 8151 } 8152 break; 8153 8154 case 0xc2: /* Macronix */ 8155 /* 8156 * This Density -> Size decoding table is taken from Macronix 8157 * Data Sheets. 8158 */ 8159 density = (flashid >> 16) & 0xff; 8160 switch (density) { 8161 case 0x17: size = 1 << 23; break; /* 8MB */ 8162 case 0x18: size = 1 << 24; break; /* 16MB */ 8163 } 8164 break; 8165 8166 case 0xef: /* Winbond */ 8167 /* 8168 * This Density -> Size decoding table is taken from Winbond 8169 * Data Sheets. 8170 */ 8171 density = (flashid >> 16) & 0xff; 8172 switch (density) { 8173 case 0x17: size = 1 << 23; break; /* 8MB */ 8174 case 0x18: size = 1 << 24; break; /* 16MB */ 8175 } 8176 break; 8177 } 8178 8179 /* If we didn't recognize the FLASH part, that's no real issue: the 8180 * Hardware/Software contract says that Hardware will _*ALWAYS*_ 8181 * use a FLASH part which is at least 4MB in size and has 64KB 8182 * sectors. The unrecognized FLASH part is likely to be much larger 8183 * than 4MB, but that's all we really need. 8184 */ 8185 if (size == 0) { 8186 CH_WARN(adapter, "Unknown Flash Part, ID = %#x, assuming 4MB\n", flashid); 8187 size = 1 << 22; 8188 } 8189 8190 /* 8191 * Store decoded Flash size and fall through into vetting code. 8192 */ 8193 adapter->params.sf_size = size; 8194 adapter->params.sf_nsec = size / SF_SEC_SIZE; 8195 8196 found: 8197 /* 8198 * We should ~probably~ reject adapters with FLASHes which are too 8199 * small but we have some legacy FPGAs with small FLASHes that we'd 8200 * still like to use. So instead we emit a scary message ... 8201 */ 8202 if (adapter->params.sf_size < FLASH_MIN_SIZE) 8203 CH_WARN(adapter, "WARNING: Flash Part ID %#x, size %#x < %#x\n", 8204 flashid, adapter->params.sf_size, FLASH_MIN_SIZE); 8205 8206 return 0; 8207 } 8208 8209 static void set_pcie_completion_timeout(struct adapter *adapter, 8210 u8 range) 8211 { 8212 u16 val; 8213 u32 pcie_cap; 8214 8215 pcie_cap = t4_os_find_pci_capability(adapter, PCI_CAP_ID_EXP); 8216 if (pcie_cap) { 8217 t4_os_pci_read_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, &val); 8218 val &= 0xfff0; 8219 val |= range ; 8220 t4_os_pci_write_cfg2(adapter, pcie_cap + PCI_EXP_DEVCTL2, val); 8221 } 8222 } 8223 8224 const struct chip_params *t4_get_chip_params(int chipid) 8225 { 8226 static const struct chip_params chip_params[] = { 8227 { 8228 /* T4 */ 8229 .nchan = NCHAN, 8230 .pm_stats_cnt = PM_NSTATS, 8231 .cng_ch_bits_log = 2, 8232 .nsched_cls = 15, 8233 .cim_num_obq = CIM_NUM_OBQ, 8234 .mps_rplc_size = 128, 8235 .vfcount = 128, 8236 .sge_fl_db = F_DBPRIO, 8237 .mps_tcam_size = NUM_MPS_CLS_SRAM_L_INSTANCES, 8238 }, 8239 { 8240 /* T5 */ 8241 .nchan = NCHAN, 8242 .pm_stats_cnt = PM_NSTATS, 8243 .cng_ch_bits_log = 2, 8244 .nsched_cls = 16, 8245 .cim_num_obq = CIM_NUM_OBQ_T5, 8246 .mps_rplc_size = 128, 8247 .vfcount = 128, 8248 .sge_fl_db = F_DBPRIO | F_DBTYPE, 8249 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8250 }, 8251 { 8252 /* T6 */ 8253 .nchan = T6_NCHAN, 8254 .pm_stats_cnt = T6_PM_NSTATS, 8255 .cng_ch_bits_log = 3, 8256 .nsched_cls = 16, 8257 .cim_num_obq = CIM_NUM_OBQ_T5, 8258 .mps_rplc_size = 256, 8259 .vfcount = 256, 8260 .sge_fl_db = 0, 8261 .mps_tcam_size = NUM_MPS_T5_CLS_SRAM_L_INSTANCES, 8262 }, 8263 }; 8264 8265 chipid -= CHELSIO_T4; 8266 if (chipid < 0 || chipid >= ARRAY_SIZE(chip_params)) 8267 return NULL; 8268 8269 return &chip_params[chipid]; 8270 } 8271 8272 /** 8273 * t4_prep_adapter - prepare SW and HW for operation 8274 * @adapter: the adapter 8275 * @buf: temporary space of at least VPD_LEN size provided by the caller. 8276 * 8277 * Initialize adapter SW state for the various HW modules, set initial 8278 * values for some adapter tunables, take PHYs out of reset, and 8279 * initialize the MDIO interface. 8280 */ 8281 int t4_prep_adapter(struct adapter *adapter, u32 *buf) 8282 { 8283 int ret; 8284 uint16_t device_id; 8285 uint32_t pl_rev; 8286 8287 get_pci_mode(adapter, &adapter->params.pci); 8288 8289 pl_rev = t4_read_reg(adapter, A_PL_REV); 8290 adapter->params.chipid = G_CHIPID(pl_rev); 8291 adapter->params.rev = G_REV(pl_rev); 8292 if (adapter->params.chipid == 0) { 8293 /* T4 did not have chipid in PL_REV (T5 onwards do) */ 8294 adapter->params.chipid = CHELSIO_T4; 8295 8296 /* T4A1 chip is not supported */ 8297 if (adapter->params.rev == 1) { 8298 CH_ALERT(adapter, "T4 rev 1 chip is not supported.\n"); 8299 return -EINVAL; 8300 } 8301 } 8302 8303 adapter->chip_params = t4_get_chip_params(chip_id(adapter)); 8304 if (adapter->chip_params == NULL) 8305 return -EINVAL; 8306 8307 adapter->params.pci.vpd_cap_addr = 8308 t4_os_find_pci_capability(adapter, PCI_CAP_ID_VPD); 8309 8310 ret = t4_get_flash_params(adapter); 8311 if (ret < 0) 8312 return ret; 8313 8314 /* Cards with real ASICs have the chipid in the PCIe device id */ 8315 t4_os_pci_read_cfg2(adapter, PCI_DEVICE_ID, &device_id); 8316 if (device_id >> 12 == chip_id(adapter)) 8317 adapter->params.cim_la_size = CIMLA_SIZE; 8318 else { 8319 /* FPGA */ 8320 adapter->params.fpga = 1; 8321 adapter->params.cim_la_size = 2 * CIMLA_SIZE; 8322 } 8323 8324 ret = get_vpd_params(adapter, &adapter->params.vpd, device_id, buf); 8325 if (ret < 0) 8326 return ret; 8327 8328 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 8329 8330 /* 8331 * Default port and clock for debugging in case we can't reach FW. 8332 */ 8333 adapter->params.nports = 1; 8334 adapter->params.portvec = 1; 8335 adapter->params.vpd.cclk = 50000; 8336 8337 /* Set pci completion timeout value to 4 seconds. */ 8338 set_pcie_completion_timeout(adapter, 0xd); 8339 return 0; 8340 } 8341 8342 /** 8343 * t4_shutdown_adapter - shut down adapter, host & wire 8344 * @adapter: the adapter 8345 * 8346 * Perform an emergency shutdown of the adapter and stop it from 8347 * continuing any further communication on the ports or DMA to the 8348 * host. This is typically used when the adapter and/or firmware 8349 * have crashed and we want to prevent any further accidental 8350 * communication with the rest of the world. This will also force 8351 * the port Link Status to go down -- if register writes work -- 8352 * which should help our peers figure out that we're down. 8353 */ 8354 int t4_shutdown_adapter(struct adapter *adapter) 8355 { 8356 int port; 8357 8358 t4_intr_disable(adapter); 8359 t4_write_reg(adapter, A_DBG_GPIO_EN, 0); 8360 for_each_port(adapter, port) { 8361 u32 a_port_cfg = is_t4(adapter) ? 8362 PORT_REG(port, A_XGMAC_PORT_CFG) : 8363 T5_PORT_REG(port, A_MAC_PORT_CFG); 8364 8365 t4_write_reg(adapter, a_port_cfg, 8366 t4_read_reg(adapter, a_port_cfg) 8367 & ~V_SIGNAL_DET(1)); 8368 } 8369 t4_set_reg_field(adapter, A_SGE_CONTROL, F_GLOBALENABLE, 0); 8370 8371 return 0; 8372 } 8373 8374 /** 8375 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information 8376 * @adapter: the adapter 8377 * @qid: the Queue ID 8378 * @qtype: the Ingress or Egress type for @qid 8379 * @user: true if this request is for a user mode queue 8380 * @pbar2_qoffset: BAR2 Queue Offset 8381 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues 8382 * 8383 * Returns the BAR2 SGE Queue Registers information associated with the 8384 * indicated Absolute Queue ID. These are passed back in return value 8385 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue 8386 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues. 8387 * 8388 * This may return an error which indicates that BAR2 SGE Queue 8389 * registers aren't available. If an error is not returned, then the 8390 * following values are returned: 8391 * 8392 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers 8393 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid 8394 * 8395 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which 8396 * require the "Inferred Queue ID" ability may be used. E.g. the 8397 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0, 8398 * then these "Inferred Queue ID" register may not be used. 8399 */ 8400 int t4_bar2_sge_qregs(struct adapter *adapter, 8401 unsigned int qid, 8402 enum t4_bar2_qtype qtype, 8403 int user, 8404 u64 *pbar2_qoffset, 8405 unsigned int *pbar2_qid) 8406 { 8407 unsigned int page_shift, page_size, qpp_shift, qpp_mask; 8408 u64 bar2_page_offset, bar2_qoffset; 8409 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred; 8410 8411 /* T4 doesn't support BAR2 SGE Queue registers for kernel 8412 * mode queues. 8413 */ 8414 if (!user && is_t4(adapter)) 8415 return -EINVAL; 8416 8417 /* Get our SGE Page Size parameters. 8418 */ 8419 page_shift = adapter->params.sge.page_shift; 8420 page_size = 1 << page_shift; 8421 8422 /* Get the right Queues per Page parameters for our Queue. 8423 */ 8424 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS 8425 ? adapter->params.sge.eq_s_qpp 8426 : adapter->params.sge.iq_s_qpp); 8427 qpp_mask = (1 << qpp_shift) - 1; 8428 8429 /* Calculate the basics of the BAR2 SGE Queue register area: 8430 * o The BAR2 page the Queue registers will be in. 8431 * o The BAR2 Queue ID. 8432 * o The BAR2 Queue ID Offset into the BAR2 page. 8433 */ 8434 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift); 8435 bar2_qid = qid & qpp_mask; 8436 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE; 8437 8438 /* If the BAR2 Queue ID Offset is less than the Page Size, then the 8439 * hardware will infer the Absolute Queue ID simply from the writes to 8440 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a 8441 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply 8442 * write to the first BAR2 SGE Queue Area within the BAR2 Page with 8443 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID 8444 * from the BAR2 Page and BAR2 Queue ID. 8445 * 8446 * One important censequence of this is that some BAR2 SGE registers 8447 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID 8448 * there. But other registers synthesize the SGE Queue ID purely 8449 * from the writes to the registers -- the Write Combined Doorbell 8450 * Buffer is a good example. These BAR2 SGE Registers are only 8451 * available for those BAR2 SGE Register areas where the SGE Absolute 8452 * Queue ID can be inferred from simple writes. 8453 */ 8454 bar2_qoffset = bar2_page_offset; 8455 bar2_qinferred = (bar2_qid_offset < page_size); 8456 if (bar2_qinferred) { 8457 bar2_qoffset += bar2_qid_offset; 8458 bar2_qid = 0; 8459 } 8460 8461 *pbar2_qoffset = bar2_qoffset; 8462 *pbar2_qid = bar2_qid; 8463 return 0; 8464 } 8465 8466 /** 8467 * t4_init_devlog_params - initialize adapter->params.devlog 8468 * @adap: the adapter 8469 * @fw_attach: whether we can talk to the firmware 8470 * 8471 * Initialize various fields of the adapter's Firmware Device Log 8472 * Parameters structure. 8473 */ 8474 int t4_init_devlog_params(struct adapter *adap, int fw_attach) 8475 { 8476 struct devlog_params *dparams = &adap->params.devlog; 8477 u32 pf_dparams; 8478 unsigned int devlog_meminfo; 8479 struct fw_devlog_cmd devlog_cmd; 8480 int ret; 8481 8482 /* If we're dealing with newer firmware, the Device Log Paramerters 8483 * are stored in a designated register which allows us to access the 8484 * Device Log even if we can't talk to the firmware. 8485 */ 8486 pf_dparams = 8487 t4_read_reg(adap, PCIE_FW_REG(A_PCIE_FW_PF, PCIE_FW_PF_DEVLOG)); 8488 if (pf_dparams) { 8489 unsigned int nentries, nentries128; 8490 8491 dparams->memtype = G_PCIE_FW_PF_DEVLOG_MEMTYPE(pf_dparams); 8492 dparams->start = G_PCIE_FW_PF_DEVLOG_ADDR16(pf_dparams) << 4; 8493 8494 nentries128 = G_PCIE_FW_PF_DEVLOG_NENTRIES128(pf_dparams); 8495 nentries = (nentries128 + 1) * 128; 8496 dparams->size = nentries * sizeof(struct fw_devlog_e); 8497 8498 return 0; 8499 } 8500 8501 /* 8502 * For any failing returns ... 8503 */ 8504 memset(dparams, 0, sizeof *dparams); 8505 8506 /* 8507 * If we can't talk to the firmware, there's really nothing we can do 8508 * at this point. 8509 */ 8510 if (!fw_attach) 8511 return -ENXIO; 8512 8513 /* Otherwise, ask the firmware for it's Device Log Parameters. 8514 */ 8515 memset(&devlog_cmd, 0, sizeof devlog_cmd); 8516 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 8517 F_FW_CMD_REQUEST | F_FW_CMD_READ); 8518 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 8519 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), 8520 &devlog_cmd); 8521 if (ret) 8522 return ret; 8523 8524 devlog_meminfo = 8525 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog); 8526 dparams->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(devlog_meminfo); 8527 dparams->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(devlog_meminfo) << 4; 8528 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog); 8529 8530 return 0; 8531 } 8532 8533 /** 8534 * t4_init_sge_params - initialize adap->params.sge 8535 * @adapter: the adapter 8536 * 8537 * Initialize various fields of the adapter's SGE Parameters structure. 8538 */ 8539 int t4_init_sge_params(struct adapter *adapter) 8540 { 8541 u32 r; 8542 struct sge_params *sp = &adapter->params.sge; 8543 unsigned i, tscale = 1; 8544 8545 r = t4_read_reg(adapter, A_SGE_INGRESS_RX_THRESHOLD); 8546 sp->counter_val[0] = G_THRESHOLD_0(r); 8547 sp->counter_val[1] = G_THRESHOLD_1(r); 8548 sp->counter_val[2] = G_THRESHOLD_2(r); 8549 sp->counter_val[3] = G_THRESHOLD_3(r); 8550 8551 if (chip_id(adapter) >= CHELSIO_T6) { 8552 r = t4_read_reg(adapter, A_SGE_ITP_CONTROL); 8553 tscale = G_TSCALE(r); 8554 if (tscale == 0) 8555 tscale = 1; 8556 else 8557 tscale += 2; 8558 } 8559 8560 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_0_AND_1); 8561 sp->timer_val[0] = core_ticks_to_us(adapter, G_TIMERVALUE0(r)) * tscale; 8562 sp->timer_val[1] = core_ticks_to_us(adapter, G_TIMERVALUE1(r)) * tscale; 8563 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_2_AND_3); 8564 sp->timer_val[2] = core_ticks_to_us(adapter, G_TIMERVALUE2(r)) * tscale; 8565 sp->timer_val[3] = core_ticks_to_us(adapter, G_TIMERVALUE3(r)) * tscale; 8566 r = t4_read_reg(adapter, A_SGE_TIMER_VALUE_4_AND_5); 8567 sp->timer_val[4] = core_ticks_to_us(adapter, G_TIMERVALUE4(r)) * tscale; 8568 sp->timer_val[5] = core_ticks_to_us(adapter, G_TIMERVALUE5(r)) * tscale; 8569 8570 r = t4_read_reg(adapter, A_SGE_CONM_CTRL); 8571 sp->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1; 8572 if (is_t4(adapter)) 8573 sp->fl_starve_threshold2 = sp->fl_starve_threshold; 8574 else if (is_t5(adapter)) 8575 sp->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1; 8576 else 8577 sp->fl_starve_threshold2 = G_T6_EGRTHRESHOLDPACKING(r) * 2 + 1; 8578 8579 /* egress queues: log2 of # of doorbells per BAR2 page */ 8580 r = t4_read_reg(adapter, A_SGE_EGRESS_QUEUES_PER_PAGE_PF); 8581 r >>= S_QUEUESPERPAGEPF0 + 8582 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8583 sp->eq_s_qpp = r & M_QUEUESPERPAGEPF0; 8584 8585 /* ingress queues: log2 of # of doorbells per BAR2 page */ 8586 r = t4_read_reg(adapter, A_SGE_INGRESS_QUEUES_PER_PAGE_PF); 8587 r >>= S_QUEUESPERPAGEPF0 + 8588 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * adapter->pf; 8589 sp->iq_s_qpp = r & M_QUEUESPERPAGEPF0; 8590 8591 r = t4_read_reg(adapter, A_SGE_HOST_PAGE_SIZE); 8592 r >>= S_HOSTPAGESIZEPF0 + 8593 (S_HOSTPAGESIZEPF1 - S_HOSTPAGESIZEPF0) * adapter->pf; 8594 sp->page_shift = (r & M_HOSTPAGESIZEPF0) + 10; 8595 8596 r = t4_read_reg(adapter, A_SGE_CONTROL); 8597 sp->sge_control = r; 8598 sp->spg_len = r & F_EGRSTATUSPAGESIZE ? 128 : 64; 8599 sp->fl_pktshift = G_PKTSHIFT(r); 8600 if (chip_id(adapter) <= CHELSIO_T5) { 8601 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8602 X_INGPADBOUNDARY_SHIFT); 8603 } else { 8604 sp->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 8605 X_T6_INGPADBOUNDARY_SHIFT); 8606 } 8607 if (is_t4(adapter)) 8608 sp->pack_boundary = sp->pad_boundary; 8609 else { 8610 r = t4_read_reg(adapter, A_SGE_CONTROL2); 8611 if (G_INGPACKBOUNDARY(r) == 0) 8612 sp->pack_boundary = 16; 8613 else 8614 sp->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5); 8615 } 8616 for (i = 0; i < SGE_FLBUF_SIZES; i++) 8617 sp->sge_fl_buffer_size[i] = t4_read_reg(adapter, 8618 A_SGE_FL_BUFFER_SIZE0 + (4 * i)); 8619 8620 return 0; 8621 } 8622 8623 /* 8624 * Read and cache the adapter's compressed filter mode and ingress config. 8625 */ 8626 static void read_filter_mode_and_ingress_config(struct adapter *adap, 8627 bool sleep_ok) 8628 { 8629 uint32_t v; 8630 struct tp_params *tpp = &adap->params.tp; 8631 8632 t4_tp_pio_read(adap, &tpp->vlan_pri_map, 1, A_TP_VLAN_PRI_MAP, 8633 sleep_ok); 8634 t4_tp_pio_read(adap, &tpp->ingress_config, 1, A_TP_INGRESS_CONFIG, 8635 sleep_ok); 8636 8637 /* 8638 * Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 8639 * shift positions of several elements of the Compressed Filter Tuple 8640 * for this adapter which we need frequently ... 8641 */ 8642 tpp->fcoe_shift = t4_filter_field_shift(adap, F_FCOE); 8643 tpp->port_shift = t4_filter_field_shift(adap, F_PORT); 8644 tpp->vnic_shift = t4_filter_field_shift(adap, F_VNIC_ID); 8645 tpp->vlan_shift = t4_filter_field_shift(adap, F_VLAN); 8646 tpp->tos_shift = t4_filter_field_shift(adap, F_TOS); 8647 tpp->protocol_shift = t4_filter_field_shift(adap, F_PROTOCOL); 8648 tpp->ethertype_shift = t4_filter_field_shift(adap, F_ETHERTYPE); 8649 tpp->macmatch_shift = t4_filter_field_shift(adap, F_MACMATCH); 8650 tpp->matchtype_shift = t4_filter_field_shift(adap, F_MPSHITTYPE); 8651 tpp->frag_shift = t4_filter_field_shift(adap, F_FRAGMENTATION); 8652 8653 if (chip_id(adap) > CHELSIO_T4) { 8654 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(3)); 8655 adap->params.tp.hash_filter_mask = v; 8656 v = t4_read_reg(adap, LE_HASH_MASK_GEN_IPV4T5(4)); 8657 adap->params.tp.hash_filter_mask |= (u64)v << 32; 8658 } 8659 } 8660 8661 /** 8662 * t4_init_tp_params - initialize adap->params.tp 8663 * @adap: the adapter 8664 * 8665 * Initialize various fields of the adapter's TP Parameters structure. 8666 */ 8667 int t4_init_tp_params(struct adapter *adap, bool sleep_ok) 8668 { 8669 int chan; 8670 u32 v; 8671 struct tp_params *tpp = &adap->params.tp; 8672 8673 v = t4_read_reg(adap, A_TP_TIMER_RESOLUTION); 8674 tpp->tre = G_TIMERRESOLUTION(v); 8675 tpp->dack_re = G_DELAYEDACKRESOLUTION(v); 8676 8677 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 8678 for (chan = 0; chan < MAX_NCHAN; chan++) 8679 tpp->tx_modq[chan] = chan; 8680 8681 read_filter_mode_and_ingress_config(adap, sleep_ok); 8682 8683 /* 8684 * Cache a mask of the bits that represent the error vector portion of 8685 * rx_pkt.err_vec. T6+ can use a compressed error vector to make room 8686 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE). 8687 */ 8688 tpp->err_vec_mask = htobe16(0xffff); 8689 if (chip_id(adap) > CHELSIO_T5) { 8690 v = t4_read_reg(adap, A_TP_OUT_CONFIG); 8691 if (v & F_CRXPKTENC) { 8692 tpp->err_vec_mask = 8693 htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC)); 8694 } 8695 } 8696 8697 return 0; 8698 } 8699 8700 /** 8701 * t4_filter_field_shift - calculate filter field shift 8702 * @adap: the adapter 8703 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits) 8704 * 8705 * Return the shift position of a filter field within the Compressed 8706 * Filter Tuple. The filter field is specified via its selection bit 8707 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN. 8708 */ 8709 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) 8710 { 8711 unsigned int filter_mode = adap->params.tp.vlan_pri_map; 8712 unsigned int sel; 8713 int field_shift; 8714 8715 if ((filter_mode & filter_sel) == 0) 8716 return -1; 8717 8718 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) { 8719 switch (filter_mode & sel) { 8720 case F_FCOE: 8721 field_shift += W_FT_FCOE; 8722 break; 8723 case F_PORT: 8724 field_shift += W_FT_PORT; 8725 break; 8726 case F_VNIC_ID: 8727 field_shift += W_FT_VNIC_ID; 8728 break; 8729 case F_VLAN: 8730 field_shift += W_FT_VLAN; 8731 break; 8732 case F_TOS: 8733 field_shift += W_FT_TOS; 8734 break; 8735 case F_PROTOCOL: 8736 field_shift += W_FT_PROTOCOL; 8737 break; 8738 case F_ETHERTYPE: 8739 field_shift += W_FT_ETHERTYPE; 8740 break; 8741 case F_MACMATCH: 8742 field_shift += W_FT_MACMATCH; 8743 break; 8744 case F_MPSHITTYPE: 8745 field_shift += W_FT_MPSHITTYPE; 8746 break; 8747 case F_FRAGMENTATION: 8748 field_shift += W_FT_FRAGMENTATION; 8749 break; 8750 } 8751 } 8752 return field_shift; 8753 } 8754 8755 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id) 8756 { 8757 u8 addr[6]; 8758 int ret, i, j; 8759 u16 rss_size; 8760 struct port_info *p = adap2pinfo(adap, port_id); 8761 u32 param, val; 8762 8763 for (i = 0, j = -1; i <= p->port_id; i++) { 8764 do { 8765 j++; 8766 } while ((adap->params.portvec & (1 << j)) == 0); 8767 } 8768 8769 p->tx_chan = j; 8770 p->mps_bg_map = t4_get_mps_bg_map(adap, j); 8771 p->rx_e_chan_map = t4_get_rx_e_chan_map(adap, j); 8772 p->lport = j; 8773 8774 if (!(adap->flags & IS_VF) || 8775 adap->params.vfres.r_caps & FW_CMD_CAP_PORT) { 8776 t4_update_port_info(p); 8777 } 8778 8779 ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size); 8780 if (ret < 0) 8781 return ret; 8782 8783 p->vi[0].viid = ret; 8784 if (chip_id(adap) <= CHELSIO_T5) 8785 p->vi[0].smt_idx = (ret & 0x7f) << 1; 8786 else 8787 p->vi[0].smt_idx = (ret & 0x7f); 8788 p->vi[0].rss_size = rss_size; 8789 t4_os_set_hw_addr(p, addr); 8790 8791 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 8792 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) | 8793 V_FW_PARAMS_PARAM_YZ(p->vi[0].viid); 8794 ret = t4_query_params(adap, mbox, pf, vf, 1, ¶m, &val); 8795 if (ret) 8796 p->vi[0].rss_base = 0xffff; 8797 else { 8798 /* MPASS((val >> 16) == rss_size); */ 8799 p->vi[0].rss_base = val & 0xffff; 8800 } 8801 8802 return 0; 8803 } 8804 8805 /** 8806 * t4_read_cimq_cfg - read CIM queue configuration 8807 * @adap: the adapter 8808 * @base: holds the queue base addresses in bytes 8809 * @size: holds the queue sizes in bytes 8810 * @thres: holds the queue full thresholds in bytes 8811 * 8812 * Returns the current configuration of the CIM queues, starting with 8813 * the IBQs, then the OBQs. 8814 */ 8815 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) 8816 { 8817 unsigned int i, v; 8818 int cim_num_obq = adap->chip_params->cim_num_obq; 8819 8820 for (i = 0; i < CIM_NUM_IBQ; i++) { 8821 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_IBQSELECT | 8822 V_QUENUMSELECT(i)); 8823 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8824 /* value is in 256-byte units */ 8825 *base++ = G_CIMQBASE(v) * 256; 8826 *size++ = G_CIMQSIZE(v) * 256; 8827 *thres++ = G_QUEFULLTHRSH(v) * 8; /* 8-byte unit */ 8828 } 8829 for (i = 0; i < cim_num_obq; i++) { 8830 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8831 V_QUENUMSELECT(i)); 8832 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8833 /* value is in 256-byte units */ 8834 *base++ = G_CIMQBASE(v) * 256; 8835 *size++ = G_CIMQSIZE(v) * 256; 8836 } 8837 } 8838 8839 /** 8840 * t4_read_cim_ibq - read the contents of a CIM inbound queue 8841 * @adap: the adapter 8842 * @qid: the queue index 8843 * @data: where to store the queue contents 8844 * @n: capacity of @data in 32-bit words 8845 * 8846 * Reads the contents of the selected CIM queue starting at address 0 up 8847 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8848 * error and the number of 32-bit words actually read on success. 8849 */ 8850 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8851 { 8852 int i, err, attempts; 8853 unsigned int addr; 8854 const unsigned int nwords = CIM_IBQ_SIZE * 4; 8855 8856 if (qid > 5 || (n & 3)) 8857 return -EINVAL; 8858 8859 addr = qid * nwords; 8860 if (n > nwords) 8861 n = nwords; 8862 8863 /* It might take 3-10ms before the IBQ debug read access is allowed. 8864 * Wait for 1 Sec with a delay of 1 usec. 8865 */ 8866 attempts = 1000000; 8867 8868 for (i = 0; i < n; i++, addr++) { 8869 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, V_IBQDBGADDR(addr) | 8870 F_IBQDBGEN); 8871 err = t4_wait_op_done(adap, A_CIM_IBQ_DBG_CFG, F_IBQDBGBUSY, 0, 8872 attempts, 1); 8873 if (err) 8874 return err; 8875 *data++ = t4_read_reg(adap, A_CIM_IBQ_DBG_DATA); 8876 } 8877 t4_write_reg(adap, A_CIM_IBQ_DBG_CFG, 0); 8878 return i; 8879 } 8880 8881 /** 8882 * t4_read_cim_obq - read the contents of a CIM outbound queue 8883 * @adap: the adapter 8884 * @qid: the queue index 8885 * @data: where to store the queue contents 8886 * @n: capacity of @data in 32-bit words 8887 * 8888 * Reads the contents of the selected CIM queue starting at address 0 up 8889 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on 8890 * error and the number of 32-bit words actually read on success. 8891 */ 8892 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) 8893 { 8894 int i, err; 8895 unsigned int addr, v, nwords; 8896 int cim_num_obq = adap->chip_params->cim_num_obq; 8897 8898 if ((qid > (cim_num_obq - 1)) || (n & 3)) 8899 return -EINVAL; 8900 8901 t4_write_reg(adap, A_CIM_QUEUE_CONFIG_REF, F_OBQSELECT | 8902 V_QUENUMSELECT(qid)); 8903 v = t4_read_reg(adap, A_CIM_QUEUE_CONFIG_CTRL); 8904 8905 addr = G_CIMQBASE(v) * 64; /* muliple of 256 -> muliple of 4 */ 8906 nwords = G_CIMQSIZE(v) * 64; /* same */ 8907 if (n > nwords) 8908 n = nwords; 8909 8910 for (i = 0; i < n; i++, addr++) { 8911 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, V_OBQDBGADDR(addr) | 8912 F_OBQDBGEN); 8913 err = t4_wait_op_done(adap, A_CIM_OBQ_DBG_CFG, F_OBQDBGBUSY, 0, 8914 2, 1); 8915 if (err) 8916 return err; 8917 *data++ = t4_read_reg(adap, A_CIM_OBQ_DBG_DATA); 8918 } 8919 t4_write_reg(adap, A_CIM_OBQ_DBG_CFG, 0); 8920 return i; 8921 } 8922 8923 enum { 8924 CIM_QCTL_BASE = 0, 8925 CIM_CTL_BASE = 0x2000, 8926 CIM_PBT_ADDR_BASE = 0x2800, 8927 CIM_PBT_LRF_BASE = 0x3000, 8928 CIM_PBT_DATA_BASE = 0x3800 8929 }; 8930 8931 /** 8932 * t4_cim_read - read a block from CIM internal address space 8933 * @adap: the adapter 8934 * @addr: the start address within the CIM address space 8935 * @n: number of words to read 8936 * @valp: where to store the result 8937 * 8938 * Reads a block of 4-byte words from the CIM intenal address space. 8939 */ 8940 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 8941 unsigned int *valp) 8942 { 8943 int ret = 0; 8944 8945 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8946 return -EBUSY; 8947 8948 for ( ; !ret && n--; addr += 4) { 8949 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr); 8950 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8951 0, 5, 2); 8952 if (!ret) 8953 *valp++ = t4_read_reg(adap, A_CIM_HOST_ACC_DATA); 8954 } 8955 return ret; 8956 } 8957 8958 /** 8959 * t4_cim_write - write a block into CIM internal address space 8960 * @adap: the adapter 8961 * @addr: the start address within the CIM address space 8962 * @n: number of words to write 8963 * @valp: set of values to write 8964 * 8965 * Writes a block of 4-byte words into the CIM intenal address space. 8966 */ 8967 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 8968 const unsigned int *valp) 8969 { 8970 int ret = 0; 8971 8972 if (t4_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY) 8973 return -EBUSY; 8974 8975 for ( ; !ret && n--; addr += 4) { 8976 t4_write_reg(adap, A_CIM_HOST_ACC_DATA, *valp++); 8977 t4_write_reg(adap, A_CIM_HOST_ACC_CTRL, addr | F_HOSTWRITE); 8978 ret = t4_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY, 8979 0, 5, 2); 8980 } 8981 return ret; 8982 } 8983 8984 static int t4_cim_write1(struct adapter *adap, unsigned int addr, 8985 unsigned int val) 8986 { 8987 return t4_cim_write(adap, addr, 1, &val); 8988 } 8989 8990 /** 8991 * t4_cim_ctl_read - read a block from CIM control region 8992 * @adap: the adapter 8993 * @addr: the start address within the CIM control region 8994 * @n: number of words to read 8995 * @valp: where to store the result 8996 * 8997 * Reads a block of 4-byte words from the CIM control region. 8998 */ 8999 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 9000 unsigned int *valp) 9001 { 9002 return t4_cim_read(adap, addr + CIM_CTL_BASE, n, valp); 9003 } 9004 9005 /** 9006 * t4_cim_read_la - read CIM LA capture buffer 9007 * @adap: the adapter 9008 * @la_buf: where to store the LA data 9009 * @wrptr: the HW write pointer within the capture buffer 9010 * 9011 * Reads the contents of the CIM LA buffer with the most recent entry at 9012 * the end of the returned data and with the entry at @wrptr first. 9013 * We try to leave the LA in the running state we find it in. 9014 */ 9015 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) 9016 { 9017 int i, ret; 9018 unsigned int cfg, val, idx; 9019 9020 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &cfg); 9021 if (ret) 9022 return ret; 9023 9024 if (cfg & F_UPDBGLAEN) { /* LA is running, freeze it */ 9025 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 0); 9026 if (ret) 9027 return ret; 9028 } 9029 9030 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9031 if (ret) 9032 goto restart; 9033 9034 idx = G_UPDBGLAWRPTR(val); 9035 if (wrptr) 9036 *wrptr = idx; 9037 9038 for (i = 0; i < adap->params.cim_la_size; i++) { 9039 ret = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9040 V_UPDBGLARDPTR(idx) | F_UPDBGLARDEN); 9041 if (ret) 9042 break; 9043 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_CFG, 1, &val); 9044 if (ret) 9045 break; 9046 if (val & F_UPDBGLARDEN) { 9047 ret = -ETIMEDOUT; 9048 break; 9049 } 9050 ret = t4_cim_read(adap, A_UP_UP_DBG_LA_DATA, 1, &la_buf[i]); 9051 if (ret) 9052 break; 9053 9054 /* address can't exceed 0xfff (UpDbgLaRdPtr is of 12-bits) */ 9055 idx = (idx + 1) & M_UPDBGLARDPTR; 9056 /* 9057 * Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to 9058 * identify the 32-bit portion of the full 312-bit data 9059 */ 9060 if (is_t6(adap)) 9061 while ((idx & 0xf) > 9) 9062 idx = (idx + 1) % M_UPDBGLARDPTR; 9063 } 9064 restart: 9065 if (cfg & F_UPDBGLAEN) { 9066 int r = t4_cim_write1(adap, A_UP_UP_DBG_LA_CFG, 9067 cfg & ~F_UPDBGLARDEN); 9068 if (!ret) 9069 ret = r; 9070 } 9071 return ret; 9072 } 9073 9074 /** 9075 * t4_tp_read_la - read TP LA capture buffer 9076 * @adap: the adapter 9077 * @la_buf: where to store the LA data 9078 * @wrptr: the HW write pointer within the capture buffer 9079 * 9080 * Reads the contents of the TP LA buffer with the most recent entry at 9081 * the end of the returned data and with the entry at @wrptr first. 9082 * We leave the LA in the running state we find it in. 9083 */ 9084 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) 9085 { 9086 bool last_incomplete; 9087 unsigned int i, cfg, val, idx; 9088 9089 cfg = t4_read_reg(adap, A_TP_DBG_LA_CONFIG) & 0xffff; 9090 if (cfg & F_DBGLAENABLE) /* freeze LA */ 9091 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9092 adap->params.tp.la_mask | (cfg ^ F_DBGLAENABLE)); 9093 9094 val = t4_read_reg(adap, A_TP_DBG_LA_CONFIG); 9095 idx = G_DBGLAWPTR(val); 9096 last_incomplete = G_DBGLAMODE(val) >= 2 && (val & F_DBGLAWHLF) == 0; 9097 if (last_incomplete) 9098 idx = (idx + 1) & M_DBGLARPTR; 9099 if (wrptr) 9100 *wrptr = idx; 9101 9102 val &= 0xffff; 9103 val &= ~V_DBGLARPTR(M_DBGLARPTR); 9104 val |= adap->params.tp.la_mask; 9105 9106 for (i = 0; i < TPLA_SIZE; i++) { 9107 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, V_DBGLARPTR(idx) | val); 9108 la_buf[i] = t4_read_reg64(adap, A_TP_DBG_LA_DATAL); 9109 idx = (idx + 1) & M_DBGLARPTR; 9110 } 9111 9112 /* Wipe out last entry if it isn't valid */ 9113 if (last_incomplete) 9114 la_buf[TPLA_SIZE - 1] = ~0ULL; 9115 9116 if (cfg & F_DBGLAENABLE) /* restore running state */ 9117 t4_write_reg(adap, A_TP_DBG_LA_CONFIG, 9118 cfg | adap->params.tp.la_mask); 9119 } 9120 9121 /* 9122 * SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in 9123 * seconds). If we find one of the SGE Ingress DMA State Machines in the same 9124 * state for more than the Warning Threshold then we'll issue a warning about 9125 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel 9126 * appears to be hung every Warning Repeat second till the situation clears. 9127 * If the situation clears, we'll note that as well. 9128 */ 9129 #define SGE_IDMA_WARN_THRESH 1 9130 #define SGE_IDMA_WARN_REPEAT 300 9131 9132 /** 9133 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor 9134 * @adapter: the adapter 9135 * @idma: the adapter IDMA Monitor state 9136 * 9137 * Initialize the state of an SGE Ingress DMA Monitor. 9138 */ 9139 void t4_idma_monitor_init(struct adapter *adapter, 9140 struct sge_idma_monitor_state *idma) 9141 { 9142 /* Initialize the state variables for detecting an SGE Ingress DMA 9143 * hang. The SGE has internal counters which count up on each clock 9144 * tick whenever the SGE finds its Ingress DMA State Engines in the 9145 * same state they were on the previous clock tick. The clock used is 9146 * the Core Clock so we have a limit on the maximum "time" they can 9147 * record; typically a very small number of seconds. For instance, 9148 * with a 600MHz Core Clock, we can only count up to a bit more than 9149 * 7s. So we'll synthesize a larger counter in order to not run the 9150 * risk of having the "timers" overflow and give us the flexibility to 9151 * maintain a Hung SGE State Machine of our own which operates across 9152 * a longer time frame. 9153 */ 9154 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */ 9155 idma->idma_stalled[0] = idma->idma_stalled[1] = 0; 9156 } 9157 9158 /** 9159 * t4_idma_monitor - monitor SGE Ingress DMA state 9160 * @adapter: the adapter 9161 * @idma: the adapter IDMA Monitor state 9162 * @hz: number of ticks/second 9163 * @ticks: number of ticks since the last IDMA Monitor call 9164 */ 9165 void t4_idma_monitor(struct adapter *adapter, 9166 struct sge_idma_monitor_state *idma, 9167 int hz, int ticks) 9168 { 9169 int i, idma_same_state_cnt[2]; 9170 9171 /* Read the SGE Debug Ingress DMA Same State Count registers. These 9172 * are counters inside the SGE which count up on each clock when the 9173 * SGE finds its Ingress DMA State Engines in the same states they 9174 * were in the previous clock. The counters will peg out at 9175 * 0xffffffff without wrapping around so once they pass the 1s 9176 * threshold they'll stay above that till the IDMA state changes. 9177 */ 9178 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 13); 9179 idma_same_state_cnt[0] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_HIGH); 9180 idma_same_state_cnt[1] = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9181 9182 for (i = 0; i < 2; i++) { 9183 u32 debug0, debug11; 9184 9185 /* If the Ingress DMA Same State Counter ("timer") is less 9186 * than 1s, then we can reset our synthesized Stall Timer and 9187 * continue. If we have previously emitted warnings about a 9188 * potential stalled Ingress Queue, issue a note indicating 9189 * that the Ingress Queue has resumed forward progress. 9190 */ 9191 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) { 9192 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH*hz) 9193 CH_WARN(adapter, "SGE idma%d, queue %u, " 9194 "resumed after %d seconds\n", 9195 i, idma->idma_qid[i], 9196 idma->idma_stalled[i]/hz); 9197 idma->idma_stalled[i] = 0; 9198 continue; 9199 } 9200 9201 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz 9202 * domain. The first time we get here it'll be because we 9203 * passed the 1s Threshold; each additional time it'll be 9204 * because the RX Timer Callback is being fired on its regular 9205 * schedule. 9206 * 9207 * If the stall is below our Potential Hung Ingress Queue 9208 * Warning Threshold, continue. 9209 */ 9210 if (idma->idma_stalled[i] == 0) { 9211 idma->idma_stalled[i] = hz; 9212 idma->idma_warn[i] = 0; 9213 } else { 9214 idma->idma_stalled[i] += ticks; 9215 idma->idma_warn[i] -= ticks; 9216 } 9217 9218 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH*hz) 9219 continue; 9220 9221 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds. 9222 */ 9223 if (idma->idma_warn[i] > 0) 9224 continue; 9225 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT*hz; 9226 9227 /* Read and save the SGE IDMA State and Queue ID information. 9228 * We do this every time in case it changes across time ... 9229 * can't be too careful ... 9230 */ 9231 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 0); 9232 debug0 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9233 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f; 9234 9235 t4_write_reg(adapter, A_SGE_DEBUG_INDEX, 11); 9236 debug11 = t4_read_reg(adapter, A_SGE_DEBUG_DATA_LOW); 9237 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff; 9238 9239 CH_WARN(adapter, "SGE idma%u, queue %u, potentially stuck in " 9240 " state %u for %d seconds (debug0=%#x, debug11=%#x)\n", 9241 i, idma->idma_qid[i], idma->idma_state[i], 9242 idma->idma_stalled[i]/hz, 9243 debug0, debug11); 9244 t4_sge_decode_idma_state(adapter, idma->idma_state[i]); 9245 } 9246 } 9247 9248 /** 9249 * t4_read_pace_tbl - read the pace table 9250 * @adap: the adapter 9251 * @pace_vals: holds the returned values 9252 * 9253 * Returns the values of TP's pace table in microseconds. 9254 */ 9255 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]) 9256 { 9257 unsigned int i, v; 9258 9259 for (i = 0; i < NTX_SCHED; i++) { 9260 t4_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i); 9261 v = t4_read_reg(adap, A_TP_PACE_TABLE); 9262 pace_vals[i] = dack_ticks_to_usec(adap, v); 9263 } 9264 } 9265 9266 /** 9267 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler 9268 * @adap: the adapter 9269 * @sched: the scheduler index 9270 * @kbps: the byte rate in Kbps 9271 * @ipg: the interpacket delay in tenths of nanoseconds 9272 * 9273 * Return the current configuration of a HW Tx scheduler. 9274 */ 9275 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 9276 unsigned int *ipg, bool sleep_ok) 9277 { 9278 unsigned int v, addr, bpt, cpt; 9279 9280 if (kbps) { 9281 addr = A_TP_TX_MOD_Q1_Q0_RATE_LIMIT - sched / 2; 9282 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9283 if (sched & 1) 9284 v >>= 16; 9285 bpt = (v >> 8) & 0xff; 9286 cpt = v & 0xff; 9287 if (!cpt) 9288 *kbps = 0; /* scheduler disabled */ 9289 else { 9290 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */ 9291 *kbps = (v * bpt) / 125; 9292 } 9293 } 9294 if (ipg) { 9295 addr = A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR - sched / 2; 9296 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok); 9297 if (sched & 1) 9298 v >>= 16; 9299 v &= 0xffff; 9300 *ipg = (10000 * v) / core_ticks_per_usec(adap); 9301 } 9302 } 9303 9304 /** 9305 * t4_load_cfg - download config file 9306 * @adap: the adapter 9307 * @cfg_data: the cfg text file to write 9308 * @size: text file size 9309 * 9310 * Write the supplied config text file to the card's serial flash. 9311 */ 9312 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) 9313 { 9314 int ret, i, n, cfg_addr; 9315 unsigned int addr; 9316 unsigned int flash_cfg_start_sec; 9317 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9318 9319 cfg_addr = t4_flash_cfg_addr(adap); 9320 if (cfg_addr < 0) 9321 return cfg_addr; 9322 9323 addr = cfg_addr; 9324 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9325 9326 if (size > FLASH_CFG_MAX_SIZE) { 9327 CH_ERR(adap, "cfg file too large, max is %u bytes\n", 9328 FLASH_CFG_MAX_SIZE); 9329 return -EFBIG; 9330 } 9331 9332 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */ 9333 sf_sec_size); 9334 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9335 flash_cfg_start_sec + i - 1); 9336 /* 9337 * If size == 0 then we're simply erasing the FLASH sectors associated 9338 * with the on-adapter Firmware Configuration File. 9339 */ 9340 if (ret || size == 0) 9341 goto out; 9342 9343 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9344 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9345 if ( (size - i) < SF_PAGE_SIZE) 9346 n = size - i; 9347 else 9348 n = SF_PAGE_SIZE; 9349 ret = t4_write_flash(adap, addr, n, cfg_data, 1); 9350 if (ret) 9351 goto out; 9352 9353 addr += SF_PAGE_SIZE; 9354 cfg_data += SF_PAGE_SIZE; 9355 } 9356 9357 out: 9358 if (ret) 9359 CH_ERR(adap, "config file %s failed %d\n", 9360 (size == 0 ? "clear" : "download"), ret); 9361 return ret; 9362 } 9363 9364 /** 9365 * t5_fw_init_extern_mem - initialize the external memory 9366 * @adap: the adapter 9367 * 9368 * Initializes the external memory on T5. 9369 */ 9370 int t5_fw_init_extern_mem(struct adapter *adap) 9371 { 9372 u32 params[1], val[1]; 9373 int ret; 9374 9375 if (!is_t5(adap)) 9376 return 0; 9377 9378 val[0] = 0xff; /* Initialize all MCs */ 9379 params[0] = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 9380 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_MCINIT)); 9381 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, params, val, 9382 FW_CMD_MAX_TIMEOUT); 9383 9384 return ret; 9385 } 9386 9387 /* BIOS boot headers */ 9388 typedef struct pci_expansion_rom_header { 9389 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9390 u8 reserved[22]; /* Reserved per processor Architecture data */ 9391 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9392 } pci_exp_rom_header_t; /* PCI_EXPANSION_ROM_HEADER */ 9393 9394 /* Legacy PCI Expansion ROM Header */ 9395 typedef struct legacy_pci_expansion_rom_header { 9396 u8 signature[2]; /* ROM Signature. Should be 0xaa55 */ 9397 u8 size512; /* Current Image Size in units of 512 bytes */ 9398 u8 initentry_point[4]; 9399 u8 cksum; /* Checksum computed on the entire Image */ 9400 u8 reserved[16]; /* Reserved */ 9401 u8 pcir_offset[2]; /* Offset to PCI Data Struture */ 9402 } legacy_pci_exp_rom_header_t; /* LEGACY_PCI_EXPANSION_ROM_HEADER */ 9403 9404 /* EFI PCI Expansion ROM Header */ 9405 typedef struct efi_pci_expansion_rom_header { 9406 u8 signature[2]; // ROM signature. The value 0xaa55 9407 u8 initialization_size[2]; /* Units 512. Includes this header */ 9408 u8 efi_signature[4]; /* Signature from EFI image header. 0x0EF1 */ 9409 u8 efi_subsystem[2]; /* Subsystem value for EFI image header */ 9410 u8 efi_machine_type[2]; /* Machine type from EFI image header */ 9411 u8 compression_type[2]; /* Compression type. */ 9412 /* 9413 * Compression type definition 9414 * 0x0: uncompressed 9415 * 0x1: Compressed 9416 * 0x2-0xFFFF: Reserved 9417 */ 9418 u8 reserved[8]; /* Reserved */ 9419 u8 efi_image_header_offset[2]; /* Offset to EFI Image */ 9420 u8 pcir_offset[2]; /* Offset to PCI Data Structure */ 9421 } efi_pci_exp_rom_header_t; /* EFI PCI Expansion ROM Header */ 9422 9423 /* PCI Data Structure Format */ 9424 typedef struct pcir_data_structure { /* PCI Data Structure */ 9425 u8 signature[4]; /* Signature. The string "PCIR" */ 9426 u8 vendor_id[2]; /* Vendor Identification */ 9427 u8 device_id[2]; /* Device Identification */ 9428 u8 vital_product[2]; /* Pointer to Vital Product Data */ 9429 u8 length[2]; /* PCIR Data Structure Length */ 9430 u8 revision; /* PCIR Data Structure Revision */ 9431 u8 class_code[3]; /* Class Code */ 9432 u8 image_length[2]; /* Image Length. Multiple of 512B */ 9433 u8 code_revision[2]; /* Revision Level of Code/Data */ 9434 u8 code_type; /* Code Type. */ 9435 /* 9436 * PCI Expansion ROM Code Types 9437 * 0x00: Intel IA-32, PC-AT compatible. Legacy 9438 * 0x01: Open Firmware standard for PCI. FCODE 9439 * 0x02: Hewlett-Packard PA RISC. HP reserved 9440 * 0x03: EFI Image. EFI 9441 * 0x04-0xFF: Reserved. 9442 */ 9443 u8 indicator; /* Indicator. Identifies the last image in the ROM */ 9444 u8 reserved[2]; /* Reserved */ 9445 } pcir_data_t; /* PCI__DATA_STRUCTURE */ 9446 9447 /* BOOT constants */ 9448 enum { 9449 BOOT_FLASH_BOOT_ADDR = 0x0,/* start address of boot image in flash */ 9450 BOOT_SIGNATURE = 0xaa55, /* signature of BIOS boot ROM */ 9451 BOOT_SIZE_INC = 512, /* image size measured in 512B chunks */ 9452 BOOT_MIN_SIZE = sizeof(pci_exp_rom_header_t), /* basic header */ 9453 BOOT_MAX_SIZE = 1024*BOOT_SIZE_INC, /* 1 byte * length increment */ 9454 VENDOR_ID = 0x1425, /* Vendor ID */ 9455 PCIR_SIGNATURE = 0x52494350 /* PCIR signature */ 9456 }; 9457 9458 /* 9459 * modify_device_id - Modifies the device ID of the Boot BIOS image 9460 * @adatper: the device ID to write. 9461 * @boot_data: the boot image to modify. 9462 * 9463 * Write the supplied device ID to the boot BIOS image. 9464 */ 9465 static void modify_device_id(int device_id, u8 *boot_data) 9466 { 9467 legacy_pci_exp_rom_header_t *header; 9468 pcir_data_t *pcir_header; 9469 u32 cur_header = 0; 9470 9471 /* 9472 * Loop through all chained images and change the device ID's 9473 */ 9474 while (1) { 9475 header = (legacy_pci_exp_rom_header_t *) &boot_data[cur_header]; 9476 pcir_header = (pcir_data_t *) &boot_data[cur_header + 9477 le16_to_cpu(*(u16*)header->pcir_offset)]; 9478 9479 /* 9480 * Only modify the Device ID if code type is Legacy or HP. 9481 * 0x00: Okay to modify 9482 * 0x01: FCODE. Do not be modify 9483 * 0x03: Okay to modify 9484 * 0x04-0xFF: Do not modify 9485 */ 9486 if (pcir_header->code_type == 0x00) { 9487 u8 csum = 0; 9488 int i; 9489 9490 /* 9491 * Modify Device ID to match current adatper 9492 */ 9493 *(u16*) pcir_header->device_id = device_id; 9494 9495 /* 9496 * Set checksum temporarily to 0. 9497 * We will recalculate it later. 9498 */ 9499 header->cksum = 0x0; 9500 9501 /* 9502 * Calculate and update checksum 9503 */ 9504 for (i = 0; i < (header->size512 * 512); i++) 9505 csum += (u8)boot_data[cur_header + i]; 9506 9507 /* 9508 * Invert summed value to create the checksum 9509 * Writing new checksum value directly to the boot data 9510 */ 9511 boot_data[cur_header + 7] = -csum; 9512 9513 } else if (pcir_header->code_type == 0x03) { 9514 9515 /* 9516 * Modify Device ID to match current adatper 9517 */ 9518 *(u16*) pcir_header->device_id = device_id; 9519 9520 } 9521 9522 9523 /* 9524 * Check indicator element to identify if this is the last 9525 * image in the ROM. 9526 */ 9527 if (pcir_header->indicator & 0x80) 9528 break; 9529 9530 /* 9531 * Move header pointer up to the next image in the ROM. 9532 */ 9533 cur_header += header->size512 * 512; 9534 } 9535 } 9536 9537 /* 9538 * t4_load_boot - download boot flash 9539 * @adapter: the adapter 9540 * @boot_data: the boot image to write 9541 * @boot_addr: offset in flash to write boot_data 9542 * @size: image size 9543 * 9544 * Write the supplied boot image to the card's serial flash. 9545 * The boot image has the following sections: a 28-byte header and the 9546 * boot image. 9547 */ 9548 int t4_load_boot(struct adapter *adap, u8 *boot_data, 9549 unsigned int boot_addr, unsigned int size) 9550 { 9551 pci_exp_rom_header_t *header; 9552 int pcir_offset ; 9553 pcir_data_t *pcir_header; 9554 int ret, addr; 9555 uint16_t device_id; 9556 unsigned int i; 9557 unsigned int boot_sector = (boot_addr * 1024 ); 9558 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9559 9560 /* 9561 * Make sure the boot image does not encroach on the firmware region 9562 */ 9563 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) { 9564 CH_ERR(adap, "boot image encroaching on firmware region\n"); 9565 return -EFBIG; 9566 } 9567 9568 /* 9569 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot, 9570 * and Boot configuration data sections. These 3 boot sections span 9571 * sectors 0 to 7 in flash and live right before the FW image location. 9572 */ 9573 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, 9574 sf_sec_size); 9575 ret = t4_flash_erase_sectors(adap, boot_sector >> 16, 9576 (boot_sector >> 16) + i - 1); 9577 9578 /* 9579 * If size == 0 then we're simply erasing the FLASH sectors associated 9580 * with the on-adapter option ROM file 9581 */ 9582 if (ret || (size == 0)) 9583 goto out; 9584 9585 /* Get boot header */ 9586 header = (pci_exp_rom_header_t *)boot_data; 9587 pcir_offset = le16_to_cpu(*(u16 *)header->pcir_offset); 9588 /* PCIR Data Structure */ 9589 pcir_header = (pcir_data_t *) &boot_data[pcir_offset]; 9590 9591 /* 9592 * Perform some primitive sanity testing to avoid accidentally 9593 * writing garbage over the boot sectors. We ought to check for 9594 * more but it's not worth it for now ... 9595 */ 9596 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) { 9597 CH_ERR(adap, "boot image too small/large\n"); 9598 return -EFBIG; 9599 } 9600 9601 #ifndef CHELSIO_T4_DIAGS 9602 /* 9603 * Check BOOT ROM header signature 9604 */ 9605 if (le16_to_cpu(*(u16*)header->signature) != BOOT_SIGNATURE ) { 9606 CH_ERR(adap, "Boot image missing signature\n"); 9607 return -EINVAL; 9608 } 9609 9610 /* 9611 * Check PCI header signature 9612 */ 9613 if (le32_to_cpu(*(u32*)pcir_header->signature) != PCIR_SIGNATURE) { 9614 CH_ERR(adap, "PCI header missing signature\n"); 9615 return -EINVAL; 9616 } 9617 9618 /* 9619 * Check Vendor ID matches Chelsio ID 9620 */ 9621 if (le16_to_cpu(*(u16*)pcir_header->vendor_id) != VENDOR_ID) { 9622 CH_ERR(adap, "Vendor ID missing signature\n"); 9623 return -EINVAL; 9624 } 9625 #endif 9626 9627 /* 9628 * Retrieve adapter's device ID 9629 */ 9630 t4_os_pci_read_cfg2(adap, PCI_DEVICE_ID, &device_id); 9631 /* Want to deal with PF 0 so I strip off PF 4 indicator */ 9632 device_id = device_id & 0xf0ff; 9633 9634 /* 9635 * Check PCIE Device ID 9636 */ 9637 if (le16_to_cpu(*(u16*)pcir_header->device_id) != device_id) { 9638 /* 9639 * Change the device ID in the Boot BIOS image to match 9640 * the Device ID of the current adapter. 9641 */ 9642 modify_device_id(device_id, boot_data); 9643 } 9644 9645 /* 9646 * Skip over the first SF_PAGE_SIZE worth of data and write it after 9647 * we finish copying the rest of the boot image. This will ensure 9648 * that the BIOS boot header will only be written if the boot image 9649 * was written in full. 9650 */ 9651 addr = boot_sector; 9652 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 9653 addr += SF_PAGE_SIZE; 9654 boot_data += SF_PAGE_SIZE; 9655 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data, 0); 9656 if (ret) 9657 goto out; 9658 } 9659 9660 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE, 9661 (const u8 *)header, 0); 9662 9663 out: 9664 if (ret) 9665 CH_ERR(adap, "boot image download failed, error %d\n", ret); 9666 return ret; 9667 } 9668 9669 /* 9670 * t4_flash_bootcfg_addr - return the address of the flash optionrom configuration 9671 * @adapter: the adapter 9672 * 9673 * Return the address within the flash where the OptionROM Configuration 9674 * is stored, or an error if the device FLASH is too small to contain 9675 * a OptionROM Configuration. 9676 */ 9677 static int t4_flash_bootcfg_addr(struct adapter *adapter) 9678 { 9679 /* 9680 * If the device FLASH isn't large enough to hold a Firmware 9681 * Configuration File, return an error. 9682 */ 9683 if (adapter->params.sf_size < FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE) 9684 return -ENOSPC; 9685 9686 return FLASH_BOOTCFG_START; 9687 } 9688 9689 int t4_load_bootcfg(struct adapter *adap,const u8 *cfg_data, unsigned int size) 9690 { 9691 int ret, i, n, cfg_addr; 9692 unsigned int addr; 9693 unsigned int flash_cfg_start_sec; 9694 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; 9695 9696 cfg_addr = t4_flash_bootcfg_addr(adap); 9697 if (cfg_addr < 0) 9698 return cfg_addr; 9699 9700 addr = cfg_addr; 9701 flash_cfg_start_sec = addr / SF_SEC_SIZE; 9702 9703 if (size > FLASH_BOOTCFG_MAX_SIZE) { 9704 CH_ERR(adap, "bootcfg file too large, max is %u bytes\n", 9705 FLASH_BOOTCFG_MAX_SIZE); 9706 return -EFBIG; 9707 } 9708 9709 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,/* # of sectors spanned */ 9710 sf_sec_size); 9711 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, 9712 flash_cfg_start_sec + i - 1); 9713 9714 /* 9715 * If size == 0 then we're simply erasing the FLASH sectors associated 9716 * with the on-adapter OptionROM Configuration File. 9717 */ 9718 if (ret || size == 0) 9719 goto out; 9720 9721 /* this will write to the flash up to SF_PAGE_SIZE at a time */ 9722 for (i = 0; i< size; i+= SF_PAGE_SIZE) { 9723 if ( (size - i) < SF_PAGE_SIZE) 9724 n = size - i; 9725 else 9726 n = SF_PAGE_SIZE; 9727 ret = t4_write_flash(adap, addr, n, cfg_data, 0); 9728 if (ret) 9729 goto out; 9730 9731 addr += SF_PAGE_SIZE; 9732 cfg_data += SF_PAGE_SIZE; 9733 } 9734 9735 out: 9736 if (ret) 9737 CH_ERR(adap, "boot config data %s failed %d\n", 9738 (size == 0 ? "clear" : "download"), ret); 9739 return ret; 9740 } 9741 9742 /** 9743 * t4_set_filter_mode - configure the optional components of filter tuples 9744 * @adap: the adapter 9745 * @mode_map: a bitmap selcting which optional filter components to enable 9746 * @sleep_ok: if true we may sleep while awaiting command completion 9747 * 9748 * Sets the filter mode by selecting the optional components to enable 9749 * in filter tuples. Returns 0 on success and a negative error if the 9750 * requested mode needs more bits than are available for optional 9751 * components. 9752 */ 9753 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 9754 bool sleep_ok) 9755 { 9756 static u8 width[] = { 1, 3, 17, 17, 8, 8, 16, 9, 3, 1 }; 9757 9758 int i, nbits = 0; 9759 9760 for (i = S_FCOE; i <= S_FRAGMENTATION; i++) 9761 if (mode_map & (1 << i)) 9762 nbits += width[i]; 9763 if (nbits > FILTER_OPT_LEN) 9764 return -EINVAL; 9765 t4_tp_pio_write(adap, &mode_map, 1, A_TP_VLAN_PRI_MAP, sleep_ok); 9766 read_filter_mode_and_ingress_config(adap, sleep_ok); 9767 9768 return 0; 9769 } 9770 9771 /** 9772 * t4_clr_port_stats - clear port statistics 9773 * @adap: the adapter 9774 * @idx: the port index 9775 * 9776 * Clear HW statistics for the given port. 9777 */ 9778 void t4_clr_port_stats(struct adapter *adap, int idx) 9779 { 9780 unsigned int i; 9781 u32 bgmap = adap2pinfo(adap, idx)->mps_bg_map; 9782 u32 port_base_addr; 9783 9784 if (is_t4(adap)) 9785 port_base_addr = PORT_BASE(idx); 9786 else 9787 port_base_addr = T5_PORT_BASE(idx); 9788 9789 for (i = A_MPS_PORT_STAT_TX_PORT_BYTES_L; 9790 i <= A_MPS_PORT_STAT_TX_PORT_PPP7_H; i += 8) 9791 t4_write_reg(adap, port_base_addr + i, 0); 9792 for (i = A_MPS_PORT_STAT_RX_PORT_BYTES_L; 9793 i <= A_MPS_PORT_STAT_RX_PORT_LESS_64B_H; i += 8) 9794 t4_write_reg(adap, port_base_addr + i, 0); 9795 for (i = 0; i < 4; i++) 9796 if (bgmap & (1 << i)) { 9797 t4_write_reg(adap, 9798 A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L + i * 8, 0); 9799 t4_write_reg(adap, 9800 A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L + i * 8, 0); 9801 } 9802 } 9803 9804 /** 9805 * t4_i2c_rd - read I2C data from adapter 9806 * @adap: the adapter 9807 * @port: Port number if per-port device; <0 if not 9808 * @devid: per-port device ID or absolute device ID 9809 * @offset: byte offset into device I2C space 9810 * @len: byte length of I2C space data 9811 * @buf: buffer in which to return I2C data 9812 * 9813 * Reads the I2C data from the indicated device and location. 9814 */ 9815 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 9816 int port, unsigned int devid, 9817 unsigned int offset, unsigned int len, 9818 u8 *buf) 9819 { 9820 u32 ldst_addrspace; 9821 struct fw_ldst_cmd ldst; 9822 int ret; 9823 9824 if (port >= 4 || 9825 devid >= 256 || 9826 offset >= 256 || 9827 len > sizeof ldst.u.i2c.data) 9828 return -EINVAL; 9829 9830 memset(&ldst, 0, sizeof ldst); 9831 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9832 ldst.op_to_addrspace = 9833 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9834 F_FW_CMD_REQUEST | 9835 F_FW_CMD_READ | 9836 ldst_addrspace); 9837 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9838 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9839 ldst.u.i2c.did = devid; 9840 ldst.u.i2c.boffset = offset; 9841 ldst.u.i2c.blen = len; 9842 ret = t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9843 if (!ret) 9844 memcpy(buf, ldst.u.i2c.data, len); 9845 return ret; 9846 } 9847 9848 /** 9849 * t4_i2c_wr - write I2C data to adapter 9850 * @adap: the adapter 9851 * @port: Port number if per-port device; <0 if not 9852 * @devid: per-port device ID or absolute device ID 9853 * @offset: byte offset into device I2C space 9854 * @len: byte length of I2C space data 9855 * @buf: buffer containing new I2C data 9856 * 9857 * Write the I2C data to the indicated device and location. 9858 */ 9859 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 9860 int port, unsigned int devid, 9861 unsigned int offset, unsigned int len, 9862 u8 *buf) 9863 { 9864 u32 ldst_addrspace; 9865 struct fw_ldst_cmd ldst; 9866 9867 if (port >= 4 || 9868 devid >= 256 || 9869 offset >= 256 || 9870 len > sizeof ldst.u.i2c.data) 9871 return -EINVAL; 9872 9873 memset(&ldst, 0, sizeof ldst); 9874 ldst_addrspace = V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_I2C); 9875 ldst.op_to_addrspace = 9876 cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9877 F_FW_CMD_REQUEST | 9878 F_FW_CMD_WRITE | 9879 ldst_addrspace); 9880 ldst.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst)); 9881 ldst.u.i2c.pid = (port < 0 ? 0xff : port); 9882 ldst.u.i2c.did = devid; 9883 ldst.u.i2c.boffset = offset; 9884 ldst.u.i2c.blen = len; 9885 memcpy(ldst.u.i2c.data, buf, len); 9886 return t4_wr_mbox(adap, mbox, &ldst, sizeof ldst, &ldst); 9887 } 9888 9889 /** 9890 * t4_sge_ctxt_rd - read an SGE context through FW 9891 * @adap: the adapter 9892 * @mbox: mailbox to use for the FW command 9893 * @cid: the context id 9894 * @ctype: the context type 9895 * @data: where to store the context data 9896 * 9897 * Issues a FW command through the given mailbox to read an SGE context. 9898 */ 9899 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 9900 enum ctxt_type ctype, u32 *data) 9901 { 9902 int ret; 9903 struct fw_ldst_cmd c; 9904 9905 if (ctype == CTXT_EGRESS) 9906 ret = FW_LDST_ADDRSPC_SGE_EGRC; 9907 else if (ctype == CTXT_INGRESS) 9908 ret = FW_LDST_ADDRSPC_SGE_INGC; 9909 else if (ctype == CTXT_FLM) 9910 ret = FW_LDST_ADDRSPC_SGE_FLMC; 9911 else 9912 ret = FW_LDST_ADDRSPC_SGE_CONMC; 9913 9914 memset(&c, 0, sizeof(c)); 9915 c.op_to_addrspace = cpu_to_be32(V_FW_CMD_OP(FW_LDST_CMD) | 9916 F_FW_CMD_REQUEST | F_FW_CMD_READ | 9917 V_FW_LDST_CMD_ADDRSPACE(ret)); 9918 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c)); 9919 c.u.idctxt.physid = cpu_to_be32(cid); 9920 9921 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); 9922 if (ret == 0) { 9923 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0); 9924 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1); 9925 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2); 9926 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3); 9927 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4); 9928 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5); 9929 } 9930 return ret; 9931 } 9932 9933 /** 9934 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW 9935 * @adap: the adapter 9936 * @cid: the context id 9937 * @ctype: the context type 9938 * @data: where to store the context data 9939 * 9940 * Reads an SGE context directly, bypassing FW. This is only for 9941 * debugging when FW is unavailable. 9942 */ 9943 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 9944 u32 *data) 9945 { 9946 int i, ret; 9947 9948 t4_write_reg(adap, A_SGE_CTXT_CMD, V_CTXTQID(cid) | V_CTXTTYPE(ctype)); 9949 ret = t4_wait_op_done(adap, A_SGE_CTXT_CMD, F_BUSY, 0, 3, 1); 9950 if (!ret) 9951 for (i = A_SGE_CTXT_DATA0; i <= A_SGE_CTXT_DATA5; i += 4) 9952 *data++ = t4_read_reg(adap, i); 9953 return ret; 9954 } 9955 9956 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 9957 int sleep_ok) 9958 { 9959 struct fw_sched_cmd cmd; 9960 9961 memset(&cmd, 0, sizeof(cmd)); 9962 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9963 F_FW_CMD_REQUEST | 9964 F_FW_CMD_WRITE); 9965 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9966 9967 cmd.u.config.sc = FW_SCHED_SC_CONFIG; 9968 cmd.u.config.type = type; 9969 cmd.u.config.minmaxen = minmaxen; 9970 9971 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 9972 NULL, sleep_ok); 9973 } 9974 9975 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 9976 int rateunit, int ratemode, int channel, int cl, 9977 int minrate, int maxrate, int weight, int pktsize, 9978 int burstsize, int sleep_ok) 9979 { 9980 struct fw_sched_cmd cmd; 9981 9982 memset(&cmd, 0, sizeof(cmd)); 9983 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 9984 F_FW_CMD_REQUEST | 9985 F_FW_CMD_WRITE); 9986 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 9987 9988 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 9989 cmd.u.params.type = type; 9990 cmd.u.params.level = level; 9991 cmd.u.params.mode = mode; 9992 cmd.u.params.ch = channel; 9993 cmd.u.params.cl = cl; 9994 cmd.u.params.unit = rateunit; 9995 cmd.u.params.rate = ratemode; 9996 cmd.u.params.min = cpu_to_be32(minrate); 9997 cmd.u.params.max = cpu_to_be32(maxrate); 9998 cmd.u.params.weight = cpu_to_be16(weight); 9999 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10000 cmd.u.params.burstsize = cpu_to_be16(burstsize); 10001 10002 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10003 NULL, sleep_ok); 10004 } 10005 10006 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 10007 unsigned int maxrate, int sleep_ok) 10008 { 10009 struct fw_sched_cmd cmd; 10010 10011 memset(&cmd, 0, sizeof(cmd)); 10012 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10013 F_FW_CMD_REQUEST | 10014 F_FW_CMD_WRITE); 10015 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10016 10017 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10018 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10019 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CH_RL; 10020 cmd.u.params.ch = channel; 10021 cmd.u.params.rate = ratemode; /* REL or ABS */ 10022 cmd.u.params.max = cpu_to_be32(maxrate);/* % or kbps */ 10023 10024 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10025 NULL, sleep_ok); 10026 } 10027 10028 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 10029 int weight, int sleep_ok) 10030 { 10031 struct fw_sched_cmd cmd; 10032 10033 if (weight < 0 || weight > 100) 10034 return -EINVAL; 10035 10036 memset(&cmd, 0, sizeof(cmd)); 10037 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10038 F_FW_CMD_REQUEST | 10039 F_FW_CMD_WRITE); 10040 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10041 10042 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10043 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10044 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_WRR; 10045 cmd.u.params.ch = channel; 10046 cmd.u.params.cl = cl; 10047 cmd.u.params.weight = cpu_to_be16(weight); 10048 10049 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10050 NULL, sleep_ok); 10051 } 10052 10053 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 10054 int mode, unsigned int maxrate, int pktsize, int sleep_ok) 10055 { 10056 struct fw_sched_cmd cmd; 10057 10058 memset(&cmd, 0, sizeof(cmd)); 10059 cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_SCHED_CMD) | 10060 F_FW_CMD_REQUEST | 10061 F_FW_CMD_WRITE); 10062 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd)); 10063 10064 cmd.u.params.sc = FW_SCHED_SC_PARAMS; 10065 cmd.u.params.type = FW_SCHED_TYPE_PKTSCHED; 10066 cmd.u.params.level = FW_SCHED_PARAMS_LEVEL_CL_RL; 10067 cmd.u.params.mode = mode; 10068 cmd.u.params.ch = channel; 10069 cmd.u.params.cl = cl; 10070 cmd.u.params.unit = FW_SCHED_PARAMS_UNIT_BITRATE; 10071 cmd.u.params.rate = FW_SCHED_PARAMS_RATE_ABS; 10072 cmd.u.params.max = cpu_to_be32(maxrate); 10073 cmd.u.params.pktsize = cpu_to_be16(pktsize); 10074 10075 return t4_wr_mbox_meat(adapter,adapter->mbox, &cmd, sizeof(cmd), 10076 NULL, sleep_ok); 10077 } 10078 10079 /* 10080 * t4_config_watchdog - configure (enable/disable) a watchdog timer 10081 * @adapter: the adapter 10082 * @mbox: mailbox to use for the FW command 10083 * @pf: the PF owning the queue 10084 * @vf: the VF owning the queue 10085 * @timeout: watchdog timeout in ms 10086 * @action: watchdog timer / action 10087 * 10088 * There are separate watchdog timers for each possible watchdog 10089 * action. Configure one of the watchdog timers by setting a non-zero 10090 * timeout. Disable a watchdog timer by using a timeout of zero. 10091 */ 10092 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 10093 unsigned int pf, unsigned int vf, 10094 unsigned int timeout, unsigned int action) 10095 { 10096 struct fw_watchdog_cmd wdog; 10097 unsigned int ticks; 10098 10099 /* 10100 * The watchdog command expects a timeout in units of 10ms so we need 10101 * to convert it here (via rounding) and force a minimum of one 10ms 10102 * "tick" if the timeout is non-zero but the conversion results in 0 10103 * ticks. 10104 */ 10105 ticks = (timeout + 5)/10; 10106 if (timeout && !ticks) 10107 ticks = 1; 10108 10109 memset(&wdog, 0, sizeof wdog); 10110 wdog.op_to_vfn = cpu_to_be32(V_FW_CMD_OP(FW_WATCHDOG_CMD) | 10111 F_FW_CMD_REQUEST | 10112 F_FW_CMD_WRITE | 10113 V_FW_PARAMS_CMD_PFN(pf) | 10114 V_FW_PARAMS_CMD_VFN(vf)); 10115 wdog.retval_len16 = cpu_to_be32(FW_LEN16(wdog)); 10116 wdog.timeout = cpu_to_be32(ticks); 10117 wdog.action = cpu_to_be32(action); 10118 10119 return t4_wr_mbox(adapter, mbox, &wdog, sizeof wdog, NULL); 10120 } 10121 10122 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level) 10123 { 10124 struct fw_devlog_cmd devlog_cmd; 10125 int ret; 10126 10127 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10128 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10129 F_FW_CMD_REQUEST | F_FW_CMD_READ); 10130 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10131 ret = t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10132 sizeof(devlog_cmd), &devlog_cmd); 10133 if (ret) 10134 return ret; 10135 10136 *level = devlog_cmd.level; 10137 return 0; 10138 } 10139 10140 int t4_set_devlog_level(struct adapter *adapter, unsigned int level) 10141 { 10142 struct fw_devlog_cmd devlog_cmd; 10143 10144 memset(&devlog_cmd, 0, sizeof(devlog_cmd)); 10145 devlog_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_DEVLOG_CMD) | 10146 F_FW_CMD_REQUEST | 10147 F_FW_CMD_WRITE); 10148 devlog_cmd.level = level; 10149 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd)); 10150 return t4_wr_mbox(adapter, adapter->mbox, &devlog_cmd, 10151 sizeof(devlog_cmd), &devlog_cmd); 10152 } 10153