1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef __CHELSIO_COMMON_H 31 #define __CHELSIO_COMMON_H 32 33 #include "t4_hw.h" 34 35 36 enum { 37 MAX_NPORTS = 4, /* max # of ports */ 38 SERNUM_LEN = 24, /* Serial # length */ 39 EC_LEN = 16, /* E/C length */ 40 ID_LEN = 16, /* ID length */ 41 PN_LEN = 16, /* Part Number length */ 42 MACADDR_LEN = 12, /* MAC Address length */ 43 }; 44 45 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 46 47 enum { 48 MEMWIN0_APERTURE = 2048, 49 MEMWIN0_BASE = 0x1b800, 50 51 MEMWIN1_APERTURE = 32768, 52 MEMWIN1_BASE = 0x28000, 53 54 MEMWIN2_APERTURE_T4 = 65536, 55 MEMWIN2_BASE_T4 = 0x30000, 56 57 MEMWIN2_APERTURE_T5 = 128 * 1024, 58 MEMWIN2_BASE_T5 = 0x60000, 59 }; 60 61 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 62 63 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 64 65 enum { 66 PAUSE_RX = 1 << 0, 67 PAUSE_TX = 1 << 1, 68 PAUSE_AUTONEG = 1 << 2 69 }; 70 71 struct memwin { 72 uint32_t base; 73 uint32_t aperture; 74 }; 75 76 struct port_stats { 77 u64 tx_octets; /* total # of octets in good frames */ 78 u64 tx_frames; /* all good frames */ 79 u64 tx_bcast_frames; /* all broadcast frames */ 80 u64 tx_mcast_frames; /* all multicast frames */ 81 u64 tx_ucast_frames; /* all unicast frames */ 82 u64 tx_error_frames; /* all error frames */ 83 84 u64 tx_frames_64; /* # of Tx frames in a particular range */ 85 u64 tx_frames_65_127; 86 u64 tx_frames_128_255; 87 u64 tx_frames_256_511; 88 u64 tx_frames_512_1023; 89 u64 tx_frames_1024_1518; 90 u64 tx_frames_1519_max; 91 92 u64 tx_drop; /* # of dropped Tx frames */ 93 u64 tx_pause; /* # of transmitted pause frames */ 94 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 95 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 96 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 97 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 98 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 99 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 100 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 101 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 102 103 u64 rx_octets; /* total # of octets in good frames */ 104 u64 rx_frames; /* all good frames */ 105 u64 rx_bcast_frames; /* all broadcast frames */ 106 u64 rx_mcast_frames; /* all multicast frames */ 107 u64 rx_ucast_frames; /* all unicast frames */ 108 u64 rx_too_long; /* # of frames exceeding MTU */ 109 u64 rx_jabber; /* # of jabber frames */ 110 u64 rx_fcs_err; /* # of received frames with bad FCS */ 111 u64 rx_len_err; /* # of received frames with length error */ 112 u64 rx_symbol_err; /* symbol errors */ 113 u64 rx_runt; /* # of short frames */ 114 115 u64 rx_frames_64; /* # of Rx frames in a particular range */ 116 u64 rx_frames_65_127; 117 u64 rx_frames_128_255; 118 u64 rx_frames_256_511; 119 u64 rx_frames_512_1023; 120 u64 rx_frames_1024_1518; 121 u64 rx_frames_1519_max; 122 123 u64 rx_pause; /* # of received pause frames */ 124 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 125 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 126 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 127 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 128 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 129 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 130 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 131 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 132 133 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 134 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 135 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 136 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 137 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 138 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 139 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 140 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 141 }; 142 143 struct lb_port_stats { 144 u64 octets; 145 u64 frames; 146 u64 bcast_frames; 147 u64 mcast_frames; 148 u64 ucast_frames; 149 u64 error_frames; 150 151 u64 frames_64; 152 u64 frames_65_127; 153 u64 frames_128_255; 154 u64 frames_256_511; 155 u64 frames_512_1023; 156 u64 frames_1024_1518; 157 u64 frames_1519_max; 158 159 u64 drop; 160 161 u64 ovflow0; 162 u64 ovflow1; 163 u64 ovflow2; 164 u64 ovflow3; 165 u64 trunc0; 166 u64 trunc1; 167 u64 trunc2; 168 u64 trunc3; 169 }; 170 171 struct tp_tcp_stats { 172 u32 tcp_out_rsts; 173 u64 tcp_in_segs; 174 u64 tcp_out_segs; 175 u64 tcp_retrans_segs; 176 }; 177 178 struct tp_usm_stats { 179 u32 frames; 180 u32 drops; 181 u64 octets; 182 }; 183 184 struct tp_fcoe_stats { 185 u32 frames_ddp; 186 u32 frames_drop; 187 u64 octets_ddp; 188 }; 189 190 struct tp_err_stats { 191 u32 mac_in_errs[MAX_NCHAN]; 192 u32 hdr_in_errs[MAX_NCHAN]; 193 u32 tcp_in_errs[MAX_NCHAN]; 194 u32 tnl_cong_drops[MAX_NCHAN]; 195 u32 ofld_chan_drops[MAX_NCHAN]; 196 u32 tnl_tx_drops[MAX_NCHAN]; 197 u32 ofld_vlan_drops[MAX_NCHAN]; 198 u32 tcp6_in_errs[MAX_NCHAN]; 199 u32 ofld_no_neigh; 200 u32 ofld_cong_defer; 201 }; 202 203 struct tp_proxy_stats { 204 u32 proxy[MAX_NCHAN]; 205 }; 206 207 struct tp_cpl_stats { 208 u32 req[MAX_NCHAN]; 209 u32 rsp[MAX_NCHAN]; 210 }; 211 212 struct tp_rdma_stats { 213 u32 rqe_dfr_pkt; 214 u32 rqe_dfr_mod; 215 }; 216 217 struct tp_params { 218 unsigned int ntxchan; /* # of Tx channels */ 219 unsigned int tre; /* log2 of core clocks per TP tick */ 220 unsigned int dack_re; /* DACK timer resolution */ 221 unsigned int la_mask; /* what events are recorded by TP LA */ 222 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 223 uint32_t vlan_pri_map; 224 uint32_t ingress_config; 225 int8_t vlan_shift; 226 int8_t vnic_shift; 227 int8_t port_shift; 228 int8_t protocol_shift; 229 }; 230 231 struct vpd_params { 232 unsigned int cclk; 233 u8 ec[EC_LEN + 1]; 234 u8 sn[SERNUM_LEN + 1]; 235 u8 id[ID_LEN + 1]; 236 u8 pn[PN_LEN + 1]; 237 u8 na[MACADDR_LEN + 1]; 238 }; 239 240 struct pci_params { 241 unsigned int vpd_cap_addr; 242 unsigned int mps; 243 unsigned short speed; 244 unsigned short width; 245 }; 246 247 /* 248 * Firmware device log. 249 */ 250 struct devlog_params { 251 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 252 u32 start; /* start of log in firmware memory */ 253 u32 size; /* size of log */ 254 }; 255 256 /* Stores chip specific parameters */ 257 struct chip_params { 258 u8 nchan; 259 u8 pm_stats_cnt; 260 u8 cng_ch_bits_log; /* congestion channel map bits width */ 261 u8 nsched_cls; 262 u8 cim_num_obq; 263 u16 mps_rplc_size; 264 u16 vfcount; 265 u32 sge_fl_db; 266 u16 mps_tcam_size; 267 }; 268 269 struct adapter_params { 270 struct tp_params tp; 271 struct vpd_params vpd; 272 struct pci_params pci; 273 struct devlog_params devlog; 274 275 unsigned int sf_size; /* serial flash size in bytes */ 276 unsigned int sf_nsec; /* # of flash sectors */ 277 278 unsigned int fw_vers; 279 unsigned int tp_vers; 280 281 unsigned short mtus[NMTUS]; 282 unsigned short a_wnd[NCCTRL_WIN]; 283 unsigned short b_wnd[NCCTRL_WIN]; 284 285 u_int ftid_min; 286 u_int ftid_max; 287 u_int etid_min; 288 u_int netids; 289 290 unsigned int cim_la_size; 291 292 uint8_t nports; /* # of ethernet ports */ 293 uint8_t portvec; 294 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 295 unsigned int rev:4; /* chip revision */ 296 unsigned int fpga:1; /* this is an FPGA */ 297 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 298 resources for TOE operation. */ 299 unsigned int bypass:1; /* this is a bypass card */ 300 unsigned int ethoffload:1; 301 302 unsigned int ofldq_wr_cred; 303 unsigned int eo_wr_cred; 304 }; 305 306 #define CHELSIO_T4 0x4 307 #define CHELSIO_T5 0x5 308 #define CHELSIO_T6 0x6 309 310 struct trace_params { 311 u32 data[TRACE_LEN / 4]; 312 u32 mask[TRACE_LEN / 4]; 313 unsigned short snap_len; 314 unsigned short min_len; 315 unsigned char skip_ofst; 316 unsigned char skip_len; 317 unsigned char invert; 318 unsigned char port; 319 }; 320 321 struct link_config { 322 unsigned short supported; /* link capabilities */ 323 unsigned short advertising; /* advertised capabilities */ 324 unsigned short requested_speed; /* speed user has requested */ 325 unsigned short speed; /* actual link speed */ 326 unsigned char requested_fc; /* flow control user has requested */ 327 unsigned char fc; /* actual link flow control */ 328 unsigned char autoneg; /* autonegotiating? */ 329 unsigned char link_ok; /* link up? */ 330 }; 331 332 #include "adapter.h" 333 334 #ifndef PCI_VENDOR_ID_CHELSIO 335 # define PCI_VENDOR_ID_CHELSIO 0x1425 336 #endif 337 338 #define for_each_port(adapter, iter) \ 339 for (iter = 0; iter < (adapter)->params.nports; ++iter) 340 341 static inline int is_ftid(const struct adapter *sc, u_int tid) 342 { 343 344 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max); 345 } 346 347 static inline int is_etid(const struct adapter *sc, u_int tid) 348 { 349 350 return (tid >= sc->params.etid_min); 351 } 352 353 static inline int is_offload(const struct adapter *adap) 354 { 355 return adap->params.offload; 356 } 357 358 static inline int is_ethoffload(const struct adapter *adap) 359 { 360 return adap->params.ethoffload; 361 } 362 363 static inline int chip_id(struct adapter *adap) 364 { 365 return adap->params.chipid; 366 } 367 368 static inline int chip_rev(struct adapter *adap) 369 { 370 return adap->params.rev; 371 } 372 373 static inline int is_t4(struct adapter *adap) 374 { 375 return adap->params.chipid == CHELSIO_T4; 376 } 377 378 static inline int is_t5(struct adapter *adap) 379 { 380 return adap->params.chipid == CHELSIO_T5; 381 } 382 383 static inline int is_t6(struct adapter *adap) 384 { 385 return adap->params.chipid == CHELSIO_T6; 386 } 387 388 static inline int is_fpga(struct adapter *adap) 389 { 390 return adap->params.fpga; 391 } 392 393 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 394 { 395 return adap->params.vpd.cclk / 1000; 396 } 397 398 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 399 unsigned int us) 400 { 401 return (us * adap->params.vpd.cclk) / 1000; 402 } 403 404 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 405 unsigned int ticks) 406 { 407 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 408 } 409 410 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 411 412 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 413 void *rpl, bool sleep_ok); 414 415 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 416 int size, void *rpl) 417 { 418 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 419 } 420 421 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 422 int size, void *rpl) 423 { 424 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 425 } 426 427 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 428 unsigned int data_reg, u32 *vals, unsigned int nregs, 429 unsigned int start_idx); 430 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 431 unsigned int data_reg, const u32 *vals, 432 unsigned int nregs, unsigned int start_idx); 433 434 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 435 436 struct fw_filter_wr; 437 438 void t4_intr_enable(struct adapter *adapter); 439 void t4_intr_disable(struct adapter *adapter); 440 void t4_intr_clear(struct adapter *adapter); 441 int t4_slow_intr_handler(struct adapter *adapter); 442 443 int t4_hash_mac_addr(const u8 *addr); 444 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 445 struct link_config *lc); 446 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 447 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 448 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 449 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 450 int t4_seeprom_wp(struct adapter *adapter, int enable); 451 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 452 u32 *data, int byte_oriented); 453 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 454 int t4_load_boot(struct adapter *adap, u8 *boot_data, 455 unsigned int boot_addr, unsigned int size); 456 int t4_flash_cfg_addr(struct adapter *adapter); 457 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 458 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 459 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 460 int t4_check_fw_version(struct adapter *adapter); 461 int t4_init_hw(struct adapter *adapter, u32 fw_params); 462 int t4_prep_adapter(struct adapter *adapter); 463 int t4_init_tp_params(struct adapter *adap); 464 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 465 int t4_port_init(struct port_info *p, int mbox, int pf, int vf); 466 int t4_reinit_adapter(struct adapter *adap); 467 void t4_fatal_err(struct adapter *adapter); 468 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 469 int filter_index, int enable); 470 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 471 int filter_index, int *enabled); 472 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 473 int start, int n, const u16 *rspq, unsigned int nrspq); 474 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 475 unsigned int flags); 476 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 477 unsigned int flags, unsigned int defq); 478 int t4_read_rss(struct adapter *adapter, u16 *entries); 479 void t4_read_rss_key(struct adapter *adapter, u32 *key); 480 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx); 481 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp); 482 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val); 483 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 484 u32 *vfl, u32 *vfh); 485 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 486 u32 vfl, u32 vfh); 487 u32 t4_read_rss_pf_map(struct adapter *adapter); 488 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap); 489 u32 t4_read_rss_pf_mask(struct adapter *adapter); 490 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask); 491 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 492 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 493 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 494 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 495 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 496 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 497 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 498 unsigned int *valp); 499 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 500 const unsigned int *valp); 501 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 502 unsigned int *valp); 503 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 504 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 505 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 506 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 507 int t4_mc_read(struct adapter *adap, int idx, u32 addr, 508 __be32 *data, u64 *parity); 509 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 510 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 511 __be32 *data); 512 513 const char *t4_get_port_type_description(enum fw_port_type port_type); 514 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 515 void t4_get_port_stats_offset(struct adapter *adap, int idx, 516 struct port_stats *stats, 517 struct port_stats *offset); 518 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 519 void t4_clr_port_stats(struct adapter *adap, int idx); 520 521 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 522 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 523 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 524 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 525 unsigned int *ipg); 526 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 527 unsigned int mask, unsigned int val); 528 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 529 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 530 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st); 531 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 532 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 533 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 534 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 535 struct tp_tcp_stats *v6); 536 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 537 struct tp_fcoe_stats *st); 538 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 539 const unsigned short *alpha, const unsigned short *beta); 540 541 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 542 543 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 544 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 545 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 546 unsigned int start, unsigned int n); 547 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 548 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map); 549 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 550 551 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 552 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 553 u64 mask0, u64 mask1, unsigned int crc, bool enable); 554 555 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 556 enum dev_master master, enum dev_state *state); 557 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 558 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 559 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 560 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 561 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 562 const u8 *fw_data, unsigned int size, int force); 563 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 564 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 565 unsigned int vf, unsigned int nparams, const u32 *params, 566 u32 *val); 567 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 568 unsigned int vf, unsigned int nparams, const u32 *params, 569 const u32 *val); 570 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 571 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 572 unsigned int rxqi, unsigned int rxq, unsigned int tc, 573 unsigned int vi, unsigned int cmask, unsigned int pmask, 574 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 575 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 576 unsigned int port, unsigned int pf, unsigned int vf, 577 unsigned int nmac, u8 *mac, u16 *rss_size, 578 unsigned int portfunc, unsigned int idstype); 579 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 580 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 581 u16 *rss_size); 582 int t4_free_vi(struct adapter *adap, unsigned int mbox, 583 unsigned int pf, unsigned int vf, 584 unsigned int viid); 585 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 586 int mtu, int promisc, int all_multi, int bcast, int vlanex, 587 bool sleep_ok); 588 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 589 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 590 u64 *hash, bool sleep_ok); 591 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 592 int idx, const u8 *addr, bool persist, bool add_smt); 593 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 594 bool ucast, u64 vec, bool sleep_ok); 595 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 596 bool rx_en, bool tx_en); 597 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 598 unsigned int nblinks); 599 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 600 unsigned int mmd, unsigned int reg, unsigned int *valp); 601 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 602 unsigned int mmd, unsigned int reg, unsigned int val); 603 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 604 int port, unsigned int devid, 605 unsigned int offset, unsigned int len, 606 u8 *buf); 607 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 608 int port, unsigned int devid, 609 unsigned int offset, unsigned int len, 610 u8 *buf); 611 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 612 unsigned int vf, unsigned int iqtype, unsigned int iqid, 613 unsigned int fl0id, unsigned int fl1id); 614 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 615 unsigned int vf, unsigned int eqid); 616 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 617 unsigned int vf, unsigned int eqid); 618 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 619 unsigned int vf, unsigned int eqid); 620 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 621 enum ctxt_type ctype, u32 *data); 622 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 623 u32 *data); 624 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 625 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 626 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 627 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 628 int sleep_ok); 629 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 630 int rateunit, int ratemode, int channel, int cl, 631 int minrate, int maxrate, int weight, int pktsize, 632 int sleep_ok); 633 #endif /* __CHELSIO_COMMON_H */ 634