1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef __CHELSIO_COMMON_H 31 #define __CHELSIO_COMMON_H 32 33 #include "t4_hw.h" 34 35 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 36 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 37 F_CPL_SWITCH | F_SGE | F_ULP_TX) 38 39 enum { 40 MAX_NPORTS = 4, /* max # of ports */ 41 SERNUM_LEN = 24, /* Serial # length */ 42 EC_LEN = 16, /* E/C length */ 43 ID_LEN = 16, /* ID length */ 44 PN_LEN = 16, /* Part Number length */ 45 MACADDR_LEN = 12, /* MAC Address length */ 46 }; 47 48 enum { 49 T4_REGMAP_SIZE = (160 * 1024), 50 T5_REGMAP_SIZE = (332 * 1024), 51 }; 52 53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 54 55 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 56 57 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 58 59 enum { 60 PAUSE_RX = 1 << 0, 61 PAUSE_TX = 1 << 1, 62 PAUSE_AUTONEG = 1 << 2 63 }; 64 65 enum { 66 FEC_RS = 1 << 0, 67 FEC_BASER_RS = 1 << 1, 68 FEC_RESERVED = 1 << 2, 69 }; 70 71 struct port_stats { 72 u64 tx_octets; /* total # of octets in good frames */ 73 u64 tx_frames; /* all good frames */ 74 u64 tx_bcast_frames; /* all broadcast frames */ 75 u64 tx_mcast_frames; /* all multicast frames */ 76 u64 tx_ucast_frames; /* all unicast frames */ 77 u64 tx_error_frames; /* all error frames */ 78 79 u64 tx_frames_64; /* # of Tx frames in a particular range */ 80 u64 tx_frames_65_127; 81 u64 tx_frames_128_255; 82 u64 tx_frames_256_511; 83 u64 tx_frames_512_1023; 84 u64 tx_frames_1024_1518; 85 u64 tx_frames_1519_max; 86 87 u64 tx_drop; /* # of dropped Tx frames */ 88 u64 tx_pause; /* # of transmitted pause frames */ 89 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 90 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 91 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 92 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 93 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 94 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 95 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 96 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 97 98 u64 rx_octets; /* total # of octets in good frames */ 99 u64 rx_frames; /* all good frames */ 100 u64 rx_bcast_frames; /* all broadcast frames */ 101 u64 rx_mcast_frames; /* all multicast frames */ 102 u64 rx_ucast_frames; /* all unicast frames */ 103 u64 rx_too_long; /* # of frames exceeding MTU */ 104 u64 rx_jabber; /* # of jabber frames */ 105 u64 rx_fcs_err; /* # of received frames with bad FCS */ 106 u64 rx_len_err; /* # of received frames with length error */ 107 u64 rx_symbol_err; /* symbol errors */ 108 u64 rx_runt; /* # of short frames */ 109 110 u64 rx_frames_64; /* # of Rx frames in a particular range */ 111 u64 rx_frames_65_127; 112 u64 rx_frames_128_255; 113 u64 rx_frames_256_511; 114 u64 rx_frames_512_1023; 115 u64 rx_frames_1024_1518; 116 u64 rx_frames_1519_max; 117 118 u64 rx_pause; /* # of received pause frames */ 119 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 120 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 121 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 122 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 123 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 124 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 125 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 126 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 127 128 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 129 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 130 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 131 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 132 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 133 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 134 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 135 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 136 }; 137 138 struct lb_port_stats { 139 u64 octets; 140 u64 frames; 141 u64 bcast_frames; 142 u64 mcast_frames; 143 u64 ucast_frames; 144 u64 error_frames; 145 146 u64 frames_64; 147 u64 frames_65_127; 148 u64 frames_128_255; 149 u64 frames_256_511; 150 u64 frames_512_1023; 151 u64 frames_1024_1518; 152 u64 frames_1519_max; 153 154 u64 drop; 155 156 u64 ovflow0; 157 u64 ovflow1; 158 u64 ovflow2; 159 u64 ovflow3; 160 u64 trunc0; 161 u64 trunc1; 162 u64 trunc2; 163 u64 trunc3; 164 }; 165 166 struct tp_tcp_stats { 167 u32 tcp_out_rsts; 168 u64 tcp_in_segs; 169 u64 tcp_out_segs; 170 u64 tcp_retrans_segs; 171 }; 172 173 struct tp_usm_stats { 174 u32 frames; 175 u32 drops; 176 u64 octets; 177 }; 178 179 struct tp_fcoe_stats { 180 u32 frames_ddp; 181 u32 frames_drop; 182 u64 octets_ddp; 183 }; 184 185 struct tp_err_stats { 186 u32 mac_in_errs[MAX_NCHAN]; 187 u32 hdr_in_errs[MAX_NCHAN]; 188 u32 tcp_in_errs[MAX_NCHAN]; 189 u32 tnl_cong_drops[MAX_NCHAN]; 190 u32 ofld_chan_drops[MAX_NCHAN]; 191 u32 tnl_tx_drops[MAX_NCHAN]; 192 u32 ofld_vlan_drops[MAX_NCHAN]; 193 u32 tcp6_in_errs[MAX_NCHAN]; 194 u32 ofld_no_neigh; 195 u32 ofld_cong_defer; 196 }; 197 198 struct tp_proxy_stats { 199 u32 proxy[MAX_NCHAN]; 200 }; 201 202 struct tp_cpl_stats { 203 u32 req[MAX_NCHAN]; 204 u32 rsp[MAX_NCHAN]; 205 }; 206 207 struct tp_rdma_stats { 208 u32 rqe_dfr_pkt; 209 u32 rqe_dfr_mod; 210 }; 211 212 struct sge_params { 213 int timer_val[SGE_NTIMERS]; /* final, scaled values */ 214 int counter_val[SGE_NCOUNTERS]; 215 int fl_starve_threshold; 216 int fl_starve_threshold2; 217 int page_shift; 218 int eq_s_qpp; 219 int iq_s_qpp; 220 int spg_len; 221 int pad_boundary; 222 int pack_boundary; 223 int fl_pktshift; 224 u32 sge_control; 225 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES]; 226 }; 227 228 struct tp_params { 229 unsigned int tre; /* log2 of core clocks per TP tick */ 230 unsigned int dack_re; /* DACK timer resolution */ 231 unsigned int la_mask; /* what events are recorded by TP LA */ 232 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 233 234 uint32_t vlan_pri_map; 235 uint32_t ingress_config; 236 __be16 err_vec_mask; 237 238 int8_t fcoe_shift; 239 int8_t port_shift; 240 int8_t vnic_shift; 241 int8_t vlan_shift; 242 int8_t tos_shift; 243 int8_t protocol_shift; 244 int8_t ethertype_shift; 245 int8_t macmatch_shift; 246 int8_t matchtype_shift; 247 int8_t frag_shift; 248 }; 249 250 struct vpd_params { 251 unsigned int cclk; 252 u8 ec[EC_LEN + 1]; 253 u8 sn[SERNUM_LEN + 1]; 254 u8 id[ID_LEN + 1]; 255 u8 pn[PN_LEN + 1]; 256 u8 na[MACADDR_LEN + 1]; 257 }; 258 259 struct pci_params { 260 unsigned int vpd_cap_addr; 261 unsigned int mps; 262 unsigned short speed; 263 unsigned short width; 264 }; 265 266 /* 267 * Firmware device log. 268 */ 269 struct devlog_params { 270 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 271 u32 start; /* start of log in firmware memory */ 272 u32 size; /* size of log */ 273 u32 addr; /* start address in flat addr space */ 274 }; 275 276 /* Stores chip specific parameters */ 277 struct chip_params { 278 u8 nchan; 279 u8 pm_stats_cnt; 280 u8 cng_ch_bits_log; /* congestion channel map bits width */ 281 u8 nsched_cls; 282 u8 cim_num_obq; 283 u16 mps_rplc_size; 284 u16 vfcount; 285 u32 sge_fl_db; 286 u16 mps_tcam_size; 287 }; 288 289 /* VF-only parameters. */ 290 291 /* 292 * Global Receive Side Scaling (RSS) parameters in host-native format. 293 */ 294 struct rss_params { 295 unsigned int mode; /* RSS mode */ 296 union { 297 struct { 298 u_int synmapen:1; /* SYN Map Enable */ 299 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ 300 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ 301 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ 302 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ 303 u_int ofdmapen:1; /* Offload Map Enable */ 304 u_int tnlmapen:1; /* Tunnel Map Enable */ 305 u_int tnlalllookup:1; /* Tunnel All Lookup */ 306 u_int hashtoeplitz:1; /* use Toeplitz hash */ 307 } basicvirtual; 308 } u; 309 }; 310 311 /* 312 * Maximum resources provisioned for a PCI VF. 313 */ 314 struct vf_resources { 315 unsigned int nvi; /* N virtual interfaces */ 316 unsigned int neq; /* N egress Qs */ 317 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 318 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 319 unsigned int niq; /* N ingress Qs */ 320 unsigned int tc; /* PCI-E traffic class */ 321 unsigned int pmask; /* port access rights mask */ 322 unsigned int nexactf; /* N exact MPS filters */ 323 unsigned int r_caps; /* read capabilities */ 324 unsigned int wx_caps; /* write/execute capabilities */ 325 }; 326 327 struct adapter_params { 328 struct sge_params sge; 329 struct tp_params tp; /* PF-only */ 330 struct vpd_params vpd; 331 struct pci_params pci; 332 struct devlog_params devlog; /* PF-only */ 333 struct rss_params rss; /* VF-only */ 334 struct vf_resources vfres; /* VF-only */ 335 336 unsigned int sf_size; /* serial flash size in bytes */ 337 unsigned int sf_nsec; /* # of flash sectors */ 338 339 unsigned int fw_vers; /* firmware version */ 340 unsigned int bs_vers; /* bootstrap version */ 341 unsigned int tp_vers; /* TP microcode version */ 342 unsigned int er_vers; /* expansion ROM version */ 343 unsigned int scfg_vers; /* Serial Configuration version */ 344 unsigned int vpd_vers; /* VPD version */ 345 346 unsigned short mtus[NMTUS]; 347 unsigned short a_wnd[NCCTRL_WIN]; 348 unsigned short b_wnd[NCCTRL_WIN]; 349 350 u_int ftid_min; 351 u_int ftid_max; 352 u_int etid_min; 353 u_int netids; 354 355 unsigned int cim_la_size; 356 357 uint8_t nports; /* # of ethernet ports */ 358 uint8_t portvec; 359 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 360 unsigned int rev:4; /* chip revision */ 361 unsigned int fpga:1; /* this is an FPGA */ 362 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 363 resources for TOE operation. */ 364 unsigned int bypass:1; /* this is a bypass card */ 365 unsigned int ethoffload:1; 366 367 unsigned int ofldq_wr_cred; 368 unsigned int eo_wr_cred; 369 370 unsigned int max_ordird_qp; 371 unsigned int max_ird_adapter; 372 }; 373 374 #define CHELSIO_T4 0x4 375 #define CHELSIO_T5 0x5 376 #define CHELSIO_T6 0x6 377 378 /* 379 * State needed to monitor the forward progress of SGE Ingress DMA activities 380 * and possible hangs. 381 */ 382 struct sge_idma_monitor_state { 383 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 384 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 385 unsigned int idma_state[2]; /* IDMA Hang detect state */ 386 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 387 unsigned int idma_warn[2]; /* time to warning in HZ */ 388 }; 389 390 struct trace_params { 391 u32 data[TRACE_LEN / 4]; 392 u32 mask[TRACE_LEN / 4]; 393 unsigned short snap_len; 394 unsigned short min_len; 395 unsigned char skip_ofst; 396 unsigned char skip_len; 397 unsigned char invert; 398 unsigned char port; 399 }; 400 401 struct link_config { 402 /* OS-specific code owns all the requested_* fields */ 403 unsigned char requested_aneg; /* link aneg user has requested */ 404 unsigned char requested_fc; /* flow control user has requested */ 405 unsigned char requested_fec; /* FEC user has requested */ 406 unsigned int requested_speed; /* speed user has requested */ 407 408 unsigned short supported; /* link capabilities */ 409 unsigned short advertising; /* advertised capabilities */ 410 unsigned short lp_advertising; /* peer advertised capabilities */ 411 unsigned int speed; /* actual link speed */ 412 unsigned char fc; /* actual link flow control */ 413 unsigned char fec; /* actual FEC */ 414 unsigned char link_ok; /* link up? */ 415 unsigned char link_down_rc; /* link down reason */ 416 }; 417 418 #include "adapter.h" 419 420 #ifndef PCI_VENDOR_ID_CHELSIO 421 # define PCI_VENDOR_ID_CHELSIO 0x1425 422 #endif 423 424 #define for_each_port(adapter, iter) \ 425 for (iter = 0; iter < (adapter)->params.nports; ++iter) 426 427 static inline int is_ftid(const struct adapter *sc, u_int tid) 428 { 429 430 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max); 431 } 432 433 static inline int is_etid(const struct adapter *sc, u_int tid) 434 { 435 436 return (tid >= sc->params.etid_min); 437 } 438 439 static inline int is_offload(const struct adapter *adap) 440 { 441 return adap->params.offload; 442 } 443 444 static inline int is_ethoffload(const struct adapter *adap) 445 { 446 return adap->params.ethoffload; 447 } 448 449 static inline int chip_id(struct adapter *adap) 450 { 451 return adap->params.chipid; 452 } 453 454 static inline int chip_rev(struct adapter *adap) 455 { 456 return adap->params.rev; 457 } 458 459 static inline int is_t4(struct adapter *adap) 460 { 461 return adap->params.chipid == CHELSIO_T4; 462 } 463 464 static inline int is_t5(struct adapter *adap) 465 { 466 return adap->params.chipid == CHELSIO_T5; 467 } 468 469 static inline int is_t6(struct adapter *adap) 470 { 471 return adap->params.chipid == CHELSIO_T6; 472 } 473 474 static inline int is_fpga(struct adapter *adap) 475 { 476 return adap->params.fpga; 477 } 478 479 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 480 { 481 return adap->params.vpd.cclk / 1000; 482 } 483 484 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 485 unsigned int us) 486 { 487 return (us * adap->params.vpd.cclk) / 1000; 488 } 489 490 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 491 unsigned int ticks) 492 { 493 /* add Core Clock / 2 to round ticks to nearest uS */ 494 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 495 adapter->params.vpd.cclk); 496 } 497 498 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 499 unsigned int ticks) 500 { 501 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 502 } 503 504 static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us) 505 { 506 507 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre); 508 } 509 510 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 511 512 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 513 int size, void *rpl, bool sleep_ok, int timeout); 514 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 515 void *rpl, bool sleep_ok); 516 517 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 518 const void *cmd, int size, void *rpl, 519 int timeout) 520 { 521 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 522 timeout); 523 } 524 525 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 526 int size, void *rpl) 527 { 528 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 529 } 530 531 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 532 int size, void *rpl) 533 { 534 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 535 } 536 537 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 538 unsigned int data_reg, u32 *vals, unsigned int nregs, 539 unsigned int start_idx); 540 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 541 unsigned int data_reg, const u32 *vals, 542 unsigned int nregs, unsigned int start_idx); 543 544 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 545 546 struct fw_filter_wr; 547 548 void t4_intr_enable(struct adapter *adapter); 549 void t4_intr_disable(struct adapter *adapter); 550 void t4_intr_clear(struct adapter *adapter); 551 int t4_slow_intr_handler(struct adapter *adapter); 552 553 int t4_hash_mac_addr(const u8 *addr); 554 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 555 struct link_config *lc); 556 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 557 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 558 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 559 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 560 int t4_seeprom_wp(struct adapter *adapter, int enable); 561 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 562 u32 *data, int byte_oriented); 563 int t4_write_flash(struct adapter *adapter, unsigned int addr, 564 unsigned int n, const u8 *data, int byte_oriented); 565 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 566 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 567 int t5_fw_init_extern_mem(struct adapter *adap); 568 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 569 int t4_load_boot(struct adapter *adap, u8 *boot_data, 570 unsigned int boot_addr, unsigned int size); 571 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 572 int t4_flash_cfg_addr(struct adapter *adapter); 573 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 574 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 575 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 576 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 577 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 578 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 579 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 580 int t4_get_version_info(struct adapter *adapter); 581 int t4_init_hw(struct adapter *adapter, u32 fw_params); 582 const struct chip_params *t4_get_chip_params(int chipid); 583 int t4_prep_adapter(struct adapter *adapter, u8 *buf); 584 int t4_shutdown_adapter(struct adapter *adapter); 585 int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 586 int t4_init_sge_params(struct adapter *adapter); 587 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 588 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 589 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); 590 void t4_fatal_err(struct adapter *adapter); 591 void t4_db_full(struct adapter *adapter); 592 void t4_db_dropped(struct adapter *adapter); 593 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 594 int filter_index, int enable); 595 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 596 int filter_index, int *enabled); 597 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 598 int start, int n, const u16 *rspq, unsigned int nrspq); 599 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 600 unsigned int flags); 601 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 602 unsigned int flags, unsigned int defq, unsigned int skeyidx, 603 unsigned int skey); 604 int t4_read_rss(struct adapter *adapter, u16 *entries); 605 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 606 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 607 bool sleep_ok); 608 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 609 u32 *valp, bool sleep_ok); 610 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 611 u32 val, bool sleep_ok); 612 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 613 u32 *vfl, u32 *vfh, bool sleep_ok); 614 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 615 u32 vfl, u32 vfh, bool sleep_ok); 616 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 617 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok); 618 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 619 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok); 620 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 621 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 622 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 623 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 624 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 625 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 626 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 627 unsigned int *valp); 628 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 629 const unsigned int *valp); 630 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 631 unsigned int *valp); 632 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 633 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 634 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 635 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 636 int t4_get_flash_params(struct adapter *adapter); 637 638 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 639 int t4_mc_read(struct adapter *adap, int idx, u32 addr, 640 __be32 *data, u64 *parity); 641 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 642 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 643 __be32 *data); 644 void t4_idma_monitor_init(struct adapter *adapter, 645 struct sge_idma_monitor_state *idma); 646 void t4_idma_monitor(struct adapter *adapter, 647 struct sge_idma_monitor_state *idma, 648 int hz, int ticks); 649 650 unsigned int t4_get_regs_len(struct adapter *adapter); 651 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); 652 653 const char *t4_get_port_type_description(enum fw_port_type port_type); 654 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 655 void t4_get_port_stats_offset(struct adapter *adap, int idx, 656 struct port_stats *stats, 657 struct port_stats *offset); 658 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 659 void t4_clr_port_stats(struct adapter *adap, int idx); 660 661 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 662 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 663 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 664 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 665 unsigned int *ipg, bool sleep_ok); 666 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 667 unsigned int mask, unsigned int val); 668 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 669 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 670 bool sleep_ok); 671 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 672 bool sleep_ok); 673 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 674 bool sleep_ok); 675 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 676 bool sleep_ok); 677 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 678 bool sleep_ok); 679 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 680 struct tp_tcp_stats *v6, bool sleep_ok); 681 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 682 struct tp_fcoe_stats *st, bool sleep_ok); 683 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 684 const unsigned short *alpha, const unsigned short *beta); 685 686 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 687 688 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 689 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 690 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 691 unsigned int start, unsigned int n); 692 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 693 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 694 bool sleep_ok); 695 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 696 697 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 698 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 699 u64 mask0, u64 mask1, unsigned int crc, bool enable); 700 701 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 702 enum dev_master master, enum dev_state *state); 703 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 704 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 705 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 706 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 707 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 708 const u8 *fw_data, unsigned int size, int force); 709 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data, 710 unsigned int size); 711 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 712 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 713 unsigned int vf, unsigned int nparams, const u32 *params, 714 u32 *val); 715 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 716 unsigned int vf, unsigned int nparams, const u32 *params, 717 u32 *val, int rw); 718 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 719 unsigned int pf, unsigned int vf, 720 unsigned int nparams, const u32 *params, 721 const u32 *val, int timeout); 722 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 723 unsigned int vf, unsigned int nparams, const u32 *params, 724 const u32 *val); 725 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 726 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 727 unsigned int rxqi, unsigned int rxq, unsigned int tc, 728 unsigned int vi, unsigned int cmask, unsigned int pmask, 729 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 730 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 731 unsigned int port, unsigned int pf, unsigned int vf, 732 unsigned int nmac, u8 *mac, u16 *rss_size, 733 unsigned int portfunc, unsigned int idstype); 734 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 735 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 736 u16 *rss_size); 737 int t4_free_vi(struct adapter *adap, unsigned int mbox, 738 unsigned int pf, unsigned int vf, 739 unsigned int viid); 740 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 741 int mtu, int promisc, int all_multi, int bcast, int vlanex, 742 bool sleep_ok); 743 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 744 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 745 u64 *hash, bool sleep_ok); 746 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 747 int idx, const u8 *addr, bool persist, bool add_smt); 748 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 749 bool ucast, u64 vec, bool sleep_ok); 750 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 751 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 752 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 753 bool rx_en, bool tx_en); 754 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 755 unsigned int nblinks); 756 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 757 unsigned int mmd, unsigned int reg, unsigned int *valp); 758 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 759 unsigned int mmd, unsigned int reg, unsigned int val); 760 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 761 int port, unsigned int devid, 762 unsigned int offset, unsigned int len, 763 u8 *buf); 764 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 765 int port, unsigned int devid, 766 unsigned int offset, unsigned int len, 767 u8 *buf); 768 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 769 unsigned int vf, unsigned int iqtype, unsigned int iqid, 770 unsigned int fl0id, unsigned int fl1id); 771 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 772 unsigned int vf, unsigned int iqtype, unsigned int iqid, 773 unsigned int fl0id, unsigned int fl1id); 774 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 775 unsigned int vf, unsigned int eqid); 776 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 777 unsigned int vf, unsigned int eqid); 778 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 779 unsigned int vf, unsigned int eqid); 780 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 781 enum ctxt_type ctype, u32 *data); 782 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 783 u32 *data); 784 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 785 const char *t4_link_down_rc_str(unsigned char link_down_rc); 786 int t4_update_port_info(struct port_info *pi); 787 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 788 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 789 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 790 int sleep_ok); 791 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 792 int rateunit, int ratemode, int channel, int cl, 793 int minrate, int maxrate, int weight, int pktsize, 794 int sleep_ok); 795 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 796 unsigned int maxrate, int sleep_ok); 797 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 798 int weight, int sleep_ok); 799 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 800 int mode, unsigned int maxrate, int pktsize, 801 int sleep_ok); 802 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 803 unsigned int pf, unsigned int vf, 804 unsigned int timeout, unsigned int action); 805 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 806 int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 807 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 808 809 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 810 u32 start_index, bool sleep_ok); 811 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 812 u32 start_index, bool sleep_ok); 813 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 814 u32 start_index, bool sleep_ok); 815 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 816 u32 start_index, bool sleep_ok); 817 818 static inline int t4vf_query_params(struct adapter *adapter, 819 unsigned int nparams, const u32 *params, 820 u32 *vals) 821 { 822 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals); 823 } 824 825 static inline int t4vf_set_params(struct adapter *adapter, 826 unsigned int nparams, const u32 *params, 827 const u32 *vals) 828 { 829 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals); 830 } 831 832 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd, 833 int size, void *rpl) 834 { 835 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl); 836 } 837 838 int t4vf_wait_dev_ready(struct adapter *adapter); 839 int t4vf_fw_reset(struct adapter *adapter); 840 int t4vf_get_sge_params(struct adapter *adapter); 841 int t4vf_get_rss_glb_config(struct adapter *adapter); 842 int t4vf_get_vfres(struct adapter *adapter); 843 int t4vf_prep_adapter(struct adapter *adapter); 844 845 #endif /* __CHELSIO_COMMON_H */ 846