1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef __CHELSIO_COMMON_H 31 #define __CHELSIO_COMMON_H 32 33 #include "t4_hw.h" 34 35 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 36 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 37 F_CPL_SWITCH | F_SGE | F_ULP_TX) 38 39 enum { 40 MAX_NPORTS = 4, /* max # of ports */ 41 SERNUM_LEN = 24, /* Serial # length */ 42 EC_LEN = 16, /* E/C length */ 43 ID_LEN = 16, /* ID length */ 44 PN_LEN = 16, /* Part Number length */ 45 MACADDR_LEN = 12, /* MAC Address length */ 46 }; 47 48 enum { 49 T4_REGMAP_SIZE = (160 * 1024), 50 T5_REGMAP_SIZE = (332 * 1024), 51 }; 52 53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 54 55 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 56 57 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 58 59 enum { 60 PAUSE_RX = 1 << 0, 61 PAUSE_TX = 1 << 1, 62 PAUSE_AUTONEG = 1 << 2 63 }; 64 65 enum { 66 FEC_RS = 1 << 0, 67 FEC_BASER_RS = 1 << 1, 68 FEC_RESERVED = 1 << 2, 69 }; 70 71 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 72 73 struct port_stats { 74 u64 tx_octets; /* total # of octets in good frames */ 75 u64 tx_frames; /* all good frames */ 76 u64 tx_bcast_frames; /* all broadcast frames */ 77 u64 tx_mcast_frames; /* all multicast frames */ 78 u64 tx_ucast_frames; /* all unicast frames */ 79 u64 tx_error_frames; /* all error frames */ 80 81 u64 tx_frames_64; /* # of Tx frames in a particular range */ 82 u64 tx_frames_65_127; 83 u64 tx_frames_128_255; 84 u64 tx_frames_256_511; 85 u64 tx_frames_512_1023; 86 u64 tx_frames_1024_1518; 87 u64 tx_frames_1519_max; 88 89 u64 tx_drop; /* # of dropped Tx frames */ 90 u64 tx_pause; /* # of transmitted pause frames */ 91 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 92 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 93 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 94 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 95 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 96 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 97 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 98 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 99 100 u64 rx_octets; /* total # of octets in good frames */ 101 u64 rx_frames; /* all good frames */ 102 u64 rx_bcast_frames; /* all broadcast frames */ 103 u64 rx_mcast_frames; /* all multicast frames */ 104 u64 rx_ucast_frames; /* all unicast frames */ 105 u64 rx_too_long; /* # of frames exceeding MTU */ 106 u64 rx_jabber; /* # of jabber frames */ 107 u64 rx_fcs_err; /* # of received frames with bad FCS */ 108 u64 rx_len_err; /* # of received frames with length error */ 109 u64 rx_symbol_err; /* symbol errors */ 110 u64 rx_runt; /* # of short frames */ 111 112 u64 rx_frames_64; /* # of Rx frames in a particular range */ 113 u64 rx_frames_65_127; 114 u64 rx_frames_128_255; 115 u64 rx_frames_256_511; 116 u64 rx_frames_512_1023; 117 u64 rx_frames_1024_1518; 118 u64 rx_frames_1519_max; 119 120 u64 rx_pause; /* # of received pause frames */ 121 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 122 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 123 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 124 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 125 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 126 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 127 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 128 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 129 130 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 131 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 132 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 133 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 134 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 135 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 136 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 137 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 138 }; 139 140 struct lb_port_stats { 141 u64 octets; 142 u64 frames; 143 u64 bcast_frames; 144 u64 mcast_frames; 145 u64 ucast_frames; 146 u64 error_frames; 147 148 u64 frames_64; 149 u64 frames_65_127; 150 u64 frames_128_255; 151 u64 frames_256_511; 152 u64 frames_512_1023; 153 u64 frames_1024_1518; 154 u64 frames_1519_max; 155 156 u64 drop; 157 158 u64 ovflow0; 159 u64 ovflow1; 160 u64 ovflow2; 161 u64 ovflow3; 162 u64 trunc0; 163 u64 trunc1; 164 u64 trunc2; 165 u64 trunc3; 166 }; 167 168 struct tp_tcp_stats { 169 u32 tcp_out_rsts; 170 u64 tcp_in_segs; 171 u64 tcp_out_segs; 172 u64 tcp_retrans_segs; 173 }; 174 175 struct tp_usm_stats { 176 u32 frames; 177 u32 drops; 178 u64 octets; 179 }; 180 181 struct tp_fcoe_stats { 182 u32 frames_ddp; 183 u32 frames_drop; 184 u64 octets_ddp; 185 }; 186 187 struct tp_err_stats { 188 u32 mac_in_errs[MAX_NCHAN]; 189 u32 hdr_in_errs[MAX_NCHAN]; 190 u32 tcp_in_errs[MAX_NCHAN]; 191 u32 tnl_cong_drops[MAX_NCHAN]; 192 u32 ofld_chan_drops[MAX_NCHAN]; 193 u32 tnl_tx_drops[MAX_NCHAN]; 194 u32 ofld_vlan_drops[MAX_NCHAN]; 195 u32 tcp6_in_errs[MAX_NCHAN]; 196 u32 ofld_no_neigh; 197 u32 ofld_cong_defer; 198 }; 199 200 struct tp_proxy_stats { 201 u32 proxy[MAX_NCHAN]; 202 }; 203 204 struct tp_cpl_stats { 205 u32 req[MAX_NCHAN]; 206 u32 rsp[MAX_NCHAN]; 207 }; 208 209 struct tp_rdma_stats { 210 u32 rqe_dfr_pkt; 211 u32 rqe_dfr_mod; 212 }; 213 214 struct sge_params { 215 int timer_val[SGE_NTIMERS]; /* final, scaled values */ 216 int counter_val[SGE_NCOUNTERS]; 217 int fl_starve_threshold; 218 int fl_starve_threshold2; 219 int page_shift; 220 int eq_s_qpp; 221 int iq_s_qpp; 222 int spg_len; 223 int pad_boundary; 224 int pack_boundary; 225 int fl_pktshift; 226 u32 sge_control; 227 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES]; 228 }; 229 230 struct tp_params { 231 unsigned int tre; /* log2 of core clocks per TP tick */ 232 unsigned int dack_re; /* DACK timer resolution */ 233 unsigned int la_mask; /* what events are recorded by TP LA */ 234 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 235 236 uint32_t vlan_pri_map; 237 uint32_t ingress_config; 238 __be16 err_vec_mask; 239 240 int8_t fcoe_shift; 241 int8_t port_shift; 242 int8_t vnic_shift; 243 int8_t vlan_shift; 244 int8_t tos_shift; 245 int8_t protocol_shift; 246 int8_t ethertype_shift; 247 int8_t macmatch_shift; 248 int8_t matchtype_shift; 249 int8_t frag_shift; 250 }; 251 252 struct vpd_params { 253 unsigned int cclk; 254 u8 ec[EC_LEN + 1]; 255 u8 sn[SERNUM_LEN + 1]; 256 u8 id[ID_LEN + 1]; 257 u8 pn[PN_LEN + 1]; 258 u8 na[MACADDR_LEN + 1]; 259 }; 260 261 struct pci_params { 262 unsigned int vpd_cap_addr; 263 unsigned int mps; 264 unsigned short speed; 265 unsigned short width; 266 }; 267 268 /* 269 * Firmware device log. 270 */ 271 struct devlog_params { 272 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 273 u32 start; /* start of log in firmware memory */ 274 u32 size; /* size of log */ 275 u32 addr; /* start address in flat addr space */ 276 }; 277 278 /* Stores chip specific parameters */ 279 struct chip_params { 280 u8 nchan; 281 u8 pm_stats_cnt; 282 u8 cng_ch_bits_log; /* congestion channel map bits width */ 283 u8 nsched_cls; 284 u8 cim_num_obq; 285 u16 mps_rplc_size; 286 u16 vfcount; 287 u32 sge_fl_db; 288 u16 mps_tcam_size; 289 }; 290 291 /* VF-only parameters. */ 292 293 /* 294 * Global Receive Side Scaling (RSS) parameters in host-native format. 295 */ 296 struct rss_params { 297 unsigned int mode; /* RSS mode */ 298 union { 299 struct { 300 u_int synmapen:1; /* SYN Map Enable */ 301 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ 302 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ 303 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ 304 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ 305 u_int ofdmapen:1; /* Offload Map Enable */ 306 u_int tnlmapen:1; /* Tunnel Map Enable */ 307 u_int tnlalllookup:1; /* Tunnel All Lookup */ 308 u_int hashtoeplitz:1; /* use Toeplitz hash */ 309 } basicvirtual; 310 } u; 311 }; 312 313 /* 314 * Maximum resources provisioned for a PCI VF. 315 */ 316 struct vf_resources { 317 unsigned int nvi; /* N virtual interfaces */ 318 unsigned int neq; /* N egress Qs */ 319 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 320 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 321 unsigned int niq; /* N ingress Qs */ 322 unsigned int tc; /* PCI-E traffic class */ 323 unsigned int pmask; /* port access rights mask */ 324 unsigned int nexactf; /* N exact MPS filters */ 325 unsigned int r_caps; /* read capabilities */ 326 unsigned int wx_caps; /* write/execute capabilities */ 327 }; 328 329 struct adapter_params { 330 struct sge_params sge; 331 struct tp_params tp; /* PF-only */ 332 struct vpd_params vpd; 333 struct pci_params pci; 334 struct devlog_params devlog; /* PF-only */ 335 struct rss_params rss; /* VF-only */ 336 struct vf_resources vfres; /* VF-only */ 337 unsigned int core_vdd; 338 339 unsigned int sf_size; /* serial flash size in bytes */ 340 unsigned int sf_nsec; /* # of flash sectors */ 341 342 unsigned int fw_vers; /* firmware version */ 343 unsigned int bs_vers; /* bootstrap version */ 344 unsigned int tp_vers; /* TP microcode version */ 345 unsigned int er_vers; /* expansion ROM version */ 346 unsigned int scfg_vers; /* Serial Configuration version */ 347 unsigned int vpd_vers; /* VPD version */ 348 349 unsigned short mtus[NMTUS]; 350 unsigned short a_wnd[NCCTRL_WIN]; 351 unsigned short b_wnd[NCCTRL_WIN]; 352 353 u_int ftid_min; 354 u_int ftid_max; 355 u_int etid_min; 356 u_int netids; 357 358 unsigned int cim_la_size; 359 360 uint8_t nports; /* # of ethernet ports */ 361 uint8_t portvec; 362 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 363 unsigned int rev:4; /* chip revision */ 364 unsigned int fpga:1; /* this is an FPGA */ 365 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 366 resources for TOE operation. */ 367 unsigned int bypass:1; /* this is a bypass card */ 368 unsigned int ethoffload:1; 369 370 unsigned int ofldq_wr_cred; 371 unsigned int eo_wr_cred; 372 373 unsigned int max_ordird_qp; 374 unsigned int max_ird_adapter; 375 376 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */ 377 378 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 379 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 380 }; 381 382 #define CHELSIO_T4 0x4 383 #define CHELSIO_T5 0x5 384 #define CHELSIO_T6 0x6 385 386 /* 387 * State needed to monitor the forward progress of SGE Ingress DMA activities 388 * and possible hangs. 389 */ 390 struct sge_idma_monitor_state { 391 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 392 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 393 unsigned int idma_state[2]; /* IDMA Hang detect state */ 394 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 395 unsigned int idma_warn[2]; /* time to warning in HZ */ 396 }; 397 398 struct trace_params { 399 u32 data[TRACE_LEN / 4]; 400 u32 mask[TRACE_LEN / 4]; 401 unsigned short snap_len; 402 unsigned short min_len; 403 unsigned char skip_ofst; 404 unsigned char skip_len; 405 unsigned char invert; 406 unsigned char port; 407 }; 408 409 struct link_config { 410 /* OS-specific code owns all the requested_* fields */ 411 unsigned char requested_aneg; /* link aneg user has requested */ 412 unsigned char requested_fc; /* flow control user has requested */ 413 unsigned char requested_fec; /* FEC user has requested */ 414 unsigned int requested_speed; /* speed user has requested */ 415 416 unsigned short supported; /* link capabilities */ 417 unsigned short advertising; /* advertised capabilities */ 418 unsigned short lp_advertising; /* peer advertised capabilities */ 419 unsigned int speed; /* actual link speed */ 420 unsigned char fc; /* actual link flow control */ 421 unsigned char fec; /* actual FEC */ 422 unsigned char link_ok; /* link up? */ 423 unsigned char link_down_rc; /* link down reason */ 424 }; 425 426 #include "adapter.h" 427 428 #ifndef PCI_VENDOR_ID_CHELSIO 429 # define PCI_VENDOR_ID_CHELSIO 0x1425 430 #endif 431 432 #define for_each_port(adapter, iter) \ 433 for (iter = 0; iter < (adapter)->params.nports; ++iter) 434 435 static inline int is_ftid(const struct adapter *sc, u_int tid) 436 { 437 438 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max); 439 } 440 441 static inline int is_etid(const struct adapter *sc, u_int tid) 442 { 443 444 return (tid >= sc->params.etid_min); 445 } 446 447 static inline int is_offload(const struct adapter *adap) 448 { 449 return adap->params.offload; 450 } 451 452 static inline int is_ethoffload(const struct adapter *adap) 453 { 454 return adap->params.ethoffload; 455 } 456 457 static inline int chip_id(struct adapter *adap) 458 { 459 return adap->params.chipid; 460 } 461 462 static inline int chip_rev(struct adapter *adap) 463 { 464 return adap->params.rev; 465 } 466 467 static inline int is_t4(struct adapter *adap) 468 { 469 return adap->params.chipid == CHELSIO_T4; 470 } 471 472 static inline int is_t5(struct adapter *adap) 473 { 474 return adap->params.chipid == CHELSIO_T5; 475 } 476 477 static inline int is_t6(struct adapter *adap) 478 { 479 return adap->params.chipid == CHELSIO_T6; 480 } 481 482 static inline int is_fpga(struct adapter *adap) 483 { 484 return adap->params.fpga; 485 } 486 487 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 488 { 489 return adap->params.vpd.cclk / 1000; 490 } 491 492 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 493 unsigned int us) 494 { 495 return (us * adap->params.vpd.cclk) / 1000; 496 } 497 498 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 499 unsigned int ticks) 500 { 501 /* add Core Clock / 2 to round ticks to nearest uS */ 502 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 503 adapter->params.vpd.cclk); 504 } 505 506 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 507 unsigned int ticks) 508 { 509 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 510 } 511 512 static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us) 513 { 514 515 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre); 516 } 517 518 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 519 520 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 521 int size, void *rpl, bool sleep_ok, int timeout); 522 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 523 void *rpl, bool sleep_ok); 524 525 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 526 const void *cmd, int size, void *rpl, 527 int timeout) 528 { 529 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 530 timeout); 531 } 532 533 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 534 int size, void *rpl) 535 { 536 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 537 } 538 539 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 540 int size, void *rpl) 541 { 542 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 543 } 544 545 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 546 unsigned int data_reg, u32 *vals, unsigned int nregs, 547 unsigned int start_idx); 548 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 549 unsigned int data_reg, const u32 *vals, 550 unsigned int nregs, unsigned int start_idx); 551 552 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 553 554 struct fw_filter_wr; 555 556 void t4_intr_enable(struct adapter *adapter); 557 void t4_intr_disable(struct adapter *adapter); 558 void t4_intr_clear(struct adapter *adapter); 559 int t4_slow_intr_handler(struct adapter *adapter); 560 561 int t4_hash_mac_addr(const u8 *addr); 562 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 563 struct link_config *lc); 564 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 565 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 566 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 567 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 568 int t4_seeprom_wp(struct adapter *adapter, int enable); 569 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 570 u32 *data, int byte_oriented); 571 int t4_write_flash(struct adapter *adapter, unsigned int addr, 572 unsigned int n, const u8 *data, int byte_oriented); 573 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 574 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 575 int t5_fw_init_extern_mem(struct adapter *adap); 576 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 577 int t4_load_boot(struct adapter *adap, u8 *boot_data, 578 unsigned int boot_addr, unsigned int size); 579 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 580 int t4_flash_cfg_addr(struct adapter *adapter); 581 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 582 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 583 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 584 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 585 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 586 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 587 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 588 int t4_get_version_info(struct adapter *adapter); 589 int t4_init_hw(struct adapter *adapter, u32 fw_params); 590 const struct chip_params *t4_get_chip_params(int chipid); 591 int t4_prep_adapter(struct adapter *adapter, u8 *buf); 592 int t4_shutdown_adapter(struct adapter *adapter); 593 int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 594 int t4_init_sge_params(struct adapter *adapter); 595 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 596 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 597 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); 598 void t4_fatal_err(struct adapter *adapter); 599 void t4_db_full(struct adapter *adapter); 600 void t4_db_dropped(struct adapter *adapter); 601 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 602 int filter_index, int enable); 603 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 604 int filter_index, int *enabled); 605 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 606 int start, int n, const u16 *rspq, unsigned int nrspq); 607 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 608 unsigned int flags); 609 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 610 unsigned int flags, unsigned int defq, unsigned int skeyidx, 611 unsigned int skey); 612 int t4_read_rss(struct adapter *adapter, u16 *entries); 613 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 614 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 615 bool sleep_ok); 616 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 617 u32 *valp, bool sleep_ok); 618 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 619 u32 val, bool sleep_ok); 620 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 621 u32 *vfl, u32 *vfh, bool sleep_ok); 622 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 623 u32 vfl, u32 vfh, bool sleep_ok); 624 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 625 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok); 626 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 627 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok); 628 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 629 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 630 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 631 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 632 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 633 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 634 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 635 unsigned int *valp); 636 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 637 const unsigned int *valp); 638 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 639 unsigned int *valp); 640 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 641 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 642 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 643 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 644 int t4_get_flash_params(struct adapter *adapter); 645 646 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 647 int t4_mc_read(struct adapter *adap, int idx, u32 addr, 648 __be32 *data, u64 *parity); 649 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 650 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 651 __be32 *data); 652 void t4_idma_monitor_init(struct adapter *adapter, 653 struct sge_idma_monitor_state *idma); 654 void t4_idma_monitor(struct adapter *adapter, 655 struct sge_idma_monitor_state *idma, 656 int hz, int ticks); 657 658 unsigned int t4_get_regs_len(struct adapter *adapter); 659 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); 660 661 const char *t4_get_port_type_description(enum fw_port_type port_type); 662 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 663 void t4_get_port_stats_offset(struct adapter *adap, int idx, 664 struct port_stats *stats, 665 struct port_stats *offset); 666 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 667 void t4_clr_port_stats(struct adapter *adap, int idx); 668 669 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 670 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 671 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 672 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 673 unsigned int *ipg, bool sleep_ok); 674 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 675 unsigned int mask, unsigned int val); 676 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 677 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 678 bool sleep_ok); 679 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 680 bool sleep_ok); 681 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 682 bool sleep_ok); 683 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 684 bool sleep_ok); 685 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 686 bool sleep_ok); 687 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 688 struct tp_tcp_stats *v6, bool sleep_ok); 689 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 690 struct tp_fcoe_stats *st, bool sleep_ok); 691 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 692 const unsigned short *alpha, const unsigned short *beta); 693 694 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 695 696 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 697 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 698 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 699 unsigned int start, unsigned int n); 700 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 701 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 702 bool sleep_ok); 703 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 704 705 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 706 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 707 u64 mask0, u64 mask1, unsigned int crc, bool enable); 708 709 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 710 enum dev_master master, enum dev_state *state); 711 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 712 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 713 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 714 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 715 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 716 const u8 *fw_data, unsigned int size, int force); 717 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data, 718 unsigned int size); 719 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 720 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 721 unsigned int vf, unsigned int nparams, const u32 *params, 722 u32 *val); 723 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 724 unsigned int vf, unsigned int nparams, const u32 *params, 725 u32 *val, int rw); 726 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 727 unsigned int pf, unsigned int vf, 728 unsigned int nparams, const u32 *params, 729 const u32 *val, int timeout); 730 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 731 unsigned int vf, unsigned int nparams, const u32 *params, 732 const u32 *val); 733 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 734 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 735 unsigned int rxqi, unsigned int rxq, unsigned int tc, 736 unsigned int vi, unsigned int cmask, unsigned int pmask, 737 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 738 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 739 unsigned int port, unsigned int pf, unsigned int vf, 740 unsigned int nmac, u8 *mac, u16 *rss_size, 741 unsigned int portfunc, unsigned int idstype); 742 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 743 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 744 u16 *rss_size); 745 int t4_free_vi(struct adapter *adap, unsigned int mbox, 746 unsigned int pf, unsigned int vf, 747 unsigned int viid); 748 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 749 int mtu, int promisc, int all_multi, int bcast, int vlanex, 750 bool sleep_ok); 751 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 752 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 753 u64 *hash, bool sleep_ok); 754 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 755 int idx, const u8 *addr, bool persist, bool add_smt); 756 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 757 bool ucast, u64 vec, bool sleep_ok); 758 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 759 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 760 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 761 bool rx_en, bool tx_en); 762 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 763 unsigned int nblinks); 764 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 765 unsigned int mmd, unsigned int reg, unsigned int *valp); 766 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 767 unsigned int mmd, unsigned int reg, unsigned int val); 768 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 769 int port, unsigned int devid, 770 unsigned int offset, unsigned int len, 771 u8 *buf); 772 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 773 int port, unsigned int devid, 774 unsigned int offset, unsigned int len, 775 u8 *buf); 776 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 777 unsigned int vf, unsigned int iqtype, unsigned int iqid, 778 unsigned int fl0id, unsigned int fl1id); 779 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 780 unsigned int vf, unsigned int iqtype, unsigned int iqid, 781 unsigned int fl0id, unsigned int fl1id); 782 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 783 unsigned int vf, unsigned int eqid); 784 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 785 unsigned int vf, unsigned int eqid); 786 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 787 unsigned int vf, unsigned int eqid); 788 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 789 enum ctxt_type ctype, u32 *data); 790 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 791 u32 *data); 792 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 793 const char *t4_link_down_rc_str(unsigned char link_down_rc); 794 int t4_update_port_info(struct port_info *pi); 795 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 796 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 797 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 798 int sleep_ok); 799 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 800 int rateunit, int ratemode, int channel, int cl, 801 int minrate, int maxrate, int weight, int pktsize, 802 int sleep_ok); 803 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 804 unsigned int maxrate, int sleep_ok); 805 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 806 int weight, int sleep_ok); 807 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 808 int mode, unsigned int maxrate, int pktsize, 809 int sleep_ok); 810 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 811 unsigned int pf, unsigned int vf, 812 unsigned int timeout, unsigned int action); 813 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 814 int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 815 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 816 817 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 818 u32 start_index, bool sleep_ok); 819 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 820 u32 start_index, bool sleep_ok); 821 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 822 u32 start_index, bool sleep_ok); 823 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 824 u32 start_index, bool sleep_ok); 825 826 static inline int t4vf_query_params(struct adapter *adapter, 827 unsigned int nparams, const u32 *params, 828 u32 *vals) 829 { 830 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals); 831 } 832 833 static inline int t4vf_set_params(struct adapter *adapter, 834 unsigned int nparams, const u32 *params, 835 const u32 *vals) 836 { 837 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals); 838 } 839 840 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd, 841 int size, void *rpl) 842 { 843 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl); 844 } 845 846 int t4vf_wait_dev_ready(struct adapter *adapter); 847 int t4vf_fw_reset(struct adapter *adapter); 848 int t4vf_get_sge_params(struct adapter *adapter); 849 int t4vf_get_rss_glb_config(struct adapter *adapter); 850 int t4vf_get_vfres(struct adapter *adapter); 851 int t4vf_prep_adapter(struct adapter *adapter); 852 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 853 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset, 854 unsigned int *pbar2_qid); 855 856 #endif /* __CHELSIO_COMMON_H */ 857