1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32 #ifndef __CHELSIO_COMMON_H 33 #define __CHELSIO_COMMON_H 34 35 #include "t4_hw.h" 36 37 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 38 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 39 F_CPL_SWITCH | F_SGE | F_ULP_TX) 40 41 enum { 42 MAX_NPORTS = 4, /* max # of ports */ 43 SERNUM_LEN = 24, /* Serial # length */ 44 EC_LEN = 16, /* E/C length */ 45 ID_LEN = 16, /* ID length */ 46 PN_LEN = 16, /* Part Number length */ 47 MD_LEN = 16, /* MFG diags version length */ 48 MACADDR_LEN = 12, /* MAC Address length */ 49 }; 50 51 enum { 52 T4_REGMAP_SIZE = (160 * 1024), 53 T5_REGMAP_SIZE = (332 * 1024), 54 }; 55 56 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 57 58 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 59 60 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 61 62 enum { 63 PAUSE_RX = 1 << 0, 64 PAUSE_TX = 1 << 1, 65 PAUSE_AUTONEG = 1 << 2 66 }; 67 68 enum { 69 FEC_RS = 1 << 0, 70 FEC_BASER_RS = 1 << 1, 71 FEC_RESERVED = 1 << 2, 72 }; 73 74 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS }; 75 76 struct port_stats { 77 u64 tx_octets; /* total # of octets in good frames */ 78 u64 tx_frames; /* all good frames */ 79 u64 tx_bcast_frames; /* all broadcast frames */ 80 u64 tx_mcast_frames; /* all multicast frames */ 81 u64 tx_ucast_frames; /* all unicast frames */ 82 u64 tx_error_frames; /* all error frames */ 83 84 u64 tx_frames_64; /* # of Tx frames in a particular range */ 85 u64 tx_frames_65_127; 86 u64 tx_frames_128_255; 87 u64 tx_frames_256_511; 88 u64 tx_frames_512_1023; 89 u64 tx_frames_1024_1518; 90 u64 tx_frames_1519_max; 91 92 u64 tx_drop; /* # of dropped Tx frames */ 93 u64 tx_pause; /* # of transmitted pause frames */ 94 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 95 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 96 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 97 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 98 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 99 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 100 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 101 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 102 103 u64 rx_octets; /* total # of octets in good frames */ 104 u64 rx_frames; /* all good frames */ 105 u64 rx_bcast_frames; /* all broadcast frames */ 106 u64 rx_mcast_frames; /* all multicast frames */ 107 u64 rx_ucast_frames; /* all unicast frames */ 108 u64 rx_too_long; /* # of frames exceeding MTU */ 109 u64 rx_jabber; /* # of jabber frames */ 110 u64 rx_fcs_err; /* # of received frames with bad FCS */ 111 u64 rx_len_err; /* # of received frames with length error */ 112 u64 rx_symbol_err; /* symbol errors */ 113 u64 rx_runt; /* # of short frames */ 114 115 u64 rx_frames_64; /* # of Rx frames in a particular range */ 116 u64 rx_frames_65_127; 117 u64 rx_frames_128_255; 118 u64 rx_frames_256_511; 119 u64 rx_frames_512_1023; 120 u64 rx_frames_1024_1518; 121 u64 rx_frames_1519_max; 122 123 u64 rx_pause; /* # of received pause frames */ 124 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 125 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 126 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 127 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 128 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 129 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 130 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 131 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 132 133 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 134 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 135 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 136 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 137 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 138 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 139 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 140 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 141 }; 142 143 struct lb_port_stats { 144 u64 octets; 145 u64 frames; 146 u64 bcast_frames; 147 u64 mcast_frames; 148 u64 ucast_frames; 149 u64 error_frames; 150 151 u64 frames_64; 152 u64 frames_65_127; 153 u64 frames_128_255; 154 u64 frames_256_511; 155 u64 frames_512_1023; 156 u64 frames_1024_1518; 157 u64 frames_1519_max; 158 159 u64 drop; 160 161 u64 ovflow0; 162 u64 ovflow1; 163 u64 ovflow2; 164 u64 ovflow3; 165 u64 trunc0; 166 u64 trunc1; 167 u64 trunc2; 168 u64 trunc3; 169 }; 170 171 struct tp_tcp_stats { 172 u32 tcp_out_rsts; 173 u64 tcp_in_segs; 174 u64 tcp_out_segs; 175 u64 tcp_retrans_segs; 176 }; 177 178 struct tp_usm_stats { 179 u32 frames; 180 u32 drops; 181 u64 octets; 182 }; 183 184 struct tp_fcoe_stats { 185 u32 frames_ddp; 186 u32 frames_drop; 187 u64 octets_ddp; 188 }; 189 190 struct tp_err_stats { 191 u32 mac_in_errs[MAX_NCHAN]; 192 u32 hdr_in_errs[MAX_NCHAN]; 193 u32 tcp_in_errs[MAX_NCHAN]; 194 u32 tnl_cong_drops[MAX_NCHAN]; 195 u32 ofld_chan_drops[MAX_NCHAN]; 196 u32 tnl_tx_drops[MAX_NCHAN]; 197 u32 ofld_vlan_drops[MAX_NCHAN]; 198 u32 tcp6_in_errs[MAX_NCHAN]; 199 u32 ofld_no_neigh; 200 u32 ofld_cong_defer; 201 }; 202 203 struct tp_proxy_stats { 204 u32 proxy[MAX_NCHAN]; 205 }; 206 207 struct tp_cpl_stats { 208 u32 req[MAX_NCHAN]; 209 u32 rsp[MAX_NCHAN]; 210 }; 211 212 struct tp_rdma_stats { 213 u32 rqe_dfr_pkt; 214 u32 rqe_dfr_mod; 215 }; 216 217 struct sge_params { 218 int timer_val[SGE_NTIMERS]; /* final, scaled values */ 219 int counter_val[SGE_NCOUNTERS]; 220 int fl_starve_threshold; 221 int fl_starve_threshold2; 222 int page_shift; 223 int eq_s_qpp; 224 int iq_s_qpp; 225 int spg_len; 226 int pad_boundary; 227 int pack_boundary; 228 int fl_pktshift; 229 u32 sge_control; 230 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES]; 231 }; 232 233 struct tp_params { 234 unsigned int tre; /* log2 of core clocks per TP tick */ 235 unsigned int dack_re; /* DACK timer resolution */ 236 unsigned int la_mask; /* what events are recorded by TP LA */ 237 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 238 239 uint32_t vlan_pri_map; 240 uint32_t ingress_config; 241 __be16 err_vec_mask; 242 243 int8_t fcoe_shift; 244 int8_t port_shift; 245 int8_t vnic_shift; 246 int8_t vlan_shift; 247 int8_t tos_shift; 248 int8_t protocol_shift; 249 int8_t ethertype_shift; 250 int8_t macmatch_shift; 251 int8_t matchtype_shift; 252 int8_t frag_shift; 253 }; 254 255 struct vpd_params { 256 unsigned int cclk; 257 u8 ec[EC_LEN + 1]; 258 u8 sn[SERNUM_LEN + 1]; 259 u8 id[ID_LEN + 1]; 260 u8 pn[PN_LEN + 1]; 261 u8 na[MACADDR_LEN + 1]; 262 u8 md[MD_LEN + 1]; 263 }; 264 265 struct pci_params { 266 unsigned int vpd_cap_addr; 267 unsigned int mps; 268 unsigned short speed; 269 unsigned short width; 270 }; 271 272 /* 273 * Firmware device log. 274 */ 275 struct devlog_params { 276 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 277 u32 start; /* start of log in firmware memory */ 278 u32 size; /* size of log */ 279 u32 addr; /* start address in flat addr space */ 280 }; 281 282 /* Stores chip specific parameters */ 283 struct chip_params { 284 u8 nchan; 285 u8 pm_stats_cnt; 286 u8 cng_ch_bits_log; /* congestion channel map bits width */ 287 u8 nsched_cls; 288 u8 cim_num_obq; 289 u16 mps_rplc_size; 290 u16 vfcount; 291 u32 sge_fl_db; 292 u16 mps_tcam_size; 293 }; 294 295 /* VF-only parameters. */ 296 297 /* 298 * Global Receive Side Scaling (RSS) parameters in host-native format. 299 */ 300 struct rss_params { 301 unsigned int mode; /* RSS mode */ 302 union { 303 struct { 304 u_int synmapen:1; /* SYN Map Enable */ 305 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ 306 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ 307 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ 308 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ 309 u_int ofdmapen:1; /* Offload Map Enable */ 310 u_int tnlmapen:1; /* Tunnel Map Enable */ 311 u_int tnlalllookup:1; /* Tunnel All Lookup */ 312 u_int hashtoeplitz:1; /* use Toeplitz hash */ 313 } basicvirtual; 314 } u; 315 }; 316 317 /* 318 * Maximum resources provisioned for a PCI VF. 319 */ 320 struct vf_resources { 321 unsigned int nvi; /* N virtual interfaces */ 322 unsigned int neq; /* N egress Qs */ 323 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 324 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 325 unsigned int niq; /* N ingress Qs */ 326 unsigned int tc; /* PCI-E traffic class */ 327 unsigned int pmask; /* port access rights mask */ 328 unsigned int nexactf; /* N exact MPS filters */ 329 unsigned int r_caps; /* read capabilities */ 330 unsigned int wx_caps; /* write/execute capabilities */ 331 }; 332 333 struct adapter_params { 334 struct sge_params sge; 335 struct tp_params tp; /* PF-only */ 336 struct vpd_params vpd; 337 struct pci_params pci; 338 struct devlog_params devlog; /* PF-only */ 339 struct rss_params rss; /* VF-only */ 340 struct vf_resources vfres; /* VF-only */ 341 unsigned int core_vdd; 342 343 unsigned int sf_size; /* serial flash size in bytes */ 344 unsigned int sf_nsec; /* # of flash sectors */ 345 346 unsigned int fw_vers; /* firmware version */ 347 unsigned int bs_vers; /* bootstrap version */ 348 unsigned int tp_vers; /* TP microcode version */ 349 unsigned int er_vers; /* expansion ROM version */ 350 unsigned int scfg_vers; /* Serial Configuration version */ 351 unsigned int vpd_vers; /* VPD version */ 352 353 unsigned short mtus[NMTUS]; 354 unsigned short a_wnd[NCCTRL_WIN]; 355 unsigned short b_wnd[NCCTRL_WIN]; 356 357 u_int ftid_min; 358 u_int ftid_max; 359 u_int etid_min; 360 u_int netids; 361 362 unsigned int cim_la_size; 363 364 uint8_t nports; /* # of ethernet ports */ 365 uint8_t portvec; 366 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 367 unsigned int rev:4; /* chip revision */ 368 unsigned int fpga:1; /* this is an FPGA */ 369 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 370 resources for TOE operation. */ 371 unsigned int bypass:1; /* this is a bypass card */ 372 unsigned int ethoffload:1; 373 unsigned int hash_filter:1; 374 unsigned int filter2_wr_support:1; 375 376 unsigned int ofldq_wr_cred; 377 unsigned int eo_wr_cred; 378 379 unsigned int max_ordird_qp; 380 unsigned int max_ird_adapter; 381 382 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */ 383 384 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */ 385 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */ 386 }; 387 388 #define CHELSIO_T4 0x4 389 #define CHELSIO_T5 0x5 390 #define CHELSIO_T6 0x6 391 392 /* 393 * State needed to monitor the forward progress of SGE Ingress DMA activities 394 * and possible hangs. 395 */ 396 struct sge_idma_monitor_state { 397 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 398 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 399 unsigned int idma_state[2]; /* IDMA Hang detect state */ 400 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 401 unsigned int idma_warn[2]; /* time to warning in HZ */ 402 }; 403 404 struct trace_params { 405 u32 data[TRACE_LEN / 4]; 406 u32 mask[TRACE_LEN / 4]; 407 unsigned short snap_len; 408 unsigned short min_len; 409 unsigned char skip_ofst; 410 unsigned char skip_len; 411 unsigned char invert; 412 unsigned char port; 413 }; 414 415 struct link_config { 416 /* OS-specific code owns all the requested_* fields */ 417 unsigned char requested_aneg; /* link aneg user has requested */ 418 unsigned char requested_fc; /* flow control user has requested */ 419 unsigned char requested_fec; /* FEC user has requested */ 420 unsigned int requested_speed; /* speed user has requested */ 421 422 unsigned short supported; /* link capabilities */ 423 unsigned short advertising; /* advertised capabilities */ 424 unsigned short lp_advertising; /* peer advertised capabilities */ 425 unsigned int speed; /* actual link speed */ 426 unsigned char fc; /* actual link flow control */ 427 unsigned char fec; /* actual FEC */ 428 unsigned char link_ok; /* link up? */ 429 unsigned char link_down_rc; /* link down reason */ 430 }; 431 432 #include "adapter.h" 433 434 #ifndef PCI_VENDOR_ID_CHELSIO 435 # define PCI_VENDOR_ID_CHELSIO 0x1425 436 #endif 437 438 #define for_each_port(adapter, iter) \ 439 for (iter = 0; iter < (adapter)->params.nports; ++iter) 440 441 static inline int is_ftid(const struct adapter *sc, u_int tid) 442 { 443 444 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max); 445 } 446 447 static inline int is_etid(const struct adapter *sc, u_int tid) 448 { 449 450 return (tid >= sc->params.etid_min); 451 } 452 453 static inline int is_offload(const struct adapter *adap) 454 { 455 return adap->params.offload; 456 } 457 458 static inline int is_ethoffload(const struct adapter *adap) 459 { 460 return adap->params.ethoffload; 461 } 462 463 static inline int is_hashfilter(const struct adapter *adap) 464 { 465 return adap->params.hash_filter; 466 } 467 468 static inline int chip_id(struct adapter *adap) 469 { 470 return adap->params.chipid; 471 } 472 473 static inline int chip_rev(struct adapter *adap) 474 { 475 return adap->params.rev; 476 } 477 478 static inline int is_t4(struct adapter *adap) 479 { 480 return adap->params.chipid == CHELSIO_T4; 481 } 482 483 static inline int is_t5(struct adapter *adap) 484 { 485 return adap->params.chipid == CHELSIO_T5; 486 } 487 488 static inline int is_t6(struct adapter *adap) 489 { 490 return adap->params.chipid == CHELSIO_T6; 491 } 492 493 static inline int is_fpga(struct adapter *adap) 494 { 495 return adap->params.fpga; 496 } 497 498 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 499 { 500 return adap->params.vpd.cclk / 1000; 501 } 502 503 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 504 unsigned int us) 505 { 506 return (us * adap->params.vpd.cclk) / 1000; 507 } 508 509 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 510 unsigned int ticks) 511 { 512 /* add Core Clock / 2 to round ticks to nearest uS */ 513 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 514 adapter->params.vpd.cclk); 515 } 516 517 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 518 unsigned int ticks) 519 { 520 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 521 } 522 523 static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us) 524 { 525 526 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre); 527 } 528 529 static inline u_int tcp_ticks_to_us(const struct adapter *adap, u_int ticks) 530 { 531 return ((uint64_t)ticks << adap->params.tp.tre) / 532 core_ticks_per_usec(adap); 533 } 534 535 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 536 537 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 538 int size, void *rpl, bool sleep_ok, int timeout); 539 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 540 void *rpl, bool sleep_ok); 541 542 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 543 const void *cmd, int size, void *rpl, 544 int timeout) 545 { 546 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 547 timeout); 548 } 549 550 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 551 int size, void *rpl) 552 { 553 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 554 } 555 556 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 557 int size, void *rpl) 558 { 559 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 560 } 561 562 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 563 unsigned int data_reg, u32 *vals, unsigned int nregs, 564 unsigned int start_idx); 565 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 566 unsigned int data_reg, const u32 *vals, 567 unsigned int nregs, unsigned int start_idx); 568 569 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 570 571 struct fw_filter_wr; 572 573 void t4_intr_enable(struct adapter *adapter); 574 void t4_intr_disable(struct adapter *adapter); 575 void t4_intr_clear(struct adapter *adapter); 576 int t4_slow_intr_handler(struct adapter *adapter); 577 578 int t4_hash_mac_addr(const u8 *addr); 579 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 580 struct link_config *lc); 581 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 582 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 583 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 584 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 585 int t4_seeprom_wp(struct adapter *adapter, int enable); 586 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 587 u32 *data, int byte_oriented); 588 int t4_write_flash(struct adapter *adapter, unsigned int addr, 589 unsigned int n, const u8 *data, int byte_oriented); 590 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 591 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 592 int t5_fw_init_extern_mem(struct adapter *adap); 593 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 594 int t4_load_boot(struct adapter *adap, u8 *boot_data, 595 unsigned int boot_addr, unsigned int size); 596 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 597 int t4_flash_cfg_addr(struct adapter *adapter); 598 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 599 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 600 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 601 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 602 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 603 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 604 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 605 int t4_get_version_info(struct adapter *adapter); 606 int t4_init_hw(struct adapter *adapter, u32 fw_params); 607 const struct chip_params *t4_get_chip_params(int chipid); 608 int t4_prep_adapter(struct adapter *adapter, u32 *buf); 609 int t4_shutdown_adapter(struct adapter *adapter); 610 int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 611 int t4_init_sge_params(struct adapter *adapter); 612 int t4_init_tp_params(struct adapter *adap, bool sleep_ok); 613 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 614 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); 615 void t4_fatal_err(struct adapter *adapter); 616 void t4_db_full(struct adapter *adapter); 617 void t4_db_dropped(struct adapter *adapter); 618 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 619 int filter_index, int enable); 620 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 621 int filter_index, int *enabled); 622 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 623 int start, int n, const u16 *rspq, unsigned int nrspq); 624 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 625 unsigned int flags); 626 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 627 unsigned int flags, unsigned int defq, unsigned int skeyidx, 628 unsigned int skey); 629 int t4_read_rss(struct adapter *adapter, u16 *entries); 630 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok); 631 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx, 632 bool sleep_ok); 633 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, 634 u32 *valp, bool sleep_ok); 635 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, 636 u32 val, bool sleep_ok); 637 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 638 u32 *vfl, u32 *vfh, bool sleep_ok); 639 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 640 u32 vfl, u32 vfh, bool sleep_ok); 641 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok); 642 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok); 643 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok); 644 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok); 645 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 646 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 647 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 648 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 649 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 650 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 651 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 652 unsigned int *valp); 653 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 654 const unsigned int *valp); 655 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 656 unsigned int *valp); 657 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 658 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 659 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 660 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 661 int t4_get_flash_params(struct adapter *adapter); 662 663 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 664 int t4_mc_read(struct adapter *adap, int idx, u32 addr, 665 __be32 *data, u64 *parity); 666 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 667 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 668 __be32 *data); 669 void t4_idma_monitor_init(struct adapter *adapter, 670 struct sge_idma_monitor_state *idma); 671 void t4_idma_monitor(struct adapter *adapter, 672 struct sge_idma_monitor_state *idma, 673 int hz, int ticks); 674 675 unsigned int t4_get_regs_len(struct adapter *adapter); 676 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); 677 678 const char *t4_get_port_type_description(enum fw_port_type port_type); 679 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 680 void t4_get_port_stats_offset(struct adapter *adap, int idx, 681 struct port_stats *stats, 682 struct port_stats *offset); 683 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 684 void t4_clr_port_stats(struct adapter *adap, int idx); 685 686 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 687 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 688 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 689 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 690 unsigned int *ipg, bool sleep_ok); 691 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 692 unsigned int mask, unsigned int val); 693 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 694 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st, 695 bool sleep_ok); 696 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st, 697 bool sleep_ok); 698 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st, 699 bool sleep_ok); 700 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st, 701 bool sleep_ok); 702 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st, 703 bool sleep_ok); 704 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 705 struct tp_tcp_stats *v6, bool sleep_ok); 706 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 707 struct tp_fcoe_stats *st, bool sleep_ok); 708 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 709 const unsigned short *alpha, const unsigned short *beta); 710 711 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 712 713 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 714 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 715 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 716 unsigned int start, unsigned int n); 717 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 718 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map, 719 bool sleep_ok); 720 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 721 722 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 723 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 724 u64 mask0, u64 mask1, unsigned int crc, bool enable); 725 726 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 727 enum dev_master master, enum dev_state *state); 728 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 729 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 730 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 731 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 732 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 733 const u8 *fw_data, unsigned int size, int force); 734 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data, 735 unsigned int size); 736 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 737 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 738 unsigned int vf, unsigned int nparams, const u32 *params, 739 u32 *val); 740 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 741 unsigned int vf, unsigned int nparams, const u32 *params, 742 u32 *val, int rw); 743 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 744 unsigned int pf, unsigned int vf, 745 unsigned int nparams, const u32 *params, 746 const u32 *val, int timeout); 747 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 748 unsigned int vf, unsigned int nparams, const u32 *params, 749 const u32 *val); 750 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 751 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 752 unsigned int rxqi, unsigned int rxq, unsigned int tc, 753 unsigned int vi, unsigned int cmask, unsigned int pmask, 754 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 755 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 756 unsigned int port, unsigned int pf, unsigned int vf, 757 unsigned int nmac, u8 *mac, u16 *rss_size, 758 unsigned int portfunc, unsigned int idstype); 759 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 760 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 761 u16 *rss_size); 762 int t4_free_vi(struct adapter *adap, unsigned int mbox, 763 unsigned int pf, unsigned int vf, 764 unsigned int viid); 765 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 766 int mtu, int promisc, int all_multi, int bcast, int vlanex, 767 bool sleep_ok); 768 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 769 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 770 u64 *hash, bool sleep_ok); 771 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 772 int idx, const u8 *addr, bool persist, bool add_smt); 773 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 774 bool ucast, u64 vec, bool sleep_ok); 775 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 776 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 777 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 778 bool rx_en, bool tx_en); 779 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 780 unsigned int nblinks); 781 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 782 unsigned int mmd, unsigned int reg, unsigned int *valp); 783 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 784 unsigned int mmd, unsigned int reg, unsigned int val); 785 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 786 int port, unsigned int devid, 787 unsigned int offset, unsigned int len, 788 u8 *buf); 789 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 790 int port, unsigned int devid, 791 unsigned int offset, unsigned int len, 792 u8 *buf); 793 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 794 unsigned int vf, unsigned int iqtype, unsigned int iqid, 795 unsigned int fl0id, unsigned int fl1id); 796 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 797 unsigned int vf, unsigned int iqtype, unsigned int iqid, 798 unsigned int fl0id, unsigned int fl1id); 799 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 800 unsigned int vf, unsigned int eqid); 801 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 802 unsigned int vf, unsigned int eqid); 803 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 804 unsigned int vf, unsigned int eqid); 805 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 806 enum ctxt_type ctype, u32 *data); 807 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 808 u32 *data); 809 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 810 const char *t4_link_down_rc_str(unsigned char link_down_rc); 811 int t4_update_port_info(struct port_info *pi); 812 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 813 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 814 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 815 int sleep_ok); 816 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 817 int rateunit, int ratemode, int channel, int cl, 818 int minrate, int maxrate, int weight, int pktsize, 819 int sleep_ok); 820 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode, 821 unsigned int maxrate, int sleep_ok); 822 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl, 823 int weight, int sleep_ok); 824 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl, 825 int mode, unsigned int maxrate, int pktsize, 826 int sleep_ok); 827 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 828 unsigned int pf, unsigned int vf, 829 unsigned int timeout, unsigned int action); 830 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 831 int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 832 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 833 834 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 835 u32 start_index, bool sleep_ok); 836 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs, 837 u32 start_index, bool sleep_ok); 838 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs, 839 u32 start_index, bool sleep_ok); 840 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, 841 u32 start_index, bool sleep_ok); 842 843 static inline int t4vf_query_params(struct adapter *adapter, 844 unsigned int nparams, const u32 *params, 845 u32 *vals) 846 { 847 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals); 848 } 849 850 static inline int t4vf_set_params(struct adapter *adapter, 851 unsigned int nparams, const u32 *params, 852 const u32 *vals) 853 { 854 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals); 855 } 856 857 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd, 858 int size, void *rpl) 859 { 860 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl); 861 } 862 863 int t4vf_wait_dev_ready(struct adapter *adapter); 864 int t4vf_fw_reset(struct adapter *adapter); 865 int t4vf_get_sge_params(struct adapter *adapter); 866 int t4vf_get_rss_glb_config(struct adapter *adapter); 867 int t4vf_get_vfres(struct adapter *adapter); 868 int t4vf_prep_adapter(struct adapter *adapter); 869 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid, 870 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset, 871 unsigned int *pbar2_qid); 872 873 #endif /* __CHELSIO_COMMON_H */ 874