1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef __CHELSIO_COMMON_H 31 #define __CHELSIO_COMMON_H 32 33 #include "t4_hw.h" 34 35 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ 36 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ 37 F_CPL_SWITCH | F_SGE | F_ULP_TX) 38 39 enum { 40 MAX_NPORTS = 4, /* max # of ports */ 41 SERNUM_LEN = 24, /* Serial # length */ 42 EC_LEN = 16, /* E/C length */ 43 ID_LEN = 16, /* ID length */ 44 PN_LEN = 16, /* Part Number length */ 45 MACADDR_LEN = 12, /* MAC Address length */ 46 }; 47 48 enum { 49 T4_REGMAP_SIZE = (160 * 1024), 50 T5_REGMAP_SIZE = (332 * 1024), 51 }; 52 53 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 54 55 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST }; 56 57 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR }; 58 59 enum { 60 PAUSE_RX = 1 << 0, 61 PAUSE_TX = 1 << 1, 62 PAUSE_AUTONEG = 1 << 2 63 }; 64 65 struct port_stats { 66 u64 tx_octets; /* total # of octets in good frames */ 67 u64 tx_frames; /* all good frames */ 68 u64 tx_bcast_frames; /* all broadcast frames */ 69 u64 tx_mcast_frames; /* all multicast frames */ 70 u64 tx_ucast_frames; /* all unicast frames */ 71 u64 tx_error_frames; /* all error frames */ 72 73 u64 tx_frames_64; /* # of Tx frames in a particular range */ 74 u64 tx_frames_65_127; 75 u64 tx_frames_128_255; 76 u64 tx_frames_256_511; 77 u64 tx_frames_512_1023; 78 u64 tx_frames_1024_1518; 79 u64 tx_frames_1519_max; 80 81 u64 tx_drop; /* # of dropped Tx frames */ 82 u64 tx_pause; /* # of transmitted pause frames */ 83 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */ 84 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */ 85 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */ 86 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */ 87 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */ 88 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */ 89 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */ 90 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */ 91 92 u64 rx_octets; /* total # of octets in good frames */ 93 u64 rx_frames; /* all good frames */ 94 u64 rx_bcast_frames; /* all broadcast frames */ 95 u64 rx_mcast_frames; /* all multicast frames */ 96 u64 rx_ucast_frames; /* all unicast frames */ 97 u64 rx_too_long; /* # of frames exceeding MTU */ 98 u64 rx_jabber; /* # of jabber frames */ 99 u64 rx_fcs_err; /* # of received frames with bad FCS */ 100 u64 rx_len_err; /* # of received frames with length error */ 101 u64 rx_symbol_err; /* symbol errors */ 102 u64 rx_runt; /* # of short frames */ 103 104 u64 rx_frames_64; /* # of Rx frames in a particular range */ 105 u64 rx_frames_65_127; 106 u64 rx_frames_128_255; 107 u64 rx_frames_256_511; 108 u64 rx_frames_512_1023; 109 u64 rx_frames_1024_1518; 110 u64 rx_frames_1519_max; 111 112 u64 rx_pause; /* # of received pause frames */ 113 u64 rx_ppp0; /* # of received PPP prio 0 frames */ 114 u64 rx_ppp1; /* # of received PPP prio 1 frames */ 115 u64 rx_ppp2; /* # of received PPP prio 2 frames */ 116 u64 rx_ppp3; /* # of received PPP prio 3 frames */ 117 u64 rx_ppp4; /* # of received PPP prio 4 frames */ 118 u64 rx_ppp5; /* # of received PPP prio 5 frames */ 119 u64 rx_ppp6; /* # of received PPP prio 6 frames */ 120 u64 rx_ppp7; /* # of received PPP prio 7 frames */ 121 122 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */ 123 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */ 124 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */ 125 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */ 126 u64 rx_trunc0; /* buffer-group 0 truncated packets */ 127 u64 rx_trunc1; /* buffer-group 1 truncated packets */ 128 u64 rx_trunc2; /* buffer-group 2 truncated packets */ 129 u64 rx_trunc3; /* buffer-group 3 truncated packets */ 130 }; 131 132 struct lb_port_stats { 133 u64 octets; 134 u64 frames; 135 u64 bcast_frames; 136 u64 mcast_frames; 137 u64 ucast_frames; 138 u64 error_frames; 139 140 u64 frames_64; 141 u64 frames_65_127; 142 u64 frames_128_255; 143 u64 frames_256_511; 144 u64 frames_512_1023; 145 u64 frames_1024_1518; 146 u64 frames_1519_max; 147 148 u64 drop; 149 150 u64 ovflow0; 151 u64 ovflow1; 152 u64 ovflow2; 153 u64 ovflow3; 154 u64 trunc0; 155 u64 trunc1; 156 u64 trunc2; 157 u64 trunc3; 158 }; 159 160 struct tp_tcp_stats { 161 u32 tcp_out_rsts; 162 u64 tcp_in_segs; 163 u64 tcp_out_segs; 164 u64 tcp_retrans_segs; 165 }; 166 167 struct tp_usm_stats { 168 u32 frames; 169 u32 drops; 170 u64 octets; 171 }; 172 173 struct tp_fcoe_stats { 174 u32 frames_ddp; 175 u32 frames_drop; 176 u64 octets_ddp; 177 }; 178 179 struct tp_err_stats { 180 u32 mac_in_errs[MAX_NCHAN]; 181 u32 hdr_in_errs[MAX_NCHAN]; 182 u32 tcp_in_errs[MAX_NCHAN]; 183 u32 tnl_cong_drops[MAX_NCHAN]; 184 u32 ofld_chan_drops[MAX_NCHAN]; 185 u32 tnl_tx_drops[MAX_NCHAN]; 186 u32 ofld_vlan_drops[MAX_NCHAN]; 187 u32 tcp6_in_errs[MAX_NCHAN]; 188 u32 ofld_no_neigh; 189 u32 ofld_cong_defer; 190 }; 191 192 struct tp_proxy_stats { 193 u32 proxy[MAX_NCHAN]; 194 }; 195 196 struct tp_cpl_stats { 197 u32 req[MAX_NCHAN]; 198 u32 rsp[MAX_NCHAN]; 199 }; 200 201 struct tp_rdma_stats { 202 u32 rqe_dfr_pkt; 203 u32 rqe_dfr_mod; 204 }; 205 206 struct sge_params { 207 int timer_val[SGE_NTIMERS]; 208 int counter_val[SGE_NCOUNTERS]; 209 int fl_starve_threshold; 210 int fl_starve_threshold2; 211 int page_shift; 212 int eq_s_qpp; 213 int iq_s_qpp; 214 int spg_len; 215 int pad_boundary; 216 int pack_boundary; 217 int fl_pktshift; 218 u32 sge_control; 219 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES]; 220 }; 221 222 struct tp_params { 223 unsigned int tre; /* log2 of core clocks per TP tick */ 224 unsigned int dack_re; /* DACK timer resolution */ 225 unsigned int la_mask; /* what events are recorded by TP LA */ 226 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */ 227 228 uint32_t vlan_pri_map; 229 uint32_t ingress_config; 230 uint32_t rx_pkt_encap; 231 232 int8_t fcoe_shift; 233 int8_t port_shift; 234 int8_t vnic_shift; 235 int8_t vlan_shift; 236 int8_t tos_shift; 237 int8_t protocol_shift; 238 int8_t ethertype_shift; 239 int8_t macmatch_shift; 240 int8_t matchtype_shift; 241 int8_t frag_shift; 242 }; 243 244 struct vpd_params { 245 unsigned int cclk; 246 u8 ec[EC_LEN + 1]; 247 u8 sn[SERNUM_LEN + 1]; 248 u8 id[ID_LEN + 1]; 249 u8 pn[PN_LEN + 1]; 250 u8 na[MACADDR_LEN + 1]; 251 }; 252 253 struct pci_params { 254 unsigned int vpd_cap_addr; 255 unsigned int mps; 256 unsigned short speed; 257 unsigned short width; 258 }; 259 260 /* 261 * Firmware device log. 262 */ 263 struct devlog_params { 264 u32 memtype; /* which memory (FW_MEMTYPE_* ) */ 265 u32 start; /* start of log in firmware memory */ 266 u32 size; /* size of log */ 267 u32 addr; /* start address in flat addr space */ 268 }; 269 270 /* Stores chip specific parameters */ 271 struct chip_params { 272 u8 nchan; 273 u8 pm_stats_cnt; 274 u8 cng_ch_bits_log; /* congestion channel map bits width */ 275 u8 nsched_cls; 276 u8 cim_num_obq; 277 u16 mps_rplc_size; 278 u16 vfcount; 279 u32 sge_fl_db; 280 u16 mps_tcam_size; 281 }; 282 283 /* VF-only parameters. */ 284 285 /* 286 * Global Receive Side Scaling (RSS) parameters in host-native format. 287 */ 288 struct rss_params { 289 unsigned int mode; /* RSS mode */ 290 union { 291 struct { 292 u_int synmapen:1; /* SYN Map Enable */ 293 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */ 294 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */ 295 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */ 296 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */ 297 u_int ofdmapen:1; /* Offload Map Enable */ 298 u_int tnlmapen:1; /* Tunnel Map Enable */ 299 u_int tnlalllookup:1; /* Tunnel All Lookup */ 300 u_int hashtoeplitz:1; /* use Toeplitz hash */ 301 } basicvirtual; 302 } u; 303 }; 304 305 /* 306 * Maximum resources provisioned for a PCI VF. 307 */ 308 struct vf_resources { 309 unsigned int nvi; /* N virtual interfaces */ 310 unsigned int neq; /* N egress Qs */ 311 unsigned int nethctrl; /* N egress ETH or CTRL Qs */ 312 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */ 313 unsigned int niq; /* N ingress Qs */ 314 unsigned int tc; /* PCI-E traffic class */ 315 unsigned int pmask; /* port access rights mask */ 316 unsigned int nexactf; /* N exact MPS filters */ 317 unsigned int r_caps; /* read capabilities */ 318 unsigned int wx_caps; /* write/execute capabilities */ 319 }; 320 321 struct adapter_params { 322 struct sge_params sge; 323 struct tp_params tp; /* PF-only */ 324 struct vpd_params vpd; 325 struct pci_params pci; 326 struct devlog_params devlog; /* PF-only */ 327 struct rss_params rss; /* VF-only */ 328 struct vf_resources vfres; /* VF-only */ 329 330 unsigned int sf_size; /* serial flash size in bytes */ 331 unsigned int sf_nsec; /* # of flash sectors */ 332 333 unsigned int fw_vers; /* firmware version */ 334 unsigned int bs_vers; /* bootstrap version */ 335 unsigned int tp_vers; /* TP microcode version */ 336 unsigned int er_vers; /* expansion ROM version */ 337 unsigned int scfg_vers; /* Serial Configuration version */ 338 unsigned int vpd_vers; /* VPD version */ 339 340 unsigned short mtus[NMTUS]; 341 unsigned short a_wnd[NCCTRL_WIN]; 342 unsigned short b_wnd[NCCTRL_WIN]; 343 344 u_int ftid_min; 345 u_int ftid_max; 346 u_int etid_min; 347 u_int netids; 348 349 unsigned int cim_la_size; 350 351 uint8_t nports; /* # of ethernet ports */ 352 uint8_t portvec; 353 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */ 354 unsigned int rev:4; /* chip revision */ 355 unsigned int fpga:1; /* this is an FPGA */ 356 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card 357 resources for TOE operation. */ 358 unsigned int bypass:1; /* this is a bypass card */ 359 unsigned int ethoffload:1; 360 361 unsigned int ofldq_wr_cred; 362 unsigned int eo_wr_cred; 363 }; 364 365 #define CHELSIO_T4 0x4 366 #define CHELSIO_T5 0x5 367 #define CHELSIO_T6 0x6 368 369 /* 370 * State needed to monitor the forward progress of SGE Ingress DMA activities 371 * and possible hangs. 372 */ 373 struct sge_idma_monitor_state { 374 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */ 375 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */ 376 unsigned int idma_state[2]; /* IDMA Hang detect state */ 377 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */ 378 unsigned int idma_warn[2]; /* time to warning in HZ */ 379 }; 380 381 struct trace_params { 382 u32 data[TRACE_LEN / 4]; 383 u32 mask[TRACE_LEN / 4]; 384 unsigned short snap_len; 385 unsigned short min_len; 386 unsigned char skip_ofst; 387 unsigned char skip_len; 388 unsigned char invert; 389 unsigned char port; 390 }; 391 392 struct link_config { 393 unsigned short supported; /* link capabilities */ 394 unsigned short advertising; /* advertised capabilities */ 395 unsigned short requested_speed; /* speed user has requested */ 396 unsigned short speed; /* actual link speed */ 397 unsigned char requested_fc; /* flow control user has requested */ 398 unsigned char fc; /* actual link flow control */ 399 unsigned char autoneg; /* autonegotiating? */ 400 unsigned char link_ok; /* link up? */ 401 }; 402 403 #include "adapter.h" 404 405 #ifndef PCI_VENDOR_ID_CHELSIO 406 # define PCI_VENDOR_ID_CHELSIO 0x1425 407 #endif 408 409 #define for_each_port(adapter, iter) \ 410 for (iter = 0; iter < (adapter)->params.nports; ++iter) 411 412 static inline int is_ftid(const struct adapter *sc, u_int tid) 413 { 414 415 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max); 416 } 417 418 static inline int is_etid(const struct adapter *sc, u_int tid) 419 { 420 421 return (tid >= sc->params.etid_min); 422 } 423 424 static inline int is_offload(const struct adapter *adap) 425 { 426 return adap->params.offload; 427 } 428 429 static inline int is_ethoffload(const struct adapter *adap) 430 { 431 return adap->params.ethoffload; 432 } 433 434 static inline int chip_id(struct adapter *adap) 435 { 436 return adap->params.chipid; 437 } 438 439 static inline int chip_rev(struct adapter *adap) 440 { 441 return adap->params.rev; 442 } 443 444 static inline int is_t4(struct adapter *adap) 445 { 446 return adap->params.chipid == CHELSIO_T4; 447 } 448 449 static inline int is_t5(struct adapter *adap) 450 { 451 return adap->params.chipid == CHELSIO_T5; 452 } 453 454 static inline int is_t6(struct adapter *adap) 455 { 456 return adap->params.chipid == CHELSIO_T6; 457 } 458 459 static inline int is_fpga(struct adapter *adap) 460 { 461 return adap->params.fpga; 462 } 463 464 static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 465 { 466 return adap->params.vpd.cclk / 1000; 467 } 468 469 static inline unsigned int us_to_core_ticks(const struct adapter *adap, 470 unsigned int us) 471 { 472 return (us * adap->params.vpd.cclk) / 1000; 473 } 474 475 static inline unsigned int core_ticks_to_us(const struct adapter *adapter, 476 unsigned int ticks) 477 { 478 /* add Core Clock / 2 to round ticks to nearest uS */ 479 return ((ticks * 1000 + adapter->params.vpd.cclk/2) / 480 adapter->params.vpd.cclk); 481 } 482 483 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap, 484 unsigned int ticks) 485 { 486 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 487 } 488 489 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val); 490 491 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, 492 int size, void *rpl, bool sleep_ok, int timeout); 493 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, 494 void *rpl, bool sleep_ok); 495 496 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox, 497 const void *cmd, int size, void *rpl, 498 int timeout) 499 { 500 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true, 501 timeout); 502 } 503 504 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd, 505 int size, void *rpl) 506 { 507 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true); 508 } 509 510 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd, 511 int size, void *rpl) 512 { 513 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false); 514 } 515 516 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, 517 unsigned int data_reg, u32 *vals, unsigned int nregs, 518 unsigned int start_idx); 519 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, 520 unsigned int data_reg, const u32 *vals, 521 unsigned int nregs, unsigned int start_idx); 522 523 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg); 524 525 struct fw_filter_wr; 526 527 void t4_intr_enable(struct adapter *adapter); 528 void t4_intr_disable(struct adapter *adapter); 529 void t4_intr_clear(struct adapter *adapter); 530 int t4_slow_intr_handler(struct adapter *adapter); 531 532 int t4_hash_mac_addr(const u8 *addr); 533 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port, 534 struct link_config *lc); 535 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port); 536 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data); 537 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data); 538 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz); 539 int t4_seeprom_wp(struct adapter *adapter, int enable); 540 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords, 541 u32 *data, int byte_oriented); 542 int t4_write_flash(struct adapter *adapter, unsigned int addr, 543 unsigned int n, const u8 *data, int byte_oriented); 544 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); 545 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op); 546 int t5_fw_init_extern_mem(struct adapter *adap); 547 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 548 int t4_load_boot(struct adapter *adap, u8 *boot_data, 549 unsigned int boot_addr, unsigned int size); 550 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end); 551 int t4_flash_cfg_addr(struct adapter *adapter); 552 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size); 553 int t4_get_fw_version(struct adapter *adapter, u32 *vers); 554 int t4_get_bs_version(struct adapter *adapter, u32 *vers); 555 int t4_get_tp_version(struct adapter *adapter, u32 *vers); 556 int t4_get_exprom_version(struct adapter *adapter, u32 *vers); 557 int t4_get_scfg_version(struct adapter *adapter, u32 *vers); 558 int t4_get_vpd_version(struct adapter *adapter, u32 *vers); 559 int t4_get_version_info(struct adapter *adapter); 560 int t4_init_hw(struct adapter *adapter, u32 fw_params); 561 int t4_prep_adapter(struct adapter *adapter, u8 *buf); 562 int t4_shutdown_adapter(struct adapter *adapter); 563 int t4_init_devlog_params(struct adapter *adapter, int fw_attach); 564 int t4_init_sge_params(struct adapter *adapter); 565 int t4_init_tp_params(struct adapter *adap); 566 int t4_filter_field_shift(const struct adapter *adap, int filter_sel); 567 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id); 568 void t4_fatal_err(struct adapter *adapter); 569 void t4_db_full(struct adapter *adapter); 570 void t4_db_dropped(struct adapter *adapter); 571 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, 572 int filter_index, int enable); 573 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, 574 int filter_index, int *enabled); 575 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid, 576 int start, int n, const u16 *rspq, unsigned int nrspq); 577 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode, 578 unsigned int flags); 579 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid, 580 unsigned int flags, unsigned int defq); 581 int t4_read_rss(struct adapter *adapter, u16 *entries); 582 void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, 583 unsigned int start_index, unsigned int rw); 584 void t4_read_rss_key(struct adapter *adapter, u32 *key); 585 void t4_write_rss_key(struct adapter *adap, u32 *key, int idx); 586 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index, u32 *valp); 587 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index, u32 val); 588 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index, 589 u32 *vfl, u32 *vfh); 590 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index, 591 u32 vfl, u32 vfh); 592 u32 t4_read_rss_pf_map(struct adapter *adapter); 593 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap); 594 u32 t4_read_rss_pf_mask(struct adapter *adapter); 595 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask); 596 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 597 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 598 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]); 599 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres); 600 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 601 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n); 602 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, 603 unsigned int *valp); 604 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, 605 const unsigned int *valp); 606 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n, 607 unsigned int *valp); 608 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr); 609 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, 610 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr); 611 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp); 612 int t4_get_flash_params(struct adapter *adapter); 613 614 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach); 615 int t4_mc_read(struct adapter *adap, int idx, u32 addr, 616 __be32 *data, u64 *parity); 617 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity); 618 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size, 619 __be32 *data); 620 void t4_idma_monitor_init(struct adapter *adapter, 621 struct sge_idma_monitor_state *idma); 622 void t4_idma_monitor(struct adapter *adapter, 623 struct sge_idma_monitor_state *idma, 624 int hz, int ticks); 625 626 unsigned int t4_get_regs_len(struct adapter *adapter); 627 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size); 628 629 const char *t4_get_port_type_description(enum fw_port_type port_type); 630 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 631 void t4_get_port_stats_offset(struct adapter *adap, int idx, 632 struct port_stats *stats, 633 struct port_stats *offset); 634 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p); 635 void t4_clr_port_stats(struct adapter *adap, int idx); 636 637 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 638 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]); 639 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]); 640 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps, 641 unsigned int *ipg); 642 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 643 unsigned int mask, unsigned int val); 644 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr); 645 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st); 646 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st); 647 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st); 648 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st); 649 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st); 650 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 651 struct tp_tcp_stats *v6); 652 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, 653 struct tp_fcoe_stats *st); 654 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, 655 const unsigned short *alpha, const unsigned short *beta); 656 657 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf); 658 659 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps); 660 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg); 661 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals, 662 unsigned int start, unsigned int n); 663 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate); 664 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map); 665 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid); 666 667 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr); 668 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map, 669 u64 mask0, u64 mask1, unsigned int crc, bool enable); 670 671 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, 672 enum dev_master master, enum dev_state *state); 673 int t4_fw_bye(struct adapter *adap, unsigned int mbox); 674 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset); 675 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force); 676 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset); 677 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, 678 const u8 *fw_data, unsigned int size, int force); 679 int t4_fw_initialize(struct adapter *adap, unsigned int mbox); 680 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 681 unsigned int vf, unsigned int nparams, const u32 *params, 682 u32 *val); 683 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, 684 unsigned int vf, unsigned int nparams, const u32 *params, 685 u32 *val, int rw); 686 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, 687 unsigned int pf, unsigned int vf, 688 unsigned int nparams, const u32 *params, 689 const u32 *val, int timeout); 690 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, 691 unsigned int vf, unsigned int nparams, const u32 *params, 692 const u32 *val); 693 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, 694 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl, 695 unsigned int rxqi, unsigned int rxq, unsigned int tc, 696 unsigned int vi, unsigned int cmask, unsigned int pmask, 697 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps); 698 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox, 699 unsigned int port, unsigned int pf, unsigned int vf, 700 unsigned int nmac, u8 *mac, u16 *rss_size, 701 unsigned int portfunc, unsigned int idstype); 702 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, 703 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac, 704 u16 *rss_size); 705 int t4_free_vi(struct adapter *adap, unsigned int mbox, 706 unsigned int pf, unsigned int vf, 707 unsigned int viid); 708 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, 709 int mtu, int promisc, int all_multi, int bcast, int vlanex, 710 bool sleep_ok); 711 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid, 712 bool free, unsigned int naddr, const u8 **addr, u16 *idx, 713 u64 *hash, bool sleep_ok); 714 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, 715 int idx, const u8 *addr, bool persist, bool add_smt); 716 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, 717 bool ucast, u64 vec, bool sleep_ok); 718 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, 719 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en); 720 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, 721 bool rx_en, bool tx_en); 722 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, 723 unsigned int nblinks); 724 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 725 unsigned int mmd, unsigned int reg, unsigned int *valp); 726 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, 727 unsigned int mmd, unsigned int reg, unsigned int val); 728 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, 729 int port, unsigned int devid, 730 unsigned int offset, unsigned int len, 731 u8 *buf); 732 int t4_i2c_wr(struct adapter *adap, unsigned int mbox, 733 int port, unsigned int devid, 734 unsigned int offset, unsigned int len, 735 u8 *buf); 736 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, 737 unsigned int vf, unsigned int iqtype, unsigned int iqid, 738 unsigned int fl0id, unsigned int fl1id); 739 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 740 unsigned int vf, unsigned int iqtype, unsigned int iqid, 741 unsigned int fl0id, unsigned int fl1id); 742 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 743 unsigned int vf, unsigned int eqid); 744 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 745 unsigned int vf, unsigned int eqid); 746 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, 747 unsigned int vf, unsigned int eqid); 748 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid, 749 enum ctxt_type ctype, u32 *data); 750 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype, 751 u32 *data); 752 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox); 753 const char *t4_link_down_rc_str(unsigned char link_down_rc); 754 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl); 755 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val); 756 int t4_sched_config(struct adapter *adapter, int type, int minmaxen, 757 int sleep_ok); 758 int t4_sched_params(struct adapter *adapter, int type, int level, int mode, 759 int rateunit, int ratemode, int channel, int cl, 760 int minrate, int maxrate, int weight, int pktsize, 761 int sleep_ok); 762 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox, 763 unsigned int pf, unsigned int vf, 764 unsigned int timeout, unsigned int action); 765 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level); 766 int t4_set_devlog_level(struct adapter *adapter, unsigned int level); 767 void t4_sge_decode_idma_state(struct adapter *adapter, int state); 768 #endif /* __CHELSIO_COMMON_H */ 769