1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "common/t4_msg.h" 58 #include "firmware/t4fw_interface.h" 59 60 #define KTR_CXGBE KTR_SPARE3 61 MALLOC_DECLARE(M_CXGBE); 62 #define CXGBE_UNIMPLEMENTED(s) \ 63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 64 65 #if defined(__i386__) || defined(__amd64__) 66 static __inline void 67 prefetch(void *x) 68 { 69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 70 } 71 #else 72 #define prefetch(x) 73 #endif 74 75 #ifndef SYSCTL_ADD_UQUAD 76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 77 #define sysctl_handle_64 sysctl_handle_quad 78 #define CTLTYPE_U64 CTLTYPE_QUAD 79 #endif 80 81 #if (__FreeBSD_version >= 900030) || \ 82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 83 #define SBUF_DRAIN 1 84 #endif 85 86 #ifdef __amd64__ 87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 88 static __inline uint64_t 89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 90 bus_size_t offset) 91 { 92 KASSERT(tag == X86_BUS_SPACE_MEM, 93 ("%s: can only handle mem space", __func__)); 94 95 return (*(volatile uint64_t *)(handle + offset)); 96 } 97 98 static __inline void 99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 100 bus_size_t offset, uint64_t value) 101 { 102 KASSERT(tag == X86_BUS_SPACE_MEM, 103 ("%s: can only handle mem space", __func__)); 104 105 *(volatile uint64_t *)(bsh + offset) = value; 106 } 107 #else 108 static __inline uint64_t 109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 110 bus_size_t offset) 111 { 112 return (uint64_t)bus_space_read_4(tag, handle, offset) + 113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 114 } 115 116 static __inline void 117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 118 bus_size_t offset, uint64_t value) 119 { 120 bus_space_write_4(tag, bsh, offset, value); 121 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 122 } 123 #endif 124 125 struct adapter; 126 typedef struct adapter adapter_t; 127 128 enum { 129 /* 130 * All ingress queues use this entry size. Note that the firmware event 131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 132 * be at least 64. 133 */ 134 IQ_ESIZE = 64, 135 136 /* Default queue sizes for all kinds of ingress queues */ 137 FW_IQ_QSIZE = 256, 138 RX_IQ_QSIZE = 1024, 139 140 /* All egress queues use this entry size */ 141 EQ_ESIZE = 64, 142 143 /* Default queue sizes for all kinds of egress queues */ 144 CTRL_EQ_QSIZE = 128, 145 TX_EQ_QSIZE = 1024, 146 147 #if MJUMPAGESIZE != MCLBYTES 148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 149 #else 150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 151 #endif 152 CL_METADATA_SIZE = CACHE_LINE_SIZE, 153 154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 155 TX_SGL_SEGS = 39, 156 TX_SGL_SEGS_TSO = 38, 157 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 158 }; 159 160 enum { 161 /* adapter intr_type */ 162 INTR_INTX = (1 << 0), 163 INTR_MSI = (1 << 1), 164 INTR_MSIX = (1 << 2) 165 }; 166 167 enum { 168 XGMAC_MTU = (1 << 0), 169 XGMAC_PROMISC = (1 << 1), 170 XGMAC_ALLMULTI = (1 << 2), 171 XGMAC_VLANEX = (1 << 3), 172 XGMAC_UCADDR = (1 << 4), 173 XGMAC_MCADDRS = (1 << 5), 174 175 XGMAC_ALL = 0xffff 176 }; 177 178 enum { 179 /* flags understood by begin_synchronized_op */ 180 HOLD_LOCK = (1 << 0), 181 SLEEP_OK = (1 << 1), 182 INTR_OK = (1 << 2), 183 184 /* flags understood by end_synchronized_op */ 185 LOCK_HELD = HOLD_LOCK, 186 }; 187 188 enum { 189 /* adapter flags */ 190 FULL_INIT_DONE = (1 << 0), 191 FW_OK = (1 << 1), 192 /* INTR_DIRECT = (1 << 2), No longer used. */ 193 MASTER_PF = (1 << 3), 194 ADAP_SYSCTL_CTX = (1 << 4), 195 /* TOM_INIT_DONE= (1 << 5), No longer used */ 196 BUF_PACKING_OK = (1 << 6), 197 198 CXGBE_BUSY = (1 << 9), 199 200 /* port flags */ 201 DOOMED = (1 << 0), 202 PORT_INIT_DONE = (1 << 1), 203 PORT_SYSCTL_CTX = (1 << 2), 204 HAS_TRACEQ = (1 << 3), 205 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 206 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 207 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */ 208 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ), 209 }; 210 211 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 212 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 213 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 214 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 215 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 216 217 struct port_info { 218 device_t dev; 219 struct adapter *adapter; 220 221 struct ifnet *ifp; 222 struct ifmedia media; 223 224 struct mtx pi_lock; 225 char lockname[16]; 226 unsigned long flags; 227 int if_flags; 228 229 uint16_t *rss; 230 uint16_t viid; 231 int16_t xact_addr_filt;/* index of exact MAC address filter */ 232 uint16_t rss_size; /* size of VI's RSS table slice */ 233 uint8_t lport; /* associated offload logical port */ 234 int8_t mdio_addr; 235 uint8_t port_type; 236 uint8_t mod_type; 237 uint8_t port_id; 238 uint8_t tx_chan; 239 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 240 241 /* These need to be int as they are used in sysctl */ 242 int ntxq; /* # of tx queues */ 243 int first_txq; /* index of first tx queue */ 244 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 245 int nrxq; /* # of rx queues */ 246 int first_rxq; /* index of first rx queue */ 247 #ifdef TCP_OFFLOAD 248 int nofldtxq; /* # of offload tx queues */ 249 int first_ofld_txq; /* index of first offload tx queue */ 250 int nofldrxq; /* # of offload rx queues */ 251 int first_ofld_rxq; /* index of first offload rx queue */ 252 #endif 253 #ifdef DEV_NETMAP 254 int nnmtxq; /* # of netmap tx queues */ 255 int first_nm_txq; /* index of first netmap tx queue */ 256 int nnmrxq; /* # of netmap rx queues */ 257 int first_nm_rxq; /* index of first netmap rx queue */ 258 259 struct ifnet *nm_ifp; 260 struct ifmedia nm_media; 261 int nmif_flags; 262 uint16_t nm_viid; 263 int16_t nm_xact_addr_filt; 264 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */ 265 #endif 266 int tmr_idx; 267 int pktc_idx; 268 int qsize_rxq; 269 int qsize_txq; 270 271 int linkdnrc; 272 struct link_config link_cfg; 273 274 struct timeval last_refreshed; 275 struct port_stats stats; 276 u_int tnl_cong_drops; 277 u_int tx_parse_error; 278 279 eventhandler_tag vlan_c; 280 281 struct callout tick; 282 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 283 284 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 285 }; 286 287 /* Where the cluster came from, how it has been carved up. */ 288 struct cluster_layout { 289 int8_t zidx; 290 int8_t hwidx; 291 uint16_t region1; /* mbufs laid out within this region */ 292 /* region2 is the DMA region */ 293 uint16_t region3; /* cluster_metadata within this region */ 294 }; 295 296 struct cluster_metadata { 297 u_int refcount; 298 #ifdef INVARIANTS 299 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 300 #endif 301 }; 302 303 struct fl_sdesc { 304 caddr_t cl; 305 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 306 struct cluster_layout cll; 307 }; 308 309 struct tx_desc { 310 __be64 flit[8]; 311 }; 312 313 struct tx_sdesc { 314 struct mbuf *m; /* m_nextpkt linked chain of frames */ 315 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 316 }; 317 318 319 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 320 struct iq_desc { 321 struct rss_header rss; 322 uint8_t cpl[IQ_PAD]; 323 struct rsp_ctrl rsp; 324 }; 325 #undef IQ_PAD 326 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 327 328 enum { 329 /* iq flags */ 330 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 331 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 332 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 333 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 334 335 /* iq state */ 336 IQS_DISABLED = 0, 337 IQS_BUSY = 1, 338 IQS_IDLE = 2, 339 }; 340 341 /* 342 * Ingress Queue: T4 is producer, driver is consumer. 343 */ 344 struct sge_iq { 345 uint32_t flags; 346 volatile int state; 347 struct adapter *adapter; 348 struct iq_desc *desc; /* KVA of descriptor ring */ 349 int8_t intr_pktc_idx; /* packet count threshold index */ 350 uint8_t gen; /* generation bit */ 351 uint8_t intr_params; /* interrupt holdoff parameters */ 352 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 353 uint16_t qsize; /* size (# of entries) of the queue */ 354 uint16_t sidx; /* index of the entry with the status page */ 355 uint16_t cidx; /* consumer index */ 356 uint16_t cntxt_id; /* SGE context id for the iq */ 357 uint16_t abs_id; /* absolute SGE id for the iq */ 358 359 STAILQ_ENTRY(sge_iq) link; 360 361 bus_dma_tag_t desc_tag; 362 bus_dmamap_t desc_map; 363 bus_addr_t ba; /* bus address of descriptor ring */ 364 }; 365 366 enum { 367 EQ_CTRL = 1, 368 EQ_ETH = 2, 369 EQ_OFLD = 3, 370 371 /* eq flags */ 372 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 373 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 374 EQ_ENABLED = (1 << 3), /* open for business */ 375 }; 376 377 /* Listed in order of preference. Update t4_sysctls too if you change these */ 378 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 379 380 /* 381 * Egress Queue: driver is producer, T4 is consumer. 382 * 383 * Note: A free list is an egress queue (driver produces the buffers and T4 384 * consumes them) but it's special enough to have its own struct (see sge_fl). 385 */ 386 struct sge_eq { 387 unsigned int flags; /* MUST be first */ 388 unsigned int cntxt_id; /* SGE context id for the eq */ 389 struct mtx eq_lock; 390 391 struct tx_desc *desc; /* KVA of descriptor ring */ 392 uint16_t doorbells; 393 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 394 u_int udb_qid; /* relative qid within the doorbell page */ 395 uint16_t sidx; /* index of the entry with the status page */ 396 uint16_t cidx; /* consumer idx (desc idx) */ 397 uint16_t pidx; /* producer idx (desc idx) */ 398 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 399 uint16_t dbidx; /* pidx of the most recent doorbell */ 400 uint16_t iqid; /* iq that gets egr_update for the eq */ 401 uint8_t tx_chan; /* tx channel used by the eq */ 402 volatile u_int equiq; /* EQUIQ outstanding */ 403 404 bus_dma_tag_t desc_tag; 405 bus_dmamap_t desc_map; 406 bus_addr_t ba; /* bus address of descriptor ring */ 407 char lockname[16]; 408 }; 409 410 struct sw_zone_info { 411 uma_zone_t zone; /* zone that this cluster comes from */ 412 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 413 int type; /* EXT_xxx type of the cluster */ 414 int8_t head_hwidx; 415 int8_t tail_hwidx; 416 }; 417 418 struct hw_buf_info { 419 int8_t zidx; /* backpointer to zone; -ve means unused */ 420 int8_t next; /* next hwidx for this zone; -1 means no more */ 421 int size; 422 }; 423 424 enum { 425 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 426 FL_DOOMED = (1 << 1), /* about to be destroyed */ 427 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 428 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 429 }; 430 431 #define FL_RUNNING_LOW(fl) \ 432 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 433 #define FL_NOT_RUNNING_LOW(fl) \ 434 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 435 436 struct sge_fl { 437 struct mtx fl_lock; 438 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 439 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 440 struct cluster_layout cll_def; /* default refill zone, layout */ 441 uint16_t lowat; /* # of buffers <= this means fl needs help */ 442 int flags; 443 uint16_t buf_boundary; 444 445 /* The 16b idx all deal with hw descriptors */ 446 uint16_t dbidx; /* hw pidx after last doorbell */ 447 uint16_t sidx; /* index of status page */ 448 volatile uint16_t hw_cidx; 449 450 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 451 uint32_t cidx; /* consumer index */ 452 uint32_t pidx; /* producer index */ 453 454 uint32_t dbval; 455 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 456 volatile uint32_t *udb; 457 458 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 459 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 460 uint64_t cl_allocated; /* # of clusters allocated */ 461 uint64_t cl_recycled; /* # of clusters recycled */ 462 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 463 464 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 465 struct mbuf *m0; 466 struct mbuf **pnext; 467 u_int remaining; 468 469 uint16_t qsize; /* # of hw descriptors (status page included) */ 470 uint16_t cntxt_id; /* SGE context id for the freelist */ 471 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 472 bus_dma_tag_t desc_tag; 473 bus_dmamap_t desc_map; 474 char lockname[16]; 475 bus_addr_t ba; /* bus address of descriptor ring */ 476 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 477 }; 478 479 struct mp_ring; 480 481 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 482 struct sge_txq { 483 struct sge_eq eq; /* MUST be first */ 484 485 struct ifnet *ifp; /* the interface this txq belongs to */ 486 struct mp_ring *r; /* tx software ring */ 487 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 488 struct sglist *gl; 489 __be32 cpl_ctrl0; /* for convenience */ 490 491 struct task tx_reclaim_task; 492 /* stats for common events first */ 493 494 uint64_t txcsum; /* # of times hardware assisted with checksum */ 495 uint64_t tso_wrs; /* # of TSO work requests */ 496 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 497 uint64_t imm_wrs; /* # of work requests with immediate data */ 498 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 499 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 500 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 501 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 502 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 503 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 504 505 /* stats for not-that-common events */ 506 } __aligned(CACHE_LINE_SIZE); 507 508 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 509 struct sge_rxq { 510 struct sge_iq iq; /* MUST be first */ 511 struct sge_fl fl; /* MUST follow iq */ 512 513 struct ifnet *ifp; /* the interface this rxq belongs to */ 514 #if defined(INET) || defined(INET6) 515 struct lro_ctrl lro; /* LRO state */ 516 #endif 517 518 /* stats for common events first */ 519 520 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 521 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 522 523 /* stats for not-that-common events */ 524 525 } __aligned(CACHE_LINE_SIZE); 526 527 static inline struct sge_rxq * 528 iq_to_rxq(struct sge_iq *iq) 529 { 530 531 return (__containerof(iq, struct sge_rxq, iq)); 532 } 533 534 535 #ifdef TCP_OFFLOAD 536 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 537 struct sge_ofld_rxq { 538 struct sge_iq iq; /* MUST be first */ 539 struct sge_fl fl; /* MUST follow iq */ 540 } __aligned(CACHE_LINE_SIZE); 541 542 static inline struct sge_ofld_rxq * 543 iq_to_ofld_rxq(struct sge_iq *iq) 544 { 545 546 return (__containerof(iq, struct sge_ofld_rxq, iq)); 547 } 548 #endif 549 550 struct wrqe { 551 STAILQ_ENTRY(wrqe) link; 552 struct sge_wrq *wrq; 553 int wr_len; 554 char wr[] __aligned(16); 555 }; 556 557 struct wrq_cookie { 558 TAILQ_ENTRY(wrq_cookie) link; 559 int ndesc; 560 int pidx; 561 }; 562 563 /* 564 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 565 * and offload tx queues are of this type. 566 */ 567 struct sge_wrq { 568 struct sge_eq eq; /* MUST be first */ 569 570 struct adapter *adapter; 571 struct task wrq_tx_task; 572 573 /* Tx desc reserved but WR not "committed" yet. */ 574 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 575 576 /* List of WRs ready to go out as soon as descriptors are available. */ 577 STAILQ_HEAD(, wrqe) wr_list; 578 u_int nwr_pending; 579 u_int ndesc_needed; 580 581 /* stats for common events first */ 582 583 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 584 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 585 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 586 587 /* stats for not-that-common events */ 588 589 /* 590 * Scratch space for work requests that wrap around after reaching the 591 * status page, and some infomation about the last WR that used it. 592 */ 593 uint16_t ss_pidx; 594 uint16_t ss_len; 595 uint8_t ss[SGE_MAX_WR_LEN]; 596 597 } __aligned(CACHE_LINE_SIZE); 598 599 600 #ifdef DEV_NETMAP 601 struct sge_nm_rxq { 602 struct port_info *pi; 603 604 struct iq_desc *iq_desc; 605 uint16_t iq_abs_id; 606 uint16_t iq_cntxt_id; 607 uint16_t iq_cidx; 608 uint16_t iq_sidx; 609 uint8_t iq_gen; 610 611 __be64 *fl_desc; 612 uint16_t fl_cntxt_id; 613 uint32_t fl_cidx; 614 uint32_t fl_pidx; 615 uint32_t fl_sidx; 616 uint32_t fl_db_val; 617 u_int fl_hwidx:4; 618 619 u_int nid; /* netmap ring # for this queue */ 620 621 /* infrequently used items after this */ 622 623 bus_dma_tag_t iq_desc_tag; 624 bus_dmamap_t iq_desc_map; 625 bus_addr_t iq_ba; 626 int intr_idx; 627 628 bus_dma_tag_t fl_desc_tag; 629 bus_dmamap_t fl_desc_map; 630 bus_addr_t fl_ba; 631 } __aligned(CACHE_LINE_SIZE); 632 633 struct sge_nm_txq { 634 struct tx_desc *desc; 635 uint16_t cidx; 636 uint16_t pidx; 637 uint16_t sidx; 638 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 639 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 640 uint16_t dbidx; /* pidx of the most recent doorbell */ 641 uint16_t doorbells; 642 volatile uint32_t *udb; 643 u_int udb_qid; 644 u_int cntxt_id; 645 __be32 cpl_ctrl0; /* for convenience */ 646 u_int nid; /* netmap ring # for this queue */ 647 648 /* infrequently used items after this */ 649 650 bus_dma_tag_t desc_tag; 651 bus_dmamap_t desc_map; 652 bus_addr_t ba; 653 int iqidx; 654 } __aligned(CACHE_LINE_SIZE); 655 #endif 656 657 struct sge { 658 int timer_val[SGE_NTIMERS]; 659 int counter_val[SGE_NCOUNTERS]; 660 int fl_starve_threshold; 661 int fl_starve_threshold2; 662 int eq_s_qpp; 663 int iq_s_qpp; 664 665 int nrxq; /* total # of Ethernet rx queues */ 666 int ntxq; /* total # of Ethernet tx tx queues */ 667 #ifdef TCP_OFFLOAD 668 int nofldrxq; /* total # of TOE rx queues */ 669 int nofldtxq; /* total # of TOE tx queues */ 670 #endif 671 #ifdef DEV_NETMAP 672 int nnmrxq; /* total # of netmap rx queues */ 673 int nnmtxq; /* total # of netmap tx queues */ 674 #endif 675 int niq; /* total # of ingress queues */ 676 int neq; /* total # of egress queues */ 677 678 struct sge_iq fwq; /* Firmware event queue */ 679 struct sge_wrq mgmtq; /* Management queue (control queue) */ 680 struct sge_wrq *ctrlq; /* Control queues */ 681 struct sge_txq *txq; /* NIC tx queues */ 682 struct sge_rxq *rxq; /* NIC rx queues */ 683 #ifdef TCP_OFFLOAD 684 struct sge_wrq *ofld_txq; /* TOE tx queues */ 685 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 686 #endif 687 #ifdef DEV_NETMAP 688 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 689 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 690 #endif 691 692 uint16_t iq_start; 693 int eq_start; 694 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 695 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 696 697 int pad_boundary; 698 int pack_boundary; 699 int8_t safe_hwidx1; /* may not have room for metadata */ 700 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 701 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 702 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 703 }; 704 705 struct rss_header; 706 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 707 struct mbuf *); 708 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 709 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 710 711 struct adapter { 712 SLIST_ENTRY(adapter) link; 713 device_t dev; 714 struct cdev *cdev; 715 716 /* PCIe register resources */ 717 int regs_rid; 718 struct resource *regs_res; 719 int msix_rid; 720 struct resource *msix_res; 721 bus_space_handle_t bh; 722 bus_space_tag_t bt; 723 bus_size_t mmio_len; 724 int udbs_rid; 725 struct resource *udbs_res; 726 volatile uint8_t *udbs_base; 727 728 unsigned int pf; 729 unsigned int mbox; 730 731 /* Interrupt information */ 732 int intr_type; 733 int intr_count; 734 struct irq { 735 struct resource *res; 736 int rid; 737 void *tag; 738 } *irq; 739 740 bus_dma_tag_t dmat; /* Parent DMA tag */ 741 742 struct sge sge; 743 int lro_timeout; 744 745 struct taskqueue *tq[NCHAN]; /* General purpose taskqueues */ 746 struct port_info *port[MAX_NPORTS]; 747 uint8_t chan_map[NCHAN]; 748 749 #ifdef TCP_OFFLOAD 750 void *tom_softc; /* (struct tom_data *) */ 751 struct tom_tunables tt; 752 void *iwarp_softc; /* (struct c4iw_dev *) */ 753 void *iscsi_softc; 754 #endif 755 struct l2t_data *l2t; /* L2 table */ 756 struct tid_info tids; 757 758 uint16_t doorbells; 759 int open_device_map; 760 #ifdef TCP_OFFLOAD 761 int offload_map; /* ports with IFCAP_TOE enabled */ 762 int active_ulds; /* ULDs activated on this adapter */ 763 #endif 764 int flags; 765 766 char ifp_lockname[16]; 767 struct mtx ifp_lock; 768 struct ifnet *ifp; /* tracer ifp */ 769 struct ifmedia media; 770 int traceq; /* iq used by all tracers, -1 if none */ 771 int tracer_valid; /* bitmap of valid tracers */ 772 int tracer_enabled; /* bitmap of enabled tracers */ 773 774 char fw_version[32]; 775 char cfg_file[32]; 776 u_int cfcsum; 777 struct adapter_params params; 778 struct t4_virt_res vres; 779 780 uint16_t linkcaps; 781 uint16_t niccaps; 782 uint16_t toecaps; 783 uint16_t rdmacaps; 784 uint16_t iscsicaps; 785 uint16_t fcoecaps; 786 787 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 788 789 struct mtx sc_lock; 790 char lockname[16]; 791 792 /* Starving free lists */ 793 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 794 TAILQ_HEAD(, sge_fl) sfl; 795 struct callout sfl_callout; 796 797 struct mtx regwin_lock; /* for indirect reads and memory windows */ 798 799 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 800 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 801 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 802 803 #ifdef INVARIANTS 804 const char *last_op; 805 const void *last_op_thr; 806 #endif 807 808 int sc_do_rxcopy; 809 }; 810 811 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 812 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 813 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 814 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 815 816 #define ASSERT_SYNCHRONIZED_OP(sc) \ 817 KASSERT(IS_BUSY(sc) && \ 818 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 819 ("%s: operation not synchronized.", __func__)) 820 821 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 822 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 823 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 824 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 825 826 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 827 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 828 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 829 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 830 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 831 832 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 833 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 834 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 835 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 836 837 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 838 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 839 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 840 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 841 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 842 843 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 844 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 845 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 846 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 847 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 848 849 #define for_each_txq(pi, iter, q) \ 850 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 851 iter < pi->ntxq; ++iter, ++q) 852 #define for_each_rxq(pi, iter, q) \ 853 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 854 iter < pi->nrxq; ++iter, ++q) 855 #define for_each_ofld_txq(pi, iter, q) \ 856 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 857 iter < pi->nofldtxq; ++iter, ++q) 858 #define for_each_ofld_rxq(pi, iter, q) \ 859 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 860 iter < pi->nofldrxq; ++iter, ++q) 861 #define for_each_nm_txq(pi, iter, q) \ 862 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \ 863 iter < pi->nnmtxq; ++iter, ++q) 864 #define for_each_nm_rxq(pi, iter, q) \ 865 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \ 866 iter < pi->nnmrxq; ++iter, ++q) 867 868 #define IDXINCR(idx, incr, wrap) do { \ 869 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 870 } while (0) 871 #define IDXDIFF(head, tail, wrap) \ 872 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 873 874 /* One for errors, one for firmware events */ 875 #define T4_EXTRA_INTR 2 876 877 static inline uint32_t 878 t4_read_reg(struct adapter *sc, uint32_t reg) 879 { 880 881 return bus_space_read_4(sc->bt, sc->bh, reg); 882 } 883 884 static inline void 885 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 886 { 887 888 bus_space_write_4(sc->bt, sc->bh, reg, val); 889 } 890 891 static inline uint64_t 892 t4_read_reg64(struct adapter *sc, uint32_t reg) 893 { 894 895 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 896 } 897 898 static inline void 899 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 900 { 901 902 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 903 } 904 905 static inline void 906 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 907 { 908 909 *val = pci_read_config(sc->dev, reg, 1); 910 } 911 912 static inline void 913 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 914 { 915 916 pci_write_config(sc->dev, reg, val, 1); 917 } 918 919 static inline void 920 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 921 { 922 923 *val = pci_read_config(sc->dev, reg, 2); 924 } 925 926 static inline void 927 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 928 { 929 930 pci_write_config(sc->dev, reg, val, 2); 931 } 932 933 static inline void 934 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 935 { 936 937 *val = pci_read_config(sc->dev, reg, 4); 938 } 939 940 static inline void 941 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 942 { 943 944 pci_write_config(sc->dev, reg, val, 4); 945 } 946 947 static inline struct port_info * 948 adap2pinfo(struct adapter *sc, int idx) 949 { 950 951 return (sc->port[idx]); 952 } 953 954 static inline void 955 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 956 { 957 958 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 959 } 960 961 static inline bool 962 is_10G_port(const struct port_info *pi) 963 { 964 965 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 966 } 967 968 static inline bool 969 is_40G_port(const struct port_info *pi) 970 { 971 972 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 973 } 974 975 static inline int 976 tx_resume_threshold(struct sge_eq *eq) 977 { 978 979 /* not quite the same as qsize / 4, but this will do. */ 980 return (eq->sidx / 4); 981 } 982 983 /* t4_main.c */ 984 int t4_os_find_pci_capability(struct adapter *, int); 985 int t4_os_pci_save_state(struct adapter *); 986 int t4_os_pci_restore_state(struct adapter *); 987 void t4_os_portmod_changed(const struct adapter *, int); 988 void t4_os_link_changed(struct adapter *, int, int, int); 989 void t4_iterate(void (*)(struct adapter *, void *), void *); 990 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 991 int t4_register_an_handler(struct adapter *, an_handler_t); 992 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 993 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 994 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 995 void end_synchronized_op(struct adapter *, int); 996 int update_mac_settings(struct ifnet *, int); 997 int adapter_full_init(struct adapter *); 998 int adapter_full_uninit(struct adapter *); 999 int port_full_init(struct port_info *); 1000 int port_full_uninit(struct port_info *); 1001 1002 #ifdef DEV_NETMAP 1003 /* t4_netmap.c */ 1004 int create_netmap_ifnet(struct port_info *); 1005 int destroy_netmap_ifnet(struct port_info *); 1006 void t4_nm_intr(void *); 1007 #endif 1008 1009 /* t4_sge.c */ 1010 void t4_sge_modload(void); 1011 void t4_sge_modunload(void); 1012 uint64_t t4_sge_extfree_refs(void); 1013 void t4_init_sge_cpl_handlers(struct adapter *); 1014 void t4_tweak_chip_settings(struct adapter *); 1015 int t4_read_chip_settings(struct adapter *); 1016 int t4_create_dma_tag(struct adapter *); 1017 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1018 struct sysctl_oid_list *); 1019 int t4_destroy_dma_tag(struct adapter *); 1020 int t4_setup_adapter_queues(struct adapter *); 1021 int t4_teardown_adapter_queues(struct adapter *); 1022 int t4_setup_port_queues(struct port_info *); 1023 int t4_teardown_port_queues(struct port_info *); 1024 void t4_intr_all(void *); 1025 void t4_intr(void *); 1026 void t4_intr_err(void *); 1027 void t4_intr_evt(void *); 1028 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1029 void t4_update_fl_bufsize(struct ifnet *); 1030 int parse_pkt(struct mbuf **); 1031 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1032 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1033 1034 /* t4_tracer.c */ 1035 struct t4_tracer; 1036 void t4_tracer_modload(void); 1037 void t4_tracer_modunload(void); 1038 void t4_tracer_port_detach(struct adapter *); 1039 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1040 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1041 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1042 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1043 1044 static inline struct wrqe * 1045 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1046 { 1047 int len = offsetof(struct wrqe, wr) + wr_len; 1048 struct wrqe *wr; 1049 1050 wr = malloc(len, M_CXGBE, M_NOWAIT); 1051 if (__predict_false(wr == NULL)) 1052 return (NULL); 1053 wr->wr_len = wr_len; 1054 wr->wrq = wrq; 1055 return (wr); 1056 } 1057 1058 static inline void * 1059 wrtod(struct wrqe *wr) 1060 { 1061 return (&wr->wr[0]); 1062 } 1063 1064 static inline void 1065 free_wrqe(struct wrqe *wr) 1066 { 1067 free(wr, M_CXGBE); 1068 } 1069 1070 static inline void 1071 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1072 { 1073 struct sge_wrq *wrq = wr->wrq; 1074 1075 TXQ_LOCK(wrq); 1076 t4_wrq_tx_locked(sc, wrq, wr); 1077 TXQ_UNLOCK(wrq); 1078 } 1079 1080 #endif 1081