1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "common/t4_msg.h" 58 #include "firmware/t4fw_interface.h" 59 60 #define KTR_CXGBE KTR_SPARE3 61 MALLOC_DECLARE(M_CXGBE); 62 #define CXGBE_UNIMPLEMENTED(s) \ 63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 64 65 #if defined(__i386__) || defined(__amd64__) 66 static __inline void 67 prefetch(void *x) 68 { 69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 70 } 71 #else 72 #define prefetch(x) 73 #endif 74 75 #ifndef SYSCTL_ADD_UQUAD 76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 77 #define sysctl_handle_64 sysctl_handle_quad 78 #define CTLTYPE_U64 CTLTYPE_QUAD 79 #endif 80 81 #if (__FreeBSD_version >= 900030) || \ 82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 83 #define SBUF_DRAIN 1 84 #endif 85 86 #ifdef __amd64__ 87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 88 static __inline uint64_t 89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 90 bus_size_t offset) 91 { 92 KASSERT(tag == X86_BUS_SPACE_MEM, 93 ("%s: can only handle mem space", __func__)); 94 95 return (*(volatile uint64_t *)(handle + offset)); 96 } 97 98 static __inline void 99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 100 bus_size_t offset, uint64_t value) 101 { 102 KASSERT(tag == X86_BUS_SPACE_MEM, 103 ("%s: can only handle mem space", __func__)); 104 105 *(volatile uint64_t *)(bsh + offset) = value; 106 } 107 #else 108 static __inline uint64_t 109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 110 bus_size_t offset) 111 { 112 return (uint64_t)bus_space_read_4(tag, handle, offset) + 113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 114 } 115 116 static __inline void 117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 118 bus_size_t offset, uint64_t value) 119 { 120 bus_space_write_4(tag, bsh, offset, value); 121 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 122 } 123 #endif 124 125 struct adapter; 126 typedef struct adapter adapter_t; 127 128 enum { 129 /* 130 * All ingress queues use this entry size. Note that the firmware event 131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 132 * be at least 64. 133 */ 134 IQ_ESIZE = 64, 135 136 /* Default queue sizes for all kinds of ingress queues */ 137 FW_IQ_QSIZE = 256, 138 RX_IQ_QSIZE = 1024, 139 140 /* All egress queues use this entry size */ 141 EQ_ESIZE = 64, 142 143 /* Default queue sizes for all kinds of egress queues */ 144 CTRL_EQ_QSIZE = 128, 145 TX_EQ_QSIZE = 1024, 146 147 #if MJUMPAGESIZE != MCLBYTES 148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 149 #else 150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 151 #endif 152 CL_METADATA_SIZE = CACHE_LINE_SIZE, 153 154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 155 TX_SGL_SEGS = 39, 156 TX_SGL_SEGS_TSO = 38, 157 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 158 }; 159 160 enum { 161 /* adapter intr_type */ 162 INTR_INTX = (1 << 0), 163 INTR_MSI = (1 << 1), 164 INTR_MSIX = (1 << 2) 165 }; 166 167 enum { 168 XGMAC_MTU = (1 << 0), 169 XGMAC_PROMISC = (1 << 1), 170 XGMAC_ALLMULTI = (1 << 2), 171 XGMAC_VLANEX = (1 << 3), 172 XGMAC_UCADDR = (1 << 4), 173 XGMAC_MCADDRS = (1 << 5), 174 175 XGMAC_ALL = 0xffff 176 }; 177 178 enum { 179 /* flags understood by begin_synchronized_op */ 180 HOLD_LOCK = (1 << 0), 181 SLEEP_OK = (1 << 1), 182 INTR_OK = (1 << 2), 183 184 /* flags understood by end_synchronized_op */ 185 LOCK_HELD = HOLD_LOCK, 186 }; 187 188 enum { 189 /* adapter flags */ 190 FULL_INIT_DONE = (1 << 0), 191 FW_OK = (1 << 1), 192 /* INTR_DIRECT = (1 << 2), No longer used. */ 193 MASTER_PF = (1 << 3), 194 ADAP_SYSCTL_CTX = (1 << 4), 195 /* TOM_INIT_DONE= (1 << 5), No longer used */ 196 BUF_PACKING_OK = (1 << 6), 197 198 CXGBE_BUSY = (1 << 9), 199 200 /* port flags */ 201 DOOMED = (1 << 0), 202 PORT_INIT_DONE = (1 << 1), 203 PORT_SYSCTL_CTX = (1 << 2), 204 HAS_TRACEQ = (1 << 3), 205 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 206 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 207 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */ 208 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ), 209 210 /* adapter debug_flags */ 211 DF_DUMP_MBOX = (1 << 0), 212 }; 213 214 #define IS_DOOMED(pi) ((pi)->flags & DOOMED) 215 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0) 216 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 217 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 218 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 219 220 struct port_info { 221 device_t dev; 222 struct adapter *adapter; 223 224 struct ifnet *ifp; 225 struct ifmedia media; 226 227 struct mtx pi_lock; 228 char lockname[16]; 229 unsigned long flags; 230 int if_flags; 231 232 uint16_t *rss; 233 uint16_t viid; 234 int16_t xact_addr_filt;/* index of exact MAC address filter */ 235 uint16_t rss_size; /* size of VI's RSS table slice */ 236 uint16_t rss_base; /* start of VI's RSS table slice */ 237 uint8_t lport; /* associated offload logical port */ 238 int8_t mdio_addr; 239 uint8_t port_type; 240 uint8_t mod_type; 241 uint8_t port_id; 242 uint8_t tx_chan; 243 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 244 245 /* These need to be int as they are used in sysctl */ 246 int ntxq; /* # of tx queues */ 247 int first_txq; /* index of first tx queue */ 248 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 249 int nrxq; /* # of rx queues */ 250 int first_rxq; /* index of first rx queue */ 251 #ifdef TCP_OFFLOAD 252 int nofldtxq; /* # of offload tx queues */ 253 int first_ofld_txq; /* index of first offload tx queue */ 254 int nofldrxq; /* # of offload rx queues */ 255 int first_ofld_rxq; /* index of first offload rx queue */ 256 #endif 257 #ifdef DEV_NETMAP 258 int nnmtxq; /* # of netmap tx queues */ 259 int first_nm_txq; /* index of first netmap tx queue */ 260 int nnmrxq; /* # of netmap rx queues */ 261 int first_nm_rxq; /* index of first netmap rx queue */ 262 263 struct ifnet *nm_ifp; 264 struct ifmedia nm_media; 265 int nmif_flags; 266 uint16_t nm_viid; 267 int16_t nm_xact_addr_filt; 268 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */ 269 #endif 270 int tmr_idx; 271 int pktc_idx; 272 int qsize_rxq; 273 int qsize_txq; 274 275 int linkdnrc; 276 struct link_config link_cfg; 277 278 struct timeval last_refreshed; 279 struct port_stats stats; 280 u_int tnl_cong_drops; 281 u_int tx_parse_error; 282 283 eventhandler_tag vlan_c; 284 285 struct callout tick; 286 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 287 288 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 289 }; 290 291 /* Where the cluster came from, how it has been carved up. */ 292 struct cluster_layout { 293 int8_t zidx; 294 int8_t hwidx; 295 uint16_t region1; /* mbufs laid out within this region */ 296 /* region2 is the DMA region */ 297 uint16_t region3; /* cluster_metadata within this region */ 298 }; 299 300 struct cluster_metadata { 301 u_int refcount; 302 #ifdef INVARIANTS 303 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 304 #endif 305 }; 306 307 struct fl_sdesc { 308 caddr_t cl; 309 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 310 struct cluster_layout cll; 311 }; 312 313 struct tx_desc { 314 __be64 flit[8]; 315 }; 316 317 struct tx_sdesc { 318 struct mbuf *m; /* m_nextpkt linked chain of frames */ 319 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 320 }; 321 322 323 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 324 struct iq_desc { 325 struct rss_header rss; 326 uint8_t cpl[IQ_PAD]; 327 struct rsp_ctrl rsp; 328 }; 329 #undef IQ_PAD 330 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 331 332 enum { 333 /* iq flags */ 334 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 335 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 336 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 337 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 338 339 /* iq state */ 340 IQS_DISABLED = 0, 341 IQS_BUSY = 1, 342 IQS_IDLE = 2, 343 }; 344 345 /* 346 * Ingress Queue: T4 is producer, driver is consumer. 347 */ 348 struct sge_iq { 349 uint32_t flags; 350 volatile int state; 351 struct adapter *adapter; 352 struct iq_desc *desc; /* KVA of descriptor ring */ 353 int8_t intr_pktc_idx; /* packet count threshold index */ 354 uint8_t gen; /* generation bit */ 355 uint8_t intr_params; /* interrupt holdoff parameters */ 356 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 357 uint16_t qsize; /* size (# of entries) of the queue */ 358 uint16_t sidx; /* index of the entry with the status page */ 359 uint16_t cidx; /* consumer index */ 360 uint16_t cntxt_id; /* SGE context id for the iq */ 361 uint16_t abs_id; /* absolute SGE id for the iq */ 362 363 STAILQ_ENTRY(sge_iq) link; 364 365 bus_dma_tag_t desc_tag; 366 bus_dmamap_t desc_map; 367 bus_addr_t ba; /* bus address of descriptor ring */ 368 }; 369 370 enum { 371 EQ_CTRL = 1, 372 EQ_ETH = 2, 373 EQ_OFLD = 3, 374 375 /* eq flags */ 376 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 377 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 378 EQ_ENABLED = (1 << 3), /* open for business */ 379 }; 380 381 /* Listed in order of preference. Update t4_sysctls too if you change these */ 382 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 383 384 /* 385 * Egress Queue: driver is producer, T4 is consumer. 386 * 387 * Note: A free list is an egress queue (driver produces the buffers and T4 388 * consumes them) but it's special enough to have its own struct (see sge_fl). 389 */ 390 struct sge_eq { 391 unsigned int flags; /* MUST be first */ 392 unsigned int cntxt_id; /* SGE context id for the eq */ 393 struct mtx eq_lock; 394 395 struct tx_desc *desc; /* KVA of descriptor ring */ 396 uint16_t doorbells; 397 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 398 u_int udb_qid; /* relative qid within the doorbell page */ 399 uint16_t sidx; /* index of the entry with the status page */ 400 uint16_t cidx; /* consumer idx (desc idx) */ 401 uint16_t pidx; /* producer idx (desc idx) */ 402 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 403 uint16_t dbidx; /* pidx of the most recent doorbell */ 404 uint16_t iqid; /* iq that gets egr_update for the eq */ 405 uint8_t tx_chan; /* tx channel used by the eq */ 406 volatile u_int equiq; /* EQUIQ outstanding */ 407 408 bus_dma_tag_t desc_tag; 409 bus_dmamap_t desc_map; 410 bus_addr_t ba; /* bus address of descriptor ring */ 411 char lockname[16]; 412 }; 413 414 struct sw_zone_info { 415 uma_zone_t zone; /* zone that this cluster comes from */ 416 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 417 int type; /* EXT_xxx type of the cluster */ 418 int8_t head_hwidx; 419 int8_t tail_hwidx; 420 }; 421 422 struct hw_buf_info { 423 int8_t zidx; /* backpointer to zone; -ve means unused */ 424 int8_t next; /* next hwidx for this zone; -1 means no more */ 425 int size; 426 }; 427 428 enum { 429 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 430 FL_DOOMED = (1 << 1), /* about to be destroyed */ 431 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 432 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 433 }; 434 435 #define FL_RUNNING_LOW(fl) \ 436 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 437 #define FL_NOT_RUNNING_LOW(fl) \ 438 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 439 440 struct sge_fl { 441 struct mtx fl_lock; 442 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 443 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 444 struct cluster_layout cll_def; /* default refill zone, layout */ 445 uint16_t lowat; /* # of buffers <= this means fl needs help */ 446 int flags; 447 uint16_t buf_boundary; 448 449 /* The 16b idx all deal with hw descriptors */ 450 uint16_t dbidx; /* hw pidx after last doorbell */ 451 uint16_t sidx; /* index of status page */ 452 volatile uint16_t hw_cidx; 453 454 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 455 uint32_t cidx; /* consumer index */ 456 uint32_t pidx; /* producer index */ 457 458 uint32_t dbval; 459 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 460 volatile uint32_t *udb; 461 462 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 463 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 464 uint64_t cl_allocated; /* # of clusters allocated */ 465 uint64_t cl_recycled; /* # of clusters recycled */ 466 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 467 468 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 469 struct mbuf *m0; 470 struct mbuf **pnext; 471 u_int remaining; 472 473 uint16_t qsize; /* # of hw descriptors (status page included) */ 474 uint16_t cntxt_id; /* SGE context id for the freelist */ 475 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 476 bus_dma_tag_t desc_tag; 477 bus_dmamap_t desc_map; 478 char lockname[16]; 479 bus_addr_t ba; /* bus address of descriptor ring */ 480 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 481 }; 482 483 struct mp_ring; 484 485 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 486 struct sge_txq { 487 struct sge_eq eq; /* MUST be first */ 488 489 struct ifnet *ifp; /* the interface this txq belongs to */ 490 struct mp_ring *r; /* tx software ring */ 491 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 492 struct sglist *gl; 493 __be32 cpl_ctrl0; /* for convenience */ 494 495 struct task tx_reclaim_task; 496 /* stats for common events first */ 497 498 uint64_t txcsum; /* # of times hardware assisted with checksum */ 499 uint64_t tso_wrs; /* # of TSO work requests */ 500 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 501 uint64_t imm_wrs; /* # of work requests with immediate data */ 502 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 503 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 504 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 505 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 506 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 507 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 508 509 /* stats for not-that-common events */ 510 } __aligned(CACHE_LINE_SIZE); 511 512 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 513 struct sge_rxq { 514 struct sge_iq iq; /* MUST be first */ 515 struct sge_fl fl; /* MUST follow iq */ 516 517 struct ifnet *ifp; /* the interface this rxq belongs to */ 518 #if defined(INET) || defined(INET6) 519 struct lro_ctrl lro; /* LRO state */ 520 #endif 521 522 /* stats for common events first */ 523 524 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 525 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 526 527 /* stats for not-that-common events */ 528 529 } __aligned(CACHE_LINE_SIZE); 530 531 static inline struct sge_rxq * 532 iq_to_rxq(struct sge_iq *iq) 533 { 534 535 return (__containerof(iq, struct sge_rxq, iq)); 536 } 537 538 539 #ifdef TCP_OFFLOAD 540 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 541 struct sge_ofld_rxq { 542 struct sge_iq iq; /* MUST be first */ 543 struct sge_fl fl; /* MUST follow iq */ 544 } __aligned(CACHE_LINE_SIZE); 545 546 static inline struct sge_ofld_rxq * 547 iq_to_ofld_rxq(struct sge_iq *iq) 548 { 549 550 return (__containerof(iq, struct sge_ofld_rxq, iq)); 551 } 552 #endif 553 554 struct wrqe { 555 STAILQ_ENTRY(wrqe) link; 556 struct sge_wrq *wrq; 557 int wr_len; 558 char wr[] __aligned(16); 559 }; 560 561 struct wrq_cookie { 562 TAILQ_ENTRY(wrq_cookie) link; 563 int ndesc; 564 int pidx; 565 }; 566 567 /* 568 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 569 * and offload tx queues are of this type. 570 */ 571 struct sge_wrq { 572 struct sge_eq eq; /* MUST be first */ 573 574 struct adapter *adapter; 575 struct task wrq_tx_task; 576 577 /* Tx desc reserved but WR not "committed" yet. */ 578 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 579 580 /* List of WRs ready to go out as soon as descriptors are available. */ 581 STAILQ_HEAD(, wrqe) wr_list; 582 u_int nwr_pending; 583 u_int ndesc_needed; 584 585 /* stats for common events first */ 586 587 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 588 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 589 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 590 591 /* stats for not-that-common events */ 592 593 /* 594 * Scratch space for work requests that wrap around after reaching the 595 * status page, and some infomation about the last WR that used it. 596 */ 597 uint16_t ss_pidx; 598 uint16_t ss_len; 599 uint8_t ss[SGE_MAX_WR_LEN]; 600 601 } __aligned(CACHE_LINE_SIZE); 602 603 604 #ifdef DEV_NETMAP 605 struct sge_nm_rxq { 606 struct port_info *pi; 607 608 struct iq_desc *iq_desc; 609 uint16_t iq_abs_id; 610 uint16_t iq_cntxt_id; 611 uint16_t iq_cidx; 612 uint16_t iq_sidx; 613 uint8_t iq_gen; 614 615 __be64 *fl_desc; 616 uint16_t fl_cntxt_id; 617 uint32_t fl_cidx; 618 uint32_t fl_pidx; 619 uint32_t fl_sidx; 620 uint32_t fl_db_val; 621 u_int fl_hwidx:4; 622 623 u_int nid; /* netmap ring # for this queue */ 624 625 /* infrequently used items after this */ 626 627 bus_dma_tag_t iq_desc_tag; 628 bus_dmamap_t iq_desc_map; 629 bus_addr_t iq_ba; 630 int intr_idx; 631 632 bus_dma_tag_t fl_desc_tag; 633 bus_dmamap_t fl_desc_map; 634 bus_addr_t fl_ba; 635 } __aligned(CACHE_LINE_SIZE); 636 637 struct sge_nm_txq { 638 struct tx_desc *desc; 639 uint16_t cidx; 640 uint16_t pidx; 641 uint16_t sidx; 642 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 643 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 644 uint16_t dbidx; /* pidx of the most recent doorbell */ 645 uint16_t doorbells; 646 volatile uint32_t *udb; 647 u_int udb_qid; 648 u_int cntxt_id; 649 __be32 cpl_ctrl0; /* for convenience */ 650 u_int nid; /* netmap ring # for this queue */ 651 652 /* infrequently used items after this */ 653 654 bus_dma_tag_t desc_tag; 655 bus_dmamap_t desc_map; 656 bus_addr_t ba; 657 int iqidx; 658 } __aligned(CACHE_LINE_SIZE); 659 #endif 660 661 struct sge { 662 int timer_val[SGE_NTIMERS]; 663 int counter_val[SGE_NCOUNTERS]; 664 int fl_starve_threshold; 665 int fl_starve_threshold2; 666 int eq_s_qpp; 667 int iq_s_qpp; 668 669 int nrxq; /* total # of Ethernet rx queues */ 670 int ntxq; /* total # of Ethernet tx tx queues */ 671 #ifdef TCP_OFFLOAD 672 int nofldrxq; /* total # of TOE rx queues */ 673 int nofldtxq; /* total # of TOE tx queues */ 674 #endif 675 #ifdef DEV_NETMAP 676 int nnmrxq; /* total # of netmap rx queues */ 677 int nnmtxq; /* total # of netmap tx queues */ 678 #endif 679 int niq; /* total # of ingress queues */ 680 int neq; /* total # of egress queues */ 681 682 struct sge_iq fwq; /* Firmware event queue */ 683 struct sge_wrq mgmtq; /* Management queue (control queue) */ 684 struct sge_wrq *ctrlq; /* Control queues */ 685 struct sge_txq *txq; /* NIC tx queues */ 686 struct sge_rxq *rxq; /* NIC rx queues */ 687 #ifdef TCP_OFFLOAD 688 struct sge_wrq *ofld_txq; /* TOE tx queues */ 689 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 690 #endif 691 #ifdef DEV_NETMAP 692 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 693 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 694 #endif 695 696 uint16_t iq_start; 697 int eq_start; 698 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 699 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 700 701 int pad_boundary; 702 int pack_boundary; 703 int8_t safe_hwidx1; /* may not have room for metadata */ 704 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 705 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 706 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 707 }; 708 709 struct rss_header; 710 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 711 struct mbuf *); 712 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 713 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 714 715 struct adapter { 716 SLIST_ENTRY(adapter) link; 717 device_t dev; 718 struct cdev *cdev; 719 720 /* PCIe register resources */ 721 int regs_rid; 722 struct resource *regs_res; 723 int msix_rid; 724 struct resource *msix_res; 725 bus_space_handle_t bh; 726 bus_space_tag_t bt; 727 bus_size_t mmio_len; 728 int udbs_rid; 729 struct resource *udbs_res; 730 volatile uint8_t *udbs_base; 731 732 unsigned int pf; 733 unsigned int mbox; 734 735 /* Interrupt information */ 736 int intr_type; 737 int intr_count; 738 struct irq { 739 struct resource *res; 740 int rid; 741 void *tag; 742 } *irq; 743 744 bus_dma_tag_t dmat; /* Parent DMA tag */ 745 746 struct sge sge; 747 int lro_timeout; 748 749 struct taskqueue *tq[NCHAN]; /* General purpose taskqueues */ 750 struct port_info *port[MAX_NPORTS]; 751 uint8_t chan_map[NCHAN]; 752 753 #ifdef TCP_OFFLOAD 754 void *tom_softc; /* (struct tom_data *) */ 755 struct tom_tunables tt; 756 void *iwarp_softc; /* (struct c4iw_dev *) */ 757 void *iscsi_softc; 758 #endif 759 struct l2t_data *l2t; /* L2 table */ 760 struct tid_info tids; 761 762 uint16_t doorbells; 763 int open_device_map; 764 #ifdef TCP_OFFLOAD 765 int offload_map; /* ports with IFCAP_TOE enabled */ 766 int active_ulds; /* ULDs activated on this adapter */ 767 #endif 768 int flags; 769 int debug_flags; 770 771 char ifp_lockname[16]; 772 struct mtx ifp_lock; 773 struct ifnet *ifp; /* tracer ifp */ 774 struct ifmedia media; 775 int traceq; /* iq used by all tracers, -1 if none */ 776 int tracer_valid; /* bitmap of valid tracers */ 777 int tracer_enabled; /* bitmap of enabled tracers */ 778 779 char fw_version[32]; 780 char cfg_file[32]; 781 u_int cfcsum; 782 struct adapter_params params; 783 struct t4_virt_res vres; 784 785 uint16_t linkcaps; 786 uint16_t niccaps; 787 uint16_t toecaps; 788 uint16_t rdmacaps; 789 uint16_t iscsicaps; 790 uint16_t fcoecaps; 791 792 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 793 794 struct mtx sc_lock; 795 char lockname[16]; 796 797 /* Starving free lists */ 798 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 799 TAILQ_HEAD(, sge_fl) sfl; 800 struct callout sfl_callout; 801 802 struct mtx regwin_lock; /* for indirect reads and memory windows */ 803 804 an_handler_t an_handler __aligned(CACHE_LINE_SIZE); 805 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */ 806 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */ 807 808 #ifdef INVARIANTS 809 const char *last_op; 810 const void *last_op_thr; 811 #endif 812 813 int sc_do_rxcopy; 814 }; 815 816 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 817 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 818 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 819 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 820 821 #define ASSERT_SYNCHRONIZED_OP(sc) \ 822 KASSERT(IS_BUSY(sc) && \ 823 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 824 ("%s: operation not synchronized.", __func__)) 825 826 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 827 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 828 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 829 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 830 831 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 832 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 833 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 834 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 835 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 836 837 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 838 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 839 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 840 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 841 842 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 843 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 844 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 845 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 846 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 847 848 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 849 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 850 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 851 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 852 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 853 854 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 855 do { \ 856 if (sc->debug_flags & DF_DUMP_MBOX) { \ 857 log(LOG_NOTICE, \ 858 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 859 "%016llx %016llx %016llx %016llx\n", \ 860 device_get_nameunit(sc->dev), mbox, \ 861 (unsigned long long)t4_read_reg64(sc, data_reg), \ 862 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 863 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 864 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 865 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 866 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 867 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 868 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 869 } \ 870 } while (0) 871 872 #define for_each_txq(pi, iter, q) \ 873 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \ 874 iter < pi->ntxq; ++iter, ++q) 875 #define for_each_rxq(pi, iter, q) \ 876 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \ 877 iter < pi->nrxq; ++iter, ++q) 878 #define for_each_ofld_txq(pi, iter, q) \ 879 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \ 880 iter < pi->nofldtxq; ++iter, ++q) 881 #define for_each_ofld_rxq(pi, iter, q) \ 882 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \ 883 iter < pi->nofldrxq; ++iter, ++q) 884 #define for_each_nm_txq(pi, iter, q) \ 885 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \ 886 iter < pi->nnmtxq; ++iter, ++q) 887 #define for_each_nm_rxq(pi, iter, q) \ 888 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \ 889 iter < pi->nnmrxq; ++iter, ++q) 890 891 #define IDXINCR(idx, incr, wrap) do { \ 892 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 893 } while (0) 894 #define IDXDIFF(head, tail, wrap) \ 895 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 896 897 /* One for errors, one for firmware events */ 898 #define T4_EXTRA_INTR 2 899 900 static inline uint32_t 901 t4_read_reg(struct adapter *sc, uint32_t reg) 902 { 903 904 return bus_space_read_4(sc->bt, sc->bh, reg); 905 } 906 907 static inline void 908 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 909 { 910 911 bus_space_write_4(sc->bt, sc->bh, reg, val); 912 } 913 914 static inline uint64_t 915 t4_read_reg64(struct adapter *sc, uint32_t reg) 916 { 917 918 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 919 } 920 921 static inline void 922 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 923 { 924 925 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 926 } 927 928 static inline void 929 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 930 { 931 932 *val = pci_read_config(sc->dev, reg, 1); 933 } 934 935 static inline void 936 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 937 { 938 939 pci_write_config(sc->dev, reg, val, 1); 940 } 941 942 static inline void 943 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 944 { 945 946 *val = pci_read_config(sc->dev, reg, 2); 947 } 948 949 static inline void 950 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 951 { 952 953 pci_write_config(sc->dev, reg, val, 2); 954 } 955 956 static inline void 957 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 958 { 959 960 *val = pci_read_config(sc->dev, reg, 4); 961 } 962 963 static inline void 964 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 965 { 966 967 pci_write_config(sc->dev, reg, val, 4); 968 } 969 970 static inline struct port_info * 971 adap2pinfo(struct adapter *sc, int idx) 972 { 973 974 return (sc->port[idx]); 975 } 976 977 static inline void 978 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 979 { 980 981 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN); 982 } 983 984 static inline bool 985 is_10G_port(const struct port_info *pi) 986 { 987 988 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 989 } 990 991 static inline bool 992 is_40G_port(const struct port_info *pi) 993 { 994 995 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 996 } 997 998 static inline int 999 tx_resume_threshold(struct sge_eq *eq) 1000 { 1001 1002 /* not quite the same as qsize / 4, but this will do. */ 1003 return (eq->sidx / 4); 1004 } 1005 1006 /* t4_main.c */ 1007 int t4_os_find_pci_capability(struct adapter *, int); 1008 int t4_os_pci_save_state(struct adapter *); 1009 int t4_os_pci_restore_state(struct adapter *); 1010 void t4_os_portmod_changed(const struct adapter *, int); 1011 void t4_os_link_changed(struct adapter *, int, int, int); 1012 void t4_iterate(void (*)(struct adapter *, void *), void *); 1013 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t); 1014 int t4_register_an_handler(struct adapter *, an_handler_t); 1015 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t); 1016 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1017 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *); 1018 void end_synchronized_op(struct adapter *, int); 1019 int update_mac_settings(struct ifnet *, int); 1020 int adapter_full_init(struct adapter *); 1021 int adapter_full_uninit(struct adapter *); 1022 int port_full_init(struct port_info *); 1023 int port_full_uninit(struct port_info *); 1024 1025 #ifdef DEV_NETMAP 1026 /* t4_netmap.c */ 1027 int create_netmap_ifnet(struct port_info *); 1028 int destroy_netmap_ifnet(struct port_info *); 1029 void t4_nm_intr(void *); 1030 #endif 1031 1032 /* t4_sge.c */ 1033 void t4_sge_modload(void); 1034 void t4_sge_modunload(void); 1035 uint64_t t4_sge_extfree_refs(void); 1036 void t4_init_sge_cpl_handlers(struct adapter *); 1037 void t4_tweak_chip_settings(struct adapter *); 1038 int t4_read_chip_settings(struct adapter *); 1039 int t4_create_dma_tag(struct adapter *); 1040 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1041 struct sysctl_oid_list *); 1042 int t4_destroy_dma_tag(struct adapter *); 1043 int t4_setup_adapter_queues(struct adapter *); 1044 int t4_teardown_adapter_queues(struct adapter *); 1045 int t4_setup_port_queues(struct port_info *); 1046 int t4_teardown_port_queues(struct port_info *); 1047 void t4_intr_all(void *); 1048 void t4_intr(void *); 1049 void t4_intr_err(void *); 1050 void t4_intr_evt(void *); 1051 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1052 void t4_update_fl_bufsize(struct ifnet *); 1053 int parse_pkt(struct mbuf **); 1054 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1055 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1056 int tnl_cong(struct port_info *, int); 1057 1058 /* t4_tracer.c */ 1059 struct t4_tracer; 1060 void t4_tracer_modload(void); 1061 void t4_tracer_modunload(void); 1062 void t4_tracer_port_detach(struct adapter *); 1063 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1064 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1065 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1066 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1067 1068 static inline struct wrqe * 1069 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1070 { 1071 int len = offsetof(struct wrqe, wr) + wr_len; 1072 struct wrqe *wr; 1073 1074 wr = malloc(len, M_CXGBE, M_NOWAIT); 1075 if (__predict_false(wr == NULL)) 1076 return (NULL); 1077 wr->wr_len = wr_len; 1078 wr->wrq = wrq; 1079 return (wr); 1080 } 1081 1082 static inline void * 1083 wrtod(struct wrqe *wr) 1084 { 1085 return (&wr->wr[0]); 1086 } 1087 1088 static inline void 1089 free_wrqe(struct wrqe *wr) 1090 { 1091 free(wr, M_CXGBE); 1092 } 1093 1094 static inline void 1095 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1096 { 1097 struct sge_wrq *wrq = wr->wrq; 1098 1099 TXQ_LOCK(wrq); 1100 t4_wrq_tx_locked(sc, wrq, wr); 1101 TXQ_UNLOCK(wrq); 1102 } 1103 1104 #endif 1105