1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Chelsio Communications, Inc. 5 * All rights reserved. 6 * Written by: Navdeep Parhar <np@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 * 31 */ 32 33 #ifndef __T4_ADAPTER_H__ 34 #define __T4_ADAPTER_H__ 35 36 #include <sys/kernel.h> 37 #include <sys/bus.h> 38 #include <sys/counter.h> 39 #include <sys/rman.h> 40 #include <sys/types.h> 41 #include <sys/lock.h> 42 #include <sys/malloc.h> 43 #include <sys/rwlock.h> 44 #include <sys/sx.h> 45 #include <sys/vmem.h> 46 #include <vm/uma.h> 47 48 #include <dev/pci/pcivar.h> 49 #include <dev/pci/pcireg.h> 50 #include <machine/bus.h> 51 #include <sys/socket.h> 52 #include <sys/sysctl.h> 53 #include <sys/taskqueue.h> 54 #include <net/ethernet.h> 55 #include <net/if.h> 56 #include <net/if_var.h> 57 #include <net/if_media.h> 58 #include <net/pfil.h> 59 #include <netinet/in.h> 60 #include <netinet/tcp_lro.h> 61 62 #include "offload.h" 63 #include "t4_ioctl.h" 64 #include "common/t4_msg.h" 65 #include "firmware/t4fw_interface.h" 66 67 #define KTR_CXGBE KTR_SPARE3 68 MALLOC_DECLARE(M_CXGBE); 69 #define CXGBE_UNIMPLEMENTED(s) \ 70 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 71 72 /* 73 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's 74 * LIST_HEAD when building iw_cxgbe. 75 */ 76 #define CXGBE_LIST_HEAD(name, type) \ 77 struct name { \ 78 struct type *lh_first; /* first element */ \ 79 } 80 81 #ifndef SYSCTL_ADD_UQUAD 82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 83 #define sysctl_handle_64 sysctl_handle_quad 84 #define CTLTYPE_U64 CTLTYPE_QUAD 85 #endif 86 87 SYSCTL_DECL(_hw_cxgbe); 88 89 struct adapter; 90 typedef struct adapter adapter_t; 91 92 enum { 93 /* 94 * All ingress queues use this entry size. Note that the firmware event 95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 96 * be at least 64. 97 */ 98 IQ_ESIZE = 64, 99 100 /* Default queue sizes for all kinds of ingress queues */ 101 FW_IQ_QSIZE = 256, 102 RX_IQ_QSIZE = 1024, 103 104 /* All egress queues use this entry size */ 105 EQ_ESIZE = 64, 106 107 /* Default queue sizes for all kinds of egress queues */ 108 CTRL_EQ_QSIZE = 1024, 109 TX_EQ_QSIZE = 1024, 110 111 #if MJUMPAGESIZE != MCLBYTES 112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 113 #else 114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 115 #endif 116 CL_METADATA_SIZE = CACHE_LINE_SIZE, 117 118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 119 TX_SGL_SEGS = 39, 120 TX_SGL_SEGS_TSO = 38, 121 TX_SGL_SEGS_VM = 38, 122 TX_SGL_SEGS_VM_TSO = 37, 123 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */ 124 TX_SGL_SEGS_VXLAN_TSO = 37, 125 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 126 }; 127 128 enum { 129 /* adapter intr_type */ 130 INTR_INTX = (1 << 0), 131 INTR_MSI = (1 << 1), 132 INTR_MSIX = (1 << 2) 133 }; 134 135 enum { 136 XGMAC_MTU = (1 << 0), 137 XGMAC_PROMISC = (1 << 1), 138 XGMAC_ALLMULTI = (1 << 2), 139 XGMAC_VLANEX = (1 << 3), 140 XGMAC_UCADDR = (1 << 4), 141 XGMAC_MCADDRS = (1 << 5), 142 143 XGMAC_ALL = 0xffff 144 }; 145 146 enum { 147 /* flags understood by begin_synchronized_op */ 148 HOLD_LOCK = (1 << 0), 149 SLEEP_OK = (1 << 1), 150 INTR_OK = (1 << 2), 151 152 /* flags understood by end_synchronized_op */ 153 LOCK_HELD = HOLD_LOCK, 154 }; 155 156 enum { 157 /* adapter flags */ 158 FULL_INIT_DONE = (1 << 0), 159 FW_OK = (1 << 1), 160 CHK_MBOX_ACCESS = (1 << 2), 161 MASTER_PF = (1 << 3), 162 ADAP_SYSCTL_CTX = (1 << 4), 163 ADAP_ERR = (1 << 5), 164 BUF_PACKING_OK = (1 << 6), 165 IS_VF = (1 << 7), 166 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */ 167 CXGBE_BUSY = (1 << 9), 168 HW_OFF_LIMITS = (1 << 10), /* off limits to all except reset_thread */ 169 170 /* port flags */ 171 HAS_TRACEQ = (1 << 3), 172 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */ 173 174 /* VI flags */ 175 DOOMED = (1 << 0), 176 VI_INIT_DONE = (1 << 1), 177 VI_SYSCTL_CTX = (1 << 2), 178 TX_USES_VM_WR = (1 << 3), 179 VI_SKIP_STATS = (1 << 4), 180 181 /* adapter debug_flags */ 182 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */ 183 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */ 184 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */ 185 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */ 186 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */ 187 }; 188 189 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 190 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 191 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 192 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 193 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 194 195 struct vi_info { 196 device_t dev; 197 struct port_info *pi; 198 struct adapter *adapter; 199 200 struct ifnet *ifp; 201 struct pfil_head *pfil; 202 203 unsigned long flags; 204 int if_flags; 205 206 uint16_t *rss, *nm_rss; 207 uint16_t viid; /* opaque VI identifier */ 208 uint16_t smt_idx; 209 uint16_t vin; 210 uint8_t vfvld; 211 int16_t xact_addr_filt;/* index of exact MAC address filter */ 212 uint16_t rss_size; /* size of VI's RSS table slice */ 213 uint16_t rss_base; /* start of VI's RSS table slice */ 214 int hashen; 215 216 int nintr; 217 int first_intr; 218 219 /* These need to be int as they are used in sysctl */ 220 int ntxq; /* # of tx queues */ 221 int first_txq; /* index of first tx queue */ 222 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 223 int nrxq; /* # of rx queues */ 224 int first_rxq; /* index of first rx queue */ 225 int nofldtxq; /* # of offload tx queues */ 226 int first_ofld_txq; /* index of first offload tx queue */ 227 int nofldrxq; /* # of offload rx queues */ 228 int first_ofld_rxq; /* index of first offload rx queue */ 229 int nnmtxq; 230 int first_nm_txq; 231 int nnmrxq; 232 int first_nm_rxq; 233 int tmr_idx; 234 int ofld_tmr_idx; 235 int pktc_idx; 236 int ofld_pktc_idx; 237 int qsize_rxq; 238 int qsize_txq; 239 240 struct timeval last_refreshed; 241 struct fw_vi_stats_vf stats; 242 struct mtx tick_mtx; 243 struct callout tick; 244 245 struct sysctl_ctx_list ctx; 246 struct sysctl_oid *rxq_oid; 247 struct sysctl_oid *txq_oid; 248 struct sysctl_oid *nm_rxq_oid; 249 struct sysctl_oid *nm_txq_oid; 250 struct sysctl_oid *ofld_rxq_oid; 251 struct sysctl_oid *ofld_txq_oid; 252 253 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 254 }; 255 256 struct tx_ch_rl_params { 257 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */ 258 uint32_t maxrate; 259 }; 260 261 /* CLRL state */ 262 enum clrl_state { 263 CS_UNINITIALIZED = 0, 264 CS_PARAMS_SET, /* sw parameters have been set. */ 265 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */ 266 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */ 267 CS_HW_CONFIGURED /* configured in the hardware. */ 268 }; 269 270 /* CLRL flags */ 271 enum { 272 CF_USER = (1 << 0), /* was configured by driver ioctl. */ 273 }; 274 275 struct tx_cl_rl_params { 276 enum clrl_state state; 277 int refcount; 278 uint8_t flags; 279 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */ 280 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */ 281 enum fw_sched_params_mode mode; /* aggr or per-flow */ 282 uint32_t maxrate; 283 uint16_t pktsize; 284 uint16_t burstsize; 285 }; 286 287 /* Tx scheduler parameters for a channel/port */ 288 struct tx_sched_params { 289 /* Channel Rate Limiter */ 290 struct tx_ch_rl_params ch_rl; 291 292 /* Class WRR */ 293 /* XXX */ 294 295 /* Class Rate Limiter (including the default pktsize and burstsize). */ 296 int pktsize; 297 int burstsize; 298 struct tx_cl_rl_params cl_rl[]; 299 }; 300 301 struct port_info { 302 device_t dev; 303 struct adapter *adapter; 304 305 struct vi_info *vi; 306 int nvi; 307 int up_vis; 308 int uld_vis; 309 bool vxlan_tcam_entry; 310 311 struct tx_sched_params *sched_params; 312 313 struct mtx pi_lock; 314 char lockname[16]; 315 unsigned long flags; 316 317 uint8_t lport; /* associated offload logical port */ 318 int8_t mdio_addr; 319 uint8_t port_type; 320 uint8_t mod_type; 321 uint8_t port_id; 322 uint8_t tx_chan; 323 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */ 324 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */ 325 uint8_t rx_c_chan; /* rx TP c-channel */ 326 327 struct link_config link_cfg; 328 struct ifmedia media; 329 330 struct port_stats stats; 331 u_int tnl_cong_drops; 332 u_int tx_parse_error; 333 int fcs_reg; 334 uint64_t fcs_base; 335 }; 336 337 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 338 339 struct cluster_metadata { 340 uma_zone_t zone; 341 caddr_t cl; 342 u_int refcount; 343 }; 344 345 struct fl_sdesc { 346 caddr_t cl; 347 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 348 int16_t moff; /* offset of metadata from cl */ 349 uint8_t zidx; 350 }; 351 352 struct tx_desc { 353 __be64 flit[8]; 354 }; 355 356 struct tx_sdesc { 357 struct mbuf *m; /* m_nextpkt linked chain of frames */ 358 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 359 }; 360 361 362 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 363 struct iq_desc { 364 struct rss_header rss; 365 uint8_t cpl[IQ_PAD]; 366 struct rsp_ctrl rsp; 367 }; 368 #undef IQ_PAD 369 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 370 371 enum { 372 /* iq flags */ 373 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 374 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 375 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */ 376 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 377 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */ 378 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */ 379 380 /* iq state */ 381 IQS_DISABLED = 0, 382 IQS_BUSY = 1, 383 IQS_IDLE = 2, 384 385 /* netmap related flags */ 386 NM_OFF = 0, 387 NM_ON = 1, 388 NM_BUSY = 2, 389 }; 390 391 enum { 392 CPL_COOKIE_RESERVED = 0, 393 CPL_COOKIE_FILTER, 394 CPL_COOKIE_DDP0, 395 CPL_COOKIE_DDP1, 396 CPL_COOKIE_TOM, 397 CPL_COOKIE_HASHFILTER, 398 CPL_COOKIE_ETHOFLD, 399 CPL_COOKIE_KERN_TLS, 400 401 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */ 402 }; 403 404 struct sge_iq; 405 struct rss_header; 406 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 407 struct mbuf *); 408 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 409 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 410 411 /* 412 * Ingress Queue: T4 is producer, driver is consumer. 413 */ 414 struct sge_iq { 415 uint32_t flags; 416 volatile int state; 417 struct adapter *adapter; 418 struct iq_desc *desc; /* KVA of descriptor ring */ 419 int8_t intr_pktc_idx; /* packet count threshold index */ 420 uint8_t gen; /* generation bit */ 421 uint8_t intr_params; /* interrupt holdoff parameters */ 422 int8_t cong; /* congestion settings */ 423 uint16_t qsize; /* size (# of entries) of the queue */ 424 uint16_t sidx; /* index of the entry with the status page */ 425 uint16_t cidx; /* consumer index */ 426 uint16_t cntxt_id; /* SGE context id for the iq */ 427 uint16_t abs_id; /* absolute SGE id for the iq */ 428 int16_t intr_idx; /* interrupt used by the queue */ 429 430 STAILQ_ENTRY(sge_iq) link; 431 432 bus_dma_tag_t desc_tag; 433 bus_dmamap_t desc_map; 434 bus_addr_t ba; /* bus address of descriptor ring */ 435 }; 436 437 enum { 438 /* eq type */ 439 EQ_CTRL = 1, 440 EQ_ETH = 2, 441 EQ_OFLD = 3, 442 443 /* eq flags */ 444 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */ 445 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */ 446 EQ_ENABLED = (1 << 3), /* open for business */ 447 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */ 448 }; 449 450 /* Listed in order of preference. Update t4_sysctls too if you change these */ 451 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 452 453 /* 454 * Egress Queue: driver is producer, T4 is consumer. 455 * 456 * Note: A free list is an egress queue (driver produces the buffers and T4 457 * consumes them) but it's special enough to have its own struct (see sge_fl). 458 */ 459 struct sge_eq { 460 unsigned int flags; /* MUST be first */ 461 unsigned int cntxt_id; /* SGE context id for the eq */ 462 unsigned int abs_id; /* absolute SGE id for the eq */ 463 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */ 464 uint8_t doorbells; 465 uint8_t tx_chan; /* tx channel used by the eq */ 466 struct mtx eq_lock; 467 468 struct tx_desc *desc; /* KVA of descriptor ring */ 469 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 470 u_int udb_qid; /* relative qid within the doorbell page */ 471 uint16_t sidx; /* index of the entry with the status page */ 472 uint16_t cidx; /* consumer idx (desc idx) */ 473 uint16_t pidx; /* producer idx (desc idx) */ 474 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 475 uint16_t dbidx; /* pidx of the most recent doorbell */ 476 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */ 477 volatile u_int equiq; /* EQUIQ outstanding */ 478 struct sge_iq *iq; /* iq that receives egr_update for the eq */ 479 480 bus_dma_tag_t desc_tag; 481 bus_dmamap_t desc_map; 482 bus_addr_t ba; /* bus address of descriptor ring */ 483 char lockname[16]; 484 }; 485 486 struct rx_buf_info { 487 uma_zone_t zone; /* zone that this cluster comes from */ 488 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K. 489 * hwsize[hwidx1] = size1. No spare. */ 490 uint16_t size2; /* hwsize[hwidx2] = size2. 491 * spare in cluster = size1 - size2. */ 492 int8_t hwidx1; /* SGE bufsize idx for size1 */ 493 int8_t hwidx2; /* SGE bufsize idx for size2 */ 494 uint8_t type; /* EXT_xxx type of the cluster */ 495 }; 496 497 enum { 498 NUM_MEMWIN = 3, 499 500 MEMWIN0_APERTURE = 2048, 501 MEMWIN0_BASE = 0x1b800, 502 503 MEMWIN1_APERTURE = 32768, 504 MEMWIN1_BASE = 0x28000, 505 506 MEMWIN2_APERTURE_T4 = 65536, 507 MEMWIN2_BASE_T4 = 0x30000, 508 509 MEMWIN2_APERTURE_T5 = 128 * 1024, 510 MEMWIN2_BASE_T5 = 0x60000, 511 }; 512 513 struct memwin { 514 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 515 uint32_t mw_base; /* constant after setup_memwin */ 516 uint32_t mw_aperture; /* ditto */ 517 uint32_t mw_curpos; /* protected by mw_lock */ 518 }; 519 520 enum { 521 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 522 FL_DOOMED = (1 << 1), /* about to be destroyed */ 523 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 524 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 525 }; 526 527 #define FL_RUNNING_LOW(fl) \ 528 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 529 #define FL_NOT_RUNNING_LOW(fl) \ 530 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 531 532 struct sge_fl { 533 struct mtx fl_lock; 534 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 535 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 536 uint16_t zidx; /* refill zone idx */ 537 uint16_t safe_zidx; 538 uint16_t lowat; /* # of buffers <= this means fl needs help */ 539 int flags; 540 uint16_t buf_boundary; 541 542 /* The 16b idx all deal with hw descriptors */ 543 uint16_t dbidx; /* hw pidx after last doorbell */ 544 uint16_t sidx; /* index of status page */ 545 volatile uint16_t hw_cidx; 546 547 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 548 uint32_t cidx; /* consumer index */ 549 uint32_t pidx; /* producer index */ 550 551 uint32_t dbval; 552 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 553 volatile uint32_t *udb; 554 555 uint64_t cl_allocated; /* # of clusters allocated */ 556 uint64_t cl_recycled; /* # of clusters recycled */ 557 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 558 559 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 560 struct mbuf *m0; 561 struct mbuf **pnext; 562 u_int remaining; 563 564 uint16_t qsize; /* # of hw descriptors (status page included) */ 565 uint16_t cntxt_id; /* SGE context id for the freelist */ 566 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 567 bus_dma_tag_t desc_tag; 568 bus_dmamap_t desc_map; 569 char lockname[16]; 570 bus_addr_t ba; /* bus address of descriptor ring */ 571 }; 572 573 struct mp_ring; 574 575 struct txpkts { 576 uint8_t wr_type; /* type 0 or type 1 */ 577 uint8_t npkt; /* # of packets in this work request */ 578 uint8_t len16; /* # of 16B pieces used by this work request */ 579 uint8_t score; 580 uint8_t max_npkt; /* maximum number of packets allowed */ 581 uint16_t plen; /* total payload (sum of all packets) */ 582 583 /* straight from fw_eth_tx_pkts_vm_wr. */ 584 __u8 ethmacdst[6]; 585 __u8 ethmacsrc[6]; 586 __be16 ethtype; 587 __be16 vlantci; 588 589 struct mbuf *mb[15]; 590 }; 591 592 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 593 struct sge_txq { 594 struct sge_eq eq; /* MUST be first */ 595 596 struct ifnet *ifp; /* the interface this txq belongs to */ 597 struct mp_ring *r; /* tx software ring */ 598 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 599 struct sglist *gl; 600 __be32 cpl_ctrl0; /* for convenience */ 601 int tc_idx; /* traffic class */ 602 uint64_t last_tx; /* cycle count when eth_tx was last called */ 603 struct txpkts txp; 604 605 struct task tx_reclaim_task; 606 /* stats for common events first */ 607 608 uint64_t txcsum; /* # of times hardware assisted with checksum */ 609 uint64_t tso_wrs; /* # of TSO work requests */ 610 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 611 uint64_t imm_wrs; /* # of work requests with immediate data */ 612 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 613 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 614 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 615 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 616 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 617 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 618 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */ 619 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */ 620 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */ 621 uint64_t vxlan_txcsum; 622 623 uint64_t kern_tls_records; 624 uint64_t kern_tls_short; 625 uint64_t kern_tls_partial; 626 uint64_t kern_tls_full; 627 uint64_t kern_tls_octets; 628 uint64_t kern_tls_waste; 629 uint64_t kern_tls_options; 630 uint64_t kern_tls_header; 631 uint64_t kern_tls_fin; 632 uint64_t kern_tls_fin_short; 633 uint64_t kern_tls_cbc; 634 uint64_t kern_tls_gcm; 635 636 /* stats for not-that-common events */ 637 638 /* Optional scratch space for constructing work requests. */ 639 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16); 640 } __aligned(CACHE_LINE_SIZE); 641 642 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 643 struct sge_rxq { 644 struct sge_iq iq; /* MUST be first */ 645 struct sge_fl fl; /* MUST follow iq */ 646 647 struct ifnet *ifp; /* the interface this rxq belongs to */ 648 struct lro_ctrl lro; /* LRO state */ 649 650 /* stats for common events first */ 651 652 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 653 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 654 uint64_t vxlan_rxcsum; 655 656 /* stats for not-that-common events */ 657 658 } __aligned(CACHE_LINE_SIZE); 659 660 static inline struct sge_rxq * 661 iq_to_rxq(struct sge_iq *iq) 662 { 663 664 return (__containerof(iq, struct sge_rxq, iq)); 665 } 666 667 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 668 struct sge_ofld_rxq { 669 struct sge_iq iq; /* MUST be first */ 670 struct sge_fl fl; /* MUST follow iq */ 671 counter_u64_t rx_iscsi_ddp_setup_ok; 672 counter_u64_t rx_iscsi_ddp_setup_error; 673 uint64_t rx_iscsi_ddp_pdus; 674 uint64_t rx_iscsi_ddp_octets; 675 uint64_t rx_iscsi_fl_pdus; 676 uint64_t rx_iscsi_fl_octets; 677 u_long rx_toe_tls_records; 678 u_long rx_toe_tls_octets; 679 } __aligned(CACHE_LINE_SIZE); 680 681 static inline struct sge_ofld_rxq * 682 iq_to_ofld_rxq(struct sge_iq *iq) 683 { 684 685 return (__containerof(iq, struct sge_ofld_rxq, iq)); 686 } 687 688 struct wrqe { 689 STAILQ_ENTRY(wrqe) link; 690 struct sge_wrq *wrq; 691 int wr_len; 692 char wr[] __aligned(16); 693 }; 694 695 struct wrq_cookie { 696 TAILQ_ENTRY(wrq_cookie) link; 697 int ndesc; 698 int pidx; 699 }; 700 701 /* 702 * wrq: SGE egress queue that is given prebuilt work requests. Control queues 703 * are of this type. 704 */ 705 struct sge_wrq { 706 struct sge_eq eq; /* MUST be first */ 707 708 struct adapter *adapter; 709 struct task wrq_tx_task; 710 711 /* Tx desc reserved but WR not "committed" yet. */ 712 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 713 714 /* List of WRs ready to go out as soon as descriptors are available. */ 715 STAILQ_HEAD(, wrqe) wr_list; 716 u_int nwr_pending; 717 u_int ndesc_needed; 718 719 /* stats for common events first */ 720 721 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 722 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 723 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 724 725 /* stats for not-that-common events */ 726 727 /* 728 * Scratch space for work requests that wrap around after reaching the 729 * status page, and some information about the last WR that used it. 730 */ 731 uint16_t ss_pidx; 732 uint16_t ss_len; 733 uint8_t ss[SGE_MAX_WR_LEN]; 734 735 } __aligned(CACHE_LINE_SIZE); 736 737 /* ofld_txq: SGE egress queue + miscellaneous items */ 738 struct sge_ofld_txq { 739 struct sge_wrq wrq; 740 counter_u64_t tx_iscsi_pdus; 741 counter_u64_t tx_iscsi_octets; 742 counter_u64_t tx_iscsi_iso_wrs; 743 counter_u64_t tx_toe_tls_records; 744 counter_u64_t tx_toe_tls_octets; 745 } __aligned(CACHE_LINE_SIZE); 746 747 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1)) 748 struct sge_nm_rxq { 749 /* Items used by the driver rx ithread are in this cacheline. */ 750 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */ 751 u_int nid; /* netmap ring # for this queue */ 752 struct vi_info *vi; 753 754 struct iq_desc *iq_desc; 755 uint16_t iq_abs_id; 756 uint16_t iq_cntxt_id; 757 uint16_t iq_cidx; 758 uint16_t iq_sidx; 759 uint8_t iq_gen; 760 uint32_t fl_sidx; 761 762 /* Items used by netmap rxsync are in this cacheline. */ 763 __be64 *fl_desc __aligned(CACHE_LINE_SIZE); 764 uint16_t fl_cntxt_id; 765 uint32_t fl_pidx; 766 uint32_t fl_sidx2; /* copy of fl_sidx */ 767 uint32_t fl_db_val; 768 u_int fl_db_saved; 769 u_int fl_db_threshold; /* in descriptors */ 770 u_int fl_hwidx:4; 771 772 /* 773 * fl_cidx is used by both the ithread and rxsync, the rest are not used 774 * in the rx fast path. 775 */ 776 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE); 777 778 bus_dma_tag_t iq_desc_tag; 779 bus_dmamap_t iq_desc_map; 780 bus_addr_t iq_ba; 781 int intr_idx; 782 783 bus_dma_tag_t fl_desc_tag; 784 bus_dmamap_t fl_desc_map; 785 bus_addr_t fl_ba; 786 }; 787 788 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1)) 789 struct sge_nm_txq { 790 struct tx_desc *desc; 791 uint16_t cidx; 792 uint16_t pidx; 793 uint16_t sidx; 794 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 795 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 796 uint16_t dbidx; /* pidx of the most recent doorbell */ 797 uint8_t doorbells; 798 volatile uint32_t *udb; 799 u_int udb_qid; 800 u_int cntxt_id; 801 __be32 cpl_ctrl0; /* for convenience */ 802 __be32 op_pkd; /* ditto */ 803 u_int nid; /* netmap ring # for this queue */ 804 805 /* infrequently used items after this */ 806 807 bus_dma_tag_t desc_tag; 808 bus_dmamap_t desc_map; 809 bus_addr_t ba; 810 int iqidx; 811 } __aligned(CACHE_LINE_SIZE); 812 813 struct sge { 814 int nrxq; /* total # of Ethernet rx queues */ 815 int ntxq; /* total # of Ethernet tx queues */ 816 int nofldrxq; /* total # of TOE rx queues */ 817 int nofldtxq; /* total # of TOE tx queues */ 818 int nnmrxq; /* total # of netmap rx queues */ 819 int nnmtxq; /* total # of netmap tx queues */ 820 int niq; /* total # of ingress queues */ 821 int neq; /* total # of egress queues */ 822 823 struct sge_iq fwq; /* Firmware event queue */ 824 struct sge_wrq *ctrlq; /* Control queues */ 825 struct sge_txq *txq; /* NIC tx queues */ 826 struct sge_rxq *rxq; /* NIC rx queues */ 827 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */ 828 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 829 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 830 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 831 832 uint16_t iq_start; /* first cntxt_id */ 833 uint16_t iq_base; /* first abs_id */ 834 int eq_start; /* first cntxt_id */ 835 int eq_base; /* first abs_id */ 836 int iqmap_sz; 837 int eqmap_sz; 838 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 839 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 840 841 int8_t safe_zidx; 842 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES]; 843 }; 844 845 struct devnames { 846 const char *nexus_name; 847 const char *ifnet_name; 848 const char *vi_ifnet_name; 849 const char *pf03_drv_name; 850 const char *vf_nexus_name; 851 const char *vf_ifnet_name; 852 }; 853 854 struct clip_entry; 855 856 struct adapter { 857 SLIST_ENTRY(adapter) link; 858 device_t dev; 859 struct cdev *cdev; 860 const struct devnames *names; 861 862 /* PCIe register resources */ 863 int regs_rid; 864 struct resource *regs_res; 865 int msix_rid; 866 struct resource *msix_res; 867 bus_space_handle_t bh; 868 bus_space_tag_t bt; 869 bus_size_t mmio_len; 870 int udbs_rid; 871 struct resource *udbs_res; 872 volatile uint8_t *udbs_base; 873 874 unsigned int pf; 875 unsigned int mbox; 876 unsigned int vpd_busy; 877 unsigned int vpd_flag; 878 879 /* Interrupt information */ 880 int intr_type; 881 int intr_count; 882 struct irq { 883 struct resource *res; 884 int rid; 885 void *tag; 886 struct sge_rxq *rxq; 887 struct sge_nm_rxq *nm_rxq; 888 } __aligned(CACHE_LINE_SIZE) *irq; 889 int sge_gts_reg; 890 int sge_kdoorbell_reg; 891 892 bus_dma_tag_t dmat; /* Parent DMA tag */ 893 894 struct sge sge; 895 int lro_timeout; 896 int sc_do_rxcopy; 897 898 int vxlan_port; 899 u_int vxlan_refcount; 900 int rawf_base; 901 int nrawf; 902 903 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 904 struct task async_event_task; 905 struct port_info *port[MAX_NPORTS]; 906 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */ 907 908 CXGBE_LIST_HEAD(, clip_entry) *clip_table; 909 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */ 910 u_long clip_mask; 911 int clip_gen; 912 struct timeout_task clip_task; 913 914 void *tom_softc; /* (struct tom_data *) */ 915 struct tom_tunables tt; 916 struct t4_offload_policy *policy; 917 struct rwlock policy_lock; 918 919 void *iwarp_softc; /* (struct c4iw_dev *) */ 920 struct iw_tunables iwt; 921 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 922 void *ccr_softc; /* (struct ccr_softc *) */ 923 struct l2t_data *l2t; /* L2 table */ 924 struct smt_data *smt; /* Source MAC Table */ 925 struct tid_info tids; 926 vmem_t *key_map; 927 struct tls_tunables tlst; 928 929 uint8_t doorbells; 930 int offload_map; /* ports with IFCAP_TOE enabled */ 931 int active_ulds; /* ULDs activated on this adapter */ 932 int flags; 933 int debug_flags; 934 935 char ifp_lockname[16]; 936 struct mtx ifp_lock; 937 struct ifnet *ifp; /* tracer ifp */ 938 struct ifmedia media; 939 int traceq; /* iq used by all tracers, -1 if none */ 940 int tracer_valid; /* bitmap of valid tracers */ 941 int tracer_enabled; /* bitmap of enabled tracers */ 942 943 char fw_version[16]; 944 char tp_version[16]; 945 char er_version[16]; 946 char bs_version[16]; 947 char cfg_file[32]; 948 u_int cfcsum; 949 struct adapter_params params; 950 const struct chip_params *chip_params; 951 struct t4_virt_res vres; 952 953 uint16_t nbmcaps; 954 uint16_t linkcaps; 955 uint16_t switchcaps; 956 uint16_t niccaps; 957 uint16_t toecaps; 958 uint16_t rdmacaps; 959 uint16_t cryptocaps; 960 uint16_t iscsicaps; 961 uint16_t fcoecaps; 962 963 struct sysctl_ctx_list ctx; 964 struct sysctl_oid *ctrlq_oid; 965 struct sysctl_oid *fwq_oid; 966 967 struct mtx sc_lock; 968 char lockname[16]; 969 970 /* Starving free lists */ 971 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 972 TAILQ_HEAD(, sge_fl) sfl; 973 struct callout sfl_callout; 974 975 /* 976 * Driver code that can run when the adapter is suspended must use this 977 * lock or a synchronized_op and check for HW_OFF_LIMITS before 978 * accessing hardware. 979 * 980 * XXX: could be changed to rwlock. wlock in suspend/resume and for 981 * indirect register access, rlock everywhere else. 982 */ 983 struct mtx reg_lock; 984 985 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 986 987 struct mtx tc_lock; 988 struct task tc_task; 989 990 struct task reset_task; 991 const void *reset_thread; 992 int num_resets; 993 int incarnation; 994 995 const char *last_op; 996 const void *last_op_thr; 997 int last_op_flags; 998 999 int swintr; 1000 int sensor_resets; 1001 1002 struct callout ktls_tick; 1003 }; 1004 1005 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 1006 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 1007 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 1008 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 1009 1010 #define ASSERT_SYNCHRONIZED_OP(sc) \ 1011 KASSERT(IS_BUSY(sc) && \ 1012 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 1013 ("%s: operation not synchronized.", __func__)) 1014 1015 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 1016 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 1017 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 1018 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 1019 1020 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 1021 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 1022 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 1023 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 1024 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 1025 1026 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 1027 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 1028 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 1029 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 1030 1031 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 1032 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 1033 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 1034 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 1035 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 1036 1037 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 1038 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 1039 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 1040 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 1041 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 1042 1043 #define for_each_txq(vi, iter, q) \ 1044 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \ 1045 iter < vi->ntxq; ++iter, ++q) 1046 #define for_each_rxq(vi, iter, q) \ 1047 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 1048 iter < vi->nrxq; ++iter, ++q) 1049 #define for_each_ofld_txq(vi, iter, q) \ 1050 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 1051 iter < vi->nofldtxq; ++iter, ++q) 1052 #define for_each_ofld_rxq(vi, iter, q) \ 1053 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 1054 iter < vi->nofldrxq; ++iter, ++q) 1055 #define for_each_nm_txq(vi, iter, q) \ 1056 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 1057 iter < vi->nnmtxq; ++iter, ++q) 1058 #define for_each_nm_rxq(vi, iter, q) \ 1059 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 1060 iter < vi->nnmrxq; ++iter, ++q) 1061 #define for_each_vi(_pi, _iter, _vi) \ 1062 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 1063 ++(_iter), ++(_vi)) 1064 1065 #define IDXINCR(idx, incr, wrap) do { \ 1066 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 1067 } while (0) 1068 #define IDXDIFF(head, tail, wrap) \ 1069 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 1070 1071 /* One for errors, one for firmware events */ 1072 #define T4_EXTRA_INTR 2 1073 1074 /* One for firmware events */ 1075 #define T4VF_EXTRA_INTR 1 1076 1077 static inline int 1078 forwarding_intr_to_fwq(struct adapter *sc) 1079 { 1080 1081 return (sc->intr_count == 1); 1082 } 1083 1084 /* Works reliably inside a sync_op or with reg_lock held. */ 1085 static inline bool 1086 hw_off_limits(struct adapter *sc) 1087 { 1088 return (__predict_false(sc->flags & HW_OFF_LIMITS)); 1089 } 1090 1091 static inline uint32_t 1092 t4_read_reg(struct adapter *sc, uint32_t reg) 1093 { 1094 if (hw_off_limits(sc)) 1095 MPASS(curthread == sc->reset_thread); 1096 return bus_space_read_4(sc->bt, sc->bh, reg); 1097 } 1098 1099 static inline void 1100 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 1101 { 1102 if (hw_off_limits(sc)) 1103 MPASS(curthread == sc->reset_thread); 1104 bus_space_write_4(sc->bt, sc->bh, reg, val); 1105 } 1106 1107 static inline uint64_t 1108 t4_read_reg64(struct adapter *sc, uint32_t reg) 1109 { 1110 if (hw_off_limits(sc)) 1111 MPASS(curthread == sc->reset_thread); 1112 #ifdef __LP64__ 1113 return bus_space_read_8(sc->bt, sc->bh, reg); 1114 #else 1115 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) + 1116 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32); 1117 1118 #endif 1119 } 1120 1121 static inline void 1122 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 1123 { 1124 if (hw_off_limits(sc)) 1125 MPASS(curthread == sc->reset_thread); 1126 #ifdef __LP64__ 1127 bus_space_write_8(sc->bt, sc->bh, reg, val); 1128 #else 1129 bus_space_write_4(sc->bt, sc->bh, reg, val); 1130 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32); 1131 #endif 1132 } 1133 1134 static inline void 1135 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 1136 { 1137 if (hw_off_limits(sc)) 1138 MPASS(curthread == sc->reset_thread); 1139 *val = pci_read_config(sc->dev, reg, 1); 1140 } 1141 1142 static inline void 1143 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 1144 { 1145 if (hw_off_limits(sc)) 1146 MPASS(curthread == sc->reset_thread); 1147 pci_write_config(sc->dev, reg, val, 1); 1148 } 1149 1150 static inline void 1151 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 1152 { 1153 1154 if (hw_off_limits(sc)) 1155 MPASS(curthread == sc->reset_thread); 1156 *val = pci_read_config(sc->dev, reg, 2); 1157 } 1158 1159 static inline void 1160 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 1161 { 1162 if (hw_off_limits(sc)) 1163 MPASS(curthread == sc->reset_thread); 1164 pci_write_config(sc->dev, reg, val, 2); 1165 } 1166 1167 static inline void 1168 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1169 { 1170 if (hw_off_limits(sc)) 1171 MPASS(curthread == sc->reset_thread); 1172 *val = pci_read_config(sc->dev, reg, 4); 1173 } 1174 1175 static inline void 1176 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1177 { 1178 if (hw_off_limits(sc)) 1179 MPASS(curthread == sc->reset_thread); 1180 pci_write_config(sc->dev, reg, val, 4); 1181 } 1182 1183 static inline struct port_info * 1184 adap2pinfo(struct adapter *sc, int idx) 1185 { 1186 1187 return (sc->port[idx]); 1188 } 1189 1190 static inline void 1191 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[]) 1192 { 1193 1194 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN); 1195 } 1196 1197 static inline int 1198 tx_resume_threshold(struct sge_eq *eq) 1199 { 1200 1201 /* not quite the same as qsize / 4, but this will do. */ 1202 return (eq->sidx / 4); 1203 } 1204 1205 static inline int 1206 t4_use_ldst(struct adapter *sc) 1207 { 1208 1209 #ifdef notyet 1210 return (sc->flags & FW_OK || !sc->use_bd); 1211 #else 1212 return (0); 1213 #endif 1214 } 1215 1216 static inline void 1217 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg, 1218 const char *msg, const __be64 *const p, const bool err) 1219 { 1220 1221 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err) 1222 return; 1223 if (p != NULL) { 1224 log(err ? LOG_ERR : LOG_DEBUG, 1225 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1226 "%016llx %016llx %016llx %016llx\n", 1227 device_get_nameunit(sc->dev), mbox, msg, 1228 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]), 1229 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]), 1230 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]), 1231 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7])); 1232 } else { 1233 log(err ? LOG_ERR : LOG_DEBUG, 1234 "%s: mbox %u %s %016llx %016llx %016llx %016llx " 1235 "%016llx %016llx %016llx %016llx\n", 1236 device_get_nameunit(sc->dev), mbox, msg, 1237 (long long)t4_read_reg64(sc, reg), 1238 (long long)t4_read_reg64(sc, reg + 8), 1239 (long long)t4_read_reg64(sc, reg + 16), 1240 (long long)t4_read_reg64(sc, reg + 24), 1241 (long long)t4_read_reg64(sc, reg + 32), 1242 (long long)t4_read_reg64(sc, reg + 40), 1243 (long long)t4_read_reg64(sc, reg + 48), 1244 (long long)t4_read_reg64(sc, reg + 56)); 1245 } 1246 } 1247 1248 /* t4_main.c */ 1249 extern int t4_ntxq; 1250 extern int t4_nrxq; 1251 extern int t4_intr_types; 1252 extern int t4_tmr_idx; 1253 extern int t4_pktc_idx; 1254 extern unsigned int t4_qsize_rxq; 1255 extern unsigned int t4_qsize_txq; 1256 extern device_method_t cxgbe_methods[]; 1257 1258 int t4_os_find_pci_capability(struct adapter *, int); 1259 int t4_os_pci_save_state(struct adapter *); 1260 int t4_os_pci_restore_state(struct adapter *); 1261 void t4_os_portmod_changed(struct port_info *); 1262 void t4_os_link_changed(struct port_info *); 1263 void t4_iterate(void (*)(struct adapter *, void *), void *); 1264 void t4_init_devnames(struct adapter *); 1265 void t4_add_adapter(struct adapter *); 1266 int t4_detach_common(device_t); 1267 int t4_map_bars_0_and_4(struct adapter *); 1268 int t4_map_bar_2(struct adapter *); 1269 int t4_setup_intr_handlers(struct adapter *); 1270 void t4_sysctls(struct adapter *); 1271 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1272 void doom_vi(struct adapter *, struct vi_info *); 1273 void end_synchronized_op(struct adapter *, int); 1274 int update_mac_settings(struct ifnet *, int); 1275 int adapter_init(struct adapter *); 1276 int vi_init(struct vi_info *); 1277 void vi_sysctls(struct vi_info *); 1278 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int); 1279 int alloc_atid(struct adapter *, void *); 1280 void *lookup_atid(struct adapter *, int); 1281 void free_atid(struct adapter *, int); 1282 void release_tid(struct adapter *, int, struct sge_wrq *); 1283 int cxgbe_media_change(struct ifnet *); 1284 void cxgbe_media_status(struct ifnet *, struct ifmediareq *); 1285 bool t4_os_dump_cimla(struct adapter *, int, bool); 1286 void t4_os_dump_devlog(struct adapter *); 1287 1288 #ifdef KERN_TLS 1289 /* t4_kern_tls.c */ 1290 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1291 struct m_snd_tag **); 1292 void cxgbe_tls_tag_free(struct m_snd_tag *); 1293 void t6_ktls_modload(void); 1294 void t6_ktls_modunload(void); 1295 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *); 1296 int t6_ktls_parse_pkt(struct mbuf *, int *, int *); 1297 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int); 1298 #endif 1299 1300 /* t4_keyctx.c */ 1301 struct auth_hash; 1302 union authctx; 1303 #ifdef KERN_TLS 1304 struct ktls_session; 1305 struct tls_key_req; 1306 struct tls_keyctx; 1307 #endif 1308 1309 void t4_aes_getdeckey(void *, const void *, unsigned int); 1310 void t4_copy_partial_hash(int, union authctx *, void *); 1311 void t4_init_gmac_hash(const char *, int, char *); 1312 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int, 1313 char *); 1314 #ifdef KERN_TLS 1315 u_int t4_tls_key_info_size(const struct ktls_session *); 1316 int t4_tls_proto_ver(const struct ktls_session *); 1317 int t4_tls_cipher_mode(const struct ktls_session *); 1318 int t4_tls_auth_mode(const struct ktls_session *); 1319 int t4_tls_hmac_ctrl(const struct ktls_session *); 1320 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *); 1321 int t4_alloc_tls_keyid(struct adapter *); 1322 void t4_free_tls_keyid(struct adapter *, int); 1323 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int, 1324 struct tls_key_req *); 1325 #endif 1326 1327 #ifdef DEV_NETMAP 1328 /* t4_netmap.c */ 1329 struct sge_nm_rxq; 1330 void cxgbe_nm_attach(struct vi_info *); 1331 void cxgbe_nm_detach(struct vi_info *); 1332 void service_nm_rxq(struct sge_nm_rxq *); 1333 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int); 1334 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *); 1335 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int); 1336 int free_nm_txq(struct vi_info *, struct sge_nm_txq *); 1337 #endif 1338 1339 /* t4_sge.c */ 1340 void t4_sge_modload(void); 1341 void t4_sge_modunload(void); 1342 uint64_t t4_sge_extfree_refs(void); 1343 void t4_tweak_chip_settings(struct adapter *); 1344 int t4_verify_chip_settings(struct adapter *); 1345 void t4_init_rx_buf_info(struct adapter *); 1346 int t4_create_dma_tag(struct adapter *); 1347 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1348 struct sysctl_oid_list *); 1349 int t4_destroy_dma_tag(struct adapter *); 1350 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *, 1351 bus_addr_t *, void **); 1352 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 1353 void *); 1354 void free_fl_buffers(struct adapter *, struct sge_fl *); 1355 int t4_setup_adapter_queues(struct adapter *); 1356 int t4_teardown_adapter_queues(struct adapter *); 1357 int t4_setup_vi_queues(struct vi_info *); 1358 int t4_teardown_vi_queues(struct vi_info *); 1359 void t4_intr_all(void *); 1360 void t4_intr(void *); 1361 #ifdef DEV_NETMAP 1362 void t4_nm_intr(void *); 1363 void t4_vi_intr(void *); 1364 #endif 1365 void t4_intr_err(void *); 1366 void t4_intr_evt(void *); 1367 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1368 void t4_update_fl_bufsize(struct ifnet *); 1369 struct mbuf *alloc_wr_mbuf(int, int); 1370 int parse_pkt(struct mbuf **, bool); 1371 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1372 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1373 int tnl_cong(struct port_info *, int); 1374 void t4_register_an_handler(an_handler_t); 1375 void t4_register_fw_msg_handler(int, fw_msg_handler_t); 1376 void t4_register_cpl_handler(int, cpl_handler_t); 1377 void t4_register_shared_cpl_handler(int, cpl_handler_t, int); 1378 #ifdef RATELIMIT 1379 int ethofld_transmit(struct ifnet *, struct mbuf *); 1380 void send_etid_flush_wr(struct cxgbe_rate_tag *); 1381 #endif 1382 1383 /* t4_tracer.c */ 1384 struct t4_tracer; 1385 void t4_tracer_modload(void); 1386 void t4_tracer_modunload(void); 1387 void t4_tracer_port_detach(struct adapter *); 1388 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1389 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1390 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1391 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1392 1393 /* t4_sched.c */ 1394 int t4_set_sched_class(struct adapter *, struct t4_sched_params *); 1395 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *); 1396 int t4_init_tx_sched(struct adapter *); 1397 int t4_free_tx_sched(struct adapter *); 1398 void t4_update_tx_sched(struct adapter *); 1399 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *); 1400 void t4_release_cl_rl(struct adapter *, int, int); 1401 int sysctl_tc(SYSCTL_HANDLER_ARGS); 1402 int sysctl_tc_params(SYSCTL_HANDLER_ARGS); 1403 #ifdef RATELIMIT 1404 void t4_init_etid_table(struct adapter *); 1405 void t4_free_etid_table(struct adapter *); 1406 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int); 1407 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *, 1408 struct m_snd_tag **); 1409 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *); 1410 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *); 1411 void cxgbe_rate_tag_free(struct m_snd_tag *); 1412 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *); 1413 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *); 1414 #endif 1415 1416 /* t4_filter.c */ 1417 int get_filter_mode(struct adapter *, uint32_t *); 1418 int set_filter_mode(struct adapter *, uint32_t); 1419 int set_filter_mask(struct adapter *, uint32_t); 1420 int get_filter(struct adapter *, struct t4_filter *); 1421 int set_filter(struct adapter *, struct t4_filter *); 1422 int del_filter(struct adapter *, struct t4_filter *); 1423 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1424 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1425 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1426 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1427 void free_hftid_hash(struct tid_info *); 1428 1429 static inline struct wrqe * 1430 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1431 { 1432 int len = offsetof(struct wrqe, wr) + wr_len; 1433 struct wrqe *wr; 1434 1435 wr = malloc(len, M_CXGBE, M_NOWAIT); 1436 if (__predict_false(wr == NULL)) 1437 return (NULL); 1438 wr->wr_len = wr_len; 1439 wr->wrq = wrq; 1440 return (wr); 1441 } 1442 1443 static inline void * 1444 wrtod(struct wrqe *wr) 1445 { 1446 return (&wr->wr[0]); 1447 } 1448 1449 static inline void 1450 free_wrqe(struct wrqe *wr) 1451 { 1452 free(wr, M_CXGBE); 1453 } 1454 1455 static inline void 1456 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1457 { 1458 struct sge_wrq *wrq = wr->wrq; 1459 1460 TXQ_LOCK(wrq); 1461 t4_wrq_tx_locked(sc, wrq, wr); 1462 TXQ_UNLOCK(wrq); 1463 } 1464 1465 static inline int 1466 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val, 1467 int len) 1468 { 1469 1470 return (rw_via_memwin(sc, idx, addr, val, len, 0)); 1471 } 1472 1473 static inline int 1474 write_via_memwin(struct adapter *sc, int idx, uint32_t addr, 1475 const uint32_t *val, int len) 1476 { 1477 1478 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1)); 1479 } 1480 1481 /* Number of len16 -> number of descriptors */ 1482 static inline int 1483 tx_len16_to_desc(int len16) 1484 { 1485 1486 return (howmany(len16, EQ_ESIZE / 16)); 1487 } 1488 #endif 1489