1 /*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31 #ifndef __T4_ADAPTER_H__ 32 #define __T4_ADAPTER_H__ 33 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/rman.h> 37 #include <sys/types.h> 38 #include <sys/lock.h> 39 #include <sys/malloc.h> 40 #include <sys/rwlock.h> 41 #include <sys/sx.h> 42 #include <vm/uma.h> 43 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcireg.h> 46 #include <machine/bus.h> 47 #include <sys/socket.h> 48 #include <sys/sysctl.h> 49 #include <net/ethernet.h> 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_media.h> 53 #include <netinet/in.h> 54 #include <netinet/tcp_lro.h> 55 56 #include "offload.h" 57 #include "t4_ioctl.h" 58 #include "common/t4_msg.h" 59 #include "firmware/t4fw_interface.h" 60 61 #define KTR_CXGBE KTR_SPARE3 62 MALLOC_DECLARE(M_CXGBE); 63 #define CXGBE_UNIMPLEMENTED(s) \ 64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__) 65 66 #if defined(__i386__) || defined(__amd64__) 67 static __inline void 68 prefetch(void *x) 69 { 70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 71 } 72 #else 73 #define prefetch(x) 74 #endif 75 76 #ifndef SYSCTL_ADD_UQUAD 77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 78 #define sysctl_handle_64 sysctl_handle_quad 79 #define CTLTYPE_U64 CTLTYPE_QUAD 80 #endif 81 82 #if (__FreeBSD_version >= 900030) || \ 83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000)) 84 #define SBUF_DRAIN 1 85 #endif 86 87 #ifdef __amd64__ 88 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */ 89 static __inline uint64_t 90 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 91 bus_size_t offset) 92 { 93 KASSERT(tag == X86_BUS_SPACE_MEM, 94 ("%s: can only handle mem space", __func__)); 95 96 return (*(volatile uint64_t *)(handle + offset)); 97 } 98 99 static __inline void 100 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 101 bus_size_t offset, uint64_t value) 102 { 103 KASSERT(tag == X86_BUS_SPACE_MEM, 104 ("%s: can only handle mem space", __func__)); 105 106 *(volatile uint64_t *)(bsh + offset) = value; 107 } 108 #else 109 static __inline uint64_t 110 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 111 bus_size_t offset) 112 { 113 return (uint64_t)bus_space_read_4(tag, handle, offset) + 114 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32); 115 } 116 117 static __inline void 118 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh, 119 bus_size_t offset, uint64_t value) 120 { 121 bus_space_write_4(tag, bsh, offset, value); 122 bus_space_write_4(tag, bsh, offset + 4, value >> 32); 123 } 124 #endif 125 126 struct adapter; 127 typedef struct adapter adapter_t; 128 129 enum { 130 /* 131 * All ingress queues use this entry size. Note that the firmware event 132 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to 133 * be at least 64. 134 */ 135 IQ_ESIZE = 64, 136 137 /* Default queue sizes for all kinds of ingress queues */ 138 FW_IQ_QSIZE = 256, 139 RX_IQ_QSIZE = 1024, 140 141 /* All egress queues use this entry size */ 142 EQ_ESIZE = 64, 143 144 /* Default queue sizes for all kinds of egress queues */ 145 CTRL_EQ_QSIZE = 128, 146 TX_EQ_QSIZE = 1024, 147 148 #if MJUMPAGESIZE != MCLBYTES 149 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */ 150 #else 151 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */ 152 #endif 153 CL_METADATA_SIZE = CACHE_LINE_SIZE, 154 155 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */ 156 TX_SGL_SEGS = 39, 157 TX_SGL_SEGS_TSO = 38, 158 TX_WR_FLITS = SGE_MAX_WR_LEN / 8 159 }; 160 161 enum { 162 /* adapter intr_type */ 163 INTR_INTX = (1 << 0), 164 INTR_MSI = (1 << 1), 165 INTR_MSIX = (1 << 2) 166 }; 167 168 enum { 169 XGMAC_MTU = (1 << 0), 170 XGMAC_PROMISC = (1 << 1), 171 XGMAC_ALLMULTI = (1 << 2), 172 XGMAC_VLANEX = (1 << 3), 173 XGMAC_UCADDR = (1 << 4), 174 XGMAC_MCADDRS = (1 << 5), 175 176 XGMAC_ALL = 0xffff 177 }; 178 179 enum { 180 /* flags understood by begin_synchronized_op */ 181 HOLD_LOCK = (1 << 0), 182 SLEEP_OK = (1 << 1), 183 INTR_OK = (1 << 2), 184 185 /* flags understood by end_synchronized_op */ 186 LOCK_HELD = HOLD_LOCK, 187 }; 188 189 enum { 190 /* adapter flags */ 191 FULL_INIT_DONE = (1 << 0), 192 FW_OK = (1 << 1), 193 /* INTR_DIRECT = (1 << 2), No longer used. */ 194 MASTER_PF = (1 << 3), 195 ADAP_SYSCTL_CTX = (1 << 4), 196 /* TOM_INIT_DONE= (1 << 5), No longer used */ 197 BUF_PACKING_OK = (1 << 6), 198 IS_VF = (1 << 7), 199 200 CXGBE_BUSY = (1 << 9), 201 202 /* port flags */ 203 HAS_TRACEQ = (1 << 3), 204 205 /* VI flags */ 206 DOOMED = (1 << 0), 207 VI_INIT_DONE = (1 << 1), 208 VI_SYSCTL_CTX = (1 << 2), 209 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */ 210 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */ 211 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ), 212 213 /* adapter debug_flags */ 214 DF_DUMP_MBOX = (1 << 0), 215 }; 216 217 #define IS_DOOMED(vi) ((vi)->flags & DOOMED) 218 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0) 219 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY) 220 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0) 221 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0) 222 223 struct vi_info { 224 device_t dev; 225 struct port_info *pi; 226 227 struct ifnet *ifp; 228 struct ifmedia media; 229 230 unsigned long flags; 231 int if_flags; 232 233 uint16_t *rss, *nm_rss; 234 uint16_t viid; 235 int16_t xact_addr_filt;/* index of exact MAC address filter */ 236 uint16_t rss_size; /* size of VI's RSS table slice */ 237 uint16_t rss_base; /* start of VI's RSS table slice */ 238 239 eventhandler_tag vlan_c; 240 241 int nintr; 242 int first_intr; 243 244 /* These need to be int as they are used in sysctl */ 245 int ntxq; /* # of tx queues */ 246 int first_txq; /* index of first tx queue */ 247 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */ 248 int nrxq; /* # of rx queues */ 249 int first_rxq; /* index of first rx queue */ 250 int nofldtxq; /* # of offload tx queues */ 251 int first_ofld_txq; /* index of first offload tx queue */ 252 int nofldrxq; /* # of offload rx queues */ 253 int first_ofld_rxq; /* index of first offload rx queue */ 254 int nnmtxq; 255 int first_nm_txq; 256 int nnmrxq; 257 int first_nm_rxq; 258 int tmr_idx; 259 int pktc_idx; 260 int qsize_rxq; 261 int qsize_txq; 262 263 struct timeval last_refreshed; 264 struct fw_vi_stats_vf stats; 265 266 struct callout tick; 267 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */ 268 269 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */ 270 }; 271 272 enum { 273 /* tx_sched_class flags */ 274 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */ 275 }; 276 277 struct tx_sched_class { 278 int refcount; 279 int flags; 280 struct t4_sched_class_params params; 281 }; 282 283 struct port_info { 284 device_t dev; 285 struct adapter *adapter; 286 287 struct vi_info *vi; 288 int nvi; 289 int up_vis; 290 int uld_vis; 291 292 struct tx_sched_class *tc; /* traffic classes for this channel */ 293 294 struct mtx pi_lock; 295 char lockname[16]; 296 unsigned long flags; 297 298 uint8_t lport; /* associated offload logical port */ 299 int8_t mdio_addr; 300 uint8_t port_type; 301 uint8_t mod_type; 302 uint8_t port_id; 303 uint8_t tx_chan; 304 uint8_t rx_chan_map; /* rx MPS channel bitmap */ 305 306 int linkdnrc; 307 struct link_config link_cfg; 308 309 struct timeval last_refreshed; 310 struct port_stats stats; 311 u_int tnl_cong_drops; 312 u_int tx_parse_error; 313 314 struct callout tick; 315 }; 316 317 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0])) 318 319 /* Where the cluster came from, how it has been carved up. */ 320 struct cluster_layout { 321 int8_t zidx; 322 int8_t hwidx; 323 uint16_t region1; /* mbufs laid out within this region */ 324 /* region2 is the DMA region */ 325 uint16_t region3; /* cluster_metadata within this region */ 326 }; 327 328 struct cluster_metadata { 329 u_int refcount; 330 struct fl_sdesc *sd; /* For debug only. Could easily be stale */ 331 }; 332 333 struct fl_sdesc { 334 caddr_t cl; 335 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */ 336 struct cluster_layout cll; 337 }; 338 339 struct tx_desc { 340 __be64 flit[8]; 341 }; 342 343 struct tx_sdesc { 344 struct mbuf *m; /* m_nextpkt linked chain of frames */ 345 uint8_t desc_used; /* # of hardware descriptors used by the WR */ 346 }; 347 348 349 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header)) 350 struct iq_desc { 351 struct rss_header rss; 352 uint8_t cpl[IQ_PAD]; 353 struct rsp_ctrl rsp; 354 }; 355 #undef IQ_PAD 356 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE); 357 358 enum { 359 /* iq flags */ 360 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */ 361 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */ 362 IQ_INTR = (1 << 2), /* iq takes direct interrupt */ 363 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */ 364 365 /* iq state */ 366 IQS_DISABLED = 0, 367 IQS_BUSY = 1, 368 IQS_IDLE = 2, 369 370 /* netmap related flags */ 371 NM_OFF = 0, 372 NM_ON = 1, 373 NM_BUSY = 2, 374 }; 375 376 struct sge_iq; 377 struct rss_header; 378 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *, 379 struct mbuf *); 380 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *); 381 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *); 382 383 /* 384 * Ingress Queue: T4 is producer, driver is consumer. 385 */ 386 struct sge_iq { 387 uint32_t flags; 388 volatile int state; 389 struct adapter *adapter; 390 cpl_handler_t set_tcb_rpl; 391 cpl_handler_t l2t_write_rpl; 392 struct iq_desc *desc; /* KVA of descriptor ring */ 393 int8_t intr_pktc_idx; /* packet count threshold index */ 394 uint8_t gen; /* generation bit */ 395 uint8_t intr_params; /* interrupt holdoff parameters */ 396 uint8_t intr_next; /* XXX: holdoff for next interrupt */ 397 uint16_t qsize; /* size (# of entries) of the queue */ 398 uint16_t sidx; /* index of the entry with the status page */ 399 uint16_t cidx; /* consumer index */ 400 uint16_t cntxt_id; /* SGE context id for the iq */ 401 uint16_t abs_id; /* absolute SGE id for the iq */ 402 403 STAILQ_ENTRY(sge_iq) link; 404 405 bus_dma_tag_t desc_tag; 406 bus_dmamap_t desc_map; 407 bus_addr_t ba; /* bus address of descriptor ring */ 408 }; 409 410 enum { 411 EQ_CTRL = 1, 412 EQ_ETH = 2, 413 EQ_OFLD = 3, 414 415 /* eq flags */ 416 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */ 417 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */ 418 EQ_ENABLED = (1 << 3), /* open for business */ 419 }; 420 421 /* Listed in order of preference. Update t4_sysctls too if you change these */ 422 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB}; 423 424 /* 425 * Egress Queue: driver is producer, T4 is consumer. 426 * 427 * Note: A free list is an egress queue (driver produces the buffers and T4 428 * consumes them) but it's special enough to have its own struct (see sge_fl). 429 */ 430 struct sge_eq { 431 unsigned int flags; /* MUST be first */ 432 unsigned int cntxt_id; /* SGE context id for the eq */ 433 unsigned int abs_id; /* absolute SGE id for the eq */ 434 struct mtx eq_lock; 435 436 struct tx_desc *desc; /* KVA of descriptor ring */ 437 uint16_t doorbells; 438 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */ 439 u_int udb_qid; /* relative qid within the doorbell page */ 440 uint16_t sidx; /* index of the entry with the status page */ 441 uint16_t cidx; /* consumer idx (desc idx) */ 442 uint16_t pidx; /* producer idx (desc idx) */ 443 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 444 uint16_t dbidx; /* pidx of the most recent doorbell */ 445 uint16_t iqid; /* iq that gets egr_update for the eq */ 446 uint8_t tx_chan; /* tx channel used by the eq */ 447 volatile u_int equiq; /* EQUIQ outstanding */ 448 449 bus_dma_tag_t desc_tag; 450 bus_dmamap_t desc_map; 451 bus_addr_t ba; /* bus address of descriptor ring */ 452 char lockname[16]; 453 }; 454 455 struct sw_zone_info { 456 uma_zone_t zone; /* zone that this cluster comes from */ 457 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */ 458 int type; /* EXT_xxx type of the cluster */ 459 int8_t head_hwidx; 460 int8_t tail_hwidx; 461 }; 462 463 struct hw_buf_info { 464 int8_t zidx; /* backpointer to zone; -ve means unused */ 465 int8_t next; /* next hwidx for this zone; -1 means no more */ 466 int size; 467 }; 468 469 enum { 470 NUM_MEMWIN = 3, 471 472 MEMWIN0_APERTURE = 2048, 473 MEMWIN0_BASE = 0x1b800, 474 475 MEMWIN1_APERTURE = 32768, 476 MEMWIN1_BASE = 0x28000, 477 478 MEMWIN2_APERTURE_T4 = 65536, 479 MEMWIN2_BASE_T4 = 0x30000, 480 481 MEMWIN2_APERTURE_T5 = 128 * 1024, 482 MEMWIN2_BASE_T5 = 0x60000, 483 }; 484 485 struct memwin { 486 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE); 487 uint32_t mw_base; /* constant after setup_memwin */ 488 uint32_t mw_aperture; /* ditto */ 489 uint32_t mw_curpos; /* protected by mw_lock */ 490 }; 491 492 enum { 493 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */ 494 FL_DOOMED = (1 << 1), /* about to be destroyed */ 495 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */ 496 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */ 497 }; 498 499 #define FL_RUNNING_LOW(fl) \ 500 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat) 501 #define FL_NOT_RUNNING_LOW(fl) \ 502 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat) 503 504 struct sge_fl { 505 struct mtx fl_lock; 506 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */ 507 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */ 508 struct cluster_layout cll_def; /* default refill zone, layout */ 509 uint16_t lowat; /* # of buffers <= this means fl needs help */ 510 int flags; 511 uint16_t buf_boundary; 512 513 /* The 16b idx all deal with hw descriptors */ 514 uint16_t dbidx; /* hw pidx after last doorbell */ 515 uint16_t sidx; /* index of status page */ 516 volatile uint16_t hw_cidx; 517 518 /* The 32b idx are all buffer idx, not hardware descriptor idx */ 519 uint32_t cidx; /* consumer index */ 520 uint32_t pidx; /* producer index */ 521 522 uint32_t dbval; 523 u_int rx_offset; /* offset in fl buf (when buffer packing) */ 524 volatile uint32_t *udb; 525 526 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */ 527 uint64_t mbuf_inlined; /* # of mbuf created within clusters */ 528 uint64_t cl_allocated; /* # of clusters allocated */ 529 uint64_t cl_recycled; /* # of clusters recycled */ 530 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */ 531 532 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */ 533 struct mbuf *m0; 534 struct mbuf **pnext; 535 u_int remaining; 536 537 uint16_t qsize; /* # of hw descriptors (status page included) */ 538 uint16_t cntxt_id; /* SGE context id for the freelist */ 539 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */ 540 bus_dma_tag_t desc_tag; 541 bus_dmamap_t desc_map; 542 char lockname[16]; 543 bus_addr_t ba; /* bus address of descriptor ring */ 544 struct cluster_layout cll_alt; /* alternate refill zone, layout */ 545 }; 546 547 struct mp_ring; 548 549 /* txq: SGE egress queue + what's needed for Ethernet NIC */ 550 struct sge_txq { 551 struct sge_eq eq; /* MUST be first */ 552 553 struct ifnet *ifp; /* the interface this txq belongs to */ 554 struct mp_ring *r; /* tx software ring */ 555 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */ 556 struct sglist *gl; 557 __be32 cpl_ctrl0; /* for convenience */ 558 int tc_idx; /* traffic class */ 559 560 struct task tx_reclaim_task; 561 /* stats for common events first */ 562 563 uint64_t txcsum; /* # of times hardware assisted with checksum */ 564 uint64_t tso_wrs; /* # of TSO work requests */ 565 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */ 566 uint64_t imm_wrs; /* # of work requests with immediate data */ 567 uint64_t sgl_wrs; /* # of work requests with direct SGL */ 568 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */ 569 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */ 570 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */ 571 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */ 572 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */ 573 574 /* stats for not-that-common events */ 575 } __aligned(CACHE_LINE_SIZE); 576 577 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */ 578 struct sge_rxq { 579 struct sge_iq iq; /* MUST be first */ 580 struct sge_fl fl; /* MUST follow iq */ 581 582 struct ifnet *ifp; /* the interface this rxq belongs to */ 583 #if defined(INET) || defined(INET6) 584 struct lro_ctrl lro; /* LRO state */ 585 #endif 586 587 /* stats for common events first */ 588 589 uint64_t rxcsum; /* # of times hardware assisted with checksum */ 590 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */ 591 592 /* stats for not-that-common events */ 593 594 } __aligned(CACHE_LINE_SIZE); 595 596 static inline struct sge_rxq * 597 iq_to_rxq(struct sge_iq *iq) 598 { 599 600 return (__containerof(iq, struct sge_rxq, iq)); 601 } 602 603 604 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */ 605 struct sge_ofld_rxq { 606 struct sge_iq iq; /* MUST be first */ 607 struct sge_fl fl; /* MUST follow iq */ 608 } __aligned(CACHE_LINE_SIZE); 609 610 static inline struct sge_ofld_rxq * 611 iq_to_ofld_rxq(struct sge_iq *iq) 612 { 613 614 return (__containerof(iq, struct sge_ofld_rxq, iq)); 615 } 616 617 struct wrqe { 618 STAILQ_ENTRY(wrqe) link; 619 struct sge_wrq *wrq; 620 int wr_len; 621 char wr[] __aligned(16); 622 }; 623 624 struct wrq_cookie { 625 TAILQ_ENTRY(wrq_cookie) link; 626 int ndesc; 627 int pidx; 628 }; 629 630 /* 631 * wrq: SGE egress queue that is given prebuilt work requests. Both the control 632 * and offload tx queues are of this type. 633 */ 634 struct sge_wrq { 635 struct sge_eq eq; /* MUST be first */ 636 637 struct adapter *adapter; 638 struct task wrq_tx_task; 639 640 /* Tx desc reserved but WR not "committed" yet. */ 641 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs; 642 643 /* List of WRs ready to go out as soon as descriptors are available. */ 644 STAILQ_HEAD(, wrqe) wr_list; 645 u_int nwr_pending; 646 u_int ndesc_needed; 647 648 /* stats for common events first */ 649 650 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */ 651 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */ 652 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */ 653 654 /* stats for not-that-common events */ 655 656 /* 657 * Scratch space for work requests that wrap around after reaching the 658 * status page, and some information about the last WR that used it. 659 */ 660 uint16_t ss_pidx; 661 uint16_t ss_len; 662 uint8_t ss[SGE_MAX_WR_LEN]; 663 664 } __aligned(CACHE_LINE_SIZE); 665 666 667 struct sge_nm_rxq { 668 struct vi_info *vi; 669 670 struct iq_desc *iq_desc; 671 uint16_t iq_abs_id; 672 uint16_t iq_cntxt_id; 673 uint16_t iq_cidx; 674 uint16_t iq_sidx; 675 uint8_t iq_gen; 676 677 __be64 *fl_desc; 678 uint16_t fl_cntxt_id; 679 uint32_t fl_cidx; 680 uint32_t fl_pidx; 681 uint32_t fl_sidx; 682 uint32_t fl_db_val; 683 u_int fl_hwidx:4; 684 685 u_int nid; /* netmap ring # for this queue */ 686 687 /* infrequently used items after this */ 688 689 bus_dma_tag_t iq_desc_tag; 690 bus_dmamap_t iq_desc_map; 691 bus_addr_t iq_ba; 692 int intr_idx; 693 694 bus_dma_tag_t fl_desc_tag; 695 bus_dmamap_t fl_desc_map; 696 bus_addr_t fl_ba; 697 } __aligned(CACHE_LINE_SIZE); 698 699 struct sge_nm_txq { 700 struct tx_desc *desc; 701 uint16_t cidx; 702 uint16_t pidx; 703 uint16_t sidx; 704 uint16_t equiqidx; /* EQUIQ last requested at this pidx */ 705 uint16_t equeqidx; /* EQUEQ last requested at this pidx */ 706 uint16_t dbidx; /* pidx of the most recent doorbell */ 707 uint16_t doorbells; 708 volatile uint32_t *udb; 709 u_int udb_qid; 710 u_int cntxt_id; 711 __be32 cpl_ctrl0; /* for convenience */ 712 u_int nid; /* netmap ring # for this queue */ 713 714 /* infrequently used items after this */ 715 716 bus_dma_tag_t desc_tag; 717 bus_dmamap_t desc_map; 718 bus_addr_t ba; 719 int iqidx; 720 } __aligned(CACHE_LINE_SIZE); 721 722 struct sge { 723 int nrxq; /* total # of Ethernet rx queues */ 724 int ntxq; /* total # of Ethernet tx tx queues */ 725 int nofldrxq; /* total # of TOE rx queues */ 726 int nofldtxq; /* total # of TOE tx queues */ 727 int nnmrxq; /* total # of netmap rx queues */ 728 int nnmtxq; /* total # of netmap tx queues */ 729 int niq; /* total # of ingress queues */ 730 int neq; /* total # of egress queues */ 731 732 struct sge_iq fwq; /* Firmware event queue */ 733 struct sge_wrq mgmtq; /* Management queue (control queue) */ 734 struct sge_wrq *ctrlq; /* Control queues */ 735 struct sge_txq *txq; /* NIC tx queues */ 736 struct sge_rxq *rxq; /* NIC rx queues */ 737 struct sge_wrq *ofld_txq; /* TOE tx queues */ 738 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */ 739 struct sge_nm_txq *nm_txq; /* netmap tx queues */ 740 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */ 741 742 uint16_t iq_start; /* first cntxt_id */ 743 uint16_t iq_base; /* first abs_id */ 744 int eq_start; /* first cntxt_id */ 745 int eq_base; /* first abs_id */ 746 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */ 747 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */ 748 749 int8_t safe_hwidx1; /* may not have room for metadata */ 750 int8_t safe_hwidx2; /* with room for metadata and maybe more */ 751 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES]; 752 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES]; 753 }; 754 755 struct adapter { 756 SLIST_ENTRY(adapter) link; 757 device_t dev; 758 struct cdev *cdev; 759 760 /* PCIe register resources */ 761 int regs_rid; 762 struct resource *regs_res; 763 int msix_rid; 764 struct resource *msix_res; 765 bus_space_handle_t bh; 766 bus_space_tag_t bt; 767 bus_size_t mmio_len; 768 int udbs_rid; 769 struct resource *udbs_res; 770 volatile uint8_t *udbs_base; 771 772 unsigned int pf; 773 unsigned int mbox; 774 unsigned int vpd_busy; 775 unsigned int vpd_flag; 776 777 /* Interrupt information */ 778 int intr_type; 779 int intr_count; 780 struct irq { 781 struct resource *res; 782 int rid; 783 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */ 784 void *tag; 785 struct sge_rxq *rxq; 786 struct sge_nm_rxq *nm_rxq; 787 } __aligned(CACHE_LINE_SIZE) *irq; 788 int sge_gts_reg; 789 int sge_kdoorbell_reg; 790 791 bus_dma_tag_t dmat; /* Parent DMA tag */ 792 793 struct sge sge; 794 int lro_timeout; 795 int sc_do_rxcopy; 796 797 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */ 798 struct port_info *port[MAX_NPORTS]; 799 uint8_t chan_map[MAX_NCHAN]; 800 801 void *tom_softc; /* (struct tom_data *) */ 802 struct tom_tunables tt; 803 void *iwarp_softc; /* (struct c4iw_dev *) */ 804 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */ 805 struct l2t_data *l2t; /* L2 table */ 806 struct tid_info tids; 807 808 uint16_t doorbells; 809 int offload_map; /* ports with IFCAP_TOE enabled */ 810 int active_ulds; /* ULDs activated on this adapter */ 811 int flags; 812 int debug_flags; 813 814 char ifp_lockname[16]; 815 struct mtx ifp_lock; 816 struct ifnet *ifp; /* tracer ifp */ 817 struct ifmedia media; 818 int traceq; /* iq used by all tracers, -1 if none */ 819 int tracer_valid; /* bitmap of valid tracers */ 820 int tracer_enabled; /* bitmap of enabled tracers */ 821 822 char fw_version[16]; 823 char tp_version[16]; 824 char exprom_version[16]; 825 char cfg_file[32]; 826 u_int cfcsum; 827 struct adapter_params params; 828 const struct chip_params *chip_params; 829 struct t4_virt_res vres; 830 831 uint16_t nbmcaps; 832 uint16_t linkcaps; 833 uint16_t switchcaps; 834 uint16_t niccaps; 835 uint16_t toecaps; 836 uint16_t rdmacaps; 837 uint16_t tlscaps; 838 uint16_t iscsicaps; 839 uint16_t fcoecaps; 840 841 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */ 842 843 struct mtx sc_lock; 844 char lockname[16]; 845 846 /* Starving free lists */ 847 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */ 848 TAILQ_HEAD(, sge_fl) sfl; 849 struct callout sfl_callout; 850 851 struct mtx reg_lock; /* for indirect register access */ 852 853 struct memwin memwin[NUM_MEMWIN]; /* memory windows */ 854 855 const char *last_op; 856 const void *last_op_thr; 857 int last_op_flags; 858 }; 859 860 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock) 861 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock) 862 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED) 863 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED) 864 865 #define ASSERT_SYNCHRONIZED_OP(sc) \ 866 KASSERT(IS_BUSY(sc) && \ 867 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \ 868 ("%s: operation not synchronized.", __func__)) 869 870 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock) 871 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock) 872 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED) 873 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED) 874 875 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock) 876 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock) 877 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock) 878 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED) 879 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED) 880 881 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl) 882 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl) 883 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl) 884 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl) 885 886 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock) 887 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock) 888 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock) 889 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED) 890 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED) 891 892 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq) 893 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq) 894 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq) 895 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq) 896 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq) 897 898 #define CH_DUMP_MBOX(sc, mbox, data_reg) \ 899 do { \ 900 if (sc->debug_flags & DF_DUMP_MBOX) { \ 901 log(LOG_NOTICE, \ 902 "%s mbox %u: %016llx %016llx %016llx %016llx " \ 903 "%016llx %016llx %016llx %016llx\n", \ 904 device_get_nameunit(sc->dev), mbox, \ 905 (unsigned long long)t4_read_reg64(sc, data_reg), \ 906 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \ 907 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \ 908 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \ 909 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \ 910 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \ 911 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \ 912 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \ 913 } \ 914 } while (0) 915 916 #define for_each_txq(vi, iter, q) \ 917 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \ 918 iter < vi->ntxq; ++iter, ++q) 919 #define for_each_rxq(vi, iter, q) \ 920 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \ 921 iter < vi->nrxq; ++iter, ++q) 922 #define for_each_ofld_txq(vi, iter, q) \ 923 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \ 924 iter < vi->nofldtxq; ++iter, ++q) 925 #define for_each_ofld_rxq(vi, iter, q) \ 926 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \ 927 iter < vi->nofldrxq; ++iter, ++q) 928 #define for_each_nm_txq(vi, iter, q) \ 929 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \ 930 iter < vi->nnmtxq; ++iter, ++q) 931 #define for_each_nm_rxq(vi, iter, q) \ 932 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \ 933 iter < vi->nnmrxq; ++iter, ++q) 934 #define for_each_vi(_pi, _iter, _vi) \ 935 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \ 936 ++(_iter), ++(_vi)) 937 938 #define IDXINCR(idx, incr, wrap) do { \ 939 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \ 940 } while (0) 941 #define IDXDIFF(head, tail, wrap) \ 942 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head)) 943 944 /* One for errors, one for firmware events */ 945 #define T4_EXTRA_INTR 2 946 947 static inline uint32_t 948 t4_read_reg(struct adapter *sc, uint32_t reg) 949 { 950 951 return bus_space_read_4(sc->bt, sc->bh, reg); 952 } 953 954 static inline void 955 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val) 956 { 957 958 bus_space_write_4(sc->bt, sc->bh, reg, val); 959 } 960 961 static inline uint64_t 962 t4_read_reg64(struct adapter *sc, uint32_t reg) 963 { 964 965 return t4_bus_space_read_8(sc->bt, sc->bh, reg); 966 } 967 968 static inline void 969 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val) 970 { 971 972 t4_bus_space_write_8(sc->bt, sc->bh, reg, val); 973 } 974 975 static inline void 976 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val) 977 { 978 979 *val = pci_read_config(sc->dev, reg, 1); 980 } 981 982 static inline void 983 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val) 984 { 985 986 pci_write_config(sc->dev, reg, val, 1); 987 } 988 989 static inline void 990 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val) 991 { 992 993 *val = pci_read_config(sc->dev, reg, 2); 994 } 995 996 static inline void 997 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val) 998 { 999 1000 pci_write_config(sc->dev, reg, val, 2); 1001 } 1002 1003 static inline void 1004 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val) 1005 { 1006 1007 *val = pci_read_config(sc->dev, reg, 4); 1008 } 1009 1010 static inline void 1011 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val) 1012 { 1013 1014 pci_write_config(sc->dev, reg, val, 4); 1015 } 1016 1017 static inline struct port_info * 1018 adap2pinfo(struct adapter *sc, int idx) 1019 { 1020 1021 return (sc->port[idx]); 1022 } 1023 1024 static inline void 1025 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[]) 1026 { 1027 1028 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN); 1029 } 1030 1031 static inline bool 1032 is_10G_port(const struct port_info *pi) 1033 { 1034 1035 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0); 1036 } 1037 1038 static inline bool 1039 is_40G_port(const struct port_info *pi) 1040 { 1041 1042 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0); 1043 } 1044 1045 static inline int 1046 port_top_speed(const struct port_info *pi) 1047 { 1048 1049 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) 1050 return (100); 1051 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 1052 return (40); 1053 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 1054 return (10); 1055 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 1056 return (1); 1057 1058 return (0); 1059 } 1060 1061 static inline int 1062 tx_resume_threshold(struct sge_eq *eq) 1063 { 1064 1065 /* not quite the same as qsize / 4, but this will do. */ 1066 return (eq->sidx / 4); 1067 } 1068 1069 static inline int 1070 t4_use_ldst(struct adapter *sc) 1071 { 1072 1073 #ifdef notyet 1074 return (sc->flags & FW_OK || !sc->use_bd); 1075 #else 1076 return (0); 1077 #endif 1078 } 1079 1080 /* t4_main.c */ 1081 int t4_os_find_pci_capability(struct adapter *, int); 1082 int t4_os_pci_save_state(struct adapter *); 1083 int t4_os_pci_restore_state(struct adapter *); 1084 void t4_os_portmod_changed(const struct adapter *, int); 1085 void t4_os_link_changed(struct adapter *, int, int, int); 1086 void t4_iterate(void (*)(struct adapter *, void *), void *); 1087 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *); 1088 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *); 1089 void doom_vi(struct adapter *, struct vi_info *); 1090 void end_synchronized_op(struct adapter *, int); 1091 int update_mac_settings(struct ifnet *, int); 1092 int adapter_full_init(struct adapter *); 1093 int adapter_full_uninit(struct adapter *); 1094 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter); 1095 int vi_full_init(struct vi_info *); 1096 int vi_full_uninit(struct vi_info *); 1097 void vi_sysctls(struct vi_info *); 1098 void vi_tick(void *); 1099 1100 #ifdef DEV_NETMAP 1101 /* t4_netmap.c */ 1102 void cxgbe_nm_attach(struct vi_info *); 1103 void cxgbe_nm_detach(struct vi_info *); 1104 void t4_nm_intr(void *); 1105 #endif 1106 1107 /* t4_sge.c */ 1108 void t4_sge_modload(void); 1109 void t4_sge_modunload(void); 1110 uint64_t t4_sge_extfree_refs(void); 1111 void t4_tweak_chip_settings(struct adapter *); 1112 int t4_read_chip_settings(struct adapter *); 1113 int t4_create_dma_tag(struct adapter *); 1114 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *, 1115 struct sysctl_oid_list *); 1116 int t4_destroy_dma_tag(struct adapter *); 1117 int t4_setup_adapter_queues(struct adapter *); 1118 int t4_teardown_adapter_queues(struct adapter *); 1119 int t4_setup_vi_queues(struct vi_info *); 1120 int t4_teardown_vi_queues(struct vi_info *); 1121 void t4_intr_all(void *); 1122 void t4_intr(void *); 1123 void t4_vi_intr(void *); 1124 void t4_intr_err(void *); 1125 void t4_intr_evt(void *); 1126 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *); 1127 void t4_update_fl_bufsize(struct ifnet *); 1128 int parse_pkt(struct mbuf **); 1129 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *); 1130 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *); 1131 int tnl_cong(struct port_info *, int); 1132 int t4_register_an_handler(an_handler_t); 1133 int t4_register_fw_msg_handler(int, fw_msg_handler_t); 1134 int t4_register_cpl_handler(int, cpl_handler_t); 1135 1136 /* t4_tracer.c */ 1137 struct t4_tracer; 1138 void t4_tracer_modload(void); 1139 void t4_tracer_modunload(void); 1140 void t4_tracer_port_detach(struct adapter *); 1141 int t4_get_tracer(struct adapter *, struct t4_tracer *); 1142 int t4_set_tracer(struct adapter *, struct t4_tracer *); 1143 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1144 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *); 1145 1146 static inline struct wrqe * 1147 alloc_wrqe(int wr_len, struct sge_wrq *wrq) 1148 { 1149 int len = offsetof(struct wrqe, wr) + wr_len; 1150 struct wrqe *wr; 1151 1152 wr = malloc(len, M_CXGBE, M_NOWAIT); 1153 if (__predict_false(wr == NULL)) 1154 return (NULL); 1155 wr->wr_len = wr_len; 1156 wr->wrq = wrq; 1157 return (wr); 1158 } 1159 1160 static inline void * 1161 wrtod(struct wrqe *wr) 1162 { 1163 return (&wr->wr[0]); 1164 } 1165 1166 static inline void 1167 free_wrqe(struct wrqe *wr) 1168 { 1169 free(wr, M_CXGBE); 1170 } 1171 1172 static inline void 1173 t4_wrq_tx(struct adapter *sc, struct wrqe *wr) 1174 { 1175 struct sge_wrq *wrq = wr->wrq; 1176 1177 TXQ_LOCK(wrq); 1178 t4_wrq_tx_locked(sc, wrq, wr); 1179 TXQ_UNLOCK(wrq); 1180 } 1181 1182 #endif 1183